1 /*
2  * Copyright (c) 2023 Nordic Semiconductor ASA
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 /*
8  * GPIOTE - GPIO tasks and events
9  * https://infocenter.nordicsemi.com/topic/ps_nrf52833/gpiote.html?cp=5_1_0_5_8
10  *
11  * This model has the following limitations:
12  *  * INTENCLR will always read as 0
13  *
14  *  * Unlike in real HW, tasks cannot occur simultaneously, they always happen in some sequence
15  *    so task priority is not accounted for
16  *
17  * 53:
18  *  * Unlike in real HW, pins security configuration is ignored. The GPIOTE channels can be connected to any
19  *    pin irrespectively of their security configuration. For the App core, this means both GPIOTE0 and GPIOTE1
20  *    can have any channel connected to any pin in the app core GPIOs.
21  *
22  *  * Check the GPIO peripheral notes. Note that the app core and net core ports are fully separate simulated ports
23  *    unlike in real HW where they are connected to the same analog pin I/Os.
24  *
25  * 53 & 54
26  *  * Split security distinctions are ignored
27  *    == there is no distinction for accesses from secure or non secure bus masters or the S/NS address ranges.
28  *    In all cases all registers are equally accessible, their read content will be the same, and writes will be
29  *    handled equally.
30  *
31  * 54L notes:
32  *  * Unlike in real HW, a GPIOTE channel can be connected to any GPIO port and pin.
33  *
34  *  * Both EVENTS_PORT.SECURE & NONSECURE will be raised at the same time. This is due to the GPIO model
35  *    not considering which pins are labeled as secure or not secure in the SPU.
36  */
37 
38 #include <stdint.h>
39 #include <string.h>
40 #include "NHW_common_types.h"
41 #include "NHW_config.h"
42 #include "NHW_peri_types.h"
43 #include "NRF_GPIOTE.h"
44 #include "NRF_GPIO.h"
45 #include "NHW_xPPI.h"
46 #include "irq_ctrl.h"
47 #include "bs_tracing.h"
48 #include "nsi_tasks.h"
49 
50 NRF_GPIOTE_Type NRF_GPIOTE_regs[NHW_GPIOTE_TOTAL_INST] = {0};
51 /* Mapping of peripheral instance to {int controller instance, int number} */
52 static struct nhw_irq_mapping nhw_gpiote_irq_map[NHW_GPIOTE_TOTAL_INST][NHW_GPIOTE_N_INT] = NHW_GPIOTE_INT_MAP;
53 
54 /* For each GPIO channel, its status */
55 struct gpiote_ch_status_t {
56   uint8_t mode;
57   uint8_t port;  /* GPIO instance */
58   uint8_t pin;   /* GPIO pin in that instance (psel) */
59   uint8_t polarity; /* Content of the CONFIG[].polarity field */
60   /* Level at which the GPIOTE has been driving this pin,
61    * or which it has been getting from the GPIO
62    * true = high, false = low */
63   bool level;
64 };
65 
66 struct gpiote_status {
67   struct gpiote_ch_status_t gpiote_ch_status[NHW_GPIOTE_MAX_CHANNELS];
68   uint n_channels;
69   uint32_t GPIOTE_ITEN[NHW_GPIOTE_N_INT];
70   bool gpiote_int_line[NHW_GPIOTE_N_INT]; /* Is the GPIOTE currently driving its interrupt line high */
71 #if (NHW_HAS_DPPI)
72   uint dppi_map;
73   struct nhw_subsc_mem subscribed_OUT[NHW_GPIOTE_MAX_CHANNELS];
74   struct nhw_subsc_mem subscribed_SET[NHW_GPIOTE_MAX_CHANNELS];
75   struct nhw_subsc_mem subscribed_CLR[NHW_GPIOTE_MAX_CHANNELS];
76 #endif
77 };
78 static struct gpiote_status gpiote_st[NHW_GPIOTE_TOTAL_INST];
79 
80 /**
81  * Initialize the GPIOs model
82  */
nrf_gpiote_init(void)83 static void nrf_gpiote_init(void) {
84   memset(&NRF_GPIOTE_regs, 0, sizeof(NRF_GPIOTE_regs));
85 
86   uint n_ch[] = NHW_GPIOTE_CHANNELS;
87 #if (NHW_HAS_DPPI)
88   uint dppi_map[] = NHW_GPIOTE_DPPI_MAP;
89 #endif
90   for (int i = 0; i < NHW_GPIOTE_TOTAL_INST; i++) {
91     gpiote_st[i].n_channels = n_ch[i];
92 #if (NHW_HAS_DPPI)
93     gpiote_st[i].dppi_map = dppi_map[i];
94 #endif
95   }
96 }
97 
98 NSI_TASK(nrf_gpiote_init, HW_INIT, 100);
99 
100 static void nhw_GPIOTE_signal_EVENTS_PORT(unsigned int inst);
101 
102 /*
103  * API for the GPIO components, in which they can signal that their DETECT output signal
104  * has been raised.
105  *
106  * We do not keep track in the GPIOTE about the signal being lowered, as the GPIOTE
107  * only reacts to raising edges.
108  * Therefore it is the responsibility of the GPIO models to call this if and only
109  * if there is a raising edge on their DETECT output signal.
110  */
nrf_gpiote_port_detect_raise(unsigned int te_inst,unsigned int port)111 void nrf_gpiote_port_detect_raise(unsigned int te_inst, unsigned int port) {
112   (void)port; /* unused */
113   nhw_GPIOTE_signal_EVENTS_PORT(te_inst);
114 }
115 
nrf_gpiote_TASKS_OUT(unsigned int inst,unsigned int n)116 void nrf_gpiote_TASKS_OUT(unsigned int inst, unsigned int n) {
117   struct gpiote_ch_status_t *sc = &gpiote_st[inst].gpiote_ch_status[n];
118   if (sc->mode != GPIOTE_CONFIG_MODE_Task) {
119     return;
120   }
121   switch (sc->polarity) {
122   case GPIOTE_CONFIG_POLARITY_None:
123     return;
124   case GPIOTE_CONFIG_POLARITY_LoToHi:
125     sc->level = true;
126     break;
127   case GPIOTE_CONFIG_POLARITY_HiToLo:
128     sc->level = false;
129     break;
130   case GPIOTE_CONFIG_POLARITY_Toggle:
131     sc->level = !sc->level;
132     break;
133   default:	/* LCOV_EXCL_START */
134     bs_trace_error_time_line("%s: Missconfigured CONFIG.CONFIG[%i]\n", n);
135     break;
136   }		/* LCOV_EXCL_STOP */
137   /* We may be calling the GPIO even if we haven't changed it, but that is fine */
138   nrf_gpio_peri_change_output(sc->port, sc->pin, sc->level);
139 }
140 
nrf_gpiote_TASKS_SET(unsigned int inst,unsigned int n)141 void nrf_gpiote_TASKS_SET(unsigned int inst, unsigned int n) {
142   struct gpiote_ch_status_t *sc = &gpiote_st[inst].gpiote_ch_status[n];
143   if (sc->mode != GPIOTE_CONFIG_MODE_Task) {
144     return;
145   }
146   sc->level = true;
147   /* We may be calling the GPIO even if we haven't changed it, but that is fine */
148   nrf_gpio_peri_change_output(sc->port, sc->pin, sc->level);
149 }
150 
nrf_gpiote_TASKS_CLR(unsigned int inst,unsigned int n)151 void nrf_gpiote_TASKS_CLR(unsigned int inst, unsigned int n) {
152   struct gpiote_ch_status_t *sc = &gpiote_st[inst].gpiote_ch_status[n];
153   if (sc->mode != GPIOTE_CONFIG_MODE_Task) {
154     return;
155   }
156   sc->level = false;
157   /* We may be calling the GPIO even if we haven't changed it, but that is fine */
158   nrf_gpio_peri_change_output(sc->port, sc->pin, sc->level);
159 }
160 
nrf_gpiote_eval_interrupt(unsigned int inst)161 static void nrf_gpiote_eval_interrupt(unsigned int inst) {
162   struct gpiote_status *st = &gpiote_st[inst];
163   bool new_int_line;
164   int mask;
165 
166   for (int line= 0; line < NHW_GPIOTE_N_INT; line ++) {
167     new_int_line = false;
168 
169     for (uint i = 0; i < st->n_channels; i++) {
170       mask = (st->GPIOTE_ITEN[line] >> i) & 0x1;
171       if (NRF_GPIOTE_regs[inst].EVENTS_IN[i] && mask) {
172         new_int_line = true;
173         break; /* No need to check more */
174       }
175     }
176 
177 #if !NHW_GPIOTE_IS_54
178     mask = (st->GPIOTE_ITEN[line] & GPIOTE_INTENCLR_PORT_Msk) >> GPIOTE_INTENCLR_PORT_Pos;
179     if (NRF_GPIOTE_regs[inst].EVENTS_PORT && mask) {
180       new_int_line = true;
181     }
182 #else
183     mask = (st->GPIOTE_ITEN[line] & GPIOTE_INTENCLR0_PORT0NONSECURE_Msk) >> GPIOTE_INTENCLR0_PORT0NONSECURE_Pos;
184     if (NRF_GPIOTE_regs[inst].EVENTS_PORT[0].NONSECURE && mask) {
185       new_int_line = true;
186     }
187     mask = (st->GPIOTE_ITEN[line] & GPIOTE_INTENCLR0_PORT0SECURE_Msk) >> GPIOTE_INTENCLR0_PORT0SECURE_Pos;
188     if (NRF_GPIOTE_regs[inst].EVENTS_PORT[0].SECURE && mask) {
189       new_int_line = true;
190     }
191 #endif
192 
193     hw_irq_ctrl_toggle_level_irq_line_if(&st->gpiote_int_line[line],
194         new_int_line,
195         &nhw_gpiote_irq_map[inst][line]);
196   }
197 }
198 
nhw_GPIOTE_signal_EVENTS_IN(unsigned int inst,unsigned int n)199 static void nhw_GPIOTE_signal_EVENTS_IN(unsigned int inst, unsigned int n) {
200   NRF_GPIOTE_regs[inst].EVENTS_IN[n] = 1;
201   nrf_gpiote_eval_interrupt(inst);
202 #if (NHW_HAS_PPI)
203   nrf_ppi_event(GPIOTE_EVENTS_IN_0 + n);
204 #elif (NHW_HAS_DPPI)
205   nhw_dppi_event_signal_if(gpiote_st[inst].dppi_map,
206                            NRF_GPIOTE_regs[inst].PUBLISH_IN[n]);
207 #endif
208 }
209 
nhw_GPIOTE_signal_EVENTS_PORT(unsigned int inst)210 static void nhw_GPIOTE_signal_EVENTS_PORT(unsigned int inst) {
211 #if !NHW_GPIOTE_IS_54
212   NRF_GPIOTE_regs[inst].EVENTS_PORT = 1;
213 #else
214   NRF_GPIOTE_regs[inst].EVENTS_PORT[0].NONSECURE = 1;
215   NRF_GPIOTE_regs[inst].EVENTS_PORT[0].SECURE = 1;
216 #endif
217   nrf_gpiote_eval_interrupt(inst);
218 
219 #if (NHW_HAS_PPI)
220   nrf_ppi_event(GPIOTE_EVENTS_PORT);
221 #elif (NHW_HAS_DPPI)
222   #if !(NHW_GPIOTE_IS_54)
223   nhw_dppi_event_signal_if(gpiote_st[inst].dppi_map,
224                            NRF_GPIOTE_regs[inst].PUBLISH_PORT);
225   #else
226   nhw_dppi_event_signal_if(gpiote_st[inst].dppi_map,
227                            NRF_GPIOTE_regs[inst].PUBLISH_PORT[0].SECURE);
228   nhw_dppi_event_signal_if(gpiote_st[inst].dppi_map,
229                            NRF_GPIOTE_regs[inst].PUBLISH_PORT[0].NONSECURE);
230   #endif
231 #endif
232 }
233 
234 /*
235  * Function to be called (by the GPIO model) when a pin changes
236  * for which an EVENTS_IN is registered
237  */
nrf_gpiote_input_change_ntf(unsigned int port,unsigned int pin_n,bool value,void * cb_data)238 static void nrf_gpiote_input_change_ntf(unsigned int port, unsigned int pin_n, bool value, void *cb_data)
239 {
240   (void)port;
241   (void)pin_n; /* Unused */
242   uint inst = (intptr_t)cb_data >> 8;
243   int ch_n = (intptr_t)cb_data & 0xFF;
244   struct gpiote_ch_status_t *sc;
245   bool generate_event = false;
246 
247   sc = &gpiote_st[inst].gpiote_ch_status[ch_n];
248 
249   switch (sc->polarity) {
250   case GPIOTE_CONFIG_POLARITY_None:
251     return;
252   case GPIOTE_CONFIG_POLARITY_LoToHi:
253     if ((sc->level == false) && (value == true)) {
254       generate_event = true;
255     }
256     break;
257   case GPIOTE_CONFIG_POLARITY_HiToLo:
258     if ((sc->level == true) && (value == false)) {
259       generate_event = true;
260     }
261     break;
262   case GPIOTE_CONFIG_POLARITY_Toggle:
263     if (sc->level != value) {
264       generate_event = true;
265     }
266     break;
267   default: /* LCOV_EXCL_START */
268     bs_trace_error_time_line("%s: Missconfigured CONFIG.CONFIG[%i]\n", ch_n);
269     break;
270   } /* LCOV_EXCL_STOP */
271   sc->level = value;
272 
273   if (generate_event) {
274     nhw_GPIOTE_signal_EVENTS_IN(inst, ch_n);
275   }
276 }
277 
278 /*
279  * Register write side-effecting functions
280  */
281 
nrf_gpiote_regw_sideeffects_TASKS_OUT(unsigned int inst,unsigned int n)282 void nrf_gpiote_regw_sideeffects_TASKS_OUT(unsigned int inst, unsigned int n) {
283   if (NRF_GPIOTE_regs[inst].TASKS_OUT[n]) {
284     NRF_GPIOTE_regs[inst].TASKS_OUT[n] = 0;
285     nrf_gpiote_TASKS_OUT(inst, n);
286   }
287 }
288 
nrf_gpiote_regw_sideeffects_TASKS_SET(unsigned int inst,unsigned int n)289 void nrf_gpiote_regw_sideeffects_TASKS_SET(unsigned int inst, unsigned int n) {
290   if (NRF_GPIOTE_regs[inst].TASKS_SET[n]) {
291     NRF_GPIOTE_regs[inst].TASKS_SET[n] = 0;
292     nrf_gpiote_TASKS_SET(inst, n);
293   }
294 }
295 
nrf_gpiote_regw_sideeffects_TASKS_CLR(unsigned int inst,unsigned int n)296 void nrf_gpiote_regw_sideeffects_TASKS_CLR(unsigned int inst, unsigned int n) {
297   if (NRF_GPIOTE_regs[inst].TASKS_CLR[n]) {
298     NRF_GPIOTE_regs[inst].TASKS_CLR[n] = 0;
299     nrf_gpiote_TASKS_CLR(inst, n);
300   }
301 }
302 
nrf_gpiote_regw_sideeffects_EVENTS_IN(unsigned int inst,unsigned int n)303 void nrf_gpiote_regw_sideeffects_EVENTS_IN(unsigned int inst, unsigned int n) {
304   (void) n;
305   nrf_gpiote_eval_interrupt(inst);
306 }
307 
nrf_gpiote_regw_sideeffects_EVENTS_PORT(unsigned int inst)308 void nrf_gpiote_regw_sideeffects_EVENTS_PORT(unsigned int inst) {
309   nrf_gpiote_eval_interrupt(inst);
310 }
311 
312 #if NHW_GPIOTE_IS_54
313 static const ptrdiff_t gpiote_int_pdiff =
314     offsetof(NRF_GPIOTE_Type, INTENSET1) - offsetof(NRF_GPIOTE_Type, INTENSET0);
315 #endif
316 
nrf_gpiote_regw_sideeffects_INTENSET(unsigned int inst,unsigned int interrupt_nbr)317 void nrf_gpiote_regw_sideeffects_INTENSET(unsigned int inst, unsigned int interrupt_nbr) {
318 #if NHW_GPIOTE_IS_54
319   uint32_t *INTENSET = (uint32_t *)((uintptr_t)&NRF_GPIOTE_regs[inst].INTENSET0 + interrupt_nbr*gpiote_int_pdiff);
320 #else
321   uint32_t *INTENSET = (uint32_t *)(uintptr_t)&NRF_GPIOTE_regs[inst].INTENSET;
322 #endif
323 
324   if (*INTENSET) {
325     gpiote_st[inst].GPIOTE_ITEN[interrupt_nbr] |= *INTENSET ;
326     *INTENSET  = gpiote_st[inst].GPIOTE_ITEN[interrupt_nbr];
327     nrf_gpiote_eval_interrupt(inst);
328   }
329 }
330 
nrf_gpiote_regw_sideeffects_INTENCLR(unsigned int inst,unsigned int interrupt_nbr)331 void nrf_gpiote_regw_sideeffects_INTENCLR(unsigned int inst, unsigned int interrupt_nbr) {
332 #if NHW_GPIOTE_IS_54
333   uint32_t *INTENCLR = (uint32_t *)((uintptr_t)&NRF_GPIOTE_regs[inst].INTENCLR0 + interrupt_nbr*gpiote_int_pdiff);
334 #else
335   uint32_t *INTENCLR = (uint32_t *)(uintptr_t)&NRF_GPIOTE_regs[inst].INTENCLR;
336 #endif
337 
338   if (*INTENCLR) {
339     gpiote_st[inst].GPIOTE_ITEN[interrupt_nbr] &= ~*INTENCLR;
340     *INTENCLR = 0;
341     nrf_gpiote_eval_interrupt(inst);
342   }
343 }
344 
nrf_gpiote_regw_sideeffects_CONFIG(unsigned int inst,unsigned int ch_n)345 void nrf_gpiote_regw_sideeffects_CONFIG(unsigned int inst, unsigned int ch_n) {
346   struct gpiote_ch_status_t *sc = &gpiote_st[inst].gpiote_ch_status[ch_n];
347   unsigned int mode = NRF_GPIOTE_regs[inst].CONFIG[ch_n] & GPIOTE_CONFIG_MODE_Msk;
348   unsigned int pin = (NRF_GPIOTE_regs[inst].CONFIG[ch_n] & GPIOTE_CONFIG_PSEL_Msk)
349                       >>GPIOTE_CONFIG_PSEL_Pos;
350   unsigned int port = (NRF_GPIOTE_regs[inst].CONFIG[ch_n] & GPIOTE_CONFIG_PORT_Msk)
351                        >>GPIOTE_CONFIG_PORT_Pos;
352 #if defined(NRF5340)
353   /* The App 0,1 ports (from SW POV) are connected in the model to the simulated ports 2 and 3 */
354   if ((inst == NHW_GPIOTE_APP0) || (inst == NHW_GPIOTE_APP1)) {
355     port += NHW_GPIO_APP_P0;
356   }
357 #endif
358   unsigned int polarity = (NRF_GPIOTE_regs[inst].CONFIG[ch_n] & GPIOTE_CONFIG_POLARITY_Msk)
359                            >>GPIOTE_CONFIG_POLARITY_Pos;
360   unsigned int outinit = (NRF_GPIOTE_regs[inst].CONFIG[ch_n] & GPIOTE_CONFIG_OUTINIT_Msk)
361                           >>GPIOTE_CONFIG_OUTINIT_Pos;
362 
363   if ((port != sc->port) || (pin != sc->pin)
364       || (mode == GPIOTE_CONFIG_MODE_Disabled  && sc->mode != GPIOTE_CONFIG_MODE_Disabled)) {
365     /* Disconnect the old GPIO pin from the GPIOTE */
366     nrf_gpio_peri_pin_control(sc->port, sc->pin, 0, 0, 0, NULL, NULL, -1);
367   }
368 
369   sc->mode = mode;
370   sc->pin = pin;
371   sc->port = port;
372   sc->polarity = polarity;
373 
374   if (mode == GPIOTE_CONFIG_MODE_Event) {
375     sc->level = nrf_gpio_get_pin_level(port, pin);
376     intptr_t cb_data = (inst<<8) + ch_n;
377     nrf_gpio_peri_pin_control(port, pin, 1, 3, 2, nrf_gpiote_input_change_ntf, (void *)cb_data, -1);
378   } else if (mode == GPIOTE_CONFIG_MODE_Task) {
379     sc->level = outinit;
380     nrf_gpio_peri_pin_control(port, pin, 1, 2, 3, NULL, NULL, outinit);
381   } else if (mode != GPIOTE_CONFIG_MODE_Disabled) { /* LCOV_EXCL_START */
382     bs_trace_error_time_line("%s: GPIOTE.CONFIG[%u].mode configured to an illegal "
383         "value(%u)\n", __func__, ch_n, mode);
384   } /* LCOV_EXCL_STOP */
385 }
386 
387 #if (NHW_HAS_DPPI)
388 #define NHW_GPIOTE_REGW_SIDEFFECTS_SUBSCRIBE(TASK_N)                                     \
389   static void nrf_gpiote_TASKS_##TASK_N##_wrap(void* param) {                            \
390     unsigned int inst = (uintptr_t)param >> 16;                                          \
391     uint ch_n = (uintptr_t)param & 0xFFFF;                                               \
392     nrf_gpiote_TASKS_##TASK_N(inst, ch_n);                                               \
393   }                                                                                      \
394                                                                                          \
395   void nhw_gpiote_regw_sideeffects_SUBSCRIBE_##TASK_N(uint inst, uint ch_n) {            \
396     struct gpiote_status *st = &gpiote_st[inst];                                         \
397                                                                                          \
398     nhw_dppi_common_subscribe_sideeffect(st->dppi_map,                                   \
399                                          NRF_GPIOTE_regs[inst].SUBSCRIBE_##TASK_N[ch_n],\
400                                          &st->subscribed_##TASK_N[ch_n],                 \
401                                          nrf_gpiote_TASKS_##TASK_N##_wrap,               \
402                                          (void*)((inst << 16) + ch_n));                  \
403   }
404 
405 NHW_GPIOTE_REGW_SIDEFFECTS_SUBSCRIBE(OUT)
NHW_GPIOTE_REGW_SIDEFFECTS_SUBSCRIBE(SET)406 NHW_GPIOTE_REGW_SIDEFFECTS_SUBSCRIBE(SET)
407 NHW_GPIOTE_REGW_SIDEFFECTS_SUBSCRIBE(CLR)
408 #endif
409 
410 /*
411  * Trampolines to automatically call from the PPI
412  */
413 /* Generated with:
414 #! /usr/bin/env python3
415 #GPIOTE.c
416 for task in {"OUT","SET","CLR"}:
417     for i in range(0,8):
418        print("void nrf_gpiote_TASKS_%s_%i(void){ nrf_gpiote_TASKS_%s(%i); }"%(task,i,task,i))
419 #GPIOTE.h
420 for task in {"OUT","SET","CLR"}:
421     for i in range(0,8):
422        print("void nrf_gpiote_TASKS_%s_%i(void);"%(task,i))
423  */
424 #if NHW_HAS_PPI
425 void nrf_gpiote_TASKS_SET_0(void){ nrf_gpiote_TASKS_SET(0, 0); }
nrf_gpiote_TASKS_SET_1(void)426 void nrf_gpiote_TASKS_SET_1(void){ nrf_gpiote_TASKS_SET(0, 1); }
nrf_gpiote_TASKS_SET_2(void)427 void nrf_gpiote_TASKS_SET_2(void){ nrf_gpiote_TASKS_SET(0, 2); }
nrf_gpiote_TASKS_SET_3(void)428 void nrf_gpiote_TASKS_SET_3(void){ nrf_gpiote_TASKS_SET(0, 3); }
nrf_gpiote_TASKS_SET_4(void)429 void nrf_gpiote_TASKS_SET_4(void){ nrf_gpiote_TASKS_SET(0, 4); }
nrf_gpiote_TASKS_SET_5(void)430 void nrf_gpiote_TASKS_SET_5(void){ nrf_gpiote_TASKS_SET(0, 5); }
nrf_gpiote_TASKS_SET_6(void)431 void nrf_gpiote_TASKS_SET_6(void){ nrf_gpiote_TASKS_SET(0, 6); }
nrf_gpiote_TASKS_SET_7(void)432 void nrf_gpiote_TASKS_SET_7(void){ nrf_gpiote_TASKS_SET(0, 7); }
nrf_gpiote_TASKS_CLR_0(void)433 void nrf_gpiote_TASKS_CLR_0(void){ nrf_gpiote_TASKS_CLR(0, 0); }
nrf_gpiote_TASKS_CLR_1(void)434 void nrf_gpiote_TASKS_CLR_1(void){ nrf_gpiote_TASKS_CLR(0, 1); }
nrf_gpiote_TASKS_CLR_2(void)435 void nrf_gpiote_TASKS_CLR_2(void){ nrf_gpiote_TASKS_CLR(0, 2); }
nrf_gpiote_TASKS_CLR_3(void)436 void nrf_gpiote_TASKS_CLR_3(void){ nrf_gpiote_TASKS_CLR(0, 3); }
nrf_gpiote_TASKS_CLR_4(void)437 void nrf_gpiote_TASKS_CLR_4(void){ nrf_gpiote_TASKS_CLR(0, 4); }
nrf_gpiote_TASKS_CLR_5(void)438 void nrf_gpiote_TASKS_CLR_5(void){ nrf_gpiote_TASKS_CLR(0, 5); }
nrf_gpiote_TASKS_CLR_6(void)439 void nrf_gpiote_TASKS_CLR_6(void){ nrf_gpiote_TASKS_CLR(0, 6); }
nrf_gpiote_TASKS_CLR_7(void)440 void nrf_gpiote_TASKS_CLR_7(void){ nrf_gpiote_TASKS_CLR(0, 7); }
nrf_gpiote_TASKS_OUT_0(void)441 void nrf_gpiote_TASKS_OUT_0(void){ nrf_gpiote_TASKS_OUT(0, 0); }
nrf_gpiote_TASKS_OUT_1(void)442 void nrf_gpiote_TASKS_OUT_1(void){ nrf_gpiote_TASKS_OUT(0, 1); }
nrf_gpiote_TASKS_OUT_2(void)443 void nrf_gpiote_TASKS_OUT_2(void){ nrf_gpiote_TASKS_OUT(0, 2); }
nrf_gpiote_TASKS_OUT_3(void)444 void nrf_gpiote_TASKS_OUT_3(void){ nrf_gpiote_TASKS_OUT(0, 3); }
nrf_gpiote_TASKS_OUT_4(void)445 void nrf_gpiote_TASKS_OUT_4(void){ nrf_gpiote_TASKS_OUT(0, 4); }
nrf_gpiote_TASKS_OUT_5(void)446 void nrf_gpiote_TASKS_OUT_5(void){ nrf_gpiote_TASKS_OUT(0, 5); }
nrf_gpiote_TASKS_OUT_6(void)447 void nrf_gpiote_TASKS_OUT_6(void){ nrf_gpiote_TASKS_OUT(0, 6); }
nrf_gpiote_TASKS_OUT_7(void)448 void nrf_gpiote_TASKS_OUT_7(void){ nrf_gpiote_TASKS_OUT(0, 7); }
449 #endif
450