1 /*
2 * Copyright (c) 2018 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_DPPI_H__
35 #define NRF_DPPI_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 #if !defined(NRF_DPPIC0) && defined(NRF_DPPIC)
44 #define NRF_DPPIC0 NRF_DPPIC
45 #endif
46
47 #if !defined(DPPIC0_CH_NUM) && defined(DPPIC_CH_NUM) && \
48 (defined(NRF_DPPIC) || defined(NRF_DPPIC0))
49 #define DPPIC0_CH_NUM DPPIC_CH_NUM
50 #endif
51
52 #if !defined(DPPIC0_GROUP_NUM) && defined(DPPIC_GROUP_NUM) && \
53 (defined(NRF_DPPIC) || defined(NRF_DPPIC0))
54 #define DPPIC0_GROUP_NUM DPPIC_GROUP_NUM
55 #endif
56
57 /*
58 * Macro for generating if statement code blocks that allow extracting
59 * the number of channels associated with the specific DPPIC instance.
60 */
61 #define NRF_INTERNAL_DPPI_CHAN_NUM_EXTRACT(chan_num, p_reg) \
62 if (0) {} \
63 NRFX_FOREACH_PRESENT(DPPIC, NRF_INTERNAL_ELSE_IF_EXTRACT_1, (), (), chan_num, _CH_NUM, p_reg) \
64 else \
65 { \
66 chan_num = 0; \
67 }
68
69 /*
70 * Macro for generating if statement code blocks that allow extracting
71 * the number of groups associated with the specific DPPIC instance.
72 */
73 #define NRF_INTERNAL_DPPI_GROUP_NUM_EXTRACT(group_num, p_reg) \
74 if (0) {} \
75 NRFX_FOREACH_PRESENT(DPPIC, NRF_INTERNAL_ELSE_IF_EXTRACT_1, (), (), group_num, _GROUP_NUM, p_reg) \
76 else \
77 { \
78 group_num = 0; \
79 }
80
81 /* Symbol specifying the maximal number of channels associated with the DPPIC instances. */
82 #define NRF_DPPI_CH_NUM_MAX \
83 NRFX_MAX_N(NRFX_FOREACH_PRESENT(DPPIC, NRFX_INTERNAL_CHAN_NUM, (), (), _) 0)
84
85 /* Symbol specifying the maximal number of groups associated with the DPPIC instances. */
86 #define NRF_DPPI_GROUP_NUM_MAX \
87 NRFX_MAX_N(NRFX_FOREACH_PRESENT(DPPIC, NRFX_INTERNAL_GROUP_NUM, (), (), _) 0)
88
89 /**
90 * @defgroup nrf_dppi_hal DPPI Controller HAL
91 * @{
92 * @ingroup nrf_dppi
93 * @brief Hardware access layer for managing the Distributed Programmable Peripheral
94 * Interconnect Controller (DPPIC).
95 */
96
97 /**
98 * @brief Macro for setting publish/subscribe register corresponding to specified event/task.
99 *
100 * @param[in] task_or_event Address of the event or task for which publish/subscribe
101 * register is to be set.
102 * @param[in] dppi_chan DPPIC channel number.
103 */
104 #if !defined(NRF_DPPI_ENDPOINT_SETUP)
105 #define NRF_DPPI_ENDPOINT_SETUP(task_or_event, dppi_chan) \
106 (*((volatile uint32_t *)(task_or_event + NRF_SUBSCRIBE_PUBLISH_OFFSET(task_or_event))) = \
107 ((uint32_t)dppi_chan | NRF_SUBSCRIBE_PUBLISH_ENABLE))
108 #endif
109
110 /**
111 * @brief Macro for clearing publish/subscribe register corresponding to specified event/task.
112 *
113 * @param[in] task_or_event Address of the event or task for which publish/subscribe
114 * register is to be cleared.
115 */
116 #if !defined(NRF_DPPI_ENDPOINT_CLEAR)
117 #define NRF_DPPI_ENDPOINT_CLEAR(task_or_event) \
118 (*((volatile uint32_t *)(task_or_event + NRF_SUBSCRIBE_PUBLISH_OFFSET(task_or_event))) = 0)
119 #endif
120
121 /** @brief DPPI channel groups. */
122 typedef enum
123 {
124 NRF_DPPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */
125 NRF_DPPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */
126 #if NRF_DPPI_GROUP_NUM_MAX > 2 || defined(__NRFX_DOXYGEN__)
127 NRF_DPPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */
128 NRF_DPPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */
129 #endif
130 #if NRF_DPPI_GROUP_NUM_MAX > 4 || defined(__NRFX_DOXYGEN__)
131 NRF_DPPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */
132 NRF_DPPI_CHANNEL_GROUP5 = 5 /**< Channel group 5. */
133 #endif
134 } nrf_dppi_channel_group_t;
135
136 /** @brief DPPI tasks. */
137 typedef enum
138 {
139 NRF_DPPI_TASK_CHG0_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[0].EN), /**< Enable channel group 0. */
140 NRF_DPPI_TASK_CHG0_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[0].DIS), /**< Disable channel group 0. */
141 NRF_DPPI_TASK_CHG1_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[1].EN), /**< Enable channel group 1. */
142 NRF_DPPI_TASK_CHG1_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[1].DIS), /**< Disable channel group 1. */
143 #if NRF_DPPI_GROUP_NUM_MAX > 2 || defined(__NRFX_DOXYGEN__)
144 NRF_DPPI_TASK_CHG2_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[2].EN), /**< Enable channel group 2. */
145 NRF_DPPI_TASK_CHG2_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[2].DIS), /**< Disable channel group 2. */
146 NRF_DPPI_TASK_CHG3_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[3].EN), /**< Enable channel group 3. */
147 NRF_DPPI_TASK_CHG3_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[3].DIS), /**< Disable channel group 3. */
148 #endif
149 #if NRF_DPPI_GROUP_NUM_MAX > 4 || defined(__NRFX_DOXYGEN__)
150 NRF_DPPI_TASK_CHG4_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[4].EN), /**< Enable channel group 4. */
151 NRF_DPPI_TASK_CHG4_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[4].DIS), /**< Disable channel group 4. */
152 NRF_DPPI_TASK_CHG5_EN = offsetof(NRF_DPPIC_Type, TASKS_CHG[5].EN), /**< Enable channel group 5. */
153 NRF_DPPI_TASK_CHG5_DIS = offsetof(NRF_DPPIC_Type, TASKS_CHG[5].DIS) /**< Disable channel group 5. */
154 #endif
155 } nrf_dppi_task_t;
156
157 /**
158 * @brief Function for getting the total number of available channels for the given DPPIC instance.
159 *
160 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
161 *
162 * @return Number of available channels.
163 */
164 NRF_STATIC_INLINE uint8_t nrf_dppi_channel_number_get(NRF_DPPIC_Type const * p_reg);
165
166 /**
167 * @brief Function for getting the total number of available groups for the given DPPIC instance.
168 *
169 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
170 *
171 * @return Number of available groups.
172 */
173 NRF_STATIC_INLINE uint8_t nrf_dppi_group_number_get(NRF_DPPIC_Type const * p_reg);
174
175 /**
176 * @brief Function for activating a DPPI task.
177 *
178 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
179 * @param[in] dppi_task Task to be activated.
180 */
181 NRF_STATIC_INLINE void nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t dppi_task);
182
183 /**
184 * @brief Function for getting the address of the specified DPPI task register.
185 *
186 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
187 * @param[in] task Requested task.
188 *
189 * @return Address of the specified task register.
190 */
191 NRF_STATIC_INLINE uint32_t nrf_dppi_task_address_get(NRF_DPPIC_Type const * p_reg,
192 nrf_dppi_task_t task);
193
194 /**
195 * @brief Function for checking the state of a specific DPPI channel.
196 *
197 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
198 * @param[in] channel Channel to be checked.
199 *
200 * @retval true The channel is enabled.
201 * @retval false The channel is not enabled.
202 */
203 NRF_STATIC_INLINE bool nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg, uint8_t channel);
204
205 /**
206 * @brief Function for enabling multiple DPPI channels.
207 *
208 * The bits in @c mask value correspond to particular channels. It means that
209 * writing 1 to bit 0 enables channel 0, writing 1 to bit 1 enables channel 1 etc.
210 *
211 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
212 * @param[in] mask Channel mask.
213 */
214 NRF_STATIC_INLINE void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask);
215
216 /**
217 * @brief Function for disabling multiple DPPI channels.
218 *
219 * The bits in @c mask value correspond to particular channels. It means that
220 * writing 1 to bit 0 disables channel 0, writing 1 to bit 1 disables channel 1 etc.
221 *
222 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
223 * @param[in] mask Channel mask.
224 */
225 NRF_STATIC_INLINE void nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg, uint32_t mask);
226
227 /**
228 * @brief Function for disabling all DPPI channels.
229 *
230 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
231 */
232 NRF_STATIC_INLINE void nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg);
233
234 /**
235 * @brief Function for setting the subscribe configuration for a given
236 * DPPI task.
237 *
238 * @warning After setting the subscription for a given task, channel group configuration
239 * associated with this task cannot be modified until @ref nrf_dppi_subscribe_clear is used.
240 *
241 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
242 * @param[in] task Task for which to set the configuration.
243 * @param[in] channel Channel through which to subscribe events.
244 */
245 NRF_STATIC_INLINE void nrf_dppi_subscribe_set(NRF_DPPIC_Type * p_reg,
246 nrf_dppi_task_t task,
247 uint8_t channel);
248
249 /**
250 * @brief Function for clearing the subscribe configuration for a given
251 * DPPI task.
252 *
253 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
254 * @param[in] task Task for which to clear the configuration.
255 */
256 NRF_STATIC_INLINE void nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t task);
257
258 /**
259 * @brief Function for setting multiple DPPI channels in a channel group.
260 *
261 * @details This function assigns all specified channels to the group.
262 * The bits in @p channel_mask value correspond to particular channels. It means that
263 * writing 1 to bit 0 includes channel 0, writing 1 to bit 1 includes channel 1, and so on.
264 *
265 * @warning All channels included previously will be overwritten.
266 *
267 * @warning Channel group configuration can be modified only if subscriptions for tasks
268 * associated with this group are disabled.
269 *
270 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
271 * @param[in] channel_mask Channels to be assigned in the group.
272 * @param[in] channel_group Channel group.
273 */
274 NRF_STATIC_INLINE void nrf_dppi_channels_group_set(NRF_DPPIC_Type * p_reg,
275 uint32_t channel_mask,
276 nrf_dppi_channel_group_t channel_group);
277
278 /**
279 * @brief Function for including multiple DPPI channels in a channel group.
280 *
281 * @details This function adds all specified channels to the group.
282 * The bits in @p channel_mask value correspond to particular channels. It means that
283 * writing 1 to bit 0 includes channel 0, writing 1 to bit 1 includes channel 1 etc.
284 *
285 * @warning Channel group configuration can be modified only if subscriptions for tasks
286 * associated with this group are disabled.
287 *
288 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
289 * @param[in] channel_mask Channels to be included in the group.
290 * @param[in] channel_group Channel group.
291 */
292 NRF_STATIC_INLINE void nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * p_reg,
293 uint32_t channel_mask,
294 nrf_dppi_channel_group_t channel_group);
295
296 /**
297 * @brief Function for removing multiple DPPI channels from a channel group.
298 *
299 * @details This function removes all specified channels from the group.
300 * The bits in @c channel_mask value correspond to particular channels. It means that
301 * writing 1 to bit 0 removes channel 0, writing 1 to bit 1 removes channel 1 etc.
302 *
303 * @warning Channel group configuration can be modified only if subscriptions for tasks
304 * associated with this group are disabled.
305 *
306 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
307 * @param[in] channel_mask Channels to be removed from the group.
308 * @param[in] channel_group Channel group.
309 */
310 NRF_STATIC_INLINE void nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg,
311 uint32_t channel_mask,
312 nrf_dppi_channel_group_t channel_group);
313
314 /**
315 * @brief Function for removing all DPPI channels from a channel group.
316 *
317 * @warning Channel group configuration can be modified only if subscriptions for tasks
318 * associated with this group are disabled.
319 *
320 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
321 * @param[in] group Channel group.
322 */
323 NRF_STATIC_INLINE void nrf_dppi_group_clear(NRF_DPPIC_Type * p_reg,
324 nrf_dppi_channel_group_t group);
325
326 /**
327 * @brief Function for enabling a channel group.
328 *
329 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
330 * @param[in] group Channel group.
331 */
332 NRF_STATIC_INLINE void nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg,
333 nrf_dppi_channel_group_t group);
334
335 /**
336 * @brief Function for disabling a channel group.
337 *
338 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
339 * @param[in] group Channel group.
340 */
341 NRF_STATIC_INLINE void nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,
342 nrf_dppi_channel_group_t group);
343
344 /**
345 * @brief Function for getting the ENABLE task associated with the specified channel group.
346 *
347 * @param[in] index Channel group index.
348 *
349 * @return Requested ENABLE task.
350 */
351 NRF_STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_enable_task_get(uint8_t index);
352
353 /**
354 * @brief Function for getting the DISABLE task associated with the specified channel group.
355 *
356 * @param[in] index Channel group index.
357 *
358 * @return Requested DISABLE task.
359 */
360 NRF_STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_disable_task_get(uint8_t index);
361
362 #ifndef NRF_DECLARE_ONLY
363
nrf_dppi_channel_number_get(NRF_DPPIC_Type const * p_reg)364 NRF_STATIC_INLINE uint8_t nrf_dppi_channel_number_get(NRF_DPPIC_Type const * p_reg)
365 {
366 uint8_t chan_num = 0;
367 NRF_INTERNAL_DPPI_CHAN_NUM_EXTRACT(chan_num, p_reg);
368 return chan_num;
369 }
370
nrf_dppi_group_number_get(NRF_DPPIC_Type const * p_reg)371 NRF_STATIC_INLINE uint8_t nrf_dppi_group_number_get(NRF_DPPIC_Type const * p_reg)
372 {
373 uint8_t group_num = 0;
374 NRF_INTERNAL_DPPI_GROUP_NUM_EXTRACT(group_num, p_reg);
375 return group_num;
376 }
377
nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg,nrf_dppi_task_t dppi_task)378 NRF_STATIC_INLINE void nrf_dppi_task_trigger(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t dppi_task)
379 {
380 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) dppi_task)) = 1;
381 }
382
nrf_dppi_task_address_get(NRF_DPPIC_Type const * p_reg,nrf_dppi_task_t task)383 NRF_STATIC_INLINE uint32_t nrf_dppi_task_address_get(NRF_DPPIC_Type const * p_reg,
384 nrf_dppi_task_t task)
385 {
386 return nrf_task_event_address_get(p_reg, task);
387 }
388
nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg,uint8_t channel)389 NRF_STATIC_INLINE bool nrf_dppi_channel_check(NRF_DPPIC_Type const * p_reg, uint8_t channel)
390 {
391 NRFX_ASSERT(channel < nrf_dppi_channel_number_get(p_reg));
392 return ((p_reg->CHEN & (DPPIC_CHEN_CH0_Enabled << (DPPIC_CHEN_CH0_Pos + channel))) != 0);
393 }
394
nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg)395 NRF_STATIC_INLINE void nrf_dppi_channels_disable_all(NRF_DPPIC_Type * p_reg)
396 {
397 p_reg->CHENCLR = 0xFFFFFFFFuL;
398 }
399
nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg,uint32_t mask)400 NRF_STATIC_INLINE void nrf_dppi_channels_enable(NRF_DPPIC_Type * p_reg, uint32_t mask)
401 {
402 p_reg->CHENSET = mask;
403 }
404
nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg,uint32_t mask)405 NRF_STATIC_INLINE void nrf_dppi_channels_disable(NRF_DPPIC_Type * p_reg, uint32_t mask)
406 {
407 p_reg->CHENCLR = mask;
408 }
409
nrf_dppi_subscribe_set(NRF_DPPIC_Type * p_reg,nrf_dppi_task_t task,uint8_t channel)410 NRF_STATIC_INLINE void nrf_dppi_subscribe_set(NRF_DPPIC_Type * p_reg,
411 nrf_dppi_task_t task,
412 uint8_t channel)
413 {
414 NRFX_ASSERT(channel < nrf_dppi_channel_number_get(p_reg));
415 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) =
416 ((uint32_t)channel | NRF_SUBSCRIBE_PUBLISH_ENABLE);
417 }
418
nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg,nrf_dppi_task_t task)419 NRF_STATIC_INLINE void nrf_dppi_subscribe_clear(NRF_DPPIC_Type * p_reg, nrf_dppi_task_t task)
420 {
421 *((volatile uint32_t *) ((uint8_t *) p_reg + (uint32_t) task + 0x80uL)) = 0;
422 }
423
nrf_dppi_channels_group_set(NRF_DPPIC_Type * p_reg,uint32_t channel_mask,nrf_dppi_channel_group_t channel_group)424 NRF_STATIC_INLINE void nrf_dppi_channels_group_set(NRF_DPPIC_Type * p_reg,
425 uint32_t channel_mask,
426 nrf_dppi_channel_group_t channel_group)
427 {
428 p_reg->CHG[(uint32_t) channel_group] = channel_mask;
429 }
430
nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * p_reg,uint32_t channel_mask,nrf_dppi_channel_group_t channel_group)431 NRF_STATIC_INLINE void nrf_dppi_channels_include_in_group(NRF_DPPIC_Type * p_reg,
432 uint32_t channel_mask,
433 nrf_dppi_channel_group_t channel_group)
434 {
435 p_reg->CHG[(uint32_t) channel_group] =
436 p_reg->CHG[(uint32_t) channel_group] | (channel_mask);
437 }
438
nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg,uint32_t channel_mask,nrf_dppi_channel_group_t channel_group)439 NRF_STATIC_INLINE void nrf_dppi_channels_remove_from_group(NRF_DPPIC_Type * p_reg,
440 uint32_t channel_mask,
441 nrf_dppi_channel_group_t channel_group)
442 {
443 p_reg->CHG[(uint32_t) channel_group] =
444 p_reg->CHG[(uint32_t) channel_group] & ~(channel_mask);
445 }
446
nrf_dppi_group_clear(NRF_DPPIC_Type * p_reg,nrf_dppi_channel_group_t group)447 NRF_STATIC_INLINE void nrf_dppi_group_clear(NRF_DPPIC_Type * p_reg,
448 nrf_dppi_channel_group_t group)
449 {
450 p_reg->CHG[(uint32_t) group] = 0;
451 }
452
nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg,nrf_dppi_channel_group_t group)453 NRF_STATIC_INLINE void nrf_dppi_group_enable(NRF_DPPIC_Type * p_reg, nrf_dppi_channel_group_t group)
454 {
455 p_reg->TASKS_CHG[(uint32_t) group].EN = 1;
456 }
457
nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,nrf_dppi_channel_group_t group)458 NRF_STATIC_INLINE void nrf_dppi_group_disable(NRF_DPPIC_Type * p_reg,
459 nrf_dppi_channel_group_t group)
460 {
461 p_reg->TASKS_CHG[(uint32_t) group].DIS = 1;
462 }
463
nrf_dppi_group_enable_task_get(uint8_t index)464 NRF_STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_enable_task_get(uint8_t index)
465 {
466 return (nrf_dppi_task_t)NRFX_OFFSETOF(NRF_DPPIC_Type, TASKS_CHG[index].EN);
467 }
468
nrf_dppi_group_disable_task_get(uint8_t index)469 NRF_STATIC_INLINE nrf_dppi_task_t nrf_dppi_group_disable_task_get(uint8_t index)
470 {
471 return (nrf_dppi_task_t)NRFX_OFFSETOF(NRF_DPPIC_Type, TASKS_CHG[index].DIS);
472 }
473
474 #endif // NRF_DECLARE_ONLY
475
476 /** @} */
477
478 #ifdef __cplusplus
479 }
480 #endif
481
482 #endif // NRF_DPPIC_H__
483
