1 /*
2 * Copyright (c) 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_CRACEN_CM_H__
35 #define NRF_CRACEN_CM_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_cracen_cm_hal CRACEN CryptoMaster HAL
45 * @{
46 * @ingroup nrf_cracen
47 * @brief Hardware access layer for managing the Crypto Accelerator Engine (CRACEN)
48 * CryptoMaster (CM) peripheral.
49 */
50
51 /** @brief CRACEN CryptoMaster configuration indirect mask. */
52 typedef enum
53 {
54 NRF_CRACEN_CM_CONFIG_INDIRECT_FETCH_MASK = CRACENCORE_CRYPTMSTRDMA_CONFIG_FETCHCTRLINDIRECT_Msk, ///< Set the fetch DMA in scatter/gather mode
55 NRF_CRACEN_CM_CONFIG_INDIRECT_PUSH_MASK = CRACENCORE_CRYPTMSTRDMA_CONFIG_PUSHCTRLINDIRECT_Msk, ///< Set the push DMA in scatter/gather mode
56 } nrf_cracen_cm_config_indirect_mask_t;
57
58 /** @brief CRACEN CryptoMaster interrupts' masks. */
59 typedef enum
60 {
61 NRF_CRACEN_CM_INT_FETCH_BLOCK_END_MASK = 0x1, ///< Interrupt on DMA fetch end of block (if enabled in the descriptor, for indirect mode only).
62 NRF_CRACEN_CM_INT_FETCH_STOPPED_MASK = 0x2, ///< Interrupt on DMA fetch stopped/ended.
63 NRF_CRACEN_CM_INT_FETCH_ERROR_MASK = 0x4, ///< Interrupt on DMA fetch bus error.
64 NRF_CRACEN_CM_INT_PUSH_BLOCK_END_MASK = 0x8, ///< Interrupt on DMA push end of block (if enabled in the descriptor, for indirect mode only).
65 NRF_CRACEN_CM_INT_PUSH_STOPPED_MASK = 0x10, ///< Interrupt on DMA push stopped/ended.
66 NRF_CRACEN_CM_INT_PUSH_ERROR_MASK = 0x20, ///< Interrupt on DMA push bus error.
67 } nrf_cracen_cm_int_mask_t;
68
69 /** @brief CRACEN CryptoMaster status busy mask. */
70 typedef enum
71 {
72 NRF_CRACEN_CM_STATUS_BUSY_FETCH_MASK = CRACENCORE_CRYPTMSTRDMA_STATUS_FETCHBUSY_Msk, ///< Fetch DMA is busy.
73 NRF_CRACEN_CM_STATUS_BUSY_PUSH_MASK = CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHBUSY_Msk, ///< Push DMA is busy.
74 NRF_CRACEN_CM_STATUS_FETCH_NOT_EMPTY_MASK = CRACENCORE_CRYPTMSTRDMA_STATUS_FETCHNOTEMPTY_Msk, ///< Fetch DMA FIFO is not empty.
75 NRF_CRACEN_CM_STATUS_PUSH_WAITING_MASK = CRACENCORE_CRYPTMSTRDMA_STATUS_PUSHWAITINGFIFO_Msk, ///< Push DMA is waiting for data from a crypto engine.
76 NRF_CRACEN_CM_STATUS_SOFTRESET_BUSY_MASK = CRACENCORE_CRYPTMSTRDMA_STATUS_SOFTRSTBUSY_Msk, ///< Soft-resetting.
77 } nrf_cracen_cm_status_mask_t;
78
79 /**
80 * @brief Function for setting the DMA fetch pointer to either the buffer from which the DMA will
81 * read data (in direct mode), or a pointer to a DMA descriptor (in scatter mode).
82 *
83 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
84 * @param[in] p_buffer Pointer to the data to read, or a read descriptor.
85 */
86 NRF_STATIC_INLINE void nrf_cracen_cm_fetch_addr_set(NRF_CRACENCORE_Type * p_reg,
87 void const * p_buffer);
88
89 /**
90 * @brief Function for setting the DMA push pointer to either the buffer into which the DMA will
91 * write data (in direct mode), or a pointer to a DMA descriptor (in scatter mode).
92 *
93 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
94 * @param[in] p_buffer Pointer to the buffer where to write, or a write descriptor.
95 */
96 NRF_STATIC_INLINE void nrf_cracen_cm_push_addr_set(NRF_CRACENCORE_Type * p_reg,
97 void const * p_buffer);
98
99 /**
100 * @brief Function for setting the DMA's indirect configuration
101 *
102 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
103 * @param[in] mask Mask selecting if the push and/or fetch DMA should be in indirect mode.
104 * Use @ref nrf_cracen_cm_config_indirect_mask_t for bit masking.
105 */
106 NRF_STATIC_INLINE void nrf_cracen_cm_config_indirect_set(NRF_CRACENCORE_Type * p_reg,
107 nrf_cracen_cm_config_indirect_mask_t mask);
108
109 /**
110 * @brief Function for soft resetting the CryptoMaster module
111 *
112 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
113 */
114 NRF_STATIC_INLINE void nrf_cracen_cm_softreset(NRF_CRACENCORE_Type * p_reg);
115
116 /**
117 * @brief Function for starting the CryptoMaster
118 *
119 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
120 *
121 * @note Both the fetch and push DMA engines will be started simultaneously.
122 */
123 NRF_STATIC_INLINE void nrf_cracen_cm_start(NRF_CRACENCORE_Type * p_reg);
124
125 /**
126 * @brief Function for enabling the specified interrupts.
127 *
128 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
129 * @param[in] mask Mask of interrupts to be enabled.
130 * Use @ref nrf_cracen_cm_int_mask_t values for bit masking.
131 */
132 NRF_STATIC_INLINE void nrf_cracen_cm_int_enable(NRF_CRACENCORE_Type * p_reg, uint32_t mask);
133
134 /**
135 * @brief Function for disabling the specified interrupts.
136 *
137 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
138 * @param[in] mask Mask of interrupts to be disabled.
139 * Use @ref nrf_cracen_cm_int_mask_t values for bit masking.
140 */
141 NRF_STATIC_INLINE void nrf_cracen_cm_int_disable(NRF_CRACENCORE_Type * p_reg, uint32_t mask);
142
143 /**
144 * @brief Function for checking if the specified interrupts are enabled.
145 *
146 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
147 * @param[in] mask Mask of interrupts to be checked.
148 * Use @ref nrf_cracen_cm_int_mask_t values for bit masking.
149 *
150 * @return Mask of enabled interrupts.
151 */
152 NRF_STATIC_INLINE uint32_t nrf_cracen_cm_int_enable_check(NRF_CRACENCORE_Type const * p_reg,
153 uint32_t mask);
154
155 /**
156 * @brief Function for clearing the specified interrupts.
157 *
158 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
159 * @param[in] mask Mask of interrupts to be cleared.
160 * Use @ref nrf_cracen_cm_int_mask_t values for bit masking.
161 */
162 NRF_STATIC_INLINE void nrf_cracen_cm_int_clear(NRF_CRACENCORE_Type * p_reg, uint32_t mask);
163
164 /**
165 * @brief Function for getting the state of pending interrupts.
166 *
167 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
168 *
169 * @return Bitmask with information about pending interrupts.
170 * Use @ref nrf_cracen_cm_int_mask_t values for bit masking.
171 */
172 NRF_STATIC_INLINE uint32_t nrf_cracen_cm_int_pending_get(NRF_CRACENCORE_Type const * p_reg);
173
174 /**
175 * @brief Function for getting the status of the CryptoMaster.
176 *
177 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
178 * @param[in] mask Mask of busy conditions to be checked.
179 * Use @ref nrf_cracen_cm_status_mask_t values for bit masking.
180 *
181 * @return Masked busy conditions.
182 */
183 NRF_STATIC_INLINE uint32_t nrf_cracen_cm_status_get(NRF_CRACENCORE_Type const * p_reg,
184 uint32_t mask);
185
186 #ifndef NRF_DECLARE_ONLY
187
nrf_cracen_cm_fetch_addr_set(NRF_CRACENCORE_Type * p_reg,void const * p_buffer)188 NRF_STATIC_INLINE void nrf_cracen_cm_fetch_addr_set(NRF_CRACENCORE_Type * p_reg,
189 void const * p_buffer)
190 {
191 p_reg->CRYPTMSTRDMA.FETCHADDRLSB = (uint32_t)p_buffer;
192 }
193
nrf_cracen_cm_push_addr_set(NRF_CRACENCORE_Type * p_reg,void const * p_buffer)194 NRF_STATIC_INLINE void nrf_cracen_cm_push_addr_set(NRF_CRACENCORE_Type * p_reg,
195 void const * p_buffer)
196 {
197 p_reg->CRYPTMSTRDMA.PUSHADDRLSB = (uint32_t)p_buffer;
198 }
199
nrf_cracen_cm_config_indirect_set(NRF_CRACENCORE_Type * p_reg,nrf_cracen_cm_config_indirect_mask_t mask)200 NRF_STATIC_INLINE void nrf_cracen_cm_config_indirect_set(NRF_CRACENCORE_Type * p_reg,
201 nrf_cracen_cm_config_indirect_mask_t mask)
202 {
203 p_reg->CRYPTMSTRDMA.CONFIG = (uint32_t)mask;
204 }
205
nrf_cracen_cm_softreset(NRF_CRACENCORE_Type * p_reg)206 NRF_STATIC_INLINE void nrf_cracen_cm_softreset(NRF_CRACENCORE_Type * p_reg)
207 {
208 p_reg->CRYPTMSTRDMA.CONFIG = CRACENCORE_CRYPTMSTRDMA_CONFIG_SOFTRST_Msk;
209 p_reg->CRYPTMSTRDMA.CONFIG = 0;
210 }
211
nrf_cracen_cm_start(NRF_CRACENCORE_Type * p_reg)212 NRF_STATIC_INLINE void nrf_cracen_cm_start(NRF_CRACENCORE_Type * p_reg)
213 {
214 p_reg->CRYPTMSTRDMA.START = CRACENCORE_CRYPTMSTRDMA_START_STARTFETCH_Msk
215 | CRACENCORE_CRYPTMSTRDMA_START_STARTPUSH_Msk;
216 }
217
nrf_cracen_cm_int_enable(NRF_CRACENCORE_Type * p_reg,uint32_t mask)218 NRF_STATIC_INLINE void nrf_cracen_cm_int_enable(NRF_CRACENCORE_Type * p_reg, uint32_t mask)
219 {
220 p_reg->CRYPTMSTRDMA.INTENSET = mask;
221 }
222
nrf_cracen_cm_int_disable(NRF_CRACENCORE_Type * p_reg,uint32_t mask)223 NRF_STATIC_INLINE void nrf_cracen_cm_int_disable(NRF_CRACENCORE_Type * p_reg, uint32_t mask)
224 {
225 p_reg->CRYPTMSTRDMA.INTENCLR = mask;
226 }
227
nrf_cracen_cm_int_enable_check(NRF_CRACENCORE_Type const * p_reg,uint32_t mask)228 NRF_STATIC_INLINE uint32_t nrf_cracen_cm_int_enable_check(NRF_CRACENCORE_Type const * p_reg,
229 uint32_t mask)
230 {
231 return p_reg->CRYPTMSTRDMA.INTENSET & mask;
232 }
233
nrf_cracen_cm_int_pending_get(NRF_CRACENCORE_Type const * p_reg)234 NRF_STATIC_INLINE uint32_t nrf_cracen_cm_int_pending_get(NRF_CRACENCORE_Type const * p_reg)
235 {
236 return p_reg->CRYPTMSTRDMA.INTSTATRAW;
237 }
238
nrf_cracen_cm_int_clear(NRF_CRACENCORE_Type * p_reg,uint32_t mask)239 NRF_STATIC_INLINE void nrf_cracen_cm_int_clear(NRF_CRACENCORE_Type * p_reg, uint32_t mask)
240 {
241 p_reg->CRYPTMSTRDMA.INTSTATCLR = mask;
242 }
243
nrf_cracen_cm_status_get(NRF_CRACENCORE_Type const * p_reg,uint32_t mask)244 NRF_STATIC_INLINE uint32_t nrf_cracen_cm_status_get(NRF_CRACENCORE_Type const * p_reg,
245 uint32_t mask)
246 {
247 return p_reg->CRYPTMSTRDMA.STATUS & mask;
248 }
249 #endif // NRF_DECLARE_ONLY
250
251 /** @} */
252
253 #ifdef __cplusplus
254 }
255 #endif
256
257 #endif // NRF_CRACEN_CM_H__
258
