1 /*
2 * Copyright (c) 2023 - 2025, Nordic Semiconductor ASA
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice, this
11 * list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef NRF_BELLBOARD_H__
35 #define NRF_BELLBOARD_H__
36
37 #include <nrfx.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 * @defgroup nrf_bellboard_hal BELLBOARD HAL
45 * @{
46 * @ingroup nrf_bellboard
47 * @brief Hardware access layer for managing the BELLBOARD peripheral.
48 */
49
50 /** @brief Symbol specifying maximum number of available events triggered. */
51 #define NRF_BELLBOARD_EVENTS_TRIGGERED_COUNT BELLBOARD_EVENTS_TRIGGERED_MaxCount
52
53 /** @brief BELLBOARD events. */
54 typedef enum
55 {
56 NRF_BELLBOARD_EVENT_TRIGGERED_0 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[0]), /**< Triggered 0 event.*/
57 NRF_BELLBOARD_EVENT_TRIGGERED_1 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[1]), /**< Triggered 1 event.*/
58 NRF_BELLBOARD_EVENT_TRIGGERED_2 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[2]), /**< Triggered 2 event.*/
59 NRF_BELLBOARD_EVENT_TRIGGERED_3 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[3]), /**< Triggered 3 event.*/
60 #if NRF_BELLBOARD_EVENTS_TRIGGERED_COUNT > 4
61 NRF_BELLBOARD_EVENT_TRIGGERED_4 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[4]), /**< Triggered 4 event.*/
62 NRF_BELLBOARD_EVENT_TRIGGERED_5 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[5]), /**< Triggered 5 event.*/
63 NRF_BELLBOARD_EVENT_TRIGGERED_6 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[6]), /**< Triggered 6 event.*/
64 NRF_BELLBOARD_EVENT_TRIGGERED_7 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[7]), /**< Triggered 7 event.*/
65 NRF_BELLBOARD_EVENT_TRIGGERED_8 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[8]), /**< Triggered 8 event.*/
66 NRF_BELLBOARD_EVENT_TRIGGERED_9 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[9]), /**< Triggered 9 event.*/
67 NRF_BELLBOARD_EVENT_TRIGGERED_10 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[10]), /**< Triggered 10 event.*/
68 NRF_BELLBOARD_EVENT_TRIGGERED_11 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[11]), /**< Triggered 11 event.*/
69 NRF_BELLBOARD_EVENT_TRIGGERED_12 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[12]), /**< Triggered 12 event.*/
70 NRF_BELLBOARD_EVENT_TRIGGERED_13 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[13]), /**< Triggered 13 event.*/
71 NRF_BELLBOARD_EVENT_TRIGGERED_14 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[14]), /**< Triggered 14 event.*/
72 NRF_BELLBOARD_EVENT_TRIGGERED_15 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[15]), /**< Triggered 15 event.*/
73 NRF_BELLBOARD_EVENT_TRIGGERED_16 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[16]), /**< Triggered 16 event.*/
74 NRF_BELLBOARD_EVENT_TRIGGERED_17 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[17]), /**< Triggered 17 event.*/
75 NRF_BELLBOARD_EVENT_TRIGGERED_18 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[18]), /**< Triggered 18 event.*/
76 NRF_BELLBOARD_EVENT_TRIGGERED_19 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[19]), /**< Triggered 19 event.*/
77 NRF_BELLBOARD_EVENT_TRIGGERED_20 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[20]), /**< Triggered 20 event.*/
78 NRF_BELLBOARD_EVENT_TRIGGERED_21 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[21]), /**< Triggered 21 event.*/
79 NRF_BELLBOARD_EVENT_TRIGGERED_22 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[22]), /**< Triggered 22 event.*/
80 NRF_BELLBOARD_EVENT_TRIGGERED_23 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[23]), /**< Triggered 23 event.*/
81 NRF_BELLBOARD_EVENT_TRIGGERED_24 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[24]), /**< Triggered 24 event.*/
82 NRF_BELLBOARD_EVENT_TRIGGERED_25 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[25]), /**< Triggered 25 event.*/
83 NRF_BELLBOARD_EVENT_TRIGGERED_26 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[26]), /**< Triggered 26 event.*/
84 NRF_BELLBOARD_EVENT_TRIGGERED_27 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[27]), /**< Triggered 27 event.*/
85 NRF_BELLBOARD_EVENT_TRIGGERED_28 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[28]), /**< Triggered 28 event.*/
86 NRF_BELLBOARD_EVENT_TRIGGERED_29 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[29]), /**< Triggered 29 event.*/
87 NRF_BELLBOARD_EVENT_TRIGGERED_30 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[30]), /**< Triggered 30 event.*/
88 NRF_BELLBOARD_EVENT_TRIGGERED_31 = offsetof(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[31]), /**< Triggered 31 event.*/
89 #endif // BELLBOARD_TASKS_TRIGGER_MaxCount > 4
90 } nrf_bellboard_event_t;
91
92 /** @brief BELLBOARD interrupts. */
93 typedef enum
94 {
95 NRF_BELLBOARD_INT_TRIGGERED_0_MASK = BELLBOARD_INTENSET0_TRIGGERED0_Msk, /**< Triggered 0 interrupt mask. */
96 NRF_BELLBOARD_INT_TRIGGERED_1_MASK = BELLBOARD_INTENSET0_TRIGGERED1_Msk, /**< Triggered 1 interrupt mask. */
97 NRF_BELLBOARD_INT_TRIGGERED_2_MASK = BELLBOARD_INTENSET0_TRIGGERED2_Msk, /**< Triggered 2 interrupt mask. */
98 NRF_BELLBOARD_INT_TRIGGERED_3_MASK = BELLBOARD_INTENSET0_TRIGGERED3_Msk, /**< Triggered 3 interrupt mask. */
99 #if NRF_BELLBOARD_EVENTS_TRIGGERED_COUNT > 4
100 NRF_BELLBOARD_INT_TRIGGERED_4_MASK = BELLBOARD_INTENSET0_TRIGGERED4_Msk, /**< Triggered 4 interrupt mask. */
101 NRF_BELLBOARD_INT_TRIGGERED_5_MASK = BELLBOARD_INTENSET0_TRIGGERED5_Msk, /**< Triggered 5 interrupt mask. */
102 NRF_BELLBOARD_INT_TRIGGERED_6_MASK = BELLBOARD_INTENSET0_TRIGGERED6_Msk, /**< Triggered 6 interrupt mask. */
103 NRF_BELLBOARD_INT_TRIGGERED_7_MASK = BELLBOARD_INTENSET0_TRIGGERED7_Msk, /**< Triggered 7 interrupt mask. */
104 NRF_BELLBOARD_INT_TRIGGERED_8_MASK = BELLBOARD_INTENSET0_TRIGGERED8_Msk, /**< Triggered 8 interrupt mask. */
105 NRF_BELLBOARD_INT_TRIGGERED_9_MASK = BELLBOARD_INTENSET0_TRIGGERED9_Msk, /**< Triggered 9 interrupt mask. */
106 NRF_BELLBOARD_INT_TRIGGERED_10_MASK = BELLBOARD_INTENSET0_TRIGGERED10_Msk, /**< Triggered 10 interrupt mask. */
107 NRF_BELLBOARD_INT_TRIGGERED_11_MASK = BELLBOARD_INTENSET0_TRIGGERED11_Msk, /**< Triggered 11 interrupt mask. */
108 NRF_BELLBOARD_INT_TRIGGERED_12_MASK = BELLBOARD_INTENSET0_TRIGGERED12_Msk, /**< Triggered 12 interrupt mask. */
109 NRF_BELLBOARD_INT_TRIGGERED_13_MASK = BELLBOARD_INTENSET0_TRIGGERED13_Msk, /**< Triggered 13 interrupt mask. */
110 NRF_BELLBOARD_INT_TRIGGERED_14_MASK = BELLBOARD_INTENSET0_TRIGGERED14_Msk, /**< Triggered 14 interrupt mask. */
111 NRF_BELLBOARD_INT_TRIGGERED_15_MASK = BELLBOARD_INTENSET0_TRIGGERED15_Msk, /**< Triggered 15 interrupt mask. */
112 NRF_BELLBOARD_INT_TRIGGERED_16_MASK = BELLBOARD_INTENSET0_TRIGGERED16_Msk, /**< Triggered 16 interrupt mask. */
113 NRF_BELLBOARD_INT_TRIGGERED_17_MASK = BELLBOARD_INTENSET0_TRIGGERED17_Msk, /**< Triggered 17 interrupt mask. */
114 NRF_BELLBOARD_INT_TRIGGERED_18_MASK = BELLBOARD_INTENSET0_TRIGGERED18_Msk, /**< Triggered 18 interrupt mask. */
115 NRF_BELLBOARD_INT_TRIGGERED_19_MASK = BELLBOARD_INTENSET0_TRIGGERED19_Msk, /**< Triggered 19 interrupt mask. */
116 NRF_BELLBOARD_INT_TRIGGERED_20_MASK = BELLBOARD_INTENSET0_TRIGGERED20_Msk, /**< Triggered 20 interrupt mask. */
117 NRF_BELLBOARD_INT_TRIGGERED_21_MASK = BELLBOARD_INTENSET0_TRIGGERED21_Msk, /**< Triggered 21 interrupt mask. */
118 NRF_BELLBOARD_INT_TRIGGERED_22_MASK = BELLBOARD_INTENSET0_TRIGGERED22_Msk, /**< Triggered 22 interrupt mask. */
119 NRF_BELLBOARD_INT_TRIGGERED_23_MASK = BELLBOARD_INTENSET0_TRIGGERED23_Msk, /**< Triggered 23 interrupt mask. */
120 NRF_BELLBOARD_INT_TRIGGERED_24_MASK = BELLBOARD_INTENSET0_TRIGGERED24_Msk, /**< Triggered 24 interrupt mask. */
121 NRF_BELLBOARD_INT_TRIGGERED_25_MASK = BELLBOARD_INTENSET0_TRIGGERED25_Msk, /**< Triggered 25 interrupt mask. */
122 NRF_BELLBOARD_INT_TRIGGERED_26_MASK = BELLBOARD_INTENSET0_TRIGGERED26_Msk, /**< Triggered 26 interrupt mask. */
123 NRF_BELLBOARD_INT_TRIGGERED_27_MASK = BELLBOARD_INTENSET0_TRIGGERED27_Msk, /**< Triggered 27 interrupt mask. */
124 NRF_BELLBOARD_INT_TRIGGERED_28_MASK = BELLBOARD_INTENSET0_TRIGGERED28_Msk, /**< Triggered 28 interrupt mask. */
125 NRF_BELLBOARD_INT_TRIGGERED_29_MASK = BELLBOARD_INTENSET0_TRIGGERED29_Msk, /**< Triggered 29 interrupt mask. */
126 NRF_BELLBOARD_INT_TRIGGERED_30_MASK = BELLBOARD_INTENSET0_TRIGGERED30_Msk, /**< Triggered 30 interrupt mask. */
127 NRF_BELLBOARD_INT_TRIGGERED_31_MASK = BELLBOARD_INTENSET0_TRIGGERED31_Msk, /**< Triggered 31 interrupt mask. */
128 #endif // BELLBOARD_TASKS_TRIGGER_MaxCount > 4
129 } nrf_bellboard_int_mask_t;
130
131 /** @brief BELLBOARD tasks. */
132 typedef enum
133 {
134 NRF_BELLBOARD_TASK_TRIGGER_0 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[0]), /**< Trigger 0 task. */
135 NRF_BELLBOARD_TASK_TRIGGER_1 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[1]), /**< Trigger 1 task. */
136 NRF_BELLBOARD_TASK_TRIGGER_2 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[2]), /**< Trigger 2 task. */
137 NRF_BELLBOARD_TASK_TRIGGER_3 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[3]), /**< Trigger 3 task. */
138 NRF_BELLBOARD_TASK_TRIGGER_4 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[4]), /**< Trigger 4 task. */
139 #if NRF_BELLBOARD_EVENTS_TRIGGERED_COUNT > 4
140 NRF_BELLBOARD_TASK_TRIGGER_5 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[5]), /**< Trigger 5 task. */
141 NRF_BELLBOARD_TASK_TRIGGER_6 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[6]), /**< Trigger 6 task. */
142 NRF_BELLBOARD_TASK_TRIGGER_7 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[7]), /**< Trigger 7 task. */
143 NRF_BELLBOARD_TASK_TRIGGER_8 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[8]), /**< Trigger 8 task. */
144 NRF_BELLBOARD_TASK_TRIGGER_9 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[9]), /**< Trigger 9 task. */
145 NRF_BELLBOARD_TASK_TRIGGER_10 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[10]), /**< Trigger 10 task. */
146 NRF_BELLBOARD_TASK_TRIGGER_11 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[11]), /**< Trigger 11 task. */
147 NRF_BELLBOARD_TASK_TRIGGER_12 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[12]), /**< Trigger 12 task. */
148 NRF_BELLBOARD_TASK_TRIGGER_13 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[13]), /**< Trigger 13 task. */
149 NRF_BELLBOARD_TASK_TRIGGER_14 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[14]), /**< Trigger 14 task. */
150 NRF_BELLBOARD_TASK_TRIGGER_15 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[15]), /**< Trigger 15 task. */
151 NRF_BELLBOARD_TASK_TRIGGER_16 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[16]), /**< Trigger 16 task. */
152 NRF_BELLBOARD_TASK_TRIGGER_17 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[17]), /**< Trigger 17 task. */
153 NRF_BELLBOARD_TASK_TRIGGER_18 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[18]), /**< Trigger 18 task. */
154 NRF_BELLBOARD_TASK_TRIGGER_19 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[19]), /**< Trigger 19 task. */
155 NRF_BELLBOARD_TASK_TRIGGER_20 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[20]), /**< Trigger 20 task. */
156 NRF_BELLBOARD_TASK_TRIGGER_21 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[21]), /**< Trigger 21 task. */
157 NRF_BELLBOARD_TASK_TRIGGER_22 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[22]), /**< Trigger 22 task. */
158 NRF_BELLBOARD_TASK_TRIGGER_23 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[23]), /**< Trigger 23 task. */
159 NRF_BELLBOARD_TASK_TRIGGER_24 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[24]), /**< Trigger 24 task. */
160 NRF_BELLBOARD_TASK_TRIGGER_25 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[25]), /**< Trigger 25 task. */
161 NRF_BELLBOARD_TASK_TRIGGER_26 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[26]), /**< Trigger 26 task. */
162 NRF_BELLBOARD_TASK_TRIGGER_27 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[27]), /**< Trigger 27 task. */
163 NRF_BELLBOARD_TASK_TRIGGER_28 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[28]), /**< Trigger 28 task. */
164 NRF_BELLBOARD_TASK_TRIGGER_29 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[29]), /**< Trigger 29 task. */
165 NRF_BELLBOARD_TASK_TRIGGER_30 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[30]), /**< Trigger 30 task. */
166 NRF_BELLBOARD_TASK_TRIGGER_31 = offsetof(NRF_BELLBOARD_Type, TASKS_TRIGGER[31]), /**< Trigger 31 task. */
167 #endif // BELLBOARD_TASKS_TRIGGER_MaxCount > 4
168 } nrf_bellboard_task_t;
169
170 /**
171 * @brief Function for triggering the specified BELLBOARD task.
172 *
173 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
174 * @param[in] task Task to be triggered.
175 */
176 NRF_STATIC_INLINE void nrf_bellboard_task_trigger(NRF_BELLBOARD_Type * p_reg,
177 nrf_bellboard_task_t task);
178
179 /**
180 * @brief Function for getting the address of the specified BELLBOARD task register.
181 *
182 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
183 * @param[in] task Specified task.
184 *
185 * @return Address of the specified task register.
186 */
187 NRF_STATIC_INLINE uint32_t nrf_bellboard_task_address_get(NRF_BELLBOARD_Type const * p_reg,
188 nrf_bellboard_task_t task);
189
190 /**
191 * @brief Function for getting the specified BELLBOARD TRIGGERED event.
192 *
193 * @param[in] index Event index.
194 *
195 * @return The specified BELLBOARD TRIGGERED event.
196 */
197 NRF_STATIC_INLINE nrf_bellboard_event_t nrf_bellboard_triggered_event_get(uint8_t index);
198
199 /**
200 * @brief Function for getting the specified BELLBOARD TRIGGER task.
201 *
202 * @param[in] index Task index.
203 *
204 * @return The specified BELLBOARD TRIGGER task.
205 */
206 NRF_STATIC_INLINE nrf_bellboard_task_t nrf_bellboard_trigger_task_get(uint8_t index);
207
208 /**
209 * @brief Function for clearing the specified BELLBOARD event.
210 *
211 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
212 * @param[in] event Event to clear.
213 */
214 NRF_STATIC_INLINE void nrf_bellboard_event_clear(NRF_BELLBOARD_Type * p_reg,
215 nrf_bellboard_event_t event);
216
217 /**
218 * @brief Function for retrieving the state of the BELLBOARD event.
219 *
220 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
221 * @param[in] event Event to be checked.
222 *
223 * @retval true The event has been generated.
224 * @retval false The event has not been generated.
225 */
226 NRF_STATIC_INLINE bool nrf_bellboard_event_check(NRF_BELLBOARD_Type const * p_reg,
227 nrf_bellboard_event_t event);
228
229 /**
230 * @brief Function for getting the address of the specified BELLBOARD event register.
231 *
232 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
233 * @param[in] event Specified event.
234 *
235 * @return Address of the specified event register.
236 */
237 NRF_STATIC_INLINE uint32_t nrf_bellboard_event_address_get(NRF_BELLBOARD_Type const * p_reg,
238 nrf_bellboard_event_t event);
239
240 /**
241 * @brief Function for enabling specified interrupts.
242 *
243 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
244 * @param[in] group_idx Index of interrupt group to be enabled.
245 * @param[in] mask Mask of interrupts to be enabled.
246 * Use @ref nrf_bellboard_int_mask_t values for bit masking.
247 */
248 NRF_STATIC_INLINE void nrf_bellboard_int_enable(NRF_BELLBOARD_Type * p_reg,
249 uint8_t group_idx,
250 uint32_t mask);
251
252 /**
253 * @brief Function for disabling specified interrupts.
254 *
255 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
256 * @param[in] group_idx Index of interrupt group to be disabled.
257 * @param[in] mask Mask of interrupts to be disabled.
258 * Use @ref nrf_bellboard_int_mask_t values for bit masking.
259 */
260 NRF_STATIC_INLINE void nrf_bellboard_int_disable(NRF_BELLBOARD_Type * p_reg,
261 uint8_t group_idx,
262 uint32_t mask);
263
264
265 /**
266 * @brief Function for checking if the specified interrupts are enabled.
267 *
268 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
269 * @param[in] group_idx Index of interrupt group to be checked.
270 * @param[in] mask Mask of interrupts to be checked.
271 * Use @ref nrf_bellboard_int_mask_t values for bit masking.
272 *
273 * @return Mask of enabled interrupts.
274 */
275 NRF_STATIC_INLINE uint32_t nrf_bellboard_int_enable_check(NRF_BELLBOARD_Type const * p_reg,
276 uint8_t group_idx,
277 uint32_t mask);
278
279 /**
280 * @brief Function for retrieving the state of pending interrupts.
281 *
282 * States of pending interrupt are saved as a bitmask.
283 * One set at particular position means that interrupt for event is pending.
284 *
285 * @param[in] p_reg Pointer to the structure of registers of the peripheral.
286 * @param[in] group_idx Index of interrupt group to be retrieved.
287 *
288 * @return Bitmask with information about pending interrupts.
289 * Use @ref nrf_bellboard_int_mask_t values for bit masking.
290 */
291 NRF_STATIC_INLINE uint32_t nrf_bellboard_int_pending_get(NRF_BELLBOARD_Type const * p_reg,
292 uint8_t group_idx);
293
294 #ifndef NRF_DECLARE_ONLY
nrf_bellboard_task_trigger(NRF_BELLBOARD_Type * p_reg,nrf_bellboard_task_t task)295 NRF_STATIC_INLINE void nrf_bellboard_task_trigger(NRF_BELLBOARD_Type * p_reg,
296 nrf_bellboard_task_t task)
297 {
298 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
299 }
300
nrf_bellboard_task_address_get(NRF_BELLBOARD_Type const * p_reg,nrf_bellboard_task_t task)301 NRF_STATIC_INLINE uint32_t nrf_bellboard_task_address_get(NRF_BELLBOARD_Type const * p_reg,
302 nrf_bellboard_task_t task)
303 {
304 return nrf_task_event_address_get(p_reg, task);
305 }
306
nrf_bellboard_triggered_event_get(uint8_t index)307 NRF_STATIC_INLINE nrf_bellboard_event_t nrf_bellboard_triggered_event_get(uint8_t index)
308 {
309 return (nrf_bellboard_event_t)NRFX_OFFSETOF(NRF_BELLBOARD_Type, EVENTS_TRIGGERED[index]);
310 }
311
nrf_bellboard_trigger_task_get(uint8_t index)312 NRF_STATIC_INLINE nrf_bellboard_task_t nrf_bellboard_trigger_task_get(uint8_t index)
313 {
314 return (nrf_bellboard_task_t)NRFX_OFFSETOF(NRF_BELLBOARD_Type, TASKS_TRIGGER[index]);
315 }
316
nrf_bellboard_event_clear(NRF_BELLBOARD_Type * p_reg,nrf_bellboard_event_t event)317 NRF_STATIC_INLINE void nrf_bellboard_event_clear(NRF_BELLBOARD_Type * p_reg,
318 nrf_bellboard_event_t event)
319 {
320 *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
321 }
322
nrf_bellboard_event_check(NRF_BELLBOARD_Type const * p_reg,nrf_bellboard_event_t event)323 NRF_STATIC_INLINE bool nrf_bellboard_event_check(NRF_BELLBOARD_Type const * p_reg,
324 nrf_bellboard_event_t event)
325 {
326 return nrf_event_check(p_reg, event);
327 }
328
nrf_bellboard_event_address_get(NRF_BELLBOARD_Type const * p_reg,nrf_bellboard_event_t event)329 NRF_STATIC_INLINE uint32_t nrf_bellboard_event_address_get(NRF_BELLBOARD_Type const * p_reg,
330 nrf_bellboard_event_t event)
331 {
332 return nrf_task_event_address_get(p_reg, event);
333 }
334
nrf_bellboard_int_enable(NRF_BELLBOARD_Type * p_reg,uint8_t group_idx,uint32_t mask)335 NRF_STATIC_INLINE void nrf_bellboard_int_enable(NRF_BELLBOARD_Type * p_reg,
336 uint8_t group_idx,
337 uint32_t mask)
338 {
339 switch (group_idx)
340 {
341 case 0:
342 p_reg->INTENSET0 = mask;
343 break;
344 case 1:
345 p_reg->INTENSET1 = mask;
346 break;
347 case 2:
348 p_reg->INTENSET2 = mask;
349 break;
350 case 3:
351 p_reg->INTENSET3 = mask;
352 break;
353 default:
354 NRFX_ASSERT(false);
355 break;
356 }
357 }
358
nrf_bellboard_int_disable(NRF_BELLBOARD_Type * p_reg,uint8_t group_idx,uint32_t mask)359 NRF_STATIC_INLINE void nrf_bellboard_int_disable(NRF_BELLBOARD_Type * p_reg,
360 uint8_t group_idx,
361 uint32_t mask)
362 {
363 switch (group_idx)
364 {
365 case 0:
366 p_reg->INTENCLR0 = mask;
367 break;
368 case 1:
369 p_reg->INTENCLR1 = mask;
370 break;
371 case 2:
372 p_reg->INTENCLR2 = mask;
373 break;
374 case 3:
375 p_reg->INTENCLR3 = mask;
376 break;
377 default:
378 NRFX_ASSERT(false);
379 break;
380 }
381 }
382
nrf_bellboard_int_enable_check(NRF_BELLBOARD_Type const * p_reg,uint8_t group_idx,uint32_t mask)383 NRF_STATIC_INLINE uint32_t nrf_bellboard_int_enable_check(NRF_BELLBOARD_Type const * p_reg,
384 uint8_t group_idx,
385 uint32_t mask)
386 {
387 switch (group_idx)
388 {
389 case 0:
390 return p_reg->INTENSET0 & mask;
391 case 1:
392 return p_reg->INTENSET1 & mask;
393 case 2:
394 return p_reg->INTENSET2 & mask;
395 case 3:
396 return p_reg->INTENSET3 & mask;
397 default:
398 NRFX_ASSERT(false);
399 return 0;
400 }
401 }
402
nrf_bellboard_int_pending_get(NRF_BELLBOARD_Type const * p_reg,uint8_t group_idx)403 NRF_STATIC_INLINE uint32_t nrf_bellboard_int_pending_get(NRF_BELLBOARD_Type const * p_reg,
404 uint8_t group_idx)
405 {
406 switch (group_idx)
407 {
408 case 0:
409 return p_reg->INTPEND0;
410 case 1:
411 return p_reg->INTPEND1;
412 case 2:
413 return p_reg->INTPEND2;
414 case 3:
415 return p_reg->INTPEND3;
416 default:
417 NRFX_ASSERT(false);
418 return 0;
419 }
420 }
421
422 #endif // NRF_DECLARE_ONLY
423
424 /** @} */
425
426 #ifdef __cplusplus
427 }
428 #endif
429
430 #endif // NRF_BELLBOARD_H__
431
