1 /*
2 * Copyright (c) 2020 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nuvoton_npcx_espi
8
9 #include <assert.h>
10 #include <stdlib.h>
11 #include <zephyr/drivers/espi.h>
12 #include <zephyr/drivers/gpio.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/drivers/pinctrl.h>
15 #include <zephyr/dt-bindings/espi/npcx_espi.h>
16 #include <zephyr/kernel.h>
17 #include <zephyr/sys/byteorder.h>
18 #include <zephyr/sys/util.h>
19 #include <soc.h>
20 #include "espi_utils.h"
21 #include "soc_host.h"
22 #include "soc_miwu.h"
23
24 #include <zephyr/logging/log.h>
25 #include <zephyr/irq.h>
26 LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
27
28 struct espi_npcx_config {
29 uintptr_t base;
30 /* clock configuration */
31 struct npcx_clk_cfg clk_cfg;
32 /* mapping table between eSPI reset signal and wake-up input */
33 struct npcx_wui espi_rst_wui;
34 /* pinmux configuration */
35 const struct pinctrl_dev_config *pcfg;
36 };
37
38 struct espi_npcx_data {
39 sys_slist_t callbacks;
40 uint8_t plt_rst_asserted;
41 uint8_t espi_rst_level;
42 uint8_t sx_state;
43 #if !defined(CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC)
44 struct k_sem oob_rx_lock;
45 #endif
46 #if defined(CONFIG_ESPI_FLASH_CHANNEL)
47 struct k_sem flash_rx_lock;
48 #endif
49 #ifdef CONFIG_ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND
50 /* tell the interrupt handler that it is a fake request */
51 bool fake_req_flag;
52 #endif
53 };
54
55 #if DT_NODE_HAS_PROP(DT_DRV_INST(0), vw_index_extend_set)
56 struct espi_npcx_vw_ex {
57 uint8_t direction;
58 uint8_t group_num;
59 uint8_t index;
60 };
61
62 /* n = node, p = property, i = index */
63 #define ESPI_NPCX_VW_EX_INFO(n, p, i) \
64 { \
65 .index = ESPI_NPCX_VW_EX_INDEX(DT_PROP_BY_IDX(n, p, i)), \
66 .group_num = ESPI_NPCX_VW_EX_GROUP_NUM(DT_PROP_BY_IDX(n, p, i)), \
67 .direction = ESPI_NPCX_VW_EX_DIR(DT_PROP_BY_IDX(n, p, i)), \
68 },
69
70 static const struct espi_npcx_vw_ex espi_npcx_vw_ex_0[] = {
71 DT_FOREACH_PROP_ELEM(DT_DRV_INST(0), vw_index_extend_set, ESPI_NPCX_VW_EX_INFO)
72 };
73 #endif
74
75 /* Driver convenience defines */
76 #define HAL_INSTANCE(dev) \
77 ((struct espi_reg *)((const struct espi_npcx_config *)(dev)->config)->base)
78
79 /* eSPI channels */
80 #define NPCX_ESPI_CH_PC 0
81 #define NPCX_ESPI_CH_VW 1
82 #define NPCX_ESPI_CH_OOB 2
83 #define NPCX_ESPI_CH_FLASH 3
84 #define NPCX_ESPI_CH_COUNT 4
85 #define NPCX_ESPI_HOST_CH_EN(ch) (ch + 4)
86
87 /* eSPI max supported frequency */
88 #define NPCX_ESPI_MAXFREQ_20 0
89 #define NPCX_ESPI_MAXFREQ_25 1
90 #define NPCX_ESPI_MAXFREQ_33 2
91 #define NPCX_ESPI_MAXFREQ_50 3
92 #define NPCX_ESPI_MAXFREQ_66 4
93
94 /* Minimum delay before acknowledging a virtual wire */
95 #define NPCX_ESPI_VWIRE_ACK_DELAY 10ul /* 10 us */
96
97 /* OOB channel maximum payload size */
98 #define NPCX_ESPI_OOB_MAX_PAYLOAD 64
99 #define NPCX_OOB_RX_PACKAGE_LEN(hdr) (((hdr & 0xff000000) >> 24) | \
100 ((hdr & 0xf0000) >> 8))
101
102 /* Flash channel maximum payload size */
103 #define NPCX_ESPI_FLASH_MAX_RX_PAYLOAD DT_INST_PROP(0, rx_plsize)
104 #define NPCX_ESPI_FLASH_MAX_TX_PAYLOAD DT_INST_PROP(0, tx_plsize)
105
106 /* eSPI cycle type field for OOB and FLASH channels */
107 #define ESPI_FLASH_READ_CYCLE_TYPE 0x00
108 #define ESPI_FLASH_WRITE_CYCLE_TYPE 0x01
109 #define ESPI_FLASH_ERASE_CYCLE_TYPE 0x02
110 #define ESPI_FLASH_SUCCESS_WITH_DATA_CYCLE_TYPE 0x0f
111 #define ESPI_FLASH_SUCCESS_WITHOUT_DATA_CYCLE_TYPE 0x06
112 #define ESPI_FLASH_HEADER_PCKT_SIZE 0x07
113 #define ESPI_FLASH_MAX_TIMEOUT 1000ul /* 1000 ms */
114 #define ESPI_OOB_GET_CYCLE_TYPE 0x21
115 #define ESPI_OOB_TAG 0x00
116 #define ESPI_OOB_MAX_TIMEOUT 500ul /* 500 ms */
117
118 /* eSPI bus interrupt configuration structure and macro function */
119 struct espi_bus_isr {
120 uint8_t status_bit; /* bit order in ESPISTS register */
121 uint8_t int_en_bit; /* bit order in ESPIIE register */
122 uint8_t wake_en_bit; /* bit order in ESPIWE register */
123 void (*bus_isr)(const struct device *dev); /* eSPI bus ISR */
124 };
125
126 #define NPCX_ESPI_BUS_INT_ITEM(event, isr) { \
127 .status_bit = NPCX_ESPISTS_##event, \
128 .int_en_bit = NPCX_ESPIIE_##event##IE, \
129 .wake_en_bit = NPCX_ESPIWE_##event##WE, \
130 .bus_isr = isr }
131
132 /* eSPI Virtual Wire Input (Master-to-Slave) signals configuration structure */
133 struct npcx_vw_in_config {
134 enum espi_vwire_signal sig; /* Virtual Wire signal */
135 uint8_t reg_idx; /* register index for VW signal */
136 uint8_t bitmask; /* VW signal bits-mask */
137 struct npcx_wui vw_wui; /* WUI mapping in MIWU modules for VW signal */
138 };
139
140 /* eSPI Virtual Wire Output (Slave-to-Master) signals configuration structure */
141 struct npcx_vw_out_config {
142 enum espi_vwire_signal sig; /* Virtual Wire signal */
143 uint8_t reg_idx; /* register index for VW signal */
144 uint8_t bitmask; /* VW signal bits-mask */
145 };
146
147 /*
148 * eSPI VW input/Output signal configuration tables. Please refer
149 * npcxn-espi-vws-map.dtsi device tree file for more detail.
150 */
151 static const struct npcx_vw_in_config vw_in_tbl[] = {
152 /* index 02h (In) */
153 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_S3, vw_slp_s3),
154 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_S4, vw_slp_s4),
155 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_S5, vw_slp_s5),
156 /* index 03h (In) */
157 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SUS_STAT, vw_sus_stat),
158 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_PLTRST, vw_plt_rst),
159 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_OOB_RST_WARN, vw_oob_rst_warn),
160 /* index 07h (In) */
161 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_HOST_RST_WARN, vw_host_rst_warn),
162 /* index 41h (In) */
163 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SUS_WARN, vw_sus_warn),
164 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SUS_PWRDN_ACK, vw_sus_pwrdn_ack),
165 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_A, vw_slp_a),
166 /* index 42h (In) */
167 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_LAN, vw_slp_lan),
168 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_WLAN, vw_slp_wlan),
169 #if DT_NODE_EXISTS(DT_CHILD(DT_PATH(npcx_espi_vws_map), vw_dnx_warn))
170 /* index 4Ah (In) */
171 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_DNX_WARN, vw_dnx_warn),
172 #endif
173 };
174
175 static const struct npcx_vw_out_config vw_out_tbl[] = {
176 /* index 04h (Out) */
177 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_OOB_RST_ACK, vw_oob_rst_ack),
178 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_WAKE, vw_wake),
179 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_PME, vw_pme),
180 /* index 05h (Out) */
181 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_BOOT_DONE, vw_slv_boot_done),
182 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_ERR_FATAL, vw_err_fatal),
183 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_ERR_NON_FATAL, vw_err_non_fatal),
184 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_BOOT_STS,
185 vw_slv_boot_sts_with_done),
186 /* index 06h (Out) */
187 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SCI, vw_sci),
188 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SMI, vw_smi),
189 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_HOST_RST_ACK, vw_host_rst_ack),
190 /* index 40h (Out) */
191 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SUS_ACK, vw_sus_ack),
192 #if DT_NODE_EXISTS(DT_CHILD(DT_PATH(npcx_espi_vws_map), vw_dnx_ack))
193 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_DNX_ACK, vw_dnx_ack),
194 #endif
195 };
196
197 /* Virtual wire GPIOs for platform level usage (High at Reset state) */
198 static const struct npcx_vw_out_config vw_out_gpio_tbl1[] = {
199 /* Only NPCX9 and later series support this feature */
200 #if defined(CONFIG_ESPI_NPCX_SUPP_VW_GPIO)
201 /* index 50h (Out) */
202 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_0, vw_slv_gpio_0),
203 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_1, vw_slv_gpio_1),
204 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_2, vw_slv_gpio_2),
205 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_3, vw_slv_gpio_3),
206 /* index 51h (Out) */
207 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_4, vw_slv_gpio_4),
208 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_5, vw_slv_gpio_5),
209 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_6, vw_slv_gpio_6),
210 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_7, vw_slv_gpio_7),
211 #endif
212 };
213
214 /* Callbacks for eSPI bus reset and Virtual Wire signals. */
215 static struct miwu_callback espi_rst_callback;
216 static struct miwu_callback vw_in_callback[ARRAY_SIZE(vw_in_tbl)];
217
218 /* eSPI VW service function forward declarations */
219 static int espi_npcx_receive_vwire(const struct device *dev,
220 enum espi_vwire_signal signal, uint8_t *level);
221 static int espi_npcx_send_vwire(const struct device *dev,
222 enum espi_vwire_signal signal, uint8_t level);
223 static void espi_vw_send_bootload_done(const struct device *dev);
224
225 #if defined(CONFIG_ESPI_FLASH_CHANNEL)
226 static int espi_npcx_flash_parse_completion_with_data(const struct device *dev,
227 struct espi_flash_packet *pckt);
228 static void espi_npcx_flash_prepare_tx_header(const struct device *dev, int cyc_type,
229 int flash_addr, int flash_len, int tx_payload);
230 #endif
231
232 /* eSPI local initialization functions */
espi_init_wui_callback(const struct device * dev,struct miwu_callback * callback,const struct npcx_wui * wui,miwu_dev_callback_handler_t handler)233 static void espi_init_wui_callback(const struct device *dev,
234 struct miwu_callback *callback, const struct npcx_wui *wui,
235 miwu_dev_callback_handler_t handler)
236 {
237 /* VW signal which has no wake-up input source */
238 if (wui->table == NPCX_MIWU_TABLE_NONE) {
239 return;
240 }
241
242 /* Install callback function */
243 npcx_miwu_init_dev_callback(callback, wui, handler, dev);
244 npcx_miwu_manage_callback(callback, 1);
245
246 /* Configure MIWU setting and enable its interrupt */
247 npcx_miwu_interrupt_configure(wui, NPCX_MIWU_MODE_EDGE,
248 NPCX_MIWU_TRIG_BOTH);
249 }
250
251 /* eSPI local bus interrupt service functions */
espi_bus_err_isr(const struct device * dev)252 static void espi_bus_err_isr(const struct device *dev)
253 {
254 struct espi_reg *const inst = HAL_INSTANCE(dev);
255 uint32_t err = inst->ESPIERR;
256
257 LOG_ERR("eSPI Bus Error %08X", err);
258 /* Clear error status bits */
259 inst->ESPIERR = err;
260 }
261
espi_bus_inband_rst_isr(const struct device * dev)262 static void espi_bus_inband_rst_isr(const struct device *dev)
263 {
264 ARG_UNUSED(dev);
265 LOG_DBG("%s issued", __func__);
266 }
267
espi_bus_reset_isr(const struct device * dev)268 static void espi_bus_reset_isr(const struct device *dev)
269 {
270 ARG_UNUSED(dev);
271 LOG_DBG("%s issued", __func__);
272 /* Do nothing! This signal is handled in ESPI_RST VW signal ISR */
273 }
274
275 #if defined(CONFIG_ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND)
espi_npcx_flash_fake_request(const struct device * dev)276 static void espi_npcx_flash_fake_request(const struct device *dev)
277 {
278 struct espi_reg *const inst = HAL_INSTANCE(dev);
279 struct espi_npcx_data *const data = dev->data;
280
281 inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_AMTEN);
282
283 data->fake_req_flag = true;
284
285 espi_npcx_flash_prepare_tx_header(dev, ESPI_FLASH_READ_CYCLE_TYPE, 0, 16, 0);
286 }
287 #endif
288
espi_bus_cfg_update_isr(const struct device * dev)289 static void espi_bus_cfg_update_isr(const struct device *dev)
290 {
291 int chan;
292 struct espi_reg *const inst = HAL_INSTANCE(dev);
293 struct espi_npcx_data *const data = dev->data;
294 struct espi_event evt = { .evt_type = ESPI_BUS_EVENT_CHANNEL_READY,
295 .evt_details = 0,
296 .evt_data = 0 };
297 /* If host enable bits are not sync with ready bits on slave side. */
298 uint8_t chg_mask = GET_FIELD(inst->ESPICFG, NPCX_ESPICFG_HCHANS_FIELD)
299 ^ GET_FIELD(inst->ESPICFG, NPCX_ESPICFG_CHANS_FIELD);
300 chg_mask &= (ESPI_CHANNEL_VWIRE | ESPI_CHANNEL_OOB |
301 ESPI_CHANNEL_FLASH);
302
303 LOG_DBG("ESPI CFG Change Updated! 0x%02X", chg_mask);
304 /*
305 * If host enable/disable channel for VW/OOB/FLASH, EC should follow
306 * except Peripheral channel. It is handled after receiving PLTRST
307 * event separately.
308 */
309 for (chan = NPCX_ESPI_CH_VW; chan < NPCX_ESPI_CH_COUNT; chan++) {
310 /* Channel ready bit isn't sync with enabled bit on host side */
311 if (chg_mask & BIT(chan)) {
312 evt.evt_data = IS_BIT_SET(inst->ESPICFG,
313 NPCX_ESPI_HOST_CH_EN(chan));
314 evt.evt_details = BIT(chan);
315
316 #if defined(CONFIG_ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND)
317 if (chan == NPCX_ESPI_CH_FLASH && evt.evt_data == 1 &&
318 IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_FLASH_TX_AVAIL)) {
319 espi_npcx_flash_fake_request(dev);
320 }
321 #endif
322
323 if (evt.evt_data) {
324 inst->ESPICFG |= BIT(chan);
325 } else {
326 inst->ESPICFG &= ~BIT(chan);
327 }
328
329 espi_send_callbacks(&data->callbacks, dev, evt);
330 }
331 }
332 LOG_DBG("ESPI CFG EC Updated! 0x%02X", GET_FIELD(inst->ESPICFG,
333 NPCX_ESPICFG_CHANS_FIELD));
334
335 /* If VW channel is enabled and ready, send bootload done VW signal */
336 if ((chg_mask & BIT(NPCX_ESPI_CH_VW)) && IS_BIT_SET(inst->ESPICFG,
337 NPCX_ESPI_HOST_CH_EN(NPCX_ESPI_CH_VW))) {
338 espi_vw_send_bootload_done(dev);
339 }
340
341 #if (defined(CONFIG_ESPI_FLASH_CHANNEL) && defined(CONFIG_ESPI_TAF))
342 /* If CONFIG_ESPI_TAF is set, set to auto or manual mode accroding
343 * to configuration.
344 */
345 if (IS_BIT_SET(inst->ESPICFG, NPCX_ESPICFG_FLCHANMODE)) {
346 #if defined(CONFIG_ESPI_TAF_AUTO_MODE)
347 inst->FLASHCTL |= BIT(NPCX_FLASHCTL_SAF_AUTO_READ);
348 #else
349 inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_SAF_AUTO_READ);
350 #endif
351 }
352 #endif
353 }
354
355 #if defined(CONFIG_ESPI_OOB_CHANNEL)
espi_bus_oob_rx_isr(const struct device * dev)356 static void espi_bus_oob_rx_isr(const struct device *dev)
357 {
358 struct espi_npcx_data *const data = dev->data;
359 #if defined(CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC)
360 struct espi_reg *const inst = HAL_INSTANCE(dev);
361 struct espi_event evt = {
362 .evt_type = ESPI_BUS_EVENT_OOB_RECEIVED,
363 .evt_details = 0,
364 .evt_data = 0,
365 };
366
367 /* Get received package length and set to additional detail of event */
368 evt.evt_details = NPCX_OOB_RX_PACKAGE_LEN(inst->OOBRXBUF[0]);
369 espi_send_callbacks(&data->callbacks, dev, evt);
370 #else
371
372 LOG_DBG("%s", __func__);
373 k_sem_give(&data->oob_rx_lock);
374 #endif
375 }
376 #endif
377
378 #if defined(CONFIG_ESPI_FLASH_CHANNEL)
379 #if defined(CONFIG_ESPI_TAF)
380 static struct espi_taf_pckt taf_pckt;
381
espi_taf_parse(const struct device * dev)382 static uint32_t espi_taf_parse(const struct device *dev)
383 {
384 struct espi_reg *const inst = HAL_INSTANCE(dev);
385 struct npcx_taf_head taf_head;
386 uint32_t taf_addr, head_data;
387 uint8_t i, roundsize;
388
389 /* Get type, length and tag from RX buffer */
390 head_data = inst->FLASHRXBUF[0];
391 taf_head = *(struct npcx_taf_head *)&head_data;
392
393 taf_pckt.type = taf_head.type;
394 taf_pckt.len = (((uint16_t)taf_head.tag_hlen & 0xF) << 8) | taf_head.llen;
395 taf_pckt.tag = taf_head.tag_hlen >> 4;
396
397 if ((taf_pckt.len == 0) && (taf_pckt.type == NPCX_ESPI_TAF_REQ_READ)) {
398 taf_pckt.len = KB(4);
399 }
400
401 /* Get address from RX buffer */
402 taf_addr = inst->FLASHRXBUF[1];
403 taf_pckt.addr = sys_cpu_to_be32(taf_addr);
404
405 /* Get written data if eSPI TAF write or RPMC OP1 */
406 if ((taf_pckt.type == NPCX_ESPI_TAF_REQ_WRITE) ||
407 (IS_ENABLED(CONFIG_ESPI_TAF_NPCX_RPMC_SUPPORT) &&
408 (taf_pckt.type == NPCX_ESPI_TAF_REQ_RPMC_OP1))) {
409 roundsize = DIV_ROUND_UP(taf_pckt.len, sizeof(uint32_t));
410 for (i = 0; i < roundsize; i++) {
411 taf_pckt.src[i] = inst->FLASHRXBUF[2 + i];
412 }
413 }
414
415 return (uint32_t)&taf_pckt;
416 }
417 #endif /* CONFIG_ESPI_TAF */
418
espi_bus_flash_rx_isr(const struct device * dev)419 static void espi_bus_flash_rx_isr(const struct device *dev)
420 {
421 struct espi_reg *const inst = HAL_INSTANCE(dev);
422 struct espi_npcx_data *const data = dev->data;
423
424 /* Controller Attached Flash Access */
425 if ((inst->ESPICFG & BIT(NPCX_ESPICFG_FLCHANMODE)) == 0) {
426 #ifdef CONFIG_ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND
427 if (data->fake_req_flag == true) {
428 uint8_t pckt_buf[16];
429 struct espi_flash_packet pckt;
430
431 pckt.buf = &pckt_buf[0];
432 espi_npcx_flash_parse_completion_with_data(dev, &pckt);
433 data->fake_req_flag = false;
434 return;
435 }
436 #endif
437 k_sem_give(&data->flash_rx_lock);
438 } else { /* Target Attached Flash Access */
439 #if defined(CONFIG_ESPI_TAF)
440 struct espi_event evt = {
441 .evt_type = ESPI_BUS_TAF_NOTIFICATION,
442 .evt_details = ESPI_CHANNEL_FLASH,
443 .evt_data = espi_taf_parse(dev),
444 };
445 espi_send_callbacks(&data->callbacks, dev, evt);
446 #else
447 LOG_WRN("ESPI TAF not supported");
448 #endif
449 }
450 }
451 #endif /* CONFIG_ESPI_FLASH_CHANNEL */
452
453 const struct espi_bus_isr espi_bus_isr_tbl[] = {
454 NPCX_ESPI_BUS_INT_ITEM(BERR, espi_bus_err_isr),
455 NPCX_ESPI_BUS_INT_ITEM(IBRST, espi_bus_inband_rst_isr),
456 NPCX_ESPI_BUS_INT_ITEM(ESPIRST, espi_bus_reset_isr),
457 NPCX_ESPI_BUS_INT_ITEM(CFGUPD, espi_bus_cfg_update_isr),
458 #if defined(CONFIG_ESPI_OOB_CHANNEL)
459 NPCX_ESPI_BUS_INT_ITEM(OOBRX, espi_bus_oob_rx_isr),
460 #endif
461 #if defined(CONFIG_ESPI_FLASH_CHANNEL)
462 NPCX_ESPI_BUS_INT_ITEM(FLASHRX, espi_bus_flash_rx_isr),
463 #endif
464 };
465
espi_bus_generic_isr(const struct device * dev)466 static void espi_bus_generic_isr(const struct device *dev)
467 {
468 struct espi_reg *const inst = HAL_INSTANCE(dev);
469 int i;
470 uint32_t mask, status;
471
472 /*
473 * Bit 17 of ESPIIE is reserved. We need to set the same bit in mask
474 * in case bit 17 in ESPISTS of npcx7 is not cleared in ISR.
475 */
476 mask = inst->ESPIIE | (1 << NPCX_ESPISTS_VWUPDW);
477 status = inst->ESPISTS & mask;
478
479 /* Clear pending bits of status register first */
480 inst->ESPISTS = status;
481
482 LOG_DBG("%s: 0x%08X", __func__, status);
483 for (i = 0; i < ARRAY_SIZE(espi_bus_isr_tbl); i++) {
484 struct espi_bus_isr entry = espi_bus_isr_tbl[i];
485
486 if (status & BIT(entry.status_bit)) {
487 if (entry.bus_isr != NULL) {
488 entry.bus_isr(dev);
489 }
490 }
491 }
492 }
493
494 /* eSPI local virtual-wire service functions */
espi_vw_config_input(const struct device * dev,const struct npcx_vw_in_config * config_in)495 static void espi_vw_config_input(const struct device *dev,
496 const struct npcx_vw_in_config *config_in)
497 {
498 struct espi_reg *const inst = HAL_INSTANCE(dev);
499 int idx = config_in->reg_idx;
500
501 /* IE & WE bits are already set? */
502 if (IS_BIT_SET(inst->VWEVMS[idx], NPCX_VWEVMS_IE) &&
503 IS_BIT_SET(inst->VWEVMS[idx], NPCX_VWEVMS_WE)) {
504 return;
505 }
506
507 /* Set IE & WE bits in VWEVMS */
508 inst->VWEVMS[idx] |= BIT(NPCX_VWEVMS_IE) | BIT(NPCX_VWEVMS_WE);
509 LOG_DBG("VWEVMS%d 0x%08X", idx, inst->VWEVMS[idx]);
510 }
511
espi_vw_config_output(const struct device * dev,const struct npcx_vw_out_config * config_out)512 static void espi_vw_config_output(const struct device *dev,
513 const struct npcx_vw_out_config *config_out)
514 {
515 struct espi_reg *const inst = HAL_INSTANCE(dev);
516 int idx = config_out->reg_idx;
517 uint8_t valid = GET_FIELD(inst->VWEVSM[idx], NPCX_VWEVSM_VALID);
518
519 /* Set valid bits for vw signal which we have declared in table. */
520 valid |= config_out->bitmask;
521 SET_FIELD(inst->VWEVSM[idx], NPCX_VWEVSM_VALID, valid);
522
523 /*
524 * Turn off hardware-wire feature which generates VW events that
525 * connected to hardware signals. We will set it manually by software.
526 */
527 SET_FIELD(inst->VWEVSM[idx], NPCX_VWEVSM_HW_WIRE, 0);
528
529 LOG_DBG("VWEVSM%d 0x%08X", idx, inst->VWEVSM[idx]);
530 }
531
espi_vw_gpio_config_output(const struct device * dev,const struct npcx_vw_out_config * config_out,uint8_t init_level)532 static void espi_vw_gpio_config_output(const struct device *dev,
533 const struct npcx_vw_out_config *config_out,
534 uint8_t init_level)
535 {
536 struct espi_reg *const inst = HAL_INSTANCE(dev);
537 int idx = config_out->reg_idx;
538 uint8_t valid = GET_FIELD(inst->VWGPSM[idx], NPCX_VWEVSM_VALID);
539 uint8_t val = GET_FIELD(inst->VWGPSM[idx], NPCX_VWEVSM_WIRE);
540
541 /* Set valid bits for vw signal which we have declared in table. */
542 valid |= config_out->bitmask;
543 SET_FIELD(inst->VWGPSM[idx], NPCX_VWEVSM_VALID, valid);
544
545 inst->VWGPSM[idx] |= BIT(NPCX_VWGPSM_INDEX_EN);
546
547 if (init_level) {
548 val |= config_out->bitmask;
549 } else {
550 val &= ~config_out->bitmask;
551 }
552
553 SET_FIELD(inst->VWGPSM[idx], NPCX_VWEVSM_WIRE, val);
554
555 LOG_DBG("VWEVSM%d 0x%08X", idx, inst->VWGPSM[idx]);
556 }
557
espi_vw_notify_system_state(const struct device * dev,enum espi_vwire_signal signal)558 static void espi_vw_notify_system_state(const struct device *dev,
559 enum espi_vwire_signal signal)
560 {
561 struct espi_npcx_data *const data = dev->data;
562 struct espi_event evt = { ESPI_BUS_EVENT_VWIRE_RECEIVED, 0, 0 };
563 uint8_t wire = 0;
564
565 espi_npcx_receive_vwire(dev, signal, &wire);
566 if (!wire) {
567 data->sx_state = signal;
568 }
569
570 evt.evt_details = signal;
571 evt.evt_data = wire;
572 espi_send_callbacks(&data->callbacks, dev, evt);
573 }
574
espi_vw_notify_host_warning(const struct device * dev,enum espi_vwire_signal signal)575 static void espi_vw_notify_host_warning(const struct device *dev,
576 enum espi_vwire_signal signal)
577 {
578 uint8_t wire;
579
580 espi_npcx_receive_vwire(dev, signal, &wire);
581
582 k_busy_wait(NPCX_ESPI_VWIRE_ACK_DELAY);
583 switch (signal) {
584 case ESPI_VWIRE_SIGNAL_HOST_RST_WARN:
585 espi_npcx_send_vwire(dev,
586 ESPI_VWIRE_SIGNAL_HOST_RST_ACK,
587 wire);
588 break;
589 case ESPI_VWIRE_SIGNAL_SUS_WARN:
590 espi_npcx_send_vwire(dev, ESPI_VWIRE_SIGNAL_SUS_ACK,
591 wire);
592 break;
593 case ESPI_VWIRE_SIGNAL_OOB_RST_WARN:
594 espi_npcx_send_vwire(dev, ESPI_VWIRE_SIGNAL_OOB_RST_ACK,
595 wire);
596 break;
597 #if DT_NODE_EXISTS(DT_CHILD(DT_PATH(npcx_espi_vws_map), vw_dnx_warn))
598 case ESPI_VWIRE_SIGNAL_DNX_WARN:
599 espi_npcx_send_vwire(dev, ESPI_VWIRE_SIGNAL_DNX_ACK, wire);
600 break;
601 #endif
602 default:
603 break;
604 }
605 }
606
espi_vw_notify_plt_rst(const struct device * dev)607 static void espi_vw_notify_plt_rst(const struct device *dev)
608 {
609 struct espi_npcx_data *const data = dev->data;
610 struct espi_reg *const inst = HAL_INSTANCE(dev);
611 struct espi_event evt = { ESPI_BUS_EVENT_VWIRE_RECEIVED,
612 ESPI_VWIRE_SIGNAL_PLTRST, 0
613 };
614 uint8_t wire = 0;
615
616 espi_npcx_receive_vwire(dev, ESPI_VWIRE_SIGNAL_PLTRST, &wire);
617 LOG_DBG("VW_PLT_RST is %d!", wire);
618 if (wire) {
619 /* Set Peripheral Channel ready when PLTRST is de-asserted */
620 inst->ESPICFG |= BIT(NPCX_ESPICFG_PCHANEN);
621 /* Configure all host sub-modules in host domain */
622 npcx_host_init_subs_host_domain();
623 }
624
625 /* PLT_RST will be received several times */
626 if (wire != data->plt_rst_asserted) {
627 data->plt_rst_asserted = wire;
628 evt.evt_data = wire;
629 espi_send_callbacks(&data->callbacks, dev, evt);
630 }
631 }
632
espi_vw_send_bootload_done(const struct device * dev)633 static void espi_vw_send_bootload_done(const struct device *dev)
634 {
635 int ret;
636 uint8_t boot_done;
637
638 ret = espi_npcx_receive_vwire(dev,
639 ESPI_VWIRE_SIGNAL_TARGET_BOOT_DONE, &boot_done);
640 LOG_DBG("%s: %d", __func__, boot_done);
641 if (!ret && !boot_done) {
642 /* Send slave boot status bit with done bit at the same time. */
643 espi_npcx_send_vwire(dev, ESPI_VWIRE_SIGNAL_TARGET_BOOT_STS, 1);
644 }
645 }
646
espi_vw_generic_isr(const struct device * dev,struct npcx_wui * wui)647 static void espi_vw_generic_isr(const struct device *dev, struct npcx_wui *wui)
648 {
649 int idx;
650 enum espi_vwire_signal signal;
651
652 LOG_DBG("%s: WUI %d %d %d", __func__, wui->table, wui->group, wui->bit);
653 for (idx = 0; idx < ARRAY_SIZE(vw_in_tbl); idx++) {
654 if (wui->table == vw_in_tbl[idx].vw_wui.table &&
655 wui->group == vw_in_tbl[idx].vw_wui.group &&
656 wui->bit == vw_in_tbl[idx].vw_wui.bit) {
657 break;
658 }
659 }
660
661 if (idx == ARRAY_SIZE(vw_in_tbl)) {
662 LOG_ERR("Unknown VW event! %d %d %d", wui->table,
663 wui->group, wui->bit);
664 return;
665 }
666
667 signal = vw_in_tbl[idx].sig;
668 if (signal == ESPI_VWIRE_SIGNAL_SLP_S3
669 || signal == ESPI_VWIRE_SIGNAL_SLP_S4
670 || signal == ESPI_VWIRE_SIGNAL_SLP_S5
671 || signal == ESPI_VWIRE_SIGNAL_SLP_A) {
672 espi_vw_notify_system_state(dev, signal);
673 #if DT_NODE_EXISTS(DT_CHILD(DT_PATH(npcx_espi_vws_map), vw_dnx_warn))
674 } else if (signal == ESPI_VWIRE_SIGNAL_HOST_RST_WARN
675 || signal == ESPI_VWIRE_SIGNAL_SUS_WARN
676 || signal == ESPI_VWIRE_SIGNAL_OOB_RST_WARN
677 || signal == ESPI_VWIRE_SIGNAL_DNX_WARN) {
678 #else
679 } else if (signal == ESPI_VWIRE_SIGNAL_HOST_RST_WARN
680 || signal == ESPI_VWIRE_SIGNAL_SUS_WARN
681 || signal == ESPI_VWIRE_SIGNAL_OOB_RST_WARN) {
682 #endif
683 espi_vw_notify_host_warning(dev, signal);
684 } else if (signal == ESPI_VWIRE_SIGNAL_PLTRST) {
685 espi_vw_notify_plt_rst(dev);
686 }
687 }
688
espi_vw_espi_rst_isr(const struct device * dev,struct npcx_wui * wui)689 static void espi_vw_espi_rst_isr(const struct device *dev, struct npcx_wui *wui)
690 {
691 struct espi_reg *const inst = HAL_INSTANCE(dev);
692 struct espi_npcx_data *const data = dev->data;
693 struct espi_event evt = { ESPI_BUS_RESET, 0, 0 };
694
695 data->espi_rst_level = IS_BIT_SET(inst->ESPISTS,
696 NPCX_ESPISTS_ESPIRST_LVL);
697 LOG_DBG("eSPI RST level is %d!", data->espi_rst_level);
698
699 evt.evt_data = data->espi_rst_level;
700 espi_send_callbacks(&data->callbacks, dev, evt);
701 }
702
703 /* eSPI api functions */
espi_npcx_configure(const struct device * dev,struct espi_cfg * cfg)704 static int espi_npcx_configure(const struct device *dev, struct espi_cfg *cfg)
705 {
706 struct espi_reg *const inst = HAL_INSTANCE(dev);
707
708 uint8_t max_freq = 0;
709 uint8_t cur_io_mode, io_mode = 0;
710
711 /* Configure eSPI frequency */
712 switch (cfg->max_freq) {
713 case 20:
714 max_freq = NPCX_ESPI_MAXFREQ_20;
715 break;
716 case 25:
717 max_freq = NPCX_ESPI_MAXFREQ_25;
718 break;
719 case 33:
720 max_freq = NPCX_ESPI_MAXFREQ_33;
721 break;
722 case 50:
723 max_freq = NPCX_ESPI_MAXFREQ_50;
724 break;
725 #ifdef CONFIG_SOC_SERIES_NPCX4
726 case 66:
727 max_freq = NPCX_ESPI_MAXFREQ_66;
728 break;
729 #endif
730 default:
731 return -EINVAL;
732 }
733 SET_FIELD(inst->ESPICFG, NPCX_ESPICFG_MAXFREQ_FIELD, max_freq);
734
735 /* Configure eSPI IO mode */
736 io_mode = (cfg->io_caps >> 1);
737 if (io_mode > 3) {
738 return -EINVAL;
739 }
740
741 cur_io_mode = GET_FIELD(inst->ESPICFG, NPCX_ESPICFG_IOMODE_FIELD);
742 if (io_mode != cur_io_mode) {
743 SET_FIELD(inst->ESPICFG, NPCX_ESPICFG_IOMODE_FIELD, io_mode);
744 }
745
746 /* Configure eSPI supported channels */
747 if (cfg->channel_caps & ESPI_CHANNEL_PERIPHERAL) {
748 inst->ESPICFG |= BIT(NPCX_ESPICFG_PCCHN_SUPP);
749 }
750
751 if (cfg->channel_caps & ESPI_CHANNEL_VWIRE) {
752 inst->ESPICFG |= BIT(NPCX_ESPICFG_VWCHN_SUPP);
753 }
754
755 if (cfg->channel_caps & ESPI_CHANNEL_OOB) {
756 inst->ESPICFG |= BIT(NPCX_ESPICFG_OOBCHN_SUPP);
757 }
758
759 if (cfg->channel_caps & ESPI_CHANNEL_FLASH) {
760 inst->ESPICFG |= BIT(NPCX_ESPICFG_FLASHCHN_SUPP);
761 }
762
763 LOG_DBG("%s: %d %d ESPICFG: 0x%08X", __func__,
764 max_freq, io_mode, inst->ESPICFG);
765
766 return 0;
767 }
768
espi_npcx_channel_ready(const struct device * dev,enum espi_channel ch)769 static bool espi_npcx_channel_ready(const struct device *dev,
770 enum espi_channel ch)
771 {
772 struct espi_reg *const inst = HAL_INSTANCE(dev);
773 bool sts;
774
775 switch (ch) {
776 case ESPI_CHANNEL_PERIPHERAL:
777 sts = IS_BIT_SET(inst->ESPICFG, NPCX_ESPICFG_PCHANEN);
778 break;
779 case ESPI_CHANNEL_VWIRE:
780 sts = IS_BIT_SET(inst->ESPICFG, NPCX_ESPICFG_VWCHANEN);
781 break;
782 case ESPI_CHANNEL_OOB:
783 sts = IS_BIT_SET(inst->ESPICFG, NPCX_ESPICFG_OOBCHANEN);
784 break;
785 case ESPI_CHANNEL_FLASH:
786 sts = IS_BIT_SET(inst->ESPICFG, NPCX_ESPICFG_FLASHCHANEN);
787 break;
788 default:
789 sts = false;
790 break;
791 }
792
793 return sts;
794 }
795
espi_npcx_send_vwire(const struct device * dev,enum espi_vwire_signal signal,uint8_t level)796 static int espi_npcx_send_vwire(const struct device *dev,
797 enum espi_vwire_signal signal, uint8_t level)
798 {
799 uint8_t reg_idx, bitmask, sig_idx, val = 0, vw_tbl_size;
800 struct espi_reg *const inst = HAL_INSTANCE(dev);
801 const struct npcx_vw_out_config *vw_tbl;
802 uint32_t reg_val;
803 char *reg_name;
804
805 if (signal >= ESPI_VWIRE_SIGNAL_COUNT) {
806 LOG_ERR("Invalid VW: %d", signal);
807 return -EINVAL;
808 }
809
810 if (signal >= ESPI_VWIRE_SIGNAL_TARGET_GPIO_0) {
811 vw_tbl = vw_out_gpio_tbl1;
812 vw_tbl_size = ARRAY_SIZE(vw_out_gpio_tbl1);
813 reg_name = "VWGPSM";
814 } else {
815 vw_tbl = vw_out_tbl;
816 vw_tbl_size = ARRAY_SIZE(vw_out_tbl);
817 reg_name = "VWEVSM";
818 }
819
820 /* Find signal in VW output table */
821 for (sig_idx = 0; sig_idx < vw_tbl_size; sig_idx++) {
822 if (vw_tbl[sig_idx].sig == signal) {
823 break;
824 }
825 }
826
827 if (sig_idx == vw_tbl_size) {
828 LOG_ERR("%s signal %d is invalid", __func__, signal);
829 return -EIO;
830 }
831
832 reg_idx = vw_tbl[sig_idx].reg_idx;
833 bitmask = vw_tbl[sig_idx].bitmask;
834
835 /* Get wire field and set/clear wire bit */
836 if (signal >= ESPI_VWIRE_SIGNAL_TARGET_GPIO_0) {
837 val = GET_FIELD(inst->VWGPSM[reg_idx], NPCX_VWEVSM_WIRE);
838 } else {
839 val = GET_FIELD(inst->VWEVSM[reg_idx], NPCX_VWEVSM_WIRE);
840 }
841
842 if (level) {
843 val |= bitmask;
844 } else {
845 val &= ~bitmask;
846 }
847
848 if (signal >= ESPI_VWIRE_SIGNAL_TARGET_GPIO_0) {
849 SET_FIELD(inst->VWGPSM[reg_idx], NPCX_VWEVSM_WIRE, val);
850 reg_val = inst->VWGPSM[reg_idx];
851 } else {
852 SET_FIELD(inst->VWEVSM[reg_idx], NPCX_VWEVSM_WIRE, val);
853 reg_val = inst->VWEVSM[reg_idx];
854 }
855
856 LOG_DBG("Send VW: %s%d 0x%08X", reg_name, reg_idx, reg_val);
857
858 return 0;
859 }
860
espi_npcx_receive_vwire(const struct device * dev,enum espi_vwire_signal signal,uint8_t * level)861 static int espi_npcx_receive_vwire(const struct device *dev,
862 enum espi_vwire_signal signal, uint8_t *level)
863 {
864 struct espi_reg *const inst = HAL_INSTANCE(dev);
865 uint8_t reg_idx, bitmask, sig_idx, val;
866
867 /* Find signal in VW input table */
868 for (sig_idx = 0; sig_idx < ARRAY_SIZE(vw_in_tbl); sig_idx++) {
869 if (vw_in_tbl[sig_idx].sig == signal) {
870 reg_idx = vw_in_tbl[sig_idx].reg_idx;
871 bitmask = vw_in_tbl[sig_idx].bitmask;
872
873 val = GET_FIELD(inst->VWEVMS[reg_idx],
874 NPCX_VWEVMS_WIRE);
875
876 if (IS_ENABLED(CONFIG_ESPI_VWIRE_VALID_BIT_CHECK)) {
877 val &= GET_FIELD(inst->VWEVMS[reg_idx],
878 NPCX_VWEVMS_VALID);
879 }
880
881 *level = !!(val & bitmask);
882 return 0;
883 }
884 }
885
886 /* Find signal in VW output table */
887 for (sig_idx = 0; sig_idx < ARRAY_SIZE(vw_out_tbl); sig_idx++) {
888 if (vw_out_tbl[sig_idx].sig == signal) {
889 reg_idx = vw_out_tbl[sig_idx].reg_idx;
890 bitmask = vw_out_tbl[sig_idx].bitmask;
891
892 val = GET_FIELD(inst->VWEVSM[reg_idx],
893 NPCX_VWEVSM_WIRE);
894
895 if (IS_ENABLED(CONFIG_ESPI_VWIRE_VALID_BIT_CHECK)) {
896 val &= GET_FIELD(inst->VWEVSM[reg_idx],
897 NPCX_VWEVSM_VALID);
898 }
899
900 *level = !!(val & bitmask);
901 return 0;
902 }
903 }
904
905 LOG_ERR("%s Out of index %d", __func__, signal);
906 return -EIO;
907 }
908
espi_npcx_manage_callback(const struct device * dev,struct espi_callback * callback,bool set)909 static int espi_npcx_manage_callback(const struct device *dev,
910 struct espi_callback *callback, bool set)
911 {
912 struct espi_npcx_data *const data = dev->data;
913
914 return espi_manage_callback(&data->callbacks, callback, set);
915 }
916
espi_npcx_read_lpc_request(const struct device * dev,enum lpc_peripheral_opcode op,uint32_t * data)917 static int espi_npcx_read_lpc_request(const struct device *dev,
918 enum lpc_peripheral_opcode op,
919 uint32_t *data)
920 {
921 ARG_UNUSED(dev);
922
923 return npcx_host_periph_read_request(op, data);
924 }
925
espi_npcx_write_lpc_request(const struct device * dev,enum lpc_peripheral_opcode op,uint32_t * data)926 static int espi_npcx_write_lpc_request(const struct device *dev,
927 enum lpc_peripheral_opcode op,
928 uint32_t *data)
929 {
930 ARG_UNUSED(dev);
931
932 return npcx_host_periph_write_request(op, data);
933 }
934
935 #if defined(CONFIG_ESPI_OOB_CHANNEL)
espi_npcx_send_oob(const struct device * dev,struct espi_oob_packet * pckt)936 static int espi_npcx_send_oob(const struct device *dev,
937 struct espi_oob_packet *pckt)
938 {
939 struct espi_reg *const inst = HAL_INSTANCE(dev);
940 uint8_t *oob_buf = pckt->buf;
941 int sz_oob_tx = pckt->len;
942 int idx_tx_buf;
943 uint32_t oob_data;
944
945 /* Check out of OOB transmitted buffer size */
946 if (sz_oob_tx > NPCX_ESPI_OOB_MAX_PAYLOAD) {
947 LOG_ERR("Out of OOB transmitted buffer: %d", sz_oob_tx);
948 return -EINVAL;
949 }
950
951 /* Check OOB Transmit Queue is empty? */
952 if (IS_BIT_SET(inst->OOBCTL, NPCX_OOBCTL_OOB_AVAIL)) {
953 LOG_ERR("OOB channel is busy");
954 return -EBUSY;
955 }
956
957 /*
958 * GET_OOB header (first 4 bytes) in npcx 32-bits tx buffer
959 *
960 * [24:31] - LEN[0:7] Data length of GET_OOB request package
961 * [20:23] - TAG Tag of GET_OOB
962 * [16:19] - LEN[8:11] Ignore it since max payload is 64 bytes
963 * [8:15] - CYCLE_TYPE Cycle type of GET_OOB
964 * [0:7] - SZ_PACK Package size plus 3 bytes header. (Npcx only)
965 */
966 inst->OOBTXBUF[0] = (sz_oob_tx + 3)
967 | (ESPI_OOB_GET_CYCLE_TYPE << 8)
968 | (ESPI_OOB_TAG << 16)
969 | (sz_oob_tx << 24);
970
971 /* Write GET_OOB data into 32-bits tx buffer in little endian */
972 for (idx_tx_buf = 0; idx_tx_buf < sz_oob_tx/4; idx_tx_buf++,
973 oob_buf += 4)
974 inst->OOBTXBUF[idx_tx_buf + 1] = oob_buf[0]
975 | (oob_buf[1] << 8)
976 | (oob_buf[2] << 16)
977 | (oob_buf[3] << 24);
978
979 /* Write remaining bytes of package */
980 if (sz_oob_tx % 4) {
981 int i;
982
983 oob_data = 0;
984 for (i = 0; i < sz_oob_tx % 4; i++) {
985 oob_data |= (oob_buf[i] << (8 * i));
986 }
987 inst->OOBTXBUF[idx_tx_buf + 1] = oob_data;
988 }
989
990 /*
991 * Notify host a new OOB packet is ready. Please don't write OOB_FREE
992 * to 1 at the same tiem in case clear it unexpectedly.
993 */
994 oob_data = inst->OOBCTL & ~(BIT(NPCX_OOBCTL_OOB_FREE));
995 oob_data |= BIT(NPCX_OOBCTL_OOB_AVAIL);
996 inst->OOBCTL = oob_data;
997
998 while (IS_BIT_SET(inst->OOBCTL, NPCX_OOBCTL_OOB_AVAIL)) {
999 ;
1000 }
1001
1002 LOG_DBG("%s issued!!", __func__);
1003 return 0;
1004 }
1005
espi_npcx_receive_oob(const struct device * dev,struct espi_oob_packet * pckt)1006 static int espi_npcx_receive_oob(const struct device *dev,
1007 struct espi_oob_packet *pckt)
1008 {
1009 struct espi_reg *const inst = HAL_INSTANCE(dev);
1010 uint8_t *oob_buf = pckt->buf;
1011 uint32_t oob_data;
1012 int idx_rx_buf, sz_oob_rx;
1013
1014 /* Check eSPI bus status first */
1015 if (IS_BIT_SET(inst->ESPISTS, NPCX_ESPISTS_BERR)) {
1016 LOG_ERR("%s: eSPI Bus Error: 0x%08X", __func__, inst->ESPIERR);
1017 return -EIO;
1018 }
1019
1020 #if !defined(CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC)
1021 struct espi_npcx_data *const data = dev->data;
1022 int ret;
1023
1024 /* Wait until get oob package or timeout */
1025 ret = k_sem_take(&data->oob_rx_lock, K_MSEC(ESPI_OOB_MAX_TIMEOUT));
1026 if (ret == -EAGAIN) {
1027 LOG_ERR("%s: Timeout", __func__);
1028 return -ETIMEDOUT;
1029 }
1030 #endif
1031
1032 /*
1033 * PUT_OOB header (first 4 bytes) in npcx 32-bits rx buffer
1034 *
1035 * [24:31] - LEN[0:7] Data length of PUT_OOB request package
1036 * [20:23] - TAG Tag of PUT_OOB
1037 * [16:19] - LEN[8:11] Data length of PUT_OOB request package
1038 * [8:15] - CYCLE_TYPE Cycle type of PUT_OOB
1039 * [0:7] - SZ_PACK Reserved. (Npcx only)
1040 */
1041 oob_data = inst->OOBRXBUF[0];
1042 /* Get received package length first */
1043 sz_oob_rx = NPCX_OOB_RX_PACKAGE_LEN(oob_data);
1044
1045 /* Check OOB received buffer size */
1046 if (sz_oob_rx > NPCX_ESPI_OOB_MAX_PAYLOAD) {
1047 LOG_ERR("Out of OOB received buffer: %d", sz_oob_rx);
1048 return -EINVAL;
1049 }
1050
1051 /* Set received size to package structure */
1052 pckt->len = sz_oob_rx;
1053
1054 /* Read PUT_OOB data into 32-bits rx buffer in little endian */
1055 for (idx_rx_buf = 0; idx_rx_buf < sz_oob_rx/4; idx_rx_buf++) {
1056 oob_data = inst->OOBRXBUF[idx_rx_buf + 1];
1057
1058 *(oob_buf++) = oob_data & 0xFF;
1059 *(oob_buf++) = (oob_data >> 8) & 0xFF;
1060 *(oob_buf++) = (oob_data >> 16) & 0xFF;
1061 *(oob_buf++) = (oob_data >> 24) & 0xFF;
1062 }
1063
1064 /* Read remaining bytes of package */
1065 if (sz_oob_rx % 4) {
1066 int i;
1067
1068 oob_data = inst->OOBRXBUF[idx_rx_buf + 1];
1069 for (i = 0; i < sz_oob_rx % 4; i++) {
1070 *(oob_buf++) = (oob_data >> (8 * i)) & 0xFF;
1071 }
1072 }
1073
1074 /* Notify host that OOB received buffer is free now. */
1075 inst->OOBCTL |= BIT(NPCX_OOBCTL_OOB_FREE);
1076 return 0;
1077 }
1078 #endif
1079
1080 #ifdef CONFIG_ESPI_FLASH_CHANNEL
espi_npcx_flash_prepare_tx_header(const struct device * dev,int cyc_type,int flash_addr,int flash_len,int tx_payload)1081 static void espi_npcx_flash_prepare_tx_header(const struct device *dev,
1082 int cyc_type, int flash_addr, int flash_len, int tx_payload)
1083 {
1084 struct espi_reg *const inst = HAL_INSTANCE(dev);
1085
1086 /*
1087 * First 3 bytes of flash cycle command header in tx buffer
1088 *
1089 * [24:31] - LEN[0:7] = n Data length of flash cycle request
1090 * [16:23] - LEN[8:15] = 0 Ignore it since max buffer size is 64 bytes
1091 * [12:15] - TAG = 0 Tag of flash cycle command is always 0 here
1092 * [8:11] - CYCLE_TYPE = 0 Cycle type of flash command
1093 * [0:7] - SZ_PACK = 7 Overall tx package size. (Used internally.)
1094 */
1095 inst->FLASHTXBUF[0] = (flash_len << 24) |
1096 (cyc_type << 8) |
1097 (tx_payload + ESPI_FLASH_HEADER_PCKT_SIZE);
1098
1099 /*
1100 * Following 4 bytes of tager flash address in tx buffer
1101 *
1102 * [24:31] - ADDR[0:7] Start address of flash cycle command request
1103 * [16:23] - ADDR[15:8]
1104 * [8:15] - ADDR[23:16]
1105 * [0:7] - ADDR[31:24]
1106 */
1107 inst->FLASHTXBUF[1] = sys_cpu_to_be32(flash_addr);
1108
1109 }
1110
espi_npcx_flash_parse_completion(const struct device * dev)1111 static int espi_npcx_flash_parse_completion(const struct device *dev)
1112 {
1113 int cycle_type;
1114 struct espi_reg *const inst = HAL_INSTANCE(dev);
1115
1116 /*
1117 * First 3 bytes of flash cycle completion header in rx buffer
1118 *
1119 * [24:31] - LEN[0:7] Data length of flash cycle completion package
1120 * [16:23] - LEN[8:15] Ignore it since rx bufer size is 64 bytes
1121 * [12:15] - TAG Tag of flash cycle completion package
1122 * [8:11] - CYCLE_TYPE Cycle type of flash completion
1123 * [0:7] - Reserved
1124 */
1125 cycle_type = (inst->FLASHRXBUF[0] & 0xff00) >> 8;
1126 if (cycle_type == ESPI_FLASH_SUCCESS_WITHOUT_DATA_CYCLE_TYPE) {
1127 return 0;
1128 }
1129
1130 return -EIO;
1131 }
1132
espi_npcx_flash_parse_completion_with_data(const struct device * dev,struct espi_flash_packet * pckt)1133 static int espi_npcx_flash_parse_completion_with_data(const struct device *dev,
1134 struct espi_flash_packet *pckt)
1135 {
1136 struct espi_reg *const inst = HAL_INSTANCE(dev);
1137 int cycle_type, sz_rx_payload;
1138
1139 /*
1140 * First 3 bytes of flash cycle completion header in rx buffer
1141 *
1142 * [24:31] - LEN[0:7] Data length of flash cycle completion package
1143 * [16:23] - LEN[8:15] Ignore it since rx bufer size is 64 bytes
1144 * [12:15] - TAG Tag of flash cycle completion package
1145 * [8:11] - CYCLE_TYPE Cycle type of flash completion
1146 * [0:7] - Reserved
1147 *
1148 * The following is flash data/
1149 */
1150 cycle_type = (inst->FLASHRXBUF[0] & 0xff00) >> 8;
1151 sz_rx_payload = inst->FLASHRXBUF[0] >> 24;
1152 if (cycle_type == ESPI_FLASH_SUCCESS_WITH_DATA_CYCLE_TYPE) {
1153 volatile uint32_t *rx_buf = &inst->FLASHRXBUF[1];
1154 uint8_t *buf = pckt->buf;
1155 uint32_t data;
1156
1157 /* Get data from flash RX buffer */
1158 for (int i = 0; i < sz_rx_payload / 4; i++, rx_buf++) {
1159 data = *rx_buf;
1160 for (int j = 0; j < 4; j++, buf++) {
1161 *buf = data & 0xff;
1162 data = data >> 8;
1163 }
1164 }
1165
1166 /* Get remaining bytes */
1167 if (sz_rx_payload % 4) {
1168 data = *rx_buf;
1169 for (int j = 0; j < sz_rx_payload % 4; j++, buf++) {
1170 *buf = data & 0xff;
1171 data = data >> 8;
1172 }
1173 }
1174
1175 return 0;
1176 }
1177
1178 return -EIO;
1179 }
1180
espi_npcx_flash_read(const struct device * dev,struct espi_flash_packet * pckt)1181 static int espi_npcx_flash_read(const struct device *dev,
1182 struct espi_flash_packet *pckt)
1183 {
1184 int ret;
1185 struct espi_reg *const inst = HAL_INSTANCE(dev);
1186 struct espi_npcx_data *const data = dev->data;
1187
1188 /* Check out of FLASH received buffer size */
1189 if (pckt->len > NPCX_ESPI_FLASH_MAX_RX_PAYLOAD) {
1190 LOG_ERR("Out of FLASH transmitted buffer: %d", pckt->len);
1191 return -EINVAL;
1192 }
1193
1194 /* Check Flash Transmit Queue is empty? */
1195 if (IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_FLASH_TX_AVAIL)) {
1196 LOG_ERR("flash channel is busy");
1197 return -EBUSY;
1198 }
1199
1200 /* Prepare FLASH_READ header in tx buffer */
1201 espi_npcx_flash_prepare_tx_header(dev,
1202 ESPI_FLASH_READ_CYCLE_TYPE,
1203 pckt->flash_addr,
1204 pckt->len,
1205 0);
1206
1207 /* Set the FLASHCTL.FLASH_TX_AVAIL bit to 1 to enqueue the packet */
1208 inst->FLASHCTL |= BIT(NPCX_FLASHCTL_FLASH_TX_AVAIL);
1209
1210 /* Wait until get flash package or timeout */
1211 ret = k_sem_take(&data->flash_rx_lock, K_MSEC(ESPI_FLASH_MAX_TIMEOUT));
1212 if (ret == -EAGAIN) {
1213 LOG_ERR("%s: Timeout", __func__);
1214 return -ETIMEDOUT;
1215 }
1216
1217 return espi_npcx_flash_parse_completion_with_data(dev, pckt);
1218 }
1219
espi_npcx_flash_write(const struct device * dev,struct espi_flash_packet * pckt)1220 static int espi_npcx_flash_write(const struct device *dev,
1221 struct espi_flash_packet *pckt)
1222 {
1223 int ret;
1224 uint32_t tx_data;
1225 struct espi_reg *const inst = HAL_INSTANCE(dev);
1226 struct espi_npcx_data *const data = dev->data;
1227 volatile uint32_t *tx_buf = &inst->FLASHTXBUF[2];
1228 uint8_t *buf = pckt->buf;
1229
1230 /* Check out of FLASH transmitted buffer size */
1231 if (pckt->len > NPCX_ESPI_FLASH_MAX_TX_PAYLOAD) {
1232 LOG_ERR("Out of FLASH transmitted buffer: %d", pckt->len);
1233 return -EINVAL;
1234 }
1235
1236 /* Check Flash Transmit Queue is empty? */
1237 if (IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_FLASH_TX_AVAIL)) {
1238 LOG_ERR("flash channel is busy");
1239 return -EBUSY;
1240 }
1241
1242 /* Prepare FLASH_WRITE header in tx buffer */
1243 espi_npcx_flash_prepare_tx_header(dev,
1244 ESPI_FLASH_WRITE_CYCLE_TYPE,
1245 pckt->flash_addr,
1246 pckt->len,
1247 pckt->len);
1248
1249 /* Put package data to flash TX buffer */
1250 for (int i = 0; i < pckt->len / 4; i++, tx_buf++) {
1251 tx_data = 0;
1252 for (int j = 0; j < 4; j++, buf++) {
1253 tx_data |= (*buf << (j * 8));
1254 }
1255 *tx_buf = tx_data;
1256 }
1257
1258 /* Put remaining bytes to flash TX buffer */
1259 if (pckt->len % 4) {
1260 tx_data = 0;
1261 for (int j = 0; j < pckt->len % 4; j++, buf++) {
1262 tx_data |= (*buf << (j * 8));
1263 }
1264 *tx_buf = tx_data;
1265 }
1266
1267 /* Set the FLASHCTL.FLASH_TX_AVAIL bit to 1 to enqueue the packet */
1268 inst->FLASHCTL |= BIT(NPCX_FLASHCTL_FLASH_TX_AVAIL);
1269
1270 /* Wait until get flash package or timeout */
1271 ret = k_sem_take(&data->flash_rx_lock, K_MSEC(ESPI_FLASH_MAX_TIMEOUT));
1272 if (ret == -EAGAIN) {
1273 LOG_ERR("%s: Timeout", __func__);
1274 return -ETIMEDOUT;
1275 }
1276
1277 /* Parse completion package in rx buffer */
1278 return espi_npcx_flash_parse_completion(dev);
1279 }
1280
espi_npcx_flash_erase(const struct device * dev,struct espi_flash_packet * pckt)1281 static int espi_npcx_flash_erase(const struct device *dev,
1282 struct espi_flash_packet *pckt)
1283 {
1284 int ret;
1285 struct espi_reg *const inst = HAL_INSTANCE(dev);
1286 struct espi_npcx_data *const data = dev->data;
1287
1288 /* Check Flash Transmit Queue is empty? */
1289 if (IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_FLASH_TX_AVAIL)) {
1290 LOG_ERR("flash channel is busy");
1291 return -EBUSY;
1292 }
1293
1294 /* Prepare FLASH_ERASE header in tx buffer */
1295 espi_npcx_flash_prepare_tx_header(dev,
1296 ESPI_FLASH_ERASE_CYCLE_TYPE,
1297 pckt->flash_addr,
1298 pckt->len,
1299 0);
1300
1301 /* Set the FLASHCTL.FLASH_TX_AVAIL bit to 1 to enqueue the packet */
1302 inst->FLASHCTL |= BIT(NPCX_FLASHCTL_FLASH_TX_AVAIL);
1303
1304 /* Wait until get flash package or timeout */
1305 ret = k_sem_take(&data->flash_rx_lock, K_MSEC(ESPI_FLASH_MAX_TIMEOUT));
1306 if (ret == -EAGAIN) {
1307 LOG_ERR("%s: Timeout", __func__);
1308 return -ETIMEDOUT;
1309 }
1310
1311 /* Parse completion package in rx buffer */
1312 return espi_npcx_flash_parse_completion(dev);
1313 }
1314 #endif
1315
1316 /* Platform specific espi module functions */
npcx_espi_enable_interrupts(const struct device * dev)1317 void npcx_espi_enable_interrupts(const struct device *dev)
1318 {
1319 const struct espi_npcx_config *const config = dev->config;
1320
1321 /* Enable eSPI bus interrupt */
1322 irq_enable(DT_INST_IRQN(0));
1323
1324 /* Turn on all VW inputs' MIWU interrupts */
1325 for (int idx = 0; idx < ARRAY_SIZE(vw_in_tbl); idx++) {
1326 npcx_miwu_irq_enable(&(vw_in_tbl[idx].vw_wui));
1327 }
1328
1329 npcx_miwu_irq_enable(&config->espi_rst_wui);
1330 }
1331
npcx_espi_disable_interrupts(const struct device * dev)1332 void npcx_espi_disable_interrupts(const struct device *dev)
1333 {
1334 const struct espi_npcx_config *const config = dev->config;
1335
1336 /* Disable eSPI bus interrupt */
1337 irq_disable(DT_INST_IRQN(0));
1338
1339 /* Turn off all VW inputs' MIWU interrupts */
1340 for (int idx = 0; idx < ARRAY_SIZE(vw_in_tbl); idx++) {
1341 npcx_miwu_irq_disable(&(vw_in_tbl[idx].vw_wui));
1342 }
1343
1344 npcx_miwu_irq_disable(&config->espi_rst_wui);
1345 }
1346
1347 /* eSPI driver registration */
1348 static int espi_npcx_init(const struct device *dev);
1349
1350 static DEVICE_API(espi, espi_npcx_driver_api) = {
1351 .config = espi_npcx_configure,
1352 .get_channel_status = espi_npcx_channel_ready,
1353 .send_vwire = espi_npcx_send_vwire,
1354 .receive_vwire = espi_npcx_receive_vwire,
1355 .manage_callback = espi_npcx_manage_callback,
1356 .read_lpc_request = espi_npcx_read_lpc_request,
1357 .write_lpc_request = espi_npcx_write_lpc_request,
1358 #if defined(CONFIG_ESPI_OOB_CHANNEL)
1359 .send_oob = espi_npcx_send_oob,
1360 .receive_oob = espi_npcx_receive_oob,
1361 #endif
1362 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1363 .flash_read = espi_npcx_flash_read,
1364 .flash_write = espi_npcx_flash_write,
1365 .flash_erase = espi_npcx_flash_erase,
1366 #endif
1367 };
1368
1369 static struct espi_npcx_data espi_npcx_data;
1370
1371 PINCTRL_DT_INST_DEFINE(0);
1372 BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
1373 "only one 'nuvoton_npcx_espi' compatible node may be present");
1374
1375 static const struct espi_npcx_config espi_npcx_config = {
1376 .base = DT_INST_REG_ADDR(0),
1377 .espi_rst_wui = NPCX_DT_WUI_ITEM_BY_NAME(0, espi_rst_wui),
1378 .clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
1379 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
1380 };
1381
1382 DEVICE_DT_INST_DEFINE(0, &espi_npcx_init, NULL,
1383 &espi_npcx_data, &espi_npcx_config,
1384 PRE_KERNEL_2, CONFIG_ESPI_INIT_PRIORITY,
1385 &espi_npcx_driver_api);
1386
espi_npcx_init(const struct device * dev)1387 static int espi_npcx_init(const struct device *dev)
1388 {
1389 const struct espi_npcx_config *const config = dev->config;
1390 struct espi_npcx_data *const data = dev->data;
1391 struct espi_reg *const inst = HAL_INSTANCE(dev);
1392 const struct device *const clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
1393 int i, ret;
1394
1395 if (!device_is_ready(clk_dev)) {
1396 LOG_ERR("clock control device not ready");
1397 return -ENODEV;
1398 }
1399
1400 /* Turn on eSPI device clock first */
1401 ret = clock_control_on(clk_dev, (clock_control_subsys_t)
1402 &config->clk_cfg);
1403 if (ret < 0) {
1404 LOG_ERR("Turn on eSPI clock fail %d", ret);
1405 return ret;
1406 }
1407
1408 if (IS_ENABLED(CONFIG_ESPI_NPCX_BYPASS_CH_ENABLE_FATAL_ERROR)) {
1409 /* Enable the access to the NPCX_ONLY_ESPI_REG2 register */
1410 inst->NPCX_ONLY_ESPI_REG1 = NPCX_ONLY_ESPI_REG1_UNLOCK_REG2;
1411 inst->NPCX_ONLY_ESPI_REG2 &= ~BIT(NPCX_ONLY_ESPI_REG2_TRANS_END_CONFIG);
1412 /* Disable the access to the NPCX_ONLY_ESPI_REG2 register */
1413 inst->NPCX_ONLY_ESPI_REG1 = NPCX_ONLY_ESPI_REG1_LOCK_REG2;
1414 }
1415
1416 /* Enable events which share the same espi bus interrupt */
1417 for (i = 0; i < ARRAY_SIZE(espi_bus_isr_tbl); i++) {
1418 inst->ESPIIE |= BIT(espi_bus_isr_tbl[i].int_en_bit);
1419 inst->ESPIWE |= BIT(espi_bus_isr_tbl[i].wake_en_bit);
1420 }
1421
1422 #if !defined(CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC)
1423 k_sem_init(&data->oob_rx_lock, 0, 1);
1424 #endif
1425
1426 #if defined(CONFIG_ESPI_FLASH_CHANNEL)
1427 k_sem_init(&data->flash_rx_lock, 0, 1);
1428 #endif
1429
1430 /* Configure Virtual Wire input signals */
1431 for (i = 0; i < ARRAY_SIZE(vw_in_tbl); i++) {
1432 espi_vw_config_input(dev, &vw_in_tbl[i]);
1433 }
1434
1435 /* Configure Virtual Wire output signals */
1436 for (i = 0; i < ARRAY_SIZE(vw_out_tbl); i++) {
1437 espi_vw_config_output(dev, &vw_out_tbl[i]);
1438 }
1439
1440 /* Configure Virtual Wire GPIOs that are output high at reset state */
1441 for (i = 0; i < ARRAY_SIZE(vw_out_gpio_tbl1); i++) {
1442 espi_vw_gpio_config_output(dev, &vw_out_gpio_tbl1[i], 1);
1443 }
1444
1445 /* Configure wake-up input and callback for eSPI VW input signal */
1446 for (i = 0; i < ARRAY_SIZE(vw_in_tbl); i++) {
1447 espi_init_wui_callback(dev, &vw_in_callback[i],
1448 &vw_in_tbl[i].vw_wui, espi_vw_generic_isr);
1449 }
1450
1451 /* Configure wake-up input and callback for ESPI_RST signal */
1452 espi_init_wui_callback(dev, &espi_rst_callback,
1453 &config->espi_rst_wui, espi_vw_espi_rst_isr);
1454
1455 #if DT_NODE_HAS_PROP(DT_DRV_INST(0), vw_index_extend_set)
1456 uint8_t vw_ex_len = ARRAY_SIZE(espi_npcx_vw_ex_0);
1457 uint8_t dir, num, index;
1458
1459 for (i = 0; i < vw_ex_len; i++) {
1460 dir = espi_npcx_vw_ex_0[i].direction;
1461 num = espi_npcx_vw_ex_0[i].group_num;
1462 index = espi_npcx_vw_ex_0[i].index;
1463
1464 if (dir == ESPI_CONTROLLER_TO_TARGET) {
1465 if (num >= NPCX_VWEVMS_MAX) {
1466 LOG_ERR("Error Setting for VW extend MS group (%x)", num);
1467 return -EINVAL;
1468 }
1469 SET_FIELD(inst->VWEVMS[num], NPCX_VWEVMS_INDEX, index);
1470 SET_FIELD(inst->VWEVMS[num], NPCX_VWEVMS_VALID, 0x0);
1471 inst->VWEVMS[num] |= BIT(NPCX_VWEVMS_INDEX_EN);
1472 } else if (dir == ESPI_TARGET_TO_CONTROLLER) {
1473 if (num >= NPCX_VWEVSM_MAX) {
1474 LOG_ERR("Error Setting for VW extend SM group (%x)", num);
1475 return -EINVAL;
1476 }
1477 SET_FIELD(inst->VWEVSM[num], NPCX_VWEVSM_INDEX, index);
1478 SET_FIELD(inst->VWEVSM[num], NPCX_VWEVSM_VALID, 0x0);
1479 inst->VWEVSM[num] |= BIT(NPCX_VWEVSM_INDEX_EN);
1480 } else {
1481 LOG_ERR("Error Setting for VW extend direction (%x)", dir);
1482 return -EINVAL;
1483 }
1484 }
1485 #endif
1486
1487 /* Configure pin-mux for eSPI bus device */
1488 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1489 if (ret < 0) {
1490 LOG_ERR("eSPI pinctrl setup failed (%d)", ret);
1491 return ret;
1492 }
1493
1494 /* Configure host sub-modules which HW blocks belong to core domain */
1495 npcx_host_init_subs_core_domain(dev, &data->callbacks);
1496
1497 #if defined(CONFIG_ESPI_FLASH_CHANNEL) && defined(CONFIG_ESPI_TAF)
1498 npcx_init_taf(dev, &data->callbacks);
1499 #endif
1500
1501 /* eSPI Bus interrupt installation */
1502 IRQ_CONNECT(DT_INST_IRQN(0),
1503 DT_INST_IRQ(0, priority),
1504 espi_bus_generic_isr,
1505 DEVICE_DT_INST_GET(0), 0);
1506
1507 /* Enable eSPI bus interrupt */
1508 irq_enable(DT_INST_IRQN(0));
1509
1510 return 0;
1511 }
1512
