1 /*
2 * Copyright (c) 2020 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nuvoton_npcx_espi
8
9 #include <assert.h>
10 #include <stdlib.h>
11 #include <zephyr/drivers/espi.h>
12 #include <zephyr/drivers/gpio.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/drivers/pinctrl.h>
15 #include <zephyr/dt-bindings/espi/npcx_espi.h>
16 #include <zephyr/kernel.h>
17 #include <zephyr/sys/byteorder.h>
18 #include <zephyr/sys/util.h>
19 #include <soc.h>
20 #include "espi_utils.h"
21 #include "soc_host.h"
22 #include "soc_miwu.h"
23
24 #include <zephyr/logging/log.h>
25 #include <zephyr/irq.h>
26 LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
27
28 struct espi_npcx_config {
29 uintptr_t base;
30 /* clock configuration */
31 struct npcx_clk_cfg clk_cfg;
32 /* mapping table between eSPI reset signal and wake-up input */
33 struct npcx_wui espi_rst_wui;
34 /* pinmux configuration */
35 const struct pinctrl_dev_config *pcfg;
36 };
37
38 struct espi_npcx_data {
39 sys_slist_t callbacks;
40 uint8_t plt_rst_asserted;
41 uint8_t espi_rst_level;
42 uint8_t sx_state;
43 #if !defined(CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC)
44 struct k_sem oob_rx_lock;
45 #endif
46 #if defined(CONFIG_ESPI_FLASH_CHANNEL)
47 struct k_sem flash_rx_lock;
48 #endif
49 #ifdef CONFIG_ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND
50 /* tell the interrupt handler that it is a fake request */
51 bool fake_req_flag;
52 #endif
53 };
54
55 /* Driver convenience defines */
56 #define HAL_INSTANCE(dev) \
57 ((struct espi_reg *)((const struct espi_npcx_config *)(dev)->config)->base)
58
59 /* eSPI channels */
60 #define NPCX_ESPI_CH_PC 0
61 #define NPCX_ESPI_CH_VW 1
62 #define NPCX_ESPI_CH_OOB 2
63 #define NPCX_ESPI_CH_FLASH 3
64 #define NPCX_ESPI_CH_COUNT 4
65 #define NPCX_ESPI_HOST_CH_EN(ch) (ch + 4)
66
67 /* eSPI max supported frequency */
68 #define NPCX_ESPI_MAXFREQ_20 0
69 #define NPCX_ESPI_MAXFREQ_25 1
70 #define NPCX_ESPI_MAXFREQ_33 2
71 #define NPCX_ESPI_MAXFREQ_50 3
72 #define NPCX_ESPI_MAXFREQ_66 4
73
74 /* Minimum delay before acknowledging a virtual wire */
75 #define NPCX_ESPI_VWIRE_ACK_DELAY 10ul /* 10 us */
76
77 /* OOB channel maximum payload size */
78 #define NPCX_ESPI_OOB_MAX_PAYLOAD 64
79 #define NPCX_OOB_RX_PACKAGE_LEN(hdr) (((hdr & 0xff000000) >> 24) | \
80 ((hdr & 0xf0000) >> 8))
81
82 /* Flash channel maximum payload size */
83 #define NPCX_ESPI_FLASH_MAX_RX_PAYLOAD DT_INST_PROP(0, rx_plsize)
84 #define NPCX_ESPI_FLASH_MAX_TX_PAYLOAD DT_INST_PROP(0, tx_plsize)
85
86 /* eSPI cycle type field for OOB and FLASH channels */
87 #define ESPI_FLASH_READ_CYCLE_TYPE 0x00
88 #define ESPI_FLASH_WRITE_CYCLE_TYPE 0x01
89 #define ESPI_FLASH_ERASE_CYCLE_TYPE 0x02
90 #define ESPI_FLASH_SUCCESS_WITH_DATA_CYCLE_TYPE 0x0f
91 #define ESPI_FLASH_SUCCESS_WITHOUT_DATA_CYCLE_TYPE 0x06
92 #define ESPI_FLASH_HEADER_PCKT_SIZE 0x07
93 #define ESPI_FLASH_MAX_TIMEOUT 1000ul /* 1000 ms */
94 #define ESPI_OOB_GET_CYCLE_TYPE 0x21
95 #define ESPI_OOB_TAG 0x00
96 #define ESPI_OOB_MAX_TIMEOUT 500ul /* 500 ms */
97
98 /* eSPI bus interrupt configuration structure and macro function */
99 struct espi_bus_isr {
100 uint8_t status_bit; /* bit order in ESPISTS register */
101 uint8_t int_en_bit; /* bit order in ESPIIE register */
102 uint8_t wake_en_bit; /* bit order in ESPIWE register */
103 void (*bus_isr)(const struct device *dev); /* eSPI bus ISR */
104 };
105
106 #define NPCX_ESPI_BUS_INT_ITEM(event, isr) { \
107 .status_bit = NPCX_ESPISTS_##event, \
108 .int_en_bit = NPCX_ESPIIE_##event##IE, \
109 .wake_en_bit = NPCX_ESPIWE_##event##WE, \
110 .bus_isr = isr }
111
112 /* eSPI Virtual Wire Input (Master-to-Slave) signals configuration structure */
113 struct npcx_vw_in_config {
114 enum espi_vwire_signal sig; /* Virtual Wire signal */
115 uint8_t reg_idx; /* register index for VW signal */
116 uint8_t bitmask; /* VW signal bits-mask */
117 struct npcx_wui vw_wui; /* WUI mapping in MIWU modules for VW signal */
118 };
119
120 /* eSPI Virtual Wire Output (Slave-to-Master) signals configuration structure */
121 struct npcx_vw_out_config {
122 enum espi_vwire_signal sig; /* Virtual Wire signal */
123 uint8_t reg_idx; /* register index for VW signal */
124 uint8_t bitmask; /* VW signal bits-mask */
125 };
126
127 /*
128 * eSPI VW input/Output signal configuration tables. Please refer
129 * npcxn-espi-vws-map.dtsi device tree file for more detail.
130 */
131 static const struct npcx_vw_in_config vw_in_tbl[] = {
132 /* index 02h (In) */
133 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_S3, vw_slp_s3),
134 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_S4, vw_slp_s4),
135 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_S5, vw_slp_s5),
136 /* index 03h (In) */
137 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SUS_STAT, vw_sus_stat),
138 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_PLTRST, vw_plt_rst),
139 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_OOB_RST_WARN, vw_oob_rst_warn),
140 /* index 07h (In) */
141 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_HOST_RST_WARN, vw_host_rst_warn),
142 /* index 41h (In) */
143 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SUS_WARN, vw_sus_warn),
144 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SUS_PWRDN_ACK, vw_sus_pwrdn_ack),
145 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_A, vw_slp_a),
146 /* index 42h (In) */
147 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_LAN, vw_slp_lan),
148 NPCX_DT_VW_IN_CONF(ESPI_VWIRE_SIGNAL_SLP_WLAN, vw_slp_wlan),
149 };
150
151 static const struct npcx_vw_out_config vw_out_tbl[] = {
152 /* index 04h (Out) */
153 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_OOB_RST_ACK, vw_oob_rst_ack),
154 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_WAKE, vw_wake),
155 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_PME, vw_pme),
156 /* index 05h (Out) */
157 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_BOOT_DONE, vw_slv_boot_done),
158 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_ERR_FATAL, vw_err_fatal),
159 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_ERR_NON_FATAL, vw_err_non_fatal),
160 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_BOOT_STS,
161 vw_slv_boot_sts_with_done),
162 /* index 06h (Out) */
163 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SCI, vw_sci),
164 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SMI, vw_smi),
165 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_HOST_RST_ACK, vw_host_rst_ack),
166 /* index 40h (Out) */
167 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_SUS_ACK, vw_sus_ack),
168 };
169
170 /* Virtual wire GPIOs for platform level usage (High at Reset state) */
171 static const struct npcx_vw_out_config vw_out_gpio_tbl1[] = {
172 /* Only NPCX9 and later series support this feature */
173 #if defined(CONFIG_ESPI_NPCX_SUPP_VW_GPIO)
174 /* index 50h (Out) */
175 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_0, vw_slv_gpio_0),
176 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_1, vw_slv_gpio_1),
177 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_2, vw_slv_gpio_2),
178 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_3, vw_slv_gpio_3),
179 /* index 51h (Out) */
180 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_4, vw_slv_gpio_4),
181 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_5, vw_slv_gpio_5),
182 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_6, vw_slv_gpio_6),
183 NPCX_DT_VW_OUT_CONF(ESPI_VWIRE_SIGNAL_TARGET_GPIO_7, vw_slv_gpio_7),
184 #endif
185 };
186
187 /* Callbacks for eSPI bus reset and Virtual Wire signals. */
188 static struct miwu_callback espi_rst_callback;
189 static struct miwu_callback vw_in_callback[ARRAY_SIZE(vw_in_tbl)];
190
191 /* eSPI VW service function forward declarations */
192 static int espi_npcx_receive_vwire(const struct device *dev,
193 enum espi_vwire_signal signal, uint8_t *level);
194 static int espi_npcx_send_vwire(const struct device *dev,
195 enum espi_vwire_signal signal, uint8_t level);
196 static void espi_vw_send_bootload_done(const struct device *dev);
197
198 #if defined(CONFIG_ESPI_FLASH_CHANNEL)
199 static int espi_npcx_flash_parse_completion_with_data(const struct device *dev,
200 struct espi_flash_packet *pckt);
201 static void espi_npcx_flash_prepare_tx_header(const struct device *dev, int cyc_type,
202 int flash_addr, int flash_len, int tx_payload);
203 #endif
204
205 /* eSPI local initialization functions */
espi_init_wui_callback(const struct device * dev,struct miwu_callback * callback,const struct npcx_wui * wui,miwu_dev_callback_handler_t handler)206 static void espi_init_wui_callback(const struct device *dev,
207 struct miwu_callback *callback, const struct npcx_wui *wui,
208 miwu_dev_callback_handler_t handler)
209 {
210 /* VW signal which has no wake-up input source */
211 if (wui->table == NPCX_MIWU_TABLE_NONE)
212 return;
213
214 /* Install callback function */
215 npcx_miwu_init_dev_callback(callback, wui, handler, dev);
216 npcx_miwu_manage_callback(callback, 1);
217
218 /* Configure MIWU setting and enable its interrupt */
219 npcx_miwu_interrupt_configure(wui, NPCX_MIWU_MODE_EDGE,
220 NPCX_MIWU_TRIG_BOTH);
221 }
222
223 /* eSPI local bus interrupt service functions */
espi_bus_err_isr(const struct device * dev)224 static void espi_bus_err_isr(const struct device *dev)
225 {
226 struct espi_reg *const inst = HAL_INSTANCE(dev);
227 uint32_t err = inst->ESPIERR;
228
229 LOG_ERR("eSPI Bus Error %08X", err);
230 /* Clear error status bits */
231 inst->ESPIERR = err;
232 }
233
espi_bus_inband_rst_isr(const struct device * dev)234 static void espi_bus_inband_rst_isr(const struct device *dev)
235 {
236 ARG_UNUSED(dev);
237 LOG_DBG("%s issued", __func__);
238 }
239
espi_bus_reset_isr(const struct device * dev)240 static void espi_bus_reset_isr(const struct device *dev)
241 {
242 ARG_UNUSED(dev);
243 LOG_DBG("%s issued", __func__);
244 /* Do nothing! This signal is handled in ESPI_RST VW signal ISR */
245 }
246
247 #if defined(CONFIG_ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND)
espi_npcx_flash_fake_request(const struct device * dev)248 static void espi_npcx_flash_fake_request(const struct device *dev)
249 {
250 struct espi_reg *const inst = HAL_INSTANCE(dev);
251 struct espi_npcx_data *const data = dev->data;
252
253 inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_AMTEN);
254
255 data->fake_req_flag = true;
256
257 espi_npcx_flash_prepare_tx_header(dev, ESPI_FLASH_READ_CYCLE_TYPE, 0, 16, 0);
258 }
259 #endif
260
espi_bus_cfg_update_isr(const struct device * dev)261 static void espi_bus_cfg_update_isr(const struct device *dev)
262 {
263 int chan;
264 struct espi_reg *const inst = HAL_INSTANCE(dev);
265 struct espi_npcx_data *const data = dev->data;
266 struct espi_event evt = { .evt_type = ESPI_BUS_EVENT_CHANNEL_READY,
267 .evt_details = 0,
268 .evt_data = 0 };
269 /* If host enable bits are not sync with ready bits on slave side. */
270 uint8_t chg_mask = GET_FIELD(inst->ESPICFG, NPCX_ESPICFG_HCHANS_FIELD)
271 ^ GET_FIELD(inst->ESPICFG, NPCX_ESPICFG_CHANS_FIELD);
272 chg_mask &= (ESPI_CHANNEL_VWIRE | ESPI_CHANNEL_OOB |
273 ESPI_CHANNEL_FLASH);
274
275 LOG_DBG("ESPI CFG Change Updated! 0x%02X", chg_mask);
276 /*
277 * If host enable/disable channel for VW/OOB/FLASH, EC should follow
278 * except Peripheral channel. It is handled after receiving PLTRST
279 * event separately.
280 */
281 for (chan = NPCX_ESPI_CH_VW; chan < NPCX_ESPI_CH_COUNT; chan++) {
282 /* Channel ready bit isn't sync with enabled bit on host side */
283 if (chg_mask & BIT(chan)) {
284 evt.evt_data = IS_BIT_SET(inst->ESPICFG,
285 NPCX_ESPI_HOST_CH_EN(chan));
286 evt.evt_details = BIT(chan);
287
288 #if defined(CONFIG_ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND)
289 if (chan == NPCX_ESPI_CH_FLASH && evt.evt_data == 1 &&
290 IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_FLASH_TX_AVAIL)) {
291 espi_npcx_flash_fake_request(dev);
292 }
293 #endif
294
295 if (evt.evt_data) {
296 inst->ESPICFG |= BIT(chan);
297 } else {
298 inst->ESPICFG &= ~BIT(chan);
299 }
300
301 espi_send_callbacks(&data->callbacks, dev, evt);
302 }
303 }
304 LOG_DBG("ESPI CFG EC Updated! 0x%02X", GET_FIELD(inst->ESPICFG,
305 NPCX_ESPICFG_CHANS_FIELD));
306
307 /* If VW channel is enabled and ready, send bootload done VW signal */
308 if ((chg_mask & BIT(NPCX_ESPI_CH_VW)) && IS_BIT_SET(inst->ESPICFG,
309 NPCX_ESPI_HOST_CH_EN(NPCX_ESPI_CH_VW))) {
310 espi_vw_send_bootload_done(dev);
311 }
312
313 #if (defined(CONFIG_ESPI_FLASH_CHANNEL) && defined(CONFIG_ESPI_TAF))
314 /* If CONFIG_ESPI_TAF is set, set to auto or manual mode accroding
315 * to configuration.
316 */
317 if (IS_BIT_SET(inst->ESPICFG, NPCX_ESPICFG_FLCHANMODE)) {
318 #if defined(CONFIG_ESPI_TAF_AUTO_MODE)
319 inst->FLASHCTL |= BIT(NPCX_FLASHCTL_SAF_AUTO_READ);
320 #else
321 inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_SAF_AUTO_READ);
322 #endif
323 }
324 #endif
325 }
326
327 #if defined(CONFIG_ESPI_OOB_CHANNEL)
espi_bus_oob_rx_isr(const struct device * dev)328 static void espi_bus_oob_rx_isr(const struct device *dev)
329 {
330 struct espi_npcx_data *const data = dev->data;
331 #if defined(CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC)
332 struct espi_reg *const inst = HAL_INSTANCE(dev);
333 struct espi_event evt = {
334 .evt_type = ESPI_BUS_EVENT_OOB_RECEIVED,
335 .evt_details = 0,
336 .evt_data = 0,
337 };
338
339 /* Get received package length and set to additional detail of event */
340 evt.evt_details = NPCX_OOB_RX_PACKAGE_LEN(inst->OOBRXBUF[0]);
341 espi_send_callbacks(&data->callbacks, dev, evt);
342 #else
343
344 LOG_DBG("%s", __func__);
345 k_sem_give(&data->oob_rx_lock);
346 #endif
347 }
348 #endif
349
350 #if defined(CONFIG_ESPI_FLASH_CHANNEL)
351 #if defined(CONFIG_ESPI_TAF)
352 static struct espi_taf_pckt taf_pckt;
353
espi_taf_parse(const struct device * dev)354 static uint32_t espi_taf_parse(const struct device *dev)
355 {
356 struct espi_reg *const inst = HAL_INSTANCE(dev);
357 struct npcx_taf_head taf_head;
358 uint32_t taf_addr;
359 uint8_t i, roundsize;
360
361 /* Get type, length and tag from RX buffer */
362 memcpy(&taf_head, (void *)&inst->FLASHRXBUF[0], sizeof(taf_head));
363 taf_pckt.type = taf_head.type;
364 taf_pckt.len = (((uint16_t)taf_head.tag_hlen & 0xF) << 8) | taf_head.llen;
365 taf_pckt.tag = taf_head.tag_hlen >> 4;
366
367 if ((taf_pckt.len == 0) && (taf_pckt.type == NPCX_ESPI_TAF_REQ_READ)) {
368 taf_pckt.len = KB(4);
369 }
370
371 /* Get address from RX buffer */
372 taf_addr = inst->FLASHRXBUF[1];
373 taf_pckt.addr = sys_cpu_to_be32(taf_addr);
374
375 /* Get written data if eSPI TAF write */
376 if (taf_pckt.type == NPCX_ESPI_TAF_REQ_WRITE) {
377 roundsize = DIV_ROUND_UP(taf_pckt.len, sizeof(uint32_t));
378 for (i = 0; i < roundsize; i++) {
379 taf_pckt.src[i] = inst->FLASHRXBUF[2 + i];
380 }
381 }
382
383 return (uint32_t)&taf_pckt;
384 }
385 #endif /* CONFIG_ESPI_TAF */
386
espi_bus_flash_rx_isr(const struct device * dev)387 static void espi_bus_flash_rx_isr(const struct device *dev)
388 {
389 struct espi_reg *const inst = HAL_INSTANCE(dev);
390 struct espi_npcx_data *const data = dev->data;
391
392 /* Controller Attached Flash Access */
393 if ((inst->ESPICFG & BIT(NPCX_ESPICFG_FLCHANMODE)) == 0) {
394 #ifdef CONFIG_ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND
395 if (data->fake_req_flag == true) {
396 uint8_t pckt_buf[16];
397 struct espi_flash_packet pckt;
398
399 pckt.buf = &pckt_buf[0];
400 espi_npcx_flash_parse_completion_with_data(dev, &pckt);
401 data->fake_req_flag = false;
402 return;
403 }
404 #endif
405 k_sem_give(&data->flash_rx_lock);
406 } else { /* Target Attached Flash Access */
407 #if defined(CONFIG_ESPI_TAF)
408 struct espi_event evt = {
409 .evt_type = ESPI_BUS_TAF_NOTIFICATION,
410 .evt_details = ESPI_CHANNEL_FLASH,
411 .evt_data = espi_taf_parse(dev),
412 };
413 espi_send_callbacks(&data->callbacks, dev, evt);
414 #else
415 LOG_WRN("ESPI TAF not supported");
416 #endif
417 }
418 }
419 #endif /* CONFIG_ESPI_FLASH_CHANNEL */
420
421 const struct espi_bus_isr espi_bus_isr_tbl[] = {
422 NPCX_ESPI_BUS_INT_ITEM(BERR, espi_bus_err_isr),
423 NPCX_ESPI_BUS_INT_ITEM(IBRST, espi_bus_inband_rst_isr),
424 NPCX_ESPI_BUS_INT_ITEM(ESPIRST, espi_bus_reset_isr),
425 NPCX_ESPI_BUS_INT_ITEM(CFGUPD, espi_bus_cfg_update_isr),
426 #if defined(CONFIG_ESPI_OOB_CHANNEL)
427 NPCX_ESPI_BUS_INT_ITEM(OOBRX, espi_bus_oob_rx_isr),
428 #endif
429 #if defined(CONFIG_ESPI_FLASH_CHANNEL)
430 NPCX_ESPI_BUS_INT_ITEM(FLASHRX, espi_bus_flash_rx_isr),
431 #endif
432 };
433
espi_bus_generic_isr(const struct device * dev)434 static void espi_bus_generic_isr(const struct device *dev)
435 {
436 struct espi_reg *const inst = HAL_INSTANCE(dev);
437 int i;
438 uint32_t mask, status;
439
440 /*
441 * Bit 17 of ESPIIE is reserved. We need to set the same bit in mask
442 * in case bit 17 in ESPISTS of npcx7 is not cleared in ISR.
443 */
444 mask = inst->ESPIIE | (1 << NPCX_ESPISTS_VWUPDW);
445 status = inst->ESPISTS & mask;
446
447 /* Clear pending bits of status register first */
448 inst->ESPISTS = status;
449
450 LOG_DBG("%s: 0x%08X", __func__, status);
451 for (i = 0; i < ARRAY_SIZE(espi_bus_isr_tbl); i++) {
452 struct espi_bus_isr entry = espi_bus_isr_tbl[i];
453
454 if (status & BIT(entry.status_bit)) {
455 if (entry.bus_isr != NULL) {
456 entry.bus_isr(dev);
457 }
458 }
459 }
460 }
461
462 /* eSPI local virtual-wire service functions */
espi_vw_config_input(const struct device * dev,const struct npcx_vw_in_config * config_in)463 static void espi_vw_config_input(const struct device *dev,
464 const struct npcx_vw_in_config *config_in)
465 {
466 struct espi_reg *const inst = HAL_INSTANCE(dev);
467 int idx = config_in->reg_idx;
468
469 /* IE & WE bits are already set? */
470 if (IS_BIT_SET(inst->VWEVMS[idx], NPCX_VWEVMS_IE) &&
471 IS_BIT_SET(inst->VWEVMS[idx], NPCX_VWEVMS_WE))
472 return;
473
474 /* Set IE & WE bits in VWEVMS */
475 inst->VWEVMS[idx] |= BIT(NPCX_VWEVMS_IE) | BIT(NPCX_VWEVMS_WE);
476 LOG_DBG("VWEVMS%d 0x%08X", idx, inst->VWEVMS[idx]);
477 }
478
espi_vw_config_output(const struct device * dev,const struct npcx_vw_out_config * config_out)479 static void espi_vw_config_output(const struct device *dev,
480 const struct npcx_vw_out_config *config_out)
481 {
482 struct espi_reg *const inst = HAL_INSTANCE(dev);
483 int idx = config_out->reg_idx;
484 uint8_t valid = GET_FIELD(inst->VWEVSM[idx], NPCX_VWEVSM_VALID);
485
486 /* Set valid bits for vw signal which we have declared in table. */
487 valid |= config_out->bitmask;
488 SET_FIELD(inst->VWEVSM[idx], NPCX_VWEVSM_VALID, valid);
489
490 /*
491 * Turn off hardware-wire feature which generates VW events that
492 * connected to hardware signals. We will set it manually by software.
493 */
494 SET_FIELD(inst->VWEVSM[idx], NPCX_VWEVSM_HW_WIRE, 0);
495
496 LOG_DBG("VWEVSM%d 0x%08X", idx, inst->VWEVSM[idx]);
497 }
498
espi_vw_gpio_config_output(const struct device * dev,const struct npcx_vw_out_config * config_out,uint8_t init_level)499 static void espi_vw_gpio_config_output(const struct device *dev,
500 const struct npcx_vw_out_config *config_out,
501 uint8_t init_level)
502 {
503 struct espi_reg *const inst = HAL_INSTANCE(dev);
504 int idx = config_out->reg_idx;
505 uint8_t valid = GET_FIELD(inst->VWGPSM[idx], NPCX_VWEVSM_VALID);
506 uint8_t val = GET_FIELD(inst->VWGPSM[idx], NPCX_VWEVSM_WIRE);
507
508 /* Set valid bits for vw signal which we have declared in table. */
509 valid |= config_out->bitmask;
510 SET_FIELD(inst->VWGPSM[idx], NPCX_VWEVSM_VALID, valid);
511
512 inst->VWGPSM[idx] |= BIT(NPCX_VWGPSM_INDEX_EN);
513
514 if (init_level) {
515 val |= config_out->bitmask;
516 } else {
517 val &= ~config_out->bitmask;
518 }
519
520 SET_FIELD(inst->VWGPSM[idx], NPCX_VWEVSM_WIRE, val);
521
522 LOG_DBG("VWEVSM%d 0x%08X", idx, inst->VWGPSM[idx]);
523 }
524
espi_vw_notify_system_state(const struct device * dev,enum espi_vwire_signal signal)525 static void espi_vw_notify_system_state(const struct device *dev,
526 enum espi_vwire_signal signal)
527 {
528 struct espi_npcx_data *const data = dev->data;
529 struct espi_event evt = { ESPI_BUS_EVENT_VWIRE_RECEIVED, 0, 0 };
530 uint8_t wire = 0;
531
532 espi_npcx_receive_vwire(dev, signal, &wire);
533 if (!wire) {
534 data->sx_state = signal;
535 }
536
537 evt.evt_details = signal;
538 evt.evt_data = wire;
539 espi_send_callbacks(&data->callbacks, dev, evt);
540 }
541
espi_vw_notify_host_warning(const struct device * dev,enum espi_vwire_signal signal)542 static void espi_vw_notify_host_warning(const struct device *dev,
543 enum espi_vwire_signal signal)
544 {
545 uint8_t wire;
546
547 espi_npcx_receive_vwire(dev, signal, &wire);
548
549 k_busy_wait(NPCX_ESPI_VWIRE_ACK_DELAY);
550 switch (signal) {
551 case ESPI_VWIRE_SIGNAL_HOST_RST_WARN:
552 espi_npcx_send_vwire(dev,
553 ESPI_VWIRE_SIGNAL_HOST_RST_ACK,
554 wire);
555 break;
556 case ESPI_VWIRE_SIGNAL_SUS_WARN:
557 espi_npcx_send_vwire(dev, ESPI_VWIRE_SIGNAL_SUS_ACK,
558 wire);
559 break;
560 case ESPI_VWIRE_SIGNAL_OOB_RST_WARN:
561 espi_npcx_send_vwire(dev, ESPI_VWIRE_SIGNAL_OOB_RST_ACK,
562 wire);
563 break;
564 default:
565 break;
566 }
567 }
568
espi_vw_notify_plt_rst(const struct device * dev)569 static void espi_vw_notify_plt_rst(const struct device *dev)
570 {
571 struct espi_npcx_data *const data = dev->data;
572 struct espi_reg *const inst = HAL_INSTANCE(dev);
573 struct espi_event evt = { ESPI_BUS_EVENT_VWIRE_RECEIVED,
574 ESPI_VWIRE_SIGNAL_PLTRST, 0
575 };
576 uint8_t wire = 0;
577
578 espi_npcx_receive_vwire(dev, ESPI_VWIRE_SIGNAL_PLTRST, &wire);
579 LOG_DBG("VW_PLT_RST is %d!", wire);
580 if (wire) {
581 /* Set Peripheral Channel ready when PLTRST is de-asserted */
582 inst->ESPICFG |= BIT(NPCX_ESPICFG_PCHANEN);
583 /* Configure all host sub-modules in host domain */
584 npcx_host_init_subs_host_domain();
585 }
586
587 /* PLT_RST will be received several times */
588 if (wire != data->plt_rst_asserted) {
589 data->plt_rst_asserted = wire;
590 evt.evt_data = wire;
591 espi_send_callbacks(&data->callbacks, dev, evt);
592 }
593 }
594
espi_vw_send_bootload_done(const struct device * dev)595 static void espi_vw_send_bootload_done(const struct device *dev)
596 {
597 int ret;
598 uint8_t boot_done;
599
600 ret = espi_npcx_receive_vwire(dev,
601 ESPI_VWIRE_SIGNAL_TARGET_BOOT_DONE, &boot_done);
602 LOG_DBG("%s: %d", __func__, boot_done);
603 if (!ret && !boot_done) {
604 /* Send slave boot status bit with done bit at the same time. */
605 espi_npcx_send_vwire(dev, ESPI_VWIRE_SIGNAL_TARGET_BOOT_STS, 1);
606 }
607 }
608
espi_vw_generic_isr(const struct device * dev,struct npcx_wui * wui)609 static void espi_vw_generic_isr(const struct device *dev, struct npcx_wui *wui)
610 {
611 int idx;
612 enum espi_vwire_signal signal;
613
614 LOG_DBG("%s: WUI %d %d %d", __func__, wui->table, wui->group, wui->bit);
615 for (idx = 0; idx < ARRAY_SIZE(vw_in_tbl); idx++) {
616 if (wui->table == vw_in_tbl[idx].vw_wui.table &&
617 wui->group == vw_in_tbl[idx].vw_wui.group &&
618 wui->bit == vw_in_tbl[idx].vw_wui.bit) {
619 break;
620 }
621 }
622
623 if (idx == ARRAY_SIZE(vw_in_tbl)) {
624 LOG_ERR("Unknown VW event! %d %d %d", wui->table,
625 wui->group, wui->bit);
626 return;
627 }
628
629 signal = vw_in_tbl[idx].sig;
630 if (signal == ESPI_VWIRE_SIGNAL_SLP_S3
631 || signal == ESPI_VWIRE_SIGNAL_SLP_S4
632 || signal == ESPI_VWIRE_SIGNAL_SLP_S5
633 || signal == ESPI_VWIRE_SIGNAL_SLP_A) {
634 espi_vw_notify_system_state(dev, signal);
635 } else if (signal == ESPI_VWIRE_SIGNAL_HOST_RST_WARN
636 || signal == ESPI_VWIRE_SIGNAL_SUS_WARN
637 || signal == ESPI_VWIRE_SIGNAL_OOB_RST_WARN) {
638 espi_vw_notify_host_warning(dev, signal);
639 } else if (signal == ESPI_VWIRE_SIGNAL_PLTRST) {
640 espi_vw_notify_plt_rst(dev);
641 }
642 }
643
espi_vw_espi_rst_isr(const struct device * dev,struct npcx_wui * wui)644 static void espi_vw_espi_rst_isr(const struct device *dev, struct npcx_wui *wui)
645 {
646 struct espi_reg *const inst = HAL_INSTANCE(dev);
647 struct espi_npcx_data *const data = dev->data;
648 struct espi_event evt = { ESPI_BUS_RESET, 0, 0 };
649
650 data->espi_rst_level = IS_BIT_SET(inst->ESPISTS,
651 NPCX_ESPISTS_ESPIRST_LVL);
652 LOG_DBG("eSPI RST level is %d!", data->espi_rst_level);
653
654 evt.evt_data = data->espi_rst_level;
655 espi_send_callbacks(&data->callbacks, dev, evt);
656 }
657
658 /* eSPI api functions */
espi_npcx_configure(const struct device * dev,struct espi_cfg * cfg)659 static int espi_npcx_configure(const struct device *dev, struct espi_cfg *cfg)
660 {
661 struct espi_reg *const inst = HAL_INSTANCE(dev);
662
663 uint8_t max_freq = 0;
664 uint8_t cur_io_mode, io_mode = 0;
665
666 /* Configure eSPI frequency */
667 switch (cfg->max_freq) {
668 case 20:
669 max_freq = NPCX_ESPI_MAXFREQ_20;
670 break;
671 case 25:
672 max_freq = NPCX_ESPI_MAXFREQ_25;
673 break;
674 case 33:
675 max_freq = NPCX_ESPI_MAXFREQ_33;
676 break;
677 case 50:
678 max_freq = NPCX_ESPI_MAXFREQ_50;
679 break;
680 #ifdef CONFIG_SOC_SERIES_NPCX4
681 case 66:
682 max_freq = NPCX_ESPI_MAXFREQ_66;
683 break;
684 #endif
685 default:
686 return -EINVAL;
687 }
688 SET_FIELD(inst->ESPICFG, NPCX_ESPICFG_MAXFREQ_FIELD, max_freq);
689
690 /* Configure eSPI IO mode */
691 io_mode = (cfg->io_caps >> 1);
692 if (io_mode > 3) {
693 return -EINVAL;
694 }
695
696 cur_io_mode = GET_FIELD(inst->ESPICFG, NPCX_ESPICFG_IOMODE_FIELD);
697 if (io_mode != cur_io_mode) {
698 SET_FIELD(inst->ESPICFG, NPCX_ESPICFG_IOMODE_FIELD, io_mode);
699 }
700
701 /* Configure eSPI supported channels */
702 if (cfg->channel_caps & ESPI_CHANNEL_PERIPHERAL)
703 inst->ESPICFG |= BIT(NPCX_ESPICFG_PCCHN_SUPP);
704
705 if (cfg->channel_caps & ESPI_CHANNEL_VWIRE)
706 inst->ESPICFG |= BIT(NPCX_ESPICFG_VWCHN_SUPP);
707
708 if (cfg->channel_caps & ESPI_CHANNEL_OOB)
709 inst->ESPICFG |= BIT(NPCX_ESPICFG_OOBCHN_SUPP);
710
711 if (cfg->channel_caps & ESPI_CHANNEL_FLASH)
712 inst->ESPICFG |= BIT(NPCX_ESPICFG_FLASHCHN_SUPP);
713
714 LOG_DBG("%s: %d %d ESPICFG: 0x%08X", __func__,
715 max_freq, io_mode, inst->ESPICFG);
716
717 return 0;
718 }
719
espi_npcx_channel_ready(const struct device * dev,enum espi_channel ch)720 static bool espi_npcx_channel_ready(const struct device *dev,
721 enum espi_channel ch)
722 {
723 struct espi_reg *const inst = HAL_INSTANCE(dev);
724 bool sts;
725
726 switch (ch) {
727 case ESPI_CHANNEL_PERIPHERAL:
728 sts = IS_BIT_SET(inst->ESPICFG, NPCX_ESPICFG_PCHANEN);
729 break;
730 case ESPI_CHANNEL_VWIRE:
731 sts = IS_BIT_SET(inst->ESPICFG, NPCX_ESPICFG_VWCHANEN);
732 break;
733 case ESPI_CHANNEL_OOB:
734 sts = IS_BIT_SET(inst->ESPICFG, NPCX_ESPICFG_OOBCHANEN);
735 break;
736 case ESPI_CHANNEL_FLASH:
737 sts = IS_BIT_SET(inst->ESPICFG, NPCX_ESPICFG_FLASHCHANEN);
738 break;
739 default:
740 sts = false;
741 break;
742 }
743
744 return sts;
745 }
746
espi_npcx_send_vwire(const struct device * dev,enum espi_vwire_signal signal,uint8_t level)747 static int espi_npcx_send_vwire(const struct device *dev,
748 enum espi_vwire_signal signal, uint8_t level)
749 {
750 uint8_t reg_idx, bitmask, sig_idx, val = 0, vw_tbl_size;
751 struct espi_reg *const inst = HAL_INSTANCE(dev);
752 const struct npcx_vw_out_config *vw_tbl;
753 uint32_t reg_val;
754 char *reg_name;
755
756 if (signal >= ESPI_VWIRE_SIGNAL_COUNT) {
757 LOG_ERR("Invalid VW: %d", signal);
758 return -EINVAL;
759 }
760
761 if (signal >= ESPI_VWIRE_SIGNAL_TARGET_GPIO_0) {
762 vw_tbl = vw_out_gpio_tbl1;
763 vw_tbl_size = ARRAY_SIZE(vw_out_gpio_tbl1);
764 reg_name = "VWGPSM";
765 } else {
766 vw_tbl = vw_out_tbl;
767 vw_tbl_size = ARRAY_SIZE(vw_out_tbl);
768 reg_name = "VWEVSM";
769 }
770
771 /* Find signal in VW output table */
772 for (sig_idx = 0; sig_idx < vw_tbl_size; sig_idx++)
773 if (vw_tbl[sig_idx].sig == signal)
774 break;
775
776 if (sig_idx == vw_tbl_size) {
777 LOG_ERR("%s signal %d is invalid", __func__, signal);
778 return -EIO;
779 }
780
781 reg_idx = vw_tbl[sig_idx].reg_idx;
782 bitmask = vw_tbl[sig_idx].bitmask;
783
784 /* Get wire field and set/clear wire bit */
785 if (signal >= ESPI_VWIRE_SIGNAL_TARGET_GPIO_0) {
786 val = GET_FIELD(inst->VWGPSM[reg_idx], NPCX_VWEVSM_WIRE);
787 } else {
788 val = GET_FIELD(inst->VWEVSM[reg_idx], NPCX_VWEVSM_WIRE);
789 }
790
791 if (level) {
792 val |= bitmask;
793 } else {
794 val &= ~bitmask;
795 }
796
797 if (signal >= ESPI_VWIRE_SIGNAL_TARGET_GPIO_0) {
798 SET_FIELD(inst->VWGPSM[reg_idx], NPCX_VWEVSM_WIRE, val);
799 reg_val = inst->VWGPSM[reg_idx];
800 } else {
801 SET_FIELD(inst->VWEVSM[reg_idx], NPCX_VWEVSM_WIRE, val);
802 reg_val = inst->VWEVSM[reg_idx];
803 }
804
805 LOG_DBG("Send VW: %s%d 0x%08X", reg_name, reg_idx, reg_val);
806
807 return 0;
808 }
809
espi_npcx_receive_vwire(const struct device * dev,enum espi_vwire_signal signal,uint8_t * level)810 static int espi_npcx_receive_vwire(const struct device *dev,
811 enum espi_vwire_signal signal, uint8_t *level)
812 {
813 struct espi_reg *const inst = HAL_INSTANCE(dev);
814 uint8_t reg_idx, bitmask, sig_idx, val;
815
816 /* Find signal in VW input table */
817 for (sig_idx = 0; sig_idx < ARRAY_SIZE(vw_in_tbl); sig_idx++)
818 if (vw_in_tbl[sig_idx].sig == signal) {
819 reg_idx = vw_in_tbl[sig_idx].reg_idx;
820 bitmask = vw_in_tbl[sig_idx].bitmask;
821
822 val = GET_FIELD(inst->VWEVMS[reg_idx],
823 NPCX_VWEVMS_WIRE);
824 val &= GET_FIELD(inst->VWEVMS[reg_idx],
825 NPCX_VWEVMS_VALID);
826
827 *level = !!(val & bitmask);
828 return 0;
829 }
830
831 /* Find signal in VW output table */
832 for (sig_idx = 0; sig_idx < ARRAY_SIZE(vw_out_tbl); sig_idx++)
833 if (vw_out_tbl[sig_idx].sig == signal) {
834 reg_idx = vw_out_tbl[sig_idx].reg_idx;
835 bitmask = vw_out_tbl[sig_idx].bitmask;
836
837 val = GET_FIELD(inst->VWEVSM[reg_idx],
838 NPCX_VWEVSM_WIRE);
839 val &= GET_FIELD(inst->VWEVSM[reg_idx],
840 NPCX_VWEVSM_VALID);
841 *level = !!(val & bitmask);
842 return 0;
843 }
844
845 LOG_ERR("%s Out of index %d", __func__, signal);
846 return -EIO;
847 }
848
espi_npcx_manage_callback(const struct device * dev,struct espi_callback * callback,bool set)849 static int espi_npcx_manage_callback(const struct device *dev,
850 struct espi_callback *callback, bool set)
851 {
852 struct espi_npcx_data *const data = dev->data;
853
854 return espi_manage_callback(&data->callbacks, callback, set);
855 }
856
espi_npcx_read_lpc_request(const struct device * dev,enum lpc_peripheral_opcode op,uint32_t * data)857 static int espi_npcx_read_lpc_request(const struct device *dev,
858 enum lpc_peripheral_opcode op,
859 uint32_t *data)
860 {
861 ARG_UNUSED(dev);
862
863 return npcx_host_periph_read_request(op, data);
864 }
865
espi_npcx_write_lpc_request(const struct device * dev,enum lpc_peripheral_opcode op,uint32_t * data)866 static int espi_npcx_write_lpc_request(const struct device *dev,
867 enum lpc_peripheral_opcode op,
868 uint32_t *data)
869 {
870 ARG_UNUSED(dev);
871
872 return npcx_host_periph_write_request(op, data);
873 }
874
875 #if defined(CONFIG_ESPI_OOB_CHANNEL)
espi_npcx_send_oob(const struct device * dev,struct espi_oob_packet * pckt)876 static int espi_npcx_send_oob(const struct device *dev,
877 struct espi_oob_packet *pckt)
878 {
879 struct espi_reg *const inst = HAL_INSTANCE(dev);
880 uint8_t *oob_buf = pckt->buf;
881 int sz_oob_tx = pckt->len;
882 int idx_tx_buf;
883 uint32_t oob_data;
884
885 /* Check out of OOB transmitted buffer size */
886 if (sz_oob_tx > NPCX_ESPI_OOB_MAX_PAYLOAD) {
887 LOG_ERR("Out of OOB transmitted buffer: %d", sz_oob_tx);
888 return -EINVAL;
889 }
890
891 /* Check OOB Transmit Queue is empty? */
892 if (IS_BIT_SET(inst->OOBCTL, NPCX_OOBCTL_OOB_AVAIL)) {
893 LOG_ERR("OOB channel is busy");
894 return -EBUSY;
895 }
896
897 /*
898 * GET_OOB header (first 4 bytes) in npcx 32-bits tx buffer
899 *
900 * [24:31] - LEN[0:7] Data length of GET_OOB request package
901 * [20:23] - TAG Tag of GET_OOB
902 * [16:19] - LEN[8:11] Ignore it since max payload is 64 bytes
903 * [8:15] - CYCLE_TYPE Cycle type of GET_OOB
904 * [0:7] - SZ_PACK Package size plus 3 bytes header. (Npcx only)
905 */
906 inst->OOBTXBUF[0] = (sz_oob_tx + 3)
907 | (ESPI_OOB_GET_CYCLE_TYPE << 8)
908 | (ESPI_OOB_TAG << 16)
909 | (sz_oob_tx << 24);
910
911 /* Write GET_OOB data into 32-bits tx buffer in little endian */
912 for (idx_tx_buf = 0; idx_tx_buf < sz_oob_tx/4; idx_tx_buf++,
913 oob_buf += 4)
914 inst->OOBTXBUF[idx_tx_buf + 1] = oob_buf[0]
915 | (oob_buf[1] << 8)
916 | (oob_buf[2] << 16)
917 | (oob_buf[3] << 24);
918
919 /* Write remaining bytes of package */
920 if (sz_oob_tx % 4) {
921 int i;
922
923 oob_data = 0;
924 for (i = 0; i < sz_oob_tx % 4; i++)
925 oob_data |= (oob_buf[i] << (8 * i));
926 inst->OOBTXBUF[idx_tx_buf + 1] = oob_data;
927 }
928
929 /*
930 * Notify host a new OOB packet is ready. Please don't write OOB_FREE
931 * to 1 at the same tiem in case clear it unexpectedly.
932 */
933 oob_data = inst->OOBCTL & ~(BIT(NPCX_OOBCTL_OOB_FREE));
934 oob_data |= BIT(NPCX_OOBCTL_OOB_AVAIL);
935 inst->OOBCTL = oob_data;
936
937 while (IS_BIT_SET(inst->OOBCTL, NPCX_OOBCTL_OOB_AVAIL))
938 ;
939
940 LOG_DBG("%s issued!!", __func__);
941 return 0;
942 }
943
espi_npcx_receive_oob(const struct device * dev,struct espi_oob_packet * pckt)944 static int espi_npcx_receive_oob(const struct device *dev,
945 struct espi_oob_packet *pckt)
946 {
947 struct espi_reg *const inst = HAL_INSTANCE(dev);
948 uint8_t *oob_buf = pckt->buf;
949 uint32_t oob_data;
950 int idx_rx_buf, sz_oob_rx;
951
952 /* Check eSPI bus status first */
953 if (IS_BIT_SET(inst->ESPISTS, NPCX_ESPISTS_BERR)) {
954 LOG_ERR("%s: eSPI Bus Error: 0x%08X", __func__, inst->ESPIERR);
955 return -EIO;
956 }
957
958 #if !defined(CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC)
959 struct espi_npcx_data *const data = dev->data;
960 int ret;
961
962 /* Wait until get oob package or timeout */
963 ret = k_sem_take(&data->oob_rx_lock, K_MSEC(ESPI_OOB_MAX_TIMEOUT));
964 if (ret == -EAGAIN) {
965 LOG_ERR("%s: Timeout", __func__);
966 return -ETIMEDOUT;
967 }
968 #endif
969
970 /*
971 * PUT_OOB header (first 4 bytes) in npcx 32-bits rx buffer
972 *
973 * [24:31] - LEN[0:7] Data length of PUT_OOB request package
974 * [20:23] - TAG Tag of PUT_OOB
975 * [16:19] - LEN[8:11] Data length of PUT_OOB request package
976 * [8:15] - CYCLE_TYPE Cycle type of PUT_OOB
977 * [0:7] - SZ_PACK Reserved. (Npcx only)
978 */
979 oob_data = inst->OOBRXBUF[0];
980 /* Get received package length first */
981 sz_oob_rx = NPCX_OOB_RX_PACKAGE_LEN(oob_data);
982
983 /* Check OOB received buffer size */
984 if (sz_oob_rx > NPCX_ESPI_OOB_MAX_PAYLOAD) {
985 LOG_ERR("Out of OOB received buffer: %d", sz_oob_rx);
986 return -EINVAL;
987 }
988
989 /* Set received size to package structure */
990 pckt->len = sz_oob_rx;
991
992 /* Read PUT_OOB data into 32-bits rx buffer in little endian */
993 for (idx_rx_buf = 0; idx_rx_buf < sz_oob_rx/4; idx_rx_buf++) {
994 oob_data = inst->OOBRXBUF[idx_rx_buf + 1];
995
996 *(oob_buf++) = oob_data & 0xFF;
997 *(oob_buf++) = (oob_data >> 8) & 0xFF;
998 *(oob_buf++) = (oob_data >> 16) & 0xFF;
999 *(oob_buf++) = (oob_data >> 24) & 0xFF;
1000 }
1001
1002 /* Read remaining bytes of package */
1003 if (sz_oob_rx % 4) {
1004 int i;
1005
1006 oob_data = inst->OOBRXBUF[idx_rx_buf + 1];
1007 for (i = 0; i < sz_oob_rx % 4; i++)
1008 *(oob_buf++) = (oob_data >> (8 * i)) & 0xFF;
1009 }
1010
1011 /* Notify host that OOB received buffer is free now. */
1012 inst->OOBCTL |= BIT(NPCX_OOBCTL_OOB_FREE);
1013 return 0;
1014 }
1015 #endif
1016
1017 #ifdef CONFIG_ESPI_FLASH_CHANNEL
espi_npcx_flash_prepare_tx_header(const struct device * dev,int cyc_type,int flash_addr,int flash_len,int tx_payload)1018 static void espi_npcx_flash_prepare_tx_header(const struct device *dev,
1019 int cyc_type, int flash_addr, int flash_len, int tx_payload)
1020 {
1021 struct espi_reg *const inst = HAL_INSTANCE(dev);
1022
1023 /*
1024 * First 3 bytes of flash cycle command header in tx buffer
1025 *
1026 * [24:31] - LEN[0:7] = n Data length of flash cycle request
1027 * [16:23] - LEN[8:15] = 0 Ignore it since max buffer size is 64 bytes
1028 * [12:15] - TAG = 0 Tag of flash cycle command is always 0 here
1029 * [8:11] - CYCLE_TYPE = 0 Cycle type of flash command
1030 * [0:7] - SZ_PACK = 7 Overall tx package size. (Used internally.)
1031 */
1032 inst->FLASHTXBUF[0] = (flash_len << 24) |
1033 (cyc_type << 8) |
1034 (tx_payload + ESPI_FLASH_HEADER_PCKT_SIZE);
1035
1036 /*
1037 * Following 4 bytes of tager flash address in tx buffer
1038 *
1039 * [24:31] - ADDR[0:7] Start address of flash cycle command request
1040 * [16:23] - ADDR[15:8]
1041 * [8:15] - ADDR[23:16]
1042 * [0:7] - ADDR[31:24]
1043 */
1044 inst->FLASHTXBUF[1] = sys_cpu_to_be32(flash_addr);
1045
1046 }
1047
espi_npcx_flash_parse_completion(const struct device * dev)1048 static int espi_npcx_flash_parse_completion(const struct device *dev)
1049 {
1050 int cycle_type;
1051 struct espi_reg *const inst = HAL_INSTANCE(dev);
1052
1053 /*
1054 * First 3 bytes of flash cycle completion header in rx buffer
1055 *
1056 * [24:31] - LEN[0:7] Data length of flash cycle completion package
1057 * [16:23] - LEN[8:15] Ignore it since rx bufer size is 64 bytes
1058 * [12:15] - TAG Tag of flash cycle completion package
1059 * [8:11] - CYCLE_TYPE Cycle type of flash completion
1060 * [0:7] - Reserved
1061 */
1062 cycle_type = (inst->FLASHRXBUF[0] & 0xff00) >> 8;
1063 if (cycle_type == ESPI_FLASH_SUCCESS_WITHOUT_DATA_CYCLE_TYPE) {
1064 return 0;
1065 }
1066
1067 return -EIO;
1068 }
1069
espi_npcx_flash_parse_completion_with_data(const struct device * dev,struct espi_flash_packet * pckt)1070 static int espi_npcx_flash_parse_completion_with_data(const struct device *dev,
1071 struct espi_flash_packet *pckt)
1072 {
1073 struct espi_reg *const inst = HAL_INSTANCE(dev);
1074 int cycle_type, sz_rx_payload;
1075
1076 /*
1077 * First 3 bytes of flash cycle completion header in rx buffer
1078 *
1079 * [24:31] - LEN[0:7] Data length of flash cycle completion package
1080 * [16:23] - LEN[8:15] Ignore it since rx bufer size is 64 bytes
1081 * [12:15] - TAG Tag of flash cycle completion package
1082 * [8:11] - CYCLE_TYPE Cycle type of flash completion
1083 * [0:7] - Reserved
1084 *
1085 * The following is flash data/
1086 */
1087 cycle_type = (inst->FLASHRXBUF[0] & 0xff00) >> 8;
1088 sz_rx_payload = inst->FLASHRXBUF[0] >> 24;
1089 if (cycle_type == ESPI_FLASH_SUCCESS_WITH_DATA_CYCLE_TYPE) {
1090 volatile uint32_t *rx_buf = &inst->FLASHRXBUF[1];
1091 uint8_t *buf = pckt->buf;
1092 uint32_t data;
1093
1094 /* Get data from flash RX buffer */
1095 for (int i = 0; i < sz_rx_payload / 4; i++, rx_buf++) {
1096 data = *rx_buf;
1097 for (int j = 0; j < 4; j++, buf++) {
1098 *buf = data & 0xff;
1099 data = data >> 8;
1100 }
1101 }
1102
1103 /* Get remaining bytes */
1104 if (sz_rx_payload % 4) {
1105 data = *rx_buf;
1106 for (int j = 0; j < sz_rx_payload % 4; j++, buf++) {
1107 *buf = data & 0xff;
1108 data = data >> 8;
1109 }
1110 }
1111
1112 return 0;
1113 }
1114
1115 return -EIO;
1116 }
1117
espi_npcx_flash_read(const struct device * dev,struct espi_flash_packet * pckt)1118 static int espi_npcx_flash_read(const struct device *dev,
1119 struct espi_flash_packet *pckt)
1120 {
1121 int ret;
1122 struct espi_reg *const inst = HAL_INSTANCE(dev);
1123 struct espi_npcx_data *const data = dev->data;
1124
1125 /* Check out of FLASH received buffer size */
1126 if (pckt->len > NPCX_ESPI_FLASH_MAX_RX_PAYLOAD) {
1127 LOG_ERR("Out of FLASH transmitted buffer: %d", pckt->len);
1128 return -EINVAL;
1129 }
1130
1131 /* Check Flash Transmit Queue is empty? */
1132 if (IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_FLASH_TX_AVAIL)) {
1133 LOG_ERR("flash channel is busy");
1134 return -EBUSY;
1135 }
1136
1137 /* Prepare FLASH_READ header in tx buffer */
1138 espi_npcx_flash_prepare_tx_header(dev,
1139 ESPI_FLASH_READ_CYCLE_TYPE,
1140 pckt->flash_addr,
1141 pckt->len,
1142 0);
1143
1144 /* Set the FLASHCTL.FLASH_TX_AVAIL bit to 1 to enqueue the packet */
1145 inst->FLASHCTL |= BIT(NPCX_FLASHCTL_FLASH_TX_AVAIL);
1146
1147 /* Wait until get flash package or timeout */
1148 ret = k_sem_take(&data->flash_rx_lock, K_MSEC(ESPI_FLASH_MAX_TIMEOUT));
1149 if (ret == -EAGAIN) {
1150 LOG_ERR("%s: Timeout", __func__);
1151 return -ETIMEDOUT;
1152 }
1153
1154 return espi_npcx_flash_parse_completion_with_data(dev, pckt);
1155 }
1156
espi_npcx_flash_write(const struct device * dev,struct espi_flash_packet * pckt)1157 static int espi_npcx_flash_write(const struct device *dev,
1158 struct espi_flash_packet *pckt)
1159 {
1160 int ret;
1161 uint32_t tx_data;
1162 struct espi_reg *const inst = HAL_INSTANCE(dev);
1163 struct espi_npcx_data *const data = dev->data;
1164 volatile uint32_t *tx_buf = &inst->FLASHTXBUF[2];
1165 uint8_t *buf = pckt->buf;
1166
1167 /* Check out of FLASH transmitted buffer size */
1168 if (pckt->len > NPCX_ESPI_FLASH_MAX_TX_PAYLOAD) {
1169 LOG_ERR("Out of FLASH transmitted buffer: %d", pckt->len);
1170 return -EINVAL;
1171 }
1172
1173 /* Check Flash Transmit Queue is empty? */
1174 if (IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_FLASH_TX_AVAIL)) {
1175 LOG_ERR("flash channel is busy");
1176 return -EBUSY;
1177 }
1178
1179 /* Prepare FLASH_WRITE header in tx buffer */
1180 espi_npcx_flash_prepare_tx_header(dev,
1181 ESPI_FLASH_WRITE_CYCLE_TYPE,
1182 pckt->flash_addr,
1183 pckt->len,
1184 pckt->len);
1185
1186 /* Put package data to flash TX buffer */
1187 for (int i = 0; i < pckt->len / 4; i++, tx_buf++) {
1188 tx_data = 0;
1189 for (int j = 0; j < 4; j++, buf++) {
1190 tx_data |= (*buf << (j * 8));
1191 }
1192 *tx_buf = tx_data;
1193 }
1194
1195 /* Put remaining bytes to flash TX buffer */
1196 if (pckt->len % 4) {
1197 tx_data = 0;
1198 for (int j = 0; j < pckt->len % 4; j++, buf++) {
1199 tx_data |= (*buf << (j * 8));
1200 }
1201 *tx_buf = tx_data;
1202 }
1203
1204 /* Set the FLASHCTL.FLASH_TX_AVAIL bit to 1 to enqueue the packet */
1205 inst->FLASHCTL |= BIT(NPCX_FLASHCTL_FLASH_TX_AVAIL);
1206
1207 /* Wait until get flash package or timeout */
1208 ret = k_sem_take(&data->flash_rx_lock, K_MSEC(ESPI_FLASH_MAX_TIMEOUT));
1209 if (ret == -EAGAIN) {
1210 LOG_ERR("%s: Timeout", __func__);
1211 return -ETIMEDOUT;
1212 }
1213
1214 /* Parse completion package in rx buffer */
1215 return espi_npcx_flash_parse_completion(dev);
1216 }
1217
espi_npcx_flash_erase(const struct device * dev,struct espi_flash_packet * pckt)1218 static int espi_npcx_flash_erase(const struct device *dev,
1219 struct espi_flash_packet *pckt)
1220 {
1221 int ret;
1222 struct espi_reg *const inst = HAL_INSTANCE(dev);
1223 struct espi_npcx_data *const data = dev->data;
1224
1225 /* Check Flash Transmit Queue is empty? */
1226 if (IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_FLASH_TX_AVAIL)) {
1227 LOG_ERR("flash channel is busy");
1228 return -EBUSY;
1229 }
1230
1231 /* Prepare FLASH_ERASE header in tx buffer */
1232 espi_npcx_flash_prepare_tx_header(dev,
1233 ESPI_FLASH_ERASE_CYCLE_TYPE,
1234 pckt->flash_addr,
1235 pckt->len,
1236 0);
1237
1238 /* Set the FLASHCTL.FLASH_TX_AVAIL bit to 1 to enqueue the packet */
1239 inst->FLASHCTL |= BIT(NPCX_FLASHCTL_FLASH_TX_AVAIL);
1240
1241 /* Wait until get flash package or timeout */
1242 ret = k_sem_take(&data->flash_rx_lock, K_MSEC(ESPI_FLASH_MAX_TIMEOUT));
1243 if (ret == -EAGAIN) {
1244 LOG_ERR("%s: Timeout", __func__);
1245 return -ETIMEDOUT;
1246 }
1247
1248 /* Parse completion package in rx buffer */
1249 return espi_npcx_flash_parse_completion(dev);
1250 }
1251 #endif
1252
1253 /* Platform specific espi module functions */
npcx_espi_enable_interrupts(const struct device * dev)1254 void npcx_espi_enable_interrupts(const struct device *dev)
1255 {
1256 const struct espi_npcx_config *const config = dev->config;
1257
1258 /* Enable eSPI bus interrupt */
1259 irq_enable(DT_INST_IRQN(0));
1260
1261 /* Turn on all VW inputs' MIWU interrupts */
1262 for (int idx = 0; idx < ARRAY_SIZE(vw_in_tbl); idx++) {
1263 npcx_miwu_irq_enable(&(vw_in_tbl[idx].vw_wui));
1264 }
1265
1266 npcx_miwu_irq_enable(&config->espi_rst_wui);
1267 }
1268
npcx_espi_disable_interrupts(const struct device * dev)1269 void npcx_espi_disable_interrupts(const struct device *dev)
1270 {
1271 const struct espi_npcx_config *const config = dev->config;
1272
1273 /* Disable eSPI bus interrupt */
1274 irq_disable(DT_INST_IRQN(0));
1275
1276 /* Turn off all VW inputs' MIWU interrupts */
1277 for (int idx = 0; idx < ARRAY_SIZE(vw_in_tbl); idx++) {
1278 npcx_miwu_irq_disable(&(vw_in_tbl[idx].vw_wui));
1279 }
1280
1281 npcx_miwu_irq_disable(&config->espi_rst_wui);
1282 }
1283
1284 /* eSPI driver registration */
1285 static int espi_npcx_init(const struct device *dev);
1286
1287 static const struct espi_driver_api espi_npcx_driver_api = {
1288 .config = espi_npcx_configure,
1289 .get_channel_status = espi_npcx_channel_ready,
1290 .send_vwire = espi_npcx_send_vwire,
1291 .receive_vwire = espi_npcx_receive_vwire,
1292 .manage_callback = espi_npcx_manage_callback,
1293 .read_lpc_request = espi_npcx_read_lpc_request,
1294 .write_lpc_request = espi_npcx_write_lpc_request,
1295 #if defined(CONFIG_ESPI_OOB_CHANNEL)
1296 .send_oob = espi_npcx_send_oob,
1297 .receive_oob = espi_npcx_receive_oob,
1298 #endif
1299 #ifdef CONFIG_ESPI_FLASH_CHANNEL
1300 .flash_read = espi_npcx_flash_read,
1301 .flash_write = espi_npcx_flash_write,
1302 .flash_erase = espi_npcx_flash_erase,
1303 #endif
1304 };
1305
1306 static struct espi_npcx_data espi_npcx_data;
1307
1308 PINCTRL_DT_INST_DEFINE(0);
1309 BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
1310 "only one 'nuvoton_npcx_espi' compatible node may be present");
1311
1312 static const struct espi_npcx_config espi_npcx_config = {
1313 .base = DT_INST_REG_ADDR(0),
1314 .espi_rst_wui = NPCX_DT_WUI_ITEM_BY_NAME(0, espi_rst_wui),
1315 .clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
1316 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
1317 };
1318
1319 DEVICE_DT_INST_DEFINE(0, &espi_npcx_init, NULL,
1320 &espi_npcx_data, &espi_npcx_config,
1321 PRE_KERNEL_2, CONFIG_ESPI_INIT_PRIORITY,
1322 &espi_npcx_driver_api);
1323
espi_npcx_init(const struct device * dev)1324 static int espi_npcx_init(const struct device *dev)
1325 {
1326 const struct espi_npcx_config *const config = dev->config;
1327 struct espi_npcx_data *const data = dev->data;
1328 struct espi_reg *const inst = HAL_INSTANCE(dev);
1329 const struct device *const clk_dev = DEVICE_DT_GET(NPCX_CLK_CTRL_NODE);
1330 int i, ret;
1331
1332 /* If booter doesn't set the host interface type */
1333 if (!NPCX_BOOTER_IS_HIF_TYPE_SET()) {
1334 npcx_host_interface_sel(NPCX_HIF_TYPE_ESPI_SHI);
1335 }
1336
1337 if (!device_is_ready(clk_dev)) {
1338 LOG_ERR("clock control device not ready");
1339 return -ENODEV;
1340 }
1341
1342 /* Turn on eSPI device clock first */
1343 ret = clock_control_on(clk_dev, (clock_control_subsys_t)
1344 &config->clk_cfg);
1345 if (ret < 0) {
1346 LOG_ERR("Turn on eSPI clock fail %d", ret);
1347 return ret;
1348 }
1349
1350 if (IS_ENABLED(CONFIG_ESPI_NPCX_BYPASS_CH_ENABLE_FATAL_ERROR)) {
1351 /* Enable the access to the NPCX_ONLY_ESPI_REG2 register */
1352 inst->NPCX_ONLY_ESPI_REG1 = NPCX_ONLY_ESPI_REG1_UNLOCK_REG2;
1353 inst->NPCX_ONLY_ESPI_REG2 &= ~BIT(NPCX_ONLY_ESPI_REG2_TRANS_END_CONFIG);
1354 /* Disable the access to the NPCX_ONLY_ESPI_REG2 register */
1355 inst->NPCX_ONLY_ESPI_REG1 = NPCX_ONLY_ESPI_REG1_LOCK_REG2;
1356 }
1357
1358 /* Enable events which share the same espi bus interrupt */
1359 for (i = 0; i < ARRAY_SIZE(espi_bus_isr_tbl); i++) {
1360 inst->ESPIIE |= BIT(espi_bus_isr_tbl[i].int_en_bit);
1361 inst->ESPIWE |= BIT(espi_bus_isr_tbl[i].wake_en_bit);
1362 }
1363
1364 #if !defined(CONFIG_ESPI_OOB_CHANNEL_RX_ASYNC)
1365 k_sem_init(&data->oob_rx_lock, 0, 1);
1366 #endif
1367
1368 #if defined(CONFIG_ESPI_FLASH_CHANNEL)
1369 k_sem_init(&data->flash_rx_lock, 0, 1);
1370 #endif
1371
1372 /* Configure Virtual Wire input signals */
1373 for (i = 0; i < ARRAY_SIZE(vw_in_tbl); i++)
1374 espi_vw_config_input(dev, &vw_in_tbl[i]);
1375
1376 /* Configure Virtual Wire output signals */
1377 for (i = 0; i < ARRAY_SIZE(vw_out_tbl); i++)
1378 espi_vw_config_output(dev, &vw_out_tbl[i]);
1379
1380 /* Configure Virtual Wire GPIOs that are output high at reset state */
1381 for (i = 0; i < ARRAY_SIZE(vw_out_gpio_tbl1); i++) {
1382 espi_vw_gpio_config_output(dev, &vw_out_gpio_tbl1[i], 1);
1383 }
1384
1385 /* Configure wake-up input and callback for eSPI VW input signal */
1386 for (i = 0; i < ARRAY_SIZE(vw_in_tbl); i++)
1387 espi_init_wui_callback(dev, &vw_in_callback[i],
1388 &vw_in_tbl[i].vw_wui, espi_vw_generic_isr);
1389
1390 /* Configure wake-up input and callback for ESPI_RST signal */
1391 espi_init_wui_callback(dev, &espi_rst_callback,
1392 &config->espi_rst_wui, espi_vw_espi_rst_isr);
1393
1394 /* Configure pin-mux for eSPI bus device */
1395 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1396 if (ret < 0) {
1397 LOG_ERR("eSPI pinctrl setup failed (%d)", ret);
1398 return ret;
1399 }
1400
1401 /* Configure host sub-modules which HW blocks belong to core domain */
1402 npcx_host_init_subs_core_domain(dev, &data->callbacks);
1403
1404 #if defined(CONFIG_ESPI_FLASH_CHANNEL) && defined(CONFIG_ESPI_TAF)
1405 npcx_init_taf(dev, &data->callbacks);
1406 #endif
1407
1408 /* eSPI Bus interrupt installation */
1409 IRQ_CONNECT(DT_INST_IRQN(0),
1410 DT_INST_IRQ(0, priority),
1411 espi_bus_generic_isr,
1412 DEVICE_DT_INST_GET(0), 0);
1413
1414 /* Enable eSPI bus interrupt */
1415 irq_enable(DT_INST_IRQN(0));
1416
1417 return 0;
1418 }
1419
