1 /* 2 * Copyright (c) 2017-2019 Arm Limited 3 * Copyright (c) 2020 Nordic Semiconductor ASA 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 18 #ifndef __TARGET_CFG_H__ 19 #define __TARGET_CFG_H__ 20 21 /** 22 * \file target_cfg.h 23 * \brief Target configuration header 24 * 25 * This file contains the platform specific functions to configure 26 * the Cortex-M33 core, memory permissions and security attribution. 27 * on the nordic_nrf platform. 28 * 29 * Memory permissions and security attribution are configured via 30 * the System Protection Unit (SPU) which is the nRF specific Implementation 31 * Defined Attribution Unit (IDAU). 32 */ 33 34 35 #include "tfm_plat_defs.h" 36 #include "region_defs.h" 37 38 // TODO: NCSDK-25009: Support configuring which UART is used by TF-M on nrf54L 39 40 #ifndef NRF_SECURE_UART_INSTANCE 41 #define TFM_DRIVER_STDIO Driver_USART1 42 #elif NRF_SECURE_UART_INSTANCE == 0 43 #define TFM_DRIVER_STDIO Driver_USART0 44 #elif NRF_SECURE_UART_INSTANCE == 1 45 #define TFM_DRIVER_STDIO Driver_USART1 46 #elif NRF_SECURE_UART_INSTANCE == 22 47 #define TFM_DRIVER_STDIO Driver_USART22 48 #endif 49 50 #ifdef NRF54L15_ENGA_XXAA 51 #define NS_DRIVER_STDIO Driver_USART20 52 #else 53 #define NS_DRIVER_STDIO Driver_USART0 54 #endif 55 56 /** 57 * \brief Store the addresses of memory regions 58 */ 59 struct memory_region_limits { 60 uint32_t non_secure_code_start; 61 uint32_t non_secure_partition_base; 62 uint32_t non_secure_partition_limit; 63 uint32_t veneer_base; 64 uint32_t veneer_limit; 65 #ifdef NRF_NS_SECONDARY 66 uint32_t secondary_partition_base; 67 uint32_t secondary_partition_limit; 68 #endif /* NRF_NS_SECONDARY */ 69 #ifdef NRF_NS_STORAGE_PARTITION_START 70 uint32_t non_secure_storage_partition_base; 71 uint32_t non_secure_storage_partition_limit; 72 #endif /* NRF_NS_STORAGE_PARTITION_START */ 73 }; 74 75 /** 76 * \brief Holds the data necessary to do isolation for a specific peripheral. 77 */ 78 struct platform_data_t 79 { 80 uint32_t periph_start; 81 uint32_t periph_limit; 82 }; 83 84 /** 85 * \brief Configures memory permissions via the System Protection Unit. 86 * 87 * \return Returns values as specified by the \ref tfm_plat_err_t 88 */ 89 enum tfm_plat_err_t spu_init_cfg(void); 90 91 /** 92 * \brief Configures peripheral permissions via the System Protection Unit. 93 * 94 * The function does the following: 95 * - grants Non-Secure access to nRF peripherals that are not Secure-only 96 * - grants Non-Secure access to DDPI channels 97 * - grants Non-Secure access to GPIO pins 98 * - On nrf5340 enforces that the external domain is still at the HW reset value 99 * of non-secure and locking it 100 * 101 * \return Returns values as specified by the \ref tfm_plat_err_t 102 */ 103 enum tfm_plat_err_t spu_periph_init_cfg(void); 104 105 /** 106 * \brief Clears SPU interrupt. 107 */ 108 void spu_clear_irq(void); 109 110 /** 111 * \brief Configures memory permissions via the MPC. 112 * 113 * \return Returns values as specified by the \ref tfm_plat_err_t 114 */ 115 enum tfm_plat_err_t nrf_mpc_init_cfg(void); 116 117 /** 118 * \brief Configures SAU and IDAU. 119 */ 120 void sau_and_idau_cfg(void); 121 122 /** 123 * \brief Enables the fault handlers and sets priorities. 124 * 125 * \return Returns values as specified by the \ref tfm_plat_err_t 126 */ 127 enum tfm_plat_err_t enable_fault_handlers(void); 128 129 /** 130 * \brief Configures the system reset request properties 131 * 132 * \return Returns values as specified by the \ref tfm_plat_err_t 133 */ 134 enum tfm_plat_err_t system_reset_cfg(void); 135 136 /** 137 * \brief Configures the system debug properties. 138 * 139 * \return Returns values as specified by the \ref tfm_plat_err_t 140 */ 141 enum tfm_plat_err_t init_debug(void); 142 143 /** 144 * \brief Configures all external interrupts to target the 145 * NS state, apart for the ones associated to secure 146 * peripherals (plus SPU) 147 * 148 * \return Returns values as specified by the \ref tfm_plat_err_t 149 */ 150 enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void); 151 152 /** 153 * \brief This function enable the interrupts associated 154 * to the secure peripherals (plus the isolation boundary violation 155 * interrupts) 156 * 157 * \return Returns values as specified by the \ref tfm_plat_err_t 158 */ 159 enum tfm_plat_err_t nvic_interrupt_enable(void); 160 161 #endif /* __TARGET_CFG_H__ */ 162
