1 /*
2 * Copyright (c) 2016 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /**
8 * @file
9 * @brief Nios II specific kernel interface header
10 * This header contains the Nios II specific kernel interface. It is
11 * included by the generic kernel interface header (include/arch/cpu.h)
12 */
13
14 #ifndef ZEPHYR_INCLUDE_ARCH_NIOS2_ARCH_H_
15 #define ZEPHYR_INCLUDE_ARCH_NIOS2_ARCH_H_
16
17 #include <system.h>
18
19 #include <zephyr/arch/nios2/thread.h>
20 #include <zephyr/arch/nios2/exception.h>
21 #include <zephyr/arch/nios2/asm_inline.h>
22 #include <zephyr/arch/common/addr_types.h>
23 #include <zephyr/devicetree.h>
24 #include <zephyr/arch/nios2/nios2.h>
25 #include <zephyr/arch/common/sys_bitops.h>
26 #include <zephyr/sys/sys_io.h>
27 #include <zephyr/arch/common/ffs.h>
28
29 #define ARCH_STACK_PTR_ALIGN 4
30
31 #ifndef _ASMLANGUAGE
32 #include <zephyr/types.h>
33 #include <zephyr/irq.h>
34 #include <zephyr/sw_isr_table.h>
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 /* There is no notion of priority with the Nios II internal interrupt
41 * controller and no flags are currently supported.
42 */
43 #define ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
44 { \
45 Z_ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
46 }
47
arch_irq_lock(void)48 static ALWAYS_INLINE unsigned int arch_irq_lock(void)
49 {
50 unsigned int key, tmp;
51
52 __asm__ volatile (
53 "rdctl %[key], status\n\t"
54 "movi %[tmp], -2\n\t"
55 "and %[tmp], %[key], %[tmp]\n\t"
56 "wrctl status, %[tmp]\n\t"
57 : [key] "=r" (key), [tmp] "=r" (tmp)
58 : : "memory");
59
60 return key;
61 }
62
arch_irq_unlock(unsigned int key)63 static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
64 {
65 /* If the CPU is built without certain features, then
66 * the only writable bit in the status register is PIE
67 * in which case we can just write the value stored in key,
68 * all the other writable bits will be the same.
69 *
70 * If not, other stuff could have changed and we need to
71 * specifically flip just that bit.
72 */
73
74 #if (ALT_CPU_NUM_OF_SHADOW_REG_SETS > 0) || \
75 (defined ALT_CPU_EIC_PRESENT) || \
76 (defined ALT_CPU_MMU_PRESENT) || \
77 (defined ALT_CPU_MPU_PRESENT)
78 __asm__ volatile (
79 "andi %[key], %[key], 1\n\t"
80 "beq %[key], zero, 1f\n\t"
81 "rdctl %[key], status\n\t"
82 "ori %[key], %[key], 1\n\t"
83 "wrctl status, %[key]\n\t"
84 "1:\n\t"
85 : [key] "+r" (key)
86 : : "memory");
87 #else
88 __asm__ volatile (
89 "wrctl status, %[key]"
90 : : [key] "r" (key)
91 : "memory");
92 #endif
93 }
94
arch_irq_unlocked(unsigned int key)95 static ALWAYS_INLINE bool arch_irq_unlocked(unsigned int key)
96 {
97 return key & 1;
98 }
99
100 void arch_irq_enable(unsigned int irq);
101 void arch_irq_disable(unsigned int irq);
102
103 FUNC_NORETURN void z_SysFatalErrorHandler(unsigned int reason,
104 const struct arch_esf *esf);
105
106 FUNC_NORETURN void z_NanoFatalErrorHandler(unsigned int reason,
107 const struct arch_esf *esf);
108
109 enum nios2_exception_cause {
110 NIOS2_EXCEPTION_UNKNOWN = -1,
111 NIOS2_EXCEPTION_RESET = 0,
112 NIOS2_EXCEPTION_CPU_ONLY_RESET_REQUEST = 1,
113 NIOS2_EXCEPTION_INTERRUPT = 2,
114 NIOS2_EXCEPTION_TRAP_INST = 3,
115 NIOS2_EXCEPTION_UNIMPLEMENTED_INST = 4,
116 NIOS2_EXCEPTION_ILLEGAL_INST = 5,
117 NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR = 6,
118 NIOS2_EXCEPTION_MISALIGNED_TARGET_PC = 7,
119 NIOS2_EXCEPTION_DIVISION_ERROR = 8,
120 NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST_ADDR = 9,
121 NIOS2_EXCEPTION_SUPERVISOR_ONLY_INST = 10,
122 NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR = 11,
123 NIOS2_EXCEPTION_TLB_MISS = 12,
124 NIOS2_EXCEPTION_TLB_EXECUTE_PERM_VIOLATION = 13,
125 NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION = 14,
126 NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION = 15,
127 NIOS2_EXCEPTION_MPU_INST_REGION_VIOLATION = 16,
128 NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION = 17,
129 NIOS2_EXCEPTION_ECC_TLB_ERR = 18,
130 NIOS2_EXCEPTION_ECC_FETCH_ERR = 19,
131 NIOS2_EXCEPTION_ECC_REGISTER_FILE_ERR = 20,
132 NIOS2_EXCEPTION_ECC_DATA_ERR = 21,
133 NIOS2_EXCEPTION_ECC_DATA_CACHE_WRITEBACK_ERR = 22
134 };
135
136 /* Bitfield indicating which exception cause codes report a valid
137 * badaddr register. NIOS2_EXCEPTION_TLB_MISS and NIOS2_EXCEPTION_ECC_TLB_ERR
138 * are deliberately not included here, you need to check if TLBMISC.D=1
139 */
140 #define NIOS2_BADADDR_CAUSE_MASK \
141 (BIT(NIOS2_EXCEPTION_SUPERVISOR_ONLY_DATA_ADDR) | \
142 BIT(NIOS2_EXCEPTION_MISALIGNED_DATA_ADDR) | \
143 BIT(NIOS2_EXCEPTION_MISALIGNED_TARGET_PC) | \
144 BIT(NIOS2_EXCEPTION_TLB_READ_PERM_VIOLATION) | \
145 BIT(NIOS2_EXCEPTION_TLB_WRITE_PERM_VIOLATION) | \
146 BIT(NIOS2_EXCEPTION_MPU_DATA_REGION_VIOLATION) | \
147 BIT(NIOS2_EXCEPTION_ECC_DATA_ERR))
148
149
150 extern uint32_t sys_clock_cycle_get_32(void);
151
arch_k_cycle_get_32(void)152 static inline uint32_t arch_k_cycle_get_32(void)
153 {
154 return sys_clock_cycle_get_32();
155 }
156
157 extern uint64_t sys_clock_cycle_get_64(void);
158
arch_k_cycle_get_64(void)159 static inline uint64_t arch_k_cycle_get_64(void)
160 {
161 return sys_clock_cycle_get_64();
162 }
163
arch_nop(void)164 static ALWAYS_INLINE void arch_nop(void)
165 {
166 __asm__ volatile("nop");
167 }
168
169 #ifdef __cplusplus
170 }
171 #endif
172
173 #endif /* _ASMLANGUAGE */
174
175 #endif /* ZEPHYR_INCLUDE_ARCH_NIOS2_ARCH_H_ */
176
