1 /** 2 * @file srcc_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SRCC_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _SRCC_REVA_REGS_H_ 27 #define _SRCC_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup srcc_reva 65 * @defgroup srcc_reva_registers SRCC_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the SRCC_REVA Peripheral Module. 67 * @details SPIX Cache Controller Registers. 68 */ 69 70 /** 71 * @ingroup srcc_reva_registers 72 * Structure type to access the SRCC_REVA Registers. 73 */ 74 typedef struct { 75 __I uint32_t cache_id; /**< <tt>\b 0x0000:</tt> SRCC_REVA CACHE_ID Register */ 76 __I uint32_t memcfg; /**< <tt>\b 0x0004:</tt> SRCC_REVA MEMCFG Register */ 77 __R uint32_t rsv_0x8_0xff[62]; 78 __IO uint32_t cache_ctrl; /**< <tt>\b 0x0100:</tt> SRCC_REVA CACHE_CTRL Register */ 79 __R uint32_t rsv_0x104_0x6ff[383]; 80 __IO uint32_t invalidate; /**< <tt>\b 0x0700:</tt> SRCC_REVA INVALIDATE Register */ 81 } mxc_srcc_reva_regs_t; 82 83 /* Register offsets for module SRCC_REVA */ 84 /** 85 * @ingroup srcc_reva_registers 86 * @defgroup SRCC_REVA_Register_Offsets Register Offsets 87 * @brief SRCC_REVA Peripheral Register Offsets from the SRCC_REVA Base Peripheral Address. 88 * @{ 89 */ 90 #define MXC_R_SRCC_REVA_CACHE_ID ((uint32_t)0x00000000UL) /**< Offset from SRCC_REVA Base Address: <tt> 0x0000</tt> */ 91 #define MXC_R_SRCC_REVA_MEMCFG ((uint32_t)0x00000004UL) /**< Offset from SRCC_REVA Base Address: <tt> 0x0004</tt> */ 92 #define MXC_R_SRCC_REVA_CACHE_CTRL ((uint32_t)0x00000100UL) /**< Offset from SRCC_REVA Base Address: <tt> 0x0100</tt> */ 93 #define MXC_R_SRCC_REVA_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from SRCC_REVA Base Address: <tt> 0x0700</tt> */ 94 /**@} end of group srcc_reva_registers */ 95 96 /** 97 * @ingroup srcc_reva_registers 98 * @defgroup SRCC_REVA_CACHE_ID SRCC_REVA_CACHE_ID 99 * @brief Cache ID Register. 100 * @{ 101 */ 102 #define MXC_F_SRCC_REVA_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */ 103 #define MXC_F_SRCC_REVA_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_SRCC_REVA_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */ 104 105 #define MXC_F_SRCC_REVA_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */ 106 #define MXC_F_SRCC_REVA_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_SRCC_REVA_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */ 107 108 #define MXC_F_SRCC_REVA_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */ 109 #define MXC_F_SRCC_REVA_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_SRCC_REVA_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */ 110 111 /**@} end of group SRCC_REVA_CACHE_ID_Register */ 112 113 /** 114 * @ingroup srcc_reva_registers 115 * @defgroup SRCC_REVA_MEMCFG SRCC_REVA_MEMCFG 116 * @brief Memory Configuration Register. 117 * @{ 118 */ 119 #define MXC_F_SRCC_REVA_MEMCFG_CCHSZ_POS 0 /**< MEMCFG_CCHSZ Position */ 120 #define MXC_F_SRCC_REVA_MEMCFG_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_SRCC_REVA_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */ 121 122 #define MXC_F_SRCC_REVA_MEMCFG_MEMSZ_POS 16 /**< MEMCFG_MEMSZ Position */ 123 #define MXC_F_SRCC_REVA_MEMCFG_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_SRCC_REVA_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */ 124 125 /**@} end of group SRCC_REVA_MEMCFG_Register */ 126 127 /** 128 * @ingroup srcc_reva_registers 129 * @defgroup SRCC_REVA_CACHE_CTRL SRCC_REVA_CACHE_CTRL 130 * @brief Cache Control and Status Register. 131 * @{ 132 */ 133 #define MXC_F_SRCC_REVA_CACHE_CTRL_CACHE_EN_POS 0 /**< CACHE_CTRL_CACHE_EN Position */ 134 #define MXC_F_SRCC_REVA_CACHE_CTRL_CACHE_EN ((uint32_t)(0x1UL << MXC_F_SRCC_REVA_CACHE_CTRL_CACHE_EN_POS)) /**< CACHE_CTRL_CACHE_EN Mask */ 135 136 #define MXC_F_SRCC_REVA_CACHE_CTRL_WRITE_ALLOC_EN_POS 1 /**< CACHE_CTRL_WRITE_ALLOC_EN Position */ 137 #define MXC_F_SRCC_REVA_CACHE_CTRL_WRITE_ALLOC_EN ((uint32_t)(0x1UL << MXC_F_SRCC_REVA_CACHE_CTRL_WRITE_ALLOC_EN_POS)) /**< CACHE_CTRL_WRITE_ALLOC_EN Mask */ 138 139 #define MXC_F_SRCC_REVA_CACHE_CTRL_CWFST_DIS_POS 2 /**< CACHE_CTRL_CWFST_DIS Position */ 140 #define MXC_F_SRCC_REVA_CACHE_CTRL_CWFST_DIS ((uint32_t)(0x1UL << MXC_F_SRCC_REVA_CACHE_CTRL_CWFST_DIS_POS)) /**< CACHE_CTRL_CWFST_DIS Mask */ 141 142 #define MXC_F_SRCC_REVA_CACHE_CTRL_CACHE_RDY_POS 16 /**< CACHE_CTRL_CACHE_RDY Position */ 143 #define MXC_F_SRCC_REVA_CACHE_CTRL_CACHE_RDY ((uint32_t)(0x1UL << MXC_F_SRCC_REVA_CACHE_CTRL_CACHE_RDY_POS)) /**< CACHE_CTRL_CACHE_RDY Mask */ 144 145 /**@} end of group SRCC_REVA_CACHE_CTRL_Register */ 146 147 /** 148 * @ingroup srcc_reva_registers 149 * @defgroup SRCC_REVA_INVALIDATE SRCC_REVA_INVALIDATE 150 * @brief Invalidate All Cache Contents. Any time this register location is written 151 * (regardless of the data value), the cache controller immediately begins 152 * invalidating the entire contents of the cache memory. The cache will be in 153 * bypass mode until the invalidate operation is complete. System software can 154 * examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the 155 * invalidate operation is complete. Note that it is not necessary to disable the 156 * cache controller prior to beginning this operation. Reads from this register 157 * always return 0. 158 * @{ 159 */ 160 #define MXC_F_SRCC_REVA_INVALIDATE_IA_POS 0 /**< INVALIDATE_IA Position */ 161 #define MXC_F_SRCC_REVA_INVALIDATE_IA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SRCC_REVA_INVALIDATE_IA_POS)) /**< INVALIDATE_IA Mask */ 162 163 /**@} end of group SRCC_REVA_INVALIDATE_Register */ 164 165 #ifdef __cplusplus 166 } 167 #endif 168 169 #endif /* _SRCC_REVA_REGS_H_ */ 170
