1 /** 2 * @file spixfc_fifo_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIXFC_FIFO_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _SPIXFC_FIFO_REVA_REGS_H_ 27 #define _SPIXFC_FIFO_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup spixfc_fifo_reva 65 * @defgroup spixfc_fifo_reva_registers SPIXFC_FIFO_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the SPIXFC_FIFO_REVA Peripheral Module. 67 * @details SPI XiP Master Controller FIFO. 68 */ 69 70 /** 71 * @ingroup spixfc_fifo_reva_registers 72 * Structure type to access the SPIXFC_FIFO_REVA Registers. 73 */ 74 typedef struct { 75 union{ 76 __IO uint8_t tx_8; /**< <tt>\b 0x00:</tt> SPIXFC_FIFO_REVA TX_8 Register */ 77 __IO uint16_t tx_16; /**< <tt>\b 0x00:</tt> SPIXFC_FIFO_REVA TX_16 Register */ 78 __IO uint32_t tx_32; /**< <tt>\b 0x00:</tt> SPIXFC_FIFO_REVA TX_32 Register */ 79 }; 80 union{ 81 __IO uint8_t rx_8; /**< <tt>\b 0x04:</tt> SPIXFC_FIFO_REVA RX_8 Register */ 82 __IO uint16_t rx_16; /**< <tt>\b 0x04:</tt> SPIXFC_FIFO_REVA RX_16 Register */ 83 __IO uint32_t rx_32; /**< <tt>\b 0x04:</tt> SPIXFC_FIFO_REVA RX_32 Register */ 84 }; 85 } mxc_spixfc_fifo_reva_regs_t; 86 87 /* Register offsets for module SPIXFC_FIFO_REVA */ 88 /** 89 * @ingroup spixfc_fifo_reva_registers 90 * @defgroup SPIXFC_FIFO_REVA_Register_Offsets Register Offsets 91 * @brief SPIXFC_FIFO_REVA Peripheral Register Offsets from the SPIXFC_FIFO_REVA Base Peripheral Address. 92 * @{ 93 */ 94 #define MXC_R_SPIXFC_FIFO_REVA_TX_8 ((uint32_t)0x00000000UL) /**< Offset from SPIXFC_FIFO_REVA Base Address: <tt> 0x0000</tt> */ 95 #define MXC_R_SPIXFC_FIFO_REVA_TX_16 ((uint32_t)0x00000000UL) /**< Offset from SPIXFC_FIFO_REVA Base Address: <tt> 0x0000</tt> */ 96 #define MXC_R_SPIXFC_FIFO_REVA_TX_32 ((uint32_t)0x00000000UL) /**< Offset from SPIXFC_FIFO_REVA Base Address: <tt> 0x0000</tt> */ 97 #define MXC_R_SPIXFC_FIFO_REVA_RX_8 ((uint32_t)0x00000004UL) /**< Offset from SPIXFC_FIFO_REVA Base Address: <tt> 0x0004</tt> */ 98 #define MXC_R_SPIXFC_FIFO_REVA_RX_16 ((uint32_t)0x00000004UL) /**< Offset from SPIXFC_FIFO_REVA Base Address: <tt> 0x0004</tt> */ 99 #define MXC_R_SPIXFC_FIFO_REVA_RX_32 ((uint32_t)0x00000004UL) /**< Offset from SPIXFC_FIFO_REVA Base Address: <tt> 0x0004</tt> */ 100 /**@} end of group spixfc_fifo_reva_registers */ 101 102 #ifdef __cplusplus 103 } 104 #endif 105 106 #endif /* _SPIXFC_FIFO_REVA_REGS_H_ */ 107
