1 /** 2 * @file adc_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the ADC_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _ADC_REVA_REGS_H_ 27 #define _ADC_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup adc_reva 65 * @defgroup adc_reva_registers ADC_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the ADC_REVA Peripheral Module. 67 * @details 10-bit Analog to Digital Converter 68 */ 69 70 /** 71 * @ingroup adc_reva_registers 72 * Structure type to access the ADC_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> ADC_REVA CTRL Register */ 76 __IO uint32_t status; /**< <tt>\b 0x0004:</tt> ADC_REVA STATUS Register */ 77 __IO uint32_t data; /**< <tt>\b 0x0008:</tt> ADC_REVA DATA Register */ 78 __IO uint32_t intr; /**< <tt>\b 0x000C:</tt> ADC_REVA INTR Register */ 79 __IO uint32_t limit[4]; /**< <tt>\b 0x0010:</tt> ADC_REVA LIMIT Register */ 80 } mxc_adc_reva_regs_t; 81 82 /* Register offsets for module ADC_REVA */ 83 /** 84 * @ingroup adc_reva_registers 85 * @defgroup ADC_REVA_Register_Offsets Register Offsets 86 * @brief ADC_REVA Peripheral Register Offsets from the ADC_REVA Base Peripheral Address. 87 * @{ 88 */ 89 #define MXC_R_ADC_REVA_CTRL ((uint32_t)0x00000000UL) /**< Offset from ADC_REVA Base Address: <tt> 0x0000</tt> */ 90 #define MXC_R_ADC_REVA_STATUS ((uint32_t)0x00000004UL) /**< Offset from ADC_REVA Base Address: <tt> 0x0004</tt> */ 91 #define MXC_R_ADC_REVA_DATA ((uint32_t)0x00000008UL) /**< Offset from ADC_REVA Base Address: <tt> 0x0008</tt> */ 92 #define MXC_R_ADC_REVA_INTR ((uint32_t)0x0000000CUL) /**< Offset from ADC_REVA Base Address: <tt> 0x000C</tt> */ 93 #define MXC_R_ADC_REVA_LIMIT ((uint32_t)0x00000010UL) /**< Offset from ADC_REVA Base Address: <tt> 0x0010</tt> */ 94 /**@} end of group adc_reva_registers */ 95 96 /** 97 * @ingroup adc_reva_registers 98 * @defgroup ADC_REVA_CTRL ADC_REVA_CTRL 99 * @brief ADC Control 100 * @{ 101 */ 102 #define MXC_F_ADC_REVA_CTRL_START_POS 0 /**< CTRL_START Position */ 103 #define MXC_F_ADC_REVA_CTRL_START ((uint32_t)(0x1UL << MXC_F_ADC_REVA_CTRL_START_POS)) /**< CTRL_START Mask */ 104 105 #define MXC_F_ADC_REVA_CTRL_PWR_POS 1 /**< CTRL_PWR Position */ 106 #define MXC_F_ADC_REVA_CTRL_PWR ((uint32_t)(0x1UL << MXC_F_ADC_REVA_CTRL_PWR_POS)) /**< CTRL_PWR Mask */ 107 108 #define MXC_F_ADC_REVA_CTRL_REFBUF_PWR_POS 3 /**< CTRL_REFBUF_PWR Position */ 109 #define MXC_F_ADC_REVA_CTRL_REFBUF_PWR ((uint32_t)(0x1UL << MXC_F_ADC_REVA_CTRL_REFBUF_PWR_POS)) /**< CTRL_REFBUF_PWR Mask */ 110 111 #define MXC_F_ADC_REVA_CTRL_REF_SEL_POS 4 /**< CTRL_REF_SEL Position */ 112 #define MXC_F_ADC_REVA_CTRL_REF_SEL ((uint32_t)(0x1UL << MXC_F_ADC_REVA_CTRL_REF_SEL_POS)) /**< CTRL_REF_SEL Mask */ 113 114 #define MXC_F_ADC_REVA_CTRL_REF_SCALE_POS 8 /**< CTRL_REF_SCALE Position */ 115 #define MXC_F_ADC_REVA_CTRL_REF_SCALE ((uint32_t)(0x1UL << MXC_F_ADC_REVA_CTRL_REF_SCALE_POS)) /**< CTRL_REF_SCALE Mask */ 116 117 #define MXC_F_ADC_REVA_CTRL_SCALE_POS 9 /**< CTRL_SCALE Position */ 118 #define MXC_F_ADC_REVA_CTRL_SCALE ((uint32_t)(0x1UL << MXC_F_ADC_REVA_CTRL_SCALE_POS)) /**< CTRL_SCALE Mask */ 119 120 #define MXC_F_ADC_REVA_CTRL_CLK_EN_POS 11 /**< CTRL_CLK_EN Position */ 121 #define MXC_F_ADC_REVA_CTRL_CLK_EN ((uint32_t)(0x1UL << MXC_F_ADC_REVA_CTRL_CLK_EN_POS)) /**< CTRL_CLK_EN Mask */ 122 123 #define MXC_F_ADC_REVA_CTRL_CH_SEL_POS 12 /**< CTRL_CH_SEL Position */ 124 #define MXC_F_ADC_REVA_CTRL_CH_SEL ((uint32_t)(0x1FUL << MXC_F_ADC_REVA_CTRL_CH_SEL_POS)) /**< CTRL_CH_SEL Mask */ 125 #define MXC_V_ADC_REVA_CTRL_CH_SEL_AIN0 ((uint32_t)0x0UL) /**< CTRL_CH_SEL_AIN0 Value */ 126 #define MXC_S_ADC_REVA_CTRL_CH_SEL_AIN0 (MXC_V_ADC_REVA_CTRL_CH_SEL_AIN0 << MXC_F_ADC_REVA_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN0 Setting */ 127 #define MXC_V_ADC_REVA_CTRL_CH_SEL_AIN1 ((uint32_t)0x1UL) /**< CTRL_CH_SEL_AIN1 Value */ 128 #define MXC_S_ADC_REVA_CTRL_CH_SEL_AIN1 (MXC_V_ADC_REVA_CTRL_CH_SEL_AIN1 << MXC_F_ADC_REVA_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN1 Setting */ 129 #define MXC_V_ADC_REVA_CTRL_CH_SEL_AIN2 ((uint32_t)0x2UL) /**< CTRL_CH_SEL_AIN2 Value */ 130 #define MXC_S_ADC_REVA_CTRL_CH_SEL_AIN2 (MXC_V_ADC_REVA_CTRL_CH_SEL_AIN2 << MXC_F_ADC_REVA_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN2 Setting */ 131 #define MXC_V_ADC_REVA_CTRL_CH_SEL_AIN3 ((uint32_t)0x3UL) /**< CTRL_CH_SEL_AIN3 Value */ 132 #define MXC_S_ADC_REVA_CTRL_CH_SEL_AIN3 (MXC_V_ADC_REVA_CTRL_CH_SEL_AIN3 << MXC_F_ADC_REVA_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN3 Setting */ 133 #define MXC_V_ADC_REVA_CTRL_CH_SEL_AIN4 ((uint32_t)0x4UL) /**< CTRL_CH_SEL_AIN4 Value */ 134 #define MXC_S_ADC_REVA_CTRL_CH_SEL_AIN4 (MXC_V_ADC_REVA_CTRL_CH_SEL_AIN4 << MXC_F_ADC_REVA_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN4 Setting */ 135 #define MXC_V_ADC_REVA_CTRL_CH_SEL_AIN5 ((uint32_t)0x5UL) /**< CTRL_CH_SEL_AIN5 Value */ 136 #define MXC_S_ADC_REVA_CTRL_CH_SEL_AIN5 (MXC_V_ADC_REVA_CTRL_CH_SEL_AIN5 << MXC_F_ADC_REVA_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN5 Setting */ 137 #define MXC_V_ADC_REVA_CTRL_CH_SEL_AIN6 ((uint32_t)0x6UL) /**< CTRL_CH_SEL_AIN6 Value */ 138 #define MXC_S_ADC_REVA_CTRL_CH_SEL_AIN6 (MXC_V_ADC_REVA_CTRL_CH_SEL_AIN6 << MXC_F_ADC_REVA_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN6 Setting */ 139 #define MXC_V_ADC_REVA_CTRL_CH_SEL_AIN7 ((uint32_t)0x7UL) /**< CTRL_CH_SEL_AIN7 Value */ 140 #define MXC_S_ADC_REVA_CTRL_CH_SEL_AIN7 (MXC_V_ADC_REVA_CTRL_CH_SEL_AIN7 << MXC_F_ADC_REVA_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN7 Setting */ 141 #define MXC_V_ADC_REVA_CTRL_CH_SEL_VCOREA ((uint32_t)0x8UL) /**< CTRL_CH_SEL_VCOREA Value */ 142 #define MXC_S_ADC_REVA_CTRL_CH_SEL_VCOREA (MXC_V_ADC_REVA_CTRL_CH_SEL_VCOREA << MXC_F_ADC_REVA_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VCOREA Setting */ 143 #define MXC_V_ADC_REVA_CTRL_CH_SEL_VCOREB ((uint32_t)0x9UL) /**< CTRL_CH_SEL_VCOREB Value */ 144 #define MXC_S_ADC_REVA_CTRL_CH_SEL_VCOREB (MXC_V_ADC_REVA_CTRL_CH_SEL_VCOREB << MXC_F_ADC_REVA_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VCOREB Setting */ 145 #define MXC_V_ADC_REVA_CTRL_CH_SEL_VRXOUT ((uint32_t)0xAUL) /**< CTRL_CH_SEL_VRXOUT Value */ 146 #define MXC_S_ADC_REVA_CTRL_CH_SEL_VRXOUT (MXC_V_ADC_REVA_CTRL_CH_SEL_VRXOUT << MXC_F_ADC_REVA_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VRXOUT Setting */ 147 #define MXC_V_ADC_REVA_CTRL_CH_SEL_VTXOUT ((uint32_t)0xBUL) /**< CTRL_CH_SEL_VTXOUT Value */ 148 #define MXC_S_ADC_REVA_CTRL_CH_SEL_VTXOUT (MXC_V_ADC_REVA_CTRL_CH_SEL_VTXOUT << MXC_F_ADC_REVA_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VTXOUT Setting */ 149 #define MXC_V_ADC_REVA_CTRL_CH_SEL_VDDA ((uint32_t)0xCUL) /**< CTRL_CH_SEL_VDDA Value */ 150 #define MXC_S_ADC_REVA_CTRL_CH_SEL_VDDA (MXC_V_ADC_REVA_CTRL_CH_SEL_VDDA << MXC_F_ADC_REVA_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDA Setting */ 151 #define MXC_V_ADC_REVA_CTRL_CH_SEL_VDDB ((uint32_t)0xDUL) /**< CTRL_CH_SEL_VDDB Value */ 152 #define MXC_S_ADC_REVA_CTRL_CH_SEL_VDDB (MXC_V_ADC_REVA_CTRL_CH_SEL_VDDB << MXC_F_ADC_REVA_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDB Setting */ 153 #define MXC_V_ADC_REVA_CTRL_CH_SEL_VDDIO ((uint32_t)0xEUL) /**< CTRL_CH_SEL_VDDIO Value */ 154 #define MXC_S_ADC_REVA_CTRL_CH_SEL_VDDIO (MXC_V_ADC_REVA_CTRL_CH_SEL_VDDIO << MXC_F_ADC_REVA_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDIO Setting */ 155 #define MXC_V_ADC_REVA_CTRL_CH_SEL_VDDIOH ((uint32_t)0xFUL) /**< CTRL_CH_SEL_VDDIOH Value */ 156 #define MXC_S_ADC_REVA_CTRL_CH_SEL_VDDIOH (MXC_V_ADC_REVA_CTRL_CH_SEL_VDDIOH << MXC_F_ADC_REVA_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDIOH Setting */ 157 #define MXC_V_ADC_REVA_CTRL_CH_SEL_VREGI ((uint32_t)0x10UL) /**< CTRL_CH_SEL_VREGI Value */ 158 #define MXC_S_ADC_REVA_CTRL_CH_SEL_VREGI (MXC_V_ADC_REVA_CTRL_CH_SEL_VREGI << MXC_F_ADC_REVA_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VREGI Setting */ 159 160 #define MXC_F_ADC_REVA_CTRL_ADC_DIVSEL_POS 17 /**< CTRL_ADC_DIVSEL Position */ 161 #define MXC_F_ADC_REVA_CTRL_ADC_DIVSEL ((uint32_t)(0x3UL << MXC_F_ADC_REVA_CTRL_ADC_DIVSEL_POS)) /**< CTRL_ADC_DIVSEL Mask */ 162 #define MXC_V_ADC_REVA_CTRL_ADC_DIVSEL_DIV1 ((uint32_t)0x0UL) /**< CTRL_ADC_DIVSEL_DIV1 Value */ 163 #define MXC_S_ADC_REVA_CTRL_ADC_DIVSEL_DIV1 (MXC_V_ADC_REVA_CTRL_ADC_DIVSEL_DIV1 << MXC_F_ADC_REVA_CTRL_ADC_DIVSEL_POS) /**< CTRL_ADC_DIVSEL_DIV1 Setting */ 164 #define MXC_V_ADC_REVA_CTRL_ADC_DIVSEL_DIV2 ((uint32_t)0x1UL) /**< CTRL_ADC_DIVSEL_DIV2 Value */ 165 #define MXC_S_ADC_REVA_CTRL_ADC_DIVSEL_DIV2 (MXC_V_ADC_REVA_CTRL_ADC_DIVSEL_DIV2 << MXC_F_ADC_REVA_CTRL_ADC_DIVSEL_POS) /**< CTRL_ADC_DIVSEL_DIV2 Setting */ 166 #define MXC_V_ADC_REVA_CTRL_ADC_DIVSEL_DIV3 ((uint32_t)0x2UL) /**< CTRL_ADC_DIVSEL_DIV3 Value */ 167 #define MXC_S_ADC_REVA_CTRL_ADC_DIVSEL_DIV3 (MXC_V_ADC_REVA_CTRL_ADC_DIVSEL_DIV3 << MXC_F_ADC_REVA_CTRL_ADC_DIVSEL_POS) /**< CTRL_ADC_DIVSEL_DIV3 Setting */ 168 #define MXC_V_ADC_REVA_CTRL_ADC_DIVSEL_DIV4 ((uint32_t)0x3UL) /**< CTRL_ADC_DIVSEL_DIV4 Value */ 169 #define MXC_S_ADC_REVA_CTRL_ADC_DIVSEL_DIV4 (MXC_V_ADC_REVA_CTRL_ADC_DIVSEL_DIV4 << MXC_F_ADC_REVA_CTRL_ADC_DIVSEL_POS) /**< CTRL_ADC_DIVSEL_DIV4 Setting */ 170 171 #define MXC_F_ADC_REVA_CTRL_DATA_ALIGN_POS 20 /**< CTRL_DATA_ALIGN Position */ 172 #define MXC_F_ADC_REVA_CTRL_DATA_ALIGN ((uint32_t)(0x1UL << MXC_F_ADC_REVA_CTRL_DATA_ALIGN_POS)) /**< CTRL_DATA_ALIGN Mask */ 173 174 /**@} end of group ADC_REVA_CTRL_Register */ 175 176 /** 177 * @ingroup adc_reva_registers 178 * @defgroup ADC_REVA_STATUS ADC_REVA_STATUS 179 * @brief ADC Status 180 * @{ 181 */ 182 #define MXC_F_ADC_REVA_STATUS_ACTIVE_POS 0 /**< STATUS_ACTIVE Position */ 183 #define MXC_F_ADC_REVA_STATUS_ACTIVE ((uint32_t)(0x1UL << MXC_F_ADC_REVA_STATUS_ACTIVE_POS)) /**< STATUS_ACTIVE Mask */ 184 185 #define MXC_F_ADC_REVA_STATUS_AFE_PWR_UP_ACTIVE_POS 2 /**< STATUS_AFE_PWR_UP_ACTIVE Position */ 186 #define MXC_F_ADC_REVA_STATUS_AFE_PWR_UP_ACTIVE ((uint32_t)(0x1UL << MXC_F_ADC_REVA_STATUS_AFE_PWR_UP_ACTIVE_POS)) /**< STATUS_AFE_PWR_UP_ACTIVE Mask */ 187 188 #define MXC_F_ADC_REVA_STATUS_OVERFLOW_POS 3 /**< STATUS_OVERFLOW Position */ 189 #define MXC_F_ADC_REVA_STATUS_OVERFLOW ((uint32_t)(0x1UL << MXC_F_ADC_REVA_STATUS_OVERFLOW_POS)) /**< STATUS_OVERFLOW Mask */ 190 191 /**@} end of group ADC_REVA_STATUS_Register */ 192 193 /** 194 * @ingroup adc_reva_registers 195 * @defgroup ADC_REVA_DATA ADC_REVA_DATA 196 * @brief ADC Output Data 197 * @{ 198 */ 199 #define MXC_F_ADC_REVA_DATA_ADC_DATA_POS 0 /**< DATA_ADC_DATA Position */ 200 #define MXC_F_ADC_REVA_DATA_ADC_DATA ((uint32_t)(0xFFFFUL << MXC_F_ADC_REVA_DATA_ADC_DATA_POS)) /**< DATA_ADC_DATA Mask */ 201 202 /**@} end of group ADC_REVA_DATA_Register */ 203 204 /** 205 * @ingroup adc_reva_registers 206 * @defgroup ADC_REVA_INTR ADC_REVA_INTR 207 * @brief ADC Interrupt Control Register 208 * @{ 209 */ 210 #define MXC_F_ADC_REVA_INTR_DONE_IE_POS 0 /**< INTR_DONE_IE Position */ 211 #define MXC_F_ADC_REVA_INTR_DONE_IE ((uint32_t)(0x1UL << MXC_F_ADC_REVA_INTR_DONE_IE_POS)) /**< INTR_DONE_IE Mask */ 212 213 #define MXC_F_ADC_REVA_INTR_REF_READY_IE_POS 1 /**< INTR_REF_READY_IE Position */ 214 #define MXC_F_ADC_REVA_INTR_REF_READY_IE ((uint32_t)(0x1UL << MXC_F_ADC_REVA_INTR_REF_READY_IE_POS)) /**< INTR_REF_READY_IE Mask */ 215 216 #define MXC_F_ADC_REVA_INTR_HI_LIMIT_IE_POS 2 /**< INTR_HI_LIMIT_IE Position */ 217 #define MXC_F_ADC_REVA_INTR_HI_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_ADC_REVA_INTR_HI_LIMIT_IE_POS)) /**< INTR_HI_LIMIT_IE Mask */ 218 219 #define MXC_F_ADC_REVA_INTR_LO_LIMIT_IE_POS 3 /**< INTR_LO_LIMIT_IE Position */ 220 #define MXC_F_ADC_REVA_INTR_LO_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_ADC_REVA_INTR_LO_LIMIT_IE_POS)) /**< INTR_LO_LIMIT_IE Mask */ 221 222 #define MXC_F_ADC_REVA_INTR_OVERFLOW_IE_POS 4 /**< INTR_OVERFLOW_IE Position */ 223 #define MXC_F_ADC_REVA_INTR_OVERFLOW_IE ((uint32_t)(0x1UL << MXC_F_ADC_REVA_INTR_OVERFLOW_IE_POS)) /**< INTR_OVERFLOW_IE Mask */ 224 225 #define MXC_F_ADC_REVA_INTR_DONE_IF_POS 16 /**< INTR_DONE_IF Position */ 226 #define MXC_F_ADC_REVA_INTR_DONE_IF ((uint32_t)(0x1UL << MXC_F_ADC_REVA_INTR_DONE_IF_POS)) /**< INTR_DONE_IF Mask */ 227 228 #define MXC_F_ADC_REVA_INTR_REF_READY_IF_POS 17 /**< INTR_REF_READY_IF Position */ 229 #define MXC_F_ADC_REVA_INTR_REF_READY_IF ((uint32_t)(0x1UL << MXC_F_ADC_REVA_INTR_REF_READY_IF_POS)) /**< INTR_REF_READY_IF Mask */ 230 231 #define MXC_F_ADC_REVA_INTR_HI_LIMIT_IF_POS 18 /**< INTR_HI_LIMIT_IF Position */ 232 #define MXC_F_ADC_REVA_INTR_HI_LIMIT_IF ((uint32_t)(0x1UL << MXC_F_ADC_REVA_INTR_HI_LIMIT_IF_POS)) /**< INTR_HI_LIMIT_IF Mask */ 233 234 #define MXC_F_ADC_REVA_INTR_LO_LIMIT_IF_POS 19 /**< INTR_LO_LIMIT_IF Position */ 235 #define MXC_F_ADC_REVA_INTR_LO_LIMIT_IF ((uint32_t)(0x1UL << MXC_F_ADC_REVA_INTR_LO_LIMIT_IF_POS)) /**< INTR_LO_LIMIT_IF Mask */ 236 237 #define MXC_F_ADC_REVA_INTR_OVERFLOW_IF_POS 20 /**< INTR_OVERFLOW_IF Position */ 238 #define MXC_F_ADC_REVA_INTR_OVERFLOW_IF ((uint32_t)(0x1UL << MXC_F_ADC_REVA_INTR_OVERFLOW_IF_POS)) /**< INTR_OVERFLOW_IF Mask */ 239 240 #define MXC_F_ADC_REVA_INTR_PENDING_POS 22 /**< INTR_PENDING Position */ 241 #define MXC_F_ADC_REVA_INTR_PENDING ((uint32_t)(0x1UL << MXC_F_ADC_REVA_INTR_PENDING_POS)) /**< INTR_PENDING Mask */ 242 243 /**@} end of group ADC_REVA_INTR_Register */ 244 245 /** 246 * @ingroup adc_reva_registers 247 * @defgroup ADC_REVA_LIMIT ADC_REVA_LIMIT 248 * @brief ADC Limit 249 * @{ 250 */ 251 #define MXC_F_ADC_REVA_LIMIT_CH_LO_LIMIT_POS 0 /**< LIMIT_CH_LO_LIMIT Position */ 252 #define MXC_F_ADC_REVA_LIMIT_CH_LO_LIMIT ((uint32_t)(0x3FFUL << MXC_F_ADC_REVA_LIMIT_CH_LO_LIMIT_POS)) /**< LIMIT_CH_LO_LIMIT Mask */ 253 254 #define MXC_F_ADC_REVA_LIMIT_CH_HI_LIMIT_POS 12 /**< LIMIT_CH_HI_LIMIT Position */ 255 #define MXC_F_ADC_REVA_LIMIT_CH_HI_LIMIT ((uint32_t)(0x3FFUL << MXC_F_ADC_REVA_LIMIT_CH_HI_LIMIT_POS)) /**< LIMIT_CH_HI_LIMIT Mask */ 256 257 #define MXC_F_ADC_REVA_LIMIT_CH_SEL_POS 24 /**< LIMIT_CH_SEL Position */ 258 #define MXC_F_ADC_REVA_LIMIT_CH_SEL ((uint32_t)(0x1FUL << MXC_F_ADC_REVA_LIMIT_CH_SEL_POS)) /**< LIMIT_CH_SEL Mask */ 259 260 #define MXC_F_ADC_REVA_LIMIT_CH_LO_LIMIT_EN_POS 29 /**< LIMIT_CH_LO_LIMIT_EN Position */ 261 #define MXC_F_ADC_REVA_LIMIT_CH_LO_LIMIT_EN ((uint32_t)(0x1UL << MXC_F_ADC_REVA_LIMIT_CH_LO_LIMIT_EN_POS)) /**< LIMIT_CH_LO_LIMIT_EN Mask */ 262 263 #define MXC_F_ADC_REVA_LIMIT_CH_HI_LIMIT_EN_POS 30 /**< LIMIT_CH_HI_LIMIT_EN Position */ 264 #define MXC_F_ADC_REVA_LIMIT_CH_HI_LIMIT_EN ((uint32_t)(0x1UL << MXC_F_ADC_REVA_LIMIT_CH_HI_LIMIT_EN_POS)) /**< LIMIT_CH_HI_LIMIT_EN Mask */ 265 266 /**@} end of group ADC_REVA_LIMIT_Register */ 267 268 #ifdef __cplusplus 269 } 270 #endif 271 272 #endif /* _ADC_REVA_REGS_H_ */ 273
