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Searched defs:mux (Results 1 – 17 of 17) sorted by relevance

/Zephyr-Core-3.7.0/soc/nxp/rw/
Dpinctrl_defs.h25 #define IOMUX_GET_SCTIMER_OUT_CLR_ENABLE(mux) ((mux) & 0x1) argument
26 #define IOMUX_GET_SCTIMER_OUT_CLR_OFFSET(mux) (((mux) >> 1) & 0x7) argument
27 #define IOMUX_GET_SCTIMER_IN_CLR_ENABLE(mux) (((mux) >> 4) & 0x1) argument
28 #define IOMUX_GET_SCTIMER_IN_CLR_OFFSET(mux) (((mux) >> 5) & 0x7) argument
29 #define IOMUX_GET_CTIMER_CLR_ENABLE(mux) (((mux) >> 8) & 0x1ULL) argument
30 #define IOMUX_GET_CTIMER_CLR_OFFSET(mux) (((mux) >> 9) & 0xFULL) argument
31 #define IOMUX_GET_FSEL_CLR_MASK(mux) (((mux) >> 13) & 0xFFFFFFFFULL) argument
32 #define IOMUX_GET_FLEXCOMM_CLR_MASK(mux) \ argument
34 #define IOMUX_GET_FLEXCOMM_CLR_IDX(mux) \ argument
40 #define IOMUX_GET_GPIO_IDX(mux) ((mux) & 0x7F) argument
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/Zephyr-Core-3.7.0/drivers/pinctrl/
Dpinctrl_rv32m1.c24 #define PIN(mux) (((mux) & 0xFC00000) >> 22) argument
25 #define PORT(mux) (((mux) & 0xF0000000) >> 28) argument
26 #define PINCFG(mux) ((mux) & Z_PINCTRL_RV32M1_PCR_MASK) argument
38 uint16_t mux = PINCFG(pins[i]); in pinctrl_configure_pins() local
Dpinctrl_kinetis.c33 #define PIN(mux) (((mux) & 0xFC00000) >> 22) argument
34 #define PORT(mux) (((mux) & 0xF0000000) >> 28) argument
35 #define PINCFG(mux) ((mux) & Z_PINCTRL_KINETIS_PCR_MASK) argument
48 uint16_t mux = PINCFG(pins[i]); in pinctrl_configure_pins() local
Dpinctrl_lpc_iocon.c14 #define OFFSET(mux) (((mux) & 0xFFF00000) >> 20) argument
15 #define TYPE(mux) (((mux) & 0xC0000) >> 18) argument
Dpinctrl_stm32.c226 uint32_t pin, mux; in pinctrl_configure_pins() local
/Zephyr-Core-3.7.0/include/zephyr/dt-bindings/pinctrl/
Drv32m1-pinctrl.h17 #define RV32M1_MUX(port, pin, mux) \ argument
Dti-cc32xx-pinctrl.h44 #define TI_CC32XX_PINMUX(pin, mux) \ argument
Dlpc11u6x-pinctrl.h106 #define IOCON_MUX(offset, type, mux) \ argument
/Zephyr-Core-3.7.0/boards/digilent/arty_a7/
Dboard.c22 struct gpio_dt_spec mux = GPIO_DT_SPEC_GET(DAPLINK_QSPI_MUX_NODE, mux_gpios); in board_daplink_qspi_mux_select() local
/Zephyr-Core-3.7.0/soc/nxp/imx/imx8/adsp/
Dpinctrl_soc.h19 uint32_t mux; member
/Zephyr-Core-3.7.0/soc/nxp/imx/imx8x/adsp/
Dpinctrl_soc.h19 uint32_t mux; member
/Zephyr-Core-3.7.0/tests/kernel/device/src/
Dmain.c102 const struct device *mux; in ZTEST_USER() local
120 const struct device *mux; in ZTEST_USER() local
141 const struct device *mux; in ZTEST_USER() local
/Zephyr-Core-3.7.0/drivers/clock_control/
Dclock_control_mcux_ccm_rev2.c149 uint32_t mux = CLOCK_GetRootClockMux(clock_root); in mcux_ccm_get_subsys_rate() local
Dclock_control_mcux_ccm.c308 uint32_t mux = CLOCK_GetRootMux(kCLOCK_RootGpt1); in mcux_ccm_get_subsys_rate() local
/Zephyr-Core-3.7.0/soc/nxp/imxrt/imxrt10xx/
Dlpm_rt1064.c55 static void clock_set_mux(clock_mux_t mux, uint32_t value) in clock_set_mux()
/Zephyr-Core-3.7.0/drivers/adc/
Dadc_ads1x1x.c599 #define ADS1X1X_INIT(t, n, odr_delay_us, res, mux, pgab) \ argument
Dadc_max1125x.c779 #define MAX1125X_INIT(t, n, odr_delay_us, res, mux, pgab) \ argument