1 /*
2 * Copyright (c) 2018-2019 Arm Limited. All rights reserved.
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include "musca_b1_scc_drv.h"
18
19 /* The first pin of the upper pins (out of 64) */
20 #define GPIO_UPPER_PINS_MIN_VALUE 32U
21
22 struct musca_b1_scc_reg_map_t {
23 volatile uint32_t clk_ctrl_sel; /* 0x00 RW Clock Control Select */
24 volatile uint32_t clk_pll_prediv_ctrl; /* 0x04 RW clk_pll_prediv_ctrl */
25 volatile uint32_t reserved1; /* 0x08 Reserved */
26 volatile uint32_t clk_postdiv_ctrl_flash; /* 0x0C RW clk_postdiv_ctrl_flash */
27 volatile uint32_t clk_postdiv_qspi; /* 0x10 RW clk_postdiv_qspi */
28 volatile uint32_t clk_postdiv_rtc; /* 0x14 RW clk_postdiv_rtc */
29 volatile uint32_t clk_postdiv_sd; /* 0x18 RW clk_postdiv_sd */
30 volatile uint32_t clk_postdiv_test; /* 0x1C RW clk_postdiv_test */
31 volatile uint32_t ctrl_bypass_div; /* 0x20 RW ctrl_bypass_div */
32 volatile uint32_t pll_ctrl_pll0_clk; /* 0x24 RW pll_ctrl_pll0_clk */
33 volatile uint32_t pll_postdiv_ctrl_pll0_clk; /* 0x28 RW pll_postdiv_ctrl_pll0_clk */
34 volatile uint32_t pll_ctrl_mult_pll0_clk; /* 0x2C RW pll_ctrl_mult_pll0_clk */
35 volatile uint32_t clk_ctrl_enable; /* 0x30 RW Clock Control Enable */
36 volatile uint32_t clk_status; /* 0x34 RO Clock Status */
37 volatile uint32_t reserved2[2]; /* 0x38 Reserved */
38 volatile uint32_t reset_ctrl; /* 0x40 RW Reset Control Register */
39 volatile uint32_t reserved3; /* 0x44 Reserved */
40 volatile uint32_t dbg_ctrl; /* 0x48 RW Debug Control Register */
41 volatile uint32_t sram_ctrl; /* 0x4C RW SRAM Control Register */
42 volatile uint32_t intr_ctrl; /* 0x50 RW Interupt Control Register */
43 volatile uint32_t clk_test_ctrl; /* 0x54 RW Clock Test Control Register */
44 volatile uint32_t cpu0_vtor; /* 0x58 RW Reset vector for CPU0 */
45 volatile uint32_t reserved4; /* 0x5C RW Reset vector for KX CPU */
46 volatile uint32_t cpu1_vtor; /* 0x60 Reserved */
47 volatile uint32_t az_cpu_vtor; /* 0x64 RW AZ_CPU_VTOR Register */
48 volatile uint32_t iomux_main_insel_0; /* 0x68 RW Main function in data select */
49 volatile uint32_t iomux_main_insel_1; /* 0x6C RW Main function in data select */
50 volatile uint32_t iomux_main_outsel_0; /* 0x70 RW Main function out data select */
51 volatile uint32_t iomux_main_outsel_1; /* 0x74 RW Main function out data select */
52 volatile uint32_t iomux_main_oensel_0; /* 0x78 RW Main function out enable select */
53 volatile uint32_t iomux_main_oensel_1; /* 0x7C RW Main function out enable select */
54 volatile uint32_t iomux_main_default_in_0; /* 0x80 RW Main function default in select */
55 volatile uint32_t iomux_main_default_in_1; /* 0x84 RW Main function default in select */
56 volatile uint32_t iomux_altf1_insel_0; /* 0x88 RW Alt function 1 in data select */
57 volatile uint32_t iomux_altf1_insel_1; /* 0x8C RW Alt function 1 in data select */
58 volatile uint32_t iomux_altf1_outsel_0; /* 0x90 RW Alt function 1 out data select */
59 volatile uint32_t iomux_altf1_outsel_1; /* 0x94 RW Alt function 1 out data select */
60 volatile uint32_t iomux_altf1_oensel_0; /* 0x98 RW Alt function 1 out enable select */
61 volatile uint32_t iomux_altf1_oensel_1; /* 0x9C RW Alt function 1 out enable select */
62 volatile uint32_t iomux_altf1_default_in_0; /* 0xA0 RW Alt function 1 default in select */
63 volatile uint32_t iomux_altf1_default_in_1; /* 0xA4 RW Alt function 1 default in select */
64 volatile uint32_t iomux_altf2_insel_0; /* 0xA8 RW Alt function 2 in data select */
65 volatile uint32_t iomux_altf2_insel_1; /* 0xAC RW Alt function 2 in data select */
66 volatile uint32_t iomux_altf2_outsel_0; /* 0xB0 RW Alt function 2 out data select */
67 volatile uint32_t iomux_altf2_outsel_1; /* 0xB4 RW Alt function 2 out data select */
68 volatile uint32_t iomux_altf2_oensel_0; /* 0xB8 RW Alt function 2 out enable select */
69 volatile uint32_t iomux_altf2_oensel_1; /* 0xBC RW Alt function 2 out enable select */
70 volatile uint32_t iomux_altf2_default_in_0; /* 0xC0 RW Alt function 2 default in select */
71 volatile uint32_t iomux_altf2_default_in_1; /* 0xC4 RW Alt function 2 default in select */
72 volatile uint32_t reserved5[8]; /* 0xC8 Reserved */
73 volatile uint32_t iopad_ds0_0; /* 0xE8 RW Drive Select 0 */
74 volatile uint32_t iopad_ds0_1; /* 0xEC RW Drive Select 0 */
75 volatile uint32_t iopad_ds1_0; /* 0xF0 RW Drive Select 1 */
76 volatile uint32_t iopad_ds1_1; /* 0xF4 RW Drive Select 1 */
77 volatile uint32_t iopad_pe_0; /* 0xF8 RW Pull Enable */
78 volatile uint32_t iopad_pe_1; /* 0xFC RW Pull Enable */
79 volatile uint32_t iopad_ps_0; /* 0x100 RW Pull Select */
80 volatile uint32_t iopad_ps_1; /* 0x104 RW Pull Select */
81 volatile uint32_t iopad_sr_0; /* 0x108 RW Slew Select */
82 volatile uint32_t iopad_sr_1; /* 0x10C RW Slew Select */
83 volatile uint32_t iopad_is_0; /* 0x110 RW Input Select */
84 volatile uint32_t iopad_is_1; /* 0x114 RW Input Select */
85 volatile uint32_t pvt_ctrl; /* 0x118 RW PVT control register */
86 volatile uint32_t reserved6[5]; /* 0x11C Reserved */
87 volatile uint32_t spare0; /* 0x130 RW spare0 */
88 volatile uint32_t reserved7[2]; /* 0x134 Reserved */
89 volatile uint32_t static_conf_sig1; /* 0x13C RW static_conf_sig1 */
90 volatile uint32_t reserved8[24]; /* 0x140 Reserved */
91 volatile uint32_t flash0_din_0; /* 0x1A0 RW flash0_or 1 din_0 */
92 volatile uint32_t flash0_din_1; /* 0x1A4 RW flash0 or 1 din_1 */
93 volatile uint32_t flash0_din_2; /* 0x1A8 RW flash0_or 1 din_2 */
94 volatile uint32_t flash0_din_3; /* 0x1AC RW flash0_or 1 din_3 */
95 volatile uint32_t reserved9[4]; /* 0x1B0 Reserved */
96 volatile uint32_t flash0_dout_0; /* 0x1C0 RO flash0_dout_0 */
97 volatile uint32_t flash0_dout_1; /* 0x1C4 RO flash0_dout_1 */
98 volatile uint32_t flash0_dout_2; /* 0x1C8 RO flash0_dout_2 */
99 volatile uint32_t flash0_dout_3; /* 0x1CC RO flash0_dout_3 */
100 volatile uint32_t flash1_dout_0; /* 0x1D0 RO flash1_dout_0 */
101 volatile uint32_t flash1_dout_1; /* 0x1D4 RO flash1_dout_1 */
102 volatile uint32_t flash1_dout_2; /* 0x1D8 RO flash1_dout_2 */
103 volatile uint32_t flash1_dout_3; /* 0x1DC RO flash1_dout_2 */
104 volatile uint32_t selection_control_reg; /* 0x1E0 RW Selection Control Register */
105 volatile uint32_t az_rom_remap_mask; /* 0x1E4 RW az_rom_remap_mask */
106 volatile uint32_t az_rom_remap_offset; /* 0x1E8 RW az_rom_remap_offset */
107 volatile uint32_t az_code_remap_mask; /* 0x1EC RW az_code_remap_mask */
108 volatile uint32_t az_code_remap_offset; /* 0x1F0 RW az_code_remap_offset */
109 volatile uint32_t az_sys_remap_mask; /* 0x1F4 RW az_sys_remap_mask */
110 volatile uint32_t az_sys_remap_offset; /* 0x1F8 RW az_sys_remap_offset */
111 volatile uint32_t reserved10; /* 0x1FC RW Kalix Control */
112 volatile uint32_t az_ctrl; /* 0x200 RW Alcatraz Control */
113 volatile uint32_t reserved11; /* 0x204 Reserved */
114 volatile uint32_t sse200_otp_rd_data; /* 0x208 RO SSE200_otp_ctrl */
115 volatile uint32_t reserved12; /* 0x20C Reserved */
116 volatile uint32_t az_otp_rd_data; /* 0x210 RO az_otp_rd_data */
117 volatile uint32_t reserved13[2]; /* 0x214 Reserved */
118 volatile uint32_t spare_ctrl0; /* 0x21C RW spare_ctrl0 */
119 volatile uint32_t spare_ctrl1; /* 0x220 RW spare_ctrl1 */
120 volatile uint32_t reserved[119]; /* 0x224 Reserved */
121 volatile uint32_t chip_id; /* 0x400 RO Chip ID 0x07D00477 */
122 };
123
124 #define AZ_CONTROL_AZ_BOOT_REMAP (1UL << 0U)
125 #define AZ_CONTROL_DBGRESET_N (1UL << 7U)
126 #define AZ_CONTROL_HRESET_N (1UL << 8U)
127
128 /**
129 * \brief Clears selected alternate functions for selected pins
130 *
131 * \param[in] scc_regs SCC register map pointer \ref musca_b1_scc_reg_map_t
132 * \param[in] func_mask Bitmask of alternate functions to clear
133 * \ref gpio_altfunc_mask_t
134 * \param[in] pin_mask Pin mask for the alternate functions
135 * \param[in] upper_pins True if pin_mask represents the upper 32 pins
136 */
scc_clear_alt_func(struct musca_b1_scc_reg_map_t * scc_regs,enum gpio_altfunc_mask_t func_mask,uint32_t pin_mask,bool upper_pins)137 static void scc_clear_alt_func(struct musca_b1_scc_reg_map_t* scc_regs,
138 enum gpio_altfunc_mask_t func_mask,
139 uint32_t pin_mask, bool upper_pins)
140 {
141 /* The pin select pointers are pointing to the registers
142 * which control the lower 32 pins of the whole 64. If we need to reach
143 * the upper 32 pins, the pointers need to be incremented.
144 * Registers are 32 bites wide so offset is in 4 byte steps.
145 */
146 uint32_t reg_offset = (upper_pins ? 1U : 0U);
147
148 if (func_mask & GPIO_MAIN_FUNC_MASK) {
149 *(&scc_regs->iomux_main_insel_0 + reg_offset) &= (~pin_mask);
150 *(&scc_regs->iomux_main_outsel_0 + reg_offset) &= (~pin_mask);
151 *(&scc_regs->iomux_main_oensel_0 + reg_offset) &= (~pin_mask);
152 }
153 if (func_mask & GPIO_ALTFUNC_1_MASK) {
154 *(&scc_regs->iomux_altf1_insel_0 + reg_offset) &= (~pin_mask);
155 *(&scc_regs->iomux_altf1_outsel_0 + reg_offset) &= (~pin_mask);
156 *(&scc_regs->iomux_altf1_oensel_0 + reg_offset) &= (~pin_mask);
157 }
158 if (func_mask & GPIO_ALTFUNC_2_MASK) {
159 *(&scc_regs->iomux_altf2_insel_0 + reg_offset) &= (~pin_mask);
160 *(&scc_regs->iomux_altf2_outsel_0 + reg_offset) &= (~pin_mask);
161 *(&scc_regs->iomux_altf2_oensel_0 + reg_offset) &= (~pin_mask);
162 }
163 }
164
165 /**
166 * \brief Sets selected alternate functions for selected (max 32) pins
167 *
168 * \param[in] scc_regs SCC register map pointer \ref musca_b1_scc_reg_map_t
169 * \param[in] altfunc Alternate function to set \ref gpio_altfunc_t
170 * \param[in] pin_mask Pin mask for the alternate functions
171 * \param[in] upper_pins True if pin_mask represents the upper 32 pins
172 *
173 * \note This function doesn't check if scc dev is NULL.
174 * \note If no alternate function is selected then this API won't do anything
175 */
scc_set_alt_func(struct musca_b1_scc_reg_map_t * scc_regs,enum gpio_altfunc_t altfunc,uint32_t pin_mask,bool upper_pins)176 static void scc_set_alt_func(struct musca_b1_scc_reg_map_t* scc_regs,
177 enum gpio_altfunc_t altfunc, uint32_t pin_mask,
178 bool upper_pins)
179 {
180 enum gpio_altfunc_mask_t altfunc_to_clear = GPIO_ALTFUNC_NONE;
181 volatile uint32_t *insel = NULL;
182 volatile uint32_t *outse = NULL;
183 volatile uint32_t *oense = NULL;
184
185 switch (altfunc) {
186 case GPIO_MAIN_FUNC:
187 insel = &scc_regs->iomux_main_insel_0;
188 outse = &scc_regs->iomux_main_outsel_0;
189 oense = &scc_regs->iomux_main_oensel_0;
190 altfunc_to_clear = GPIO_MAIN_FUNC_NEG_MASK;
191 break;
192
193 case GPIO_ALTFUNC_1:
194 insel = &scc_regs->iomux_altf1_insel_0;
195 outse = &scc_regs->iomux_altf1_outsel_0;
196 oense = &scc_regs->iomux_altf1_oensel_0;
197 altfunc_to_clear = GPIO_ALTFUNC_1_NEG_MASK;
198 break;
199
200 case GPIO_ALTFUNC_2:
201 insel = &scc_regs->iomux_altf2_insel_0;
202 outse = &scc_regs->iomux_altf2_outsel_0;
203 oense = &scc_regs->iomux_altf2_oensel_0;
204 altfunc_to_clear = GPIO_ALTFUNC_2_NEG_MASK;
205 break;
206
207 case GPIO_ALTFUNC_3:
208 /* Nothing to do, clearing the other functions enables ALTFUNC 3 */
209 altfunc_to_clear = GPIO_ALTFUNC_3_NEG_MASK;
210 scc_clear_alt_func(scc_regs, altfunc_to_clear, pin_mask, upper_pins);
211 return;
212 default:
213 return;
214 }
215
216 if (upper_pins == true) {
217 /* All the pin select pointers are pointing to the registers
218 * which control the lower 32 pins of the whole 64. If we need to reach
219 * the upper 32 pins, the pointers need to be incremented.
220 */
221 insel++;
222 outse++;
223 oense++;
224 }
225
226 /* Select the wanted function's output enable bit first.
227 * This way the output won't be disabled which is desired
228 * if we switch from output to output function
229 */
230 *oense |= pin_mask;
231
232 /* Clear all alternate function registers which are not selected */
233 scc_clear_alt_func(scc_regs, altfunc_to_clear, pin_mask, upper_pins);
234
235 /* Enable input and output data line */
236 *insel |= pin_mask;
237 *outse |= pin_mask;
238 }
239
240 enum musca_b1_scc_error_t
musca_b1_scc_set_alt_func(struct musca_b1_scc_dev_t * dev,enum gpio_altfunc_t altfunc,uint64_t pin_mask)241 musca_b1_scc_set_alt_func(struct musca_b1_scc_dev_t* dev,
242 enum gpio_altfunc_t altfunc, uint64_t pin_mask)
243 {
244 struct musca_b1_scc_reg_map_t* scc_regs =
245 (struct musca_b1_scc_reg_map_t*) dev->cfg->base;
246 uint32_t pin_mask_lo = (uint32_t)pin_mask;
247 uint32_t pin_mask_hi = (uint32_t)(pin_mask >> GPIO_UPPER_PINS_MIN_VALUE);
248
249 if (altfunc >= GPIO_ALTFUNC_MAX) {
250 /* Invalid input */
251 return SCC_INVALID_ARG;
252 }
253
254 /* Set alternate functions for the lower 32 pins - if needed */
255 if (pin_mask_lo != 0U) {
256 scc_set_alt_func(scc_regs, altfunc, pin_mask_lo, false);
257 }
258
259 /* Set alternate functions for the upper 32 pins - if needed */
260 if (pin_mask_hi != 0U) {
261 scc_set_alt_func(scc_regs, altfunc, pin_mask_hi, true);
262 }
263
264 return SCC_ERR_NONE;
265 }
266
267 /**
268 * \brief Sets pinmode for the given pins
269 *
270 * \param[in] scc_regs SCC register map pointer \ref musca_b1_scc_reg_map_t
271 * \param[in] pin_mask Pin mask for the alternate functions
272 * \param[in] mode Pin mode to set \ref pinmode_select_t
273 * \param[in] upper_pins True if the pinmask is for the upper 32 pins,
274 * false otherwise
275 */
scc_set_pinmode(struct musca_b1_scc_reg_map_t * scc_regs,uint32_t pin_mask,enum pinmode_select_t mode,bool upper_pins)276 static void scc_set_pinmode(struct musca_b1_scc_reg_map_t* scc_regs,
277 uint32_t pin_mask,
278 enum pinmode_select_t mode, bool upper_pins)
279 {
280 /* The pin select pointers are pointing to the registers
281 * which control the lower 32 pins of the whole 64. If we need to reach
282 * the upper 32 pins, the pointers need to be incremented.
283 * Registers are 32 bites wide so offset is in 4 byte steps.
284 */
285 uint32_t reg_offset = (upper_pins ? 1U : 0U);
286
287 switch (mode) {
288 case PINMODE_NONE:
289 *(&scc_regs->iopad_pe_0 + reg_offset) &= (~pin_mask);
290 break;
291 case PINMODE_PULL_DOWN:
292 /* If the pull select bit is set to 0 it means pull down */
293 *(&scc_regs->iopad_ps_0 + reg_offset) &= (~pin_mask);
294 *(&scc_regs->iopad_pe_0 + reg_offset) |= pin_mask;
295 break;
296 case PINMODE_PULL_UP:
297 /* If the pull select bit is set to 1 it means pull up */
298 *(&scc_regs->iopad_ps_0 + reg_offset) |= pin_mask;
299 *(&scc_regs->iopad_pe_0 + reg_offset) |= pin_mask;
300 break;
301 default:
302 break;
303 }
304 }
305
306 enum musca_b1_scc_error_t
musca_b1_scc_set_pinmode(struct musca_b1_scc_dev_t * dev,uint64_t pin_mask,enum pinmode_select_t mode)307 musca_b1_scc_set_pinmode(struct musca_b1_scc_dev_t* dev, uint64_t pin_mask,
308 enum pinmode_select_t mode)
309 {
310 struct musca_b1_scc_reg_map_t* scc_regs =
311 (struct musca_b1_scc_reg_map_t*) dev->cfg->base;
312 uint32_t pin_mask_lo = (uint32_t)pin_mask;
313 uint32_t pin_mask_hi = (uint32_t)(pin_mask >> 32);
314
315 if (mode >= PINMODE_MAX) {
316 /* Invalid input */
317 return SCC_INVALID_ARG;
318 }
319
320 /* Set pin mode for the lower 32 pins - if needed */
321 if (pin_mask_lo != 0U) {
322 scc_set_pinmode(scc_regs, pin_mask_lo, mode, false);
323 }
324
325 /* Set pin mode for the lower 32 pins - if needed */
326 if (pin_mask_hi != 0U) {
327 scc_set_pinmode(scc_regs, pin_mask_hi, mode, true);
328 }
329
330 return SCC_ERR_NONE;
331 }
332
333 enum musca_b1_scc_error_t
musca_b1_scc_set_default_in(struct musca_b1_scc_dev_t * dev,enum gpio_altfunc_t altfunc,uint32_t pin_num,bool default_in_value)334 musca_b1_scc_set_default_in(struct musca_b1_scc_dev_t* dev,
335 enum gpio_altfunc_t altfunc,
336 uint32_t pin_num,
337 bool default_in_value)
338 {
339 struct musca_b1_scc_reg_map_t* scc_regs =
340 (struct musca_b1_scc_reg_map_t*) dev->cfg->base;
341 uint32_t iomux_value = 0U;
342 uint32_t pin_mask = 0U;
343 uint32_t default_in_mask = 0U;
344 uint32_t reg_offset = 0U;
345
346 if ((altfunc >= GPIO_ALTFUNC_MAX) || (pin_num >= GPIO_ALTFUNC_MAX_PINS)) {
347 /* Invalid input */
348 return SCC_INVALID_ARG;
349 }
350
351 /* Check if pin is the upper section */
352 if (pin_num >= GPIO_UPPER_PINS_MIN_VALUE) {
353 pin_num -= GPIO_UPPER_PINS_MIN_VALUE;
354 /* The pin select pointers are pointing to the registers
355 * which control the lower 32 pins of the whole 64. If we need
356 * to reach the upper 32 pins, the pointers need to be incremented.
357 * Registers are 32 bites wide so offset is in 4 byte steps.
358 */
359 reg_offset = 1U;
360 }
361
362 pin_mask = (1U << pin_num);
363 default_in_mask = ((default_in_value ? 1U : 0U) << pin_num);
364
365 switch (altfunc) {
366 case GPIO_MAIN_FUNC:
367 iomux_value =
368 *(&scc_regs->iomux_main_default_in_0 + reg_offset) & (~pin_mask);
369 *(&scc_regs->iomux_main_default_in_0 + reg_offset) =
370 (iomux_value | default_in_mask);
371 *(&scc_regs->iomux_main_insel_0 + reg_offset) =
372 (*(&scc_regs->iomux_main_insel_0 + reg_offset) & (~pin_mask));
373 break;
374 case GPIO_ALTFUNC_1:
375 iomux_value =
376 *(&scc_regs->iomux_altf1_default_in_0 + reg_offset) & (~pin_mask);
377 *(&scc_regs->iomux_altf1_default_in_0 + reg_offset) =
378 (iomux_value | default_in_mask);
379 *(&scc_regs->iomux_altf1_insel_0 + reg_offset) =
380 (*(&scc_regs->iomux_altf1_insel_0 + reg_offset) & (~pin_mask));
381 break;
382 case GPIO_ALTFUNC_2:
383 iomux_value =
384 *(&scc_regs->iomux_altf2_default_in_0 + reg_offset) & (~pin_mask);
385 *(&scc_regs->iomux_altf2_default_in_0 + reg_offset) =
386 (iomux_value | default_in_mask);
387 *(&scc_regs->iomux_altf2_insel_0 + reg_offset) =
388 (*(&scc_regs->iomux_altf2_insel_0 + reg_offset) & (~pin_mask));
389 break;
390 case GPIO_ALTFUNC_3:
391 /* Reserved */
392 break;
393 default:
394 /* Code should already returned error but just to be safe
395 * return here as well
396 */
397 return SCC_INVALID_ARG;
398 }
399
400 return SCC_ERR_NONE;
401 }
402
403 enum musca_b1_scc_error_t
musca_b1_scc_set_az_cpu_vtor(struct musca_b1_scc_dev_t * dev,uint8_t az_sys_remap,uint8_t az_code_remap,uint8_t az_rom_remap)404 musca_b1_scc_set_az_cpu_vtor(struct musca_b1_scc_dev_t* dev,
405 uint8_t az_sys_remap, uint8_t az_code_remap,
406 uint8_t az_rom_remap)
407 {
408 struct musca_b1_scc_reg_map_t* scc_regs =
409 (struct musca_b1_scc_reg_map_t*) dev->cfg->base;
410
411 scc_regs->az_cpu_vtor = ((az_rom_remap) |
412 (az_code_remap << 8UL) |
413 (az_sys_remap << 16UL));
414
415 return SCC_ERR_NONE;
416 }
417
418 enum musca_b1_scc_error_t
musca_b1_scc_set_az_rom_remap(struct musca_b1_scc_dev_t * dev,uint32_t offset,uint32_t mask)419 musca_b1_scc_set_az_rom_remap(struct musca_b1_scc_dev_t* dev,
420 uint32_t offset, uint32_t mask)
421 {
422 struct musca_b1_scc_reg_map_t* scc_regs =
423 (struct musca_b1_scc_reg_map_t*) dev->cfg->base;
424
425 scc_regs->az_rom_remap_offset = offset;
426 scc_regs->az_rom_remap_mask = mask;
427
428 return SCC_ERR_NONE;
429 }
430
431 enum musca_b1_scc_error_t
musca_b1_scc_set_az_code_remap(struct musca_b1_scc_dev_t * dev,uint32_t offset,uint32_t mask)432 musca_b1_scc_set_az_code_remap(struct musca_b1_scc_dev_t* dev,
433 uint32_t offset, uint32_t mask)
434 {
435 struct musca_b1_scc_reg_map_t* scc_regs =
436 (struct musca_b1_scc_reg_map_t*) dev->cfg->base;
437
438 scc_regs->az_code_remap_offset = offset;
439 scc_regs->az_code_remap_mask = mask;
440
441 return SCC_ERR_NONE;
442 }
443
444 enum musca_b1_scc_error_t
musca_b1_scc_set_az_sys_remap(struct musca_b1_scc_dev_t * dev,uint32_t offset,uint32_t mask)445 musca_b1_scc_set_az_sys_remap(struct musca_b1_scc_dev_t* dev,
446 uint32_t offset, uint32_t mask)
447 {
448 struct musca_b1_scc_reg_map_t* scc_regs =
449 (struct musca_b1_scc_reg_map_t*) dev->cfg->base;
450
451 scc_regs->az_sys_remap_offset = offset;
452 scc_regs->az_sys_remap_mask = mask;
453
454 return SCC_ERR_NONE;
455 }
456
457 enum musca_b1_scc_error_t
musca_b1_scc_enable_az_boot_remap(struct musca_b1_scc_dev_t * dev)458 musca_b1_scc_enable_az_boot_remap(struct musca_b1_scc_dev_t* dev)
459 {
460 struct musca_b1_scc_reg_map_t* scc_regs =
461 (struct musca_b1_scc_reg_map_t*) dev->cfg->base;
462
463 scc_regs->az_ctrl |= AZ_CONTROL_AZ_BOOT_REMAP;
464
465 return SCC_ERR_NONE;
466 }
467
468 enum musca_b1_scc_error_t
musca_b1_scc_disable_az_boot_remap(struct musca_b1_scc_dev_t * dev)469 musca_b1_scc_disable_az_boot_remap(struct musca_b1_scc_dev_t* dev)
470 {
471 struct musca_b1_scc_reg_map_t* scc_regs =
472 (struct musca_b1_scc_reg_map_t*) dev->cfg->base;
473
474 scc_regs->az_ctrl &= ~AZ_CONTROL_AZ_BOOT_REMAP;
475
476 return SCC_ERR_NONE;
477 }
478
479 enum musca_b1_scc_error_t
musca_b1_scc_az_release_from_reset(struct musca_b1_scc_dev_t * dev)480 musca_b1_scc_az_release_from_reset(struct musca_b1_scc_dev_t* dev)
481 {
482 struct musca_b1_scc_reg_map_t* scc_regs =
483 (struct musca_b1_scc_reg_map_t*) dev->cfg->base;
484
485 scc_regs->az_ctrl |= (AZ_CONTROL_DBGRESET_N | AZ_CONTROL_HRESET_N);
486
487 return SCC_ERR_NONE;
488 }
489
