1 /******************************************************************************
2  * Copyright 2020 Microchip Corporation.
3  *
4  * SPDX-License-Identifier: MIT
5  *
6  * This file contains type definitions used throughout the PolarFire SoC MSS
7  * Ethernet MAC and PHY device drivers. User need not include this file in
8  * application source code.
9  * Inclusion of mss_ethernet_mac.h inherits these types.
10  *
11  */
12 #ifndef MSS_ETHERNET_MAC_TYPES_H_
13 #define MSS_ETHERNET_MAC_TYPES_H_
14 #include <stdint.h>
15 
16 #if defined(MSS_MAC_PHY_HW_RESET) || defined(MSS_MAC_PHY_HW_SRESET)
17 #include "drivers/mss_gpio/mss_gpio.h"
18 #endif
19 
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23 
24 /*******************************************************************************/
25 /* Public type definitions                                                     */
26 /*******************************************************************************/
27 
28 /***************************************************************************//**
29  * MAC interface speed indicator
30  *
31  * This enumeration specifies the various interface speeds supported by the MAC
32  * hardware. These values are used by _MSS_MAC_get_link_status()_ to indicate the
33  * current link speed.
34  */
35 typedef enum __mss_mac_speed_t
36 {
37     MSS_MAC_10MBPS     = 0x00,
38     MSS_MAC_100MBPS    = 0x01,
39     MSS_MAC_1000MBPS   = 0x02,
40     INVALID_SPEED      = 0x03
41 } mss_mac_speed_t;
42 
43 /***************************************************************************//**
44  * MAC interface speed mode selector
45  *
46  * This enumeration specifies the various interface speed mode to use when
47  * calling _MSS_MAC_change_speed()_. Anything other than _MSS_MAC_SPEED_AN_
48  * results in a fixed speed/duplex configuration and the link partner must be
49  * configured the same way for proper communications to be achieved.
50  *
51  * __Note:__ If the link partner is configured for autonegotiation, then
52  * selection of a fixed speed, full duplex mode will probably result in a half
53  * duplex mismatched mode of operation due to the way autonegotiation works.
54  */
55 typedef enum __mss_mac_speed_mode_t
56 {
57     MSS_MAC_SPEED_AN   = 0x00, /*!< Link operates in autonegotiation mode */
58     MSS_MAC_10_HDX     = 0x01, /*!< Link operates in 10M half duplex mode */
59     MSS_MAC_10_FDX     = 0x02, /*!< Link operates in 10M full duplex mode */
60     MSS_MAC_100_HDX    = 0x03, /*!< Link operates in 100M half duplex mode */
61     MSS_MAC_100_FDX    = 0x04, /*!< Link operates in 100M full duplex mode */
62     MSS_MAC_1000_HDX   = 0x05, /*!< Link operates in 1000M half duplex mode */
63     MSS_MAC_1000_FDX   = 0x06, /*!< Link operates in 1000M full duplex mode */
64     INVALID_SPEED_MODE = 0x07
65 } mss_mac_speed_mode_t;
66 
67 /****************************************************************************//**
68  * MAC RX interrupt control
69  *
70  * This enumeration indicates the action to take in relation to the RX interrupt
71  * when configuring an RX buffer with _MSS_MAC_receive_pkt()_. These values
72  * enable control of the interrupt setup so that the receive descriptors can be
73  * initialized safely.
74  */
75 typedef enum __mss_mac_rx_int_ctrl_t
76 {
77     MSS_MAC_INT_ARM     = -1, /*!< Last buffer in chain so arm the RX interrupt */
78     MSS_MAC_INT_DISABLE =  0, /*!< Disable interrupts on exit */
79     MSS_MAC_INT_ENABLE  =  1, /*!< Leave interrupts enabled on exit */
80 } mss_mac_rx_int_ctrl_t;
81 
82 /****************************************************************************//**
83  * MAC PHY Reset type
84  *
85  * This enumeration specifies the type of reset signal to act on when calling
86  * _MSS_MAC_phy_reset()_.
87  */
88 typedef enum __mss_mac_phy_reset_t
89 {
90     MSS_MAC_SOFT_RESET = 0,
91     MSS_MAC_HARD_RESET = 1
92 } mss_mac_phy_reset_t;
93 
94 
95 
96 /***************************************************************************//**
97  * AMBA burst length defines. These are used when setting the
98  * _amba_burst_length_ field in the _mss_mac_cfg_t structure_.
99  */
100 
101 #define MSS_MAC_AMBA_BURST_256  (0U)
102 #define MSS_MAC_AMBA_BURST_1    (1U)
103 #define MSS_MAC_AMBA_BURST_4    (4U)
104 #define MSS_MAC_AMBA_BURST_8    (8U)
105 #define MSS_MAC_AMBA_BURST_16   (16U)
106 #define MSS_MAC_AMBA_BURST_MASK (31U)
107 
108 
109 /***************************************************************************//**
110  * Pointer to PHY init function
111  *
112  * This defines the prototype for the PHY driver function which is called by the
113  * MSS Ethernet MAC driver to initialize the PHY. This function is registered
114  * with the MSS Ethernet MAC driver via the _phy_init_ entry in the
115  * _mss_mac_cfg_t_ structure passed to _MSS_MAC_init()_.
116  *
117  * The function should match the following prototype:
118  *     `void MSS_MAC_phy_init(const void *this_mac, uint8_t phy_addr);`
119  *
120  * - The _this_mac_ parameter is actually a pointer to the
121  * _mss_mac_instance_t_ for the GEM to which the PHY is attached. It is declared
122  * as `void *` to avoid issues with recursive structure name references.
123  *
124  * - The _phy_addr_ parameter is the address of the PHY on the MDIO interface.
125  *
126  */
127 typedef void (*mss_mac_phy_init_t)(/* mss_mac_instance_t */ const void *this_mac, uint8_t phy_addr);
128 
129 
130 /***************************************************************************//**
131  * Pointer to PHY set link speed function
132  *
133  * This defines the prototype for the PHY driver function which is called by the
134  * MSS Ethernet MAC driver to set the link speed for the PHY. This function is
135  * registered with the MSS Ethernet MAC driver via the _phy_set_link_speed_
136  * entry in the _mss_mac_cfg_t_ structure passed to _MSS_MAC_init()_.
137  *
138  * The function should match the following prototype:
139  * `void MSS_MAC_phy_set_link_speed
140  * (
141  *      const void *this_mac,
142  *      uint32_t speed_duplex_select,
143  *      mss_mac_speed_mode_t speed_mode
144  * );`
145  *
146  * - The _this_mac_ parameter is actually a pointer to the
147  * _mss_mac_instance_t_ for the GEM to which the PHY is attached. It is declared
148  * as `void *` to avoid issues with recursive structure name references.
149  *
150  * - The _speed_duplex_select_ parameter indicates the link speed and duplex
151  * combinations to allow when autonegotiation is selected via speed_mode.
152  *
153  * - The _speed_mode_ parameter either selects a specific single duplex and
154  * speed combination or autonegotiation as the mode to use.
155  */
156 typedef void (*mss_mac_phy_set_speed_t)(/* mss_mac_instance_t */ void *this_mac, uint32_t speed_duplex_select, mss_mac_speed_mode_t speed_mode);
157 
158 
159 /***************************************************************************//**
160  * Pointer to PHY autonegotiate function
161  *
162  * This defines the prototype for the PHY driver functions which are called by
163  * the MSS Ethernet MAC driver to instruct the PHY to carry out an
164  * autonegotiation operation on the Ethernet link or the SGMII link. These
165  * functions are registered with the MSS Ethernet MAC driver via the
166  * _phy_autonegotiate_ and _phy_mac_autonegotiate_ entries in the
167  * _mss_mac_cfg_t_ structure passed to _MSS_MAC_init()_.
168  *
169  * The function should match the following prototype:
170  *     `void MSS_MAC_phy_autonegotiate(const void *this_mac);`
171  *
172  * - The _this_mac_ parameter is actually a pointer to the
173  * _mss_mac_instance_t_ for the GEM to which the PHY is attached. It is declared
174  * as `void *` to avoid issues with recursive structure name references.
175  */
176 typedef void (*mss_mac_phy_autonegotiate_t)(/* mss_mac_instance_t */ const void *this_mac);
177 
178 
179 /***************************************************************************//**
180  * Pointer to PHY get link status function
181  *
182  * This defines the prototype for the PHY driver function which is called by the
183  * MSS Ethernet MAC driver to fetch the link status from the PHY. This function
184  * is registered with the MSS Ethernet MAC driver via the _phy_get_link_status_
185  * entry in the _mss_mac_cfg_t_ structure passed to _MSS_MAC_init()_.
186  *
187  * The function should match the following prototype:
188  * `uint8_t MSS_MAC_phy_get_link_status
189  * (
190  *     const void *this_mac,
191  *     mss_mac_speed_t * speed,
192  *     uint8_t * fullduplex
193  * );`
194  *
195  * - The _this_mac_ parameter is actually a pointer to the
196  * _mss_mac_instance_t_ for the GEM to which the PHY is attached. It is declared
197  * as `void *` to avoid issues with recursive structure name references.
198  *
199  * - The _speed parameter_ is a pointer to where to store the current link
200  * speed.
201  *
202  * - The _full_duplex_ parameter is a pointer to where to store the current link
203  * duplex state - 0 for half duplex and 1 for full duplex.
204  *
205  * - The function returns 0 if the link is currently down and 1 if it is currently
206  * active.
207  *
208  * __Note:__ If the link is not active, the speed and duplex values will not be
209  * updated.
210  */
211 typedef uint8_t (*mss_mac_phy_get_link_status_t)
212 (
213     /* mss_mac_instance_t*/ const void *this_mac,
214     mss_mac_speed_t * speed,
215     uint8_t * fullduplex
216 );
217 
218 
219 #if MSS_MAC_USE_PHY_DP83867
220 /***************************************************************************//**
221  * Pointer to PHY extended read function.
222  *
223  * Many of the example PHY devices support access to registers outside of the
224  * 0 to 31 address range available via the management interface through the use
225  * of paging registers and this can be done via the normal PHY register access
226  * routines. The DP83867 PHYs use a different addressing mechanism for accessing
227  * extended registers and this function implements the read support.
228  *
229  * The function should match the following prototype:
230  * `uint16_t ti_read_extended_regs(const void * this_mac, uint16_t reg);`
231  *
232  * - The _this_mac_ parameter is actually a pointer to the
233  * _mss_mac_instance_t_ for the GEM to which the PHY is attached. It is declared
234  * as `void *` to avoid issues with recursive structure name references.
235  *
236  * - The _reg_ parameter identifies the register to read from.
237  */
238 typedef uint16_t (*mss_mac_phy_extended_read_t)(/* mss_mac_instance_t */ const void *this_mac, uint16_t reg);
239 
240 
241 /***************************************************************************//**
242  * Pointer to PHY extended write function
243  *
244  * Many of the example PHY devices support access to registers outside of the
245  * 0 to 31 address range available via the management interface through the use
246  * of paging registers and this can be done via the normal PHY register access
247  * routines. The DP83867 PHYs use a different addressing mechanism for accessing
248  * extended registers and this function implements the write  support.
249  *
250  * The function should match the following prototype:
251  * `void ti_write_extended_regs(mss_mac_instance_t * this_mac, uint16_t reg);`
252  *
253  * - The _this_mac_ parameter is actually a pointer to the
254  * _mss_mac_instance_t_ for the GEM to which the PHY is attached. It is declared
255  * as `void *` to avoid issues with recursive structure name references.
256  *
257  * - The _reg_ parameter identifies the register to write to.
258  *
259  * - The _data_ parameter is the value to write to the register.
260  */
261 typedef void (*mss_mac_phy_extended_write_t)(/* mss_mac_instance_t */ const void *this_mac, uint16_t reg, uint16_t data);
262 #endif
263 
264 
265 /***************************************************************************//**
266   PolarFire SoC MSS Ethernet MAC Configuration Structure.
267 
268   The _mss_mac_cfg_t_ type contains the initial configuration values for the
269   MPFS Ethernet MAC. You need to create a record of this type to hold the
270   configuration of the MAC. _MSS_MAC_cfg_struct_def_init()_ is used to
271   initialize the configuration record to default values. Later, the
272   configuration elements in the record can be changed to desired values before
273   passing them to _MSS_MAC_init()_.
274 
275   __Note:__ Even though most of these values are small, we use _uint32_t_ for
276   most values here as they will be used in calculations that are based on
277   _uint32_t_ values and this avoids having to put casts everywhere...
278 
279   ___interface_type___:
280     This indicates the type of interface between the MAC and the PHY. The
281     currently supported values are:
282 
283       - _NULL_PHY_   – No PHY involved, usually for direct connection via the
284                        fabric.
285       - _GMII_       – Connection via GMII routed through the fabric to external
286                        PHY device.
287       - _TBI_        – Connection via SGMII block to external PHY device.
288       - _GMII_SGMII_ – Emulation platform specific option using SGMII to GMII
289                        bridge.
290 
291   ___phy_type___:
292     This indicates the type of PHY device connected to the MAC. The currently
293     supported values are:
294 
295       - _MSS_MAC_DEV_PHY_NULL_         – No PHY device.
296       - _MSS_MAC_DEV_PHY_VSC8575_      – VSC8575 with full VTSS API.
297       - _MSS_MAC_DEV_PHY_VSC8575_LITE_ – VSC8757 with Lite VTSS API.
298       - _MSS_MAC_DEV_PHY_VSC8541_      – VSC8541 without VTSS API.
299       - _MSS_MAC_DEV_PHY_VSC8662_      – VSC88662 without VTSS API.
300       - _MSS_MAC_DEV_PHY_DP83867_      – TI DP83867.
301 
302   ___phy_init___
303   ___phy_set_link_speed___
304   ___phy_autonegotiate___
305   ___phy_autonegotiate_mac___
306   ___phy_get_link_status___
307   ___phy_extended_read___
308   ___phy_init_extended_write___:
309     These are callback functions for the PHY support within the driver. These
310     should be set to the appropriate PHY driver functions for the attached PHY
311     device. See _mss_mac_phy_init_t_, _mss_mac_phy_set_speed_t_,
312     _mss_mac_phy_autonegotiate_t_, _mss_mac_phy_get_link_status_t_,
313     _mss_mac_phy_extended_read_t_ and _mss_mac_phy_extended_write_t_ for
314     details.
315 
316   ___queue_enable___:
317     This array of values of length _MSS_MAC_QUEUE_COUNT_, indicates which queues
318     are to be enabled. 0 in an entry indicates disabled and 1 indicates enabled.
319 
320   ___speed_mode___:
321     This parameter specifies the mode of operation for the Ethernet interface.
322     The following values are supported:
323 
324       - _MSS_MAC_SPEED_AN_
325       - _MSS_MAC_10_HDX_
326       - _MSS_MAC_10_FDX_
327       - _MSS_MAC_100_HDX_
328       - _MSS_MAC_100_FDX_
329       - _MSS_MAC_1000_HDX_
330       - _MSS_MAC_1000_FDX_
331 
332     If _MSS_MAC_SPEED_AN_ is selected then the _speed_duplex_select_
333     configuration parameter indicates the allowed speed combinations. For all
334     other modes, the link autonegotiation is disabled.
335 
336   ___speed_duplex_select___:
337     This configuration parameter specifies the allowed link speeds when
338     autonegotiation is enabled. It is a bit-mask of the various link speed and
339     duplex modes. The speed_duplex_select configuration can be set to a bitmask
340     of the following defines to specify the allowed link speed and duplex mode:
341 
342       - _MSS_MAC_ANEG_10M_FD_
343       - _MSS_MAC_ANEG_10M_HD_
344       - _MSS_MAC_ANEG_100M_FD_
345       - _MSS_MAC_ANEG_100M_HD_
346       - _MSS_MAC_ANEG_1000M_FD_
347       - _MSS_MAC_ANEG_1000M_HD_
348 
349     The _MSS_MAC_cfg_struct_def_init()_ function sets this configuration
350     parameter to _MSS_MAC_ANEG_ALL_SPEEDS_ indicating that a link will be setup
351     for best available speed and duplex combination.
352 
353   ___mac_addr___:
354     This configuration parameter is a 6-byte array containing the local MAC
355     address of the Ethernet MAC. For correct operation, this value should be
356     unique for each of the 4 MAC elements within the MSS and if more than one
357     system containing an MPFS device is present on a LAN then the MAC addresses
358     must all be unique. Tha management and allocation of the MAC addresses is
359     left up to the user.
360 
361   ___phy_address___:
362     This parameter specifies the address of the PHY device, usually set in
363     hardware by the address pins of the PHY device.
364 
365   ___pcs_phy_address___:
366     This parameter specifies the address of the control device for hidden SGMII
367     type interfaces such as that in the G5 SoC emulation platform.
368 
369   ___phy_soft_reset_gpio___:
370     Identifies the MSS GPIO device that the PHY soft reset pin is connected to.
371     A Value of _NULL_ indicates the soft reset signal is not available for
372     control via an MSS GPIO pin.
373 
374   ___phy_soft_reset_pin___:
375     Identifies the MSS GPIO pin that the PHY soft reset pin is connected to.
376 
377   ___phy_hard_reset_gpio___:
378     Identifies the MSS GPIO device that the PHY hard reset pin is connected to.
379     A Value of _NULL_ indicates the hard reset signal is not available for
380     control via an MSS GPIO pin.
381 
382   ___phy_hard_reset_pin___:
383     Identifies the MSS GPIO pin that the PHY hard reset pin is connected to.
384 
385   ___phy_controller___:
386     Pointer to the MAC instance structure to which the PHY is connected. This
387     supports the use of multi-port PHY devices which may be connected to a
388     single MAC device or configurations where only a single MDIO interface is
389     exposed to the outside world. If _NULL_, the current MAC device is used.
390 
391     In configurations that use this feature, it is important that the MAC device
392     that the PHY is connected to is initialized first.
393 
394   ___tx_edc_enable___:
395     This parameter specifies enable or disable error detection and correction
396     for tx FIFOs. The allowed values for the tx_edc_enable configuration
397     parameter are:
398 
399       - _MSS_MAC_ERR_DET_CORR_ENABLE_
400       - _MSS_MAC_ERR_DET_CORR_DISABLE_
401 
402     The _MSS_MAC_cfg_struct_def_init()_ function sets this configuration
403     parameter to _MSS_MAC_ERR_DET_CORR_DISABLE_.
404 
405   ___rx_edc_enable___:
406     This parameter specifies enable or disable error detection and correction
407     for rx FIFOs. The allowed values for the _rx_edc_enable_ configuration
408     parameter are:
409 
410       - _MSS_MAC_ERR_DET_CORR_ENABLE_
411       - _MSS_MAC_ERR_DET_CORR_DISABLE_
412 
413     The _MSS_MAC_cfg_struct_def_init()_ function sets this configuration
414     parameter to _MSS_MAC_ERR_DET_CORR_DISABLE_.
415 
416   ___jumbo_frame_enable___:
417     This parameter allows enabling or disabling jumbo frame support. When
418     enabled, it allows frames longer than the standard 1536 byte maximum frame
419     length to be transmitted and received. When disabled, the MAC limits the
420     length of frames at the maximum frame length. The allowed values for the
421     _jumbo_frame_enable_ configuration parameter are:
422 
423       - _MSS_MAC_JUMBO_FRAME_ENABLE_
424       - _MSS_MAC_JUMBO_FRAME_DISABLE_
425 
426     The _MSS_MAC_cfg_struct_def_init()_ function sets this configuration
427     parameter to _MSS_MAC_JUMBO_FRAME_DISABLE_.
428 
429   ___jumbo_frame_default___:
430     This parameter sets the initial maximum jumbo frame length. The
431     _MSS_MAC_cfg_struct_def_init()_ function sets this configuration parameter
432     to _MSS_MAC_MAX_PACKET_SIZE_.
433 
434   ___length_field_check___:
435     This parameter specifies enable or disable length field check. When enabled,
436     the MAC checks the frame length field of received frames to ensure it
437     matches the actual data field length. The allowed values for the
438     _length_field_check_ configuration parameter are:
439 
440       - _MSS_MAC_LENGTH_FIELD_CHECK_ENABLE_
441       - _MSS_MAC_LENGTH_FIELD_CHECK_DISABLE_
442 
443     The _MSS_MAC_cfg_struct_def_init()_ function sets this configuration
444     parameter to _MSS_MAC_LENGTH_FIELD_CHECK_ENABLE_
445 
446   ___append_CRC___:
447     This parameter specifies enable or disable appending a CRC to transmitted
448     packets. When enabled, the MAC appends a CRC to all frames. When disabled,
449     frames presented to the MAC must have a valid length and contain a valid
450     CRC. The allowed values for the _append_CRC_ parameter are:
451 
452       - _MSS_MAC_CRC_ENABLE_
453       - _MSS_MAC_CRC_DISABLE_
454 
455     The _MSS_MAC_cfg_struct_def_init()_ function sets this configuration
456     parameter to _MSS_MAC_CRC_ENABLE_.
457 
458   ___fullduplex___:
459     This specifies enable or disable full duplex. When enabled, the MAC operates
460     in full duplex mode. When disabled, the MAC operates in half duplex mode.
461     The allowed values for the _fullduplex_ configuration parameter are:
462 
463       - _MSS_MAC_FULLDUPLEX_ENABLE_
464       - _MSS_MAC_FULLDUPLEX_DISABLE_
465 
466     The _MSS_MAC_cfg_struct_def_init()_ function sets this configuration
467     parameter to _MSS_MAC_FULLDUPLEX_ENABLE_.
468 
469   ___loopback___:
470     This parameter specifies enable or disable loop back mode. When enabled, the
471     MAC transmit outputs to be looped back to its receiving inputs. The allowed
472     values for the _loopback_ configuration parameter are:
473 
474       - _MSS_MAC_LOOPBACK_ENABLE_
475       - _MSS_MAC_LOOPBACK_DISABLE_
476 
477     The _MSS_MAC_cfg_struct_def_init()_ function sets this configuration
478     parameter to _MSS_MAC_LOOPBACK_DISABLE_.
479 
480   ___rx_flow_ctrl___:
481     This parameter allows enabling or disabling receiver flow control. When
482     enabled, the MAC detects and acts on PAUSE flow control frames. When
483     disabled, it ignores PAUSE flow control frames. The allowed values for the
484     _rx_flow_ctrl_ configuration parameter are:
485 
486       - _MSS_MAC_RX_FLOW_CTRL_ENABLE_
487       - _MSS_MAC_RX_FLOW_CTRL_DISABLE_
488 
489     The _MSS_MAC_cfg_struct_def_init()_ function sets this configuration
490     parameter to _MSS_MAC_RX_FLOW_CTRL_ENABLE_.
491 
492   ___tx_flow_ctrl___:
493     This parameter allows enabling or disabling transmitter flow control. When
494     enabled, the transmitter sends PAUSE flow control frames when requested by
495     the system. When disabled, prevents the transmitter from sending flow
496     control frames. The allowed values for the _tx_flow_ctrl_ configuration
497     parameter are:
498 
499       - _MSS_MAC_TX_FLOW_CTRL_ENABLE_
500       - _MSS_MAC_TX_FLOW_CTRL_DISABLE_
501 
502     The _MSS_MAC_cfg_struct_def_init()_ function sets this configuration
503     parameter to _MSS_MAC_TX_FLOW_CTRL_ENABLE_.
504 
505   ___ipg_multiplier___
506   ___ipg_divisor___:
507     These parameters specify the minimum size of gap (IPG/IFG) to enforce
508     between frames (expressed in bit times). They are both 8 bit values and are
509     used to calculate an IPG value based on the last packet sent by multiplying
510     the length by _ipg_multiplier_ and dividing the result by _ipg_divisor_. The
511     resulting number of bits is used if it is greater than the default 96 bits.
512 
513     To select standard 96 bit IPG, set _ipg_multiplier_ to _MSS_MAC_IPG_DEFVAL_.
514 
515     The _MSS_MAC_cfg_struct_def_init()_ function sets this configuration
516     parameter to _MSS_MAC_IPG_DEFVAL_.
517 
518   ___phyclk___:
519     This parameter specifies the MII management clock divider value. PCLK
520     is the source clock. This should be chosen to ensure that MDC has a
521     frequency that is no greater than 2.5MHz. The allowed values for the phyclk
522     configuration parameter are:
523 
524       - _MSS_MAC_DEF_PHY_CLK_
525       - _MSS_MAC_BY8_PHY_CLK_
526       - _MSS_MAC_BY16_PHY_CLK_
527       - _MSS_MAC_BY32_PHY_CLK_
528       - _MSS_MAC_BY48_PHY_CLK_
529       - _MSS_MAC_BY64_PHY_CLK_
530       - _MSS_MAC_BY96_PHY_CLK_
531       - _MSS_MAC_BY128_PHY_CLK_
532       - _MSS_MAC_BY224_PHY_CLK_
533 
534     The _MSS_MAC_cfg_struct_def_init()_ function sets this configuration
535     parameter to _MSS_MAC_DEF_PHY_CLK_.
536 
537   ___max_frame_length___:
538     This parameter specifies the maximum frame size in both the transmit and
539     receive directions. The allowed values for the _max_frame_length_
540     configuration parameter are:
541 
542       - _MSS_MAC_MAXFRAMELEN_DEFVAL_
543       - _MSS_MAC_MAXFRAMELEN_MAXVAL_
544 
545     The _MSS_MAC_cfg_struct_def_init()_ function sets this configuration
546     parameter to _MSS_MAC_MAXFRAMELEN_DEFVAL_.
547 
548   ___use_hi_address___:
549     When set to 0, _use_hi_address_ selects the default AXI slave slot 5 address
550     for the location of the registers of the GEM device. When set to non 0, AXI
551     slave slot 6 is used to access the device.
552 
553     The _MSS_MAC_cfg_struct_def_init()_ function sets this configuration
554     parameter to 0.
555 
556   ___use_local_ints___:
557     When set to 0, _use_local_ints_ selects the PLIC interrupts as the source
558     for interrupts from the GEM. When set to non 0, local interrupts are used.
559     GEM0 is connected to the local interrupts of U54 numbers 1 and 2. GEM1 is
560     connected to the local interrupts of U54 numbers 3 and 4.
561 
562     The _MSS_MAC_cfg_struct_def_init()_ function sets this configuration
563     parameter to 0.
564 
565   ___queue0_int_priority___:
566   ___queue1_int_priority___:
567   ___queue2_int_priority___:
568   ___queue3_int_priority___:
569   ___mmsl_int_priority___:
570     These parameters indicate the interrupt priority to use for each of the
571     interrupt sources that the GEM supports. A priority of 0 effectively
572     disables an interrupt and a priority of 7 is the highest priority that can
573     be assigned.
574 
575     _queue0_int_priority_ is the priority for the primary queue for the pMAC and
576     the only queue for the eMAC.
577 
578     The _MSS_MAC_cfg_struct_def_init()_ function sets these configuration
579     parameters to 7.
580 
581   ___tsu_clock_select___:
582     Selects the TSU clock source. 0 is the default TSU clock source and 1 is the
583     alternative TSU clock source driven from the fabric.
584 
585     The _MSS_MAC_cfg_struct_def_init()_ function sets this configuration
586     parameter to 0.
587 
588   ___amba_burst_length___:
589     Sets the burst length for the DMA AXI data access transfers. Valid values
590     are:
591 
592     - 0x00 - Attempt to use bursts up to 256
593     - 0x01 - Always use single bursts
594     - 0x02 - Always use single bursts
595     - 0x04 - Attempt to use bursts up to 4
596     - 0x08 - Attempt to use bursts up to 8
597     - 0x10 - Attempt to use bursts up to 16
598 
599     The _MSS_MAC_cfg_struct_def_init()_ function sets this configuration parameter
600     to 0x10 for bursts up to 16.
601  */
602 
603 typedef struct __mss_mac_cfg_t
604 {
605     uint32_t interface_type;            /*!< Type of network interface associated with this GEM */
606     uint32_t phy_type;                    /*!< PHY device type associated with this GEM */
607     /* PHY interface functions */
608     mss_mac_phy_init_t            phy_init; /*!< Pointer to PHY init function */
609     mss_mac_phy_set_speed_t       phy_set_link_speed; /*!< Pointer to PHY set link speed function */
610     mss_mac_phy_autonegotiate_t   phy_autonegotiate; /*!< Pointer to PHY initiate autonegotiation function */
611     mss_mac_phy_autonegotiate_t   phy_mac_autonegotiate; /*!< Pointer to PHY initiate autonegotiation for SGMII link function */
612     mss_mac_phy_get_link_status_t phy_get_link_status; /*!< Pointer to PHY get link status function */
613 #if MSS_MAC_USE_PHY_DP83867
614     mss_mac_phy_extended_read_t   phy_extended_read; /*!< Pointer to PHY extended read function */
615     mss_mac_phy_extended_write_t  phy_extended_write; /*!< Pointer to PHY extended write function */
616 #endif
617     uint32_t queue_enable[MSS_MAC_QUEUE_COUNT]; /*!< Enables for additional queues */
618     mss_mac_speed_mode_t speed_mode;    /*!< Link speed mode of operation */
619     uint32_t speed_duplex_select;       /*!< Link speed and duplex mode allowed to setup a link when autonegotiation is enabled. */
620     uint8_t  mac_addr[6];               /*!< Station's MAC address */
621     uint32_t phy_addr;                  /*!< Address of Ethernet PHY on MII management interface. */
622     uint32_t pcs_phy_addr;              /*!< Address of SGMII interface controller on MII management interface. */
623 #if defined(MSS_MAC_PHY_HW_RESET) || defined(MSS_MAC_PHY_HW_SRESET)
624     GPIO_TypeDef  *phy_soft_reset_gpio; /*!< GPIO device soft reset for PHY is connected to */
625     mss_gpio_id_t  phy_soft_reset_pin;  /*!< GPIO pin soft reset for PHY is connected to */
626     GPIO_TypeDef  *phy_hard_reset_gpio; /*!< GPIO device hard reset for PHY is connected to */
627     mss_gpio_id_t  phy_hard_reset_pin;  /*!< GPIO pin hard reset for PHY is connected to */
628 #endif
629     /* Use struct instead of typedef as compiler gets confused otherwise... */
630     struct mss_mac_instance *phy_controller; /* Which MAC structure PHY is connected to */
631     uint32_t tx_edc_enable;             /*!< Enable / disable error detection and correction for tx FIFOs */
632     uint32_t rx_edc_enable;             /*!< Enable / disable error detection and correction for rx FIFOs */
633     uint32_t jumbo_frame_enable;        /*!< Enable / disable jumbo frame support: default is disable 0 */
634     uint32_t jumbo_frame_default;       /*!< Default maximum size for jumbo frames */
635     uint32_t length_field_check;        /*!< Enable / disable length field checking */
636     uint32_t append_CRC;                /*!< Enable / disable appending CRC */
637     uint32_t fullduplex;                /*!< Enable / disable full duplex: default is disable 0 */
638     uint32_t loopback;                  /*!< Enable / disable loopback mode: default is disable 0 */
639     uint32_t rx_flow_ctrl;              /*!< Enable / disable receiver flow control: default is disable 0 */
640     uint32_t tx_flow_ctrl;              /*!< Enable / disable transmitter flow control: default is disable 0 */
641     uint32_t ipg_multiplier;            /*!< 8-bit IPG multiplication factor, if 0 we disable IPG stretching */
642     uint32_t ipg_divisor;               /*!< 8-bit back to back inter-frame gap value */
643     uint32_t phyclk;                    /*!< 3-bit MGMT clock divider value */
644     uint32_t max_frame_length;          /*!< Maximum frame length: default value is 0x0600(1536d) */
645     uint32_t use_hi_address;            /*!< Non 0 means use upper address range for this device */
646     uint32_t use_local_ints;            /*!< non 0 means use local interrupts for MAC instead of PLIC */
647     uint32_t queue0_int_priority;       /*!< Main MAC interrupt */
648     uint32_t queue1_int_priority;       /*!< Queue 1 interrupt */
649     uint32_t queue2_int_priority;       /*!< Queue 2 interrupt */
650     uint32_t queue3_int_priority;       /*!< Queue 3 interrupt */
651     uint32_t mmsl_int_priority;         /*!< MMSL interrupt */
652     uint32_t tsu_clock_select;          /*!< 0 for default TSU clock, 1 for fabric tsu clock */
653     uint32_t amba_burst_length;         /*!< AXI burst length for DMA data transfers */
654 } mss_mac_cfg_t;
655 
656 /***************************************************************************//**
657  * This enumeration is used for accessing Transmit and Receive statistics. The
658  * statistic which is desired to be read is passed to _MSS_MAC_read_stat()_. The
659  * width of the returned statistic value is indicated in the comment against the
660  * statistic.
661  *
662  * These registers are cleared when read, so in order to maintain a proper
663  * running total, the software should maintain counts which are updated by
664  * adding the values each time a statistic count is read.
665  *
666  * __Note:__ Counts do not roll over when the maximum is reached so a reading of
667  * 2^n - 1 indicates that at least that many of the indicated event have
668  * occurred since the last read.
669  */
670 typedef enum __mss_mac_stat_t
671 {
672     MSS_MAC_TX_OCTETS_LOW,                /*!< 32-bit - LSBs of transmitted octets count */
673     MSS_MAC_TX_OCTETS_HIGH,               /*!< 16-bit - MSBs of transmitted octets count */
674     MSS_MAC_TX_FRAMES_OK,                 /*!< 32-bit - Overall count of frames successfully transmitted */
675     MSS_MAC_TX_BCAST_FRAMES_OK,           /*!< 32-bit - Count of broadcast frames successfully transmitted */
676     MSS_MAC_TX_MCAST_FRAMES_OK,           /*!< 32-bit - Count of multicast frames successfully transmitted */
677     MSS_MAC_TX_PAUSE_FRAMES_OK,           /*!< 32-bit - Count of pause successfully transmitted */
678     MSS_MAC_TX_64_BYTE_FRAMES_OK,         /*!< 32-bit - Count of 64 byte frames successfully transmitted (excluding pause frames) */
679     MSS_MAC_TX_65_BYTE_FRAMES_OK,         /*!< 32-bit - Count of 65 to 127 byte frames successfully transmitted */
680     MSS_MAC_TX_128_BYTE_FRAMES_OK,        /*!< 32-bit - Count of 128 to 255 byte frames successfully transmitted */
681     MSS_MAC_TX_256_BYTE_FRAMES_OK,        /*!< 32-bit - Count of 256 to 511 byte frames successfully transmitted */
682     MSS_MAC_TX_512_BYTE_FRAMES_OK,        /*!< 32-bit - Count of 512 to 1023 byte frames successfully transmitted */
683     MSS_MAC_TX_1024_BYTE_FRAMES_OK,       /*!< 32-bit - Count of 1024 to 1518 byte frames successfully transmitted */
684     MSS_MAC_TX_1519_BYTE_FRAMES_OK,       /*!< 32-bit - Count of frames longer than 1518 bytes successfully transmitted */
685     MSS_MAC_TX_UNDERRUNS,                 /*!< 10-bit - Count of frames not transmitted due to under runs */
686     MSS_MAC_TX_SINGLE_COLLISIONS,         /*!< 18-bit - Count of single collision transmit events */
687     MSS_MAC_TX_MULTIPLE_COLLISIONS,       /*!< 18-bit - Count of 2 to 15 collision burst events */
688     MSS_MAC_TX_EXCESSIVE_COLLISIONS,      /*!< 10-bit - Count of frames discarded because 16 collisions occurred */
689     MSS_MAC_TX_LATE_COLLISIONS,           /*!< 10-bit - Count of collisions detected after the 512 bit slot time */
690     MSS_MAC_TX_DEFERRED_FRAMES,           /*!< 18-bit - Count of frames deferred due to carrier sense being active */
691     MSS_MAC_TX_CRS_ERRORS,                /*!< 10-bit - Count of Carrier Sense Errors  */
692 
693     MSS_MAC_RX_OCTETS_LOW,                /*!< 32-bit - LSBs of received octets count */
694     MSS_MAC_RX_OCTETS_HIGH,               /*!< 16-bit - MSBs of received octets count */
695     MSS_MAC_RX_FRAMES_OK,                 /*!< 32-bit - Overall count of frames successfully received */
696     MSS_MAC_RX_BCAST_FRAMES_OK,           /*!< 32-bit - Count of broadcast frames successfully received */
697     MSS_MAC_RX_MCAST_FRAMES_OK,           /*!< 32-bit - Count of multicast cast frames successfully received */
698     MSS_MAC_RX_PAUSE_FRAMES_OK,           /*!< 32-bit - Count of pause frames successfully received */
699     MSS_MAC_RX_64_BYTE_FRAMES_OK,         /*!< 32-bit - Count of 64 byte frames successfully received (excluding pause frames) */
700     MSS_MAC_RX_65_BYTE_FRAMES_OK,         /*!< 32-bit - Count of 65 to 127 byte frames successfully received */
701     MSS_MAC_RX_128_BYTE_FRAMES_OK,        /*!< 32-bit - Count of 128 to 255 byte frames successfully received */
702     MSS_MAC_RX_256_BYTE_FRAMES_OK,        /*!< 32-bit - Count of 256 to 511 byte frames successfully received */
703     MSS_MAC_RX_512_BYTE_FRAMES_OK,        /*!< 32-bit - Count of 512 to 1023 byte frames successfully received */
704     MSS_MAC_RX_1024_BYTE_FRAMES_OK,       /*!< 32-bit - Count of 1024 to 1518 byte frames successfully received */
705     MSS_MAC_RX_1519_BYTE_FRAMES_OK,       /*!< 32-bit - Count of frames longer than 1518 bytes successfully received */
706     MSS_MAC_RX_UNDERSIZE_FRAMES_OK,       /*!< 10-bit - Count of undersize frames received */
707     MSS_MAC_RX_OVERSIZE_FRAMES_OK,        /*!< 10-bit - Count of frames received over the maximum allowed length (1518, 1536 or 10240 depending on settings) */
708     MSS_MAC_RX_JABBERS,                   /*!< 10-bit - Count of received jabber frames - excess length with errors */
709     MSS_MAC_RX_FCS_ERRORS,                /*!< 10-bit - Count of frames received with incorrect CRC values */
710     MSS_MAC_RX_LENGTH_ERRORS,             /*!< 10-bit - Count of frames received ok where the length received does not match the length field */
711     MSS_MAC_RX_SYMBOL_ERRORS,             /*!< 10-bit - Count of frames received with symbol errors */
712     MSS_MAC_RX_ALIGNMENT_ERRORS,          /*!< 10-bit - Count of frames received with non integral byte counts */
713     MSS_MAC_RX_RESOURCE_ERRORS,           /*!< 18-bit - Count of times a receive buffer descriptor was read with the used bit set */
714     MSS_MAC_RX_OVERRUNS,                  /*!< 10-bit - Count of frames not copied to memory due to receive overrun */
715     MSS_MAC_RX_IP_CHECKSUM_ERRORS,        /*!<  8-bit - Count of frames received with IP header checksum errors */
716     MSS_MAC_RX_TCP_CHECKSUM_ERRORS,       /*!<  8-bit - Count of frames received with TCP checksum errors */
717     MSS_MAC_RX_UDP_CHECKSUM_ERRORS,       /*!<  8-bit - Count of frames received with UDP checksum errors */
718     MSS_MAC_RX_AUTO_FLUSHED_PACKETS,      /*!< 16-bit - Count of frames flushed from receive SRAM buffers  */
719 
720     MSS_MAC_LAST_STAT                     /*!< Marker for end of valid statistics references */
721 } mss_mac_stat_t;
722 
723 /***************************************************************************//**
724  * This enumeration indicates which direction unicast packet is being
725  * referenced. This is used with the _MSS_MAC_set_TSU_unicast_addr()_ and
726  * _MSS_MAC_get_TSU_unicast_addr()_ functions.
727  */
728 typedef enum __mss_mac_tsu_addr_t
729 {
730     MSS_MAC_TSU_UNICAST_RX,
731     MSS_MAC_TSU_UNICAST_TX
732 } mss_mac_tsu_addr_t;
733 
734 /***************************************************************************//**
735  * This enumeration indicates DMA descriptor time stamp insertion modes. This
736  * indicates which types of packets should have their IEEE 1588 timestamps
737  * recorded in the transmit or receive descriptors.
738  *
739  *
740  * This value is used with the _MSS_MAC_get_TSU_rx_mode()_,
741  * _MSS_MAC_set_TSU_rx_mode()_, _MSS_MAC_get_TSU_tx_mode()_ and
742  * _MSS_MAC_set_TSU_tx_mode()_ functions.
743  */
744 typedef enum __mss_mac_tsu_mode_t
745 {
746     MSS_MAC_TSU_MODE_DISABLED,  /*!< Time stamp insertion disabled */
747     MSS_MAC_TSU_MODE_PTP_EVENT, /*!< Time stamp insertion for PTP Event frames only */
748     MSS_MAC_TSU_MODE_PTP_ALL,   /*!< Time stamp insertion all PTP frames */
749     MSS_MAC_TSU_MODE_ALL,       /*!< Time stamp insertion for all frames */
750     MSS_MAC_TSU_MODE_END
751 } mss_mac_tsu_mode_t;
752 
753 /***************************************************************************//**
754  * This enumeration indicates hash matching modes for accepting received frames.
755  * This value is used with the _MSS_MAC_set_hash_mode()_ and
756  * _MSS_MAC_get_hash_mode()_ functions.
757  */
758 typedef enum __mss_mac_hash_mode_t
759 {
760     MSS_MAC_HASH_NONE      = 0x00,     /*!< Hash matching disabled */
761     MSS_MAC_HASH_MULTICAST = 0x40,     /*!< Multicast matching enabled */
762     MSS_MAC_HASH_UNIICAST  = 0x80,     /*!< Unicast matching enabled */
763     MSS_MAC_HASH_ALL       = 0xC0      /*!< Multicast and Unicast matching enabled */
764 } mss_mac_hash_mode_t;
765 
766 /***************************************************************************//**
767  * This enumeration indicates sync time stamp adjust modes to use for One Step
768  * Synce operation (OSS). This value is used with the
769  * _MSS_MAC_set_TSU_oss_mode()_ and _MSS_MAC_get_TSU_oss_mode()_ functions.
770  */
771 typedef enum __mss_mac_oss_mode_t
772 {
773     MSS_MAC_OSS_MODE_DISABLED,  /*!< Sync time stamp adjust disabled */
774     MSS_MAC_OSS_MODE_REPLACE,   /*!< Sync time stamp replace mode */
775     MSS_MAC_OSS_MODE_ADJUST,    /*!< Sync time stamp adjust correction field mode */
776     MSS_MAC_OSS_MODE_INVALID,   /*!< Only for reporting mis-configured setup, not setting things... */
777     MSS_MAC_OSS_MODE_END
778 } mss_mac_oss_mode_t;
779 
780 
781 /***************************************************************************//**
782  * This enumeration indicates the pre-emption minimum fragment size which
783  * also determines the minimum number of bytes which the pMAC sends before
784  * pre-emption is allowed.
785  *
786  * This value is used in the _mss_mac_mssl_config_t_ structure _frag_size_
787  * field.
788  */
789 typedef enum __mss_mac_frag_size_t
790 {
791     MSS_MAC_FRAG_SIZE_64,
792     MSS_MAC_FRAG_SIZE_128,
793     MSS_MAC_FRAG_SIZE_192,
794     MSS_MAC_FRAG_SIZE_256,
795     MSS_MAC_FRAG_SIZE_END
796 } mss_mac_frag_size_t;
797 
798 
799 /***************************************************************************//**
800  * DMA Descriptor control and status bit field defines.
801  *
802  * The MSS Ethernet MAC driver creates and manages two descriptor rings for each
803  * queue to control the transmission and reception of packets. These defines are
804  * used when configuring the descriptors and when decoding the results of a
805  * packet receive or transmit operation.
806  *
807  * __Note:__ The driver currently uses a buffer scheme of one buffer per packet
808  * but it is possible to use multiple buffers which each contain a portion of
809  * the packet and some of the bit fields are of more importance in that type of
810  * buffer scheme.
811  *
812  * __Note:__ Some bits have different meanings based on the active configuration
813  * of the GEM and these defines represent the values for the configuration(s)
814  * used by the driver.
815  *
816  * The following are the transmit offload error codes and their meanings:
817  *  - 000 - No Error
818  *  - 001 - The Packet was identified as a VLAN type, but the header was not
819  *          fully complete, or had an error in it.
820  *  - 010 - The Packet was identified as a SNAP type, but the header was not
821  *          fully complete, or had an error in it.
822  *  - 011 - The Packet was not of an IP type, or the IP packet was invalidly
823  *          short, or the IP was not of type IPv4/IPv6.
824  *  - 100 - The Packet was not identified as VLAN, SNAP or IP.
825  *  - 101 - Non supported packet fragmentation occurred. For IPv4 packets, the
826  *          IP checksum was generated and inserted.
827  *  - 110 - Packet type detected was not TCP or UDP. TCP/UDP checksum was
828  *          therefore not generated. For IPv4 packets, the IP checksum was
829  *          generated and inserted.
830  *  - 111 - A premature end of packet was detected and the TCP/UDP checksum
831  *          could not be generated.
832  */
833 
834 #define GEM_RX_DMA_TS_PRESENT     BIT_02 /*!< @brief This descriptor contains a
835                                            valid time stamp which indicates the
836                                            receive time. */
837 #define GEM_RX_DMA_WRAP           BIT_01 /*!< @brief This is the last descriptor
838                                            in the chain and the DMA controller
839                                            will next access the first descriptor
840                                            in the chain. */
841 #define GEM_RX_DMA_USED           BIT_00 /*!< @brief Set to 0 by the driver to
842                                            indicate associated buffer is free.
843                                            Set to 1 by the GEM once a packet
844                                            or packet fragment is received into
845                                            the buffer. */
846 #define GEM_RX_DMA_BCAST          BIT_31 /*!< @brief  The received packet was
847                                            sent to the Ethernet global
848                                            broadcast address. */
849 #define GEM_RX_DMA_MULTICAST_HASH BIT_30 /*!< @brief The recieved packet matched
850                                            a multicast hash address. */
851 #define GEM_RX_DMA_UNICAST_HASH   BIT_29 /*!< @brief The recieved packet matched
852                                            a unicast hash address. */
853 #define GEM_RX_DMA_EXT_ADDR_MATCH BIT_28 /*!< @brief The recieved packet matched
854                                            an external address matching filter. */
855 #define GEM_RX_DMA_SPECIFIC_ADDR  BIT_27 /*!< @brief The recieved packet matched
856                                            an internal specific address matching
857                                            filter. */
858 #define GEM_RX_DMA_ADDR_REGISTER  (BIT_25 | BIT_26) /*!< @brief Bitfield
859                                                       indicating the specific
860                                                       address register the
861                                                       packet matched. */
862 #define GEM_RX_DMA_TYPE_ID_MATCH  BIT_24 /*!< @brief  If set a type ID register
863                                            match occurred. */
864 #define GEM_RX_DMA_TYPE_ID        (BIT_22 | BIT_23) /*!< @brief Bitfield
865                                                       indicating which ID
866                                                       register was matched. */
867 #define GEM_RX_DMA_VLAN_TAG       BIT_21 /*!< @brief Set if a VLAN tag was
868                                            detected in the packet. */
869 #define GEM_RX_DMA_PRIORITY_TAG   BIT_20 /*!< @brief Priority tag detected —
870                                            type ID of 0x8100 and null VLAN
871                                            identifier. For packets incorporating
872                                            the stacked VLAN processing feature,
873                                            this bit will be set if the second
874                                            VLAN tag received has a type ID of
875                                            0x8100 and a null VLAN identifier. */
876 #define GEM_RX_DMA_VLAN_PRIORITY  (BITS_03 << 17) /*!< @brief Bitfield
877                                                     indicating the VLAN
878                                                     priority. */
879 #define GEM_RX_DMA_FCS_ERROR      BIT_16 /*!< @brief Received FCS did not match
880                                            calculated FCS. */
881 #define GEM_RX_DMA_START_OF_FRAME BIT_15 /*!< @brief Set when this buffer holds
882                                            the start of a packet. */
883 #define GEM_RX_DMA_END_OF_FRAME   BIT_14 /*!< @brief Set when this buffer holds
884                                            the end of a packet. */
885 #define GEM_RX_DMA_JUMBO_BIT_13   BIT_13 /*!< @brief If jumbo frame reception
886                                            is enabled this is b13 of the packet
887                                            length. */
888 #define GEM_RX_DMA_BUFF_LEN       BITS_13 /*!< @brief b0 to b12 of the packet
889                                             length.  */
890 
891 #define GEM_TX_DMA_USED           BIT_31 /*!< @brief Set to 0 by the driver to
892                                            indicate buffer contains data to be
893                                            transmitted. Set to 1 by the GEM once
894                                            packet or packet fragment has been
895                                            sent from the buffer. */
896 #define GEM_TX_DMA_WRAP           BIT_30 /*!< @brief This is the last descriptor
897                                            in the chain and the DMA controller
898                                            will next access the first descriptor
899                                            in the chain. */
900 #define GEM_TX_DMA_RETRY_ERROR    BIT_29 /*!< @brief Retry limit exceeded, tx
901                                            error detected. */
902 #define GEM_TX_DMA_UNDERRUN       BIT_28 /*!< @brief Transmit underrun. This is
903                                            not used as the GEM DMA is configured
904                                            for packet buffer mode. */
905 #define GEM_TX_DMA_BUS_ERROR      BIT_27 /*!< @brief Transmit frame corruption
906                                            due to AHB/AXI error. */
907 #define GEM_TX_DMA_LATE_COL_ERROR BIT_26 /*!< @brief Late collision transmit
908                                            error detected. */
909 #define GEM_TX_DMA_TS_PRESENT     BIT_23 /*!< @brief This descriptor holds a
910                                            valid time stamp which indicates the
911                                            transmit time. */
912 #define GEM_TX_DMA_OFFLOAD_ERRORS (BITS_03 << 20) /*!< @brief Transmit
913                                                     IP/TCP/UDP checksum
914                                                     generation offload errors:
915                                                     See above for details. */
916 #define GEM_TX_DMA_NO_CRC         BIT_16 /*!< @brief If set, GEM assumes buffer
917                                            contains a CRC and does not calculate
918                                            and append one. */
919 #define GEM_TX_DMA_LAST           BIT_15 /*!< @brief When set indicates this is
920                                            the last buffer in a frame. */
921 #define GEM_TX_DMA_BUFF_LEN       BITS_14 /*!< @brief 14 bit buffer length. */
922 
923 /*******************************************************************************
924  * __Note:__ In the following definitions we use void * for the this_mac
925  * parameter as they are used in the definition of the _mss_mac_instance_t_
926  * structure and this confuses the compiler if we try to use the proper
927  * structure pointer in the definition of these function pointers...
928  */
929 
930 
931 /***************************************************************************//**
932  * Transmit DMA descriptor.
933  *
934  * This structure is used to configure the transmit descriptors for the DMA
935  * engine. The exact format depends on the _MSS_MAC_64_BIT_ADDRESS_MODE_ and
936  * _MSS_MAC_TIME_STAMPED_MODE_ macros and the driver only supports compile time
937  * configuration of the descriptor type.
938  */
939 typedef struct mss_mac_tx_desc mss_mac_tx_desc_t;
940 struct mss_mac_tx_desc
941 {
942     uint32_t          addr_low;     /*!< Buffer address low portion */
943     volatile uint32_t status;       /*!< Status and options for transmit operation */
944 #if defined(MSS_MAC_64_BIT_ADDRESS_MODE)
945     uint32_t          addr_high;    /*!< High portion of address in 64bit addressing mode */
946     uint32_t          unused;       /*!< Unused word in 64bit mode */
947 #endif
948 #if defined(MSS_MAC_TIME_STAMPED_MODE)
949     volatile uint32_t nano_seconds; /*!< Nanoseconds and LSBs of seconds for timestamp */
950     volatile uint32_t seconds;      /*!< MSBs of timestamp seconds */
951 #endif
952 };
953 
954 /***************************************************************************//**
955  * Receive DMA descriptor.
956  *
957  * This structure is used to configure the receive descriptors for the DMA
958  * engine. The exact format depends on the _MSS_MAC_64_BIT_ADDRESS_MODE_ and
959  * _MSS_MAC_TIME_STAMPED_MODE_ macros and the driver only supports compile time
960  * configuration of the descriptor type.
961  */
962 typedef struct mss_mac_rx_desc mss_mac_rx_desc_t;
963 struct mss_mac_rx_desc
964 {
965     uint32_t          addr_low;     /*!< Buffer address low portion */
966     volatile uint32_t status;       /*!< Status and options for transmit operation */
967 #if defined(MSS_MAC_64_BIT_ADDRESS_MODE)
968     uint32_t          addr_high;    /*!< High portion of address in 64bit addressing mode */
969     uint32_t          unused;       /*!< Unused word in 64bit mode */
970 #endif
971 #if defined(MSS_MAC_TIME_STAMPED_MODE)
972     volatile uint32_t nano_seconds; /*!< Nanoseconds and LSBs of seconds for timestamp */
973     volatile uint32_t seconds;      /*!< MSBs of timestamp seconds */
974 #endif
975 };
976 
977 /***************************************************************************//**
978  * Transmit callback function.
979  *
980  * This is the prototype for the user function which the MSS Ethernet MAC driver
981  * calls when a packet has been transmitted. The users function is responsible
982  * for processing any post transmit processing required for the packets.
983  *
984  *   - ___this_mac___    - pointer to global structure for the MAC in question.
985  *   - ___queue_no___    - 0 to 3 for pMAC and always 0 for eMAC.
986  *   - ___cdesc___       - pointer to the DMA descriptor associated with this
987  *                         packet.
988  *   - ___p_user_data___ - original user data pointer associated with the packet
989  *                         buffer.
990  */
991 typedef void (*mss_mac_transmit_callback_t)(/* mss_mac_instance_t*/ void *this_mac,
992                                        uint32_t queue_no,
993                                        mss_mac_tx_desc_t *cdesc,
994                                        void * p_user_data);
995 
996 /***************************************************************************//**
997  * Receive callback function.
998  *
999  * This is the prototype for the user function which the MSS Ethernet MAC driver
1000  * calls when a packet has been received. The users function is responsible for
1001  * processing any post receive processing required for the packets and for
1002  * returning the packet buffer to the receive chain so that further packets can
1003  * be received with this buffer.
1004  *
1005  *   - ___this_mac___    - pointer to global structure for the MAC in question.
1006  *   - ___queue_no___    - 0 to 3 for pMAC and always 0 for eMAC.
1007  *   - ___p_rx_packet___ - pointer to the buffer for the packet to be processed.
1008  *   - ___pckt_length___ - length of packet to be processed.
1009  *   - ___cdesc___       - pointer to the DMA descriptor associated with this
1010  *                         packet.
1011  *   - ___p_user_data___ - original user data pointer associated with the packet
1012  *                         buffer.
1013  */
1014 typedef void (*mss_mac_receive_callback_t)(/* mss_mac_instance_t*/ void *this_mac,
1015                                        uint32_t queue_no,
1016                                        uint8_t *p_rx_packet,
1017                                        uint32_t pckt_length,
1018                                        mss_mac_rx_desc_t *cdesc,
1019                                        void *p_user_data);
1020 
1021 /***************************************************************************//**
1022  * TSU timer time value.
1023  *
1024  * This structure represents the time value from the TSU and is used with the
1025  * _MSS_MAC_read_TSU() function_.
1026  */
1027 typedef struct mss_mac_tsu_time mss_mac_tsu_time_t;
1028 struct mss_mac_tsu_time
1029 {
1030     uint32_t secs_msb;        /*!< Most significant bits of seconds count */
1031     uint32_t secs_lsb;        /*!< Least significant bits of seconds count */
1032     uint32_t nanoseconds;     /*!< Nanoseconds count */
1033 };
1034 
1035 
1036 /***************************************************************************//**
1037  * TSU configuration structure.
1038  *
1039  * This structure is used with the _MSS_MAC_init_TSU()_ function to configure
1040  * the initial count value and increment values for the TSU. The driver
1041  * configures the timer to operate in Increment Mode.
1042  */
1043 typedef struct mss_mac_tsu_config mss_mac_tsu_config_t;
1044 struct mss_mac_tsu_config
1045 {
1046     /* initial values */
1047     uint32_t secs_msb;        /*!< Most significant bits of seconds count */
1048     uint32_t secs_lsb;        /*!< Least significant bits of seconds count */
1049     uint32_t nanoseconds;     /*!< Nanoseconds count  */
1050 
1051     /* Per TSU tick values */
1052     uint32_t ns_inc;          /*!< Nanoseconds TSU increment value */
1053     uint32_t sub_ns_inc;      /*!< Sub-nanoseconds TSU increment value */
1054 };
1055 
1056 
1057 /***************************************************************************//**
1058  * Type 1 filter structure.
1059  *
1060  * This structure is used to configure Type 1 Screening Filters which allow
1061  * routing or dropping of packets based on a UDP port number and the
1062  * differentiated services/traffic class field.
1063  *
1064  * The match results are ANDed together which means all enabled filters must
1065  * match for a successful match. Packets can either be dropped or sent to the
1066  * indicated queue on a match.
1067  *
1068  * Both the eMAC and pMAC support 4 Type 1 Screening Filters
1069  */
1070 typedef struct mss_mac_type_1_filter mss_mac_type_1_filter_t;
1071 struct mss_mac_type_1_filter
1072 {
1073     uint16_t udp_port;        /*!< UDP port number to match */
1074     uint8_t  dstc;            /*!< Designated Services/Traffic Class value to match */
1075     uint8_t  queue_no;        /*!< Queue to send to on match */
1076     uint8_t  drop_on_match;   /*!< Drop packet instead of routing to queue */
1077     uint8_t  dstc_enable;     /*!< Enable DS/TC matching */
1078     uint8_t  udp_port_enable; /*!< Enable UDP port matching */
1079 };
1080 
1081 /***************************************************************************//**
1082  * Type 2 filter structure.
1083  *
1084  * This structure is used to configure Type 2 Screening Filters which allow
1085  * routing or dropping of packets based on Ethertype field values, VLAN priority
1086  * and arbitrary packet data patterns.
1087  *
1088  * Ethertype matching is perfromed using a combination of a Type 2 Filter and
1089  * and an Ethertype screening register.
1090  *
1091  * Arbitrary data matching is perfromed using a combination of a Type 2 Filter
1092  * and between 1 and 3 Type 2 Comparer blocks.
1093  *
1094  * The match results are ANDed together which means all enabled filters must
1095  * match for a successful match. Packets can either be dropped or sent to the
1096  * indicated queue on a match.
1097  *
1098  * The eMAC supports 2 Type 2 Screening Filters and the pMAC supports 4.
1099  */
1100 typedef struct mss_mac_type_2_filter mss_mac_type_2_filter_t;
1101 struct mss_mac_type_2_filter
1102 {
1103     uint8_t  ethertype_enable;     /*!< Enable Ethertype matching */
1104     uint8_t  ethertype_index;      /*!< Which Ethertype compare block to use */
1105     uint8_t  vlan_priority_enable; /*!< Enable VLAN priority matching */
1106     uint8_t  vlan_priority;        /*!< VLAN priority level to use. */
1107     uint8_t  drop_on_match;        /*!< Drop packet instead of routing to queue */
1108     uint8_t  compare_a_enable;     /*!< Enable data comparer A */
1109     uint8_t  compare_a_index;      /*!< Index to data comparator to use for A */
1110     uint8_t  compare_b_enable;     /*!< Enable data comparer B */
1111     uint8_t  compare_b_index;      /*!< Index to data comparator to use for B */
1112     uint8_t  compare_c_enable;     /*!< Enable data comparer C */
1113     uint8_t  compare_c_index;      /*!< Index to data comparator to use for C */
1114     uint8_t  queue_no;             /*!< The queue to route packet to on match */
1115 };
1116 
1117 /***************************************************************************//**
1118  * Type 2 filter comparer structures.
1119  *
1120  * This structure is used to configure Type 2 Screening Filter data comparers
1121  * which allow filtering on arbitrary packet data patterns. Alternatively the
1122  * comparer can be configured to match a normal or stacked VLAN tag.
1123  *
1124  * For data comparision, the user can select between a straight 32 bit compare
1125  * operation and a 16 bit compare operation with a 16 bit mask value. When the
1126  * masked compare is used, the mask value is used to determine which bits are
1127  * included in the match - a value of zero in a mask bit masks the corresponding
1128  * data bit, a value of 1 enables the comparison.
1129  *
1130  * For data compare operations, b0-b7 correspond to the byte at the offset,
1131  * b8-b15 correspond to the byte at offset + 1 and so on.
1132  *
1133  * If either compare_vlan_c_id or compare_vlan_s_id is set then the data value
1134  * represents the VLAN tag. __Note:__ The byte order is such that if 81 00 00 20
1135  * is received to indicate a C-TAG frame with VID 020 0x00200FFF would be
1136  * written to the compare register. So in the special case of VLAN comparison
1137  * the last byte received is the least significant byte in the compare register
1138  *
1139  * The eMAC supports 6 Type 2 comparers and the pMAC supports 12.
1140  */
1141 typedef struct mss_mac_type_2_compare mss_mac_type_2_compare_t;
1142 struct mss_mac_type_2_compare
1143 {
1144     uint32_t data;              /*!< 32 bits of data or 16 bits of data */
1145     uint16_t mask;              /*!< 16 bit mask if data is 16 bit */
1146     uint8_t  disable_mask;      /*!< True to select raw 32 bit data match */
1147     uint8_t  compare_vlan_c_id; /*!< Compare VLAN C tag - higher precedence than S tag */
1148     uint8_t  compare_vlan_s_id; /*!< Compare VLAN S tag */
1149     uint8_t  compare_offset;    /*!< Offset type - see MSS_MAC_OFFSET_* definitions */
1150     uint8_t  offset_value;      /*!< Offset value */
1151 };
1152 
1153 /***************************************************************************//**
1154  * Media Merge Sublayer configuration structure.
1155  *
1156  * This structure is used to configure the operation of the MMSL via the
1157  * _MSS_MAC_set_mmsl_mode()_ function and retrieve the current settings via the
1158  * _MSS_MAC_get_mmsl_mode()_ function.
1159  *
1160  * The default operation mode on reset, is no pre-emption and all receive
1161  * traffic routed to the pMAC.
1162  *
1163  * If verify_disable is true then the link will switch to pre-emption without
1164  * negotitation of capabilities with the link partner when preemption is set to
1165  * true.
1166  */
1167 typedef struct mss_mac_mmsl_config mss_mac_mmsl_config_t;
1168 struct mss_mac_mmsl_config
1169 {
1170     mss_mac_frag_size_t frag_size; /*!< See  mss_mac_frag_size_t for details */
1171     uint8_t preemption;            /*!< Enable preemption */
1172     uint8_t verify_disable;        /*!< Set true to force preemption without testing link */
1173     uint8_t use_pmac;              /*!< Receive all to pMAC if not preempting */
1174 };
1175 
1176 /***************************************************************************//**
1177  * Media Merge Sublayer statistics structure.
1178  *
1179  * This structure is used to return the MMSL statistics counts via the
1180  * _MSS_MAC_get_mmsl_stats()_ function.
1181  *
1182  * __Note:__ These values are actually a mix of 8 and 17 bits but we return them
1183  * all as 32 bits to simplify collecting the stats.
1184  *
1185  * These registers are cleared when read so in order to maintain a proper
1186  * running total, the software should maintain counts which are updated by
1187  * adding the values each time a statistic count is read.
1188  *
1189  * Counts do not roll over when the maximum is reached so a reading of 2^n - 1
1190  * indicates that at least that many of the indicated event have occurred since
1191  * the last read.
1192  */
1193 
1194 typedef struct mss_mac_mmsl_stats mss_mac_mmsl_stats_t;
1195 
1196 struct mss_mac_mmsl_stats
1197 {
1198     uint32_t smd_err_count; /*!< 8 bit count of unknown SMD values received */
1199     uint32_t ass_err_count; /*!< 8 bit count of frames with reassembly errors */
1200     uint32_t ass_ok_count;  /*!< 17 bit count of frames reassembled ok */
1201     uint32_t frag_count_rx; /*!< 17 bit count of mPackets received */
1202     uint32_t frag_count_tx; /*!< 17 bit count of mPackets sent */
1203 };
1204 
1205 
1206 /***************************************************************************//**
1207  * Multi packet transmit structure
1208  *
1209  * This structure is used with the _MSS_MAC_send_pkts()_ function to define the
1210  * list of packets to tranjsmit. The application is responsible for allocating
1211  * the list and populating it with the details for each packet.
1212  *
1213  * To send n packets, the list needs to contain n+1 entries with the last entry
1214  * having a 0 length and a null pointer for the packet data buffer address.
1215  */
1216 typedef struct mss_mac_tx_pkt_info mss_mac_tx_pkt_info_t;
1217 
1218 struct mss_mac_tx_pkt_info
1219 {
1220     uint32_t  queue_no;    /*!< Queue number for this packet */
1221     uint32_t  length;      /*!< Length of this packet - 0 for end of list */
1222     uint8_t  *tx_buffer;   /*!< Pointer to packet data - 0 for end of list */
1223     void     *p_user_data; /*!< Pointer to user data for this packet */
1224 };
1225 
1226 
1227 /***************************************************************************//**
1228  * Per queue specific info for device management structure.
1229  *
1230  * This structure instantiates the queue specific information for managing the
1231  * MSS Ethernet MAC driver.
1232  */
1233 typedef struct mss_mac_queue
1234 {
1235 #if defined(MSS_MAC_USE_DDR)
1236     mss_mac_tx_desc_t            *tx_desc_tab;  /*!< Transmit descriptor table */
1237 #else
1238     mss_mac_tx_desc_t            tx_desc_tab[MSS_MAC_TX_RING_SIZE];  /*!< Transmit descriptor table */
1239 #endif
1240 
1241 #if defined(MSS_MAC_USE_DDR)
1242     mss_mac_rx_desc_t            *rx_desc_tab;  /*!< Receive descriptor table */
1243 #else
1244     mss_mac_rx_desc_t            rx_desc_tab[MSS_MAC_RX_RING_SIZE];  /*!< Receive descriptor table */
1245 #endif
1246     void                        *tx_caller_info[MSS_MAC_TX_RING_SIZE]; /*!< Pointers to tx user specific data */
1247     void                        *rx_caller_info[MSS_MAC_RX_RING_SIZE]; /*!< Pointers to rx user specific data */
1248     mss_mac_transmit_callback_t  pckt_tx_callback; /*!< Pointer to transmit handler call back function */
1249     mss_mac_receive_callback_t   pckt_rx_callback; /*!< Pointer to receive handler call back function */
1250     volatile uint32_t            nb_available_tx_desc; /*!< Number of free TX descriptors available */
1251     volatile uint32_t            current_tx_desc; /*!< Oldest in the queue... */
1252     volatile uint32_t            nb_available_rx_desc; /*!< Number of free RX descriptors available */
1253     volatile uint32_t            next_free_rx_desc_index; /*!< Next RX descriptor to allocate */
1254     volatile uint32_t            first_rx_desc_index; /*!< Descriptor to process next when receive handler called */
1255     uint32_t                     rx_discard; /*!< If set, silently discard incoming packets */
1256     uint32_t                     overflow_counter; /*!< Overflows since last normal receive operation */
1257     uint32_t                     tries;  /*!< Keeps track of failure to sends... */
1258     volatile int32_t             in_isr; /*!< Set when processing ISR so functions don't call PLIC enable/disable for protection */
1259 
1260     /* Queue specific register addresses to simplify the driver code */
1261     volatile uint32_t           *int_status;        /*!< interrupt status */
1262     volatile uint32_t           *int_mask;          /*!< interrupt mask */
1263     volatile uint32_t           *int_enable;        /*!< interrupt enable */
1264     volatile uint32_t           *int_disable;       /*!< interrupt disable */
1265     volatile uint32_t           *receive_q_ptr;     /*!< RX queue pointer */
1266     volatile uint32_t           *transmit_q_ptr;    /*!< TX queue pointer */
1267     volatile uint32_t           *dma_rxbuf_size;    /*!< RX queue buffer size */
1268 
1269     /* Statistics counters */
1270 
1271     volatile uint64_t ingress; /*!< Count of bytes received on this queue */
1272     volatile uint64_t egress; /*!< Count of bytes transmitted on this queue */
1273     volatile uint64_t rx_overflow; /*!< Number of receive overflow events on this queue */
1274     volatile uint64_t hresp_error; /*!< Number of receive hresp error events on this queue*/
1275     volatile uint64_t rx_restart; /*!< Number of times reception has been restarted on this queue */
1276     volatile uint64_t tx_amba_errors; /*!< Number of receive amba error events on this queue */
1277     volatile uint64_t tx_restart; /*!< Number of times transmission has been restarted on this queue */
1278     volatile uint64_t tx_reenable; /*!< Number of times transmission has been reenabled on this queue */
1279 } mss_mac_queue_t;
1280 
1281 
1282 /***************************************************************************//**
1283  * G5SoC Ethernet MAC instance
1284  * A local record of this type will be created and maintained by the driver for
1285  * each pMAC and eMAC.
1286  */
1287 typedef struct mss_mac_instance
1288 {
1289     uint32_t          is_emac;    /*!< 0 for primary MAC and non zero for eMAC */
1290     MAC_TypeDef       *mac_base;  /*!< Register start address - _NULL_ if eMAC */
1291     eMAC_TypeDef      *emac_base; /*!< Register start address - _NULL_ if primary MAC */
1292     PLIC_IRQn_Type    mac_q_int[MSS_MAC_QUEUE_COUNT]; /*!< Interrupt numbers for each queue */
1293 #if defined(TARGET_G5_SOC)
1294     PLIC_IRQn_Type    mmsl_int; /*!< interrupt number for MMSL interrupt */
1295 #endif
1296 
1297     mss_mac_queue_t   queue[MSS_MAC_QUEUE_COUNT]; /*!< Queue specific information */
1298 
1299     volatile uint64_t tx_pause; /*!< Count of pause frames sent */
1300     volatile uint64_t rx_pause; /*!< Count of pause frames received */
1301     volatile uint64_t pause_elapsed; /*!< Count of pause frame elapsed events */
1302 
1303     uint32_t          rx_discard; /*!< Flag for discarding all received data */
1304     volatile uint32_t mac_available; /*!< Flag to show init is done and MAC and PHY can be used */
1305 
1306     /* These are set from the cfg structure */
1307 
1308     uint32_t jumbo_frame_enable;        /*!< Enable / disable jumbo frame support: */
1309     uint32_t append_CRC;                /*!< Enable / disable GEM CRC calculation */
1310     uint32_t interface_type;            /*!< Type of network interface associated with this GEM */
1311     uint32_t phy_type;                  /*!< PHY device type associated with this GEM */
1312     uint32_t phy_addr;                  /*!< Address of Ethernet PHY on MII management interface. */
1313     uint32_t pcs_phy_addr;              /*!< Address of SGMII interface controller on MII management interface. */
1314 #if defined(MSS_MAC_PHY_HW_RESET) || defined(MSS_MAC_PHY_HW_SRESET)
1315 
1316     GPIO_TypeDef  *phy_soft_reset_gpio; /*!< GPIO device soft reset for PHY is connected to */
1317     mss_gpio_id_t  phy_soft_reset_pin;  /*!< GPIO pin soft reset for PHY is connected to */
1318     uint32_t       phy_soft_reset_done; /*!< Flag to indicate soft reset is done so multi-port devices
1319                                          *   can avoid additional resets - set by phy driver */
1320     GPIO_TypeDef  *phy_hard_reset_gpio; /*!< GPIO device hard reset for PHY is connected to */
1321     mss_gpio_id_t  phy_hard_reset_pin;  /*!< GPIO pin hard reset for PHY is connected to */
1322     uint32_t       phy_hard_reset_done; /*!< Flag to indicate hard reset is done so multi-port devices
1323                                          *   can avoid additional resets - set by phy driver */
1324 #endif
1325     /* Use struct instead of typedef as compiler gets confused otherwise... */
1326     struct mss_mac_instance *phy_controller; /*!< Which MAC structure PHY is connected to */
1327     uint32_t use_hi_address;            /*!< Non 0 means use upper address range for this device */
1328     uint32_t use_local_ints;            /*!< non 0 meams use local interrupts for MAC instead of PLIC */
1329     uint8_t  mac_addr[6];               /*!< Station's MAC address */
1330     mss_mac_speed_mode_t speed_mode;    /*!< Link speed mode of operation */
1331     uint32_t speed_duplex_select;       /*!< Link speed and duplex mode allowed to setup a link when autonegotiation is enabled. */
1332 
1333     /* PHY interface functions */
1334     mss_mac_phy_init_t            phy_init;              /*!< Pointer to PHY init function */
1335     mss_mac_phy_set_speed_t       phy_set_link_speed;    /*!< Pointer to PHY set link speed function */
1336     mss_mac_phy_autonegotiate_t   phy_autonegotiate;     /*!< Pointer to PHY autonegotiate function */
1337     mss_mac_phy_autonegotiate_t   phy_mac_autonegotiate; /*!< Pointer to PHY MAC link autonegotiate function */
1338     mss_mac_phy_get_link_status_t phy_get_link_status;   /*!< Pointer to PHY get link status function */
1339 #if MSS_MAC_USE_PHY_DP83867
1340     mss_mac_phy_extended_read_t   phy_extended_read;     /*!< Pointer to PHY extended read function */
1341     mss_mac_phy_extended_write_t  phy_extended_write;    /*!< Pointer to PHY extended write function */
1342 #endif
1343 
1344 } mss_mac_instance_t;
1345 
1346 /***************************************************************************//**
1347  * Flag value to indicate this MAC has been set up and is safe to call functions
1348  */
1349 #define MSS_MAC_AVAILABLE (0XAAF1D055U)
1350 
1351 #ifdef __cplusplus
1352 }
1353 #endif
1354 
1355 #endif /* MSS_ETHERNET_MAC_TYPES_H_ */
1356