1 /** 2 * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 /** Group: Configuration Register */ 14 /** Type of uart0_conf register 15 * UART0 configuration register 16 */ 17 typedef union { 18 struct { 19 /** uart0_clk_en : R/W; bitpos: [0]; default: 1; 20 * Set 1 to enable uart0 apb clock 21 */ 22 uint32_t uart0_clk_en:1; 23 /** uart0_rst_en : R/W; bitpos: [1]; default: 0; 24 * Set 0 to reset uart0 module 25 */ 26 uint32_t uart0_rst_en:1; 27 uint32_t reserved_2:30; 28 }; 29 uint32_t val; 30 } pcr_uart0_conf_reg_t; 31 32 /** Type of uart0_sclk_conf register 33 * UART0_SCLK configuration register 34 */ 35 typedef union { 36 struct { 37 /** uart0_sclk_div_a : R/W; bitpos: [5:0]; default: 0; 38 * The denominator of the frequency divider factor of the uart0 function clock. 39 */ 40 uint32_t uart0_sclk_div_a:6; 41 /** uart0_sclk_div_b : R/W; bitpos: [11:6]; default: 0; 42 * The numerator of the frequency divider factor of the uart0 function clock. 43 */ 44 uint32_t uart0_sclk_div_b:6; 45 /** uart0_sclk_div_num : R/W; bitpos: [19:12]; default: 0; 46 * The integral part of the frequency divider factor of the uart0 function clock. 47 */ 48 uint32_t uart0_sclk_div_num:8; 49 /** uart0_sclk_sel : R/W; bitpos: [21:20]; default: 3; 50 * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: 51 * FOSC, 3(default): XTAL. 52 */ 53 uint32_t uart0_sclk_sel:2; 54 /** uart0_sclk_en : R/W; bitpos: [22]; default: 1; 55 * Set 1 to enable uart0 function clock 56 */ 57 uint32_t uart0_sclk_en:1; 58 uint32_t reserved_23:9; 59 }; 60 uint32_t val; 61 } pcr_uart0_sclk_conf_reg_t; 62 63 /** Type of uart0_pd_ctrl register 64 * UART0 power control register 65 */ 66 typedef union { 67 struct { 68 uint32_t reserved_0:1; 69 /** uart0_mem_force_pu : R/W; bitpos: [1]; default: 1; 70 * Set this bit to force power down UART0 memory. 71 */ 72 uint32_t uart0_mem_force_pu:1; 73 /** uart0_mem_force_pd : R/W; bitpos: [2]; default: 0; 74 * Set this bit to force power up UART0 memory. 75 */ 76 uint32_t uart0_mem_force_pd:1; 77 uint32_t reserved_3:29; 78 }; 79 uint32_t val; 80 } pcr_uart0_pd_ctrl_reg_t; 81 82 /** Type of uart1_conf register 83 * UART1 configuration register 84 */ 85 typedef union { 86 struct { 87 /** uart1_clk_en : R/W; bitpos: [0]; default: 1; 88 * Set 1 to enable uart1 apb clock 89 */ 90 uint32_t uart1_clk_en:1; 91 /** uart1_rst_en : R/W; bitpos: [1]; default: 0; 92 * Set 0 to reset uart1 module 93 */ 94 uint32_t uart1_rst_en:1; 95 uint32_t reserved_2:30; 96 }; 97 uint32_t val; 98 } pcr_uart1_conf_reg_t; 99 100 /** Type of uart1_sclk_conf register 101 * UART1_SCLK configuration register 102 */ 103 typedef union { 104 struct { 105 /** uart1_sclk_div_a : R/W; bitpos: [5:0]; default: 0; 106 * The denominator of the frequency divider factor of the uart1 function clock. 107 */ 108 uint32_t uart1_sclk_div_a:6; 109 /** uart1_sclk_div_b : R/W; bitpos: [11:6]; default: 0; 110 * The numerator of the frequency divider factor of the uart1 function clock. 111 */ 112 uint32_t uart1_sclk_div_b:6; 113 /** uart1_sclk_div_num : R/W; bitpos: [19:12]; default: 0; 114 * The integral part of the frequency divider factor of the uart1 function clock. 115 */ 116 uint32_t uart1_sclk_div_num:8; 117 /** uart1_sclk_sel : R/W; bitpos: [21:20]; default: 3; 118 * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: 119 * FOSC, 3(default): XTAL. 120 */ 121 uint32_t uart1_sclk_sel:2; 122 /** uart1_sclk_en : R/W; bitpos: [22]; default: 1; 123 * Set 1 to enable uart0 function clock 124 */ 125 uint32_t uart1_sclk_en:1; 126 uint32_t reserved_23:9; 127 }; 128 uint32_t val; 129 } pcr_uart1_sclk_conf_reg_t; 130 131 /** Type of uart1_pd_ctrl register 132 * UART1 power control register 133 */ 134 typedef union { 135 struct { 136 uint32_t reserved_0:1; 137 /** uart1_mem_force_pu : R/W; bitpos: [1]; default: 1; 138 * Set this bit to force power down UART1 memory. 139 */ 140 uint32_t uart1_mem_force_pu:1; 141 /** uart1_mem_force_pd : R/W; bitpos: [2]; default: 0; 142 * Set this bit to force power up UART1 memory. 143 */ 144 uint32_t uart1_mem_force_pd:1; 145 uint32_t reserved_3:29; 146 }; 147 uint32_t val; 148 } pcr_uart1_pd_ctrl_reg_t; 149 150 /** Type of mspi_conf register 151 * MSPI configuration register 152 */ 153 typedef union { 154 struct { 155 /** mspi_clk_en : R/W; bitpos: [0]; default: 1; 156 * Set 1 to enable mspi clock, include mspi pll clock 157 */ 158 uint32_t mspi_clk_en:1; 159 /** mspi_rst_en : R/W; bitpos: [1]; default: 0; 160 * Set 0 to reset mspi module 161 */ 162 uint32_t mspi_rst_en:1; 163 /** mspi_pll_clk_en : R/W; bitpos: [2]; default: 1; 164 * Set 1 to enable mspi pll clock 165 */ 166 uint32_t mspi_pll_clk_en:1; 167 uint32_t reserved_3:29; 168 }; 169 uint32_t val; 170 } pcr_mspi_conf_reg_t; 171 172 /** Type of mspi_clk_conf register 173 * MSPI_CLK configuration register 174 */ 175 typedef union { 176 struct { 177 /** mspi_fast_ls_div_num : R/W; bitpos: [7:0]; default: 0; 178 * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed 179 * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a 180 * low-speed clock-source such as XTAL/FOSC. 181 */ 182 uint32_t mspi_fast_ls_div_num:8; 183 /** mspi_fast_hs_div_num : R/W; bitpos: [15:8]; default: 3; 184 * Set as one within (3,4,5) to generate div4(default)/div5/div6 of high-speed 185 * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a 186 * high-speed clock-source such as SPLL. 187 */ 188 uint32_t mspi_fast_hs_div_num:8; 189 uint32_t reserved_16:16; 190 }; 191 uint32_t val; 192 } pcr_mspi_clk_conf_reg_t; 193 194 /** Type of i2c_conf register 195 * I2C configuration register 196 */ 197 typedef union { 198 struct { 199 /** i2c_clk_en : R/W; bitpos: [0]; default: 1; 200 * Set 1 to enable i2c apb clock 201 */ 202 uint32_t i2c_clk_en:1; 203 /** i2c_rst_en : R/W; bitpos: [1]; default: 0; 204 * Set 0 to reset i2c module 205 */ 206 uint32_t i2c_rst_en:1; 207 uint32_t reserved_2:30; 208 }; 209 uint32_t val; 210 } pcr_i2c_conf_reg_t; 211 212 /** Type of i2c_sclk_conf register 213 * I2C_SCLK configuration register 214 */ 215 typedef union { 216 struct { 217 /** i2c_sclk_div_a : R/W; bitpos: [5:0]; default: 0; 218 * The denominator of the frequency divider factor of the i2c function clock. 219 */ 220 uint32_t i2c_sclk_div_a:6; 221 /** i2c_sclk_div_b : R/W; bitpos: [11:6]; default: 0; 222 * The numerator of the frequency divider factor of the i2c function clock. 223 */ 224 uint32_t i2c_sclk_div_b:6; 225 /** i2c_sclk_div_num : R/W; bitpos: [19:12]; default: 0; 226 * The integral part of the frequency divider factor of the i2c function clock. 227 */ 228 uint32_t i2c_sclk_div_num:8; 229 /** i2c_sclk_sel : R/W; bitpos: [20]; default: 0; 230 * set this field to select clock-source. 0(default): XTAL, 1: FOSC. 231 */ 232 uint32_t i2c_sclk_sel:1; 233 uint32_t reserved_21:1; 234 /** i2c_sclk_en : R/W; bitpos: [22]; default: 1; 235 * Set 1 to enable i2c function clock 236 */ 237 uint32_t i2c_sclk_en:1; 238 uint32_t reserved_23:9; 239 }; 240 uint32_t val; 241 } pcr_i2c_sclk_conf_reg_t; 242 243 /** Type of uhci_conf register 244 * UHCI configuration register 245 */ 246 typedef union { 247 struct { 248 /** uhci_clk_en : R/W; bitpos: [0]; default: 1; 249 * Set 1 to enable uhci clock 250 */ 251 uint32_t uhci_clk_en:1; 252 /** uhci_rst_en : R/W; bitpos: [1]; default: 0; 253 * Set 0 to reset uhci module 254 */ 255 uint32_t uhci_rst_en:1; 256 uint32_t reserved_2:30; 257 }; 258 uint32_t val; 259 } pcr_uhci_conf_reg_t; 260 261 /** Type of rmt_conf register 262 * RMT configuration register 263 */ 264 typedef union { 265 struct { 266 /** rmt_clk_en : R/W; bitpos: [0]; default: 1; 267 * Set 1 to enable rmt apb clock 268 */ 269 uint32_t rmt_clk_en:1; 270 /** rmt_rst_en : R/W; bitpos: [1]; default: 0; 271 * Set 0 to reset rmt module 272 */ 273 uint32_t rmt_rst_en:1; 274 uint32_t reserved_2:30; 275 }; 276 uint32_t val; 277 } pcr_rmt_conf_reg_t; 278 279 /** Type of rmt_sclk_conf register 280 * RMT_SCLK configuration register 281 */ 282 typedef union { 283 struct { 284 /** rmt_sclk_div_a : R/W; bitpos: [5:0]; default: 0; 285 * The denominator of the frequency divider factor of the rmt function clock. 286 */ 287 uint32_t rmt_sclk_div_a:6; 288 /** rmt_sclk_div_b : R/W; bitpos: [11:6]; default: 0; 289 * The numerator of the frequency divider factor of the rmt function clock. 290 */ 291 uint32_t rmt_sclk_div_b:6; 292 /** rmt_sclk_div_num : R/W; bitpos: [19:12]; default: 1; 293 * The integral part of the frequency divider factor of the rmt function clock. 294 */ 295 uint32_t rmt_sclk_div_num:8; 296 /** rmt_sclk_sel : R/W; bitpos: [21:20]; default: 1; 297 * set this field to select clock-source. 0: do not select anyone clock, 1(default): 298 * 80MHz, 2: FOSC, 3: XTAL. 299 */ 300 uint32_t rmt_sclk_sel:2; 301 /** rmt_sclk_en : R/W; bitpos: [22]; default: 1; 302 * Set 1 to enable rmt function clock 303 */ 304 uint32_t rmt_sclk_en:1; 305 uint32_t reserved_23:9; 306 }; 307 uint32_t val; 308 } pcr_rmt_sclk_conf_reg_t; 309 310 /** Type of ledc_conf register 311 * LEDC configuration register 312 */ 313 typedef union { 314 struct { 315 /** ledc_clk_en : R/W; bitpos: [0]; default: 1; 316 * Set 1 to enable ledc apb clock 317 */ 318 uint32_t ledc_clk_en:1; 319 /** ledc_rst_en : R/W; bitpos: [1]; default: 0; 320 * Set 0 to reset ledc module 321 */ 322 uint32_t ledc_rst_en:1; 323 uint32_t reserved_2:30; 324 }; 325 uint32_t val; 326 } pcr_ledc_conf_reg_t; 327 328 /** Type of ledc_sclk_conf register 329 * LEDC_SCLK configuration register 330 */ 331 typedef union { 332 struct { 333 uint32_t reserved_0:20; 334 /** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0; 335 * set this field to select clock-source. 0(default): do not select anyone clock, 1: 336 * 80MHz, 2: FOSC, 3: XTAL. 337 */ 338 uint32_t ledc_sclk_sel:2; 339 /** ledc_sclk_en : R/W; bitpos: [22]; default: 1; 340 * Set 1 to enable ledc function clock 341 */ 342 uint32_t ledc_sclk_en:1; 343 uint32_t reserved_23:9; 344 }; 345 uint32_t val; 346 } pcr_ledc_sclk_conf_reg_t; 347 348 /** Type of timergroup0_conf register 349 * TIMERGROUP0 configuration register 350 */ 351 typedef union { 352 struct { 353 /** tg0_clk_en : R/W; bitpos: [0]; default: 1; 354 * Set 1 to enable timer_group0 apb clock 355 */ 356 uint32_t tg0_clk_en:1; 357 /** tg0_rst_en : R/W; bitpos: [1]; default: 0; 358 * Set 0 to reset timer_group0 module 359 */ 360 uint32_t tg0_rst_en:1; 361 uint32_t reserved_2:30; 362 }; 363 uint32_t val; 364 } pcr_timergroup0_conf_reg_t; 365 366 /** Type of timergroup0_timer_clk_conf register 367 * TIMERGROUP0_TIMER_CLK configuration register 368 */ 369 typedef union { 370 struct { 371 uint32_t reserved_0:20; 372 /** tg0_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; 373 * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: 374 * reserved. 375 */ 376 uint32_t tg0_timer_clk_sel:2; 377 /** tg0_timer_clk_en : R/W; bitpos: [22]; default: 1; 378 * Set 1 to enable timer_group0 timer clock 379 */ 380 uint32_t tg0_timer_clk_en:1; 381 uint32_t reserved_23:9; 382 }; 383 uint32_t val; 384 } pcr_timergroup0_timer_clk_conf_reg_t; 385 386 /** Type of timergroup0_wdt_clk_conf register 387 * TIMERGROUP0_WDT_CLK configuration register 388 */ 389 typedef union { 390 struct { 391 uint32_t reserved_0:20; 392 /** tg0_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; 393 * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: 394 * reserved. 395 */ 396 uint32_t tg0_wdt_clk_sel:2; 397 /** tg0_wdt_clk_en : R/W; bitpos: [22]; default: 1; 398 * Set 1 to enable timer_group0 wdt clock 399 */ 400 uint32_t tg0_wdt_clk_en:1; 401 uint32_t reserved_23:9; 402 }; 403 uint32_t val; 404 } pcr_timergroup0_wdt_clk_conf_reg_t; 405 406 /** Type of timergroup1_conf register 407 * TIMERGROUP1 configuration register 408 */ 409 typedef union { 410 struct { 411 /** tg1_clk_en : R/W; bitpos: [0]; default: 1; 412 * Set 1 to enable timer_group1 apb clock 413 */ 414 uint32_t tg1_clk_en:1; 415 /** tg1_rst_en : R/W; bitpos: [1]; default: 0; 416 * Set 0 to reset timer_group1 module 417 */ 418 uint32_t tg1_rst_en:1; 419 uint32_t reserved_2:30; 420 }; 421 uint32_t val; 422 } pcr_timergroup1_conf_reg_t; 423 424 /** Type of timergroup1_timer_clk_conf register 425 * TIMERGROUP1_TIMER_CLK configuration register 426 */ 427 typedef union { 428 struct { 429 uint32_t reserved_0:20; 430 /** tg1_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; 431 * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: 432 * reserved. 433 */ 434 uint32_t tg1_timer_clk_sel:2; 435 /** tg1_timer_clk_en : R/W; bitpos: [22]; default: 1; 436 * Set 1 to enable timer_group1 timer clock 437 */ 438 uint32_t tg1_timer_clk_en:1; 439 uint32_t reserved_23:9; 440 }; 441 uint32_t val; 442 } pcr_timergroup1_timer_clk_conf_reg_t; 443 444 /** Type of timergroup1_wdt_clk_conf register 445 * TIMERGROUP1_WDT_CLK configuration register 446 */ 447 typedef union { 448 struct { 449 uint32_t reserved_0:20; 450 /** tg1_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; 451 * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: 452 * reserved. 453 */ 454 uint32_t tg1_wdt_clk_sel:2; 455 /** tg1_wdt_clk_en : R/W; bitpos: [22]; default: 1; 456 * Set 1 to enable timer_group0 wdt clock 457 */ 458 uint32_t tg1_wdt_clk_en:1; 459 uint32_t reserved_23:9; 460 }; 461 uint32_t val; 462 } pcr_timergroup1_wdt_clk_conf_reg_t; 463 464 /** Type of systimer_conf register 465 * SYSTIMER configuration register 466 */ 467 typedef union { 468 struct { 469 /** systimer_clk_en : R/W; bitpos: [0]; default: 1; 470 * Set 1 to enable systimer apb clock 471 */ 472 uint32_t systimer_clk_en:1; 473 /** systimer_rst_en : R/W; bitpos: [1]; default: 0; 474 * Set 0 to reset systimer module 475 */ 476 uint32_t systimer_rst_en:1; 477 uint32_t reserved_2:30; 478 }; 479 uint32_t val; 480 } pcr_systimer_conf_reg_t; 481 482 /** Type of systimer_func_clk_conf register 483 * SYSTIMER_FUNC_CLK configuration register 484 */ 485 typedef union { 486 struct { 487 uint32_t reserved_0:20; 488 /** systimer_func_clk_sel : R/W; bitpos: [20]; default: 0; 489 * set this field to select clock-source. 0(default): XTAL, 1: FOSC. 490 */ 491 uint32_t systimer_func_clk_sel:1; 492 uint32_t reserved_21:1; 493 /** systimer_func_clk_en : R/W; bitpos: [22]; default: 1; 494 * Set 1 to enable systimer function clock 495 */ 496 uint32_t systimer_func_clk_en:1; 497 uint32_t reserved_23:9; 498 }; 499 uint32_t val; 500 } pcr_systimer_func_clk_conf_reg_t; 501 502 /** Type of twai0_conf register 503 * TWAI0 configuration register 504 */ 505 typedef union { 506 struct { 507 /** twai0_clk_en : R/W; bitpos: [0]; default: 1; 508 * Set 1 to enable twai0 apb clock 509 */ 510 uint32_t twai0_clk_en:1; 511 /** twai0_rst_en : R/W; bitpos: [1]; default: 0; 512 * Set 0 to reset twai0 module 513 */ 514 uint32_t twai0_rst_en:1; 515 uint32_t reserved_2:30; 516 }; 517 uint32_t val; 518 } pcr_twai0_conf_reg_t; 519 520 /** Type of twai0_func_clk_conf register 521 * TWAI0_FUNC_CLK configuration register 522 */ 523 typedef union { 524 struct { 525 uint32_t reserved_0:20; 526 /** twai0_func_clk_sel : R/W; bitpos: [20]; default: 0; 527 * set this field to select clock-source. 0(default): XTAL, 1: FOSC. 528 */ 529 uint32_t twai0_func_clk_sel:1; 530 uint32_t reserved_21:1; 531 /** twai0_func_clk_en : R/W; bitpos: [22]; default: 1; 532 * Set 1 to enable twai0 function clock 533 */ 534 uint32_t twai0_func_clk_en:1; 535 uint32_t reserved_23:9; 536 }; 537 uint32_t val; 538 } pcr_twai0_func_clk_conf_reg_t; 539 540 /** Type of twai1_conf register 541 * TWAI1 configuration register 542 */ 543 typedef union { 544 struct { 545 /** twai1_clk_en : R/W; bitpos: [0]; default: 1; 546 * Set 1 to enable twai1 apb clock 547 */ 548 uint32_t twai1_clk_en:1; 549 /** twai1_rst_en : R/W; bitpos: [1]; default: 0; 550 * Set 0 to reset twai1 module 551 */ 552 uint32_t twai1_rst_en:1; 553 uint32_t reserved_2:30; 554 }; 555 uint32_t val; 556 } pcr_twai1_conf_reg_t; 557 558 /** Type of twai1_func_clk_conf register 559 * TWAI1_FUNC_CLK configuration register 560 */ 561 typedef union { 562 struct { 563 uint32_t reserved_0:20; 564 /** twai1_func_clk_sel : R/W; bitpos: [20]; default: 0; 565 * set this field to select clock-source. 0(default): XTAL, 1: FOSC. 566 */ 567 uint32_t twai1_func_clk_sel:1; 568 uint32_t reserved_21:1; 569 /** twai1_func_clk_en : R/W; bitpos: [22]; default: 1; 570 * Set 1 to enable twai1 function clock 571 */ 572 uint32_t twai1_func_clk_en:1; 573 uint32_t reserved_23:9; 574 }; 575 uint32_t val; 576 } pcr_twai1_func_clk_conf_reg_t; 577 578 /** Type of i2s_conf register 579 * I2S configuration register 580 */ 581 typedef union { 582 struct { 583 /** i2s_clk_en : R/W; bitpos: [0]; default: 1; 584 * Set 1 to enable i2s apb clock 585 */ 586 uint32_t i2s_clk_en:1; 587 /** i2s_rst_en : R/W; bitpos: [1]; default: 0; 588 * Set 0 to reset i2s module 589 */ 590 uint32_t i2s_rst_en:1; 591 uint32_t reserved_2:30; 592 }; 593 uint32_t val; 594 } pcr_i2s_conf_reg_t; 595 596 /** Type of i2s_tx_clkm_conf register 597 * I2S_TX_CLKM configuration register 598 */ 599 typedef union { 600 struct { 601 uint32_t reserved_0:12; 602 /** i2s_tx_clkm_div_num : R/W; bitpos: [19:12]; default: 2; 603 * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be 604 * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= 605 * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * 606 * (n+1)-div] + y * (n+1)-div. 607 */ 608 uint32_t i2s_tx_clkm_div_num:8; 609 /** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0; 610 * Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: 611 * I2S_MCLK_in. 612 */ 613 uint32_t i2s_tx_clkm_sel:2; 614 /** i2s_tx_clkm_en : R/W; bitpos: [22]; default: 1; 615 * Set 1 to enable i2s_tx function clock 616 */ 617 uint32_t i2s_tx_clkm_en:1; 618 uint32_t reserved_23:9; 619 }; 620 uint32_t val; 621 } pcr_i2s_tx_clkm_conf_reg_t; 622 623 /** Type of i2s_tx_clkm_div_conf register 624 * I2S_TX_CLKM_DIV configuration register 625 */ 626 typedef union { 627 struct { 628 /** i2s_tx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; 629 * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of 630 * I2S_TX_CLKM_DIV_Z is (a-b). 631 */ 632 uint32_t i2s_tx_clkm_div_z:9; 633 /** i2s_tx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; 634 * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of 635 * I2S_TX_CLKM_DIV_Y is (a%(a-b)). 636 */ 637 uint32_t i2s_tx_clkm_div_y:9; 638 /** i2s_tx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; 639 * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value 640 * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. 641 */ 642 uint32_t i2s_tx_clkm_div_x:9; 643 /** i2s_tx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; 644 * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of 645 * I2S_TX_CLKM_DIV_YN1 is 1. 646 */ 647 uint32_t i2s_tx_clkm_div_yn1:1; 648 uint32_t reserved_28:4; 649 }; 650 uint32_t val; 651 } pcr_i2s_tx_clkm_div_conf_reg_t; 652 653 /** Type of i2s_rx_clkm_conf register 654 * I2S_RX_CLKM configuration register 655 */ 656 typedef union { 657 struct { 658 uint32_t reserved_0:12; 659 /** i2s_rx_clkm_div_num : R/W; bitpos: [19:12]; default: 2; 660 * Integral I2S clock divider value 661 */ 662 uint32_t i2s_rx_clkm_div_num:8; 663 /** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0; 664 * Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in. 665 */ 666 uint32_t i2s_rx_clkm_sel:2; 667 /** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1; 668 * Set 1 to enable i2s_rx function clock 669 */ 670 uint32_t i2s_rx_clkm_en:1; 671 /** i2s_mclk_sel : R/W; bitpos: [23]; default: 0; 672 * This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx 673 */ 674 uint32_t i2s_mclk_sel:1; 675 uint32_t reserved_24:8; 676 }; 677 uint32_t val; 678 } pcr_i2s_rx_clkm_conf_reg_t; 679 680 /** Type of i2s_rx_clkm_div_conf register 681 * I2S_RX_CLKM_DIV configuration register 682 */ 683 typedef union { 684 struct { 685 /** i2s_rx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; 686 * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of 687 * I2S_RX_CLKM_DIV_Z is (a-b). 688 */ 689 uint32_t i2s_rx_clkm_div_z:9; 690 /** i2s_rx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; 691 * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of 692 * I2S_RX_CLKM_DIV_Y is (a%(a-b)). 693 */ 694 uint32_t i2s_rx_clkm_div_y:9; 695 /** i2s_rx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; 696 * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value 697 * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. 698 */ 699 uint32_t i2s_rx_clkm_div_x:9; 700 /** i2s_rx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; 701 * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of 702 * I2S_RX_CLKM_DIV_YN1 is 1. 703 */ 704 uint32_t i2s_rx_clkm_div_yn1:1; 705 uint32_t reserved_28:4; 706 }; 707 uint32_t val; 708 } pcr_i2s_rx_clkm_div_conf_reg_t; 709 710 /** Type of saradc_conf register 711 * SARADC configuration register 712 */ 713 typedef union { 714 struct { 715 /** saradc_clk_en : R/W; bitpos: [0]; default: 1; 716 * no use 717 */ 718 uint32_t saradc_clk_en:1; 719 /** saradc_rst_en : R/W; bitpos: [1]; default: 0; 720 * Set 0 to reset function_register of saradc module 721 */ 722 uint32_t saradc_rst_en:1; 723 /** saradc_reg_clk_en : R/W; bitpos: [2]; default: 1; 724 * Set 1 to enable saradc apb clock 725 */ 726 uint32_t saradc_reg_clk_en:1; 727 /** saradc_reg_rst_en : R/W; bitpos: [3]; default: 0; 728 * Set 0 to reset apb_register of saradc module 729 */ 730 uint32_t saradc_reg_rst_en:1; 731 uint32_t reserved_4:28; 732 }; 733 uint32_t val; 734 } pcr_saradc_conf_reg_t; 735 736 /** Type of saradc_clkm_conf register 737 * SARADC_CLKM configuration register 738 */ 739 typedef union { 740 struct { 741 /** saradc_clkm_div_a : R/W; bitpos: [5:0]; default: 0; 742 * The denominator of the frequency divider factor of the saradc function clock. 743 */ 744 uint32_t saradc_clkm_div_a:6; 745 /** saradc_clkm_div_b : R/W; bitpos: [11:6]; default: 0; 746 * The numerator of the frequency divider factor of the saradc function clock. 747 */ 748 uint32_t saradc_clkm_div_b:6; 749 /** saradc_clkm_div_num : R/W; bitpos: [19:12]; default: 4; 750 * The integral part of the frequency divider factor of the saradc function clock. 751 */ 752 uint32_t saradc_clkm_div_num:8; 753 /** saradc_clkm_sel : R/W; bitpos: [21:20]; default: 0; 754 * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: 755 * reserved. 756 */ 757 uint32_t saradc_clkm_sel:2; 758 /** saradc_clkm_en : R/W; bitpos: [22]; default: 1; 759 * Set 1 to enable saradc function clock 760 */ 761 uint32_t saradc_clkm_en:1; 762 uint32_t reserved_23:9; 763 }; 764 uint32_t val; 765 } pcr_saradc_clkm_conf_reg_t; 766 767 /** Type of tsens_clk_conf register 768 * TSENS_CLK configuration register 769 */ 770 typedef union { 771 struct { 772 uint32_t reserved_0:20; 773 /** tsens_clk_sel : R/W; bitpos: [20]; default: 0; 774 * set this field to select clock-source. 0(default): FOSC, 1: XTAL. 775 */ 776 uint32_t tsens_clk_sel:1; 777 uint32_t reserved_21:1; 778 /** tsens_clk_en : R/W; bitpos: [22]; default: 1; 779 * Set 1 to enable tsens clock 780 */ 781 uint32_t tsens_clk_en:1; 782 /** tsens_rst_en : R/W; bitpos: [23]; default: 0; 783 * Set 0 to reset tsens module 784 */ 785 uint32_t tsens_rst_en:1; 786 uint32_t reserved_24:8; 787 }; 788 uint32_t val; 789 } pcr_tsens_clk_conf_reg_t; 790 791 /** Type of usb_device_conf register 792 * USB_DEVICE configuration register 793 */ 794 typedef union { 795 struct { 796 /** usb_device_clk_en : R/W; bitpos: [0]; default: 1; 797 * Set 1 to enable usb_device clock 798 */ 799 uint32_t usb_device_clk_en:1; 800 /** usb_device_rst_en : R/W; bitpos: [1]; default: 0; 801 * Set 0 to reset usb_device module 802 */ 803 uint32_t usb_device_rst_en:1; 804 uint32_t reserved_2:30; 805 }; 806 uint32_t val; 807 } pcr_usb_device_conf_reg_t; 808 809 /** Type of intmtx_conf register 810 * INTMTX configuration register 811 */ 812 typedef union { 813 struct { 814 /** intmtx_clk_en : R/W; bitpos: [0]; default: 1; 815 * Set 1 to enable intmtx clock 816 */ 817 uint32_t intmtx_clk_en:1; 818 /** intmtx_rst_en : R/W; bitpos: [1]; default: 0; 819 * Set 0 to reset intmtx module 820 */ 821 uint32_t intmtx_rst_en:1; 822 uint32_t reserved_2:30; 823 }; 824 uint32_t val; 825 } pcr_intmtx_conf_reg_t; 826 827 /** Type of pcnt_conf register 828 * PCNT configuration register 829 */ 830 typedef union { 831 struct { 832 /** pcnt_clk_en : R/W; bitpos: [0]; default: 1; 833 * Set 1 to enable pcnt clock 834 */ 835 uint32_t pcnt_clk_en:1; 836 /** pcnt_rst_en : R/W; bitpos: [1]; default: 0; 837 * Set 0 to reset pcnt module 838 */ 839 uint32_t pcnt_rst_en:1; 840 uint32_t reserved_2:30; 841 }; 842 uint32_t val; 843 } pcr_pcnt_conf_reg_t; 844 845 /** Type of etm_conf register 846 * ETM configuration register 847 */ 848 typedef union { 849 struct { 850 /** etm_clk_en : R/W; bitpos: [0]; default: 1; 851 * Set 1 to enable etm clock 852 */ 853 uint32_t etm_clk_en:1; 854 /** etm_rst_en : R/W; bitpos: [1]; default: 0; 855 * Set 0 to reset etm module 856 */ 857 uint32_t etm_rst_en:1; 858 uint32_t reserved_2:30; 859 }; 860 uint32_t val; 861 } pcr_etm_conf_reg_t; 862 863 /** Type of pwm_conf register 864 * PWM configuration register 865 */ 866 typedef union { 867 struct { 868 /** pwm_clk_en : R/W; bitpos: [0]; default: 1; 869 * Set 1 to enable pwm clock 870 */ 871 uint32_t pwm_clk_en:1; 872 /** pwm_rst_en : R/W; bitpos: [1]; default: 0; 873 * Set 0 to reset pwm module 874 */ 875 uint32_t pwm_rst_en:1; 876 uint32_t reserved_2:30; 877 }; 878 uint32_t val; 879 } pcr_pwm_conf_reg_t; 880 881 /** Type of pwm_clk_conf register 882 * PWM_CLK configuration register 883 */ 884 typedef union { 885 struct { 886 uint32_t reserved_0:12; 887 /** pwm_div_num : R/W; bitpos: [19:12]; default: 4; 888 * The integral part of the frequency divider factor of the pwm function clock. 889 */ 890 uint32_t pwm_div_num:8; 891 /** pwm_clkm_sel : R/W; bitpos: [21:20]; default: 0; 892 * set this field to select clock-source. 0(default): do not select anyone clock, 1: 893 * 160MHz, 2: XTAL, 3: FOSC. 894 */ 895 uint32_t pwm_clkm_sel:2; 896 /** pwm_clkm_en : R/W; bitpos: [22]; default: 1; 897 * set this field as 1 to activate pwm clkm. 898 */ 899 uint32_t pwm_clkm_en:1; 900 uint32_t reserved_23:9; 901 }; 902 uint32_t val; 903 } pcr_pwm_clk_conf_reg_t; 904 905 /** Type of parl_io_conf register 906 * PARL_IO configuration register 907 */ 908 typedef union { 909 struct { 910 /** parl_clk_en : R/W; bitpos: [0]; default: 1; 911 * Set 1 to enable parl apb clock 912 */ 913 uint32_t parl_clk_en:1; 914 /** parl_rst_en : R/W; bitpos: [1]; default: 0; 915 * Set 0 to reset parl apb reg 916 */ 917 uint32_t parl_rst_en:1; 918 uint32_t reserved_2:30; 919 }; 920 uint32_t val; 921 } pcr_parl_io_conf_reg_t; 922 923 /** Type of parl_clk_rx_conf register 924 * PARL_CLK_RX configuration register 925 */ 926 typedef union { 927 struct { 928 /** parl_clk_rx_div_num : R/W; bitpos: [15:0]; default: 0; 929 * The integral part of the frequency divider factor of the parl rx clock. 930 */ 931 uint32_t parl_clk_rx_div_num:16; 932 /** parl_clk_rx_sel : R/W; bitpos: [17:16]; default: 0; 933 * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: 934 * user clock from pad. 935 */ 936 uint32_t parl_clk_rx_sel:2; 937 /** parl_clk_rx_en : R/W; bitpos: [18]; default: 1; 938 * Set 1 to enable parl rx clock 939 */ 940 uint32_t parl_clk_rx_en:1; 941 /** parl_rx_rst_en : R/W; bitpos: [19]; default: 0; 942 * Set 0 to reset parl rx module 943 */ 944 uint32_t parl_rx_rst_en:1; 945 uint32_t reserved_20:12; 946 }; 947 uint32_t val; 948 } pcr_parl_clk_rx_conf_reg_t; 949 950 /** Type of parl_clk_tx_conf register 951 * PARL_CLK_TX configuration register 952 */ 953 typedef union { 954 struct { 955 /** parl_clk_tx_div_num : R/W; bitpos: [15:0]; default: 0; 956 * The integral part of the frequency divider factor of the parl tx clock. 957 */ 958 uint32_t parl_clk_tx_div_num:16; 959 /** parl_clk_tx_sel : R/W; bitpos: [17:16]; default: 0; 960 * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: 961 * user clock from pad. 962 */ 963 uint32_t parl_clk_tx_sel:2; 964 /** parl_clk_tx_en : R/W; bitpos: [18]; default: 1; 965 * Set 1 to enable parl tx clock 966 */ 967 uint32_t parl_clk_tx_en:1; 968 /** parl_tx_rst_en : R/W; bitpos: [19]; default: 0; 969 * Set 0 to reset parl tx module 970 */ 971 uint32_t parl_tx_rst_en:1; 972 uint32_t reserved_20:12; 973 }; 974 uint32_t val; 975 } pcr_parl_clk_tx_conf_reg_t; 976 977 /** Type of sdio_slave_conf register 978 * SDIO_SLAVE configuration register 979 */ 980 typedef union { 981 struct { 982 /** sdio_slave_clk_en : R/W; bitpos: [0]; default: 1; 983 * Set 1 to enable sdio_slave clock 984 */ 985 uint32_t sdio_slave_clk_en:1; 986 /** sdio_slave_rst_en : R/W; bitpos: [1]; default: 0; 987 * Set 0 to reset sdio_slave module 988 */ 989 uint32_t sdio_slave_rst_en:1; 990 uint32_t reserved_2:30; 991 }; 992 uint32_t val; 993 } pcr_sdio_slave_conf_reg_t; 994 995 /** Type of pvt_monitor_conf register 996 * PVT_MONITOR configuration register 997 */ 998 typedef union { 999 struct { 1000 /** pvt_monitor_clk_en : R/W; bitpos: [0]; default: 1; 1001 * Set 1 to enable apb clock of pvt module 1002 */ 1003 uint32_t pvt_monitor_clk_en:1; 1004 /** pvt_monitor_rst_en : R/W; bitpos: [1]; default: 0; 1005 * Set 0 to reset all pvt monitor module 1006 */ 1007 uint32_t pvt_monitor_rst_en:1; 1008 /** pvt_monitor_site1_clk_en : R/W; bitpos: [2]; default: 1; 1009 * Set 1 to enable function clock of modem pvt module 1010 */ 1011 uint32_t pvt_monitor_site1_clk_en:1; 1012 /** pvt_monitor_site2_clk_en : R/W; bitpos: [3]; default: 1; 1013 * Set 1 to enable function clock of cpu pvt module 1014 */ 1015 uint32_t pvt_monitor_site2_clk_en:1; 1016 /** pvt_monitor_site3_clk_en : R/W; bitpos: [4]; default: 1; 1017 * Set 1 to enable function clock of hp_peri pvt module 1018 */ 1019 uint32_t pvt_monitor_site3_clk_en:1; 1020 uint32_t reserved_5:27; 1021 }; 1022 uint32_t val; 1023 } pcr_pvt_monitor_conf_reg_t; 1024 1025 /** Type of pvt_monitor_func_clk_conf register 1026 * PVT_MONITOR function clock configuration register 1027 */ 1028 typedef union { 1029 struct { 1030 /** pvt_monitor_func_clk_div_num : R/W; bitpos: [3:0]; default: 0; 1031 * The integral part of the frequency divider factor of the pvt_monitor function clock. 1032 */ 1033 uint32_t pvt_monitor_func_clk_div_num:4; 1034 uint32_t reserved_4:16; 1035 /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0; 1036 * set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL 1037 * divided by 3. 1038 */ 1039 uint32_t pvt_monitor_func_clk_sel:1; 1040 uint32_t reserved_21:1; 1041 /** pvt_monitor_func_clk_en : R/W; bitpos: [22]; default: 1; 1042 * Set 1 to enable source clock of pvt sitex 1043 */ 1044 uint32_t pvt_monitor_func_clk_en:1; 1045 uint32_t reserved_23:9; 1046 }; 1047 uint32_t val; 1048 } pcr_pvt_monitor_func_clk_conf_reg_t; 1049 1050 /** Type of gdma_conf register 1051 * GDMA configuration register 1052 */ 1053 typedef union { 1054 struct { 1055 /** gdma_clk_en : R/W; bitpos: [0]; default: 1; 1056 * Set 1 to enable gdma clock 1057 */ 1058 uint32_t gdma_clk_en:1; 1059 /** gdma_rst_en : R/W; bitpos: [1]; default: 0; 1060 * Set 0 to reset gdma module 1061 */ 1062 uint32_t gdma_rst_en:1; 1063 uint32_t reserved_2:30; 1064 }; 1065 uint32_t val; 1066 } pcr_gdma_conf_reg_t; 1067 1068 /** Type of spi2_conf register 1069 * SPI2 configuration register 1070 */ 1071 typedef union { 1072 struct { 1073 /** spi2_clk_en : R/W; bitpos: [0]; default: 1; 1074 * Set 1 to enable spi2 apb clock 1075 */ 1076 uint32_t spi2_clk_en:1; 1077 /** spi2_rst_en : R/W; bitpos: [1]; default: 0; 1078 * Set 0 to reset spi2 module 1079 */ 1080 uint32_t spi2_rst_en:1; 1081 uint32_t reserved_2:30; 1082 }; 1083 uint32_t val; 1084 } pcr_spi2_conf_reg_t; 1085 1086 /** Type of spi2_clkm_conf register 1087 * SPI2_CLKM configuration register 1088 */ 1089 typedef union { 1090 struct { 1091 uint32_t reserved_0:20; 1092 /** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0; 1093 * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: 1094 * reserved. 1095 */ 1096 uint32_t spi2_clkm_sel:2; 1097 /** spi2_clkm_en : R/W; bitpos: [22]; default: 1; 1098 * Set 1 to enable spi2 function clock 1099 */ 1100 uint32_t spi2_clkm_en:1; 1101 uint32_t reserved_23:9; 1102 }; 1103 uint32_t val; 1104 } pcr_spi2_clkm_conf_reg_t; 1105 1106 /** Type of aes_conf register 1107 * AES configuration register 1108 */ 1109 typedef union { 1110 struct { 1111 /** aes_clk_en : R/W; bitpos: [0]; default: 1; 1112 * Set 1 to enable aes clock 1113 */ 1114 uint32_t aes_clk_en:1; 1115 /** aes_rst_en : R/W; bitpos: [1]; default: 0; 1116 * Set 0 to reset aes module 1117 */ 1118 uint32_t aes_rst_en:1; 1119 uint32_t reserved_2:30; 1120 }; 1121 uint32_t val; 1122 } pcr_aes_conf_reg_t; 1123 1124 /** Type of sha_conf register 1125 * SHA configuration register 1126 */ 1127 typedef union { 1128 struct { 1129 /** sha_clk_en : R/W; bitpos: [0]; default: 1; 1130 * Set 1 to enable sha clock 1131 */ 1132 uint32_t sha_clk_en:1; 1133 /** sha_rst_en : R/W; bitpos: [1]; default: 0; 1134 * Set 0 to reset sha module 1135 */ 1136 uint32_t sha_rst_en:1; 1137 uint32_t reserved_2:30; 1138 }; 1139 uint32_t val; 1140 } pcr_sha_conf_reg_t; 1141 1142 /** Type of rsa_conf register 1143 * RSA configuration register 1144 */ 1145 typedef union { 1146 struct { 1147 /** rsa_clk_en : R/W; bitpos: [0]; default: 1; 1148 * Set 1 to enable rsa clock 1149 */ 1150 uint32_t rsa_clk_en:1; 1151 /** rsa_rst_en : R/W; bitpos: [1]; default: 0; 1152 * Set 0 to reset rsa module 1153 */ 1154 uint32_t rsa_rst_en:1; 1155 uint32_t reserved_2:30; 1156 }; 1157 uint32_t val; 1158 } pcr_rsa_conf_reg_t; 1159 1160 /** Type of rsa_pd_ctrl register 1161 * RSA power control register 1162 */ 1163 typedef union { 1164 struct { 1165 /** rsa_mem_pd : R/W; bitpos: [0]; default: 0; 1166 * Set this bit to power down rsa internal memory. 1167 */ 1168 uint32_t rsa_mem_pd:1; 1169 /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 1; 1170 * Set this bit to force power up rsa internal memory 1171 */ 1172 uint32_t rsa_mem_force_pu:1; 1173 /** rsa_mem_force_pd : R/W; bitpos: [2]; default: 0; 1174 * Set this bit to force power down rsa internal memory. 1175 */ 1176 uint32_t rsa_mem_force_pd:1; 1177 uint32_t reserved_3:29; 1178 }; 1179 uint32_t val; 1180 } pcr_rsa_pd_ctrl_reg_t; 1181 1182 /** Type of ecc_conf register 1183 * ECC configuration register 1184 */ 1185 typedef union { 1186 struct { 1187 /** ecc_clk_en : R/W; bitpos: [0]; default: 1; 1188 * Set 1 to enable ecc clock 1189 */ 1190 uint32_t ecc_clk_en:1; 1191 /** ecc_rst_en : R/W; bitpos: [1]; default: 0; 1192 * Set 0 to reset ecc module 1193 */ 1194 uint32_t ecc_rst_en:1; 1195 uint32_t reserved_2:30; 1196 }; 1197 uint32_t val; 1198 } pcr_ecc_conf_reg_t; 1199 1200 /** Type of ecc_pd_ctrl register 1201 * ECC power control register 1202 */ 1203 typedef union { 1204 struct { 1205 /** ecc_mem_pd : R/W; bitpos: [0]; default: 0; 1206 * Set this bit to power down ecc internal memory. 1207 */ 1208 uint32_t ecc_mem_pd:1; 1209 /** ecc_mem_force_pu : R/W; bitpos: [1]; default: 1; 1210 * Set this bit to force power up ecc internal memory 1211 */ 1212 uint32_t ecc_mem_force_pu:1; 1213 /** ecc_mem_force_pd : R/W; bitpos: [2]; default: 0; 1214 * Set this bit to force power down ecc internal memory. 1215 */ 1216 uint32_t ecc_mem_force_pd:1; 1217 uint32_t reserved_3:29; 1218 }; 1219 uint32_t val; 1220 } pcr_ecc_pd_ctrl_reg_t; 1221 1222 /** Type of ds_conf register 1223 * DS configuration register 1224 */ 1225 typedef union { 1226 struct { 1227 /** ds_clk_en : R/W; bitpos: [0]; default: 1; 1228 * Set 1 to enable ds clock 1229 */ 1230 uint32_t ds_clk_en:1; 1231 /** ds_rst_en : R/W; bitpos: [1]; default: 0; 1232 * Set 0 to reset ds module 1233 */ 1234 uint32_t ds_rst_en:1; 1235 uint32_t reserved_2:30; 1236 }; 1237 uint32_t val; 1238 } pcr_ds_conf_reg_t; 1239 1240 /** Type of hmac_conf register 1241 * HMAC configuration register 1242 */ 1243 typedef union { 1244 struct { 1245 /** hmac_clk_en : R/W; bitpos: [0]; default: 1; 1246 * Set 1 to enable hmac clock 1247 */ 1248 uint32_t hmac_clk_en:1; 1249 /** hmac_rst_en : R/W; bitpos: [1]; default: 0; 1250 * Set 0 to reset hmac module 1251 */ 1252 uint32_t hmac_rst_en:1; 1253 uint32_t reserved_2:30; 1254 }; 1255 uint32_t val; 1256 } pcr_hmac_conf_reg_t; 1257 1258 /** Type of iomux_conf register 1259 * IOMUX configuration register 1260 */ 1261 typedef union { 1262 struct { 1263 /** iomux_clk_en : R/W; bitpos: [0]; default: 1; 1264 * Set 1 to enable iomux apb clock 1265 */ 1266 uint32_t iomux_clk_en:1; 1267 /** iomux_rst_en : R/W; bitpos: [1]; default: 0; 1268 * Set 0 to reset iomux module 1269 */ 1270 uint32_t iomux_rst_en:1; 1271 uint32_t reserved_2:30; 1272 }; 1273 uint32_t val; 1274 } pcr_iomux_conf_reg_t; 1275 1276 /** Type of iomux_clk_conf register 1277 * IOMUX_CLK configuration register 1278 */ 1279 typedef union { 1280 struct { 1281 uint32_t reserved_0:20; 1282 /** iomux_func_clk_sel : R/W; bitpos: [21:20]; default: 3; 1283 * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: 1284 * FOSC, 3(default): XTAL. 1285 */ 1286 uint32_t iomux_func_clk_sel:2; 1287 /** iomux_func_clk_en : R/W; bitpos: [22]; default: 1; 1288 * Set 1 to enable iomux function clock 1289 */ 1290 uint32_t iomux_func_clk_en:1; 1291 uint32_t reserved_23:9; 1292 }; 1293 uint32_t val; 1294 } pcr_iomux_clk_conf_reg_t; 1295 1296 /** Type of mem_monitor_conf register 1297 * MEM_MONITOR configuration register 1298 */ 1299 typedef union { 1300 struct { 1301 /** mem_monitor_clk_en : R/W; bitpos: [0]; default: 1; 1302 * Set 1 to enable mem_monitor clock 1303 */ 1304 uint32_t mem_monitor_clk_en:1; 1305 /** mem_monitor_rst_en : R/W; bitpos: [1]; default: 0; 1306 * Set 0 to reset mem_monitor module 1307 */ 1308 uint32_t mem_monitor_rst_en:1; 1309 uint32_t reserved_2:30; 1310 }; 1311 uint32_t val; 1312 } pcr_mem_monitor_conf_reg_t; 1313 1314 /** Type of regdma_conf register 1315 * REGDMA configuration register 1316 */ 1317 typedef union { 1318 struct { 1319 /** regdma_clk_en : R/W; bitpos: [0]; default: 0; 1320 * Set 1 to enable regdma clock 1321 */ 1322 uint32_t regdma_clk_en:1; 1323 /** regdma_rst_en : R/W; bitpos: [1]; default: 0; 1324 * Set 0 to reset regdma module 1325 */ 1326 uint32_t regdma_rst_en:1; 1327 uint32_t reserved_2:30; 1328 }; 1329 uint32_t val; 1330 } pcr_regdma_conf_reg_t; 1331 1332 /** Type of retention_conf register 1333 * retention configuration register 1334 */ 1335 typedef union { 1336 struct { 1337 /** retention_clk_en : R/W; bitpos: [0]; default: 0; 1338 * Set 1 to enable retention clock 1339 */ 1340 uint32_t retention_clk_en:1; 1341 /** retention_rst_en : R/W; bitpos: [1]; default: 0; 1342 * Set 0 to reset retention module 1343 */ 1344 uint32_t retention_rst_en:1; 1345 uint32_t reserved_2:30; 1346 }; 1347 uint32_t val; 1348 } pcr_retention_conf_reg_t; 1349 1350 /** Type of trace_conf register 1351 * TRACE configuration register 1352 */ 1353 typedef union { 1354 struct { 1355 /** trace_clk_en : R/W; bitpos: [0]; default: 1; 1356 * Set 1 to enable trace clock 1357 */ 1358 uint32_t trace_clk_en:1; 1359 /** trace_rst_en : R/W; bitpos: [1]; default: 0; 1360 * Set 0 to reset trace module 1361 */ 1362 uint32_t trace_rst_en:1; 1363 uint32_t reserved_2:30; 1364 }; 1365 uint32_t val; 1366 } pcr_trace_conf_reg_t; 1367 1368 /** Type of assist_conf register 1369 * ASSIST configuration register 1370 */ 1371 typedef union { 1372 struct { 1373 /** assist_clk_en : R/W; bitpos: [0]; default: 1; 1374 * Set 1 to enable assist clock 1375 */ 1376 uint32_t assist_clk_en:1; 1377 /** assist_rst_en : R/W; bitpos: [1]; default: 0; 1378 * Set 0 to reset assist module 1379 */ 1380 uint32_t assist_rst_en:1; 1381 uint32_t reserved_2:30; 1382 }; 1383 uint32_t val; 1384 } pcr_assist_conf_reg_t; 1385 1386 /** Type of cache_conf register 1387 * CACHE configuration register 1388 */ 1389 typedef union { 1390 struct { 1391 /** cache_clk_en : R/W; bitpos: [0]; default: 1; 1392 * Set 1 to enable cache clock 1393 */ 1394 uint32_t cache_clk_en:1; 1395 /** cache_rst_en : R/W; bitpos: [1]; default: 0; 1396 * Set 0 to reset cache module 1397 */ 1398 uint32_t cache_rst_en:1; 1399 uint32_t reserved_2:30; 1400 }; 1401 uint32_t val; 1402 } pcr_cache_conf_reg_t; 1403 1404 /** Type of modem_apb_conf register 1405 * MODEM_APB configuration register 1406 */ 1407 typedef union { 1408 struct { 1409 /** modem_apb_clk_en : R/W; bitpos: [0]; default: 1; 1410 * This field indicates if modem_apb clock is enable. 0: disable, 1: enable(default). 1411 */ 1412 uint32_t modem_apb_clk_en:1; 1413 /** modem_rst_en : R/W; bitpos: [1]; default: 0; 1414 * Set this file as 1 to reset modem-subsystem. 1415 */ 1416 uint32_t modem_rst_en:1; 1417 uint32_t reserved_2:30; 1418 }; 1419 uint32_t val; 1420 } pcr_modem_apb_conf_reg_t; 1421 1422 /** Type of timeout_conf register 1423 * TIMEOUT configuration register 1424 */ 1425 typedef union { 1426 struct { 1427 uint32_t reserved_0:1; 1428 /** cpu_timeout_rst_en : R/W; bitpos: [1]; default: 0; 1429 * Set 0 to reset cpu_peri timeout module 1430 */ 1431 uint32_t cpu_timeout_rst_en:1; 1432 /** hp_timeout_rst_en : R/W; bitpos: [2]; default: 0; 1433 * Set 0 to reset hp_peri timeout module and hp_modem timeout module 1434 */ 1435 uint32_t hp_timeout_rst_en:1; 1436 uint32_t reserved_3:29; 1437 }; 1438 uint32_t val; 1439 } pcr_timeout_conf_reg_t; 1440 1441 /** Type of sysclk_conf register 1442 * SYSCLK configuration register 1443 */ 1444 typedef union { 1445 struct { 1446 /** ls_div_num : HRO; bitpos: [7:0]; default: 0; 1447 * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed 1448 * clock-source such as XTAL/FOSC. 1449 */ 1450 uint32_t ls_div_num:8; 1451 /** hs_div_num : HRO; bitpos: [15:8]; default: 2; 1452 * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. 1453 */ 1454 uint32_t hs_div_num:8; 1455 /** soc_clk_sel : R/W; bitpos: [17:16]; default: 0; 1456 * This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved. 1457 */ 1458 uint32_t soc_clk_sel:2; 1459 uint32_t reserved_18:6; 1460 /** clk_xtal_freq : RO; bitpos: [30:24]; default: 40; 1461 * This field indicates the frequency(MHz) of XTAL. 1462 */ 1463 uint32_t clk_xtal_freq:7; 1464 uint32_t reserved_31:1; 1465 }; 1466 uint32_t val; 1467 } pcr_sysclk_conf_reg_t; 1468 1469 /** Type of cpu_waiti_conf register 1470 * CPU_WAITI configuration register 1471 */ 1472 typedef union { 1473 struct { 1474 /** cpuperiod_sel : HRO; bitpos: [1:0]; default: 1; 1475 * Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM 1476 */ 1477 uint32_t cpuperiod_sel:2; 1478 /** pll_freq_sel : HRO; bitpos: [2]; default: 1; 1479 * Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and PCR_CPU_LS_DIV_NUM 1480 */ 1481 uint32_t pll_freq_sel:1; 1482 /** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1; 1483 * Set 1 to force cpu_waiti_clk enable. 1484 */ 1485 uint32_t cpu_wait_mode_force_on:1; 1486 /** cpu_waiti_delay_num : R/W; bitpos: [7:4]; default: 0; 1487 * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk 1488 * will close 1489 */ 1490 uint32_t cpu_waiti_delay_num:4; 1491 uint32_t reserved_8:24; 1492 }; 1493 uint32_t val; 1494 } pcr_cpu_waiti_conf_reg_t; 1495 1496 /** Type of cpu_freq_conf register 1497 * CPU_FREQ configuration register 1498 */ 1499 typedef union { 1500 struct { 1501 /** cpu_ls_div_num : R/W; bitpos: [7:0]; default: 0; 1502 * Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is 1503 * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed 1504 * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_LS_DIV_NUM. 1505 */ 1506 uint32_t cpu_ls_div_num:8; 1507 /** cpu_hs_div_num : R/W; bitpos: [15:8]; default: 0; 1508 * Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The clk_cpu is 1509 * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for high-speed 1510 * clock-source such as SPLL, and should be used together with PCR_AHB_HS_DIV_NUM. 1511 */ 1512 uint32_t cpu_hs_div_num:8; 1513 /** cpu_hs_120m_force : R/W; bitpos: [16]; default: 0; 1514 * Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu at 120MHz. 1515 * Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is driven by SPLL. 1516 */ 1517 uint32_t cpu_hs_120m_force:1; 1518 uint32_t reserved_17:15; 1519 }; 1520 uint32_t val; 1521 } pcr_cpu_freq_conf_reg_t; 1522 1523 /** Type of ahb_freq_conf register 1524 * AHB_FREQ configuration register 1525 */ 1526 typedef union { 1527 struct { 1528 /** ahb_ls_div_num : R/W; bitpos: [7:0]; default: 0; 1529 * Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The clk_ahb 1530 * is div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for 1531 * low-speed clock-source such as XTAL/FOSC, and should be used together with 1532 * PCR_CPU_LS_DIV_NUM. 1533 */ 1534 uint32_t ahb_ls_div_num:8; 1535 /** ahb_hs_div_num : R/W; bitpos: [15:8]; default: 3; 1536 * Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The clk_ahb is 1537 * div4(default)/div8/div16 of clk_hproot. This field is only avaliable for high-speed 1538 * clock-source such as SPLL, and should be used together with PCR_CPU_HS_DIV_NUM. 1539 */ 1540 uint32_t ahb_hs_div_num:8; 1541 uint32_t reserved_16:16; 1542 }; 1543 uint32_t val; 1544 } pcr_ahb_freq_conf_reg_t; 1545 1546 /** Type of apb_freq_conf register 1547 * APB_FREQ configuration register 1548 */ 1549 typedef union { 1550 struct { 1551 /** apb_decrease_div_num : R/W; bitpos: [7:0]; default: 0; 1552 * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be 1553 * automatically down to clk_apb_decrease only when no access is on apb-bus, and will 1554 * recover to the previous frequency when a new access appears on apb-bus. Set as one 1555 * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note 1556 * that enable this function will reduce performance. Users can set this field as zero 1557 * to disable the auto-decrease-apb-freq function. By default, this function is 1558 * disable. 1559 */ 1560 uint32_t apb_decrease_div_num:8; 1561 /** apb_div_num : R/W; bitpos: [15:8]; default: 0; 1562 * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is 1563 * div1(default)/div2/div4 of clk_ahb. 1564 */ 1565 uint32_t apb_div_num:8; 1566 uint32_t reserved_16:16; 1567 }; 1568 uint32_t val; 1569 } pcr_apb_freq_conf_reg_t; 1570 1571 /** Type of pll_div_clk_en register 1572 * SPLL DIV clock-gating configuration register 1573 */ 1574 typedef union { 1575 struct { 1576 /** pll_240m_clk_en : R/W; bitpos: [0]; default: 1; 1577 * This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. 0: close, 1578 * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. 1579 */ 1580 uint32_t pll_240m_clk_en:1; 1581 /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1; 1582 * This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. 0: close, 1583 * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. 1584 */ 1585 uint32_t pll_160m_clk_en:1; 1586 /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1; 1587 * This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. 0: close, 1588 * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. 1589 */ 1590 uint32_t pll_120m_clk_en:1; 1591 /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1; 1592 * This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. 0: close, 1593 * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. 1594 */ 1595 uint32_t pll_80m_clk_en:1; 1596 /** pll_48m_clk_en : R/W; bitpos: [4]; default: 1; 1597 * This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. 0: close, 1598 * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. 1599 */ 1600 uint32_t pll_48m_clk_en:1; 1601 /** pll_40m_clk_en : R/W; bitpos: [5]; default: 1; 1602 * This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. 0: close, 1603 * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. 1604 */ 1605 uint32_t pll_40m_clk_en:1; 1606 /** pll_20m_clk_en : R/W; bitpos: [6]; default: 1; 1607 * This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. 0: close, 1608 * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. 1609 */ 1610 uint32_t pll_20m_clk_en:1; 1611 uint32_t reserved_7:25; 1612 }; 1613 uint32_t val; 1614 } pcr_pll_div_clk_en_reg_t; 1615 1616 /** Type of ctrl_clk_out_en register 1617 * CLK_OUT_EN configuration register 1618 */ 1619 typedef union { 1620 struct { 1621 /** clk20_oen : R/W; bitpos: [0]; default: 1; 1622 * Set 1 to enable 20m clock 1623 */ 1624 uint32_t clk20_oen:1; 1625 /** clk22_oen : R/W; bitpos: [1]; default: 1; 1626 * Set 1 to enable 22m clock 1627 */ 1628 uint32_t clk22_oen:1; 1629 /** clk44_oen : R/W; bitpos: [2]; default: 1; 1630 * Set 1 to enable 44m clock 1631 */ 1632 uint32_t clk44_oen:1; 1633 /** clk_bb_oen : R/W; bitpos: [3]; default: 1; 1634 * Set 1 to enable bb clock 1635 */ 1636 uint32_t clk_bb_oen:1; 1637 /** clk80_oen : R/W; bitpos: [4]; default: 1; 1638 * Set 1 to enable 80m clock 1639 */ 1640 uint32_t clk80_oen:1; 1641 /** clk160_oen : R/W; bitpos: [5]; default: 1; 1642 * Set 1 to enable 160m clock 1643 */ 1644 uint32_t clk160_oen:1; 1645 /** clk_320m_oen : R/W; bitpos: [6]; default: 1; 1646 * Set 1 to enable 320m clock 1647 */ 1648 uint32_t clk_320m_oen:1; 1649 /** clk_adc_inf_oen : R/W; bitpos: [7]; default: 1; 1650 * Reserved 1651 */ 1652 uint32_t clk_adc_inf_oen:1; 1653 /** clk_dac_cpu_oen : R/W; bitpos: [8]; default: 1; 1654 * Reserved 1655 */ 1656 uint32_t clk_dac_cpu_oen:1; 1657 /** clk40x_bb_oen : R/W; bitpos: [9]; default: 1; 1658 * Set 1 to enable 40x_bb clock 1659 */ 1660 uint32_t clk40x_bb_oen:1; 1661 /** clk_xtal_oen : R/W; bitpos: [10]; default: 1; 1662 * Set 1 to enable xtal clock 1663 */ 1664 uint32_t clk_xtal_oen:1; 1665 uint32_t reserved_11:21; 1666 }; 1667 uint32_t val; 1668 } pcr_ctrl_clk_out_en_reg_t; 1669 1670 /** Type of ctrl_tick_conf register 1671 * TICK configuration register 1672 */ 1673 typedef union { 1674 struct { 1675 /** xtal_tick_num : R/W; bitpos: [7:0]; default: 39; 1676 * ******* Description *********** 1677 */ 1678 uint32_t xtal_tick_num:8; 1679 /** fosc_tick_num : R/W; bitpos: [15:8]; default: 7; 1680 * ******* Description *********** 1681 */ 1682 uint32_t fosc_tick_num:8; 1683 /** tick_enable : R/W; bitpos: [16]; default: 1; 1684 * ******* Description *********** 1685 */ 1686 uint32_t tick_enable:1; 1687 /** rst_tick_cnt : R/W; bitpos: [17]; default: 0; 1688 * ******* Description *********** 1689 */ 1690 uint32_t rst_tick_cnt:1; 1691 uint32_t reserved_18:14; 1692 }; 1693 uint32_t val; 1694 } pcr_ctrl_tick_conf_reg_t; 1695 1696 /** Type of ctrl_32k_conf register 1697 * 32KHz clock configuration register 1698 */ 1699 typedef union { 1700 struct { 1701 /** clk_32k_sel : R/W; bitpos: [1:0]; default: 0; 1702 * This field indicates which one 32KHz clock will be used by timergroup. 1703 * 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. 1704 */ 1705 uint32_t clk_32k_sel:2; 1706 uint32_t reserved_2:30; 1707 }; 1708 uint32_t val; 1709 } pcr_ctrl_32k_conf_reg_t; 1710 1711 /** Type of sram_power_conf register 1712 * HP SRAM/ROM configuration register 1713 */ 1714 typedef union { 1715 struct { 1716 /** sram_force_pu : R/W; bitpos: [3:0]; default: 15; 1717 * Set this bit to force power up SRAM 1718 */ 1719 uint32_t sram_force_pu:4; 1720 /** sram_force_pd : R/W; bitpos: [7:4]; default: 0; 1721 * Set this bit to force power down SRAM. 1722 */ 1723 uint32_t sram_force_pd:4; 1724 /** sram_clkgate_force_on : R/W; bitpos: [11:8]; default: 0; 1725 * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A 1726 * gate-clock will be used when accessing the SRAM. 1727 */ 1728 uint32_t sram_clkgate_force_on:4; 1729 /** rom_force_pu : R/W; bitpos: [14:12]; default: 7; 1730 * Set this bit to force power up ROM 1731 */ 1732 uint32_t rom_force_pu:3; 1733 /** rom_force_pd : R/W; bitpos: [17:15]; default: 0; 1734 * Set this bit to force power down ROM. 1735 */ 1736 uint32_t rom_force_pd:3; 1737 /** rom_clkgate_force_on : R/W; bitpos: [20:18]; default: 0; 1738 * 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A 1739 * gate-clock will be used when accessing the ROM. 1740 */ 1741 uint32_t rom_clkgate_force_on:3; 1742 uint32_t reserved_21:11; 1743 }; 1744 uint32_t val; 1745 } pcr_sram_power_conf_reg_t; 1746 1747 /** Type of reset_event_bypass register 1748 * reset event bypass backdoor configuration register 1749 */ 1750 typedef union { 1751 struct { 1752 /** reset_event_bypass_apm : R/W; bitpos: [0]; default: 0; 1753 * This field is used to control reset event relationship for 1754 * tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset 1755 * by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg 1756 * will not only be reset by power-reset, but also some reset event. 1757 */ 1758 uint32_t reset_event_bypass_apm:1; 1759 /** reset_event_bypass : R/W; bitpos: [1]; default: 1; 1760 * This field is used to control reset event relationship for system-bus. 1: system 1761 * bus (including arbiter/router) will only be reset by power-reset. some reset event 1762 * will be bypass. 0: system bus (including arbiter/router) will not only be reset by 1763 * power-reset, but also some reset event. 1764 */ 1765 uint32_t reset_event_bypass:1; 1766 uint32_t reserved_2:30; 1767 }; 1768 uint32_t val; 1769 } pcr_reset_event_bypass_reg_t; 1770 1771 /** Type of clock_gate register 1772 * PCR clock gating configure register 1773 */ 1774 typedef union { 1775 struct { 1776 /** clk_en : R/W; bitpos: [0]; default: 0; 1777 * Set this bit as 1 to force on clock gating. 1778 */ 1779 uint32_t clk_en:1; 1780 uint32_t reserved_1:31; 1781 }; 1782 uint32_t val; 1783 } pcr_clock_gate_reg_t; 1784 1785 1786 /** Group: Frequency Statistics Register */ 1787 /** Type of sysclk_freq_query_0 register 1788 * SYSCLK frequency query 0 register 1789 */ 1790 typedef union { 1791 struct { 1792 /** fosc_freq : HRO; bitpos: [7:0]; default: 20; 1793 * This field indicates the frequency(MHz) of FOSC. 1794 */ 1795 uint32_t fosc_freq:8; 1796 /** pll_freq : HRO; bitpos: [17:8]; default: 480; 1797 * This field indicates the frequency(MHz) of SPLL. 1798 */ 1799 uint32_t pll_freq:10; 1800 uint32_t reserved_18:14; 1801 }; 1802 uint32_t val; 1803 } pcr_sysclk_freq_query_0_reg_t; 1804 1805 1806 /** Group: FPGA Debug Register */ 1807 /** Type of fpga_debug register 1808 * fpga debug register 1809 */ 1810 typedef union { 1811 struct { 1812 /** fpga_debug : R/W; bitpos: [31:0]; default: 4294967295; 1813 * Only used in fpga debug. 1814 */ 1815 uint32_t fpga_debug:32; 1816 }; 1817 uint32_t val; 1818 } pcr_fpga_debug_reg_t; 1819 1820 1821 /** Group: Version Register */ 1822 /** Type of date register 1823 * Date register. 1824 */ 1825 typedef union { 1826 struct { 1827 /** date : R/W; bitpos: [27:0]; default: 35676496; 1828 * PCR version information. 1829 */ 1830 uint32_t date:28; 1831 uint32_t reserved_28:4; 1832 }; 1833 uint32_t val; 1834 } pcr_date_reg_t; 1835 1836 1837 typedef struct pcr_dev_t { 1838 volatile pcr_uart0_conf_reg_t uart0_conf; 1839 volatile pcr_uart0_sclk_conf_reg_t uart0_sclk_conf; 1840 volatile pcr_uart0_pd_ctrl_reg_t uart0_pd_ctrl; 1841 volatile pcr_uart1_conf_reg_t uart1_conf; 1842 volatile pcr_uart1_sclk_conf_reg_t uart1_sclk_conf; 1843 volatile pcr_uart1_pd_ctrl_reg_t uart1_pd_ctrl; 1844 volatile pcr_mspi_conf_reg_t mspi_conf; 1845 volatile pcr_mspi_clk_conf_reg_t mspi_clk_conf; 1846 volatile pcr_i2c_conf_reg_t i2c_conf; 1847 volatile pcr_i2c_sclk_conf_reg_t i2c_sclk_conf; 1848 volatile pcr_uhci_conf_reg_t uhci_conf; 1849 volatile pcr_rmt_conf_reg_t rmt_conf; 1850 volatile pcr_rmt_sclk_conf_reg_t rmt_sclk_conf; 1851 volatile pcr_ledc_conf_reg_t ledc_conf; 1852 volatile pcr_ledc_sclk_conf_reg_t ledc_sclk_conf; 1853 volatile pcr_timergroup0_conf_reg_t timergroup0_conf; 1854 volatile pcr_timergroup0_timer_clk_conf_reg_t timergroup0_timer_clk_conf; 1855 volatile pcr_timergroup0_wdt_clk_conf_reg_t timergroup0_wdt_clk_conf; 1856 volatile pcr_timergroup1_conf_reg_t timergroup1_conf; 1857 volatile pcr_timergroup1_timer_clk_conf_reg_t timergroup1_timer_clk_conf; 1858 volatile pcr_timergroup1_wdt_clk_conf_reg_t timergroup1_wdt_clk_conf; 1859 volatile pcr_systimer_conf_reg_t systimer_conf; 1860 volatile pcr_systimer_func_clk_conf_reg_t systimer_func_clk_conf; 1861 volatile pcr_twai0_conf_reg_t twai0_conf; 1862 volatile pcr_twai0_func_clk_conf_reg_t twai0_func_clk_conf; 1863 volatile pcr_twai1_conf_reg_t twai1_conf; 1864 volatile pcr_twai1_func_clk_conf_reg_t twai1_func_clk_conf; 1865 volatile pcr_i2s_conf_reg_t i2s_conf; 1866 volatile pcr_i2s_tx_clkm_conf_reg_t i2s_tx_clkm_conf; 1867 volatile pcr_i2s_tx_clkm_div_conf_reg_t i2s_tx_clkm_div_conf; 1868 volatile pcr_i2s_rx_clkm_conf_reg_t i2s_rx_clkm_conf; 1869 volatile pcr_i2s_rx_clkm_div_conf_reg_t i2s_rx_clkm_div_conf; 1870 volatile pcr_saradc_conf_reg_t saradc_conf; 1871 volatile pcr_saradc_clkm_conf_reg_t saradc_clkm_conf; 1872 volatile pcr_tsens_clk_conf_reg_t tsens_clk_conf; 1873 volatile pcr_usb_device_conf_reg_t usb_device_conf; 1874 volatile pcr_intmtx_conf_reg_t intmtx_conf; 1875 volatile pcr_pcnt_conf_reg_t pcnt_conf; 1876 volatile pcr_etm_conf_reg_t etm_conf; 1877 volatile pcr_pwm_conf_reg_t pwm_conf; 1878 volatile pcr_pwm_clk_conf_reg_t pwm_clk_conf; 1879 volatile pcr_parl_io_conf_reg_t parl_io_conf; 1880 volatile pcr_parl_clk_rx_conf_reg_t parl_clk_rx_conf; 1881 volatile pcr_parl_clk_tx_conf_reg_t parl_clk_tx_conf; 1882 volatile pcr_sdio_slave_conf_reg_t sdio_slave_conf; 1883 volatile pcr_pvt_monitor_conf_reg_t pvt_monitor_conf; 1884 volatile pcr_pvt_monitor_func_clk_conf_reg_t pvt_monitor_func_clk_conf; 1885 volatile pcr_gdma_conf_reg_t gdma_conf; 1886 volatile pcr_spi2_conf_reg_t spi2_conf; 1887 volatile pcr_spi2_clkm_conf_reg_t spi2_clkm_conf; 1888 volatile pcr_aes_conf_reg_t aes_conf; 1889 volatile pcr_sha_conf_reg_t sha_conf; 1890 volatile pcr_rsa_conf_reg_t rsa_conf; 1891 volatile pcr_rsa_pd_ctrl_reg_t rsa_pd_ctrl; 1892 volatile pcr_ecc_conf_reg_t ecc_conf; 1893 volatile pcr_ecc_pd_ctrl_reg_t ecc_pd_ctrl; 1894 volatile pcr_ds_conf_reg_t ds_conf; 1895 volatile pcr_hmac_conf_reg_t hmac_conf; 1896 volatile pcr_iomux_conf_reg_t iomux_conf; 1897 volatile pcr_iomux_clk_conf_reg_t iomux_clk_conf; 1898 volatile pcr_mem_monitor_conf_reg_t mem_monitor_conf; 1899 volatile pcr_regdma_conf_reg_t regdma_conf; 1900 volatile pcr_retention_conf_reg_t retention_conf; 1901 volatile pcr_trace_conf_reg_t trace_conf; 1902 volatile pcr_assist_conf_reg_t assist_conf; 1903 volatile pcr_cache_conf_reg_t cache_conf; 1904 volatile pcr_modem_apb_conf_reg_t modem_apb_conf; 1905 volatile pcr_timeout_conf_reg_t timeout_conf; 1906 volatile pcr_sysclk_conf_reg_t sysclk_conf; 1907 volatile pcr_cpu_waiti_conf_reg_t cpu_waiti_conf; 1908 volatile pcr_cpu_freq_conf_reg_t cpu_freq_conf; 1909 volatile pcr_ahb_freq_conf_reg_t ahb_freq_conf; 1910 volatile pcr_apb_freq_conf_reg_t apb_freq_conf; 1911 volatile pcr_sysclk_freq_query_0_reg_t sysclk_freq_query_0; 1912 volatile pcr_pll_div_clk_en_reg_t pll_div_clk_en; 1913 volatile pcr_ctrl_clk_out_en_reg_t ctrl_clk_out_en; 1914 volatile pcr_ctrl_tick_conf_reg_t ctrl_tick_conf; 1915 volatile pcr_ctrl_32k_conf_reg_t ctrl_32k_conf; 1916 volatile pcr_sram_power_conf_reg_t sram_power_conf; 1917 uint32_t reserved_13c[941]; 1918 volatile pcr_reset_event_bypass_reg_t reset_event_bypass; 1919 volatile pcr_fpga_debug_reg_t fpga_debug; 1920 volatile pcr_clock_gate_reg_t clock_gate; 1921 volatile pcr_date_reg_t date; 1922 } pcr_dev_t; 1923 1924 extern pcr_dev_t PCR; 1925 1926 #ifndef __cplusplus 1927 _Static_assert(sizeof(pcr_dev_t) == 0x1000, "Invalid size of pcr_dev_t structure"); 1928 #endif 1929 1930 #ifdef __cplusplus 1931 } 1932 #endif 1933