1 /** 2 * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #pragma once 7 8 #include <stdint.h> 9 #ifdef __cplusplus 10 extern "C" { 11 #endif 12 13 /** Group: Configuration Register */ 14 /** Type of uart0_conf register 15 * UART0 configuration register 16 */ 17 typedef union { 18 struct { 19 /** uart0_clk_en : R/W; bitpos: [0]; default: 1; 20 * Set 1 to enable uart0 apb clock 21 */ 22 uint32_t uart0_clk_en:1; 23 /** uart0_rst_en : R/W; bitpos: [1]; default: 0; 24 * Set 0 to reset uart0 module 25 */ 26 uint32_t uart0_rst_en:1; 27 /** uart0_ready : RO; bitpos: [2]; default: 1; 28 * Query this field after reset uart0 module 29 */ 30 uint32_t uart0_ready:1; 31 uint32_t reserved_3:29; 32 }; 33 uint32_t val; 34 } pcr_uart0_conf_reg_t; 35 36 /** Type of uart0_sclk_conf register 37 * UART0_SCLK configuration register 38 */ 39 typedef union { 40 struct { 41 /** uart0_sclk_div_a : R/W; bitpos: [5:0]; default: 0; 42 * The denominator of the frequency divider factor of the uart0 function clock. 43 */ 44 uint32_t uart0_sclk_div_a:6; 45 /** uart0_sclk_div_b : R/W; bitpos: [11:6]; default: 0; 46 * The numerator of the frequency divider factor of the uart0 function clock. 47 */ 48 uint32_t uart0_sclk_div_b:6; 49 /** uart0_sclk_div_num : R/W; bitpos: [19:12]; default: 0; 50 * The integral part of the frequency divider factor of the uart0 function clock. 51 */ 52 uint32_t uart0_sclk_div_num:8; 53 /** uart0_sclk_sel : R/W; bitpos: [21:20]; default: 3; 54 * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: 55 * FOSC, 3(default): XTAL. 56 */ 57 uint32_t uart0_sclk_sel:2; 58 /** uart0_sclk_en : R/W; bitpos: [22]; default: 1; 59 * Set 1 to enable uart0 function clock 60 */ 61 uint32_t uart0_sclk_en:1; 62 uint32_t reserved_23:9; 63 }; 64 uint32_t val; 65 } pcr_uart0_sclk_conf_reg_t; 66 67 /** Type of uart0_pd_ctrl register 68 * UART0 power control register 69 */ 70 typedef union { 71 struct { 72 uint32_t reserved_0:1; 73 /** uart0_mem_force_pu : R/W; bitpos: [1]; default: 1; 74 * Set this bit to force power down UART0 memory. 75 */ 76 uint32_t uart0_mem_force_pu:1; 77 /** uart0_mem_force_pd : R/W; bitpos: [2]; default: 0; 78 * Set this bit to force power up UART0 memory. 79 */ 80 uint32_t uart0_mem_force_pd:1; 81 uint32_t reserved_3:29; 82 }; 83 uint32_t val; 84 } pcr_uart0_pd_ctrl_reg_t; 85 86 /** Type of uart1_conf register 87 * UART1 configuration register 88 */ 89 typedef union { 90 struct { 91 /** uart1_clk_en : R/W; bitpos: [0]; default: 1; 92 * Set 1 to enable uart1 apb clock 93 */ 94 uint32_t uart1_clk_en:1; 95 /** uart1_rst_en : R/W; bitpos: [1]; default: 0; 96 * Set 0 to reset uart1 module 97 */ 98 uint32_t uart1_rst_en:1; 99 /** uart1_ready : RO; bitpos: [2]; default: 1; 100 * Query this field after reset uart1 module 101 */ 102 uint32_t uart1_ready:1; 103 uint32_t reserved_3:29; 104 }; 105 uint32_t val; 106 } pcr_uart1_conf_reg_t; 107 108 /** Type of uart1_sclk_conf register 109 * UART1_SCLK configuration register 110 */ 111 typedef union { 112 struct { 113 /** uart1_sclk_div_a : R/W; bitpos: [5:0]; default: 0; 114 * The denominator of the frequency divider factor of the uart1 function clock. 115 */ 116 uint32_t uart1_sclk_div_a:6; 117 /** uart1_sclk_div_b : R/W; bitpos: [11:6]; default: 0; 118 * The numerator of the frequency divider factor of the uart1 function clock. 119 */ 120 uint32_t uart1_sclk_div_b:6; 121 /** uart1_sclk_div_num : R/W; bitpos: [19:12]; default: 0; 122 * The integral part of the frequency divider factor of the uart1 function clock. 123 */ 124 uint32_t uart1_sclk_div_num:8; 125 /** uart1_sclk_sel : R/W; bitpos: [21:20]; default: 3; 126 * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: 127 * FOSC, 3(default): XTAL. 128 */ 129 uint32_t uart1_sclk_sel:2; 130 /** uart1_sclk_en : R/W; bitpos: [22]; default: 1; 131 * Set 1 to enable uart0 function clock 132 */ 133 uint32_t uart1_sclk_en:1; 134 uint32_t reserved_23:9; 135 }; 136 uint32_t val; 137 } pcr_uart1_sclk_conf_reg_t; 138 139 /** Type of uart1_pd_ctrl register 140 * UART1 power control register 141 */ 142 typedef union { 143 struct { 144 uint32_t reserved_0:1; 145 /** uart1_mem_force_pu : R/W; bitpos: [1]; default: 1; 146 * Set this bit to force power down UART1 memory. 147 */ 148 uint32_t uart1_mem_force_pu:1; 149 /** uart1_mem_force_pd : R/W; bitpos: [2]; default: 0; 150 * Set this bit to force power up UART1 memory. 151 */ 152 uint32_t uart1_mem_force_pd:1; 153 uint32_t reserved_3:29; 154 }; 155 uint32_t val; 156 } pcr_uart1_pd_ctrl_reg_t; 157 158 /** Type of mspi_conf register 159 * MSPI configuration register 160 */ 161 typedef union { 162 struct { 163 /** mspi_clk_en : R/W; bitpos: [0]; default: 1; 164 * Set 1 to enable mspi clock, include mspi pll clock 165 */ 166 uint32_t mspi_clk_en:1; 167 /** mspi_rst_en : R/W; bitpos: [1]; default: 0; 168 * Set 0 to reset mspi module 169 */ 170 uint32_t mspi_rst_en:1; 171 /** mspi_pll_clk_en : R/W; bitpos: [2]; default: 1; 172 * Set 1 to enable mspi pll clock 173 */ 174 uint32_t mspi_pll_clk_en:1; 175 /** mspi_clk_sel : R/W; bitpos: [4:3]; default: 0; 176 * set this field to select clock-source. 177 */ 178 uint32_t mspi_clk_sel:2; 179 /** mspi_ready : RO; bitpos: [5]; default: 1; 180 * Query this field after reset mspi module 181 */ 182 uint32_t mspi_ready:1; 183 uint32_t reserved_6:26; 184 }; 185 uint32_t val; 186 } pcr_mspi_conf_reg_t; 187 188 /** Type of mspi_clk_conf register 189 * MSPI_CLK configuration register 190 */ 191 typedef union { 192 struct { 193 /** mspi_fast_div_num : R/W; bitpos: [7:0]; default: 0; 194 * Set as one within (0,1,2) to generate div1(default)/div2/div4 of low-speed 195 * clock-source to drive clk_mspi_fast. Only avaiable whe the clck-source is a 196 * low-speed clock-source such as XTAL/FOSC. 197 */ 198 uint32_t mspi_fast_div_num:8; 199 uint32_t reserved_8:24; 200 }; 201 uint32_t val; 202 } pcr_mspi_clk_conf_reg_t; 203 204 /** Type of i2c_conf register 205 * I2C configuration register 206 */ 207 typedef union { 208 struct { 209 /** i2c_clk_en : R/W; bitpos: [0]; default: 1; 210 * Set 1 to enable i2c apb clock 211 */ 212 uint32_t i2c_clk_en:1; 213 /** i2c_rst_en : R/W; bitpos: [1]; default: 0; 214 * Set 0 to reset i2c module 215 */ 216 uint32_t i2c_rst_en:1; 217 /** i2c_ready : RO; bitpos: [2]; default: 1; 218 * Query this field after reset i2c module 219 */ 220 uint32_t i2c_ready:1; 221 uint32_t reserved_3:29; 222 }; 223 uint32_t val; 224 } pcr_i2c_conf_reg_t; 225 226 /** Type of i2c_sclk_conf register 227 * I2C_SCLK configuration register 228 */ 229 typedef union { 230 struct { 231 /** i2c_sclk_div_a : R/W; bitpos: [5:0]; default: 0; 232 * The denominator of the frequency divider factor of the i2c function clock. 233 */ 234 uint32_t i2c_sclk_div_a:6; 235 /** i2c_sclk_div_b : R/W; bitpos: [11:6]; default: 0; 236 * The numerator of the frequency divider factor of the i2c function clock. 237 */ 238 uint32_t i2c_sclk_div_b:6; 239 /** i2c_sclk_div_num : R/W; bitpos: [19:12]; default: 0; 240 * The integral part of the frequency divider factor of the i2c function clock. 241 */ 242 uint32_t i2c_sclk_div_num:8; 243 /** i2c_sclk_sel : R/W; bitpos: [20]; default: 0; 244 * set this field to select clock-source. 0(default): XTAL, 1: FOSC. 245 */ 246 uint32_t i2c_sclk_sel:1; 247 uint32_t reserved_21:1; 248 /** i2c_sclk_en : R/W; bitpos: [22]; default: 1; 249 * Set 1 to enable i2c function clock 250 */ 251 uint32_t i2c_sclk_en:1; 252 uint32_t reserved_23:9; 253 }; 254 uint32_t val; 255 } pcr_i2c_sclk_conf_reg_t; 256 257 /** Type of uhci_conf register 258 * UHCI configuration register 259 */ 260 typedef union { 261 struct { 262 /** uhci_clk_en : R/W; bitpos: [0]; default: 1; 263 * Set 1 to enable uhci clock 264 */ 265 uint32_t uhci_clk_en:1; 266 /** uhci_rst_en : R/W; bitpos: [1]; default: 0; 267 * Set 0 to reset uhci module 268 */ 269 uint32_t uhci_rst_en:1; 270 /** uhci_ready : RO; bitpos: [2]; default: 1; 271 * Query this field after reset uhci module 272 */ 273 uint32_t uhci_ready:1; 274 uint32_t reserved_3:29; 275 }; 276 uint32_t val; 277 } pcr_uhci_conf_reg_t; 278 279 /** Type of rmt_conf register 280 * RMT configuration register 281 */ 282 typedef union { 283 struct { 284 /** rmt_clk_en : R/W; bitpos: [0]; default: 1; 285 * Set 1 to enable rmt apb clock 286 */ 287 uint32_t rmt_clk_en:1; 288 /** rmt_rst_en : R/W; bitpos: [1]; default: 0; 289 * Set 0 to reset rmt module 290 */ 291 uint32_t rmt_rst_en:1; 292 /** rmt_ready : RO; bitpos: [2]; default: 1; 293 * Query this field after reset rmt module 294 */ 295 uint32_t rmt_ready:1; 296 uint32_t reserved_3:29; 297 }; 298 uint32_t val; 299 } pcr_rmt_conf_reg_t; 300 301 /** Type of rmt_sclk_conf register 302 * RMT_SCLK configuration register 303 */ 304 typedef union { 305 struct { 306 /** rmt_sclk_div_a : R/W; bitpos: [5:0]; default: 0; 307 * The denominator of the frequency divider factor of the rmt function clock. 308 */ 309 uint32_t rmt_sclk_div_a:6; 310 /** rmt_sclk_div_b : R/W; bitpos: [11:6]; default: 0; 311 * The numerator of the frequency divider factor of the rmt function clock. 312 */ 313 uint32_t rmt_sclk_div_b:6; 314 /** rmt_sclk_div_num : R/W; bitpos: [19:12]; default: 1; 315 * The integral part of the frequency divider factor of the rmt function clock. 316 */ 317 uint32_t rmt_sclk_div_num:8; 318 /** rmt_sclk_sel : R/W; bitpos: [20]; default: 1; 319 * set this field to select clock-source. 0: do not select anyone clock, 1(default): 320 * 80MHz, 2: FOSC, 3: XTAL. 321 */ 322 uint32_t rmt_sclk_sel:1; 323 /** rmt_sclk_en : R/W; bitpos: [21]; default: 1; 324 * Set 1 to enable rmt function clock 325 */ 326 uint32_t rmt_sclk_en:1; 327 uint32_t reserved_22:10; 328 }; 329 uint32_t val; 330 } pcr_rmt_sclk_conf_reg_t; 331 332 /** Type of ledc_conf register 333 * LEDC configuration register 334 */ 335 typedef union { 336 struct { 337 /** ledc_clk_en : R/W; bitpos: [0]; default: 1; 338 * Set 1 to enable ledc apb clock 339 */ 340 uint32_t ledc_clk_en:1; 341 /** ledc_rst_en : R/W; bitpos: [1]; default: 0; 342 * Set 0 to reset ledc module 343 */ 344 uint32_t ledc_rst_en:1; 345 /** ledc_ready : RO; bitpos: [2]; default: 1; 346 * Query this field after reset ledc module 347 */ 348 uint32_t ledc_ready:1; 349 uint32_t reserved_3:29; 350 }; 351 uint32_t val; 352 } pcr_ledc_conf_reg_t; 353 354 /** Type of ledc_sclk_conf register 355 * LEDC_SCLK configuration register 356 */ 357 typedef union { 358 struct { 359 uint32_t reserved_0:20; 360 /** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0; 361 * set this field to select clock-source. 0(default): do not select anyone clock, 1: 362 * 80MHz, 2: FOSC, 3: XTAL. 363 */ 364 uint32_t ledc_sclk_sel:2; 365 /** ledc_sclk_en : R/W; bitpos: [22]; default: 1; 366 * Set 1 to enable ledc function clock 367 */ 368 uint32_t ledc_sclk_en:1; 369 uint32_t reserved_23:9; 370 }; 371 uint32_t val; 372 } pcr_ledc_sclk_conf_reg_t; 373 374 /** Type of timergroup0_conf register 375 * TIMERGROUP0 configuration register 376 */ 377 typedef union { 378 struct { 379 /** tg0_clk_en : R/W; bitpos: [0]; default: 1; 380 * Set 1 to enable timer_group0 apb clock 381 */ 382 uint32_t tg0_clk_en:1; 383 /** tg0_rst_en : R/W; bitpos: [1]; default: 0; 384 * Set 0 to reset timer_group0 module 385 */ 386 uint32_t tg0_rst_en:1; 387 /** tg0_wdt_ready : RO; bitpos: [2]; default: 1; 388 * Query this field after reset timer_group0 wdt module 389 */ 390 uint32_t tg0_wdt_ready:1; 391 /** tg0_timer0_ready : RO; bitpos: [3]; default: 1; 392 * Query this field after reset timer_group0 timer0 module 393 */ 394 uint32_t tg0_timer0_ready:1; 395 /** tg0_timer1_ready : RO; bitpos: [4]; default: 1; 396 * reserved 397 */ 398 uint32_t tg0_timer1_ready:1; 399 uint32_t reserved_5:27; 400 }; 401 uint32_t val; 402 } pcr_timergroup0_conf_reg_t; 403 404 /** Type of timergroup0_timer_clk_conf register 405 * TIMERGROUP0_TIMER_CLK configuration register 406 */ 407 typedef union { 408 struct { 409 uint32_t reserved_0:20; 410 /** tg0_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; 411 * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: 412 * reserved. 413 */ 414 uint32_t tg0_timer_clk_sel:2; 415 /** tg0_timer_clk_en : R/W; bitpos: [22]; default: 1; 416 * Set 1 to enable timer_group0 timer clock 417 */ 418 uint32_t tg0_timer_clk_en:1; 419 uint32_t reserved_23:9; 420 }; 421 uint32_t val; 422 } pcr_timergroup0_timer_clk_conf_reg_t; 423 424 /** Type of timergroup0_wdt_clk_conf register 425 * TIMERGROUP0_WDT_CLK configuration register 426 */ 427 typedef union { 428 struct { 429 uint32_t reserved_0:20; 430 /** tg0_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; 431 * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: 432 * reserved. 433 */ 434 uint32_t tg0_wdt_clk_sel:2; 435 /** tg0_wdt_clk_en : R/W; bitpos: [22]; default: 1; 436 * Set 1 to enable timer_group0 wdt clock 437 */ 438 uint32_t tg0_wdt_clk_en:1; 439 uint32_t reserved_23:9; 440 }; 441 uint32_t val; 442 } pcr_timergroup0_wdt_clk_conf_reg_t; 443 444 /** Type of timergroup1_conf register 445 * TIMERGROUP1 configuration register 446 */ 447 typedef union { 448 struct { 449 /** tg1_clk_en : R/W; bitpos: [0]; default: 1; 450 * Set 1 to enable timer_group1 apb clock 451 */ 452 uint32_t tg1_clk_en:1; 453 /** tg1_rst_en : R/W; bitpos: [1]; default: 0; 454 * Set 0 to reset timer_group1 module 455 */ 456 uint32_t tg1_rst_en:1; 457 /** tg1_wdt_ready : RO; bitpos: [2]; default: 1; 458 * Query this field after reset timer_group1 wdt module 459 */ 460 uint32_t tg1_wdt_ready:1; 461 /** tg1_timer0_ready : RO; bitpos: [3]; default: 1; 462 * Query this field after reset timer_group1 timer0 module 463 */ 464 uint32_t tg1_timer0_ready:1; 465 /** tg1_timer1_ready : RO; bitpos: [4]; default: 1; 466 * reserved 467 */ 468 uint32_t tg1_timer1_ready:1; 469 uint32_t reserved_5:27; 470 }; 471 uint32_t val; 472 } pcr_timergroup1_conf_reg_t; 473 474 /** Type of timergroup1_timer_clk_conf register 475 * TIMERGROUP1_TIMER_CLK configuration register 476 */ 477 typedef union { 478 struct { 479 uint32_t reserved_0:20; 480 /** tg1_timer_clk_sel : R/W; bitpos: [21:20]; default: 0; 481 * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: 482 * reserved. 483 */ 484 uint32_t tg1_timer_clk_sel:2; 485 /** tg1_timer_clk_en : R/W; bitpos: [22]; default: 1; 486 * Set 1 to enable timer_group1 timer clock 487 */ 488 uint32_t tg1_timer_clk_en:1; 489 uint32_t reserved_23:9; 490 }; 491 uint32_t val; 492 } pcr_timergroup1_timer_clk_conf_reg_t; 493 494 /** Type of timergroup1_wdt_clk_conf register 495 * TIMERGROUP1_WDT_CLK configuration register 496 */ 497 typedef union { 498 struct { 499 uint32_t reserved_0:20; 500 /** tg1_wdt_clk_sel : R/W; bitpos: [21:20]; default: 0; 501 * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: FOSC, 3: 502 * reserved. 503 */ 504 uint32_t tg1_wdt_clk_sel:2; 505 /** tg1_wdt_clk_en : R/W; bitpos: [22]; default: 1; 506 * Set 1 to enable timer_group0 wdt clock 507 */ 508 uint32_t tg1_wdt_clk_en:1; 509 uint32_t reserved_23:9; 510 }; 511 uint32_t val; 512 } pcr_timergroup1_wdt_clk_conf_reg_t; 513 514 /** Type of systimer_conf register 515 * SYSTIMER configuration register 516 */ 517 typedef union { 518 struct { 519 /** systimer_clk_en : R/W; bitpos: [0]; default: 1; 520 * Set 1 to enable systimer apb clock 521 */ 522 uint32_t systimer_clk_en:1; 523 /** systimer_rst_en : R/W; bitpos: [1]; default: 0; 524 * Set 0 to reset systimer module 525 */ 526 uint32_t systimer_rst_en:1; 527 /** systimer_ready : RO; bitpos: [2]; default: 1; 528 * Query this field after reset systimer module 529 */ 530 uint32_t systimer_ready:1; 531 uint32_t reserved_3:29; 532 }; 533 uint32_t val; 534 } pcr_systimer_conf_reg_t; 535 536 /** Type of systimer_func_clk_conf register 537 * SYSTIMER_FUNC_CLK configuration register 538 */ 539 typedef union { 540 struct { 541 uint32_t reserved_0:20; 542 /** systimer_func_clk_sel : R/W; bitpos: [20]; default: 0; 543 * set this field to select clock-source. 0(default): XTAL, 1: FOSC. 544 */ 545 uint32_t systimer_func_clk_sel:1; 546 uint32_t reserved_21:1; 547 /** systimer_func_clk_en : R/W; bitpos: [22]; default: 1; 548 * Set 1 to enable systimer function clock 549 */ 550 uint32_t systimer_func_clk_en:1; 551 uint32_t reserved_23:9; 552 }; 553 uint32_t val; 554 } pcr_systimer_func_clk_conf_reg_t; 555 556 /** Type of twai0_conf register 557 * TWAI0 configuration register 558 */ 559 typedef union { 560 struct { 561 /** twai0_clk_en : R/W; bitpos: [0]; default: 1; 562 * Set 1 to enable twai0 apb clock 563 */ 564 uint32_t twai0_clk_en:1; 565 /** twai0_rst_en : R/W; bitpos: [1]; default: 0; 566 * Set 0 to reset twai0 module 567 */ 568 uint32_t twai0_rst_en:1; 569 /** twai0_ready : RO; bitpos: [2]; default: 1; 570 * Query this field after reset twai0 module 571 */ 572 uint32_t twai0_ready:1; 573 uint32_t reserved_3:29; 574 }; 575 uint32_t val; 576 } pcr_twai0_conf_reg_t; 577 578 /** Type of twai0_func_clk_conf register 579 * TWAI0_FUNC_CLK configuration register 580 */ 581 typedef union { 582 struct { 583 uint32_t reserved_0:20; 584 /** twai0_func_clk_sel : R/W; bitpos: [20]; default: 0; 585 * set this field to select clock-source. 0(default): XTAL, 1: FOSC. 586 */ 587 uint32_t twai0_func_clk_sel:1; 588 uint32_t reserved_21:1; 589 /** twai0_func_clk_en : R/W; bitpos: [22]; default: 1; 590 * Set 1 to enable twai0 function clock 591 */ 592 uint32_t twai0_func_clk_en:1; 593 uint32_t reserved_23:9; 594 }; 595 uint32_t val; 596 } pcr_twai0_func_clk_conf_reg_t; 597 598 /** Type of i2s_conf register 599 * I2S configuration register 600 */ 601 typedef union { 602 struct { 603 /** i2s_clk_en : R/W; bitpos: [0]; default: 1; 604 * Set 1 to enable i2s apb clock 605 */ 606 uint32_t i2s_clk_en:1; 607 /** i2s_rst_en : R/W; bitpos: [1]; default: 0; 608 * Set 0 to reset i2s module 609 */ 610 uint32_t i2s_rst_en:1; 611 /** i2s_rx_ready : RO; bitpos: [2]; default: 1; 612 * Query this field before using i2s rx function, after reset i2s module 613 */ 614 uint32_t i2s_rx_ready:1; 615 /** i2s_tx_ready : RO; bitpos: [3]; default: 1; 616 * Query this field before using i2s tx function, after reset i2s module 617 */ 618 uint32_t i2s_tx_ready:1; 619 uint32_t reserved_4:28; 620 }; 621 uint32_t val; 622 } pcr_i2s_conf_reg_t; 623 624 /** Type of i2s_tx_clkm_conf register 625 * I2S_TX_CLKM configuration register 626 */ 627 typedef union { 628 struct { 629 uint32_t reserved_0:12; 630 /** i2s_tx_clkm_div_num : R/W; bitpos: [19:12]; default: 2; 631 * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be 632 * (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= 633 * a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * 634 * (n+1)-div] + y * (n+1)-div. 635 */ 636 uint32_t i2s_tx_clkm_div_num:8; 637 /** i2s_tx_clkm_sel : R/W; bitpos: [21:20]; default: 0; 638 * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: 639 * I2S_MCLK_in. 640 */ 641 uint32_t i2s_tx_clkm_sel:2; 642 /** i2s_tx_clkm_en : R/W; bitpos: [22]; default: 1; 643 * Set 1 to enable i2s_tx function clock 644 */ 645 uint32_t i2s_tx_clkm_en:1; 646 uint32_t reserved_23:9; 647 }; 648 uint32_t val; 649 } pcr_i2s_tx_clkm_conf_reg_t; 650 651 /** Type of i2s_tx_clkm_div_conf register 652 * I2S_TX_CLKM_DIV configuration register 653 */ 654 typedef union { 655 struct { 656 /** i2s_tx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; 657 * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of 658 * I2S_TX_CLKM_DIV_Z is (a-b). 659 */ 660 uint32_t i2s_tx_clkm_div_z:9; 661 /** i2s_tx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; 662 * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of 663 * I2S_TX_CLKM_DIV_Y is (a%(a-b)). 664 */ 665 uint32_t i2s_tx_clkm_div_y:9; 666 /** i2s_tx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; 667 * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value 668 * of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. 669 */ 670 uint32_t i2s_tx_clkm_div_x:9; 671 /** i2s_tx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; 672 * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of 673 * I2S_TX_CLKM_DIV_YN1 is 1. 674 */ 675 uint32_t i2s_tx_clkm_div_yn1:1; 676 uint32_t reserved_28:4; 677 }; 678 uint32_t val; 679 } pcr_i2s_tx_clkm_div_conf_reg_t; 680 681 /** Type of i2s_rx_clkm_conf register 682 * I2S_RX_CLKM configuration register 683 */ 684 typedef union { 685 struct { 686 uint32_t reserved_0:12; 687 /** i2s_rx_clkm_div_num : R/W; bitpos: [19:12]; default: 2; 688 * Integral I2S clock divider value 689 */ 690 uint32_t i2s_rx_clkm_div_num:8; 691 /** i2s_rx_clkm_sel : R/W; bitpos: [21:20]; default: 0; 692 * Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in. 693 */ 694 uint32_t i2s_rx_clkm_sel:2; 695 /** i2s_rx_clkm_en : R/W; bitpos: [22]; default: 1; 696 * Set 1 to enable i2s_rx function clock 697 */ 698 uint32_t i2s_rx_clkm_en:1; 699 /** i2s_mclk_sel : R/W; bitpos: [23]; default: 0; 700 * This field is used to select master-clock. 0(default): clk_i2s_rx, 1: clk_i2s_tx 701 */ 702 uint32_t i2s_mclk_sel:1; 703 uint32_t reserved_24:8; 704 }; 705 uint32_t val; 706 } pcr_i2s_rx_clkm_conf_reg_t; 707 708 /** Type of i2s_rx_clkm_div_conf register 709 * I2S_RX_CLKM_DIV configuration register 710 */ 711 typedef union { 712 struct { 713 /** i2s_rx_clkm_div_z : R/W; bitpos: [8:0]; default: 0; 714 * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of 715 * I2S_RX_CLKM_DIV_Z is (a-b). 716 */ 717 uint32_t i2s_rx_clkm_div_z:9; 718 /** i2s_rx_clkm_div_y : R/W; bitpos: [17:9]; default: 1; 719 * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of 720 * I2S_RX_CLKM_DIV_Y is (a%(a-b)). 721 */ 722 uint32_t i2s_rx_clkm_div_y:9; 723 /** i2s_rx_clkm_div_x : R/W; bitpos: [26:18]; default: 0; 724 * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value 725 * of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. 726 */ 727 uint32_t i2s_rx_clkm_div_x:9; 728 /** i2s_rx_clkm_div_yn1 : R/W; bitpos: [27]; default: 0; 729 * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of 730 * I2S_RX_CLKM_DIV_YN1 is 1. 731 */ 732 uint32_t i2s_rx_clkm_div_yn1:1; 733 uint32_t reserved_28:4; 734 }; 735 uint32_t val; 736 } pcr_i2s_rx_clkm_div_conf_reg_t; 737 738 /** Type of saradc_conf register 739 * SARADC configuration register 740 */ 741 typedef union { 742 struct { 743 /** saradc_clk_en : R/W; bitpos: [0]; default: 1; 744 * no use 745 */ 746 uint32_t saradc_clk_en:1; 747 /** saradc_rst_en : R/W; bitpos: [1]; default: 0; 748 * Set 0 to reset function_register of saradc module 749 */ 750 uint32_t saradc_rst_en:1; 751 /** saradc_reg_clk_en : R/W; bitpos: [2]; default: 1; 752 * Set 1 to enable saradc apb clock 753 */ 754 uint32_t saradc_reg_clk_en:1; 755 /** saradc_reg_rst_en : R/W; bitpos: [3]; default: 0; 756 * Set 0 to reset apb_register of saradc module 757 */ 758 uint32_t saradc_reg_rst_en:1; 759 uint32_t reserved_4:28; 760 }; 761 uint32_t val; 762 } pcr_saradc_conf_reg_t; 763 764 /** Type of saradc_clkm_conf register 765 * SARADC_CLKM configuration register 766 */ 767 typedef union { 768 struct { 769 /** saradc_clkm_div_a : R/W; bitpos: [5:0]; default: 0; 770 * The denominator of the frequency divider factor of the saradc function clock. 771 */ 772 uint32_t saradc_clkm_div_a:6; 773 /** saradc_clkm_div_b : R/W; bitpos: [11:6]; default: 0; 774 * The numerator of the frequency divider factor of the saradc function clock. 775 */ 776 uint32_t saradc_clkm_div_b:6; 777 /** saradc_clkm_div_num : R/W; bitpos: [19:12]; default: 4; 778 * The integral part of the frequency divider factor of the saradc function clock. 779 */ 780 uint32_t saradc_clkm_div_num:8; 781 /** saradc_clkm_sel : R/W; bitpos: [21:20]; default: 0; 782 * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: 783 * reserved. 784 */ 785 uint32_t saradc_clkm_sel:2; 786 /** saradc_clkm_en : R/W; bitpos: [22]; default: 1; 787 * Set 1 to enable saradc function clock 788 */ 789 uint32_t saradc_clkm_en:1; 790 uint32_t reserved_23:9; 791 }; 792 uint32_t val; 793 } pcr_saradc_clkm_conf_reg_t; 794 795 /** Type of tsens_clk_conf register 796 * TSENS_CLK configuration register 797 */ 798 typedef union { 799 struct { 800 uint32_t reserved_0:20; 801 /** tsens_clk_sel : R/W; bitpos: [20]; default: 0; 802 * set this field to select clock-source. 0(default): FOSC, 1: XTAL. 803 */ 804 uint32_t tsens_clk_sel:1; 805 uint32_t reserved_21:1; 806 /** tsens_clk_en : R/W; bitpos: [22]; default: 1; 807 * Set 1 to enable tsens clock 808 */ 809 uint32_t tsens_clk_en:1; 810 /** tsens_rst_en : R/W; bitpos: [23]; default: 0; 811 * Set 0 to reset tsens module 812 */ 813 uint32_t tsens_rst_en:1; 814 uint32_t reserved_24:8; 815 }; 816 uint32_t val; 817 } pcr_tsens_clk_conf_reg_t; 818 819 /** Type of usb_device_conf register 820 * USB_DEVICE configuration register 821 */ 822 typedef union { 823 struct { 824 /** usb_device_clk_en : R/W; bitpos: [0]; default: 1; 825 * Set 1 to enable usb_device clock 826 */ 827 uint32_t usb_device_clk_en:1; 828 /** usb_device_rst_en : R/W; bitpos: [1]; default: 0; 829 * Set 0 to reset usb_device module 830 */ 831 uint32_t usb_device_rst_en:1; 832 /** usb_device_ready : RO; bitpos: [2]; default: 1; 833 * Query this field after reset usb_device module 834 */ 835 uint32_t usb_device_ready:1; 836 uint32_t reserved_3:29; 837 }; 838 uint32_t val; 839 } pcr_usb_device_conf_reg_t; 840 841 /** Type of intmtx_conf register 842 * INTMTX configuration register 843 */ 844 typedef union { 845 struct { 846 /** intmtx_clk_en : R/W; bitpos: [0]; default: 1; 847 * Set 1 to enable intmtx clock 848 */ 849 uint32_t intmtx_clk_en:1; 850 /** intmtx_rst_en : R/W; bitpos: [1]; default: 0; 851 * Set 0 to reset intmtx module 852 */ 853 uint32_t intmtx_rst_en:1; 854 /** intmtx_ready : RO; bitpos: [2]; default: 1; 855 * Query this field after reset intmtx module 856 */ 857 uint32_t intmtx_ready:1; 858 uint32_t reserved_3:29; 859 }; 860 uint32_t val; 861 } pcr_intmtx_conf_reg_t; 862 863 /** Type of pcnt_conf register 864 * PCNT configuration register 865 */ 866 typedef union { 867 struct { 868 /** pcnt_clk_en : R/W; bitpos: [0]; default: 1; 869 * Set 1 to enable pcnt clock 870 */ 871 uint32_t pcnt_clk_en:1; 872 /** pcnt_rst_en : R/W; bitpos: [1]; default: 0; 873 * Set 0 to reset pcnt module 874 */ 875 uint32_t pcnt_rst_en:1; 876 /** pcnt_ready : RO; bitpos: [2]; default: 1; 877 * Query this field after reset pcnt module 878 */ 879 uint32_t pcnt_ready:1; 880 uint32_t reserved_3:29; 881 }; 882 uint32_t val; 883 } pcr_pcnt_conf_reg_t; 884 885 /** Type of etm_conf register 886 * ETM configuration register 887 */ 888 typedef union { 889 struct { 890 /** etm_clk_en : R/W; bitpos: [0]; default: 1; 891 * Set 1 to enable etm clock 892 */ 893 uint32_t etm_clk_en:1; 894 /** etm_rst_en : R/W; bitpos: [1]; default: 0; 895 * Set 0 to reset etm module 896 */ 897 uint32_t etm_rst_en:1; 898 /** etm_ready : RO; bitpos: [2]; default: 1; 899 * Query this field after reset etm module 900 */ 901 uint32_t etm_ready:1; 902 uint32_t reserved_3:29; 903 }; 904 uint32_t val; 905 } pcr_etm_conf_reg_t; 906 907 /** Type of pwm_conf register 908 * PWM configuration register 909 */ 910 typedef union { 911 struct { 912 /** pwm_clk_en : R/W; bitpos: [0]; default: 1; 913 * Set 1 to enable pwm clock 914 */ 915 uint32_t pwm_clk_en:1; 916 /** pwm_rst_en : R/W; bitpos: [1]; default: 0; 917 * Set 0 to reset pwm module 918 */ 919 uint32_t pwm_rst_en:1; 920 /** pwm_ready : RO; bitpos: [2]; default: 1; 921 * Query this field after reset pwm module 922 */ 923 uint32_t pwm_ready:1; 924 uint32_t reserved_3:29; 925 }; 926 uint32_t val; 927 } pcr_pwm_conf_reg_t; 928 929 /** Type of pwm_clk_conf register 930 * PWM_CLK configuration register 931 */ 932 typedef union { 933 struct { 934 uint32_t reserved_0:12; 935 /** pwm_div_num : R/W; bitpos: [19:12]; default: 4; 936 * The integral part of the frequency divider factor of the pwm function clock. 937 */ 938 uint32_t pwm_div_num:8; 939 /** pwm_clkm_sel : R/W; bitpos: [21:20]; default: 0; 940 * set this field to select clock-source. 0(default): do not select anyone clock, 1: 941 * 160MHz, 2: XTAL, 3: FOSC. 942 */ 943 uint32_t pwm_clkm_sel:2; 944 /** pwm_clkm_en : R/W; bitpos: [22]; default: 1; 945 * set this field as 1 to activate pwm clkm. 946 */ 947 uint32_t pwm_clkm_en:1; 948 uint32_t reserved_23:9; 949 }; 950 uint32_t val; 951 } pcr_pwm_clk_conf_reg_t; 952 953 /** Type of parl_io_conf register 954 * PARL_IO configuration register 955 */ 956 typedef union { 957 struct { 958 /** parl_clk_en : R/W; bitpos: [0]; default: 1; 959 * Set 1 to enable parl apb clock 960 */ 961 uint32_t parl_clk_en:1; 962 /** parl_rst_en : R/W; bitpos: [1]; default: 0; 963 * Set 0 to reset parl apb reg 964 */ 965 uint32_t parl_rst_en:1; 966 /** parl_ready : RO; bitpos: [2]; default: 1; 967 * Query this field after reset parl module 968 */ 969 uint32_t parl_ready:1; 970 uint32_t reserved_3:29; 971 }; 972 uint32_t val; 973 } pcr_parl_io_conf_reg_t; 974 975 /** Type of parl_clk_rx_conf register 976 * PARL_CLK_RX configuration register 977 */ 978 typedef union { 979 struct { 980 /** parl_clk_rx_div_num : R/W; bitpos: [15:0]; default: 0; 981 * The integral part of the frequency divider factor of the parl rx clock. 982 */ 983 uint32_t parl_clk_rx_div_num:16; 984 /** parl_clk_rx_sel : R/W; bitpos: [17:16]; default: 0; 985 * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: 986 * user clock from pad. 987 */ 988 uint32_t parl_clk_rx_sel:2; 989 /** parl_clk_rx_en : R/W; bitpos: [18]; default: 1; 990 * Set 1 to enable parl rx clock 991 */ 992 uint32_t parl_clk_rx_en:1; 993 /** parl_rx_rst_en : R/W; bitpos: [19]; default: 0; 994 * Set 0 to reset parl rx module 995 */ 996 uint32_t parl_rx_rst_en:1; 997 uint32_t reserved_20:12; 998 }; 999 uint32_t val; 1000 } pcr_parl_clk_rx_conf_reg_t; 1001 1002 /** Type of parl_clk_tx_conf register 1003 * PARL_CLK_TX configuration register 1004 */ 1005 typedef union { 1006 struct { 1007 /** parl_clk_tx_div_num : R/W; bitpos: [15:0]; default: 0; 1008 * The integral part of the frequency divider factor of the parl tx clock. 1009 */ 1010 uint32_t parl_clk_tx_div_num:16; 1011 /** parl_clk_tx_sel : R/W; bitpos: [17:16]; default: 0; 1012 * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: FOSC, 3: 1013 * user clock from pad. 1014 */ 1015 uint32_t parl_clk_tx_sel:2; 1016 /** parl_clk_tx_en : R/W; bitpos: [18]; default: 1; 1017 * Set 1 to enable parl tx clock 1018 */ 1019 uint32_t parl_clk_tx_en:1; 1020 /** parl_tx_rst_en : R/W; bitpos: [19]; default: 0; 1021 * Set 0 to reset parl tx module 1022 */ 1023 uint32_t parl_tx_rst_en:1; 1024 uint32_t reserved_20:12; 1025 }; 1026 uint32_t val; 1027 } pcr_parl_clk_tx_conf_reg_t; 1028 1029 /** Type of pvt_monitor_conf register 1030 * PVT_MONITOR configuration register 1031 */ 1032 typedef union { 1033 struct { 1034 /** pvt_monitor_clk_en : R/W; bitpos: [0]; default: 1; 1035 * Set 1 to enable apb clock of pvt module 1036 */ 1037 uint32_t pvt_monitor_clk_en:1; 1038 /** pvt_monitor_rst_en : R/W; bitpos: [1]; default: 0; 1039 * Set 0 to reset all pvt monitor module 1040 */ 1041 uint32_t pvt_monitor_rst_en:1; 1042 /** pvt_monitor_site1_clk_en : R/W; bitpos: [2]; default: 1; 1043 * Set 1 to enable function clock of modem pvt module 1044 */ 1045 uint32_t pvt_monitor_site1_clk_en:1; 1046 /** pvt_monitor_site2_clk_en : R/W; bitpos: [3]; default: 1; 1047 * Set 1 to enable function clock of cpu pvt module 1048 */ 1049 uint32_t pvt_monitor_site2_clk_en:1; 1050 /** pvt_monitor_site3_clk_en : R/W; bitpos: [4]; default: 1; 1051 * Set 1 to enable function clock of hp_peri pvt module 1052 */ 1053 uint32_t pvt_monitor_site3_clk_en:1; 1054 uint32_t reserved_5:27; 1055 }; 1056 uint32_t val; 1057 } pcr_pvt_monitor_conf_reg_t; 1058 1059 /** Type of pvt_monitor_func_clk_conf register 1060 * PVT_MONITOR function clock configuration register 1061 */ 1062 typedef union { 1063 struct { 1064 /** pvt_monitor_func_clk_div_num : R/W; bitpos: [3:0]; default: 0; 1065 * The integral part of the frequency divider factor of the pvt_monitor function clock. 1066 */ 1067 uint32_t pvt_monitor_func_clk_div_num:4; 1068 uint32_t reserved_4:16; 1069 /** pvt_monitor_func_clk_sel : R/W; bitpos: [20]; default: 0; 1070 * set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived by SPLL 1071 * divided by 3. 1072 */ 1073 uint32_t pvt_monitor_func_clk_sel:1; 1074 uint32_t reserved_21:1; 1075 /** pvt_monitor_func_clk_en : R/W; bitpos: [22]; default: 1; 1076 * Set 1 to enable source clock of pvt sitex 1077 */ 1078 uint32_t pvt_monitor_func_clk_en:1; 1079 uint32_t reserved_23:9; 1080 }; 1081 uint32_t val; 1082 } pcr_pvt_monitor_func_clk_conf_reg_t; 1083 1084 /** Type of gdma_conf register 1085 * GDMA configuration register 1086 */ 1087 typedef union { 1088 struct { 1089 /** gdma_clk_en : R/W; bitpos: [0]; default: 1; 1090 * Set 1 to enable gdma clock 1091 */ 1092 uint32_t gdma_clk_en:1; 1093 /** gdma_rst_en : R/W; bitpos: [1]; default: 0; 1094 * Set 0 to reset gdma module 1095 */ 1096 uint32_t gdma_rst_en:1; 1097 uint32_t reserved_2:30; 1098 }; 1099 uint32_t val; 1100 } pcr_gdma_conf_reg_t; 1101 1102 /** Type of spi2_conf register 1103 * SPI2 configuration register 1104 */ 1105 typedef union { 1106 struct { 1107 /** spi2_clk_en : R/W; bitpos: [0]; default: 1; 1108 * Set 1 to enable spi2 apb clock 1109 */ 1110 uint32_t spi2_clk_en:1; 1111 /** spi2_rst_en : R/W; bitpos: [1]; default: 0; 1112 * Set 0 to reset spi2 module 1113 */ 1114 uint32_t spi2_rst_en:1; 1115 /** spi2_ready : RO; bitpos: [2]; default: 1; 1116 * Query this field after reset spi2 module 1117 */ 1118 uint32_t spi2_ready:1; 1119 uint32_t reserved_3:29; 1120 }; 1121 uint32_t val; 1122 } pcr_spi2_conf_reg_t; 1123 1124 /** Type of spi2_clkm_conf register 1125 * SPI2_CLKM configuration register 1126 */ 1127 typedef union { 1128 struct { 1129 uint32_t reserved_0:20; 1130 /** spi2_clkm_sel : R/W; bitpos: [21:20]; default: 0; 1131 * set this field to select clock-source. 0(default): XTAL, 1: 48MHz, 2: FOSC, 3: 1132 * reserved. 1133 */ 1134 uint32_t spi2_clkm_sel:2; 1135 /** spi2_clkm_en : R/W; bitpos: [22]; default: 1; 1136 * Set 1 to enable spi2 function clock 1137 */ 1138 uint32_t spi2_clkm_en:1; 1139 uint32_t reserved_23:9; 1140 }; 1141 uint32_t val; 1142 } pcr_spi2_clkm_conf_reg_t; 1143 1144 /** Type of aes_conf register 1145 * AES configuration register 1146 */ 1147 typedef union { 1148 struct { 1149 /** aes_clk_en : R/W; bitpos: [0]; default: 1; 1150 * Set 1 to enable aes clock 1151 */ 1152 uint32_t aes_clk_en:1; 1153 /** aes_rst_en : R/W; bitpos: [1]; default: 0; 1154 * Set 0 to reset aes module 1155 */ 1156 uint32_t aes_rst_en:1; 1157 /** aes_ready : RO; bitpos: [2]; default: 1; 1158 * Query this field after reset aes module 1159 */ 1160 uint32_t aes_ready:1; 1161 uint32_t reserved_3:29; 1162 }; 1163 uint32_t val; 1164 } pcr_aes_conf_reg_t; 1165 1166 /** Type of sha_conf register 1167 * SHA configuration register 1168 */ 1169 typedef union { 1170 struct { 1171 /** sha_clk_en : R/W; bitpos: [0]; default: 1; 1172 * Set 1 to enable sha clock 1173 */ 1174 uint32_t sha_clk_en:1; 1175 /** sha_rst_en : R/W; bitpos: [1]; default: 0; 1176 * Set 0 to reset sha module 1177 */ 1178 uint32_t sha_rst_en:1; 1179 /** sha_ready : RO; bitpos: [2]; default: 1; 1180 * Query this field after reset sha module 1181 */ 1182 uint32_t sha_ready:1; 1183 uint32_t reserved_3:29; 1184 }; 1185 uint32_t val; 1186 } pcr_sha_conf_reg_t; 1187 1188 /** Type of rsa_conf register 1189 * RSA configuration register 1190 */ 1191 typedef union { 1192 struct { 1193 /** rsa_clk_en : R/W; bitpos: [0]; default: 1; 1194 * Set 1 to enable rsa clock 1195 */ 1196 uint32_t rsa_clk_en:1; 1197 /** rsa_rst_en : R/W; bitpos: [1]; default: 0; 1198 * Set 0 to reset rsa module 1199 */ 1200 uint32_t rsa_rst_en:1; 1201 /** rsa_ready : RO; bitpos: [2]; default: 1; 1202 * Query this field after reset rsa module 1203 */ 1204 uint32_t rsa_ready:1; 1205 uint32_t reserved_3:29; 1206 }; 1207 uint32_t val; 1208 } pcr_rsa_conf_reg_t; 1209 1210 /** Type of rsa_pd_ctrl register 1211 * RSA power control register 1212 */ 1213 typedef union { 1214 struct { 1215 /** rsa_mem_pd : R/W; bitpos: [0]; default: 0; 1216 * Set this bit to power down rsa internal memory. 1217 */ 1218 uint32_t rsa_mem_pd:1; 1219 /** rsa_mem_force_pu : R/W; bitpos: [1]; default: 1; 1220 * Set this bit to force power up rsa internal memory 1221 */ 1222 uint32_t rsa_mem_force_pu:1; 1223 /** rsa_mem_force_pd : R/W; bitpos: [2]; default: 0; 1224 * Set this bit to force power down rsa internal memory. 1225 */ 1226 uint32_t rsa_mem_force_pd:1; 1227 uint32_t reserved_3:29; 1228 }; 1229 uint32_t val; 1230 } pcr_rsa_pd_ctrl_reg_t; 1231 1232 /** Type of ecc_conf register 1233 * ECC configuration register 1234 */ 1235 typedef union { 1236 struct { 1237 /** ecc_clk_en : R/W; bitpos: [0]; default: 1; 1238 * Set 1 to enable ecc clock 1239 */ 1240 uint32_t ecc_clk_en:1; 1241 /** ecc_rst_en : R/W; bitpos: [1]; default: 0; 1242 * Set 0 to reset ecc module 1243 */ 1244 uint32_t ecc_rst_en:1; 1245 /** ecc_ready : RO; bitpos: [2]; default: 1; 1246 * Query this field after reset ecc module 1247 */ 1248 uint32_t ecc_ready:1; 1249 uint32_t reserved_3:29; 1250 }; 1251 uint32_t val; 1252 } pcr_ecc_conf_reg_t; 1253 1254 /** Type of ecc_pd_ctrl register 1255 * ECC power control register 1256 */ 1257 typedef union { 1258 struct { 1259 /** ecc_mem_pd : R/W; bitpos: [0]; default: 0; 1260 * Set this bit to power down ecc internal memory. 1261 */ 1262 uint32_t ecc_mem_pd:1; 1263 /** ecc_mem_force_pu : R/W; bitpos: [1]; default: 1; 1264 * Set this bit to force power up ecc internal memory 1265 */ 1266 uint32_t ecc_mem_force_pu:1; 1267 /** ecc_mem_force_pd : R/W; bitpos: [2]; default: 0; 1268 * Set this bit to force power down ecc internal memory. 1269 */ 1270 uint32_t ecc_mem_force_pd:1; 1271 uint32_t reserved_3:29; 1272 }; 1273 uint32_t val; 1274 } pcr_ecc_pd_ctrl_reg_t; 1275 1276 /** Type of ds_conf register 1277 * DS configuration register 1278 */ 1279 typedef union { 1280 struct { 1281 /** ds_clk_en : R/W; bitpos: [0]; default: 1; 1282 * Set 1 to enable ds clock 1283 */ 1284 uint32_t ds_clk_en:1; 1285 /** ds_rst_en : R/W; bitpos: [1]; default: 0; 1286 * Set 0 to reset ds module 1287 */ 1288 uint32_t ds_rst_en:1; 1289 /** ds_ready : RO; bitpos: [2]; default: 1; 1290 * Query this field after reset ds module 1291 */ 1292 uint32_t ds_ready:1; 1293 uint32_t reserved_3:29; 1294 }; 1295 uint32_t val; 1296 } pcr_ds_conf_reg_t; 1297 1298 /** Type of hmac_conf register 1299 * HMAC configuration register 1300 */ 1301 typedef union { 1302 struct { 1303 /** hmac_clk_en : R/W; bitpos: [0]; default: 1; 1304 * Set 1 to enable hmac clock 1305 */ 1306 uint32_t hmac_clk_en:1; 1307 /** hmac_rst_en : R/W; bitpos: [1]; default: 0; 1308 * Set 0 to reset hmac module 1309 */ 1310 uint32_t hmac_rst_en:1; 1311 /** hmac_ready : RO; bitpos: [2]; default: 1; 1312 * Query this field after reset hmac module 1313 */ 1314 uint32_t hmac_ready:1; 1315 uint32_t reserved_3:29; 1316 }; 1317 uint32_t val; 1318 } pcr_hmac_conf_reg_t; 1319 1320 /** Type of ecdsa_conf register 1321 * ECDSA configuration register 1322 */ 1323 typedef union { 1324 struct { 1325 /** ecdsa_clk_en : R/W; bitpos: [0]; default: 1; 1326 * Set 1 to enable ecdsa clock 1327 */ 1328 uint32_t ecdsa_clk_en:1; 1329 /** ecdsa_rst_en : R/W; bitpos: [1]; default: 0; 1330 * Set 0 to reset ecdsa module 1331 */ 1332 uint32_t ecdsa_rst_en:1; 1333 /** ecdsa_ready : RO; bitpos: [2]; default: 1; 1334 * Query this field after reset ecdsa module 1335 */ 1336 uint32_t ecdsa_ready:1; 1337 uint32_t reserved_3:29; 1338 }; 1339 uint32_t val; 1340 } pcr_ecdsa_conf_reg_t; 1341 1342 /** Type of iomux_conf register 1343 * IOMUX configuration register 1344 */ 1345 typedef union { 1346 struct { 1347 /** iomux_clk_en : R/W; bitpos: [0]; default: 1; 1348 * Set 1 to enable iomux apb clock 1349 */ 1350 uint32_t iomux_clk_en:1; 1351 /** iomux_rst_en : R/W; bitpos: [1]; default: 0; 1352 * Set 0 to reset iomux module 1353 */ 1354 uint32_t iomux_rst_en:1; 1355 uint32_t reserved_2:30; 1356 }; 1357 uint32_t val; 1358 } pcr_iomux_conf_reg_t; 1359 1360 /** Type of iomux_clk_conf register 1361 * IOMUX_CLK configuration register 1362 */ 1363 typedef union { 1364 struct { 1365 uint32_t reserved_0:20; 1366 /** iomux_func_clk_sel : R/W; bitpos: [21:20]; default: 0; 1367 * set this field to select clock-source. 0: do not select anyone clock, 1: 80MHz, 2: 1368 * FOSC, 3(default): XTAL. 1369 */ 1370 uint32_t iomux_func_clk_sel:2; 1371 /** iomux_func_clk_en : R/W; bitpos: [22]; default: 1; 1372 * Set 1 to enable iomux function clock 1373 */ 1374 uint32_t iomux_func_clk_en:1; 1375 uint32_t reserved_23:9; 1376 }; 1377 uint32_t val; 1378 } pcr_iomux_clk_conf_reg_t; 1379 1380 /** Type of mem_monitor_conf register 1381 * MEM_MONITOR configuration register 1382 */ 1383 typedef union { 1384 struct { 1385 /** mem_monitor_clk_en : R/W; bitpos: [0]; default: 1; 1386 * Set 1 to enable mem_monitor clock 1387 */ 1388 uint32_t mem_monitor_clk_en:1; 1389 /** mem_monitor_rst_en : R/W; bitpos: [1]; default: 0; 1390 * Set 0 to reset mem_monitor module 1391 */ 1392 uint32_t mem_monitor_rst_en:1; 1393 /** mem_monitor_ready : RO; bitpos: [2]; default: 1; 1394 * Query this field after reset mem_monitor module 1395 */ 1396 uint32_t mem_monitor_ready:1; 1397 uint32_t reserved_3:29; 1398 }; 1399 uint32_t val; 1400 } pcr_mem_monitor_conf_reg_t; 1401 1402 /** Type of regdma_conf register 1403 * REGDMA configuration register 1404 */ 1405 typedef union { 1406 struct { 1407 /** regdma_clk_en : R/W; bitpos: [0]; default: 0; 1408 * Set 1 to enable regdma clock 1409 */ 1410 uint32_t regdma_clk_en:1; 1411 /** regdma_rst_en : R/W; bitpos: [1]; default: 0; 1412 * Set 0 to reset regdma module 1413 */ 1414 uint32_t regdma_rst_en:1; 1415 uint32_t reserved_2:30; 1416 }; 1417 uint32_t val; 1418 } pcr_regdma_conf_reg_t; 1419 1420 /** Type of trace_conf register 1421 * TRACE configuration register 1422 */ 1423 typedef union { 1424 struct { 1425 /** trace_clk_en : R/W; bitpos: [0]; default: 1; 1426 * Set 1 to enable trace clock 1427 */ 1428 uint32_t trace_clk_en:1; 1429 /** trace_rst_en : R/W; bitpos: [1]; default: 0; 1430 * Set 0 to reset trace module 1431 */ 1432 uint32_t trace_rst_en:1; 1433 uint32_t reserved_2:30; 1434 }; 1435 uint32_t val; 1436 } pcr_trace_conf_reg_t; 1437 1438 /** Type of assist_conf register 1439 * ASSIST configuration register 1440 */ 1441 typedef union { 1442 struct { 1443 /** assist_clk_en : R/W; bitpos: [0]; default: 1; 1444 * Set 1 to enable assist clock 1445 */ 1446 uint32_t assist_clk_en:1; 1447 /** assist_rst_en : R/W; bitpos: [1]; default: 0; 1448 * Set 0 to reset assist module 1449 */ 1450 uint32_t assist_rst_en:1; 1451 uint32_t reserved_2:30; 1452 }; 1453 uint32_t val; 1454 } pcr_assist_conf_reg_t; 1455 1456 /** Type of cache_conf register 1457 * CACHE configuration register 1458 */ 1459 typedef union { 1460 struct { 1461 /** cache_clk_en : R/W; bitpos: [0]; default: 1; 1462 * Set 1 to enable cache clock 1463 */ 1464 uint32_t cache_clk_en:1; 1465 /** cache_rst_en : R/W; bitpos: [1]; default: 0; 1466 * Set 0 to reset cache module 1467 */ 1468 uint32_t cache_rst_en:1; 1469 uint32_t reserved_2:30; 1470 }; 1471 uint32_t val; 1472 } pcr_cache_conf_reg_t; 1473 1474 /** Type of modem_conf register 1475 * MODEM_APB configuration register 1476 */ 1477 typedef union { 1478 struct { 1479 /** modem_clk_sel : R/W; bitpos: [0]; default: 0; 1480 * xxxx 1481 */ 1482 uint32_t modem_clk_sel:1; 1483 /** modem_clk_en : R/W; bitpos: [1]; default: 1; 1484 * xxxx 1485 */ 1486 uint32_t modem_clk_en:1; 1487 /** modem_rst_en : R/W; bitpos: [2]; default: 0; 1488 * Set this file as 1 to reset modem-subsystem. 1489 */ 1490 uint32_t modem_rst_en:1; 1491 uint32_t reserved_3:29; 1492 }; 1493 uint32_t val; 1494 } pcr_modem_conf_reg_t; 1495 1496 /** Type of timeout_conf register 1497 * TIMEOUT configuration register 1498 */ 1499 typedef union { 1500 struct { 1501 uint32_t reserved_0:1; 1502 /** cpu_timeout_rst_en : R/W; bitpos: [1]; default: 0; 1503 * Set 0 to reset cpu_peri timeout module 1504 */ 1505 uint32_t cpu_timeout_rst_en:1; 1506 /** hp_timeout_rst_en : R/W; bitpos: [2]; default: 0; 1507 * Set 0 to reset hp_peri timeout module and hp_modem timeout module 1508 */ 1509 uint32_t hp_timeout_rst_en:1; 1510 uint32_t reserved_3:29; 1511 }; 1512 uint32_t val; 1513 } pcr_timeout_conf_reg_t; 1514 1515 /** Type of sysclk_conf register 1516 * SYSCLK configuration register 1517 */ 1518 typedef union { 1519 struct { 1520 /** ls_div_num : HRO; bitpos: [7:0]; default: 0; 1521 * clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed 1522 * clock-source such as XTAL/FOSC. 1523 */ 1524 uint32_t ls_div_num:8; 1525 /** hs_div_num : HRO; bitpos: [15:8]; default: 2; 1526 * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. 1527 */ 1528 uint32_t hs_div_num:8; 1529 /** soc_clk_sel : R/W; bitpos: [17:16]; default: 0; 1530 * This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved. 1531 */ 1532 uint32_t soc_clk_sel:2; 1533 uint32_t reserved_18:6; 1534 /** clk_xtal_freq : RO; bitpos: [30:24]; default: 32; 1535 * This field indicates the frequency(MHz) of XTAL. 1536 */ 1537 uint32_t clk_xtal_freq:7; 1538 uint32_t reserved_31:1; 1539 }; 1540 uint32_t val; 1541 } pcr_sysclk_conf_reg_t; 1542 1543 /** Type of cpu_waiti_conf register 1544 * CPU_WAITI configuration register 1545 */ 1546 typedef union { 1547 struct { 1548 /** cpuperiod_sel : HRO; bitpos: [1:0]; default: 1; 1549 * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM 1550 */ 1551 uint32_t cpuperiod_sel:2; 1552 /** pll_freq_sel : HRO; bitpos: [2]; default: 1; 1553 * Reserved. This filed has been replaced by PCR_CPU_DIV_NUM 1554 */ 1555 uint32_t pll_freq_sel:1; 1556 /** cpu_wait_mode_force_on : R/W; bitpos: [3]; default: 1; 1557 * Set 1 to force cpu_waiti_clk enable. 1558 */ 1559 uint32_t cpu_wait_mode_force_on:1; 1560 /** cpu_waiti_delay_num : R/W; bitpos: [7:4]; default: 0; 1561 * This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk 1562 * will close 1563 */ 1564 uint32_t cpu_waiti_delay_num:4; 1565 uint32_t reserved_8:24; 1566 }; 1567 uint32_t val; 1568 } pcr_cpu_waiti_conf_reg_t; 1569 1570 /** Type of cpu_freq_conf register 1571 * CPU_FREQ configuration register 1572 */ 1573 typedef union { 1574 struct { 1575 /** cpu_div_num : R/W; bitpos: [7:0]; default: 0; 1576 * Set this field to generate clk_cpu drived by clk_hproot. The clk_cpu is 1577 * div1(default)/div2/div4 of clk_hproot. This field is only avaliable for low-speed 1578 * clock-source such as XTAL/FOSC, and should be used together with PCR_AHB_DIV_NUM. 1579 */ 1580 uint32_t cpu_div_num:8; 1581 uint32_t reserved_8:24; 1582 }; 1583 uint32_t val; 1584 } pcr_cpu_freq_conf_reg_t; 1585 1586 /** Type of ahb_freq_conf register 1587 * AHB_FREQ configuration register 1588 */ 1589 typedef union { 1590 struct { 1591 /** ahb_div_num : R/W; bitpos: [7:0]; default: 0; 1592 * Set this field to generate clk_ahb drived by clk_hproot. The clk_ahb is 1593 * div1(default)/div2/div4/div8 of clk_hproot. This field is only avaliable for 1594 * low-speed clock-source such as XTAL/FOSC, and should be used together with 1595 * PCR_CPU_DIV_NUM. 1596 */ 1597 uint32_t ahb_div_num:8; 1598 uint32_t reserved_8:24; 1599 }; 1600 uint32_t val; 1601 } pcr_ahb_freq_conf_reg_t; 1602 1603 /** Type of apb_freq_conf register 1604 * APB_FREQ configuration register 1605 */ 1606 typedef union { 1607 struct { 1608 /** apb_decrease_div_num : R/W; bitpos: [7:0]; default: 0; 1609 * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be 1610 * automatically down to clk_apb_decrease only when no access is on apb-bus, and will 1611 * recover to the previous frequency when a new access appears on apb-bus. Set as one 1612 * within (0,1,3) to set clk_apb_decrease as div1/div2/div4(default) of clk_ahb. Note 1613 * that enable this function will reduce performance. Users can set this field as zero 1614 * to disable the auto-decrease-apb-freq function. By default, this function is 1615 * disable. 1616 */ 1617 uint32_t apb_decrease_div_num:8; 1618 /** apb_div_num : R/W; bitpos: [15:8]; default: 0; 1619 * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The clk_apb is 1620 * div1(default)/div2/div4 of clk_ahb. 1621 */ 1622 uint32_t apb_div_num:8; 1623 uint32_t reserved_16:16; 1624 }; 1625 uint32_t val; 1626 } pcr_apb_freq_conf_reg_t; 1627 1628 /** Type of pll_div_clk_en register 1629 * SPLL DIV clock-gating configuration register 1630 */ 1631 typedef union { 1632 struct { 1633 /** pll_240m_clk_en : R/W; bitpos: [0]; default: 1; 1634 * This field is used to open 96 MHz clock (SPLL) drived from SPLL. 0: close, 1: 1635 * open(default). Only avaliable when high-speed clock-source SPLL is active. 1636 */ 1637 uint32_t pll_240m_clk_en:1; 1638 /** pll_160m_clk_en : R/W; bitpos: [1]; default: 1; 1639 * This field is used to open 64 MHz clock (div3 of SPLL) drived from SPLL. 0: close, 1640 * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. 1641 */ 1642 uint32_t pll_160m_clk_en:1; 1643 /** pll_120m_clk_en : R/W; bitpos: [2]; default: 1; 1644 * This field is used to open 48 MHz clock (div4 of SPLL) drived from SPLL. 0: close, 1645 * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. 1646 */ 1647 uint32_t pll_120m_clk_en:1; 1648 /** pll_80m_clk_en : R/W; bitpos: [3]; default: 1; 1649 * This field is used to open 32 MHz clock (div6 of SPLL) drived from SPLL. 0: close, 1650 * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. 1651 */ 1652 uint32_t pll_80m_clk_en:1; 1653 /** pll_48m_clk_en : R/W; bitpos: [4]; default: 1; 1654 * This field is used to open 16 MHz clock (div10 of SPLL) drived from SPLL. 0: close, 1655 * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. 1656 */ 1657 uint32_t pll_48m_clk_en:1; 1658 /** pll_40m_clk_en : R/W; bitpos: [5]; default: 1; 1659 * This field is used to open 8 MHz clock (div12 of SPLL) drived from SPLL. 0: close, 1660 * 1: open(default). Only avaliable when high-speed clock-source SPLL is active. 1661 */ 1662 uint32_t pll_40m_clk_en:1; 1663 uint32_t reserved_6:26; 1664 }; 1665 uint32_t val; 1666 } pcr_pll_div_clk_en_reg_t; 1667 1668 /** Type of ctrl_clk_out_en register 1669 * CLK_OUT_EN configuration register 1670 */ 1671 typedef union { 1672 struct { 1673 /** clk8_oen : R/W; bitpos: [0]; default: 1; 1674 * Set 1 to enable 8m clock 1675 */ 1676 uint32_t clk8_oen:1; 1677 /** clk16_oen : R/W; bitpos: [1]; default: 1; 1678 * Set 1 to enable 16m clock 1679 */ 1680 uint32_t clk16_oen:1; 1681 /** clk32_oen : R/W; bitpos: [2]; default: 1; 1682 * Set 1 to enable 32m clock 1683 */ 1684 uint32_t clk32_oen:1; 1685 /** clk_adc_inf_oen : R/W; bitpos: [3]; default: 1; 1686 * Reserved 1687 */ 1688 uint32_t clk_adc_inf_oen:1; 1689 /** clk_dfm_inf_oen : R/W; bitpos: [4]; default: 1; 1690 * Reserved 1691 */ 1692 uint32_t clk_dfm_inf_oen:1; 1693 /** clk_sdm_mod_oen : R/W; bitpos: [5]; default: 1; 1694 * Reserved 1695 */ 1696 uint32_t clk_sdm_mod_oen:1; 1697 /** clk_xtal_oen : R/W; bitpos: [6]; default: 1; 1698 * Set 1 to enable xtal clock 1699 */ 1700 uint32_t clk_xtal_oen:1; 1701 uint32_t reserved_7:25; 1702 }; 1703 uint32_t val; 1704 } pcr_ctrl_clk_out_en_reg_t; 1705 1706 /** Type of ctrl_tick_conf register 1707 * TICK configuration register 1708 */ 1709 typedef union { 1710 struct { 1711 /** xtal_tick_num : R/W; bitpos: [7:0]; default: 39; 1712 * ******* Description *********** 1713 */ 1714 uint32_t xtal_tick_num:8; 1715 /** fosc_tick_num : R/W; bitpos: [15:8]; default: 7; 1716 * ******* Description *********** 1717 */ 1718 uint32_t fosc_tick_num:8; 1719 /** tick_enable : R/W; bitpos: [16]; default: 1; 1720 * ******* Description *********** 1721 */ 1722 uint32_t tick_enable:1; 1723 /** rst_tick_cnt : R/W; bitpos: [17]; default: 0; 1724 * ******* Description *********** 1725 */ 1726 uint32_t rst_tick_cnt:1; 1727 uint32_t reserved_18:14; 1728 }; 1729 uint32_t val; 1730 } pcr_ctrl_tick_conf_reg_t; 1731 1732 /** Type of ctrl_32k_conf register 1733 * 32KHz clock configuration register 1734 */ 1735 typedef union { 1736 struct { 1737 /** 32k_sel : R/W; bitpos: [1:0]; default: 0; 1738 * This field indicates which one 32KHz clock will be used by timergroup. 0: 1739 * OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. 1740 */ 1741 uint32_t clk_32k_sel:2; 1742 /** 32k_modem_sel : R/W; bitpos: [3:2]; default: 0; 1743 * This field indicates which one 32KHz clock will be used by MODEM_SYSTEM. 0: 1744 * OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. 1745 */ 1746 uint32_t clk_32k_modem_sel:2; 1747 uint32_t reserved_4:28; 1748 }; 1749 uint32_t val; 1750 } pcr_ctrl_32k_conf_reg_t; 1751 1752 /** Type of sram_power_conf_0 register 1753 * HP SRAM/ROM configuration register 1754 */ 1755 typedef union { 1756 struct { 1757 uint32_t reserved_0:13; 1758 /** rom_force_pu : R/W; bitpos: [14:13]; default: 3; 1759 * Set this bit to force power up ROM 1760 */ 1761 uint32_t rom_force_pu:2; 1762 /** rom_force_pd : R/W; bitpos: [16:15]; default: 0; 1763 * Set this bit to force power down ROM. 1764 */ 1765 uint32_t rom_force_pd:2; 1766 /** rom_clkgate_force_on : R/W; bitpos: [18:17]; default: 0; 1767 * 1: Force to open the clock and bypass the gate-clock when accessing the ROM. 0: A 1768 * gate-clock will be used when accessing the ROM. 1769 */ 1770 uint32_t rom_clkgate_force_on:2; 1771 uint32_t reserved_19:13; 1772 }; 1773 uint32_t val; 1774 } pcr_sram_power_conf_0_reg_t; 1775 1776 /** Type of sram_power_conf_1 register 1777 * HP SRAM/ROM configuration register 1778 */ 1779 typedef union { 1780 struct { 1781 /** sram_force_pu : R/W; bitpos: [4:0]; default: 31; 1782 * Set this bit to force power up SRAM 1783 */ 1784 uint32_t sram_force_pu:5; 1785 uint32_t reserved_5:5; 1786 /** sram_force_pd : R/W; bitpos: [14:10]; default: 0; 1787 * Set this bit to force power down SRAM. 1788 */ 1789 uint32_t sram_force_pd:5; 1790 uint32_t reserved_15:10; 1791 /** sram_clkgate_force_on : R/W; bitpos: [29:25]; default: 0; 1792 * 1: Force to open the clock and bypass the gate-clock when accessing the SRAM. 0: A 1793 * gate-clock will be used when accessing the SRAM. 1794 */ 1795 uint32_t sram_clkgate_force_on:5; 1796 uint32_t reserved_30:2; 1797 }; 1798 uint32_t val; 1799 } pcr_sram_power_conf_1_reg_t; 1800 1801 /** Type of sec_conf register 1802 * xxxx 1803 */ 1804 typedef union { 1805 struct { 1806 /** sec_clk_sel : R/W; bitpos: [1:0]; default: 0; 1807 * xxxx 1808 */ 1809 uint32_t sec_clk_sel:2; 1810 uint32_t reserved_2:30; 1811 }; 1812 uint32_t val; 1813 } pcr_sec_conf_reg_t; 1814 1815 /** Type of adc_inv_phase_conf register 1816 * xxxx 1817 */ 1818 typedef union { 1819 struct { 1820 /** clk_adc_inv_phase_ena : R/W; bitpos: [0]; default: 0; 1821 * xxxx 1822 */ 1823 uint32_t clk_adc_inv_phase_ena:1; 1824 uint32_t reserved_1:31; 1825 }; 1826 uint32_t val; 1827 } pcr_adc_inv_phase_conf_reg_t; 1828 1829 /** Type of sdm_inv_phase_conf register 1830 * xxxx 1831 */ 1832 typedef union { 1833 struct { 1834 /** clk_sdm_inv_phase_ena : R/W; bitpos: [0]; default: 0; 1835 * xxxx 1836 */ 1837 uint32_t clk_sdm_inv_phase_ena:1; 1838 /** clk_sdm_inv_phase_sel : R/W; bitpos: [3:1]; default: 0; 1839 * xxxx 1840 */ 1841 uint32_t clk_sdm_inv_phase_sel:3; 1842 uint32_t reserved_4:28; 1843 }; 1844 uint32_t val; 1845 } pcr_sdm_inv_phase_conf_reg_t; 1846 1847 /** Type of bus_clk_update register 1848 * xxxx 1849 */ 1850 typedef union { 1851 struct { 1852 /** bus_clock_update : R/W/WTC; bitpos: [0]; default: 0; 1853 * xxxx 1854 */ 1855 uint32_t bus_clock_update:1; 1856 uint32_t reserved_1:31; 1857 }; 1858 uint32_t val; 1859 } pcr_bus_clk_update_reg_t; 1860 1861 /** Type of sar_clk_div register 1862 * xxxx 1863 */ 1864 typedef union { 1865 struct { 1866 /** sar2_clk_div_num : R/W; bitpos: [7:0]; default: 4; 1867 * xxxx 1868 */ 1869 uint32_t sar2_clk_div_num:8; 1870 /** sar1_clk_div_num : R/W; bitpos: [15:8]; default: 4; 1871 * xxxx 1872 */ 1873 uint32_t sar1_clk_div_num:8; 1874 uint32_t reserved_16:16; 1875 }; 1876 uint32_t val; 1877 } pcr_sar_clk_div_reg_t; 1878 1879 /** Type of pwdet_sar_clk_conf register 1880 * xxxx 1881 */ 1882 typedef union { 1883 struct { 1884 /** pwdet_sar_clk_div_num : R/W; bitpos: [7:0]; default: 7; 1885 * xxxx 1886 */ 1887 uint32_t pwdet_sar_clk_div_num:8; 1888 /** pwdet_sar_reader_en : R/W; bitpos: [8]; default: 1; 1889 * xxxx 1890 */ 1891 uint32_t pwdet_sar_reader_en:1; 1892 uint32_t reserved_9:23; 1893 }; 1894 uint32_t val; 1895 } pcr_pwdet_sar_clk_conf_reg_t; 1896 1897 /** Type of reset_event_bypass register 1898 * reset event bypass backdoor configuration register 1899 */ 1900 typedef union { 1901 struct { 1902 /** reset_event_bypass_apm : R/W; bitpos: [0]; default: 0; 1903 * This field is used to control reset event relationship for 1904 * tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only be reset 1905 * by power-reset. some reset event will be bypass. 0: tee_reg/apm_reg/hp_system_reg 1906 * will not only be reset by power-reset, but also some reset event. 1907 */ 1908 uint32_t reset_event_bypass_apm:1; 1909 /** reset_event_bypass : R/W; bitpos: [1]; default: 1; 1910 * This field is used to control reset event relationship for system-bus. 1: system 1911 * bus (including arbiter/router) will only be reset by power-reset. some reset event 1912 * will be bypass. 0: system bus (including arbiter/router) will not only be reset by 1913 * power-reset, but also some reset event. 1914 */ 1915 uint32_t reset_event_bypass:1; 1916 uint32_t reserved_2:30; 1917 }; 1918 uint32_t val; 1919 } pcr_reset_event_bypass_reg_t; 1920 1921 /** Type of clock_gate register 1922 * PCR clock gating configure register 1923 */ 1924 typedef union { 1925 struct { 1926 /** clk_en : R/W; bitpos: [0]; default: 0; 1927 * Set this bit as 1 to force on clock gating. 1928 */ 1929 uint32_t clk_en:1; 1930 uint32_t reserved_1:31; 1931 }; 1932 uint32_t val; 1933 } pcr_clock_gate_reg_t; 1934 1935 1936 /** Group: Frequency Statistics Register */ 1937 /** Type of sysclk_freq_query_0 register 1938 * SYSCLK frequency query 0 register 1939 */ 1940 typedef union { 1941 struct { 1942 /** fosc_freq : HRO; bitpos: [7:0]; default: 8; 1943 * This field indicates the frequency(MHz) of FOSC. 1944 */ 1945 uint32_t fosc_freq:8; 1946 /** pll_freq : HRO; bitpos: [17:8]; default: 96; 1947 * This field indicates the frequency(MHz) of SPLL. 1948 */ 1949 uint32_t pll_freq:10; 1950 uint32_t reserved_18:14; 1951 }; 1952 uint32_t val; 1953 } pcr_sysclk_freq_query_0_reg_t; 1954 1955 1956 /** Group: FPGA Debug Register */ 1957 /** Type of fpga_debug register 1958 * fpga debug register 1959 */ 1960 typedef union { 1961 struct { 1962 /** fpga_debug : R/W; bitpos: [31:0]; default: 4294967295; 1963 * Only used in fpga debug. 1964 */ 1965 uint32_t fpga_debug:32; 1966 }; 1967 uint32_t val; 1968 } pcr_fpga_debug_reg_t; 1969 1970 1971 /** Group: Version Register */ 1972 /** Type of date register 1973 * Date register. 1974 */ 1975 typedef union { 1976 struct { 1977 /** date : R/W; bitpos: [27:0]; default: 35717248; 1978 * PCR version information. 1979 */ 1980 uint32_t date:28; 1981 uint32_t reserved_28:4; 1982 }; 1983 uint32_t val; 1984 } pcr_date_reg_t; 1985 1986 1987 /** 1988 * @brief The struct of I2C configuration registers 1989 */ 1990 typedef struct { 1991 pcr_i2c_conf_reg_t i2c_conf; 1992 pcr_i2c_sclk_conf_reg_t i2c_sclk_conf; 1993 } pcr_i2c_reg_t; 1994 1995 typedef struct { 1996 volatile pcr_uart0_conf_reg_t uart0_conf; 1997 volatile pcr_uart0_sclk_conf_reg_t uart0_sclk_conf; 1998 volatile pcr_uart0_pd_ctrl_reg_t uart0_pd_ctrl; 1999 volatile pcr_uart1_conf_reg_t uart1_conf; 2000 volatile pcr_uart1_sclk_conf_reg_t uart1_sclk_conf; 2001 volatile pcr_uart1_pd_ctrl_reg_t uart1_pd_ctrl; 2002 volatile pcr_mspi_conf_reg_t mspi_conf; 2003 volatile pcr_mspi_clk_conf_reg_t mspi_clk_conf; 2004 volatile pcr_i2c_reg_t i2c[2]; 2005 volatile pcr_uhci_conf_reg_t uhci_conf; 2006 volatile pcr_rmt_conf_reg_t rmt_conf; 2007 volatile pcr_rmt_sclk_conf_reg_t rmt_sclk_conf; 2008 volatile pcr_ledc_conf_reg_t ledc_conf; 2009 volatile pcr_ledc_sclk_conf_reg_t ledc_sclk_conf; 2010 volatile pcr_timergroup0_conf_reg_t timergroup0_conf; 2011 volatile pcr_timergroup0_timer_clk_conf_reg_t timergroup0_timer_clk_conf; 2012 volatile pcr_timergroup0_wdt_clk_conf_reg_t timergroup0_wdt_clk_conf; 2013 volatile pcr_timergroup1_conf_reg_t timergroup1_conf; 2014 volatile pcr_timergroup1_timer_clk_conf_reg_t timergroup1_timer_clk_conf; 2015 volatile pcr_timergroup1_wdt_clk_conf_reg_t timergroup1_wdt_clk_conf; 2016 volatile pcr_systimer_conf_reg_t systimer_conf; 2017 volatile pcr_systimer_func_clk_conf_reg_t systimer_func_clk_conf; 2018 volatile pcr_twai0_conf_reg_t twai0_conf; 2019 volatile pcr_twai0_func_clk_conf_reg_t twai0_func_clk_conf; 2020 volatile pcr_i2s_conf_reg_t i2s_conf; 2021 volatile pcr_i2s_tx_clkm_conf_reg_t i2s_tx_clkm_conf; 2022 volatile pcr_i2s_tx_clkm_div_conf_reg_t i2s_tx_clkm_div_conf; 2023 volatile pcr_i2s_rx_clkm_conf_reg_t i2s_rx_clkm_conf; 2024 volatile pcr_i2s_rx_clkm_div_conf_reg_t i2s_rx_clkm_div_conf; 2025 volatile pcr_saradc_conf_reg_t saradc_conf; 2026 volatile pcr_saradc_clkm_conf_reg_t saradc_clkm_conf; 2027 volatile pcr_tsens_clk_conf_reg_t tsens_clk_conf; 2028 volatile pcr_usb_device_conf_reg_t usb_device_conf; 2029 volatile pcr_intmtx_conf_reg_t intmtx_conf; 2030 volatile pcr_pcnt_conf_reg_t pcnt_conf; 2031 volatile pcr_etm_conf_reg_t etm_conf; 2032 volatile pcr_pwm_conf_reg_t pwm_conf; 2033 volatile pcr_pwm_clk_conf_reg_t pwm_clk_conf; 2034 volatile pcr_parl_io_conf_reg_t parl_io_conf; 2035 volatile pcr_parl_clk_rx_conf_reg_t parl_clk_rx_conf; 2036 volatile pcr_parl_clk_tx_conf_reg_t parl_clk_tx_conf; 2037 volatile pcr_pvt_monitor_conf_reg_t pvt_monitor_conf; 2038 volatile pcr_pvt_monitor_func_clk_conf_reg_t pvt_monitor_func_clk_conf; 2039 volatile pcr_gdma_conf_reg_t gdma_conf; 2040 volatile pcr_spi2_conf_reg_t spi2_conf; 2041 volatile pcr_spi2_clkm_conf_reg_t spi2_clkm_conf; 2042 volatile pcr_aes_conf_reg_t aes_conf; 2043 volatile pcr_sha_conf_reg_t sha_conf; 2044 volatile pcr_rsa_conf_reg_t rsa_conf; 2045 volatile pcr_rsa_pd_ctrl_reg_t rsa_pd_ctrl; 2046 volatile pcr_ecc_conf_reg_t ecc_conf; 2047 volatile pcr_ecc_pd_ctrl_reg_t ecc_pd_ctrl; 2048 volatile pcr_ds_conf_reg_t ds_conf; 2049 volatile pcr_hmac_conf_reg_t hmac_conf; 2050 volatile pcr_ecdsa_conf_reg_t ecdsa_conf; 2051 volatile pcr_iomux_conf_reg_t iomux_conf; 2052 volatile pcr_iomux_clk_conf_reg_t iomux_clk_conf; 2053 volatile pcr_mem_monitor_conf_reg_t mem_monitor_conf; 2054 volatile pcr_regdma_conf_reg_t regdma_conf; 2055 volatile pcr_trace_conf_reg_t trace_conf; 2056 volatile pcr_assist_conf_reg_t assist_conf; 2057 volatile pcr_cache_conf_reg_t cache_conf; 2058 volatile pcr_modem_conf_reg_t modem_conf; 2059 volatile pcr_timeout_conf_reg_t timeout_conf; 2060 volatile pcr_sysclk_conf_reg_t sysclk_conf; 2061 volatile pcr_cpu_waiti_conf_reg_t cpu_waiti_conf; 2062 volatile pcr_cpu_freq_conf_reg_t cpu_freq_conf; 2063 volatile pcr_ahb_freq_conf_reg_t ahb_freq_conf; 2064 volatile pcr_apb_freq_conf_reg_t apb_freq_conf; 2065 volatile pcr_sysclk_freq_query_0_reg_t sysclk_freq_query_0; 2066 volatile pcr_pll_div_clk_en_reg_t pll_div_clk_en; 2067 volatile pcr_ctrl_clk_out_en_reg_t ctrl_clk_out_en; 2068 volatile pcr_ctrl_tick_conf_reg_t ctrl_tick_conf; 2069 volatile pcr_ctrl_32k_conf_reg_t ctrl_32k_conf; 2070 volatile pcr_sram_power_conf_0_reg_t sram_power_conf_0; 2071 volatile pcr_sram_power_conf_1_reg_t sram_power_conf_1; 2072 volatile pcr_sec_conf_reg_t sec_conf; 2073 volatile pcr_adc_inv_phase_conf_reg_t adc_inv_phase_conf; 2074 volatile pcr_sdm_inv_phase_conf_reg_t sdm_inv_phase_conf; 2075 volatile pcr_bus_clk_update_reg_t bus_clk_update; 2076 volatile pcr_sar_clk_div_reg_t sar_clk_div; 2077 volatile pcr_pwdet_sar_clk_conf_reg_t pwdet_sar_clk_conf; 2078 uint32_t reserved_154[935]; 2079 volatile pcr_reset_event_bypass_reg_t reset_event_bypass; 2080 volatile pcr_fpga_debug_reg_t fpga_debug; 2081 volatile pcr_clock_gate_reg_t clock_gate; 2082 volatile pcr_date_reg_t date; 2083 } pcr_dev_t; 2084 2085 extern pcr_dev_t PCR; 2086 2087 #ifndef __cplusplus 2088 _Static_assert(sizeof(pcr_dev_t) == 0x1000, "Invalid size of pcr_dev_t structure"); 2089 #endif 2090 2091 #ifdef __cplusplus 2092 } 2093 #endif 2094
