1 /*
2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef ARCH_HELPERS_H
8 #define ARCH_HELPERS_H
9
10 #include <cdefs.h>
11 #include <stdbool.h>
12 #include <stdint.h>
13 #include <string.h>
14
15 #include <arch.h>
16
17 /**********************************************************************
18 * Macros which create inline functions to read or write CPU system
19 * registers
20 *********************************************************************/
21
22 #define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
23 static inline u_register_t read_ ## _name(void) \
24 { \
25 u_register_t v; \
26 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
27 return v; \
28 }
29
30 #define _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name) \
31 static inline u_register_t read_ ## _name(void) \
32 { \
33 u_register_t v; \
34 __asm__ ("mrs %0, " #_reg_name : "=r" (v)); \
35 return v; \
36 }
37
38 #define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
39 static inline void write_ ## _name(u_register_t v) \
40 { \
41 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
42 }
43
44 #define SYSREG_WRITE_CONST(reg_name, v) \
45 __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v))
46
47 /* Define read function for system register */
48 #define DEFINE_SYSREG_READ_FUNC(_name) \
49 _DEFINE_SYSREG_READ_FUNC(_name, _name)
50
51 /* Define read & write function for system register */
52 #define DEFINE_SYSREG_RW_FUNCS(_name) \
53 _DEFINE_SYSREG_READ_FUNC(_name, _name) \
54 _DEFINE_SYSREG_WRITE_FUNC(_name, _name)
55
56 /* Define read & write function for renamed system register */
57 #define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \
58 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
59 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
60
61 /* Define read function for renamed system register */
62 #define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \
63 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name)
64
65 /* Define write function for renamed system register */
66 #define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \
67 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
68
69 /* Define read function for ID register (w/o volatile qualifier) */
70 #define DEFINE_IDREG_READ_FUNC(_name) \
71 _DEFINE_SYSREG_READ_FUNC_NV(_name, _name)
72
73 /* Define read function for renamed ID register (w/o volatile qualifier) */
74 #define DEFINE_RENAME_IDREG_READ_FUNC(_name, _reg_name) \
75 _DEFINE_SYSREG_READ_FUNC_NV(_name, _reg_name)
76
77 /**********************************************************************
78 * Macros to create inline functions for system instructions
79 *********************************************************************/
80
81 /* Define function for simple system instruction */
82 #define DEFINE_SYSOP_FUNC(_op) \
83 static inline void _op(void) \
84 { \
85 __asm__ (#_op); \
86 }
87
88 /* Define function for system instruction with register parameter */
89 #define DEFINE_SYSOP_PARAM_FUNC(_op) \
90 static inline void _op(uint64_t v) \
91 { \
92 __asm__ (#_op " %0" : : "r" (v)); \
93 }
94
95 /* Define function for system instruction with type specifier */
96 #define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
97 static inline void _op ## _type(void) \
98 { \
99 __asm__ (#_op " " #_type : : : "memory"); \
100 }
101
102 /* Define function for system instruction with register parameter */
103 #define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
104 static inline void _op ## _type(uint64_t v) \
105 { \
106 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \
107 }
108
109 /*******************************************************************************
110 * TLB maintenance accessor prototypes
111 ******************************************************************************/
112
113 #if ERRATA_A57_813419 || ERRATA_A76_1286807
114 /*
115 * Define function for TLBI instruction with type specifier that implements
116 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of
117 * Cortex-A76.
118 */
119 #define DEFINE_TLBIOP_ERRATA_TYPE_FUNC(_type)\
120 static inline void tlbi ## _type(void) \
121 { \
122 __asm__("tlbi " #_type "\n" \
123 "dsb ish\n" \
124 "tlbi " #_type); \
125 }
126
127 /*
128 * Define function for TLBI instruction with register parameter that implements
129 * the workaround for errata 813419 of Cortex-A57 or errata 1286807 of
130 * Cortex-A76.
131 */
132 #define DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(_type) \
133 static inline void tlbi ## _type(uint64_t v) \
134 { \
135 __asm__("tlbi " #_type ", %0\n" \
136 "dsb ish\n" \
137 "tlbi " #_type ", %0" : : "r" (v)); \
138 }
139 #endif /* ERRATA_A57_813419 */
140
141 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
142 /*
143 * Define function for DC instruction with register parameter that enables
144 * the workaround for errata 819472, 824069 and 827319 of Cortex-A53.
145 */
146 #define DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(_name, _type) \
147 static inline void dc ## _name(uint64_t v) \
148 { \
149 __asm__("dc " #_type ", %0" : : "r" (v)); \
150 }
151 #endif /* ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319 */
152
153 #if ERRATA_A57_813419
154 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
155 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
156 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
157 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
158 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3)
159 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is)
160 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
161 #elif ERRATA_A76_1286807
162 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1)
163 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle1is)
164 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2)
165 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle2is)
166 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3)
167 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(alle3is)
168 DEFINE_TLBIOP_ERRATA_TYPE_FUNC(vmalle1)
169 #else
170 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
171 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
172 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
173 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
174 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3)
175 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is)
176 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
177 #endif
178
179 #if ERRATA_A57_813419
180 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
181 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
182 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
183 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
184 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is)
185 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is)
186 #elif ERRATA_A76_1286807
187 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaae1is)
188 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vaale1is)
189 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae2is)
190 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale2is)
191 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vae3is)
192 DEFINE_TLBIOP_ERRATA_TYPE_PARAM_FUNC(vale3is)
193 #else
194 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
195 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
196 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
197 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
198 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is)
199 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is)
200 #endif
201
202 /*******************************************************************************
203 * Cache maintenance accessor prototypes
204 ******************************************************************************/
205 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw)
206 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw)
207 #if ERRATA_A53_827319
208 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(csw, cisw)
209 #else
210 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw)
211 #endif
212 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
213 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvac, civac)
214 #else
215 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac)
216 #endif
217 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac)
218 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac)
219 #if ERRATA_A53_819472 || ERRATA_A53_824069 || ERRATA_A53_827319
220 DEFINE_DCOP_ERRATA_A53_TYPE_PARAM_FUNC(cvau, civac)
221 #else
222 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau)
223 #endif
224 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva)
225
226 /*******************************************************************************
227 * Address translation accessor prototypes
228 ******************************************************************************/
229 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r)
230 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w)
231 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r)
232 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w)
233 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r)
234 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r)
235 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r)
236
237 /*******************************************************************************
238 * Strip Pointer Authentication Code
239 ******************************************************************************/
240 DEFINE_SYSOP_PARAM_FUNC(xpaci)
241
242 void flush_dcache_range(uintptr_t addr, size_t size);
243 void flush_dcache_to_popa_range(uintptr_t addr, size_t size);
244 void clean_dcache_range(uintptr_t addr, size_t size);
245 void inv_dcache_range(uintptr_t addr, size_t size);
246 bool is_dcache_enabled(void);
247
248 void dcsw_op_louis(u_register_t op_type);
249 void dcsw_op_all(u_register_t op_type);
250
251 void disable_mmu_el1(void);
252 void disable_mmu_el3(void);
253 void disable_mpu_el2(void);
254 void disable_mmu_icache_el1(void);
255 void disable_mmu_icache_el3(void);
256 void disable_mpu_icache_el2(void);
257
258 /*******************************************************************************
259 * Misc. accessor prototypes
260 ******************************************************************************/
261
262 #define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val)
263 #define write_daifset(val) SYSREG_WRITE_CONST(daifset, val)
264
265 DEFINE_SYSREG_RW_FUNCS(par_el1)
DEFINE_IDREG_READ_FUNC(id_pfr1_el1)266 DEFINE_IDREG_READ_FUNC(id_pfr1_el1)
267 DEFINE_IDREG_READ_FUNC(id_aa64isar0_el1)
268 DEFINE_IDREG_READ_FUNC(id_aa64isar1_el1)
269 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64isar2_el1, ID_AA64ISAR2_EL1)
270 DEFINE_IDREG_READ_FUNC(id_aa64pfr0_el1)
271 DEFINE_IDREG_READ_FUNC(id_aa64pfr1_el1)
272 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64pfr2_el1, ID_AA64PFR2_EL1)
273 DEFINE_IDREG_READ_FUNC(id_aa64dfr0_el1)
274 DEFINE_IDREG_READ_FUNC(id_afr0_el1)
275 DEFINE_SYSREG_READ_FUNC(CurrentEl)
276 DEFINE_SYSREG_READ_FUNC(ctr_el0)
277 DEFINE_SYSREG_RW_FUNCS(daif)
278 DEFINE_SYSREG_RW_FUNCS(spsr_el1)
279 DEFINE_SYSREG_RW_FUNCS(spsr_el2)
280 DEFINE_SYSREG_RW_FUNCS(spsr_el3)
281 DEFINE_SYSREG_RW_FUNCS(elr_el1)
282 DEFINE_SYSREG_RW_FUNCS(elr_el2)
283 DEFINE_SYSREG_RW_FUNCS(elr_el3)
284 DEFINE_SYSREG_RW_FUNCS(mdccsr_el0)
285 DEFINE_SYSREG_RW_FUNCS(dbgdtrrx_el0)
286 DEFINE_SYSREG_RW_FUNCS(dbgdtrtx_el0)
287 DEFINE_SYSREG_RW_FUNCS(sp_el1)
288 DEFINE_SYSREG_RW_FUNCS(sp_el2)
289
290 DEFINE_SYSOP_FUNC(wfi)
291 DEFINE_SYSOP_FUNC(wfe)
292 DEFINE_SYSOP_FUNC(sev)
293 DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
294 DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
295 DEFINE_SYSOP_TYPE_FUNC(dmb, st)
296 DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
297 DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
298 DEFINE_SYSOP_TYPE_FUNC(dsb, osh)
299 DEFINE_SYSOP_TYPE_FUNC(dsb, nsh)
300 DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
301 DEFINE_SYSOP_TYPE_FUNC(dsb, oshst)
302 DEFINE_SYSOP_TYPE_FUNC(dmb, oshld)
303 DEFINE_SYSOP_TYPE_FUNC(dmb, oshst)
304 DEFINE_SYSOP_TYPE_FUNC(dmb, osh)
305 DEFINE_SYSOP_TYPE_FUNC(dmb, nshld)
306 DEFINE_SYSOP_TYPE_FUNC(dmb, nshst)
307 DEFINE_SYSOP_TYPE_FUNC(dmb, nsh)
308 DEFINE_SYSOP_TYPE_FUNC(dmb, ishld)
309 DEFINE_SYSOP_TYPE_FUNC(dmb, ishst)
310 DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
311 DEFINE_SYSOP_FUNC(isb)
312
313 static inline void enable_irq(void)
314 {
315 /*
316 * The compiler memory barrier will prevent the compiler from
317 * scheduling non-volatile memory access after the write to the
318 * register.
319 *
320 * This could happen if some initialization code issues non-volatile
321 * accesses to an area used by an interrupt handler, in the assumption
322 * that it is safe as the interrupts are disabled at the time it does
323 * that (according to program order). However, non-volatile accesses
324 * are not necessarily in program order relatively with volatile inline
325 * assembly statements (and volatile accesses).
326 */
327 COMPILER_BARRIER();
328 write_daifclr(DAIF_IRQ_BIT);
329 isb();
330 }
331
enable_fiq(void)332 static inline void enable_fiq(void)
333 {
334 COMPILER_BARRIER();
335 write_daifclr(DAIF_FIQ_BIT);
336 isb();
337 }
338
enable_serror(void)339 static inline void enable_serror(void)
340 {
341 COMPILER_BARRIER();
342 write_daifclr(DAIF_ABT_BIT);
343 isb();
344 }
345
enable_debug_exceptions(void)346 static inline void enable_debug_exceptions(void)
347 {
348 COMPILER_BARRIER();
349 write_daifclr(DAIF_DBG_BIT);
350 isb();
351 }
352
disable_irq(void)353 static inline void disable_irq(void)
354 {
355 COMPILER_BARRIER();
356 write_daifset(DAIF_IRQ_BIT);
357 isb();
358 }
359
disable_fiq(void)360 static inline void disable_fiq(void)
361 {
362 COMPILER_BARRIER();
363 write_daifset(DAIF_FIQ_BIT);
364 isb();
365 }
366
disable_serror(void)367 static inline void disable_serror(void)
368 {
369 COMPILER_BARRIER();
370 write_daifset(DAIF_ABT_BIT);
371 isb();
372 }
373
disable_debug_exceptions(void)374 static inline void disable_debug_exceptions(void)
375 {
376 COMPILER_BARRIER();
377 write_daifset(DAIF_DBG_BIT);
378 isb();
379 }
380
381 void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
382 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
383
384 /*******************************************************************************
385 * System register accessor prototypes
386 ******************************************************************************/
387 DEFINE_IDREG_READ_FUNC(midr_el1)
DEFINE_SYSREG_READ_FUNC(mpidr_el1)388 DEFINE_SYSREG_READ_FUNC(mpidr_el1)
389 DEFINE_IDREG_READ_FUNC(id_aa64mmfr0_el1)
390 DEFINE_IDREG_READ_FUNC(id_aa64mmfr1_el1)
391
392 DEFINE_SYSREG_RW_FUNCS(scr_el3)
393 DEFINE_SYSREG_RW_FUNCS(hcr_el2)
394
395 DEFINE_SYSREG_RW_FUNCS(vbar_el1)
396 DEFINE_SYSREG_RW_FUNCS(vbar_el2)
397 DEFINE_SYSREG_RW_FUNCS(vbar_el3)
398
399 DEFINE_SYSREG_RW_FUNCS(sctlr_el1)
400 DEFINE_SYSREG_RW_FUNCS(sctlr_el2)
401 DEFINE_SYSREG_RW_FUNCS(sctlr_el3)
402
403 DEFINE_SYSREG_RW_FUNCS(actlr_el1)
404 DEFINE_SYSREG_RW_FUNCS(actlr_el2)
405 DEFINE_SYSREG_RW_FUNCS(actlr_el3)
406
407 DEFINE_SYSREG_RW_FUNCS(esr_el1)
408 DEFINE_SYSREG_RW_FUNCS(esr_el2)
409 DEFINE_SYSREG_RW_FUNCS(esr_el3)
410
411 DEFINE_SYSREG_RW_FUNCS(afsr0_el1)
412 DEFINE_SYSREG_RW_FUNCS(afsr0_el2)
413 DEFINE_SYSREG_RW_FUNCS(afsr0_el3)
414
415 DEFINE_SYSREG_RW_FUNCS(afsr1_el1)
416 DEFINE_SYSREG_RW_FUNCS(afsr1_el2)
417 DEFINE_SYSREG_RW_FUNCS(afsr1_el3)
418
419 DEFINE_SYSREG_RW_FUNCS(far_el1)
420 DEFINE_SYSREG_RW_FUNCS(far_el2)
421 DEFINE_SYSREG_RW_FUNCS(far_el3)
422
423 DEFINE_SYSREG_RW_FUNCS(mair_el1)
424 DEFINE_SYSREG_RW_FUNCS(mair_el2)
425 DEFINE_SYSREG_RW_FUNCS(mair_el3)
426
427 DEFINE_SYSREG_RW_FUNCS(amair_el1)
428 DEFINE_SYSREG_RW_FUNCS(amair_el2)
429 DEFINE_SYSREG_RW_FUNCS(amair_el3)
430
431 DEFINE_SYSREG_READ_FUNC(rvbar_el1)
432 DEFINE_SYSREG_READ_FUNC(rvbar_el2)
433 DEFINE_SYSREG_READ_FUNC(rvbar_el3)
434
435 DEFINE_SYSREG_RW_FUNCS(rmr_el1)
436 DEFINE_SYSREG_RW_FUNCS(rmr_el2)
437 DEFINE_SYSREG_RW_FUNCS(rmr_el3)
438
439 DEFINE_SYSREG_RW_FUNCS(tcr_el1)
440 DEFINE_SYSREG_RW_FUNCS(tcr_el2)
441 DEFINE_SYSREG_RW_FUNCS(tcr_el3)
442
443 DEFINE_SYSREG_RW_FUNCS(ttbr0_el1)
444 DEFINE_SYSREG_RW_FUNCS(ttbr0_el2)
445 DEFINE_SYSREG_RW_FUNCS(ttbr0_el3)
446
447 DEFINE_SYSREG_RW_FUNCS(ttbr1_el1)
448
449 DEFINE_SYSREG_RW_FUNCS(vttbr_el2)
450
451 DEFINE_SYSREG_RW_FUNCS(cptr_el2)
452 DEFINE_SYSREG_RW_FUNCS(cptr_el3)
453
454 DEFINE_SYSREG_RW_FUNCS(cpacr_el1)
455 DEFINE_SYSREG_RW_FUNCS(cntfrq_el0)
456 DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2)
457 DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2)
458 DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2)
459 DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1)
460 DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1)
461 DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1)
462 DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0)
463 DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0)
464 DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0)
465 DEFINE_SYSREG_READ_FUNC(cntpct_el0)
466 DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
467
468 DEFINE_SYSREG_RW_FUNCS(vtcr_el2)
469
470 #define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \
471 CNTP_CTL_ENABLE_MASK)
472 #define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \
473 CNTP_CTL_IMASK_MASK)
474 #define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \
475 CNTP_CTL_ISTATUS_MASK)
476
477 #define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT))
478 #define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT))
479
480 #define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT))
481 #define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT))
482
483 DEFINE_SYSREG_RW_FUNCS(tpidr_el3)
484
485 DEFINE_SYSREG_RW_FUNCS(cntvoff_el2)
486
487 DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
488 DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
489
490 DEFINE_SYSREG_RW_FUNCS(hacr_el2)
491 DEFINE_SYSREG_RW_FUNCS(hpfar_el2)
492 DEFINE_SYSREG_RW_FUNCS(tpidr_el2)
493 DEFINE_SYSREG_RW_FUNCS(dbgvcr32_el2)
494 DEFINE_RENAME_SYSREG_RW_FUNCS(ich_hcr_el2, ICH_HCR_EL2)
495 DEFINE_RENAME_SYSREG_RW_FUNCS(ich_vmcr_el2, ICH_VMCR_EL2)
496
497 DEFINE_SYSREG_READ_FUNC(isr_el1)
498
499 DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
500 DEFINE_SYSREG_RW_FUNCS(mdcr_el3)
501 DEFINE_SYSREG_RW_FUNCS(hstr_el2)
502 DEFINE_SYSREG_RW_FUNCS(pmcr_el0)
503
504 /* GICv3 System Registers */
505
506 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
507 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2)
508 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3)
509 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1)
510 DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1)
511 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3)
512 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1)
513 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1)
514 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1)
515 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1)
516 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1)
517 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1)
518 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1)
519 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1)
520 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1)
521 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R)
522 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_asgi1r, ICC_ASGI1R)
523
524 DEFINE_RENAME_SYSREG_READ_FUNC(amcfgr_el0, AMCFGR_EL0)
525 DEFINE_RENAME_SYSREG_READ_FUNC(amcgcr_el0, AMCGCR_EL0)
526 DEFINE_RENAME_SYSREG_READ_FUNC(amcg1idr_el0, AMCG1IDR_EL0)
527 DEFINE_RENAME_SYSREG_RW_FUNCS(amcr_el0, AMCR_EL0)
528 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0)
529 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0)
530 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0)
531 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0)
532
533 DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1)
534
535 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3)
536 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2)
537
538 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64smfr0_el1, ID_AA64SMFR0_EL1)
539 DEFINE_RENAME_SYSREG_RW_FUNCS(smcr_el3, SMCR_EL3)
540
541 DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1)
542 DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1)
543
544 DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1)
545 DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1)
546 DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1)
547 DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1)
548 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1)
549 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1)
550
551 DEFINE_RENAME_SYSREG_RW_FUNCS(scxtnum_el2, SCXTNUM_EL2)
552
553 /* Armv8.1 VHE Registers */
554 DEFINE_RENAME_SYSREG_RW_FUNCS(contextidr_el2, CONTEXTIDR_EL2)
555 DEFINE_RENAME_SYSREG_RW_FUNCS(ttbr1_el2, TTBR1_EL2)
556
557 /* Armv8.2 ID Registers */
558 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr2_el1, ID_AA64MMFR2_EL1)
559
560 /* Armv8.2 RAS Registers */
561 DEFINE_RENAME_SYSREG_RW_FUNCS(vdisr_el2, VDISR_EL2)
562 DEFINE_RENAME_SYSREG_RW_FUNCS(vsesr_el2, VSESR_EL2)
563
564 /* Armv8.2 MPAM Registers */
565 DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1)
566 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3)
567 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2)
568 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2)
569 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm0_el2, MPAMVPM0_EL2)
570 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm1_el2, MPAMVPM1_EL2)
571 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm2_el2, MPAMVPM2_EL2)
572 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm3_el2, MPAMVPM3_EL2)
573 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm4_el2, MPAMVPM4_EL2)
574 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm5_el2, MPAMVPM5_EL2)
575 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm6_el2, MPAMVPM6_EL2)
576 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpm7_el2, MPAMVPM7_EL2)
577 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamvpmv_el2, MPAMVPMV_EL2)
578
579 /* Armv8.3 Pointer Authentication Registers */
580 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeyhi_el1, APIAKeyHi_EL1)
581 DEFINE_RENAME_SYSREG_RW_FUNCS(apiakeylo_el1, APIAKeyLo_EL1)
582
583 /* Armv8.4 Data Independent Timing Register */
584 DEFINE_RENAME_SYSREG_RW_FUNCS(dit, DIT)
585
586 /* Armv8.4 FEAT_TRF Register */
587 DEFINE_RENAME_SYSREG_RW_FUNCS(trfcr_el2, TRFCR_EL2)
588 DEFINE_RENAME_SYSREG_RW_FUNCS(vncr_el2, VNCR_EL2)
589
590 /* Armv8.5 MTE Registers */
591 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsre0_el1, TFSRE0_EL1)
592 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1)
593 DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1)
594 DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1)
595 DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el2, TFSR_EL2)
596
597 /* Armv8.5 FEAT_RNG Registers */
598 DEFINE_RENAME_SYSREG_READ_FUNC(rndr, RNDR)
599 DEFINE_RENAME_SYSREG_READ_FUNC(rndrrs, RNDRRS)
600
601 /* Armv8.6 FEAT_FGT Registers */
602 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgrtr_el2, HDFGRTR_EL2)
603 DEFINE_RENAME_SYSREG_RW_FUNCS(hafgrtr_el2, HAFGRTR_EL2)
604 DEFINE_RENAME_SYSREG_RW_FUNCS(hdfgwtr_el2, HDFGWTR_EL2)
605 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgitr_el2, HFGITR_EL2)
606 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgrtr_el2, HFGRTR_EL2)
607 DEFINE_RENAME_SYSREG_RW_FUNCS(hfgwtr_el2, HFGWTR_EL2)
608
609 /* ARMv8.6 FEAT_ECV Register */
610 DEFINE_RENAME_SYSREG_RW_FUNCS(cntpoff_el2, CNTPOFF_EL2)
611
612 /* FEAT_HCX Register */
613 DEFINE_RENAME_SYSREG_RW_FUNCS(hcrx_el2, HCRX_EL2)
614
615 /* Armv8.9 system registers */
616 DEFINE_RENAME_IDREG_READ_FUNC(id_aa64mmfr3_el1, ID_AA64MMFR3_EL1)
617
618 /* FEAT_TCR2 Register */
619 DEFINE_RENAME_SYSREG_RW_FUNCS(tcr2_el2, TCR2_EL2)
620
621 /* FEAT_SxPIE Registers */
622 DEFINE_RENAME_SYSREG_RW_FUNCS(pire0_el2, PIRE0_EL2)
623 DEFINE_RENAME_SYSREG_RW_FUNCS(pir_el2, PIR_EL2)
624 DEFINE_RENAME_SYSREG_RW_FUNCS(s2pir_el2, S2PIR_EL2)
625
626 /* FEAT_SxPOE Registers */
627 DEFINE_RENAME_SYSREG_RW_FUNCS(por_el2, POR_EL2)
628
629 /* FEAT_GCS Registers */
630 DEFINE_RENAME_SYSREG_RW_FUNCS(gcscr_el2, GCSCR_EL2)
631 DEFINE_RENAME_SYSREG_RW_FUNCS(gcspr_el2, GCSPR_EL2)
632
633 /* DynamIQ Shared Unit power management */
634 DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)
635
636 /* CPU Power/Performance Management registers */
637 DEFINE_RENAME_SYSREG_RW_FUNCS(cpuppmcr_el3, CPUPPMCR_EL3)
638 DEFINE_RENAME_SYSREG_RW_FUNCS(cpumpmmcr_el3, CPUMPMMCR_EL3)
639
640 /* Armv9.2 RME Registers */
641 DEFINE_RENAME_SYSREG_RW_FUNCS(gptbr_el3, GPTBR_EL3)
642 DEFINE_RENAME_SYSREG_RW_FUNCS(gpccr_el3, GPCCR_EL3)
643
644 #define IS_IN_EL(x) \
645 (GET_EL(read_CurrentEl()) == MODE_EL##x)
646
647 #define IS_IN_EL1() IS_IN_EL(1)
648 #define IS_IN_EL2() IS_IN_EL(2)
649 #define IS_IN_EL3() IS_IN_EL(3)
650
651 static inline unsigned int get_current_el(void)
652 {
653 return GET_EL(read_CurrentEl());
654 }
655
get_current_el_maybe_constant(void)656 static inline unsigned int get_current_el_maybe_constant(void)
657 {
658 #if defined(IMAGE_AT_EL1)
659 return 1;
660 #elif defined(IMAGE_AT_EL2)
661 return 2; /* no use-case in TF-A */
662 #elif defined(IMAGE_AT_EL3)
663 return 3;
664 #else
665 /*
666 * If we do not know which exception level this is being built for
667 * (e.g. built for library), fall back to run-time detection.
668 */
669 return get_current_el();
670 #endif
671 }
672
673 /*
674 * Check if an EL is implemented from AA64PFR0 register fields.
675 */
el_implemented(unsigned int el)676 static inline uint64_t el_implemented(unsigned int el)
677 {
678 if (el > 3U) {
679 return EL_IMPL_NONE;
680 } else {
681 unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el;
682
683 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK;
684 }
685 }
686
687 /*
688 * TLBIPAALLOS instruction
689 * (TLB Inivalidate GPT Information by PA,
690 * All Entries, Outer Shareable)
691 */
tlbipaallos(void)692 static inline void tlbipaallos(void)
693 {
694 __asm__("SYS #6,c8,c1,#4");
695 }
696
697 /*
698 * Invalidate TLBs of GPT entries by Physical address, last level.
699 *
700 * @pa: the starting address for the range
701 * of invalidation
702 * @size: size of the range of invalidation
703 */
704 void gpt_tlbi_by_pa_ll(uint64_t pa, size_t size);
705
706
707 /* Previously defined accessor functions with incomplete register names */
708
709 #define read_current_el() read_CurrentEl()
710
711 #define dsb() dsbsy()
712
713 #define read_midr() read_midr_el1()
714
715 #define read_mpidr() read_mpidr_el1()
716
717 #define read_scr() read_scr_el3()
718 #define write_scr(_v) write_scr_el3(_v)
719
720 #define read_hcr() read_hcr_el2()
721 #define write_hcr(_v) write_hcr_el2(_v)
722
723 #define read_cpacr() read_cpacr_el1()
724 #define write_cpacr(_v) write_cpacr_el1(_v)
725
726 #define read_clusterpwrdn() read_clusterpwrdn_el1()
727 #define write_clusterpwrdn(_v) write_clusterpwrdn_el1(_v)
728
729 #if ERRATA_SPECULATIVE_AT
730 /*
731 * Assuming SCTLR.M bit is already enabled
732 * 1. Enable page table walk by clearing TCR_EL1.EPDx bits
733 * 2. Execute AT instruction for lower EL1/0
734 * 3. Disable page table walk by setting TCR_EL1.EPDx bits
735 */
736 #define AT(_at_inst, _va) \
737 { \
738 assert((read_sctlr_el1() & SCTLR_M_BIT) != 0ULL); \
739 write_tcr_el1(read_tcr_el1() & ~(TCR_EPD0_BIT | TCR_EPD1_BIT)); \
740 isb(); \
741 _at_inst(_va); \
742 write_tcr_el1(read_tcr_el1() | (TCR_EPD0_BIT | TCR_EPD1_BIT)); \
743 isb(); \
744 }
745 #else
746 #define AT(_at_inst, _va) _at_inst(_va)
747 #endif
748
749 #endif /* ARCH_HELPERS_H */
750
