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Searched defs:module (Results 1 – 10 of 10) sorted by relevance

/Zephyr-Core-3.5.0/scripts/
Dzephyr_module.py173 def process_module(module): argument
205 def process_cmake(module, meta): argument
236 def process_sysbuildcmake(module, meta): argument
270 def process_settings(module, meta): argument
298 def process_blobs(module, meta): argument
332 def process_kconfig(module, meta): argument
356 def process_sysbuildkconfig(module, meta): argument
380 def process_twister(module, meta): argument
/Zephyr-Core-3.5.0/drivers/sensor/vl53l1x/
Dvl53l1_platform_log.h161 #define _LOG_TRACE_PRINT(module, level, function, ...) \ argument
164 #define _LOG_FUNCTION_START(module, fmt, ...) \ argument
168 #define _LOG_FUNCTION_END(module, status, ...)\ argument
172 #define _LOG_FUNCTION_END_FMT(module, status, fmt, ...)\ argument
190 #define _LOG_TRACE_PRINT(module, level, function, ...) argument
191 #define _LOG_FUNCTION_START(module, fmt, ...) argument
192 #define _LOG_FUNCTION_END(module, status, ...) argument
193 #define _LOG_FUNCTION_END_FMT(module, status, fmt, ...) argument
/Zephyr-Core-3.5.0/doc/contribute/
Dexternal.rst106 Integration in main manifest file (west.yaml)
119 Integration as optional modules
139 Integration as external modules
/Zephyr-Core-3.5.0/drivers/sensor/vl53l0x/
Dvl53l0x_platform_log.h46 #define _LOG_FUNCTION_START(module, fmt, ...) (void)0 argument
47 #define _LOG_FUNCTION_END(module, status, ...) (void)0 argument
48 #define _LOG_FUNCTION_END_FMT(module, status, fmt, ...) (void)0 argument
/Zephyr-Core-3.5.0/include/zephyr/drivers/clock_control/
Drenesas_cpg_mssr.h17 uint32_t module; member
/Zephyr-Core-3.5.0/drivers/clock_control/
Dclock_control_r8a7795_cpg_mssr.c174 static uint32_t r8a7795_get_div_helper(uint32_t reg_val, uint32_t module) in r8a7795_get_div_helper()
211 static int r8a7795_set_rate_helper(uint32_t module, uint32_t *divider, uint32_t *div_mask) in r8a7795_set_rate_helper()
Dclock_control_renesas_cpg_mssr.c33 int rcar_cpg_mstp_clock_endisable(uint32_t base_address, uint32_t module, bool enable) in rcar_cpg_mstp_clock_endisable()
61 uint32_t module = (uintptr_t)key; in cmp_cpg_clk_info_table_items() local
269 uint32_t module; in rcar_cpg_set_rate() local
Dclock_control_renesas_cpg_mssr.h19 uint32_t module; member
/Zephyr-Core-3.5.0/doc/develop/
Dmodules.rst524 .. _sysbuild_module_integration:
1119 .. _changes_to_existing_module:
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/common/include/
Dmanifest.h190 struct sof_man_module module; member