1 /*
2  * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #pragma once
8 
9 #include "soc/ext_mem_defs.h"
10 #include "soc/memprot_defs.h"
11 #include "hal/memprot_types.h"
12 #include "soc/sensitive_reg.h"
13 
14 /* Uncomment to enable MPS debug assertions on false register writes.
15  * It irregularly happens the PMS registers cannot be written which causes unpredictable malfunction of the Memprot feature
16  * Once the issue is found & resolved, the assertions can be removed
17  */
18 //#define PMS_DEBUG_ASSERTIONS
19 
20 #ifdef PMS_DEBUG_ASSERTIONS
21 #include "hal/assert.h"
22 #endif
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 //highest address of each Level slot in the SRAM's 3rd memory region (I/D access, 416kB)
29 //quick resolver of split-address category bits
30 static const intptr_t sram_rg3_level_hlimits[] = {
31         0x4037FFFF, //level 2 (32KB)
32         0x4038FFFF, //level 3 (64KB)
33         0x4039FFFF, //level 4 (64KB)
34         0x403AFFFF, //level 5 (64KB)
35         0x403BFFFF, //level 6 (64KB)
36         0x403CFFFF, //level 7 (64KB)
37         0x403DFFFF  //level 8 (64KB)
38 };
39 
40 /* ******************************************************************************************************
41  * *** COMMON ***
42  * ******************************************************************************************************/
memprot_ll_set_iram0_dram0_split_line_lock(void)43 static inline void memprot_ll_set_iram0_dram0_split_line_lock(void)
44 {
45     REG_WRITE(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG, 1);
46 #ifdef PMS_DEBUG_ASSERTIONS
47     HAL_ASSERT((REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG) == 1) && "Value not stored to required register");
48 #endif
49 }
50 
memprot_ll_get_iram0_dram0_split_line_lock(void)51 static inline bool memprot_ll_get_iram0_dram0_split_line_lock(void)
52 {
53     return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG) == 1;
54 }
55 
memprot_ll_get_split_addr_from_reg(const uint32_t regval,const uint32_t base)56 static inline void *memprot_ll_get_split_addr_from_reg(const uint32_t regval, const uint32_t base)
57 {
58     constrain_reg_fields_t reg_val;
59     reg_val.val = regval;
60 
61     uint32_t off = reg_val.splitaddr << I_D_SPLIT_LINE_SHIFT;
62     uint32_t level_off = 0;
63 
64     do {
65         if (reg_val.cat0 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break;
66         level_off += I_D_SRAM_SEGMENT_SIZE/2;
67         if (reg_val.cat1 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break;
68         level_off += I_D_SRAM_SEGMENT_SIZE;
69         if (reg_val.cat2 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break;
70         level_off += I_D_SRAM_SEGMENT_SIZE;
71         if (reg_val.cat3 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break;
72         level_off += I_D_SRAM_SEGMENT_SIZE;
73         if (reg_val.cat4 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break;
74         level_off += I_D_SRAM_SEGMENT_SIZE;
75         if (reg_val.cat5 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break;
76         level_off += I_D_SRAM_SEGMENT_SIZE;
77         if (reg_val.cat6 == MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA) break;
78         return NULL; //wrong configuration
79     } while(0);
80 
81     return (void *)(base + level_off + off);
82 }
83 
84 /* ******************************************************************************************************
85  * *** ICACHE ***
86  * ******************************************************************************************************/
memprot_ll_icache_set_permissions(const bool r,const bool w,const bool x)87 static inline uint32_t memprot_ll_icache_set_permissions(const bool r, const bool w, const bool x)
88 {
89     uint32_t permissions = 0;
90     if (r) {
91         permissions |= SENSITIVE_CORE_X_ICACHE_PMS_CONSTRAIN_SRAM_WORLD_X_R;
92     }
93     if (w) {
94         permissions |= SENSITIVE_CORE_X_ICACHE_PMS_CONSTRAIN_SRAM_WORLD_X_W;
95     }
96     if (x) {
97         permissions |= SENSITIVE_CORE_X_ICACHE_PMS_CONSTRAIN_SRAM_WORLD_X_F;
98     }
99 
100     return permissions;
101 }
102 
memprot_ll_icache_set_pms_area_0(const bool r,const bool w,const bool x)103 static inline void memprot_ll_icache_set_pms_area_0(const bool r, const bool w, const bool x)
104 {
105     REG_SET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0, memprot_ll_icache_set_permissions(r, w, x));
106 #ifdef PMS_DEBUG_ASSERTIONS
107     uint32_t expected = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0);
108     HAL_ASSERT((expected == memprot_ll_icache_set_permissions(r, w, x)) && "Value not stored to required register");
109 #endif
110 }
111 
memprot_ll_icache_set_pms_area_1(const bool r,const bool w,const bool x)112 static inline void memprot_ll_icache_set_pms_area_1(const bool r, const bool w, const bool x)
113 {
114     REG_SET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1, memprot_ll_icache_set_permissions(r, w, x));
115 #ifdef PMS_DEBUG_ASSERTIONS
116     uint32_t expected = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1);
117     HAL_ASSERT((expected == memprot_ll_icache_set_permissions(r, w, x)) && "Value not stored to required register");
118 #endif
119 }
120 
memprot_ll_icache_get_permissions(const uint32_t perms,bool * r,bool * w,bool * x)121 static inline void memprot_ll_icache_get_permissions(const uint32_t perms, bool *r, bool *w, bool *x)
122 {
123     *r = perms & SENSITIVE_CORE_X_ICACHE_PMS_CONSTRAIN_SRAM_WORLD_X_R;
124     *w = perms & SENSITIVE_CORE_X_ICACHE_PMS_CONSTRAIN_SRAM_WORLD_X_W;
125     *x = perms & SENSITIVE_CORE_X_ICACHE_PMS_CONSTRAIN_SRAM_WORLD_X_F;
126 }
127 
memprot_ll_icache_get_pms_area_0(bool * r,bool * w,bool * x)128 static inline void memprot_ll_icache_get_pms_area_0(bool *r, bool *w, bool *x)
129 {
130     uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0);
131     memprot_ll_icache_get_permissions(permissions, r, w, x);
132 }
133 
memprot_ll_icache_get_pms_area_1(bool * r,bool * w,bool * x)134 static inline void memprot_ll_icache_get_pms_area_1(bool *r, bool *w, bool *x)
135 {
136     uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1);
137     memprot_ll_icache_get_permissions(permissions, r, w, x);
138 }
139 
140 /* ******************************************************************************************************
141  * *** IRAM0 ***
142  * ******************************************************************************************************/
memprot_ll_iram0_get_intr_source_num(const int core,uint32_t * src_num)143 static inline memprot_hal_err_t memprot_ll_iram0_get_intr_source_num(const int core, uint32_t* src_num)
144 {
145     switch (core) {
146         case PRO_CPU_NUM:
147             *src_num = ETS_CORE0_IRAM0_PMS_INTR_SOURCE;
148             break;
149         case APP_CPU_NUM:
150             *src_num = ETS_CORE1_IRAM0_PMS_INTR_SOURCE;
151             break;
152         default:
153             return MEMP_HAL_FAIL;
154     }
155 
156     return MEMP_HAL_OK;
157 }
158 
159 ///////////////////////////////////
160 // IRAM0 - SPLIT LINES
memprot_ll_get_iram0_split_line_main_I_D_regval(void)161 static inline uint32_t memprot_ll_get_iram0_split_line_main_I_D_regval(void)
162 {
163     return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG);
164 }
165 
memprot_ll_get_iram0_split_line_main_I_0_regval(void)166 static inline uint32_t memprot_ll_get_iram0_split_line_main_I_0_regval(void)
167 {
168     return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG);
169 }
170 
memprot_ll_get_iram0_split_line_main_I_1_regval(void)171 static inline uint32_t memprot_ll_get_iram0_split_line_main_I_1_regval(void)
172 {
173     return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG);
174 }
175 
memprot_ll_prepare_iram0_split_line_regval(const uint32_t addr,uint32_t * regval)176 static inline void memprot_ll_prepare_iram0_split_line_regval(const uint32_t addr, uint32_t* regval)
177 {
178     //set category bits for given split line
179     uint32_t cat[7] = {[0 ... 6]=MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA};
180     for (size_t x=0; x<7; x++) {
181         if (addr <= sram_rg3_level_hlimits[x]) {
182             cat[x] = MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA;
183             break;
184         } else {
185             cat[x] = MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_BELOW_SA;
186         }
187     }
188 
189     //resolve split address' significant bits
190     uint32_t conf_add = ((addr >> I_D_SPLIT_LINE_SHIFT) & SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V);
191 
192     //write values to required configuration-register
193     constrain_reg_fields_t cfg_reg_val = {
194             .cat0 = cat[0],
195             .cat1 = cat[1],
196             .cat2 = cat[2],
197             .cat3 = cat[3],
198             .cat4 = cat[4],
199             .cat5 = cat[5],
200             .cat6 = cat[6],
201             .splitaddr = conf_add,
202             .reserved = 0
203     };
204 
205     *regval = cfg_reg_val.val;
206 }
207 
208 // all the split lines registers have the same layout
memprot_ll_set_iram0_split_line(const void * line_addr,const uint32_t sensitive_reg)209 static inline memprot_hal_err_t memprot_ll_set_iram0_split_line(const void *line_addr, const uint32_t sensitive_reg)
210 {
211     uint32_t addr = (uint32_t)line_addr;
212 
213     //sanity check
214     MEMP_HAL_CHECK_IRAM_ADDR_IN_RANGE(addr)
215     MEMP_HAL_CHECK_SPLIT_ADDR_ALIGNED(addr)
216 
217     uint32_t regval;
218     memprot_ll_prepare_iram0_split_line_regval(addr, &regval);
219 
220     REG_WRITE(sensitive_reg, regval);
221 #ifdef PMS_DEBUG_ASSERTIONS
222     HAL_ASSERT((REG_READ(sensitive_reg) == regval) && "Value not stored to required register");
223 #endif
224 
225     return MEMP_HAL_OK;
226 }
227 
228 // set the main I/D splitting address - can be defined within either IRAM0 or DRAM0 range (IRAM0 preferred as the Memprot API stereotype)
memprot_ll_set_iram0_split_line_main_I_D(const void * line_addr)229 static inline memprot_hal_err_t memprot_ll_set_iram0_split_line_main_I_D(const void *line_addr)
230 {
231     return memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG);
232 }
233 
234 // set auxiliary split lines (IRAM0 range address required)
memprot_ll_set_iram0_split_line_I_0(const void * line_addr)235 static inline memprot_hal_err_t memprot_ll_set_iram0_split_line_I_0(const void *line_addr)
236 {
237     return memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG);
238 }
239 
memprot_ll_set_iram0_split_line_I_1(const void * line_addr)240 static inline memprot_hal_err_t memprot_ll_set_iram0_split_line_I_1(const void *line_addr)
241 {
242     return memprot_ll_set_iram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG);
243 }
244 
245 // get configured category bits
memprot_ll_get_iram0_split_line_main_I_D_cat(void)246 static inline uint32_t memprot_ll_get_iram0_split_line_main_I_D_cat(void)
247 {
248     return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG) & 0x3FFF;
249 }
250 
memprot_ll_get_iram0_split_line_I_0_cat(void)251 static inline uint32_t memprot_ll_get_iram0_split_line_I_0_cat(void)
252 {
253     return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG) & 0x3FFF;
254 }
255 
memprot_ll_get_iram0_split_line_I_1_cat(void)256 static inline uint32_t memprot_ll_get_iram0_split_line_I_1_cat(void)
257 {
258     return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG) & 0x3FFF;
259 }
260 
261 // get configured splitting address (IRAM0-based)
memprot_ll_get_iram0_split_line_main_I_D(void)262 static inline void *memprot_ll_get_iram0_split_line_main_I_D(void)
263 {
264     return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG), SOC_DIRAM_IRAM_LOW);
265 }
266 
memprot_ll_get_iram0_split_line_I_0(void)267 static inline void *memprot_ll_get_iram0_split_line_I_0(void)
268 {
269     return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG), SOC_DIRAM_IRAM_LOW);
270 }
271 
memprot_ll_get_iram0_split_line_I_1(void)272 static inline void *memprot_ll_get_iram0_split_line_I_1(void)
273 {
274     return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG), SOC_DIRAM_IRAM_LOW);
275 }
276 
277 ///////////////////////////////////
278 // IRAM0 - PMS CONFIGURATION
279 
280 // lock
memprot_ll_iram0_set_pms_lock(void)281 static inline void memprot_ll_iram0_set_pms_lock(void)
282 {
283     REG_WRITE(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG, 1);
284 #ifdef PMS_DEBUG_ASSERTIONS
285     HAL_ASSERT((REG_READ(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG) == 1) && "Value not stored to required register");
286 #endif
287 }
288 
memprot_ll_iram0_get_pms_lock(void)289 static inline bool memprot_ll_iram0_get_pms_lock(void)
290 {
291     return REG_READ(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG) == 1;
292 }
293 
294 // permission settings
memprot_ll_iram0_set_permissions(const bool r,const bool w,const bool x)295 static inline uint32_t memprot_ll_iram0_set_permissions(const bool r, const bool w, const bool x)
296 {
297     uint32_t permissions = 0;
298     if (r) {
299         permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R;
300     }
301     if (w) {
302         permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W;
303     }
304     if (x) {
305         permissions |= SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F;
306     }
307 
308     return permissions;
309 }
310 
memprot_ll_iram0_set_pms_area_0(const bool r,const bool w,const bool x)311 static inline void memprot_ll_iram0_set_pms_area_0(const bool r, const bool w, const bool x)
312 {
313     REG_SET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0, memprot_ll_iram0_set_permissions(r, w, x));
314 #ifdef PMS_DEBUG_ASSERTIONS
315     uint32_t expected = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0);
316     HAL_ASSERT((expected == memprot_ll_iram0_set_permissions(r, w, x)) && "Value not stored to required register");
317 #endif
318 }
319 
memprot_ll_iram0_set_pms_area_1(const bool r,const bool w,const bool x)320 static inline void memprot_ll_iram0_set_pms_area_1(const bool r, const bool w, const bool x)
321 {
322     REG_SET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1, memprot_ll_iram0_set_permissions(r, w, x));
323 #ifdef PMS_DEBUG_ASSERTIONS
324     uint32_t expected = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1);
325     HAL_ASSERT((expected == memprot_ll_iram0_set_permissions(r, w, x)) && "Value not stored to required register");
326 #endif
327 }
328 
memprot_ll_iram0_set_pms_area_2(const bool r,const bool w,const bool x)329 static inline void memprot_ll_iram0_set_pms_area_2(const bool r, const bool w, const bool x)
330 {
331     REG_SET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2, memprot_ll_iram0_set_permissions(r, w, x));
332 #ifdef PMS_DEBUG_ASSERTIONS
333     uint32_t expected = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2);
334     HAL_ASSERT((expected == memprot_ll_iram0_set_permissions(r, w, x)) && "Value not stored to required register");
335 #endif
336 }
337 
memprot_ll_iram0_set_pms_area_3(const bool r,const bool w,const bool x)338 static inline void memprot_ll_iram0_set_pms_area_3(const bool r, const bool w, const bool x)
339 {
340     REG_SET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3, memprot_ll_iram0_set_permissions(r, w, x));
341 #ifdef PMS_DEBUG_ASSERTIONS
342     uint32_t expected = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3);
343     HAL_ASSERT((expected == memprot_ll_iram0_set_permissions(r, w, x)) && "Value not stored to required register");
344 #endif
345 }
346 
memprot_ll_iram0_get_permissions(const uint32_t perms,bool * r,bool * w,bool * x)347 static inline void memprot_ll_iram0_get_permissions(const uint32_t perms, bool *r, bool *w, bool *x)
348 {
349     *r = perms & SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R;
350     *w = perms & SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W;
351     *x = perms & SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_F;
352 }
353 
memprot_ll_iram0_get_pms_area_0(bool * r,bool * w,bool * x)354 static inline void memprot_ll_iram0_get_pms_area_0(bool *r, bool *w, bool *x)
355 {
356     uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0);
357     memprot_ll_iram0_get_permissions(permissions, r, w, x);
358 }
359 
memprot_ll_iram0_get_pms_area_1(bool * r,bool * w,bool * x)360 static inline void memprot_ll_iram0_get_pms_area_1(bool *r, bool *w, bool *x)
361 {
362     uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1);
363     memprot_ll_iram0_get_permissions(permissions, r, w, x);
364 }
365 
memprot_ll_iram0_get_pms_area_2(bool * r,bool * w,bool * x)366 static inline void memprot_ll_iram0_get_pms_area_2(bool *r, bool *w, bool *x)
367 {
368     uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2);
369     memprot_ll_iram0_get_permissions(permissions, r, w, x);
370 }
371 
memprot_ll_iram0_get_pms_area_3(bool * r,bool * w,bool * x)372 static inline void memprot_ll_iram0_get_pms_area_3(bool *r, bool *w, bool *x)
373 {
374     uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3);
375     memprot_ll_iram0_get_permissions(permissions, r, w, x);
376 }
377 
378 
379 ///////////////////////////////////
380 // IRAM0 - MONITOR
381 
382 // lock
memprot_ll_iram0_set_monitor_lock(const int core)383 static inline memprot_hal_err_t memprot_ll_iram0_set_monitor_lock(const int core)
384 {
385     switch (core) {
386         case PRO_CPU_NUM:
387             REG_WRITE(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG, 1);
388 #ifdef PMS_DEBUG_ASSERTIONS
389             HAL_ASSERT((REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG) == 1) && "Value not stored to required register");
390 #endif
391             break;
392         case APP_CPU_NUM:
393             REG_WRITE(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG, 1);
394 #ifdef PMS_DEBUG_ASSERTIONS
395             HAL_ASSERT((REG_READ(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG) == 1) && "Value not stored to required register");
396 #endif
397             break;
398         default:
399             return MEMP_HAL_ERR_CORE_INVALID;
400     }
401 
402     return MEMP_HAL_OK;
403 }
404 
memprot_ll_iram0_get_monitor_lock(const int core,bool * locked)405 static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_lock(const int core, bool* locked)
406 {
407     switch (core) {
408         case PRO_CPU_NUM:
409             *locked = REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG) == 1;
410             break;
411         case APP_CPU_NUM:
412             *locked = REG_READ(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG) == 1;
413             break;
414         default:
415             return MEMP_HAL_ERR_CORE_INVALID;
416     }
417 
418     return MEMP_HAL_OK;
419 }
420 
421 // interrupt enable/clear
memprot_ll_iram0_set_monitor_en(const int core,const bool enable)422 static inline memprot_hal_err_t memprot_ll_iram0_set_monitor_en(const int core, const bool enable)
423 {
424     switch (core) {
425         case PRO_CPU_NUM:
426             if (enable) {
427                 REG_SET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN);
428 #ifdef PMS_DEBUG_ASSERTIONS
429                 HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN) > 0) && "Value not stored to required register");
430 #endif
431             } else {
432                 REG_CLR_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN);
433 #ifdef PMS_DEBUG_ASSERTIONS
434                 HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN) == 0) && "Value not stored to required register");
435 #endif
436             }
437             break;
438         case APP_CPU_NUM:
439             if (enable) {
440                 REG_SET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN);
441 #ifdef PMS_DEBUG_ASSERTIONS
442                 HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN) > 0) && "Value not stored to required register");
443 #endif
444             } else {
445                 REG_CLR_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN);
446 #ifdef PMS_DEBUG_ASSERTIONS
447                 HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN) == 0) && "Value not stored to required register");
448 #endif
449             }
450             break;
451         default:
452             return MEMP_HAL_ERR_CORE_INVALID;
453     }
454 
455     return MEMP_HAL_OK;
456 }
457 
memprot_ll_iram0_get_monitor_en(const int core,bool * enabled)458 static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_en(const int core, bool* enabled)
459 {
460     switch (core) {
461         case PRO_CPU_NUM:
462             *enabled = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN) == 1;
463             break;
464         case APP_CPU_NUM:
465             *enabled = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN) == 1;
466             break;
467         default:
468             return MEMP_HAL_ERR_CORE_INVALID;
469     }
470 
471     return MEMP_HAL_OK;
472 }
473 
memprot_ll_iram0_set_monitor_intrclr(const int core)474 static inline memprot_hal_err_t memprot_ll_iram0_set_monitor_intrclr(const int core)
475 {
476     switch (core) {
477         case PRO_CPU_NUM:
478             REG_SET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR);
479 #ifdef PMS_DEBUG_ASSERTIONS
480             HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR) > 0) && "Value not stored to required register");
481 #endif
482             break;
483         case APP_CPU_NUM:
484             REG_SET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR);
485 #ifdef PMS_DEBUG_ASSERTIONS
486             HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR) > 0) && "Value not stored to required register");
487 #endif
488             break;
489         default:
490             return MEMP_HAL_ERR_CORE_INVALID;
491     }
492 
493     return MEMP_HAL_OK;
494 }
495 
memprot_ll_iram0_reset_monitor_intrclr(const int core)496 static inline memprot_hal_err_t memprot_ll_iram0_reset_monitor_intrclr(const int core)
497 {
498     switch (core) {
499         case PRO_CPU_NUM:
500             REG_CLR_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR);
501 #ifdef PMS_DEBUG_ASSERTIONS
502             HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR) == 0) && "Value not stored to required register");
503 #endif
504             break;
505         case APP_CPU_NUM:
506             REG_CLR_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR);
507 #ifdef PMS_DEBUG_ASSERTIONS
508             HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR) == 0) && "Value not stored to required register");
509 #endif
510             break;
511         default:
512             return MEMP_HAL_ERR_CORE_INVALID;
513     }
514 
515     return MEMP_HAL_OK;
516 }
517 
memprot_ll_iram0_get_monitor_intrclr(const int core,bool * cleared)518 static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_intrclr(const int core, bool* cleared)
519 {
520     switch (core) {
521         case PRO_CPU_NUM:
522             *cleared = REG_GET_BIT(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR) > 0;
523             break;
524         case APP_CPU_NUM:
525             *cleared = REG_GET_BIT(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR) > 0;
526             break;
527         default:
528             return MEMP_HAL_ERR_CORE_INVALID;
529     }
530 
531     return MEMP_HAL_OK;
532 }
533 
memprot_ll_iram0_get_monitor_enable_register(const int core,uint32_t * regval)534 static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_enable_register(const int core, uint32_t* regval)
535 {
536     switch (core) {
537         case PRO_CPU_NUM:
538             *regval = REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG);
539             break;
540         case APP_CPU_NUM:
541             *regval = REG_READ(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG);
542             break;
543         default:
544             return MEMP_HAL_ERR_CORE_INVALID;
545     }
546 
547     return MEMP_HAL_OK;
548 }
549 
550 // permission violation status
memprot_ll_iram0_get_monitor_status_intr(const int core,uint32_t * regval)551 static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_intr(const int core, uint32_t* regval)
552 {
553     switch (core) {
554         case PRO_CPU_NUM:
555             *regval = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR);
556             break;
557         case APP_CPU_NUM:
558             *regval = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR);
559             break;
560         default:
561             return MEMP_HAL_ERR_CORE_INVALID;
562     }
563 
564     return MEMP_HAL_OK;
565 }
566 
memprot_ll_iram0_get_monitor_status_fault_wr(const int core,uint32_t * regval)567 static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_fault_wr(const int core, uint32_t* regval)
568 {
569     switch (core) {
570         case PRO_CPU_NUM:
571             *regval = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR);
572             break;
573         case APP_CPU_NUM:
574             *regval = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR);
575             break;
576         default:
577             return MEMP_HAL_ERR_CORE_INVALID;
578     }
579 
580     return MEMP_HAL_OK;
581 }
582 
memprot_ll_iram0_get_monitor_status_fault_loadstore(const int core,uint32_t * regval)583 static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_fault_loadstore(const int core, uint32_t* regval)
584 {
585     switch (core) {
586         case PRO_CPU_NUM:
587             *regval = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE);
588             break;
589         case APP_CPU_NUM:
590             *regval = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE);
591             break;
592         default:
593             return MEMP_HAL_ERR_CORE_INVALID;
594     }
595 
596     return MEMP_HAL_OK;
597 }
598 
memprot_ll_iram0_get_monitor_status_fault_world(const int core,uint32_t * regval)599 static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_fault_world(const int core, uint32_t* regval)
600 {
601     switch (core) {
602         case PRO_CPU_NUM:
603             *regval = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD);
604             break;
605         case APP_CPU_NUM:
606             *regval = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD);
607             break;
608         default:
609             return MEMP_HAL_ERR_CORE_INVALID;
610     }
611 
612     return MEMP_HAL_OK;
613 }
614 
memprot_ll_iram0_get_monitor_status_fault_addr(const int core,void ** addr)615 static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_fault_addr(const int core, void** addr)
616 {
617     uint32_t reg_off;
618 
619     switch (core) {
620         case PRO_CPU_NUM:
621             reg_off = REG_GET_FIELD(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR);
622             break;
623         case APP_CPU_NUM:
624             reg_off = REG_GET_FIELD(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR);
625             break;
626         default:
627             return MEMP_HAL_ERR_CORE_INVALID;
628     }
629 
630     *addr = (void*)(reg_off > 0 ? (reg_off << I_FAULT_ADDR_SHIFT) + IRAM0_VIOLATE_STATUS_ADDR_OFFSET : 0);
631 
632     return MEMP_HAL_OK;
633 }
634 
memprot_ll_iram0_get_monitor_status_register(const int core,uint32_t * regval)635 static inline memprot_hal_err_t memprot_ll_iram0_get_monitor_status_register(const int core, uint32_t* regval)
636 {
637     switch (core) {
638         case PRO_CPU_NUM:
639             *regval = REG_READ(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG);
640             break;
641         case APP_CPU_NUM:
642             *regval = REG_READ(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG);
643             break;
644         default:
645             return MEMP_HAL_ERR_CORE_INVALID;
646     }
647 
648     return MEMP_HAL_OK;
649 }
650 
651 
652 /* ******************************************************************************************************
653  * *** RTC_FAST ***
654  */
655 
memprot_ll_rtcfast_get_intr_source_num(const int core,uint32_t * src_num)656 static inline memprot_hal_err_t memprot_ll_rtcfast_get_intr_source_num(const int core, uint32_t* src_num)
657 {
658     switch (core) {
659         case PRO_CPU_NUM:
660             *src_num = ETS_CORE0_PIF_PMS_INTR_SOURCE;
661             break;
662         case APP_CPU_NUM:
663             *src_num = ETS_CORE1_PIF_PMS_INTR_SOURCE;
664             break;
665         default:
666             return MEMP_HAL_ERR_CORE_INVALID;
667     }
668 
669     return MEMP_HAL_OK;
670 }
671 
672 //shared PIF PMS lock
673 //!!!: use after ALL the constraints have been set
memprot_ll_set_pif_constraint_lock(const int core)674 static inline memprot_hal_err_t memprot_ll_set_pif_constraint_lock(const int core)
675 {
676     switch (core) {
677         case PRO_CPU_NUM:
678             REG_WRITE(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG, 1);
679 #ifdef PMS_DEBUG_ASSERTIONS
680             HAL_ASSERT((REG_READ(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG) == 1) && "Value not stored to required register");
681 #endif
682             break;
683         case APP_CPU_NUM:
684             REG_WRITE(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG, 1);
685 #ifdef PMS_DEBUG_ASSERTIONS
686             HAL_ASSERT((REG_READ(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG) == 1) && "Value not stored to required register");
687 #endif
688             break;
689         default:
690             return MEMP_HAL_ERR_CORE_INVALID;
691     }
692 
693     return MEMP_HAL_OK;
694 }
695 
memprot_ll_get_pif_constraint_lock(const int core,bool * locked)696 static inline memprot_hal_err_t memprot_ll_get_pif_constraint_lock(const int core, bool* locked)
697 {
698     switch (core) {
699         case PRO_CPU_NUM:
700             *locked = REG_READ(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG) == 1;
701             break;
702         case APP_CPU_NUM:
703             *locked = REG_READ(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG) == 1;
704             break;
705         default:
706             return MEMP_HAL_ERR_CORE_INVALID;
707     }
708 
709     return MEMP_HAL_OK;
710 }
711 
memprot_ll_rtcfast_get_splitaddr_register(const int core,uint32_t * regval)712 static inline memprot_hal_err_t memprot_ll_rtcfast_get_splitaddr_register(const int core, uint32_t* regval)
713 {
714     switch (core) {
715         case PRO_CPU_NUM:
716             *regval = REG_READ(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG);
717             break;
718         case APP_CPU_NUM:
719             *regval = REG_READ(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_REG);
720             break;
721         default:
722             return MEMP_HAL_ERR_CORE_INVALID;
723     }
724 
725     return MEMP_HAL_OK;
726 }
727 
728 /* ********************************
729  * IRAM0 RTCFAST - SPLIT LINES
730  */
731 
memprot_ll_set_rtcfast_split_line(const int core,const void * line_addr,const memprot_hal_world_t world)732 static inline memprot_hal_err_t memprot_ll_set_rtcfast_split_line(const int core, const void *line_addr, const memprot_hal_world_t world)
733 {
734     uint32_t addr = (uint32_t)line_addr;
735 
736     if (addr < SOC_RTC_IRAM_LOW || addr >= SOC_RTC_IRAM_HIGH) {
737         return MEMP_HAL_ERR_SPLIT_ADDR_OUT_OF_RANGE;
738     }
739 
740     if (addr % 0x4 != 0) {
741         return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED;
742     }
743 
744     if (core != PRO_CPU_NUM && core != APP_CPU_NUM) {
745         return MEMP_HAL_ERR_CORE_INVALID;
746     }
747 
748     uint32_t mask;
749     uint32_t val;
750 
751     switch (world) {
752     case MEMP_HAL_WORLD_0:
753         mask = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M;
754         val = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V;
755         break;
756     case MEMP_HAL_WORLD_1:
757         mask = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M;
758         val = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V;
759         break;
760     default:
761         return MEMP_HAL_ERR_WORLD_INVALID;
762     }
763 
764     uint32_t reg = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_REG;
765 
766     CLEAR_PERI_REG_MASK(reg, mask);
767 #ifdef PMS_DEBUG_ASSERTIONS
768     HAL_ASSERT((GET_PERI_REG_MASK(reg, mask) == 0) && "Value not stored to required register");
769 #endif
770     REG_SET_BITS(reg, mask, (addr >> 2) & val);
771 #ifdef PMS_DEBUG_ASSERTIONS
772     uint32_t expected = REG_READ(reg) & mask;
773     HAL_ASSERT((expected == ((addr >> 2) & val)) && "Value not stored to required register");
774 #endif
775     return MEMP_HAL_OK;
776 }
777 
memprot_ll_get_rtcfast_split_line(const int core,const memprot_hal_world_t world,void ** line_addr)778 static inline memprot_hal_err_t memprot_ll_get_rtcfast_split_line(const int core, const memprot_hal_world_t world, void **line_addr)
779 {
780     if (core != PRO_CPU_NUM && core != APP_CPU_NUM) {
781         return MEMP_HAL_ERR_CORE_INVALID;
782     }
783 
784     uint32_t mask;
785     uint32_t shift;
786 
787     switch (world) {
788     case MEMP_HAL_WORLD_0:
789         mask = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M;
790         shift = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S;
791         break;
792     case MEMP_HAL_WORLD_1:
793         mask = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M;
794         shift = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S;
795         break;
796     default:
797         return MEMP_HAL_ERR_WORLD_INVALID;
798     }
799 
800     uint32_t reg_addr = REG_READ(core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_REG);
801 
802     *line_addr = (void *)((((reg_addr & mask) >> shift) << 2) + SOC_RTC_IRAM_LOW);
803 
804     return MEMP_HAL_OK;
805 }
806 
807 ///////////////////////////////////
808 // RTC_FAST - PMS CONFIGURATION
809 
810 // permission settings
memprot_ll_rtcfast_set_permissions(const bool r,const bool w,const bool x)811 static inline uint32_t memprot_ll_rtcfast_set_permissions(const bool r, const bool w, const bool x)
812 {
813     uint32_t permissions = 0;
814     if (r) {
815         permissions |= SENSITIVE_CORE_X_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R;
816     }
817     if (w) {
818         permissions |= SENSITIVE_CORE_X_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W;
819     }
820     if (x) {
821         permissions |= SENSITIVE_CORE_X_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F;
822     }
823 
824     return permissions;
825 }
826 
memprot_ll_rtcfast_set_pms_area(const int core,const bool r,const bool w,const bool x,const memprot_hal_world_t world,const memprot_hal_area_t area)827 static inline memprot_hal_err_t memprot_ll_rtcfast_set_pms_area(const int core, const bool r, const bool w, const bool x, const memprot_hal_world_t world, const memprot_hal_area_t area)
828 {
829     if (core != PRO_CPU_NUM && core != APP_CPU_NUM) {
830         return MEMP_HAL_ERR_CORE_INVALID;
831     }
832 
833     uint32_t bits;
834     uint32_t mask;
835 
836     switch (world) {
837     case MEMP_HAL_WORLD_0: {
838         switch (area) {
839         case MEMP_HAL_AREA_LOW:
840             bits = memprot_ll_rtcfast_set_permissions(r, w, x) << (core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S);
841             mask = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M;
842             break;
843         case MEMP_HAL_AREA_HIGH:
844             bits = memprot_ll_rtcfast_set_permissions(r, w, x) << (core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S);
845             mask = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M;
846             break;
847         default:
848             return MEMP_HAL_ERR_AREA_INVALID;
849         }
850     } break;
851     case MEMP_HAL_WORLD_1: {
852         switch (area) {
853         case MEMP_HAL_AREA_LOW:
854             bits = memprot_ll_rtcfast_set_permissions(r, w, x) << (core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S);
855             mask = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M;
856             break;
857         case MEMP_HAL_AREA_HIGH:
858             bits = memprot_ll_rtcfast_set_permissions(r, w, x) << (core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S);
859             mask = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M;
860             break;
861         default:
862             return MEMP_HAL_ERR_AREA_INVALID;
863         }
864     } break;
865     default:
866         return MEMP_HAL_ERR_WORLD_INVALID;
867     }
868 
869     uint32_t reg = core == PRO_CPU_NUM ? SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG : SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG;
870 
871     CLEAR_PERI_REG_MASK(reg, mask);
872 #ifdef PMS_DEBUG_ASSERTIONS
873     HAL_ASSERT((GET_PERI_REG_MASK(reg, mask) == 0) && "Value not stored to required register");
874 #endif
875     REG_SET_BITS(reg, bits, mask);
876 #ifdef PMS_DEBUG_ASSERTIONS
877     uint32_t expected = REG_READ(reg) & mask;
878     HAL_ASSERT((expected == bits) && "Value not stored to required register");
879 #endif
880 
881     return MEMP_HAL_OK;
882 }
883 
memprot_ll_rtcfast_get_permissions(const uint32_t perms,bool * r,bool * w,bool * x)884 static inline void memprot_ll_rtcfast_get_permissions(const uint32_t perms, bool *r, bool *w, bool *x)
885 {
886     *r = perms & SENSITIVE_CORE_X_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_R;
887     *w = perms & SENSITIVE_CORE_X_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_W;
888     *x = perms & SENSITIVE_CORE_X_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_X_F;
889 }
890 
memprot_ll_rtcfast_get_pms_area(const int core,bool * r,bool * w,bool * x,const memprot_hal_world_t world,const memprot_hal_area_t area)891 static inline memprot_hal_err_t memprot_ll_rtcfast_get_pms_area(const int core, bool *r, bool *w, bool *x, const memprot_hal_world_t world, const memprot_hal_area_t area)
892 {
893     if (core != PRO_CPU_NUM && core != APP_CPU_NUM) {
894         return MEMP_HAL_ERR_CORE_INVALID;
895     }
896 
897     uint32_t permissions = 0;
898 
899     switch (world) {
900     case MEMP_HAL_WORLD_0: {
901         switch (area) {
902         case MEMP_HAL_AREA_LOW:
903             if (core == PRO_CPU_NUM) {
904                 permissions = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L);
905             } else {
906                 permissions = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L);
907             }
908             break;
909         case MEMP_HAL_AREA_HIGH:
910             if (core == PRO_CPU_NUM) {
911                 permissions = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H);
912             } else {
913                 permissions = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H);
914             }
915             break;
916         default:
917             return MEMP_HAL_ERR_AREA_INVALID;
918         }
919     } break;
920     case MEMP_HAL_WORLD_1: {
921         switch (area) {
922         case MEMP_HAL_AREA_LOW:
923             if (core == PRO_CPU_NUM) {
924                 permissions = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L);
925             } else {
926                 permissions = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L);
927             }
928             break;
929         case MEMP_HAL_AREA_HIGH:
930             if (core == PRO_CPU_NUM) {
931                 permissions = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H);
932             } else {
933                 permissions = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG, SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H);
934             }
935             break;
936         default:
937             return MEMP_HAL_ERR_AREA_INVALID;
938         }
939     } break;
940     default:
941         return MEMP_HAL_ERR_WORLD_INVALID;
942     }
943 
944     memprot_ll_rtcfast_get_permissions(permissions, r, w, x);
945 
946     return MEMP_HAL_OK;
947 }
948 
memprot_ll_rtcfast_get_permission_register(const int core,uint32_t * regval)949 static inline memprot_hal_err_t memprot_ll_rtcfast_get_permission_register(const int core, uint32_t* regval)
950 {
951     switch (core) {
952         case PRO_CPU_NUM:
953             *regval = REG_READ(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG);
954             break;
955         case APP_CPU_NUM:
956             *regval = REG_READ(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG);
957             break;
958         default:
959             return MEMP_HAL_ERR_CORE_INVALID;
960     }
961 
962     return MEMP_HAL_OK;
963 }
964 
965 ///////////////////////////////////
966 // RTC_FAST - MONITOR
967 
968 // lock
memprot_ll_rtcfast_set_monitor_lock(const int core)969 static inline memprot_hal_err_t memprot_ll_rtcfast_set_monitor_lock(const int core)
970 {
971     switch (core) {
972         case PRO_CPU_NUM:
973             REG_WRITE(SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG, 1);
974 #ifdef PMS_DEBUG_ASSERTIONS
975             HAL_ASSERT((REG_READ(SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG) == 1) && "Value not stored to required register");
976 #endif
977             break;
978         case APP_CPU_NUM:
979             REG_WRITE(SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG, 1);
980 #ifdef PMS_DEBUG_ASSERTIONS
981             HAL_ASSERT((REG_READ(SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG) == 1) && "Value not stored to required register");
982 #endif
983             break;
984         default:
985             return MEMP_HAL_ERR_CORE_INVALID;
986     }
987 
988     return MEMP_HAL_OK;
989 }
990 
memprot_ll_rtcfast_get_monitor_lock(const int core,bool * locked)991 static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_lock(const int core, bool* locked)
992 {
993     switch (core) {
994         case PRO_CPU_NUM:
995             *locked = REG_READ(SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG) == 1;
996             break;
997         case APP_CPU_NUM:
998             *locked = REG_READ(SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG) == 1;
999             break;
1000         default:
1001             return MEMP_HAL_ERR_CORE_INVALID;
1002     }
1003 
1004     return MEMP_HAL_OK;
1005 }
1006 
1007 // interrupt enable/clear
memprot_ll_rtcfast_set_monitor_en(const int core,const bool enable)1008 static inline memprot_hal_err_t memprot_ll_rtcfast_set_monitor_en(const int core, const bool enable)
1009 {
1010     switch (core) {
1011         case PRO_CPU_NUM:
1012             if (enable) {
1013                 REG_SET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN);
1014 #ifdef PMS_DEBUG_ASSERTIONS
1015                 HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN) > 0) && "Value not stored to required register");
1016 #endif
1017             } else {
1018                 REG_CLR_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN);
1019 #ifdef PMS_DEBUG_ASSERTIONS
1020                 HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN) == 0) && "Value not stored to required register");
1021 #endif
1022             }
1023             break;
1024         case APP_CPU_NUM:
1025             if (enable) {
1026                 REG_SET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN);
1027 #ifdef PMS_DEBUG_ASSERTIONS
1028                 HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN) > 0) && "Value not stored to required register");
1029 #endif
1030             } else {
1031                 REG_CLR_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN);
1032 #ifdef PMS_DEBUG_ASSERTIONS
1033                 HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN) == 0) && "Value not stored to required register");
1034 #endif
1035             }
1036             break;
1037         default:
1038             return MEMP_HAL_ERR_CORE_INVALID;
1039     }
1040 
1041     return MEMP_HAL_OK;
1042 }
1043 
memprot_ll_rtcfast_get_monitor_en(const int core,bool * enabled)1044 static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_en(const int core, bool* enabled)
1045 {
1046     switch (core) {
1047         case PRO_CPU_NUM:
1048             *enabled = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN) > 0;
1049             break;
1050         case APP_CPU_NUM:
1051             *enabled = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN) > 0;
1052             break;
1053         default:
1054             return MEMP_HAL_ERR_CORE_INVALID;
1055     }
1056 
1057     return MEMP_HAL_OK;
1058 }
1059 
memprot_ll_rtcfast_get_monitor_intrclr(const int core,bool * cleared)1060 static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_intrclr(const int core, bool* cleared)
1061 {
1062     switch (core) {
1063         case PRO_CPU_NUM:
1064             *cleared = REG_GET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR) > 0;
1065             break;
1066         case APP_CPU_NUM:
1067             *cleared = REG_GET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR) > 0;
1068             break;
1069         default:
1070             return MEMP_HAL_ERR_CORE_INVALID;
1071     }
1072 
1073     return MEMP_HAL_OK;
1074 }
1075 
memprot_ll_rtcfast_set_monitor_intrclr(const int core)1076 static inline memprot_hal_err_t memprot_ll_rtcfast_set_monitor_intrclr(const int core)
1077 {
1078     switch (core) {
1079         case PRO_CPU_NUM:
1080             REG_SET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR);
1081 #ifdef PMS_DEBUG_ASSERTIONS
1082             HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR) > 0) && "Value not stored to required register");
1083 #endif
1084             break;
1085         case APP_CPU_NUM:
1086             REG_SET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR);
1087 #ifdef PMS_DEBUG_ASSERTIONS
1088             HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR) > 0) && "Value not stored to required register");
1089 #endif
1090             break;
1091         default:
1092             return MEMP_HAL_ERR_CORE_INVALID;
1093     }
1094 
1095     return MEMP_HAL_OK;
1096 }
1097 
memprot_ll_rtcfast_reset_monitor_intrclr(const int core)1098 static inline memprot_hal_err_t memprot_ll_rtcfast_reset_monitor_intrclr(const int core)
1099 {
1100     switch (core) {
1101         case PRO_CPU_NUM:
1102             REG_CLR_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR);
1103 #ifdef PMS_DEBUG_ASSERTIONS
1104             HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR) == 0) && "Value not stored to required register");
1105 #endif
1106             break;
1107         case APP_CPU_NUM:
1108             REG_CLR_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR);
1109 #ifdef PMS_DEBUG_ASSERTIONS
1110             HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR) == 0) && "Value not stored to required register");
1111 #endif
1112             break;
1113         default:
1114             return MEMP_HAL_ERR_CORE_INVALID;
1115     }
1116 
1117     return MEMP_HAL_OK;
1118 }
1119 
memprot_ll_rtcfast_get_monitor_register(const int core,uint32_t * regval)1120 static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_register(const int core, uint32_t* regval)
1121 {
1122     switch (core) {
1123         case PRO_CPU_NUM:
1124             *regval = REG_READ(SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG);
1125             break;
1126         case APP_CPU_NUM:
1127             *regval = REG_READ(SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG);
1128             break;
1129         default:
1130             return MEMP_HAL_ERR_CORE_INVALID;
1131     }
1132 
1133     return MEMP_HAL_OK;
1134 }
1135 
1136 // permission violation status
memprot_ll_rtcfast_get_monitor_status_intr(const int core,uint32_t * regval)1137 static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_intr(const int core, uint32_t* regval)
1138 {
1139     switch (core) {
1140         case PRO_CPU_NUM:
1141             *regval = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR);
1142             break;
1143         case APP_CPU_NUM:
1144             *regval = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR);
1145             break;
1146         default:
1147             return MEMP_HAL_ERR_CORE_INVALID;
1148     }
1149 
1150     return MEMP_HAL_OK;
1151 }
1152 
memprot_ll_rtcfast_get_monitor_status_fault_addr(const int core,void ** addr)1153 static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_fault_addr(const int core, void** addr)
1154 {
1155     switch (core) {
1156         case PRO_CPU_NUM:
1157             *addr = (void*)REG_READ(SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG);
1158             break;
1159         case APP_CPU_NUM:
1160             *addr = (void*)REG_READ(SENSITIVE_CORE_1_PIF_PMS_MONITOR_3_REG);
1161             break;
1162         default:
1163             return MEMP_HAL_ERR_CORE_INVALID;
1164     }
1165 
1166     return MEMP_HAL_OK;
1167 }
1168 
memprot_ll_rtcfast_get_monitor_status_fault_world(const int core,uint32_t * regval)1169 static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_fault_world(const int core, uint32_t* regval)
1170 {
1171     switch (core) {
1172         case PRO_CPU_NUM:
1173             *regval = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD);
1174             break;
1175         case APP_CPU_NUM:
1176             *regval = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD);
1177             break;
1178         default:
1179             return MEMP_HAL_ERR_CORE_INVALID;
1180     }
1181 
1182     return MEMP_HAL_OK;
1183 }
1184 
memprot_ll_rtcfast_get_monitor_status_fault_loadstore(const int core,uint32_t * regval)1185 static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_fault_loadstore(const int core, uint32_t* regval)
1186 {
1187     switch (core) {
1188         case PRO_CPU_NUM:
1189             *regval = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0);
1190             break;
1191         case APP_CPU_NUM:
1192             *regval = REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0);
1193             break;
1194         default:
1195             return MEMP_HAL_ERR_CORE_INVALID;
1196     }
1197 
1198     return MEMP_HAL_OK;
1199 }
1200 
memprot_ll_rtcfast_get_monitor_status_fault_wr(const int core,uint32_t * regval)1201 static inline memprot_hal_err_t memprot_ll_rtcfast_get_monitor_status_fault_wr(const int core, uint32_t* regval)
1202 {
1203     switch (core) {
1204         case PRO_CPU_NUM:
1205             *regval = REG_GET_FIELD(SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE);
1206             break;
1207         case APP_CPU_NUM:
1208             *regval =  REG_GET_FIELD(SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE);
1209             break;
1210         default:
1211             return MEMP_HAL_ERR_CORE_INVALID;
1212     }
1213 
1214     return MEMP_HAL_OK;
1215 }
1216 
1217 
1218 /* ******************************************************************************************************
1219  * *** DRAM0 ***
1220  * ******************************************************************************************************/
1221 
memprot_ll_dram0_get_intr_source_num(const int core,uint32_t * src_num)1222 static inline memprot_hal_err_t memprot_ll_dram0_get_intr_source_num(const int core, uint32_t* src_num)
1223 {
1224     switch (core) {
1225         case PRO_CPU_NUM:
1226             *src_num = ETS_CORE0_DRAM0_PMS_INTR_SOURCE;
1227             break;
1228         case APP_CPU_NUM:
1229             *src_num = ETS_CORE1_DRAM0_PMS_INTR_SOURCE;
1230             break;
1231         default:
1232             return MEMP_HAL_ERR_CORE_INVALID;
1233     }
1234 
1235     return MEMP_HAL_OK;
1236 }
1237 
1238 ///////////////////////////////////
1239 // DRAM0 - SPLIT LINES
memprot_ll_get_dram0_split_line_main_D_0_regval(void)1240 static inline uint32_t memprot_ll_get_dram0_split_line_main_D_0_regval(void)
1241 {
1242     return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG);
1243 }
1244 
memprot_ll_get_dram0_split_line_main_D_1_regval(void)1245 static inline uint32_t memprot_ll_get_dram0_split_line_main_D_1_regval(void)
1246 {
1247     return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG);
1248 }
1249 
memprot_ll_prepare_dram0_split_line_regval(const uint32_t addr,uint32_t * regval)1250 static inline void memprot_ll_prepare_dram0_split_line_regval(const uint32_t addr, uint32_t* regval)
1251 {
1252     //set category bits for given split line
1253     uint32_t cat[7] = {[0 ... 6]=MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_ABOVE_SA};
1254     for (size_t x=0; x<7; x++) {
1255         if (addr <= MAP_IRAM_TO_DRAM(sram_rg3_level_hlimits[x])) {
1256             cat[x] = MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_EQUAL_SA;
1257             break;
1258         } else {
1259             cat[x] = MEMP_HAL_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_BITS_BELOW_SA;
1260         }
1261     }
1262 
1263     //resolve split address' significant bits
1264     uint32_t conf_add = ((addr >> I_D_SPLIT_LINE_SHIFT) & SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V);
1265 
1266     //write values to required configuration-register
1267     constrain_reg_fields_t cfg_reg_val = {
1268             .cat0 = cat[0],
1269             .cat1 = cat[1],
1270             .cat2 = cat[2],
1271             .cat3 = cat[3],
1272             .cat4 = cat[4],
1273             .cat5 = cat[5],
1274             .cat6 = cat[6],
1275             .splitaddr = conf_add,
1276             .reserved = 0
1277     };
1278 
1279 
1280     *regval = cfg_reg_val.val;
1281 }
1282 
memprot_ll_set_dram0_split_line(const void * line_addr,const uint32_t sensitive_reg)1283 static inline memprot_hal_err_t memprot_ll_set_dram0_split_line(const void *line_addr, const uint32_t sensitive_reg)
1284 {
1285     uint32_t addr = (uint32_t)line_addr;
1286 
1287     //sanity check
1288     MEMP_HAL_CHECK_DRAM_ADDR_IN_RANGE(addr)
1289     MEMP_HAL_CHECK_SPLIT_ADDR_ALIGNED(addr)
1290 
1291     uint32_t regval;
1292     memprot_ll_prepare_dram0_split_line_regval(addr, &regval);
1293 
1294     REG_WRITE(sensitive_reg, regval);
1295 #ifdef PMS_DEBUG_ASSERTIONS
1296     HAL_ASSERT((REG_READ(sensitive_reg) == regval) && "Value not stored to required register");
1297 #endif
1298 
1299     return MEMP_HAL_OK;
1300 }
1301 
memprot_ll_set_dram0_split_line_D_0(const void * line_addr)1302 static inline memprot_hal_err_t memprot_ll_set_dram0_split_line_D_0(const void *line_addr)
1303 {
1304     return memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG);
1305 }
1306 
memprot_ll_set_dram0_split_line_D_1(const void * line_addr)1307 static inline memprot_hal_err_t memprot_ll_set_dram0_split_line_D_1(const void *line_addr)
1308 {
1309     return memprot_ll_set_dram0_split_line(line_addr, SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG);
1310 }
1311 
memprot_ll_get_dram0_split_line_D_0(void)1312 static inline void *memprot_ll_get_dram0_split_line_D_0(void)
1313 {
1314     return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG), SOC_DIRAM_DRAM_LOW);
1315 }
1316 
memprot_ll_get_dram0_split_line_D_1(void)1317 static inline void *memprot_ll_get_dram0_split_line_D_1(void)
1318 {
1319     return memprot_ll_get_split_addr_from_reg(REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG), SOC_DIRAM_DRAM_LOW);
1320 }
1321 
memprot_ll_get_dram0_split_line_D_0_cat(void)1322 static inline uint32_t memprot_ll_get_dram0_split_line_D_0_cat(void)
1323 {
1324     return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG) & 0x3FFF;
1325 }
1326 
memprot_ll_get_dram0_split_line_D_1_cat(void)1327 static inline uint32_t memprot_ll_get_dram0_split_line_D_1_cat(void)
1328 {
1329     return REG_READ(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG) & 0x3FFF;
1330 }
1331 
1332 ///////////////////////////////////
1333 // DRAM0 - PMS CONFIGURATION
1334 
1335 // lock
memprot_ll_dram0_set_pms_lock(void)1336 static inline void memprot_ll_dram0_set_pms_lock(void)
1337 {
1338     REG_WRITE(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG, 1);
1339 #ifdef PMS_DEBUG_ASSERTIONS
1340     HAL_ASSERT((REG_READ(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG) == 1) && "Value not stored to required register");
1341 #endif
1342 }
1343 
memprot_ll_dram0_get_pms_lock(void)1344 static inline bool memprot_ll_dram0_get_pms_lock(void)
1345 {
1346     return REG_READ(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG) == 1;
1347 }
1348 
1349 // permission settings
memprot_ll_dram0_set_permissions(const bool r,const bool w)1350 static inline uint32_t memprot_ll_dram0_set_permissions(const bool r, const bool w)
1351 {
1352     uint32_t permissions = 0;
1353     if (r) {
1354         permissions |= SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R;
1355     }
1356     if (w) {
1357         permissions |= SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W;
1358     }
1359 
1360     return permissions;
1361 }
1362 
memprot_ll_dram0_set_pms_area_0(const bool r,const bool w)1363 static inline void memprot_ll_dram0_set_pms_area_0(const bool r, const bool w)
1364 {
1365     REG_SET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0, memprot_ll_dram0_set_permissions(r, w));
1366 #ifdef PMS_DEBUG_ASSERTIONS
1367     uint32_t expected = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0);
1368     HAL_ASSERT((expected == memprot_ll_dram0_set_permissions(r, w)) && "Value not stored to required register");
1369 #endif
1370 }
1371 
memprot_ll_dram0_set_pms_area_1(const bool r,const bool w)1372 static inline void memprot_ll_dram0_set_pms_area_1(const bool r, const bool w)
1373 {
1374     REG_SET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1, memprot_ll_dram0_set_permissions(r, w));
1375 #ifdef PMS_DEBUG_ASSERTIONS
1376     uint32_t expected = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1);
1377     HAL_ASSERT((expected == memprot_ll_dram0_set_permissions(r, w)) && "Value not stored to required register");
1378 #endif
1379 }
1380 
memprot_ll_dram0_set_pms_area_2(const bool r,const bool w)1381 static inline void memprot_ll_dram0_set_pms_area_2(const bool r, const bool w)
1382 {
1383     REG_SET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2, memprot_ll_dram0_set_permissions(r, w));
1384 #ifdef PMS_DEBUG_ASSERTIONS
1385     uint32_t expected = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2);
1386     HAL_ASSERT((expected == memprot_ll_dram0_set_permissions(r, w)) && "Value not stored to required register");
1387 #endif
1388 }
1389 
memprot_ll_dram0_set_pms_area_3(const bool r,const bool w)1390 static inline void memprot_ll_dram0_set_pms_area_3(const bool r, const bool w)
1391 {
1392     REG_SET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3, memprot_ll_dram0_set_permissions(r, w));
1393 #ifdef PMS_DEBUG_ASSERTIONS
1394     uint32_t expected = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3);
1395     HAL_ASSERT((expected == memprot_ll_dram0_set_permissions(r, w)) && "Value not stored to required register");
1396 #endif
1397 }
1398 
memprot_ll_dram0_get_permissions(const uint32_t perms,bool * r,bool * w)1399 static inline void memprot_ll_dram0_get_permissions(const uint32_t perms, bool *r, bool *w )
1400 {
1401     *r = perms & SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_R;
1402     *w = perms & SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_X_W;
1403 }
1404 
memprot_ll_dram0_get_pms_area_0(bool * r,bool * w)1405 static inline void memprot_ll_dram0_get_pms_area_0(bool *r, bool *w)
1406 {
1407     uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0);
1408     memprot_ll_dram0_get_permissions(permissions, r, w);
1409 }
1410 
memprot_ll_dram0_get_pms_area_1(bool * r,bool * w)1411 static inline void memprot_ll_dram0_get_pms_area_1(bool *r, bool *w)
1412 {
1413     uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1);
1414     memprot_ll_dram0_get_permissions(permissions, r, w);
1415 }
1416 
memprot_ll_dram0_get_pms_area_2(bool * r,bool * w)1417 static inline void memprot_ll_dram0_get_pms_area_2(bool *r, bool *w)
1418 {
1419     uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2);
1420     memprot_ll_dram0_get_permissions(permissions, r, w);
1421 }
1422 
memprot_ll_dram0_get_pms_area_3(bool * r,bool * w)1423 static inline void memprot_ll_dram0_get_pms_area_3(bool *r, bool *w)
1424 {
1425     uint32_t permissions = REG_GET_FIELD(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3);
1426     memprot_ll_dram0_get_permissions(permissions, r, w);
1427 }
1428 
1429 
1430 ///////////////////////////////////
1431 // DRAM0 - MONITOR
1432 
1433 // lock
memprot_ll_dram0_set_monitor_lock(const int core)1434 static inline memprot_hal_err_t memprot_ll_dram0_set_monitor_lock(const int core)
1435 {
1436     switch (core) {
1437         case PRO_CPU_NUM:
1438             REG_WRITE(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG, 1);
1439 #ifdef PMS_DEBUG_ASSERTIONS
1440             HAL_ASSERT((REG_READ(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG) == 1) && "Value not stored to required register");
1441 #endif
1442             break;
1443         case APP_CPU_NUM:
1444             REG_WRITE(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG, 1);
1445 #ifdef PMS_DEBUG_ASSERTIONS
1446             HAL_ASSERT((REG_READ(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG) == 1) && "Value not stored to required register");
1447 #endif
1448             break;
1449         default:
1450             return MEMP_HAL_ERR_CORE_INVALID;
1451     }
1452 
1453     return MEMP_HAL_OK;
1454 }
1455 
memprot_ll_dram0_get_monitor_lock(const int core,bool * locked)1456 static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_lock(const int core, bool* locked)
1457 {
1458     switch (core) {
1459         case PRO_CPU_NUM:
1460             *locked = REG_READ(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG) == 1;
1461             break;
1462         case APP_CPU_NUM:
1463             *locked = REG_READ(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG) == 1;
1464             break;
1465         default:
1466             return MEMP_HAL_ERR_CORE_INVALID;
1467     }
1468 
1469     return MEMP_HAL_OK;
1470 }
1471 
1472 // interrupt enable/clear
memprot_ll_dram0_set_monitor_en(const int core,const bool enable)1473 static inline memprot_hal_err_t memprot_ll_dram0_set_monitor_en(const int core, const bool enable)
1474 {
1475     switch (core) {
1476         case PRO_CPU_NUM:
1477             if (enable) {
1478                 REG_SET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN);
1479 #ifdef PMS_DEBUG_ASSERTIONS
1480                 HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN) > 0) && "Value not stored to required register");
1481 #endif
1482             } else {
1483                 REG_CLR_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN);
1484 #ifdef PMS_DEBUG_ASSERTIONS
1485                 HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN) == 0) && "Value not stored to required register");
1486 #endif
1487             }
1488             break;
1489         case APP_CPU_NUM:
1490             if (enable) {
1491                 REG_SET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN);
1492 #ifdef PMS_DEBUG_ASSERTIONS
1493                 HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN) > 0) && "Value not stored to required register");
1494 #endif
1495             } else {
1496                 REG_CLR_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN);
1497 #ifdef PMS_DEBUG_ASSERTIONS
1498                 HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN) == 0) && "Value not stored to required register");
1499 #endif
1500             }
1501             break;
1502         default:
1503             return MEMP_HAL_ERR_CORE_INVALID;
1504     }
1505 
1506     return MEMP_HAL_OK;
1507 }
1508 
memprot_ll_dram0_get_monitor_en(const int core,bool * enabled)1509 static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_en(const int core, bool* enabled)
1510 {
1511     switch (core) {
1512         case PRO_CPU_NUM:
1513             *enabled = REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN) > 0;
1514             break;
1515         case APP_CPU_NUM:
1516             *enabled = REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN) > 0;
1517             break;
1518         default:
1519             return MEMP_HAL_ERR_CORE_INVALID;
1520     }
1521 
1522     return MEMP_HAL_OK;
1523 }
1524 
memprot_ll_dram0_set_monitor_intrclr(const int core)1525 static inline memprot_hal_err_t memprot_ll_dram0_set_monitor_intrclr(const int core)
1526 {
1527     switch (core) {
1528         case PRO_CPU_NUM:
1529             REG_SET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR);
1530 #ifdef PMS_DEBUG_ASSERTIONS
1531             HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR) > 0) && "Value not stored to required register");
1532 #endif
1533             break;
1534         case APP_CPU_NUM:
1535             REG_SET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR);
1536 #ifdef PMS_DEBUG_ASSERTIONS
1537             HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR) > 0) && "Value not stored to required register");
1538 #endif
1539             break;
1540         default:
1541             return MEMP_HAL_ERR_CORE_INVALID;
1542     }
1543 
1544     return MEMP_HAL_OK;
1545 }
1546 
memprot_ll_dram0_reset_monitor_intrclr(const int core)1547 static inline memprot_hal_err_t memprot_ll_dram0_reset_monitor_intrclr(const int core)
1548 {
1549     switch (core) {
1550         case PRO_CPU_NUM:
1551             REG_CLR_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR);
1552 #ifdef PMS_DEBUG_ASSERTIONS
1553             HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR) == 0) && "Value not stored to required register");
1554 #endif
1555             break;
1556         case APP_CPU_NUM:
1557             REG_CLR_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR);
1558 #ifdef PMS_DEBUG_ASSERTIONS
1559             HAL_ASSERT((REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR) == 0) && "Value not stored to required register");
1560 #endif
1561             break;
1562         default:
1563             return MEMP_HAL_ERR_CORE_INVALID;
1564     }
1565 
1566     return MEMP_HAL_OK;
1567 }
1568 
memprot_ll_dram0_get_monitor_intrclr(const int core,bool * cleared)1569 static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_intrclr(const int core, bool* cleared)
1570 {
1571     switch (core) {
1572         case PRO_CPU_NUM:
1573             *cleared = REG_GET_BIT(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR) > 0;
1574             break;
1575         case APP_CPU_NUM:
1576             *cleared = REG_GET_BIT(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR) > 0;
1577             break;
1578         default:
1579             return MEMP_HAL_ERR_CORE_INVALID;
1580     }
1581 
1582     return MEMP_HAL_OK;
1583 }
1584 
memprot_ll_dram0_get_monitor_enable_register(const int core,uint32_t * regval)1585 static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_enable_register(const int core, uint32_t* regval)
1586 {
1587     switch (core) {
1588         case PRO_CPU_NUM:
1589             *regval = REG_READ(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG);
1590             break;
1591         case APP_CPU_NUM:
1592             *regval = REG_READ(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG);
1593             break;
1594         default:
1595             return MEMP_HAL_ERR_CORE_INVALID;
1596     }
1597 
1598     return MEMP_HAL_OK;
1599 }
1600 
1601 // permission violation status
memprot_ll_dram0_get_monitor_status_intr(const int core,uint32_t * regval)1602 static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_intr(const int core, uint32_t* regval)
1603 {
1604     switch (core) {
1605         case PRO_CPU_NUM:
1606             *regval = REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR);
1607             break;
1608         case APP_CPU_NUM:
1609             *regval = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR);
1610             break;
1611         default:
1612             return MEMP_HAL_ERR_CORE_INVALID;
1613     }
1614 
1615     return MEMP_HAL_OK;
1616 }
1617 
memprot_ll_dram0_get_monitor_status_fault_world(const int core,uint32_t * regval)1618 static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_fault_world(const int core, uint32_t* regval)
1619 {
1620     switch (core) {
1621         case PRO_CPU_NUM:
1622             *regval = REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD);
1623             break;
1624         case APP_CPU_NUM:
1625             *regval = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD);
1626             break;
1627         default:
1628             return MEMP_HAL_ERR_CORE_INVALID;
1629     }
1630 
1631     return MEMP_HAL_OK;
1632 }
1633 
memprot_ll_dram0_get_monitor_status_fault_addr(const int core,void ** addr)1634 static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_fault_addr(const int core, void** addr)
1635 {
1636     uint32_t reg_off;
1637 
1638     switch (core) {
1639         case PRO_CPU_NUM:
1640             reg_off = REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR);
1641             break;
1642         case APP_CPU_NUM:
1643             reg_off = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR);
1644             break;
1645         default:
1646             return MEMP_HAL_ERR_CORE_INVALID;
1647     }
1648 
1649     *addr = (void*)(reg_off > 0 ? (reg_off << D_FAULT_ADDR_SHIFT) + DRAM0_VIOLATE_STATUS_ADDR_OFFSET : 0);
1650 
1651     return MEMP_HAL_OK;
1652 }
1653 
memprot_ll_dram0_get_monitor_status_fault_wr(const int core,uint32_t * regval)1654 static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_fault_wr(const int core, uint32_t* regval)
1655 {
1656     switch (core) {
1657         case PRO_CPU_NUM:
1658             *regval = REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR);
1659             break;
1660         case APP_CPU_NUM:
1661             *regval = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_3_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR);
1662             break;
1663         default:
1664             return MEMP_HAL_ERR_CORE_INVALID;
1665     }
1666 
1667     return MEMP_HAL_OK;
1668 }
1669 
memprot_ll_dram0_get_monitor_status_fault_byte_en(const int core,uint32_t * regval)1670 static inline memprot_hal_err_t memprot_ll_dram0_get_monitor_status_fault_byte_en(const int core, uint32_t* regval)
1671 {
1672     switch (core) {
1673         case PRO_CPU_NUM:
1674             *regval = REG_GET_FIELD(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN);
1675             break;
1676         case APP_CPU_NUM:
1677             *regval = REG_GET_FIELD(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG, SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN);
1678             break;
1679         default:
1680             return MEMP_HAL_ERR_CORE_INVALID;
1681     }
1682 
1683     return MEMP_HAL_OK;
1684 }
1685 
1686 #ifdef __cplusplus
1687 }
1688 #endif
1689