1 /*
2 * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #pragma once
8
9 #include <stdbool.h>
10 #include "soc/memprot_defs.h"
11 #include "hal/memprot_types.h"
12 #include "soc/dport_reg.h"
13
14 #ifdef __cplusplus
15 extern "C" {
16 #endif
17
18 /**
19 * ========================================================================================
20 * === IRAM0 common
21 * ========================================================================================
22 */
memprot_ll_iram0_clear_intr(void)23 static inline void memprot_ll_iram0_clear_intr(void)
24 {
25 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_4_REG, DPORT_PMS_PRO_IRAM0_ILG_CLR);
26 DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_4_REG, DPORT_PMS_PRO_IRAM0_ILG_CLR);
27 }
28
memprot_ll_iram0_get_intr_source_num(void)29 static inline uint32_t memprot_ll_iram0_get_intr_source_num(void)
30 {
31 return ETS_PMS_PRO_IRAM0_ILG_INTR_SOURCE;
32 }
33
memprot_ll_iram0_intr_ena(bool enable)34 static inline void memprot_ll_iram0_intr_ena(bool enable)
35 {
36 if (enable) {
37 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_4_REG, DPORT_PMS_PRO_IRAM0_ILG_EN);
38 } else {
39 DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_4_REG, DPORT_PMS_PRO_IRAM0_ILG_EN);
40 }
41 }
42
memprot_ll_iram0_get_conf_reg(void)43 static inline uint32_t memprot_ll_iram0_get_conf_reg(void)
44 {
45 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_IRAM0_4_REG);
46 }
47
memprot_ll_iram0_get_fault_reg(void)48 static inline uint32_t memprot_ll_iram0_get_fault_reg(void)
49 {
50 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_IRAM0_5_REG);
51 }
52
memprot_ll_iram0_get_fault_op_type(uint32_t * op_type,uint32_t * op_subtype)53 static inline void memprot_ll_iram0_get_fault_op_type(uint32_t *op_type, uint32_t *op_subtype)
54 {
55 uint32_t status_bits = memprot_ll_iram0_get_fault_reg();
56 *op_type = (uint32_t)status_bits & IRAM0_INTR_ST_OP_RW_BIT;
57 *op_subtype = (uint32_t)status_bits & IRAM0_INTR_ST_OP_TYPE_BIT;
58 }
59
memprot_ll_iram0_is_assoc_intr(void)60 static inline bool memprot_ll_iram0_is_assoc_intr(void)
61 {
62 return DPORT_GET_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_4_REG, DPORT_PMS_PRO_IRAM0_ILG_INTR) > 0;
63 }
64
memprot_ll_iram0_get_intr_ena_bit(void)65 static inline uint32_t memprot_ll_iram0_get_intr_ena_bit(void)
66 {
67 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_4_REG, DPORT_PMS_PRO_IRAM0_ILG_EN);
68 }
69
memprot_ll_iram0_get_intr_on_bit(void)70 static inline uint32_t memprot_ll_iram0_get_intr_on_bit(void)
71 {
72 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_4_REG, DPORT_PMS_PRO_IRAM0_ILG_INTR);
73 }
74
memprot_ll_iram0_get_intr_clr_bit(void)75 static inline uint32_t memprot_ll_iram0_get_intr_clr_bit(void)
76 {
77 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_4_REG, DPORT_PMS_PRO_IRAM0_ILG_CLR);
78 }
79
80 //resets automatically on CPU restart
memprot_ll_iram0_set_lock(void)81 static inline void memprot_ll_iram0_set_lock(void)
82 {
83 DPORT_WRITE_PERI_REG( DPORT_PMS_PRO_IRAM0_0_REG, DPORT_PMS_PRO_IRAM0_LOCK);
84 }
85
memprot_ll_iram0_get_lock_reg(void)86 static inline uint32_t memprot_ll_iram0_get_lock_reg(void)
87 {
88 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_IRAM0_0_REG);
89 }
90
memprot_ll_iram0_get_lock_bit(void)91 static inline uint32_t memprot_ll_iram0_get_lock_bit(void)
92 {
93 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_0_REG, DPORT_PMS_PRO_IRAM0_LOCK);
94 }
95
96 /**
97 * ========================================================================================
98 * === IRAM0 SRAM
99 * ========================================================================================
100 */
memprot_ll_iram0_sram_get_fault_address(void)101 static inline intptr_t memprot_ll_iram0_sram_get_fault_address(void)
102 {
103 uint32_t status_bits = memprot_ll_iram0_get_fault_reg();
104 return (intptr_t)((status_bits & IRAM0_INTR_ST_FAULTADDR_M) | IRAM0_SRAM_INTR_ST_FAULTADDR_HI);
105 }
106
memprot_ll_iram0_sram_is_intr_mine(void)107 static inline bool memprot_ll_iram0_sram_is_intr_mine(void)
108 {
109 if (memprot_ll_iram0_is_assoc_intr()) {
110 uint32_t faulting_address = (uint32_t)memprot_ll_iram0_sram_get_fault_address();
111 return faulting_address >= IRAM0_SRAM_ADDRESS_LOW && faulting_address <= IRAM0_SRAM_ADDRESS_HIGH;
112 }
113 return false;
114 }
115
116 //block 0-3
memprot_ll_iram0_sram_set_uni_block_perm(uint32_t block,bool write_perm,bool read_perm,bool exec_perm)117 static inline bool memprot_ll_iram0_sram_set_uni_block_perm(uint32_t block, bool write_perm, bool read_perm, bool exec_perm)
118 {
119 uint32_t write_bit, read_bit, exec_bit;
120
121 switch (block) {
122 case IRAM0_SRAM_UNI_BLOCK_0:
123 write_bit = DPORT_PMS_PRO_IRAM0_SRAM_0_W;
124 read_bit = DPORT_PMS_PRO_IRAM0_SRAM_0_R;
125 exec_bit = DPORT_PMS_PRO_IRAM0_SRAM_0_F;
126 break;
127 case IRAM0_SRAM_UNI_BLOCK_1:
128 write_bit = DPORT_PMS_PRO_IRAM0_SRAM_1_W;
129 read_bit = DPORT_PMS_PRO_IRAM0_SRAM_1_R;
130 exec_bit = DPORT_PMS_PRO_IRAM0_SRAM_1_F;
131 break;
132 case IRAM0_SRAM_UNI_BLOCK_2:
133 write_bit = DPORT_PMS_PRO_IRAM0_SRAM_2_W;
134 read_bit = DPORT_PMS_PRO_IRAM0_SRAM_2_R;
135 exec_bit = DPORT_PMS_PRO_IRAM0_SRAM_2_F;
136 break;
137 case IRAM0_SRAM_UNI_BLOCK_3:
138 write_bit = DPORT_PMS_PRO_IRAM0_SRAM_3_W;
139 read_bit = DPORT_PMS_PRO_IRAM0_SRAM_3_R;
140 exec_bit = DPORT_PMS_PRO_IRAM0_SRAM_3_F;
141 break;
142 default:
143 return false;
144 }
145
146 if (write_perm) {
147 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_1_REG, write_bit);
148 } else {
149 DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_1_REG, write_bit);
150 }
151
152 if (read_perm) {
153 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_1_REG, read_bit);
154 } else {
155 DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_1_REG, read_bit);
156 }
157
158 if (exec_perm) {
159 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_1_REG, exec_bit);
160 } else {
161 DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_IRAM0_1_REG, exec_bit);
162 }
163
164 return true;
165 }
166
memprot_ll_iram0_sram_get_uni_block_read_bit(uint32_t block,uint32_t * read_bit)167 static inline bool memprot_ll_iram0_sram_get_uni_block_read_bit(uint32_t block, uint32_t *read_bit)
168 {
169 switch (block) {
170 case IRAM0_SRAM_UNI_BLOCK_0:
171 *read_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_0_R);
172 break;
173 case IRAM0_SRAM_UNI_BLOCK_1:
174 *read_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_1_R);
175 break;
176 case IRAM0_SRAM_UNI_BLOCK_2:
177 *read_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_2_R);
178 break;
179 case IRAM0_SRAM_UNI_BLOCK_3:
180 *read_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_3_R);
181 break;
182 default:
183 return false;
184 }
185
186 return true;
187 }
188
memprot_ll_iram0_sram_get_uni_block_write_bit(uint32_t block,uint32_t * write_bit)189 static inline bool memprot_ll_iram0_sram_get_uni_block_write_bit(uint32_t block, uint32_t *write_bit)
190 {
191 switch (block) {
192 case IRAM0_SRAM_UNI_BLOCK_0:
193 *write_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_0_W);
194 break;
195 case IRAM0_SRAM_UNI_BLOCK_1:
196 *write_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_1_W);
197 break;
198 case IRAM0_SRAM_UNI_BLOCK_2:
199 *write_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_2_W);
200 break;
201 case IRAM0_SRAM_UNI_BLOCK_3:
202 *write_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_3_W);
203 break;
204 default:
205 return false;
206 }
207
208 return true;
209 }
210
memprot_ll_iram0_sram_get_uni_block_exec_bit(uint32_t block,uint32_t * exec_bit)211 static inline bool memprot_ll_iram0_sram_get_uni_block_exec_bit(uint32_t block, uint32_t *exec_bit)
212 {
213 switch (block) {
214 case IRAM0_SRAM_UNI_BLOCK_0:
215 *exec_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_0_F);
216 break;
217 case IRAM0_SRAM_UNI_BLOCK_1:
218 *exec_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_1_F);
219 break;
220 case IRAM0_SRAM_UNI_BLOCK_2:
221 *exec_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_2_F);
222 break;
223 case IRAM0_SRAM_UNI_BLOCK_3:
224 *exec_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_1_REG, DPORT_PMS_PRO_IRAM0_SRAM_3_F);
225 break;
226 default:
227 return false;
228 }
229
230 return true;
231 }
232
memprot_ll_iram0_sram_get_uni_block_sgnf_bits(uint32_t block,uint32_t * write_bit,uint32_t * read_bit,uint32_t * exec_bit)233 static inline bool memprot_ll_iram0_sram_get_uni_block_sgnf_bits(uint32_t block, uint32_t *write_bit, uint32_t *read_bit, uint32_t *exec_bit)
234 {
235 switch (block) {
236 case IRAM0_SRAM_UNI_BLOCK_0:
237 *write_bit = DPORT_PMS_PRO_IRAM0_SRAM_0_W;
238 *read_bit = DPORT_PMS_PRO_IRAM0_SRAM_0_R;
239 *exec_bit = DPORT_PMS_PRO_IRAM0_SRAM_0_F;
240 break;
241 case IRAM0_SRAM_UNI_BLOCK_1:
242 *write_bit = DPORT_PMS_PRO_IRAM0_SRAM_1_W;
243 *read_bit = DPORT_PMS_PRO_IRAM0_SRAM_1_R;
244 *exec_bit = DPORT_PMS_PRO_IRAM0_SRAM_1_F;
245 break;
246 case IRAM0_SRAM_UNI_BLOCK_2:
247 *write_bit = DPORT_PMS_PRO_IRAM0_SRAM_2_W;
248 *read_bit = DPORT_PMS_PRO_IRAM0_SRAM_2_R;
249 *exec_bit = DPORT_PMS_PRO_IRAM0_SRAM_2_F;
250 break;
251 case IRAM0_SRAM_UNI_BLOCK_3:
252 *write_bit = DPORT_PMS_PRO_IRAM0_SRAM_3_W;
253 *read_bit = DPORT_PMS_PRO_IRAM0_SRAM_3_R;
254 *exec_bit = DPORT_PMS_PRO_IRAM0_SRAM_3_F;
255 break;
256 default:
257 return false;
258 }
259
260 return true;
261 }
262
memprot_ll_iram0_sram_get_perm_uni_reg(void)263 static inline uint32_t memprot_ll_iram0_sram_get_perm_uni_reg(void)
264 {
265 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_IRAM0_1_REG);
266 }
267
memprot_ll_iram0_sram_get_perm_split_reg(void)268 static inline uint32_t memprot_ll_iram0_sram_get_perm_split_reg(void)
269 {
270 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_IRAM0_2_REG);
271 }
272
memprot_ll_iram0_sram_set_prot(uint32_t * split_addr,bool lw,bool lr,bool lx,bool hw,bool hr,bool hx)273 static inline memprot_hal_err_t memprot_ll_iram0_sram_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
274 {
275 uint32_t addr = (uint32_t)split_addr;
276
277 //sanity check: split address required above unified mgmt region & 32bit aligned
278 if (addr > IRAM0_SRAM_SPL_BLOCK_HIGH) {
279 return MEMP_HAL_ERR_SPLIT_ADDR_INVALID;
280 }
281 if (addr % 0x4 != 0) {
282 return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED;
283 }
284
285 //find possible split.address in low region blocks
286 int uni_blocks_low = -1;
287 if (addr >= IRAM0_SRAM_UNI_BLOCK_0_LOW) {
288 uni_blocks_low++;
289 }
290 if (addr >= IRAM0_SRAM_UNI_BLOCK_1_LOW) {
291 uni_blocks_low++;
292 }
293 if (addr >= IRAM0_SRAM_UNI_BLOCK_2_LOW) {
294 uni_blocks_low++;
295 }
296 if (addr >= IRAM0_SRAM_UNI_BLOCK_3_LOW) {
297 uni_blocks_low++;
298 }
299
300 //unified mgmt settings per block (bits W/R/X: [11:9] bl3, [8:6] bl2, [5:3] bl1, [2:0] bl0)
301 uint32_t write_bit, read_bit, exec_bit;
302 uint32_t uni_block_perm = 0;
303
304 for (int x = 0; x < IRAM0_SRAM_TOTAL_UNI_BLOCKS; x++) {
305 if (!memprot_ll_iram0_sram_get_uni_block_sgnf_bits(x, &write_bit, &read_bit, &exec_bit)) {
306 return MEMP_HAL_ERR_UNI_BLOCK_INVALID;
307 }
308 if (x <= uni_blocks_low) {
309 if (lw) {
310 uni_block_perm |= write_bit;
311 }
312 if (lr) {
313 uni_block_perm |= read_bit;
314 }
315 if (lx) {
316 uni_block_perm |= exec_bit;
317 }
318 } else {
319 if (hw) {
320 uni_block_perm |= write_bit;
321 }
322 if (hr) {
323 uni_block_perm |= read_bit;
324 }
325 if (hx) {
326 uni_block_perm |= exec_bit;
327 }
328 }
329 }
330
331 //if splt.ddr not set yet, do required normalization to make the addr writeble into splt.mgmt cfg register
332 uint32_t reg_split_addr = 0;
333
334 if (addr >= IRAM0_SRAM_SPL_BLOCK_LOW) {
335 reg_split_addr = IRAM0_SRAM_ADDR_TO_CONF_REG(addr); //cfg reg - [16:0]
336 }
337
338 //prepare high & low permission mask (bits: [22:20] high range, [19:17] low range)
339 uint32_t permission_mask = 0;
340 if (lw) {
341 permission_mask |= DPORT_PMS_PRO_IRAM0_SRAM_4_L_W;
342 }
343 if (lr) {
344 permission_mask |= DPORT_PMS_PRO_IRAM0_SRAM_4_L_R;
345 }
346 if (lx) {
347 permission_mask |= DPORT_PMS_PRO_IRAM0_SRAM_4_L_F;
348 }
349 if (hw) {
350 permission_mask |= DPORT_PMS_PRO_IRAM0_SRAM_4_H_W;
351 }
352 if (hr) {
353 permission_mask |= DPORT_PMS_PRO_IRAM0_SRAM_4_H_R;
354 }
355 if (hx) {
356 permission_mask |= DPORT_PMS_PRO_IRAM0_SRAM_4_H_F;
357 }
358
359 //write IRAM SRAM uni & splt cfg. registers
360 DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_IRAM0_1_REG, uni_block_perm);
361 DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_IRAM0_2_REG, (uint32_t)(reg_split_addr | permission_mask));
362
363 return MEMP_HAL_OK;
364 }
365
memprot_ll_iram0_sram_get_split_sgnf_bits(bool * lw,bool * lr,bool * lx,bool * hw,bool * hr,bool * hx)366 static inline void memprot_ll_iram0_sram_get_split_sgnf_bits(bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx)
367 {
368 *lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_L_W);
369 *lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_L_R);
370 *lx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_L_F);
371 *hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_W);
372 *hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_R);
373 *hx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_F);
374 }
375
memprot_ll_iram0_sram_set_read_perm(bool lr,bool hr)376 static inline void memprot_ll_iram0_sram_set_read_perm(bool lr, bool hr)
377 {
378 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_L_R, lr ? 1 : 0);
379 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_R, hr ? 1 : 0);
380 }
381
memprot_ll_iram0_sram_set_write_perm(bool lw,bool hw)382 static inline void memprot_ll_iram0_sram_set_write_perm(bool lw, bool hw)
383 {
384 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_L_W, lw ? 1 : 0);
385 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_W, hw ? 1 : 0);
386 }
387
memprot_ll_iram0_sram_set_exec_perm(bool lx,bool hx)388 static inline void memprot_ll_iram0_sram_set_exec_perm(bool lx, bool hx)
389 {
390 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_L_F, lx ? 1 : 0);
391 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_2_REG, DPORT_PMS_PRO_IRAM0_SRAM_4_H_F, hx ? 1 : 0);
392 }
393
394
395 /**
396 * ========================================================================================
397 * === IRAM0 RTC FAST
398 * ========================================================================================
399 */
memprot_ll_iram0_rtcfast_get_fault_address(void)400 static inline intptr_t memprot_ll_iram0_rtcfast_get_fault_address(void)
401 {
402 uint32_t status_bits = memprot_ll_iram0_get_fault_reg();
403 return (intptr_t)((status_bits & IRAM0_INTR_ST_FAULTADDR_M) | IRAM0_RTCFAST_INTR_ST_FAULTADDR_HI);
404 }
405
memprot_ll_iram0_rtcfast_is_intr_mine(void)406 static inline bool memprot_ll_iram0_rtcfast_is_intr_mine(void)
407 {
408 if (memprot_ll_iram0_is_assoc_intr()) {
409 uint32_t faulting_address = (uint32_t)memprot_ll_iram0_rtcfast_get_fault_address();
410 return faulting_address >= IRAM0_RTCFAST_ADDRESS_LOW && faulting_address <= IRAM0_RTCFAST_ADDRESS_HIGH;
411 }
412 return false;
413 }
414
memprot_ll_iram0_rtcfast_get_perm_split_reg(void)415 static inline uint32_t memprot_ll_iram0_rtcfast_get_perm_split_reg(void)
416 {
417 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_IRAM0_3_REG);
418 }
419
memprot_ll_iram0_rtcfast_set_prot(uint32_t * split_addr,bool lw,bool lr,bool lx,bool hw,bool hr,bool hx)420 static inline memprot_hal_err_t memprot_ll_iram0_rtcfast_set_prot(uint32_t *split_addr, bool lw, bool lr, bool lx, bool hw, bool hr, bool hx)
421 {
422 uint32_t addr = (uint32_t)split_addr;
423
424 //32bit aligned
425 if (addr < IRAM0_RTCFAST_ADDRESS_LOW || addr > IRAM0_RTCFAST_ADDRESS_HIGH) {
426 return MEMP_HAL_ERR_SPLIT_ADDR_INVALID;
427 }
428 if (addr % 0x4 != 0) {
429 return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED;
430 }
431
432 //conf reg [10:0]
433 uint32_t reg_split_addr = IRAM0_RTCFAST_ADDR_TO_CONF_REG(addr);
434
435 //prepare high & low permission mask (bits: [16:14] high range, [13:11] low range)
436 uint32_t permission_mask = 0;
437 if (lw) {
438 permission_mask |= DPORT_PMS_PRO_IRAM0_RTCFAST_L_W;
439 }
440 if (lr) {
441 permission_mask |= DPORT_PMS_PRO_IRAM0_RTCFAST_L_R;
442 }
443 if (lx) {
444 permission_mask |= DPORT_PMS_PRO_IRAM0_RTCFAST_L_F;
445 }
446 if (hw) {
447 permission_mask |= DPORT_PMS_PRO_IRAM0_RTCFAST_H_W;
448 }
449 if (hr) {
450 permission_mask |= DPORT_PMS_PRO_IRAM0_RTCFAST_H_R;
451 }
452 if (hx) {
453 permission_mask |= DPORT_PMS_PRO_IRAM0_RTCFAST_H_F;
454 }
455
456 //write IRAM0 RTCFAST cfg register
457 DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_IRAM0_3_REG, reg_split_addr | permission_mask);
458
459 return MEMP_HAL_OK;
460 }
461
memprot_ll_iram0_rtcfast_get_split_sgnf_bits(bool * lw,bool * lr,bool * lx,bool * hw,bool * hr,bool * hx)462 static inline void memprot_ll_iram0_rtcfast_get_split_sgnf_bits(bool *lw, bool *lr, bool *lx, bool *hw, bool *hr, bool *hx)
463 {
464 *lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_L_W);
465 *lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_L_R);
466 *lx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_L_F);
467 *hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_H_W);
468 *hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_H_R);
469 *hx = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_H_F);
470 }
471
memprot_ll_iram0_rtcfast_set_read_perm(bool lr,bool hr)472 static inline void memprot_ll_iram0_rtcfast_set_read_perm(bool lr, bool hr)
473 {
474 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_L_R, lr ? 1 : 0);
475 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_H_R, hr ? 1 : 0);
476 }
477
memprot_ll_iram0_rtcfast_set_write_perm(bool lw,bool hw)478 static inline void memprot_ll_iram0_rtcfast_set_write_perm(bool lw, bool hw)
479 {
480 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_L_W, lw ? 1 : 0);
481 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_H_W, hw ? 1 : 0);
482 }
483
memprot_ll_iram0_rtcfast_set_exec_perm(bool lx,bool hx)484 static inline void memprot_ll_iram0_rtcfast_set_exec_perm(bool lx, bool hx)
485 {
486 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_L_F, lx ? 1 : 0);
487 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_IRAM0_3_REG, DPORT_PMS_PRO_IRAM0_RTCFAST_H_F, hx ? 1 : 0);
488 }
489
490
491 /**
492 * ========================================================================================
493 * === DRAM0 common
494 * ========================================================================================
495 */
memprot_ll_dram0_get_intr_source_num(void)496 static inline uint32_t memprot_ll_dram0_get_intr_source_num(void)
497 {
498 return ETS_PMS_PRO_DRAM0_ILG_INTR_SOURCE;
499 }
500
memprot_ll_dram0_intr_ena(bool enable)501 static inline void memprot_ll_dram0_intr_ena(bool enable)
502 {
503 if (enable) {
504 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_EN);
505 } else {
506 DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_EN);
507 }
508 }
509
memprot_ll_dram0_is_assoc_intr(void)510 static inline bool memprot_ll_dram0_is_assoc_intr(void)
511 {
512 return DPORT_GET_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_INTR) > 0;
513 }
514
memprot_ll_dram0_clear_intr(void)515 static inline void memprot_ll_dram0_clear_intr(void)
516 {
517 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_CLR);
518 DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_CLR);
519 }
520
memprot_ll_dram0_get_intr_ena_bit(void)521 static inline uint32_t memprot_ll_dram0_get_intr_ena_bit(void)
522 {
523 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_EN);
524 }
525
memprot_ll_dram0_get_intr_on_bit(void)526 static inline uint32_t memprot_ll_dram0_get_intr_on_bit(void)
527 {
528 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_INTR);
529 }
530
memprot_ll_dram0_get_intr_clr_bit(void)531 static inline uint32_t memprot_ll_dram0_get_intr_clr_bit(void)
532 {
533 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_3_REG, DPORT_PMS_PRO_DRAM0_ILG_CLR);
534 }
535
536 //lock resets automatically on CPU restart
memprot_ll_dram0_set_lock(void)537 static inline void memprot_ll_dram0_set_lock(void)
538 {
539 DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_DRAM0_0_REG, DPORT_PMS_PRO_DRAM0_LOCK);
540 }
541
memprot_ll_dram0_get_lock_reg(void)542 static inline uint32_t memprot_ll_dram0_get_lock_reg(void)
543 {
544 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DRAM0_0_REG);
545 }
546
memprot_ll_dram0_get_lock_bit(void)547 static inline uint32_t memprot_ll_dram0_get_lock_bit(void)
548 {
549 return DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_0_REG, DPORT_PMS_PRO_DRAM0_LOCK);
550 }
551
memprot_ll_dram0_get_conf_reg(void)552 static inline uint32_t memprot_ll_dram0_get_conf_reg(void)
553 {
554 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DRAM0_3_REG);
555 }
556
memprot_ll_dram0_get_fault_reg(void)557 static inline uint32_t memprot_ll_dram0_get_fault_reg(void)
558 {
559 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DRAM0_4_REG);
560 }
561
memprot_ll_dram0_get_fault_op_type(uint32_t * op_type,uint32_t * op_subtype)562 static inline void memprot_ll_dram0_get_fault_op_type(uint32_t *op_type, uint32_t *op_subtype)
563 {
564 uint32_t status_bits = memprot_ll_dram0_get_fault_reg();
565 *op_type = status_bits & DRAM0_INTR_ST_OP_RW_BIT;
566 *op_subtype = status_bits & DRAM0_INTR_ST_OP_ATOMIC_BIT;
567 }
568
569 /**
570 * ========================================================================================
571 * === DRAM0 SRAM
572 * ========================================================================================
573 */
memprot_ll_dram0_sram_get_fault_address(void)574 static inline intptr_t memprot_ll_dram0_sram_get_fault_address(void)
575 {
576 uint32_t status_bits = memprot_ll_dram0_get_fault_reg();
577 return (intptr_t)(((status_bits & DRAM0_INTR_ST_FAULTADDR_M) >> DRAM0_INTR_ST_FAULTADDR_S) | DRAM0_SRAM_INTR_ST_FAULTADDR_HI);
578 }
579
memprot_ll_dram0_sram_is_intr_mine(void)580 static inline bool memprot_ll_dram0_sram_is_intr_mine(void)
581 {
582 if (memprot_ll_dram0_is_assoc_intr()) {
583 uint32_t faulting_address = (uint32_t)memprot_ll_dram0_sram_get_fault_address();
584 return faulting_address >= DRAM0_SRAM_ADDRESS_LOW && faulting_address <= DRAM0_SRAM_ADDRESS_HIGH;
585 }
586 return false;
587 }
588
memprot_ll_dram0_sram_get_uni_block_sgnf_bits(uint32_t block,uint32_t * write_bit,uint32_t * read_bit)589 static inline bool memprot_ll_dram0_sram_get_uni_block_sgnf_bits(uint32_t block, uint32_t *write_bit, uint32_t *read_bit)
590 {
591 switch (block) {
592 case DRAM0_SRAM_UNI_BLOCK_0:
593 *write_bit = DPORT_PMS_PRO_DRAM0_SRAM_0_W;
594 *read_bit = DPORT_PMS_PRO_DRAM0_SRAM_0_R;
595 break;
596 case DRAM0_SRAM_UNI_BLOCK_1:
597 *write_bit = DPORT_PMS_PRO_DRAM0_SRAM_1_W;
598 *read_bit = DPORT_PMS_PRO_DRAM0_SRAM_1_R;
599 break;
600 case DRAM0_SRAM_UNI_BLOCK_2:
601 *write_bit = DPORT_PMS_PRO_DRAM0_SRAM_2_W;
602 *read_bit = DPORT_PMS_PRO_DRAM0_SRAM_2_R;
603 break;
604 case DRAM0_SRAM_UNI_BLOCK_3:
605 *write_bit = DPORT_PMS_PRO_DRAM0_SRAM_3_W;
606 *read_bit = DPORT_PMS_PRO_DRAM0_SRAM_3_R;
607 break;
608 default:
609 return false;
610 }
611
612 return true;
613 }
614
memprot_ll_dram0_sram_set_uni_block_perm(uint32_t block,bool write_perm,bool read_perm)615 static inline memprot_hal_err_t memprot_ll_dram0_sram_set_uni_block_perm(uint32_t block, bool write_perm, bool read_perm)
616 {
617 //get block-specific WR flags offset within the conf.register
618 uint32_t write_bit_offset, read_bit_offset;
619 if (!memprot_ll_dram0_sram_get_uni_block_sgnf_bits(block, &write_bit_offset, &read_bit_offset)) {
620 return MEMP_HAL_ERR_UNI_BLOCK_INVALID;
621 }
622
623 //set/reset required flags
624 if (write_perm) {
625 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_1_REG, write_bit_offset);
626 } else {
627 DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_1_REG, write_bit_offset);
628 }
629
630 if (read_perm) {
631 DPORT_SET_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_1_REG, read_bit_offset);
632 } else {
633 DPORT_CLEAR_PERI_REG_MASK(DPORT_PMS_PRO_DRAM0_1_REG, read_bit_offset);
634 }
635
636 return MEMP_HAL_OK;
637 }
638
memprot_ll_dram0_sram_get_uni_block_read_bit(uint32_t block,uint32_t * read_bit)639 static inline bool memprot_ll_dram0_sram_get_uni_block_read_bit(uint32_t block, uint32_t *read_bit)
640 {
641 switch (block) {
642 case DRAM0_SRAM_UNI_BLOCK_0:
643 *read_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_0_R);
644 break;
645 case DRAM0_SRAM_UNI_BLOCK_1:
646 *read_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_1_R);
647 break;
648 case DRAM0_SRAM_UNI_BLOCK_2:
649 *read_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_2_R);
650 break;
651 case DRAM0_SRAM_UNI_BLOCK_3:
652 *read_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_3_R);
653 break;
654 default:
655 return false;
656 }
657
658 return true;
659 }
660
memprot_ll_dram0_sram_get_uni_block_write_bit(uint32_t block,uint32_t * write_bit)661 static inline bool memprot_ll_dram0_sram_get_uni_block_write_bit(uint32_t block, uint32_t *write_bit)
662 {
663 switch (block) {
664 case DRAM0_SRAM_UNI_BLOCK_0:
665 *write_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_0_W);
666 break;
667 case DRAM0_SRAM_UNI_BLOCK_1:
668 *write_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_1_W);
669 break;
670 case DRAM0_SRAM_UNI_BLOCK_2:
671 *write_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_2_W);
672 break;
673 case DRAM0_SRAM_UNI_BLOCK_3:
674 *write_bit = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_3_W);
675 break;
676 default:
677 return false;
678 }
679
680 return true;
681 }
682
683 //DRAM0 has both unified blocks and split address configured in 1 register
memprot_ll_dram0_sram_get_perm_reg(void)684 static inline uint32_t memprot_ll_dram0_sram_get_perm_reg(void)
685 {
686 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DRAM0_1_REG);
687 }
688
memprot_ll_dram0_sram_set_prot(uint32_t * split_addr,bool lw,bool lr,bool hw,bool hr)689 static inline memprot_hal_err_t memprot_ll_dram0_sram_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr)
690 {
691 uint32_t addr = (uint32_t)split_addr;
692
693 //low boundary check provided by LD script. see comment in memprot_ll_iram0_sram_set_prot()
694 if (addr > DRAM0_SRAM_SPL_BLOCK_HIGH) {
695 return MEMP_HAL_ERR_SPLIT_ADDR_INVALID;
696 }
697 if (addr % 0x4 != 0) {
698 return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED;
699 }
700
701 //set low region
702 int uni_blocks_low = -1;
703 if (addr >= DRAM0_SRAM_UNI_BLOCK_0_LOW) {
704 uni_blocks_low++;
705 }
706 if (addr >= DRAM0_SRAM_UNI_BLOCK_1_LOW) {
707 uni_blocks_low++;
708 }
709 if (addr >= DRAM0_SRAM_UNI_BLOCK_2_LOW) {
710 uni_blocks_low++;
711 }
712 if (addr >= DRAM0_SRAM_UNI_BLOCK_3_LOW) {
713 uni_blocks_low++;
714 }
715
716 //set unified mgmt region
717 uint32_t write_bit, read_bit, uni_block_perm = 0;
718 for (int x = 0; x < DRAM0_SRAM_TOTAL_UNI_BLOCKS; x++) {
719 if (!memprot_ll_dram0_sram_get_uni_block_sgnf_bits(x, &write_bit, &read_bit)) {
720 return MEMP_HAL_ERR_UNI_BLOCK_INVALID;
721 }
722 if (x <= uni_blocks_low) {
723 if (lw) {
724 uni_block_perm |= write_bit;
725 }
726 if (lr) {
727 uni_block_perm |= read_bit;
728 }
729 } else {
730 if (hw) {
731 uni_block_perm |= write_bit;
732 }
733 if (hr) {
734 uni_block_perm |= read_bit;
735 }
736 }
737 }
738
739 //conf reg [24:8]
740 uint32_t reg_split_addr = DRAM0_SRAM_ADDR_TO_CONF_REG(addr);
741
742 //prepare high & low permission mask
743 uint32_t permission_mask = 0;
744 if (lw) {
745 permission_mask |= DPORT_PMS_PRO_DRAM0_SRAM_4_L_W;
746 }
747 if (lr) {
748 permission_mask |= DPORT_PMS_PRO_DRAM0_SRAM_4_L_R;
749 }
750 if (hw) {
751 permission_mask |= DPORT_PMS_PRO_DRAM0_SRAM_4_H_W;
752 }
753 if (hr) {
754 permission_mask |= DPORT_PMS_PRO_DRAM0_SRAM_4_H_R;
755 }
756
757 //write DRAM0 SRAM cfg register
758 DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_DRAM0_1_REG, reg_split_addr | permission_mask | uni_block_perm);
759
760 return MEMP_HAL_OK;
761 }
762
memprot_ll_dram0_sram_get_split_sgnf_bits(bool * lw,bool * lr,bool * hw,bool * hr)763 static inline void memprot_ll_dram0_sram_get_split_sgnf_bits(bool *lw, bool *lr, bool *hw, bool *hr)
764 {
765 *lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_L_W);
766 *lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_L_R);
767 *hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_H_W);
768 *hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_H_R);
769 }
770
memprot_ll_dram0_sram_set_read_perm(bool lr,bool hr)771 static inline void memprot_ll_dram0_sram_set_read_perm(bool lr, bool hr)
772 {
773 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_L_R, lr ? 1 : 0);
774 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_H_R, hr ? 1 : 0);
775 }
776
memprot_ll_dram0_sram_set_write_perm(bool lw,bool hw)777 static inline void memprot_ll_dram0_sram_set_write_perm(bool lw, bool hw)
778 {
779 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_L_W, lw ? 1 : 0);
780 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DRAM0_1_REG, DPORT_PMS_PRO_DRAM0_SRAM_4_H_W, hw ? 1 : 0);
781 }
782
783
784 /**
785 * ========================================================================================
786 * === DRAM0 RTC FAST
787 * ========================================================================================
788 */
memprot_ll_dram0_rtcfast_get_fault_address(void)789 static inline intptr_t memprot_ll_dram0_rtcfast_get_fault_address(void)
790 {
791 uint32_t status_bits = memprot_ll_dram0_get_fault_reg();
792 return (intptr_t)(((status_bits & DRAM0_INTR_ST_FAULTADDR_M) >> DRAM0_INTR_ST_FAULTADDR_S) | DRAM0_RTCFAST_INTR_ST_FAULTADDR_HI);
793 }
794
memprot_ll_dram0_rtcfast_is_intr_mine(void)795 static inline bool memprot_ll_dram0_rtcfast_is_intr_mine(void)
796 {
797 if (memprot_ll_dram0_is_assoc_intr()) {
798 uint32_t faulting_address = (uint32_t)memprot_ll_dram0_rtcfast_get_fault_address();
799 return faulting_address >= DRAM0_RTCFAST_ADDRESS_LOW && faulting_address <= DRAM0_RTCFAST_ADDRESS_HIGH;
800 }
801 return false;
802 }
803
memprot_ll_dram0_rtcfast_set_prot(uint32_t * split_addr,bool lw,bool lr,bool hw,bool hr)804 static inline memprot_hal_err_t memprot_ll_dram0_rtcfast_set_prot(uint32_t *split_addr, bool lw, bool lr, bool hw, bool hr)
805 {
806 uint32_t addr = (uint32_t)split_addr;
807
808 //addr: 32bit aligned, inside corresponding range
809 if (addr < DRAM0_RTCFAST_ADDRESS_LOW || addr > DRAM0_RTCFAST_ADDRESS_HIGH) {
810 return MEMP_HAL_ERR_SPLIT_ADDR_INVALID;
811 }
812 if (addr % 0x4 != 0) {
813 return MEMP_HAL_ERR_SPLIT_ADDR_UNALIGNED;
814 }
815
816 //conf reg [10:0]
817 uint32_t reg_split_addr = DRAM0_RTCFAST_ADDR_TO_CONF_REG(addr);
818
819 //prepare high & low permission mask
820 uint32_t permission_mask = 0;
821 if (lw) {
822 permission_mask |= DPORT_PMS_PRO_DRAM0_RTCFAST_L_W;
823 }
824 if (lr) {
825 permission_mask |= DPORT_PMS_PRO_DRAM0_RTCFAST_L_R;
826 }
827 if (hw) {
828 permission_mask |= DPORT_PMS_PRO_DRAM0_RTCFAST_H_W;
829 }
830 if (hr) {
831 permission_mask |= DPORT_PMS_PRO_DRAM0_RTCFAST_H_R;
832 }
833
834 //write DRAM0 RTC FAST cfg register
835 DPORT_WRITE_PERI_REG(DPORT_PMS_PRO_DRAM0_2_REG, reg_split_addr | permission_mask);
836
837 return MEMP_HAL_OK;
838 }
839
memprot_ll_dram0_rtcfast_get_split_sgnf_bits(bool * lw,bool * lr,bool * hw,bool * hr)840 static inline void memprot_ll_dram0_rtcfast_get_split_sgnf_bits(bool *lw, bool *lr, bool *hw, bool *hr)
841 {
842 *lw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_2_REG, DPORT_PMS_PRO_DRAM0_RTCFAST_L_W);
843 *lr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_2_REG, DPORT_PMS_PRO_DRAM0_RTCFAST_L_R);
844 *hw = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_2_REG, DPORT_PMS_PRO_DRAM0_RTCFAST_H_W);
845 *hr = DPORT_REG_GET_FIELD(DPORT_PMS_PRO_DRAM0_2_REG, DPORT_PMS_PRO_DRAM0_RTCFAST_H_R);
846 }
847
memprot_ll_dram0_rtcfast_get_perm_split_reg(void)848 static inline uint32_t memprot_ll_dram0_rtcfast_get_perm_split_reg(void)
849 {
850 return DPORT_READ_PERI_REG(DPORT_PMS_PRO_DRAM0_2_REG);
851 }
852
memprot_ll_dram0_rtcfast_set_read_perm(bool lr,bool hr)853 static inline void memprot_ll_dram0_rtcfast_set_read_perm(bool lr, bool hr)
854 {
855 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DRAM0_2_REG, DPORT_PMS_PRO_DRAM0_RTCFAST_L_R, lr ? 1 : 0);
856 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DRAM0_2_REG, DPORT_PMS_PRO_DRAM0_RTCFAST_H_R, hr ? 1 : 0);
857 }
858
memprot_ll_dram0_rtcfast_set_write_perm(bool lw,bool hw)859 static inline void memprot_ll_dram0_rtcfast_set_write_perm(bool lw, bool hw)
860 {
861 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DRAM0_2_REG, DPORT_PMS_PRO_DRAM0_RTCFAST_L_W, lw ? 1 : 0);
862 DPORT_REG_SET_FIELD(DPORT_PMS_PRO_DRAM0_2_REG, DPORT_PMS_PRO_DRAM0_RTCFAST_H_W, hw ? 1 : 0);
863 }
864
865 #ifdef __cplusplus
866 }
867 #endif
868
