1 /*
2 * Copyright 2017-2023 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_flexram.h"
10
11 /*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14
15 /* Component ID definition, used by tools. */
16 #ifndef FSL_COMPONENT_ID
17 #define FSL_COMPONENT_ID "platform.drivers.flexram"
18 #endif
19
20 /*******************************************************************************
21 * Prototypes
22 ******************************************************************************/
23 /*!
24 * @brief Gets the instance from the base address to be used to gate or ungate the module clock
25 *
26 * @param base FLEXRAM base address
27 *
28 * @return The FLEXRAM instance
29 */
30 static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base);
31
32 /*******************************************************************************
33 * Variables
34 ******************************************************************************/
35 /*! @brief Pointers to FLEXRAM bases for each instance. */
36 static FLEXRAM_Type *const s_flexramBases[] = FLEXRAM_BASE_PTRS;
37
38 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
39 /*! @brief Pointers to FLEXRAM clocks for each instance. */
40 static const clock_ip_name_t s_flexramClocks[] = FLEXRAM_CLOCKS;
41 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
42
43 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
44 /*! Look-up table to calculate single-bit error bit position for ITCM. */
45 static const uint8_t ItcmLookUpTable[64] = {
46 0xC1, 0x43, 0x9E, 0x83, 0x15, 0x4C, 0x4A, 0x8C, 0x31, 0x1C, 0xA2, 0xE0, 0x51, 0x2C, 0xC2, 0xD0,
47 0x19, 0x1A, 0x26, 0xEA, 0x29, 0x94, 0x16, 0x64, 0x37, 0xA4, 0x0D, 0xC4, 0x75, 0x38, 0x4F, 0x58,
48 0x46, 0x91, 0x86, 0x61, 0x49, 0x98, 0x89, 0x68, 0x32, 0x34, 0x07, 0xC8, 0x92, 0xA8, 0xA7, 0x54,
49 0xA1, 0xD9, 0x25, 0xF8, 0x0E, 0x0B, 0x8A, 0x2A, 0x52, 0x45, 0x13, 0x85, 0x62, 0x70, 0x23, 0xB0};
50 /*! Look-up table to calculate single-bit error bit position for DTCM. */
51 static const uint8_t DtcmLookUpTable[32] = {0x61, 0x51, 0x19, 0x45, 0x43, 0x31, 0x29, 0x13, 0x62, 0x52, 0x4A,
52 0x46, 0x32, 0x2A, 0x23, 0x1A, 0x2C, 0x64, 0x26, 0x25, 0x34, 0x16,
53 0x15, 0x54, 0x0B, 0x58, 0x1C, 0x4C, 0x38, 0x0E, 0x0D, 0x49};
54 #endif /* FLEXRAM_ECC_ERROR_DETAILED_INFO */
55
56 /*******************************************************************************
57 * Code
58 ******************************************************************************/
FLEXRAM_GetInstance(FLEXRAM_Type * base)59 static uint32_t FLEXRAM_GetInstance(FLEXRAM_Type *base)
60 {
61 uint32_t instance;
62
63 /* Find the instance index from base address mappings. */
64 for (instance = 0; instance < ARRAY_SIZE(s_flexramBases); instance++)
65 {
66 if (s_flexramBases[instance] == base)
67 {
68 break;
69 }
70 }
71
72 assert(instance < ARRAY_SIZE(s_flexramBases));
73
74 return instance;
75 }
76
77 /*!
78 * brief FLEXRAM module initialization function.
79 *
80 * param base FLEXRAM base address.
81 */
FLEXRAM_Init(FLEXRAM_Type * base)82 void FLEXRAM_Init(FLEXRAM_Type *base)
83 {
84 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
85 /* Ungate ENET clock. */
86 CLOCK_EnableClock(s_flexramClocks[FLEXRAM_GetInstance(base)]);
87 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
88
89 /* enable all the interrupt status */
90 base->INT_STAT_EN |= (uint32_t)kFLEXRAM_InterruptStatusAll;
91 /* clear all the interrupt status */
92 base->INT_STATUS |= (uint32_t)kFLEXRAM_InterruptStatusAll;
93 /* disable all the interrpt */
94 base->INT_SIG_EN = 0U;
95 }
96
97 /*!
98 * brief Deinitializes the FLEXRAM.
99 *
100 */
FLEXRAM_Deinit(FLEXRAM_Type * base)101 void FLEXRAM_Deinit(FLEXRAM_Type *base)
102 {
103 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
104 /* Ungate ENET clock. */
105 CLOCK_DisableClock(s_flexramClocks[FLEXRAM_GetInstance(base)]);
106 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
107 }
108
109 #if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC) && FSL_FEATURE_FLEXRAM_HAS_ECC)
FLEXRAM_EnableECC(FLEXRAM_Type * base,bool OcramECCEnable,bool TcmECCEnable)110 void FLEXRAM_EnableECC(FLEXRAM_Type *base, bool OcramECCEnable, bool TcmECCEnable)
111 {
112 if (true == OcramECCEnable)
113 {
114 base->FLEXRAM_CTRL |= FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK;
115 }
116 else
117 {
118 base->FLEXRAM_CTRL &= ~FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK;
119 }
120
121 if (true == TcmECCEnable)
122 {
123 base->FLEXRAM_CTRL |= FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK;
124 }
125 else
126 {
127 base->FLEXRAM_CTRL &= ~FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK;
128 }
129 }
130
131 #if (defined(FSL_FEATURE_FLEXRAM_HAS_ECC_ERROR_INJECTION) && (FSL_FEATURE_FLEXRAM_HAS_ECC_ERROR_INJECTION))
FLEXRAM_ErrorInjection(FLEXRAM_Type * base,flexram_memory_type_t memory,flexram_ecc_error_type_t * error)132 void FLEXRAM_ErrorInjection(FLEXRAM_Type *base, flexram_memory_type_t memory, flexram_ecc_error_type_t *error)
133 {
134 assert(error != NULL);
135
136 switch (memory)
137 {
138 case kFLEXRAM_OCRAM:
139 base->OCRAM_ECC_ERROR_INJEC =
140 FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_ERR1BIT(error->SingleBitPos) |
141 FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_ERR2BIT(error->SecondBitPos) |
142 FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FR11BI(error->Fource1BitDataInversion) |
143 FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FR1NCI(error->FourceOneNCDataInversion) |
144 FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FRC1BI(error->FourceConti1BitDataInversion) |
145 FLEXRAM_OCRAM_ECC_ERROR_INJEC_OCRAM_FRCNCI(error->FourceContiNCDataInversion);
146 break;
147 case kFLEXRAM_ITCM:
148 base->ITCM_ECC_ERROR_INJEC = FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_ERR1BIT(error->SingleBitPos) |
149 FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_ERR2BIT(error->SecondBitPos) |
150 FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FR11BI(error->Fource1BitDataInversion) |
151 FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FR1NCI(error->FourceOneNCDataInversion) |
152 FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FRC1BI(error->FourceConti1BitDataInversion) |
153 FLEXRAM_ITCM_ECC_ERROR_INJEC_ITCM_FRCNCI(error->FourceContiNCDataInversion);
154 break;
155 case kFLEXRAM_D0TCM:
156 base->D0TCM_ECC_ERROR_INJEC =
157 FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_ERR1BIT(error->SingleBitPos) |
158 FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_ERR2BIT(error->SecondBitPos) |
159 FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FR11BI(error->Fource1BitDataInversion) |
160 FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FR1NCI(error->FourceOneNCDataInversion) |
161 FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FRC1BI(error->FourceConti1BitDataInversion) |
162 FLEXRAM_D0TCM_ECC_ERROR_INJEC_D0TCM_FRCNCI(error->FourceContiNCDataInversion);
163 break;
164 case kFLEXRAM_D1TCM:
165 base->D1TCM_ECC_ERROR_INJEC =
166 FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_ERR1BIT(error->SingleBitPos) |
167 FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_ERR2BIT(error->SecondBitPos) |
168 FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FR11BI(error->Fource1BitDataInversion) |
169 FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FR1NCI(error->FourceOneNCDataInversion) |
170 FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FRC1BI(error->FourceConti1BitDataInversion) |
171 FLEXRAM_D1TCM_ECC_ERROR_INJEC_D1TCM_FRCNCI(error->FourceContiNCDataInversion);
172 break;
173 default:
174 assert(NULL);
175 break;
176 }
177
178 __DSB();
179 }
180 #endif /* FSL_FEATURE_FLEXRAM_HAS_ECC_ERROR_INJECTION */
181
FLEXRAM_GetOcramSingleErroInfo(FLEXRAM_Type * base,flexram_ocram_ecc_single_error_info_t * info)182 void FLEXRAM_GetOcramSingleErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_single_error_info_t *info)
183 {
184 assert(NULL != info);
185
186 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
187 info->OcramSingleErrorECCCipher =
188 (uint8_t)((base->OCRAM_ECC_SINGLE_ERROR_INFO & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK) >>
189 FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT);
190 info->OcramSingleErrorECCSyndrome =
191 (uint8_t)((base->OCRAM_ECC_SINGLE_ERROR_INFO & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK) >>
192 FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT);
193 #else
194 info->OcramSingleErrorInfo = base->OCRAM_ECC_SINGLE_ERROR_INFO;
195 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
196
197 info->OcramSingleErrorAddr = base->OCRAM_ECC_SINGLE_ERROR_ADDR;
198 info->OcramSingleErrorDataLSB = base->OCRAM_ECC_SINGLE_ERROR_DATA_LSB;
199 info->OcramSingleErrorDataMSB = base->OCRAM_ECC_SINGLE_ERROR_DATA_MSB;
200 }
201
FLEXRAM_GetOcramMultiErroInfo(FLEXRAM_Type * base,flexram_ocram_ecc_multi_error_info_t * info)202 void FLEXRAM_GetOcramMultiErroInfo(FLEXRAM_Type *base, flexram_ocram_ecc_multi_error_info_t *info)
203 {
204 assert(NULL != info);
205
206 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
207 info->OcramMultiErrorECCCipher =
208 (uint8_t)((base->OCRAM_ECC_MULTI_ERROR_INFO & FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK) >>
209 FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT);
210 #else
211 info->OcramMultiErrorInfo = base->OCRAM_ECC_MULTI_ERROR_INFO;
212 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
213 info->OcramMultiErrorAddr = base->OCRAM_ECC_MULTI_ERROR_ADDR;
214 info->OcramMultiErrorDataLSB = base->OCRAM_ECC_MULTI_ERROR_DATA_LSB;
215 info->OcramMultiErrorDataMSB = base->OCRAM_ECC_MULTI_ERROR_DATA_MSB;
216 }
217
FLEXRAM_GetItcmSingleErroInfo(FLEXRAM_Type * base,flexram_itcm_ecc_single_error_info_t * info)218 void FLEXRAM_GetItcmSingleErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_single_error_info_t *info)
219 {
220 assert(NULL != info);
221
222 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
223 /* ECC error corresponding syndrome, which can be used to locate the Error bit using a look-up table. */
224 uint8_t singleErrorECCSyndrome = 0x00U;
225
226 info->ItcmSingleErrorTCMWriteRead =
227 (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK) >>
228 FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT);
229 info->ItcmSingleErrorTCMAccessSize =
230 (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK) >>
231 FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT);
232 info->ItcmSingleErrorTCMMaster =
233 (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK) >>
234 FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT);
235 info->ItcmSingleErrorTCMPrivilege =
236 (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK) >>
237 FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT);
238 singleErrorECCSyndrome =
239 (uint8_t)((base->ITCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK) >>
240 FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT);
241
242 for (uint8_t i = 0x00U; i < sizeof(ItcmLookUpTable) / sizeof(ItcmLookUpTable[0]); i++)
243 {
244 if (singleErrorECCSyndrome == ItcmLookUpTable[i])
245 {
246 info->ItcmSingleErrorBitPostion = i;
247 break;
248 }
249 }
250 #else
251 info->ItcmSingleErrorInfo = base->ITCM_ECC_SINGLE_ERROR_INFO;
252 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
253
254 info->ItcmSingleErrorAddr = base->ITCM_ECC_SINGLE_ERROR_ADDR;
255 info->ItcmSingleErrorDataLSB = base->ITCM_ECC_SINGLE_ERROR_DATA_LSB;
256 info->ItcmSingleErrorDataMSB = base->ITCM_ECC_SINGLE_ERROR_DATA_MSB;
257 }
258
FLEXRAM_GetItcmMultiErroInfo(FLEXRAM_Type * base,flexram_itcm_ecc_multi_error_info_t * info)259 void FLEXRAM_GetItcmMultiErroInfo(FLEXRAM_Type *base, flexram_itcm_ecc_multi_error_info_t *info)
260 {
261 assert(NULL != info);
262
263 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
264 info->ItcmMultiErrorTCMWriteRead =
265 (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFW_MASK) >>
266 FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFW_SHIFT);
267 info->ItcmMultiErrorTCMAccessSize =
268 (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK) >>
269 FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT);
270 info->ItcmMultiErrorTCMMaster =
271 (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFMST_MASK) >>
272 FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT);
273 info->ItcmMultiErrorTCMPrivilege =
274 (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFPRT_MASK) >>
275 FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT);
276 info->ItcmMultiErrorECCSyndrome =
277 (uint8_t)((base->ITCM_ECC_MULTI_ERROR_INFO & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSYN_MASK) >>
278 FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT);
279 #else
280 info->ItcmMultiErrorInfo = base->ITCM_ECC_MULTI_ERROR_INFO;
281 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
282
283 info->ItcmMultiErrorAddr = base->ITCM_ECC_MULTI_ERROR_ADDR;
284 info->ItcmMultiErrorDataLSB = base->ITCM_ECC_MULTI_ERROR_DATA_LSB;
285 info->ItcmMultiErrorDataMSB = base->ITCM_ECC_MULTI_ERROR_DATA_MSB;
286 }
287
FLEXRAM_GetDtcmSingleErroInfo(FLEXRAM_Type * base,flexram_dtcm_ecc_single_error_info_t * info,uint8_t bank)288 void FLEXRAM_GetDtcmSingleErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_single_error_info_t *info, uint8_t bank)
289 {
290 assert(NULL != info);
291 assert((0x00U == bank) || (0x01U == bank));
292
293 if (0x00U == bank)
294 {
295 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
296 /* ECC error corresponding syndrome, which can be used to locate the Error bit using a look-up table. */
297 uint8_t singleErrorECCSyndrome = 0x00U;
298
299 info->DtcmSingleErrorTCMWriteRead =
300 (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK) >>
301 FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT);
302 info->DtcmSingleErrorTCMAccessSize =
303 (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK) >>
304 FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT);
305 info->DtcmSingleErrorTCMMaster =
306 (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK) >>
307 FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT);
308 info->DtcmSingleErrorTCMPrivilege =
309 (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK) >>
310 FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT);
311 singleErrorECCSyndrome =
312 (uint8_t)((base->D0TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK) >>
313 FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT);
314
315 for (uint8_t i = 0x00U; i < sizeof(ItcmLookUpTable) / sizeof(ItcmLookUpTable[0]); i++)
316 {
317 if (singleErrorECCSyndrome == ItcmLookUpTable[i])
318 {
319 info->DtcmSingleErrorBitPostion = i;
320 break;
321 }
322 }
323 #else
324 info->DtcmSingleErrorInfo = base->D0TCM_ECC_SINGLE_ERROR_INFO;
325 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
326
327 info->DtcmSingleErrorAddr = base->D0TCM_ECC_SINGLE_ERROR_ADDR;
328 info->DtcmSingleErrorData = base->D0TCM_ECC_SINGLE_ERROR_DATA;
329 }
330 else
331 {
332 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
333 /* ECC error corresponding syndrome, which can be used to locate the Error bit using a look-up table. */
334 uint8_t singleErrorECCSyndrome = 0x00U;
335
336 info->DtcmSingleErrorTCMWriteRead =
337 (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK) >>
338 FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT);
339 info->DtcmSingleErrorTCMAccessSize =
340 (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK) >>
341 FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT);
342 info->DtcmSingleErrorTCMMaster =
343 (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK) >>
344 FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT);
345 info->DtcmSingleErrorTCMPrivilege =
346 (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK) >>
347 FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT);
348 singleErrorECCSyndrome =
349 (uint8_t)((base->D1TCM_ECC_SINGLE_ERROR_INFO & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK) >>
350 FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT);
351
352 for (uint8_t i = 0x00U; i < sizeof(DtcmLookUpTable) / sizeof(DtcmLookUpTable[0]); i++)
353 {
354 if (singleErrorECCSyndrome == DtcmLookUpTable[i])
355 {
356 info->DtcmSingleErrorBitPostion = i;
357 break;
358 }
359 }
360 #else
361 info->DtcmSingleErrorInfo = base->D1TCM_ECC_SINGLE_ERROR_INFO;
362 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
363
364 info->DtcmSingleErrorAddr = base->D1TCM_ECC_SINGLE_ERROR_ADDR;
365 info->DtcmSingleErrorData = base->D1TCM_ECC_SINGLE_ERROR_DATA;
366 }
367 }
368
FLEXRAM_GetDtcmMultiErroInfo(FLEXRAM_Type * base,flexram_dtcm_ecc_multi_error_info_t * info,uint8_t bank)369 void FLEXRAM_GetDtcmMultiErroInfo(FLEXRAM_Type *base, flexram_dtcm_ecc_multi_error_info_t *info, uint8_t bank)
370 {
371 assert(NULL != info);
372 assert((0x00U == bank) || (0x01U == bank));
373
374 if (0x00U == bank)
375 {
376 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
377 info->DtcmMultiErrorTCMWriteRead =
378 (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFW_MASK) >>
379 FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT);
380 info->DtcmMultiErrorTCMAccessSize =
381 (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK) >>
382 FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT);
383 info->DtcmMultiErrorTCMMaster =
384 (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFMST_MASK) >>
385 FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT);
386 info->DtcmMultiErrorTCMPrivilege =
387 (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK) >>
388 FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT);
389 info->DtcmMultiErrorECCSyndrome =
390 (uint8_t)((base->D0TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK) >>
391 FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT);
392 #else
393 info->DtcmMultiErrorInfo = base->D0TCM_ECC_MULTI_ERROR_INFO;
394 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
395
396 info->DtcmMultiErrorAddr = base->D0TCM_ECC_MULTI_ERROR_ADDR;
397 info->DtcmMultiErrorData = base->D0TCM_ECC_MULTI_ERROR_DATA;
398 }
399 else
400 {
401 #if defined(FLEXRAM_ECC_ERROR_DETAILED_INFO) && FLEXRAM_ECC_ERROR_DETAILED_INFO
402 info->DtcmMultiErrorTCMWriteRead =
403 (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFW_MASK) >>
404 FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT);
405 info->DtcmMultiErrorTCMAccessSize =
406 (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK) >>
407 FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT);
408 info->DtcmMultiErrorTCMMaster =
409 (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFMST_MASK) >>
410 FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT);
411 info->DtcmMultiErrorTCMPrivilege =
412 (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFPRT_MASK) >>
413 FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT);
414 info->DtcmMultiErrorECCSyndrome =
415 (uint8_t)((base->D1TCM_ECC_MULTI_ERROR_INFO & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_ITCM_ECCS_EFSYN_MASK) >>
416 FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT);
417 #else
418 info->DtcmMultiErrorInfo = base->D1TCM_ECC_MULTI_ERROR_INFO;
419 #endif /*FLEXRAM_ECC_ERROR_DETAILED_INFO*/
420
421 info->DtcmMultiErrorAddr = base->D1TCM_ECC_MULTI_ERROR_ADDR;
422 info->DtcmMultiErrorData = base->D1TCM_ECC_MULTI_ERROR_DATA;
423 }
424 }
425 #endif /* FSL_FEATURE_FLEXRAM_HAS_ECC */
426
