1 /* 2 * Licensed to the Apache Software Foundation (ASF) under one 3 * or more contributor license agreements. See the NOTICE file 4 * distributed with this work for additional information 5 * regarding copyright ownership. The ASF licenses this file 6 * to you under the Apache License, Version 2.0 (the 7 * "License"); you may not use this file except in compliance 8 * with the License. You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, 13 * software distributed under the License is distributed on an 14 * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY 15 * KIND, either express or implied. See the License for the 16 * specific language governing permissions and limitations 17 * under the License. 18 */ 19 20 #ifndef __IPC_CMAC_SHM_H_ 21 #define __IPC_CMAC_SHM_H_ 22 23 #include <stdint.h> 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 #define MEMCTRL_BSR_SET_REG (*(volatile uint32_t *)0x50050074) 30 #define MEMCTRL_BSR_STAT_REG (*(volatile uint32_t *)0x5005007c) 31 #define MEMCTRL_BSR_RESET_REG (*(volatile uint32_t *)0x50050078) 32 33 #define CMAC_SHM_LOCK_VAL 0x40000000 34 35 #define CMAC_SHM_CB_MAGIC 0xc3ac 36 37 #define CMAC_SHM_CB_PENDING_OP_LP_CLK 0x0001 38 #define CMAC_SHM_CB_PENDING_OP_RF_CAL 0x0002 39 40 #define CMAC_SHM_VECT_MAGIC 0xc3ac0001 41 #define CMAC_SHM_VECT_CRASHINFO 0x00000001 42 #define CMAC_SHM_VECT_DEBUGDATA 0x00000002 43 44 struct cmac_shm_config { 45 uint16_t mbox_s2c_size; 46 uint16_t mbox_c2s_size; 47 uint8_t trim_rfcu_size; 48 uint8_t trim_rfcu_mode1_size; 49 uint8_t trim_rfcu_mode2_size; 50 uint8_t trim_synth_size; 51 uint16_t rand_size; 52 }; 53 54 struct cmac_shm_ctrl { 55 volatile uint16_t magic; 56 uint16_t pending_ops; 57 uint16_t lp_clock_freq; 58 uint16_t xtal32m_settle_us; 59 }; 60 61 struct cmac_shm_mbox { 62 uint16_t rd_off; 63 uint16_t wr_off; 64 uint8_t data[]; 65 }; 66 67 struct cmac_shm_trim { 68 uint8_t rfcu_len; 69 uint8_t rfcu_mode1_len; 70 uint8_t rfcu_mode2_len; 71 uint8_t synth_len; 72 uint32_t data[]; 73 }; 74 75 struct cmac_shm_rand { 76 uint16_t cmr_active; 77 uint16_t cmr_in; 78 uint16_t cmr_out; 79 uint32_t cmr_buf[]; 80 }; 81 82 struct cmac_shm_dcdc { 83 uint8_t enabled; 84 uint32_t v18; 85 uint32_t v18p; 86 uint32_t vdd; 87 uint32_t v14; 88 uint32_t ctrl1; 89 }; 90 91 struct cmac_shm_crashinfo { 92 uint32_t lr; 93 uint32_t pc; 94 uint32_t assert; 95 const char *assert_file; 96 uint32_t assert_line; 97 98 uint32_t CM_STAT_REG; 99 uint32_t CM_LL_TIMER1_36_10_REG; 100 uint32_t CM_LL_TIMER1_9_0_REG; 101 uint32_t CM_ERROR_REG; 102 uint32_t CM_EXC_STAT_REG; 103 }; 104 105 struct cmac_shm_debugdata { 106 int8_t tx_power_ovr_enable; 107 int8_t tx_power_ovr; 108 int8_t last_rx_rssi; 109 110 uint32_t cal_res_1; 111 uint32_t cal_res_2; 112 uint32_t trim_val1_tx_1; 113 uint32_t trim_val1_tx_2; 114 uint32_t trim_val2_tx; 115 uint32_t trim_val2_rx; 116 }; 117 118 struct cmac_shm { 119 struct cmac_shm_config *config; 120 struct cmac_shm_ctrl *ctrl; 121 struct cmac_shm_mbox *mbox_s2c; 122 struct cmac_shm_mbox *mbox_c2s; 123 struct cmac_shm_trim *trim; 124 struct cmac_shm_rand *rand; 125 struct cmac_shm_dcdc *dcdc; 126 struct cmac_shm_crashinfo *crashinfo; 127 struct cmac_shm_debugdata *debugdata; 128 }; 129 130 extern struct cmac_shm g_cmac_shm; 131 extern void cmac_read_req(void); 132 133 void cmac_cmac2sys_isr(void); 134 135 void cmac_configure_shm(void); 136 137 void cmac_configure_pdc(void); 138 void cmac_load_image(void); 139 void cmac_enable(void); 140 void cmac_disable(void); 141 142 void cmac_request_lp_clock_freq_set(uint32_t freq); 143 144 void cmac_signal(void); 145 146 static inline void cmac_shm_lock(void)147cmac_shm_lock(void) 148 { 149 while ((MEMCTRL->BUSY_STAT_REG & MEMCTRL_BUSY_RESET_REG_BUSY_SPARE_Msk) != 0x40000000) { 150 MEMCTRL->BUSY_SET_REG = 0x40000000; 151 } 152 } 153 154 static inline void cmac_shm_unlock(void)155cmac_shm_unlock(void) 156 { 157 MEMCTRL->BUSY_RESET_REG = 0x40000000; 158 } 159 160 #ifdef __cplusplus 161 } 162 #endif 163 164 #endif /* __IPC_CMAC_SHM_H_ */ 165
