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/trusted-firmware-m-latest/platform/ext/target/arm/drivers/gpio/pl061/
Dgpio_pl061_drv.h50 void pl061_set_gpio(pl061_regblk_t * pdev, uint8_t mask, uint8_t pins) in pl061_set_gpio()
63 void pl061_set_high(pl061_regblk_t * pdev, uint8_t mask) in pl061_set_high()
76 void gpio_set_low(pl061_regblk_t * pdev, uint8_t mask) in gpio_set_low()
90 uint8_t pl061_get_gpio(pl061_regblk_t * pdev, uint8_t mask) in pl061_get_gpio()
103 void pl061_set_input(pl061_regblk_t * pdev, uint8_t mask) in pl061_set_input()
115 void pl061_set_output(pl061_regblk_t * pdev, uint8_t mask) in pl061_set_output()
/trusted-firmware-m-latest/platform/ext/target/arm/rse/common/native_drivers/
Dppc_rse_drv.c117 ppc_rse_config_privilege(struct ppc_rse_dev_t* dev, uint32_t mask, in ppc_rse_config_privilege()
153 uint32_t mask) in ppc_rse_is_periph_priv_only()
180 ppc_rse_config_security(struct ppc_rse_dev_t* dev, uint32_t mask, in ppc_rse_config_security()
197 uint32_t mask) in ppc_rse_is_periph_secure()
Dmhu_v2_x.c275 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask) in mhu_v2_x_channel_mask_set()
292 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask) in mhu_v2_x_channel_mask_clear()
499 const struct mhu_v2_x_dev_t *dev, uint32_t mask) in mhu_v2_x_interrupt_enable()
529 const struct mhu_v2_x_dev_t *dev, uint32_t mask) in mhu_v2_x_interrupt_disable()
559 const struct mhu_v2_x_dev_t *dev, uint32_t mask) in mhu_v2_x_interrupt_clear()
/trusted-firmware-m-latest/platform/ext/target/nxp/common/Native_Driver/drivers/
Dfsl_gpio.h186 static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask) in GPIO_PortSet()
198 static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask) in GPIO_PortClear()
210 static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask) in GPIO_PortToggle()
239 static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask) in GPIO_PortMaskedSet()
Dfsl_gpio.c153 void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) in GPIO_PortEnableInterrupts()
177 void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) in GPIO_PortDisableInterrupts()
202 void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask) in GPIO_PortClearInterruptFlags()
Dfsl_ctimer.h379 static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask) in CTIMER_EnableInterrupts()
404 static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask) in CTIMER_DisableInterrupts()
480 static inline void CTIMER_ClearStatusFlags(CTIMER_Type *base, uint32_t mask) in CTIMER_ClearStatusFlags()
/trusted-firmware-m-latest/platform/ext/cmsis/CMSIS/Driver/VIO/Source/
Dvio.c82 void vioSetSignal (uint32_t mask, uint32_t signal) { in vioSetSignal()
98 uint32_t vioGetSignal (uint32_t mask) { in vioGetSignal()
Dvio_memory.c51 void vioSetSignal (uint32_t mask, uint32_t signal) { in vioSetSignal()
58 uint32_t vioGetSignal (uint32_t mask) { in vioGetSignal()
/trusted-firmware-m-latest/platform/ext/target/nuvoton/m2354/bsp/Library/StdDriver/inc/
Dscu.h145 #define SCU_SET_IONSSET(port, mask) (SCU->IONSSET[((uint32_t)(port)-(GPIOA_BASE))/0x40] = (mask)) argument
188 #define SCU_ENABLE_INT(mask) (SCU->SVIOIEN |= (mask)) argument
217 #define SCU_DISABLE_INT(mask) (SCU->SVIOIEN &= (~(mask))) argument
230 #define SCU_GET_INT_FLAG(mask) (SCU->SVINTSTS&(mask)) argument
/trusted-firmware-m-latest/platform/ext/target/nuvoton/m2351/bsp/Library/StdDriver/inc/
Dscu.h149 #define SCU_SET_IONSSET(mask) (SCU->IONSSET |= (mask)) argument
199 #define SCU_ENABLE_INT(mask) (SCU->SVIOIEN |= (mask)) argument
228 #define SCU_DISABLE_INT(mask) (SCU->SVIOIEN &= (~(mask))) argument
241 #define SCU_GET_INT_FLAG(mask) (SCU->SVINTSTS&(mask)) argument
/trusted-firmware-m-latest/platform/ext/target/arm/mps3/corstone310/common/native_drivers/
Dppc_corstone310_drv.c203 ppc_corstone310_config_privilege(struct ppc_corstone310_dev_t* dev, uint32_t mask, in ppc_corstone310_config_privilege()
239 uint32_t mask) in ppc_corstone310_is_periph_priv_only()
266 ppc_corstone310_config_security(struct ppc_corstone310_dev_t* dev, uint32_t mask, in ppc_corstone310_config_security()
283 uint32_t mask) in ppc_corstone310_is_periph_secure()
/trusted-firmware-m-latest/platform/ext/target/arm/mps4/corstone315/native_drivers/
Dppc_corstone315_drv.c203 ppc_corstone315_config_privilege(struct ppc_corstone315_dev_t* dev, uint32_t mask, in ppc_corstone315_config_privilege()
239 uint32_t mask) in ppc_corstone315_is_periph_priv_only()
266 ppc_corstone315_config_security(struct ppc_corstone315_dev_t* dev, uint32_t mask, in ppc_corstone315_config_security()
283 uint32_t mask) in ppc_corstone315_is_periph_secure()
/trusted-firmware-m-latest/platform/ext/cmsis/CMSIS/Core/Include/m-profile/
Darmv8m_pmu.h242 __STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) in ARM_PMU_CNTR_Enable()
254 __STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) in ARM_PMU_CNTR_Disable()
296 __STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) in ARM_PMU_Set_CNTR_OVS()
308 __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) in ARM_PMU_Set_CNTR_IRQ_Enable()
320 __STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) in ARM_PMU_Set_CNTR_IRQ_Disable()
330 __STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) in ARM_PMU_CNTR_Increment()
/trusted-firmware-m-latest/platform/ext/target/cypress/psoc64/Device/Source/iar/
Dcy_syslib_iar.c85 uint8_t mask; in Cy_SysLib_EnterCriticalSection() local
/trusted-firmware-m-latest/platform/ext/target/arm/musca_b1/Native_Driver/
Dmhu_v2_x.c258 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask) in mhu_v2_x_channel_mask_set()
275 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask) in mhu_v2_x_channel_mask_clear()
482 const struct mhu_v2_x_dev_t *dev, uint32_t mask) in mhu_v2_x_interrupt_enable()
512 const struct mhu_v2_x_dev_t *dev, uint32_t mask) in mhu_v2_x_interrupt_disable()
542 const struct mhu_v2_x_dev_t *dev, uint32_t mask) in mhu_v2_x_interrupt_clear()
/trusted-firmware-m-latest/lib/ext/cryptocell-312-runtime/codesafe/src/crypto_api/rnd_dma/
Dllf_rnd_fetrng.c105 static uint32_t LLF_RND_TRNG_RoscMaskToNum(uint32_t mask) in LLF_RND_TRNG_RoscMaskToNum()
185 uint32_t mask = 0; in LLF_RND_StartTrngHW() local
/trusted-firmware-m-latest/platform/ext/target/arm/rse/rdfremont/bl2/
Dinterrupts_bl2.c49 uint32_t ch, value, mask = 0; in CMU_MHU4_Receiver_Handler() local
/trusted-firmware-m-latest/platform/ext/target/arm/corstone1000/Native_Driver/
Dmhu_v2_x.c275 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask) in mhu_v2_x_channel_mask_set()
292 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask) in mhu_v2_x_channel_mask_clear()
499 const struct mhu_v2_x_dev_t *dev, uint32_t mask) in mhu_v2_x_interrupt_enable()
529 const struct mhu_v2_x_dev_t *dev, uint32_t mask) in mhu_v2_x_interrupt_disable()
559 const struct mhu_v2_x_dev_t *dev, uint32_t mask) in mhu_v2_x_interrupt_clear()
/trusted-firmware-m-latest/platform/ext/target/arm/drivers/usart/pl011/
Duart_pl011_drv.c252 uint32_t mask) in _uart_pl011_set_cr_bit()
279 uint32_t mask) in _uart_pl011_clear_cr_bit()
306 uint32_t mask) in _uart_pl011_set_lcr_h_bit()
323 uint32_t mask) in _uart_pl011_clear_lcr_h_bit()
464 enum uart_pl011_intr_t mask) in uart_pl011_enable_intr()
475 enum uart_pl011_intr_t mask) in uart_pl011_disable_intr()
486 enum uart_pl011_intr_t mask) in uart_pl011_clear_intr()
/trusted-firmware-m-latest/platform/ext/target/arm/mps3/corstone300/common/native_drivers/
Dppc_sse300_drv.c320 ppc_sse300_config_privilege(struct ppc_sse300_dev_t* dev, uint32_t mask, in ppc_sse300_config_privilege()
356 uint32_t mask) in ppc_sse300_is_periph_priv_only()
383 ppc_sse300_config_security(struct ppc_sse300_dev_t* dev, uint32_t mask, in ppc_sse300_config_security()
400 uint32_t mask) in ppc_sse300_is_periph_secure()
/trusted-firmware-m-latest/platform/ext/target/armchina/mps3/alcor/common/native_drivers/
Dppc_alcor_drv.c321 ppc_alcor_config_privilege(struct ppc_alcor_dev_t* dev, uint32_t mask, in ppc_alcor_config_privilege()
357 uint32_t mask) in ppc_alcor_is_periph_priv_only()
384 ppc_alcor_config_security(struct ppc_alcor_dev_t* dev, uint32_t mask, in ppc_alcor_config_security()
401 uint32_t mask) in ppc_alcor_is_periph_secure()
/trusted-firmware-m-latest/platform/ext/target/arm/musca_s1/Native_Driver/
Dcache_drv.c239 enum arm_cache_intr_t mask) in arm_cache_enable_intr()
249 enum arm_cache_intr_t mask) in arm_cache_disable_intr()
258 enum arm_cache_intr_t mask) in arm_cache_clear_intr()
/trusted-firmware-m-latest/platform/ext/target/arm/rse/common/
Ddpa_hardened_word_copy.c52 uint32_t mask; in xorshift_get_random_uint() local
/trusted-firmware-m-latest/platform/ext/accelerator/cc312/cc312-rom/
Dcc3xx_rng.c166 uint32_t mask; in cc3xx_lowlevel_rng_get_random_uint() local
/trusted-firmware-m-latest/platform/ext/target/stm/common/stm32h5xx/hal/Src/
Dstm32h5xx_hal_cryp.c2809 uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ in CRYP_DMAInCplt() local
3695 uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ in CRYP_AESGCM_Process_IT() local
4454 uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ in CRYP_AESCCM_Process_IT() local
5248 uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ in CRYP_GCMCCM_SetHeaderPhase() local
5382 uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ in CRYP_GCMCCM_SetHeaderPhase_DMA() local
5504 uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ in CRYP_GCMCCM_SetHeaderPhase_IT() local

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