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/hal_espressif-latest/components/hal/esp32s3/include/hal/
Dcache_ll.h82 cache_bus_mask_t mask = 0; in cache_ll_l1_get_bus() local
104 static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_enable_bus()
137 cache_bus_mask_t mask = 0; in cache_ll_l1_get_enabled_bus() local
165 static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_disable_bus()
197 static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) in cache_ll_l1_enable_access_error_intr()
212 static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) in cache_ll_l1_clear_access_error_intr()
229 static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) in cache_ll_l1_get_access_error_intr_status()
244 static inline void cache_ll_l1_enable_illegal_error_intr(uint32_t cache_id, uint32_t mask) in cache_ll_l1_enable_illegal_error_intr()
255 static inline void cache_ll_l1_clear_illegal_error_intr(uint32_t cache_id, uint32_t mask) in cache_ll_l1_clear_illegal_error_intr()
268 static inline uint32_t cache_ll_l1_get_illegal_error_intr_status(uint32_t cache_id, uint32_t mask) in cache_ll_l1_get_illegal_error_intr_status()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Dcache_ll.h69 cache_bus_mask_t mask = 0; in cache_ll_l1_get_bus() local
92 static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_enable_bus()
114 static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_disable_bus()
138 static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) in cache_ll_l1_enable_access_error_intr()
149 static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) in cache_ll_l1_clear_access_error_intr()
162 static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) in cache_ll_l1_get_access_error_intr_status()
173 static inline void cache_ll_l1_enable_illegal_error_intr(uint32_t cache_id, uint32_t mask) in cache_ll_l1_enable_illegal_error_intr()
184 static inline void cache_ll_l1_clear_illegal_error_intr(uint32_t cache_id, uint32_t mask) in cache_ll_l1_clear_illegal_error_intr()
197 static inline uint32_t cache_ll_l1_get_illegal_error_intr_status(uint32_t cache_id, uint32_t mask) in cache_ll_l1_get_illegal_error_intr_status()
Ddedic_gpio_cpu_ll.h22 static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) in dedic_gpio_cpu_ll_enable_output()
48 static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value) in dedic_gpio_cpu_ll_write_mask()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Dcache_ll.h70 cache_bus_mask_t mask = 0; in cache_ll_l1_get_bus() local
93 static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_enable_bus()
115 static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_disable_bus()
139 static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) in cache_ll_l1_enable_access_error_intr()
150 static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) in cache_ll_l1_clear_access_error_intr()
163 static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) in cache_ll_l1_get_access_error_intr_status()
174 static inline void cache_ll_l1_enable_illegal_error_intr(uint32_t cache_id, uint32_t mask) in cache_ll_l1_enable_illegal_error_intr()
185 static inline void cache_ll_l1_clear_illegal_error_intr(uint32_t cache_id, uint32_t mask) in cache_ll_l1_clear_illegal_error_intr()
198 static inline uint32_t cache_ll_l1_get_illegal_error_intr_status(uint32_t cache_id, uint32_t mask) in cache_ll_l1_get_illegal_error_intr_status()
Ddedic_gpio_cpu_ll.h22 static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) in dedic_gpio_cpu_ll_enable_output()
47 static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value) in dedic_gpio_cpu_ll_write_mask()
Dusb_serial_jtag_ll.h46 static inline void usb_serial_jtag_ll_ena_intr_mask(uint32_t mask) in usb_serial_jtag_ll_ena_intr_mask()
58 static inline void usb_serial_jtag_ll_disable_intr_mask(uint32_t mask) in usb_serial_jtag_ll_disable_intr_mask()
90 static inline __attribute__((always_inline)) void usb_serial_jtag_ll_clr_intsts_mask(uint32_t mask) in usb_serial_jtag_ll_clr_intsts_mask()
/hal_espressif-latest/components/hal/esp32h2/include/hal/
Dcache_ll.h44 cache_bus_mask_t mask = 0; in cache_ll_l1_get_bus() local
66 static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_enable_bus()
88 static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_disable_bus()
112 static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) in cache_ll_l1_enable_access_error_intr()
123 static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) in cache_ll_l1_clear_access_error_intr()
136 static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) in cache_ll_l1_get_access_error_intr_status()
Ddedic_gpio_cpu_ll.h22 static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) in dedic_gpio_cpu_ll_enable_output()
47 static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value) in dedic_gpio_cpu_ll_write_mask()
/hal_espressif-latest/components/hal/esp32c6/include/hal/
Dcache_ll.h44 cache_bus_mask_t mask = 0; in cache_ll_l1_get_bus() local
66 static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_enable_bus()
88 static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_disable_bus()
112 static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask) in cache_ll_l1_enable_access_error_intr()
123 static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask) in cache_ll_l1_clear_access_error_intr()
136 static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask) in cache_ll_l1_get_access_error_intr_status()
Ddedic_gpio_cpu_ll.h22 static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask) in dedic_gpio_cpu_ll_enable_output()
47 static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value) in dedic_gpio_cpu_ll_write_mask()
Dusb_serial_jtag_ll.h47 static inline void usb_serial_jtag_ll_ena_intr_mask(uint32_t mask) in usb_serial_jtag_ll_ena_intr_mask()
59 static inline void usb_serial_jtag_ll_disable_intr_mask(uint32_t mask) in usb_serial_jtag_ll_disable_intr_mask()
91 static inline __attribute__((always_inline)) void usb_serial_jtag_ll_clr_intsts_mask(uint32_t mask) in usb_serial_jtag_ll_clr_intsts_mask()
/hal_espressif-latest/components/bt/host/bluedroid/bta/ar/
Dbta_ar.c50 UINT8 mask = 0; in bta_ar_id() local
106 UINT8 mask = 0; in bta_ar_reg_avdt() local
140 UINT8 mask = 0; in bta_ar_dereg_avdt() local
195 UINT8 mask = bta_ar_id (sys_id); in bta_ar_reg_avct() local
216 UINT8 mask = bta_ar_id (sys_id); in bta_ar_dereg_avct() local
237 UINT8 mask = bta_ar_id (sys_id); in bta_ar_reg_avrc() local
282 UINT8 mask = bta_ar_id (sys_id); in bta_ar_dereg_avrc() local
/hal_espressif-latest/components/hal/
Dadc_hal.c31 #define adc_dma_ll_rx_clear_intr(dev, chan, mask) gdma_ll_rx_clear_interrupt_status(dev, chan… argument
32 #define adc_dma_ll_rx_enable_intr(dev, chan, mask) gdma_ll_rx_enable_interrupt(dev, chan, mask… argument
33 #define adc_dma_ll_rx_disable_intr(dev, chan, mask) gdma_ll_rx_enable_interrupt(dev, chan, mask… argument
47 #define adc_dma_ll_rx_get_intr(dev, mask) spi_ll_get_intr(dev, mask) argument
48 #define adc_dma_ll_rx_clear_intr(dev, chan, mask) spi_ll_clear_intr(dev, mask) argument
49 #define adc_dma_ll_rx_enable_intr(dev, chan, mask) spi_ll_enable_intr(dev, mask) argument
50 #define adc_dma_ll_rx_disable_intr(dev, chan, mask) spi_ll_disable_intr(dev, mask) argument
62 #define adc_dma_ll_rx_get_intr(dev, mask) ({i2s_ll_get_intr_status(dev) & mask;}) argument
63 #define adc_dma_ll_rx_clear_intr(dev, chan, mask) i2s_ll_clear_intr_status(dev, mask) argument
64 #define adc_dma_ll_rx_enable_intr(dev, chan, mask) do {((i2s_dev_t *)(dev))->int_ena.val |= ma… argument
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/hal_espressif-latest/components/wpa_supplicant/src/utils/
Dconst_time.h99 static inline unsigned int const_time_select(unsigned int mask, in const_time_select()
114 static inline int const_time_select_int(unsigned int mask, int true_val, in const_time_select_int()
129 static inline u8 const_time_select_u8(u8 mask, u8 true_val, u8 false_val) in const_time_select_u8()
142 static inline s8 const_time_select_s8(u8 mask, s8 true_val, s8 false_val) in const_time_select_s8()
161 static inline void const_time_select_bin(u8 mask, const u8 *true_val, in const_time_select_bin()
177 unsigned int mask; in const_time_memcmp() local
/hal_espressif-latest/components/hal/esp32/include/hal/
Dcache_ll.h98 cache_bus_mask_t mask = 0; in cache_ll_l1_get_bus() local
135 static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_enable_bus()
172 cache_bus_mask_t mask = 0; in cache_ll_l1_get_enabled_bus() local
202 static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_disable_bus()
/hal_espressif-latest/components/bt/esp_ble_mesh/mesh_common/include/
Dmesh_atomic.h236 bt_mesh_atomic_val_t mask = BLE_MESH_ATOMIC_MASK(bit); in bt_mesh_atomic_test_and_clear_bit() local
257 bt_mesh_atomic_val_t mask = BLE_MESH_ATOMIC_MASK(bit); in bt_mesh_atomic_test_and_set_bit() local
278 bt_mesh_atomic_val_t mask = BLE_MESH_ATOMIC_MASK(bit); in bt_mesh_atomic_clear_bit() local
296 bt_mesh_atomic_val_t mask = BLE_MESH_ATOMIC_MASK(bit); in bt_mesh_atomic_set_bit() local
315 bt_mesh_atomic_val_t mask = BLE_MESH_ATOMIC_MASK(bit); in bt_mesh_atomic_set_bit_to() local
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Dcache_ll.h66 cache_bus_mask_t mask = 0; in cache_ll_l1_get_bus() local
111 static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_enable_bus()
135 static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask) in cache_ll_l1_disable_bus()
/hal_espressif-latest/components/hal/include/hal/
Duart_hal.h60 #define uart_hal_clr_intsts_mask(hal, mask) uart_ll_clr_intsts_mask((hal)->dev, mask) argument
70 #define uart_hal_disable_intr_mask(hal, mask) uart_ll_disable_intr_mask((hal)->dev, mask) argument
80 #define uart_hal_ena_intr_mask(hal, mask) uart_ll_ena_intr_mask((hal)->dev, mask) argument
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Ddport_access.h90 #define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&… argument
93 #define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|… argument
96 #define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) argument
105 #define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) argument
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Ddport_access.h87 #define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&… argument
90 #define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|… argument
93 #define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) argument
102 #define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) argument
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Ddport_access.h89 #define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&… argument
92 #define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|… argument
95 #define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) argument
104 #define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) argument
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Ddport_access.h90 #define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&… argument
93 #define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|… argument
96 #define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) argument
105 #define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) argument
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Ddport_access.h90 #define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&… argument
93 #define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|… argument
96 #define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) argument
105 #define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) argument
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Ddport_access.h88 #define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&… argument
91 #define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|… argument
94 #define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) argument
103 #define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) argument
/hal_espressif-latest/components/soc/esp32/include/soc/
Ddport_access.h181 #define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&… argument
184 #define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|… argument
187 #define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) argument
196 #define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) argument

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