1 /**
2 ******************************************************************************
3 * @file lsm6dsv_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSV driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dsv_reg.h"
21
22 /**
23 * @defgroup LSM6DSV
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dsv enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup Interfaces functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx communication interface handler.(ptr)
43 * @param reg first register address to read.
44 * @param data buffer for data read.(ptr)
45 * @param len number of consecutive register to read.
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6dsv_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dsv_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx communication interface handler.(ptr)
69 * @param reg first register address to write.
70 * @param data the buffer contains data to be written.(ptr)
71 * @param len number of consecutive register to write.
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lsm6dsv_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lsm6dsv_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup Private functions
98 * @brief Section collect all the utility functions needed by APIs.
99 * @{
100 *
101 */
102
bytecpy(uint8_t * target,uint8_t * source)103 static void bytecpy(uint8_t *target, uint8_t *source)
104 {
105 if ((target != NULL) && (source != NULL))
106 {
107 *target = *source;
108 }
109 }
110
111 /**
112 * @}
113 *
114 */
115
116 /**
117 * @defgroup Sensitivity
118 * @brief These functions convert raw-data into engineering units.
119 * @{
120 *
121 */
lsm6dsv_from_sflp_to_mg(int16_t lsb)122 float_t lsm6dsv_from_sflp_to_mg(int16_t lsb)
123 {
124 return ((float_t)lsb) * 0.061f;
125 }
126
lsm6dsv_from_fs2_to_mg(int16_t lsb)127 float_t lsm6dsv_from_fs2_to_mg(int16_t lsb)
128 {
129 return ((float_t)lsb) * 0.061f;
130 }
131
lsm6dsv_from_fs4_to_mg(int16_t lsb)132 float_t lsm6dsv_from_fs4_to_mg(int16_t lsb)
133 {
134 return ((float_t)lsb) * 0.122f;
135 }
136
lsm6dsv_from_fs8_to_mg(int16_t lsb)137 float_t lsm6dsv_from_fs8_to_mg(int16_t lsb)
138 {
139 return ((float_t)lsb) * 0.244f;
140 }
141
lsm6dsv_from_fs16_to_mg(int16_t lsb)142 float_t lsm6dsv_from_fs16_to_mg(int16_t lsb)
143 {
144 return ((float_t)lsb) * 0.488f;
145 }
146
lsm6dsv_from_fs125_to_mdps(int16_t lsb)147 float_t lsm6dsv_from_fs125_to_mdps(int16_t lsb)
148 {
149 return ((float_t)lsb) * 4.375f;
150 }
151
lsm6dsv_from_fs250_to_mdps(int16_t lsb)152 float_t lsm6dsv_from_fs250_to_mdps(int16_t lsb)
153 {
154 return ((float_t)lsb) * 8.750f;
155 }
156
lsm6dsv_from_fs500_to_mdps(int16_t lsb)157 float_t lsm6dsv_from_fs500_to_mdps(int16_t lsb)
158 {
159 return ((float_t)lsb) * 17.50f;
160 }
161
lsm6dsv_from_fs1000_to_mdps(int16_t lsb)162 float_t lsm6dsv_from_fs1000_to_mdps(int16_t lsb)
163 {
164 return ((float_t)lsb) * 35.0f;
165 }
166
lsm6dsv_from_fs2000_to_mdps(int16_t lsb)167 float_t lsm6dsv_from_fs2000_to_mdps(int16_t lsb)
168 {
169 return ((float_t)lsb) * 70.0f;
170 }
171
lsm6dsv_from_fs4000_to_mdps(int16_t lsb)172 float_t lsm6dsv_from_fs4000_to_mdps(int16_t lsb)
173 {
174 return ((float_t)lsb) * 140.0f;
175 }
176
lsm6dsv_from_lsb_to_celsius(int16_t lsb)177 float_t lsm6dsv_from_lsb_to_celsius(int16_t lsb)
178 {
179 return (((float_t)lsb / 256.0f) + 25.0f);
180 }
181
lsm6dsv_from_lsb_to_nsec(uint32_t lsb)182 float_t lsm6dsv_from_lsb_to_nsec(uint32_t lsb)
183 {
184 return ((float_t)lsb * 21750.0f);
185 }
186
187 /*
188 * Original conversion routines taken from: https://github.com/numpy/numpy
189 *
190 * Converts from half-precision (16-bit) float number to single precision (32-bit).
191 *
192 * uint32_t static uint32_t ToFloatBits(uint16_t h);
193 * Released under BSD-3-Clause License
194 */
ToFloatBits(uint16_t h)195 static uint32_t ToFloatBits(uint16_t h)
196 {
197 uint16_t h_exp = (h & 0x7c00u);
198 uint32_t f_sgn = ((uint32_t)h & 0x8000u) << 16;
199 switch (h_exp)
200 {
201 case 0x0000u: // 0 or subnormal
202 {
203 uint16_t h_sig = (h & 0x03ffu);
204 // Signed zero
205 if (h_sig == 0)
206 {
207 return f_sgn;
208 }
209 // Subnormal
210 h_sig <<= 1;
211 while ((h_sig & 0x0400u) == 0)
212 {
213 h_sig <<= 1;
214 h_exp++;
215 }
216 uint32_t f_exp = ((uint32_t)(127 - 15 - h_exp)) << 23;
217 uint32_t f_sig = ((uint32_t)(h_sig & 0x03ffu)) << 13;
218 return f_sgn + f_exp + f_sig;
219 }
220 case 0x7c00u: // inf or NaN
221 // All-ones exponent and a copy of the significand
222 return f_sgn + 0x7f800000u + (((uint32_t)(h & 0x03ffu)) << 13);
223 default: // normalized
224 // Just need to adjust the exponent and shift
225 return f_sgn + (((uint32_t)(h & 0x7fffu) + 0x1c000u) << 13);
226 }
227 }
228
229 /**
230 * @brief Convert from 16-bit to 32-bit float number
231 *
232 * @param val Batching in FIFO buffer of SFLP values.
233 * @retval interface status (MANDATORY: return 0 -> no Error)
234 *
235 */
lsm6dsv_from_f16_to_f32(uint16_t val)236 uint32_t lsm6dsv_from_f16_to_f32(uint16_t val)
237 {
238 return ToFloatBits(val);
239 }
240
241 /**
242 * @}
243 *
244 */
245
246 /**
247 * @defgroup Accelerometer user offset correction
248 * @brief This section groups all the functions concerning the
249 * usage of Accelerometer user offset correction
250 * @{
251 *
252 */
253
254 /**
255 * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[set]
256 *
257 * @param ctx read / write interface definitions
258 * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path.
259 * @retval interface status (MANDATORY: return 0 -> no Error)
260 *
261 */
lsm6dsv_xl_offset_on_out_set(const stmdev_ctx_t * ctx,uint8_t val)262 int32_t lsm6dsv_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val)
263 {
264 lsm6dsv_ctrl9_t ctrl9;
265 int32_t ret;
266
267 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1);
268 if (ret == 0)
269 {
270 ctrl9.usr_off_on_out = val;
271 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1);
272 }
273
274 return ret;
275 }
276
277 /**
278 * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[get]
279 *
280 * @param ctx read / write interface definitions
281 * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path.
282 * @retval interface status (MANDATORY: return 0 -> no Error)
283 *
284 */
lsm6dsv_xl_offset_on_out_get(const stmdev_ctx_t * ctx,uint8_t * val)285 int32_t lsm6dsv_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val)
286 {
287 lsm6dsv_ctrl9_t ctrl9;
288 int32_t ret;
289
290 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1);
291 *val = ctrl9.usr_off_on_out;
292
293 return ret;
294 }
295
296 /**
297 * @brief Accelerometer user offset correction values in mg.[set]
298 *
299 * @param ctx read / write interface definitions
300 * @param val Accelerometer user offset correction values in mg.
301 * @retval interface status (MANDATORY: return 0 -> no Error)
302 *
303 */
lsm6dsv_xl_offset_mg_set(const stmdev_ctx_t * ctx,lsm6dsv_xl_offset_mg_t val)304 int32_t lsm6dsv_xl_offset_mg_set(const stmdev_ctx_t *ctx,
305 lsm6dsv_xl_offset_mg_t val)
306 {
307 lsm6dsv_z_ofs_usr_t z_ofs_usr;
308 lsm6dsv_y_ofs_usr_t y_ofs_usr;
309 lsm6dsv_x_ofs_usr_t x_ofs_usr;
310 lsm6dsv_ctrl9_t ctrl9;
311 int32_t ret;
312 float_t tmp;
313
314 ret = lsm6dsv_read_reg(ctx, LSM6DSV_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
315 ret += lsm6dsv_read_reg(ctx, LSM6DSV_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
316 ret += lsm6dsv_read_reg(ctx, LSM6DSV_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
317 if (ret != 0)
318 {
319 return ret;
320 }
321
322
323 if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) &&
324 (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) &&
325 (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f)))
326 {
327 ctrl9.usr_off_w = 0;
328
329 tmp = val.z_mg / 0.0078125f;
330 z_ofs_usr.z_ofs_usr = (uint8_t)tmp;
331
332 tmp = val.y_mg / 0.0078125f;
333 y_ofs_usr.y_ofs_usr = (uint8_t)tmp;
334
335 tmp = val.x_mg / 0.0078125f;
336 x_ofs_usr.x_ofs_usr = (uint8_t)tmp;
337 }
338 else if ((val.x_mg < (0.125f * 127.0f)) && (val.x_mg > (0.125f * -127.0f)) &&
339 (val.y_mg < (0.125f * 127.0f)) && (val.y_mg > (0.125f * -127.0f)) &&
340 (val.z_mg < (0.125f * 127.0f)) && (val.z_mg > (0.125f * -127.0f)))
341 {
342 ctrl9.usr_off_w = 1;
343
344 tmp = val.z_mg / 0.125f;
345 z_ofs_usr.z_ofs_usr = (uint8_t)tmp;
346
347 tmp = val.y_mg / 0.125f;
348 y_ofs_usr.y_ofs_usr = (uint8_t)tmp;
349
350 tmp = val.x_mg / 0.125f;
351 x_ofs_usr.x_ofs_usr = (uint8_t)tmp;
352 }
353 else // out of limit
354 {
355 ctrl9.usr_off_w = 1;
356 z_ofs_usr.z_ofs_usr = 0xFFU;
357 y_ofs_usr.y_ofs_usr = 0xFFU;
358 x_ofs_usr.x_ofs_usr = 0xFFU;
359 }
360
361 ret = lsm6dsv_write_reg(ctx, LSM6DSV_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
362 ret += lsm6dsv_write_reg(ctx, LSM6DSV_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
363 ret += lsm6dsv_write_reg(ctx, LSM6DSV_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
364 ret += lsm6dsv_write_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1);
365
366 return ret;
367 }
368
369 /**
370 * @brief Accelerometer user offset correction values in mg.[get]
371 *
372 * @param ctx read / write interface definitions
373 * @param val Accelerometer user offset correction values in mg.
374 * @retval interface status (MANDATORY: return 0 -> no Error)
375 *
376 */
lsm6dsv_xl_offset_mg_get(const stmdev_ctx_t * ctx,lsm6dsv_xl_offset_mg_t * val)377 int32_t lsm6dsv_xl_offset_mg_get(const stmdev_ctx_t *ctx,
378 lsm6dsv_xl_offset_mg_t *val)
379 {
380 lsm6dsv_z_ofs_usr_t z_ofs_usr;
381 lsm6dsv_y_ofs_usr_t y_ofs_usr;
382 lsm6dsv_x_ofs_usr_t x_ofs_usr;
383 lsm6dsv_ctrl9_t ctrl9;
384 int32_t ret;
385
386 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1);
387 ret += lsm6dsv_read_reg(ctx, LSM6DSV_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
388 ret += lsm6dsv_read_reg(ctx, LSM6DSV_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
389 ret += lsm6dsv_read_reg(ctx, LSM6DSV_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
390 if (ret != 0)
391 {
392 return ret;
393 }
394
395 if (ctrl9.usr_off_w == PROPERTY_DISABLE)
396 {
397 val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.0078125f);
398 val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.0078125f);
399 val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.0078125f);
400 }
401 else
402 {
403 val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.125f);
404 val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.125f);
405 val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.125f);
406 }
407
408 return ret;
409 }
410
411 /**
412 * @}
413 *
414 */
415
416 /**
417 * @brief Reset of the device.[set]
418 *
419 * @param ctx read / write interface definitions
420 * @param val Reset of the device.
421 * @retval interface status (MANDATORY: return 0 -> no Error)
422 *
423 */
lsm6dsv_reset_set(const stmdev_ctx_t * ctx,lsm6dsv_reset_t val)424 int32_t lsm6dsv_reset_set(const stmdev_ctx_t *ctx, lsm6dsv_reset_t val)
425 {
426 lsm6dsv_func_cfg_access_t func_cfg_access;
427 lsm6dsv_ctrl3_t ctrl3;
428 int32_t ret;
429
430 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1);
431 ret += lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
432 if (ret != 0)
433 {
434 return ret;
435 }
436
437 ctrl3.boot = ((uint8_t)val & 0x04U) >> 2;
438 ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1;
439 func_cfg_access.sw_por = (uint8_t)val & 0x01U;
440
441 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1);
442 ret += lsm6dsv_write_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
443
444 return ret;
445 }
446
447 /**
448 * @brief Global reset of the device.[get]
449 *
450 * @param ctx read / write interface definitions
451 * @param val Global reset of the device.
452 * @retval interface status (MANDATORY: return 0 -> no Error)
453 *
454 */
lsm6dsv_reset_get(const stmdev_ctx_t * ctx,lsm6dsv_reset_t * val)455 int32_t lsm6dsv_reset_get(const stmdev_ctx_t *ctx, lsm6dsv_reset_t *val)
456 {
457 lsm6dsv_func_cfg_access_t func_cfg_access;
458 lsm6dsv_ctrl3_t ctrl3;
459 int32_t ret;
460
461 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1);
462 ret += lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
463 if (ret != 0)
464 {
465 return ret;
466 }
467
468 switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por)
469 {
470 case LSM6DSV_READY:
471 *val = LSM6DSV_READY;
472 break;
473
474 case LSM6DSV_GLOBAL_RST:
475 *val = LSM6DSV_GLOBAL_RST;
476 break;
477
478 case LSM6DSV_RESTORE_CAL_PARAM:
479 *val = LSM6DSV_RESTORE_CAL_PARAM;
480 break;
481
482 case LSM6DSV_RESTORE_CTRL_REGS:
483 *val = LSM6DSV_RESTORE_CTRL_REGS;
484 break;
485
486 default:
487 *val = LSM6DSV_GLOBAL_RST;
488 break;
489 }
490
491 return ret;
492 }
493
494 /**
495 * @brief Change memory bank.[set]
496 *
497 * @param ctx read / write interface definitions
498 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK,
499 * @retval interface status (MANDATORY: return 0 -> no Error)
500 *
501 */
lsm6dsv_mem_bank_set(const stmdev_ctx_t * ctx,lsm6dsv_mem_bank_t val)502 int32_t lsm6dsv_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsv_mem_bank_t val)
503 {
504 lsm6dsv_func_cfg_access_t func_cfg_access;
505 int32_t ret;
506
507 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
508 if (ret != 0)
509 {
510 return ret;
511 }
512
513 func_cfg_access.shub_reg_access = ((uint8_t)val & 0x02U) >> 1;
514 func_cfg_access.emb_func_reg_access = (uint8_t)val & 0x01U;
515 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
516
517 return ret;
518 }
519
520 /**
521 * @brief Change memory bank.[get]
522 *
523 * @param ctx read / write interface definitions
524 * @param val MAIN_MEM_BANK, SENSOR_HUB_MEM_BANK, EMBED_FUNC_MEM_BANK,
525 * @retval interface status (MANDATORY: return 0 -> no Error)
526 *
527 */
lsm6dsv_mem_bank_get(const stmdev_ctx_t * ctx,lsm6dsv_mem_bank_t * val)528 int32_t lsm6dsv_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsv_mem_bank_t *val)
529 {
530 lsm6dsv_func_cfg_access_t func_cfg_access;
531 int32_t ret;
532
533 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
534 if (ret != 0)
535 {
536 return ret;
537 }
538
539 switch ((func_cfg_access.shub_reg_access << 1) + func_cfg_access.emb_func_reg_access)
540 {
541 case LSM6DSV_MAIN_MEM_BANK:
542 *val = LSM6DSV_MAIN_MEM_BANK;
543 break;
544
545 case LSM6DSV_EMBED_FUNC_MEM_BANK:
546 *val = LSM6DSV_EMBED_FUNC_MEM_BANK;
547 break;
548
549 case LSM6DSV_SENSOR_HUB_MEM_BANK:
550 *val = LSM6DSV_SENSOR_HUB_MEM_BANK;
551 break;
552
553 default:
554 *val = LSM6DSV_MAIN_MEM_BANK;
555 break;
556 }
557
558 return ret;
559 }
560
561 /**
562 * @brief Device ID.[get] THis function works also for OIS
563 * (WHO_AM_I and SPI2_WHO_AM_I have same address)
564 *
565 * @param ctx read / write interface definitions
566 * @param val Device ID.
567 * @retval interface status (MANDATORY: return 0 -> no Error)
568 *
569 */
lsm6dsv_device_id_get(const stmdev_ctx_t * ctx,uint8_t * val)570 int32_t lsm6dsv_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val)
571 {
572 int32_t ret;
573
574 ret = lsm6dsv_read_reg(ctx, LSM6DSV_WHO_AM_I, val, 1);
575
576 return ret;
577 }
578
579 /**
580 * @brief Accelerometer output data rate (ODR) selection.[set]
581 *
582 * @param ctx read / write interface definitions
583 * @param val lsm6dsv_data_rate_t enum
584 * @retval interface status (MANDATORY: return 0 -> no Error)
585 *
586 */
lsm6dsv_xl_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv_data_rate_t val)587 int32_t lsm6dsv_xl_data_rate_set(const stmdev_ctx_t *ctx,
588 lsm6dsv_data_rate_t val)
589 {
590 lsm6dsv_ctrl1_t ctrl1;
591 lsm6dsv_haodr_cfg_t haodr;
592 uint8_t sel;
593 int32_t ret;
594
595 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL1, (uint8_t *)&ctrl1, 1);
596 if (ret != 0)
597 {
598 return ret;
599 }
600
601 ctrl1.odr_xl = (uint8_t)val & 0x0Fu;
602 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL1, (uint8_t *)&ctrl1, 1);
603 if (ret != 0)
604 {
605 return ret;
606 }
607
608 sel = ((uint8_t)val >> 4) & 0xFU;
609 if (sel != 0U)
610 {
611 ret += lsm6dsv_read_reg(ctx, LSM6DSV_HAODR_CFG, (uint8_t *)&haodr, 1);
612 haodr.haodr_sel = sel;
613 ret += lsm6dsv_write_reg(ctx, LSM6DSV_HAODR_CFG, (uint8_t *)&haodr, 1);
614 }
615
616 return ret;
617 }
618
619 /**
620 * @brief Accelerometer output data rate (ODR) selection.[get]
621 *
622 * @param ctx read / write interface definitions
623 * @param val lsm6dsv_data_rate_t enum
624 * @retval interface status (MANDATORY: return 0 -> no Error)
625 *
626 */
lsm6dsv_xl_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv_data_rate_t * val)627 int32_t lsm6dsv_xl_data_rate_get(const stmdev_ctx_t *ctx,
628 lsm6dsv_data_rate_t *val)
629 {
630 lsm6dsv_ctrl1_t ctrl1;
631 lsm6dsv_haodr_cfg_t haodr;
632 uint8_t sel;
633 int32_t ret;
634
635 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL1, (uint8_t *)&ctrl1, 1);
636 ret += lsm6dsv_read_reg(ctx, LSM6DSV_HAODR_CFG, (uint8_t *)&haodr, 1);
637 if (ret != 0)
638 {
639 return ret;
640 }
641
642 sel = haodr.haodr_sel;
643
644 switch (ctrl1.odr_xl)
645 {
646 case LSM6DSV_ODR_OFF:
647 *val = LSM6DSV_ODR_OFF;
648 break;
649
650 case LSM6DSV_ODR_AT_1Hz875:
651 *val = LSM6DSV_ODR_AT_1Hz875;
652 break;
653
654 case LSM6DSV_ODR_AT_7Hz5:
655 *val = LSM6DSV_ODR_AT_7Hz5;
656 break;
657
658 case LSM6DSV_ODR_AT_15Hz:
659 switch (sel)
660 {
661 default:
662 case 0:
663 *val = LSM6DSV_ODR_AT_15Hz;
664 break;
665 case 1:
666 *val = LSM6DSV_ODR_HA01_AT_15Hz625;
667 break;
668 case 2:
669 *val = LSM6DSV_ODR_HA02_AT_12Hz5;
670 break;
671 }
672 break;
673
674 case LSM6DSV_ODR_AT_30Hz:
675 switch (sel)
676 {
677 default:
678 case 0:
679 *val = LSM6DSV_ODR_AT_30Hz;
680 break;
681 case 1:
682 *val = LSM6DSV_ODR_HA01_AT_31Hz25;
683 break;
684 case 2:
685 *val = LSM6DSV_ODR_HA02_AT_25Hz;
686 break;
687 }
688 break;
689
690 case LSM6DSV_ODR_AT_60Hz:
691 switch (sel)
692 {
693 default:
694 case 0:
695 *val = LSM6DSV_ODR_AT_60Hz;
696 break;
697 case 1:
698 *val = LSM6DSV_ODR_HA01_AT_62Hz5;
699 break;
700 case 2:
701 *val = LSM6DSV_ODR_HA02_AT_50Hz;
702 break;
703 }
704 break;
705
706 case LSM6DSV_ODR_AT_120Hz:
707 switch (sel)
708 {
709 default:
710 case 0:
711 *val = LSM6DSV_ODR_AT_120Hz;
712 break;
713 case 1:
714 *val = LSM6DSV_ODR_HA01_AT_125Hz;
715 break;
716 case 2:
717 *val = LSM6DSV_ODR_HA02_AT_100Hz;
718 break;
719 }
720 break;
721
722 case LSM6DSV_ODR_AT_240Hz:
723 switch (sel)
724 {
725 default:
726 case 0:
727 *val = LSM6DSV_ODR_AT_240Hz;
728 break;
729 case 1:
730 *val = LSM6DSV_ODR_HA01_AT_250Hz;
731 break;
732 case 2:
733 *val = LSM6DSV_ODR_HA02_AT_200Hz;
734 break;
735 }
736 break;
737
738 case LSM6DSV_ODR_AT_480Hz:
739 switch (sel)
740 {
741 default:
742 case 0:
743 *val = LSM6DSV_ODR_AT_480Hz;
744 break;
745 case 1:
746 *val = LSM6DSV_ODR_HA01_AT_500Hz;
747 break;
748 case 2:
749 *val = LSM6DSV_ODR_HA02_AT_400Hz;
750 break;
751 }
752 break;
753
754 case LSM6DSV_ODR_AT_960Hz:
755 switch (sel)
756 {
757 default:
758 case 0:
759 *val = LSM6DSV_ODR_AT_960Hz;
760 break;
761 case 1:
762 *val = LSM6DSV_ODR_HA01_AT_1000Hz;
763 break;
764 case 2:
765 *val = LSM6DSV_ODR_HA02_AT_800Hz;
766 break;
767 }
768 break;
769
770 case LSM6DSV_ODR_AT_1920Hz:
771 switch (sel)
772 {
773 default:
774 case 0:
775 *val = LSM6DSV_ODR_AT_1920Hz;
776 break;
777 case 1:
778 *val = LSM6DSV_ODR_HA01_AT_2000Hz;
779 break;
780 case 2:
781 *val = LSM6DSV_ODR_HA02_AT_1600Hz;
782 break;
783 }
784 break;
785
786 case LSM6DSV_ODR_AT_3840Hz:
787 switch (sel)
788 {
789 default:
790 case 0:
791 *val = LSM6DSV_ODR_AT_3840Hz;
792 break;
793 case 1:
794 *val = LSM6DSV_ODR_HA01_AT_4000Hz;
795 break;
796 case 2:
797 *val = LSM6DSV_ODR_HA02_AT_3200Hz;
798 break;
799 }
800 break;
801
802 case LSM6DSV_ODR_AT_7680Hz:
803 switch (sel)
804 {
805 default:
806 case 0:
807 *val = LSM6DSV_ODR_AT_7680Hz;
808 break;
809 case 1:
810 *val = LSM6DSV_ODR_HA01_AT_8000Hz;
811 break;
812 case 2:
813 *val = LSM6DSV_ODR_HA02_AT_6400Hz;
814 break;
815 }
816 break;
817
818 default:
819 *val = LSM6DSV_ODR_OFF;
820 break;
821 }
822
823 return ret;
824 }
825
826 /**
827 * @brief Accelerometer operating mode selection.[set]
828 *
829 * @param ctx read / write interface definitions
830 * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURACY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD,
831 * @retval interface status (MANDATORY: return 0 -> no Error)
832 *
833 */
lsm6dsv_xl_mode_set(const stmdev_ctx_t * ctx,lsm6dsv_xl_mode_t val)834 int32_t lsm6dsv_xl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_xl_mode_t val)
835 {
836 lsm6dsv_ctrl1_t ctrl1;
837 int32_t ret;
838
839 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL1, (uint8_t *)&ctrl1, 1);
840
841 if (ret == 0)
842 {
843 ctrl1.op_mode_xl = (uint8_t)val & 0x07U;
844 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL1, (uint8_t *)&ctrl1, 1);
845 }
846
847 return ret;
848 }
849
850 /**
851 * @brief Accelerometer operating mode selection.[get]
852 *
853 * @param ctx read / write interface definitions
854 * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURACY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD,
855 * @retval interface status (MANDATORY: return 0 -> no Error)
856 *
857 */
lsm6dsv_xl_mode_get(const stmdev_ctx_t * ctx,lsm6dsv_xl_mode_t * val)858 int32_t lsm6dsv_xl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_xl_mode_t *val)
859 {
860 lsm6dsv_ctrl1_t ctrl1;
861 int32_t ret;
862
863 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL1, (uint8_t *)&ctrl1, 1);
864 if (ret != 0)
865 {
866 return ret;
867 }
868
869 switch (ctrl1.op_mode_xl)
870 {
871 case LSM6DSV_XL_HIGH_PERFORMANCE_MD:
872 *val = LSM6DSV_XL_HIGH_PERFORMANCE_MD;
873 break;
874
875 case LSM6DSV_XL_HIGH_ACCURACY_ODR_MD:
876 *val = LSM6DSV_XL_HIGH_ACCURACY_ODR_MD;
877 break;
878
879 case LSM6DSV_XL_ODR_TRIGGERED_MD:
880 *val = LSM6DSV_XL_ODR_TRIGGERED_MD;
881 break;
882
883 case LSM6DSV_XL_LOW_POWER_2_AVG_MD:
884 *val = LSM6DSV_XL_LOW_POWER_2_AVG_MD;
885 break;
886
887 case LSM6DSV_XL_LOW_POWER_4_AVG_MD:
888 *val = LSM6DSV_XL_LOW_POWER_4_AVG_MD;
889 break;
890
891 case LSM6DSV_XL_LOW_POWER_8_AVG_MD:
892 *val = LSM6DSV_XL_LOW_POWER_8_AVG_MD;
893 break;
894
895 case LSM6DSV_XL_NORMAL_MD:
896 *val = LSM6DSV_XL_NORMAL_MD;
897 break;
898
899 default:
900 *val = LSM6DSV_XL_HIGH_PERFORMANCE_MD;
901 break;
902 }
903
904 return ret;
905 }
906
907 /**
908 * @brief Gyroscope output data rate (ODR) selection.[set]
909 *
910 * @param ctx read / write interface definitions
911 * @param val lsm6dsv_data_rate_t enum
912 * @retval interface status (MANDATORY: return 0 -> no Error)
913 *
914 */
lsm6dsv_gy_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv_data_rate_t val)915 int32_t lsm6dsv_gy_data_rate_set(const stmdev_ctx_t *ctx,
916 lsm6dsv_data_rate_t val)
917 {
918 lsm6dsv_ctrl2_t ctrl2;
919 lsm6dsv_haodr_cfg_t haodr;
920 uint8_t sel;
921 int32_t ret;
922
923 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL2, (uint8_t *)&ctrl2, 1);
924
925 ctrl2.odr_g = (uint8_t)val & 0x0Fu;
926 ret += lsm6dsv_write_reg(ctx, LSM6DSV_CTRL2, (uint8_t *)&ctrl2, 1);
927 if (ret != 0)
928 {
929 return ret;
930 }
931
932 sel = ((uint8_t)val >> 4) & 0xFU;
933 if (sel != 0U)
934 {
935 ret += lsm6dsv_read_reg(ctx, LSM6DSV_HAODR_CFG, (uint8_t *)&haodr, 1);
936 haodr.haodr_sel = sel;
937 ret += lsm6dsv_write_reg(ctx, LSM6DSV_HAODR_CFG, (uint8_t *)&haodr, 1);
938 }
939
940 return ret;
941 }
942
943 /**
944 * @brief Gyroscope output data rate (ODR) selection.[get]
945 *
946 * @param ctx read / write interface definitions
947 * @param val lsm6dsv_data_rate_t enum
948 * @retval interface status (MANDATORY: return 0 -> no Error)
949 *
950 */
lsm6dsv_gy_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv_data_rate_t * val)951 int32_t lsm6dsv_gy_data_rate_get(const stmdev_ctx_t *ctx,
952 lsm6dsv_data_rate_t *val)
953 {
954 lsm6dsv_ctrl2_t ctrl2;
955 lsm6dsv_haodr_cfg_t haodr;
956 uint8_t sel;
957 int32_t ret;
958
959 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL2, (uint8_t *)&ctrl2, 1);
960 ret += lsm6dsv_read_reg(ctx, LSM6DSV_HAODR_CFG, (uint8_t *)&haodr, 1);
961 if (ret != 0)
962 {
963 return ret;
964 }
965
966 sel = haodr.haodr_sel;
967
968 switch (ctrl2.odr_g)
969 {
970 case LSM6DSV_ODR_OFF:
971 *val = LSM6DSV_ODR_OFF;
972 break;
973
974 case LSM6DSV_ODR_AT_1Hz875:
975 *val = LSM6DSV_ODR_AT_1Hz875;
976 break;
977
978 case LSM6DSV_ODR_AT_7Hz5:
979 *val = LSM6DSV_ODR_AT_7Hz5;
980 break;
981
982 case LSM6DSV_ODR_AT_15Hz:
983 switch (sel)
984 {
985 default:
986 case 0:
987 *val = LSM6DSV_ODR_AT_15Hz;
988 break;
989 case 1:
990 *val = LSM6DSV_ODR_HA01_AT_15Hz625;
991 break;
992 case 2:
993 *val = LSM6DSV_ODR_HA02_AT_12Hz5;
994 break;
995 }
996 break;
997
998 case LSM6DSV_ODR_AT_30Hz:
999 switch (sel)
1000 {
1001 default:
1002 case 0:
1003 *val = LSM6DSV_ODR_AT_30Hz;
1004 break;
1005 case 1:
1006 *val = LSM6DSV_ODR_HA01_AT_31Hz25;
1007 break;
1008 case 2:
1009 *val = LSM6DSV_ODR_HA02_AT_25Hz;
1010 break;
1011 }
1012 break;
1013
1014 case LSM6DSV_ODR_AT_60Hz:
1015 switch (sel)
1016 {
1017 default:
1018 case 0:
1019 *val = LSM6DSV_ODR_AT_60Hz;
1020 break;
1021 case 1:
1022 *val = LSM6DSV_ODR_HA01_AT_62Hz5;
1023 break;
1024 case 2:
1025 *val = LSM6DSV_ODR_HA02_AT_50Hz;
1026 break;
1027 }
1028 break;
1029
1030 case LSM6DSV_ODR_AT_120Hz:
1031 switch (sel)
1032 {
1033 default:
1034 case 0:
1035 *val = LSM6DSV_ODR_AT_120Hz;
1036 break;
1037 case 1:
1038 *val = LSM6DSV_ODR_HA01_AT_125Hz;
1039 break;
1040 case 2:
1041 *val = LSM6DSV_ODR_HA02_AT_100Hz;
1042 break;
1043 }
1044 break;
1045
1046 case LSM6DSV_ODR_AT_240Hz:
1047 switch (sel)
1048 {
1049 default:
1050 case 0:
1051 *val = LSM6DSV_ODR_AT_240Hz;
1052 break;
1053 case 1:
1054 *val = LSM6DSV_ODR_HA01_AT_250Hz;
1055 break;
1056 case 2:
1057 *val = LSM6DSV_ODR_HA02_AT_200Hz;
1058 break;
1059 }
1060 break;
1061
1062 case LSM6DSV_ODR_AT_480Hz:
1063 switch (sel)
1064 {
1065 default:
1066 case 0:
1067 *val = LSM6DSV_ODR_AT_480Hz;
1068 break;
1069 case 1:
1070 *val = LSM6DSV_ODR_HA01_AT_500Hz;
1071 break;
1072 case 2:
1073 *val = LSM6DSV_ODR_HA02_AT_400Hz;
1074 break;
1075 }
1076 break;
1077
1078 case LSM6DSV_ODR_AT_960Hz:
1079 switch (sel)
1080 {
1081 default:
1082 case 0:
1083 *val = LSM6DSV_ODR_AT_960Hz;
1084 break;
1085 case 1:
1086 *val = LSM6DSV_ODR_HA01_AT_1000Hz;
1087 break;
1088 case 2:
1089 *val = LSM6DSV_ODR_HA02_AT_800Hz;
1090 break;
1091 }
1092 break;
1093
1094 case LSM6DSV_ODR_AT_1920Hz:
1095 switch (sel)
1096 {
1097 default:
1098 case 0:
1099 *val = LSM6DSV_ODR_AT_1920Hz;
1100 break;
1101 case 1:
1102 *val = LSM6DSV_ODR_HA01_AT_2000Hz;
1103 break;
1104 case 2:
1105 *val = LSM6DSV_ODR_HA02_AT_1600Hz;
1106 break;
1107 }
1108 break;
1109
1110 case LSM6DSV_ODR_AT_3840Hz:
1111 switch (sel)
1112 {
1113 default:
1114 case 0:
1115 *val = LSM6DSV_ODR_AT_3840Hz;
1116 break;
1117 case 1:
1118 *val = LSM6DSV_ODR_HA01_AT_4000Hz;
1119 break;
1120 case 2:
1121 *val = LSM6DSV_ODR_HA02_AT_3200Hz;
1122 break;
1123 }
1124 break;
1125
1126 case LSM6DSV_ODR_AT_7680Hz:
1127 switch (sel)
1128 {
1129 default:
1130 case 0:
1131 *val = LSM6DSV_ODR_AT_7680Hz;
1132 break;
1133 case 1:
1134 *val = LSM6DSV_ODR_HA01_AT_8000Hz;
1135 break;
1136 case 2:
1137 *val = LSM6DSV_ODR_HA02_AT_6400Hz;
1138 break;
1139 }
1140 break;
1141
1142 default:
1143 *val = LSM6DSV_ODR_OFF;
1144 break;
1145 }
1146
1147 return ret;
1148 }
1149
1150 /**
1151 * @brief Gyroscope operating mode selection.[set]
1152 *
1153 * @param ctx read / write interface definitions
1154 * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURACY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD,
1155 * @retval interface status (MANDATORY: return 0 -> no Error)
1156 *
1157 */
lsm6dsv_gy_mode_set(const stmdev_ctx_t * ctx,lsm6dsv_gy_mode_t val)1158 int32_t lsm6dsv_gy_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_gy_mode_t val)
1159 {
1160 lsm6dsv_ctrl2_t ctrl2;
1161 int32_t ret;
1162
1163 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL2, (uint8_t *)&ctrl2, 1);
1164 if (ret == 0)
1165 {
1166 ctrl2.op_mode_g = (uint8_t)val & 0x07U;
1167 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL2, (uint8_t *)&ctrl2, 1);
1168 }
1169
1170 return ret;
1171 }
1172
1173 /**
1174 * @brief Gyroscope operating mode selection.[get]
1175 *
1176 * @param ctx read / write interface definitions
1177 * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURACY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD,
1178 * @retval interface status (MANDATORY: return 0 -> no Error)
1179 *
1180 */
lsm6dsv_gy_mode_get(const stmdev_ctx_t * ctx,lsm6dsv_gy_mode_t * val)1181 int32_t lsm6dsv_gy_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_gy_mode_t *val)
1182 {
1183 lsm6dsv_ctrl2_t ctrl2;
1184 int32_t ret;
1185
1186 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL2, (uint8_t *)&ctrl2, 1);
1187 if (ret != 0)
1188 {
1189 return ret;
1190 }
1191
1192 switch (ctrl2.op_mode_g)
1193 {
1194 case LSM6DSV_GY_HIGH_PERFORMANCE_MD:
1195 *val = LSM6DSV_GY_HIGH_PERFORMANCE_MD;
1196 break;
1197
1198 case LSM6DSV_GY_HIGH_ACCURACY_ODR_MD:
1199 *val = LSM6DSV_GY_HIGH_ACCURACY_ODR_MD;
1200 break;
1201
1202 case LSM6DSV_GY_SLEEP_MD:
1203 *val = LSM6DSV_GY_SLEEP_MD;
1204 break;
1205
1206 case LSM6DSV_GY_LOW_POWER_MD:
1207 *val = LSM6DSV_GY_LOW_POWER_MD;
1208 break;
1209
1210 default:
1211 *val = LSM6DSV_GY_HIGH_PERFORMANCE_MD;
1212 break;
1213 }
1214
1215 return ret;
1216 }
1217
1218 /**
1219 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set]
1220 *
1221 * @param ctx read / write interface definitions
1222 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
1223 * @retval interface status (MANDATORY: return 0 -> no Error)
1224 *
1225 */
lsm6dsv_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)1226 int32_t lsm6dsv_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
1227 {
1228 lsm6dsv_ctrl3_t ctrl3;
1229 int32_t ret;
1230
1231 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1);
1232 if (ret == 0)
1233 {
1234 ctrl3.if_inc = val;
1235 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1);
1236 }
1237
1238 return ret;
1239 }
1240
1241 /**
1242 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get]
1243 *
1244 * @param ctx read / write interface definitions
1245 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
1246 * @retval interface status (MANDATORY: return 0 -> no Error)
1247 *
1248 */
lsm6dsv_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)1249 int32_t lsm6dsv_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
1250 {
1251 lsm6dsv_ctrl3_t ctrl3;
1252 int32_t ret;
1253
1254 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1);
1255 *val = ctrl3.if_inc;
1256
1257 return ret;
1258 }
1259
1260 /**
1261 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set]
1262 *
1263 * @param ctx read / write interface definitions
1264 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
1265 * @retval interface status (MANDATORY: return 0 -> no Error)
1266 *
1267 */
lsm6dsv_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)1268 int32_t lsm6dsv_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
1269 {
1270 lsm6dsv_ctrl3_t ctrl3;
1271 int32_t ret;
1272
1273 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1);
1274
1275 if (ret == 0)
1276 {
1277 ctrl3.bdu = val;
1278 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1);
1279 }
1280
1281 return ret;
1282 }
1283
1284 /**
1285 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get]
1286 *
1287 * @param ctx read / write interface definitions
1288 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
1289 * @retval interface status (MANDATORY: return 0 -> no Error)
1290 *
1291 */
lsm6dsv_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)1292 int32_t lsm6dsv_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
1293 {
1294 lsm6dsv_ctrl3_t ctrl3;
1295 int32_t ret;
1296
1297 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL3, (uint8_t *)&ctrl3, 1);
1298 *val = ctrl3.bdu;
1299
1300 return ret;
1301 }
1302
1303 /**
1304 * @brief Configure ODR trigger. [set]
1305 *
1306 * @param ctx read / write interface definitions
1307 * @param val number of data in the reference period.
1308 * @retval interface status (MANDATORY: return 0 -> no Error)
1309 *
1310 */
lsm6dsv_odr_trig_cfg_set(const stmdev_ctx_t * ctx,uint8_t val)1311 int32_t lsm6dsv_odr_trig_cfg_set(const stmdev_ctx_t *ctx, uint8_t val)
1312 {
1313 lsm6dsv_odr_trig_cfg_t odr_trig;
1314 int32_t ret;
1315
1316 if (val >= 1U && val <= 3U)
1317 {
1318 return -1;
1319 }
1320
1321 ret = lsm6dsv_read_reg(ctx, LSM6DSV_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1);
1322
1323 if (ret == 0)
1324 {
1325 odr_trig.odr_trig_nodr = val;
1326 ret = lsm6dsv_write_reg(ctx, LSM6DSV_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1);
1327 }
1328
1329 return ret;
1330 }
1331
1332 /**
1333 * @brief Configure ODR trigger. [get]
1334 *
1335 * @param ctx read / write interface definitions
1336 * @param val number of data in the reference period.
1337 * @retval interface status (MANDATORY: return 0 -> no Error)
1338 *
1339 */
lsm6dsv_odr_trig_cfg_get(const stmdev_ctx_t * ctx,uint8_t * val)1340 int32_t lsm6dsv_odr_trig_cfg_get(const stmdev_ctx_t *ctx, uint8_t *val)
1341 {
1342 lsm6dsv_odr_trig_cfg_t odr_trig;
1343 int32_t ret;
1344
1345 ret = lsm6dsv_read_reg(ctx, LSM6DSV_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1);
1346 *val = odr_trig.odr_trig_nodr;
1347
1348 return ret;
1349 }
1350
1351 /**
1352 * @brief Enables pulsed data-ready mode (~75 us).[set]
1353 *
1354 * @param ctx read / write interface definitions
1355 * @param val DRDY_LATCHED, DRDY_PULSED,
1356 * @retval interface status (MANDATORY: return 0 -> no Error)
1357 *
1358 */
lsm6dsv_data_ready_mode_set(const stmdev_ctx_t * ctx,lsm6dsv_data_ready_mode_t val)1359 int32_t lsm6dsv_data_ready_mode_set(const stmdev_ctx_t *ctx,
1360 lsm6dsv_data_ready_mode_t val)
1361 {
1362 lsm6dsv_ctrl4_t ctrl4;
1363 int32_t ret;
1364
1365 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1);
1366
1367 if (ret == 0)
1368 {
1369 ctrl4.drdy_pulsed = (uint8_t)val & 0x1U;
1370 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1);
1371 }
1372
1373 return ret;
1374 }
1375
1376 /**
1377 * @brief Enables pulsed data-ready mode (~75 us).[get]
1378 *
1379 * @param ctx read / write interface definitions
1380 * @param val DRDY_LATCHED, DRDY_PULSED,
1381 * @retval interface status (MANDATORY: return 0 -> no Error)
1382 *
1383 */
lsm6dsv_data_ready_mode_get(const stmdev_ctx_t * ctx,lsm6dsv_data_ready_mode_t * val)1384 int32_t lsm6dsv_data_ready_mode_get(const stmdev_ctx_t *ctx,
1385 lsm6dsv_data_ready_mode_t *val)
1386 {
1387 lsm6dsv_ctrl4_t ctrl4;
1388 int32_t ret;
1389
1390 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1);
1391
1392 switch (ctrl4.drdy_pulsed)
1393 {
1394 case LSM6DSV_DRDY_LATCHED:
1395 *val = LSM6DSV_DRDY_LATCHED;
1396 break;
1397
1398 case LSM6DSV_DRDY_PULSED:
1399 *val = LSM6DSV_DRDY_PULSED;
1400 break;
1401
1402 default:
1403 *val = LSM6DSV_DRDY_LATCHED;
1404 break;
1405 }
1406
1407 return ret;
1408 }
1409
1410 /**
1411 * @brief Enables interrupt.[set]
1412 *
1413 * @param ctx read / write interface definitions
1414 * @param val enable/disable, latched/pulsed
1415 * @retval interface status (MANDATORY: return 0 -> no Error)
1416 *
1417 */
lsm6dsv_interrupt_enable_set(const stmdev_ctx_t * ctx,lsm6dsv_interrupt_mode_t val)1418 int32_t lsm6dsv_interrupt_enable_set(const stmdev_ctx_t *ctx,
1419 lsm6dsv_interrupt_mode_t val)
1420 {
1421 lsm6dsv_tap_cfg0_t cfg;
1422 lsm6dsv_functions_enable_t func;
1423 int32_t ret;
1424
1425 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&func, 1);
1426 func.interrupts_enable = val.enable;
1427 ret += lsm6dsv_write_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&func, 1);
1428 if (ret != 0)
1429 {
1430 return ret;
1431 }
1432
1433 ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&cfg, 1);
1434 cfg.lir = val.lir;
1435 ret += lsm6dsv_write_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&cfg, 1);
1436
1437 return ret;
1438 }
1439
1440 /**
1441 * @brief Enables latched interrupt mode.[get]
1442 *
1443 * @param ctx read / write interface definitions
1444 * @param val enable/disable, latched/pulsed
1445 * @retval interface status (MANDATORY: return 0 -> no Error)
1446 *
1447 */
lsm6dsv_interrupt_enable_get(const stmdev_ctx_t * ctx,lsm6dsv_interrupt_mode_t * val)1448 int32_t lsm6dsv_interrupt_enable_get(const stmdev_ctx_t *ctx,
1449 lsm6dsv_interrupt_mode_t *val)
1450 {
1451 lsm6dsv_tap_cfg0_t cfg;
1452 lsm6dsv_functions_enable_t func;
1453 int32_t ret;
1454
1455 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&func, 1);
1456 ret += lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&cfg, 1);
1457 if (ret != 0)
1458 {
1459 return ret;
1460 }
1461
1462 val->enable = func.interrupts_enable;
1463 val->lir = cfg.lir;
1464
1465 return ret;
1466 }
1467
1468 /**
1469 * @brief Gyroscope full-scale selection[set]
1470 *
1471 * @param ctx read / write interface definitions
1472 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
1473 * @retval interface status (MANDATORY: return 0 -> no Error)
1474 *
1475 */
lsm6dsv_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv_gy_full_scale_t val)1476 int32_t lsm6dsv_gy_full_scale_set(const stmdev_ctx_t *ctx,
1477 lsm6dsv_gy_full_scale_t val)
1478 {
1479 lsm6dsv_ctrl6_t ctrl6;
1480 int32_t ret;
1481
1482 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL6, (uint8_t *)&ctrl6, 1);
1483
1484 if (ret == 0)
1485 {
1486 ctrl6.fs_g = (uint8_t)val & 0xfu;
1487 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL6, (uint8_t *)&ctrl6, 1);
1488 }
1489
1490 return ret;
1491 }
1492
1493 /**
1494 * @brief Gyroscope full-scale selection[get]
1495 *
1496 * @param ctx read / write interface definitions
1497 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
1498 * @retval interface status (MANDATORY: return 0 -> no Error)
1499 *
1500 */
lsm6dsv_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv_gy_full_scale_t * val)1501 int32_t lsm6dsv_gy_full_scale_get(const stmdev_ctx_t *ctx,
1502 lsm6dsv_gy_full_scale_t *val)
1503 {
1504 lsm6dsv_ctrl6_t ctrl6;
1505 int32_t ret;
1506
1507 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL6, (uint8_t *)&ctrl6, 1);
1508 if (ret != 0)
1509 {
1510 return ret;
1511 }
1512
1513 switch (ctrl6.fs_g)
1514 {
1515 case LSM6DSV_125dps:
1516 *val = LSM6DSV_125dps;
1517 break;
1518
1519 case LSM6DSV_250dps:
1520 *val = LSM6DSV_250dps;
1521 break;
1522
1523 case LSM6DSV_500dps:
1524 *val = LSM6DSV_500dps;
1525 break;
1526
1527 case LSM6DSV_1000dps:
1528 *val = LSM6DSV_1000dps;
1529 break;
1530
1531 case LSM6DSV_2000dps:
1532 *val = LSM6DSV_2000dps;
1533 break;
1534
1535 case LSM6DSV_4000dps:
1536 *val = LSM6DSV_4000dps;
1537 break;
1538
1539 default:
1540 *val = LSM6DSV_125dps;
1541 break;
1542 }
1543
1544 return ret;
1545 }
1546
1547 /**
1548 * @brief Accelerometer full-scale selection.[set]
1549 *
1550 * @param ctx read / write interface definitions
1551 * @param val lsm6dsv_xl_full_scale_t
1552 * @retval interface status (MANDATORY: return 0 -> no Error)
1553 *
1554 */
lsm6dsv_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv_xl_full_scale_t val)1555 int32_t lsm6dsv_xl_full_scale_set(const stmdev_ctx_t *ctx,
1556 lsm6dsv_xl_full_scale_t val)
1557 {
1558 lsm6dsv_ctrl8_t ctrl8;
1559 int32_t ret;
1560
1561 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1);
1562
1563 if (ret == 0)
1564 {
1565 ctrl8.fs_xl = (uint8_t)val & 0x3U;
1566 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1);
1567 }
1568
1569 return ret;
1570 }
1571
1572 /**
1573 * @brief Accelerometer full-scale selection.[get]
1574 *
1575 * @param ctx read / write interface definitions
1576 * @param val lsm6dsv_xl_full_scale_t
1577 * @retval interface status (MANDATORY: return 0 -> no Error)
1578 *
1579 */
lsm6dsv_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv_xl_full_scale_t * val)1580 int32_t lsm6dsv_xl_full_scale_get(const stmdev_ctx_t *ctx,
1581 lsm6dsv_xl_full_scale_t *val)
1582 {
1583 lsm6dsv_ctrl8_t ctrl8;
1584 int32_t ret;
1585
1586 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1);
1587 if (ret != 0)
1588 {
1589 return ret;
1590 }
1591
1592 switch (ctrl8.fs_xl)
1593 {
1594 case LSM6DSV_2g:
1595 *val = LSM6DSV_2g;
1596 break;
1597
1598 case LSM6DSV_4g:
1599 *val = LSM6DSV_4g;
1600 break;
1601
1602 case LSM6DSV_8g:
1603 *val = LSM6DSV_8g;
1604 break;
1605
1606 case LSM6DSV_16g:
1607 *val = LSM6DSV_16g;
1608 break;
1609
1610 default:
1611 *val = LSM6DSV_2g;
1612 break;
1613 }
1614
1615 return ret;
1616 }
1617
1618 /**
1619 * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[set]
1620 *
1621 * @param ctx read / write interface definitions
1622 * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.
1623 * @retval interface status (MANDATORY: return 0 -> no Error)
1624 *
1625 */
lsm6dsv_xl_dual_channel_set(const stmdev_ctx_t * ctx,uint8_t val)1626 int32_t lsm6dsv_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val)
1627 {
1628 lsm6dsv_ctrl8_t ctrl8;
1629 int32_t ret;
1630
1631 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1);
1632
1633 if (ret == 0)
1634 {
1635 ctrl8.xl_dualc_en = val;
1636 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1);
1637 }
1638
1639 return ret;
1640 }
1641
1642 /**
1643 * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[get]
1644 *
1645 * @param ctx read / write interface definitions
1646 * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.
1647 * @retval interface status (MANDATORY: return 0 -> no Error)
1648 *
1649 */
lsm6dsv_xl_dual_channel_get(const stmdev_ctx_t * ctx,uint8_t * val)1650 int32_t lsm6dsv_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val)
1651 {
1652 lsm6dsv_ctrl8_t ctrl8;
1653 int32_t ret;
1654
1655 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1);
1656 *val = ctrl8.xl_dualc_en;
1657
1658 return ret;
1659 }
1660
1661 /**
1662 * @brief Accelerometer self-test selection.[set]
1663 *
1664 * @param ctx read / write interface definitions
1665 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1666 * @retval interface status (MANDATORY: return 0 -> no Error)
1667 *
1668 */
lsm6dsv_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6dsv_xl_self_test_t val)1669 int32_t lsm6dsv_xl_self_test_set(const stmdev_ctx_t *ctx,
1670 lsm6dsv_xl_self_test_t val)
1671 {
1672 lsm6dsv_ctrl10_t ctrl10;
1673 int32_t ret;
1674
1675 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1);
1676
1677 if (ret == 0)
1678 {
1679 ctrl10.st_xl = (uint8_t)val & 0x3U;
1680 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1);
1681 }
1682
1683 return ret;
1684 }
1685
1686 /**
1687 * @brief Accelerometer self-test selection.[get]
1688 *
1689 * @param ctx read / write interface definitions
1690 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1691 * @retval interface status (MANDATORY: return 0 -> no Error)
1692 *
1693 */
lsm6dsv_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6dsv_xl_self_test_t * val)1694 int32_t lsm6dsv_xl_self_test_get(const stmdev_ctx_t *ctx,
1695 lsm6dsv_xl_self_test_t *val)
1696 {
1697 lsm6dsv_ctrl10_t ctrl10;
1698 int32_t ret;
1699
1700 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1);
1701 if (ret != 0)
1702 {
1703 return ret;
1704 }
1705
1706 switch (ctrl10.st_xl)
1707 {
1708 case LSM6DSV_XL_ST_DISABLE:
1709 *val = LSM6DSV_XL_ST_DISABLE;
1710 break;
1711
1712 case LSM6DSV_XL_ST_POSITIVE:
1713 *val = LSM6DSV_XL_ST_POSITIVE;
1714 break;
1715
1716 case LSM6DSV_XL_ST_NEGATIVE:
1717 *val = LSM6DSV_XL_ST_NEGATIVE;
1718 break;
1719
1720 default:
1721 *val = LSM6DSV_XL_ST_DISABLE;
1722 break;
1723 }
1724
1725 return ret;
1726 }
1727
1728 /**
1729 * @brief Gyroscope self-test selection.[set]
1730 *
1731 * @param ctx read / write interface definitions
1732 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1733 * @retval interface status (MANDATORY: return 0 -> no Error)
1734 *
1735 */
lsm6dsv_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dsv_gy_self_test_t val)1736 int32_t lsm6dsv_gy_self_test_set(const stmdev_ctx_t *ctx,
1737 lsm6dsv_gy_self_test_t val)
1738 {
1739 lsm6dsv_ctrl10_t ctrl10;
1740 int32_t ret;
1741
1742 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1);
1743
1744 if (ret == 0)
1745 {
1746 ctrl10.st_g = (uint8_t)val & 0x3U;
1747 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1);
1748 }
1749
1750 return ret;
1751 }
1752
1753 /**
1754 * @brief Gyroscope self-test selection.[get]
1755 *
1756 * @param ctx read / write interface definitions
1757 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1758 * @retval interface status (MANDATORY: return 0 -> no Error)
1759 *
1760 */
lsm6dsv_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dsv_gy_self_test_t * val)1761 int32_t lsm6dsv_gy_self_test_get(const stmdev_ctx_t *ctx,
1762 lsm6dsv_gy_self_test_t *val)
1763 {
1764 lsm6dsv_ctrl10_t ctrl10;
1765 int32_t ret;
1766
1767 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1);
1768 if (ret != 0)
1769 {
1770 return ret;
1771 }
1772
1773 switch (ctrl10.st_g)
1774 {
1775 case LSM6DSV_GY_ST_DISABLE:
1776 *val = LSM6DSV_GY_ST_DISABLE;
1777 break;
1778
1779 case LSM6DSV_GY_ST_POSITIVE:
1780 *val = LSM6DSV_GY_ST_POSITIVE;
1781 break;
1782
1783 case LSM6DSV_GY_ST_NEGATIVE:
1784 *val = LSM6DSV_GY_ST_NEGATIVE;
1785 break;
1786
1787 default:
1788 *val = LSM6DSV_GY_ST_DISABLE;
1789 break;
1790 }
1791
1792 return ret;
1793 }
1794
1795 /**
1796 * @brief SPI2 Accelerometer self-test selection.[set]
1797 *
1798 * @param ctx read / write interface definitions
1799 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1800 * @retval interface status (MANDATORY: return 0 -> no Error)
1801 *
1802 */
lsm6dsv_ois_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6dsv_ois_xl_self_test_t val)1803 int32_t lsm6dsv_ois_xl_self_test_set(const stmdev_ctx_t *ctx,
1804 lsm6dsv_ois_xl_self_test_t val)
1805 {
1806 lsm6dsv_spi2_int_ois_t spi2_int_ois;
1807 int32_t ret;
1808
1809 ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1810
1811 if (ret == 0)
1812 {
1813 spi2_int_ois.st_xl_ois = ((uint8_t)val & 0x3U);
1814 ret = lsm6dsv_write_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1815 }
1816
1817 return ret;
1818 }
1819
1820 /**
1821 * @brief SPI2 Accelerometer self-test selection.[get]
1822 *
1823 * @param ctx read / write interface definitions
1824 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1825 * @retval interface status (MANDATORY: return 0 -> no Error)
1826 *
1827 */
lsm6dsv_ois_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6dsv_ois_xl_self_test_t * val)1828 int32_t lsm6dsv_ois_xl_self_test_get(const stmdev_ctx_t *ctx,
1829 lsm6dsv_ois_xl_self_test_t *val)
1830 {
1831 lsm6dsv_spi2_int_ois_t spi2_int_ois;
1832 int32_t ret;
1833
1834 ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1835 if (ret != 0)
1836 {
1837 return ret;
1838 }
1839
1840 switch (spi2_int_ois.st_xl_ois)
1841 {
1842 case LSM6DSV_OIS_XL_ST_DISABLE:
1843 *val = LSM6DSV_OIS_XL_ST_DISABLE;
1844 break;
1845
1846 case LSM6DSV_OIS_XL_ST_POSITIVE:
1847 *val = LSM6DSV_OIS_XL_ST_POSITIVE;
1848 break;
1849
1850 case LSM6DSV_OIS_XL_ST_NEGATIVE:
1851 *val = LSM6DSV_OIS_XL_ST_NEGATIVE;
1852 break;
1853
1854 default:
1855 *val = LSM6DSV_OIS_XL_ST_DISABLE;
1856 break;
1857 }
1858
1859 return ret;
1860 }
1861
1862 /**
1863 * @brief SPI2 Accelerometer self-test selection.[set]
1864 *
1865 * @param ctx read / write interface definitions
1866 * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, LSM6DSV_OIS_GY_ST_CLAMP_POS, LSM6DSV_OIS_GY_ST_CLAMP_NEG
1867 * @retval interface status (MANDATORY: return 0 -> no Error)
1868 *
1869 */
lsm6dsv_ois_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dsv_ois_gy_self_test_t val)1870 int32_t lsm6dsv_ois_gy_self_test_set(const stmdev_ctx_t *ctx,
1871 lsm6dsv_ois_gy_self_test_t val)
1872 {
1873 lsm6dsv_spi2_int_ois_t spi2_int_ois;
1874 int32_t ret;
1875
1876 ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1877
1878 if (ret == 0)
1879 {
1880 spi2_int_ois.st_g_ois = ((uint8_t)val & 0x3U);
1881 spi2_int_ois.st_ois_clampdis = ((uint8_t)val & 0x04U) >> 2;
1882 ret = lsm6dsv_write_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1883 }
1884
1885 return ret;
1886 }
1887
1888 /**
1889 * @brief SPI2 Accelerometer self-test selection.[get]
1890 *
1891 * @param ctx read / write interface definitions
1892 * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, LSM6DSV_OIS_GY_ST_CLAMP_POS, LSM6DSV_OIS_GY_ST_CLAMP_NEG
1893 * @retval interface status (MANDATORY: return 0 -> no Error)
1894 *
1895 */
lsm6dsv_ois_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dsv_ois_gy_self_test_t * val)1896 int32_t lsm6dsv_ois_gy_self_test_get(const stmdev_ctx_t *ctx,
1897 lsm6dsv_ois_gy_self_test_t *val)
1898 {
1899 lsm6dsv_spi2_int_ois_t spi2_int_ois;
1900 int32_t ret;
1901
1902 ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1903 if (ret != 0)
1904 {
1905 return ret;
1906 }
1907
1908 switch (spi2_int_ois.st_g_ois)
1909 {
1910 case LSM6DSV_OIS_GY_ST_DISABLE:
1911 *val = LSM6DSV_OIS_GY_ST_DISABLE;
1912 break;
1913
1914 case LSM6DSV_OIS_GY_ST_POSITIVE:
1915 *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV_OIS_GY_ST_CLAMP_POS :
1916 LSM6DSV_OIS_GY_ST_POSITIVE;
1917 break;
1918
1919 case LSM6DSV_OIS_GY_ST_NEGATIVE:
1920 *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV_OIS_GY_ST_CLAMP_NEG :
1921 LSM6DSV_OIS_GY_ST_NEGATIVE;
1922 break;
1923
1924 default:
1925 *val = LSM6DSV_OIS_GY_ST_DISABLE;
1926 break;
1927 }
1928
1929 return ret;
1930 }
1931
1932 /**
1933 * @defgroup interrupt_pins
1934 * @brief This section groups all the functions that manage
1935 * interrupt pins
1936 * @{
1937 *
1938 */
1939
1940 /**
1941 * @brief Select the signal that need to route on int1 pad[set]
1942 *
1943 * @param ctx Read / write interface definitions.(ptr)
1944 * @param val the signals to route on int1 pin.
1945 * @retval Interface status (MANDATORY: return 0 -> no Error).
1946 *
1947 */
lsm6dsv_pin_int1_route_set(const stmdev_ctx_t * ctx,lsm6dsv_pin_int_route_t * val)1948 int32_t lsm6dsv_pin_int1_route_set(const stmdev_ctx_t *ctx,
1949 lsm6dsv_pin_int_route_t *val)
1950 {
1951 lsm6dsv_int1_ctrl_t int1_ctrl;
1952 lsm6dsv_md1_cfg_t md1_cfg;
1953 int32_t ret;
1954
1955 /* not available on INT1 */
1956 if (val->drdy_temp == 1)
1957 {
1958 return -1;
1959 }
1960
1961 ret = lsm6dsv_read_reg(ctx, LSM6DSV_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
1962 if (ret != 0)
1963 {
1964 return ret;
1965 }
1966
1967 int1_ctrl.int1_drdy_xl = val->drdy_xl;
1968 int1_ctrl.int1_drdy_g = val->drdy_g;
1969 int1_ctrl.int1_fifo_th = val->fifo_th;
1970 int1_ctrl.int1_fifo_ovr = val->fifo_ovr;
1971 int1_ctrl.int1_fifo_full = val->fifo_full;
1972 int1_ctrl.int1_cnt_bdr = val->cnt_bdr;
1973
1974 ret = lsm6dsv_write_reg(ctx, LSM6DSV_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
1975 if (ret != 0)
1976 {
1977 return ret;
1978 }
1979
1980 ret = lsm6dsv_read_reg(ctx, LSM6DSV_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1981 if (ret != 0)
1982 {
1983 return ret;
1984 }
1985
1986 md1_cfg.int1_shub = val->shub;
1987 md1_cfg.int1_emb_func = val->emb_func;
1988 md1_cfg.int1_6d = val->sixd;
1989 md1_cfg.int1_single_tap = val->single_tap;
1990 md1_cfg.int1_double_tap = val->double_tap;
1991 md1_cfg.int1_wu = val->wakeup;
1992 md1_cfg.int1_ff = val->freefall;
1993 md1_cfg.int1_sleep_change = val->sleep_change;
1994
1995 ret = lsm6dsv_write_reg(ctx, LSM6DSV_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1996
1997 return ret;
1998 }
1999
2000 /**
2001 * @brief Select the signal that need to route on int1 pad.[get]
2002 *
2003 * @param ctx Read / write interface definitions.(ptr)
2004 * @param val the signals that are routed on int1 pin.(ptr)
2005 * @retval Interface status (MANDATORY: return 0 -> no Error).
2006 *
2007 */
lsm6dsv_pin_int1_route_get(const stmdev_ctx_t * ctx,lsm6dsv_pin_int_route_t * val)2008 int32_t lsm6dsv_pin_int1_route_get(const stmdev_ctx_t *ctx,
2009 lsm6dsv_pin_int_route_t *val)
2010 {
2011 lsm6dsv_int1_ctrl_t int1_ctrl;
2012 lsm6dsv_md1_cfg_t md1_cfg;
2013 int32_t ret;
2014
2015 ret = lsm6dsv_read_reg(ctx, LSM6DSV_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
2016 if (ret != 0)
2017 {
2018 return ret;
2019 }
2020
2021 val->drdy_xl = int1_ctrl.int1_drdy_xl;
2022 val->drdy_g = int1_ctrl.int1_drdy_g;
2023 val->fifo_th = int1_ctrl.int1_fifo_th;
2024 val->fifo_ovr = int1_ctrl.int1_fifo_ovr;
2025 val->fifo_full = int1_ctrl.int1_fifo_full;
2026 val->cnt_bdr = int1_ctrl.int1_cnt_bdr;
2027
2028 ret = lsm6dsv_read_reg(ctx, LSM6DSV_MD1_CFG, (uint8_t *)&md1_cfg, 1);
2029 if (ret != 0)
2030 {
2031 return ret;
2032 }
2033
2034 val->shub = md1_cfg.int1_shub;
2035 val->emb_func = md1_cfg.int1_emb_func;
2036 val->sixd = md1_cfg.int1_6d;
2037 val->single_tap = md1_cfg.int1_single_tap;
2038 val->double_tap = md1_cfg.int1_double_tap;
2039 val->wakeup = md1_cfg.int1_wu;
2040 val->freefall = md1_cfg.int1_ff;
2041 val->sleep_change = md1_cfg.int1_sleep_change;
2042
2043 return ret;
2044 }
2045
2046 /**
2047 * @brief Select the signal that need to route on int2 pad[set]
2048 *
2049 * @param ctx Read / write interface definitions.(ptr)
2050 * @param val the signals to route on int2 pin.
2051 * @retval Interface status (MANDATORY: return 0 -> no Error).
2052 *
2053 */
lsm6dsv_pin_int2_route_set(const stmdev_ctx_t * ctx,lsm6dsv_pin_int_route_t * val)2054 int32_t lsm6dsv_pin_int2_route_set(const stmdev_ctx_t *ctx,
2055 lsm6dsv_pin_int_route_t *val)
2056 {
2057 lsm6dsv_int2_ctrl_t int2_ctrl;
2058 lsm6dsv_ctrl4_t ctrl4;
2059 lsm6dsv_md2_cfg_t md2_cfg;
2060 int32_t ret;
2061
2062 ret = lsm6dsv_read_reg(ctx, LSM6DSV_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2063 if (ret != 0)
2064 {
2065 return ret;
2066 }
2067
2068 int2_ctrl.int2_drdy_xl = val->drdy_xl;
2069 int2_ctrl.int2_drdy_g = val->drdy_g;
2070 int2_ctrl.int2_fifo_th = val->fifo_th;
2071 int2_ctrl.int2_fifo_ovr = val->fifo_ovr;
2072 int2_ctrl.int2_fifo_full = val->fifo_full;
2073 int2_ctrl.int2_cnt_bdr = val->cnt_bdr;
2074 int2_ctrl.int2_drdy_g_eis = val->drdy_g_eis;
2075 int2_ctrl.int2_emb_func_endop = val->emb_func_endop;
2076
2077 ret = lsm6dsv_write_reg(ctx, LSM6DSV_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2078 if (ret != 0)
2079 {
2080 return ret;
2081 }
2082
2083 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1);
2084 ctrl4.int2_drdy_temp = val->drdy_temp;
2085 ret += lsm6dsv_write_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1);
2086 if (ret != 0)
2087 {
2088 return ret;
2089 }
2090
2091 ret = lsm6dsv_read_reg(ctx, LSM6DSV_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2092 if (ret != 0)
2093 {
2094 return ret;
2095 }
2096
2097 md2_cfg.int2_timestamp = val->timestamp;
2098 md2_cfg.int2_emb_func = val->emb_func;
2099 md2_cfg.int2_6d = val->sixd;
2100 md2_cfg.int2_single_tap = val->single_tap;
2101 md2_cfg.int2_double_tap = val->double_tap;
2102 md2_cfg.int2_wu = val->wakeup;
2103 md2_cfg.int2_ff = val->freefall;
2104 md2_cfg.int2_sleep_change = val->sleep_change;
2105
2106 ret = lsm6dsv_write_reg(ctx, LSM6DSV_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2107
2108 return ret;
2109 }
2110
2111 /**
2112 * @brief Select the signal that need to route on int2 pad.[get]
2113 *
2114 * @param ctx Read / write interface definitions.(ptr)
2115 * @param val the signals that are routed on int2 pin.(ptr)
2116 * @retval Interface status (MANDATORY: return 0 -> no Error).
2117 *
2118 */
lsm6dsv_pin_int2_route_get(const stmdev_ctx_t * ctx,lsm6dsv_pin_int_route_t * val)2119 int32_t lsm6dsv_pin_int2_route_get(const stmdev_ctx_t *ctx,
2120 lsm6dsv_pin_int_route_t *val)
2121 {
2122 lsm6dsv_int2_ctrl_t int2_ctrl;
2123 lsm6dsv_ctrl4_t ctrl4;
2124 lsm6dsv_md2_cfg_t md2_cfg;
2125 int32_t ret;
2126
2127 ret = lsm6dsv_read_reg(ctx, LSM6DSV_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2128 if (ret != 0)
2129 {
2130 return ret;
2131 }
2132
2133 val->drdy_xl = int2_ctrl.int2_drdy_xl;
2134 val->drdy_g = int2_ctrl.int2_drdy_g;
2135 val->fifo_th = int2_ctrl.int2_fifo_th;
2136 val->fifo_ovr = int2_ctrl.int2_fifo_ovr;
2137 val->fifo_full = int2_ctrl.int2_fifo_full;
2138 val->cnt_bdr = int2_ctrl.int2_cnt_bdr;
2139 val->drdy_g_eis = int2_ctrl.int2_drdy_g_eis;
2140 val->emb_func_endop = int2_ctrl.int2_emb_func_endop;
2141
2142 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1);
2143 if (ret != 0)
2144 {
2145 return ret;
2146 }
2147
2148 val->drdy_temp = ctrl4.int2_drdy_temp;
2149
2150 ret = lsm6dsv_read_reg(ctx, LSM6DSV_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2151 if (ret != 0)
2152 {
2153 return ret;
2154 }
2155
2156 val->timestamp = md2_cfg.int2_timestamp;
2157 val->emb_func = md2_cfg.int2_emb_func;
2158 val->sixd = md2_cfg.int2_6d;
2159 val->single_tap = md2_cfg.int2_single_tap;
2160 val->double_tap = md2_cfg.int2_double_tap;
2161 val->wakeup = md2_cfg.int2_wu;
2162 val->freefall = md2_cfg.int2_ff;
2163 val->sleep_change = md2_cfg.int2_sleep_change;
2164
2165 return ret;
2166 }
2167
2168 /**
2169 * @brief routes embedded func interrupt signals on INT 1 pin.[set]
2170 *
2171 * @param ctx read / write interface definitions
2172 * @param val routes embedded func interrupt signals on INT 1 pin.
2173 * @retval interface status (MANDATORY: return 0 -> no Error)
2174 *
2175 */
lsm6dsv_emb_pin_int1_route_set(const stmdev_ctx_t * ctx,const lsm6dsv_emb_pin_int_route_t * val)2176 int32_t lsm6dsv_emb_pin_int1_route_set(const stmdev_ctx_t *ctx,
2177 const lsm6dsv_emb_pin_int_route_t *val)
2178 {
2179 lsm6dsv_emb_func_int1_t emb_func_int1;
2180 lsm6dsv_md1_cfg_t md1_cfg;
2181 int32_t ret;
2182
2183 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
2184 if (ret == 0)
2185 {
2186 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
2187 }
2188
2189 if (ret == 0)
2190 {
2191 emb_func_int1.int1_tilt = val->tilt;
2192 emb_func_int1.int1_sig_mot = val->sig_mot;
2193 emb_func_int1.int1_step_detector = val->step_det;
2194 emb_func_int1.int1_fsm_lc = val->fsm_lc;
2195
2196 ret = lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
2197 }
2198 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
2199
2200 ret += lsm6dsv_read_reg(ctx, LSM6DSV_MD1_CFG, (uint8_t *)&md1_cfg, 1);
2201 if (ret == 0)
2202 {
2203 md1_cfg.int1_emb_func = 1;
2204 ret = lsm6dsv_write_reg(ctx, LSM6DSV_MD1_CFG, (uint8_t *)&md1_cfg, 1);
2205 }
2206
2207 return ret;
2208 }
2209
2210 /**
2211 * @brief routes embedded func interrupt signals on INT 1 pin.[get]
2212 *
2213 * @param ctx read / write interface definitions
2214 * @param val routes embedded func interrupt signals on INT 1 pin.
2215 * @retval interface status (MANDATORY: return 0 -> no Error)
2216 *
2217 */
lsm6dsv_emb_pin_int1_route_get(const stmdev_ctx_t * ctx,lsm6dsv_emb_pin_int_route_t * val)2218 int32_t lsm6dsv_emb_pin_int1_route_get(const stmdev_ctx_t *ctx,
2219 lsm6dsv_emb_pin_int_route_t *val)
2220 {
2221 lsm6dsv_emb_func_int1_t emb_func_int1;
2222 int32_t ret;
2223
2224 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
2225 if (ret == 0)
2226 {
2227 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
2228 }
2229
2230 if (ret == 0)
2231 {
2232 val->tilt = emb_func_int1.int1_tilt;
2233 val->sig_mot = emb_func_int1.int1_sig_mot;
2234 val->step_det = emb_func_int1.int1_step_detector;
2235 val->fsm_lc = emb_func_int1.int1_fsm_lc;
2236 }
2237 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
2238
2239 return ret;
2240 }
2241
2242 /**
2243 * @brief routes embedded func interrupt signals on INT 2 pin.[set]
2244 *
2245 * @param ctx read / write interface definitions
2246 * @param val routes embedded func interrupt signals on INT 2 pin.
2247 * @retval interface status (MANDATORY: return 0 -> no Error)
2248 *
2249 */
lsm6dsv_emb_pin_int2_route_set(const stmdev_ctx_t * ctx,const lsm6dsv_emb_pin_int_route_t * val)2250 int32_t lsm6dsv_emb_pin_int2_route_set(const stmdev_ctx_t *ctx,
2251 const lsm6dsv_emb_pin_int_route_t *val)
2252 {
2253 lsm6dsv_emb_func_int2_t emb_func_int2;
2254 lsm6dsv_md2_cfg_t md2_cfg;
2255 int32_t ret;
2256
2257 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
2258 if (ret == 0)
2259 {
2260 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
2261 }
2262
2263 if (ret == 0)
2264 {
2265 emb_func_int2.int2_tilt = val->tilt;
2266 emb_func_int2.int2_sig_mot = val->sig_mot;
2267 emb_func_int2.int2_step_detector = val->step_det;
2268 emb_func_int2.int2_fsm_lc = val->fsm_lc;
2269
2270 ret = lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
2271 }
2272 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
2273
2274 ret += lsm6dsv_read_reg(ctx, LSM6DSV_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2275 if (ret == 0)
2276 {
2277 md2_cfg.int2_emb_func = 1;
2278 ret = lsm6dsv_write_reg(ctx, LSM6DSV_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2279 }
2280
2281 return ret;
2282 }
2283
2284 /**
2285 * @brief routes embedded func interrupt signals on INT 2 pin.[get]
2286 *
2287 * @param ctx read / write interface definitions
2288 * @param val routes embedded func interrupt signals on INT 2 pin.
2289 * @retval interface status (MANDATORY: return 0 -> no Error)
2290 *
2291 */
lsm6dsv_emb_pin_int2_route_get(const stmdev_ctx_t * ctx,lsm6dsv_emb_pin_int_route_t * val)2292 int32_t lsm6dsv_emb_pin_int2_route_get(const stmdev_ctx_t *ctx,
2293 lsm6dsv_emb_pin_int_route_t *val)
2294 {
2295 lsm6dsv_emb_func_int2_t emb_func_int2;
2296 int32_t ret;
2297
2298 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
2299 if (ret == 0)
2300 {
2301 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
2302 }
2303
2304 if (ret == 0)
2305 {
2306 val->tilt = emb_func_int2.int2_tilt;
2307 val->sig_mot = emb_func_int2.int2_sig_mot;
2308 val->step_det = emb_func_int2.int2_step_detector;
2309 val->fsm_lc = emb_func_int2.int2_fsm_lc;
2310 }
2311 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
2312
2313 return ret;
2314 }
2315
2316 /**
2317 * @brief Embedded Interrupt configuration mode.[set]
2318 *
2319 * @param ctx read / write interface definitions
2320 * @param val INT_PULSED, INT_LATCHED
2321 * @retval interface status (MANDATORY: return 0 -> no Error)
2322 *
2323 */
lsm6dsv_embedded_int_cfg_set(const stmdev_ctx_t * ctx,lsm6dsv_embedded_int_config_t val)2324 int32_t lsm6dsv_embedded_int_cfg_set(const stmdev_ctx_t *ctx, lsm6dsv_embedded_int_config_t val)
2325 {
2326 lsm6dsv_page_rw_t page_rw;
2327 int32_t ret;
2328
2329 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
2330 if (ret == 0)
2331 {
2332 ret = lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1);
2333
2334 switch (val)
2335 {
2336 case LSM6DSV_INT_LATCH_DISABLE:
2337 page_rw.emb_func_lir = 0;
2338 break;
2339
2340 case LSM6DSV_INT_LATCH_ENABLE:
2341 default:
2342 page_rw.emb_func_lir = 1;
2343 break;
2344 }
2345
2346 ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1);
2347 }
2348
2349 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
2350
2351 return ret;
2352 }
2353
2354 /**
2355 * @brief Interrupt configuration mode.[get]
2356 *
2357 * @param ctx read / write interface definitions
2358 * @param val INT_DISABLED, INT_PULSED, INT_LATCHED
2359 * @retval interface status (MANDATORY: return 0 -> no Error)
2360 *
2361 */
lsm6dsv_embedded_int_cfg_get(const stmdev_ctx_t * ctx,lsm6dsv_embedded_int_config_t * val)2362 int32_t lsm6dsv_embedded_int_cfg_get(const stmdev_ctx_t *ctx,
2363 lsm6dsv_embedded_int_config_t *val)
2364 {
2365 lsm6dsv_page_rw_t page_rw;
2366 int32_t ret;
2367
2368 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
2369 if (ret == 0)
2370 {
2371 ret = lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1);
2372
2373 if (page_rw.emb_func_lir == 0U)
2374 {
2375 *val = LSM6DSV_INT_LATCH_DISABLE;
2376 }
2377 else
2378 {
2379 *val = LSM6DSV_INT_LATCH_ENABLE;
2380 }
2381 }
2382
2383 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
2384
2385 return ret;
2386 }
2387
2388 /**
2389 * @brief Get the status of embedded functions.[get]
2390 *
2391 * @param ctx read / write interface definitions
2392 * @param val lsm6dsv_embedded_status_t ptr
2393 * @retval interface status (MANDATORY: return 0 -> no Error)
2394 *
2395 */
lsm6dsv_embedded_status_get(const stmdev_ctx_t * ctx,lsm6dsv_embedded_status_t * val)2396 int32_t lsm6dsv_embedded_status_get(const stmdev_ctx_t *ctx,
2397 lsm6dsv_embedded_status_t *val)
2398 {
2399 lsm6dsv_emb_func_status_mainpage_t emb_func_status;
2400 lsm6dsv_emb_func_src_t emb_func_src;
2401 int32_t ret;
2402
2403 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_STATUS_MAINPAGE, (uint8_t *)&emb_func_status, 1);
2404 if (ret != 0)
2405 {
2406 return ret;
2407 }
2408
2409 val->step_detector = emb_func_status.is_step_det;
2410 val->tilt = emb_func_status.is_tilt;
2411 val->sig_mot = emb_func_status.is_sigmot;
2412 val->fsm_lc = emb_func_status.is_fsm_lc;
2413
2414 /* embedded func */
2415 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
2416 ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
2417 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
2418 if (ret != 0)
2419 {
2420 return ret;
2421 }
2422
2423 val->step_count_inc = emb_func_src.stepcounter_bit_set;
2424 val->step_count_overflow = emb_func_src.step_overflow;
2425 val->step_on_delta_time = emb_func_src.step_count_delta_ia;
2426 val->step_detector = emb_func_src.step_detected;
2427
2428 return ret;
2429 }
2430
2431 /**
2432 * @}
2433 *
2434 */
2435
2436 /**
2437 * @brief Get the status of all the interrupt sources.[get]
2438 *
2439 * @param ctx read / write interface definitions
2440 * @param val Get the status of all the interrupt sources.
2441 * @retval interface status (MANDATORY: return 0 -> no Error)
2442 *
2443 */
lsm6dsv_all_sources_get(const stmdev_ctx_t * ctx,lsm6dsv_all_sources_t * val)2444 int32_t lsm6dsv_all_sources_get(const stmdev_ctx_t *ctx,
2445 lsm6dsv_all_sources_t *val)
2446 {
2447 lsm6dsv_emb_func_status_mainpage_t emb_func_status_mainpage;
2448 lsm6dsv_emb_func_exec_status_t emb_func_exec_status;
2449 lsm6dsv_fsm_status_mainpage_t fsm_status_mainpage;
2450 lsm6dsv_functions_enable_t functions_enable;
2451 lsm6dsv_emb_func_src_t emb_func_src;
2452 lsm6dsv_fifo_status2_t fifo_status2;
2453 lsm6dsv_all_int_src_t all_int_src;
2454 lsm6dsv_wake_up_src_t wake_up_src;
2455 lsm6dsv_status_reg_t status_reg;
2456 lsm6dsv_d6d_src_t d6d_src;
2457 lsm6dsv_tap_src_t tap_src;
2458 lsm6dsv_ui_status_reg_ois_t status_reg_ois;
2459 lsm6dsv_status_master_t status_shub;
2460 uint8_t buff[8];
2461 int32_t ret;
2462
2463 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
2464 functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE;
2465 ret += lsm6dsv_write_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
2466 if (ret != 0)
2467 {
2468 return ret;
2469 }
2470
2471 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_STATUS1, (uint8_t *)&buff, 4);
2472 if (ret != 0)
2473 {
2474 return ret;
2475 }
2476
2477 bytecpy((uint8_t *)&fifo_status2, &buff[1]);
2478 bytecpy((uint8_t *)&all_int_src, &buff[2]);
2479 bytecpy((uint8_t *)&status_reg, &buff[3]);
2480
2481 val->fifo_ovr = fifo_status2.fifo_ovr_ia;
2482 val->fifo_bdr = fifo_status2.counter_bdr_ia;
2483 val->fifo_full = fifo_status2.fifo_full_ia;
2484 val->fifo_th = fifo_status2.fifo_wtm_ia;
2485
2486 val->free_fall = all_int_src.ff_ia;
2487 val->wake_up = all_int_src.wu_ia;
2488 val->six_d = all_int_src.d6d_ia;
2489
2490 val->drdy_xl = status_reg.xlda;
2491 val->drdy_gy = status_reg.gda;
2492 val->drdy_temp = status_reg.tda;
2493 val->drdy_eis = status_reg.gda_eis;
2494 val->drdy_ois = status_reg.ois_drdy;
2495 val->timestamp = status_reg.timestamp_endcount;
2496
2497 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
2498 functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE;
2499 ret += lsm6dsv_write_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
2500 if (ret != 0)
2501 {
2502 return ret;
2503 }
2504
2505 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_STATUS_REG_OIS, (uint8_t *)&buff, 8);
2506 if (ret != 0)
2507 {
2508 return ret;
2509 }
2510
2511 bytecpy((uint8_t *)&status_reg_ois, &buff[0]);
2512 bytecpy((uint8_t *)&wake_up_src, &buff[1]);
2513 bytecpy((uint8_t *)&tap_src, &buff[2]);
2514 bytecpy((uint8_t *)&d6d_src, &buff[3]);
2515 bytecpy((uint8_t *)&emb_func_status_mainpage, &buff[5]);
2516 bytecpy((uint8_t *)&fsm_status_mainpage, &buff[6]);
2517
2518 val->gy_settling = status_reg_ois.gyro_settling;
2519 val->sleep_change = wake_up_src.sleep_change_ia;
2520 val->wake_up_x = wake_up_src.x_wu;
2521 val->wake_up_y = wake_up_src.y_wu;
2522 val->wake_up_z = wake_up_src.z_wu;
2523 val->sleep_state = wake_up_src.sleep_state;
2524
2525 val->tap_x = tap_src.x_tap;
2526 val->tap_y = tap_src.y_tap;
2527 val->tap_z = tap_src.z_tap;
2528 val->tap_sign = tap_src.tap_sign;
2529 val->double_tap = tap_src.double_tap;
2530 val->single_tap = tap_src.single_tap;
2531
2532 val->six_d_zl = d6d_src.zl;
2533 val->six_d_zh = d6d_src.zh;
2534 val->six_d_yl = d6d_src.yl;
2535 val->six_d_yh = d6d_src.yh;
2536 val->six_d_xl = d6d_src.xl;
2537 val->six_d_xh = d6d_src.xh;
2538
2539 val->step_detector = emb_func_status_mainpage.is_step_det;
2540 val->tilt = emb_func_status_mainpage.is_tilt;
2541 val->sig_mot = emb_func_status_mainpage.is_sigmot;
2542 val->fsm_lc = emb_func_status_mainpage.is_fsm_lc;
2543
2544 val->fsm1 = fsm_status_mainpage.is_fsm1;
2545 val->fsm2 = fsm_status_mainpage.is_fsm2;
2546 val->fsm3 = fsm_status_mainpage.is_fsm3;
2547 val->fsm4 = fsm_status_mainpage.is_fsm4;
2548 val->fsm5 = fsm_status_mainpage.is_fsm5;
2549 val->fsm6 = fsm_status_mainpage.is_fsm6;
2550 val->fsm7 = fsm_status_mainpage.is_fsm7;
2551 val->fsm8 = fsm_status_mainpage.is_fsm8;
2552
2553 /* embedded func */
2554 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
2555 ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, 1);
2556 ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
2557 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
2558 if (ret != 0)
2559 {
2560 return ret;
2561 }
2562
2563 val->emb_func_stand_by = emb_func_exec_status.emb_func_endop;
2564 val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr;
2565 val->step_count_inc = emb_func_src.stepcounter_bit_set;
2566 val->step_count_overflow = emb_func_src.step_overflow;
2567 val->step_on_delta_time = emb_func_src.step_count_delta_ia;
2568
2569 val->step_detector = emb_func_src.step_detected;
2570
2571 /* sensor hub */
2572 ret = lsm6dsv_read_reg(ctx, LSM6DSV_STATUS_MASTER_MAINPAGE, (uint8_t *)&status_shub, 1);
2573 if (ret != 0)
2574 {
2575 return ret;
2576 }
2577
2578 val->sh_endop = status_shub.sens_hub_endop;
2579 val->sh_wr_once = status_shub.wr_once_done;
2580 val->sh_slave3_nack = status_shub.slave3_nack;
2581 val->sh_slave2_nack = status_shub.slave2_nack;
2582 val->sh_slave1_nack = status_shub.slave1_nack;
2583 val->sh_slave0_nack = status_shub.slave0_nack;
2584
2585 return ret;
2586 }
2587
lsm6dsv_flag_data_ready_get(const stmdev_ctx_t * ctx,lsm6dsv_data_ready_t * val)2588 int32_t lsm6dsv_flag_data_ready_get(const stmdev_ctx_t *ctx,
2589 lsm6dsv_data_ready_t *val)
2590 {
2591 lsm6dsv_status_reg_t status;
2592 int32_t ret;
2593
2594 ret = lsm6dsv_read_reg(ctx, LSM6DSV_STATUS_REG, (uint8_t *)&status, 1);
2595 if (ret != 0)
2596 {
2597 return ret;
2598 }
2599
2600 val->drdy_xl = status.xlda;
2601 val->drdy_gy = status.gda;
2602 val->drdy_temp = status.tda;
2603
2604 return ret;
2605 }
2606
2607 /**
2608 * @brief Mask status bit reset[set]
2609 *
2610 * @param ctx read / write interface definitions
2611 * @param val Mask to prevent status bit being reset
2612 * @retval interface status (MANDATORY: return 0 -> no Error)
2613 *
2614 */
lsm6dsv_int_ack_mask_set(const stmdev_ctx_t * ctx,uint8_t val)2615 int32_t lsm6dsv_int_ack_mask_set(const stmdev_ctx_t *ctx, uint8_t val)
2616 {
2617 int32_t ret;
2618
2619 ret = lsm6dsv_write_reg(ctx, LSM6DSV_INT_ACK_MASK, &val, 1);
2620
2621 return ret;
2622 }
2623
2624 /**
2625 * @brief Mask status bit reset[get]
2626 *
2627 * @param ctx read / write interface definitions
2628 * @param val Mask to prevent status bit being reset
2629 * @retval interface status (MANDATORY: return 0 -> no Error)
2630 *
2631 */
lsm6dsv_int_ack_mask_get(const stmdev_ctx_t * ctx,uint8_t * val)2632 int32_t lsm6dsv_int_ack_mask_get(const stmdev_ctx_t *ctx, uint8_t *val)
2633 {
2634 int32_t ret;
2635
2636 ret = lsm6dsv_read_reg(ctx, LSM6DSV_INT_ACK_MASK, val, 1);
2637
2638 return ret;
2639 }
2640
2641 /**
2642 * @brief Temperature data output register[get]
2643 *
2644 * @param ctx read / write interface definitions
2645 * @param val Temperature data output register
2646 * @retval interface status (MANDATORY: return 0 -> no Error)
2647 *
2648 */
lsm6dsv_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2649 int32_t lsm6dsv_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2650 {
2651 uint8_t buff[2];
2652 int32_t ret;
2653
2654 ret = lsm6dsv_read_reg(ctx, LSM6DSV_OUT_TEMP_L, &buff[0], 2);
2655 if (ret != 0)
2656 {
2657 return ret;
2658 }
2659
2660 *val = (int16_t)buff[1];
2661 *val = (*val * 256) + (int16_t)buff[0];
2662
2663 return ret;
2664 }
2665
2666 /**
2667 * @brief Angular rate sensor.[get]
2668 *
2669 * @param ctx read / write interface definitions
2670 * @param val Angular rate sensor.
2671 * @retval interface status (MANDATORY: return 0 -> no Error)
2672 *
2673 */
lsm6dsv_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2674 int32_t lsm6dsv_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2675 {
2676 uint8_t buff[6];
2677 int32_t ret;
2678
2679 ret = lsm6dsv_read_reg(ctx, LSM6DSV_OUTX_L_G, &buff[0], 6);
2680 if (ret != 0)
2681 {
2682 return ret;
2683 }
2684
2685 val[0] = (int16_t)buff[1];
2686 val[0] = (val[0] * 256) + (int16_t)buff[0];
2687 val[1] = (int16_t)buff[3];
2688 val[1] = (val[1] * 256) + (int16_t)buff[2];
2689 val[2] = (int16_t)buff[5];
2690 val[2] = (val[2] * 256) + (int16_t)buff[4];
2691
2692 return ret;
2693 }
2694
2695 /**
2696 * @brief Angular rate sensor.[get]
2697 *
2698 * @param ctx read / write interface definitions
2699 * @param val OIS Angular rate sensor (thru SPI2).
2700 * @retval interface status (MANDATORY: return 0 -> no Error)
2701 *
2702 */
lsm6dsv_ois_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2703 int32_t lsm6dsv_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2704 {
2705 uint8_t buff[6];
2706 int32_t ret;
2707
2708 ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_OUTX_L_G_OIS, &buff[0], 6);
2709 if (ret != 0)
2710 {
2711 return ret;
2712 }
2713
2714 val[0] = (int16_t)buff[1];
2715 val[0] = (*val * 256) + (int16_t)buff[0];
2716 val[1] = (int16_t)buff[3];
2717 val[1] = (*val * 256) + (int16_t)buff[2];
2718 val[2] = (int16_t)buff[5];
2719 val[2] = (*val * 256) + (int16_t)buff[4];
2720
2721 return ret;
2722 }
2723
2724 /**
2725 * @brief Angular rate sensor for OIS gyro or the EIS gyro channel.[get]
2726 *
2727 * @param ctx read / write interface definitions
2728 * @param val Angular rate sensor for OIS gyro or the EIS gyro channel.
2729 * @retval interface status (MANDATORY: return 0 -> no Error)
2730 *
2731 */
lsm6dsv_ois_eis_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2732 int32_t lsm6dsv_ois_eis_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2733 {
2734 uint8_t buff[6];
2735 int32_t ret;
2736
2737 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_OUTX_L_G_OIS_EIS, &buff[0], 6);
2738 if (ret != 0)
2739 {
2740 return ret;
2741 }
2742
2743 val[0] = (int16_t)buff[1];
2744 val[0] = (*val * 256) + (int16_t)buff[0];
2745 val[1] = (int16_t)buff[3];
2746 val[1] = (*val * 256) + (int16_t)buff[2];
2747 val[2] = (int16_t)buff[5];
2748 val[2] = (*val * 256) + (int16_t)buff[4];
2749
2750 return ret;
2751 }
2752
2753 /**
2754 * @brief Linear acceleration sensor.[get]
2755 *
2756 * @param ctx read / write interface definitions
2757 * @param val Linear acceleration sensor.
2758 * @retval interface status (MANDATORY: return 0 -> no Error)
2759 *
2760 */
lsm6dsv_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2761 int32_t lsm6dsv_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2762 {
2763 uint8_t buff[6];
2764 int32_t ret;
2765
2766 ret = lsm6dsv_read_reg(ctx, LSM6DSV_OUTX_L_A, &buff[0], 6);
2767 if (ret != 0)
2768 {
2769 return ret;
2770 }
2771
2772 val[0] = (int16_t)buff[1];
2773 val[0] = (val[0] * 256) + (int16_t)buff[0];
2774 val[1] = (int16_t)buff[3];
2775 val[1] = (val[1] * 256) + (int16_t)buff[2];
2776 val[2] = (int16_t)buff[5];
2777 val[2] = (val[2] * 256) + (int16_t)buff[4];
2778
2779 return ret;
2780 }
2781
2782 /**
2783 * @brief Linear acceleration sensor for Dual channel mode.[get]
2784 *
2785 * @param ctx read / write interface definitions
2786 * @param val Linear acceleration sensor or Dual channel mode.
2787 * @retval interface status (MANDATORY: return 0 -> no Error)
2788 *
2789 */
lsm6dsv_dual_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2790 int32_t lsm6dsv_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2791 {
2792 uint8_t buff[6];
2793 int32_t ret;
2794
2795 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_OUTX_L_A_OIS_DUALC, &buff[0], 6);
2796 if (ret != 0)
2797 {
2798 return ret;
2799 }
2800
2801 val[0] = (int16_t)buff[1];
2802 val[0] = (val[0] * 256) + (int16_t)buff[0];
2803 val[1] = (int16_t)buff[3];
2804 val[1] = (val[1] * 256) + (int16_t)buff[2];
2805 val[2] = (int16_t)buff[5];
2806 val[2] = (val[2] * 256) + (int16_t)buff[4];
2807
2808 return ret;
2809 }
2810
2811 /**
2812 * @brief Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.[get]
2813 *
2814 * @param ctx read / write interface definitions
2815 * @param val Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.
2816 * @retval interface status (MANDATORY: return 0 -> no Error)
2817 *
2818 */
lsm6dsv_odr_cal_reg_get(const stmdev_ctx_t * ctx,int8_t * val)2819 int32_t lsm6dsv_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val)
2820 {
2821 lsm6dsv_internal_freq_t internal_freq;
2822 int32_t ret;
2823
2824 ret = lsm6dsv_read_reg(ctx, LSM6DSV_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1);
2825 *val = (int8_t)internal_freq.freq_fine;
2826
2827 return ret;
2828 }
2829
2830 /**
2831 * @brief Write buffer in a page.[set]
2832 *
2833 * @param ctx read / write interface definitions
2834 * @param val Write buffer in a page.
2835 * @retval interface status (MANDATORY: return 0 -> no Error)
2836 *
2837 */
lsm6dsv_ln_pg_write(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)2838 int32_t lsm6dsv_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address,
2839 uint8_t *buf, uint8_t len)
2840 {
2841 lsm6dsv_page_address_t page_address;
2842 lsm6dsv_page_sel_t page_sel;
2843 lsm6dsv_page_rw_t page_rw;
2844 uint8_t msb;
2845 uint8_t lsb;
2846 int32_t ret;
2847 uint8_t i ;
2848
2849 msb = ((uint8_t)(address >> 8) & 0x0FU);
2850 lsb = (uint8_t)address & 0xFFU;
2851
2852 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
2853 if (ret != 0)
2854 {
2855 return ret;
2856 }
2857
2858 /* set page write */
2859 ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1);
2860 page_rw.page_read = PROPERTY_DISABLE;
2861 page_rw.page_write = PROPERTY_ENABLE;
2862 ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1);
2863 if (ret != 0)
2864 {
2865 goto exit;
2866 }
2867
2868 /* select page */
2869 ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1);
2870 page_sel.page_sel = msb;
2871 page_sel.not_used0 = 1; // Default value
2872 ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1);
2873 if (ret != 0)
2874 {
2875 goto exit;
2876 }
2877
2878 /* set page addr */
2879 page_address.page_addr = lsb;
2880 ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_ADDRESS,
2881 (uint8_t *)&page_address, 1);
2882 if (ret != 0)
2883 {
2884 goto exit;
2885 }
2886
2887 for (i = 0; ((i < len) && (ret == 0)); i++)
2888 {
2889 ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_VALUE, &buf[i], 1);
2890 if (ret != 0)
2891 {
2892 goto exit;
2893 }
2894
2895 lsb++;
2896
2897 /* Check if page wrap */
2898 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
2899 {
2900 msb++;
2901 ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1);
2902 if (ret != 0)
2903 {
2904 goto exit;
2905 }
2906
2907 page_sel.page_sel = msb;
2908 page_sel.not_used0 = 1; // Default value
2909 ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1);
2910 if (ret != 0)
2911 {
2912 goto exit;
2913 }
2914 }
2915 }
2916
2917 page_sel.page_sel = 0;
2918 page_sel.not_used0 = 1;// Default value
2919 ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1);
2920 if (ret != 0)
2921 {
2922 goto exit;
2923 }
2924
2925 /* unset page write */
2926 ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1);
2927 page_rw.page_read = PROPERTY_DISABLE;
2928 page_rw.page_write = PROPERTY_DISABLE;
2929 ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1);
2930
2931 exit:
2932 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
2933
2934 return ret;
2935 }
2936
2937 /**
2938 * @defgroup Common
2939 * @brief This section groups common useful functions.
2940 * @{/
2941 *
2942 */
2943
2944 /**
2945 * @brief Read buffer in a page.[set]
2946 *
2947 * @param ctx read / write interface definitions
2948 * @param val Write buffer in a page.
2949 * @retval interface status (MANDATORY: return 0 -> no Error)
2950 *
2951 */
lsm6dsv_ln_pg_read(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)2952 int32_t lsm6dsv_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf,
2953 uint8_t len)
2954 {
2955 lsm6dsv_page_address_t page_address;
2956 lsm6dsv_page_sel_t page_sel;
2957 lsm6dsv_page_rw_t page_rw;
2958 uint8_t msb;
2959 uint8_t lsb;
2960 int32_t ret;
2961 uint8_t i ;
2962
2963 msb = ((uint8_t)(address >> 8) & 0x0FU);
2964 lsb = (uint8_t)address & 0xFFU;
2965
2966 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
2967 if (ret != 0)
2968 {
2969 return ret;
2970 }
2971
2972 /* set page write */
2973 ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1);
2974 page_rw.page_read = PROPERTY_ENABLE;
2975 page_rw.page_write = PROPERTY_DISABLE;
2976 ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1);
2977 if (ret != 0)
2978 {
2979 goto exit;
2980 }
2981
2982 /* select page */
2983 ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1);
2984 page_sel.page_sel = msb;
2985 page_sel.not_used0 = 1; // Default value
2986 ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1);
2987 if (ret != 0)
2988 {
2989 goto exit;
2990 }
2991
2992 /* set page addr */
2993 page_address.page_addr = lsb;
2994 ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_ADDRESS,
2995 (uint8_t *)&page_address, 1);
2996 if (ret != 0)
2997 {
2998 goto exit;
2999 }
3000
3001 for (i = 0; ((i < len) && (ret == 0)); i++)
3002 {
3003 ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_VALUE, &buf[i], 1);
3004 if (ret != 0)
3005 {
3006 goto exit;
3007 }
3008
3009 lsb++;
3010
3011 /* Check if page wrap */
3012 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
3013 {
3014 msb++;
3015 ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1);
3016 if (ret != 0)
3017 {
3018 goto exit;
3019 }
3020
3021 page_sel.page_sel = msb;
3022 page_sel.not_used0 = 1; // Default value
3023 ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1);
3024 if (ret != 0)
3025 {
3026 goto exit;
3027 }
3028 }
3029 }
3030
3031 page_sel.page_sel = 0;
3032 page_sel.not_used0 = 1;// Default value
3033 ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_SEL, (uint8_t *)&page_sel, 1);
3034 if (ret != 0)
3035 {
3036 goto exit;
3037 }
3038
3039 /* unset page write */
3040 ret += lsm6dsv_read_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1);
3041 page_rw.page_read = PROPERTY_DISABLE;
3042 page_rw.page_write = PROPERTY_DISABLE;
3043 ret += lsm6dsv_write_reg(ctx, LSM6DSV_PAGE_RW, (uint8_t *)&page_rw, 1);
3044
3045 exit:
3046 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
3047
3048 return ret;
3049 }
3050
3051 /**
3052 * @brief Enable debug mode for embedded functions [set]
3053 *
3054 * @param ctx read / write interface definitions
3055 * @param val 0, 1
3056 * @retval interface status (MANDATORY: return 0 -> no Error)
3057 *
3058 */
lsm6dsv_emb_function_dbg_set(const stmdev_ctx_t * ctx,uint8_t val)3059 int32_t lsm6dsv_emb_function_dbg_set(const stmdev_ctx_t *ctx, uint8_t val)
3060 {
3061 lsm6dsv_ctrl10_t ctrl10;
3062 int32_t ret;
3063
3064 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1);
3065
3066 if (ret == 0)
3067 {
3068 ctrl10.emb_func_debug = val;
3069 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1);
3070 }
3071
3072 return ret;
3073 }
3074
3075 /**
3076 * @brief Enable debug mode for embedded functions [get]
3077 *
3078 * @param ctx read / write interface definitions
3079 * @param val 0, 1
3080 * @retval interface status (MANDATORY: return 0 -> no Error)
3081 *
3082 */
lsm6dsv_emb_function_dbg_get(const stmdev_ctx_t * ctx,uint8_t * val)3083 int32_t lsm6dsv_emb_function_dbg_get(const stmdev_ctx_t *ctx, uint8_t *val)
3084 {
3085 lsm6dsv_ctrl10_t ctrl10;
3086 int32_t ret;
3087
3088 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1);
3089 if (ret != 0)
3090 {
3091 return ret;
3092 }
3093
3094 *val = ctrl10.emb_func_debug;
3095
3096 return ret;
3097 }
3098
3099 /**
3100 * @}
3101 *
3102 */
3103
3104 /**
3105 * @defgroup Data ENable (DEN)
3106 * @brief This section groups all the functions concerning
3107 * DEN functionality.
3108 * @{
3109 *
3110 */
3111
3112 /**
3113 * @brief It changes the polarity of INT2 pin input trigger for data enable (DEN) or embedded functions.[set]
3114 *
3115 * @param ctx read / write interface definitions
3116 * @param val DEN_ACT_LOW, DEN_ACT_HIGH,
3117 * @retval interface status (MANDATORY: return 0 -> no Error)
3118 *
3119 */
lsm6dsv_den_polarity_set(const stmdev_ctx_t * ctx,lsm6dsv_den_polarity_t val)3120 int32_t lsm6dsv_den_polarity_set(const stmdev_ctx_t *ctx,
3121 lsm6dsv_den_polarity_t val)
3122 {
3123 lsm6dsv_ctrl4_t ctrl4;
3124 int32_t ret;
3125
3126 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1);
3127
3128 if (ret == 0)
3129 {
3130 ctrl4.int2_in_lh = (uint8_t)val & 0x1U;
3131 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1);
3132 }
3133
3134 return ret;
3135 }
3136
3137 /**
3138 * @brief It changes the polarity of INT2 pin input trigger for data enable (DEN) or embedded functions.[get]
3139 *
3140 * @param ctx read / write interface definitions
3141 * @param val DEN_ACT_LOW, DEN_ACT_HIGH,
3142 * @retval interface status (MANDATORY: return 0 -> no Error)
3143 *
3144 */
lsm6dsv_den_polarity_get(const stmdev_ctx_t * ctx,lsm6dsv_den_polarity_t * val)3145 int32_t lsm6dsv_den_polarity_get(const stmdev_ctx_t *ctx,
3146 lsm6dsv_den_polarity_t *val)
3147 {
3148 lsm6dsv_ctrl4_t ctrl4;
3149 int32_t ret;
3150
3151 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1);
3152 if (ret != 0)
3153 {
3154 return ret;
3155 }
3156
3157 switch (ctrl4.int2_in_lh)
3158 {
3159 case LSM6DSV_DEN_ACT_LOW:
3160 *val = LSM6DSV_DEN_ACT_LOW;
3161 break;
3162
3163 case LSM6DSV_DEN_ACT_HIGH:
3164 *val = LSM6DSV_DEN_ACT_HIGH;
3165 break;
3166
3167 default:
3168 *val = LSM6DSV_DEN_ACT_LOW;
3169 break;
3170 }
3171
3172 return ret;
3173 }
3174
3175 /**
3176 * @brief Data ENable (DEN) configuration.[set]
3177 *
3178 * @param ctx read / write interface definitions
3179 * @param val Data ENable (DEN) configuration.
3180 * @retval interface status (MANDATORY: return 0 -> no Error)
3181 *
3182 */
lsm6dsv_den_conf_set(const stmdev_ctx_t * ctx,lsm6dsv_den_conf_t val)3183 int32_t lsm6dsv_den_conf_set(const stmdev_ctx_t *ctx, lsm6dsv_den_conf_t val)
3184 {
3185 lsm6dsv_den_t den;
3186 int32_t ret;
3187
3188 ret = lsm6dsv_read_reg(ctx, LSM6DSV_DEN, (uint8_t *)&den, 1);
3189 if (ret != 0)
3190 {
3191 return ret;
3192 }
3193
3194 den.den_z = val.den_z;
3195 den.den_y = val.den_y;
3196 den.den_x = val.den_x;
3197
3198 den.lvl2_en = (uint8_t)val.mode & 0x1U;
3199 den.lvl1_en = ((uint8_t)val.mode & 0x2U) >> 1;
3200
3201 if (val.stamp_in_gy_data == PROPERTY_ENABLE && val.stamp_in_xl_data == PROPERTY_ENABLE)
3202 {
3203 den.den_xl_g = PROPERTY_DISABLE;
3204 den.den_xl_en = PROPERTY_ENABLE;
3205 }
3206 else if (val.stamp_in_gy_data == PROPERTY_ENABLE && val.stamp_in_xl_data == PROPERTY_DISABLE)
3207 {
3208 den.den_xl_g = PROPERTY_DISABLE;
3209 den.den_xl_en = PROPERTY_DISABLE;
3210 }
3211 else if (val.stamp_in_gy_data == PROPERTY_DISABLE && val.stamp_in_xl_data == PROPERTY_ENABLE)
3212 {
3213 den.den_xl_g = PROPERTY_ENABLE;
3214 den.den_xl_en = PROPERTY_DISABLE;
3215 }
3216 else
3217 {
3218 den.den_xl_g = PROPERTY_DISABLE;
3219 den.den_xl_en = PROPERTY_DISABLE;
3220 den.den_z = PROPERTY_DISABLE;
3221 den.den_y = PROPERTY_DISABLE;
3222 den.den_x = PROPERTY_DISABLE;
3223 den.lvl2_en = PROPERTY_DISABLE;
3224 den.lvl1_en = PROPERTY_DISABLE;
3225 }
3226
3227 ret = lsm6dsv_write_reg(ctx, LSM6DSV_DEN, (uint8_t *)&den, 1);
3228
3229 return ret;
3230 }
3231
3232
3233 /**
3234 * @brief Data ENable (DEN) configuration.[get]
3235 *
3236 * @param ctx read / write interface definitions
3237 * @param val Data ENable (DEN) configuration.
3238 * @retval interface status (MANDATORY: return 0 -> no Error)
3239 *
3240 */
lsm6dsv_den_conf_get(const stmdev_ctx_t * ctx,lsm6dsv_den_conf_t * val)3241 int32_t lsm6dsv_den_conf_get(const stmdev_ctx_t *ctx, lsm6dsv_den_conf_t *val)
3242 {
3243 lsm6dsv_den_t den;
3244 int32_t ret;
3245
3246 ret = lsm6dsv_read_reg(ctx, LSM6DSV_DEN, (uint8_t *)&den, 1);
3247 if (ret != 0)
3248 {
3249 return ret;
3250 }
3251
3252 val->den_z = den.den_z;
3253 val->den_y = den.den_y;
3254 val->den_x = den.den_x;
3255
3256 if ((den.den_x | den.den_y | den.den_z) == PROPERTY_ENABLE)
3257 {
3258 if (den.den_xl_g == PROPERTY_DISABLE && den.den_xl_en == PROPERTY_ENABLE)
3259 {
3260 val->stamp_in_gy_data = PROPERTY_ENABLE;
3261 val->stamp_in_xl_data = PROPERTY_ENABLE;
3262 }
3263 else if (den.den_xl_g == PROPERTY_DISABLE && den.den_xl_en == PROPERTY_DISABLE)
3264 {
3265 val->stamp_in_gy_data = PROPERTY_ENABLE;
3266 val->stamp_in_xl_data = PROPERTY_DISABLE;
3267 }
3268 else // ( (den.den_xl_g & !den.den_xl_en) == PROPERTY_ENABLE )
3269 {
3270 val->stamp_in_gy_data = PROPERTY_DISABLE;
3271 val->stamp_in_xl_data = PROPERTY_ENABLE;
3272 }
3273 }
3274 else
3275 {
3276 val->stamp_in_gy_data = PROPERTY_DISABLE;
3277 val->stamp_in_xl_data = PROPERTY_DISABLE;
3278 }
3279
3280 switch ((den.lvl1_en << 1) + den.lvl2_en)
3281 {
3282 case LSM6DSV_LEVEL_TRIGGER:
3283 val->mode = LSM6DSV_LEVEL_TRIGGER;
3284 break;
3285
3286 case LSM6DSV_LEVEL_LATCHED:
3287 val->mode = LSM6DSV_LEVEL_LATCHED;
3288 break;
3289
3290 default:
3291 val->mode = LSM6DSV_DEN_NOT_DEFINED;
3292 break;
3293 }
3294
3295 return ret;
3296 }
3297
3298 /**
3299 * @}
3300 *
3301 */
3302
3303 /**
3304 * @defgroup Electronic Image Stabilization (EIS)
3305 * @brief Electronic Image Stabilization (EIS)
3306 * @{/
3307 *
3308 */
3309
3310 /**
3311 * @brief Gyroscope full-scale selection for EIS channel. WARNING: 4000dps will be available only if also User Interface chain is set to 4000dps[set]
3312 *
3313 * @param ctx read / write interface definitions
3314 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
3315 * @retval interface status (MANDATORY: return 0 -> no Error)
3316 *
3317 */
lsm6dsv_eis_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv_eis_gy_full_scale_t val)3318 int32_t lsm6dsv_eis_gy_full_scale_set(const stmdev_ctx_t *ctx,
3319 lsm6dsv_eis_gy_full_scale_t val)
3320 {
3321 lsm6dsv_ctrl_eis_t ctrl_eis;
3322 int32_t ret;
3323
3324 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3325
3326 if (ret == 0)
3327 {
3328 ctrl_eis.fs_g_eis = (uint8_t)val & 0x7U;
3329 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3330 }
3331
3332 return ret;
3333 }
3334
3335 /**
3336 * @brief Gyroscope full-scale selection for EIS channel. WARNING: 4000dps will be available only if also User Interface chain is set to 4000dps[get]
3337 *
3338 * @param ctx read / write interface definitions
3339 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps
3340 * @retval interface status (MANDATORY: return 0 -> no Error)
3341 *
3342 */
lsm6dsv_eis_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv_eis_gy_full_scale_t * val)3343 int32_t lsm6dsv_eis_gy_full_scale_get(const stmdev_ctx_t *ctx,
3344 lsm6dsv_eis_gy_full_scale_t *val)
3345 {
3346 lsm6dsv_ctrl_eis_t ctrl_eis;
3347 int32_t ret;
3348
3349 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3350 if (ret != 0)
3351 {
3352 return ret;
3353 }
3354
3355 switch (ctrl_eis.fs_g_eis)
3356 {
3357 case LSM6DSV_EIS_125dps:
3358 *val = LSM6DSV_EIS_125dps;
3359 break;
3360
3361 case LSM6DSV_EIS_250dps:
3362 *val = LSM6DSV_EIS_250dps;
3363 break;
3364
3365 case LSM6DSV_EIS_500dps:
3366 *val = LSM6DSV_EIS_500dps;
3367 break;
3368
3369 case LSM6DSV_EIS_1000dps:
3370 *val = LSM6DSV_EIS_1000dps;
3371 break;
3372
3373 case LSM6DSV_EIS_2000dps:
3374 *val = LSM6DSV_EIS_2000dps;
3375 break;
3376
3377 default:
3378 *val = LSM6DSV_EIS_125dps;
3379 break;
3380 }
3381 return ret;
3382 }
3383
3384 /**
3385 * @brief Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).[set]
3386 *
3387 * @param ctx read / write interface definitions
3388 * @param val Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).
3389 * @retval interface status (MANDATORY: return 0 -> no Error)
3390 *
3391 */
lsm6dsv_eis_gy_on_spi2_set(const stmdev_ctx_t * ctx,uint8_t val)3392 int32_t lsm6dsv_eis_gy_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val)
3393 {
3394 lsm6dsv_ctrl_eis_t ctrl_eis;
3395 int32_t ret;
3396
3397 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3398
3399 if (ret == 0)
3400 {
3401 ctrl_eis.g_eis_on_g_ois_out_reg = val;
3402 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3403 }
3404
3405 return ret;
3406 }
3407
3408 /**
3409 * @brief Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).[get]
3410 *
3411 * @param ctx read / write interface definitions
3412 * @param val Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).
3413 * @retval interface status (MANDATORY: return 0 -> no Error)
3414 *
3415 */
lsm6dsv_eis_gy_on_spi2_get(const stmdev_ctx_t * ctx,uint8_t * val)3416 int32_t lsm6dsv_eis_gy_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val)
3417 {
3418 lsm6dsv_ctrl_eis_t ctrl_eis;
3419 int32_t ret;
3420
3421 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3422 *val = ctrl_eis.g_eis_on_g_ois_out_reg;
3423
3424 return ret;
3425 }
3426
3427 /**
3428 * @brief Enables and selects the ODR of the gyroscope EIS channel.[set]
3429 *
3430 * @param ctx read / write interface definitions
3431 * @param val EIS_1920Hz, EIS_960Hz,
3432 * @retval interface status (MANDATORY: return 0 -> no Error)
3433 *
3434 */
lsm6dsv_gy_eis_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv_gy_eis_data_rate_t val)3435 int32_t lsm6dsv_gy_eis_data_rate_set(const stmdev_ctx_t *ctx,
3436 lsm6dsv_gy_eis_data_rate_t val)
3437 {
3438 lsm6dsv_ctrl_eis_t ctrl_eis;
3439 int32_t ret;
3440
3441 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3442
3443 if (ret == 0)
3444 {
3445 ctrl_eis.odr_g_eis = (uint8_t)val & 0x03U;
3446 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3447 }
3448
3449 return ret;
3450 }
3451
3452 /**
3453 * @brief Enables and selects the ODR of the gyroscope EIS channel.[get]
3454 *
3455 * @param ctx read / write interface definitions
3456 * @param val EIS_1920Hz, EIS_960Hz,
3457 * @retval interface status (MANDATORY: return 0 -> no Error)
3458 *
3459 */
lsm6dsv_gy_eis_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv_gy_eis_data_rate_t * val)3460 int32_t lsm6dsv_gy_eis_data_rate_get(const stmdev_ctx_t *ctx,
3461 lsm6dsv_gy_eis_data_rate_t *val)
3462 {
3463 lsm6dsv_ctrl_eis_t ctrl_eis;
3464 int32_t ret;
3465
3466 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3467 if (ret != 0)
3468 {
3469 return ret;
3470 }
3471
3472 switch (ctrl_eis.odr_g_eis)
3473 {
3474 case LSM6DSV_EIS_ODR_OFF:
3475 *val = LSM6DSV_EIS_ODR_OFF;
3476 break;
3477
3478 case LSM6DSV_EIS_1920Hz:
3479 *val = LSM6DSV_EIS_1920Hz;
3480 break;
3481
3482 case LSM6DSV_EIS_960Hz:
3483 *val = LSM6DSV_EIS_960Hz;
3484 break;
3485
3486 default:
3487 *val = LSM6DSV_EIS_1920Hz;
3488 break;
3489 }
3490
3491 return ret;
3492 }
3493
3494 /**
3495 * @}
3496 *
3497 */
3498
3499 /**
3500 * @defgroup FIFO
3501 * @brief This section group all the functions concerning the FIFO usage
3502 * @{
3503 *
3504 */
3505
3506 /**
3507 * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[set]
3508 *
3509 * @param ctx read / write interface definitions
3510 * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).
3511 * @retval interface status (MANDATORY: return 0 -> no Error)
3512 *
3513 */
lsm6dsv_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)3514 int32_t lsm6dsv_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
3515 {
3516 lsm6dsv_fifo_ctrl1_t fifo_ctrl1;
3517 int32_t ret;
3518
3519 fifo_ctrl1.wtm = val;
3520 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
3521
3522 return ret;
3523 }
3524
3525 /**
3526 * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[get]
3527 *
3528 * @param ctx read / write interface definitions
3529 * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).
3530 * @retval interface status (MANDATORY: return 0 -> no Error)
3531 *
3532 */
lsm6dsv_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)3533 int32_t lsm6dsv_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
3534 {
3535 lsm6dsv_fifo_ctrl1_t fifo_ctrl1;
3536 int32_t ret;
3537
3538 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
3539 *val = fifo_ctrl1.wtm;
3540
3541 return ret;
3542 }
3543
3544 /**
3545 * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[set]
3546 *
3547 * @param ctx read / write interface definitions
3548 * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.
3549 * @retval interface status (MANDATORY: return 0 -> no Error)
3550 *
3551 */
lsm6dsv_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t * ctx,uint8_t val)3552 int32_t lsm6dsv_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
3553 {
3554 lsm6dsv_fifo_ctrl2_t fifo_ctrl2;
3555 int32_t ret;
3556
3557 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3558 if (ret == 0)
3559 {
3560 fifo_ctrl2.xl_dualc_batch_from_fsm = val;
3561 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3562 }
3563
3564 return ret;
3565 }
3566
3567 /**
3568 * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[get]
3569 *
3570 * @param ctx read / write interface definitions
3571 * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.
3572 * @retval interface status (MANDATORY: return 0 -> no Error)
3573 *
3574 */
lsm6dsv_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)3575 int32_t lsm6dsv_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
3576 {
3577 lsm6dsv_fifo_ctrl2_t fifo_ctrl2;
3578 int32_t ret;
3579
3580 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3581 *val = fifo_ctrl2.xl_dualc_batch_from_fsm;
3582
3583 return ret;
3584 }
3585
3586 /**
3587 * @brief It configures the compression algorithm to write non-compressed data at each rate.[set]
3588 *
3589 * @param ctx read / write interface definitions
3590 * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1,
3591 * @retval interface status (MANDATORY: return 0 -> no Error)
3592 *
3593 */
lsm6dsv_fifo_compress_algo_set(const stmdev_ctx_t * ctx,lsm6dsv_fifo_compress_algo_t val)3594 int32_t lsm6dsv_fifo_compress_algo_set(const stmdev_ctx_t *ctx,
3595 lsm6dsv_fifo_compress_algo_t val)
3596 {
3597 lsm6dsv_fifo_ctrl2_t fifo_ctrl2;
3598 int32_t ret;
3599
3600 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3601 if (ret == 0)
3602 {
3603 fifo_ctrl2.uncompr_rate = (uint8_t)val & 0x03U;
3604 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3605 }
3606
3607 return ret;
3608 }
3609
3610 /**
3611 * @brief It configures the compression algorithm to write non-compressed data at each rate.[get]
3612 *
3613 * @param ctx read / write interface definitions
3614 * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1,
3615 * @retval interface status (MANDATORY: return 0 -> no Error)
3616 *
3617 */
lsm6dsv_fifo_compress_algo_get(const stmdev_ctx_t * ctx,lsm6dsv_fifo_compress_algo_t * val)3618 int32_t lsm6dsv_fifo_compress_algo_get(const stmdev_ctx_t *ctx,
3619 lsm6dsv_fifo_compress_algo_t *val)
3620 {
3621 lsm6dsv_fifo_ctrl2_t fifo_ctrl2;
3622 int32_t ret;
3623
3624 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3625 if (ret != 0)
3626 {
3627 return ret;
3628 }
3629
3630 switch (fifo_ctrl2.uncompr_rate)
3631 {
3632 case LSM6DSV_CMP_DISABLE:
3633 *val = LSM6DSV_CMP_DISABLE;
3634 break;
3635
3636 case LSM6DSV_CMP_8_TO_1:
3637 *val = LSM6DSV_CMP_8_TO_1;
3638 break;
3639
3640 case LSM6DSV_CMP_16_TO_1:
3641 *val = LSM6DSV_CMP_16_TO_1;
3642 break;
3643
3644 case LSM6DSV_CMP_32_TO_1:
3645 *val = LSM6DSV_CMP_32_TO_1;
3646 break;
3647
3648 default:
3649 *val = LSM6DSV_CMP_DISABLE;
3650 break;
3651 }
3652 return ret;
3653 }
3654
3655 /**
3656 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
3657 *
3658 * @param ctx read / write interface definitions
3659 * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO.
3660 * @retval interface status (MANDATORY: return 0 -> no Error)
3661 *
3662 */
lsm6dsv_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t * ctx,uint8_t val)3663 int32_t lsm6dsv_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val)
3664 {
3665 lsm6dsv_fifo_ctrl2_t fifo_ctrl2;
3666 int32_t ret;
3667
3668 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3669 if (ret == 0)
3670 {
3671 fifo_ctrl2.odr_chg_en = val;
3672 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3673 }
3674
3675 return ret;
3676 }
3677
3678 /**
3679 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
3680 *
3681 * @param ctx read / write interface definitions
3682 * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO.
3683 * @retval interface status (MANDATORY: return 0 -> no Error)
3684 *
3685 */
lsm6dsv_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t * ctx,uint8_t * val)3686 int32_t lsm6dsv_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx,
3687 uint8_t *val)
3688 {
3689 lsm6dsv_fifo_ctrl2_t fifo_ctrl2;
3690 int32_t ret;
3691
3692 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3693 *val = fifo_ctrl2.odr_chg_en;
3694
3695 return ret;
3696 }
3697
3698 /**
3699 * @brief Enables/Disables compression algorithm runtime.[set]
3700 *
3701 * @param ctx read / write interface definitions
3702 * @param val Enables/Disables compression algorithm runtime.
3703 * @retval interface status (MANDATORY: return 0 -> no Error)
3704 *
3705 */
lsm6dsv_fifo_compress_algo_real_time_set(const stmdev_ctx_t * ctx,uint8_t val)3706 int32_t lsm6dsv_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx,
3707 uint8_t val)
3708 {
3709 lsm6dsv_emb_func_en_b_t emb_func_en_b;
3710 lsm6dsv_fifo_ctrl2_t fifo_ctrl2;
3711
3712 int32_t ret;
3713
3714 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3715 fifo_ctrl2.fifo_compr_rt_en = val;
3716 ret += lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3717 if (ret != 0)
3718 {
3719 return ret;
3720 }
3721
3722 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
3723 if (ret != 0)
3724 {
3725 return ret;
3726 }
3727
3728 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
3729 emb_func_en_b.fifo_compr_en = val;
3730 ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
3731 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
3732
3733 return ret;
3734 }
3735
3736 /**
3737 * @brief Enables/Disables compression algorithm runtime.[get]
3738 *
3739 * @param ctx read / write interface definitions
3740 * @param val Enables/Disables compression algorithm runtime.
3741 * @retval interface status (MANDATORY: return 0 -> no Error)
3742 *
3743 */
lsm6dsv_fifo_compress_algo_real_time_get(const stmdev_ctx_t * ctx,uint8_t * val)3744 int32_t lsm6dsv_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx,
3745 uint8_t *val)
3746 {
3747 lsm6dsv_fifo_ctrl2_t fifo_ctrl2;
3748 int32_t ret;
3749
3750 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3751
3752 *val = fifo_ctrl2.fifo_compr_rt_en;
3753
3754 return ret;
3755 }
3756
3757 /**
3758 * @brief Sensing chain FIFO stop values memorization at threshold level.[set]
3759 *
3760 * @param ctx read / write interface definitions
3761 * @param val Sensing chain FIFO stop values memorization at threshold level.
3762 * @retval interface status (MANDATORY: return 0 -> no Error)
3763 *
3764 */
lsm6dsv_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)3765 int32_t lsm6dsv_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
3766 {
3767 lsm6dsv_fifo_ctrl2_t fifo_ctrl2;
3768 int32_t ret;
3769
3770 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3771 if (ret == 0)
3772 {
3773 fifo_ctrl2.stop_on_wtm = val;
3774 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3775 }
3776
3777 return ret;
3778 }
3779
3780 /**
3781 * @brief Sensing chain FIFO stop values memorization at threshold level.[get]
3782 *
3783 * @param ctx read / write interface definitions
3784 * @param val Sensing chain FIFO stop values memorization at threshold level.
3785 * @retval interface status (MANDATORY: return 0 -> no Error)
3786 *
3787 */
lsm6dsv_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)3788 int32_t lsm6dsv_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val)
3789 {
3790 lsm6dsv_fifo_ctrl2_t fifo_ctrl2;
3791 int32_t ret;
3792
3793 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3794 *val = fifo_ctrl2.stop_on_wtm;
3795
3796 return ret;
3797 }
3798
3799 /**
3800 * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[set]
3801 *
3802 * @param ctx read / write interface definitions
3803 * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz,
3804 * @retval interface status (MANDATORY: return 0 -> no Error)
3805 *
3806 */
lsm6dsv_fifo_xl_batch_set(const stmdev_ctx_t * ctx,lsm6dsv_fifo_xl_batch_t val)3807 int32_t lsm6dsv_fifo_xl_batch_set(const stmdev_ctx_t *ctx,
3808 lsm6dsv_fifo_xl_batch_t val)
3809 {
3810 lsm6dsv_fifo_ctrl3_t fifo_ctrl3;
3811 int32_t ret;
3812
3813 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3814 if (ret == 0)
3815 {
3816 fifo_ctrl3.bdr_xl = (uint8_t)val & 0xFu;
3817 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3818 }
3819
3820 return ret;
3821 }
3822
3823 /**
3824 * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[get]
3825 *
3826 * @param ctx read / write interface definitions
3827 * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz,
3828 * @retval interface status (MANDATORY: return 0 -> no Error)
3829 *
3830 */
lsm6dsv_fifo_xl_batch_get(const stmdev_ctx_t * ctx,lsm6dsv_fifo_xl_batch_t * val)3831 int32_t lsm6dsv_fifo_xl_batch_get(const stmdev_ctx_t *ctx,
3832 lsm6dsv_fifo_xl_batch_t *val)
3833 {
3834 lsm6dsv_fifo_ctrl3_t fifo_ctrl3;
3835 int32_t ret;
3836
3837 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3838 if (ret != 0)
3839 {
3840 return ret;
3841 }
3842
3843 switch (fifo_ctrl3.bdr_xl)
3844 {
3845 case LSM6DSV_XL_NOT_BATCHED:
3846 *val = LSM6DSV_XL_NOT_BATCHED;
3847 break;
3848
3849 case LSM6DSV_XL_BATCHED_AT_1Hz875:
3850 *val = LSM6DSV_XL_BATCHED_AT_1Hz875;
3851 break;
3852
3853 case LSM6DSV_XL_BATCHED_AT_7Hz5:
3854 *val = LSM6DSV_XL_BATCHED_AT_7Hz5;
3855 break;
3856
3857 case LSM6DSV_XL_BATCHED_AT_15Hz:
3858 *val = LSM6DSV_XL_BATCHED_AT_15Hz;
3859 break;
3860
3861 case LSM6DSV_XL_BATCHED_AT_30Hz:
3862 *val = LSM6DSV_XL_BATCHED_AT_30Hz;
3863 break;
3864
3865 case LSM6DSV_XL_BATCHED_AT_60Hz:
3866 *val = LSM6DSV_XL_BATCHED_AT_60Hz;
3867 break;
3868
3869 case LSM6DSV_XL_BATCHED_AT_120Hz:
3870 *val = LSM6DSV_XL_BATCHED_AT_120Hz;
3871 break;
3872
3873 case LSM6DSV_XL_BATCHED_AT_240Hz:
3874 *val = LSM6DSV_XL_BATCHED_AT_240Hz;
3875 break;
3876
3877 case LSM6DSV_XL_BATCHED_AT_480Hz:
3878 *val = LSM6DSV_XL_BATCHED_AT_480Hz;
3879 break;
3880
3881 case LSM6DSV_XL_BATCHED_AT_960Hz:
3882 *val = LSM6DSV_XL_BATCHED_AT_960Hz;
3883 break;
3884
3885 case LSM6DSV_XL_BATCHED_AT_1920Hz:
3886 *val = LSM6DSV_XL_BATCHED_AT_1920Hz;
3887 break;
3888
3889 case LSM6DSV_XL_BATCHED_AT_3840Hz:
3890 *val = LSM6DSV_XL_BATCHED_AT_3840Hz;
3891 break;
3892
3893 case LSM6DSV_XL_BATCHED_AT_7680Hz:
3894 *val = LSM6DSV_XL_BATCHED_AT_7680Hz;
3895 break;
3896
3897 default:
3898 *val = LSM6DSV_XL_NOT_BATCHED;
3899 break;
3900 }
3901
3902 return ret;
3903 }
3904
3905 /**
3906 * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[set]
3907 *
3908 * @param ctx read / write interface definitions
3909 * @param val GY_NOT_BATCHED, GY_BATCHED_AT_1Hz875, GY_BATCHED_AT_7Hz5, GY_BATCHED_AT_15Hz, GY_BATCHED_AT_30Hz, GY_BATCHED_AT_60Hz, GY_BATCHED_AT_120Hz, GY_BATCHED_AT_240Hz, GY_BATCHED_AT_480Hz, GY_BATCHED_AT_960Hz, GY_BATCHED_AT_1920Hz, GY_BATCHED_AT_3840Hz, GY_BATCHED_AT_7680Hz,
3910 * @retval interface status (MANDATORY: return 0 -> no Error)
3911 *
3912 */
lsm6dsv_fifo_gy_batch_set(const stmdev_ctx_t * ctx,lsm6dsv_fifo_gy_batch_t val)3913 int32_t lsm6dsv_fifo_gy_batch_set(const stmdev_ctx_t *ctx,
3914 lsm6dsv_fifo_gy_batch_t val)
3915 {
3916 lsm6dsv_fifo_ctrl3_t fifo_ctrl3;
3917 int32_t ret;
3918
3919 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3920 if (ret == 0)
3921 {
3922 fifo_ctrl3.bdr_gy = (uint8_t)val & 0x0Fu;
3923 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3924 }
3925
3926 return ret;
3927 }
3928
3929 /**
3930 * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[get]
3931 *
3932 * @param ctx read / write interface definitions
3933 * @param val GY_NOT_BATCHED, GY_BATCHED_AT_1Hz875, GY_BATCHED_AT_7Hz5, GY_BATCHED_AT_15Hz, GY_BATCHED_AT_30Hz, GY_BATCHED_AT_60Hz, GY_BATCHED_AT_120Hz, GY_BATCHED_AT_240Hz, GY_BATCHED_AT_480Hz, GY_BATCHED_AT_960Hz, GY_BATCHED_AT_1920Hz, GY_BATCHED_AT_3840Hz, GY_BATCHED_AT_7680Hz,
3934 * @retval interface status (MANDATORY: return 0 -> no Error)
3935 *
3936 */
lsm6dsv_fifo_gy_batch_get(const stmdev_ctx_t * ctx,lsm6dsv_fifo_gy_batch_t * val)3937 int32_t lsm6dsv_fifo_gy_batch_get(const stmdev_ctx_t *ctx,
3938 lsm6dsv_fifo_gy_batch_t *val)
3939 {
3940 lsm6dsv_fifo_ctrl3_t fifo_ctrl3;
3941 int32_t ret;
3942
3943 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3944 if (ret != 0)
3945 {
3946 return ret;
3947 }
3948
3949 switch (fifo_ctrl3.bdr_gy)
3950 {
3951 case LSM6DSV_GY_NOT_BATCHED:
3952 *val = LSM6DSV_GY_NOT_BATCHED;
3953 break;
3954
3955 case LSM6DSV_GY_BATCHED_AT_1Hz875:
3956 *val = LSM6DSV_GY_BATCHED_AT_1Hz875;
3957 break;
3958
3959 case LSM6DSV_GY_BATCHED_AT_7Hz5:
3960 *val = LSM6DSV_GY_BATCHED_AT_7Hz5;
3961 break;
3962
3963 case LSM6DSV_GY_BATCHED_AT_15Hz:
3964 *val = LSM6DSV_GY_BATCHED_AT_15Hz;
3965 break;
3966
3967 case LSM6DSV_GY_BATCHED_AT_30Hz:
3968 *val = LSM6DSV_GY_BATCHED_AT_30Hz;
3969 break;
3970
3971 case LSM6DSV_GY_BATCHED_AT_60Hz:
3972 *val = LSM6DSV_GY_BATCHED_AT_60Hz;
3973 break;
3974
3975 case LSM6DSV_GY_BATCHED_AT_120Hz:
3976 *val = LSM6DSV_GY_BATCHED_AT_120Hz;
3977 break;
3978
3979 case LSM6DSV_GY_BATCHED_AT_240Hz:
3980 *val = LSM6DSV_GY_BATCHED_AT_240Hz;
3981 break;
3982
3983 case LSM6DSV_GY_BATCHED_AT_480Hz:
3984 *val = LSM6DSV_GY_BATCHED_AT_480Hz;
3985 break;
3986
3987 case LSM6DSV_GY_BATCHED_AT_960Hz:
3988 *val = LSM6DSV_GY_BATCHED_AT_960Hz;
3989 break;
3990
3991 case LSM6DSV_GY_BATCHED_AT_1920Hz:
3992 *val = LSM6DSV_GY_BATCHED_AT_1920Hz;
3993 break;
3994
3995 case LSM6DSV_GY_BATCHED_AT_3840Hz:
3996 *val = LSM6DSV_GY_BATCHED_AT_3840Hz;
3997 break;
3998
3999 case LSM6DSV_GY_BATCHED_AT_7680Hz:
4000 *val = LSM6DSV_GY_BATCHED_AT_7680Hz;
4001 break;
4002
4003 default:
4004 *val = LSM6DSV_GY_NOT_BATCHED;
4005 break;
4006 }
4007 return ret;
4008 }
4009
4010
4011 /**
4012 * @brief FIFO mode selection.[set]
4013 *
4014 * @param ctx read / write interface definitions
4015 * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
4016 * @retval interface status (MANDATORY: return 0 -> no Error)
4017 *
4018 */
lsm6dsv_fifo_mode_set(const stmdev_ctx_t * ctx,lsm6dsv_fifo_mode_t val)4019 int32_t lsm6dsv_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_fifo_mode_t val)
4020 {
4021 lsm6dsv_fifo_ctrl4_t fifo_ctrl4;
4022 int32_t ret;
4023
4024 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4025 if (ret == 0)
4026 {
4027 fifo_ctrl4.fifo_mode = (uint8_t)val & 0x07U;
4028 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4029 }
4030
4031 return ret;
4032 }
4033
4034 /**
4035 * @brief FIFO mode selection.[get]
4036 *
4037 * @param ctx read / write interface definitions
4038 * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
4039 * @retval interface status (MANDATORY: return 0 -> no Error)
4040 *
4041 */
lsm6dsv_fifo_mode_get(const stmdev_ctx_t * ctx,lsm6dsv_fifo_mode_t * val)4042 int32_t lsm6dsv_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_fifo_mode_t *val)
4043 {
4044 lsm6dsv_fifo_ctrl4_t fifo_ctrl4;
4045 int32_t ret;
4046
4047 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4048 if (ret != 0)
4049 {
4050 return ret;
4051 }
4052
4053 switch (fifo_ctrl4.fifo_mode)
4054 {
4055 case LSM6DSV_BYPASS_MODE:
4056 *val = LSM6DSV_BYPASS_MODE;
4057 break;
4058
4059 case LSM6DSV_FIFO_MODE:
4060 *val = LSM6DSV_FIFO_MODE;
4061 break;
4062
4063 case LSM6DSV_STREAM_WTM_TO_FULL_MODE:
4064 *val = LSM6DSV_STREAM_WTM_TO_FULL_MODE;
4065 break;
4066
4067 case LSM6DSV_STREAM_TO_FIFO_MODE:
4068 *val = LSM6DSV_STREAM_TO_FIFO_MODE;
4069 break;
4070
4071 case LSM6DSV_BYPASS_TO_STREAM_MODE:
4072 *val = LSM6DSV_BYPASS_TO_STREAM_MODE;
4073 break;
4074
4075 case LSM6DSV_STREAM_MODE:
4076 *val = LSM6DSV_STREAM_MODE;
4077 break;
4078
4079 case LSM6DSV_BYPASS_TO_FIFO_MODE:
4080 *val = LSM6DSV_BYPASS_TO_FIFO_MODE;
4081 break;
4082
4083 default:
4084 *val = LSM6DSV_BYPASS_MODE;
4085 break;
4086 }
4087 return ret;
4088 }
4089
4090 /**
4091 * @brief Enables FIFO batching of EIS gyroscope output values.[set]
4092 *
4093 * @param ctx read / write interface definitions
4094 * @param val Enables FIFO batching of EIS gyroscope output values.
4095 * @retval interface status (MANDATORY: return 0 -> no Error)
4096 *
4097 */
lsm6dsv_fifo_gy_eis_batch_set(const stmdev_ctx_t * ctx,uint8_t val)4098 int32_t lsm6dsv_fifo_gy_eis_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
4099 {
4100 lsm6dsv_fifo_ctrl4_t fifo_ctrl4;
4101 int32_t ret;
4102
4103 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4104 if (ret == 0)
4105 {
4106 fifo_ctrl4.g_eis_fifo_en = val;
4107 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4108 }
4109
4110 return ret;
4111 }
4112
4113 /**
4114 * @brief Enables FIFO batching of EIS gyroscope output values.[get]
4115 *
4116 * @param ctx read / write interface definitions
4117 * @param val Enables FIFO batching of EIS gyroscope output values.
4118 * @retval interface status (MANDATORY: return 0 -> no Error)
4119 *
4120 */
lsm6dsv_fifo_gy_eis_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)4121 int32_t lsm6dsv_fifo_gy_eis_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
4122 {
4123 lsm6dsv_fifo_ctrl4_t fifo_ctrl4;
4124 int32_t ret;
4125
4126 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4127 *val = fifo_ctrl4.g_eis_fifo_en;
4128
4129 return ret;
4130 }
4131
4132 /**
4133 * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[set]
4134 *
4135 * @param ctx read / write interface definitions
4136 * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz,
4137 * @retval interface status (MANDATORY: return 0 -> no Error)
4138 *
4139 */
lsm6dsv_fifo_temp_batch_set(const stmdev_ctx_t * ctx,lsm6dsv_fifo_temp_batch_t val)4140 int32_t lsm6dsv_fifo_temp_batch_set(const stmdev_ctx_t *ctx,
4141 lsm6dsv_fifo_temp_batch_t val)
4142 {
4143 lsm6dsv_fifo_ctrl4_t fifo_ctrl4;
4144 int32_t ret;
4145
4146 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4147 if (ret == 0)
4148 {
4149 fifo_ctrl4.odr_t_batch = (uint8_t)val & 0x03U;
4150 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4151 }
4152
4153 return ret;
4154 }
4155
4156 /**
4157 * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[get]
4158 *
4159 * @param ctx read / write interface definitions
4160 * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz,
4161 * @retval interface status (MANDATORY: return 0 -> no Error)
4162 *
4163 */
lsm6dsv_fifo_temp_batch_get(const stmdev_ctx_t * ctx,lsm6dsv_fifo_temp_batch_t * val)4164 int32_t lsm6dsv_fifo_temp_batch_get(const stmdev_ctx_t *ctx,
4165 lsm6dsv_fifo_temp_batch_t *val)
4166 {
4167 lsm6dsv_fifo_ctrl4_t fifo_ctrl4;
4168 int32_t ret;
4169
4170 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4171 if (ret != 0)
4172 {
4173 return ret;
4174 }
4175
4176 switch (fifo_ctrl4.odr_t_batch)
4177 {
4178 case LSM6DSV_TEMP_NOT_BATCHED:
4179 *val = LSM6DSV_TEMP_NOT_BATCHED;
4180 break;
4181
4182 case LSM6DSV_TEMP_BATCHED_AT_1Hz875:
4183 *val = LSM6DSV_TEMP_BATCHED_AT_1Hz875;
4184 break;
4185
4186 case LSM6DSV_TEMP_BATCHED_AT_15Hz:
4187 *val = LSM6DSV_TEMP_BATCHED_AT_15Hz;
4188 break;
4189
4190 case LSM6DSV_TEMP_BATCHED_AT_60Hz:
4191 *val = LSM6DSV_TEMP_BATCHED_AT_60Hz;
4192 break;
4193
4194 default:
4195 *val = LSM6DSV_TEMP_NOT_BATCHED;
4196 break;
4197 }
4198 return ret;
4199 }
4200
4201 /**
4202 * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[set]
4203 *
4204 * @param ctx read / write interface definitions
4205 * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32,
4206 * @retval interface status (MANDATORY: return 0 -> no Error)
4207 *
4208 */
lsm6dsv_fifo_timestamp_batch_set(const stmdev_ctx_t * ctx,lsm6dsv_fifo_timestamp_batch_t val)4209 int32_t lsm6dsv_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx,
4210 lsm6dsv_fifo_timestamp_batch_t val)
4211 {
4212 lsm6dsv_fifo_ctrl4_t fifo_ctrl4;
4213 int32_t ret;
4214
4215 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4216 if (ret == 0)
4217 {
4218 fifo_ctrl4.dec_ts_batch = (uint8_t)val & 0x03U;
4219 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4220 }
4221
4222 return ret;
4223 }
4224
4225 /**
4226 * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[get]
4227 *
4228 * @param ctx read / write interface definitions
4229 * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32,
4230 * @retval interface status (MANDATORY: return 0 -> no Error)
4231 *
4232 */
lsm6dsv_fifo_timestamp_batch_get(const stmdev_ctx_t * ctx,lsm6dsv_fifo_timestamp_batch_t * val)4233 int32_t lsm6dsv_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx,
4234 lsm6dsv_fifo_timestamp_batch_t *val)
4235 {
4236 lsm6dsv_fifo_ctrl4_t fifo_ctrl4;
4237 int32_t ret;
4238
4239 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4240 if (ret != 0)
4241 {
4242 return ret;
4243 }
4244
4245 switch (fifo_ctrl4.dec_ts_batch)
4246 {
4247 case LSM6DSV_TMSTMP_NOT_BATCHED:
4248 *val = LSM6DSV_TMSTMP_NOT_BATCHED;
4249 break;
4250
4251 case LSM6DSV_TMSTMP_DEC_1:
4252 *val = LSM6DSV_TMSTMP_DEC_1;
4253 break;
4254
4255 case LSM6DSV_TMSTMP_DEC_8:
4256 *val = LSM6DSV_TMSTMP_DEC_8;
4257 break;
4258
4259 case LSM6DSV_TMSTMP_DEC_32:
4260 *val = LSM6DSV_TMSTMP_DEC_32;
4261 break;
4262
4263 default:
4264 *val = LSM6DSV_TMSTMP_NOT_BATCHED;
4265 break;
4266 }
4267
4268 return ret;
4269 }
4270
4271 /**
4272 * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[set]
4273 *
4274 * @param ctx read / write interface definitions
4275 * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.
4276 * @retval interface status (MANDATORY: return 0 -> no Error)
4277 *
4278 */
lsm6dsv_fifo_batch_counter_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)4279 int32_t lsm6dsv_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx,
4280 uint16_t val)
4281 {
4282 lsm6dsv_counter_bdr_reg1_t counter_bdr_reg1;
4283 lsm6dsv_counter_bdr_reg2_t counter_bdr_reg2;
4284 int32_t ret;
4285
4286 ret = lsm6dsv_read_reg(ctx, LSM6DSV_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
4287
4288 if (ret == 0)
4289 {
4290 counter_bdr_reg2.cnt_bdr_th = (uint8_t)val & 0xFFU;
4291 counter_bdr_reg1.cnt_bdr_th = (uint8_t)(val >> 8) & 0x3U;
4292 ret = lsm6dsv_write_reg(ctx, LSM6DSV_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
4293 ret += lsm6dsv_write_reg(ctx, LSM6DSV_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1);
4294 }
4295
4296 return ret;
4297 }
4298
4299 /**
4300 * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[get]
4301 *
4302 * @param ctx read / write interface definitions
4303 * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.
4304 * @retval interface status (MANDATORY: return 0 -> no Error)
4305 *
4306 */
lsm6dsv_fifo_batch_counter_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)4307 int32_t lsm6dsv_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx,
4308 uint16_t *val)
4309 {
4310 uint8_t buff[2];
4311 int32_t ret;
4312
4313 ret = lsm6dsv_read_reg(ctx, LSM6DSV_COUNTER_BDR_REG1, &buff[0], 2);
4314 if (ret != 0)
4315 {
4316 return ret;
4317 }
4318
4319 *val = (uint16_t)buff[0] & 0x3U;
4320 *val = (*val * 256U) + (uint16_t)buff[1];
4321
4322 return ret;
4323 }
4324
4325 /**
4326 * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[set]
4327 *
4328 * @param ctx read / write interface definitions
4329 * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT,
4330 * @retval interface status (MANDATORY: return 0 -> no Error)
4331 *
4332 */
lsm6dsv_fifo_batch_cnt_event_set(const stmdev_ctx_t * ctx,lsm6dsv_fifo_batch_cnt_event_t val)4333 int32_t lsm6dsv_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx,
4334 lsm6dsv_fifo_batch_cnt_event_t val)
4335 {
4336 lsm6dsv_counter_bdr_reg1_t counter_bdr_reg1;
4337 int32_t ret;
4338
4339 ret = lsm6dsv_read_reg(ctx, LSM6DSV_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
4340 if (ret == 0)
4341 {
4342 counter_bdr_reg1.trig_counter_bdr = (uint8_t)val & 0x03U;
4343 ret = lsm6dsv_write_reg(ctx, LSM6DSV_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
4344 }
4345
4346 return ret;
4347 }
4348
4349 /**
4350 * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[get]
4351 *
4352 * @param ctx read / write interface definitions
4353 * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT,
4354 * @retval interface status (MANDATORY: return 0 -> no Error)
4355 *
4356 */
lsm6dsv_fifo_batch_cnt_event_get(const stmdev_ctx_t * ctx,lsm6dsv_fifo_batch_cnt_event_t * val)4357 int32_t lsm6dsv_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx,
4358 lsm6dsv_fifo_batch_cnt_event_t *val)
4359 {
4360 lsm6dsv_counter_bdr_reg1_t counter_bdr_reg1;
4361 int32_t ret;
4362
4363 ret = lsm6dsv_read_reg(ctx, LSM6DSV_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
4364 if (ret != 0)
4365 {
4366 return ret;
4367 }
4368
4369 switch (counter_bdr_reg1.trig_counter_bdr)
4370 {
4371 case LSM6DSV_XL_BATCH_EVENT:
4372 *val = LSM6DSV_XL_BATCH_EVENT;
4373 break;
4374
4375 case LSM6DSV_GY_BATCH_EVENT:
4376 *val = LSM6DSV_GY_BATCH_EVENT;
4377 break;
4378
4379 case LSM6DSV_GY_EIS_BATCH_EVENT:
4380 *val = LSM6DSV_GY_EIS_BATCH_EVENT;
4381 break;
4382
4383 default:
4384 *val = LSM6DSV_XL_BATCH_EVENT;
4385 break;
4386 }
4387
4388 return ret;
4389 }
4390
lsm6dsv_fifo_status_get(const stmdev_ctx_t * ctx,lsm6dsv_fifo_status_t * val)4391 int32_t lsm6dsv_fifo_status_get(const stmdev_ctx_t *ctx,
4392 lsm6dsv_fifo_status_t *val)
4393 {
4394 uint8_t buff[2];
4395 lsm6dsv_fifo_status2_t status;
4396 int32_t ret;
4397
4398 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_STATUS1, (uint8_t *)&buff[0], 2);
4399 if (ret != 0)
4400 {
4401 return ret;
4402 }
4403
4404 bytecpy((uint8_t *)&status, &buff[1]);
4405
4406 val->fifo_bdr = status.counter_bdr_ia;
4407 val->fifo_ovr = status.fifo_ovr_ia;
4408 val->fifo_full = status.fifo_full_ia;
4409 val->fifo_th = status.fifo_wtm_ia;
4410
4411 val->fifo_level = (uint16_t)buff[1] & 0x01U;
4412 val->fifo_level = (val->fifo_level * 256U) + buff[0];
4413
4414 return ret;
4415 }
4416
4417
4418 /**
4419 * @brief FIFO data output[get]
4420 *
4421 * @param ctx read / write interface definitions
4422 * @param val lsm6dsv_fifo_out_raw_t
4423 * @retval interface status (MANDATORY: return 0 -> no Error)
4424 *
4425 */
lsm6dsv_fifo_out_raw_get(const stmdev_ctx_t * ctx,lsm6dsv_fifo_out_raw_t * val)4426 int32_t lsm6dsv_fifo_out_raw_get(const stmdev_ctx_t *ctx,
4427 lsm6dsv_fifo_out_raw_t *val)
4428 {
4429 lsm6dsv_fifo_data_out_tag_t fifo_data_out_tag;
4430 uint8_t buff[7];
4431 int32_t ret;
4432
4433 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FIFO_DATA_OUT_TAG, buff, 7);
4434 if (ret != 0)
4435 {
4436 return ret;
4437 }
4438
4439 bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]);
4440
4441 switch (fifo_data_out_tag.tag_sensor)
4442 {
4443 case LSM6DSV_FIFO_EMPTY:
4444 val->tag = LSM6DSV_FIFO_EMPTY;
4445 break;
4446
4447 case LSM6DSV_GY_NC_TAG:
4448 val->tag = LSM6DSV_GY_NC_TAG;
4449 break;
4450
4451 case LSM6DSV_XL_NC_TAG:
4452 val->tag = LSM6DSV_XL_NC_TAG;
4453 break;
4454
4455 case LSM6DSV_TIMESTAMP_TAG:
4456 val->tag = LSM6DSV_TIMESTAMP_TAG;
4457 break;
4458
4459 case LSM6DSV_TEMPERATURE_TAG:
4460 val->tag = LSM6DSV_TEMPERATURE_TAG;
4461 break;
4462
4463 case LSM6DSV_CFG_CHANGE_TAG:
4464 val->tag = LSM6DSV_CFG_CHANGE_TAG;
4465 break;
4466
4467 case LSM6DSV_XL_NC_T_2_TAG:
4468 val->tag = LSM6DSV_XL_NC_T_2_TAG;
4469 break;
4470
4471 case LSM6DSV_XL_NC_T_1_TAG:
4472 val->tag = LSM6DSV_XL_NC_T_1_TAG;
4473 break;
4474
4475 case LSM6DSV_XL_2XC_TAG:
4476 val->tag = LSM6DSV_XL_2XC_TAG;
4477 break;
4478
4479 case LSM6DSV_XL_3XC_TAG:
4480 val->tag = LSM6DSV_XL_3XC_TAG;
4481 break;
4482
4483 case LSM6DSV_GY_NC_T_2_TAG:
4484 val->tag = LSM6DSV_GY_NC_T_2_TAG;
4485 break;
4486
4487 case LSM6DSV_GY_NC_T_1_TAG:
4488 val->tag = LSM6DSV_GY_NC_T_1_TAG;
4489 break;
4490
4491 case LSM6DSV_GY_2XC_TAG:
4492 val->tag = LSM6DSV_GY_2XC_TAG;
4493 break;
4494
4495 case LSM6DSV_GY_3XC_TAG:
4496 val->tag = LSM6DSV_GY_3XC_TAG;
4497 break;
4498
4499 case LSM6DSV_SENSORHUB_SLAVE0_TAG:
4500 val->tag = LSM6DSV_SENSORHUB_SLAVE0_TAG;
4501 break;
4502
4503 case LSM6DSV_SENSORHUB_SLAVE1_TAG:
4504 val->tag = LSM6DSV_SENSORHUB_SLAVE1_TAG;
4505 break;
4506
4507 case LSM6DSV_SENSORHUB_SLAVE2_TAG:
4508 val->tag = LSM6DSV_SENSORHUB_SLAVE2_TAG;
4509 break;
4510
4511 case LSM6DSV_SENSORHUB_SLAVE3_TAG:
4512 val->tag = LSM6DSV_SENSORHUB_SLAVE3_TAG;
4513 break;
4514
4515 case LSM6DSV_STEP_COUNTER_TAG:
4516 val->tag = LSM6DSV_STEP_COUNTER_TAG;
4517 break;
4518
4519 case LSM6DSV_SFLP_GAME_ROTATION_VECTOR_TAG:
4520 val->tag = LSM6DSV_SFLP_GAME_ROTATION_VECTOR_TAG;
4521 break;
4522
4523 case LSM6DSV_SFLP_GYROSCOPE_BIAS_TAG:
4524 val->tag = LSM6DSV_SFLP_GYROSCOPE_BIAS_TAG;
4525 break;
4526
4527 case LSM6DSV_SFLP_GRAVITY_VECTOR_TAG:
4528 val->tag = LSM6DSV_SFLP_GRAVITY_VECTOR_TAG;
4529 break;
4530
4531 case LSM6DSV_SENSORHUB_NACK_TAG:
4532 val->tag = LSM6DSV_SENSORHUB_NACK_TAG;
4533 break;
4534
4535 case LSM6DSV_XL_DUAL_CORE:
4536 val->tag = LSM6DSV_XL_DUAL_CORE;
4537 break;
4538
4539 case LSM6DSV_GY_ENHANCED_EIS:
4540 val->tag = LSM6DSV_GY_ENHANCED_EIS;
4541 break;
4542
4543 default:
4544 val->tag = LSM6DSV_FIFO_EMPTY;
4545 break;
4546 }
4547
4548 val->cnt = fifo_data_out_tag.tag_cnt;
4549
4550 val->data[0] = buff[1];
4551 val->data[1] = buff[2];
4552 val->data[2] = buff[3];
4553 val->data[3] = buff[4];
4554 val->data[4] = buff[5];
4555 val->data[5] = buff[6];
4556
4557 return ret;
4558 }
4559
4560 /**
4561 * @brief Batching in FIFO buffer of step counter value.[set]
4562 *
4563 * @param ctx read / write interface definitions
4564 * @param val Batching in FIFO buffer of step counter value.
4565 * @retval interface status (MANDATORY: return 0 -> no Error)
4566 *
4567 */
lsm6dsv_fifo_stpcnt_batch_set(const stmdev_ctx_t * ctx,uint8_t val)4568 int32_t lsm6dsv_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
4569 {
4570 lsm6dsv_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4571 int32_t ret;
4572
4573 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
4574 if (ret != 0)
4575 {
4576 return ret;
4577 }
4578
4579 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4580 emb_func_fifo_en_a.step_counter_fifo_en = val;
4581 ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4582
4583 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
4584
4585 return ret;
4586 }
4587
4588 /**
4589 * @brief Batching in FIFO buffer of step counter value.[get]
4590 *
4591 * @param ctx read / write interface definitions
4592 * @param val Batching in FIFO buffer of step counter value.
4593 * @retval interface status (MANDATORY: return 0 -> no Error)
4594 *
4595 */
lsm6dsv_fifo_stpcnt_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)4596 int32_t lsm6dsv_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
4597 {
4598 lsm6dsv_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4599 int32_t ret;
4600
4601 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
4602 if (ret != 0)
4603 {
4604 return ret;
4605 }
4606
4607 ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4608 *val = emb_func_fifo_en_a.step_counter_fifo_en;
4609
4610 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
4611
4612 return ret;
4613 }
4614
4615 /**
4616 * @brief Enable FIFO data batching of slave idx.[set]
4617 *
4618 * @param ctx read / write interface definitions
4619 * @param val Enable FIFO data batching of slave idx.
4620 * @retval interface status (MANDATORY: return 0 -> no Error)
4621 *
4622 */
lsm6dsv_fifo_sh_batch_slave_set(const stmdev_ctx_t * ctx,uint8_t idx,uint8_t val)4623 int32_t lsm6dsv_fifo_sh_batch_slave_set(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t val)
4624 {
4625 lsm6dsv_slv0_config_t slv_config;
4626 int32_t ret;
4627
4628 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
4629 if (ret != 0)
4630 {
4631 return ret;
4632 }
4633
4634 ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1);
4635 slv_config.batch_ext_sens_0_en = val;
4636 ret += lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1);
4637
4638 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
4639
4640 return ret;
4641 }
4642
4643 /**
4644 * @brief Enable FIFO data batching of slave idx.[get]
4645 *
4646 * @param ctx read / write interface definitions
4647 * @param val Enable FIFO data batching of slave idx.
4648 * @retval interface status (MANDATORY: return 0 -> no Error)
4649 *
4650 */
lsm6dsv_fifo_sh_batch_slave_get(const stmdev_ctx_t * ctx,uint8_t idx,uint8_t * val)4651 int32_t lsm6dsv_fifo_sh_batch_slave_get(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val)
4652 {
4653 lsm6dsv_slv0_config_t slv_config;
4654 int32_t ret;
4655
4656 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
4657 if (ret != 0)
4658 {
4659 return ret;
4660 }
4661
4662 ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1);
4663 *val = slv_config.batch_ext_sens_0_en;
4664
4665 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
4666
4667 return ret;
4668 }
4669
4670 /**
4671 * @brief Batching in FIFO buffer of SFLP.[set]
4672 *
4673 * @param ctx read / write interface definitions
4674 * @param val Batching in FIFO buffer of SFLP values.
4675 * @retval interface status (MANDATORY: return 0 -> no Error)
4676 *
4677 */
lsm6dsv_fifo_sflp_batch_set(const stmdev_ctx_t * ctx,lsm6dsv_fifo_sflp_raw_t val)4678 int32_t lsm6dsv_fifo_sflp_batch_set(const stmdev_ctx_t *ctx,
4679 lsm6dsv_fifo_sflp_raw_t val)
4680 {
4681 lsm6dsv_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4682 int32_t ret;
4683
4684 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
4685 if (ret == 0)
4686 {
4687 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4688 emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation;
4689 emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity;
4690 emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias;
4691 ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_FIFO_EN_A,
4692 (uint8_t *)&emb_func_fifo_en_a, 1);
4693 }
4694
4695 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
4696
4697 return ret;
4698 }
4699
4700 /**
4701 * @brief Batching in FIFO buffer of SFLP.[get]
4702 *
4703 * @param ctx read / write interface definitions
4704 * @param val Batching in FIFO buffer of SFLP values.
4705 * @retval interface status (MANDATORY: return 0 -> no Error)
4706 *
4707 */
lsm6dsv_fifo_sflp_batch_get(const stmdev_ctx_t * ctx,lsm6dsv_fifo_sflp_raw_t * val)4708 int32_t lsm6dsv_fifo_sflp_batch_get(const stmdev_ctx_t *ctx,
4709 lsm6dsv_fifo_sflp_raw_t *val)
4710 {
4711 lsm6dsv_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4712 int32_t ret;
4713
4714 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
4715 if (ret == 0)
4716 {
4717 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4718
4719 val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en;
4720 val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en;
4721 val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en;
4722 }
4723
4724 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
4725
4726 return ret;
4727 }
4728
4729 /**
4730 * @}
4731 *
4732 */
4733
4734 /**
4735 * @defgroup Filters
4736 * @brief This section group all the functions concerning the
4737 * filters configuration
4738 * @{
4739 *
4740 */
4741
4742 /**
4743 * @brief Protocol anti-spike filters.[set]
4744 *
4745 * @param ctx read / write interface definitions
4746 * @param val AUTO, ALWAYS_ACTIVE,
4747 * @retval interface status (MANDATORY: return 0 -> no Error)
4748 *
4749 */
lsm6dsv_filt_anti_spike_set(const stmdev_ctx_t * ctx,lsm6dsv_filt_anti_spike_t val)4750 int32_t lsm6dsv_filt_anti_spike_set(const stmdev_ctx_t *ctx,
4751 lsm6dsv_filt_anti_spike_t val)
4752 {
4753 lsm6dsv_if_cfg_t if_cfg;
4754 int32_t ret;
4755
4756 ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1);
4757
4758 if (ret == 0)
4759 {
4760 if_cfg.asf_ctrl = (uint8_t)val & 0x01U;
4761 ret = lsm6dsv_write_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1);
4762 }
4763
4764 return ret;
4765 }
4766
4767 /**
4768 * @brief Protocol anti-spike filters.[get]
4769 *
4770 * @param ctx read / write interface definitions
4771 * @param val AUTO, ALWAYS_ACTIVE,
4772 * @retval interface status (MANDATORY: return 0 -> no Error)
4773 *
4774 */
lsm6dsv_filt_anti_spike_get(const stmdev_ctx_t * ctx,lsm6dsv_filt_anti_spike_t * val)4775 int32_t lsm6dsv_filt_anti_spike_get(const stmdev_ctx_t *ctx,
4776 lsm6dsv_filt_anti_spike_t *val)
4777 {
4778 lsm6dsv_if_cfg_t if_cfg;
4779 int32_t ret;
4780
4781 ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1);
4782 if (ret != 0)
4783 {
4784 return ret;
4785 }
4786
4787 switch (if_cfg.asf_ctrl)
4788 {
4789 case LSM6DSV_AUTO:
4790 *val = LSM6DSV_AUTO;
4791 break;
4792
4793 case LSM6DSV_ALWAYS_ACTIVE:
4794 *val = LSM6DSV_ALWAYS_ACTIVE;
4795 break;
4796
4797 default:
4798 *val = LSM6DSV_AUTO;
4799 break;
4800 }
4801
4802 return ret;
4803 }
4804
4805 /**
4806 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set]
4807 *
4808 * @param ctx read / write interface definitions
4809 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
4810 * @retval interface status (MANDATORY: return 0 -> no Error)
4811 *
4812 */
lsm6dsv_filt_settling_mask_set(const stmdev_ctx_t * ctx,lsm6dsv_filt_settling_mask_t val)4813 int32_t lsm6dsv_filt_settling_mask_set(const stmdev_ctx_t *ctx,
4814 lsm6dsv_filt_settling_mask_t val)
4815 {
4816 lsm6dsv_emb_func_cfg_t emb_func_cfg;
4817 lsm6dsv_ui_int_ois_t ui_int_ois;
4818 lsm6dsv_ctrl4_t ctrl4;
4819 int32_t ret;
4820
4821 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1);
4822 ctrl4.drdy_mask = val.drdy;
4823 ret += lsm6dsv_write_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1);
4824 if (ret != 0)
4825 {
4826 return ret;
4827 }
4828
4829 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
4830 emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl;
4831 emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g;
4832 ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
4833 if (ret != 0)
4834 {
4835 return ret;
4836 }
4837
4838 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1);
4839 ui_int_ois.drdy_mask_ois = val.ois_drdy;
4840 ret += lsm6dsv_write_reg(ctx, LSM6DSV_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1);
4841
4842 return ret;
4843 }
4844
4845 /**
4846 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get]
4847 *
4848 * @param ctx read / write interface definitions
4849 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
4850 * @retval interface status (MANDATORY: return 0 -> no Error)
4851 *
4852 */
lsm6dsv_filt_settling_mask_get(const stmdev_ctx_t * ctx,lsm6dsv_filt_settling_mask_t * val)4853 int32_t lsm6dsv_filt_settling_mask_get(const stmdev_ctx_t *ctx,
4854 lsm6dsv_filt_settling_mask_t *val)
4855 {
4856 lsm6dsv_emb_func_cfg_t emb_func_cfg;
4857 lsm6dsv_ui_int_ois_t ui_int_ois;
4858 lsm6dsv_ctrl4_t ctrl4;
4859 int32_t ret;
4860
4861 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL4, (uint8_t *)&ctrl4, 1);
4862 ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
4863 ret += lsm6dsv_read_reg(ctx, LSM6DSV_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1);
4864
4865 val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl;
4866 val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl;
4867 val->drdy = ctrl4.drdy_mask;
4868
4869 return ret;
4870 }
4871
4872 /**
4873 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set]
4874 *
4875 * @param ctx read / write interface definitions
4876 * @param val It masks DRDY and Interrupts RQ until filter settling ends from OIS interface.
4877 * @retval interface status (MANDATORY: return 0 -> no Error)
4878 *
4879 */
lsm6dsv_filt_ois_settling_mask_set(const stmdev_ctx_t * ctx,lsm6dsv_filt_ois_settling_mask_t val)4880 int32_t lsm6dsv_filt_ois_settling_mask_set(const stmdev_ctx_t *ctx,
4881 lsm6dsv_filt_ois_settling_mask_t val)
4882 {
4883 lsm6dsv_spi2_int_ois_t spi2_int_ois;
4884 int32_t ret;
4885
4886 ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
4887
4888 if (ret == 0)
4889 {
4890 spi2_int_ois.drdy_mask_ois = val.ois_drdy;
4891 ret = lsm6dsv_write_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
4892 }
4893
4894 return ret;
4895 }
4896
4897 /**
4898 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get]
4899 *
4900 * @param ctx read / write interface definitions
4901 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
4902 * @retval interface status (MANDATORY: return 0 -> no Error)
4903 *
4904 */
lsm6dsv_filt_ois_settling_mask_get(const stmdev_ctx_t * ctx,lsm6dsv_filt_ois_settling_mask_t * val)4905 int32_t lsm6dsv_filt_ois_settling_mask_get(const stmdev_ctx_t *ctx,
4906 lsm6dsv_filt_ois_settling_mask_t *val)
4907 {
4908
4909 lsm6dsv_spi2_int_ois_t spi2_int_ois;
4910 int32_t ret;
4911
4912 ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
4913 val->ois_drdy = spi2_int_ois.drdy_mask_ois;
4914
4915 return ret;
4916 }
4917
4918 /**
4919 * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[set]
4920 *
4921 * @param ctx read / write interface definitions
4922 * @param val GY_ULTRA_LIGHT, GY_VERY_LIGHT, GY_LIGHT, GY_MEDIUM, GY_STRONG, GY_VERY_STRONG, GY_AGGRESSIVE, GY_XTREME,
4923 * @retval interface status (MANDATORY: return 0 -> no Error)
4924 *
4925 */
lsm6dsv_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsv_filt_gy_lp1_bandwidth_t val)4926 int32_t lsm6dsv_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
4927 lsm6dsv_filt_gy_lp1_bandwidth_t val)
4928 {
4929 lsm6dsv_ctrl6_t ctrl6;
4930 int32_t ret;
4931
4932 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL6, (uint8_t *)&ctrl6, 1);
4933 if (ret == 0)
4934 {
4935 ctrl6.lpf1_g_bw = (uint8_t)val & 0x0Fu;
4936 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL6, (uint8_t *)&ctrl6, 1);
4937 }
4938
4939 return ret;
4940 }
4941
4942 /**
4943 * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[get]
4944 *
4945 * @param ctx read / write interface definitions
4946 * @param val GY_ULTRA_LIGHT, GY_VERY_LIGHT, GY_LIGHT, GY_MEDIUM, GY_STRONG, GY_VERY_STRONG, GY_AGGRESSIVE, GY_XTREME,
4947 * @retval interface status (MANDATORY: return 0 -> no Error)
4948 *
4949 */
lsm6dsv_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsv_filt_gy_lp1_bandwidth_t * val)4950 int32_t lsm6dsv_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
4951 lsm6dsv_filt_gy_lp1_bandwidth_t *val)
4952 {
4953 lsm6dsv_ctrl6_t ctrl6;
4954 int32_t ret;
4955
4956 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL6, (uint8_t *)&ctrl6, 1);
4957 if (ret != 0)
4958 {
4959 return ret;
4960 }
4961
4962 switch (ctrl6.lpf1_g_bw)
4963 {
4964 case LSM6DSV_GY_ULTRA_LIGHT:
4965 *val = LSM6DSV_GY_ULTRA_LIGHT;
4966 break;
4967
4968 case LSM6DSV_GY_VERY_LIGHT:
4969 *val = LSM6DSV_GY_VERY_LIGHT;
4970 break;
4971
4972 case LSM6DSV_GY_LIGHT:
4973 *val = LSM6DSV_GY_LIGHT;
4974 break;
4975
4976 case LSM6DSV_GY_MEDIUM:
4977 *val = LSM6DSV_GY_MEDIUM;
4978 break;
4979
4980 case LSM6DSV_GY_STRONG:
4981 *val = LSM6DSV_GY_STRONG;
4982 break;
4983
4984 case LSM6DSV_GY_VERY_STRONG:
4985 *val = LSM6DSV_GY_VERY_STRONG;
4986 break;
4987
4988 case LSM6DSV_GY_AGGRESSIVE:
4989 *val = LSM6DSV_GY_AGGRESSIVE;
4990 break;
4991
4992 case LSM6DSV_GY_XTREME:
4993 *val = LSM6DSV_GY_XTREME;
4994 break;
4995
4996 default:
4997 *val = LSM6DSV_GY_ULTRA_LIGHT;
4998 break;
4999 }
5000
5001 return ret;
5002 }
5003
5004 /**
5005 * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[set]
5006 *
5007 * @param ctx read / write interface definitions
5008 * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.
5009 * @retval interface status (MANDATORY: return 0 -> no Error)
5010 *
5011 */
lsm6dsv_filt_gy_lp1_set(const stmdev_ctx_t * ctx,uint8_t val)5012 int32_t lsm6dsv_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val)
5013 {
5014 lsm6dsv_ctrl7_t ctrl7;
5015 int32_t ret;
5016
5017 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL7, (uint8_t *)&ctrl7, 1);
5018 if (ret == 0)
5019 {
5020 ctrl7.lpf1_g_en = val;
5021 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL7, (uint8_t *)&ctrl7, 1);
5022 }
5023
5024 return ret;
5025 }
5026
5027
5028 /**
5029 * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[get]
5030 *
5031 * @param ctx read / write interface definitions
5032 * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.
5033 * @retval interface status (MANDATORY: return 0 -> no Error)
5034 *
5035 */
lsm6dsv_filt_gy_lp1_get(const stmdev_ctx_t * ctx,uint8_t * val)5036 int32_t lsm6dsv_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val)
5037 {
5038 lsm6dsv_ctrl7_t ctrl7;
5039 int32_t ret;
5040
5041 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL7, (uint8_t *)&ctrl7, 1);
5042 *val = ctrl7.lpf1_g_en;
5043
5044 return ret;
5045 }
5046
5047 /**
5048 * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[set]
5049 *
5050 * @param ctx read / write interface definitions
5051 * @param val XL_ULTRA_LIGHT, XL_VERY_LIGHT, XL_LIGHT, XL_MEDIUM, XL_STRONG, XL_VERY_STRONG, XL_AGGRESSIVE, XL_XTREME,
5052 * @retval interface status (MANDATORY: return 0 -> no Error)
5053 *
5054 */
lsm6dsv_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsv_filt_xl_lp2_bandwidth_t val)5055 int32_t lsm6dsv_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx,
5056 lsm6dsv_filt_xl_lp2_bandwidth_t val)
5057 {
5058 lsm6dsv_ctrl8_t ctrl8;
5059 int32_t ret;
5060
5061 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1);
5062 if (ret == 0)
5063 {
5064 ctrl8.hp_lpf2_xl_bw = (uint8_t)val & 0x07U;
5065 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1);
5066 }
5067
5068 return ret;
5069 }
5070
5071 /**
5072 * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[get]
5073 *
5074 * @param ctx read / write interface definitions
5075 * @param val XL_ULTRA_LIGHT, XL_VERY_LIGHT, XL_LIGHT, XL_MEDIUM, XL_STRONG, XL_VERY_STRONG, XL_AGGRESSIVE, XL_XTREME,
5076 * @retval interface status (MANDATORY: return 0 -> no Error)
5077 *
5078 */
lsm6dsv_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsv_filt_xl_lp2_bandwidth_t * val)5079 int32_t lsm6dsv_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx,
5080 lsm6dsv_filt_xl_lp2_bandwidth_t *val)
5081 {
5082 lsm6dsv_ctrl8_t ctrl8;
5083 int32_t ret;
5084
5085 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL8, (uint8_t *)&ctrl8, 1);
5086 if (ret != 0)
5087 {
5088 return ret;
5089 }
5090
5091 switch (ctrl8.hp_lpf2_xl_bw)
5092 {
5093 case LSM6DSV_XL_ULTRA_LIGHT:
5094 *val = LSM6DSV_XL_ULTRA_LIGHT;
5095 break;
5096
5097 case LSM6DSV_XL_VERY_LIGHT:
5098 *val = LSM6DSV_XL_VERY_LIGHT;
5099 break;
5100
5101 case LSM6DSV_XL_LIGHT:
5102 *val = LSM6DSV_XL_LIGHT;
5103 break;
5104
5105 case LSM6DSV_XL_MEDIUM:
5106 *val = LSM6DSV_XL_MEDIUM;
5107 break;
5108
5109 case LSM6DSV_XL_STRONG:
5110 *val = LSM6DSV_XL_STRONG;
5111 break;
5112
5113 case LSM6DSV_XL_VERY_STRONG:
5114 *val = LSM6DSV_XL_VERY_STRONG;
5115 break;
5116
5117 case LSM6DSV_XL_AGGRESSIVE:
5118 *val = LSM6DSV_XL_AGGRESSIVE;
5119 break;
5120
5121 case LSM6DSV_XL_XTREME:
5122 *val = LSM6DSV_XL_XTREME;
5123 break;
5124
5125 default:
5126 *val = LSM6DSV_XL_ULTRA_LIGHT;
5127 break;
5128 }
5129
5130 return ret;
5131 }
5132
5133 /**
5134 * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[set]
5135 *
5136 * @param ctx read / write interface definitions
5137 * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.
5138 * @retval interface status (MANDATORY: return 0 -> no Error)
5139 *
5140 */
lsm6dsv_filt_xl_lp2_set(const stmdev_ctx_t * ctx,uint8_t val)5141 int32_t lsm6dsv_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val)
5142 {
5143 lsm6dsv_ctrl9_t ctrl9;
5144 int32_t ret;
5145
5146 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1);
5147 if (ret == 0)
5148 {
5149 ctrl9.lpf2_xl_en = val;
5150 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1);
5151 }
5152
5153 return ret;
5154 }
5155
5156 /**
5157 * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[get]
5158 *
5159 * @param ctx read / write interface definitions
5160 * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.
5161 * @retval interface status (MANDATORY: return 0 -> no Error)
5162 *
5163 */
lsm6dsv_filt_xl_lp2_get(const stmdev_ctx_t * ctx,uint8_t * val)5164 int32_t lsm6dsv_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val)
5165 {
5166 lsm6dsv_ctrl9_t ctrl9;
5167 int32_t ret;
5168
5169 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1);
5170 *val = ctrl9.lpf2_xl_en;
5171
5172 return ret;
5173 }
5174
5175 /**
5176 * @brief Accelerometer slope filter / high-pass filter selection.[set]
5177 *
5178 * @param ctx read / write interface definitions
5179 * @param val Accelerometer slope filter / high-pass filter selection.
5180 * @retval interface status (MANDATORY: return 0 -> no Error)
5181 *
5182 */
lsm6dsv_filt_xl_hp_set(const stmdev_ctx_t * ctx,uint8_t val)5183 int32_t lsm6dsv_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val)
5184 {
5185 lsm6dsv_ctrl9_t ctrl9;
5186 int32_t ret;
5187
5188 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1);
5189 if (ret == 0)
5190 {
5191 ctrl9.hp_slope_xl_en = val;
5192 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1);
5193 }
5194
5195 return ret;
5196 }
5197
5198 /**
5199 * @brief Accelerometer slope filter / high-pass filter selection.[get]
5200 *
5201 * @param ctx read / write interface definitions
5202 * @param val Accelerometer slope filter / high-pass filter selection.
5203 * @retval interface status (MANDATORY: return 0 -> no Error)
5204 *
5205 */
lsm6dsv_filt_xl_hp_get(const stmdev_ctx_t * ctx,uint8_t * val)5206 int32_t lsm6dsv_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val)
5207 {
5208 lsm6dsv_ctrl9_t ctrl9;
5209 int32_t ret;
5210
5211 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1);
5212 *val = ctrl9.hp_slope_xl_en;
5213
5214 return ret;
5215 }
5216
5217 /**
5218 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[set]
5219 *
5220 * @param ctx read / write interface definitions
5221 * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.
5222 * @retval interface status (MANDATORY: return 0 -> no Error)
5223 *
5224 */
lsm6dsv_filt_xl_fast_settling_set(const stmdev_ctx_t * ctx,uint8_t val)5225 int32_t lsm6dsv_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val)
5226 {
5227 lsm6dsv_ctrl9_t ctrl9;
5228 int32_t ret;
5229
5230 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1);
5231 if (ret == 0)
5232 {
5233 ctrl9.xl_fastsettl_mode = val;
5234 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1);
5235 }
5236
5237 return ret;
5238 }
5239
5240 /**
5241 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[get]
5242 *
5243 * @param ctx read / write interface definitions
5244 * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.
5245 * @retval interface status (MANDATORY: return 0 -> no Error)
5246 *
5247 */
lsm6dsv_filt_xl_fast_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)5248 int32_t lsm6dsv_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val)
5249 {
5250 lsm6dsv_ctrl9_t ctrl9;
5251 int32_t ret;
5252
5253 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1);
5254 *val = ctrl9.xl_fastsettl_mode;
5255
5256 return ret;
5257 }
5258
5259 /**
5260 * @brief Accelerometer high-pass filter mode.[set]
5261 *
5262 * @param ctx read / write interface definitions
5263 * @param val HP_MD_NORMAL, HP_MD_REFERENCE,
5264 * @retval interface status (MANDATORY: return 0 -> no Error)
5265 *
5266 */
lsm6dsv_filt_xl_hp_mode_set(const stmdev_ctx_t * ctx,lsm6dsv_filt_xl_hp_mode_t val)5267 int32_t lsm6dsv_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx,
5268 lsm6dsv_filt_xl_hp_mode_t val)
5269 {
5270 lsm6dsv_ctrl9_t ctrl9;
5271 int32_t ret;
5272
5273 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1);
5274 if (ret == 0)
5275 {
5276 ctrl9.hp_ref_mode_xl = (uint8_t)val & 0x01U;
5277 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1);
5278 }
5279
5280 return ret;
5281 }
5282
5283 /**
5284 * @brief Accelerometer high-pass filter mode.[get]
5285 *
5286 * @param ctx read / write interface definitions
5287 * @param val HP_MD_NORMAL, HP_MD_REFERENCE,
5288 * @retval interface status (MANDATORY: return 0 -> no Error)
5289 *
5290 */
lsm6dsv_filt_xl_hp_mode_get(const stmdev_ctx_t * ctx,lsm6dsv_filt_xl_hp_mode_t * val)5291 int32_t lsm6dsv_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx,
5292 lsm6dsv_filt_xl_hp_mode_t *val)
5293 {
5294 lsm6dsv_ctrl9_t ctrl9;
5295 int32_t ret;
5296
5297 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL9, (uint8_t *)&ctrl9, 1);
5298 if (ret != 0)
5299 {
5300 return ret;
5301 }
5302
5303 switch (ctrl9.hp_ref_mode_xl)
5304 {
5305 case LSM6DSV_HP_MD_NORMAL:
5306 *val = LSM6DSV_HP_MD_NORMAL;
5307 break;
5308
5309 case LSM6DSV_HP_MD_REFERENCE:
5310 *val = LSM6DSV_HP_MD_REFERENCE;
5311 break;
5312
5313 default:
5314 *val = LSM6DSV_HP_MD_NORMAL;
5315 break;
5316 }
5317
5318 return ret;
5319 }
5320
5321 /**
5322 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[set]
5323 *
5324 * @param ctx read / write interface definitions
5325 * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, WK_FEED_LP_WITH_OFFSET,
5326 * @retval interface status (MANDATORY: return 0 -> no Error)
5327 *
5328 */
lsm6dsv_filt_wkup_act_feed_set(const stmdev_ctx_t * ctx,lsm6dsv_filt_wkup_act_feed_t val)5329 int32_t lsm6dsv_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx,
5330 lsm6dsv_filt_wkup_act_feed_t val)
5331 {
5332 lsm6dsv_wake_up_ths_t wake_up_ths;
5333 lsm6dsv_tap_cfg0_t tap_cfg0;
5334 int32_t ret;
5335
5336 ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
5337 ret += lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5338 if (ret != 0)
5339 {
5340 return ret;
5341 }
5342
5343 tap_cfg0.slope_fds = (uint8_t)val & 0x01U;
5344 ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5345 if (ret != 0)
5346 {
5347 return ret;
5348 }
5349
5350 wake_up_ths.usr_off_on_wu = ((uint8_t)val & 0x02U) >> 1;
5351 ret = lsm6dsv_write_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
5352
5353 return ret;
5354 }
5355
5356 /**
5357 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[get]
5358 *
5359 * @param ctx read / write interface definitions
5360 * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, WK_FEED_LP_WITH_OFFSET,
5361 * @retval interface status (MANDATORY: return 0 -> no Error)
5362 *
5363 */
lsm6dsv_filt_wkup_act_feed_get(const stmdev_ctx_t * ctx,lsm6dsv_filt_wkup_act_feed_t * val)5364 int32_t lsm6dsv_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx,
5365 lsm6dsv_filt_wkup_act_feed_t *val)
5366 {
5367 lsm6dsv_wake_up_ths_t wake_up_ths;
5368 lsm6dsv_tap_cfg0_t tap_cfg0;
5369 int32_t ret;
5370
5371 ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
5372 ret += lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5373 if (ret != 0)
5374 {
5375 return ret;
5376 }
5377
5378 switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds)
5379 {
5380 case LSM6DSV_WK_FEED_SLOPE:
5381 *val = LSM6DSV_WK_FEED_SLOPE;
5382 break;
5383
5384 case LSM6DSV_WK_FEED_HIGH_PASS:
5385 *val = LSM6DSV_WK_FEED_HIGH_PASS;
5386 break;
5387
5388 case LSM6DSV_WK_FEED_LP_WITH_OFFSET:
5389 *val = LSM6DSV_WK_FEED_LP_WITH_OFFSET;
5390 break;
5391
5392 default:
5393 *val = LSM6DSV_WK_FEED_SLOPE;
5394 break;
5395 }
5396
5397 return ret;
5398 }
5399
5400 /**
5401 * @brief Mask hw function triggers when xl is settling.[set]
5402 *
5403 * @param ctx read / write interface definitions
5404 * @param val 0 or 1,
5405 * @retval interface status (MANDATORY: return 0 -> no Error)
5406 *
5407 */
lsm6dsv_mask_trigger_xl_settl_set(const stmdev_ctx_t * ctx,uint8_t val)5408 int32_t lsm6dsv_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val)
5409 {
5410 lsm6dsv_tap_cfg0_t tap_cfg0;
5411 int32_t ret;
5412
5413 ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5414
5415 if (ret == 0)
5416 {
5417 tap_cfg0.hw_func_mask_xl_settl = val & 0x01U;
5418 ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5419 }
5420
5421 return ret;
5422 }
5423
5424 /**
5425 * @brief Mask hw function triggers when xl is settling.[get]
5426 *
5427 * @param ctx read / write interface definitions
5428 * @param val 0 or 1,
5429 * @retval interface status (MANDATORY: return 0 -> no Error)
5430 *
5431 */
lsm6dsv_mask_trigger_xl_settl_get(const stmdev_ctx_t * ctx,uint8_t * val)5432 int32_t lsm6dsv_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val)
5433 {
5434 lsm6dsv_tap_cfg0_t tap_cfg0;
5435 int32_t ret;
5436
5437 ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5438 *val = tap_cfg0.hw_func_mask_xl_settl;
5439
5440 return ret;
5441 }
5442
5443 /**
5444 * @brief LPF2 filter on 6D (sixd) function selection.[set]
5445 *
5446 * @param ctx read / write interface definitions
5447 * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS,
5448 * @retval interface status (MANDATORY: return 0 -> no Error)
5449 *
5450 */
lsm6dsv_filt_sixd_feed_set(const stmdev_ctx_t * ctx,lsm6dsv_filt_sixd_feed_t val)5451 int32_t lsm6dsv_filt_sixd_feed_set(const stmdev_ctx_t *ctx,
5452 lsm6dsv_filt_sixd_feed_t val)
5453 {
5454 lsm6dsv_tap_cfg0_t tap_cfg0;
5455 int32_t ret;
5456
5457 ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5458
5459 if (ret == 0)
5460 {
5461 tap_cfg0.low_pass_on_6d = (uint8_t)val & 0x01U;
5462 ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5463 }
5464
5465 return ret;
5466 }
5467
5468 /**
5469 * @brief LPF2 filter on 6D (sixd) function selection.[get]
5470 *
5471 * @param ctx read / write interface definitions
5472 * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS,
5473 * @retval interface status (MANDATORY: return 0 -> no Error)
5474 *
5475 */
lsm6dsv_filt_sixd_feed_get(const stmdev_ctx_t * ctx,lsm6dsv_filt_sixd_feed_t * val)5476 int32_t lsm6dsv_filt_sixd_feed_get(const stmdev_ctx_t *ctx,
5477 lsm6dsv_filt_sixd_feed_t *val)
5478 {
5479 lsm6dsv_tap_cfg0_t tap_cfg0;
5480 int32_t ret;
5481
5482 ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5483 if (ret != 0)
5484 {
5485 return ret;
5486 }
5487
5488 switch (tap_cfg0.low_pass_on_6d)
5489 {
5490 case LSM6DSV_SIXD_FEED_ODR_DIV_2:
5491 *val = LSM6DSV_SIXD_FEED_ODR_DIV_2;
5492 break;
5493
5494 case LSM6DSV_SIXD_FEED_LOW_PASS:
5495 *val = LSM6DSV_SIXD_FEED_LOW_PASS;
5496 break;
5497
5498 default:
5499 *val = LSM6DSV_SIXD_FEED_ODR_DIV_2;
5500 break;
5501 }
5502
5503 return ret;
5504 }
5505
5506 /**
5507 * @brief Gyroscope digital LPF_EIS filter bandwidth selection.[set]
5508 *
5509 * @param ctx read / write interface definitions
5510 * @param val EIS_LP_NORMAL, EIS_LP_LIGHT,
5511 * @retval interface status (MANDATORY: return 0 -> no Error)
5512 *
5513 */
lsm6dsv_filt_gy_eis_lp_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsv_filt_gy_eis_lp_bandwidth_t val)5514 int32_t lsm6dsv_filt_gy_eis_lp_bandwidth_set(const stmdev_ctx_t *ctx,
5515 lsm6dsv_filt_gy_eis_lp_bandwidth_t val)
5516 {
5517 lsm6dsv_ctrl_eis_t ctrl_eis;
5518 int32_t ret;
5519
5520 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
5521
5522 if (ret == 0)
5523 {
5524 ctrl_eis.lpf_g_eis_bw = (uint8_t)val & 0x01U;
5525 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
5526 }
5527
5528 return ret;
5529 }
5530
5531 /**
5532 * @brief Gyroscope digital LPF_EIS filter bandwidth selection.[get]
5533 *
5534 * @param ctx read / write interface definitions
5535 * @param val EIS_LP_NORMAL, EIS_LP_LIGHT,
5536 * @retval interface status (MANDATORY: return 0 -> no Error)
5537 *
5538 */
lsm6dsv_filt_gy_eis_lp_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsv_filt_gy_eis_lp_bandwidth_t * val)5539 int32_t lsm6dsv_filt_gy_eis_lp_bandwidth_get(const stmdev_ctx_t *ctx,
5540 lsm6dsv_filt_gy_eis_lp_bandwidth_t *val)
5541 {
5542 lsm6dsv_ctrl_eis_t ctrl_eis;
5543 int32_t ret;
5544
5545 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
5546 if (ret != 0)
5547 {
5548 return ret;
5549 }
5550
5551 switch (ctrl_eis.lpf_g_eis_bw)
5552 {
5553 case LSM6DSV_EIS_LP_NORMAL:
5554 *val = LSM6DSV_EIS_LP_NORMAL;
5555 break;
5556
5557 case LSM6DSV_EIS_LP_LIGHT:
5558 *val = LSM6DSV_EIS_LP_LIGHT;
5559 break;
5560
5561 default:
5562 *val = LSM6DSV_EIS_LP_NORMAL;
5563 break;
5564 }
5565
5566 return ret;
5567 }
5568
5569 /**
5570 * @brief Gyroscope OIS digital LPF1 filter bandwidth selection. This function works also on OIS interface (SPI2_CTRL2_OIS = UI_CTRL2_OIS).[set]
5571 *
5572 * @param ctx read / write interface definitions
5573 * @param val OIS_GY_LP_NORMAL, OIS_GY_LP_STRONG, OIS_GY_LP_AGGRESSIVE, OIS_GY_LP_LIGHT,
5574 * @retval interface status (MANDATORY: return 0 -> no Error)
5575 *
5576 */
lsm6dsv_filt_gy_ois_lp_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsv_filt_gy_ois_lp_bandwidth_t val)5577 int32_t lsm6dsv_filt_gy_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx,
5578 lsm6dsv_filt_gy_ois_lp_bandwidth_t val)
5579 {
5580 lsm6dsv_ui_ctrl2_ois_t ui_ctrl2_ois;
5581 int32_t ret;
5582
5583 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
5584
5585 if (ret == 0)
5586 {
5587 ui_ctrl2_ois.lpf1_g_ois_bw = (uint8_t)val & 0x03U;
5588 ret = lsm6dsv_write_reg(ctx, LSM6DSV_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
5589 }
5590
5591 return ret;
5592 }
5593
5594 /**
5595 * @brief Gyroscope OIS digital LPF1 filter bandwidth selection. This function works also on OIS interface (SPI2_CTRL2_OIS = UI_CTRL2_OIS).[get]
5596 *
5597 * @param ctx read / write interface definitions
5598 * @param val OIS_GY_LP_NORMAL, OIS_GY_LP_STRONG, OIS_GY_LP_AGGRESSIVE, OIS_GY_LP_LIGHT,
5599 * @retval interface status (MANDATORY: return 0 -> no Error)
5600 *
5601 */
lsm6dsv_filt_gy_ois_lp_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsv_filt_gy_ois_lp_bandwidth_t * val)5602 int32_t lsm6dsv_filt_gy_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx,
5603 lsm6dsv_filt_gy_ois_lp_bandwidth_t *val)
5604 {
5605
5606 lsm6dsv_ui_ctrl2_ois_t ui_ctrl2_ois;
5607 int32_t ret;
5608
5609 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
5610 if (ret != 0)
5611 {
5612 return ret;
5613 }
5614
5615 switch (ui_ctrl2_ois.lpf1_g_ois_bw)
5616 {
5617 case LSM6DSV_OIS_GY_LP_NORMAL:
5618 *val = LSM6DSV_OIS_GY_LP_NORMAL;
5619 break;
5620
5621 case LSM6DSV_OIS_GY_LP_STRONG:
5622 *val = LSM6DSV_OIS_GY_LP_STRONG;
5623 break;
5624
5625 case LSM6DSV_OIS_GY_LP_AGGRESSIVE:
5626 *val = LSM6DSV_OIS_GY_LP_AGGRESSIVE;
5627 break;
5628
5629 case LSM6DSV_OIS_GY_LP_LIGHT:
5630 *val = LSM6DSV_OIS_GY_LP_LIGHT;
5631 break;
5632
5633 default:
5634 *val = LSM6DSV_OIS_GY_LP_NORMAL;
5635 break;
5636 }
5637
5638 return ret;
5639 }
5640
5641 /**
5642 * @brief Selects accelerometer OIS channel bandwidth. This function works also on OIS interface (SPI2_CTRL3_OIS = UI_CTRL3_OIS).[set]
5643 *
5644 * @param ctx read / write interface definitions
5645 * @param val OIS_XL_LP_ULTRA_LIGHT, OIS_XL_LP_VERY_LIGHT, OIS_XL_LP_LIGHT, OIS_XL_LP_NORMAL, OIS_XL_LP_STRONG, OIS_XL_LP_VERY_STRONG, OIS_XL_LP_AGGRESSIVE, OIS_XL_LP_XTREME,
5646 * @retval interface status (MANDATORY: return 0 -> no Error)
5647 *
5648 */
lsm6dsv_filt_xl_ois_lp_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsv_filt_xl_ois_lp_bandwidth_t val)5649 int32_t lsm6dsv_filt_xl_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx,
5650 lsm6dsv_filt_xl_ois_lp_bandwidth_t val)
5651 {
5652 lsm6dsv_ui_ctrl3_ois_t ui_ctrl3_ois;
5653 int32_t ret;
5654
5655 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
5656
5657 if (ret == 0)
5658 {
5659 ui_ctrl3_ois.lpf_xl_ois_bw = (uint8_t)val & 0x07U;
5660 ret = lsm6dsv_write_reg(ctx, LSM6DSV_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
5661 }
5662
5663 return ret;
5664 }
5665
5666 /**
5667 * @brief Selects accelerometer OIS channel bandwidth. This function works also on OIS interface (SPI2_CTRL3_OIS = UI_CTRL3_OIS).[get]
5668 *
5669 * @param ctx read / write interface definitions
5670 * @param val OIS_XL_LP_ULTRA_LIGHT, OIS_XL_LP_VERY_LIGHT, OIS_XL_LP_LIGHT, OIS_XL_LP_NORMAL, OIS_XL_LP_STRONG, OIS_XL_LP_VERY_STRONG, OIS_XL_LP_AGGRESSIVE, OIS_XL_LP_XTREME,
5671 * @retval interface status (MANDATORY: return 0 -> no Error)
5672 *
5673 */
lsm6dsv_filt_xl_ois_lp_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsv_filt_xl_ois_lp_bandwidth_t * val)5674 int32_t lsm6dsv_filt_xl_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx,
5675 lsm6dsv_filt_xl_ois_lp_bandwidth_t *val)
5676 {
5677 lsm6dsv_ui_ctrl3_ois_t ui_ctrl3_ois;
5678 int32_t ret;
5679
5680 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
5681 if (ret != 0)
5682 {
5683 return ret;
5684 }
5685
5686 switch (ui_ctrl3_ois.lpf_xl_ois_bw)
5687 {
5688 case LSM6DSV_OIS_XL_LP_ULTRA_LIGHT:
5689 *val = LSM6DSV_OIS_XL_LP_ULTRA_LIGHT;
5690 break;
5691
5692 case LSM6DSV_OIS_XL_LP_VERY_LIGHT:
5693 *val = LSM6DSV_OIS_XL_LP_VERY_LIGHT;
5694 break;
5695
5696 case LSM6DSV_OIS_XL_LP_LIGHT:
5697 *val = LSM6DSV_OIS_XL_LP_LIGHT;
5698 break;
5699
5700 case LSM6DSV_OIS_XL_LP_NORMAL:
5701 *val = LSM6DSV_OIS_XL_LP_NORMAL;
5702 break;
5703
5704 case LSM6DSV_OIS_XL_LP_STRONG:
5705 *val = LSM6DSV_OIS_XL_LP_STRONG;
5706 break;
5707
5708 case LSM6DSV_OIS_XL_LP_VERY_STRONG:
5709 *val = LSM6DSV_OIS_XL_LP_VERY_STRONG;
5710 break;
5711
5712 case LSM6DSV_OIS_XL_LP_AGGRESSIVE:
5713 *val = LSM6DSV_OIS_XL_LP_AGGRESSIVE;
5714 break;
5715
5716 case LSM6DSV_OIS_XL_LP_XTREME:
5717 *val = LSM6DSV_OIS_XL_LP_XTREME;
5718 break;
5719
5720 default:
5721 *val = LSM6DSV_OIS_XL_LP_ULTRA_LIGHT;
5722 break;
5723 }
5724
5725 return ret;
5726 }
5727
5728 /**
5729 * @}
5730 *
5731 */
5732
5733 /**
5734 * @defgroup Finite State Machine (FSM)
5735 * @brief This section groups all the functions that manage the
5736 * state_machine.
5737 * @{
5738 *
5739 */
5740
5741 /**
5742 * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[set]
5743 *
5744 * @param ctx read / write interface definitions
5745 * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG,
5746 * @retval interface status (MANDATORY: return 0 -> no Error)
5747 *
5748 */
lsm6dsv_fsm_permission_set(const stmdev_ctx_t * ctx,lsm6dsv_fsm_permission_t val)5749 int32_t lsm6dsv_fsm_permission_set(const stmdev_ctx_t *ctx,
5750 lsm6dsv_fsm_permission_t val)
5751 {
5752 lsm6dsv_func_cfg_access_t func_cfg_access;
5753 int32_t ret;
5754
5755 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
5756
5757 if (ret == 0)
5758 {
5759 func_cfg_access.fsm_wr_ctrl_en = (uint8_t)val & 0x01U;
5760 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
5761 }
5762
5763 return ret;
5764 }
5765
5766 /**
5767 * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[get]
5768 *
5769 * @param ctx read / write interface definitions
5770 * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG,
5771 * @retval interface status (MANDATORY: return 0 -> no Error)
5772 *
5773 */
lsm6dsv_fsm_permission_get(const stmdev_ctx_t * ctx,lsm6dsv_fsm_permission_t * val)5774 int32_t lsm6dsv_fsm_permission_get(const stmdev_ctx_t *ctx,
5775 lsm6dsv_fsm_permission_t *val)
5776 {
5777 lsm6dsv_func_cfg_access_t func_cfg_access;
5778 int32_t ret;
5779
5780 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
5781 if (ret != 0)
5782 {
5783 return ret;
5784 }
5785
5786 switch (func_cfg_access.fsm_wr_ctrl_en)
5787 {
5788 case LSM6DSV_PROTECT_CTRL_REGS:
5789 *val = LSM6DSV_PROTECT_CTRL_REGS;
5790 break;
5791
5792 case LSM6DSV_WRITE_CTRL_REG:
5793 *val = LSM6DSV_WRITE_CTRL_REG;
5794 break;
5795
5796 default:
5797 *val = LSM6DSV_PROTECT_CTRL_REGS;
5798 break;
5799 }
5800
5801 return ret;
5802 }
5803
5804 /**
5805 * @brief Get the FSM permission status
5806 *
5807 * @param ctx read / write interface definitions
5808 * @param val 0: All reg writable from std if - 1: some regs are under FSM control.
5809 * @retval interface status (MANDATORY: return 0 -> no Error)
5810 *
5811 */
lsm6dsv_fsm_permission_status(const stmdev_ctx_t * ctx,uint8_t * val)5812 int32_t lsm6dsv_fsm_permission_status(const stmdev_ctx_t *ctx, uint8_t *val)
5813 {
5814 lsm6dsv_ctrl_status_t ctrl_status;
5815 int32_t ret;
5816
5817 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL_STATUS, (uint8_t *)&ctrl_status, 1);
5818
5819 *val = ctrl_status.fsm_wr_ctrl_status;
5820
5821 return ret;
5822 }
5823
5824 /**
5825 * @brief Enable Finite State Machine (FSM) feature.[set]
5826 *
5827 * @param ctx read / write interface definitions
5828 * @param val Enable Finite State Machine (FSM) feature.
5829 * @retval interface status (MANDATORY: return 0 -> no Error)
5830 *
5831 */
lsm6dsv_fsm_mode_set(const stmdev_ctx_t * ctx,lsm6dsv_fsm_mode_t val)5832 int32_t lsm6dsv_fsm_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_fsm_mode_t val)
5833 {
5834 lsm6dsv_emb_func_en_b_t emb_func_en_b;
5835 lsm6dsv_fsm_enable_t fsm_enable;
5836 int32_t ret;
5837
5838 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
5839 if (ret != 0)
5840 {
5841 return ret;
5842 }
5843
5844 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
5845 ret += lsm6dsv_read_reg(ctx, LSM6DSV_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
5846 if (ret != 0)
5847 {
5848 goto exit;
5849 }
5850
5851 if ((val.fsm1_en | val.fsm2_en | val.fsm3_en | val.fsm4_en
5852 | val.fsm5_en | val.fsm6_en | val.fsm7_en | val.fsm8_en) == PROPERTY_ENABLE)
5853 {
5854 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
5855 }
5856 else
5857 {
5858 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
5859 }
5860
5861 fsm_enable.fsm1_en = val.fsm1_en;
5862 fsm_enable.fsm2_en = val.fsm2_en;
5863 fsm_enable.fsm3_en = val.fsm3_en;
5864 fsm_enable.fsm4_en = val.fsm4_en;
5865 fsm_enable.fsm5_en = val.fsm5_en;
5866 fsm_enable.fsm6_en = val.fsm6_en;
5867 fsm_enable.fsm7_en = val.fsm7_en;
5868 fsm_enable.fsm8_en = val.fsm8_en;
5869
5870 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
5871 ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
5872
5873 exit:
5874 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
5875
5876 return ret;
5877 }
5878
5879 /**
5880 * @brief Enable Finite State Machine (FSM) feature.[get]
5881 *
5882 * @param ctx read / write interface definitions
5883 * @param val Enable Finite State Machine (FSM) feature.
5884 * @retval interface status (MANDATORY: return 0 -> no Error)
5885 *
5886 */
lsm6dsv_fsm_mode_get(const stmdev_ctx_t * ctx,lsm6dsv_fsm_mode_t * val)5887 int32_t lsm6dsv_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_mode_t *val)
5888 {
5889 lsm6dsv_fsm_enable_t fsm_enable;
5890 int32_t ret;
5891
5892 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
5893 ret += lsm6dsv_read_reg(ctx, LSM6DSV_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
5894 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
5895 if (ret != 0)
5896 {
5897 return ret;
5898 }
5899
5900 val->fsm1_en = fsm_enable.fsm1_en;
5901 val->fsm2_en = fsm_enable.fsm2_en;
5902 val->fsm3_en = fsm_enable.fsm3_en;
5903 val->fsm4_en = fsm_enable.fsm4_en;
5904 val->fsm5_en = fsm_enable.fsm5_en;
5905 val->fsm6_en = fsm_enable.fsm6_en;
5906 val->fsm7_en = fsm_enable.fsm7_en;
5907 val->fsm8_en = fsm_enable.fsm8_en;
5908
5909 return ret;
5910 }
5911
5912 /**
5913 * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[set]
5914 *
5915 * @param ctx read / write interface definitions
5916 * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).
5917 * @retval interface status (MANDATORY: return 0 -> no Error)
5918 *
5919 */
lsm6dsv_fsm_long_cnt_set(const stmdev_ctx_t * ctx,uint16_t val)5920 int32_t lsm6dsv_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val)
5921 {
5922 uint8_t buff[2];
5923 int32_t ret;
5924
5925 buff[1] = (uint8_t)(val / 256U);
5926 buff[0] = (uint8_t)(val - (buff[1] * 256U));
5927
5928 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
5929 ret += lsm6dsv_write_reg(ctx, LSM6DSV_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2);
5930 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
5931
5932 return ret;
5933 }
5934
5935 /**
5936 * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[get]
5937 *
5938 * @param ctx read / write interface definitions
5939 * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).
5940 * @retval interface status (MANDATORY: return 0 -> no Error)
5941 *
5942 */
lsm6dsv_fsm_long_cnt_get(const stmdev_ctx_t * ctx,uint16_t * val)5943 int32_t lsm6dsv_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val)
5944 {
5945 uint8_t buff[2];
5946 int32_t ret;
5947
5948 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
5949 ret += lsm6dsv_read_reg(ctx, LSM6DSV_FSM_LONG_COUNTER_L, &buff[0], 2);
5950 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
5951 if (ret != 0)
5952 {
5953 return ret;
5954 }
5955
5956 *val = buff[1];
5957 *val = (*val * 256U) + buff[0];
5958
5959 return ret;
5960 }
5961
5962 /**
5963 * @brief FSM output registers[get]
5964 *
5965 * @param ctx read / write interface definitions
5966 * @param val FSM output registers
5967 * @retval interface status (MANDATORY: return 0 -> no Error)
5968 *
5969 */
lsm6dsv_fsm_out_get(const stmdev_ctx_t * ctx,lsm6dsv_fsm_out_t * val)5970 int32_t lsm6dsv_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_out_t *val)
5971 {
5972 int32_t ret;
5973
5974 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
5975 ret += lsm6dsv_read_reg(ctx, LSM6DSV_FSM_OUTS1, (uint8_t *)val, 8);
5976 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
5977
5978 return ret;
5979 }
5980
5981 /**
5982 * @brief Finite State Machine Output Data Rate (ODR) configuration.[set]
5983 *
5984 * @param ctx read / write interface definitions
5985 * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz,
5986 * @retval interface status (MANDATORY: return 0 -> no Error)
5987 *
5988 */
lsm6dsv_fsm_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv_fsm_data_rate_t val)5989 int32_t lsm6dsv_fsm_data_rate_set(const stmdev_ctx_t *ctx,
5990 lsm6dsv_fsm_data_rate_t val)
5991 {
5992 lsm6dsv_fsm_odr_t fsm_odr;
5993 int32_t ret;
5994
5995 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
5996 ret += lsm6dsv_read_reg(ctx, LSM6DSV_FSM_ODR, (uint8_t *)&fsm_odr, 1);
5997 if (ret != 0)
5998 {
5999 goto exit;
6000 }
6001
6002 fsm_odr.fsm_odr = (uint8_t)val & 0x07U;
6003 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FSM_ODR, (uint8_t *)&fsm_odr, 1);
6004
6005 exit:
6006 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
6007
6008 return ret;
6009 }
6010
6011 /**
6012 * @brief Finite State Machine Output Data Rate (ODR) configuration.[get]
6013 *
6014 * @param ctx read / write interface definitions
6015 * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz,
6016 * @retval interface status (MANDATORY: return 0 -> no Error)
6017 *
6018 */
lsm6dsv_fsm_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv_fsm_data_rate_t * val)6019 int32_t lsm6dsv_fsm_data_rate_get(const stmdev_ctx_t *ctx,
6020 lsm6dsv_fsm_data_rate_t *val)
6021 {
6022 lsm6dsv_fsm_odr_t fsm_odr;
6023 int32_t ret;
6024
6025 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
6026 ret += lsm6dsv_read_reg(ctx, LSM6DSV_FSM_ODR, (uint8_t *)&fsm_odr, 1);
6027 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
6028 if (ret != 0)
6029 {
6030 return ret;
6031 }
6032
6033 switch (fsm_odr.fsm_odr)
6034 {
6035 case LSM6DSV_FSM_15Hz:
6036 *val = LSM6DSV_FSM_15Hz;
6037 break;
6038
6039 case LSM6DSV_FSM_30Hz:
6040 *val = LSM6DSV_FSM_30Hz;
6041 break;
6042
6043 case LSM6DSV_FSM_60Hz:
6044 *val = LSM6DSV_FSM_60Hz;
6045 break;
6046
6047 case LSM6DSV_FSM_120Hz:
6048 *val = LSM6DSV_FSM_120Hz;
6049 break;
6050
6051 case LSM6DSV_FSM_240Hz:
6052 *val = LSM6DSV_FSM_240Hz;
6053 break;
6054
6055 case LSM6DSV_FSM_480Hz:
6056 *val = LSM6DSV_FSM_480Hz;
6057 break;
6058
6059 case LSM6DSV_FSM_960Hz:
6060 *val = LSM6DSV_FSM_960Hz;
6061 break;
6062
6063 default:
6064 *val = LSM6DSV_FSM_15Hz;
6065 break;
6066 }
6067
6068 return ret;
6069 }
6070
6071 /*
6072 * Original conversion routines taken from: https://github.com/numpy/numpy
6073 *
6074 * uint16_t npy_floatbits_to_halfbits(uint32_t f);
6075 * uint16_t npy_float_to_half(float_t f);
6076 *
6077 * Released under BSD-3-Clause License
6078 */
6079
6080 #define NPY_HALF_GENERATE_OVERFLOW 0 /* do not trigger FP overflow */
6081 #define NPY_HALF_GENERATE_UNDERFLOW 0 /* do not trigger FP underflow */
6082 #ifndef NPY_HALF_ROUND_TIES_TO_EVEN
6083 #define NPY_HALF_ROUND_TIES_TO_EVEN 1
6084 #endif
6085
npy_floatbits_to_halfbits(uint32_t f)6086 static uint16_t npy_floatbits_to_halfbits(uint32_t f)
6087 {
6088 uint32_t f_exp, f_sig;
6089 uint16_t h_sgn, h_exp, h_sig;
6090
6091 h_sgn = (uint16_t)((f & 0x80000000u) >> 16);
6092 f_exp = (f & 0x7f800000u);
6093
6094 /* Exponent overflow/NaN converts to signed inf/NaN */
6095 if (f_exp >= 0x47800000u)
6096 {
6097 if (f_exp == 0x7f800000u)
6098 {
6099 /* Inf or NaN */
6100 f_sig = (f & 0x007fffffu);
6101 if (f_sig != 0U)
6102 {
6103 /* NaN - propagate the flag in the significand... */
6104 uint16_t ret = (uint16_t)(0x7c00u + (f_sig >> 13));
6105 /* ...but make sure it stays a NaN */
6106 if (ret == 0x7c00u)
6107 {
6108 ret++;
6109 }
6110 return h_sgn + ret;
6111 }
6112 else
6113 {
6114 /* signed inf */
6115 return (uint16_t)(h_sgn + 0x7c00u);
6116 }
6117 }
6118 else
6119 {
6120 /* overflow to signed inf */
6121 #if NPY_HALF_GENERATE_OVERFLOW
6122 npy_set_floatstatus_overflow();
6123 #endif
6124 return (uint16_t)(h_sgn + 0x7c00u);
6125 }
6126 }
6127
6128 /* Exponent underflow converts to a subnormal half or signed zero */
6129 if (f_exp <= 0x38000000u)
6130 {
6131 /*
6132 * Signed zeros, subnormal floats, and floats with small
6133 * exponents all convert to signed zero half-floats.
6134 */
6135 if (f_exp < 0x33000000u)
6136 {
6137 #if NPY_HALF_GENERATE_UNDERFLOW
6138 /* If f != 0, it underflowed to 0 */
6139 if ((f & 0x7fffffff) != 0)
6140 {
6141 npy_set_floatstatus_underflow();
6142 }
6143 #endif
6144 return h_sgn;
6145 }
6146 /* Make the subnormal significand */
6147 f_exp >>= 23;
6148 f_sig = (0x00800000u + (f & 0x007fffffu));
6149 #if NPY_HALF_GENERATE_UNDERFLOW
6150 /* If it's not exactly represented, it underflowed */
6151 if ((f_sig & (((uint32_t)1 << (126 - f_exp)) - 1)) != 0)
6152 {
6153 npy_set_floatstatus_underflow();
6154 }
6155 #endif
6156 /*
6157 * Usually the significand is shifted by 13. For subnormals an
6158 * additional shift needs to occur. This shift is one for the largest
6159 * exponent giving a subnormal `f_exp = 0x38000000 >> 23 = 112`, which
6160 * offsets the new first bit. At most the shift can be 1+10 bits.
6161 */
6162 f_sig >>= (113U - f_exp);
6163 /* Handle rounding by adding 1 to the bit beyond half precision */
6164 #if NPY_HALF_ROUND_TIES_TO_EVEN
6165 /*
6166 * If the last bit in the half significand is 0 (already even), and
6167 * the remaining bit pattern is 1000...0, then we do not add one
6168 * to the bit after the half significand. However, the (113 - f_exp)
6169 * shift can lose up to 11 bits, so the || checks them in the original.
6170 * In all other cases, we can just add one.
6171 */
6172 if (((f_sig & 0x00003fffu) != 0x00001000u) || (f & 0x000007ffu))
6173 {
6174 f_sig += 0x00001000u;
6175 }
6176 #else
6177 f_sig += 0x00001000u;
6178 #endif
6179 h_sig = (uint16_t)(f_sig >> 13);
6180 /*
6181 * If the rounding causes a bit to spill into h_exp, it will
6182 * increment h_exp from zero to one and h_sig will be zero.
6183 * This is the correct result.
6184 */
6185 return (uint16_t)(h_sgn + h_sig);
6186 }
6187
6188 /* Regular case with no overflow or underflow */
6189 h_exp = (uint16_t)((f_exp - 0x38000000u) >> 13);
6190 /* Handle rounding by adding 1 to the bit beyond half precision */
6191 f_sig = (f & 0x007fffffu);
6192 #if NPY_HALF_ROUND_TIES_TO_EVEN
6193 /*
6194 * If the last bit in the half significand is 0 (already even), and
6195 * the remaining bit pattern is 1000...0, then we do not add one
6196 * to the bit after the half significand. In all other cases, we do.
6197 */
6198 if ((f_sig & 0x00003fffu) != 0x00001000u)
6199 {
6200 f_sig += 0x00001000u;
6201 }
6202 #else
6203 f_sig += 0x00001000u;
6204 #endif
6205 h_sig = (uint16_t)(f_sig >> 13);
6206 /*
6207 * If the rounding causes a bit to spill into h_exp, it will
6208 * increment h_exp by one and h_sig will be zero. This is the
6209 * correct result. h_exp may increment to 15, at greatest, in
6210 * which case the result overflows to a signed inf.
6211 */
6212 #if NPY_HALF_GENERATE_OVERFLOW
6213 h_sig += h_exp;
6214 if (h_sig == 0x7c00u)
6215 {
6216 npy_set_floatstatus_overflow();
6217 }
6218 return h_sgn + h_sig;
6219 #else
6220 return h_sgn + h_exp + h_sig;
6221 #endif
6222 }
6223
npy_float_to_half(float_t f)6224 static uint16_t npy_float_to_half(float_t f)
6225 {
6226 union
6227 {
6228 float_t f;
6229 uint32_t fbits;
6230 } conv;
6231 conv.f = f;
6232 return npy_floatbits_to_halfbits(conv.fbits);
6233 }
6234
6235 /**
6236 * @brief SFLP GBIAS value. The register value is expressed as half-precision
6237 * floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent
6238 * bits; F: 10 fraction bits).[set]
6239 *
6240 * @param ctx read / write interface definitions
6241 * @param val GBIAS x/y/z val.
6242 * @retval interface status (MANDATORY: return 0 -> no Error)
6243 *
6244 */
lsm6dsv_sflp_game_gbias_set(const stmdev_ctx_t * ctx,lsm6dsv_sflp_gbias_t * val)6245 int32_t lsm6dsv_sflp_game_gbias_set(const stmdev_ctx_t *ctx,
6246 lsm6dsv_sflp_gbias_t *val)
6247 {
6248 lsm6dsv_sflp_data_rate_t sflp_odr;
6249 lsm6dsv_emb_func_exec_status_t emb_func_sts;
6250 lsm6dsv_data_ready_t drdy;
6251 lsm6dsv_xl_full_scale_t xl_fs;
6252 lsm6dsv_ctrl10_t ctrl10;
6253 uint8_t master_config;
6254 uint8_t emb_func_en_saved[2];
6255 uint8_t conf_saved[2];
6256 uint8_t reg_zero[2] = {0x0, 0x0};
6257 uint16_t gbias_hf[3];
6258 float_t k = 0.005f;
6259 int16_t xl_data[3];
6260 int32_t data_tmp;
6261 uint8_t *data_ptr = (uint8_t *)&data_tmp;
6262 uint8_t i, j;
6263 int32_t ret;
6264
6265 ret = lsm6dsv_sflp_data_rate_get(ctx, &sflp_odr);
6266 if (ret != 0)
6267 {
6268 return ret;
6269 }
6270
6271 /* Calculate k factor */
6272 switch (sflp_odr)
6273 {
6274 default:
6275 case LSM6DSV_SFLP_15Hz:
6276 k = 0.04f;
6277 break;
6278 case LSM6DSV_SFLP_30Hz:
6279 k = 0.02f;
6280 break;
6281 case LSM6DSV_SFLP_60Hz:
6282 k = 0.01f;
6283 break;
6284 case LSM6DSV_SFLP_120Hz:
6285 k = 0.005f;
6286 break;
6287 case LSM6DSV_SFLP_240Hz:
6288 k = 0.0025f;
6289 break;
6290 case LSM6DSV_SFLP_480Hz:
6291 k = 0.00125f;
6292 break;
6293 }
6294
6295 /* compute gbias as half precision float in order to be put in embedded advanced feature register */
6296 gbias_hf[0] = npy_float_to_half(val->gbias_x * (3.14159265358979323846f / 180.0f) / k);
6297 gbias_hf[1] = npy_float_to_half(val->gbias_y * (3.14159265358979323846f / 180.0f) / k);
6298 gbias_hf[2] = npy_float_to_half(val->gbias_z * (3.14159265358979323846f / 180.0f) / k);
6299
6300 /* Save sensor configuration and set high-performance mode (if the sensor is in power-down mode, turn it on) */
6301 ret += lsm6dsv_read_reg(ctx, LSM6DSV_CTRL1, conf_saved, 2);
6302 ret += lsm6dsv_xl_mode_set(ctx, LSM6DSV_XL_HIGH_PERFORMANCE_MD);
6303 ret += lsm6dsv_gy_mode_set(ctx, LSM6DSV_GY_HIGH_PERFORMANCE_MD);
6304 if (((uint8_t)conf_saved[0] & 0x0FU) == (uint8_t)LSM6DSV_ODR_OFF)
6305 {
6306 ret += lsm6dsv_xl_data_rate_set(ctx, LSM6DSV_ODR_AT_120Hz);
6307 }
6308
6309 /* Make sure to turn the sensor-hub master off */
6310 ret += lsm6dsv_sh_master_get(ctx, &master_config);
6311 ret += lsm6dsv_sh_master_set(ctx, 0);
6312
6313 /* disable algos */
6314 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
6315 ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, emb_func_en_saved, 2);
6316 ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, reg_zero, 2);
6317 do
6318 {
6319 ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EXEC_STATUS,
6320 (uint8_t *)&emb_func_sts, 1);
6321 } while (emb_func_sts.emb_func_endop != 1U);
6322 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
6323
6324 // enable gbias setting
6325 ret += lsm6dsv_read_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1);
6326 ctrl10.emb_func_debug = 1;
6327 ret += lsm6dsv_write_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1);
6328
6329 /* enable algos */
6330 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
6331 emb_func_en_saved[0] |= 0x02U; /* force SFLP GAME en */
6332 ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, emb_func_en_saved,
6333 2);
6334 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
6335
6336 ret += lsm6dsv_xl_full_scale_get(ctx, &xl_fs);
6337
6338 /* Read XL data */
6339 do
6340 {
6341 ret += lsm6dsv_flag_data_ready_get(ctx, &drdy);
6342 } while (drdy.drdy_xl != 1U);
6343 ret += lsm6dsv_acceleration_raw_get(ctx, xl_data);
6344
6345 /* force sflp initialization */
6346 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
6347 for (i = 0; i < 3U; i++)
6348 {
6349 j = 0;
6350 data_tmp = (int32_t)xl_data[i];
6351 data_tmp <<= xl_fs; // shift based on current fs
6352 ret += lsm6dsv_write_reg(ctx, LSM6DSV_SENSOR_HUB_1 + 3U * i,
6353 &data_ptr[j++], 1);
6354 ret += lsm6dsv_write_reg(ctx, LSM6DSV_SENSOR_HUB_2 + 3U * i,
6355 &data_ptr[j++], 1);
6356 ret += lsm6dsv_write_reg(ctx, LSM6DSV_SENSOR_HUB_3 + 3U * i, &data_ptr[j],
6357 1);
6358 }
6359 for (i = 0; i < 3U; i++)
6360 {
6361 j = 0;
6362 data_tmp = 0;
6363 ret += lsm6dsv_write_reg(ctx, LSM6DSV_SENSOR_HUB_10 + 3U * i,
6364 &data_ptr[j++], 1);
6365 ret += lsm6dsv_write_reg(ctx, LSM6DSV_SENSOR_HUB_11 + 3U * i,
6366 &data_ptr[j++], 1);
6367 ret += lsm6dsv_write_reg(ctx, LSM6DSV_SENSOR_HUB_12 + 3U * i, &data_ptr[j],
6368 1);
6369 }
6370 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
6371
6372 // wait end_op (and at least 30 us)
6373 ctx->mdelay(1);
6374 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
6375 do
6376 {
6377 ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EXEC_STATUS,
6378 (uint8_t *)&emb_func_sts, 1);
6379 } while (emb_func_sts.emb_func_endop != 1U);
6380 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
6381
6382 /* write gbias in embedded advanced features registers */
6383 ret += lsm6dsv_ln_pg_write(ctx, LSM6DSV_SFLP_GAME_GBIASX_L,
6384 (uint8_t *)gbias_hf, 6);
6385
6386 /* reload previous sensor configuration */
6387 ret += lsm6dsv_write_reg(ctx, LSM6DSV_CTRL1, conf_saved, 2);
6388
6389 // disable gbias setting
6390 ctrl10.emb_func_debug = 0;
6391 ret += lsm6dsv_write_reg(ctx, LSM6DSV_CTRL10, (uint8_t *)&ctrl10, 1);
6392
6393 /* reload previous master configuration */
6394 ret += lsm6dsv_sh_master_set(ctx, master_config);
6395
6396 return ret;
6397 }
6398
6399 /**
6400 * @brief External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).[set]
6401 *
6402 * @param ctx read / write interface definitions
6403 * @param val External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).
6404 * @retval interface status (MANDATORY: return 0 -> no Error)
6405 *
6406 */
lsm6dsv_fsm_ext_sens_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)6407 int32_t lsm6dsv_fsm_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val)
6408 {
6409 uint8_t buff[2];
6410 int32_t ret;
6411
6412 buff[1] = (uint8_t)(val / 256U);
6413 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6414 ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_FSM_EXT_SENSITIVITY_L, (uint8_t *)&buff[0], 2);
6415
6416 return ret;
6417 }
6418
6419 /**
6420 * @brief External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).[get]
6421 *
6422 * @param ctx read / write interface definitions
6423 * @param val External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).
6424 * @retval interface status (MANDATORY: return 0 -> no Error)
6425 *
6426 */
lsm6dsv_fsm_ext_sens_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)6427 int32_t lsm6dsv_fsm_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx,
6428 uint16_t *val)
6429 {
6430 uint8_t buff[2];
6431 int32_t ret;
6432
6433 ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_FSM_EXT_SENSITIVITY_L, &buff[0], 2);
6434 if (ret != 0)
6435 {
6436 return ret;
6437 }
6438
6439 *val = buff[1];
6440 *val = (*val * 256U) + buff[0];
6441
6442 return ret;
6443 }
6444
6445 /**
6446 * @brief External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set]
6447 *
6448 * @param ctx read / write interface definitions
6449 * @param val External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
6450 * @retval interface status (MANDATORY: return 0 -> no Error)
6451 *
6452 */
lsm6dsv_fsm_ext_sens_offset_set(const stmdev_ctx_t * ctx,lsm6dsv_xl_fsm_ext_sens_offset_t val)6453 int32_t lsm6dsv_fsm_ext_sens_offset_set(const stmdev_ctx_t *ctx,
6454 lsm6dsv_xl_fsm_ext_sens_offset_t val)
6455 {
6456 uint8_t buff[6];
6457 int32_t ret;
6458
6459 buff[1] = (uint8_t)(val.x / 256U);
6460 buff[0] = (uint8_t)(val.x - (buff[1] * 256U));
6461 buff[3] = (uint8_t)(val.y / 256U);
6462 buff[2] = (uint8_t)(val.y - (buff[3] * 256U));
6463 buff[5] = (uint8_t)(val.z / 256U);
6464 buff[4] = (uint8_t)(val.z - (buff[5] * 256U));
6465 ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_FSM_EXT_OFFX_L, (uint8_t *)&buff[0], 6);
6466
6467 return ret;
6468 }
6469
6470 /**
6471 * @brief External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get]
6472 *
6473 * @param ctx read / write interface definitions
6474 * @param val External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
6475 * @retval interface status (MANDATORY: return 0 -> no Error)
6476 *
6477 */
lsm6dsv_fsm_ext_sens_offset_get(const stmdev_ctx_t * ctx,lsm6dsv_xl_fsm_ext_sens_offset_t * val)6478 int32_t lsm6dsv_fsm_ext_sens_offset_get(const stmdev_ctx_t *ctx,
6479 lsm6dsv_xl_fsm_ext_sens_offset_t *val)
6480 {
6481 uint8_t buff[6];
6482 int32_t ret;
6483
6484 ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_FSM_EXT_OFFX_L, &buff[0], 6);
6485 if (ret != 0)
6486 {
6487 return ret;
6488 }
6489
6490 val->x = buff[1];
6491 val->x = (val->x * 256U) + buff[0];
6492 val->y = buff[3];
6493 val->y = (val->y * 256U) + buff[2];
6494 val->z = buff[5];
6495 val->z = (val->z * 256U) + buff[4];
6496
6497 return ret;
6498 }
6499
6500 /**
6501 * @brief External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set]
6502 *
6503 * @param ctx read / write interface definitions
6504 * @param val External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
6505 * @retval interface status (MANDATORY: return 0 -> no Error)
6506 *
6507 */
lsm6dsv_fsm_ext_sens_matrix_set(const stmdev_ctx_t * ctx,lsm6dsv_xl_fsm_ext_sens_matrix_t val)6508 int32_t lsm6dsv_fsm_ext_sens_matrix_set(const stmdev_ctx_t *ctx,
6509 lsm6dsv_xl_fsm_ext_sens_matrix_t val)
6510 {
6511 uint8_t buff[12];
6512 int32_t ret;
6513
6514 buff[1] = (uint8_t)(val.xx / 256U);
6515 buff[0] = (uint8_t)(val.xx - (buff[1] * 256U));
6516 buff[3] = (uint8_t)(val.xy / 256U);
6517 buff[2] = (uint8_t)(val.xy - (buff[3] * 256U));
6518 buff[5] = (uint8_t)(val.xz / 256U);
6519 buff[4] = (uint8_t)(val.xz - (buff[5] * 256U));
6520 buff[7] = (uint8_t)(val.yy / 256U);
6521 buff[6] = (uint8_t)(val.yy - (buff[7] * 256U));
6522 buff[9] = (uint8_t)(val.yz / 256U);
6523 buff[8] = (uint8_t)(val.yz - (buff[9] * 256U));
6524 buff[11] = (uint8_t)(val.zz / 256U);
6525 buff[10] = (uint8_t)(val.zz - (buff[11] * 256U));
6526 ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_FSM_EXT_MATRIX_XX_L, (uint8_t *)&buff[0], 12);
6527
6528 return ret;
6529 }
6530
6531 /**
6532 * @brief External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get]
6533 *
6534 * @param ctx read / write interface definitions
6535 * @param val External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
6536 * @retval interface status (MANDATORY: return 0 -> no Error)
6537 *
6538 */
lsm6dsv_fsm_ext_sens_matrix_get(const stmdev_ctx_t * ctx,lsm6dsv_xl_fsm_ext_sens_matrix_t * val)6539 int32_t lsm6dsv_fsm_ext_sens_matrix_get(const stmdev_ctx_t *ctx,
6540 lsm6dsv_xl_fsm_ext_sens_matrix_t *val)
6541 {
6542 uint8_t buff[12];
6543 int32_t ret;
6544
6545 ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_FSM_EXT_MATRIX_XX_L, &buff[0], 12);
6546 if (ret != 0)
6547 {
6548 return ret;
6549 }
6550
6551 val->xx = buff[1];
6552 val->xx = (val->xx * 256U) + buff[0];
6553 val->xy = buff[3];
6554 val->xy = (val->xy * 256U) + buff[2];
6555 val->xz = buff[5];
6556 val->xz = (val->xz * 256U) + buff[4];
6557 val->yy = buff[7];
6558 val->yy = (val->yy * 256U) + buff[6];
6559 val->yz = buff[9];
6560 val->yz = (val->yz * 256U) + buff[8];
6561 val->zz = buff[11];
6562 val->zz = (val->zz * 256U) + buff[10];
6563
6564 return ret;
6565 }
6566
6567 /**
6568 * @brief External sensor z-axis coordinates rotation.[set]
6569 *
6570 * @param ctx read / write interface definitions
6571 * @param val Z_EQ_Y, Z_EQ_MIN_Y, Z_EQ_X, Z_EQ_MIN_X, Z_EQ_MIN_Z, Z_EQ_Z,
6572 * @retval interface status (MANDATORY: return 0 -> no Error)
6573 *
6574 */
lsm6dsv_fsm_ext_sens_z_orient_set(const stmdev_ctx_t * ctx,lsm6dsv_fsm_ext_sens_z_orient_t val)6575 int32_t lsm6dsv_fsm_ext_sens_z_orient_set(const stmdev_ctx_t *ctx,
6576 lsm6dsv_fsm_ext_sens_z_orient_t val)
6577 {
6578 lsm6dsv_ext_cfg_a_t ext_cfg_a;
6579 int32_t ret;
6580
6581 ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6582 ext_cfg_a.ext_z_axis = (uint8_t)val & 0x07U;
6583 ret += lsm6dsv_ln_pg_write(ctx, LSM6DSV_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6584
6585 return ret;
6586 }
6587
6588 /**
6589 * @brief External sensor z-axis coordinates rotation.[get]
6590 *
6591 * @param ctx read / write interface definitions
6592 * @param val Z_EQ_Y, Z_EQ_MIN_Y, Z_EQ_X, Z_EQ_MIN_X, Z_EQ_MIN_Z, Z_EQ_Z,
6593 * @retval interface status (MANDATORY: return 0 -> no Error)
6594 *
6595 */
lsm6dsv_fsm_ext_sens_z_orient_get(const stmdev_ctx_t * ctx,lsm6dsv_fsm_ext_sens_z_orient_t * val)6596 int32_t lsm6dsv_fsm_ext_sens_z_orient_get(const stmdev_ctx_t *ctx,
6597 lsm6dsv_fsm_ext_sens_z_orient_t *val)
6598 {
6599 lsm6dsv_ext_cfg_a_t ext_cfg_a;
6600 int32_t ret;
6601
6602 ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6603 if (ret != 0)
6604 {
6605 return ret;
6606 }
6607
6608 switch (ext_cfg_a.ext_z_axis)
6609 {
6610 case LSM6DSV_Z_EQ_Y:
6611 *val = LSM6DSV_Z_EQ_Y;
6612 break;
6613
6614 case LSM6DSV_Z_EQ_MIN_Y:
6615 *val = LSM6DSV_Z_EQ_MIN_Y;
6616 break;
6617
6618 case LSM6DSV_Z_EQ_X:
6619 *val = LSM6DSV_Z_EQ_X;
6620 break;
6621
6622 case LSM6DSV_Z_EQ_MIN_X:
6623 *val = LSM6DSV_Z_EQ_MIN_X;
6624 break;
6625
6626 case LSM6DSV_Z_EQ_MIN_Z:
6627 *val = LSM6DSV_Z_EQ_MIN_Z;
6628 break;
6629
6630 case LSM6DSV_Z_EQ_Z:
6631 *val = LSM6DSV_Z_EQ_Z;
6632 break;
6633
6634 default:
6635 *val = LSM6DSV_Z_EQ_Y;
6636 break;
6637 }
6638
6639 return ret;
6640 }
6641
6642 /**
6643 * @brief External sensor Y-axis coordinates rotation.[set]
6644 *
6645 * @param ctx read / write interface definitions
6646 * @param val Y_EQ_Y, Y_EQ_MIN_Y, Y_EQ_X, Y_EQ_MIN_X, Y_EQ_MIN_Z, Y_EQ_Z,
6647 * @retval interface status (MANDATORY: return 0 -> no Error)
6648 *
6649 */
lsm6dsv_fsm_ext_sens_y_orient_set(const stmdev_ctx_t * ctx,lsm6dsv_fsm_ext_sens_y_orient_t val)6650 int32_t lsm6dsv_fsm_ext_sens_y_orient_set(const stmdev_ctx_t *ctx,
6651 lsm6dsv_fsm_ext_sens_y_orient_t val)
6652 {
6653 lsm6dsv_ext_cfg_a_t ext_cfg_a;
6654 int32_t ret;
6655
6656 ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6657 if (ret == 0)
6658 {
6659 ext_cfg_a.ext_y_axis = (uint8_t)val & 0x7U;
6660 ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6661 }
6662
6663 return ret;
6664 }
6665
6666 /**
6667 * @brief External sensor Y-axis coordinates rotation.[get]
6668 *
6669 * @param ctx read / write interface definitions
6670 * @param val Y_EQ_Y, Y_EQ_MIN_Y, Y_EQ_X, Y_EQ_MIN_X, Y_EQ_MIN_Z, Y_EQ_Z,
6671 * @retval interface status (MANDATORY: return 0 -> no Error)
6672 *
6673 */
lsm6dsv_fsm_ext_sens_y_orient_get(const stmdev_ctx_t * ctx,lsm6dsv_fsm_ext_sens_y_orient_t * val)6674 int32_t lsm6dsv_fsm_ext_sens_y_orient_get(const stmdev_ctx_t *ctx,
6675 lsm6dsv_fsm_ext_sens_y_orient_t *val)
6676 {
6677 lsm6dsv_ext_cfg_a_t ext_cfg_a;
6678 int32_t ret;
6679
6680 ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6681 if (ret != 0)
6682 {
6683 return ret;
6684 }
6685
6686 switch (ext_cfg_a.ext_y_axis)
6687 {
6688 case LSM6DSV_Y_EQ_Y:
6689 *val = LSM6DSV_Y_EQ_Y;
6690 break;
6691
6692 case LSM6DSV_Y_EQ_MIN_Y:
6693 *val = LSM6DSV_Y_EQ_MIN_Y;
6694 break;
6695
6696 case LSM6DSV_Y_EQ_X:
6697 *val = LSM6DSV_Y_EQ_X;
6698 break;
6699
6700 case LSM6DSV_Y_EQ_MIN_X:
6701 *val = LSM6DSV_Y_EQ_MIN_X;
6702 break;
6703
6704 case LSM6DSV_Y_EQ_MIN_Z:
6705 *val = LSM6DSV_Y_EQ_MIN_Z;
6706 break;
6707
6708 case LSM6DSV_Y_EQ_Z:
6709 *val = LSM6DSV_Y_EQ_Z;
6710 break;
6711
6712 default:
6713 *val = LSM6DSV_Y_EQ_Y;
6714 break;
6715 }
6716
6717 return ret;
6718 }
6719
6720 /**
6721 * @brief External sensor X-axis coordinates rotation.[set]
6722 *
6723 * @param ctx read / write interface definitions
6724 * @param val X_EQ_Y, X_EQ_MIN_Y, X_EQ_X, X_EQ_MIN_X, X_EQ_MIN_Z, X_EQ_Z,
6725 * @retval interface status (MANDATORY: return 0 -> no Error)
6726 *
6727 */
lsm6dsv_fsm_ext_sens_x_orient_set(const stmdev_ctx_t * ctx,lsm6dsv_fsm_ext_sens_x_orient_t val)6728 int32_t lsm6dsv_fsm_ext_sens_x_orient_set(const stmdev_ctx_t *ctx,
6729 lsm6dsv_fsm_ext_sens_x_orient_t val)
6730 {
6731 lsm6dsv_ext_cfg_b_t ext_cfg_b;
6732 int32_t ret;
6733
6734 ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1);
6735 if (ret == 0)
6736 {
6737 ext_cfg_b.ext_x_axis = (uint8_t)val & 0x7U;
6738 ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1);
6739 }
6740
6741 return ret;
6742 }
6743
6744 /**
6745 * @brief External sensor X-axis coordinates rotation.[get]
6746 *
6747 * @param ctx read / write interface definitions
6748 * @param val X_EQ_Y, X_EQ_MIN_Y, X_EQ_X, X_EQ_MIN_X, X_EQ_MIN_Z, X_EQ_Z,
6749 * @retval interface status (MANDATORY: return 0 -> no Error)
6750 *
6751 */
lsm6dsv_fsm_ext_sens_x_orient_get(const stmdev_ctx_t * ctx,lsm6dsv_fsm_ext_sens_x_orient_t * val)6752 int32_t lsm6dsv_fsm_ext_sens_x_orient_get(const stmdev_ctx_t *ctx,
6753 lsm6dsv_fsm_ext_sens_x_orient_t *val)
6754 {
6755 lsm6dsv_ext_cfg_b_t ext_cfg_b;
6756 int32_t ret;
6757
6758 ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1);
6759 if (ret != 0)
6760 {
6761 return ret;
6762 }
6763
6764 switch (ext_cfg_b.ext_x_axis)
6765 {
6766 case LSM6DSV_X_EQ_Y:
6767 *val = LSM6DSV_X_EQ_Y;
6768 break;
6769
6770 case LSM6DSV_X_EQ_MIN_Y:
6771 *val = LSM6DSV_X_EQ_MIN_Y;
6772 break;
6773
6774 case LSM6DSV_X_EQ_X:
6775 *val = LSM6DSV_X_EQ_X;
6776 break;
6777
6778 case LSM6DSV_X_EQ_MIN_X:
6779 *val = LSM6DSV_X_EQ_MIN_X;
6780 break;
6781
6782 case LSM6DSV_X_EQ_MIN_Z:
6783 *val = LSM6DSV_X_EQ_MIN_Z;
6784 break;
6785
6786 case LSM6DSV_X_EQ_Z:
6787 *val = LSM6DSV_X_EQ_Z;
6788 break;
6789
6790 default:
6791 *val = LSM6DSV_X_EQ_Y;
6792 break;
6793 }
6794
6795 return ret;
6796 }
6797
6798 /**
6799 * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[set]
6800 *
6801 * @param ctx read / write interface definitions
6802 * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.
6803 * @retval interface status (MANDATORY: return 0 -> no Error)
6804 *
6805 */
lsm6dsv_fsm_long_cnt_timeout_set(const stmdev_ctx_t * ctx,uint16_t val)6806 int32_t lsm6dsv_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val)
6807 {
6808 uint8_t buff[2];
6809 int32_t ret;
6810
6811 buff[1] = (uint8_t)(val / 256U);
6812 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6813 ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_LC_TIMEOUT_L, (uint8_t *)&buff[0],
6814 2);
6815
6816 return ret;
6817 }
6818
6819 /**
6820 * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[get]
6821 *
6822 * @param ctx read / write interface definitions
6823 * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.
6824 * @retval interface status (MANDATORY: return 0 -> no Error)
6825 *
6826 */
lsm6dsv_fsm_long_cnt_timeout_get(const stmdev_ctx_t * ctx,uint16_t * val)6827 int32_t lsm6dsv_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val)
6828 {
6829 uint8_t buff[2];
6830 int32_t ret;
6831
6832 ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_LC_TIMEOUT_L, &buff[0], 2);
6833 if (ret != 0)
6834 {
6835 return ret;
6836 }
6837
6838 *val = buff[1];
6839 *val = (*val * 256U) + buff[0];
6840
6841 return ret;
6842 }
6843
6844 /**
6845 * @brief FSM number of programs.[set]
6846 *
6847 * @param ctx read / write interface definitions
6848 * @param val FSM number of programs.
6849 * @retval interface status (MANDATORY: return 0 -> no Error)
6850 *
6851 */
lsm6dsv_fsm_number_of_programs_set(const stmdev_ctx_t * ctx,uint8_t val)6852 int32_t lsm6dsv_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val)
6853 {
6854 lsm6dsv_fsm_programs_t fsm_programs;
6855 int32_t ret;
6856
6857 ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_PROGRAMS, (uint8_t *)&fsm_programs,
6858 1);
6859 if (ret == 0)
6860 {
6861 fsm_programs.fsm_n_prog = val;
6862 ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_PROGRAMS,
6863 (uint8_t *)&fsm_programs, 1);
6864 }
6865
6866 return ret;
6867 }
6868
6869 /**
6870 * @brief FSM number of programs.[get]
6871 *
6872 * @param ctx read / write interface definitions
6873 * @param val FSM number of programs.
6874 * @retval interface status (MANDATORY: return 0 -> no Error)
6875 *
6876 */
lsm6dsv_fsm_number_of_programs_get(const stmdev_ctx_t * ctx,uint8_t * val)6877 int32_t lsm6dsv_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val)
6878 {
6879 lsm6dsv_fsm_programs_t fsm_programs;
6880 int32_t ret;
6881
6882 ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_PROGRAMS, (uint8_t *)&fsm_programs,
6883 1);
6884 *val = fsm_programs.fsm_n_prog;
6885
6886 return ret;
6887 }
6888
6889 /**
6890 * @brief FSM start address. First available address is 0x35C.[set]
6891 *
6892 * @param ctx read / write interface definitions
6893 * @param val FSM start address. First available address is 0x35C.
6894 * @retval interface status (MANDATORY: return 0 -> no Error)
6895 *
6896 */
lsm6dsv_fsm_start_address_set(const stmdev_ctx_t * ctx,uint16_t val)6897 int32_t lsm6dsv_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val)
6898 {
6899 uint8_t buff[2];
6900 int32_t ret;
6901
6902 buff[1] = (uint8_t)(val / 256U);
6903 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6904 ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_START_ADD_L, (uint8_t *)&buff[0],
6905 2);
6906
6907 return ret;
6908 }
6909
6910 /**
6911 * @brief FSM start address. First available address is 0x35C.[get]
6912 *
6913 * @param ctx read / write interface definitions
6914 * @param val FSM start address. First available address is 0x35C.
6915 * @retval interface status (MANDATORY: return 0 -> no Error)
6916 *
6917 */
lsm6dsv_fsm_start_address_get(const stmdev_ctx_t * ctx,uint16_t * val)6918 int32_t lsm6dsv_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val)
6919 {
6920 uint8_t buff[2];
6921 int32_t ret;
6922
6923 ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_FSM_START_ADD_L, &buff[0], 2);
6924 if (ret != 0)
6925 {
6926 return ret;
6927 }
6928
6929 *val = buff[1];
6930 *val = (*val * 256U) + buff[0];
6931
6932 return ret;
6933 }
6934
6935 /**
6936 * @}
6937 *
6938 */
6939
6940 /**
6941 * @defgroup Free fall
6942 * @brief This section group all the functions concerning the free
6943 * fall detection.
6944 * @{
6945 *
6946 */
6947
6948 /**
6949 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set]
6950 *
6951 * @param ctx read / write interface definitions
6952 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
6953 * @retval interface status (MANDATORY: return 0 -> no Error)
6954 *
6955 */
lsm6dsv_ff_time_windows_set(const stmdev_ctx_t * ctx,uint8_t val)6956 int32_t lsm6dsv_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val)
6957 {
6958 lsm6dsv_wake_up_dur_t wake_up_dur;
6959 lsm6dsv_free_fall_t free_fall;
6960 int32_t ret;
6961
6962 ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
6963 wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
6964 ret += lsm6dsv_write_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
6965 if (ret != 0)
6966 {
6967 return ret;
6968 }
6969
6970 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FREE_FALL, (uint8_t *)&free_fall, 1);
6971 free_fall.ff_dur = (uint8_t)val & 0x1FU;
6972 ret += lsm6dsv_write_reg(ctx, LSM6DSV_FREE_FALL, (uint8_t *)&free_fall, 1);
6973
6974 return ret;
6975 }
6976
6977 /**
6978 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get]
6979 *
6980 * @param ctx read / write interface definitions
6981 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
6982 * @retval interface status (MANDATORY: return 0 -> no Error)
6983 *
6984 */
lsm6dsv_ff_time_windows_get(const stmdev_ctx_t * ctx,uint8_t * val)6985 int32_t lsm6dsv_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val)
6986 {
6987 lsm6dsv_wake_up_dur_t wake_up_dur;
6988 lsm6dsv_free_fall_t free_fall;
6989 int32_t ret;
6990
6991 ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
6992 ret += lsm6dsv_read_reg(ctx, LSM6DSV_FREE_FALL, (uint8_t *)&free_fall, 1);
6993
6994 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
6995
6996 return ret;
6997 }
6998
6999 /**
7000 * @brief Free fall threshold setting.[set]
7001 *
7002 * @param ctx read / write interface definitions
7003 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
7004 * @retval interface status (MANDATORY: return 0 -> no Error)
7005 *
7006 */
lsm6dsv_ff_thresholds_set(const stmdev_ctx_t * ctx,lsm6dsv_ff_thresholds_t val)7007 int32_t lsm6dsv_ff_thresholds_set(const stmdev_ctx_t *ctx,
7008 lsm6dsv_ff_thresholds_t val)
7009 {
7010 lsm6dsv_free_fall_t free_fall;
7011 int32_t ret;
7012
7013 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FREE_FALL, (uint8_t *)&free_fall, 1);
7014 if (ret == 0)
7015 {
7016 free_fall.ff_ths = (uint8_t)val & 0x7U;
7017 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FREE_FALL, (uint8_t *)&free_fall, 1);
7018 }
7019
7020 return ret;
7021 }
7022
7023 /**
7024 * @brief Free fall threshold setting.[get]
7025 *
7026 * @param ctx read / write interface definitions
7027 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
7028 * @retval interface status (MANDATORY: return 0 -> no Error)
7029 *
7030 */
lsm6dsv_ff_thresholds_get(const stmdev_ctx_t * ctx,lsm6dsv_ff_thresholds_t * val)7031 int32_t lsm6dsv_ff_thresholds_get(const stmdev_ctx_t *ctx,
7032 lsm6dsv_ff_thresholds_t *val)
7033 {
7034 lsm6dsv_free_fall_t free_fall;
7035 int32_t ret;
7036
7037 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FREE_FALL, (uint8_t *)&free_fall, 1);
7038 if (ret != 0)
7039 {
7040 return ret;
7041 }
7042
7043 switch (free_fall.ff_ths)
7044 {
7045 case LSM6DSV_156_mg:
7046 *val = LSM6DSV_156_mg;
7047 break;
7048
7049 case LSM6DSV_219_mg:
7050 *val = LSM6DSV_219_mg;
7051 break;
7052
7053 case LSM6DSV_250_mg:
7054 *val = LSM6DSV_250_mg;
7055 break;
7056
7057 case LSM6DSV_312_mg:
7058 *val = LSM6DSV_312_mg;
7059 break;
7060
7061 case LSM6DSV_344_mg:
7062 *val = LSM6DSV_344_mg;
7063 break;
7064
7065 case LSM6DSV_406_mg:
7066 *val = LSM6DSV_406_mg;
7067 break;
7068
7069 case LSM6DSV_469_mg:
7070 *val = LSM6DSV_469_mg;
7071 break;
7072
7073 case LSM6DSV_500_mg:
7074 *val = LSM6DSV_500_mg;
7075 break;
7076
7077 default:
7078 *val = LSM6DSV_156_mg;
7079 break;
7080 }
7081
7082 return ret;
7083 }
7084
7085 /**
7086 * @}
7087 *
7088 */
7089
7090 /**
7091 * @defgroup Optical Image Stabilization (OIS)
7092 * @brief This section groups all the functions concerning
7093 * Optical Image Stabilization (OIS).
7094 * @{
7095 *
7096 */
7097
7098 /**
7099 * @brief Enable the full control of OIS configurations from the UI (User Interface).[set]
7100 *
7101 * @param ctx read / write interface definitions
7102 * @param val OIS_CTRL_FROM_OIS, OIS_CTRL_FROM_UI,
7103 * @retval interface status (MANDATORY: return 0 -> no Error)
7104 *
7105 */
lsm6dsv_ois_ctrl_mode_set(const stmdev_ctx_t * ctx,lsm6dsv_ois_ctrl_mode_t val)7106 int32_t lsm6dsv_ois_ctrl_mode_set(const stmdev_ctx_t *ctx,
7107 lsm6dsv_ois_ctrl_mode_t val)
7108 {
7109 lsm6dsv_func_cfg_access_t func_cfg_access;
7110 int32_t ret;
7111
7112 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
7113 if (ret == 0)
7114 {
7115 func_cfg_access.ois_ctrl_from_ui = (uint8_t)val & 0x1U;
7116 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
7117 }
7118
7119 return ret;
7120 }
7121
7122 /**
7123 * @brief Enable the full control of OIS configurations from the UI (User Interface).[get]
7124 *
7125 * @param ctx read / write interface definitions
7126 * @param val OIS_CTRL_FROM_OIS, OIS_CTRL_FROM_UI,
7127 * @retval interface status (MANDATORY: return 0 -> no Error)
7128 *
7129 */
lsm6dsv_ois_ctrl_mode_get(const stmdev_ctx_t * ctx,lsm6dsv_ois_ctrl_mode_t * val)7130 int32_t lsm6dsv_ois_ctrl_mode_get(const stmdev_ctx_t *ctx,
7131 lsm6dsv_ois_ctrl_mode_t *val)
7132 {
7133 lsm6dsv_func_cfg_access_t func_cfg_access;
7134 int32_t ret;
7135
7136 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
7137 if (ret != 0)
7138 {
7139 return ret;
7140 }
7141
7142 switch (func_cfg_access.ois_ctrl_from_ui)
7143 {
7144 case LSM6DSV_OIS_CTRL_FROM_OIS:
7145 *val = LSM6DSV_OIS_CTRL_FROM_OIS;
7146 break;
7147
7148 case LSM6DSV_OIS_CTRL_FROM_UI:
7149 *val = LSM6DSV_OIS_CTRL_FROM_UI;
7150 break;
7151
7152 default:
7153 *val = LSM6DSV_OIS_CTRL_FROM_OIS;
7154 break;
7155 }
7156
7157 return ret;
7158 }
7159
7160 /**
7161 * @brief Resets the control registers of OIS from the UI (User Interface)[set]
7162 *
7163 * @param ctx read / write interface definitions
7164 * @param val Resets the control registers of OIS from the UI (User Interface)
7165 * @retval interface status (MANDATORY: return 0 -> no Error)
7166 *
7167 */
lsm6dsv_ois_reset_set(const stmdev_ctx_t * ctx,int8_t val)7168 int32_t lsm6dsv_ois_reset_set(const stmdev_ctx_t *ctx, int8_t val)
7169 {
7170 lsm6dsv_func_cfg_access_t func_cfg_access;
7171 int32_t ret;
7172
7173 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
7174 if (ret == 0)
7175 {
7176 func_cfg_access.spi2_reset = (uint8_t)val;
7177 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
7178 }
7179
7180 return ret;
7181 }
7182
7183 /**
7184 * @brief Resets the control registers of OIS from the UI (User Interface)[get]
7185 *
7186 * @param ctx read / write interface definitions
7187 * @param val Resets the control registers of OIS from the UI (User Interface)
7188 * @retval interface status (MANDATORY: return 0 -> no Error)
7189 *
7190 */
lsm6dsv_ois_reset_get(const stmdev_ctx_t * ctx,int8_t * val)7191 int32_t lsm6dsv_ois_reset_get(const stmdev_ctx_t *ctx, int8_t *val)
7192 {
7193 lsm6dsv_func_cfg_access_t func_cfg_access;
7194 int32_t ret;
7195
7196 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
7197 *val = (int8_t)func_cfg_access.spi2_reset;
7198
7199 return ret;
7200 }
7201
7202 /**
7203 * @brief Enable/disable pull up on OIS interface.[set]
7204 *
7205 * @param ctx read / write interface definitions
7206 * @param val Enable/disable pull up on OIS interface.
7207 * @retval interface status (MANDATORY: return 0 -> no Error)
7208 *
7209 */
lsm6dsv_ois_interface_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)7210 int32_t lsm6dsv_ois_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
7211 {
7212 lsm6dsv_pin_ctrl_t pin_ctrl;
7213 int32_t ret;
7214
7215 ret = lsm6dsv_read_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7216 if (ret == 0)
7217 {
7218 pin_ctrl.ois_pu_dis = val;
7219 ret = lsm6dsv_write_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7220 }
7221
7222 return ret;
7223 }
7224
7225 /**
7226 * @brief Enable/disable pull up on OIS interface.[get]
7227 *
7228 * @param ctx read / write interface definitions
7229 * @param val Enable/disable pull up on OIS interface.
7230 * @retval interface status (MANDATORY: return 0 -> no Error)
7231 *
7232 */
lsm6dsv_ois_interface_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)7233 int32_t lsm6dsv_ois_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
7234 {
7235 lsm6dsv_pin_ctrl_t pin_ctrl;
7236 int32_t ret;
7237
7238 ret = lsm6dsv_read_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7239 *val = pin_ctrl.ois_pu_dis;
7240
7241 return ret;
7242 }
7243
7244 /**
7245 * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[set]
7246 *
7247 * @param ctx read / write interface definitions
7248 * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.
7249 * @retval interface status (MANDATORY: return 0 -> no Error)
7250 *
7251 */
lsm6dsv_ois_handshake_from_ui_set(const stmdev_ctx_t * ctx,lsm6dsv_ois_handshake_t val)7252 int32_t lsm6dsv_ois_handshake_from_ui_set(const stmdev_ctx_t *ctx,
7253 lsm6dsv_ois_handshake_t val)
7254 {
7255 lsm6dsv_ui_handshake_ctrl_t ui_handshake_ctrl;
7256 int32_t ret;
7257
7258 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1);
7259 if (ret == 0)
7260 {
7261 ui_handshake_ctrl.ui_shared_ack = val.ack;
7262 ui_handshake_ctrl.ui_shared_req = val.req;
7263 ret = lsm6dsv_write_reg(ctx, LSM6DSV_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1);
7264 }
7265
7266 return ret;
7267 }
7268
7269 /**
7270 * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[get]
7271 *
7272 * @param ctx read / write interface definitions
7273 * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.
7274 * @retval interface status (MANDATORY: return 0 -> no Error)
7275 *
7276 */
lsm6dsv_ois_handshake_from_ui_get(const stmdev_ctx_t * ctx,lsm6dsv_ois_handshake_t * val)7277 int32_t lsm6dsv_ois_handshake_from_ui_get(const stmdev_ctx_t *ctx,
7278 lsm6dsv_ois_handshake_t *val)
7279 {
7280 lsm6dsv_ui_handshake_ctrl_t ui_handshake_ctrl;
7281 int32_t ret;
7282
7283 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1);
7284 if (ret != 0)
7285 {
7286 return ret;
7287 }
7288
7289 val->ack = ui_handshake_ctrl.ui_shared_ack;
7290 val->req = ui_handshake_ctrl.ui_shared_req;
7291
7292 return ret;
7293 }
7294
7295 /**
7296 * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[set]
7297 *
7298 * @param ctx read / write interface definitions
7299 * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.
7300 * @retval interface status (MANDATORY: return 0 -> no Error)
7301 *
7302 */
lsm6dsv_ois_handshake_from_ois_set(const stmdev_ctx_t * ctx,lsm6dsv_ois_handshake_t val)7303 int32_t lsm6dsv_ois_handshake_from_ois_set(const stmdev_ctx_t *ctx,
7304 lsm6dsv_ois_handshake_t val)
7305 {
7306 lsm6dsv_spi2_handshake_ctrl_t spi2_handshake_ctrl;
7307 int32_t ret;
7308
7309 ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1);
7310 if (ret == 0)
7311 {
7312 spi2_handshake_ctrl.spi2_shared_ack = val.ack;
7313 spi2_handshake_ctrl.spi2_shared_req = val.req;
7314 ret = lsm6dsv_write_reg(ctx, LSM6DSV_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1);
7315 }
7316
7317 return ret;
7318 }
7319
7320 /**
7321 * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[get]
7322 *
7323 * @param ctx read / write interface definitions
7324 * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.
7325 * @retval interface status (MANDATORY: return 0 -> no Error)
7326 *
7327 */
lsm6dsv_ois_handshake_from_ois_get(const stmdev_ctx_t * ctx,lsm6dsv_ois_handshake_t * val)7328 int32_t lsm6dsv_ois_handshake_from_ois_get(const stmdev_ctx_t *ctx,
7329 lsm6dsv_ois_handshake_t *val)
7330 {
7331 lsm6dsv_spi2_handshake_ctrl_t spi2_handshake_ctrl;
7332 int32_t ret;
7333
7334 ret = lsm6dsv_read_reg(ctx, LSM6DSV_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1);
7335 if (ret != 0)
7336 {
7337 return ret;
7338 }
7339
7340 val->ack = spi2_handshake_ctrl.spi2_shared_ack;
7341 val->req = spi2_handshake_ctrl.spi2_shared_req;
7342
7343 return ret;
7344 }
7345
7346 /**
7347 * @brief User interface (UI) / SPI2 (OIS) shared registers[set]
7348 *
7349 * @param ctx read / write interface definitions
7350 * @param val User interface (UI) / SPI2 (OIS) shared registers
7351 * @retval interface status (MANDATORY: return 0 -> no Error)
7352 *
7353 */
lsm6dsv_ois_shared_set(const stmdev_ctx_t * ctx,uint8_t val[6])7354 int32_t lsm6dsv_ois_shared_set(const stmdev_ctx_t *ctx, uint8_t val[6])
7355 {
7356 int32_t ret;
7357
7358 ret = lsm6dsv_write_reg(ctx, LSM6DSV_UI_SPI2_SHARED_0, val, 6);
7359
7360 return ret;
7361 }
7362
7363 /**
7364 * @brief User interface (UI) / SPI2 (OIS) shared registers[get]
7365 *
7366 * @param ctx read / write interface definitions
7367 * @param val User interface (UI) / SPI2 (OIS) shared registers
7368 * @retval interface status (MANDATORY: return 0 -> no Error)
7369 *
7370 */
lsm6dsv_ois_shared_get(const stmdev_ctx_t * ctx,uint8_t val[6])7371 int32_t lsm6dsv_ois_shared_get(const stmdev_ctx_t *ctx, uint8_t val[6])
7372 {
7373 int32_t ret;
7374
7375 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_SPI2_SHARED_0, val, 6);
7376
7377 return ret;
7378 }
7379
7380 /**
7381 * @brief In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set]
7382 *
7383 * @param ctx read / write interface definitions
7384 * @param val In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data.
7385 * @retval interface status (MANDATORY: return 0 -> no Error)
7386 *
7387 */
lsm6dsv_ois_on_spi2_set(const stmdev_ctx_t * ctx,uint8_t val)7388 int32_t lsm6dsv_ois_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val)
7389 {
7390 lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois;
7391 int32_t ret;
7392
7393 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7394 if (ret == 0)
7395 {
7396 ui_ctrl1_ois.spi2_read_en = val;
7397 ret = lsm6dsv_write_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7398 }
7399
7400 return ret;
7401 }
7402
7403 /**
7404 * @brief In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[get]
7405 *
7406 * @param ctx read / write interface definitions
7407 * @param val In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data.
7408 * @retval interface status (MANDATORY: return 0 -> no Error)
7409 *
7410 */
lsm6dsv_ois_on_spi2_get(const stmdev_ctx_t * ctx,uint8_t * val)7411 int32_t lsm6dsv_ois_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val)
7412 {
7413 lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois;
7414 int32_t ret;
7415
7416 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7417 *val = ui_ctrl1_ois.spi2_read_en;
7418
7419 return ret;
7420 }
7421
7422 /**
7423 * @brief Enables gyroscope/accelerometer OIS chain. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set]
7424 *
7425 * @param ctx read / write interface definitions
7426 * @param val Enables gyroscope/accelerometer OIS chain.
7427 * @retval interface status (MANDATORY: return 0 -> no Error)
7428 *
7429 */
lsm6dsv_ois_chain_set(const stmdev_ctx_t * ctx,lsm6dsv_ois_chain_t val)7430 int32_t lsm6dsv_ois_chain_set(const stmdev_ctx_t *ctx, lsm6dsv_ois_chain_t val)
7431 {
7432 lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois;
7433 int32_t ret;
7434
7435 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7436 if (ret == 0)
7437 {
7438 ui_ctrl1_ois.ois_g_en = val.gy;
7439 ui_ctrl1_ois.ois_xl_en = val.xl;
7440 ret = lsm6dsv_write_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7441 }
7442
7443 return ret;
7444 }
7445
7446 /**
7447 * @brief Enables gyroscope/accelerometer OIS chain.[get]
7448 *
7449 * @param ctx read / write interface definitions
7450 * @param val Enables gyroscope/accelerometer OIS chain.
7451 * @retval interface status (MANDATORY: return 0 -> no Error)
7452 *
7453 */
lsm6dsv_ois_chain_get(const stmdev_ctx_t * ctx,lsm6dsv_ois_chain_t * val)7454 int32_t lsm6dsv_ois_chain_get(const stmdev_ctx_t *ctx, lsm6dsv_ois_chain_t *val)
7455 {
7456 lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois;
7457 int32_t ret;
7458
7459 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7460 if (ret != 0)
7461 {
7462 return ret;
7463 }
7464
7465 val->gy = ui_ctrl1_ois.ois_g_en;
7466 val->xl = ui_ctrl1_ois.ois_xl_en;
7467
7468 return ret;
7469 }
7470
7471 /**
7472 * @brief Gyroscope OIS full-scale selection[set]
7473 *
7474 * @param ctx read / write interface definitions
7475 * @param val OIS_125dps, OIS_250dps, OIS_500dps, OIS_1000dps, OIS_2000dps,
7476 * @retval interface status (MANDATORY: return 0 -> no Error)
7477 *
7478 */
lsm6dsv_ois_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv_ois_gy_full_scale_t val)7479 int32_t lsm6dsv_ois_gy_full_scale_set(const stmdev_ctx_t *ctx,
7480 lsm6dsv_ois_gy_full_scale_t val)
7481 {
7482 lsm6dsv_ui_ctrl2_ois_t ui_ctrl2_ois;
7483 int32_t ret;
7484
7485 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
7486 if (ret == 0)
7487 {
7488 ui_ctrl2_ois.fs_g_ois = (uint8_t)val & 0x03U;
7489 ret = lsm6dsv_write_reg(ctx, LSM6DSV_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
7490 }
7491
7492 return ret;
7493 }
7494
7495 /**
7496 * @brief Gyroscope OIS full-scale selection[get]
7497 *
7498 * @param ctx read / write interface definitions
7499 * @param val OIS_125dps, OIS_250dps, OIS_500dps, OIS_1000dps, OIS_2000dps,
7500 * @retval interface status (MANDATORY: return 0 -> no Error)
7501 *
7502 */
lsm6dsv_ois_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv_ois_gy_full_scale_t * val)7503 int32_t lsm6dsv_ois_gy_full_scale_get(const stmdev_ctx_t *ctx,
7504 lsm6dsv_ois_gy_full_scale_t *val)
7505 {
7506 lsm6dsv_ui_ctrl2_ois_t ui_ctrl2_ois;
7507 int32_t ret;
7508
7509 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
7510 if (ret != 0)
7511 {
7512 return ret;
7513 }
7514
7515 switch (ui_ctrl2_ois.fs_g_ois)
7516 {
7517 case LSM6DSV_OIS_125dps:
7518 *val = LSM6DSV_OIS_125dps;
7519 break;
7520
7521 case LSM6DSV_OIS_250dps:
7522 *val = LSM6DSV_OIS_250dps;
7523 break;
7524
7525 case LSM6DSV_OIS_500dps:
7526 *val = LSM6DSV_OIS_500dps;
7527 break;
7528
7529 case LSM6DSV_OIS_1000dps:
7530 *val = LSM6DSV_OIS_1000dps;
7531 break;
7532
7533 case LSM6DSV_OIS_2000dps:
7534 *val = LSM6DSV_OIS_2000dps;
7535 break;
7536
7537 default:
7538 *val = LSM6DSV_OIS_125dps;
7539 break;
7540 }
7541
7542 return ret;
7543 }
7544
7545 /**
7546 * @brief Selects accelerometer OIS channel full-scale.[set]
7547 *
7548 * @param ctx read / write interface definitions
7549 * @param val lsm6dsv_ois_xl_full_scale_t
7550 * @retval interface status (MANDATORY: return 0 -> no Error)
7551 *
7552 */
lsm6dsv_ois_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv_ois_xl_full_scale_t val)7553 int32_t lsm6dsv_ois_xl_full_scale_set(const stmdev_ctx_t *ctx,
7554 lsm6dsv_ois_xl_full_scale_t val)
7555 {
7556 lsm6dsv_ui_ctrl3_ois_t ui_ctrl3_ois;
7557 int32_t ret;
7558
7559 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
7560 if (ret == 0)
7561 {
7562 ui_ctrl3_ois.fs_xl_ois = (uint8_t)val & 0x3U;
7563 ret = lsm6dsv_write_reg(ctx, LSM6DSV_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
7564 }
7565
7566 return ret;
7567 }
7568
7569 /**
7570 * @brief Selects accelerometer OIS channel full-scale.[get]
7571 *
7572 * @param ctx read / write interface definitions
7573 * @param val lsm6dsv_ois_xl_full_scale_t
7574 * @retval interface status (MANDATORY: return 0 -> no Error)
7575 *
7576 */
lsm6dsv_ois_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv_ois_xl_full_scale_t * val)7577 int32_t lsm6dsv_ois_xl_full_scale_get(const stmdev_ctx_t *ctx,
7578 lsm6dsv_ois_xl_full_scale_t *val)
7579 {
7580 lsm6dsv_ui_ctrl3_ois_t ui_ctrl3_ois;
7581 int32_t ret;
7582
7583 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
7584 if (ret != 0)
7585 {
7586 return ret;
7587 }
7588
7589 switch (ui_ctrl3_ois.fs_xl_ois)
7590 {
7591 case LSM6DSV_OIS_2g:
7592 *val = LSM6DSV_OIS_2g;
7593 break;
7594
7595 case LSM6DSV_OIS_4g:
7596 *val = LSM6DSV_OIS_4g;
7597 break;
7598
7599 case LSM6DSV_OIS_8g:
7600 *val = LSM6DSV_OIS_8g;
7601 break;
7602
7603 case LSM6DSV_OIS_16g:
7604 *val = LSM6DSV_OIS_16g;
7605 break;
7606
7607 default:
7608 *val = LSM6DSV_OIS_2g;
7609 break;
7610 }
7611
7612 return ret;
7613 }
7614
7615 /**
7616 * @}
7617 *
7618 */
7619
7620 /**
7621 * @defgroup Orientation 6D (and 4D)
7622 * @brief This section groups all the functions concerning six position
7623 * detection (6D).
7624 * @{
7625 *
7626 */
7627
7628 /**
7629 * @brief Threshold for 4D/6D function.[set]
7630 *
7631 * @param ctx read / write interface definitions
7632 * @param val DEG_80, DEG_70, DEG_60, DEG_50,
7633 * @retval interface status (MANDATORY: return 0 -> no Error)
7634 *
7635 */
lsm6dsv_6d_threshold_set(const stmdev_ctx_t * ctx,lsm6dsv_6d_threshold_t val)7636 int32_t lsm6dsv_6d_threshold_set(const stmdev_ctx_t *ctx,
7637 lsm6dsv_6d_threshold_t val)
7638 {
7639 lsm6dsv_tap_ths_6d_t tap_ths_6d;
7640 int32_t ret;
7641
7642 ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
7643 if (ret == 0)
7644 {
7645 tap_ths_6d.sixd_ths = (uint8_t)val & 0x03U;
7646 ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
7647 }
7648
7649 return ret;
7650 }
7651
7652 /**
7653 * @brief Threshold for 4D/6D function.[get]
7654 *
7655 * @param ctx read / write interface definitions
7656 * @param val DEG_80, DEG_70, DEG_60, DEG_50,
7657 * @retval interface status (MANDATORY: return 0 -> no Error)
7658 *
7659 */
lsm6dsv_6d_threshold_get(const stmdev_ctx_t * ctx,lsm6dsv_6d_threshold_t * val)7660 int32_t lsm6dsv_6d_threshold_get(const stmdev_ctx_t *ctx,
7661 lsm6dsv_6d_threshold_t *val)
7662 {
7663 lsm6dsv_tap_ths_6d_t tap_ths_6d;
7664 int32_t ret;
7665
7666 ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
7667 if (ret != 0)
7668 {
7669 return ret;
7670 }
7671
7672 switch (tap_ths_6d.sixd_ths)
7673 {
7674 case LSM6DSV_DEG_80:
7675 *val = LSM6DSV_DEG_80;
7676 break;
7677
7678 case LSM6DSV_DEG_70:
7679 *val = LSM6DSV_DEG_70;
7680 break;
7681
7682 case LSM6DSV_DEG_60:
7683 *val = LSM6DSV_DEG_60;
7684 break;
7685
7686 case LSM6DSV_DEG_50:
7687 *val = LSM6DSV_DEG_50;
7688 break;
7689
7690 default:
7691 *val = LSM6DSV_DEG_80;
7692 break;
7693 }
7694
7695 return ret;
7696 }
7697
7698 /**
7699 * @brief 4D orientation detection enable. Z-axis position detection is disabled.[set]
7700 *
7701 * @param ctx read / write interface definitions
7702 * @param val 4D orientation detection enable. Z-axis position detection is disabled.
7703 * @retval interface status (MANDATORY: return 0 -> no Error)
7704 *
7705 */
lsm6dsv_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)7706 int32_t lsm6dsv_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
7707 {
7708 lsm6dsv_tap_ths_6d_t tap_ths_6d;
7709 int32_t ret;
7710
7711 ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
7712 if (ret == 0)
7713 {
7714 tap_ths_6d.d4d_en = val;
7715 ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
7716 }
7717
7718 return ret;
7719 }
7720
7721 /**
7722 * @brief 4D orientation detection enable. Z-axis position detection is disabled.[get]
7723 *
7724 * @param ctx read / write interface definitions
7725 * @param val 4D orientation detection enable. Z-axis position detection is disabled.
7726 * @retval interface status (MANDATORY: return 0 -> no Error)
7727 *
7728 */
lsm6dsv_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)7729 int32_t lsm6dsv_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
7730 {
7731 lsm6dsv_tap_ths_6d_t tap_ths_6d;
7732 int32_t ret;
7733
7734 ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
7735 *val = tap_ths_6d.d4d_en;
7736
7737 return ret;
7738 }
7739
7740 /**
7741 * @}
7742 *
7743 */
7744
7745 /**
7746 * @defgroup SenseWire (I3C)
7747 * @brief This section group all the functions concerning the
7748 * usage of SenseWire (I3C)
7749 * @{
7750 *
7751 */
7752
7753 /**
7754 * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[set]
7755 *
7756 * @param ctx read / write interface definitions
7757 * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST,
7758 * @retval interface status (MANDATORY: return 0 -> no Error)
7759 *
7760 */
lsm6dsv_i3c_reset_mode_set(const stmdev_ctx_t * ctx,lsm6dsv_i3c_reset_mode_t val)7761 int32_t lsm6dsv_i3c_reset_mode_set(const stmdev_ctx_t *ctx,
7762 lsm6dsv_i3c_reset_mode_t val)
7763 {
7764 lsm6dsv_pin_ctrl_t pin_ctrl;
7765 int32_t ret;
7766
7767 ret = lsm6dsv_read_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7768 if (ret == 0)
7769 {
7770 pin_ctrl.ibhr_por_en = (uint8_t)val & 0x01U;
7771 ret = lsm6dsv_write_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7772 }
7773
7774 return ret;
7775 }
7776
7777 /**
7778 * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[get]
7779 *
7780 * @param ctx read / write interface definitions
7781 * @param val SW_RST_DYN_ADDRESS_RST, I3C_GLOBAL_RST,
7782 * @retval interface status (MANDATORY: return 0 -> no Error)
7783 *
7784 */
lsm6dsv_i3c_reset_mode_get(const stmdev_ctx_t * ctx,lsm6dsv_i3c_reset_mode_t * val)7785 int32_t lsm6dsv_i3c_reset_mode_get(const stmdev_ctx_t *ctx,
7786 lsm6dsv_i3c_reset_mode_t *val)
7787 {
7788 lsm6dsv_pin_ctrl_t pin_ctrl;
7789 int32_t ret;
7790
7791 ret = lsm6dsv_read_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7792 if (ret != 0)
7793 {
7794 return ret;
7795 }
7796
7797 switch (pin_ctrl.ibhr_por_en)
7798 {
7799 case LSM6DSV_SW_RST_DYN_ADDRESS_RST:
7800 *val = LSM6DSV_SW_RST_DYN_ADDRESS_RST;
7801 break;
7802
7803 case LSM6DSV_I3C_GLOBAL_RST:
7804 *val = LSM6DSV_I3C_GLOBAL_RST;
7805 break;
7806
7807 default:
7808 *val = LSM6DSV_SW_RST_DYN_ADDRESS_RST;
7809 break;
7810 }
7811
7812 return ret;
7813 }
7814
7815 /**
7816 * @brief Enable/Disable INT pin when I3C is used.[set]
7817 *
7818 * @param ctx read / write interface definitions
7819 * @param val 0: disabled, 1: enabled
7820 * @retval interface status (MANDATORY: return 0 -> no Error)
7821 *
7822 */
lsm6dsv_i3c_int_en_set(const stmdev_ctx_t * ctx,uint8_t val)7823 int32_t lsm6dsv_i3c_int_en_set(const stmdev_ctx_t *ctx, uint8_t val)
7824 {
7825 lsm6dsv_ctrl5_t ctrl5;
7826 int32_t ret;
7827
7828 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL5, (uint8_t *)&ctrl5, 1);
7829 if (ret == 0)
7830 {
7831 ctrl5.int_en_i3c = (uint8_t)val & 0x01U;
7832 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL5, (uint8_t *)&ctrl5, 1);
7833 }
7834
7835 return ret;
7836 }
7837
7838 /**
7839 * @brief Enable/Disable INT pin when I3C is used.[get]
7840 *
7841 * @param ctx read / write interface definitions
7842 * @param val 0: disabled, 1: enabled
7843 * @retval interface status (MANDATORY: return 0 -> no Error)
7844 *
7845 */
lsm6dsv_i3c_int_en_get(const stmdev_ctx_t * ctx,uint8_t * val)7846 int32_t lsm6dsv_i3c_int_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
7847 {
7848 lsm6dsv_ctrl5_t ctrl5;
7849 int32_t ret;
7850
7851 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL5, (uint8_t *)&ctrl5, 1);
7852 *val = ctrl5.int_en_i3c;
7853
7854 return ret;
7855 }
7856
7857 /**
7858 * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[set]
7859 *
7860 * @param ctx read / write interface definitions
7861 * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms,
7862 * @retval interface status (MANDATORY: return 0 -> no Error)
7863 *
7864 */
lsm6dsv_i3c_ibi_time_set(const stmdev_ctx_t * ctx,lsm6dsv_i3c_ibi_time_t val)7865 int32_t lsm6dsv_i3c_ibi_time_set(const stmdev_ctx_t *ctx,
7866 lsm6dsv_i3c_ibi_time_t val)
7867 {
7868 lsm6dsv_ctrl5_t ctrl5;
7869 int32_t ret;
7870
7871 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL5, (uint8_t *)&ctrl5, 1);
7872 if (ret == 0)
7873 {
7874 ctrl5.bus_act_sel = (uint8_t)val & 0x03U;
7875 ret = lsm6dsv_write_reg(ctx, LSM6DSV_CTRL5, (uint8_t *)&ctrl5, 1);
7876 }
7877
7878 return ret;
7879 }
7880
7881 /**
7882 * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[get]
7883 *
7884 * @param ctx read / write interface definitions
7885 * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms,
7886 * @retval interface status (MANDATORY: return 0 -> no Error)
7887 *
7888 */
lsm6dsv_i3c_ibi_time_get(const stmdev_ctx_t * ctx,lsm6dsv_i3c_ibi_time_t * val)7889 int32_t lsm6dsv_i3c_ibi_time_get(const stmdev_ctx_t *ctx,
7890 lsm6dsv_i3c_ibi_time_t *val)
7891 {
7892 lsm6dsv_ctrl5_t ctrl5;
7893 int32_t ret;
7894
7895 ret = lsm6dsv_read_reg(ctx, LSM6DSV_CTRL5, (uint8_t *)&ctrl5, 1);
7896 if (ret != 0)
7897 {
7898 return ret;
7899 }
7900
7901 switch (ctrl5.bus_act_sel)
7902 {
7903 case LSM6DSV_IBI_2us:
7904 *val = LSM6DSV_IBI_2us;
7905 break;
7906
7907 case LSM6DSV_IBI_50us:
7908 *val = LSM6DSV_IBI_50us;
7909 break;
7910
7911 case LSM6DSV_IBI_1ms:
7912 *val = LSM6DSV_IBI_1ms;
7913 break;
7914
7915 case LSM6DSV_IBI_25ms:
7916 *val = LSM6DSV_IBI_25ms;
7917 break;
7918
7919 default:
7920 *val = LSM6DSV_IBI_2us;
7921 break;
7922 }
7923
7924 return ret;
7925 }
7926
7927 /**
7928 * @}
7929 *
7930 */
7931
7932 /**
7933 * @defgroup Sensor hub
7934 * @brief This section groups all the functions that manage the
7935 * sensor hub.
7936 * @{
7937 *
7938 */
7939
7940 /**
7941 * @brief Sensor Hub master I2C pull-up enable.[set]
7942 *
7943 * @param ctx read / write interface definitions
7944 * @param val Sensor Hub master I2C pull-up enable.
7945 * @retval interface status (MANDATORY: return 0 -> no Error)
7946 *
7947 */
lsm6dsv_sh_master_interface_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)7948 int32_t lsm6dsv_sh_master_interface_pull_up_set(const stmdev_ctx_t *ctx,
7949 uint8_t val)
7950 {
7951 lsm6dsv_if_cfg_t if_cfg;
7952 int32_t ret;
7953
7954 ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1);
7955 if (ret == 0)
7956 {
7957 if_cfg.shub_pu_en = val;
7958 ret = lsm6dsv_write_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1);
7959 }
7960
7961 return ret;
7962 }
7963
7964 /**
7965 * @brief Sensor Hub master I2C pull-up enable.[get]
7966 *
7967 * @param ctx read / write interface definitions
7968 * @param val Sensor Hub master I2C pull-up enable.
7969 * @retval interface status (MANDATORY: return 0 -> no Error)
7970 *
7971 */
lsm6dsv_sh_master_interface_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)7972 int32_t lsm6dsv_sh_master_interface_pull_up_get(const stmdev_ctx_t *ctx,
7973 uint8_t *val)
7974 {
7975 lsm6dsv_if_cfg_t if_cfg;
7976 int32_t ret;
7977
7978 ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1);
7979 *val = if_cfg.shub_pu_en;
7980
7981 return ret;
7982 }
7983
7984 /**
7985 * @brief Sensor hub output registers.[get]
7986 *
7987 * @param ctx read / write interface definitions
7988 * @param val Sensor hub output registers.
7989 * @retval interface status (MANDATORY: return 0 -> no Error)
7990 *
7991 */
lsm6dsv_sh_read_data_raw_get(const stmdev_ctx_t * ctx,uint8_t * val,uint8_t len)7992 int32_t lsm6dsv_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val,
7993 uint8_t len)
7994 {
7995 int32_t ret;
7996
7997 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
7998 ret += lsm6dsv_read_reg(ctx, LSM6DSV_SENSOR_HUB_1, val, len);
7999 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8000
8001 return ret;
8002 }
8003
8004 /**
8005 * @brief Number of external sensors to be read by the sensor hub.[set]
8006 *
8007 * @param ctx read / write interface definitions
8008 * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3,
8009 * @retval interface status (MANDATORY: return 0 -> no Error)
8010 *
8011 */
lsm6dsv_sh_slave_connected_set(const stmdev_ctx_t * ctx,lsm6dsv_sh_slave_connected_t val)8012 int32_t lsm6dsv_sh_slave_connected_set(const stmdev_ctx_t *ctx,
8013 lsm6dsv_sh_slave_connected_t val)
8014 {
8015 lsm6dsv_master_config_t master_config;
8016 int32_t ret;
8017
8018 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
8019 ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8020 if (ret != 0)
8021 {
8022 goto exit;
8023 }
8024
8025 master_config.aux_sens_on = (uint8_t)val & 0x3U;
8026 ret = lsm6dsv_write_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8027
8028 exit:
8029 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8030
8031 return ret;
8032 }
8033
8034 /**
8035 * @brief Number of external sensors to be read by the sensor hub.[get]
8036 *
8037 * @param ctx read / write interface definitions
8038 * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3,
8039 * @retval interface status (MANDATORY: return 0 -> no Error)
8040 *
8041 */
lsm6dsv_sh_slave_connected_get(const stmdev_ctx_t * ctx,lsm6dsv_sh_slave_connected_t * val)8042 int32_t lsm6dsv_sh_slave_connected_get(const stmdev_ctx_t *ctx,
8043 lsm6dsv_sh_slave_connected_t *val)
8044 {
8045 lsm6dsv_master_config_t master_config;
8046 int32_t ret;
8047
8048 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
8049 ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8050 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8051 if (ret != 0)
8052 {
8053 return ret;
8054 }
8055
8056 switch (master_config.aux_sens_on)
8057 {
8058 case LSM6DSV_SLV_0:
8059 *val = LSM6DSV_SLV_0;
8060 break;
8061
8062 case LSM6DSV_SLV_0_1:
8063 *val = LSM6DSV_SLV_0_1;
8064 break;
8065
8066 case LSM6DSV_SLV_0_1_2:
8067 *val = LSM6DSV_SLV_0_1_2;
8068 break;
8069
8070 case LSM6DSV_SLV_0_1_2_3:
8071 *val = LSM6DSV_SLV_0_1_2_3;
8072 break;
8073
8074 default:
8075 *val = LSM6DSV_SLV_0;
8076 break;
8077 }
8078
8079 return ret;
8080 }
8081
8082 /**
8083 * @brief Sensor hub I2C master enable.[set]
8084 *
8085 * @param ctx read / write interface definitions
8086 * @param val Sensor hub I2C master enable.
8087 * @retval interface status (MANDATORY: return 0 -> no Error)
8088 *
8089 */
lsm6dsv_sh_master_set(const stmdev_ctx_t * ctx,uint8_t val)8090 int32_t lsm6dsv_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val)
8091 {
8092 lsm6dsv_master_config_t master_config;
8093 int32_t ret;
8094
8095 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
8096 ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8097 if (ret != 0)
8098 {
8099 goto exit;
8100 }
8101
8102 master_config.master_on = val;
8103 ret = lsm6dsv_write_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8104
8105 exit:
8106 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8107
8108 return ret;
8109 }
8110
8111 /**
8112 * @brief Sensor hub I2C master enable.[get]
8113 *
8114 * @param ctx read / write interface definitions
8115 * @param val Sensor hub I2C master enable.
8116 * @retval interface status (MANDATORY: return 0 -> no Error)
8117 *
8118 */
lsm6dsv_sh_master_get(const stmdev_ctx_t * ctx,uint8_t * val)8119 int32_t lsm6dsv_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val)
8120 {
8121 lsm6dsv_master_config_t master_config;
8122 int32_t ret;
8123
8124 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
8125 ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8126
8127 *val = master_config.master_on;
8128
8129 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8130
8131 return ret;
8132 }
8133
8134 /**
8135 * @brief I2C interface pass-through.[set]
8136 *
8137 * @param ctx read / write interface definitions
8138 * @param val I2C interface pass-through.
8139 * @retval interface status (MANDATORY: return 0 -> no Error)
8140 *
8141 */
lsm6dsv_sh_pass_through_set(const stmdev_ctx_t * ctx,uint8_t val)8142 int32_t lsm6dsv_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val)
8143 {
8144 lsm6dsv_master_config_t master_config;
8145 int32_t ret;
8146
8147 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
8148 ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8149 if (ret != 0)
8150 {
8151 goto exit;
8152 }
8153
8154 master_config.pass_through_mode = val;
8155 ret = lsm6dsv_write_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8156
8157 exit:
8158 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8159
8160 return ret;
8161 }
8162
8163 /**
8164 * @brief I2C interface pass-through.[get]
8165 *
8166 * @param ctx read / write interface definitions
8167 * @param val I2C interface pass-through.
8168 * @retval interface status (MANDATORY: return 0 -> no Error)
8169 *
8170 */
lsm6dsv_sh_pass_through_get(const stmdev_ctx_t * ctx,uint8_t * val)8171 int32_t lsm6dsv_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val)
8172 {
8173 lsm6dsv_master_config_t master_config;
8174 int32_t ret;
8175
8176 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
8177 ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8178
8179 *val = master_config.pass_through_mode;
8180
8181 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8182
8183 return ret;
8184 }
8185
8186 /**
8187 * @brief Sensor hub trigger signal selection.[set]
8188 *
8189 * @param ctx read / write interface definitions
8190 * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2,
8191 * @retval interface status (MANDATORY: return 0 -> no Error)
8192 *
8193 */
lsm6dsv_sh_syncro_mode_set(const stmdev_ctx_t * ctx,lsm6dsv_sh_syncro_mode_t val)8194 int32_t lsm6dsv_sh_syncro_mode_set(const stmdev_ctx_t *ctx,
8195 lsm6dsv_sh_syncro_mode_t val)
8196 {
8197 lsm6dsv_master_config_t master_config;
8198 int32_t ret;
8199
8200 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
8201 ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8202 if (ret != 0)
8203 {
8204 goto exit;
8205 }
8206
8207 master_config.start_config = (uint8_t)val & 0x01U;
8208 ret = lsm6dsv_write_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8209
8210 exit:
8211 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8212
8213 return ret;
8214 }
8215
8216 /**
8217 * @brief Sensor hub trigger signal selection.[get]
8218 *
8219 * @param ctx read / write interface definitions
8220 * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2,
8221 * @retval interface status (MANDATORY: return 0 -> no Error)
8222 *
8223 */
lsm6dsv_sh_syncro_mode_get(const stmdev_ctx_t * ctx,lsm6dsv_sh_syncro_mode_t * val)8224 int32_t lsm6dsv_sh_syncro_mode_get(const stmdev_ctx_t *ctx,
8225 lsm6dsv_sh_syncro_mode_t *val)
8226 {
8227 lsm6dsv_master_config_t master_config;
8228 int32_t ret;
8229
8230 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
8231 ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8232 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8233 if (ret != 0)
8234 {
8235 return ret;
8236 }
8237
8238 switch (master_config.start_config)
8239 {
8240 case LSM6DSV_SH_TRG_XL_GY_DRDY:
8241 *val = LSM6DSV_SH_TRG_XL_GY_DRDY;
8242 break;
8243
8244 case LSM6DSV_SH_TRIG_INT2:
8245 *val = LSM6DSV_SH_TRIG_INT2;
8246 break;
8247
8248 default:
8249 *val = LSM6DSV_SH_TRG_XL_GY_DRDY;
8250 break;
8251 }
8252
8253 return ret;
8254 }
8255
8256 /**
8257 * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[set]
8258 *
8259 * @param ctx read / write interface definitions
8260 * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE,
8261 * @retval interface status (MANDATORY: return 0 -> no Error)
8262 *
8263 */
lsm6dsv_sh_write_mode_set(const stmdev_ctx_t * ctx,lsm6dsv_sh_write_mode_t val)8264 int32_t lsm6dsv_sh_write_mode_set(const stmdev_ctx_t *ctx,
8265 lsm6dsv_sh_write_mode_t val)
8266 {
8267 lsm6dsv_master_config_t master_config;
8268 int32_t ret;
8269
8270 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
8271 ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8272 if (ret != 0)
8273 {
8274 goto exit;
8275 }
8276
8277 master_config.write_once = (uint8_t)val & 0x01U;
8278 ret = lsm6dsv_write_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8279
8280 exit:
8281 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8282
8283 return ret;
8284 }
8285
8286 /**
8287 * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[get]
8288 *
8289 * @param ctx read / write interface definitions
8290 * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE,
8291 * @retval interface status (MANDATORY: return 0 -> no Error)
8292 *
8293 */
lsm6dsv_sh_write_mode_get(const stmdev_ctx_t * ctx,lsm6dsv_sh_write_mode_t * val)8294 int32_t lsm6dsv_sh_write_mode_get(const stmdev_ctx_t *ctx,
8295 lsm6dsv_sh_write_mode_t *val)
8296 {
8297 lsm6dsv_master_config_t master_config;
8298 int32_t ret;
8299
8300 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
8301 ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8302 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8303 if (ret != 0)
8304 {
8305 return ret;
8306 }
8307
8308 switch (master_config.write_once)
8309 {
8310 case LSM6DSV_EACH_SH_CYCLE:
8311 *val = LSM6DSV_EACH_SH_CYCLE;
8312 break;
8313
8314 case LSM6DSV_ONLY_FIRST_CYCLE:
8315 *val = LSM6DSV_ONLY_FIRST_CYCLE;
8316 break;
8317
8318 default:
8319 *val = LSM6DSV_EACH_SH_CYCLE;
8320 break;
8321 }
8322
8323 return ret;
8324 }
8325
8326 /**
8327 * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[set]
8328 *
8329 * @param ctx read / write interface definitions
8330 * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.
8331 * @retval interface status (MANDATORY: return 0 -> no Error)
8332 *
8333 */
lsm6dsv_sh_reset_set(const stmdev_ctx_t * ctx,uint8_t val)8334 int32_t lsm6dsv_sh_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
8335 {
8336 lsm6dsv_master_config_t master_config;
8337 int32_t ret;
8338
8339 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
8340 ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8341 if (ret != 0)
8342 {
8343 goto exit;
8344 }
8345
8346 master_config.rst_master_regs = val;
8347 ret = lsm6dsv_write_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8348
8349 exit:
8350 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8351
8352 return ret;
8353 }
8354
8355 /**
8356 * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[get]
8357 *
8358 * @param ctx read / write interface definitions
8359 * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.
8360 * @retval interface status (MANDATORY: return 0 -> no Error)
8361 *
8362 */
lsm6dsv_sh_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)8363 int32_t lsm6dsv_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
8364 {
8365 lsm6dsv_master_config_t master_config;
8366 int32_t ret;
8367
8368 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
8369 ret += lsm6dsv_read_reg(ctx, LSM6DSV_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8370
8371 *val = master_config.rst_master_regs;
8372
8373 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8374
8375 return ret;
8376 }
8377
8378 /**
8379 * @brief Configure slave 0 for perform a write.[set]
8380 *
8381 * @param ctx read / write interface definitions
8382 * @param val a structure that contain
8383 * - uint8_t slv1_add; 8 bit i2c device address
8384 * - uint8_t slv1_subadd; 8 bit register device address
8385 * - uint8_t slv1_data; 8 bit data to write
8386 * @retval interface status (MANDATORY: return 0 -> no Error)
8387 *
8388 */
lsm6dsv_sh_cfg_write(const stmdev_ctx_t * ctx,lsm6dsv_sh_cfg_write_t * val)8389 int32_t lsm6dsv_sh_cfg_write(const stmdev_ctx_t *ctx,
8390 lsm6dsv_sh_cfg_write_t *val)
8391 {
8392 lsm6dsv_slv0_add_t reg;
8393 int32_t ret;
8394
8395 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
8396 if (ret != 0)
8397 {
8398 return ret;
8399 }
8400
8401 reg.slave0_add = val->slv0_add;
8402 reg.rw_0 = 0;
8403 ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_ADD, (uint8_t *)®, 1);
8404 if (ret != 0)
8405 {
8406 goto exit;
8407 }
8408
8409 ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_SUBADD,
8410 &(val->slv0_subadd), 1);
8411 if (ret != 0)
8412 {
8413 goto exit;
8414 }
8415
8416 ret = lsm6dsv_write_reg(ctx, LSM6DSV_DATAWRITE_SLV0,
8417 &(val->slv0_data), 1);
8418
8419 exit:
8420 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8421
8422 return ret;
8423 }
8424
8425 /**
8426 * @brief Rate at which the master communicates.[set]
8427 *
8428 * @param ctx read / write interface definitions
8429 * @param val SH_15Hz, SH_30Hz, SH_60Hz, SH_120Hz, SH_240Hz, SH_480Hz,
8430 * @retval interface status (MANDATORY: return 0 -> no Error)
8431 *
8432 */
lsm6dsv_sh_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv_sh_data_rate_t val)8433 int32_t lsm6dsv_sh_data_rate_set(const stmdev_ctx_t *ctx,
8434 lsm6dsv_sh_data_rate_t val)
8435 {
8436 lsm6dsv_slv0_config_t slv0_config;
8437 int32_t ret;
8438
8439 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
8440 ret += lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG, (uint8_t *)&slv0_config, 1);
8441 if (ret != 0)
8442 {
8443 goto exit;
8444 }
8445
8446 slv0_config.shub_odr = (uint8_t)val & 0x07U;
8447 ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_CONFIG, (uint8_t *)&slv0_config, 1);
8448
8449 exit:
8450 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8451
8452 return ret;
8453 }
8454
8455 /**
8456 * @brief Rate at which the master communicates.[get]
8457 *
8458 * @param ctx read / write interface definitions
8459 * @param val SH_15Hz, SH_30Hz, SH_60Hz, SH_120Hz, SH_240Hz, SH_480Hz,
8460 * @retval interface status (MANDATORY: return 0 -> no Error)
8461 *
8462 */
lsm6dsv_sh_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv_sh_data_rate_t * val)8463 int32_t lsm6dsv_sh_data_rate_get(const stmdev_ctx_t *ctx,
8464 lsm6dsv_sh_data_rate_t *val)
8465 {
8466 lsm6dsv_slv0_config_t slv0_config;
8467 int32_t ret;
8468
8469 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
8470 ret += lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG, (uint8_t *)&slv0_config, 1);
8471 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8472 if (ret != 0)
8473 {
8474 return ret;
8475 }
8476
8477 switch (slv0_config.shub_odr)
8478 {
8479 case LSM6DSV_SH_15Hz:
8480 *val = LSM6DSV_SH_15Hz;
8481 break;
8482
8483 case LSM6DSV_SH_30Hz:
8484 *val = LSM6DSV_SH_30Hz;
8485 break;
8486
8487 case LSM6DSV_SH_60Hz:
8488 *val = LSM6DSV_SH_60Hz;
8489 break;
8490
8491 case LSM6DSV_SH_120Hz:
8492 *val = LSM6DSV_SH_120Hz;
8493 break;
8494
8495 case LSM6DSV_SH_240Hz:
8496 *val = LSM6DSV_SH_240Hz;
8497 break;
8498
8499 case LSM6DSV_SH_480Hz:
8500 *val = LSM6DSV_SH_480Hz;
8501 break;
8502
8503 default:
8504 *val = LSM6DSV_SH_15Hz;
8505 break;
8506 }
8507
8508 return ret;
8509 }
8510
8511 /**
8512 * @brief Configure slave idx for perform a read.[set]
8513 *
8514 * @param ctx read / write interface definitions
8515 * @param val Structure that contain
8516 * - uint8_t slv_add; 8 bit i2c device address
8517 * - uint8_t slv_subadd; 8 bit register device address
8518 * - uint8_t slv_len; num of bit to read
8519 * @retval interface status (MANDATORY: return 0 -> no Error)
8520 *
8521 */
lsm6dsv_sh_slv_cfg_read(const stmdev_ctx_t * ctx,uint8_t idx,lsm6dsv_sh_cfg_read_t * val)8522 int32_t lsm6dsv_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx,
8523 lsm6dsv_sh_cfg_read_t *val)
8524 {
8525 lsm6dsv_slv0_add_t slv_add;
8526 lsm6dsv_slv0_config_t slv_config;
8527 int32_t ret;
8528
8529 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_SENSOR_HUB_MEM_BANK);
8530 if (ret != 0)
8531 {
8532 return ret;
8533 }
8534
8535 slv_add.slave0_add = val->slv_add;
8536 slv_add.rw_0 = 1;
8537 ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_ADD + idx * 3U,
8538 (uint8_t *)&slv_add, 1);
8539 if (ret != 0)
8540 {
8541 goto exit;
8542 }
8543
8544 ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_SUBADD + idx * 3U,
8545 &(val->slv_subadd), 1);
8546 if (ret != 0)
8547 {
8548 goto exit;
8549 }
8550
8551 ret = lsm6dsv_read_reg(ctx, LSM6DSV_SLV0_CONFIG + idx * 3U,
8552 (uint8_t *)&slv_config, 1);
8553 if (ret != 0)
8554 {
8555 goto exit;
8556 }
8557
8558 slv_config.slave0_numop = val->slv_len;
8559 ret = lsm6dsv_write_reg(ctx, LSM6DSV_SLV0_CONFIG + idx * 3U,
8560 (uint8_t *)&slv_config, 1);
8561
8562 exit:
8563 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8564
8565 return ret;
8566 }
8567
8568 /**
8569 * @brief Sensor hub source register.[get]
8570 *
8571 * @param ctx read / write interface definitions
8572 * @param val union of registers from STATUS_MASTER to
8573 * @retval interface status (MANDATORY: return 0 -> no Error)
8574 *
8575 */
lsm6dsv_sh_status_get(const stmdev_ctx_t * ctx,lsm6dsv_status_master_t * val)8576 int32_t lsm6dsv_sh_status_get(const stmdev_ctx_t *ctx,
8577 lsm6dsv_status_master_t *val)
8578 {
8579 int32_t ret;
8580
8581 ret = lsm6dsv_read_reg(ctx, LSM6DSV_STATUS_MASTER_MAINPAGE, (uint8_t *) val, 1);
8582
8583 return ret;
8584 }
8585
8586 /**
8587 * @}
8588 *
8589 */
8590
8591 /**
8592 * @defgroup Serial interfaces
8593 * @brief This section groups all the functions concerning
8594 * serial interfaces management (not auxiliary)
8595 * @{
8596 *
8597 */
8598
8599 /**
8600 * @brief Enables pull-up on SDO pin of UI (User Interface).[set]
8601 *
8602 * @param ctx read / write interface definitions
8603 * @param val Enables pull-up on SDO pin of UI (User Interface).
8604 * @retval interface status (MANDATORY: return 0 -> no Error)
8605 *
8606 */
lsm6dsv_ui_sdo_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)8607 int32_t lsm6dsv_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
8608 {
8609 lsm6dsv_pin_ctrl_t pin_ctrl;
8610 int32_t ret;
8611
8612 ret = lsm6dsv_read_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8613 if (ret == 0)
8614 {
8615 pin_ctrl.sdo_pu_en = val;
8616 ret = lsm6dsv_write_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8617 }
8618
8619 return ret;
8620 }
8621
8622 /**
8623 * @brief Enables pull-up on SDO pin of UI (User Interface).[get]
8624 *
8625 * @param ctx read / write interface definitions
8626 * @param val Enables pull-up on SDO pin of UI (User Interface).
8627 * @retval interface status (MANDATORY: return 0 -> no Error)
8628 *
8629 */
lsm6dsv_ui_sdo_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)8630 int32_t lsm6dsv_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
8631 {
8632 lsm6dsv_pin_ctrl_t pin_ctrl;
8633 int32_t ret;
8634
8635 ret = lsm6dsv_read_reg(ctx, LSM6DSV_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8636 *val = pin_ctrl.sdo_pu_en;
8637
8638 return ret;
8639 }
8640
8641 /**
8642 * @brief Disables I2C and I3C on UI (User Interface).[set]
8643 *
8644 * @param ctx read / write interface definitions
8645 * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE,
8646 * @retval interface status (MANDATORY: return 0 -> no Error)
8647 *
8648 */
lsm6dsv_ui_i2c_i3c_mode_set(const stmdev_ctx_t * ctx,lsm6dsv_ui_i2c_i3c_mode_t val)8649 int32_t lsm6dsv_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx,
8650 lsm6dsv_ui_i2c_i3c_mode_t val)
8651 {
8652 lsm6dsv_if_cfg_t if_cfg;
8653 int32_t ret;
8654
8655 ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1);
8656 if (ret == 0)
8657 {
8658 if_cfg.i2c_i3c_disable = (uint8_t)val & 0x1U;
8659 ret = lsm6dsv_write_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1);
8660 }
8661
8662 return ret;
8663 }
8664
8665 /**
8666 * @brief Disables I2C and I3C on UI (User Interface).[get]
8667 *
8668 * @param ctx read / write interface definitions
8669 * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE,
8670 * @retval interface status (MANDATORY: return 0 -> no Error)
8671 *
8672 */
lsm6dsv_ui_i2c_i3c_mode_get(const stmdev_ctx_t * ctx,lsm6dsv_ui_i2c_i3c_mode_t * val)8673 int32_t lsm6dsv_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx,
8674 lsm6dsv_ui_i2c_i3c_mode_t *val)
8675 {
8676 lsm6dsv_if_cfg_t if_cfg;
8677 int32_t ret;
8678
8679 ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1);
8680 if (ret != 0)
8681 {
8682 return ret;
8683 }
8684
8685 switch (if_cfg.i2c_i3c_disable)
8686 {
8687 case LSM6DSV_I2C_I3C_ENABLE:
8688 *val = LSM6DSV_I2C_I3C_ENABLE;
8689 break;
8690
8691 case LSM6DSV_I2C_I3C_DISABLE:
8692 *val = LSM6DSV_I2C_I3C_DISABLE;
8693 break;
8694
8695 default:
8696 *val = LSM6DSV_I2C_I3C_ENABLE;
8697 break;
8698 }
8699
8700 return ret;
8701 }
8702
8703 /**
8704 * @brief SPI Serial Interface Mode selection.[set]
8705 *
8706 * @param ctx read / write interface definitions
8707 * @param val SPI_4_WIRE, SPI_3_WIRE,
8708 * @retval interface status (MANDATORY: return 0 -> no Error)
8709 *
8710 */
lsm6dsv_spi_mode_set(const stmdev_ctx_t * ctx,lsm6dsv_spi_mode_t val)8711 int32_t lsm6dsv_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_spi_mode_t val)
8712 {
8713 lsm6dsv_if_cfg_t if_cfg;
8714 int32_t ret;
8715
8716 ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1);
8717 if (ret == 0)
8718 {
8719 if_cfg.sim = (uint8_t)val & 0x01U;
8720 ret = lsm6dsv_write_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1);
8721 }
8722
8723 return ret;
8724 }
8725
8726 /**
8727 * @brief SPI Serial Interface Mode selection.[get]
8728 *
8729 * @param ctx read / write interface definitions
8730 * @param val SPI_4_WIRE, SPI_3_WIRE,
8731 * @retval interface status (MANDATORY: return 0 -> no Error)
8732 *
8733 */
lsm6dsv_spi_mode_get(const stmdev_ctx_t * ctx,lsm6dsv_spi_mode_t * val)8734 int32_t lsm6dsv_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_spi_mode_t *val)
8735 {
8736 lsm6dsv_if_cfg_t if_cfg;
8737 int32_t ret;
8738
8739 ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1);
8740 if (ret != 0)
8741 {
8742 return ret;
8743 }
8744
8745 switch (if_cfg.sim)
8746 {
8747 case LSM6DSV_SPI_4_WIRE:
8748 *val = LSM6DSV_SPI_4_WIRE;
8749 break;
8750
8751 case LSM6DSV_SPI_3_WIRE:
8752 *val = LSM6DSV_SPI_3_WIRE;
8753 break;
8754
8755 default:
8756 *val = LSM6DSV_SPI_4_WIRE;
8757 break;
8758 }
8759
8760 return ret;
8761 }
8762
8763 /**
8764 * @brief Enables pull-up on SDA pin.[set]
8765 *
8766 * @param ctx read / write interface definitions
8767 * @param val Enables pull-up on SDA pin.
8768 * @retval interface status (MANDATORY: return 0 -> no Error)
8769 *
8770 */
lsm6dsv_ui_sda_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)8771 int32_t lsm6dsv_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
8772 {
8773 lsm6dsv_if_cfg_t if_cfg;
8774 int32_t ret;
8775
8776 ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1);
8777 if (ret == 0)
8778 {
8779 if_cfg.sda_pu_en = val;
8780 ret = lsm6dsv_write_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1);
8781 }
8782
8783 return ret;
8784 }
8785
8786 /**
8787 * @brief Enables pull-up on SDA pin.[get]
8788 *
8789 * @param ctx read / write interface definitions
8790 * @param val Enables pull-up on SDA pin.
8791 * @retval interface status (MANDATORY: return 0 -> no Error)
8792 *
8793 */
lsm6dsv_ui_sda_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)8794 int32_t lsm6dsv_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
8795 {
8796 lsm6dsv_if_cfg_t if_cfg;
8797 int32_t ret;
8798
8799 ret = lsm6dsv_read_reg(ctx, LSM6DSV_IF_CFG, (uint8_t *)&if_cfg, 1);
8800 *val = if_cfg.sda_pu_en;
8801
8802 return ret;
8803 }
8804
8805 /**
8806 * @brief SPI2 (OIS Inteface) Serial Interface Mode selection. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set]
8807 *
8808 * @param ctx read / write interface definitions
8809 * @param val SPI2_4_WIRE, SPI2_3_WIRE,
8810 * @retval interface status (MANDATORY: return 0 -> no Error)
8811 *
8812 */
lsm6dsv_spi2_mode_set(const stmdev_ctx_t * ctx,lsm6dsv_spi2_mode_t val)8813 int32_t lsm6dsv_spi2_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_spi2_mode_t val)
8814 {
8815 lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois;
8816 int32_t ret;
8817
8818 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
8819 if (ret == 0)
8820 {
8821 ui_ctrl1_ois.sim_ois = (uint8_t)val & 0x01U;
8822 ret = lsm6dsv_write_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
8823 }
8824
8825 return ret;
8826 }
8827
8828 /**
8829 * @brief SPI2 (OIS Inteface) Serial Interface Mode selection. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[get]
8830 *
8831 * @param ctx read / write interface definitions
8832 * @param val SPI2_4_WIRE, SPI2_3_WIRE,
8833 * @retval interface status (MANDATORY: return 0 -> no Error)
8834 *
8835 */
lsm6dsv_spi2_mode_get(const stmdev_ctx_t * ctx,lsm6dsv_spi2_mode_t * val)8836 int32_t lsm6dsv_spi2_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_spi2_mode_t *val)
8837 {
8838 lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois;
8839 int32_t ret;
8840
8841 ret = lsm6dsv_read_reg(ctx, LSM6DSV_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
8842 if (ret != 0)
8843 {
8844 return ret;
8845 }
8846
8847 switch (ui_ctrl1_ois.sim_ois)
8848 {
8849 case LSM6DSV_SPI2_4_WIRE:
8850 *val = LSM6DSV_SPI2_4_WIRE;
8851 break;
8852
8853 case LSM6DSV_SPI2_3_WIRE:
8854 *val = LSM6DSV_SPI2_3_WIRE;
8855 break;
8856
8857 default:
8858 *val = LSM6DSV_SPI2_4_WIRE;
8859 break;
8860 }
8861
8862 return ret;
8863 }
8864
8865 /**
8866 * @}
8867 *
8868 */
8869
8870 /**
8871 * @defgroup Significant motion detection
8872 * @brief This section groups all the functions that manage the
8873 * significant motion detection.
8874 * @{
8875 *
8876 */
8877
8878
8879 /**
8880 * @brief Enables significant motion detection function.[set]
8881 *
8882 * @param ctx read / write interface definitions
8883 * @param val Enables significant motion detection function.
8884 * @retval interface status (MANDATORY: return 0 -> no Error)
8885 *
8886 */
lsm6dsv_sigmot_mode_set(const stmdev_ctx_t * ctx,uint8_t val)8887 int32_t lsm6dsv_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
8888 {
8889 lsm6dsv_emb_func_en_a_t emb_func_en_a;
8890 int32_t ret;
8891
8892 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
8893 if (ret != 0)
8894 {
8895 return ret;
8896 }
8897
8898 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
8899 emb_func_en_a.sign_motion_en = val;
8900 ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
8901
8902 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8903
8904 return ret;
8905 }
8906
8907 /**
8908 * @brief Enables significant motion detection function.[get]
8909 *
8910 * @param ctx read / write interface definitions
8911 * @param val Enables significant motion detection function.
8912 * @retval interface status (MANDATORY: return 0 -> no Error)
8913 *
8914 */
lsm6dsv_sigmot_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)8915 int32_t lsm6dsv_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
8916 {
8917 lsm6dsv_emb_func_en_a_t emb_func_en_a;
8918 int32_t ret;
8919
8920 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
8921 if (ret != 0)
8922 {
8923 return ret;
8924 }
8925
8926 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
8927 *val = emb_func_en_a.sign_motion_en;
8928
8929 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8930
8931 return ret;
8932 }
8933
8934 /**
8935 * @}
8936 *
8937 */
8938
8939 /**
8940 * @defgroup Step Counter (Pedometer)
8941 * @brief This section groups all the functions that manage pedometer.
8942 * @{
8943 *
8944 */
8945
8946 /**
8947 * @brief Step counter mode[set]
8948 *
8949 * @param ctx read / write interface definitions
8950 * @param val Step counter mode
8951 * @retval interface status (MANDATORY: return 0 -> no Error)
8952 *
8953 */
lsm6dsv_stpcnt_mode_set(const stmdev_ctx_t * ctx,lsm6dsv_stpcnt_mode_t val)8954 int32_t lsm6dsv_stpcnt_mode_set(const stmdev_ctx_t *ctx,
8955 lsm6dsv_stpcnt_mode_t val)
8956 {
8957 lsm6dsv_emb_func_en_a_t emb_func_en_a;
8958 int32_t ret;
8959
8960 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
8961 if (ret != 0)
8962 {
8963 return ret;
8964 }
8965
8966 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
8967 if (ret != 0)
8968 {
8969 goto exit;
8970 }
8971
8972 emb_func_en_a.pedo_en = val.step_counter_enable;
8973 ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
8974
8975 exit:
8976 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8977
8978 return ret;
8979 }
8980
8981 /**
8982 * @brief Step counter mode[get]
8983 *
8984 * @param ctx read / write interface definitions
8985 * @param val false_step_rej, step_counter, step_detector,
8986 * @retval interface status (MANDATORY: return 0 -> no Error)
8987 *
8988 */
lsm6dsv_stpcnt_mode_get(const stmdev_ctx_t * ctx,lsm6dsv_stpcnt_mode_t * val)8989 int32_t lsm6dsv_stpcnt_mode_get(const stmdev_ctx_t *ctx,
8990 lsm6dsv_stpcnt_mode_t *val)
8991 {
8992 lsm6dsv_emb_func_en_a_t emb_func_en_a;
8993 int32_t ret;
8994
8995 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
8996 ret += lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
8997 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
8998 if (ret != 0)
8999 {
9000 return ret;
9001 }
9002
9003 return ret;
9004 }
9005
9006 /**
9007 * @brief Step counter output, number of detected steps.[get]
9008 *
9009 * @param ctx read / write interface definitions
9010 * @param val Step counter output, number of detected steps.
9011 * @retval interface status (MANDATORY: return 0 -> no Error)
9012 *
9013 */
lsm6dsv_stpcnt_steps_get(const stmdev_ctx_t * ctx,uint16_t * val)9014 int32_t lsm6dsv_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val)
9015 {
9016 uint8_t buff[2];
9017 int32_t ret;
9018
9019 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
9020 ret += lsm6dsv_read_reg(ctx, LSM6DSV_STEP_COUNTER_L, &buff[0], 2);
9021 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
9022 if (ret != 0)
9023 {
9024 return ret;
9025 }
9026
9027 *val = buff[1];
9028 *val = (*val * 256U) + buff[0];
9029
9030 return ret;
9031 }
9032
9033 /**
9034 * @brief Reset step counter.[set]
9035 *
9036 * @param ctx read / write interface definitions
9037 * @param val Reset step counter.
9038 * @retval interface status (MANDATORY: return 0 -> no Error)
9039 *
9040 */
lsm6dsv_stpcnt_rst_step_set(const stmdev_ctx_t * ctx,uint8_t val)9041 int32_t lsm6dsv_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val)
9042 {
9043 lsm6dsv_emb_func_src_t emb_func_src;
9044 int32_t ret;
9045
9046 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
9047 if (ret != 0)
9048 {
9049 return ret;
9050 }
9051
9052 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
9053 if (ret != 0)
9054 {
9055 goto exit;
9056 }
9057
9058 emb_func_src.pedo_rst_step = val;
9059 ret = lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
9060
9061 exit:
9062 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
9063
9064 return ret;
9065 }
9066
9067 /**
9068 * @brief Reset step counter.[get]
9069 *
9070 * @param ctx read / write interface definitions
9071 * @param val Reset step counter.
9072 * @retval interface status (MANDATORY: return 0 -> no Error)
9073 *
9074 */
lsm6dsv_stpcnt_rst_step_get(const stmdev_ctx_t * ctx,uint8_t * val)9075 int32_t lsm6dsv_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val)
9076 {
9077 lsm6dsv_emb_func_src_t emb_func_src;
9078 int32_t ret;
9079
9080 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
9081 if (ret != 0)
9082 {
9083 return ret;
9084 }
9085
9086 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
9087 *val = emb_func_src.pedo_rst_step;
9088
9089 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
9090
9091 return ret;
9092 }
9093
9094 /**
9095 * @brief Pedometer debounce configuration.[set]
9096 *
9097 * @param ctx read / write interface definitions
9098 * @param val Pedometer debounce configuration.
9099 * @retval interface status (MANDATORY: return 0 -> no Error)
9100 *
9101 */
lsm6dsv_stpcnt_debounce_set(const stmdev_ctx_t * ctx,uint8_t val)9102 int32_t lsm6dsv_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val)
9103 {
9104 lsm6dsv_pedo_deb_steps_conf_t pedo_deb_steps_conf;
9105 int32_t ret;
9106
9107 ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_DEB_STEPS_CONF,
9108 (uint8_t *)&pedo_deb_steps_conf, 1);
9109 if (ret == 0)
9110 {
9111 pedo_deb_steps_conf.deb_step = val;
9112 ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_DEB_STEPS_CONF,
9113 (uint8_t *)&pedo_deb_steps_conf, 1);
9114 }
9115
9116 return ret;
9117 }
9118
9119 /**
9120 * @brief Pedometer debounce configuration.[get]
9121 *
9122 * @param ctx read / write interface definitions
9123 * @param val Pedometer debounce configuration.
9124 * @retval interface status (MANDATORY: return 0 -> no Error)
9125 *
9126 */
lsm6dsv_stpcnt_debounce_get(const stmdev_ctx_t * ctx,uint8_t * val)9127 int32_t lsm6dsv_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val)
9128 {
9129 lsm6dsv_pedo_deb_steps_conf_t pedo_deb_steps_conf;
9130 int32_t ret;
9131
9132 ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_DEB_STEPS_CONF,
9133 (uint8_t *)&pedo_deb_steps_conf, 1);
9134 *val = pedo_deb_steps_conf.deb_step;
9135
9136 return ret;
9137 }
9138
9139 /**
9140 * @brief Time period register for step detection on delta time.[set]
9141 *
9142 * @param ctx read / write interface definitions
9143 * @param val Time period register for step detection on delta time.
9144 * @retval interface status (MANDATORY: return 0 -> no Error)
9145 *
9146 */
lsm6dsv_stpcnt_period_set(const stmdev_ctx_t * ctx,uint16_t val)9147 int32_t lsm6dsv_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val)
9148 {
9149 uint8_t buff[2];
9150 int32_t ret;
9151
9152 buff[1] = (uint8_t)(val / 256U);
9153 buff[0] = (uint8_t)(val - (buff[1] * 256U));
9154 ret = lsm6dsv_ln_pg_write(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_SC_DELTAT_L, (uint8_t *)&buff[0],
9155 2);
9156
9157 return ret;
9158 }
9159
9160 /**
9161 * @brief Time period register for step detection on delta time.[get]
9162 *
9163 * @param ctx read / write interface definitions
9164 * @param val Time period register for step detection on delta time.
9165 * @retval interface status (MANDATORY: return 0 -> no Error)
9166 *
9167 */
lsm6dsv_stpcnt_period_get(const stmdev_ctx_t * ctx,uint16_t * val)9168 int32_t lsm6dsv_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val)
9169 {
9170 uint8_t buff[2];
9171 int32_t ret;
9172
9173 ret = lsm6dsv_ln_pg_read(ctx, LSM6DSV_EMB_ADV_PG_1 + LSM6DSV_PEDO_SC_DELTAT_L, &buff[0], 2);
9174 if (ret != 0)
9175 {
9176 return ret;
9177 }
9178
9179 *val = buff[1];
9180 *val = (*val * 256U) + buff[0];
9181
9182 return ret;
9183 }
9184
9185 /**
9186 * @}
9187 *
9188 */
9189
9190 /**
9191 * @defgroup Sensor Fusion Low Power (SFLP)
9192 * @brief This section groups all the functions that manage pedometer.
9193 * @{
9194 *
9195 */
9196
9197 /**
9198 * @brief Enable SFLP Game Rotation Vector (6x).[set]
9199 *
9200 * @param ctx read / write interface definitions
9201 * @param val Enable/Disable game rotation value (0/1).
9202 * @retval interface status (MANDATORY: return 0 -> no Error)
9203 *
9204 */
lsm6dsv_sflp_game_rotation_set(const stmdev_ctx_t * ctx,uint8_t val)9205 int32_t lsm6dsv_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint8_t val)
9206 {
9207 lsm6dsv_emb_func_en_a_t emb_func_en_a;
9208 int32_t ret;
9209
9210 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
9211 if (ret != 0)
9212 {
9213 return ret;
9214 }
9215
9216 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9217 if (ret != 0)
9218 {
9219 goto exit;
9220 }
9221
9222 emb_func_en_a.sflp_game_en = val;
9223 ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A,
9224 (uint8_t *)&emb_func_en_a, 1);
9225
9226 exit:
9227 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
9228
9229 return ret;
9230 }
9231
9232 /**
9233 * @brief Enable SFLP Game Rotation Vector (6x).[get]
9234 *
9235 * @param ctx read / write interface definitions
9236 * @param val Enable/Disable game rotation value (0/1).
9237 * @retval interface status (MANDATORY: return 0 -> no Error)
9238 *
9239 */
lsm6dsv_sflp_game_rotation_get(const stmdev_ctx_t * ctx,uint8_t * val)9240 int32_t lsm6dsv_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint8_t *val)
9241 {
9242 lsm6dsv_emb_func_en_a_t emb_func_en_a;
9243 int32_t ret;
9244
9245 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
9246 if (ret != 0)
9247 {
9248 return ret;
9249 }
9250
9251 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9252 *val = emb_func_en_a.sflp_game_en;
9253
9254 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
9255
9256 return ret;
9257 }
9258
9259 /**
9260 * @brief SFLP Data Rate (ODR) configuration.[set]
9261 *
9262 * @param ctx read / write interface definitions
9263 * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz
9264 * @retval interface status (MANDATORY: return 0 -> no Error)
9265 *
9266 */
lsm6dsv_sflp_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv_sflp_data_rate_t val)9267 int32_t lsm6dsv_sflp_data_rate_set(const stmdev_ctx_t *ctx,
9268 lsm6dsv_sflp_data_rate_t val)
9269 {
9270 lsm6dsv_sflp_odr_t sflp_odr;
9271 int32_t ret;
9272
9273 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
9274 if (ret != 0)
9275 {
9276 return ret;
9277 }
9278
9279 ret = lsm6dsv_read_reg(ctx, LSM6DSV_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
9280 if (ret != 0)
9281 {
9282 goto exit;
9283 }
9284
9285 sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U;
9286 ret += lsm6dsv_write_reg(ctx, LSM6DSV_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
9287
9288 exit:
9289 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
9290
9291 return ret;
9292 }
9293
9294 /**
9295 * @brief SFLP Data Rate (ODR) configuration.[get]
9296 *
9297 * @param ctx read / write interface definitions
9298 * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz
9299 * @retval interface status (MANDATORY: return 0 -> no Error)
9300 *
9301 */
lsm6dsv_sflp_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv_sflp_data_rate_t * val)9302 int32_t lsm6dsv_sflp_data_rate_get(const stmdev_ctx_t *ctx,
9303 lsm6dsv_sflp_data_rate_t *val)
9304 {
9305 lsm6dsv_sflp_odr_t sflp_odr;
9306 int32_t ret;
9307
9308 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
9309 ret += lsm6dsv_read_reg(ctx, LSM6DSV_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
9310 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
9311 if (ret != 0)
9312 {
9313 return ret;
9314 }
9315
9316 switch (sflp_odr.sflp_game_odr)
9317 {
9318 case LSM6DSV_SFLP_15Hz:
9319 *val = LSM6DSV_SFLP_15Hz;
9320 break;
9321
9322 case LSM6DSV_SFLP_30Hz:
9323 *val = LSM6DSV_SFLP_30Hz;
9324 break;
9325
9326 case LSM6DSV_SFLP_60Hz:
9327 *val = LSM6DSV_SFLP_60Hz;
9328 break;
9329
9330 case LSM6DSV_SFLP_120Hz:
9331 *val = LSM6DSV_SFLP_120Hz;
9332 break;
9333
9334 case LSM6DSV_SFLP_240Hz:
9335 *val = LSM6DSV_SFLP_240Hz;
9336 break;
9337
9338 case LSM6DSV_SFLP_480Hz:
9339 *val = LSM6DSV_SFLP_480Hz;
9340 break;
9341
9342 default:
9343 *val = LSM6DSV_SFLP_15Hz;
9344 break;
9345 }
9346
9347 return ret;
9348 }
9349
9350 /**
9351 * @}
9352 *
9353 */
9354
9355 /**
9356 * @defgroup Tap - Double Tap
9357 * @brief This section groups all the functions that manage the
9358 * tap and double tap event generation.
9359 * @{
9360 *
9361 */
9362
9363 /**
9364 * @brief Enable axis for Tap - Double Tap detection.[set]
9365 *
9366 * @param ctx read / write interface definitions
9367 * @param val Enable axis for Tap - Double Tap detection.
9368 * @retval interface status (MANDATORY: return 0 -> no Error)
9369 *
9370 */
lsm6dsv_tap_detection_set(const stmdev_ctx_t * ctx,lsm6dsv_tap_detection_t val)9371 int32_t lsm6dsv_tap_detection_set(const stmdev_ctx_t *ctx,
9372 lsm6dsv_tap_detection_t val)
9373 {
9374 lsm6dsv_tap_cfg0_t tap_cfg0;
9375 int32_t ret;
9376
9377 ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
9378 if (ret == 0)
9379 {
9380 tap_cfg0.tap_x_en = val.tap_x_en;
9381 tap_cfg0.tap_y_en = val.tap_y_en;
9382 tap_cfg0.tap_z_en = val.tap_z_en;
9383 ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
9384 }
9385
9386 return ret;
9387 }
9388
9389 /**
9390 * @brief Enable axis for Tap - Double Tap detection.[get]
9391 *
9392 * @param ctx read / write interface definitions
9393 * @param val Enable axis for Tap - Double Tap detection.
9394 * @retval interface status (MANDATORY: return 0 -> no Error)
9395 *
9396 */
lsm6dsv_tap_detection_get(const stmdev_ctx_t * ctx,lsm6dsv_tap_detection_t * val)9397 int32_t lsm6dsv_tap_detection_get(const stmdev_ctx_t *ctx,
9398 lsm6dsv_tap_detection_t *val)
9399 {
9400 lsm6dsv_tap_cfg0_t tap_cfg0;
9401 int32_t ret;
9402
9403 ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
9404 if (ret != 0)
9405 {
9406 return ret;
9407 }
9408
9409 val->tap_x_en = tap_cfg0.tap_x_en;
9410 val->tap_y_en = tap_cfg0.tap_y_en;
9411 val->tap_z_en = tap_cfg0.tap_z_en;
9412
9413 return ret;
9414 }
9415
9416 /**
9417 * @brief axis Tap - Double Tap recognition thresholds.[set]
9418 *
9419 * @param ctx read / write interface definitions
9420 * @param val axis Tap - Double Tap recognition thresholds.
9421 * @retval interface status (MANDATORY: return 0 -> no Error)
9422 *
9423 */
lsm6dsv_tap_thresholds_set(const stmdev_ctx_t * ctx,lsm6dsv_tap_thresholds_t val)9424 int32_t lsm6dsv_tap_thresholds_set(const stmdev_ctx_t *ctx,
9425 lsm6dsv_tap_thresholds_t val)
9426 {
9427 lsm6dsv_tap_ths_6d_t tap_ths_6d;
9428 lsm6dsv_tap_cfg2_t tap_cfg2;
9429 lsm6dsv_tap_cfg1_t tap_cfg1;
9430 int32_t ret;
9431
9432 ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
9433 ret += lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
9434 ret += lsm6dsv_read_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
9435 if (ret != 0)
9436 {
9437 return ret;
9438 }
9439
9440 tap_cfg1.tap_ths_x = val.x;
9441 tap_cfg2.tap_ths_y = val.y;
9442 tap_ths_6d.tap_ths_z = val.z;
9443
9444 ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
9445 ret += lsm6dsv_write_reg(ctx, LSM6DSV_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
9446 ret += lsm6dsv_write_reg(ctx, LSM6DSV_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
9447
9448 return ret;
9449 }
9450
9451 /**
9452 * @brief axis Tap - Double Tap recognition thresholds.[get]
9453 *
9454 * @param ctx read / write interface definitions
9455 * @param val axis Tap - Double Tap recognition thresholds.
9456 * @retval interface status (MANDATORY: return 0 -> no Error)
9457 *
9458 */
lsm6dsv_tap_thresholds_get(const stmdev_ctx_t * ctx,lsm6dsv_tap_thresholds_t * val)9459 int32_t lsm6dsv_tap_thresholds_get(const stmdev_ctx_t *ctx,
9460 lsm6dsv_tap_thresholds_t *val)
9461 {
9462 lsm6dsv_tap_ths_6d_t tap_ths_6d;
9463 lsm6dsv_tap_cfg2_t tap_cfg2;
9464 lsm6dsv_tap_cfg1_t tap_cfg1;
9465 int32_t ret;
9466
9467 ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
9468 ret += lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
9469 ret += lsm6dsv_read_reg(ctx, LSM6DSV_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
9470 if (ret != 0)
9471 {
9472 return ret;
9473 }
9474
9475 val->x = tap_cfg1.tap_ths_x;
9476 val->y = tap_cfg2.tap_ths_y;
9477 val->z = tap_ths_6d.tap_ths_z;
9478
9479 return ret;
9480 }
9481
9482 /**
9483 * @brief Selection of axis priority for TAP detection.[set]
9484 *
9485 * @param ctx read / write interface definitions
9486 * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY ,
9487 * @retval interface status (MANDATORY: return 0 -> no Error)
9488 *
9489 */
lsm6dsv_tap_axis_priority_set(const stmdev_ctx_t * ctx,lsm6dsv_tap_axis_priority_t val)9490 int32_t lsm6dsv_tap_axis_priority_set(const stmdev_ctx_t *ctx,
9491 lsm6dsv_tap_axis_priority_t val)
9492 {
9493 lsm6dsv_tap_cfg1_t tap_cfg1;
9494 int32_t ret;
9495
9496 ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
9497 if (ret == 0)
9498 {
9499 tap_cfg1.tap_priority = (uint8_t)val & 0x7U;
9500 ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
9501 }
9502
9503 return ret;
9504 }
9505
9506 /**
9507 * @brief Selection of axis priority for TAP detection.[get]
9508 *
9509 * @param ctx read / write interface definitions
9510 * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY ,
9511 * @retval interface status (MANDATORY: return 0 -> no Error)
9512 *
9513 */
lsm6dsv_tap_axis_priority_get(const stmdev_ctx_t * ctx,lsm6dsv_tap_axis_priority_t * val)9514 int32_t lsm6dsv_tap_axis_priority_get(const stmdev_ctx_t *ctx,
9515 lsm6dsv_tap_axis_priority_t *val)
9516 {
9517 lsm6dsv_tap_cfg1_t tap_cfg1;
9518 int32_t ret;
9519
9520 ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
9521 if (ret != 0)
9522 {
9523 return ret;
9524 }
9525
9526 switch (tap_cfg1.tap_priority)
9527 {
9528 case LSM6DSV_XYZ :
9529 *val = LSM6DSV_XYZ ;
9530 break;
9531
9532 case LSM6DSV_YXZ :
9533 *val = LSM6DSV_YXZ ;
9534 break;
9535
9536 case LSM6DSV_XZY:
9537 *val = LSM6DSV_XZY;
9538 break;
9539
9540 case LSM6DSV_ZYX :
9541 *val = LSM6DSV_ZYX ;
9542 break;
9543
9544 case LSM6DSV_YZX :
9545 *val = LSM6DSV_YZX ;
9546 break;
9547
9548 case LSM6DSV_ZXY :
9549 *val = LSM6DSV_ZXY ;
9550 break;
9551
9552 default:
9553 *val = LSM6DSV_XYZ ;
9554 break;
9555 }
9556
9557 return ret;
9558 }
9559
9560 /**
9561 * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[set]
9562 *
9563 * @param ctx read / write interface definitions
9564 * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.
9565 * @retval interface status (MANDATORY: return 0 -> no Error)
9566 *
9567 */
lsm6dsv_tap_time_windows_set(const stmdev_ctx_t * ctx,lsm6dsv_tap_time_windows_t val)9568 int32_t lsm6dsv_tap_time_windows_set(const stmdev_ctx_t *ctx,
9569 lsm6dsv_tap_time_windows_t val)
9570 {
9571 lsm6dsv_tap_dur_t tap_dur;
9572 int32_t ret;
9573
9574 ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_DUR, (uint8_t *)&tap_dur, 1);
9575 if (ret == 0)
9576 {
9577 tap_dur.shock = val.shock;
9578 tap_dur.quiet = val.quiet;
9579 tap_dur.dur = val.tap_gap;
9580 ret = lsm6dsv_write_reg(ctx, LSM6DSV_TAP_DUR, (uint8_t *)&tap_dur, 1);
9581 }
9582
9583 return ret;
9584 }
9585
9586 /**
9587 * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[get]
9588 *
9589 * @param ctx read / write interface definitions
9590 * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.
9591 * @retval interface status (MANDATORY: return 0 -> no Error)
9592 *
9593 */
lsm6dsv_tap_time_windows_get(const stmdev_ctx_t * ctx,lsm6dsv_tap_time_windows_t * val)9594 int32_t lsm6dsv_tap_time_windows_get(const stmdev_ctx_t *ctx,
9595 lsm6dsv_tap_time_windows_t *val)
9596 {
9597 lsm6dsv_tap_dur_t tap_dur;
9598 int32_t ret;
9599
9600 ret = lsm6dsv_read_reg(ctx, LSM6DSV_TAP_DUR, (uint8_t *)&tap_dur, 1);
9601 if (ret != 0)
9602 {
9603 return ret;
9604 }
9605
9606 val->shock = tap_dur.shock;
9607 val->quiet = tap_dur.quiet;
9608 val->tap_gap = tap_dur.dur;
9609
9610 return ret;
9611 }
9612
9613 /**
9614 * @brief Single/double-tap event enable.[set]
9615 *
9616 * @param ctx read / write interface definitions
9617 * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE,
9618 * @retval interface status (MANDATORY: return 0 -> no Error)
9619 *
9620 */
lsm6dsv_tap_mode_set(const stmdev_ctx_t * ctx,lsm6dsv_tap_mode_t val)9621 int32_t lsm6dsv_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_tap_mode_t val)
9622 {
9623 lsm6dsv_wake_up_ths_t wake_up_ths;
9624 int32_t ret;
9625
9626 ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
9627 if (ret == 0)
9628 {
9629 wake_up_ths.single_double_tap = (uint8_t)val & 0x01U;
9630 ret = lsm6dsv_write_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
9631 }
9632
9633 return ret;
9634 }
9635
9636 /**
9637 * @brief Single/double-tap event enable.[get]
9638 *
9639 * @param ctx read / write interface definitions
9640 * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE,
9641 * @retval interface status (MANDATORY: return 0 -> no Error)
9642 *
9643 */
lsm6dsv_tap_mode_get(const stmdev_ctx_t * ctx,lsm6dsv_tap_mode_t * val)9644 int32_t lsm6dsv_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_tap_mode_t *val)
9645 {
9646 lsm6dsv_wake_up_ths_t wake_up_ths;
9647 int32_t ret;
9648
9649 ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
9650 if (ret != 0)
9651 {
9652 return ret;
9653 }
9654
9655 switch (wake_up_ths.single_double_tap)
9656 {
9657 case LSM6DSV_ONLY_SINGLE:
9658 *val = LSM6DSV_ONLY_SINGLE;
9659 break;
9660
9661 case LSM6DSV_BOTH_SINGLE_DOUBLE:
9662 *val = LSM6DSV_BOTH_SINGLE_DOUBLE;
9663 break;
9664
9665 default:
9666 *val = LSM6DSV_ONLY_SINGLE;
9667 break;
9668 }
9669
9670 return ret;
9671 }
9672
9673 /**
9674 * @}
9675 *
9676 */
9677
9678 /**
9679 * @defgroup Tilt detection
9680 * @brief This section groups all the functions that manage the tilt
9681 * event detection.
9682 * @{
9683 *
9684 */
9685
9686 /**
9687 * @brief Tilt calculation.[set]
9688 *
9689 * @param ctx read / write interface definitions
9690 * @param val Tilt calculation.
9691 * @retval interface status (MANDATORY: return 0 -> no Error)
9692 *
9693 */
lsm6dsv_tilt_mode_set(const stmdev_ctx_t * ctx,uint8_t val)9694 int32_t lsm6dsv_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
9695 {
9696 lsm6dsv_emb_func_en_a_t emb_func_en_a;
9697 int32_t ret;
9698
9699 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
9700 if (ret != 0)
9701 {
9702 return ret;
9703 }
9704
9705 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9706 emb_func_en_a.tilt_en = val;
9707 ret += lsm6dsv_write_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9708
9709 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
9710
9711 return ret;
9712 }
9713
9714 /**
9715 * @brief Tilt calculation.[get]
9716 *
9717 * @param ctx read / write interface definitions
9718 * @param val Tilt calculation.
9719 * @retval interface status (MANDATORY: return 0 -> no Error)
9720 *
9721 */
lsm6dsv_tilt_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)9722 int32_t lsm6dsv_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
9723 {
9724 lsm6dsv_emb_func_en_a_t emb_func_en_a;
9725 int32_t ret;
9726
9727 ret = lsm6dsv_mem_bank_set(ctx, LSM6DSV_EMBED_FUNC_MEM_BANK);
9728 if (ret != 0)
9729 {
9730 return ret;
9731 }
9732
9733 ret = lsm6dsv_read_reg(ctx, LSM6DSV_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9734 *val = emb_func_en_a.tilt_en;
9735
9736 ret += lsm6dsv_mem_bank_set(ctx, LSM6DSV_MAIN_MEM_BANK);
9737
9738 return ret;
9739 }
9740
9741 /**
9742 * @}
9743 *
9744 */
9745
9746 /**
9747 * @defgroup Timestamp
9748 * @brief This section groups all the functions that manage the
9749 * timestamp generation.
9750 * @{
9751 *
9752 */
9753
9754 /**
9755 * @brief Timestamp data output.[get]
9756 *
9757 * @param ctx read / write interface definitions
9758 * @param val Timestamp data output.
9759 * @retval interface status (MANDATORY: return 0 -> no Error)
9760 *
9761 */
lsm6dsv_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)9762 int32_t lsm6dsv_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
9763 {
9764 uint8_t buff[4];
9765 int32_t ret;
9766
9767 ret = lsm6dsv_read_reg(ctx, LSM6DSV_TIMESTAMP0, &buff[0], 4);
9768 if (ret != 0)
9769 {
9770 return ret;
9771 }
9772
9773 *val = buff[3];
9774 *val = (*val * 256U) + buff[2];
9775 *val = (*val * 256U) + buff[1];
9776 *val = (*val * 256U) + buff[0];
9777
9778 return ret;
9779 }
9780
9781 /**
9782 * @brief Enables timestamp counter.[set]
9783 *
9784 * @param ctx read / write interface definitions
9785 * @param val Enables timestamp counter.
9786 * @retval interface status (MANDATORY: return 0 -> no Error)
9787 *
9788 */
lsm6dsv_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)9789 int32_t lsm6dsv_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
9790 {
9791 lsm6dsv_functions_enable_t functions_enable;
9792 int32_t ret;
9793
9794 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
9795 if (ret == 0)
9796 {
9797 functions_enable.timestamp_en = val;
9798 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
9799 }
9800
9801 return ret;
9802 }
9803
9804 /**
9805 * @brief Enables timestamp counter.[get]
9806 *
9807 * @param ctx read / write interface definitions
9808 * @param val Enables timestamp counter.
9809 * @retval interface status (MANDATORY: return 0 -> no Error)
9810 *
9811 */
lsm6dsv_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)9812 int32_t lsm6dsv_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
9813 {
9814 lsm6dsv_functions_enable_t functions_enable;
9815 int32_t ret;
9816
9817 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
9818 *val = functions_enable.timestamp_en;
9819
9820 return ret;
9821 }
9822
9823 /**
9824 * @}
9825 *
9826 */
9827
9828 /**
9829 * @defgroup Wake Up - Activity - Inactivity (Sleep)
9830 * @brief This section groups all the functions that manage the Wake Up
9831 * event generation.
9832 * @{
9833 *
9834 */
9835
9836 /**
9837 * @brief Enable activity/inactivity (sleep) function.[set]
9838 *
9839 * @param ctx read / write interface definitions
9840 * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN,
9841 * @retval interface status (MANDATORY: return 0 -> no Error)
9842 *
9843 */
lsm6dsv_act_mode_set(const stmdev_ctx_t * ctx,lsm6dsv_act_mode_t val)9844 int32_t lsm6dsv_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_act_mode_t val)
9845 {
9846 lsm6dsv_functions_enable_t functions_enable;
9847 int32_t ret;
9848
9849 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
9850 if (ret == 0)
9851 {
9852 functions_enable.inact_en = (uint8_t)val & 0x3U;
9853 ret = lsm6dsv_write_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
9854 }
9855
9856 return ret;
9857 }
9858
9859 /**
9860 * @brief Enable activity/inactivity (sleep) function.[get]
9861 *
9862 * @param ctx read / write interface definitions
9863 * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN,
9864 * @retval interface status (MANDATORY: return 0 -> no Error)
9865 *
9866 */
lsm6dsv_act_mode_get(const stmdev_ctx_t * ctx,lsm6dsv_act_mode_t * val)9867 int32_t lsm6dsv_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_act_mode_t *val)
9868 {
9869 lsm6dsv_functions_enable_t functions_enable;
9870 int32_t ret;
9871
9872 ret = lsm6dsv_read_reg(ctx, LSM6DSV_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
9873 if (ret != 0)
9874 {
9875 return ret;
9876 }
9877
9878 switch (functions_enable.inact_en)
9879 {
9880 case LSM6DSV_XL_AND_GY_NOT_AFFECTED:
9881 *val = LSM6DSV_XL_AND_GY_NOT_AFFECTED;
9882 break;
9883
9884 case LSM6DSV_XL_LOW_POWER_GY_NOT_AFFECTED:
9885 *val = LSM6DSV_XL_LOW_POWER_GY_NOT_AFFECTED;
9886 break;
9887
9888 case LSM6DSV_XL_LOW_POWER_GY_SLEEP:
9889 *val = LSM6DSV_XL_LOW_POWER_GY_SLEEP;
9890 break;
9891
9892 case LSM6DSV_XL_LOW_POWER_GY_POWER_DOWN:
9893 *val = LSM6DSV_XL_LOW_POWER_GY_POWER_DOWN;
9894 break;
9895
9896 default:
9897 *val = LSM6DSV_XL_AND_GY_NOT_AFFECTED;
9898 break;
9899 }
9900
9901 return ret;
9902 }
9903
9904 /**
9905 * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[set]
9906 *
9907 * @param ctx read / write interface definitions
9908 * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE,
9909 * @retval interface status (MANDATORY: return 0 -> no Error)
9910 *
9911 */
lsm6dsv_act_from_sleep_to_act_dur_set(const stmdev_ctx_t * ctx,lsm6dsv_act_from_sleep_to_act_dur_t val)9912 int32_t lsm6dsv_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx,
9913 lsm6dsv_act_from_sleep_to_act_dur_t val)
9914 {
9915 lsm6dsv_inactivity_dur_t inactivity_dur;
9916 int32_t ret;
9917
9918 ret = lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
9919 if (ret == 0)
9920 {
9921 inactivity_dur.inact_dur = (uint8_t)val & 0x3U;
9922 ret = lsm6dsv_write_reg(ctx, LSM6DSV_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
9923 }
9924
9925 return ret;
9926 }
9927
9928 /**
9929 * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[get]
9930 *
9931 * @param ctx read / write interface definitions
9932 * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE,
9933 * @retval interface status (MANDATORY: return 0 -> no Error)
9934 *
9935 */
lsm6dsv_act_from_sleep_to_act_dur_get(const stmdev_ctx_t * ctx,lsm6dsv_act_from_sleep_to_act_dur_t * val)9936 int32_t lsm6dsv_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx,
9937 lsm6dsv_act_from_sleep_to_act_dur_t *val)
9938 {
9939 lsm6dsv_inactivity_dur_t inactivity_dur;
9940 int32_t ret;
9941
9942 ret = lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
9943 if (ret != 0)
9944 {
9945 return ret;
9946 }
9947
9948 switch (inactivity_dur.inact_dur)
9949 {
9950 case LSM6DSV_SLEEP_TO_ACT_AT_1ST_SAMPLE:
9951 *val = LSM6DSV_SLEEP_TO_ACT_AT_1ST_SAMPLE;
9952 break;
9953
9954 case LSM6DSV_SLEEP_TO_ACT_AT_2ND_SAMPLE:
9955 *val = LSM6DSV_SLEEP_TO_ACT_AT_2ND_SAMPLE;
9956 break;
9957
9958 case LSM6DSV_SLEEP_TO_ACT_AT_3RD_SAMPLE:
9959 *val = LSM6DSV_SLEEP_TO_ACT_AT_3RD_SAMPLE;
9960 break;
9961
9962 case LSM6DSV_SLEEP_TO_ACT_AT_4th_SAMPLE:
9963 *val = LSM6DSV_SLEEP_TO_ACT_AT_4th_SAMPLE;
9964 break;
9965
9966 default:
9967 *val = LSM6DSV_SLEEP_TO_ACT_AT_1ST_SAMPLE;
9968 break;
9969 }
9970
9971 return ret;
9972 }
9973
9974 /**
9975 * @brief Selects the accelerometer data rate during Inactivity.[set]
9976 *
9977 * @param ctx read / write interface definitions
9978 * @param val 1Hz875, 15Hz, 30Hz, 60Hz,
9979 * @retval interface status (MANDATORY: return 0 -> no Error)
9980 *
9981 */
lsm6dsv_act_sleep_xl_odr_set(const stmdev_ctx_t * ctx,lsm6dsv_act_sleep_xl_odr_t val)9982 int32_t lsm6dsv_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx,
9983 lsm6dsv_act_sleep_xl_odr_t val)
9984 {
9985 lsm6dsv_inactivity_dur_t inactivity_dur;
9986 int32_t ret;
9987
9988 ret = lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
9989 if (ret == 0)
9990 {
9991 inactivity_dur.xl_inact_odr = (uint8_t)val & 0x03U;
9992 ret = lsm6dsv_write_reg(ctx, LSM6DSV_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
9993 }
9994
9995 return ret;
9996 }
9997
9998 /**
9999 * @brief Selects the accelerometer data rate during Inactivity.[get]
10000 *
10001 * @param ctx read / write interface definitions
10002 * @param val 1Hz875, 15Hz, 30Hz, 60Hz,
10003 * @retval interface status (MANDATORY: return 0 -> no Error)
10004 *
10005 */
lsm6dsv_act_sleep_xl_odr_get(const stmdev_ctx_t * ctx,lsm6dsv_act_sleep_xl_odr_t * val)10006 int32_t lsm6dsv_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx,
10007 lsm6dsv_act_sleep_xl_odr_t *val)
10008 {
10009 lsm6dsv_inactivity_dur_t inactivity_dur;
10010 int32_t ret;
10011
10012 ret = lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10013 if (ret != 0)
10014 {
10015 return ret;
10016 }
10017
10018 switch (inactivity_dur.xl_inact_odr)
10019 {
10020 case LSM6DSV_1Hz875:
10021 *val = LSM6DSV_1Hz875;
10022 break;
10023
10024 case LSM6DSV_15Hz:
10025 *val = LSM6DSV_15Hz;
10026 break;
10027
10028 case LSM6DSV_30Hz:
10029 *val = LSM6DSV_30Hz;
10030 break;
10031
10032 case LSM6DSV_60Hz:
10033 *val = LSM6DSV_60Hz;
10034 break;
10035
10036 default:
10037 *val = LSM6DSV_1Hz875;
10038 break;
10039 }
10040
10041 return ret;
10042 }
10043
10044 /**
10045 * @brief Wakeup and activity/inactivity threshold.[set]
10046 *
10047 * @param ctx read / write interface definitions
10048 * @param val Wakeup and activity/inactivity threshold.
10049 * @retval interface status (MANDATORY: return 0 -> no Error)
10050 *
10051 */
lsm6dsv_act_thresholds_set(const stmdev_ctx_t * ctx,lsm6dsv_act_thresholds_t * val)10052 int32_t lsm6dsv_act_thresholds_set(const stmdev_ctx_t *ctx,
10053 lsm6dsv_act_thresholds_t *val)
10054 {
10055 lsm6dsv_inactivity_ths_t inactivity_ths;
10056 lsm6dsv_inactivity_dur_t inactivity_dur;
10057 lsm6dsv_wake_up_ths_t wake_up_ths;
10058 lsm6dsv_wake_up_dur_t wake_up_dur;
10059 int32_t ret;
10060
10061 ret = lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10062 ret += lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
10063 ret += lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
10064 ret += lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
10065 if (ret != 0)
10066 {
10067 return ret;
10068 }
10069
10070 inactivity_dur.wu_inact_ths_w = val->inactivity_cfg.wu_inact_ths_w;
10071 inactivity_dur.xl_inact_odr = val->inactivity_cfg.xl_inact_odr;
10072 inactivity_dur.inact_dur = val->inactivity_cfg.inact_dur;
10073
10074 inactivity_ths.inact_ths = val->inactivity_ths;
10075 wake_up_ths.wk_ths = val->threshold;
10076 wake_up_dur.wake_dur = val->duration;
10077
10078 ret += lsm6dsv_write_reg(ctx, LSM6DSV_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10079 ret += lsm6dsv_write_reg(ctx, LSM6DSV_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
10080 ret += lsm6dsv_write_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
10081 ret += lsm6dsv_write_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
10082
10083 return ret;
10084 }
10085
10086 /**
10087 * @brief Wakeup and activity/inactivity threshold.[get]
10088 *
10089 * @param ctx read / write interface definitions
10090 * @param val Wakeup and activity/inactivity threshold.
10091 * @retval interface status (MANDATORY: return 0 -> no Error)
10092 *
10093 */
lsm6dsv_act_thresholds_get(const stmdev_ctx_t * ctx,lsm6dsv_act_thresholds_t * val)10094 int32_t lsm6dsv_act_thresholds_get(const stmdev_ctx_t *ctx,
10095 lsm6dsv_act_thresholds_t *val)
10096 {
10097 lsm6dsv_inactivity_dur_t inactivity_dur;
10098 lsm6dsv_inactivity_ths_t inactivity_ths;
10099 lsm6dsv_wake_up_ths_t wake_up_ths;
10100 lsm6dsv_wake_up_dur_t wake_up_dur;
10101 int32_t ret;
10102
10103 ret = lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10104 ret += lsm6dsv_read_reg(ctx, LSM6DSV_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
10105 ret += lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
10106 ret += lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
10107 if (ret != 0)
10108 {
10109 return ret;
10110 }
10111
10112 val->inactivity_cfg.wu_inact_ths_w = inactivity_dur.wu_inact_ths_w;
10113 val->inactivity_cfg.xl_inact_odr = inactivity_dur.xl_inact_odr;
10114 val->inactivity_cfg.inact_dur = inactivity_dur.inact_dur;
10115
10116 val->inactivity_ths = inactivity_ths.inact_ths;
10117 val->threshold = wake_up_ths.wk_ths;
10118 val->duration = wake_up_dur.wake_dur;
10119
10120 return ret;
10121 }
10122
10123 /**
10124 * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [set]
10125 *
10126 * @param ctx read / write interface definitions
10127 * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time.
10128 * @retval interface status (MANDATORY: return 0 -> no Error)
10129 *
10130 */
lsm6dsv_act_wkup_time_windows_set(const stmdev_ctx_t * ctx,lsm6dsv_act_wkup_time_windows_t val)10131 int32_t lsm6dsv_act_wkup_time_windows_set(const stmdev_ctx_t *ctx,
10132 lsm6dsv_act_wkup_time_windows_t val)
10133 {
10134 lsm6dsv_wake_up_dur_t wake_up_dur;
10135 int32_t ret;
10136
10137 ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
10138 if (ret == 0)
10139 {
10140 wake_up_dur.wake_dur = val.shock;
10141 wake_up_dur.sleep_dur = val.quiet;
10142 ret = lsm6dsv_write_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
10143 }
10144
10145 return ret;
10146 }
10147
10148 /**
10149 * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [get]
10150 *
10151 * @param ctx read / write interface definitions
10152 * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time.
10153 * @retval interface status (MANDATORY: return 0 -> no Error)
10154 *
10155 */
lsm6dsv_act_wkup_time_windows_get(const stmdev_ctx_t * ctx,lsm6dsv_act_wkup_time_windows_t * val)10156 int32_t lsm6dsv_act_wkup_time_windows_get(const stmdev_ctx_t *ctx,
10157 lsm6dsv_act_wkup_time_windows_t *val)
10158 {
10159 lsm6dsv_wake_up_dur_t wake_up_dur;
10160 int32_t ret;
10161
10162 ret = lsm6dsv_read_reg(ctx, LSM6DSV_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
10163 if (ret != 0)
10164 {
10165 return ret;
10166 }
10167
10168 val->shock = wake_up_dur.wake_dur;
10169 val->quiet = wake_up_dur.sleep_dur;
10170
10171 return ret;
10172 }
10173
10174 /**
10175 * @}
10176 *
10177 */
10178
