1 /** 2 ****************************************************************************** 3 * @file lsm6dsv_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm6dsv_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2024 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM6DSV_REGS_H 23 #define LSM6DSV_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM6DSV 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LSM6DSV_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define LSM6DSV_I2C_ADD_L 0xD5U 173 #define LSM6DSV_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define LSM6DSV_ID 0x70U 177 178 /** 179 * @} 180 * 181 */ 182 183 /** @defgroup bitfields page main 184 * @{ 185 * 186 */ 187 188 #define LSM6DSV_FUNC_CFG_ACCESS 0x1U 189 typedef struct 190 { 191 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 192 uint8_t ois_ctrl_from_ui : 1; 193 uint8_t spi2_reset : 1; 194 uint8_t sw_por : 1; 195 uint8_t fsm_wr_ctrl_en : 1; 196 uint8_t not_used0 : 2; 197 uint8_t shub_reg_access : 1; 198 uint8_t emb_func_reg_access : 1; 199 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 200 uint8_t emb_func_reg_access : 1; 201 uint8_t shub_reg_access : 1; 202 uint8_t not_used0 : 2; 203 uint8_t fsm_wr_ctrl_en : 1; 204 uint8_t sw_por : 1; 205 uint8_t spi2_reset : 1; 206 uint8_t ois_ctrl_from_ui : 1; 207 #endif /* DRV_BYTE_ORDER */ 208 } lsm6dsv_func_cfg_access_t; 209 210 #define LSM6DSV_PIN_CTRL 0x2U 211 typedef struct 212 { 213 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 214 uint8_t not_used0 : 5; 215 uint8_t ibhr_por_en : 1; 216 uint8_t sdo_pu_en : 1; 217 uint8_t ois_pu_dis : 1; 218 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 219 uint8_t ois_pu_dis : 1; 220 uint8_t sdo_pu_en : 1; 221 uint8_t ibhr_por_en : 1; 222 uint8_t not_used0 : 5; 223 #endif /* DRV_BYTE_ORDER */ 224 } lsm6dsv_pin_ctrl_t; 225 226 #define LSM6DSV_IF_CFG 0x3U 227 typedef struct 228 { 229 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 230 uint8_t i2c_i3c_disable : 1; 231 uint8_t not_used0 : 1; 232 uint8_t sim : 1; 233 uint8_t pp_od : 1; 234 uint8_t h_lactive : 1; 235 uint8_t asf_ctrl : 1; 236 uint8_t shub_pu_en : 1; 237 uint8_t sda_pu_en : 1; 238 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 239 uint8_t sda_pu_en : 1; 240 uint8_t shub_pu_en : 1; 241 uint8_t asf_ctrl : 1; 242 uint8_t h_lactive : 1; 243 uint8_t pp_od : 1; 244 uint8_t sim : 1; 245 uint8_t not_used0 : 1; 246 uint8_t i2c_i3c_disable : 1; 247 #endif /* DRV_BYTE_ORDER */ 248 } lsm6dsv_if_cfg_t; 249 250 #define LSM6DSV_ODR_TRIG_CFG 0x6U 251 typedef struct 252 { 253 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 254 uint8_t odr_trig_nodr : 8; 255 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 256 uint8_t odr_trig_nodr : 8; 257 #endif /* DRV_BYTE_ORDER */ 258 } lsm6dsv_odr_trig_cfg_t; 259 260 #define LSM6DSV_FIFO_CTRL1 0x7U 261 typedef struct 262 { 263 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 264 uint8_t wtm : 8; 265 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 266 uint8_t wtm : 8; 267 #endif /* DRV_BYTE_ORDER */ 268 } lsm6dsv_fifo_ctrl1_t; 269 270 #define LSM6DSV_FIFO_CTRL2 0x8U 271 typedef struct 272 { 273 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 274 uint8_t xl_dualc_batch_from_fsm : 1; 275 uint8_t uncompr_rate : 2; 276 uint8_t not_used0 : 1; 277 uint8_t odr_chg_en : 1; 278 uint8_t not_used1 : 1; 279 uint8_t fifo_compr_rt_en : 1; 280 uint8_t stop_on_wtm : 1; 281 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 282 uint8_t stop_on_wtm : 1; 283 uint8_t fifo_compr_rt_en : 1; 284 uint8_t not_used1 : 1; 285 uint8_t odr_chg_en : 1; 286 uint8_t not_used0 : 1; 287 uint8_t uncompr_rate : 2; 288 uint8_t xl_dualc_batch_from_fsm : 1; 289 #endif /* DRV_BYTE_ORDER */ 290 } lsm6dsv_fifo_ctrl2_t; 291 292 #define LSM6DSV_FIFO_CTRL3 0x9U 293 typedef struct 294 { 295 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 296 uint8_t bdr_xl : 4; 297 uint8_t bdr_gy : 4; 298 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 299 uint8_t bdr_gy : 4; 300 uint8_t bdr_xl : 4; 301 #endif /* DRV_BYTE_ORDER */ 302 } lsm6dsv_fifo_ctrl3_t; 303 304 #define LSM6DSV_FIFO_CTRL4 0x0AU 305 typedef struct 306 { 307 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 308 uint8_t fifo_mode : 3; 309 uint8_t g_eis_fifo_en : 1; 310 uint8_t odr_t_batch : 2; 311 uint8_t dec_ts_batch : 2; 312 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 313 uint8_t dec_ts_batch : 2; 314 uint8_t odr_t_batch : 2; 315 uint8_t g_eis_fifo_en : 1; 316 uint8_t fifo_mode : 3; 317 #endif /* DRV_BYTE_ORDER */ 318 } lsm6dsv_fifo_ctrl4_t; 319 320 #define LSM6DSV_COUNTER_BDR_REG1 0x0BU 321 typedef struct 322 { 323 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 324 uint8_t cnt_bdr_th : 2; 325 uint8_t not_used0 : 3; 326 uint8_t trig_counter_bdr : 2; 327 uint8_t not_used1 : 1; 328 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 329 uint8_t not_used1 : 1; 330 uint8_t trig_counter_bdr : 2; 331 uint8_t not_used0 : 3; 332 uint8_t cnt_bdr_th : 2; 333 #endif /* DRV_BYTE_ORDER */ 334 } lsm6dsv_counter_bdr_reg1_t; 335 336 #define LSM6DSV_COUNTER_BDR_REG2 0x0CU 337 typedef struct 338 { 339 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 340 uint8_t cnt_bdr_th : 8; 341 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 342 uint8_t cnt_bdr_th : 8; 343 #endif /* DRV_BYTE_ORDER */ 344 } lsm6dsv_counter_bdr_reg2_t; 345 346 #define LSM6DSV_INT1_CTRL 0x0DU 347 typedef struct 348 { 349 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 350 uint8_t int1_drdy_xl : 1; 351 uint8_t int1_drdy_g : 1; 352 uint8_t not_used0 : 1; 353 uint8_t int1_fifo_th : 1; 354 uint8_t int1_fifo_ovr : 1; 355 uint8_t int1_fifo_full : 1; 356 uint8_t int1_cnt_bdr : 1; 357 uint8_t not_used1 : 1; 358 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 359 uint8_t not_used1 : 1; 360 uint8_t int1_cnt_bdr : 1; 361 uint8_t int1_fifo_full : 1; 362 uint8_t int1_fifo_ovr : 1; 363 uint8_t int1_fifo_th : 1; 364 uint8_t not_used0 : 1; 365 uint8_t int1_drdy_g : 1; 366 uint8_t int1_drdy_xl : 1; 367 #endif /* DRV_BYTE_ORDER */ 368 } lsm6dsv_int1_ctrl_t; 369 370 #define LSM6DSV_INT2_CTRL 0x0EU 371 typedef struct 372 { 373 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 374 uint8_t int2_drdy_xl : 1; 375 uint8_t int2_drdy_g : 1; 376 uint8_t int2_drdy_g_eis : 1; 377 uint8_t int2_fifo_th : 1; 378 uint8_t int2_fifo_ovr : 1; 379 uint8_t int2_fifo_full : 1; 380 uint8_t int2_cnt_bdr : 1; 381 uint8_t int2_emb_func_endop : 1; 382 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 383 uint8_t int2_emb_func_endop : 1; 384 uint8_t int2_cnt_bdr : 1; 385 uint8_t int2_fifo_full : 1; 386 uint8_t int2_fifo_ovr : 1; 387 uint8_t int2_fifo_th : 1; 388 uint8_t int2_drdy_g_eis : 1; 389 uint8_t int2_drdy_g : 1; 390 uint8_t int2_drdy_xl : 1; 391 #endif /* DRV_BYTE_ORDER */ 392 } lsm6dsv_int2_ctrl_t; 393 394 #define LSM6DSV_WHO_AM_I 0x0FU 395 typedef struct 396 { 397 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 398 uint8_t id : 8; 399 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 400 uint8_t id : 8; 401 #endif /* DRV_BYTE_ORDER */ 402 } lsm6dsv_who_am_i_t; 403 404 #define LSM6DSV_CTRL1 0x10U 405 typedef struct 406 { 407 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 408 uint8_t odr_xl : 4; 409 uint8_t op_mode_xl : 3; 410 uint8_t not_used0 : 1; 411 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 412 uint8_t not_used0 : 1; 413 uint8_t op_mode_xl : 3; 414 uint8_t odr_xl : 4; 415 #endif /* DRV_BYTE_ORDER */ 416 } lsm6dsv_ctrl1_t; 417 418 #define LSM6DSV_CTRL2 0x11U 419 typedef struct 420 { 421 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 422 uint8_t odr_g : 4; 423 uint8_t op_mode_g : 3; 424 uint8_t not_used0 : 1; 425 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 426 uint8_t not_used0 : 1; 427 uint8_t op_mode_g : 3; 428 uint8_t odr_g : 4; 429 #endif /* DRV_BYTE_ORDER */ 430 } lsm6dsv_ctrl2_t; 431 432 #define LSM6DSV_CTRL3 0x12U 433 typedef struct 434 { 435 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 436 uint8_t sw_reset : 1; 437 uint8_t not_used0 : 1; 438 uint8_t if_inc : 1; 439 uint8_t not_used1 : 3; 440 uint8_t bdu : 1; 441 uint8_t boot : 1; 442 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 443 uint8_t boot : 1; 444 uint8_t bdu : 1; 445 uint8_t not_used1 : 3; 446 uint8_t if_inc : 1; 447 uint8_t not_used0 : 1; 448 uint8_t sw_reset : 1; 449 #endif /* DRV_BYTE_ORDER */ 450 } lsm6dsv_ctrl3_t; 451 452 #define LSM6DSV_CTRL4 0x13U 453 typedef struct 454 { 455 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 456 uint8_t int2_in_lh : 1; 457 uint8_t drdy_pulsed : 1; 458 uint8_t int2_drdy_temp : 1; 459 uint8_t drdy_mask : 1; 460 uint8_t int2_on_int1 : 1; 461 uint8_t not_used0 : 3; 462 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 463 uint8_t not_used0 : 3; 464 uint8_t int2_on_int1 : 1; 465 uint8_t drdy_mask : 1; 466 uint8_t int2_drdy_temp : 1; 467 uint8_t drdy_pulsed : 1; 468 uint8_t int2_in_lh : 1; 469 #endif /* DRV_BYTE_ORDER */ 470 } lsm6dsv_ctrl4_t; 471 472 #define LSM6DSV_CTRL5 0x14U 473 typedef struct 474 { 475 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 476 uint8_t int_en_i3c : 1; 477 uint8_t bus_act_sel : 2; 478 uint8_t not_used0 : 5; 479 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 480 uint8_t not_used0 : 5; 481 uint8_t bus_act_sel : 2; 482 uint8_t int_en_i3c : 1; 483 #endif /* DRV_BYTE_ORDER */ 484 } lsm6dsv_ctrl5_t; 485 486 #define LSM6DSV_CTRL6 0x15U 487 typedef struct 488 { 489 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 490 uint8_t fs_g : 4; 491 uint8_t lpf1_g_bw : 3; 492 uint8_t not_used0 : 1; 493 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 494 uint8_t not_used0 : 1; 495 uint8_t lpf1_g_bw : 3; 496 uint8_t fs_g : 4; 497 #endif /* DRV_BYTE_ORDER */ 498 } lsm6dsv_ctrl6_t; 499 500 #define LSM6DSV_CTRL7 0x16U 501 typedef struct 502 { 503 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 504 uint8_t lpf1_g_en : 1; 505 uint8_t not_used0 : 7; 506 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 507 uint8_t not_used0 : 7; 508 uint8_t lpf1_g_en : 1; 509 #endif /* DRV_BYTE_ORDER */ 510 } lsm6dsv_ctrl7_t; 511 512 #define LSM6DSV_CTRL8 0x17U 513 typedef struct 514 { 515 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 516 uint8_t fs_xl : 2; 517 uint8_t not_used0 : 1; 518 uint8_t xl_dualc_en : 1; 519 uint8_t not_used1 : 1; 520 uint8_t hp_lpf2_xl_bw : 3; 521 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 522 uint8_t hp_lpf2_xl_bw : 3; 523 uint8_t not_used1 : 1; 524 uint8_t xl_dualc_en : 1; 525 uint8_t not_used0 : 1; 526 uint8_t fs_xl : 2; 527 #endif /* DRV_BYTE_ORDER */ 528 } lsm6dsv_ctrl8_t; 529 530 #define LSM6DSV_CTRL9 0x18U 531 typedef struct 532 { 533 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 534 uint8_t usr_off_on_out : 1; 535 uint8_t usr_off_w : 1; 536 uint8_t not_used0 : 1; 537 uint8_t lpf2_xl_en : 1; 538 uint8_t hp_slope_xl_en : 1; 539 uint8_t xl_fastsettl_mode : 1; 540 uint8_t hp_ref_mode_xl : 1; 541 uint8_t not_used1 : 1; 542 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 543 uint8_t not_used1 : 1; 544 uint8_t hp_ref_mode_xl : 1; 545 uint8_t xl_fastsettl_mode : 1; 546 uint8_t hp_slope_xl_en : 1; 547 uint8_t lpf2_xl_en : 1; 548 uint8_t not_used0 : 1; 549 uint8_t usr_off_w : 1; 550 uint8_t usr_off_on_out : 1; 551 #endif /* DRV_BYTE_ORDER */ 552 } lsm6dsv_ctrl9_t; 553 554 #define LSM6DSV_CTRL10 0x19U 555 typedef struct 556 { 557 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 558 uint8_t st_xl : 2; 559 uint8_t st_g : 2; 560 uint8_t not_used0 : 2; 561 uint8_t emb_func_debug : 1; 562 uint8_t not_used1 : 1; 563 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 564 uint8_t not_used1 : 1; 565 uint8_t emb_func_debug : 1; 566 uint8_t not_used0 : 2; 567 uint8_t st_g : 2; 568 uint8_t st_xl : 2; 569 #endif /* DRV_BYTE_ORDER */ 570 } lsm6dsv_ctrl10_t; 571 572 #define LSM6DSV_CTRL_STATUS 0x1AU 573 typedef struct 574 { 575 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 576 uint8_t not_used0 : 2; 577 uint8_t fsm_wr_ctrl_status : 1; 578 uint8_t not_used1 : 5; 579 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 580 uint8_t not_used1 : 5; 581 uint8_t fsm_wr_ctrl_status : 1; 582 uint8_t not_used0 : 2; 583 #endif /* DRV_BYTE_ORDER */ 584 } lsm6dsv_ctrl_status_t; 585 586 #define LSM6DSV_FIFO_STATUS1 0x1BU 587 typedef struct 588 { 589 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 590 uint8_t diff_fifo : 8; 591 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 592 uint8_t diff_fifo : 8; 593 #endif /* DRV_BYTE_ORDER */ 594 } lsm6dsv_fifo_status1_t; 595 596 #define LSM6DSV_FIFO_STATUS2 0x1CU 597 typedef struct 598 { 599 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 600 uint8_t diff_fifo : 1; 601 uint8_t not_used0 : 2; 602 uint8_t fifo_ovr_latched : 1; 603 uint8_t counter_bdr_ia : 1; 604 uint8_t fifo_full_ia : 1; 605 uint8_t fifo_ovr_ia : 1; 606 uint8_t fifo_wtm_ia : 1; 607 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 608 uint8_t fifo_wtm_ia : 1; 609 uint8_t fifo_ovr_ia : 1; 610 uint8_t fifo_full_ia : 1; 611 uint8_t counter_bdr_ia : 1; 612 uint8_t fifo_ovr_latched : 1; 613 uint8_t not_used0 : 2; 614 uint8_t diff_fifo : 1; 615 #endif /* DRV_BYTE_ORDER */ 616 } lsm6dsv_fifo_status2_t; 617 618 #define LSM6DSV_ALL_INT_SRC 0x1DU 619 typedef struct 620 { 621 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 622 uint8_t ff_ia : 1; 623 uint8_t wu_ia : 1; 624 uint8_t tap_ia : 1; 625 uint8_t not_used0 : 1; 626 uint8_t d6d_ia : 1; 627 uint8_t sleep_change_ia : 1; 628 uint8_t shub_ia : 1; 629 uint8_t emb_func_ia : 1; 630 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 631 uint8_t emb_func_ia : 1; 632 uint8_t shub_ia : 1; 633 uint8_t sleep_change_ia : 1; 634 uint8_t d6d_ia : 1; 635 uint8_t not_used0 : 1; 636 uint8_t tap_ia : 1; 637 uint8_t wu_ia : 1; 638 uint8_t ff_ia : 1; 639 #endif /* DRV_BYTE_ORDER */ 640 } lsm6dsv_all_int_src_t; 641 642 #define LSM6DSV_STATUS_REG 0x1EU 643 typedef struct 644 { 645 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 646 uint8_t xlda : 1; 647 uint8_t gda : 1; 648 uint8_t tda : 1; 649 uint8_t not_used1 : 1; 650 uint8_t gda_eis : 1; 651 uint8_t ois_drdy : 1; 652 uint8_t not_used0 : 1; 653 uint8_t timestamp_endcount : 1; 654 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 655 uint8_t timestamp_endcount : 1; 656 uint8_t not_used0 : 1; 657 uint8_t ois_drdy : 1; 658 uint8_t gda_eis : 1; 659 uint8_t not_used1 : 1; 660 uint8_t tda : 1; 661 uint8_t gda : 1; 662 uint8_t xlda : 1; 663 #endif /* DRV_BYTE_ORDER */ 664 } lsm6dsv_status_reg_t; 665 666 #define LSM6DSV_OUT_TEMP_L 0x20U 667 typedef struct 668 { 669 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 670 uint8_t temp : 8; 671 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 672 uint8_t temp : 8; 673 #endif /* DRV_BYTE_ORDER */ 674 } lsm6dsv_out_temp_l_t; 675 676 #define LSM6DSV_OUT_TEMP_H 0x21U 677 typedef struct 678 { 679 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 680 uint8_t temp : 8; 681 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 682 uint8_t temp : 8; 683 #endif /* DRV_BYTE_ORDER */ 684 } lsm6dsv_out_temp_h_t; 685 686 #define LSM6DSV_OUTX_L_G 0x22U 687 typedef struct 688 { 689 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 690 uint8_t outx_g : 8; 691 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 692 uint8_t outx_g : 8; 693 #endif /* DRV_BYTE_ORDER */ 694 } lsm6dsv_outx_l_g_t; 695 696 #define LSM6DSV_OUTX_H_G 0x23U 697 typedef struct 698 { 699 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 700 uint8_t outx_g : 8; 701 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 702 uint8_t outx_g : 8; 703 #endif /* DRV_BYTE_ORDER */ 704 } lsm6dsv_outx_h_g_t; 705 706 #define LSM6DSV_OUTY_L_G 0x24U 707 typedef struct 708 { 709 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 710 uint8_t outy_g : 8; 711 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 712 uint8_t outy_g : 8; 713 #endif /* DRV_BYTE_ORDER */ 714 } lsm6dsv_outy_l_g_t; 715 716 #define LSM6DSV_OUTY_H_G 0x25U 717 typedef struct 718 { 719 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 720 uint8_t outy_g : 8; 721 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 722 uint8_t outy_g : 8; 723 #endif /* DRV_BYTE_ORDER */ 724 } lsm6dsv_outy_h_g_t; 725 726 #define LSM6DSV_OUTZ_L_G 0x26U 727 typedef struct 728 { 729 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 730 uint8_t outz_g : 8; 731 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 732 uint8_t outz_g : 8; 733 #endif /* DRV_BYTE_ORDER */ 734 } lsm6dsv_outz_l_g_t; 735 736 #define LSM6DSV_OUTZ_H_G 0x27U 737 typedef struct 738 { 739 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 740 uint8_t outz_g : 8; 741 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 742 uint8_t outz_g : 8; 743 #endif /* DRV_BYTE_ORDER */ 744 } lsm6dsv_outz_h_g_t; 745 746 #define LSM6DSV_OUTX_L_A 0x28U 747 typedef struct 748 { 749 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 750 uint8_t outx_a : 8; 751 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 752 uint8_t outx_a : 8; 753 #endif /* DRV_BYTE_ORDER */ 754 } lsm6dsv_outx_l_a_t; 755 756 #define LSM6DSV_OUTX_H_A 0x29U 757 typedef struct 758 { 759 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 760 uint8_t outx_a : 8; 761 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 762 uint8_t outx_a : 8; 763 #endif /* DRV_BYTE_ORDER */ 764 } lsm6dsv_outx_h_a_t; 765 766 #define LSM6DSV_OUTY_L_A 0x2AU 767 typedef struct 768 { 769 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 770 uint8_t outy_a : 8; 771 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 772 uint8_t outy_a : 8; 773 #endif /* DRV_BYTE_ORDER */ 774 } lsm6dsv_outy_l_a_t; 775 776 #define LSM6DSV_OUTY_H_A 0x2BU 777 typedef struct 778 { 779 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 780 uint8_t outy_a : 8; 781 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 782 uint8_t outy_a : 8; 783 #endif /* DRV_BYTE_ORDER */ 784 } lsm6dsv_outy_h_a_t; 785 786 #define LSM6DSV_OUTZ_L_A 0x2CU 787 typedef struct 788 { 789 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 790 uint8_t outz_a : 8; 791 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 792 uint8_t outz_a : 8; 793 #endif /* DRV_BYTE_ORDER */ 794 } lsm6dsv_outz_l_a_t; 795 796 #define LSM6DSV_OUTZ_H_A 0x2DU 797 typedef struct 798 { 799 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 800 uint8_t outz_a : 8; 801 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 802 uint8_t outz_a : 8; 803 #endif /* DRV_BYTE_ORDER */ 804 } lsm6dsv_outz_h_a_t; 805 806 #define LSM6DSV_UI_OUTX_L_G_OIS_EIS 0x2EU 807 typedef struct 808 { 809 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 810 uint8_t ui_outx_g_ois_eis : 8; 811 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 812 uint8_t ui_outx_g_ois_eis : 8; 813 #endif /* DRV_BYTE_ORDER */ 814 } lsm6dsv_ui_outx_l_g_ois_eis_t; 815 816 #define LSM6DSV_UI_OUTX_H_G_OIS_EIS 0x2FU 817 typedef struct 818 { 819 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 820 uint8_t ui_outx_g_ois_eis : 8; 821 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 822 uint8_t ui_outx_g_ois_eis : 8; 823 #endif /* DRV_BYTE_ORDER */ 824 } lsm6dsv_ui_outx_h_g_ois_eis_t; 825 826 #define LSM6DSV_UI_OUTY_L_G_OIS_EIS 0x30U 827 typedef struct 828 { 829 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 830 uint8_t ui_outy_g_ois_eis : 8; 831 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 832 uint8_t ui_outy_g_ois_eis : 8; 833 #endif /* DRV_BYTE_ORDER */ 834 } lsm6dsv_ui_outy_l_g_ois_eis_t; 835 836 #define LSM6DSV_UI_OUTY_H_G_OIS_EIS 0x31U 837 typedef struct 838 { 839 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 840 uint8_t ui_outy_g_ois_eis : 8; 841 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 842 uint8_t ui_outy_g_ois_eis : 8; 843 #endif /* DRV_BYTE_ORDER */ 844 } lsm6dsv_ui_outy_h_g_ois_eis_t; 845 846 #define LSM6DSV_UI_OUTZ_L_G_OIS_EIS 0x32U 847 typedef struct 848 { 849 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 850 uint8_t ui_outz_g_ois_eis : 8; 851 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 852 uint8_t ui_outz_g_ois_eis : 8; 853 #endif /* DRV_BYTE_ORDER */ 854 } lsm6dsv_ui_outz_l_g_ois_eis_t; 855 856 #define LSM6DSV_UI_OUTZ_H_G_OIS_EIS 0x33U 857 typedef struct 858 { 859 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 860 uint8_t ui_outz_g_ois_eis : 8; 861 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 862 uint8_t ui_outz_g_ois_eis : 8; 863 #endif /* DRV_BYTE_ORDER */ 864 } lsm6dsv_ui_outz_h_g_ois_eis_t; 865 866 #define LSM6DSV_UI_OUTX_L_A_OIS_DUALC 0x34U 867 typedef struct 868 { 869 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 870 uint8_t ui_outx_a_ois_dualc : 8; 871 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 872 uint8_t ui_outx_a_ois_dualc : 8; 873 #endif /* DRV_BYTE_ORDER */ 874 } lsm6dsv_ui_outx_l_a_ois_dualc_t; 875 876 #define LSM6DSV_UI_OUTX_H_A_OIS_DUALC 0x35U 877 typedef struct 878 { 879 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 880 uint8_t ui_outx_a_ois_dualc : 8; 881 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 882 uint8_t ui_outx_a_ois_dualc : 8; 883 #endif /* DRV_BYTE_ORDER */ 884 } lsm6dsv_ui_outx_h_a_ois_dualc_t; 885 886 #define LSM6DSV_UI_OUTY_L_A_OIS_DUALC 0x36U 887 typedef struct 888 { 889 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 890 uint8_t ui_outy_a_ois_dualc : 8; 891 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 892 uint8_t ui_outy_a_ois_dualc : 8; 893 #endif /* DRV_BYTE_ORDER */ 894 } lsm6dsv_ui_outy_l_a_ois_dualc_t; 895 896 #define LSM6DSV_UI_OUTY_H_A_OIS_DUALC 0x37U 897 typedef struct 898 { 899 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 900 uint8_t ui_outy_a_ois_dualc : 8; 901 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 902 uint8_t ui_outy_a_ois_dualc : 8; 903 #endif /* DRV_BYTE_ORDER */ 904 } lsm6dsv_ui_outy_h_a_ois_dualc_t; 905 906 #define LSM6DSV_UI_OUTZ_L_A_OIS_DUALC 0x38U 907 typedef struct 908 { 909 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 910 uint8_t ui_outz_a_ois_dualc : 8; 911 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 912 uint8_t ui_outz_a_ois_dualc : 8; 913 #endif /* DRV_BYTE_ORDER */ 914 } lsm6dsv_ui_outz_l_a_ois_dualc_t; 915 916 #define LSM6DSV_UI_OUTZ_H_A_OIS_DUALC 0x39U 917 typedef struct 918 { 919 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 920 uint8_t ui_outz_a_ois_dualc : 8; 921 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 922 uint8_t ui_outz_a_ois_dualc : 8; 923 #endif /* DRV_BYTE_ORDER */ 924 } lsm6dsv_ui_outz_h_a_ois_dualc_t; 925 926 #define LSM6DSV_TIMESTAMP0 0x40U 927 typedef struct 928 { 929 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 930 uint8_t timestamp : 8; 931 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 932 uint8_t timestamp : 8; 933 #endif /* DRV_BYTE_ORDER */ 934 } lsm6dsv_timestamp0_t; 935 936 #define LSM6DSV_TIMESTAMP1 0x41U 937 typedef struct 938 { 939 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 940 uint8_t timestamp : 8; 941 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 942 uint8_t timestamp : 8; 943 #endif /* DRV_BYTE_ORDER */ 944 } lsm6dsv_timestamp1_t; 945 946 #define LSM6DSV_TIMESTAMP2 0x42U 947 typedef struct 948 { 949 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 950 uint8_t timestamp : 8; 951 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 952 uint8_t timestamp : 8; 953 #endif /* DRV_BYTE_ORDER */ 954 } lsm6dsv_timestamp2_t; 955 956 #define LSM6DSV_TIMESTAMP3 0x43U 957 typedef struct 958 { 959 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 960 uint8_t timestamp : 8; 961 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 962 uint8_t timestamp : 8; 963 #endif /* DRV_BYTE_ORDER */ 964 } lsm6dsv_timestamp3_t; 965 966 #define LSM6DSV_UI_STATUS_REG_OIS 0x44U 967 typedef struct 968 { 969 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 970 uint8_t xlda_ois : 1; 971 uint8_t gda_ois : 1; 972 uint8_t gyro_settling : 1; 973 uint8_t not_used0 : 5; 974 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 975 uint8_t not_used0 : 5; 976 uint8_t gyro_settling : 1; 977 uint8_t gda_ois : 1; 978 uint8_t xlda_ois : 1; 979 #endif /* DRV_BYTE_ORDER */ 980 } lsm6dsv_ui_status_reg_ois_t; 981 982 #define LSM6DSV_WAKE_UP_SRC 0x45U 983 typedef struct 984 { 985 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 986 uint8_t z_wu : 1; 987 uint8_t y_wu : 1; 988 uint8_t x_wu : 1; 989 uint8_t wu_ia : 1; 990 uint8_t sleep_state : 1; 991 uint8_t ff_ia : 1; 992 uint8_t sleep_change_ia : 1; 993 uint8_t not_used0 : 1; 994 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 995 uint8_t not_used0 : 1; 996 uint8_t sleep_change_ia : 1; 997 uint8_t ff_ia : 1; 998 uint8_t sleep_state : 1; 999 uint8_t wu_ia : 1; 1000 uint8_t x_wu : 1; 1001 uint8_t y_wu : 1; 1002 uint8_t z_wu : 1; 1003 #endif /* DRV_BYTE_ORDER */ 1004 } lsm6dsv_wake_up_src_t; 1005 1006 #define LSM6DSV_TAP_SRC 0x46U 1007 typedef struct 1008 { 1009 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1010 uint8_t z_tap : 1; 1011 uint8_t y_tap : 1; 1012 uint8_t x_tap : 1; 1013 uint8_t tap_sign : 1; 1014 uint8_t double_tap : 1; 1015 uint8_t single_tap : 1; 1016 uint8_t tap_ia : 1; 1017 uint8_t not_used0 : 1; 1018 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1019 uint8_t not_used0 : 1; 1020 uint8_t tap_ia : 1; 1021 uint8_t single_tap : 1; 1022 uint8_t double_tap : 1; 1023 uint8_t tap_sign : 1; 1024 uint8_t x_tap : 1; 1025 uint8_t y_tap : 1; 1026 uint8_t z_tap : 1; 1027 #endif /* DRV_BYTE_ORDER */ 1028 } lsm6dsv_tap_src_t; 1029 1030 #define LSM6DSV_D6D_SRC 0x47U 1031 typedef struct 1032 { 1033 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1034 uint8_t xl : 1; 1035 uint8_t xh : 1; 1036 uint8_t yl : 1; 1037 uint8_t yh : 1; 1038 uint8_t zl : 1; 1039 uint8_t zh : 1; 1040 uint8_t d6d_ia : 1; 1041 uint8_t not_used0 : 1; 1042 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1043 uint8_t not_used0 : 1; 1044 uint8_t d6d_ia : 1; 1045 uint8_t zh : 1; 1046 uint8_t zl : 1; 1047 uint8_t yh : 1; 1048 uint8_t yl : 1; 1049 uint8_t xh : 1; 1050 uint8_t xl : 1; 1051 #endif /* DRV_BYTE_ORDER */ 1052 } lsm6dsv_d6d_src_t; 1053 1054 #define LSM6DSV_STATUS_MASTER_MAINPAGE 0x48U 1055 typedef struct 1056 { 1057 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1058 uint8_t sens_hub_endop : 1; 1059 uint8_t not_used0 : 2; 1060 uint8_t slave0_nack : 1; 1061 uint8_t slave1_nack : 1; 1062 uint8_t slave2_nack : 1; 1063 uint8_t slave3_nack : 1; 1064 uint8_t wr_once_done : 1; 1065 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1066 uint8_t wr_once_done : 1; 1067 uint8_t slave3_nack : 1; 1068 uint8_t slave2_nack : 1; 1069 uint8_t slave1_nack : 1; 1070 uint8_t slave0_nack : 1; 1071 uint8_t not_used0 : 2; 1072 uint8_t sens_hub_endop : 1; 1073 #endif /* DRV_BYTE_ORDER */ 1074 } lsm6dsv_status_master_mainpage_t; 1075 1076 #define LSM6DSV_EMB_FUNC_STATUS_MAINPAGE 0x49U 1077 typedef struct 1078 { 1079 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1080 uint8_t not_used0 : 3; 1081 uint8_t is_step_det : 1; 1082 uint8_t is_tilt : 1; 1083 uint8_t is_sigmot : 1; 1084 uint8_t not_used1 : 1; 1085 uint8_t is_fsm_lc : 1; 1086 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1087 uint8_t is_fsm_lc : 1; 1088 uint8_t not_used1 : 1; 1089 uint8_t is_sigmot : 1; 1090 uint8_t is_tilt : 1; 1091 uint8_t is_step_det : 1; 1092 uint8_t not_used0 : 3; 1093 #endif /* DRV_BYTE_ORDER */ 1094 } lsm6dsv_emb_func_status_mainpage_t; 1095 1096 #define LSM6DSV_FSM_STATUS_MAINPAGE 0x4AU 1097 typedef struct 1098 { 1099 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1100 uint8_t is_fsm1 : 1; 1101 uint8_t is_fsm2 : 1; 1102 uint8_t is_fsm3 : 1; 1103 uint8_t is_fsm4 : 1; 1104 uint8_t is_fsm5 : 1; 1105 uint8_t is_fsm6 : 1; 1106 uint8_t is_fsm7 : 1; 1107 uint8_t is_fsm8 : 1; 1108 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1109 uint8_t is_fsm8 : 1; 1110 uint8_t is_fsm7 : 1; 1111 uint8_t is_fsm6 : 1; 1112 uint8_t is_fsm5 : 1; 1113 uint8_t is_fsm4 : 1; 1114 uint8_t is_fsm3 : 1; 1115 uint8_t is_fsm2 : 1; 1116 uint8_t is_fsm1 : 1; 1117 #endif /* DRV_BYTE_ORDER */ 1118 } lsm6dsv_fsm_status_mainpage_t; 1119 1120 #define LSM6DSV_INTERNAL_FREQ 0x4FU 1121 typedef struct 1122 { 1123 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1124 uint8_t freq_fine : 8; 1125 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1126 uint8_t freq_fine : 8; 1127 #endif /* DRV_BYTE_ORDER */ 1128 } lsm6dsv_internal_freq_t; 1129 1130 #define LSM6DSV_FUNCTIONS_ENABLE 0x50U 1131 typedef struct 1132 { 1133 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1134 uint8_t inact_en : 2; 1135 uint8_t not_used0 : 1; 1136 uint8_t dis_rst_lir_all_int : 1; 1137 uint8_t not_used1 : 2; 1138 uint8_t timestamp_en : 1; 1139 uint8_t interrupts_enable : 1; 1140 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1141 uint8_t interrupts_enable : 1; 1142 uint8_t timestamp_en : 1; 1143 uint8_t not_used1 : 2; 1144 uint8_t dis_rst_lir_all_int : 1; 1145 uint8_t not_used0 : 1; 1146 uint8_t inact_en : 2; 1147 #endif /* DRV_BYTE_ORDER */ 1148 } lsm6dsv_functions_enable_t; 1149 1150 #define LSM6DSV_DEN 0x51U 1151 typedef struct 1152 { 1153 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1154 uint8_t den_xl_g : 1; 1155 uint8_t den_z : 1; 1156 uint8_t den_y : 1; 1157 uint8_t den_x : 1; 1158 uint8_t den_xl_en : 1; 1159 uint8_t lvl2_en : 1; 1160 uint8_t lvl1_en : 1; 1161 uint8_t not_used0 : 1; 1162 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1163 uint8_t not_used0 : 1; 1164 uint8_t lvl1_en : 1; 1165 uint8_t lvl2_en : 1; 1166 uint8_t den_xl_en : 1; 1167 uint8_t den_x : 1; 1168 uint8_t den_y : 1; 1169 uint8_t den_z : 1; 1170 uint8_t den_xl_g : 1; 1171 #endif /* DRV_BYTE_ORDER */ 1172 } lsm6dsv_den_t; 1173 1174 #define LSM6DSV_INACTIVITY_DUR 0x54U 1175 typedef struct 1176 { 1177 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1178 uint8_t inact_dur : 2; 1179 uint8_t xl_inact_odr : 2; 1180 uint8_t wu_inact_ths_w : 3; 1181 uint8_t sleep_status_on_int : 1; 1182 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1183 uint8_t sleep_status_on_int : 1; 1184 uint8_t wu_inact_ths_w : 3; 1185 uint8_t xl_inact_odr : 2; 1186 uint8_t inact_dur : 2; 1187 #endif /* DRV_BYTE_ORDER */ 1188 } lsm6dsv_inactivity_dur_t; 1189 1190 #define LSM6DSV_INACTIVITY_THS 0x55U 1191 typedef struct 1192 { 1193 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1194 uint8_t inact_ths : 6; 1195 uint8_t not_used0 : 2; 1196 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1197 uint8_t not_used0 : 2; 1198 uint8_t inact_ths : 6; 1199 #endif /* DRV_BYTE_ORDER */ 1200 } lsm6dsv_inactivity_ths_t; 1201 1202 #define LSM6DSV_TAP_CFG0 0x56U 1203 typedef struct 1204 { 1205 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1206 uint8_t lir : 1; 1207 uint8_t tap_z_en : 1; 1208 uint8_t tap_y_en : 1; 1209 uint8_t tap_x_en : 1; 1210 uint8_t slope_fds : 1; 1211 uint8_t hw_func_mask_xl_settl : 1; 1212 uint8_t low_pass_on_6d : 1; 1213 uint8_t not_used1 : 1; 1214 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1215 uint8_t not_used1 : 1; 1216 uint8_t low_pass_on_6d : 1; 1217 uint8_t hw_func_mask_xl_settl : 1; 1218 uint8_t slope_fds : 1; 1219 uint8_t tap_x_en : 1; 1220 uint8_t tap_y_en : 1; 1221 uint8_t tap_z_en : 1; 1222 uint8_t lir : 1; 1223 #endif /* DRV_BYTE_ORDER */ 1224 } lsm6dsv_tap_cfg0_t; 1225 1226 #define LSM6DSV_TAP_CFG1 0x57U 1227 typedef struct 1228 { 1229 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1230 uint8_t tap_ths_x : 5; 1231 uint8_t tap_priority : 3; 1232 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1233 uint8_t tap_priority : 3; 1234 uint8_t tap_ths_x : 5; 1235 #endif /* DRV_BYTE_ORDER */ 1236 } lsm6dsv_tap_cfg1_t; 1237 1238 #define LSM6DSV_TAP_CFG2 0x58U 1239 typedef struct 1240 { 1241 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1242 uint8_t tap_ths_y : 5; 1243 uint8_t not_used0 : 3; 1244 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1245 uint8_t not_used0 : 3; 1246 uint8_t tap_ths_y : 5; 1247 #endif /* DRV_BYTE_ORDER */ 1248 } lsm6dsv_tap_cfg2_t; 1249 1250 #define LSM6DSV_TAP_THS_6D 0x59U 1251 typedef struct 1252 { 1253 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1254 uint8_t tap_ths_z : 5; 1255 uint8_t sixd_ths : 2; 1256 uint8_t d4d_en : 1; 1257 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1258 uint8_t d4d_en : 1; 1259 uint8_t sixd_ths : 2; 1260 uint8_t tap_ths_z : 5; 1261 #endif /* DRV_BYTE_ORDER */ 1262 } lsm6dsv_tap_ths_6d_t; 1263 1264 #define LSM6DSV_TAP_DUR 0x5AU 1265 typedef struct 1266 { 1267 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1268 uint8_t shock : 2; 1269 uint8_t quiet : 2; 1270 uint8_t dur : 4; 1271 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1272 uint8_t dur : 4; 1273 uint8_t quiet : 2; 1274 uint8_t shock : 2; 1275 #endif /* DRV_BYTE_ORDER */ 1276 } lsm6dsv_tap_dur_t; 1277 1278 #define LSM6DSV_WAKE_UP_THS 0x5BU 1279 typedef struct 1280 { 1281 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1282 uint8_t wk_ths : 6; 1283 uint8_t usr_off_on_wu : 1; 1284 uint8_t single_double_tap : 1; 1285 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1286 uint8_t single_double_tap : 1; 1287 uint8_t usr_off_on_wu : 1; 1288 uint8_t wk_ths : 6; 1289 #endif /* DRV_BYTE_ORDER */ 1290 } lsm6dsv_wake_up_ths_t; 1291 1292 #define LSM6DSV_WAKE_UP_DUR 0x5CU 1293 typedef struct 1294 { 1295 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1296 uint8_t sleep_dur : 4; 1297 uint8_t not_used0 : 1; 1298 uint8_t wake_dur : 2; 1299 uint8_t ff_dur : 1; 1300 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1301 uint8_t ff_dur : 1; 1302 uint8_t wake_dur : 2; 1303 uint8_t not_used0 : 1; 1304 uint8_t sleep_dur : 4; 1305 #endif /* DRV_BYTE_ORDER */ 1306 } lsm6dsv_wake_up_dur_t; 1307 1308 #define LSM6DSV_FREE_FALL 0x5DU 1309 typedef struct 1310 { 1311 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1312 uint8_t ff_ths : 3; 1313 uint8_t ff_dur : 5; 1314 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1315 uint8_t ff_dur : 5; 1316 uint8_t ff_ths : 3; 1317 #endif /* DRV_BYTE_ORDER */ 1318 } lsm6dsv_free_fall_t; 1319 1320 #define LSM6DSV_MD1_CFG 0x5EU 1321 typedef struct 1322 { 1323 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1324 uint8_t int1_shub : 1; 1325 uint8_t int1_emb_func : 1; 1326 uint8_t int1_6d : 1; 1327 uint8_t int1_double_tap : 1; 1328 uint8_t int1_ff : 1; 1329 uint8_t int1_wu : 1; 1330 uint8_t int1_single_tap : 1; 1331 uint8_t int1_sleep_change : 1; 1332 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1333 uint8_t int1_sleep_change : 1; 1334 uint8_t int1_single_tap : 1; 1335 uint8_t int1_wu : 1; 1336 uint8_t int1_ff : 1; 1337 uint8_t int1_double_tap : 1; 1338 uint8_t int1_6d : 1; 1339 uint8_t int1_emb_func : 1; 1340 uint8_t int1_shub : 1; 1341 #endif /* DRV_BYTE_ORDER */ 1342 } lsm6dsv_md1_cfg_t; 1343 1344 #define LSM6DSV_MD2_CFG 0x5FU 1345 typedef struct 1346 { 1347 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1348 uint8_t int2_timestamp : 1; 1349 uint8_t int2_emb_func : 1; 1350 uint8_t int2_6d : 1; 1351 uint8_t int2_double_tap : 1; 1352 uint8_t int2_ff : 1; 1353 uint8_t int2_wu : 1; 1354 uint8_t int2_single_tap : 1; 1355 uint8_t int2_sleep_change : 1; 1356 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1357 uint8_t int2_sleep_change : 1; 1358 uint8_t int2_single_tap : 1; 1359 uint8_t int2_wu : 1; 1360 uint8_t int2_ff : 1; 1361 uint8_t int2_double_tap : 1; 1362 uint8_t int2_6d : 1; 1363 uint8_t int2_emb_func : 1; 1364 uint8_t int2_timestamp : 1; 1365 #endif /* DRV_BYTE_ORDER */ 1366 } lsm6dsv_md2_cfg_t; 1367 1368 #define LSM6DSV_HAODR_CFG 0x62U 1369 typedef struct 1370 { 1371 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1372 uint8_t haodr_sel : 2; 1373 uint8_t not_used0 : 6; 1374 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1375 uint8_t not_used0 : 6; 1376 uint8_t haodr_sel : 2; 1377 #endif /* DRV_BYTE_ORDER */ 1378 } lsm6dsv_haodr_cfg_t; 1379 1380 #define LSM6DSV_EMB_FUNC_CFG 0x63U 1381 typedef struct 1382 { 1383 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1384 uint8_t not_used0 : 3; 1385 uint8_t emb_func_disable : 1; 1386 uint8_t emb_func_irq_mask_xl_settl : 1; 1387 uint8_t emb_func_irq_mask_g_settl : 1; 1388 uint8_t not_used1 : 2; 1389 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1390 uint8_t not_used1 : 2; 1391 uint8_t emb_func_irq_mask_g_settl : 1; 1392 uint8_t emb_func_irq_mask_xl_settl : 1; 1393 uint8_t emb_func_disable : 1; 1394 uint8_t not_used0 : 3; 1395 #endif /* DRV_BYTE_ORDER */ 1396 } lsm6dsv_emb_func_cfg_t; 1397 1398 #define LSM6DSV_UI_HANDSHAKE_CTRL 0x64U 1399 typedef struct 1400 { 1401 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1402 uint8_t ui_shared_req : 1; 1403 uint8_t ui_shared_ack : 1; 1404 uint8_t not_used0 : 6; 1405 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1406 uint8_t not_used0 : 6; 1407 uint8_t ui_shared_ack : 1; 1408 uint8_t ui_shared_req : 1; 1409 #endif /* DRV_BYTE_ORDER */ 1410 } lsm6dsv_ui_handshake_ctrl_t; 1411 1412 #define LSM6DSV_UI_SPI2_SHARED_0 0x65U 1413 typedef struct 1414 { 1415 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1416 uint8_t ui_spi2_shared : 8; 1417 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1418 uint8_t ui_spi2_shared : 8; 1419 #endif /* DRV_BYTE_ORDER */ 1420 } lsm6dsv_ui_spi2_shared_0_t; 1421 1422 #define LSM6DSV_UI_SPI2_SHARED_1 0x66U 1423 typedef struct 1424 { 1425 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1426 uint8_t ui_spi2_shared : 8; 1427 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1428 uint8_t ui_spi2_shared : 8; 1429 #endif /* DRV_BYTE_ORDER */ 1430 } lsm6dsv_ui_spi2_shared_1_t; 1431 1432 #define LSM6DSV_UI_SPI2_SHARED_2 0x67U 1433 typedef struct 1434 { 1435 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1436 uint8_t ui_spi2_shared : 8; 1437 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1438 uint8_t ui_spi2_shared : 8; 1439 #endif /* DRV_BYTE_ORDER */ 1440 } lsm6dsv_ui_spi2_shared_2_t; 1441 1442 #define LSM6DSV_UI_SPI2_SHARED_3 0x68U 1443 typedef struct 1444 { 1445 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1446 uint8_t ui_spi2_shared : 8; 1447 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1448 uint8_t ui_spi2_shared : 8; 1449 #endif /* DRV_BYTE_ORDER */ 1450 } lsm6dsv_ui_spi2_shared_3_t; 1451 1452 #define LSM6DSV_UI_SPI2_SHARED_4 0x69U 1453 typedef struct 1454 { 1455 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1456 uint8_t ui_spi2_shared : 8; 1457 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1458 uint8_t ui_spi2_shared : 8; 1459 #endif /* DRV_BYTE_ORDER */ 1460 } lsm6dsv_ui_spi2_shared_4_t; 1461 1462 #define LSM6DSV_UI_SPI2_SHARED_5 0x6AU 1463 typedef struct 1464 { 1465 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1466 uint8_t ui_spi2_shared : 8; 1467 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1468 uint8_t ui_spi2_shared : 8; 1469 #endif /* DRV_BYTE_ORDER */ 1470 } lsm6dsv_ui_spi2_shared_5_t; 1471 1472 #define LSM6DSV_CTRL_EIS 0x6BU 1473 typedef struct 1474 { 1475 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1476 uint8_t fs_g_eis : 3; 1477 uint8_t g_eis_on_g_ois_out_reg : 1; 1478 uint8_t lpf_g_eis_bw : 1; 1479 uint8_t not_used0 : 1; 1480 uint8_t odr_g_eis : 2; 1481 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1482 uint8_t odr_g_eis : 2; 1483 uint8_t not_used0 : 1; 1484 uint8_t lpf_g_eis_bw : 1; 1485 uint8_t g_eis_on_g_ois_out_reg : 1; 1486 uint8_t fs_g_eis : 3; 1487 #endif /* DRV_BYTE_ORDER */ 1488 } lsm6dsv_ctrl_eis_t; 1489 1490 #define LSM6DSV_UI_INT_OIS 0x6FU 1491 typedef struct 1492 { 1493 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1494 uint8_t not_used0 : 4; 1495 uint8_t st_ois_clampdis : 1; 1496 uint8_t not_used1 : 1; 1497 uint8_t drdy_mask_ois : 1; 1498 uint8_t int2_drdy_ois : 1; 1499 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1500 uint8_t int2_drdy_ois : 1; 1501 uint8_t drdy_mask_ois : 1; 1502 uint8_t not_used1 : 1; 1503 uint8_t st_ois_clampdis : 1; 1504 uint8_t not_used0 : 4; 1505 #endif /* DRV_BYTE_ORDER */ 1506 } lsm6dsv_ui_int_ois_t; 1507 1508 #define LSM6DSV_UI_CTRL1_OIS 0x70U 1509 typedef struct 1510 { 1511 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1512 uint8_t spi2_read_en : 1; 1513 uint8_t ois_g_en : 1; 1514 uint8_t ois_xl_en : 1; 1515 uint8_t not_used0 : 2; 1516 uint8_t sim_ois : 1; 1517 uint8_t not_used1 : 2; 1518 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1519 uint8_t not_used1 : 2; 1520 uint8_t sim_ois : 1; 1521 uint8_t not_used0 : 2; 1522 uint8_t ois_xl_en : 1; 1523 uint8_t ois_g_en : 1; 1524 uint8_t spi2_read_en : 1; 1525 #endif /* DRV_BYTE_ORDER */ 1526 } lsm6dsv_ui_ctrl1_ois_t; 1527 1528 #define LSM6DSV_UI_CTRL2_OIS 0x71U 1529 typedef struct 1530 { 1531 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1532 uint8_t fs_g_ois : 3; 1533 uint8_t lpf1_g_ois_bw : 2; 1534 uint8_t not_used0 : 3; 1535 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1536 uint8_t not_used0 : 3; 1537 uint8_t lpf1_g_ois_bw : 2; 1538 uint8_t fs_g_ois : 3; 1539 #endif /* DRV_BYTE_ORDER */ 1540 } lsm6dsv_ui_ctrl2_ois_t; 1541 1542 #define LSM6DSV_UI_CTRL3_OIS 0x72U 1543 typedef struct 1544 { 1545 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1546 uint8_t fs_xl_ois : 2; 1547 uint8_t not_used0 : 1; 1548 uint8_t lpf_xl_ois_bw : 3; 1549 uint8_t not_used1 : 2; 1550 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1551 uint8_t not_used1 : 2; 1552 uint8_t lpf_xl_ois_bw : 3; 1553 uint8_t not_used0 : 1; 1554 uint8_t fs_xl_ois : 2; 1555 #endif /* DRV_BYTE_ORDER */ 1556 } lsm6dsv_ui_ctrl3_ois_t; 1557 1558 #define LSM6DSV_X_OFS_USR 0x73U 1559 typedef struct 1560 { 1561 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1562 uint8_t x_ofs_usr : 8; 1563 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1564 uint8_t x_ofs_usr : 8; 1565 #endif /* DRV_BYTE_ORDER */ 1566 } lsm6dsv_x_ofs_usr_t; 1567 1568 #define LSM6DSV_Y_OFS_USR 0x74U 1569 typedef struct 1570 { 1571 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1572 uint8_t y_ofs_usr : 8; 1573 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1574 uint8_t y_ofs_usr : 8; 1575 #endif /* DRV_BYTE_ORDER */ 1576 } lsm6dsv_y_ofs_usr_t; 1577 1578 #define LSM6DSV_Z_OFS_USR 0x75U 1579 typedef struct 1580 { 1581 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1582 uint8_t z_ofs_usr : 8; 1583 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1584 uint8_t z_ofs_usr : 8; 1585 #endif /* DRV_BYTE_ORDER */ 1586 } lsm6dsv_z_ofs_usr_t; 1587 1588 #define LSM6DSV_FIFO_DATA_OUT_TAG 0x78U 1589 typedef struct 1590 { 1591 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1592 uint8_t not_used0 : 1; 1593 uint8_t tag_cnt : 2; 1594 uint8_t tag_sensor : 5; 1595 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1596 uint8_t tag_sensor : 5; 1597 uint8_t tag_cnt : 2; 1598 uint8_t not_used0 : 1; 1599 #endif /* DRV_BYTE_ORDER */ 1600 } lsm6dsv_fifo_data_out_tag_t; 1601 1602 #define LSM6DSV_FIFO_DATA_OUT_X_L 0x79U 1603 typedef struct 1604 { 1605 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1606 uint8_t fifo_data_out : 8; 1607 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1608 uint8_t fifo_data_out : 8; 1609 #endif /* DRV_BYTE_ORDER */ 1610 } lsm6dsv_fifo_data_out_x_l_t; 1611 1612 #define LSM6DSV_FIFO_DATA_OUT_X_H 0x7AU 1613 typedef struct 1614 { 1615 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1616 uint8_t fifo_data_out : 8; 1617 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1618 uint8_t fifo_data_out : 8; 1619 #endif /* DRV_BYTE_ORDER */ 1620 } lsm6dsv_fifo_data_out_x_h_t; 1621 1622 #define LSM6DSV_FIFO_DATA_OUT_Y_L 0x7BU 1623 typedef struct 1624 { 1625 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1626 uint8_t fifo_data_out : 8; 1627 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1628 uint8_t fifo_data_out : 8; 1629 #endif /* DRV_BYTE_ORDER */ 1630 } lsm6dsv_fifo_data_out_y_l_t; 1631 1632 #define LSM6DSV_FIFO_DATA_OUT_Y_H 0x7CU 1633 typedef struct 1634 { 1635 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1636 uint8_t fifo_data_out : 8; 1637 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1638 uint8_t fifo_data_out : 8; 1639 #endif /* DRV_BYTE_ORDER */ 1640 } lsm6dsv_fifo_data_out_y_h_t; 1641 1642 #define LSM6DSV_FIFO_DATA_OUT_Z_L 0x7DU 1643 typedef struct 1644 { 1645 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1646 uint8_t fifo_data_out : 8; 1647 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1648 uint8_t fifo_data_out : 8; 1649 #endif /* DRV_BYTE_ORDER */ 1650 } lsm6dsv_fifo_data_out_z_l_t; 1651 1652 #define LSM6DSV_FIFO_DATA_OUT_Z_H 0x7EU 1653 typedef struct 1654 { 1655 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1656 uint8_t fifo_data_out : 8; 1657 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1658 uint8_t fifo_data_out : 8; 1659 #endif /* DRV_BYTE_ORDER */ 1660 } lsm6dsv_fifo_data_out_z_h_t; 1661 1662 /** 1663 * @} 1664 * 1665 */ 1666 1667 /** @defgroup bitfields page spi2 1668 * @{ 1669 * 1670 */ 1671 1672 #define LSM6DSV_SPI2_WHO_AM_I 0x0FU 1673 typedef struct 1674 { 1675 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1676 uint8_t id : 8; 1677 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1678 uint8_t id : 8; 1679 #endif /* DRV_BYTE_ORDER */ 1680 } lsm6dsv_spi2_who_am_i_t; 1681 1682 #define LSM6DSV_SPI2_STATUS_REG_OIS 0x1EU 1683 typedef struct 1684 { 1685 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1686 uint8_t xlda : 1; 1687 uint8_t gda : 1; 1688 uint8_t gyro_settling : 1; 1689 uint8_t not_used0 : 5; 1690 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1691 uint8_t not_used0 : 5; 1692 uint8_t gyro_settling : 1; 1693 uint8_t gda : 1; 1694 uint8_t xlda : 1; 1695 #endif /* DRV_BYTE_ORDER */ 1696 } lsm6dsv_spi2_status_reg_ois_t; 1697 1698 #define LSM6DSV_SPI2_OUT_TEMP_L 0x20U 1699 typedef struct 1700 { 1701 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1702 uint8_t temp : 8; 1703 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1704 uint8_t temp : 8; 1705 #endif /* DRV_BYTE_ORDER */ 1706 } lsm6dsv_spi2_out_temp_l_t; 1707 1708 #define LSM6DSV_SPI2_OUT_TEMP_H 0x21U 1709 typedef struct 1710 { 1711 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1712 uint8_t temp : 8; 1713 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1714 uint8_t temp : 8; 1715 #endif /* DRV_BYTE_ORDER */ 1716 } lsm6dsv_spi2_out_temp_h_t; 1717 1718 #define LSM6DSV_SPI2_OUTX_L_G_OIS 0x22U 1719 typedef struct 1720 { 1721 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1722 uint8_t spi2_outx_g_ois : 8; 1723 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1724 uint8_t spi2_outx_g_ois : 8; 1725 #endif /* DRV_BYTE_ORDER */ 1726 } lsm6dsv_spi2_outx_l_g_ois_t; 1727 1728 #define LSM6DSV_SPI2_OUTX_H_G_OIS 0x23U 1729 typedef struct 1730 { 1731 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1732 uint8_t spi2_outx_g_ois : 8; 1733 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1734 uint8_t spi2_outx_g_ois : 8; 1735 #endif /* DRV_BYTE_ORDER */ 1736 } lsm6dsv_spi2_outx_h_g_ois_t; 1737 1738 #define LSM6DSV_SPI2_OUTY_L_G_OIS 0x24U 1739 typedef struct 1740 { 1741 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1742 uint8_t spi2_outy_g_ois : 8; 1743 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1744 uint8_t spi2_outy_g_ois : 8; 1745 #endif /* DRV_BYTE_ORDER */ 1746 } lsm6dsv_spi2_outy_l_g_ois_t; 1747 1748 #define LSM6DSV_SPI2_OUTY_H_G_OIS 0x25U 1749 typedef struct 1750 { 1751 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1752 uint8_t spi2_outy_g_ois : 8; 1753 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1754 uint8_t spi2_outy_g_ois : 8; 1755 #endif /* DRV_BYTE_ORDER */ 1756 } lsm6dsv_spi2_outy_h_g_ois_t; 1757 1758 #define LSM6DSV_SPI2_OUTZ_L_G_OIS 0x26U 1759 typedef struct 1760 { 1761 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1762 uint8_t spi2_outz_g_ois : 8; 1763 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1764 uint8_t spi2_outz_g_ois : 8; 1765 #endif /* DRV_BYTE_ORDER */ 1766 } lsm6dsv_spi2_outz_l_g_ois_t; 1767 1768 #define LSM6DSV_SPI2_OUTZ_H_G_OIS 0x27U 1769 typedef struct 1770 { 1771 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1772 uint8_t spi2_outz_g_ois : 8; 1773 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1774 uint8_t spi2_outz_g_ois : 8; 1775 #endif /* DRV_BYTE_ORDER */ 1776 } lsm6dsv_spi2_outz_h_g_ois_t; 1777 1778 #define LSM6DSV_SPI2_OUTX_L_A_OIS 0x28U 1779 typedef struct 1780 { 1781 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1782 uint8_t spi2_outx_a_ois : 8; 1783 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1784 uint8_t spi2_outx_a_ois : 8; 1785 #endif /* DRV_BYTE_ORDER */ 1786 } lsm6dsv_spi2_outx_l_a_ois_t; 1787 1788 #define LSM6DSV_SPI2_OUTX_H_A_OIS 0x29U 1789 typedef struct 1790 { 1791 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1792 uint8_t spi2_outx_a_ois : 8; 1793 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1794 uint8_t spi2_outx_a_ois : 8; 1795 #endif /* DRV_BYTE_ORDER */ 1796 } lsm6dsv_spi2_outx_h_a_ois_t; 1797 1798 #define LSM6DSV_SPI2_OUTY_L_A_OIS 0x2AU 1799 typedef struct 1800 { 1801 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1802 uint8_t spi2_outy_a_ois : 8; 1803 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1804 uint8_t spi2_outy_a_ois : 8; 1805 #endif /* DRV_BYTE_ORDER */ 1806 } lsm6dsv_spi2_outy_l_a_ois_t; 1807 1808 #define LSM6DSV_SPI2_OUTY_H_A_OIS 0x2BU 1809 typedef struct 1810 { 1811 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1812 uint8_t spi2_outy_a_ois : 8; 1813 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1814 uint8_t spi2_outy_a_ois : 8; 1815 #endif /* DRV_BYTE_ORDER */ 1816 } lsm6dsv_spi2_outy_h_a_ois_t; 1817 1818 #define LSM6DSV_SPI2_OUTZ_L_A_OIS 0x2CU 1819 typedef struct 1820 { 1821 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1822 uint8_t spi2_outz_a_ois : 8; 1823 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1824 uint8_t spi2_outz_a_ois : 8; 1825 #endif /* DRV_BYTE_ORDER */ 1826 } lsm6dsv_spi2_outz_l_a_ois_t; 1827 1828 #define LSM6DSV_SPI2_OUTZ_H_A_OIS 0x2DU 1829 typedef struct 1830 { 1831 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1832 uint8_t spi2_outz_a_ois : 8; 1833 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1834 uint8_t spi2_outz_a_ois : 8; 1835 #endif /* DRV_BYTE_ORDER */ 1836 } lsm6dsv_spi2_outz_h_a_ois_t; 1837 1838 #define LSM6DSV_SPI2_HANDSHAKE_CTRL 0x6EU 1839 typedef struct 1840 { 1841 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1842 uint8_t spi2_shared_ack : 1; 1843 uint8_t spi2_shared_req : 1; 1844 uint8_t not_used0 : 6; 1845 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1846 uint8_t not_used0 : 6; 1847 uint8_t spi2_shared_req : 1; 1848 uint8_t spi2_shared_ack : 1; 1849 #endif /* DRV_BYTE_ORDER */ 1850 } lsm6dsv_spi2_handshake_ctrl_t; 1851 1852 #define LSM6DSV_SPI2_INT_OIS 0x6FU 1853 typedef struct 1854 { 1855 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1856 uint8_t st_xl_ois : 2; 1857 uint8_t st_g_ois : 2; 1858 uint8_t st_ois_clampdis : 1; 1859 uint8_t not_used0 : 1; 1860 uint8_t drdy_mask_ois : 1; 1861 uint8_t int2_drdy_ois : 1; 1862 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1863 uint8_t int2_drdy_ois : 1; 1864 uint8_t drdy_mask_ois : 1; 1865 uint8_t not_used0 : 1; 1866 uint8_t st_ois_clampdis : 1; 1867 uint8_t st_g_ois : 2; 1868 uint8_t st_xl_ois : 2; 1869 #endif /* DRV_BYTE_ORDER */ 1870 } lsm6dsv_spi2_int_ois_t; 1871 1872 #define LSM6DSV_SPI2_CTRL1_OIS 0x70U 1873 typedef struct 1874 { 1875 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1876 uint8_t spi2_read_en : 1; 1877 uint8_t ois_g_en : 1; 1878 uint8_t ois_xl_en : 1; 1879 uint8_t not_used0 : 2; 1880 uint8_t sim_ois : 1; 1881 uint8_t not_used1 : 2; 1882 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1883 uint8_t not_used1 : 2; 1884 uint8_t sim_ois : 1; 1885 uint8_t not_used0 : 2; 1886 uint8_t ois_xl_en : 1; 1887 uint8_t ois_g_en : 1; 1888 uint8_t spi2_read_en : 1; 1889 #endif /* DRV_BYTE_ORDER */ 1890 } lsm6dsv_spi2_ctrl1_ois_t; 1891 1892 #define LSM6DSV_SPI2_CTRL2_OIS 0x71U 1893 typedef struct 1894 { 1895 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1896 uint8_t fs_g_ois : 3; 1897 uint8_t lpf1_g_ois_bw : 2; 1898 uint8_t not_used0 : 3; 1899 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1900 uint8_t not_used0 : 3; 1901 uint8_t lpf1_g_ois_bw : 2; 1902 uint8_t fs_g_ois : 3; 1903 #endif /* DRV_BYTE_ORDER */ 1904 } lsm6dsv_spi2_ctrl2_ois_t; 1905 1906 #define LSM6DSV_SPI2_CTRL3_OIS 0x72U 1907 typedef struct 1908 { 1909 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1910 uint8_t fs_xl_ois : 2; 1911 uint8_t not_used0 : 1; 1912 uint8_t lpf_xl_ois_bw : 3; 1913 uint8_t not_used1 : 2; 1914 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1915 uint8_t not_used1 : 2; 1916 uint8_t lpf_xl_ois_bw : 3; 1917 uint8_t not_used0 : 1; 1918 uint8_t fs_xl_ois : 2; 1919 #endif /* DRV_BYTE_ORDER */ 1920 } lsm6dsv_spi2_ctrl3_ois_t; 1921 1922 /** 1923 * @} 1924 * 1925 */ 1926 1927 /** @defgroup bitfields page embedded 1928 * @{ 1929 * 1930 */ 1931 1932 #define LSM6DSV_PAGE_SEL 0x2U 1933 typedef struct 1934 { 1935 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1936 uint8_t not_used0 : 4; 1937 uint8_t page_sel : 4; 1938 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1939 uint8_t page_sel : 4; 1940 uint8_t not_used0 : 4; 1941 #endif /* DRV_BYTE_ORDER */ 1942 } lsm6dsv_page_sel_t; 1943 1944 #define LSM6DSV_EMB_FUNC_EN_A 0x4U 1945 typedef struct 1946 { 1947 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1948 uint8_t not_used0 : 1; 1949 uint8_t sflp_game_en : 1; 1950 uint8_t not_used2 : 1; 1951 uint8_t pedo_en : 1; 1952 uint8_t tilt_en : 1; 1953 uint8_t sign_motion_en : 1; 1954 uint8_t not_used1 : 2; 1955 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1956 uint8_t not_used1 : 2; 1957 uint8_t sign_motion_en : 1; 1958 uint8_t tilt_en : 1; 1959 uint8_t pedo_en : 1; 1960 uint8_t not_used2 : 1; 1961 uint8_t sflp_game_en : 1; 1962 uint8_t not_used0 : 1; 1963 #endif /* DRV_BYTE_ORDER */ 1964 } lsm6dsv_emb_func_en_a_t; 1965 1966 #define LSM6DSV_EMB_FUNC_EN_B 0x5U 1967 typedef struct 1968 { 1969 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1970 uint8_t fsm_en : 1; 1971 uint8_t not_used0 : 2; 1972 uint8_t fifo_compr_en : 1; 1973 uint8_t not_used1 : 4; 1974 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1975 uint8_t not_used1 : 4; 1976 uint8_t fifo_compr_en : 1; 1977 uint8_t not_used0 : 2; 1978 uint8_t fsm_en : 1; 1979 #endif /* DRV_BYTE_ORDER */ 1980 } lsm6dsv_emb_func_en_b_t; 1981 1982 #define LSM6DSV_EMB_FUNC_EXEC_STATUS 0x7U 1983 typedef struct 1984 { 1985 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1986 uint8_t emb_func_endop : 1; 1987 uint8_t emb_func_exec_ovr : 1; 1988 uint8_t not_used0 : 6; 1989 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1990 uint8_t not_used0 : 6; 1991 uint8_t emb_func_exec_ovr : 1; 1992 uint8_t emb_func_endop : 1; 1993 #endif /* DRV_BYTE_ORDER */ 1994 } lsm6dsv_emb_func_exec_status_t; 1995 1996 #define LSM6DSV_PAGE_ADDRESS 0x8U 1997 typedef struct 1998 { 1999 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2000 uint8_t page_addr : 8; 2001 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2002 uint8_t page_addr : 8; 2003 #endif /* DRV_BYTE_ORDER */ 2004 } lsm6dsv_page_address_t; 2005 2006 #define LSM6DSV_PAGE_VALUE 0x9U 2007 typedef struct 2008 { 2009 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2010 uint8_t page_value : 8; 2011 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2012 uint8_t page_value : 8; 2013 #endif /* DRV_BYTE_ORDER */ 2014 } lsm6dsv_page_value_t; 2015 2016 #define LSM6DSV_EMB_FUNC_INT1 0x0AU 2017 typedef struct 2018 { 2019 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2020 uint8_t not_used0 : 3; 2021 uint8_t int1_step_detector : 1; 2022 uint8_t int1_tilt : 1; 2023 uint8_t int1_sig_mot : 1; 2024 uint8_t not_used1 : 1; 2025 uint8_t int1_fsm_lc : 1; 2026 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2027 uint8_t int1_fsm_lc : 1; 2028 uint8_t not_used1 : 1; 2029 uint8_t int1_sig_mot : 1; 2030 uint8_t int1_tilt : 1; 2031 uint8_t int1_step_detector : 1; 2032 uint8_t not_used0 : 3; 2033 #endif /* DRV_BYTE_ORDER */ 2034 } lsm6dsv_emb_func_int1_t; 2035 2036 #define LSM6DSV_FSM_INT1 0x0BU 2037 typedef struct 2038 { 2039 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2040 uint8_t int1_fsm1 : 1; 2041 uint8_t int1_fsm2 : 1; 2042 uint8_t int1_fsm3 : 1; 2043 uint8_t int1_fsm4 : 1; 2044 uint8_t int1_fsm5 : 1; 2045 uint8_t int1_fsm6 : 1; 2046 uint8_t int1_fsm7 : 1; 2047 uint8_t int1_fsm8 : 1; 2048 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2049 uint8_t int1_fsm8 : 1; 2050 uint8_t int1_fsm7 : 1; 2051 uint8_t int1_fsm6 : 1; 2052 uint8_t int1_fsm5 : 1; 2053 uint8_t int1_fsm4 : 1; 2054 uint8_t int1_fsm3 : 1; 2055 uint8_t int1_fsm2 : 1; 2056 uint8_t int1_fsm1 : 1; 2057 #endif /* DRV_BYTE_ORDER */ 2058 } lsm6dsv_fsm_int1_t; 2059 2060 #define LSM6DSV_EMB_FUNC_INT2 0x0EU 2061 typedef struct 2062 { 2063 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2064 uint8_t not_used0 : 3; 2065 uint8_t int2_step_detector : 1; 2066 uint8_t int2_tilt : 1; 2067 uint8_t int2_sig_mot : 1; 2068 uint8_t not_used1 : 1; 2069 uint8_t int2_fsm_lc : 1; 2070 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2071 uint8_t int2_fsm_lc : 1; 2072 uint8_t not_used1 : 1; 2073 uint8_t int2_sig_mot : 1; 2074 uint8_t int2_tilt : 1; 2075 uint8_t int2_step_detector : 1; 2076 uint8_t not_used0 : 3; 2077 #endif /* DRV_BYTE_ORDER */ 2078 } lsm6dsv_emb_func_int2_t; 2079 2080 #define LSM6DSV_FSM_INT2 0x0FU 2081 typedef struct 2082 { 2083 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2084 uint8_t int2_fsm1 : 1; 2085 uint8_t int2_fsm2 : 1; 2086 uint8_t int2_fsm3 : 1; 2087 uint8_t int2_fsm4 : 1; 2088 uint8_t int2_fsm5 : 1; 2089 uint8_t int2_fsm6 : 1; 2090 uint8_t int2_fsm7 : 1; 2091 uint8_t int2_fsm8 : 1; 2092 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2093 uint8_t int2_fsm8 : 1; 2094 uint8_t int2_fsm7 : 1; 2095 uint8_t int2_fsm6 : 1; 2096 uint8_t int2_fsm5 : 1; 2097 uint8_t int2_fsm4 : 1; 2098 uint8_t int2_fsm3 : 1; 2099 uint8_t int2_fsm2 : 1; 2100 uint8_t int2_fsm1 : 1; 2101 #endif /* DRV_BYTE_ORDER */ 2102 } lsm6dsv_fsm_int2_t; 2103 2104 #define LSM6DSV_EMB_FUNC_STATUS 0x12U 2105 typedef struct 2106 { 2107 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2108 uint8_t not_used0 : 3; 2109 uint8_t is_step_det : 1; 2110 uint8_t is_tilt : 1; 2111 uint8_t is_sigmot : 1; 2112 uint8_t not_used1 : 1; 2113 uint8_t is_fsm_lc : 1; 2114 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2115 uint8_t is_fsm_lc : 1; 2116 uint8_t not_used1 : 1; 2117 uint8_t is_sigmot : 1; 2118 uint8_t is_tilt : 1; 2119 uint8_t is_step_det : 1; 2120 uint8_t not_used0 : 3; 2121 #endif /* DRV_BYTE_ORDER */ 2122 } lsm6dsv_emb_func_status_t; 2123 2124 #define LSM6DSV_FSM_STATUS 0x13U 2125 typedef struct 2126 { 2127 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2128 uint8_t is_fsm1 : 1; 2129 uint8_t is_fsm2 : 1; 2130 uint8_t is_fsm3 : 1; 2131 uint8_t is_fsm4 : 1; 2132 uint8_t is_fsm5 : 1; 2133 uint8_t is_fsm6 : 1; 2134 uint8_t is_fsm7 : 1; 2135 uint8_t is_fsm8 : 1; 2136 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2137 uint8_t is_fsm8 : 1; 2138 uint8_t is_fsm7 : 1; 2139 uint8_t is_fsm6 : 1; 2140 uint8_t is_fsm5 : 1; 2141 uint8_t is_fsm4 : 1; 2142 uint8_t is_fsm3 : 1; 2143 uint8_t is_fsm2 : 1; 2144 uint8_t is_fsm1 : 1; 2145 #endif /* DRV_BYTE_ORDER */ 2146 } lsm6dsv_fsm_status_t; 2147 2148 #define LSM6DSV_PAGE_RW 0x17U 2149 typedef struct 2150 { 2151 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2152 uint8_t not_used0 : 5; 2153 uint8_t page_read : 1; 2154 uint8_t page_write : 1; 2155 uint8_t emb_func_lir : 1; 2156 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2157 uint8_t emb_func_lir : 1; 2158 uint8_t page_write : 1; 2159 uint8_t page_read : 1; 2160 uint8_t not_used0 : 5; 2161 #endif /* DRV_BYTE_ORDER */ 2162 } lsm6dsv_page_rw_t; 2163 2164 #define LSM6DSV_EMB_FUNC_FIFO_EN_A 0x44U 2165 typedef struct 2166 { 2167 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2168 uint8_t not_used0 : 1; 2169 uint8_t sflp_game_fifo_en : 1; 2170 uint8_t not_used1 : 2; 2171 uint8_t sflp_gravity_fifo_en : 1; 2172 uint8_t sflp_gbias_fifo_en : 1; 2173 uint8_t step_counter_fifo_en : 1; 2174 uint8_t not_used2 : 1; 2175 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2176 uint8_t not_used2 : 1; 2177 uint8_t step_counter_fifo_en : 1; 2178 uint8_t sflp_gbias_fifo_en : 1; 2179 uint8_t sflp_gravity_fifo_en : 1; 2180 uint8_t not_used1 : 2; 2181 uint8_t sflp_game_fifo_en : 1; 2182 uint8_t not_used0 : 1; 2183 #endif /* DRV_BYTE_ORDER */ 2184 } lsm6dsv_emb_func_fifo_en_a_t; 2185 2186 #define LSM6DSV_FSM_ENABLE 0x46U 2187 typedef struct 2188 { 2189 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2190 uint8_t fsm1_en : 1; 2191 uint8_t fsm2_en : 1; 2192 uint8_t fsm3_en : 1; 2193 uint8_t fsm4_en : 1; 2194 uint8_t fsm5_en : 1; 2195 uint8_t fsm6_en : 1; 2196 uint8_t fsm7_en : 1; 2197 uint8_t fsm8_en : 1; 2198 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2199 uint8_t fsm8_en : 1; 2200 uint8_t fsm7_en : 1; 2201 uint8_t fsm6_en : 1; 2202 uint8_t fsm5_en : 1; 2203 uint8_t fsm4_en : 1; 2204 uint8_t fsm3_en : 1; 2205 uint8_t fsm2_en : 1; 2206 uint8_t fsm1_en : 1; 2207 #endif /* DRV_BYTE_ORDER */ 2208 } lsm6dsv_fsm_enable_t; 2209 2210 #define LSM6DSV_FSM_LONG_COUNTER_L 0x48U 2211 typedef struct 2212 { 2213 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2214 uint8_t fsm_lc : 8; 2215 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2216 uint8_t fsm_lc : 8; 2217 #endif /* DRV_BYTE_ORDER */ 2218 } lsm6dsv_fsm_long_counter_l_t; 2219 2220 #define LSM6DSV_FSM_LONG_COUNTER_H 0x49U 2221 typedef struct 2222 { 2223 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2224 uint8_t fsm_lc : 8; 2225 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2226 uint8_t fsm_lc : 8; 2227 #endif /* DRV_BYTE_ORDER */ 2228 } lsm6dsv_fsm_long_counter_h_t; 2229 2230 #define LSM6DSV_INT_ACK_MASK 0x4BU 2231 typedef struct 2232 { 2233 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2234 uint8_t iack_mask : 8; 2235 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2236 uint8_t iack_mask : 8; 2237 #endif /* DRV_BYTE_ORDER */ 2238 } lsm6dsv_int_ack_mask_t; 2239 2240 #define LSM6DSV_FSM_OUTS1 0x4CU 2241 typedef struct 2242 { 2243 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2244 uint8_t fsm1_n_v : 1; 2245 uint8_t fsm1_p_v : 1; 2246 uint8_t fsm1_n_z : 1; 2247 uint8_t fsm1_p_z : 1; 2248 uint8_t fsm1_n_y : 1; 2249 uint8_t fsm1_p_y : 1; 2250 uint8_t fsm1_n_x : 1; 2251 uint8_t fsm1_p_x : 1; 2252 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2253 uint8_t fsm1_p_x : 1; 2254 uint8_t fsm1_n_x : 1; 2255 uint8_t fsm1_p_y : 1; 2256 uint8_t fsm1_n_y : 1; 2257 uint8_t fsm1_p_z : 1; 2258 uint8_t fsm1_n_z : 1; 2259 uint8_t fsm1_p_v : 1; 2260 uint8_t fsm1_n_v : 1; 2261 #endif /* DRV_BYTE_ORDER */ 2262 } lsm6dsv_fsm_outs1_t; 2263 2264 #define LSM6DSV_FSM_OUTS2 0x4DU 2265 typedef struct 2266 { 2267 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2268 uint8_t fsm2_n_v : 1; 2269 uint8_t fsm2_p_v : 1; 2270 uint8_t fsm2_n_z : 1; 2271 uint8_t fsm2_p_z : 1; 2272 uint8_t fsm2_n_y : 1; 2273 uint8_t fsm2_p_y : 1; 2274 uint8_t fsm2_n_x : 1; 2275 uint8_t fsm2_p_x : 1; 2276 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2277 uint8_t fsm2_p_x : 1; 2278 uint8_t fsm2_n_x : 1; 2279 uint8_t fsm2_p_y : 1; 2280 uint8_t fsm2_n_y : 1; 2281 uint8_t fsm2_p_z : 1; 2282 uint8_t fsm2_n_z : 1; 2283 uint8_t fsm2_p_v : 1; 2284 uint8_t fsm2_n_v : 1; 2285 #endif /* DRV_BYTE_ORDER */ 2286 } lsm6dsv_fsm_outs2_t; 2287 2288 #define LSM6DSV_FSM_OUTS3 0x4EU 2289 typedef struct 2290 { 2291 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2292 uint8_t fsm3_n_v : 1; 2293 uint8_t fsm3_p_v : 1; 2294 uint8_t fsm3_n_z : 1; 2295 uint8_t fsm3_p_z : 1; 2296 uint8_t fsm3_n_y : 1; 2297 uint8_t fsm3_p_y : 1; 2298 uint8_t fsm3_n_x : 1; 2299 uint8_t fsm3_p_x : 1; 2300 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2301 uint8_t fsm3_p_x : 1; 2302 uint8_t fsm3_n_x : 1; 2303 uint8_t fsm3_p_y : 1; 2304 uint8_t fsm3_n_y : 1; 2305 uint8_t fsm3_p_z : 1; 2306 uint8_t fsm3_n_z : 1; 2307 uint8_t fsm3_p_v : 1; 2308 uint8_t fsm3_n_v : 1; 2309 #endif /* DRV_BYTE_ORDER */ 2310 } lsm6dsv_fsm_outs3_t; 2311 2312 #define LSM6DSV_FSM_OUTS4 0x4FU 2313 typedef struct 2314 { 2315 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2316 uint8_t fsm4_n_v : 1; 2317 uint8_t fsm4_p_v : 1; 2318 uint8_t fsm4_n_z : 1; 2319 uint8_t fsm4_p_z : 1; 2320 uint8_t fsm4_n_y : 1; 2321 uint8_t fsm4_p_y : 1; 2322 uint8_t fsm4_n_x : 1; 2323 uint8_t fsm4_p_x : 1; 2324 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2325 uint8_t fsm4_p_x : 1; 2326 uint8_t fsm4_n_x : 1; 2327 uint8_t fsm4_p_y : 1; 2328 uint8_t fsm4_n_y : 1; 2329 uint8_t fsm4_p_z : 1; 2330 uint8_t fsm4_n_z : 1; 2331 uint8_t fsm4_p_v : 1; 2332 uint8_t fsm4_n_v : 1; 2333 #endif /* DRV_BYTE_ORDER */ 2334 } lsm6dsv_fsm_outs4_t; 2335 2336 #define LSM6DSV_FSM_OUTS5 0x50U 2337 typedef struct 2338 { 2339 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2340 uint8_t fsm5_n_v : 1; 2341 uint8_t fsm5_p_v : 1; 2342 uint8_t fsm5_n_z : 1; 2343 uint8_t fsm5_p_z : 1; 2344 uint8_t fsm5_n_y : 1; 2345 uint8_t fsm5_p_y : 1; 2346 uint8_t fsm5_n_x : 1; 2347 uint8_t fsm5_p_x : 1; 2348 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2349 uint8_t fsm5_p_x : 1; 2350 uint8_t fsm5_n_x : 1; 2351 uint8_t fsm5_p_y : 1; 2352 uint8_t fsm5_n_y : 1; 2353 uint8_t fsm5_p_z : 1; 2354 uint8_t fsm5_n_z : 1; 2355 uint8_t fsm5_p_v : 1; 2356 uint8_t fsm5_n_v : 1; 2357 #endif /* DRV_BYTE_ORDER */ 2358 } lsm6dsv_fsm_outs5_t; 2359 2360 #define LSM6DSV_FSM_OUTS6 0x51U 2361 typedef struct 2362 { 2363 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2364 uint8_t fsm6_n_v : 1; 2365 uint8_t fsm6_p_v : 1; 2366 uint8_t fsm6_n_z : 1; 2367 uint8_t fsm6_p_z : 1; 2368 uint8_t fsm6_n_y : 1; 2369 uint8_t fsm6_p_y : 1; 2370 uint8_t fsm6_n_x : 1; 2371 uint8_t fsm6_p_x : 1; 2372 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2373 uint8_t fsm6_p_x : 1; 2374 uint8_t fsm6_n_x : 1; 2375 uint8_t fsm6_p_y : 1; 2376 uint8_t fsm6_n_y : 1; 2377 uint8_t fsm6_p_z : 1; 2378 uint8_t fsm6_n_z : 1; 2379 uint8_t fsm6_p_v : 1; 2380 uint8_t fsm6_n_v : 1; 2381 #endif /* DRV_BYTE_ORDER */ 2382 } lsm6dsv_fsm_outs6_t; 2383 2384 #define LSM6DSV_FSM_OUTS7 0x52U 2385 typedef struct 2386 { 2387 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2388 uint8_t fsm7_n_v : 1; 2389 uint8_t fsm7_p_v : 1; 2390 uint8_t fsm7_n_z : 1; 2391 uint8_t fsm7_p_z : 1; 2392 uint8_t fsm7_n_y : 1; 2393 uint8_t fsm7_p_y : 1; 2394 uint8_t fsm7_n_x : 1; 2395 uint8_t fsm7_p_x : 1; 2396 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2397 uint8_t fsm7_p_x : 1; 2398 uint8_t fsm7_n_x : 1; 2399 uint8_t fsm7_p_y : 1; 2400 uint8_t fsm7_n_y : 1; 2401 uint8_t fsm7_p_z : 1; 2402 uint8_t fsm7_n_z : 1; 2403 uint8_t fsm7_p_v : 1; 2404 uint8_t fsm7_n_v : 1; 2405 #endif /* DRV_BYTE_ORDER */ 2406 } lsm6dsv_fsm_outs7_t; 2407 2408 #define LSM6DSV_FSM_OUTS8 0x53U 2409 typedef struct 2410 { 2411 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2412 uint8_t fsm8_n_v : 1; 2413 uint8_t fsm8_p_v : 1; 2414 uint8_t fsm8_n_z : 1; 2415 uint8_t fsm8_p_z : 1; 2416 uint8_t fsm8_n_y : 1; 2417 uint8_t fsm8_p_y : 1; 2418 uint8_t fsm8_n_x : 1; 2419 uint8_t fsm8_p_x : 1; 2420 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2421 uint8_t fsm8_p_x : 1; 2422 uint8_t fsm8_n_x : 1; 2423 uint8_t fsm8_p_y : 1; 2424 uint8_t fsm8_n_y : 1; 2425 uint8_t fsm8_p_z : 1; 2426 uint8_t fsm8_n_z : 1; 2427 uint8_t fsm8_p_v : 1; 2428 uint8_t fsm8_n_v : 1; 2429 #endif /* DRV_BYTE_ORDER */ 2430 } lsm6dsv_fsm_outs8_t; 2431 2432 #define LSM6DSV_SFLP_ODR 0x5EU 2433 typedef struct 2434 { 2435 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2436 uint8_t not_used0 : 3; 2437 uint8_t sflp_game_odr : 3; 2438 uint8_t not_used1 : 2; 2439 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2440 uint8_t not_used1 : 2; 2441 uint8_t sflp_game_odr : 3; 2442 uint8_t not_used0 : 3; 2443 #endif /* DRV_BYTE_ORDER */ 2444 } lsm6dsv_sflp_odr_t; 2445 2446 #define LSM6DSV_FSM_ODR 0x5FU 2447 typedef struct 2448 { 2449 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2450 uint8_t not_used0 : 3; 2451 uint8_t fsm_odr : 3; 2452 uint8_t not_used1 : 2; 2453 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2454 uint8_t not_used1 : 2; 2455 uint8_t fsm_odr : 3; 2456 uint8_t not_used0 : 3; 2457 #endif /* DRV_BYTE_ORDER */ 2458 } lsm6dsv_fsm_odr_t; 2459 2460 #define LSM6DSV_STEP_COUNTER_L 0x62U 2461 typedef struct 2462 { 2463 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2464 uint8_t step : 8; 2465 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2466 uint8_t step : 8; 2467 #endif /* DRV_BYTE_ORDER */ 2468 } lsm6dsv_step_counter_l_t; 2469 2470 #define LSM6DSV_STEP_COUNTER_H 0x63U 2471 typedef struct 2472 { 2473 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2474 uint8_t step : 8; 2475 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2476 uint8_t step : 8; 2477 #endif /* DRV_BYTE_ORDER */ 2478 } lsm6dsv_step_counter_h_t; 2479 2480 #define LSM6DSV_EMB_FUNC_SRC 0x64U 2481 typedef struct 2482 { 2483 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2484 uint8_t not_used0 : 2; 2485 uint8_t stepcounter_bit_set : 1; 2486 uint8_t step_overflow : 1; 2487 uint8_t step_count_delta_ia : 1; 2488 uint8_t step_detected : 1; 2489 uint8_t not_used1 : 1; 2490 uint8_t pedo_rst_step : 1; 2491 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2492 uint8_t pedo_rst_step : 1; 2493 uint8_t not_used1 : 1; 2494 uint8_t step_detected : 1; 2495 uint8_t step_count_delta_ia : 1; 2496 uint8_t step_overflow : 1; 2497 uint8_t stepcounter_bit_set : 1; 2498 uint8_t not_used0 : 2; 2499 #endif /* DRV_BYTE_ORDER */ 2500 } lsm6dsv_emb_func_src_t; 2501 2502 #define LSM6DSV_EMB_FUNC_INIT_A 0x66U 2503 typedef struct 2504 { 2505 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2506 uint8_t not_used0 : 1; 2507 uint8_t sflp_game_init : 1; 2508 uint8_t not_used2 : 1; 2509 uint8_t step_det_init : 1; 2510 uint8_t tilt_init : 1; 2511 uint8_t sig_mot_init : 1; 2512 uint8_t not_used1 : 2; 2513 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2514 uint8_t not_used1 : 2; 2515 uint8_t sig_mot_init : 1; 2516 uint8_t tilt_init : 1; 2517 uint8_t step_det_init : 1; 2518 uint8_t not_used2 : 1; 2519 uint8_t sflp_game_init : 1; 2520 uint8_t not_used0 : 1; 2521 #endif /* DRV_BYTE_ORDER */ 2522 } lsm6dsv_emb_func_init_a_t; 2523 2524 #define LSM6DSV_EMB_FUNC_INIT_B 0x67U 2525 typedef struct 2526 { 2527 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2528 uint8_t fsm_init : 1; 2529 uint8_t not_used0 : 2; 2530 uint8_t fifo_compr_init : 1; 2531 uint8_t not_used1 : 4; 2532 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2533 uint8_t not_used1 : 4; 2534 uint8_t fifo_compr_init : 1; 2535 uint8_t not_used0 : 2; 2536 uint8_t fsm_init : 1; 2537 #endif /* DRV_BYTE_ORDER */ 2538 } lsm6dsv_emb_func_init_b_t; 2539 2540 /** 2541 * @} 2542 * 2543 */ 2544 2545 /** @defgroup bitfields page pg0_emb_adv 2546 * @{ 2547 * 2548 */ 2549 #define LSM6DSV_EMB_ADV_PG_0 0x000U 2550 2551 #define LSM6DSV_SFLP_GAME_GBIASX_L 0x6EU 2552 typedef struct 2553 { 2554 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2555 uint8_t gbiasx : 8; 2556 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2557 uint8_t gbiasx : 8; 2558 #endif /* DRV_BYTE_ORDER */ 2559 } lsm6dsv_sflp_game_gbiasx_l_t; 2560 2561 #define LSM6DSV_SFLP_GAME_GBIASX_H 0x6FU 2562 typedef struct 2563 { 2564 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2565 uint8_t gbiasx : 8; 2566 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2567 uint8_t gbiasx : 8; 2568 #endif /* DRV_BYTE_ORDER */ 2569 } lsm6dsv_sflp_game_gbiasx_h_t; 2570 2571 #define LSM6DSV_SFLP_GAME_GBIASY_L 0x70U 2572 typedef struct 2573 { 2574 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2575 uint8_t gbiasy : 8; 2576 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2577 uint8_t gbiasy : 8; 2578 #endif /* DRV_BYTE_ORDER */ 2579 } lsm6dsv_sflp_game_gbiasy_l_t; 2580 2581 #define LSM6DSV_SFLP_GAME_GBIASY_H 0x71U 2582 typedef struct 2583 { 2584 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2585 uint8_t gbiasy : 8; 2586 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2587 uint8_t gbiasy : 8; 2588 #endif /* DRV_BYTE_ORDER */ 2589 } lsm6dsv_sflp_game_gbiasy_h_t; 2590 2591 #define LSM6DSV_SFLP_GAME_GBIASZ_L 0x72U 2592 typedef struct 2593 { 2594 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2595 uint8_t gbiasz : 8; 2596 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2597 uint8_t gbiasz : 8; 2598 #endif /* DRV_BYTE_ORDER */ 2599 } lsm6dsv_sflp_game_gbiasz_l_t; 2600 2601 #define LSM6DSV_SFLP_GAME_GBIASZ_H 0x73U 2602 typedef struct 2603 { 2604 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2605 uint8_t gbiasz : 8; 2606 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2607 uint8_t gbiasz : 8; 2608 #endif /* DRV_BYTE_ORDER */ 2609 } lsm6dsv_sflp_game_gbiasz_h_t; 2610 2611 #define LSM6DSV_FSM_EXT_SENSITIVITY_L 0xBAU 2612 typedef struct 2613 { 2614 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2615 uint8_t fsm_ext_s : 8; 2616 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2617 uint8_t fsm_ext_s : 8; 2618 #endif /* DRV_BYTE_ORDER */ 2619 } lsm6dsv_fsm_ext_sensitivity_l_t; 2620 2621 #define LSM6DSV_FSM_EXT_SENSITIVITY_H 0xBBU 2622 typedef struct 2623 { 2624 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2625 uint8_t fsm_ext_s : 8; 2626 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2627 uint8_t fsm_ext_s : 8; 2628 #endif /* DRV_BYTE_ORDER */ 2629 } lsm6dsv_fsm_ext_sensitivity_h_t; 2630 2631 #define LSM6DSV_FSM_EXT_OFFX_L 0xC0U 2632 typedef struct 2633 { 2634 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2635 uint8_t fsm_ext_offx : 8; 2636 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2637 uint8_t fsm_ext_offx : 8; 2638 #endif /* DRV_BYTE_ORDER */ 2639 } lsm6dsv_fsm_ext_offx_l_t; 2640 2641 #define LSM6DSV_FSM_EXT_OFFX_H 0xC1U 2642 typedef struct 2643 { 2644 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2645 uint8_t fsm_ext_offx : 8; 2646 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2647 uint8_t fsm_ext_offx : 8; 2648 #endif /* DRV_BYTE_ORDER */ 2649 } lsm6dsv_fsm_ext_offx_h_t; 2650 2651 #define LSM6DSV_FSM_EXT_OFFY_L 0xC2U 2652 typedef struct 2653 { 2654 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2655 uint8_t fsm_ext_offy : 8; 2656 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2657 uint8_t fsm_ext_offy : 8; 2658 #endif /* DRV_BYTE_ORDER */ 2659 } lsm6dsv_fsm_ext_offy_l_t; 2660 2661 #define LSM6DSV_FSM_EXT_OFFY_H 0xC3U 2662 typedef struct 2663 { 2664 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2665 uint8_t fsm_ext_offy : 8; 2666 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2667 uint8_t fsm_ext_offy : 8; 2668 #endif /* DRV_BYTE_ORDER */ 2669 } lsm6dsv_fsm_ext_offy_h_t; 2670 2671 #define LSM6DSV_FSM_EXT_OFFZ_L 0xC4U 2672 typedef struct 2673 { 2674 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2675 uint8_t fsm_ext_offz : 8; 2676 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2677 uint8_t fsm_ext_offz : 8; 2678 #endif /* DRV_BYTE_ORDER */ 2679 } lsm6dsv_fsm_ext_offz_l_t; 2680 2681 #define LSM6DSV_FSM_EXT_OFFZ_H 0xC5U 2682 typedef struct 2683 { 2684 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2685 uint8_t fsm_ext_offz : 8; 2686 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2687 uint8_t fsm_ext_offz : 8; 2688 #endif /* DRV_BYTE_ORDER */ 2689 } lsm6dsv_fsm_ext_offz_h_t; 2690 2691 #define LSM6DSV_FSM_EXT_MATRIX_XX_L 0xC6U 2692 typedef struct 2693 { 2694 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2695 uint8_t fsm_ext_mat_xx : 8; 2696 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2697 uint8_t fsm_ext_mat_xx : 8; 2698 #endif /* DRV_BYTE_ORDER */ 2699 } lsm6dsv_fsm_ext_matrix_xx_l_t; 2700 2701 #define LSM6DSV_FSM_EXT_MATRIX_XX_H 0xC7U 2702 typedef struct 2703 { 2704 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2705 uint8_t fsm_ext_mat_xx : 8; 2706 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2707 uint8_t fsm_ext_mat_xx : 8; 2708 #endif /* DRV_BYTE_ORDER */ 2709 } lsm6dsv_fsm_ext_matrix_xx_h_t; 2710 2711 #define LSM6DSV_FSM_EXT_MATRIX_XY_L 0xC8U 2712 typedef struct 2713 { 2714 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2715 uint8_t fsm_ext_mat_xy : 8; 2716 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2717 uint8_t fsm_ext_mat_xy : 8; 2718 #endif /* DRV_BYTE_ORDER */ 2719 } lsm6dsv_fsm_ext_matrix_xy_l_t; 2720 2721 #define LSM6DSV_FSM_EXT_MATRIX_XY_H 0xC9U 2722 typedef struct 2723 { 2724 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2725 uint8_t fsm_ext_mat_xy : 8; 2726 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2727 uint8_t fsm_ext_mat_xy : 8; 2728 #endif /* DRV_BYTE_ORDER */ 2729 } lsm6dsv_fsm_ext_matrix_xy_h_t; 2730 2731 #define LSM6DSV_FSM_EXT_MATRIX_XZ_L 0xCAU 2732 typedef struct 2733 { 2734 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2735 uint8_t fsm_ext_mat_xz : 8; 2736 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2737 uint8_t fsm_ext_mat_xz : 8; 2738 #endif /* DRV_BYTE_ORDER */ 2739 } lsm6dsv_fsm_ext_matrix_xz_l_t; 2740 2741 #define LSM6DSV_FSM_EXT_MATRIX_XZ_H 0xCBU 2742 typedef struct 2743 { 2744 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2745 uint8_t fsm_ext_mat_xz : 8; 2746 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2747 uint8_t fsm_ext_mat_xz : 8; 2748 #endif /* DRV_BYTE_ORDER */ 2749 } lsm6dsv_fsm_ext_matrix_xz_h_t; 2750 2751 #define LSM6DSV_FSM_EXT_MATRIX_YY_L 0xCCU 2752 typedef struct 2753 { 2754 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2755 uint8_t fsm_ext_mat_yy : 8; 2756 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2757 uint8_t fsm_ext_mat_yy : 8; 2758 #endif /* DRV_BYTE_ORDER */ 2759 } lsm6dsv_fsm_ext_matrix_yy_l_t; 2760 2761 #define LSM6DSV_FSM_EXT_MATRIX_YY_H 0xCDU 2762 typedef struct 2763 { 2764 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2765 uint8_t fsm_ext_mat_yy : 8; 2766 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2767 uint8_t fsm_ext_mat_yy : 8; 2768 #endif /* DRV_BYTE_ORDER */ 2769 } lsm6dsv_fsm_ext_matrix_yy_h_t; 2770 2771 #define LSM6DSV_FSM_EXT_MATRIX_YZ_L 0xCEU 2772 typedef struct 2773 { 2774 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2775 uint8_t fsm_ext_mat_yz : 8; 2776 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2777 uint8_t fsm_ext_mat_yz : 8; 2778 #endif /* DRV_BYTE_ORDER */ 2779 } lsm6dsv_fsm_ext_matrix_yz_l_t; 2780 2781 #define LSM6DSV_FSM_EXT_MATRIX_YZ_H 0xCFU 2782 typedef struct 2783 { 2784 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2785 uint8_t fsm_ext_mat_yz : 8; 2786 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2787 uint8_t fsm_ext_mat_yz : 8; 2788 #endif /* DRV_BYTE_ORDER */ 2789 } lsm6dsv_fsm_ext_matrix_yz_h_t; 2790 2791 #define LSM6DSV_FSM_EXT_MATRIX_ZZ_L 0xD0U 2792 typedef struct 2793 { 2794 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2795 uint8_t fsm_ext_mat_zz : 8; 2796 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2797 uint8_t fsm_ext_mat_zz : 8; 2798 #endif /* DRV_BYTE_ORDER */ 2799 } lsm6dsv_fsm_ext_matrix_zz_l_t; 2800 2801 #define LSM6DSV_FSM_EXT_MATRIX_ZZ_H 0xD1U 2802 typedef struct 2803 { 2804 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2805 uint8_t fsm_ext_mat_zz : 8; 2806 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2807 uint8_t fsm_ext_mat_zz : 8; 2808 #endif /* DRV_BYTE_ORDER */ 2809 } lsm6dsv_fsm_ext_matrix_zz_h_t; 2810 2811 #define LSM6DSV_EXT_CFG_A 0xD4U 2812 typedef struct 2813 { 2814 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2815 uint8_t ext_z_axis : 3; 2816 uint8_t not_used0 : 1; 2817 uint8_t ext_y_axis : 3; 2818 uint8_t not_used1 : 1; 2819 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2820 uint8_t not_used1 : 1; 2821 uint8_t ext_y_axis : 3; 2822 uint8_t not_used0 : 1; 2823 uint8_t ext_z_axis : 3; 2824 #endif /* DRV_BYTE_ORDER */ 2825 } lsm6dsv_ext_cfg_a_t; 2826 2827 #define LSM6DSV_EXT_CFG_B 0xD5U 2828 typedef struct 2829 { 2830 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2831 uint8_t ext_x_axis : 3; 2832 uint8_t not_used0 : 5; 2833 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2834 uint8_t not_used0 : 5; 2835 uint8_t ext_x_axis : 3; 2836 #endif /* DRV_BYTE_ORDER */ 2837 } lsm6dsv_ext_cfg_b_t; 2838 2839 /** 2840 * @} 2841 * 2842 */ 2843 2844 /** @defgroup bitfields page pg1_emb_adv 2845 * @{ 2846 * 2847 */ 2848 #define LSM6DSV_EMB_ADV_PG_1 0x100U 2849 2850 #define LSM6DSV_FSM_LC_TIMEOUT_L 0x7AU 2851 typedef struct 2852 { 2853 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2854 uint8_t fsm_lc_timeout : 8; 2855 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2856 uint8_t fsm_lc_timeout : 8; 2857 #endif /* DRV_BYTE_ORDER */ 2858 } lsm6dsv_fsm_lc_timeout_l_t; 2859 2860 #define LSM6DSV_FSM_LC_TIMEOUT_H 0x7BU 2861 typedef struct 2862 { 2863 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2864 uint8_t fsm_lc_timeout : 8; 2865 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2866 uint8_t fsm_lc_timeout : 8; 2867 #endif /* DRV_BYTE_ORDER */ 2868 } lsm6dsv_fsm_lc_timeout_h_t; 2869 2870 #define LSM6DSV_FSM_PROGRAMS 0x7CU 2871 typedef struct 2872 { 2873 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2874 uint8_t fsm_n_prog : 8; 2875 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2876 uint8_t fsm_n_prog : 8; 2877 #endif /* DRV_BYTE_ORDER */ 2878 } lsm6dsv_fsm_programs_t; 2879 2880 #define LSM6DSV_FSM_START_ADD_L 0x7EU 2881 typedef struct 2882 { 2883 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2884 uint8_t fsm_start : 8; 2885 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2886 uint8_t fsm_start : 8; 2887 #endif /* DRV_BYTE_ORDER */ 2888 } lsm6dsv_fsm_start_add_l_t; 2889 2890 #define LSM6DSV_FSM_START_ADD_H 0x7FU 2891 typedef struct 2892 { 2893 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2894 uint8_t fsm_start : 8; 2895 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2896 uint8_t fsm_start : 8; 2897 #endif /* DRV_BYTE_ORDER */ 2898 } lsm6dsv_fsm_start_add_h_t; 2899 2900 #define LSM6DSV_PEDO_CMD_REG 0x83U 2901 typedef struct 2902 { 2903 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2904 uint8_t not_used0 : 3; 2905 uint8_t carry_count_en : 1; 2906 uint8_t not_used1 : 4; 2907 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2908 uint8_t not_used1 : 4; 2909 uint8_t carry_count_en : 1; 2910 uint8_t not_used0 : 3; 2911 #endif /* DRV_BYTE_ORDER */ 2912 } lsm6dsv_pedo_cmd_reg_t; 2913 2914 #define LSM6DSV_PEDO_DEB_STEPS_CONF 0x84U 2915 typedef struct 2916 { 2917 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2918 uint8_t deb_step : 8; 2919 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2920 uint8_t deb_step : 8; 2921 #endif /* DRV_BYTE_ORDER */ 2922 } lsm6dsv_pedo_deb_steps_conf_t; 2923 2924 #define LSM6DSV_PEDO_SC_DELTAT_L 0xD0U 2925 typedef struct 2926 { 2927 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2928 uint8_t pd_sc : 8; 2929 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2930 uint8_t pd_sc : 8; 2931 #endif /* DRV_BYTE_ORDER */ 2932 } lsm6dsv_pedo_sc_deltat_l_t; 2933 2934 #define LSM6DSV_PEDO_SC_DELTAT_H 0xD1U 2935 typedef struct 2936 { 2937 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2938 uint8_t pd_sc : 8; 2939 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2940 uint8_t pd_sc : 8; 2941 #endif /* DRV_BYTE_ORDER */ 2942 } lsm6dsv_pedo_sc_deltat_h_t; 2943 2944 /** @defgroup bitfields page pg2_emb_adv 2945 * @{ 2946 * 2947 */ 2948 #define LSM6DSV_EMB_ADV_PG_2 0x200U 2949 2950 #define LSM6DSV_EXT_FORMAT 0x00 2951 typedef struct 2952 { 2953 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2954 uint8_t not_used0 : 2; 2955 uint8_t ext_format_sel : 1; 2956 uint8_t not_used1 : 5; 2957 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2958 uint8_t not_used1 : 5; 2959 uint8_t ext_format_sel : 1; 2960 uint8_t not_used0 : 2; 2961 #endif /* DRV_BYTE_ORDER */ 2962 } lsm6dsv_ext_format_t; 2963 2964 #define LSM6DSV_EXT_3BYTE_SENSITIVITY_L 0x02U 2965 typedef struct 2966 { 2967 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2968 uint8_t ext_3byte_s : 8; 2969 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2970 uint8_t ext_3byte_s : 8; 2971 #endif /* DRV_BYTE_ORDER */ 2972 } lsm6dsv_ext_3byte_sensitivity_l_t; 2973 2974 #define LSM6DSV_EXT_3BYTE_SENSITIVITY_H 0x03U 2975 typedef struct 2976 { 2977 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2978 uint8_t ext_3byte_s : 8; 2979 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2980 uint8_t ext_3byte_s : 8; 2981 #endif /* DRV_BYTE_ORDER */ 2982 } lsm6dsv_ext_3byte_sensitivity_h_t; 2983 2984 #define LSM6DSV_EXT_3BYTE_OFFSET_XL 0x06U 2985 typedef struct 2986 { 2987 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2988 uint8_t ext_3byte_off : 8; 2989 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2990 uint8_t ext_3byte_off : 8; 2991 #endif /* DRV_BYTE_ORDER */ 2992 } lsm6dsv_ext_3byte_offset_xl_t; 2993 2994 #define LSM6DSV_EXT_3BYTE_OFFSET_L 0x07U 2995 typedef struct 2996 { 2997 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2998 uint8_t ext_3byte_off : 8; 2999 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3000 uint8_t ext_3byte_off : 8; 3001 #endif /* DRV_BYTE_ORDER */ 3002 } lsm6dsv_ext_3byte_offset_l_t; 3003 3004 #define LSM6DSV_EXT_3BYTE_OFFSET_H 0x08U 3005 typedef struct 3006 { 3007 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3008 uint8_t ext_3byte_off : 8; 3009 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3010 uint8_t ext_3byte_off : 8; 3011 #endif /* DRV_BYTE_ORDER */ 3012 } lsm6dsv_ext_3byte_offset_h_t; 3013 3014 /** 3015 * @} 3016 * 3017 */ 3018 3019 /** @defgroup bitfields page sensor_hub 3020 * @{ 3021 * 3022 */ 3023 3024 #define LSM6DSV_SENSOR_HUB_1 0x2U 3025 typedef struct 3026 { 3027 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3028 uint8_t sensorhub1 : 8; 3029 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3030 uint8_t sensorhub1 : 8; 3031 #endif /* DRV_BYTE_ORDER */ 3032 } lsm6dsv_sensor_hub_1_t; 3033 3034 #define LSM6DSV_SENSOR_HUB_2 0x3U 3035 typedef struct 3036 { 3037 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3038 uint8_t sensorhub2 : 8; 3039 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3040 uint8_t sensorhub2 : 8; 3041 #endif /* DRV_BYTE_ORDER */ 3042 } lsm6dsv_sensor_hub_2_t; 3043 3044 #define LSM6DSV_SENSOR_HUB_3 0x4U 3045 typedef struct 3046 { 3047 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3048 uint8_t sensorhub3 : 8; 3049 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3050 uint8_t sensorhub3 : 8; 3051 #endif /* DRV_BYTE_ORDER */ 3052 } lsm6dsv_sensor_hub_3_t; 3053 3054 #define LSM6DSV_SENSOR_HUB_4 0x5U 3055 typedef struct 3056 { 3057 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3058 uint8_t sensorhub4 : 8; 3059 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3060 uint8_t sensorhub4 : 8; 3061 #endif /* DRV_BYTE_ORDER */ 3062 } lsm6dsv_sensor_hub_4_t; 3063 3064 #define LSM6DSV_SENSOR_HUB_5 0x6U 3065 typedef struct 3066 { 3067 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3068 uint8_t sensorhub5 : 8; 3069 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3070 uint8_t sensorhub5 : 8; 3071 #endif /* DRV_BYTE_ORDER */ 3072 } lsm6dsv_sensor_hub_5_t; 3073 3074 #define LSM6DSV_SENSOR_HUB_6 0x7U 3075 typedef struct 3076 { 3077 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3078 uint8_t sensorhub6 : 8; 3079 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3080 uint8_t sensorhub6 : 8; 3081 #endif /* DRV_BYTE_ORDER */ 3082 } lsm6dsv_sensor_hub_6_t; 3083 3084 #define LSM6DSV_SENSOR_HUB_7 0x8U 3085 typedef struct 3086 { 3087 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3088 uint8_t sensorhub7 : 8; 3089 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3090 uint8_t sensorhub7 : 8; 3091 #endif /* DRV_BYTE_ORDER */ 3092 } lsm6dsv_sensor_hub_7_t; 3093 3094 #define LSM6DSV_SENSOR_HUB_8 0x9U 3095 typedef struct 3096 { 3097 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3098 uint8_t sensorhub8 : 8; 3099 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3100 uint8_t sensorhub8 : 8; 3101 #endif /* DRV_BYTE_ORDER */ 3102 } lsm6dsv_sensor_hub_8_t; 3103 3104 #define LSM6DSV_SENSOR_HUB_9 0x0AU 3105 typedef struct 3106 { 3107 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3108 uint8_t sensorhub9 : 8; 3109 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3110 uint8_t sensorhub9 : 8; 3111 #endif /* DRV_BYTE_ORDER */ 3112 } lsm6dsv_sensor_hub_9_t; 3113 3114 #define LSM6DSV_SENSOR_HUB_10 0x0BU 3115 typedef struct 3116 { 3117 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3118 uint8_t sensorhub10 : 8; 3119 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3120 uint8_t sensorhub10 : 8; 3121 #endif /* DRV_BYTE_ORDER */ 3122 } lsm6dsv_sensor_hub_10_t; 3123 3124 #define LSM6DSV_SENSOR_HUB_11 0x0CU 3125 typedef struct 3126 { 3127 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3128 uint8_t sensorhub11 : 8; 3129 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3130 uint8_t sensorhub11 : 8; 3131 #endif /* DRV_BYTE_ORDER */ 3132 } lsm6dsv_sensor_hub_11_t; 3133 3134 #define LSM6DSV_SENSOR_HUB_12 0x0DU 3135 typedef struct 3136 { 3137 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3138 uint8_t sensorhub12 : 8; 3139 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3140 uint8_t sensorhub12 : 8; 3141 #endif /* DRV_BYTE_ORDER */ 3142 } lsm6dsv_sensor_hub_12_t; 3143 3144 #define LSM6DSV_SENSOR_HUB_13 0x0EU 3145 typedef struct 3146 { 3147 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3148 uint8_t sensorhub13 : 8; 3149 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3150 uint8_t sensorhub13 : 8; 3151 #endif /* DRV_BYTE_ORDER */ 3152 } lsm6dsv_sensor_hub_13_t; 3153 3154 #define LSM6DSV_SENSOR_HUB_14 0x0FU 3155 typedef struct 3156 { 3157 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3158 uint8_t sensorhub14 : 8; 3159 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3160 uint8_t sensorhub14 : 8; 3161 #endif /* DRV_BYTE_ORDER */ 3162 } lsm6dsv_sensor_hub_14_t; 3163 3164 #define LSM6DSV_SENSOR_HUB_15 0x10U 3165 typedef struct 3166 { 3167 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3168 uint8_t sensorhub15 : 8; 3169 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3170 uint8_t sensorhub15 : 8; 3171 #endif /* DRV_BYTE_ORDER */ 3172 } lsm6dsv_sensor_hub_15_t; 3173 3174 #define LSM6DSV_SENSOR_HUB_16 0x11U 3175 typedef struct 3176 { 3177 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3178 uint8_t sensorhub16 : 8; 3179 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3180 uint8_t sensorhub16 : 8; 3181 #endif /* DRV_BYTE_ORDER */ 3182 } lsm6dsv_sensor_hub_16_t; 3183 3184 #define LSM6DSV_SENSOR_HUB_17 0x12U 3185 typedef struct 3186 { 3187 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3188 uint8_t sensorhub17 : 8; 3189 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3190 uint8_t sensorhub17 : 8; 3191 #endif /* DRV_BYTE_ORDER */ 3192 } lsm6dsv_sensor_hub_17_t; 3193 3194 #define LSM6DSV_SENSOR_HUB_18 0x13U 3195 typedef struct 3196 { 3197 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3198 uint8_t sensorhub18 : 8; 3199 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3200 uint8_t sensorhub18 : 8; 3201 #endif /* DRV_BYTE_ORDER */ 3202 } lsm6dsv_sensor_hub_18_t; 3203 3204 #define LSM6DSV_MASTER_CONFIG 0x14U 3205 typedef struct 3206 { 3207 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3208 uint8_t aux_sens_on : 2; 3209 uint8_t master_on : 1; 3210 uint8_t not_used0 : 1; 3211 uint8_t pass_through_mode : 1; 3212 uint8_t start_config : 1; 3213 uint8_t write_once : 1; 3214 uint8_t rst_master_regs : 1; 3215 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3216 uint8_t rst_master_regs : 1; 3217 uint8_t write_once : 1; 3218 uint8_t start_config : 1; 3219 uint8_t pass_through_mode : 1; 3220 uint8_t not_used0 : 1; 3221 uint8_t master_on : 1; 3222 uint8_t aux_sens_on : 2; 3223 #endif /* DRV_BYTE_ORDER */ 3224 } lsm6dsv_master_config_t; 3225 3226 #define LSM6DSV_SLV0_ADD 0x15U 3227 typedef struct 3228 { 3229 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3230 uint8_t rw_0 : 1; 3231 uint8_t slave0_add : 7; 3232 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3233 uint8_t slave0_add : 7; 3234 uint8_t rw_0 : 1; 3235 #endif /* DRV_BYTE_ORDER */ 3236 } lsm6dsv_slv0_add_t; 3237 3238 #define LSM6DSV_SLV0_SUBADD 0x16U 3239 typedef struct 3240 { 3241 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3242 uint8_t slave0_reg : 8; 3243 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3244 uint8_t slave0_reg : 8; 3245 #endif /* DRV_BYTE_ORDER */ 3246 } lsm6dsv_slv0_subadd_t; 3247 3248 #define LSM6DSV_SLV0_CONFIG 0x17U 3249 typedef struct 3250 { 3251 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3252 uint8_t slave0_numop : 3; 3253 uint8_t batch_ext_sens_0_en : 1; 3254 uint8_t not_used0 : 1; 3255 uint8_t shub_odr : 3; 3256 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3257 uint8_t shub_odr : 3; 3258 uint8_t not_used0 : 1; 3259 uint8_t batch_ext_sens_0_en : 1; 3260 uint8_t slave0_numop : 3; 3261 #endif /* DRV_BYTE_ORDER */ 3262 } lsm6dsv_slv0_config_t; 3263 3264 #define LSM6DSV_SLV1_ADD 0x18U 3265 typedef struct 3266 { 3267 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3268 uint8_t r_1 : 1; 3269 uint8_t slave1_add : 7; 3270 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3271 uint8_t slave1_add : 7; 3272 uint8_t r_1 : 1; 3273 #endif /* DRV_BYTE_ORDER */ 3274 } lsm6dsv_slv1_add_t; 3275 3276 #define LSM6DSV_SLV1_SUBADD 0x19U 3277 typedef struct 3278 { 3279 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3280 uint8_t slave1_reg : 8; 3281 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3282 uint8_t slave1_reg : 8; 3283 #endif /* DRV_BYTE_ORDER */ 3284 } lsm6dsv_slv1_subadd_t; 3285 3286 #define LSM6DSV_SLV1_CONFIG 0x1AU 3287 typedef struct 3288 { 3289 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3290 uint8_t slave1_numop : 3; 3291 uint8_t batch_ext_sens_1_en : 1; 3292 uint8_t not_used0 : 4; 3293 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3294 uint8_t not_used0 : 4; 3295 uint8_t batch_ext_sens_1_en : 1; 3296 uint8_t slave1_numop : 3; 3297 #endif /* DRV_BYTE_ORDER */ 3298 } lsm6dsv_slv1_config_t; 3299 3300 #define LSM6DSV_SLV2_ADD 0x1BU 3301 typedef struct 3302 { 3303 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3304 uint8_t r_2 : 1; 3305 uint8_t slave2_add : 7; 3306 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3307 uint8_t slave2_add : 7; 3308 uint8_t r_2 : 1; 3309 #endif /* DRV_BYTE_ORDER */ 3310 } lsm6dsv_slv2_add_t; 3311 3312 #define LSM6DSV_SLV2_SUBADD 0x1CU 3313 typedef struct 3314 { 3315 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3316 uint8_t slave2_reg : 8; 3317 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3318 uint8_t slave2_reg : 8; 3319 #endif /* DRV_BYTE_ORDER */ 3320 } lsm6dsv_slv2_subadd_t; 3321 3322 #define LSM6DSV_SLV2_CONFIG 0x1DU 3323 typedef struct 3324 { 3325 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3326 uint8_t slave2_numop : 3; 3327 uint8_t batch_ext_sens_2_en : 1; 3328 uint8_t not_used0 : 4; 3329 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3330 uint8_t not_used0 : 4; 3331 uint8_t batch_ext_sens_2_en : 1; 3332 uint8_t slave2_numop : 3; 3333 #endif /* DRV_BYTE_ORDER */ 3334 } lsm6dsv_slv2_config_t; 3335 3336 #define LSM6DSV_SLV3_ADD 0x1EU 3337 typedef struct 3338 { 3339 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3340 uint8_t r_3 : 1; 3341 uint8_t slave3_add : 7; 3342 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3343 uint8_t slave3_add : 7; 3344 uint8_t r_3 : 1; 3345 #endif /* DRV_BYTE_ORDER */ 3346 } lsm6dsv_slv3_add_t; 3347 3348 #define LSM6DSV_SLV3_SUBADD 0x1FU 3349 typedef struct 3350 { 3351 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3352 uint8_t slave3_reg : 8; 3353 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3354 uint8_t slave3_reg : 8; 3355 #endif /* DRV_BYTE_ORDER */ 3356 } lsm6dsv_slv3_subadd_t; 3357 3358 #define LSM6DSV_SLV3_CONFIG 0x20U 3359 typedef struct 3360 { 3361 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3362 uint8_t slave3_numop : 3; 3363 uint8_t batch_ext_sens_3_en : 1; 3364 uint8_t not_used0 : 4; 3365 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3366 uint8_t not_used0 : 4; 3367 uint8_t batch_ext_sens_3_en : 1; 3368 uint8_t slave3_numop : 3; 3369 #endif /* DRV_BYTE_ORDER */ 3370 } lsm6dsv_slv3_config_t; 3371 3372 #define LSM6DSV_DATAWRITE_SLV0 0x21U 3373 typedef struct 3374 { 3375 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3376 uint8_t slave0_dataw : 8; 3377 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3378 uint8_t slave0_dataw : 8; 3379 #endif /* DRV_BYTE_ORDER */ 3380 } lsm6dsv_datawrite_slv0_t; 3381 3382 #define LSM6DSV_STATUS_MASTER 0x22U 3383 typedef struct 3384 { 3385 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 3386 uint8_t sens_hub_endop : 1; 3387 uint8_t not_used0 : 2; 3388 uint8_t slave0_nack : 1; 3389 uint8_t slave1_nack : 1; 3390 uint8_t slave2_nack : 1; 3391 uint8_t slave3_nack : 1; 3392 uint8_t wr_once_done : 1; 3393 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 3394 uint8_t wr_once_done : 1; 3395 uint8_t slave3_nack : 1; 3396 uint8_t slave2_nack : 1; 3397 uint8_t slave1_nack : 1; 3398 uint8_t slave0_nack : 1; 3399 uint8_t not_used0 : 2; 3400 uint8_t sens_hub_endop : 1; 3401 #endif /* DRV_BYTE_ORDER */ 3402 } lsm6dsv_status_master_t; 3403 3404 /** 3405 * @} 3406 * 3407 */ 3408 3409 /** 3410 * @defgroup LSM6DSV_Register_Union 3411 * @brief This union group all the registers having a bit-field 3412 * description. 3413 * This union is useful but it's not needed by the driver. 3414 * 3415 * REMOVING this union you are compliant with: 3416 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 3417 * 3418 * @{ 3419 * 3420 */ 3421 typedef union 3422 { 3423 lsm6dsv_func_cfg_access_t func_cfg_access; 3424 lsm6dsv_pin_ctrl_t pin_ctrl; 3425 lsm6dsv_if_cfg_t if_cfg; 3426 lsm6dsv_odr_trig_cfg_t odr_trig_cfg; 3427 lsm6dsv_fifo_ctrl1_t fifo_ctrl1; 3428 lsm6dsv_fifo_ctrl2_t fifo_ctrl2; 3429 lsm6dsv_fifo_ctrl3_t fifo_ctrl3; 3430 lsm6dsv_fifo_ctrl4_t fifo_ctrl4; 3431 lsm6dsv_counter_bdr_reg1_t counter_bdr_reg1; 3432 lsm6dsv_counter_bdr_reg2_t counter_bdr_reg2; 3433 lsm6dsv_int1_ctrl_t int1_ctrl; 3434 lsm6dsv_int2_ctrl_t int2_ctrl; 3435 lsm6dsv_who_am_i_t who_am_i; 3436 lsm6dsv_ctrl1_t ctrl1; 3437 lsm6dsv_ctrl2_t ctrl2; 3438 lsm6dsv_ctrl3_t ctrl3; 3439 lsm6dsv_ctrl4_t ctrl4; 3440 lsm6dsv_ctrl5_t ctrl5; 3441 lsm6dsv_ctrl6_t ctrl6; 3442 lsm6dsv_ctrl7_t ctrl7; 3443 lsm6dsv_ctrl8_t ctrl8; 3444 lsm6dsv_ctrl9_t ctrl9; 3445 lsm6dsv_ctrl10_t ctrl10; 3446 lsm6dsv_ctrl_status_t ctrl_status; 3447 lsm6dsv_fifo_status1_t fifo_status1; 3448 lsm6dsv_fifo_status2_t fifo_status2; 3449 lsm6dsv_all_int_src_t all_int_src; 3450 lsm6dsv_status_reg_t status_reg; 3451 lsm6dsv_out_temp_l_t out_temp_l; 3452 lsm6dsv_out_temp_h_t out_temp_h; 3453 lsm6dsv_outx_l_g_t outx_l_g; 3454 lsm6dsv_outx_h_g_t outx_h_g; 3455 lsm6dsv_outy_l_g_t outy_l_g; 3456 lsm6dsv_outy_h_g_t outy_h_g; 3457 lsm6dsv_outz_l_g_t outz_l_g; 3458 lsm6dsv_outz_h_g_t outz_h_g; 3459 lsm6dsv_outx_l_a_t outx_l_a; 3460 lsm6dsv_outx_h_a_t outx_h_a; 3461 lsm6dsv_outy_l_a_t outy_l_a; 3462 lsm6dsv_outy_h_a_t outy_h_a; 3463 lsm6dsv_outz_l_a_t outz_l_a; 3464 lsm6dsv_outz_h_a_t outz_h_a; 3465 lsm6dsv_ui_outx_l_g_ois_eis_t ui_outx_l_g_ois_eis; 3466 lsm6dsv_ui_outx_h_g_ois_eis_t ui_outx_h_g_ois_eis; 3467 lsm6dsv_ui_outy_l_g_ois_eis_t ui_outy_l_g_ois_eis; 3468 lsm6dsv_ui_outy_h_g_ois_eis_t ui_outy_h_g_ois_eis; 3469 lsm6dsv_ui_outz_l_g_ois_eis_t ui_outz_l_g_ois_eis; 3470 lsm6dsv_ui_outz_h_g_ois_eis_t ui_outz_h_g_ois_eis; 3471 lsm6dsv_ui_outx_l_a_ois_dualc_t ui_outx_l_a_ois_dualc; 3472 lsm6dsv_ui_outx_h_a_ois_dualc_t ui_outx_h_a_ois_dualc; 3473 lsm6dsv_ui_outy_l_a_ois_dualc_t ui_outy_l_a_ois_dualc; 3474 lsm6dsv_ui_outy_h_a_ois_dualc_t ui_outy_h_a_ois_dualc; 3475 lsm6dsv_ui_outz_l_a_ois_dualc_t ui_outz_l_a_ois_dualc; 3476 lsm6dsv_ui_outz_h_a_ois_dualc_t ui_outz_h_a_ois_dualc; 3477 lsm6dsv_timestamp0_t timestamp0; 3478 lsm6dsv_timestamp1_t timestamp1; 3479 lsm6dsv_timestamp2_t timestamp2; 3480 lsm6dsv_timestamp3_t timestamp3; 3481 lsm6dsv_ui_status_reg_ois_t ui_status_reg_ois; 3482 lsm6dsv_wake_up_src_t wake_up_src; 3483 lsm6dsv_tap_src_t tap_src; 3484 lsm6dsv_d6d_src_t d6d_src; 3485 lsm6dsv_status_master_mainpage_t status_master_mainpage; 3486 lsm6dsv_emb_func_status_mainpage_t emb_func_status_mainpage; 3487 lsm6dsv_fsm_status_mainpage_t fsm_status_mainpage; 3488 lsm6dsv_internal_freq_t internal_freq; 3489 lsm6dsv_functions_enable_t functions_enable; 3490 lsm6dsv_den_t den; 3491 lsm6dsv_inactivity_dur_t inactivity_dur; 3492 lsm6dsv_inactivity_ths_t inactivity_ths; 3493 lsm6dsv_tap_cfg0_t tap_cfg0; 3494 lsm6dsv_tap_cfg1_t tap_cfg1; 3495 lsm6dsv_tap_cfg2_t tap_cfg2; 3496 lsm6dsv_tap_ths_6d_t tap_ths_6d; 3497 lsm6dsv_tap_dur_t tap_dur; 3498 lsm6dsv_wake_up_ths_t wake_up_ths; 3499 lsm6dsv_wake_up_dur_t wake_up_dur; 3500 lsm6dsv_free_fall_t free_fall; 3501 lsm6dsv_md1_cfg_t md1_cfg; 3502 lsm6dsv_md2_cfg_t md2_cfg; 3503 lsm6dsv_emb_func_cfg_t emb_func_cfg; 3504 lsm6dsv_ui_handshake_ctrl_t ui_handshake_ctrl; 3505 lsm6dsv_ui_spi2_shared_0_t ui_spi2_shared_0; 3506 lsm6dsv_ui_spi2_shared_1_t ui_spi2_shared_1; 3507 lsm6dsv_ui_spi2_shared_2_t ui_spi2_shared_2; 3508 lsm6dsv_ui_spi2_shared_3_t ui_spi2_shared_3; 3509 lsm6dsv_ui_spi2_shared_4_t ui_spi2_shared_4; 3510 lsm6dsv_ui_spi2_shared_5_t ui_spi2_shared_5; 3511 lsm6dsv_ctrl_eis_t ctrl_eis; 3512 lsm6dsv_ui_int_ois_t ui_int_ois; 3513 lsm6dsv_ui_ctrl1_ois_t ui_ctrl1_ois; 3514 lsm6dsv_ui_ctrl2_ois_t ui_ctrl2_ois; 3515 lsm6dsv_ui_ctrl3_ois_t ui_ctrl3_ois; 3516 lsm6dsv_x_ofs_usr_t x_ofs_usr; 3517 lsm6dsv_y_ofs_usr_t y_ofs_usr; 3518 lsm6dsv_z_ofs_usr_t z_ofs_usr; 3519 lsm6dsv_fifo_data_out_tag_t fifo_data_out_tag; 3520 lsm6dsv_fifo_data_out_x_l_t fifo_data_out_x_l; 3521 lsm6dsv_fifo_data_out_x_h_t fifo_data_out_x_h; 3522 lsm6dsv_fifo_data_out_y_l_t fifo_data_out_y_l; 3523 lsm6dsv_fifo_data_out_y_h_t fifo_data_out_y_h; 3524 lsm6dsv_fifo_data_out_z_l_t fifo_data_out_z_l; 3525 lsm6dsv_fifo_data_out_z_h_t fifo_data_out_z_h; 3526 lsm6dsv_spi2_who_am_i_t spi2_who_am_i; 3527 lsm6dsv_spi2_status_reg_ois_t spi2_status_reg_ois; 3528 lsm6dsv_spi2_out_temp_l_t spi2_out_temp_l; 3529 lsm6dsv_spi2_out_temp_h_t spi2_out_temp_h; 3530 lsm6dsv_spi2_outx_l_g_ois_t spi2_outx_l_g_ois; 3531 lsm6dsv_spi2_outx_h_g_ois_t spi2_outx_h_g_ois; 3532 lsm6dsv_spi2_outy_l_g_ois_t spi2_outy_l_g_ois; 3533 lsm6dsv_spi2_outy_h_g_ois_t spi2_outy_h_g_ois; 3534 lsm6dsv_spi2_outz_l_g_ois_t spi2_outz_l_g_ois; 3535 lsm6dsv_spi2_outz_h_g_ois_t spi2_outz_h_g_ois; 3536 lsm6dsv_spi2_outx_l_a_ois_t spi2_outx_l_a_ois; 3537 lsm6dsv_spi2_outx_h_a_ois_t spi2_outx_h_a_ois; 3538 lsm6dsv_spi2_outy_l_a_ois_t spi2_outy_l_a_ois; 3539 lsm6dsv_spi2_outy_h_a_ois_t spi2_outy_h_a_ois; 3540 lsm6dsv_spi2_outz_l_a_ois_t spi2_outz_l_a_ois; 3541 lsm6dsv_spi2_outz_h_a_ois_t spi2_outz_h_a_ois; 3542 lsm6dsv_spi2_handshake_ctrl_t spi2_handshake_ctrl; 3543 lsm6dsv_spi2_int_ois_t spi2_int_ois; 3544 lsm6dsv_spi2_ctrl1_ois_t spi2_ctrl1_ois; 3545 lsm6dsv_spi2_ctrl2_ois_t spi2_ctrl2_ois; 3546 lsm6dsv_spi2_ctrl3_ois_t spi2_ctrl3_ois; 3547 lsm6dsv_page_sel_t page_sel; 3548 lsm6dsv_emb_func_en_a_t emb_func_en_a; 3549 lsm6dsv_emb_func_en_b_t emb_func_en_b; 3550 lsm6dsv_emb_func_exec_status_t emb_func_exec_status; 3551 lsm6dsv_page_address_t page_address; 3552 lsm6dsv_page_value_t page_value; 3553 lsm6dsv_emb_func_int1_t emb_func_int1; 3554 lsm6dsv_fsm_int1_t fsm_int1; 3555 lsm6dsv_emb_func_int2_t emb_func_int2; 3556 lsm6dsv_fsm_int2_t fsm_int2; 3557 lsm6dsv_emb_func_status_t emb_func_status; 3558 lsm6dsv_fsm_status_t fsm_status; 3559 lsm6dsv_page_rw_t page_rw; 3560 lsm6dsv_emb_func_fifo_en_a_t emb_func_fifo_en_a; 3561 lsm6dsv_fsm_enable_t fsm_enable; 3562 lsm6dsv_fsm_long_counter_l_t fsm_long_counter_l; 3563 lsm6dsv_fsm_long_counter_h_t fsm_long_counter_h; 3564 lsm6dsv_int_ack_mask_t int_ack_mask; 3565 lsm6dsv_fsm_outs1_t fsm_outs1; 3566 lsm6dsv_fsm_outs2_t fsm_outs2; 3567 lsm6dsv_fsm_outs3_t fsm_outs3; 3568 lsm6dsv_fsm_outs4_t fsm_outs4; 3569 lsm6dsv_fsm_outs5_t fsm_outs5; 3570 lsm6dsv_fsm_outs6_t fsm_outs6; 3571 lsm6dsv_fsm_outs7_t fsm_outs7; 3572 lsm6dsv_fsm_outs8_t fsm_outs8; 3573 lsm6dsv_fsm_odr_t fsm_odr; 3574 lsm6dsv_step_counter_l_t step_counter_l; 3575 lsm6dsv_step_counter_h_t step_counter_h; 3576 lsm6dsv_emb_func_src_t emb_func_src; 3577 lsm6dsv_emb_func_init_a_t emb_func_init_a; 3578 lsm6dsv_emb_func_init_b_t emb_func_init_b; 3579 lsm6dsv_fsm_ext_sensitivity_l_t fsm_ext_sensitivity_l; 3580 lsm6dsv_fsm_ext_sensitivity_h_t fsm_ext_sensitivity_h; 3581 lsm6dsv_fsm_ext_offx_l_t fsm_ext_offx_l; 3582 lsm6dsv_fsm_ext_offx_h_t fsm_ext_offx_h; 3583 lsm6dsv_fsm_ext_offy_l_t fsm_ext_offy_l; 3584 lsm6dsv_fsm_ext_offy_h_t fsm_ext_offy_h; 3585 lsm6dsv_fsm_ext_offz_l_t fsm_ext_offz_l; 3586 lsm6dsv_fsm_ext_offz_h_t fsm_ext_offz_h; 3587 lsm6dsv_fsm_ext_matrix_xx_l_t fsm_ext_matrix_xx_l; 3588 lsm6dsv_fsm_ext_matrix_xx_h_t fsm_ext_matrix_xx_h; 3589 lsm6dsv_fsm_ext_matrix_xy_l_t fsm_ext_matrix_xy_l; 3590 lsm6dsv_fsm_ext_matrix_xy_h_t fsm_ext_matrix_xy_h; 3591 lsm6dsv_fsm_ext_matrix_xz_l_t fsm_ext_matrix_xz_l; 3592 lsm6dsv_fsm_ext_matrix_xz_h_t fsm_ext_matrix_xz_h; 3593 lsm6dsv_fsm_ext_matrix_yy_l_t fsm_ext_matrix_yy_l; 3594 lsm6dsv_fsm_ext_matrix_yy_h_t fsm_ext_matrix_yy_h; 3595 lsm6dsv_fsm_ext_matrix_yz_l_t fsm_ext_matrix_yz_l; 3596 lsm6dsv_fsm_ext_matrix_yz_h_t fsm_ext_matrix_yz_h; 3597 lsm6dsv_fsm_ext_matrix_zz_l_t fsm_ext_matrix_zz_l; 3598 lsm6dsv_fsm_ext_matrix_zz_h_t fsm_ext_matrix_zz_h; 3599 lsm6dsv_ext_cfg_a_t ext_cfg_a; 3600 lsm6dsv_ext_cfg_b_t ext_cfg_b; 3601 lsm6dsv_fsm_lc_timeout_l_t fsm_lc_timeout_l; 3602 lsm6dsv_fsm_lc_timeout_h_t fsm_lc_timeout_h; 3603 lsm6dsv_fsm_programs_t fsm_programs; 3604 lsm6dsv_fsm_start_add_l_t fsm_start_add_l; 3605 lsm6dsv_fsm_start_add_h_t fsm_start_add_h; 3606 lsm6dsv_pedo_cmd_reg_t pedo_cmd_reg; 3607 lsm6dsv_pedo_deb_steps_conf_t pedo_deb_steps_conf; 3608 lsm6dsv_pedo_sc_deltat_l_t pedo_sc_deltat_l; 3609 lsm6dsv_pedo_sc_deltat_h_t pedo_sc_deltat_h; 3610 lsm6dsv_sensor_hub_1_t sensor_hub_1; 3611 lsm6dsv_sensor_hub_2_t sensor_hub_2; 3612 lsm6dsv_sensor_hub_3_t sensor_hub_3; 3613 lsm6dsv_sensor_hub_4_t sensor_hub_4; 3614 lsm6dsv_sensor_hub_5_t sensor_hub_5; 3615 lsm6dsv_sensor_hub_6_t sensor_hub_6; 3616 lsm6dsv_sensor_hub_7_t sensor_hub_7; 3617 lsm6dsv_sensor_hub_8_t sensor_hub_8; 3618 lsm6dsv_sensor_hub_9_t sensor_hub_9; 3619 lsm6dsv_sensor_hub_10_t sensor_hub_10; 3620 lsm6dsv_sensor_hub_11_t sensor_hub_11; 3621 lsm6dsv_sensor_hub_12_t sensor_hub_12; 3622 lsm6dsv_sensor_hub_13_t sensor_hub_13; 3623 lsm6dsv_sensor_hub_14_t sensor_hub_14; 3624 lsm6dsv_sensor_hub_15_t sensor_hub_15; 3625 lsm6dsv_sensor_hub_16_t sensor_hub_16; 3626 lsm6dsv_sensor_hub_17_t sensor_hub_17; 3627 lsm6dsv_sensor_hub_18_t sensor_hub_18; 3628 lsm6dsv_master_config_t master_config; 3629 lsm6dsv_slv0_add_t slv0_add; 3630 lsm6dsv_slv0_subadd_t slv0_subadd; 3631 lsm6dsv_slv0_config_t slv0_config; 3632 lsm6dsv_slv1_add_t slv1_add; 3633 lsm6dsv_slv1_subadd_t slv1_subadd; 3634 lsm6dsv_slv1_config_t slv1_config; 3635 lsm6dsv_slv2_add_t slv2_add; 3636 lsm6dsv_slv2_subadd_t slv2_subadd; 3637 lsm6dsv_slv2_config_t slv2_config; 3638 lsm6dsv_slv3_add_t slv3_add; 3639 lsm6dsv_slv3_subadd_t slv3_subadd; 3640 lsm6dsv_slv3_config_t slv3_config; 3641 lsm6dsv_datawrite_slv0_t datawrite_slv0; 3642 lsm6dsv_status_master_t status_master; 3643 bitwise_t bitwise; 3644 uint8_t byte; 3645 } lsm6dsv_reg_t; 3646 3647 /** 3648 * @} 3649 * 3650 */ 3651 3652 #ifndef __weak 3653 #define __weak __attribute__((weak)) 3654 #endif /* __weak */ 3655 3656 /* 3657 * These are the basic platform dependent I/O routines to read 3658 * and write device registers connected on a standard bus. 3659 * The driver keeps offering a default implementation based on function 3660 * pointers to read/write routines for backward compatibility. 3661 * The __weak directive allows the final application to overwrite 3662 * them with a custom implementation. 3663 */ 3664 3665 int32_t lsm6dsv_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 3666 uint8_t *data, 3667 uint16_t len); 3668 int32_t lsm6dsv_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 3669 uint8_t *data, 3670 uint16_t len); 3671 3672 float_t lsm6dsv_from_sflp_to_mg(int16_t lsb); 3673 float_t lsm6dsv_from_fs2_to_mg(int16_t lsb); 3674 float_t lsm6dsv_from_fs4_to_mg(int16_t lsb); 3675 float_t lsm6dsv_from_fs8_to_mg(int16_t lsb); 3676 float_t lsm6dsv_from_fs16_to_mg(int16_t lsb); 3677 3678 float_t lsm6dsv_from_fs125_to_mdps(int16_t lsb); 3679 float_t lsm6dsv_from_fs500_to_mdps(int16_t lsb); 3680 float_t lsm6dsv_from_fs250_to_mdps(int16_t lsb); 3681 float_t lsm6dsv_from_fs1000_to_mdps(int16_t lsb); 3682 float_t lsm6dsv_from_fs2000_to_mdps(int16_t lsb); 3683 float_t lsm6dsv_from_fs4000_to_mdps(int16_t lsb); 3684 3685 float_t lsm6dsv_from_lsb_to_celsius(int16_t lsb); 3686 3687 float_t lsm6dsv_from_lsb_to_nsec(uint32_t lsb); 3688 3689 uint32_t lsm6dsv_from_f16_to_f32(uint16_t val); 3690 3691 int32_t lsm6dsv_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val); 3692 int32_t lsm6dsv_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val); 3693 3694 typedef struct 3695 { 3696 float_t z_mg; 3697 float_t y_mg; 3698 float_t x_mg; 3699 } lsm6dsv_xl_offset_mg_t; 3700 int32_t lsm6dsv_xl_offset_mg_set(const stmdev_ctx_t *ctx, 3701 lsm6dsv_xl_offset_mg_t val); 3702 int32_t lsm6dsv_xl_offset_mg_get(const stmdev_ctx_t *ctx, 3703 lsm6dsv_xl_offset_mg_t *val); 3704 3705 typedef enum 3706 { 3707 LSM6DSV_READY = 0x0, 3708 LSM6DSV_GLOBAL_RST = 0x1, 3709 LSM6DSV_RESTORE_CAL_PARAM = 0x2, 3710 LSM6DSV_RESTORE_CTRL_REGS = 0x4, 3711 } lsm6dsv_reset_t; 3712 int32_t lsm6dsv_reset_set(const stmdev_ctx_t *ctx, lsm6dsv_reset_t val); 3713 int32_t lsm6dsv_reset_get(const stmdev_ctx_t *ctx, lsm6dsv_reset_t *val); 3714 3715 typedef enum 3716 { 3717 LSM6DSV_MAIN_MEM_BANK = 0x0, 3718 LSM6DSV_EMBED_FUNC_MEM_BANK = 0x1, 3719 LSM6DSV_SENSOR_HUB_MEM_BANK = 0x2, 3720 } lsm6dsv_mem_bank_t; 3721 int32_t lsm6dsv_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsv_mem_bank_t val); 3722 int32_t lsm6dsv_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsv_mem_bank_t *val); 3723 3724 int32_t lsm6dsv_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); 3725 3726 typedef enum 3727 { 3728 LSM6DSV_ODR_OFF = 0x0, 3729 LSM6DSV_ODR_AT_1Hz875 = 0x1, 3730 LSM6DSV_ODR_AT_7Hz5 = 0x2, 3731 LSM6DSV_ODR_AT_15Hz = 0x3, 3732 LSM6DSV_ODR_AT_30Hz = 0x4, 3733 LSM6DSV_ODR_AT_60Hz = 0x5, 3734 LSM6DSV_ODR_AT_120Hz = 0x6, 3735 LSM6DSV_ODR_AT_240Hz = 0x7, 3736 LSM6DSV_ODR_AT_480Hz = 0x8, 3737 LSM6DSV_ODR_AT_960Hz = 0x9, 3738 LSM6DSV_ODR_AT_1920Hz = 0xA, 3739 LSM6DSV_ODR_AT_3840Hz = 0xB, 3740 LSM6DSV_ODR_AT_7680Hz = 0xC, 3741 LSM6DSV_ODR_HA01_AT_15Hz625 = 0x13, 3742 LSM6DSV_ODR_HA01_AT_31Hz25 = 0x14, 3743 LSM6DSV_ODR_HA01_AT_62Hz5 = 0x15, 3744 LSM6DSV_ODR_HA01_AT_125Hz = 0x16, 3745 LSM6DSV_ODR_HA01_AT_250Hz = 0x17, 3746 LSM6DSV_ODR_HA01_AT_500Hz = 0x18, 3747 LSM6DSV_ODR_HA01_AT_1000Hz = 0x19, 3748 LSM6DSV_ODR_HA01_AT_2000Hz = 0x1A, 3749 LSM6DSV_ODR_HA01_AT_4000Hz = 0x1B, 3750 LSM6DSV_ODR_HA01_AT_8000Hz = 0x1C, 3751 LSM6DSV_ODR_HA02_AT_12Hz5 = 0x23, 3752 LSM6DSV_ODR_HA02_AT_25Hz = 0x24, 3753 LSM6DSV_ODR_HA02_AT_50Hz = 0x25, 3754 LSM6DSV_ODR_HA02_AT_100Hz = 0x26, 3755 LSM6DSV_ODR_HA02_AT_200Hz = 0x27, 3756 LSM6DSV_ODR_HA02_AT_400Hz = 0x28, 3757 LSM6DSV_ODR_HA02_AT_800Hz = 0x29, 3758 LSM6DSV_ODR_HA02_AT_1600Hz = 0x2A, 3759 LSM6DSV_ODR_HA02_AT_3200Hz = 0x2B, 3760 LSM6DSV_ODR_HA02_AT_6400Hz = 0x2C, 3761 } lsm6dsv_data_rate_t; 3762 int32_t lsm6dsv_xl_data_rate_set(const stmdev_ctx_t *ctx, 3763 lsm6dsv_data_rate_t val); 3764 int32_t lsm6dsv_xl_data_rate_get(const stmdev_ctx_t *ctx, 3765 lsm6dsv_data_rate_t *val); 3766 int32_t lsm6dsv_gy_data_rate_set(const stmdev_ctx_t *ctx, 3767 lsm6dsv_data_rate_t val); 3768 int32_t lsm6dsv_gy_data_rate_get(const stmdev_ctx_t *ctx, 3769 lsm6dsv_data_rate_t *val); 3770 3771 3772 typedef enum 3773 { 3774 LSM6DSV_XL_HIGH_PERFORMANCE_MD = 0x0, 3775 LSM6DSV_XL_HIGH_ACCURACY_ODR_MD = 0x1, 3776 LSM6DSV_XL_ODR_TRIGGERED_MD = 0x3, 3777 LSM6DSV_XL_LOW_POWER_2_AVG_MD = 0x4, 3778 LSM6DSV_XL_LOW_POWER_4_AVG_MD = 0x5, 3779 LSM6DSV_XL_LOW_POWER_8_AVG_MD = 0x6, 3780 LSM6DSV_XL_NORMAL_MD = 0x7, 3781 } lsm6dsv_xl_mode_t; 3782 int32_t lsm6dsv_xl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_xl_mode_t val); 3783 int32_t lsm6dsv_xl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_xl_mode_t *val); 3784 3785 typedef enum 3786 { 3787 LSM6DSV_GY_HIGH_PERFORMANCE_MD = 0x0, 3788 LSM6DSV_GY_HIGH_ACCURACY_ODR_MD = 0x1, 3789 LSM6DSV_GY_SLEEP_MD = 0x4, 3790 LSM6DSV_GY_LOW_POWER_MD = 0x5, 3791 } lsm6dsv_gy_mode_t; 3792 int32_t lsm6dsv_gy_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_gy_mode_t val); 3793 int32_t lsm6dsv_gy_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_gy_mode_t *val); 3794 3795 int32_t lsm6dsv_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 3796 int32_t lsm6dsv_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 3797 3798 int32_t lsm6dsv_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); 3799 int32_t lsm6dsv_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); 3800 3801 int32_t lsm6dsv_odr_trig_cfg_set(const stmdev_ctx_t *ctx, uint8_t val); 3802 int32_t lsm6dsv_odr_trig_cfg_get(const stmdev_ctx_t *ctx, uint8_t *val); 3803 3804 typedef enum 3805 { 3806 LSM6DSV_DRDY_LATCHED = 0x0, 3807 LSM6DSV_DRDY_PULSED = 0x1, 3808 } lsm6dsv_data_ready_mode_t; 3809 int32_t lsm6dsv_data_ready_mode_set(const stmdev_ctx_t *ctx, 3810 lsm6dsv_data_ready_mode_t val); 3811 int32_t lsm6dsv_data_ready_mode_get(const stmdev_ctx_t *ctx, 3812 lsm6dsv_data_ready_mode_t *val); 3813 3814 typedef struct 3815 { 3816 uint8_t enable : 1; /* interrupt enable */ 3817 uint8_t lir : 1; /* interrupt pulsed or latched */ 3818 } lsm6dsv_interrupt_mode_t; 3819 int32_t lsm6dsv_interrupt_enable_set(const stmdev_ctx_t *ctx, 3820 lsm6dsv_interrupt_mode_t val); 3821 int32_t lsm6dsv_interrupt_enable_get(const stmdev_ctx_t *ctx, 3822 lsm6dsv_interrupt_mode_t *val); 3823 3824 typedef enum 3825 { 3826 LSM6DSV_125dps = 0x0, 3827 LSM6DSV_250dps = 0x1, 3828 LSM6DSV_500dps = 0x2, 3829 LSM6DSV_1000dps = 0x3, 3830 LSM6DSV_2000dps = 0x4, 3831 LSM6DSV_4000dps = 0xc, 3832 } lsm6dsv_gy_full_scale_t; 3833 int32_t lsm6dsv_gy_full_scale_set(const stmdev_ctx_t *ctx, 3834 lsm6dsv_gy_full_scale_t val); 3835 int32_t lsm6dsv_gy_full_scale_get(const stmdev_ctx_t *ctx, 3836 lsm6dsv_gy_full_scale_t *val); 3837 3838 typedef enum 3839 { 3840 LSM6DSV_2g = 0x0, 3841 LSM6DSV_4g = 0x1, 3842 LSM6DSV_8g = 0x2, 3843 LSM6DSV_16g = 0x3, 3844 } lsm6dsv_xl_full_scale_t; 3845 int32_t lsm6dsv_xl_full_scale_set(const stmdev_ctx_t *ctx, 3846 lsm6dsv_xl_full_scale_t val); 3847 int32_t lsm6dsv_xl_full_scale_get(const stmdev_ctx_t *ctx, 3848 lsm6dsv_xl_full_scale_t *val); 3849 3850 int32_t lsm6dsv_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val); 3851 int32_t lsm6dsv_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val); 3852 3853 typedef enum 3854 { 3855 LSM6DSV_XL_ST_DISABLE = 0x0, 3856 LSM6DSV_XL_ST_POSITIVE = 0x1, 3857 LSM6DSV_XL_ST_NEGATIVE = 0x2, 3858 } lsm6dsv_xl_self_test_t; 3859 int32_t lsm6dsv_xl_self_test_set(const stmdev_ctx_t *ctx, 3860 lsm6dsv_xl_self_test_t val); 3861 int32_t lsm6dsv_xl_self_test_get(const stmdev_ctx_t *ctx, 3862 lsm6dsv_xl_self_test_t *val); 3863 3864 typedef enum 3865 { 3866 LSM6DSV_OIS_XL_ST_DISABLE = 0x0, 3867 LSM6DSV_OIS_XL_ST_POSITIVE = 0x1, 3868 LSM6DSV_OIS_XL_ST_NEGATIVE = 0x2, 3869 } lsm6dsv_ois_xl_self_test_t; 3870 int32_t lsm6dsv_ois_xl_self_test_set(const stmdev_ctx_t *ctx, 3871 lsm6dsv_ois_xl_self_test_t val); 3872 int32_t lsm6dsv_ois_xl_self_test_get(const stmdev_ctx_t *ctx, 3873 lsm6dsv_ois_xl_self_test_t *val); 3874 3875 typedef enum 3876 { 3877 LSM6DSV_GY_ST_DISABLE = 0x0, 3878 LSM6DSV_GY_ST_POSITIVE = 0x1, 3879 LSM6DSV_GY_ST_NEGATIVE = 0x2, 3880 3881 } lsm6dsv_gy_self_test_t; 3882 int32_t lsm6dsv_gy_self_test_set(const stmdev_ctx_t *ctx, 3883 lsm6dsv_gy_self_test_t val); 3884 int32_t lsm6dsv_gy_self_test_get(const stmdev_ctx_t *ctx, 3885 lsm6dsv_gy_self_test_t *val); 3886 3887 typedef enum 3888 { 3889 LSM6DSV_OIS_GY_ST_DISABLE = 0x0, 3890 LSM6DSV_OIS_GY_ST_POSITIVE = 0x1, 3891 LSM6DSV_OIS_GY_ST_NEGATIVE = 0x2, 3892 LSM6DSV_OIS_GY_ST_CLAMP_POS = 0x5, 3893 LSM6DSV_OIS_GY_ST_CLAMP_NEG = 0x6, 3894 3895 } lsm6dsv_ois_gy_self_test_t; 3896 int32_t lsm6dsv_ois_gy_self_test_set(const stmdev_ctx_t *ctx, 3897 lsm6dsv_ois_gy_self_test_t val); 3898 int32_t lsm6dsv_ois_gy_self_test_get(const stmdev_ctx_t *ctx, 3899 lsm6dsv_ois_gy_self_test_t *val); 3900 3901 typedef struct 3902 { 3903 uint8_t drdy_xl : 1; 3904 uint8_t drdy_gy : 1; 3905 uint8_t drdy_temp : 1; 3906 uint8_t drdy_eis : 1; 3907 uint8_t drdy_ois : 1; 3908 uint8_t gy_settling : 1; 3909 uint8_t timestamp : 1; 3910 uint8_t free_fall : 1; 3911 uint8_t wake_up : 1; 3912 uint8_t wake_up_z : 1; 3913 uint8_t wake_up_y : 1; 3914 uint8_t wake_up_x : 1; 3915 uint8_t single_tap : 1; 3916 uint8_t double_tap : 1; 3917 uint8_t tap_z : 1; 3918 uint8_t tap_y : 1; 3919 uint8_t tap_x : 1; 3920 uint8_t tap_sign : 1; 3921 uint8_t six_d : 1; 3922 uint8_t six_d_xl : 1; 3923 uint8_t six_d_xh : 1; 3924 uint8_t six_d_yl : 1; 3925 uint8_t six_d_yh : 1; 3926 uint8_t six_d_zl : 1; 3927 uint8_t six_d_zh : 1; 3928 uint8_t sleep_change : 1; 3929 uint8_t sleep_state : 1; 3930 uint8_t step_detector : 1; 3931 uint8_t step_count_inc : 1; 3932 uint8_t step_count_overflow : 1; 3933 uint8_t step_on_delta_time : 1; 3934 uint8_t emb_func_stand_by : 1; 3935 uint8_t emb_func_time_exceed : 1; 3936 uint8_t tilt : 1; 3937 uint8_t sig_mot : 1; 3938 uint8_t fsm_lc : 1; 3939 uint8_t fsm1 : 1; 3940 uint8_t fsm2 : 1; 3941 uint8_t fsm3 : 1; 3942 uint8_t fsm4 : 1; 3943 uint8_t fsm5 : 1; 3944 uint8_t fsm6 : 1; 3945 uint8_t fsm7 : 1; 3946 uint8_t fsm8 : 1; 3947 uint8_t sh_endop : 1; 3948 uint8_t sh_slave0_nack : 1; 3949 uint8_t sh_slave1_nack : 1; 3950 uint8_t sh_slave2_nack : 1; 3951 uint8_t sh_slave3_nack : 1; 3952 uint8_t sh_wr_once : 1; 3953 uint8_t fifo_bdr : 1; 3954 uint8_t fifo_full : 1; 3955 uint8_t fifo_ovr : 1; 3956 uint8_t fifo_th : 1; 3957 } lsm6dsv_all_sources_t; 3958 int32_t lsm6dsv_all_sources_get(const stmdev_ctx_t *ctx, 3959 lsm6dsv_all_sources_t *val); 3960 3961 typedef struct 3962 { 3963 uint8_t drdy_xl : 1; 3964 uint8_t drdy_g : 1; 3965 uint8_t drdy_g_eis : 1; 3966 uint8_t drdy_temp : 1; 3967 uint8_t fifo_th : 1; 3968 uint8_t fifo_ovr : 1; 3969 uint8_t fifo_full : 1; 3970 uint8_t cnt_bdr : 1; 3971 uint8_t emb_func_endop : 1; 3972 uint8_t timestamp : 1; 3973 uint8_t shub : 1; 3974 uint8_t emb_func : 1; 3975 uint8_t sixd : 1; 3976 uint8_t single_tap : 1; 3977 uint8_t double_tap : 1; 3978 uint8_t wakeup : 1; 3979 uint8_t freefall : 1; 3980 uint8_t sleep_change : 1; 3981 } lsm6dsv_pin_int_route_t; 3982 int32_t lsm6dsv_pin_int1_route_set(const stmdev_ctx_t *ctx, 3983 lsm6dsv_pin_int_route_t *val); 3984 int32_t lsm6dsv_pin_int1_route_get(const stmdev_ctx_t *ctx, 3985 lsm6dsv_pin_int_route_t *val); 3986 int32_t lsm6dsv_pin_int2_route_set(const stmdev_ctx_t *ctx, 3987 lsm6dsv_pin_int_route_t *val); 3988 int32_t lsm6dsv_pin_int2_route_get(const stmdev_ctx_t *ctx, 3989 lsm6dsv_pin_int_route_t *val); 3990 3991 typedef struct 3992 { 3993 uint8_t step_det : 1; /* route step detection event on INT pad */ 3994 uint8_t tilt : 1; /* route tilt event on INT pad */ 3995 uint8_t sig_mot : 1; /* route significant motion event on INT pad */ 3996 uint8_t fsm_lc : 1; /* route FSM long counter event on INT pad */ 3997 } lsm6dsv_emb_pin_int_route_t; 3998 int32_t lsm6dsv_emb_pin_int1_route_set(const stmdev_ctx_t *ctx, 3999 const lsm6dsv_emb_pin_int_route_t *val); 4000 int32_t lsm6dsv_emb_pin_int1_route_get(const stmdev_ctx_t *ctx, 4001 lsm6dsv_emb_pin_int_route_t *val); 4002 int32_t lsm6dsv_emb_pin_int2_route_set(const stmdev_ctx_t *ctx, 4003 const lsm6dsv_emb_pin_int_route_t *val); 4004 int32_t lsm6dsv_emb_pin_int2_route_get(const stmdev_ctx_t *ctx, 4005 lsm6dsv_emb_pin_int_route_t *val); 4006 4007 typedef enum 4008 { 4009 LSM6DSV_INT_LATCH_DISABLE = 0x0, 4010 LSM6DSV_INT_LATCH_ENABLE = 0x1, 4011 } lsm6dsv_embedded_int_config_t; 4012 int32_t lsm6dsv_embedded_int_cfg_set(const stmdev_ctx_t *ctx, 4013 lsm6dsv_embedded_int_config_t val); 4014 int32_t lsm6dsv_embedded_int_cfg_get(const stmdev_ctx_t *ctx, 4015 lsm6dsv_embedded_int_config_t *val); 4016 4017 typedef struct 4018 { 4019 uint8_t tilt : 1; 4020 uint8_t sig_mot : 1; 4021 uint8_t fsm_lc : 1; 4022 uint8_t step_detector : 1; 4023 uint8_t step_count_inc : 1; 4024 uint8_t step_count_overflow : 1; 4025 uint8_t step_on_delta_time : 1; 4026 } lsm6dsv_embedded_status_t; 4027 int32_t lsm6dsv_embedded_status_get(const stmdev_ctx_t *ctx, 4028 lsm6dsv_embedded_status_t *val); 4029 4030 typedef struct 4031 { 4032 uint8_t drdy_xl : 1; 4033 uint8_t drdy_gy : 1; 4034 uint8_t drdy_temp : 1; 4035 } lsm6dsv_data_ready_t; 4036 int32_t lsm6dsv_flag_data_ready_get(const stmdev_ctx_t *ctx, 4037 lsm6dsv_data_ready_t *val); 4038 4039 int32_t lsm6dsv_int_ack_mask_set(const stmdev_ctx_t *ctx, uint8_t val); 4040 int32_t lsm6dsv_int_ack_mask_get(const stmdev_ctx_t *ctx, uint8_t *val); 4041 4042 int32_t lsm6dsv_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 4043 4044 int32_t lsm6dsv_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 4045 4046 int32_t lsm6dsv_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 4047 4048 int32_t lsm6dsv_ois_eis_angular_rate_raw_get(const stmdev_ctx_t *ctx, 4049 int16_t *val); 4050 4051 int32_t lsm6dsv_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 4052 4053 int32_t lsm6dsv_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 4054 4055 int32_t lsm6dsv_ois_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, 4056 int16_t *val); 4057 4058 int32_t lsm6dsv_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val); 4059 4060 int32_t lsm6dsv_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, 4061 uint8_t *buf, uint8_t len); 4062 int32_t lsm6dsv_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf, 4063 uint8_t len); 4064 4065 int32_t lsm6dsv_emb_function_dbg_set(const stmdev_ctx_t *ctx, uint8_t val); 4066 int32_t lsm6dsv_emb_function_dbg_get(const stmdev_ctx_t *ctx, uint8_t *val); 4067 4068 typedef enum 4069 { 4070 LSM6DSV_DEN_ACT_LOW = 0x0, 4071 LSM6DSV_DEN_ACT_HIGH = 0x1, 4072 } lsm6dsv_den_polarity_t; 4073 int32_t lsm6dsv_den_polarity_set(const stmdev_ctx_t *ctx, 4074 lsm6dsv_den_polarity_t val); 4075 int32_t lsm6dsv_den_polarity_get(const stmdev_ctx_t *ctx, 4076 lsm6dsv_den_polarity_t *val); 4077 4078 typedef struct 4079 { 4080 uint8_t stamp_in_gy_data : 1; 4081 uint8_t stamp_in_xl_data : 1; 4082 uint8_t den_x : 1; 4083 uint8_t den_y : 1; 4084 uint8_t den_z : 1; 4085 enum 4086 { 4087 LSM6DSV_DEN_NOT_DEFINED = 0x00, 4088 LSM6DSV_LEVEL_TRIGGER = 0x02, 4089 LSM6DSV_LEVEL_LATCHED = 0x03, 4090 } mode; 4091 } lsm6dsv_den_conf_t; 4092 int32_t lsm6dsv_den_conf_set(const stmdev_ctx_t *ctx, lsm6dsv_den_conf_t val); 4093 int32_t lsm6dsv_den_conf_get(const stmdev_ctx_t *ctx, lsm6dsv_den_conf_t *val); 4094 4095 typedef enum 4096 { 4097 LSM6DSV_EIS_125dps = 0x0, 4098 LSM6DSV_EIS_250dps = 0x1, 4099 LSM6DSV_EIS_500dps = 0x2, 4100 LSM6DSV_EIS_1000dps = 0x3, 4101 LSM6DSV_EIS_2000dps = 0x4, 4102 } lsm6dsv_eis_gy_full_scale_t; 4103 int32_t lsm6dsv_eis_gy_full_scale_set(const stmdev_ctx_t *ctx, 4104 lsm6dsv_eis_gy_full_scale_t val); 4105 int32_t lsm6dsv_eis_gy_full_scale_get(const stmdev_ctx_t *ctx, 4106 lsm6dsv_eis_gy_full_scale_t *val); 4107 4108 int32_t lsm6dsv_eis_gy_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val); 4109 int32_t lsm6dsv_eis_gy_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val); 4110 4111 typedef enum 4112 { 4113 LSM6DSV_EIS_ODR_OFF = 0x0, 4114 LSM6DSV_EIS_1920Hz = 0x1, 4115 LSM6DSV_EIS_960Hz = 0x2, 4116 } lsm6dsv_gy_eis_data_rate_t; 4117 int32_t lsm6dsv_gy_eis_data_rate_set(const stmdev_ctx_t *ctx, 4118 lsm6dsv_gy_eis_data_rate_t val); 4119 int32_t lsm6dsv_gy_eis_data_rate_get(const stmdev_ctx_t *ctx, 4120 lsm6dsv_gy_eis_data_rate_t *val); 4121 4122 int32_t lsm6dsv_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 4123 int32_t lsm6dsv_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 4124 4125 int32_t lsm6dsv_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val); 4126 int32_t lsm6dsv_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); 4127 4128 typedef enum 4129 { 4130 LSM6DSV_CMP_DISABLE = 0x0, 4131 LSM6DSV_CMP_8_TO_1 = 0x1, 4132 LSM6DSV_CMP_16_TO_1 = 0x2, 4133 LSM6DSV_CMP_32_TO_1 = 0x3, 4134 } lsm6dsv_fifo_compress_algo_t; 4135 int32_t lsm6dsv_fifo_compress_algo_set(const stmdev_ctx_t *ctx, 4136 lsm6dsv_fifo_compress_algo_t val); 4137 int32_t lsm6dsv_fifo_compress_algo_get(const stmdev_ctx_t *ctx, 4138 lsm6dsv_fifo_compress_algo_t *val); 4139 4140 int32_t lsm6dsv_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, 4141 uint8_t val); 4142 int32_t lsm6dsv_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, 4143 uint8_t *val); 4144 4145 int32_t lsm6dsv_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, 4146 uint8_t val); 4147 int32_t lsm6dsv_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, 4148 uint8_t *val); 4149 4150 int32_t lsm6dsv_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); 4151 int32_t lsm6dsv_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); 4152 4153 typedef enum 4154 { 4155 LSM6DSV_XL_NOT_BATCHED = 0x0, 4156 LSM6DSV_XL_BATCHED_AT_1Hz875 = 0x1, 4157 LSM6DSV_XL_BATCHED_AT_7Hz5 = 0x2, 4158 LSM6DSV_XL_BATCHED_AT_15Hz = 0x3, 4159 LSM6DSV_XL_BATCHED_AT_30Hz = 0x4, 4160 LSM6DSV_XL_BATCHED_AT_60Hz = 0x5, 4161 LSM6DSV_XL_BATCHED_AT_120Hz = 0x6, 4162 LSM6DSV_XL_BATCHED_AT_240Hz = 0x7, 4163 LSM6DSV_XL_BATCHED_AT_480Hz = 0x8, 4164 LSM6DSV_XL_BATCHED_AT_960Hz = 0x9, 4165 LSM6DSV_XL_BATCHED_AT_1920Hz = 0xa, 4166 LSM6DSV_XL_BATCHED_AT_3840Hz = 0xb, 4167 LSM6DSV_XL_BATCHED_AT_7680Hz = 0xc, 4168 } lsm6dsv_fifo_xl_batch_t; 4169 int32_t lsm6dsv_fifo_xl_batch_set(const stmdev_ctx_t *ctx, 4170 lsm6dsv_fifo_xl_batch_t val); 4171 int32_t lsm6dsv_fifo_xl_batch_get(const stmdev_ctx_t *ctx, 4172 lsm6dsv_fifo_xl_batch_t *val); 4173 4174 typedef enum 4175 { 4176 LSM6DSV_GY_NOT_BATCHED = 0x0, 4177 LSM6DSV_GY_BATCHED_AT_1Hz875 = 0x1, 4178 LSM6DSV_GY_BATCHED_AT_7Hz5 = 0x2, 4179 LSM6DSV_GY_BATCHED_AT_15Hz = 0x3, 4180 LSM6DSV_GY_BATCHED_AT_30Hz = 0x4, 4181 LSM6DSV_GY_BATCHED_AT_60Hz = 0x5, 4182 LSM6DSV_GY_BATCHED_AT_120Hz = 0x6, 4183 LSM6DSV_GY_BATCHED_AT_240Hz = 0x7, 4184 LSM6DSV_GY_BATCHED_AT_480Hz = 0x8, 4185 LSM6DSV_GY_BATCHED_AT_960Hz = 0x9, 4186 LSM6DSV_GY_BATCHED_AT_1920Hz = 0xa, 4187 LSM6DSV_GY_BATCHED_AT_3840Hz = 0xb, 4188 LSM6DSV_GY_BATCHED_AT_7680Hz = 0xc, 4189 } lsm6dsv_fifo_gy_batch_t; 4190 int32_t lsm6dsv_fifo_gy_batch_set(const stmdev_ctx_t *ctx, 4191 lsm6dsv_fifo_gy_batch_t val); 4192 int32_t lsm6dsv_fifo_gy_batch_get(const stmdev_ctx_t *ctx, 4193 lsm6dsv_fifo_gy_batch_t *val); 4194 4195 typedef enum 4196 { 4197 LSM6DSV_BYPASS_MODE = 0x0, 4198 LSM6DSV_FIFO_MODE = 0x1, 4199 LSM6DSV_STREAM_WTM_TO_FULL_MODE = 0x2, 4200 LSM6DSV_STREAM_TO_FIFO_MODE = 0x3, 4201 LSM6DSV_BYPASS_TO_STREAM_MODE = 0x4, 4202 LSM6DSV_STREAM_MODE = 0x6, 4203 LSM6DSV_BYPASS_TO_FIFO_MODE = 0x7, 4204 } lsm6dsv_fifo_mode_t; 4205 int32_t lsm6dsv_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_fifo_mode_t val); 4206 int32_t lsm6dsv_fifo_mode_get(const stmdev_ctx_t *ctx, 4207 lsm6dsv_fifo_mode_t *val); 4208 4209 int32_t lsm6dsv_fifo_gy_eis_batch_set(const stmdev_ctx_t *ctx, uint8_t val); 4210 int32_t lsm6dsv_fifo_gy_eis_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); 4211 4212 typedef enum 4213 { 4214 LSM6DSV_TEMP_NOT_BATCHED = 0x0, 4215 LSM6DSV_TEMP_BATCHED_AT_1Hz875 = 0x1, 4216 LSM6DSV_TEMP_BATCHED_AT_15Hz = 0x2, 4217 LSM6DSV_TEMP_BATCHED_AT_60Hz = 0x3, 4218 } lsm6dsv_fifo_temp_batch_t; 4219 int32_t lsm6dsv_fifo_temp_batch_set(const stmdev_ctx_t *ctx, 4220 lsm6dsv_fifo_temp_batch_t val); 4221 int32_t lsm6dsv_fifo_temp_batch_get(const stmdev_ctx_t *ctx, 4222 lsm6dsv_fifo_temp_batch_t *val); 4223 4224 typedef enum 4225 { 4226 LSM6DSV_TMSTMP_NOT_BATCHED = 0x0, 4227 LSM6DSV_TMSTMP_DEC_1 = 0x1, 4228 LSM6DSV_TMSTMP_DEC_8 = 0x2, 4229 LSM6DSV_TMSTMP_DEC_32 = 0x3, 4230 } lsm6dsv_fifo_timestamp_batch_t; 4231 int32_t lsm6dsv_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, 4232 lsm6dsv_fifo_timestamp_batch_t val); 4233 int32_t lsm6dsv_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, 4234 lsm6dsv_fifo_timestamp_batch_t *val); 4235 4236 int32_t lsm6dsv_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, 4237 uint16_t val); 4238 int32_t lsm6dsv_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, 4239 uint16_t *val); 4240 4241 typedef enum 4242 { 4243 LSM6DSV_XL_BATCH_EVENT = 0x0, 4244 LSM6DSV_GY_BATCH_EVENT = 0x1, 4245 LSM6DSV_GY_EIS_BATCH_EVENT = 0x2, 4246 } lsm6dsv_fifo_batch_cnt_event_t; 4247 int32_t lsm6dsv_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx, 4248 lsm6dsv_fifo_batch_cnt_event_t val); 4249 int32_t lsm6dsv_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, 4250 lsm6dsv_fifo_batch_cnt_event_t *val); 4251 4252 typedef struct 4253 { 4254 uint16_t fifo_level : 9; 4255 uint8_t fifo_bdr : 1; 4256 uint8_t fifo_full : 1; 4257 uint8_t fifo_ovr : 1; 4258 uint8_t fifo_th : 1; 4259 } lsm6dsv_fifo_status_t; 4260 4261 int32_t lsm6dsv_fifo_status_get(const stmdev_ctx_t *ctx, 4262 lsm6dsv_fifo_status_t *val); 4263 4264 /* Accel data format in FIFO */ 4265 typedef struct 4266 { 4267 int16_t axis[3]; 4268 } lsm6dsv_fifo_xl; 4269 4270 /* Temperature data format in FIFO */ 4271 typedef struct 4272 { 4273 uint16_t temperature; 4274 } lsm6dsv_fifo_temperature; 4275 4276 /* Timestamp format in FIFO */ 4277 typedef struct 4278 { 4279 uint32_t timestamp; 4280 } lsm6dsv_fifo_timestamp; 4281 4282 /* Step counter data format in FIFO */ 4283 typedef struct 4284 { 4285 uint16_t steps; 4286 uint32_t timestamp; 4287 } lsm6dsv_fifo_step_counter; 4288 4289 typedef enum 4290 { 4291 LSM6DSV_FIFO_EMPTY = 0x0, 4292 LSM6DSV_GY_NC_TAG = 0x1, 4293 LSM6DSV_XL_NC_TAG = 0x2, 4294 LSM6DSV_TEMPERATURE_TAG = 0x3, 4295 LSM6DSV_TIMESTAMP_TAG = 0x4, 4296 LSM6DSV_CFG_CHANGE_TAG = 0x5, 4297 LSM6DSV_XL_NC_T_2_TAG = 0x6, 4298 LSM6DSV_XL_NC_T_1_TAG = 0x7, 4299 LSM6DSV_XL_2XC_TAG = 0x8, 4300 LSM6DSV_XL_3XC_TAG = 0x9, 4301 LSM6DSV_GY_NC_T_2_TAG = 0xA, 4302 LSM6DSV_GY_NC_T_1_TAG = 0xB, 4303 LSM6DSV_GY_2XC_TAG = 0xC, 4304 LSM6DSV_GY_3XC_TAG = 0xD, 4305 LSM6DSV_SENSORHUB_SLAVE0_TAG = 0xE, 4306 LSM6DSV_SENSORHUB_SLAVE1_TAG = 0xF, 4307 LSM6DSV_SENSORHUB_SLAVE2_TAG = 0x10, 4308 LSM6DSV_SENSORHUB_SLAVE3_TAG = 0x11, 4309 LSM6DSV_STEP_COUNTER_TAG = 0x12, 4310 LSM6DSV_SFLP_GAME_ROTATION_VECTOR_TAG = 0x13, 4311 LSM6DSV_SFLP_GYROSCOPE_BIAS_TAG = 0x16, 4312 LSM6DSV_SFLP_GRAVITY_VECTOR_TAG = 0x17, 4313 LSM6DSV_SENSORHUB_NACK_TAG = 0x19, 4314 LSM6DSV_XL_DUAL_CORE = 0x1D, 4315 LSM6DSV_GY_ENHANCED_EIS = 0x1E, 4316 } lsm6dsv_fifo_tag; 4317 4318 typedef struct 4319 { 4320 uint8_t tag : 5; 4321 uint8_t cnt : 2; 4322 uint8_t rsvd : 1; 4323 uint8_t data[6]; 4324 } lsm6dsv_fifo_out_raw_t; 4325 int32_t lsm6dsv_fifo_out_raw_get(const stmdev_ctx_t *ctx, 4326 lsm6dsv_fifo_out_raw_t *val); 4327 4328 int32_t lsm6dsv_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val); 4329 int32_t lsm6dsv_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); 4330 4331 int32_t lsm6dsv_fifo_sh_batch_slave_set(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t val); 4332 int32_t lsm6dsv_fifo_sh_batch_slave_get(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val); 4333 4334 typedef struct 4335 { 4336 uint8_t game_rotation : 1; 4337 uint8_t gravity : 1; 4338 uint8_t gbias : 1; 4339 } lsm6dsv_fifo_sflp_raw_t; 4340 int32_t lsm6dsv_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, 4341 lsm6dsv_fifo_sflp_raw_t val); 4342 int32_t lsm6dsv_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, 4343 lsm6dsv_fifo_sflp_raw_t *val); 4344 4345 typedef enum 4346 { 4347 LSM6DSV_AUTO = 0x0, 4348 LSM6DSV_ALWAYS_ACTIVE = 0x1, 4349 } lsm6dsv_filt_anti_spike_t; 4350 int32_t lsm6dsv_filt_anti_spike_set(const stmdev_ctx_t *ctx, 4351 lsm6dsv_filt_anti_spike_t val); 4352 int32_t lsm6dsv_filt_anti_spike_get(const stmdev_ctx_t *ctx, 4353 lsm6dsv_filt_anti_spike_t *val); 4354 4355 typedef struct 4356 { 4357 uint8_t drdy : 1; 4358 uint8_t ois_drdy : 1; 4359 uint8_t irq_xl : 1; 4360 uint8_t irq_g : 1; 4361 } lsm6dsv_filt_settling_mask_t; 4362 int32_t lsm6dsv_filt_settling_mask_set(const stmdev_ctx_t *ctx, 4363 lsm6dsv_filt_settling_mask_t val); 4364 int32_t lsm6dsv_filt_settling_mask_get(const stmdev_ctx_t *ctx, 4365 lsm6dsv_filt_settling_mask_t *val); 4366 4367 typedef struct 4368 { 4369 uint8_t ois_drdy : 1; 4370 } lsm6dsv_filt_ois_settling_mask_t; 4371 int32_t lsm6dsv_filt_ois_settling_mask_set(const stmdev_ctx_t *ctx, 4372 lsm6dsv_filt_ois_settling_mask_t val); 4373 int32_t lsm6dsv_filt_ois_settling_mask_get(const stmdev_ctx_t *ctx, 4374 lsm6dsv_filt_ois_settling_mask_t *val); 4375 4376 typedef enum 4377 { 4378 LSM6DSV_GY_ULTRA_LIGHT = 0x0, 4379 LSM6DSV_GY_VERY_LIGHT = 0x1, 4380 LSM6DSV_GY_LIGHT = 0x2, 4381 LSM6DSV_GY_MEDIUM = 0x3, 4382 LSM6DSV_GY_STRONG = 0x4, 4383 LSM6DSV_GY_VERY_STRONG = 0x5, 4384 LSM6DSV_GY_AGGRESSIVE = 0x6, 4385 LSM6DSV_GY_XTREME = 0x7, 4386 } lsm6dsv_filt_gy_lp1_bandwidth_t; 4387 int32_t lsm6dsv_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 4388 lsm6dsv_filt_gy_lp1_bandwidth_t val); 4389 int32_t lsm6dsv_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 4390 lsm6dsv_filt_gy_lp1_bandwidth_t *val); 4391 4392 int32_t lsm6dsv_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); 4393 int32_t lsm6dsv_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); 4394 4395 typedef enum 4396 { 4397 LSM6DSV_XL_ULTRA_LIGHT = 0x0, 4398 LSM6DSV_XL_VERY_LIGHT = 0x1, 4399 LSM6DSV_XL_LIGHT = 0x2, 4400 LSM6DSV_XL_MEDIUM = 0x3, 4401 LSM6DSV_XL_STRONG = 0x4, 4402 LSM6DSV_XL_VERY_STRONG = 0x5, 4403 LSM6DSV_XL_AGGRESSIVE = 0x6, 4404 LSM6DSV_XL_XTREME = 0x7, 4405 } lsm6dsv_filt_xl_lp2_bandwidth_t; 4406 int32_t lsm6dsv_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, 4407 lsm6dsv_filt_xl_lp2_bandwidth_t val); 4408 int32_t lsm6dsv_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, 4409 lsm6dsv_filt_xl_lp2_bandwidth_t *val); 4410 4411 int32_t lsm6dsv_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); 4412 int32_t lsm6dsv_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); 4413 4414 int32_t lsm6dsv_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val); 4415 int32_t lsm6dsv_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val); 4416 4417 int32_t lsm6dsv_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); 4418 int32_t lsm6dsv_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); 4419 4420 typedef enum 4421 { 4422 LSM6DSV_HP_MD_NORMAL = 0x0, 4423 LSM6DSV_HP_MD_REFERENCE = 0x1, 4424 } lsm6dsv_filt_xl_hp_mode_t; 4425 int32_t lsm6dsv_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx, 4426 lsm6dsv_filt_xl_hp_mode_t val); 4427 int32_t lsm6dsv_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, 4428 lsm6dsv_filt_xl_hp_mode_t *val); 4429 4430 typedef enum 4431 { 4432 LSM6DSV_WK_FEED_SLOPE = 0x0, 4433 LSM6DSV_WK_FEED_HIGH_PASS = 0x1, 4434 LSM6DSV_WK_FEED_LP_WITH_OFFSET = 0x2, 4435 } lsm6dsv_filt_wkup_act_feed_t; 4436 int32_t lsm6dsv_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, 4437 lsm6dsv_filt_wkup_act_feed_t val); 4438 int32_t lsm6dsv_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, 4439 lsm6dsv_filt_wkup_act_feed_t *val); 4440 4441 int32_t lsm6dsv_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val); 4442 int32_t lsm6dsv_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val); 4443 4444 typedef enum 4445 { 4446 LSM6DSV_SIXD_FEED_ODR_DIV_2 = 0x0, 4447 LSM6DSV_SIXD_FEED_LOW_PASS = 0x1, 4448 } lsm6dsv_filt_sixd_feed_t; 4449 int32_t lsm6dsv_filt_sixd_feed_set(const stmdev_ctx_t *ctx, 4450 lsm6dsv_filt_sixd_feed_t val); 4451 int32_t lsm6dsv_filt_sixd_feed_get(const stmdev_ctx_t *ctx, 4452 lsm6dsv_filt_sixd_feed_t *val); 4453 4454 typedef enum 4455 { 4456 LSM6DSV_EIS_LP_NORMAL = 0x0, 4457 LSM6DSV_EIS_LP_LIGHT = 0x1, 4458 } lsm6dsv_filt_gy_eis_lp_bandwidth_t; 4459 int32_t lsm6dsv_filt_gy_eis_lp_bandwidth_set(const stmdev_ctx_t *ctx, 4460 lsm6dsv_filt_gy_eis_lp_bandwidth_t val); 4461 int32_t lsm6dsv_filt_gy_eis_lp_bandwidth_get(const stmdev_ctx_t *ctx, 4462 lsm6dsv_filt_gy_eis_lp_bandwidth_t *val); 4463 4464 typedef enum 4465 { 4466 LSM6DSV_OIS_GY_LP_NORMAL = 0x0, 4467 LSM6DSV_OIS_GY_LP_STRONG = 0x1, 4468 LSM6DSV_OIS_GY_LP_AGGRESSIVE = 0x2, 4469 LSM6DSV_OIS_GY_LP_LIGHT = 0x3, 4470 } lsm6dsv_filt_gy_ois_lp_bandwidth_t; 4471 int32_t lsm6dsv_filt_gy_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx, 4472 lsm6dsv_filt_gy_ois_lp_bandwidth_t val); 4473 int32_t lsm6dsv_filt_gy_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx, 4474 lsm6dsv_filt_gy_ois_lp_bandwidth_t *val); 4475 4476 typedef enum 4477 { 4478 LSM6DSV_OIS_XL_LP_ULTRA_LIGHT = 0x0, 4479 LSM6DSV_OIS_XL_LP_VERY_LIGHT = 0x1, 4480 LSM6DSV_OIS_XL_LP_LIGHT = 0x2, 4481 LSM6DSV_OIS_XL_LP_NORMAL = 0x3, 4482 LSM6DSV_OIS_XL_LP_STRONG = 0x4, 4483 LSM6DSV_OIS_XL_LP_VERY_STRONG = 0x5, 4484 LSM6DSV_OIS_XL_LP_AGGRESSIVE = 0x6, 4485 LSM6DSV_OIS_XL_LP_XTREME = 0x7, 4486 } lsm6dsv_filt_xl_ois_lp_bandwidth_t; 4487 int32_t lsm6dsv_filt_xl_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx, 4488 lsm6dsv_filt_xl_ois_lp_bandwidth_t val); 4489 int32_t lsm6dsv_filt_xl_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx, 4490 lsm6dsv_filt_xl_ois_lp_bandwidth_t *val); 4491 4492 typedef enum 4493 { 4494 LSM6DSV_PROTECT_CTRL_REGS = 0x0, 4495 LSM6DSV_WRITE_CTRL_REG = 0x1, 4496 } lsm6dsv_fsm_permission_t; 4497 int32_t lsm6dsv_fsm_permission_set(const stmdev_ctx_t *ctx, 4498 lsm6dsv_fsm_permission_t val); 4499 int32_t lsm6dsv_fsm_permission_get(const stmdev_ctx_t *ctx, 4500 lsm6dsv_fsm_permission_t *val); 4501 int32_t lsm6dsv_fsm_permission_status(const stmdev_ctx_t *ctx, uint8_t *val); 4502 4503 typedef struct 4504 { 4505 uint8_t fsm1_en : 1; 4506 uint8_t fsm2_en : 1; 4507 uint8_t fsm3_en : 1; 4508 uint8_t fsm4_en : 1; 4509 uint8_t fsm5_en : 1; 4510 uint8_t fsm6_en : 1; 4511 uint8_t fsm7_en : 1; 4512 uint8_t fsm8_en : 1; 4513 } lsm6dsv_fsm_mode_t; 4514 int32_t lsm6dsv_fsm_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_fsm_mode_t val); 4515 int32_t lsm6dsv_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_mode_t *val); 4516 4517 int32_t lsm6dsv_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); 4518 int32_t lsm6dsv_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); 4519 4520 4521 typedef struct 4522 { 4523 uint8_t fsm_outs1; 4524 uint8_t fsm_outs2; 4525 uint8_t fsm_outs3; 4526 uint8_t fsm_outs4; 4527 uint8_t fsm_outs5; 4528 uint8_t fsm_outs6; 4529 uint8_t fsm_outs7; 4530 uint8_t fsm_outs8; 4531 } lsm6dsv_fsm_out_t; 4532 int32_t lsm6dsv_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv_fsm_out_t *val); 4533 4534 typedef enum 4535 { 4536 LSM6DSV_FSM_15Hz = 0x0, 4537 LSM6DSV_FSM_30Hz = 0x1, 4538 LSM6DSV_FSM_60Hz = 0x2, 4539 LSM6DSV_FSM_120Hz = 0x3, 4540 LSM6DSV_FSM_240Hz = 0x4, 4541 LSM6DSV_FSM_480Hz = 0x5, 4542 LSM6DSV_FSM_960Hz = 0x6, 4543 } lsm6dsv_fsm_data_rate_t; 4544 int32_t lsm6dsv_fsm_data_rate_set(const stmdev_ctx_t *ctx, 4545 lsm6dsv_fsm_data_rate_t val); 4546 int32_t lsm6dsv_fsm_data_rate_get(const stmdev_ctx_t *ctx, 4547 lsm6dsv_fsm_data_rate_t *val); 4548 4549 int32_t lsm6dsv_fsm_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, 4550 uint16_t val); 4551 int32_t lsm6dsv_fsm_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx, 4552 uint16_t *val); 4553 4554 typedef struct 4555 { 4556 uint16_t z; 4557 uint16_t y; 4558 uint16_t x; 4559 } lsm6dsv_xl_fsm_ext_sens_offset_t; 4560 int32_t lsm6dsv_fsm_ext_sens_offset_set(const stmdev_ctx_t *ctx, 4561 lsm6dsv_xl_fsm_ext_sens_offset_t val); 4562 int32_t lsm6dsv_fsm_ext_sens_offset_get(const stmdev_ctx_t *ctx, 4563 lsm6dsv_xl_fsm_ext_sens_offset_t *val); 4564 4565 typedef struct 4566 { 4567 uint16_t xx; 4568 uint16_t xy; 4569 uint16_t xz; 4570 uint16_t yy; 4571 uint16_t yz; 4572 uint16_t zz; 4573 } lsm6dsv_xl_fsm_ext_sens_matrix_t; 4574 int32_t lsm6dsv_fsm_ext_sens_matrix_set(const stmdev_ctx_t *ctx, 4575 lsm6dsv_xl_fsm_ext_sens_matrix_t val); 4576 int32_t lsm6dsv_fsm_ext_sens_matrix_get(const stmdev_ctx_t *ctx, 4577 lsm6dsv_xl_fsm_ext_sens_matrix_t *val); 4578 4579 typedef enum 4580 { 4581 LSM6DSV_Z_EQ_Y = 0x0, 4582 LSM6DSV_Z_EQ_MIN_Y = 0x1, 4583 LSM6DSV_Z_EQ_X = 0x2, 4584 LSM6DSV_Z_EQ_MIN_X = 0x3, 4585 LSM6DSV_Z_EQ_MIN_Z = 0x4, 4586 LSM6DSV_Z_EQ_Z = 0x5, 4587 } lsm6dsv_fsm_ext_sens_z_orient_t; 4588 int32_t lsm6dsv_fsm_ext_sens_z_orient_set(const stmdev_ctx_t *ctx, 4589 lsm6dsv_fsm_ext_sens_z_orient_t val); 4590 int32_t lsm6dsv_fsm_ext_sens_z_orient_get(const stmdev_ctx_t *ctx, 4591 lsm6dsv_fsm_ext_sens_z_orient_t *val); 4592 4593 typedef enum 4594 { 4595 LSM6DSV_Y_EQ_Y = 0x0, 4596 LSM6DSV_Y_EQ_MIN_Y = 0x1, 4597 LSM6DSV_Y_EQ_X = 0x2, 4598 LSM6DSV_Y_EQ_MIN_X = 0x3, 4599 LSM6DSV_Y_EQ_MIN_Z = 0x4, 4600 LSM6DSV_Y_EQ_Z = 0x5, 4601 } lsm6dsv_fsm_ext_sens_y_orient_t; 4602 int32_t lsm6dsv_fsm_ext_sens_y_orient_set(const stmdev_ctx_t *ctx, 4603 lsm6dsv_fsm_ext_sens_y_orient_t val); 4604 int32_t lsm6dsv_fsm_ext_sens_y_orient_get(const stmdev_ctx_t *ctx, 4605 lsm6dsv_fsm_ext_sens_y_orient_t *val); 4606 4607 typedef enum 4608 { 4609 LSM6DSV_X_EQ_Y = 0x0, 4610 LSM6DSV_X_EQ_MIN_Y = 0x1, 4611 LSM6DSV_X_EQ_X = 0x2, 4612 LSM6DSV_X_EQ_MIN_X = 0x3, 4613 LSM6DSV_X_EQ_MIN_Z = 0x4, 4614 LSM6DSV_X_EQ_Z = 0x5, 4615 } lsm6dsv_fsm_ext_sens_x_orient_t; 4616 int32_t lsm6dsv_fsm_ext_sens_x_orient_set(const stmdev_ctx_t *ctx, 4617 lsm6dsv_fsm_ext_sens_x_orient_t val); 4618 int32_t lsm6dsv_fsm_ext_sens_x_orient_get(const stmdev_ctx_t *ctx, 4619 lsm6dsv_fsm_ext_sens_x_orient_t *val); 4620 4621 int32_t lsm6dsv_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val); 4622 int32_t lsm6dsv_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val); 4623 4624 int32_t lsm6dsv_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val); 4625 int32_t lsm6dsv_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val); 4626 4627 int32_t lsm6dsv_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); 4628 int32_t lsm6dsv_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); 4629 4630 int32_t lsm6dsv_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val); 4631 int32_t lsm6dsv_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val); 4632 4633 typedef enum 4634 { 4635 LSM6DSV_156_mg = 0x0, 4636 LSM6DSV_219_mg = 0x1, 4637 LSM6DSV_250_mg = 0x2, 4638 LSM6DSV_312_mg = 0x3, 4639 LSM6DSV_344_mg = 0x4, 4640 LSM6DSV_406_mg = 0x5, 4641 LSM6DSV_469_mg = 0x6, 4642 LSM6DSV_500_mg = 0x7, 4643 } lsm6dsv_ff_thresholds_t; 4644 int32_t lsm6dsv_ff_thresholds_set(const stmdev_ctx_t *ctx, 4645 lsm6dsv_ff_thresholds_t val); 4646 int32_t lsm6dsv_ff_thresholds_get(const stmdev_ctx_t *ctx, 4647 lsm6dsv_ff_thresholds_t *val); 4648 4649 typedef enum 4650 { 4651 LSM6DSV_OIS_CTRL_FROM_OIS = 0x0, 4652 LSM6DSV_OIS_CTRL_FROM_UI = 0x1, 4653 } lsm6dsv_ois_ctrl_mode_t; 4654 int32_t lsm6dsv_ois_ctrl_mode_set(const stmdev_ctx_t *ctx, 4655 lsm6dsv_ois_ctrl_mode_t val); 4656 int32_t lsm6dsv_ois_ctrl_mode_get(const stmdev_ctx_t *ctx, 4657 lsm6dsv_ois_ctrl_mode_t *val); 4658 4659 int32_t lsm6dsv_ois_reset_set(const stmdev_ctx_t *ctx, int8_t val); 4660 int32_t lsm6dsv_ois_reset_get(const stmdev_ctx_t *ctx, int8_t *val); 4661 4662 int32_t lsm6dsv_ois_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); 4663 int32_t lsm6dsv_ois_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); 4664 4665 typedef struct 4666 { 4667 uint8_t ack : 1; 4668 uint8_t req : 1; 4669 } lsm6dsv_ois_handshake_t; 4670 int32_t lsm6dsv_ois_handshake_from_ui_set(const stmdev_ctx_t *ctx, 4671 lsm6dsv_ois_handshake_t val); 4672 int32_t lsm6dsv_ois_handshake_from_ui_get(const stmdev_ctx_t *ctx, 4673 lsm6dsv_ois_handshake_t *val); 4674 int32_t lsm6dsv_ois_handshake_from_ois_set(const stmdev_ctx_t *ctx, 4675 lsm6dsv_ois_handshake_t val); 4676 int32_t lsm6dsv_ois_handshake_from_ois_get(const stmdev_ctx_t *ctx, 4677 lsm6dsv_ois_handshake_t *val); 4678 4679 int32_t lsm6dsv_ois_shared_set(const stmdev_ctx_t *ctx, uint8_t val[6]); 4680 int32_t lsm6dsv_ois_shared_get(const stmdev_ctx_t *ctx, uint8_t val[6]); 4681 4682 int32_t lsm6dsv_ois_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val); 4683 int32_t lsm6dsv_ois_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val); 4684 4685 typedef struct 4686 { 4687 uint8_t gy : 1; 4688 uint8_t xl : 1; 4689 } lsm6dsv_ois_chain_t; 4690 int32_t lsm6dsv_ois_chain_set(const stmdev_ctx_t *ctx, lsm6dsv_ois_chain_t val); 4691 int32_t lsm6dsv_ois_chain_get(const stmdev_ctx_t *ctx, 4692 lsm6dsv_ois_chain_t *val); 4693 4694 typedef enum 4695 { 4696 LSM6DSV_OIS_125dps = 0x0, 4697 LSM6DSV_OIS_250dps = 0x1, 4698 LSM6DSV_OIS_500dps = 0x2, 4699 LSM6DSV_OIS_1000dps = 0x3, 4700 LSM6DSV_OIS_2000dps = 0x4, 4701 } lsm6dsv_ois_gy_full_scale_t; 4702 int32_t lsm6dsv_ois_gy_full_scale_set(const stmdev_ctx_t *ctx, 4703 lsm6dsv_ois_gy_full_scale_t val); 4704 int32_t lsm6dsv_ois_gy_full_scale_get(const stmdev_ctx_t *ctx, 4705 lsm6dsv_ois_gy_full_scale_t *val); 4706 4707 typedef enum 4708 { 4709 LSM6DSV_OIS_2g = 0x0, 4710 LSM6DSV_OIS_4g = 0x1, 4711 LSM6DSV_OIS_8g = 0x2, 4712 LSM6DSV_OIS_16g = 0x3, 4713 } lsm6dsv_ois_xl_full_scale_t; 4714 int32_t lsm6dsv_ois_xl_full_scale_set(const stmdev_ctx_t *ctx, 4715 lsm6dsv_ois_xl_full_scale_t val); 4716 int32_t lsm6dsv_ois_xl_full_scale_get(const stmdev_ctx_t *ctx, 4717 lsm6dsv_ois_xl_full_scale_t *val); 4718 4719 typedef enum 4720 { 4721 LSM6DSV_DEG_80 = 0x0, 4722 LSM6DSV_DEG_70 = 0x1, 4723 LSM6DSV_DEG_60 = 0x2, 4724 LSM6DSV_DEG_50 = 0x3, 4725 } lsm6dsv_6d_threshold_t; 4726 int32_t lsm6dsv_6d_threshold_set(const stmdev_ctx_t *ctx, 4727 lsm6dsv_6d_threshold_t val); 4728 int32_t lsm6dsv_6d_threshold_get(const stmdev_ctx_t *ctx, 4729 lsm6dsv_6d_threshold_t *val); 4730 4731 int32_t lsm6dsv_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 4732 int32_t lsm6dsv_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 4733 4734 typedef enum 4735 { 4736 LSM6DSV_SW_RST_DYN_ADDRESS_RST = 0x0, 4737 LSM6DSV_I3C_GLOBAL_RST = 0x1, 4738 } lsm6dsv_i3c_reset_mode_t; 4739 int32_t lsm6dsv_i3c_reset_mode_set(const stmdev_ctx_t *ctx, 4740 lsm6dsv_i3c_reset_mode_t val); 4741 int32_t lsm6dsv_i3c_reset_mode_get(const stmdev_ctx_t *ctx, 4742 lsm6dsv_i3c_reset_mode_t *val); 4743 4744 int32_t lsm6dsv_i3c_int_en_set(const stmdev_ctx_t *ctx, uint8_t val); 4745 int32_t lsm6dsv_i3c_int_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 4746 4747 typedef enum 4748 { 4749 LSM6DSV_IBI_2us = 0x0, 4750 LSM6DSV_IBI_50us = 0x1, 4751 LSM6DSV_IBI_1ms = 0x2, 4752 LSM6DSV_IBI_25ms = 0x3, 4753 } lsm6dsv_i3c_ibi_time_t; 4754 int32_t lsm6dsv_i3c_ibi_time_set(const stmdev_ctx_t *ctx, 4755 lsm6dsv_i3c_ibi_time_t val); 4756 int32_t lsm6dsv_i3c_ibi_time_get(const stmdev_ctx_t *ctx, 4757 lsm6dsv_i3c_ibi_time_t *val); 4758 4759 int32_t lsm6dsv_sh_master_interface_pull_up_set(const stmdev_ctx_t *ctx, 4760 uint8_t val); 4761 int32_t lsm6dsv_sh_master_interface_pull_up_get(const stmdev_ctx_t *ctx, 4762 uint8_t *val); 4763 4764 int32_t lsm6dsv_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val, 4765 uint8_t len); 4766 4767 typedef enum 4768 { 4769 LSM6DSV_SLV_0 = 0x0, 4770 LSM6DSV_SLV_0_1 = 0x1, 4771 LSM6DSV_SLV_0_1_2 = 0x2, 4772 LSM6DSV_SLV_0_1_2_3 = 0x3, 4773 } lsm6dsv_sh_slave_connected_t; 4774 int32_t lsm6dsv_sh_slave_connected_set(const stmdev_ctx_t *ctx, 4775 lsm6dsv_sh_slave_connected_t val); 4776 int32_t lsm6dsv_sh_slave_connected_get(const stmdev_ctx_t *ctx, 4777 lsm6dsv_sh_slave_connected_t *val); 4778 4779 int32_t lsm6dsv_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val); 4780 int32_t lsm6dsv_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val); 4781 4782 int32_t lsm6dsv_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val); 4783 int32_t lsm6dsv_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val); 4784 4785 typedef enum 4786 { 4787 LSM6DSV_SH_TRG_XL_GY_DRDY = 0x0, 4788 LSM6DSV_SH_TRIG_INT2 = 0x1, 4789 } lsm6dsv_sh_syncro_mode_t; 4790 int32_t lsm6dsv_sh_syncro_mode_set(const stmdev_ctx_t *ctx, 4791 lsm6dsv_sh_syncro_mode_t val); 4792 int32_t lsm6dsv_sh_syncro_mode_get(const stmdev_ctx_t *ctx, 4793 lsm6dsv_sh_syncro_mode_t *val); 4794 4795 typedef enum 4796 { 4797 LSM6DSV_EACH_SH_CYCLE = 0x0, 4798 LSM6DSV_ONLY_FIRST_CYCLE = 0x1, 4799 } lsm6dsv_sh_write_mode_t; 4800 int32_t lsm6dsv_sh_write_mode_set(const stmdev_ctx_t *ctx, 4801 lsm6dsv_sh_write_mode_t val); 4802 int32_t lsm6dsv_sh_write_mode_get(const stmdev_ctx_t *ctx, 4803 lsm6dsv_sh_write_mode_t *val); 4804 4805 int32_t lsm6dsv_sh_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 4806 int32_t lsm6dsv_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 4807 4808 typedef struct 4809 { 4810 uint8_t slv0_add; 4811 uint8_t slv0_subadd; 4812 uint8_t slv0_data; 4813 } lsm6dsv_sh_cfg_write_t; 4814 int32_t lsm6dsv_sh_cfg_write(const stmdev_ctx_t *ctx, 4815 lsm6dsv_sh_cfg_write_t *val); 4816 typedef enum 4817 { 4818 LSM6DSV_SH_15Hz = 0x1, 4819 LSM6DSV_SH_30Hz = 0x2, 4820 LSM6DSV_SH_60Hz = 0x3, 4821 LSM6DSV_SH_120Hz = 0x4, 4822 LSM6DSV_SH_240Hz = 0x5, 4823 LSM6DSV_SH_480Hz = 0x6, 4824 } lsm6dsv_sh_data_rate_t; 4825 int32_t lsm6dsv_sh_data_rate_set(const stmdev_ctx_t *ctx, 4826 lsm6dsv_sh_data_rate_t val); 4827 int32_t lsm6dsv_sh_data_rate_get(const stmdev_ctx_t *ctx, 4828 lsm6dsv_sh_data_rate_t *val); 4829 4830 typedef struct 4831 { 4832 uint8_t slv_add; 4833 uint8_t slv_subadd; 4834 uint8_t slv_len; 4835 } lsm6dsv_sh_cfg_read_t; 4836 int32_t lsm6dsv_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx, 4837 lsm6dsv_sh_cfg_read_t *val); 4838 4839 int32_t lsm6dsv_sh_status_get(const stmdev_ctx_t *ctx, 4840 lsm6dsv_status_master_t *val); 4841 4842 int32_t lsm6dsv_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); 4843 int32_t lsm6dsv_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); 4844 4845 typedef enum 4846 { 4847 LSM6DSV_I2C_I3C_ENABLE = 0x0, 4848 LSM6DSV_I2C_I3C_DISABLE = 0x1, 4849 } lsm6dsv_ui_i2c_i3c_mode_t; 4850 int32_t lsm6dsv_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx, 4851 lsm6dsv_ui_i2c_i3c_mode_t val); 4852 int32_t lsm6dsv_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, 4853 lsm6dsv_ui_i2c_i3c_mode_t *val); 4854 4855 typedef enum 4856 { 4857 LSM6DSV_SPI_4_WIRE = 0x0, 4858 LSM6DSV_SPI_3_WIRE = 0x1, 4859 } lsm6dsv_spi_mode_t; 4860 int32_t lsm6dsv_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_spi_mode_t val); 4861 int32_t lsm6dsv_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_spi_mode_t *val); 4862 4863 int32_t lsm6dsv_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); 4864 int32_t lsm6dsv_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); 4865 4866 typedef enum 4867 { 4868 LSM6DSV_SPI2_4_WIRE = 0x0, 4869 LSM6DSV_SPI2_3_WIRE = 0x1, 4870 } lsm6dsv_spi2_mode_t; 4871 int32_t lsm6dsv_spi2_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_spi2_mode_t val); 4872 int32_t lsm6dsv_spi2_mode_get(const stmdev_ctx_t *ctx, 4873 lsm6dsv_spi2_mode_t *val); 4874 4875 int32_t lsm6dsv_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 4876 int32_t lsm6dsv_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 4877 4878 typedef struct 4879 { 4880 uint8_t step_counter_enable : 1; 4881 } lsm6dsv_stpcnt_mode_t; 4882 int32_t lsm6dsv_stpcnt_mode_set(const stmdev_ctx_t *ctx, 4883 lsm6dsv_stpcnt_mode_t val); 4884 int32_t lsm6dsv_stpcnt_mode_get(const stmdev_ctx_t *ctx, 4885 lsm6dsv_stpcnt_mode_t *val); 4886 4887 int32_t lsm6dsv_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); 4888 4889 int32_t lsm6dsv_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val); 4890 int32_t lsm6dsv_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val); 4891 4892 int32_t lsm6dsv_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val); 4893 int32_t lsm6dsv_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val); 4894 4895 int32_t lsm6dsv_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val); 4896 int32_t lsm6dsv_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val); 4897 4898 int32_t lsm6dsv_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint8_t val); 4899 int32_t lsm6dsv_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint8_t *val); 4900 4901 typedef struct 4902 { 4903 float_t gbias_x; /* dps */ 4904 float_t gbias_y; /* dps */ 4905 float_t gbias_z; /* dps */ 4906 } lsm6dsv_sflp_gbias_t; 4907 int32_t lsm6dsv_sflp_game_gbias_set(const stmdev_ctx_t *ctx, 4908 lsm6dsv_sflp_gbias_t *val); 4909 4910 typedef enum 4911 { 4912 LSM6DSV_SFLP_15Hz = 0x0, 4913 LSM6DSV_SFLP_30Hz = 0x1, 4914 LSM6DSV_SFLP_60Hz = 0x2, 4915 LSM6DSV_SFLP_120Hz = 0x3, 4916 LSM6DSV_SFLP_240Hz = 0x4, 4917 LSM6DSV_SFLP_480Hz = 0x5, 4918 } lsm6dsv_sflp_data_rate_t; 4919 int32_t lsm6dsv_sflp_data_rate_set(const stmdev_ctx_t *ctx, 4920 lsm6dsv_sflp_data_rate_t val); 4921 int32_t lsm6dsv_sflp_data_rate_get(const stmdev_ctx_t *ctx, 4922 lsm6dsv_sflp_data_rate_t *val); 4923 4924 typedef struct 4925 { 4926 uint8_t tap_x_en : 1; 4927 uint8_t tap_y_en : 1; 4928 uint8_t tap_z_en : 1; 4929 } lsm6dsv_tap_detection_t; 4930 int32_t lsm6dsv_tap_detection_set(const stmdev_ctx_t *ctx, 4931 lsm6dsv_tap_detection_t val); 4932 int32_t lsm6dsv_tap_detection_get(const stmdev_ctx_t *ctx, 4933 lsm6dsv_tap_detection_t *val); 4934 4935 typedef struct 4936 { 4937 uint8_t x : 5; 4938 uint8_t y : 5; 4939 uint8_t z : 5; 4940 } lsm6dsv_tap_thresholds_t; 4941 int32_t lsm6dsv_tap_thresholds_set(const stmdev_ctx_t *ctx, 4942 lsm6dsv_tap_thresholds_t val); 4943 int32_t lsm6dsv_tap_thresholds_get(const stmdev_ctx_t *ctx, 4944 lsm6dsv_tap_thresholds_t *val); 4945 4946 typedef enum 4947 { 4948 LSM6DSV_XYZ = 0x0, 4949 LSM6DSV_YXZ = 0x1, 4950 LSM6DSV_XZY = 0x2, 4951 LSM6DSV_ZYX = 0x3, 4952 LSM6DSV_YZX = 0x5, 4953 LSM6DSV_ZXY = 0x6, 4954 } lsm6dsv_tap_axis_priority_t; 4955 int32_t lsm6dsv_tap_axis_priority_set(const stmdev_ctx_t *ctx, 4956 lsm6dsv_tap_axis_priority_t val); 4957 int32_t lsm6dsv_tap_axis_priority_get(const stmdev_ctx_t *ctx, 4958 lsm6dsv_tap_axis_priority_t *val); 4959 4960 typedef struct 4961 { 4962 uint8_t shock : 2; 4963 uint8_t quiet : 2; 4964 uint8_t tap_gap : 4; 4965 } lsm6dsv_tap_time_windows_t; 4966 int32_t lsm6dsv_tap_time_windows_set(const stmdev_ctx_t *ctx, 4967 lsm6dsv_tap_time_windows_t val); 4968 int32_t lsm6dsv_tap_time_windows_get(const stmdev_ctx_t *ctx, 4969 lsm6dsv_tap_time_windows_t *val); 4970 4971 typedef enum 4972 { 4973 LSM6DSV_ONLY_SINGLE = 0x0, 4974 LSM6DSV_BOTH_SINGLE_DOUBLE = 0x1, 4975 } lsm6dsv_tap_mode_t; 4976 int32_t lsm6dsv_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_tap_mode_t val); 4977 int32_t lsm6dsv_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_tap_mode_t *val); 4978 4979 int32_t lsm6dsv_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 4980 int32_t lsm6dsv_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 4981 4982 int32_t lsm6dsv_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); 4983 4984 int32_t lsm6dsv_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); 4985 int32_t lsm6dsv_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); 4986 4987 typedef enum 4988 { 4989 LSM6DSV_XL_AND_GY_NOT_AFFECTED = 0x0, 4990 LSM6DSV_XL_LOW_POWER_GY_NOT_AFFECTED = 0x1, 4991 LSM6DSV_XL_LOW_POWER_GY_SLEEP = 0x2, 4992 LSM6DSV_XL_LOW_POWER_GY_POWER_DOWN = 0x3, 4993 } lsm6dsv_act_mode_t; 4994 int32_t lsm6dsv_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsv_act_mode_t val); 4995 int32_t lsm6dsv_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsv_act_mode_t *val); 4996 4997 typedef enum 4998 { 4999 LSM6DSV_SLEEP_TO_ACT_AT_1ST_SAMPLE = 0x0, 5000 LSM6DSV_SLEEP_TO_ACT_AT_2ND_SAMPLE = 0x1, 5001 LSM6DSV_SLEEP_TO_ACT_AT_3RD_SAMPLE = 0x2, 5002 LSM6DSV_SLEEP_TO_ACT_AT_4th_SAMPLE = 0x3, 5003 } lsm6dsv_act_from_sleep_to_act_dur_t; 5004 int32_t lsm6dsv_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx, 5005 lsm6dsv_act_from_sleep_to_act_dur_t val); 5006 int32_t lsm6dsv_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, 5007 lsm6dsv_act_from_sleep_to_act_dur_t *val); 5008 5009 typedef enum 5010 { 5011 LSM6DSV_1Hz875 = 0x0, 5012 LSM6DSV_15Hz = 0x1, 5013 LSM6DSV_30Hz = 0x2, 5014 LSM6DSV_60Hz = 0x3, 5015 } lsm6dsv_act_sleep_xl_odr_t; 5016 int32_t lsm6dsv_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx, 5017 lsm6dsv_act_sleep_xl_odr_t val); 5018 int32_t lsm6dsv_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, 5019 lsm6dsv_act_sleep_xl_odr_t *val); 5020 5021 typedef struct 5022 { 5023 lsm6dsv_inactivity_dur_t inactivity_cfg; 5024 uint8_t inactivity_ths; 5025 uint8_t threshold; 5026 uint8_t duration; 5027 } lsm6dsv_act_thresholds_t; 5028 int32_t lsm6dsv_act_thresholds_set(const stmdev_ctx_t *ctx, 5029 lsm6dsv_act_thresholds_t *val); 5030 int32_t lsm6dsv_act_thresholds_get(const stmdev_ctx_t *ctx, 5031 lsm6dsv_act_thresholds_t *val); 5032 5033 typedef struct 5034 { 5035 uint8_t shock : 2; 5036 uint8_t quiet : 4; 5037 } lsm6dsv_act_wkup_time_windows_t; 5038 int32_t lsm6dsv_act_wkup_time_windows_set(const stmdev_ctx_t *ctx, 5039 lsm6dsv_act_wkup_time_windows_t val); 5040 int32_t lsm6dsv_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, 5041 lsm6dsv_act_wkup_time_windows_t *val); 5042 5043 /** 5044 * @} 5045 * 5046 */ 5047 5048 #ifdef __cplusplus 5049 } 5050 #endif 5051 5052 #endif /*LSM6DSV_DRIVER_H */ 5053 5054 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 5055
