1 /**
2 ******************************************************************************
3 * @file lsm6dsv32x_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSV32X driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dsv32x_reg.h"
21
22 /**
23 * @defgroup LSM6DSV32X
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dsv32x enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup Interfaces functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx communication interface handler.(ptr)
43 * @param reg first register address to read.
44 * @param data buffer for data read.(ptr)
45 * @param len number of consecutive register to read.
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6dsv32x_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dsv32x_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx communication interface handler.(ptr)
69 * @param reg first register address to write.
70 * @param data the buffer contains data to be written.(ptr)
71 * @param len number of consecutive register to write.
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lsm6dsv32x_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lsm6dsv32x_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup Private functions
98 * @brief Section collect all the utility functions needed by APIs.
99 * @{
100 *
101 */
102
bytecpy(uint8_t * target,uint8_t * source)103 static void bytecpy(uint8_t *target, uint8_t *source)
104 {
105 if ((target != NULL) && (source != NULL))
106 {
107 *target = *source;
108 }
109 }
110
111 /**
112 * @}
113 *
114 */
115
116 /**
117 * @defgroup Sensitivity
118 * @brief These functions convert raw-data into engineering units.
119 * @{
120 *
121 */
lsm6dsv32x_from_sflp_to_mg(int16_t lsb)122 float_t lsm6dsv32x_from_sflp_to_mg(int16_t lsb)
123 {
124 return ((float_t)lsb) * 0.061f;
125 }
126
lsm6dsv32x_from_fs4_to_mg(int16_t lsb)127 float_t lsm6dsv32x_from_fs4_to_mg(int16_t lsb)
128 {
129 return ((float_t)lsb) * 0.122f;
130 }
131
lsm6dsv32x_from_fs8_to_mg(int16_t lsb)132 float_t lsm6dsv32x_from_fs8_to_mg(int16_t lsb)
133 {
134 return ((float_t)lsb) * 0.244f;
135 }
136
lsm6dsv32x_from_fs16_to_mg(int16_t lsb)137 float_t lsm6dsv32x_from_fs16_to_mg(int16_t lsb)
138 {
139 return ((float_t)lsb) * 0.488f;
140 }
141
lsm6dsv32x_from_fs32_to_mg(int16_t lsb)142 float_t lsm6dsv32x_from_fs32_to_mg(int16_t lsb)
143 {
144 return ((float_t)lsb) * 0.976f;
145 }
146
lsm6dsv32x_from_fs125_to_mdps(int16_t lsb)147 float_t lsm6dsv32x_from_fs125_to_mdps(int16_t lsb)
148 {
149 return ((float_t)lsb) * 4.375f;
150 }
151
lsm6dsv32x_from_fs250_to_mdps(int16_t lsb)152 float_t lsm6dsv32x_from_fs250_to_mdps(int16_t lsb)
153 {
154 return ((float_t)lsb) * 8.750f;
155 }
156
lsm6dsv32x_from_fs500_to_mdps(int16_t lsb)157 float_t lsm6dsv32x_from_fs500_to_mdps(int16_t lsb)
158 {
159 return ((float_t)lsb) * 17.50f;
160 }
161
lsm6dsv32x_from_fs1000_to_mdps(int16_t lsb)162 float_t lsm6dsv32x_from_fs1000_to_mdps(int16_t lsb)
163 {
164 return ((float_t)lsb) * 35.0f;
165 }
166
lsm6dsv32x_from_fs2000_to_mdps(int16_t lsb)167 float_t lsm6dsv32x_from_fs2000_to_mdps(int16_t lsb)
168 {
169 return ((float_t)lsb) * 70.0f;
170 }
171
lsm6dsv32x_from_fs4000_to_mdps(int16_t lsb)172 float_t lsm6dsv32x_from_fs4000_to_mdps(int16_t lsb)
173 {
174 return ((float_t)lsb) * 140.0f;
175 }
176
lsm6dsv32x_from_lsb_to_celsius(int16_t lsb)177 float_t lsm6dsv32x_from_lsb_to_celsius(int16_t lsb)
178 {
179 return (((float_t)lsb / 256.0f) + 25.0f);
180 }
181
lsm6dsv32x_from_lsb_to_nsec(uint32_t lsb)182 float_t lsm6dsv32x_from_lsb_to_nsec(uint32_t lsb)
183 {
184 return ((float_t)lsb * 21750.0f);
185 }
186
lsm6dsv32x_from_lsb_to_mv(int16_t lsb)187 float_t lsm6dsv32x_from_lsb_to_mv(int16_t lsb)
188 {
189 return ((float_t)lsb) / 78.0f;
190 }
191
192 /*
193 * Original conversion routines taken from: https://github.com/numpy/numpy
194 *
195 * Converts from half-precision (16-bit) float number to single precision (32-bit).
196 *
197 * uint32_t static uint32_t ToFloatBits(uint16_t h);
198 * Released under BSD-3-Clause License
199 */
ToFloatBits(uint16_t h)200 static uint32_t ToFloatBits(uint16_t h)
201 {
202 uint16_t h_exp = (h & 0x7c00u);
203 uint32_t f_sgn = ((uint32_t)h & 0x8000u) << 16;
204 switch (h_exp)
205 {
206 case 0x0000u: // 0 or subnormal
207 {
208 uint16_t h_sig = (h & 0x03ffu);
209 // Signed zero
210 if (h_sig == 0)
211 {
212 return f_sgn;
213 }
214 // Subnormal
215 h_sig <<= 1;
216 while ((h_sig & 0x0400u) == 0)
217 {
218 h_sig <<= 1;
219 h_exp++;
220 }
221 uint32_t f_exp = ((uint32_t)(127 - 15 - h_exp)) << 23;
222 uint32_t f_sig = ((uint32_t)(h_sig & 0x03ffu)) << 13;
223 return f_sgn + f_exp + f_sig;
224 }
225 case 0x7c00u: // inf or NaN
226 // All-ones exponent and a copy of the significand
227 return f_sgn + 0x7f800000u + (((uint32_t)(h & 0x03ffu)) << 13);
228 default: // normalized
229 // Just need to adjust the exponent and shift
230 return f_sgn + (((uint32_t)(h & 0x7fffu) + 0x1c000u) << 13);
231 }
232 }
233
234 /**
235 * @brief Convert from 16-bit to 32-bit float number
236 *
237 * @param val Batching in FIFO buffer of SFLP values.
238 * @retval interface status (MANDATORY: return 0 -> no Error)
239 *
240 */
lsm6dsv32x_from_f16_to_f32(uint16_t val)241 uint32_t lsm6dsv32x_from_f16_to_f32(uint16_t val)
242 {
243 return ToFloatBits(val);
244 }
245
246 /**
247 * @}
248 *
249 */
250
251 /**
252 * @defgroup Accelerometer user offset correction
253 * @brief This section groups all the functions concerning the
254 * usage of Accelerometer user offset correction
255 * @{
256 *
257 */
258
259 /**
260 * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[set]
261 *
262 * @param ctx read / write interface definitions
263 * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path.
264 * @retval interface status (MANDATORY: return 0 -> no Error)
265 *
266 */
lsm6dsv32x_xl_offset_on_out_set(const stmdev_ctx_t * ctx,uint8_t val)267 int32_t lsm6dsv32x_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val)
268 {
269 lsm6dsv32x_ctrl9_t ctrl9;
270 int32_t ret;
271
272 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1);
273 if (ret == 0)
274 {
275 ctrl9.usr_off_on_out = val;
276 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1);
277 }
278
279 return ret;
280 }
281
282 /**
283 * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[get]
284 *
285 * @param ctx read / write interface definitions
286 * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path.
287 * @retval interface status (MANDATORY: return 0 -> no Error)
288 *
289 */
lsm6dsv32x_xl_offset_on_out_get(const stmdev_ctx_t * ctx,uint8_t * val)290 int32_t lsm6dsv32x_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val)
291 {
292 lsm6dsv32x_ctrl9_t ctrl9;
293 int32_t ret;
294
295 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1);
296 *val = ctrl9.usr_off_on_out;
297
298 return ret;
299 }
300
301 /**
302 * @brief Accelerometer user offset correction values in mg.[set]
303 *
304 * @param ctx read / write interface definitions
305 * @param val Accelerometer user offset correction values in mg.
306 * @retval interface status (MANDATORY: return 0 -> no Error)
307 *
308 */
lsm6dsv32x_xl_offset_mg_set(const stmdev_ctx_t * ctx,lsm6dsv32x_xl_offset_mg_t val)309 int32_t lsm6dsv32x_xl_offset_mg_set(const stmdev_ctx_t *ctx,
310 lsm6dsv32x_xl_offset_mg_t val)
311 {
312 lsm6dsv32x_z_ofs_usr_t z_ofs_usr;
313 lsm6dsv32x_y_ofs_usr_t y_ofs_usr;
314 lsm6dsv32x_x_ofs_usr_t x_ofs_usr;
315 lsm6dsv32x_ctrl9_t ctrl9;
316 int32_t ret;
317 float_t tmp;
318
319 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
320 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
321 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
322 if (ret != 0)
323 {
324 return ret;
325 }
326
327
328 if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) &&
329 (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) &&
330 (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f)))
331 {
332 ctrl9.usr_off_w = 0;
333
334 tmp = val.z_mg / 0.0078125f;
335 z_ofs_usr.z_ofs_usr = (uint8_t)tmp;
336
337 tmp = val.y_mg / 0.0078125f;
338 y_ofs_usr.y_ofs_usr = (uint8_t)tmp;
339
340 tmp = val.x_mg / 0.0078125f;
341 x_ofs_usr.x_ofs_usr = (uint8_t)tmp;
342 }
343 else if ((val.x_mg < (0.125f * 127.0f)) && (val.x_mg > (0.125f * -127.0f)) &&
344 (val.y_mg < (0.125f * 127.0f)) && (val.y_mg > (0.125f * -127.0f)) &&
345 (val.z_mg < (0.125f * 127.0f)) && (val.z_mg > (0.125f * -127.0f)))
346 {
347 ctrl9.usr_off_w = 1;
348
349 tmp = val.z_mg / 0.125f;
350 z_ofs_usr.z_ofs_usr = (uint8_t)tmp;
351
352 tmp = val.y_mg / 0.125f;
353 y_ofs_usr.y_ofs_usr = (uint8_t)tmp;
354
355 tmp = val.x_mg / 0.125f;
356 x_ofs_usr.x_ofs_usr = (uint8_t)tmp;
357 }
358 else // out of limit
359 {
360 ctrl9.usr_off_w = 1;
361 z_ofs_usr.z_ofs_usr = 0xFFU;
362 y_ofs_usr.y_ofs_usr = 0xFFU;
363 x_ofs_usr.x_ofs_usr = 0xFFU;
364 }
365
366 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
367 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
368 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
369 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1);
370
371 return ret;
372 }
373
374 /**
375 * @brief Accelerometer user offset correction values in mg.[get]
376 *
377 * @param ctx read / write interface definitions
378 * @param val Accelerometer user offset correction values in mg.
379 * @retval interface status (MANDATORY: return 0 -> no Error)
380 *
381 */
lsm6dsv32x_xl_offset_mg_get(const stmdev_ctx_t * ctx,lsm6dsv32x_xl_offset_mg_t * val)382 int32_t lsm6dsv32x_xl_offset_mg_get(const stmdev_ctx_t *ctx,
383 lsm6dsv32x_xl_offset_mg_t *val)
384 {
385 lsm6dsv32x_z_ofs_usr_t z_ofs_usr;
386 lsm6dsv32x_y_ofs_usr_t y_ofs_usr;
387 lsm6dsv32x_x_ofs_usr_t x_ofs_usr;
388 lsm6dsv32x_ctrl9_t ctrl9;
389 int32_t ret;
390
391 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1);
392 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
393 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
394 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
395 if (ret != 0)
396 {
397 return ret;
398 }
399
400 if (ctrl9.usr_off_w == PROPERTY_DISABLE)
401 {
402 val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.0078125f);
403 val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.0078125f);
404 val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.0078125f);
405 }
406 else
407 {
408 val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.125f);
409 val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.125f);
410 val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.125f);
411 }
412
413 return ret;
414 }
415
416 /**
417 * @}
418 *
419 */
420
421 /**
422 * @brief Reset of the device.[set]
423 *
424 * @param ctx read / write interface definitions
425 * @param val Reset of the device.
426 * @retval interface status (MANDATORY: return 0 -> no Error)
427 *
428 */
lsm6dsv32x_reset_set(const stmdev_ctx_t * ctx,lsm6dsv32x_reset_t val)429 int32_t lsm6dsv32x_reset_set(const stmdev_ctx_t *ctx, lsm6dsv32x_reset_t val)
430 {
431 lsm6dsv32x_func_cfg_access_t func_cfg_access;
432 lsm6dsv32x_ctrl3_t ctrl3;
433 int32_t ret;
434
435 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1);
436 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
437 if (ret != 0)
438 {
439 return ret;
440 }
441
442 ctrl3.boot = ((uint8_t)val & 0x04U) >> 2;
443 ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1;
444 func_cfg_access.sw_por = (uint8_t)val & 0x01U;
445
446 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1);
447 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
448
449 return ret;
450 }
451
452 /**
453 * @brief Global reset of the device.[get]
454 *
455 * @param ctx read / write interface definitions
456 * @param val Global reset of the device.
457 * @retval interface status (MANDATORY: return 0 -> no Error)
458 *
459 */
lsm6dsv32x_reset_get(const stmdev_ctx_t * ctx,lsm6dsv32x_reset_t * val)460 int32_t lsm6dsv32x_reset_get(const stmdev_ctx_t *ctx, lsm6dsv32x_reset_t *val)
461 {
462 lsm6dsv32x_func_cfg_access_t func_cfg_access;
463 lsm6dsv32x_ctrl3_t ctrl3;
464 int32_t ret;
465
466 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1);
467 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
468 if (ret != 0)
469 {
470 return ret;
471 }
472
473 switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por)
474 {
475 case LSM6DSV32X_READY:
476 *val = LSM6DSV32X_READY;
477 break;
478
479 case LSM6DSV32X_GLOBAL_RST:
480 *val = LSM6DSV32X_GLOBAL_RST;
481 break;
482
483 case LSM6DSV32X_RESTORE_CAL_PARAM:
484 *val = LSM6DSV32X_RESTORE_CAL_PARAM;
485 break;
486
487 case LSM6DSV32X_RESTORE_CTRL_REGS:
488 *val = LSM6DSV32X_RESTORE_CTRL_REGS;
489 break;
490
491 default:
492 *val = LSM6DSV32X_GLOBAL_RST;
493 break;
494 }
495
496 return ret;
497 }
498
499 /**
500 * @brief Change memory bank.[set]
501 *
502 * @param ctx read / write interface definitions
503 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK,
504 * @retval interface status (MANDATORY: return 0 -> no Error)
505 *
506 */
lsm6dsv32x_mem_bank_set(const stmdev_ctx_t * ctx,lsm6dsv32x_mem_bank_t val)507 int32_t lsm6dsv32x_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsv32x_mem_bank_t val)
508 {
509 lsm6dsv32x_func_cfg_access_t func_cfg_access;
510 int32_t ret;
511
512 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
513 if (ret != 0)
514 {
515 return ret;
516 }
517
518 func_cfg_access.shub_reg_access = ((uint8_t)val & 0x02U) >> 1;
519 func_cfg_access.emb_func_reg_access = (uint8_t)val & 0x01U;
520 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
521
522 return ret;
523 }
524
525 /**
526 * @brief Change memory bank.[get]
527 *
528 * @param ctx read / write interface definitions
529 * @param val MAIN_MEM_BANK, SENSOR_HUB_MEM_BANK, EMBED_FUNC_MEM_BANK,
530 * @retval interface status (MANDATORY: return 0 -> no Error)
531 *
532 */
lsm6dsv32x_mem_bank_get(const stmdev_ctx_t * ctx,lsm6dsv32x_mem_bank_t * val)533 int32_t lsm6dsv32x_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsv32x_mem_bank_t *val)
534 {
535 lsm6dsv32x_func_cfg_access_t func_cfg_access;
536 int32_t ret;
537
538 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
539 if (ret != 0)
540 {
541 return ret;
542 }
543
544 switch ((func_cfg_access.shub_reg_access << 1) + func_cfg_access.emb_func_reg_access)
545 {
546 case LSM6DSV32X_MAIN_MEM_BANK:
547 *val = LSM6DSV32X_MAIN_MEM_BANK;
548 break;
549
550 case LSM6DSV32X_EMBED_FUNC_MEM_BANK:
551 *val = LSM6DSV32X_EMBED_FUNC_MEM_BANK;
552 break;
553
554 case LSM6DSV32X_SENSOR_HUB_MEM_BANK:
555 *val = LSM6DSV32X_SENSOR_HUB_MEM_BANK;
556 break;
557
558 default:
559 *val = LSM6DSV32X_MAIN_MEM_BANK;
560 break;
561 }
562
563 return ret;
564 }
565
566 /**
567 * @brief Device ID.[get] THis function works also for OIS
568 * (WHO_AM_I and SPI2_WHO_AM_I have same address)
569 *
570 * @param ctx read / write interface definitions
571 * @param val Device ID.
572 * @retval interface status (MANDATORY: return 0 -> no Error)
573 *
574 */
lsm6dsv32x_device_id_get(const stmdev_ctx_t * ctx,uint8_t * val)575 int32_t lsm6dsv32x_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val)
576 {
577 int32_t ret;
578
579 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WHO_AM_I, val, 1);
580
581 return ret;
582 }
583
584 /**
585 * @brief Accelerometer output data rate (ODR) selection.[set]
586 *
587 * @param ctx read / write interface definitions
588 * @param val lsm6dsv32x_data_rate_t enum
589 * @retval interface status (MANDATORY: return 0 -> no Error)
590 *
591 */
lsm6dsv32x_xl_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv32x_data_rate_t val)592 int32_t lsm6dsv32x_xl_data_rate_set(const stmdev_ctx_t *ctx,
593 lsm6dsv32x_data_rate_t val)
594 {
595 lsm6dsv32x_ctrl1_t ctrl1;
596 lsm6dsv32x_haodr_cfg_t haodr;
597 uint8_t sel;
598 int32_t ret;
599
600 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL1, (uint8_t *)&ctrl1, 1);
601 if (ret != 0)
602 {
603 return ret;
604 }
605
606 ctrl1.odr_xl = (uint8_t)val & 0x0Fu;
607 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL1, (uint8_t *)&ctrl1, 1);
608 if (ret != 0)
609 {
610 return ret;
611 }
612
613 sel = ((uint8_t)val >> 4) & 0xFU;
614 if (sel != 0U)
615 {
616 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_HAODR_CFG, (uint8_t *)&haodr, 1);
617 haodr.haodr_sel = sel;
618 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_HAODR_CFG, (uint8_t *)&haodr, 1);
619 }
620
621 return ret;
622 }
623
624 /**
625 * @brief Accelerometer output data rate (ODR) selection.[get]
626 *
627 * @param ctx read / write interface definitions
628 * @param val lsm6dsv32x_data_rate_t enum
629 * @retval interface status (MANDATORY: return 0 -> no Error)
630 *
631 */
lsm6dsv32x_xl_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv32x_data_rate_t * val)632 int32_t lsm6dsv32x_xl_data_rate_get(const stmdev_ctx_t *ctx,
633 lsm6dsv32x_data_rate_t *val)
634 {
635 lsm6dsv32x_ctrl1_t ctrl1;
636 lsm6dsv32x_haodr_cfg_t haodr;
637 uint8_t sel;
638 int32_t ret;
639
640 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL1, (uint8_t *)&ctrl1, 1);
641 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_HAODR_CFG, (uint8_t *)&haodr, 1);
642 if (ret != 0)
643 {
644 return ret;
645 }
646
647 sel = haodr.haodr_sel;
648
649 switch (ctrl1.odr_xl)
650 {
651 case LSM6DSV32X_ODR_OFF:
652 *val = LSM6DSV32X_ODR_OFF;
653 break;
654
655 case LSM6DSV32X_ODR_AT_1Hz875:
656 *val = LSM6DSV32X_ODR_AT_1Hz875;
657 break;
658
659 case LSM6DSV32X_ODR_AT_7Hz5:
660 *val = LSM6DSV32X_ODR_AT_7Hz5;
661 break;
662
663 case LSM6DSV32X_ODR_AT_15Hz:
664 switch (sel)
665 {
666 default:
667 case 0:
668 *val = LSM6DSV32X_ODR_AT_15Hz;
669 break;
670 case 1:
671 *val = LSM6DSV32X_ODR_HA01_AT_15Hz625;
672 break;
673 case 2:
674 *val = LSM6DSV32X_ODR_HA02_AT_12Hz5;
675 break;
676 }
677 break;
678
679 case LSM6DSV32X_ODR_AT_30Hz:
680 switch (sel)
681 {
682 default:
683 case 0:
684 *val = LSM6DSV32X_ODR_AT_30Hz;
685 break;
686 case 1:
687 *val = LSM6DSV32X_ODR_HA01_AT_31Hz25;
688 break;
689 case 2:
690 *val = LSM6DSV32X_ODR_HA02_AT_25Hz;
691 break;
692 }
693 break;
694
695 case LSM6DSV32X_ODR_AT_60Hz:
696 switch (sel)
697 {
698 default:
699 case 0:
700 *val = LSM6DSV32X_ODR_AT_60Hz;
701 break;
702 case 1:
703 *val = LSM6DSV32X_ODR_HA01_AT_62Hz5;
704 break;
705 case 2:
706 *val = LSM6DSV32X_ODR_HA02_AT_50Hz;
707 break;
708 }
709 break;
710
711 case LSM6DSV32X_ODR_AT_120Hz:
712 switch (sel)
713 {
714 default:
715 case 0:
716 *val = LSM6DSV32X_ODR_AT_120Hz;
717 break;
718 case 1:
719 *val = LSM6DSV32X_ODR_HA01_AT_125Hz;
720 break;
721 case 2:
722 *val = LSM6DSV32X_ODR_HA02_AT_100Hz;
723 break;
724 }
725 break;
726
727 case LSM6DSV32X_ODR_AT_240Hz:
728 switch (sel)
729 {
730 default:
731 case 0:
732 *val = LSM6DSV32X_ODR_AT_240Hz;
733 break;
734 case 1:
735 *val = LSM6DSV32X_ODR_HA01_AT_250Hz;
736 break;
737 case 2:
738 *val = LSM6DSV32X_ODR_HA02_AT_200Hz;
739 break;
740 }
741 break;
742
743 case LSM6DSV32X_ODR_AT_480Hz:
744 switch (sel)
745 {
746 default:
747 case 0:
748 *val = LSM6DSV32X_ODR_AT_480Hz;
749 break;
750 case 1:
751 *val = LSM6DSV32X_ODR_HA01_AT_500Hz;
752 break;
753 case 2:
754 *val = LSM6DSV32X_ODR_HA02_AT_400Hz;
755 break;
756 }
757 break;
758
759 case LSM6DSV32X_ODR_AT_960Hz:
760 switch (sel)
761 {
762 default:
763 case 0:
764 *val = LSM6DSV32X_ODR_AT_960Hz;
765 break;
766 case 1:
767 *val = LSM6DSV32X_ODR_HA01_AT_1000Hz;
768 break;
769 case 2:
770 *val = LSM6DSV32X_ODR_HA02_AT_800Hz;
771 break;
772 }
773 break;
774
775 case LSM6DSV32X_ODR_AT_1920Hz:
776 switch (sel)
777 {
778 default:
779 case 0:
780 *val = LSM6DSV32X_ODR_AT_1920Hz;
781 break;
782 case 1:
783 *val = LSM6DSV32X_ODR_HA01_AT_2000Hz;
784 break;
785 case 2:
786 *val = LSM6DSV32X_ODR_HA02_AT_1600Hz;
787 break;
788 }
789 break;
790
791 case LSM6DSV32X_ODR_AT_3840Hz:
792 switch (sel)
793 {
794 default:
795 case 0:
796 *val = LSM6DSV32X_ODR_AT_3840Hz;
797 break;
798 case 1:
799 *val = LSM6DSV32X_ODR_HA01_AT_4000Hz;
800 break;
801 case 2:
802 *val = LSM6DSV32X_ODR_HA02_AT_3200Hz;
803 break;
804 }
805 break;
806
807 case LSM6DSV32X_ODR_AT_7680Hz:
808 switch (sel)
809 {
810 default:
811 case 0:
812 *val = LSM6DSV32X_ODR_AT_7680Hz;
813 break;
814 case 1:
815 *val = LSM6DSV32X_ODR_HA01_AT_8000Hz;
816 break;
817 case 2:
818 *val = LSM6DSV32X_ODR_HA02_AT_6400Hz;
819 break;
820 }
821 break;
822
823 default:
824 *val = LSM6DSV32X_ODR_OFF;
825 break;
826 }
827
828 return ret;
829 }
830
831 /**
832 * @brief Accelerometer operating mode selection.[set]
833 *
834 * @param ctx read / write interface definitions
835 * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURACY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD,
836 * @retval interface status (MANDATORY: return 0 -> no Error)
837 *
838 */
lsm6dsv32x_xl_mode_set(const stmdev_ctx_t * ctx,lsm6dsv32x_xl_mode_t val)839 int32_t lsm6dsv32x_xl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_xl_mode_t val)
840 {
841 lsm6dsv32x_ctrl1_t ctrl1;
842 int32_t ret;
843
844 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL1, (uint8_t *)&ctrl1, 1);
845
846 if (ret == 0)
847 {
848 ctrl1.op_mode_xl = (uint8_t)val & 0x07U;
849 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL1, (uint8_t *)&ctrl1, 1);
850 }
851
852 return ret;
853 }
854
855 /**
856 * @brief Accelerometer operating mode selection.[get]
857 *
858 * @param ctx read / write interface definitions
859 * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURACY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD,
860 * @retval interface status (MANDATORY: return 0 -> no Error)
861 *
862 */
lsm6dsv32x_xl_mode_get(const stmdev_ctx_t * ctx,lsm6dsv32x_xl_mode_t * val)863 int32_t lsm6dsv32x_xl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_xl_mode_t *val)
864 {
865 lsm6dsv32x_ctrl1_t ctrl1;
866 int32_t ret;
867
868 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL1, (uint8_t *)&ctrl1, 1);
869 if (ret != 0)
870 {
871 return ret;
872 }
873
874 switch (ctrl1.op_mode_xl)
875 {
876 case LSM6DSV32X_XL_HIGH_PERFORMANCE_MD:
877 *val = LSM6DSV32X_XL_HIGH_PERFORMANCE_MD;
878 break;
879
880 case LSM6DSV32X_XL_HIGH_ACCURACY_ODR_MD:
881 *val = LSM6DSV32X_XL_HIGH_ACCURACY_ODR_MD;
882 break;
883
884 case LSM6DSV32X_XL_ODR_TRIGGERED_MD:
885 *val = LSM6DSV32X_XL_ODR_TRIGGERED_MD;
886 break;
887
888 case LSM6DSV32X_XL_LOW_POWER_2_AVG_MD:
889 *val = LSM6DSV32X_XL_LOW_POWER_2_AVG_MD;
890 break;
891
892 case LSM6DSV32X_XL_LOW_POWER_4_AVG_MD:
893 *val = LSM6DSV32X_XL_LOW_POWER_4_AVG_MD;
894 break;
895
896 case LSM6DSV32X_XL_LOW_POWER_8_AVG_MD:
897 *val = LSM6DSV32X_XL_LOW_POWER_8_AVG_MD;
898 break;
899
900 case LSM6DSV32X_XL_NORMAL_MD:
901 *val = LSM6DSV32X_XL_NORMAL_MD;
902 break;
903
904 default:
905 *val = LSM6DSV32X_XL_HIGH_PERFORMANCE_MD;
906 break;
907 }
908
909 return ret;
910 }
911
912 /**
913 * @brief Gyroscope output data rate (ODR) selection.[set]
914 *
915 * @param ctx read / write interface definitions
916 * @param val lsm6dsv32x_data_rate_t enum
917 * @retval interface status (MANDATORY: return 0 -> no Error)
918 *
919 */
lsm6dsv32x_gy_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv32x_data_rate_t val)920 int32_t lsm6dsv32x_gy_data_rate_set(const stmdev_ctx_t *ctx,
921 lsm6dsv32x_data_rate_t val)
922 {
923 lsm6dsv32x_ctrl2_t ctrl2;
924 lsm6dsv32x_haodr_cfg_t haodr;
925 uint8_t sel;
926 int32_t ret;
927
928 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL2, (uint8_t *)&ctrl2, 1);
929
930 ctrl2.odr_g = (uint8_t)val & 0x0Fu;
931 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL2, (uint8_t *)&ctrl2, 1);
932 if (ret != 0)
933 {
934 return ret;
935 }
936
937 sel = ((uint8_t)val >> 4) & 0xFU;
938 if (sel != 0U)
939 {
940 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_HAODR_CFG, (uint8_t *)&haodr, 1);
941 haodr.haodr_sel = sel;
942 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_HAODR_CFG, (uint8_t *)&haodr, 1);
943 }
944
945 return ret;
946 }
947
948 /**
949 * @brief Gyroscope output data rate (ODR) selection.[get]
950 *
951 * @param ctx read / write interface definitions
952 * @param val lsm6dsv32x_data_rate_t enum
953 * @retval interface status (MANDATORY: return 0 -> no Error)
954 *
955 */
lsm6dsv32x_gy_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv32x_data_rate_t * val)956 int32_t lsm6dsv32x_gy_data_rate_get(const stmdev_ctx_t *ctx,
957 lsm6dsv32x_data_rate_t *val)
958 {
959 lsm6dsv32x_ctrl2_t ctrl2;
960 lsm6dsv32x_haodr_cfg_t haodr;
961 uint8_t sel;
962 int32_t ret;
963
964 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL2, (uint8_t *)&ctrl2, 1);
965 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_HAODR_CFG, (uint8_t *)&haodr, 1);
966 if (ret != 0)
967 {
968 return ret;
969 }
970
971 sel = haodr.haodr_sel;
972
973 switch (ctrl2.odr_g)
974 {
975 case LSM6DSV32X_ODR_OFF:
976 *val = LSM6DSV32X_ODR_OFF;
977 break;
978
979 case LSM6DSV32X_ODR_AT_1Hz875:
980 *val = LSM6DSV32X_ODR_AT_1Hz875;
981 break;
982
983 case LSM6DSV32X_ODR_AT_7Hz5:
984 *val = LSM6DSV32X_ODR_AT_7Hz5;
985 break;
986
987 case LSM6DSV32X_ODR_AT_15Hz:
988 switch (sel)
989 {
990 default:
991 case 0:
992 *val = LSM6DSV32X_ODR_AT_15Hz;
993 break;
994 case 1:
995 *val = LSM6DSV32X_ODR_HA01_AT_15Hz625;
996 break;
997 case 2:
998 *val = LSM6DSV32X_ODR_HA02_AT_12Hz5;
999 break;
1000 }
1001 break;
1002
1003 case LSM6DSV32X_ODR_AT_30Hz:
1004 switch (sel)
1005 {
1006 default:
1007 case 0:
1008 *val = LSM6DSV32X_ODR_AT_30Hz;
1009 break;
1010 case 1:
1011 *val = LSM6DSV32X_ODR_HA01_AT_31Hz25;
1012 break;
1013 case 2:
1014 *val = LSM6DSV32X_ODR_HA02_AT_25Hz;
1015 break;
1016 }
1017 break;
1018
1019 case LSM6DSV32X_ODR_AT_60Hz:
1020 switch (sel)
1021 {
1022 default:
1023 case 0:
1024 *val = LSM6DSV32X_ODR_AT_60Hz;
1025 break;
1026 case 1:
1027 *val = LSM6DSV32X_ODR_HA01_AT_62Hz5;
1028 break;
1029 case 2:
1030 *val = LSM6DSV32X_ODR_HA02_AT_50Hz;
1031 break;
1032 }
1033 break;
1034
1035 case LSM6DSV32X_ODR_AT_120Hz:
1036 switch (sel)
1037 {
1038 default:
1039 case 0:
1040 *val = LSM6DSV32X_ODR_AT_120Hz;
1041 break;
1042 case 1:
1043 *val = LSM6DSV32X_ODR_HA01_AT_125Hz;
1044 break;
1045 case 2:
1046 *val = LSM6DSV32X_ODR_HA02_AT_100Hz;
1047 break;
1048 }
1049 break;
1050
1051 case LSM6DSV32X_ODR_AT_240Hz:
1052 switch (sel)
1053 {
1054 default:
1055 case 0:
1056 *val = LSM6DSV32X_ODR_AT_240Hz;
1057 break;
1058 case 1:
1059 *val = LSM6DSV32X_ODR_HA01_AT_250Hz;
1060 break;
1061 case 2:
1062 *val = LSM6DSV32X_ODR_HA02_AT_200Hz;
1063 break;
1064 }
1065 break;
1066
1067 case LSM6DSV32X_ODR_AT_480Hz:
1068 switch (sel)
1069 {
1070 default:
1071 case 0:
1072 *val = LSM6DSV32X_ODR_AT_480Hz;
1073 break;
1074 case 1:
1075 *val = LSM6DSV32X_ODR_HA01_AT_500Hz;
1076 break;
1077 case 2:
1078 *val = LSM6DSV32X_ODR_HA02_AT_400Hz;
1079 break;
1080 }
1081 break;
1082
1083 case LSM6DSV32X_ODR_AT_960Hz:
1084 switch (sel)
1085 {
1086 default:
1087 case 0:
1088 *val = LSM6DSV32X_ODR_AT_960Hz;
1089 break;
1090 case 1:
1091 *val = LSM6DSV32X_ODR_HA01_AT_1000Hz;
1092 break;
1093 case 2:
1094 *val = LSM6DSV32X_ODR_HA02_AT_800Hz;
1095 break;
1096 }
1097 break;
1098
1099 case LSM6DSV32X_ODR_AT_1920Hz:
1100 switch (sel)
1101 {
1102 default:
1103 case 0:
1104 *val = LSM6DSV32X_ODR_AT_1920Hz;
1105 break;
1106 case 1:
1107 *val = LSM6DSV32X_ODR_HA01_AT_2000Hz;
1108 break;
1109 case 2:
1110 *val = LSM6DSV32X_ODR_HA02_AT_1600Hz;
1111 break;
1112 }
1113 break;
1114
1115 case LSM6DSV32X_ODR_AT_3840Hz:
1116 switch (sel)
1117 {
1118 default:
1119 case 0:
1120 *val = LSM6DSV32X_ODR_AT_3840Hz;
1121 break;
1122 case 1:
1123 *val = LSM6DSV32X_ODR_HA01_AT_4000Hz;
1124 break;
1125 case 2:
1126 *val = LSM6DSV32X_ODR_HA02_AT_3200Hz;
1127 break;
1128 }
1129 break;
1130
1131 case LSM6DSV32X_ODR_AT_7680Hz:
1132 switch (sel)
1133 {
1134 default:
1135 case 0:
1136 *val = LSM6DSV32X_ODR_AT_7680Hz;
1137 break;
1138 case 1:
1139 *val = LSM6DSV32X_ODR_HA01_AT_8000Hz;
1140 break;
1141 case 2:
1142 *val = LSM6DSV32X_ODR_HA02_AT_6400Hz;
1143 break;
1144 }
1145 break;
1146
1147 default:
1148 *val = LSM6DSV32X_ODR_OFF;
1149 break;
1150 }
1151
1152 return ret;
1153 }
1154
1155 /**
1156 * @brief Gyroscope operating mode selection.[set]
1157 *
1158 * @param ctx read / write interface definitions
1159 * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURACY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD,
1160 * @retval interface status (MANDATORY: return 0 -> no Error)
1161 *
1162 */
lsm6dsv32x_gy_mode_set(const stmdev_ctx_t * ctx,lsm6dsv32x_gy_mode_t val)1163 int32_t lsm6dsv32x_gy_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_gy_mode_t val)
1164 {
1165 lsm6dsv32x_ctrl2_t ctrl2;
1166 int32_t ret;
1167
1168 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL2, (uint8_t *)&ctrl2, 1);
1169 if (ret == 0)
1170 {
1171 ctrl2.op_mode_g = (uint8_t)val & 0x07U;
1172 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL2, (uint8_t *)&ctrl2, 1);
1173 }
1174
1175 return ret;
1176 }
1177
1178 /**
1179 * @brief Gyroscope operating mode selection.[get]
1180 *
1181 * @param ctx read / write interface definitions
1182 * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURACY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD,
1183 * @retval interface status (MANDATORY: return 0 -> no Error)
1184 *
1185 */
lsm6dsv32x_gy_mode_get(const stmdev_ctx_t * ctx,lsm6dsv32x_gy_mode_t * val)1186 int32_t lsm6dsv32x_gy_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_gy_mode_t *val)
1187 {
1188 lsm6dsv32x_ctrl2_t ctrl2;
1189 int32_t ret;
1190
1191 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL2, (uint8_t *)&ctrl2, 1);
1192 if (ret != 0)
1193 {
1194 return ret;
1195 }
1196
1197 switch (ctrl2.op_mode_g)
1198 {
1199 case LSM6DSV32X_GY_HIGH_PERFORMANCE_MD:
1200 *val = LSM6DSV32X_GY_HIGH_PERFORMANCE_MD;
1201 break;
1202
1203 case LSM6DSV32X_GY_HIGH_ACCURACY_ODR_MD:
1204 *val = LSM6DSV32X_GY_HIGH_ACCURACY_ODR_MD;
1205 break;
1206
1207 case LSM6DSV32X_GY_SLEEP_MD:
1208 *val = LSM6DSV32X_GY_SLEEP_MD;
1209 break;
1210
1211 case LSM6DSV32X_GY_LOW_POWER_MD:
1212 *val = LSM6DSV32X_GY_LOW_POWER_MD;
1213 break;
1214
1215 default:
1216 *val = LSM6DSV32X_GY_HIGH_PERFORMANCE_MD;
1217 break;
1218 }
1219
1220 return ret;
1221 }
1222
1223 /**
1224 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set]
1225 *
1226 * @param ctx read / write interface definitions
1227 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
1228 * @retval interface status (MANDATORY: return 0 -> no Error)
1229 *
1230 */
lsm6dsv32x_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)1231 int32_t lsm6dsv32x_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
1232 {
1233 lsm6dsv32x_ctrl3_t ctrl3;
1234 int32_t ret;
1235
1236 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1);
1237 if (ret == 0)
1238 {
1239 ctrl3.if_inc = val;
1240 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1);
1241 }
1242
1243 return ret;
1244 }
1245
1246 /**
1247 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get]
1248 *
1249 * @param ctx read / write interface definitions
1250 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
1251 * @retval interface status (MANDATORY: return 0 -> no Error)
1252 *
1253 */
lsm6dsv32x_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)1254 int32_t lsm6dsv32x_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
1255 {
1256 lsm6dsv32x_ctrl3_t ctrl3;
1257 int32_t ret;
1258
1259 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1);
1260 *val = ctrl3.if_inc;
1261
1262 return ret;
1263 }
1264
1265 /**
1266 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set]
1267 *
1268 * @param ctx read / write interface definitions
1269 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
1270 * @retval interface status (MANDATORY: return 0 -> no Error)
1271 *
1272 */
lsm6dsv32x_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)1273 int32_t lsm6dsv32x_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
1274 {
1275 lsm6dsv32x_ctrl3_t ctrl3;
1276 int32_t ret;
1277
1278 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1);
1279
1280 if (ret == 0)
1281 {
1282 ctrl3.bdu = val;
1283 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1);
1284 }
1285
1286 return ret;
1287 }
1288
1289 /**
1290 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get]
1291 *
1292 * @param ctx read / write interface definitions
1293 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
1294 * @retval interface status (MANDATORY: return 0 -> no Error)
1295 *
1296 */
lsm6dsv32x_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)1297 int32_t lsm6dsv32x_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
1298 {
1299 lsm6dsv32x_ctrl3_t ctrl3;
1300 int32_t ret;
1301
1302 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL3, (uint8_t *)&ctrl3, 1);
1303 *val = ctrl3.bdu;
1304
1305 return ret;
1306 }
1307
1308 /**
1309 * @brief Configure ODR trigger. [set]
1310 *
1311 * @param ctx read / write interface definitions
1312 * @param val number of data in the reference period.
1313 * @retval interface status (MANDATORY: return 0 -> no Error)
1314 *
1315 */
lsm6dsv32x_odr_trig_cfg_set(const stmdev_ctx_t * ctx,uint8_t val)1316 int32_t lsm6dsv32x_odr_trig_cfg_set(const stmdev_ctx_t *ctx, uint8_t val)
1317 {
1318 lsm6dsv32x_odr_trig_cfg_t odr_trig;
1319 int32_t ret;
1320
1321 if (val >= 1U && val <= 3U)
1322 {
1323 return -1;
1324 }
1325
1326 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1);
1327
1328 if (ret == 0)
1329 {
1330 odr_trig.odr_trig_nodr = val;
1331 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1);
1332 }
1333
1334 return ret;
1335 }
1336
1337 /**
1338 * @brief Configure ODR trigger. [get]
1339 *
1340 * @param ctx read / write interface definitions
1341 * @param val number of data in the reference period.
1342 * @retval interface status (MANDATORY: return 0 -> no Error)
1343 *
1344 */
lsm6dsv32x_odr_trig_cfg_get(const stmdev_ctx_t * ctx,uint8_t * val)1345 int32_t lsm6dsv32x_odr_trig_cfg_get(const stmdev_ctx_t *ctx, uint8_t *val)
1346 {
1347 lsm6dsv32x_odr_trig_cfg_t odr_trig;
1348 int32_t ret;
1349
1350 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1);
1351 *val = odr_trig.odr_trig_nodr;
1352
1353 return ret;
1354 }
1355
1356 /**
1357 * @brief Enables pulsed data-ready mode (~75 us).[set]
1358 *
1359 * @param ctx read / write interface definitions
1360 * @param val DRDY_LATCHED, DRDY_PULSED,
1361 * @retval interface status (MANDATORY: return 0 -> no Error)
1362 *
1363 */
lsm6dsv32x_data_ready_mode_set(const stmdev_ctx_t * ctx,lsm6dsv32x_data_ready_mode_t val)1364 int32_t lsm6dsv32x_data_ready_mode_set(const stmdev_ctx_t *ctx,
1365 lsm6dsv32x_data_ready_mode_t val)
1366 {
1367 lsm6dsv32x_ctrl4_t ctrl4;
1368 int32_t ret;
1369
1370 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1);
1371
1372 if (ret == 0)
1373 {
1374 ctrl4.drdy_pulsed = (uint8_t)val & 0x1U;
1375 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1);
1376 }
1377
1378 return ret;
1379 }
1380
1381 /**
1382 * @brief Enables pulsed data-ready mode (~75 us).[get]
1383 *
1384 * @param ctx read / write interface definitions
1385 * @param val DRDY_LATCHED, DRDY_PULSED,
1386 * @retval interface status (MANDATORY: return 0 -> no Error)
1387 *
1388 */
lsm6dsv32x_data_ready_mode_get(const stmdev_ctx_t * ctx,lsm6dsv32x_data_ready_mode_t * val)1389 int32_t lsm6dsv32x_data_ready_mode_get(const stmdev_ctx_t *ctx,
1390 lsm6dsv32x_data_ready_mode_t *val)
1391 {
1392 lsm6dsv32x_ctrl4_t ctrl4;
1393 int32_t ret;
1394
1395 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1);
1396
1397 switch (ctrl4.drdy_pulsed)
1398 {
1399 case LSM6DSV32X_DRDY_LATCHED:
1400 *val = LSM6DSV32X_DRDY_LATCHED;
1401 break;
1402
1403 case LSM6DSV32X_DRDY_PULSED:
1404 *val = LSM6DSV32X_DRDY_PULSED;
1405 break;
1406
1407 default:
1408 *val = LSM6DSV32X_DRDY_LATCHED;
1409 break;
1410 }
1411
1412 return ret;
1413 }
1414
1415 /**
1416 * @brief Enables interrupt.[set]
1417 *
1418 * @param ctx read / write interface definitions
1419 * @param val enable/disable, latched/pulsed
1420 * @retval interface status (MANDATORY: return 0 -> no Error)
1421 *
1422 */
lsm6dsv32x_interrupt_enable_set(const stmdev_ctx_t * ctx,lsm6dsv32x_interrupt_mode_t val)1423 int32_t lsm6dsv32x_interrupt_enable_set(const stmdev_ctx_t *ctx,
1424 lsm6dsv32x_interrupt_mode_t val)
1425 {
1426 lsm6dsv32x_tap_cfg0_t cfg;
1427 lsm6dsv32x_functions_enable_t func;
1428 int32_t ret;
1429
1430 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1);
1431 func.interrupts_enable = val.enable;
1432 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1);
1433 if (ret != 0)
1434 {
1435 return ret;
1436 }
1437
1438 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&cfg, 1);
1439 cfg.lir = val.lir;
1440 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&cfg, 1);
1441
1442 return ret;
1443 }
1444
1445 /**
1446 * @brief Enables latched interrupt mode.[get]
1447 *
1448 * @param ctx read / write interface definitions
1449 * @param val enable/disable, latched/pulsed
1450 * @retval interface status (MANDATORY: return 0 -> no Error)
1451 *
1452 */
lsm6dsv32x_interrupt_enable_get(const stmdev_ctx_t * ctx,lsm6dsv32x_interrupt_mode_t * val)1453 int32_t lsm6dsv32x_interrupt_enable_get(const stmdev_ctx_t *ctx,
1454 lsm6dsv32x_interrupt_mode_t *val)
1455 {
1456 lsm6dsv32x_tap_cfg0_t cfg;
1457 lsm6dsv32x_functions_enable_t func;
1458 int32_t ret;
1459
1460 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1);
1461 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&cfg, 1);
1462 if (ret != 0)
1463 {
1464 return ret;
1465 }
1466
1467 val->enable = func.interrupts_enable;
1468 val->lir = cfg.lir;
1469
1470 return ret;
1471 }
1472
1473 /**
1474 * @brief Gyroscope full-scale selection[set]
1475 *
1476 * @param ctx read / write interface definitions
1477 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
1478 * @retval interface status (MANDATORY: return 0 -> no Error)
1479 *
1480 */
lsm6dsv32x_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv32x_gy_full_scale_t val)1481 int32_t lsm6dsv32x_gy_full_scale_set(const stmdev_ctx_t *ctx,
1482 lsm6dsv32x_gy_full_scale_t val)
1483 {
1484 lsm6dsv32x_ctrl6_t ctrl6;
1485 int32_t ret;
1486
1487 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL6, (uint8_t *)&ctrl6, 1);
1488
1489 if (ret == 0)
1490 {
1491 ctrl6.fs_g = (uint8_t)val & 0xfu;
1492 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL6, (uint8_t *)&ctrl6, 1);
1493 }
1494
1495 return ret;
1496 }
1497
1498 /**
1499 * @brief Gyroscope full-scale selection[get]
1500 *
1501 * @param ctx read / write interface definitions
1502 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
1503 * @retval interface status (MANDATORY: return 0 -> no Error)
1504 *
1505 */
lsm6dsv32x_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv32x_gy_full_scale_t * val)1506 int32_t lsm6dsv32x_gy_full_scale_get(const stmdev_ctx_t *ctx,
1507 lsm6dsv32x_gy_full_scale_t *val)
1508 {
1509 lsm6dsv32x_ctrl6_t ctrl6;
1510 int32_t ret;
1511
1512 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL6, (uint8_t *)&ctrl6, 1);
1513 if (ret != 0)
1514 {
1515 return ret;
1516 }
1517
1518 switch (ctrl6.fs_g)
1519 {
1520 case LSM6DSV32X_125dps:
1521 *val = LSM6DSV32X_125dps;
1522 break;
1523
1524 case LSM6DSV32X_250dps:
1525 *val = LSM6DSV32X_250dps;
1526 break;
1527
1528 case LSM6DSV32X_500dps:
1529 *val = LSM6DSV32X_500dps;
1530 break;
1531
1532 case LSM6DSV32X_1000dps:
1533 *val = LSM6DSV32X_1000dps;
1534 break;
1535
1536 case LSM6DSV32X_2000dps:
1537 *val = LSM6DSV32X_2000dps;
1538 break;
1539
1540 case LSM6DSV32X_4000dps:
1541 *val = LSM6DSV32X_4000dps;
1542 break;
1543
1544 default:
1545 *val = LSM6DSV32X_125dps;
1546 break;
1547 }
1548
1549 return ret;
1550 }
1551
1552 /**
1553 * @brief Accelerometer full-scale selection.[set]
1554 *
1555 * @param ctx read / write interface definitions
1556 * @param val lsm6dsv32x_xl_full_scale_t
1557 * @retval interface status (MANDATORY: return 0 -> no Error)
1558 *
1559 */
lsm6dsv32x_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv32x_xl_full_scale_t val)1560 int32_t lsm6dsv32x_xl_full_scale_set(const stmdev_ctx_t *ctx,
1561 lsm6dsv32x_xl_full_scale_t val)
1562 {
1563 lsm6dsv32x_ctrl8_t ctrl8;
1564 int32_t ret;
1565
1566 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL8, (uint8_t *)&ctrl8, 1);
1567
1568 if (ret == 0)
1569 {
1570 ctrl8.fs_xl = (uint8_t)val & 0x3U;
1571 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL8, (uint8_t *)&ctrl8, 1);
1572 }
1573
1574 return ret;
1575 }
1576
1577 /**
1578 * @brief Accelerometer full-scale selection.[get]
1579 *
1580 * @param ctx read / write interface definitions
1581 * @param val lsm6dsv32x_xl_full_scale_t
1582 * @retval interface status (MANDATORY: return 0 -> no Error)
1583 *
1584 */
lsm6dsv32x_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv32x_xl_full_scale_t * val)1585 int32_t lsm6dsv32x_xl_full_scale_get(const stmdev_ctx_t *ctx,
1586 lsm6dsv32x_xl_full_scale_t *val)
1587 {
1588 lsm6dsv32x_ctrl8_t ctrl8;
1589 int32_t ret;
1590
1591 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL8, (uint8_t *)&ctrl8, 1);
1592 if (ret != 0)
1593 {
1594 return ret;
1595 }
1596
1597 switch (ctrl8.fs_xl)
1598 {
1599
1600 case LSM6DSV32X_4g:
1601 *val = LSM6DSV32X_4g;
1602 break;
1603
1604 case LSM6DSV32X_8g:
1605 *val = LSM6DSV32X_8g;
1606 break;
1607
1608 case LSM6DSV32X_16g:
1609 *val = LSM6DSV32X_16g;
1610 break;
1611
1612 case LSM6DSV32X_32g:
1613 *val = LSM6DSV32X_32g;
1614 break;
1615
1616 default:
1617 *val = LSM6DSV32X_4g;
1618 break;
1619 }
1620
1621 return ret;
1622 }
1623
1624 /**
1625 * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[set]
1626 *
1627 * @param ctx read / write interface definitions
1628 * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.
1629 * @retval interface status (MANDATORY: return 0 -> no Error)
1630 *
1631 */
lsm6dsv32x_xl_dual_channel_set(const stmdev_ctx_t * ctx,uint8_t val)1632 int32_t lsm6dsv32x_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val)
1633 {
1634 lsm6dsv32x_ctrl8_t ctrl8;
1635 int32_t ret;
1636
1637 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL8, (uint8_t *)&ctrl8, 1);
1638
1639 if (ret == 0)
1640 {
1641 ctrl8.xl_dualc_en = val;
1642 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL8, (uint8_t *)&ctrl8, 1);
1643 }
1644
1645 return ret;
1646 }
1647
1648 /**
1649 * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[get]
1650 *
1651 * @param ctx read / write interface definitions
1652 * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.
1653 * @retval interface status (MANDATORY: return 0 -> no Error)
1654 *
1655 */
lsm6dsv32x_xl_dual_channel_get(const stmdev_ctx_t * ctx,uint8_t * val)1656 int32_t lsm6dsv32x_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val)
1657 {
1658 lsm6dsv32x_ctrl8_t ctrl8;
1659 int32_t ret;
1660
1661 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL8, (uint8_t *)&ctrl8, 1);
1662 *val = ctrl8.xl_dualc_en;
1663
1664 return ret;
1665 }
1666
1667 /**
1668 * @brief Accelerometer self-test selection.[set]
1669 *
1670 * @param ctx read / write interface definitions
1671 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1672 * @retval interface status (MANDATORY: return 0 -> no Error)
1673 *
1674 */
lsm6dsv32x_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6dsv32x_xl_self_test_t val)1675 int32_t lsm6dsv32x_xl_self_test_set(const stmdev_ctx_t *ctx,
1676 lsm6dsv32x_xl_self_test_t val)
1677 {
1678 lsm6dsv32x_ctrl10_t ctrl10;
1679 int32_t ret;
1680
1681 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1);
1682
1683 if (ret == 0)
1684 {
1685 ctrl10.st_xl = (uint8_t)val & 0x3U;
1686 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1);
1687 }
1688
1689 return ret;
1690 }
1691
1692 /**
1693 * @brief Accelerometer self-test selection.[get]
1694 *
1695 * @param ctx read / write interface definitions
1696 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1697 * @retval interface status (MANDATORY: return 0 -> no Error)
1698 *
1699 */
lsm6dsv32x_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6dsv32x_xl_self_test_t * val)1700 int32_t lsm6dsv32x_xl_self_test_get(const stmdev_ctx_t *ctx,
1701 lsm6dsv32x_xl_self_test_t *val)
1702 {
1703 lsm6dsv32x_ctrl10_t ctrl10;
1704 int32_t ret;
1705
1706 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1);
1707 if (ret != 0)
1708 {
1709 return ret;
1710 }
1711
1712 switch (ctrl10.st_xl)
1713 {
1714 case LSM6DSV32X_XL_ST_DISABLE:
1715 *val = LSM6DSV32X_XL_ST_DISABLE;
1716 break;
1717
1718 case LSM6DSV32X_XL_ST_POSITIVE:
1719 *val = LSM6DSV32X_XL_ST_POSITIVE;
1720 break;
1721
1722 case LSM6DSV32X_XL_ST_NEGATIVE:
1723 *val = LSM6DSV32X_XL_ST_NEGATIVE;
1724 break;
1725
1726 default:
1727 *val = LSM6DSV32X_XL_ST_DISABLE;
1728 break;
1729 }
1730
1731 return ret;
1732 }
1733
1734 /**
1735 * @brief Gyroscope self-test selection.[set]
1736 *
1737 * @param ctx read / write interface definitions
1738 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1739 * @retval interface status (MANDATORY: return 0 -> no Error)
1740 *
1741 */
lsm6dsv32x_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dsv32x_gy_self_test_t val)1742 int32_t lsm6dsv32x_gy_self_test_set(const stmdev_ctx_t *ctx,
1743 lsm6dsv32x_gy_self_test_t val)
1744 {
1745 lsm6dsv32x_ctrl10_t ctrl10;
1746 int32_t ret;
1747
1748 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1);
1749
1750 if (ret == 0)
1751 {
1752 ctrl10.st_g = (uint8_t)val & 0x3U;
1753 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1);
1754 }
1755
1756 return ret;
1757 }
1758
1759 /**
1760 * @brief Gyroscope self-test selection.[get]
1761 *
1762 * @param ctx read / write interface definitions
1763 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1764 * @retval interface status (MANDATORY: return 0 -> no Error)
1765 *
1766 */
lsm6dsv32x_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dsv32x_gy_self_test_t * val)1767 int32_t lsm6dsv32x_gy_self_test_get(const stmdev_ctx_t *ctx,
1768 lsm6dsv32x_gy_self_test_t *val)
1769 {
1770 lsm6dsv32x_ctrl10_t ctrl10;
1771 int32_t ret;
1772
1773 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1);
1774 if (ret != 0)
1775 {
1776 return ret;
1777 }
1778
1779 switch (ctrl10.st_g)
1780 {
1781 case LSM6DSV32X_GY_ST_DISABLE:
1782 *val = LSM6DSV32X_GY_ST_DISABLE;
1783 break;
1784
1785 case LSM6DSV32X_GY_ST_POSITIVE:
1786 *val = LSM6DSV32X_GY_ST_POSITIVE;
1787 break;
1788
1789 case LSM6DSV32X_GY_ST_NEGATIVE:
1790 *val = LSM6DSV32X_GY_ST_NEGATIVE;
1791 break;
1792
1793 default:
1794 *val = LSM6DSV32X_GY_ST_DISABLE;
1795 break;
1796 }
1797
1798 return ret;
1799 }
1800
1801 /**
1802 * @brief SPI2 Accelerometer self-test selection.[set]
1803 *
1804 * @param ctx read / write interface definitions
1805 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1806 * @retval interface status (MANDATORY: return 0 -> no Error)
1807 *
1808 */
lsm6dsv32x_ois_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6dsv32x_ois_xl_self_test_t val)1809 int32_t lsm6dsv32x_ois_xl_self_test_set(const stmdev_ctx_t *ctx,
1810 lsm6dsv32x_ois_xl_self_test_t val)
1811 {
1812 lsm6dsv32x_spi2_int_ois_t spi2_int_ois;
1813 int32_t ret;
1814
1815 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1816
1817 if (ret == 0)
1818 {
1819 spi2_int_ois.st_xl_ois = ((uint8_t)val & 0x3U);
1820 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1821 }
1822
1823 return ret;
1824 }
1825
1826 /**
1827 * @brief SPI2 Accelerometer self-test selection.[get]
1828 *
1829 * @param ctx read / write interface definitions
1830 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1831 * @retval interface status (MANDATORY: return 0 -> no Error)
1832 *
1833 */
lsm6dsv32x_ois_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6dsv32x_ois_xl_self_test_t * val)1834 int32_t lsm6dsv32x_ois_xl_self_test_get(const stmdev_ctx_t *ctx,
1835 lsm6dsv32x_ois_xl_self_test_t *val)
1836 {
1837 lsm6dsv32x_spi2_int_ois_t spi2_int_ois;
1838 int32_t ret;
1839
1840 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1841 if (ret != 0)
1842 {
1843 return ret;
1844 }
1845
1846 switch (spi2_int_ois.st_xl_ois)
1847 {
1848 case LSM6DSV32X_OIS_XL_ST_DISABLE:
1849 *val = LSM6DSV32X_OIS_XL_ST_DISABLE;
1850 break;
1851
1852 case LSM6DSV32X_OIS_XL_ST_POSITIVE:
1853 *val = LSM6DSV32X_OIS_XL_ST_POSITIVE;
1854 break;
1855
1856 case LSM6DSV32X_OIS_XL_ST_NEGATIVE:
1857 *val = LSM6DSV32X_OIS_XL_ST_NEGATIVE;
1858 break;
1859
1860 default:
1861 *val = LSM6DSV32X_OIS_XL_ST_DISABLE;
1862 break;
1863 }
1864
1865 return ret;
1866 }
1867
1868 /**
1869 * @brief SPI2 Accelerometer self-test selection.[set]
1870 *
1871 * @param ctx read / write interface definitions
1872 * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, LSM6DSV32X_OIS_GY_ST_CLAMP_POS, LSM6DSV32X_OIS_GY_ST_CLAMP_NEG
1873 * @retval interface status (MANDATORY: return 0 -> no Error)
1874 *
1875 */
lsm6dsv32x_ois_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dsv32x_ois_gy_self_test_t val)1876 int32_t lsm6dsv32x_ois_gy_self_test_set(const stmdev_ctx_t *ctx,
1877 lsm6dsv32x_ois_gy_self_test_t val)
1878 {
1879 lsm6dsv32x_spi2_int_ois_t spi2_int_ois;
1880 int32_t ret;
1881
1882 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1883
1884 if (ret == 0)
1885 {
1886 spi2_int_ois.st_g_ois = ((uint8_t)val & 0x3U);
1887 spi2_int_ois.st_ois_clampdis = ((uint8_t)val & 0x04U) >> 2;
1888 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1889 }
1890
1891 return ret;
1892 }
1893
1894 /**
1895 * @brief SPI2 Accelerometer self-test selection.[get]
1896 *
1897 * @param ctx read / write interface definitions
1898 * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, LSM6DSV32X_OIS_GY_ST_CLAMP_POS, LSM6DSV32X_OIS_GY_ST_CLAMP_NEG
1899 * @retval interface status (MANDATORY: return 0 -> no Error)
1900 *
1901 */
lsm6dsv32x_ois_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dsv32x_ois_gy_self_test_t * val)1902 int32_t lsm6dsv32x_ois_gy_self_test_get(const stmdev_ctx_t *ctx,
1903 lsm6dsv32x_ois_gy_self_test_t *val)
1904 {
1905 lsm6dsv32x_spi2_int_ois_t spi2_int_ois;
1906 int32_t ret;
1907
1908 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1909 if (ret != 0)
1910 {
1911 return ret;
1912 }
1913
1914 switch (spi2_int_ois.st_g_ois)
1915 {
1916 case LSM6DSV32X_OIS_GY_ST_DISABLE:
1917 *val = LSM6DSV32X_OIS_GY_ST_DISABLE;
1918 break;
1919
1920 case LSM6DSV32X_OIS_GY_ST_POSITIVE:
1921 *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV32X_OIS_GY_ST_CLAMP_POS :
1922 LSM6DSV32X_OIS_GY_ST_POSITIVE;
1923 break;
1924
1925 case LSM6DSV32X_OIS_GY_ST_NEGATIVE:
1926 *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV32X_OIS_GY_ST_CLAMP_NEG :
1927 LSM6DSV32X_OIS_GY_ST_NEGATIVE;
1928 break;
1929
1930 default:
1931 *val = LSM6DSV32X_OIS_GY_ST_DISABLE;
1932 break;
1933 }
1934
1935 return ret;
1936 }
1937
1938 /**
1939 * @defgroup interrupt_pins
1940 * @brief This section groups all the functions that manage
1941 * interrupt pins
1942 * @{
1943 *
1944 */
1945
1946 /**
1947 * @brief Select the signal that need to route on int1 pad[set]
1948 *
1949 * @param ctx Read / write interface definitions.(ptr)
1950 * @param val the signals to route on int1 pin.
1951 * @retval Interface status (MANDATORY: return 0 -> no Error).
1952 *
1953 */
lsm6dsv32x_pin_int1_route_set(const stmdev_ctx_t * ctx,lsm6dsv32x_pin_int_route_t * val)1954 int32_t lsm6dsv32x_pin_int1_route_set(const stmdev_ctx_t *ctx,
1955 lsm6dsv32x_pin_int_route_t *val)
1956 {
1957 lsm6dsv32x_int1_ctrl_t int1_ctrl;
1958 lsm6dsv32x_md1_cfg_t md1_cfg;
1959 int32_t ret;
1960
1961 /* not available on INT1 */
1962 if (val->drdy_temp == 1)
1963 {
1964 return -1;
1965 }
1966
1967 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
1968 if (ret != 0)
1969 {
1970 return ret;
1971 }
1972
1973 int1_ctrl.int1_drdy_xl = val->drdy_xl;
1974 int1_ctrl.int1_drdy_g = val->drdy_g;
1975 int1_ctrl.int1_fifo_th = val->fifo_th;
1976 int1_ctrl.int1_fifo_ovr = val->fifo_ovr;
1977 int1_ctrl.int1_fifo_full = val->fifo_full;
1978 int1_ctrl.int1_cnt_bdr = val->cnt_bdr;
1979
1980 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
1981 if (ret != 0)
1982 {
1983 return ret;
1984 }
1985
1986 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1987 if (ret != 0)
1988 {
1989 return ret;
1990 }
1991
1992 md1_cfg.int1_shub = val->shub;
1993 md1_cfg.int1_emb_func = val->emb_func;
1994 md1_cfg.int1_6d = val->sixd;
1995 md1_cfg.int1_single_tap = val->single_tap;
1996 md1_cfg.int1_double_tap = val->double_tap;
1997 md1_cfg.int1_wu = val->wakeup;
1998 md1_cfg.int1_ff = val->freefall;
1999 md1_cfg.int1_sleep_change = val->sleep_change;
2000
2001 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MD1_CFG, (uint8_t *)&md1_cfg, 1);
2002
2003 return ret;
2004 }
2005
2006 /**
2007 * @brief Select the signal that need to route on int1 pad.[get]
2008 *
2009 * @param ctx Read / write interface definitions.(ptr)
2010 * @param val the signals that are routed on int1 pin.(ptr)
2011 * @retval Interface status (MANDATORY: return 0 -> no Error).
2012 *
2013 */
lsm6dsv32x_pin_int1_route_get(const stmdev_ctx_t * ctx,lsm6dsv32x_pin_int_route_t * val)2014 int32_t lsm6dsv32x_pin_int1_route_get(const stmdev_ctx_t *ctx,
2015 lsm6dsv32x_pin_int_route_t *val)
2016 {
2017 lsm6dsv32x_int1_ctrl_t int1_ctrl;
2018 lsm6dsv32x_md1_cfg_t md1_cfg;
2019 int32_t ret;
2020
2021 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
2022 if (ret != 0)
2023 {
2024 return ret;
2025 }
2026
2027 val->drdy_xl = int1_ctrl.int1_drdy_xl;
2028 val->drdy_g = int1_ctrl.int1_drdy_g;
2029 val->fifo_th = int1_ctrl.int1_fifo_th;
2030 val->fifo_ovr = int1_ctrl.int1_fifo_ovr;
2031 val->fifo_full = int1_ctrl.int1_fifo_full;
2032 val->cnt_bdr = int1_ctrl.int1_cnt_bdr;
2033
2034 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MD1_CFG, (uint8_t *)&md1_cfg, 1);
2035 if (ret != 0)
2036 {
2037 return ret;
2038 }
2039
2040 val->shub = md1_cfg.int1_shub;
2041 val->emb_func = md1_cfg.int1_emb_func;
2042 val->sixd = md1_cfg.int1_6d;
2043 val->single_tap = md1_cfg.int1_single_tap;
2044 val->double_tap = md1_cfg.int1_double_tap;
2045 val->wakeup = md1_cfg.int1_wu;
2046 val->freefall = md1_cfg.int1_ff;
2047 val->sleep_change = md1_cfg.int1_sleep_change;
2048
2049 return ret;
2050 }
2051
2052 /**
2053 * @brief Select the signal that need to route on int2 pad[set]
2054 *
2055 * @param ctx Read / write interface definitions.(ptr)
2056 * @param val the signals to route on int2 pin.
2057 * @retval Interface status (MANDATORY: return 0 -> no Error).
2058 *
2059 */
lsm6dsv32x_pin_int2_route_set(const stmdev_ctx_t * ctx,lsm6dsv32x_pin_int_route_t * val)2060 int32_t lsm6dsv32x_pin_int2_route_set(const stmdev_ctx_t *ctx,
2061 lsm6dsv32x_pin_int_route_t *val)
2062 {
2063 lsm6dsv32x_int2_ctrl_t int2_ctrl;
2064 lsm6dsv32x_ctrl4_t ctrl4;
2065 lsm6dsv32x_ctrl7_t ctrl7;
2066 lsm6dsv32x_md2_cfg_t md2_cfg;
2067 int32_t ret;
2068
2069 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2070 if (ret != 0)
2071 {
2072 return ret;
2073 }
2074
2075 int2_ctrl.int2_drdy_xl = val->drdy_xl;
2076 int2_ctrl.int2_drdy_g = val->drdy_g;
2077 int2_ctrl.int2_fifo_th = val->fifo_th;
2078 int2_ctrl.int2_fifo_ovr = val->fifo_ovr;
2079 int2_ctrl.int2_fifo_full = val->fifo_full;
2080 int2_ctrl.int2_cnt_bdr = val->cnt_bdr;
2081 int2_ctrl.int2_drdy_g_eis = val->drdy_g_eis;
2082 int2_ctrl.int2_emb_func_endop = val->emb_func_endop;
2083
2084 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2085 if (ret != 0)
2086 {
2087 return ret;
2088 }
2089
2090 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1);
2091 ctrl4.int2_drdy_temp = val->drdy_temp;
2092 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1);
2093 if (ret != 0)
2094 {
2095 return ret;
2096 }
2097
2098 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1);
2099 ctrl7.int2_drdy_ah_qvar = val->drdy_ah_qvar;
2100 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1);
2101 if (ret != 0)
2102 {
2103 return ret;
2104 }
2105
2106 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2107 if (ret != 0)
2108 {
2109 return ret;
2110 }
2111
2112 md2_cfg.int2_timestamp = val->timestamp;
2113 md2_cfg.int2_emb_func = val->emb_func;
2114 md2_cfg.int2_6d = val->sixd;
2115 md2_cfg.int2_single_tap = val->single_tap;
2116 md2_cfg.int2_double_tap = val->double_tap;
2117 md2_cfg.int2_wu = val->wakeup;
2118 md2_cfg.int2_ff = val->freefall;
2119 md2_cfg.int2_sleep_change = val->sleep_change;
2120
2121 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2122
2123 return ret;
2124 }
2125
2126 /**
2127 * @brief Select the signal that need to route on int2 pad.[get]
2128 *
2129 * @param ctx Read / write interface definitions.(ptr)
2130 * @param val the signals that are routed on int2 pin.(ptr)
2131 * @retval Interface status (MANDATORY: return 0 -> no Error).
2132 *
2133 */
lsm6dsv32x_pin_int2_route_get(const stmdev_ctx_t * ctx,lsm6dsv32x_pin_int_route_t * val)2134 int32_t lsm6dsv32x_pin_int2_route_get(const stmdev_ctx_t *ctx,
2135 lsm6dsv32x_pin_int_route_t *val)
2136 {
2137 lsm6dsv32x_int2_ctrl_t int2_ctrl;
2138 lsm6dsv32x_ctrl4_t ctrl4;
2139 lsm6dsv32x_ctrl7_t ctrl7;
2140 lsm6dsv32x_md2_cfg_t md2_cfg;
2141 int32_t ret;
2142
2143 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2144 if (ret != 0)
2145 {
2146 return ret;
2147 }
2148
2149 val->drdy_xl = int2_ctrl.int2_drdy_xl;
2150 val->drdy_g = int2_ctrl.int2_drdy_g;
2151 val->fifo_th = int2_ctrl.int2_fifo_th;
2152 val->fifo_ovr = int2_ctrl.int2_fifo_ovr;
2153 val->fifo_full = int2_ctrl.int2_fifo_full;
2154 val->cnt_bdr = int2_ctrl.int2_cnt_bdr;
2155 val->drdy_g_eis = int2_ctrl.int2_drdy_g_eis;
2156 val->emb_func_endop = int2_ctrl.int2_emb_func_endop;
2157
2158 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1);
2159 if (ret != 0)
2160 {
2161 return ret;
2162 }
2163
2164 val->drdy_temp = ctrl4.int2_drdy_temp;
2165
2166 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1);
2167 if (ret != 0)
2168 {
2169 return ret;
2170 }
2171
2172 val->drdy_ah_qvar = ctrl7.int2_drdy_ah_qvar;
2173
2174 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2175 if (ret != 0)
2176 {
2177 return ret;
2178 }
2179
2180 val->timestamp = md2_cfg.int2_timestamp;
2181 val->emb_func = md2_cfg.int2_emb_func;
2182 val->sixd = md2_cfg.int2_6d;
2183 val->single_tap = md2_cfg.int2_single_tap;
2184 val->double_tap = md2_cfg.int2_double_tap;
2185 val->wakeup = md2_cfg.int2_wu;
2186 val->freefall = md2_cfg.int2_ff;
2187 val->sleep_change = md2_cfg.int2_sleep_change;
2188
2189 return ret;
2190 }
2191
2192 /**
2193 * @brief routes embedded func interrupt signals on INT 1 pin.[set]
2194 *
2195 * @param ctx read / write interface definitions
2196 * @param val routes embedded func interrupt signals on INT 1 pin.
2197 * @retval interface status (MANDATORY: return 0 -> no Error)
2198 *
2199 */
lsm6dsv32x_emb_pin_int1_route_set(const stmdev_ctx_t * ctx,const lsm6dsv32x_emb_pin_int_route_t * val)2200 int32_t lsm6dsv32x_emb_pin_int1_route_set(const stmdev_ctx_t *ctx,
2201 const lsm6dsv32x_emb_pin_int_route_t *val)
2202 {
2203 lsm6dsv32x_emb_func_int1_t emb_func_int1;
2204 lsm6dsv32x_md1_cfg_t md1_cfg;
2205 int32_t ret;
2206
2207 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
2208 if (ret == 0)
2209 {
2210 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
2211 }
2212
2213 if (ret == 0)
2214 {
2215 emb_func_int1.int1_tilt = val->tilt;
2216 emb_func_int1.int1_sig_mot = val->sig_mot;
2217 emb_func_int1.int1_step_detector = val->step_det;
2218 emb_func_int1.int1_fsm_lc = val->fsm_lc;
2219
2220 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
2221 }
2222 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
2223
2224 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MD1_CFG, (uint8_t *)&md1_cfg, 1);
2225 if (ret == 0)
2226 {
2227 md1_cfg.int1_emb_func = 1;
2228 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MD1_CFG, (uint8_t *)&md1_cfg, 1);
2229 }
2230
2231 return ret;
2232 }
2233
2234 /**
2235 * @brief routes embedded func interrupt signals on INT 1 pin.[get]
2236 *
2237 * @param ctx read / write interface definitions
2238 * @param val routes embedded func interrupt signals on INT 1 pin.
2239 * @retval interface status (MANDATORY: return 0 -> no Error)
2240 *
2241 */
lsm6dsv32x_emb_pin_int1_route_get(const stmdev_ctx_t * ctx,lsm6dsv32x_emb_pin_int_route_t * val)2242 int32_t lsm6dsv32x_emb_pin_int1_route_get(const stmdev_ctx_t *ctx,
2243 lsm6dsv32x_emb_pin_int_route_t *val)
2244 {
2245 lsm6dsv32x_emb_func_int1_t emb_func_int1;
2246 int32_t ret;
2247
2248 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
2249 if (ret == 0)
2250 {
2251 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
2252 }
2253
2254 if (ret == 0)
2255 {
2256 val->tilt = emb_func_int1.int1_tilt;
2257 val->sig_mot = emb_func_int1.int1_sig_mot;
2258 val->step_det = emb_func_int1.int1_step_detector;
2259 val->fsm_lc = emb_func_int1.int1_fsm_lc;
2260 }
2261 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
2262
2263 return ret;
2264 }
2265
2266 /**
2267 * @brief routes embedded func interrupt signals on INT 2 pin.[set]
2268 *
2269 * @param ctx read / write interface definitions
2270 * @param val routes embedded func interrupt signals on INT 2 pin.
2271 * @retval interface status (MANDATORY: return 0 -> no Error)
2272 *
2273 */
lsm6dsv32x_emb_pin_int2_route_set(const stmdev_ctx_t * ctx,const lsm6dsv32x_emb_pin_int_route_t * val)2274 int32_t lsm6dsv32x_emb_pin_int2_route_set(const stmdev_ctx_t *ctx,
2275 const lsm6dsv32x_emb_pin_int_route_t *val)
2276 {
2277 lsm6dsv32x_emb_func_int2_t emb_func_int2;
2278 lsm6dsv32x_md2_cfg_t md2_cfg;
2279 int32_t ret;
2280
2281 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
2282 if (ret == 0)
2283 {
2284 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
2285 }
2286
2287 if (ret == 0)
2288 {
2289 emb_func_int2.int2_tilt = val->tilt;
2290 emb_func_int2.int2_sig_mot = val->sig_mot;
2291 emb_func_int2.int2_step_detector = val->step_det;
2292 emb_func_int2.int2_fsm_lc = val->fsm_lc;
2293
2294 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
2295 }
2296 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
2297
2298 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2299 if (ret == 0)
2300 {
2301 md2_cfg.int2_emb_func = 1;
2302 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2303 }
2304
2305 return ret;
2306 }
2307
2308 /**
2309 * @brief routes embedded func interrupt signals on INT 2 pin.[get]
2310 *
2311 * @param ctx read / write interface definitions
2312 * @param val routes embedded func interrupt signals on INT 2 pin.
2313 * @retval interface status (MANDATORY: return 0 -> no Error)
2314 *
2315 */
lsm6dsv32x_emb_pin_int2_route_get(const stmdev_ctx_t * ctx,lsm6dsv32x_emb_pin_int_route_t * val)2316 int32_t lsm6dsv32x_emb_pin_int2_route_get(const stmdev_ctx_t *ctx,
2317 lsm6dsv32x_emb_pin_int_route_t *val)
2318 {
2319 lsm6dsv32x_emb_func_int2_t emb_func_int2;
2320 int32_t ret;
2321
2322 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
2323 if (ret == 0)
2324 {
2325 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
2326 }
2327
2328 if (ret == 0)
2329 {
2330 val->tilt = emb_func_int2.int2_tilt;
2331 val->sig_mot = emb_func_int2.int2_sig_mot;
2332 val->step_det = emb_func_int2.int2_step_detector;
2333 val->fsm_lc = emb_func_int2.int2_fsm_lc;
2334 }
2335 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
2336
2337 return ret;
2338 }
2339
2340 /**
2341 * @brief Embedded Interrupt configuration mode.[set]
2342 *
2343 * @param ctx read / write interface definitions
2344 * @param val INT_PULSED, INT_LATCHED
2345 * @retval interface status (MANDATORY: return 0 -> no Error)
2346 *
2347 */
lsm6dsv32x_embedded_int_cfg_set(const stmdev_ctx_t * ctx,lsm6dsv32x_embedded_int_config_t val)2348 int32_t lsm6dsv32x_embedded_int_cfg_set(const stmdev_ctx_t *ctx,
2349 lsm6dsv32x_embedded_int_config_t val)
2350 {
2351 lsm6dsv32x_page_rw_t page_rw;
2352 int32_t ret;
2353
2354 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
2355 if (ret == 0)
2356 {
2357 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1);
2358
2359 switch (val)
2360 {
2361 case LSM6DSV32X_INT_LATCH_DISABLE:
2362 page_rw.emb_func_lir = 0;
2363 break;
2364
2365 case LSM6DSV32X_INT_LATCH_ENABLE:
2366 default:
2367 page_rw.emb_func_lir = 1;
2368 break;
2369 }
2370
2371 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1);
2372 }
2373
2374 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
2375
2376 return ret;
2377 }
2378
2379 /**
2380 * @brief Interrupt configuration mode.[get]
2381 *
2382 * @param ctx read / write interface definitions
2383 * @param val INT_DISABLED, INT_PULSED, INT_LATCHED
2384 * @retval interface status (MANDATORY: return 0 -> no Error)
2385 *
2386 */
lsm6dsv32x_embedded_int_cfg_get(const stmdev_ctx_t * ctx,lsm6dsv32x_embedded_int_config_t * val)2387 int32_t lsm6dsv32x_embedded_int_cfg_get(const stmdev_ctx_t *ctx,
2388 lsm6dsv32x_embedded_int_config_t *val)
2389 {
2390 lsm6dsv32x_page_rw_t page_rw;
2391 int32_t ret;
2392
2393 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
2394 if (ret == 0)
2395 {
2396 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1);
2397
2398 if (page_rw.emb_func_lir == 0U)
2399 {
2400 *val = LSM6DSV32X_INT_LATCH_DISABLE;
2401 }
2402 else
2403 {
2404 *val = LSM6DSV32X_INT_LATCH_ENABLE;
2405 }
2406 }
2407
2408 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
2409
2410 return ret;
2411 }
2412
2413 /**
2414 * @brief Get the status of embedded functions.[get]
2415 *
2416 * @param ctx read / write interface definitions
2417 * @param val lsm6dsv32x_embedded_status_t ptr
2418 * @retval interface status (MANDATORY: return 0 -> no Error)
2419 *
2420 */
lsm6dsv32x_embedded_status_get(const stmdev_ctx_t * ctx,lsm6dsv32x_embedded_status_t * val)2421 int32_t lsm6dsv32x_embedded_status_get(const stmdev_ctx_t *ctx,
2422 lsm6dsv32x_embedded_status_t *val)
2423 {
2424 lsm6dsv32x_emb_func_status_mainpage_t emb_func_status;
2425 lsm6dsv32x_emb_func_src_t emb_func_src;
2426 int32_t ret;
2427
2428 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_STATUS_MAINPAGE, (uint8_t *)&emb_func_status, 1);
2429 if (ret != 0)
2430 {
2431 return ret;
2432 }
2433
2434 val->step_detector = emb_func_status.is_step_det;
2435 val->tilt = emb_func_status.is_tilt;
2436 val->sig_mot = emb_func_status.is_sigmot;
2437 val->fsm_lc = emb_func_status.is_fsm_lc;
2438
2439 /* embedded func */
2440 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
2441 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
2442 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
2443 if (ret != 0)
2444 {
2445 return ret;
2446 }
2447
2448 val->step_count_inc = emb_func_src.stepcounter_bit_set;
2449 val->step_count_overflow = emb_func_src.step_overflow;
2450 val->step_on_delta_time = emb_func_src.step_count_delta_ia;
2451 val->step_detector = emb_func_src.step_detected;
2452
2453 return ret;
2454 }
2455
2456 /**
2457 * @}
2458 *
2459 */
2460
2461 /**
2462 * @brief Get the status of all the interrupt sources.[get]
2463 *
2464 * @param ctx read / write interface definitions
2465 * @param val Get the status of all the interrupt sources.
2466 * @retval interface status (MANDATORY: return 0 -> no Error)
2467 *
2468 */
lsm6dsv32x_all_sources_get(const stmdev_ctx_t * ctx,lsm6dsv32x_all_sources_t * val)2469 int32_t lsm6dsv32x_all_sources_get(const stmdev_ctx_t *ctx,
2470 lsm6dsv32x_all_sources_t *val)
2471 {
2472 lsm6dsv32x_emb_func_status_mainpage_t emb_func_status_mainpage;
2473 lsm6dsv32x_emb_func_exec_status_t emb_func_exec_status;
2474 lsm6dsv32x_fsm_status_mainpage_t fsm_status_mainpage;
2475 lsm6dsv32x_mlc_status_mainpage_t mlc_status_mainpage;
2476 lsm6dsv32x_functions_enable_t functions_enable;
2477 lsm6dsv32x_emb_func_src_t emb_func_src;
2478 lsm6dsv32x_fifo_status2_t fifo_status2;
2479 lsm6dsv32x_all_int_src_t all_int_src;
2480 lsm6dsv32x_wake_up_src_t wake_up_src;
2481 lsm6dsv32x_status_reg_t status_reg;
2482 lsm6dsv32x_d6d_src_t d6d_src;
2483 lsm6dsv32x_tap_src_t tap_src;
2484 lsm6dsv32x_ui_status_reg_ois_t status_reg_ois;
2485 lsm6dsv32x_status_master_t status_shub;
2486 uint8_t buff[8];
2487 int32_t ret;
2488
2489 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
2490 functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE;
2491 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
2492 if (ret != 0)
2493 {
2494 return ret;
2495 }
2496
2497 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_STATUS1, (uint8_t *)&buff, 4);
2498 if (ret != 0)
2499 {
2500 return ret;
2501 }
2502
2503 bytecpy((uint8_t *)&fifo_status2, &buff[1]);
2504 bytecpy((uint8_t *)&all_int_src, &buff[2]);
2505 bytecpy((uint8_t *)&status_reg, &buff[3]);
2506
2507 val->fifo_ovr = fifo_status2.fifo_ovr_ia;
2508 val->fifo_bdr = fifo_status2.counter_bdr_ia;
2509 val->fifo_full = fifo_status2.fifo_full_ia;
2510 val->fifo_th = fifo_status2.fifo_wtm_ia;
2511
2512 val->free_fall = all_int_src.ff_ia;
2513 val->wake_up = all_int_src.wu_ia;
2514 val->six_d = all_int_src.d6d_ia;
2515
2516 val->drdy_xl = status_reg.xlda;
2517 val->drdy_gy = status_reg.gda;
2518 val->drdy_temp = status_reg.tda;
2519 val->drdy_ah_qvar = status_reg.ah_qvarda;
2520 val->drdy_eis = status_reg.gda_eis;
2521 val->drdy_ois = status_reg.ois_drdy;
2522 val->timestamp = status_reg.timestamp_endcount;
2523
2524 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
2525 functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE;
2526 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
2527 if (ret != 0)
2528 {
2529 return ret;
2530 }
2531
2532 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_STATUS_REG_OIS, (uint8_t *)&buff, 8);
2533 if (ret != 0)
2534 {
2535 return ret;
2536 }
2537
2538 bytecpy((uint8_t *)&status_reg_ois, &buff[0]);
2539 bytecpy((uint8_t *)&wake_up_src, &buff[1]);
2540 bytecpy((uint8_t *)&tap_src, &buff[2]);
2541 bytecpy((uint8_t *)&d6d_src, &buff[3]);
2542 bytecpy((uint8_t *)&emb_func_status_mainpage, &buff[5]);
2543 bytecpy((uint8_t *)&fsm_status_mainpage, &buff[6]);
2544 bytecpy((uint8_t *)&mlc_status_mainpage, &buff[7]);
2545
2546 val->gy_settling = status_reg_ois.gyro_settling;
2547 val->sleep_change = wake_up_src.sleep_change_ia;
2548 val->wake_up_x = wake_up_src.x_wu;
2549 val->wake_up_y = wake_up_src.y_wu;
2550 val->wake_up_z = wake_up_src.z_wu;
2551 val->sleep_state = wake_up_src.sleep_state;
2552
2553 val->tap_x = tap_src.x_tap;
2554 val->tap_y = tap_src.y_tap;
2555 val->tap_z = tap_src.z_tap;
2556 val->tap_sign = tap_src.tap_sign;
2557 val->double_tap = tap_src.double_tap;
2558 val->single_tap = tap_src.single_tap;
2559
2560 val->six_d_zl = d6d_src.zl;
2561 val->six_d_zh = d6d_src.zh;
2562 val->six_d_yl = d6d_src.yl;
2563 val->six_d_yh = d6d_src.yh;
2564 val->six_d_xl = d6d_src.xl;
2565 val->six_d_xh = d6d_src.xh;
2566
2567 val->step_detector = emb_func_status_mainpage.is_step_det;
2568 val->tilt = emb_func_status_mainpage.is_tilt;
2569 val->sig_mot = emb_func_status_mainpage.is_sigmot;
2570 val->fsm_lc = emb_func_status_mainpage.is_fsm_lc;
2571
2572 val->fsm1 = fsm_status_mainpage.is_fsm1;
2573 val->fsm2 = fsm_status_mainpage.is_fsm2;
2574 val->fsm3 = fsm_status_mainpage.is_fsm3;
2575 val->fsm4 = fsm_status_mainpage.is_fsm4;
2576 val->fsm5 = fsm_status_mainpage.is_fsm5;
2577 val->fsm6 = fsm_status_mainpage.is_fsm6;
2578 val->fsm7 = fsm_status_mainpage.is_fsm7;
2579 val->fsm8 = fsm_status_mainpage.is_fsm8;
2580
2581 val->mlc1 = mlc_status_mainpage.is_mlc1;
2582 val->mlc2 = mlc_status_mainpage.is_mlc2;
2583 val->mlc3 = mlc_status_mainpage.is_mlc3;
2584 val->mlc4 = mlc_status_mainpage.is_mlc4;
2585
2586 /* embedded func */
2587 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
2588 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status,
2589 1);
2590 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
2591 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
2592 if (ret != 0)
2593 {
2594 return ret;
2595 }
2596
2597 val->emb_func_stand_by = emb_func_exec_status.emb_func_endop;
2598 val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr;
2599 val->step_count_inc = emb_func_src.stepcounter_bit_set;
2600 val->step_count_overflow = emb_func_src.step_overflow;
2601 val->step_on_delta_time = emb_func_src.step_count_delta_ia;
2602
2603 val->step_detector = emb_func_src.step_detected;
2604
2605 /* sensor hub */
2606 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_STATUS_MASTER_MAINPAGE, (uint8_t *)&status_shub, 1);
2607 if (ret != 0)
2608 {
2609 return ret;
2610 }
2611
2612 val->sh_endop = status_shub.sens_hub_endop;
2613 val->sh_wr_once = status_shub.wr_once_done;
2614 val->sh_slave3_nack = status_shub.slave3_nack;
2615 val->sh_slave2_nack = status_shub.slave2_nack;
2616 val->sh_slave1_nack = status_shub.slave1_nack;
2617 val->sh_slave0_nack = status_shub.slave0_nack;
2618
2619 return ret;
2620 }
2621
lsm6dsv32x_flag_data_ready_get(const stmdev_ctx_t * ctx,lsm6dsv32x_data_ready_t * val)2622 int32_t lsm6dsv32x_flag_data_ready_get(const stmdev_ctx_t *ctx,
2623 lsm6dsv32x_data_ready_t *val)
2624 {
2625 lsm6dsv32x_status_reg_t status;
2626 int32_t ret;
2627
2628 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_STATUS_REG, (uint8_t *)&status, 1);
2629 if (ret != 0)
2630 {
2631 return ret;
2632 }
2633
2634 val->drdy_xl = status.xlda;
2635 val->drdy_gy = status.gda;
2636 val->drdy_temp = status.tda;
2637
2638 return ret;
2639 }
2640
2641 /**
2642 * @brief Mask status bit reset[set]
2643 *
2644 * @param ctx read / write interface definitions
2645 * @param val Mask to prevent status bit being reset
2646 * @retval interface status (MANDATORY: return 0 -> no Error)
2647 *
2648 */
lsm6dsv32x_int_ack_mask_set(const stmdev_ctx_t * ctx,uint8_t val)2649 int32_t lsm6dsv32x_int_ack_mask_set(const stmdev_ctx_t *ctx, uint8_t val)
2650 {
2651 int32_t ret;
2652
2653 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_INT_ACK_MASK, &val, 1);
2654
2655 return ret;
2656 }
2657
2658 /**
2659 * @brief Mask status bit reset[get]
2660 *
2661 * @param ctx read / write interface definitions
2662 * @param val Mask to prevent status bit being reset
2663 * @retval interface status (MANDATORY: return 0 -> no Error)
2664 *
2665 */
lsm6dsv32x_int_ack_mask_get(const stmdev_ctx_t * ctx,uint8_t * val)2666 int32_t lsm6dsv32x_int_ack_mask_get(const stmdev_ctx_t *ctx, uint8_t *val)
2667 {
2668 int32_t ret;
2669
2670 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INT_ACK_MASK, val, 1);
2671
2672 return ret;
2673 }
2674
2675 /**
2676 * @brief Temperature data output register[get]
2677 *
2678 * @param ctx read / write interface definitions
2679 * @param val Temperature data output register
2680 * @retval interface status (MANDATORY: return 0 -> no Error)
2681 *
2682 */
lsm6dsv32x_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2683 int32_t lsm6dsv32x_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2684 {
2685 uint8_t buff[2];
2686 int32_t ret;
2687
2688 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_OUT_TEMP_L, &buff[0], 2);
2689 if (ret != 0)
2690 {
2691 return ret;
2692 }
2693
2694 *val = (int16_t)buff[1];
2695 *val = (*val * 256) + (int16_t)buff[0];
2696
2697 return ret;
2698 }
2699
2700 /**
2701 * @brief Angular rate sensor.[get]
2702 *
2703 * @param ctx read / write interface definitions
2704 * @param val Angular rate sensor.
2705 * @retval interface status (MANDATORY: return 0 -> no Error)
2706 *
2707 */
lsm6dsv32x_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2708 int32_t lsm6dsv32x_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2709 {
2710 uint8_t buff[6];
2711 int32_t ret;
2712
2713 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_OUTX_L_G, &buff[0], 6);
2714 if (ret != 0)
2715 {
2716 return ret;
2717 }
2718
2719 val[0] = (int16_t)buff[1];
2720 val[0] = (val[0] * 256) + (int16_t)buff[0];
2721 val[1] = (int16_t)buff[3];
2722 val[1] = (val[1] * 256) + (int16_t)buff[2];
2723 val[2] = (int16_t)buff[5];
2724 val[2] = (val[2] * 256) + (int16_t)buff[4];
2725
2726 return ret;
2727 }
2728
2729 /**
2730 * @brief Angular rate sensor.[get]
2731 *
2732 * @param ctx read / write interface definitions
2733 * @param val OIS Angular rate sensor (thru SPI2).
2734 * @retval interface status (MANDATORY: return 0 -> no Error)
2735 *
2736 */
lsm6dsv32x_ois_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2737 int32_t lsm6dsv32x_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2738 {
2739 uint8_t buff[6];
2740 int32_t ret;
2741
2742 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SPI2_OUTX_L_G_OIS, &buff[0], 6);
2743 if (ret != 0)
2744 {
2745 return ret;
2746 }
2747
2748 val[0] = (int16_t)buff[1];
2749 val[0] = (*val * 256) + (int16_t)buff[0];
2750 val[1] = (int16_t)buff[3];
2751 val[1] = (*val * 256) + (int16_t)buff[2];
2752 val[2] = (int16_t)buff[5];
2753 val[2] = (*val * 256) + (int16_t)buff[4];
2754
2755 return ret;
2756 }
2757
2758 /**
2759 * @brief Angular rate sensor for OIS gyro or the EIS gyro channel.[get]
2760 *
2761 * @param ctx read / write interface definitions
2762 * @param val Angular rate sensor for OIS gyro or the EIS gyro channel.
2763 * @retval interface status (MANDATORY: return 0 -> no Error)
2764 *
2765 */
lsm6dsv32x_ois_eis_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2766 int32_t lsm6dsv32x_ois_eis_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2767 {
2768 uint8_t buff[6];
2769 int32_t ret;
2770
2771 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_OUTX_L_G_OIS_EIS, &buff[0], 6);
2772 if (ret != 0)
2773 {
2774 return ret;
2775 }
2776
2777 val[0] = (int16_t)buff[1];
2778 val[0] = (*val * 256) + (int16_t)buff[0];
2779 val[1] = (int16_t)buff[3];
2780 val[1] = (*val * 256) + (int16_t)buff[2];
2781 val[2] = (int16_t)buff[5];
2782 val[2] = (*val * 256) + (int16_t)buff[4];
2783
2784 return ret;
2785 }
2786
2787 /**
2788 * @brief Linear acceleration sensor.[get]
2789 *
2790 * @param ctx read / write interface definitions
2791 * @param val Linear acceleration sensor.
2792 * @retval interface status (MANDATORY: return 0 -> no Error)
2793 *
2794 */
lsm6dsv32x_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2795 int32_t lsm6dsv32x_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2796 {
2797 uint8_t buff[6];
2798 int32_t ret;
2799
2800 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_OUTX_L_A, &buff[0], 6);
2801 if (ret != 0)
2802 {
2803 return ret;
2804 }
2805
2806 val[0] = (int16_t)buff[1];
2807 val[0] = (val[0] * 256) + (int16_t)buff[0];
2808 val[1] = (int16_t)buff[3];
2809 val[1] = (val[1] * 256) + (int16_t)buff[2];
2810 val[2] = (int16_t)buff[5];
2811 val[2] = (val[2] * 256) + (int16_t)buff[4];
2812
2813 return ret;
2814 }
2815
2816 /**
2817 * @brief Linear acceleration sensor for Dual channel mode.[get]
2818 *
2819 * @param ctx read / write interface definitions
2820 * @param val Linear acceleration sensor or Dual channel mode.
2821 * @retval interface status (MANDATORY: return 0 -> no Error)
2822 *
2823 */
lsm6dsv32x_dual_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2824 int32_t lsm6dsv32x_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2825 {
2826 uint8_t buff[6];
2827 int32_t ret;
2828
2829 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_OUTX_L_A_OIS_DUALC, &buff[0], 6);
2830 if (ret != 0)
2831 {
2832 return ret;
2833 }
2834
2835 val[0] = (int16_t)buff[1];
2836 val[0] = (val[0] * 256) + (int16_t)buff[0];
2837 val[1] = (int16_t)buff[3];
2838 val[1] = (val[1] * 256) + (int16_t)buff[2];
2839 val[2] = (int16_t)buff[5];
2840 val[2] = (val[2] * 256) + (int16_t)buff[4];
2841
2842 return ret;
2843 }
2844
2845 /**
2846 * @brief ah_qvar data output register.[get]
2847 *
2848 * @param ctx read / write interface definitions
2849 * @param val ah_qvar data output register.
2850 * @retval interface status (MANDATORY: return 0 -> no Error)
2851 *
2852 */
lsm6dsv32x_ah_qvar_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2853 int32_t lsm6dsv32x_ah_qvar_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2854 {
2855 uint8_t buff[2];
2856 int32_t ret;
2857
2858 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_AH_QVAR_OUT_L, &buff[0], 2);
2859 if (ret != 0)
2860 {
2861 return ret;
2862 }
2863
2864 *val = (int16_t)buff[1];
2865 *val = (*val * 256) + (int16_t)buff[0];
2866
2867 return ret;
2868 }
2869
2870 /**
2871 * @brief Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.[get]
2872 *
2873 * @param ctx read / write interface definitions
2874 * @param val Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.
2875 * @retval interface status (MANDATORY: return 0 -> no Error)
2876 *
2877 */
lsm6dsv32x_odr_cal_reg_get(const stmdev_ctx_t * ctx,int8_t * val)2878 int32_t lsm6dsv32x_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val)
2879 {
2880 lsm6dsv32x_internal_freq_t internal_freq;
2881 int32_t ret;
2882
2883 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1);
2884 *val = (int8_t)internal_freq.freq_fine;
2885
2886 return ret;
2887 }
2888
2889 /**
2890 * @brief Write buffer in a page.[set]
2891 *
2892 * @param ctx read / write interface definitions
2893 * @param val Write buffer in a page.
2894 * @retval interface status (MANDATORY: return 0 -> no Error)
2895 *
2896 */
lsm6dsv32x_ln_pg_write(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)2897 int32_t lsm6dsv32x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address,
2898 uint8_t *buf, uint8_t len)
2899 {
2900 lsm6dsv32x_page_address_t page_address;
2901 lsm6dsv32x_page_sel_t page_sel;
2902 lsm6dsv32x_page_rw_t page_rw;
2903 uint8_t msb;
2904 uint8_t lsb;
2905 int32_t ret;
2906 uint8_t i ;
2907
2908 msb = ((uint8_t)(address >> 8) & 0x0FU);
2909 lsb = (uint8_t)address & 0xFFU;
2910
2911 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
2912 if (ret != 0)
2913 {
2914 return ret;
2915 }
2916
2917 /* set page write */
2918 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1);
2919 page_rw.page_read = PROPERTY_DISABLE;
2920 page_rw.page_write = PROPERTY_ENABLE;
2921 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1);
2922 if (ret != 0)
2923 {
2924 goto exit;
2925 }
2926
2927 /* select page */
2928 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2929 page_sel.page_sel = msb;
2930 page_sel.not_used0 = 1; // Default value
2931 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2932 if (ret != 0)
2933 {
2934 goto exit;
2935 }
2936
2937 /* set page addr */
2938 page_address.page_addr = lsb;
2939 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_ADDRESS,
2940 (uint8_t *)&page_address, 1);
2941 if (ret != 0)
2942 {
2943 goto exit;
2944 }
2945
2946 for (i = 0; ((i < len) && (ret == 0)); i++)
2947 {
2948 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_VALUE, &buf[i], 1);
2949 if (ret != 0)
2950 {
2951 goto exit;
2952 }
2953
2954 lsb++;
2955
2956 /* Check if page wrap */
2957 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
2958 {
2959 msb++;
2960 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2961 if (ret != 0)
2962 {
2963 goto exit;
2964 }
2965
2966 page_sel.page_sel = msb;
2967 page_sel.not_used0 = 1; // Default value
2968 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2969 if (ret != 0)
2970 {
2971 goto exit;
2972 }
2973 }
2974 }
2975
2976 page_sel.page_sel = 0;
2977 page_sel.not_used0 = 1;// Default value
2978 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2979 if (ret != 0)
2980 {
2981 goto exit;
2982 }
2983
2984 /* unset page write */
2985 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1);
2986 page_rw.page_read = PROPERTY_DISABLE;
2987 page_rw.page_write = PROPERTY_DISABLE;
2988 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1);
2989
2990 exit:
2991 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
2992
2993 return ret;
2994 }
2995
2996 /**
2997 * @defgroup Common
2998 * @brief This section groups common useful functions.
2999 * @{/
3000 *
3001 */
3002
3003 /**
3004 * @brief Read buffer in a page.[set]
3005 *
3006 * @param ctx read / write interface definitions
3007 * @param val Write buffer in a page.
3008 * @retval interface status (MANDATORY: return 0 -> no Error)
3009 *
3010 */
lsm6dsv32x_ln_pg_read(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)3011 int32_t lsm6dsv32x_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf,
3012 uint8_t len)
3013 {
3014 lsm6dsv32x_page_address_t page_address;
3015 lsm6dsv32x_page_sel_t page_sel;
3016 lsm6dsv32x_page_rw_t page_rw;
3017 uint8_t msb;
3018 uint8_t lsb;
3019 int32_t ret;
3020 uint8_t i ;
3021
3022 msb = ((uint8_t)(address >> 8) & 0x0FU);
3023 lsb = (uint8_t)address & 0xFFU;
3024
3025 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
3026 if (ret != 0)
3027 {
3028 return ret;
3029 }
3030
3031 /* set page write */
3032 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1);
3033 page_rw.page_read = PROPERTY_ENABLE;
3034 page_rw.page_write = PROPERTY_DISABLE;
3035 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1);
3036 if (ret != 0)
3037 {
3038 goto exit;
3039 }
3040
3041 /* select page */
3042 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1);
3043 page_sel.page_sel = msb;
3044 page_sel.not_used0 = 1; // Default value
3045 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1);
3046 if (ret != 0)
3047 {
3048 goto exit;
3049 }
3050
3051 /* set page addr */
3052 page_address.page_addr = lsb;
3053 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_ADDRESS,
3054 (uint8_t *)&page_address, 1);
3055 if (ret != 0)
3056 {
3057 goto exit;
3058 }
3059
3060 for (i = 0; ((i < len) && (ret == 0)); i++)
3061 {
3062 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_VALUE, &buf[i], 1);
3063 if (ret != 0)
3064 {
3065 goto exit;
3066 }
3067
3068 lsb++;
3069
3070 /* Check if page wrap */
3071 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
3072 {
3073 msb++;
3074 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1);
3075 if (ret != 0)
3076 {
3077 goto exit;
3078 }
3079
3080 page_sel.page_sel = msb;
3081 page_sel.not_used0 = 1; // Default value
3082 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1);
3083 if (ret != 0)
3084 {
3085 goto exit;
3086 }
3087 }
3088 }
3089
3090 page_sel.page_sel = 0;
3091 page_sel.not_used0 = 1;// Default value
3092 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_SEL, (uint8_t *)&page_sel, 1);
3093 if (ret != 0)
3094 {
3095 goto exit;
3096 }
3097
3098 /* unset page write */
3099 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1);
3100 page_rw.page_read = PROPERTY_DISABLE;
3101 page_rw.page_write = PROPERTY_DISABLE;
3102 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PAGE_RW, (uint8_t *)&page_rw, 1);
3103
3104 exit:
3105 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
3106
3107 return ret;
3108 }
3109
3110 /**
3111 * @brief Enable debug mode for embedded functions [set]
3112 *
3113 * @param ctx read / write interface definitions
3114 * @param val 0, 1
3115 * @retval interface status (MANDATORY: return 0 -> no Error)
3116 *
3117 */
lsm6dsv32x_emb_function_dbg_set(const stmdev_ctx_t * ctx,uint8_t val)3118 int32_t lsm6dsv32x_emb_function_dbg_set(const stmdev_ctx_t *ctx, uint8_t val)
3119 {
3120 lsm6dsv32x_ctrl10_t ctrl10;
3121 int32_t ret;
3122
3123 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1);
3124
3125 if (ret == 0)
3126 {
3127 ctrl10.emb_func_debug = val;
3128 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1);
3129 }
3130
3131 return ret;
3132 }
3133
3134 /**
3135 * @brief Enable debug mode for embedded functions [get]
3136 *
3137 * @param ctx read / write interface definitions
3138 * @param val 0, 1
3139 * @retval interface status (MANDATORY: return 0 -> no Error)
3140 *
3141 */
lsm6dsv32x_emb_function_dbg_get(const stmdev_ctx_t * ctx,uint8_t * val)3142 int32_t lsm6dsv32x_emb_function_dbg_get(const stmdev_ctx_t *ctx, uint8_t *val)
3143 {
3144 lsm6dsv32x_ctrl10_t ctrl10;
3145 int32_t ret;
3146
3147 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1);
3148 if (ret != 0)
3149 {
3150 return ret;
3151 }
3152
3153 *val = ctrl10.emb_func_debug;
3154
3155 return ret;
3156 }
3157
3158 /**
3159 * @}
3160 *
3161 */
3162
3163 /**
3164 * @defgroup Data ENable (DEN)
3165 * @brief This section groups all the functions concerning
3166 * DEN functionality.
3167 * @{
3168 *
3169 */
3170
3171 /**
3172 * @brief It changes the polarity of INT2 pin input trigger for data enable (DEN) or embedded functions.[set]
3173 *
3174 * @param ctx read / write interface definitions
3175 * @param val DEN_ACT_LOW, DEN_ACT_HIGH,
3176 * @retval interface status (MANDATORY: return 0 -> no Error)
3177 *
3178 */
lsm6dsv32x_den_polarity_set(const stmdev_ctx_t * ctx,lsm6dsv32x_den_polarity_t val)3179 int32_t lsm6dsv32x_den_polarity_set(const stmdev_ctx_t *ctx,
3180 lsm6dsv32x_den_polarity_t val)
3181 {
3182 lsm6dsv32x_ctrl4_t ctrl4;
3183 int32_t ret;
3184
3185 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1);
3186
3187 if (ret == 0)
3188 {
3189 ctrl4.int2_in_lh = (uint8_t)val & 0x1U;
3190 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1);
3191 }
3192
3193 return ret;
3194 }
3195
3196 /**
3197 * @brief It changes the polarity of INT2 pin input trigger for data enable (DEN) or embedded functions.[get]
3198 *
3199 * @param ctx read / write interface definitions
3200 * @param val DEN_ACT_LOW, DEN_ACT_HIGH,
3201 * @retval interface status (MANDATORY: return 0 -> no Error)
3202 *
3203 */
lsm6dsv32x_den_polarity_get(const stmdev_ctx_t * ctx,lsm6dsv32x_den_polarity_t * val)3204 int32_t lsm6dsv32x_den_polarity_get(const stmdev_ctx_t *ctx,
3205 lsm6dsv32x_den_polarity_t *val)
3206 {
3207 lsm6dsv32x_ctrl4_t ctrl4;
3208 int32_t ret;
3209
3210 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1);
3211 if (ret != 0)
3212 {
3213 return ret;
3214 }
3215
3216 switch (ctrl4.int2_in_lh)
3217 {
3218 case LSM6DSV32X_DEN_ACT_LOW:
3219 *val = LSM6DSV32X_DEN_ACT_LOW;
3220 break;
3221
3222 case LSM6DSV32X_DEN_ACT_HIGH:
3223 *val = LSM6DSV32X_DEN_ACT_HIGH;
3224 break;
3225
3226 default:
3227 *val = LSM6DSV32X_DEN_ACT_LOW;
3228 break;
3229 }
3230
3231 return ret;
3232 }
3233
3234 /**
3235 * @brief Data ENable (DEN) configuration.[set]
3236 *
3237 * @param ctx read / write interface definitions
3238 * @param val Data ENable (DEN) configuration.
3239 * @retval interface status (MANDATORY: return 0 -> no Error)
3240 *
3241 */
lsm6dsv32x_den_conf_set(const stmdev_ctx_t * ctx,lsm6dsv32x_den_conf_t val)3242 int32_t lsm6dsv32x_den_conf_set(const stmdev_ctx_t *ctx, lsm6dsv32x_den_conf_t val)
3243 {
3244 lsm6dsv32x_den_t den;
3245 int32_t ret;
3246
3247 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_DEN, (uint8_t *)&den, 1);
3248 if (ret != 0)
3249 {
3250 return ret;
3251 }
3252
3253 den.den_z = val.den_z;
3254 den.den_y = val.den_y;
3255 den.den_x = val.den_x;
3256
3257 den.lvl2_en = (uint8_t)val.mode & 0x1U;
3258 den.lvl1_en = ((uint8_t)val.mode & 0x2U) >> 1;
3259
3260 if (val.stamp_in_gy_data == PROPERTY_ENABLE && val.stamp_in_xl_data == PROPERTY_ENABLE)
3261 {
3262 den.den_xl_g = PROPERTY_DISABLE;
3263 den.den_xl_en = PROPERTY_ENABLE;
3264 }
3265 else if (val.stamp_in_gy_data == PROPERTY_ENABLE && val.stamp_in_xl_data == PROPERTY_DISABLE)
3266 {
3267 den.den_xl_g = PROPERTY_DISABLE;
3268 den.den_xl_en = PROPERTY_DISABLE;
3269 }
3270 else if (val.stamp_in_gy_data == PROPERTY_DISABLE && val.stamp_in_xl_data == PROPERTY_ENABLE)
3271 {
3272 den.den_xl_g = PROPERTY_ENABLE;
3273 den.den_xl_en = PROPERTY_DISABLE;
3274 }
3275 else
3276 {
3277 den.den_xl_g = PROPERTY_DISABLE;
3278 den.den_xl_en = PROPERTY_DISABLE;
3279 den.den_z = PROPERTY_DISABLE;
3280 den.den_y = PROPERTY_DISABLE;
3281 den.den_x = PROPERTY_DISABLE;
3282 den.lvl2_en = PROPERTY_DISABLE;
3283 den.lvl1_en = PROPERTY_DISABLE;
3284 }
3285
3286 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_DEN, (uint8_t *)&den, 1);
3287
3288 return ret;
3289 }
3290
3291
3292 /**
3293 * @brief Data ENable (DEN) configuration.[get]
3294 *
3295 * @param ctx read / write interface definitions
3296 * @param val Data ENable (DEN) configuration.
3297 * @retval interface status (MANDATORY: return 0 -> no Error)
3298 *
3299 */
lsm6dsv32x_den_conf_get(const stmdev_ctx_t * ctx,lsm6dsv32x_den_conf_t * val)3300 int32_t lsm6dsv32x_den_conf_get(const stmdev_ctx_t *ctx, lsm6dsv32x_den_conf_t *val)
3301 {
3302 lsm6dsv32x_den_t den;
3303 int32_t ret;
3304
3305 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_DEN, (uint8_t *)&den, 1);
3306 if (ret != 0)
3307 {
3308 return ret;
3309 }
3310
3311 val->den_z = den.den_z;
3312 val->den_y = den.den_y;
3313 val->den_x = den.den_x;
3314
3315 if ((den.den_x | den.den_y | den.den_z) == PROPERTY_ENABLE)
3316 {
3317 if (den.den_xl_g == PROPERTY_DISABLE && den.den_xl_en == PROPERTY_ENABLE)
3318 {
3319 val->stamp_in_gy_data = PROPERTY_ENABLE;
3320 val->stamp_in_xl_data = PROPERTY_ENABLE;
3321 }
3322 else if (den.den_xl_g == PROPERTY_DISABLE && den.den_xl_en == PROPERTY_DISABLE)
3323 {
3324 val->stamp_in_gy_data = PROPERTY_ENABLE;
3325 val->stamp_in_xl_data = PROPERTY_DISABLE;
3326 }
3327 else // ( (den.den_xl_g & !den.den_xl_en) == PROPERTY_ENABLE )
3328 {
3329 val->stamp_in_gy_data = PROPERTY_DISABLE;
3330 val->stamp_in_xl_data = PROPERTY_ENABLE;
3331 }
3332 }
3333 else
3334 {
3335 val->stamp_in_gy_data = PROPERTY_DISABLE;
3336 val->stamp_in_xl_data = PROPERTY_DISABLE;
3337 }
3338
3339 switch ((den.lvl1_en << 1) + den.lvl2_en)
3340 {
3341 case LSM6DSV32X_LEVEL_TRIGGER:
3342 val->mode = LSM6DSV32X_LEVEL_TRIGGER;
3343 break;
3344
3345 case LSM6DSV32X_LEVEL_LATCHED:
3346 val->mode = LSM6DSV32X_LEVEL_LATCHED;
3347 break;
3348
3349 default:
3350 val->mode = LSM6DSV32X_DEN_NOT_DEFINED;
3351 break;
3352 }
3353
3354 return ret;
3355 }
3356
3357 /**
3358 * @}
3359 *
3360 */
3361
3362 /**
3363 * @defgroup Electronic Image Stabilization (EIS)
3364 * @brief Electronic Image Stabilization (EIS)
3365 * @{/
3366 *
3367 */
3368
3369 /**
3370 * @brief Gyroscope full-scale selection for EIS channel. WARNING: 4000dps will be available only if also User Interface chain is set to 4000dps[set]
3371 *
3372 * @param ctx read / write interface definitions
3373 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
3374 * @retval interface status (MANDATORY: return 0 -> no Error)
3375 *
3376 */
lsm6dsv32x_eis_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv32x_eis_gy_full_scale_t val)3377 int32_t lsm6dsv32x_eis_gy_full_scale_set(const stmdev_ctx_t *ctx,
3378 lsm6dsv32x_eis_gy_full_scale_t val)
3379 {
3380 lsm6dsv32x_ctrl_eis_t ctrl_eis;
3381 int32_t ret;
3382
3383 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3384
3385 if (ret == 0)
3386 {
3387 ctrl_eis.fs_g_eis = (uint8_t)val & 0x7U;
3388 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3389 }
3390
3391 return ret;
3392 }
3393
3394 /**
3395 * @brief Gyroscope full-scale selection for EIS channel. WARNING: 4000dps will be available only if also User Interface chain is set to 4000dps[get]
3396 *
3397 * @param ctx read / write interface definitions
3398 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps
3399 * @retval interface status (MANDATORY: return 0 -> no Error)
3400 *
3401 */
lsm6dsv32x_eis_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv32x_eis_gy_full_scale_t * val)3402 int32_t lsm6dsv32x_eis_gy_full_scale_get(const stmdev_ctx_t *ctx,
3403 lsm6dsv32x_eis_gy_full_scale_t *val)
3404 {
3405 lsm6dsv32x_ctrl_eis_t ctrl_eis;
3406 int32_t ret;
3407
3408 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3409 if (ret != 0)
3410 {
3411 return ret;
3412 }
3413
3414 switch (ctrl_eis.fs_g_eis)
3415 {
3416 case LSM6DSV32X_EIS_125dps:
3417 *val = LSM6DSV32X_EIS_125dps;
3418 break;
3419
3420 case LSM6DSV32X_EIS_250dps:
3421 *val = LSM6DSV32X_EIS_250dps;
3422 break;
3423
3424 case LSM6DSV32X_EIS_500dps:
3425 *val = LSM6DSV32X_EIS_500dps;
3426 break;
3427
3428 case LSM6DSV32X_EIS_1000dps:
3429 *val = LSM6DSV32X_EIS_1000dps;
3430 break;
3431
3432 case LSM6DSV32X_EIS_2000dps:
3433 *val = LSM6DSV32X_EIS_2000dps;
3434 break;
3435
3436 default:
3437 *val = LSM6DSV32X_EIS_125dps;
3438 break;
3439 }
3440 return ret;
3441 }
3442
3443 /**
3444 * @brief Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).[set]
3445 *
3446 * @param ctx read / write interface definitions
3447 * @param val Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).
3448 * @retval interface status (MANDATORY: return 0 -> no Error)
3449 *
3450 */
lsm6dsv32x_eis_gy_on_spi2_set(const stmdev_ctx_t * ctx,uint8_t val)3451 int32_t lsm6dsv32x_eis_gy_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val)
3452 {
3453 lsm6dsv32x_ctrl_eis_t ctrl_eis;
3454 int32_t ret;
3455
3456 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3457
3458 if (ret == 0)
3459 {
3460 ctrl_eis.g_eis_on_g_ois_out_reg = val;
3461 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3462 }
3463
3464 return ret;
3465 }
3466
3467 /**
3468 * @brief Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).[get]
3469 *
3470 * @param ctx read / write interface definitions
3471 * @param val Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).
3472 * @retval interface status (MANDATORY: return 0 -> no Error)
3473 *
3474 */
lsm6dsv32x_eis_gy_on_spi2_get(const stmdev_ctx_t * ctx,uint8_t * val)3475 int32_t lsm6dsv32x_eis_gy_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val)
3476 {
3477 lsm6dsv32x_ctrl_eis_t ctrl_eis;
3478 int32_t ret;
3479
3480 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3481 *val = ctrl_eis.g_eis_on_g_ois_out_reg;
3482
3483 return ret;
3484 }
3485
3486 /**
3487 * @brief Enables and selects the ODR of the gyroscope EIS channel.[set]
3488 *
3489 * @param ctx read / write interface definitions
3490 * @param val EIS_1920Hz, EIS_960Hz,
3491 * @retval interface status (MANDATORY: return 0 -> no Error)
3492 *
3493 */
lsm6dsv32x_gy_eis_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv32x_gy_eis_data_rate_t val)3494 int32_t lsm6dsv32x_gy_eis_data_rate_set(const stmdev_ctx_t *ctx,
3495 lsm6dsv32x_gy_eis_data_rate_t val)
3496 {
3497 lsm6dsv32x_ctrl_eis_t ctrl_eis;
3498 int32_t ret;
3499
3500 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3501
3502 if (ret == 0)
3503 {
3504 ctrl_eis.odr_g_eis = (uint8_t)val & 0x03U;
3505 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3506 }
3507
3508 return ret;
3509 }
3510
3511 /**
3512 * @brief Enables and selects the ODR of the gyroscope EIS channel.[get]
3513 *
3514 * @param ctx read / write interface definitions
3515 * @param val EIS_1920Hz, EIS_960Hz,
3516 * @retval interface status (MANDATORY: return 0 -> no Error)
3517 *
3518 */
lsm6dsv32x_gy_eis_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv32x_gy_eis_data_rate_t * val)3519 int32_t lsm6dsv32x_gy_eis_data_rate_get(const stmdev_ctx_t *ctx,
3520 lsm6dsv32x_gy_eis_data_rate_t *val)
3521 {
3522 lsm6dsv32x_ctrl_eis_t ctrl_eis;
3523 int32_t ret;
3524
3525 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3526 if (ret != 0)
3527 {
3528 return ret;
3529 }
3530
3531 switch (ctrl_eis.odr_g_eis)
3532 {
3533 case LSM6DSV32X_EIS_ODR_OFF:
3534 *val = LSM6DSV32X_EIS_ODR_OFF;
3535 break;
3536
3537 case LSM6DSV32X_EIS_1920Hz:
3538 *val = LSM6DSV32X_EIS_1920Hz;
3539 break;
3540
3541 case LSM6DSV32X_EIS_960Hz:
3542 *val = LSM6DSV32X_EIS_960Hz;
3543 break;
3544
3545 default:
3546 *val = LSM6DSV32X_EIS_1920Hz;
3547 break;
3548 }
3549
3550 return ret;
3551 }
3552
3553 /**
3554 * @}
3555 *
3556 */
3557
3558 /**
3559 * @defgroup FIFO
3560 * @brief This section group all the functions concerning the FIFO usage
3561 * @{
3562 *
3563 */
3564
3565 /**
3566 * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[set]
3567 *
3568 * @param ctx read / write interface definitions
3569 * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).
3570 * @retval interface status (MANDATORY: return 0 -> no Error)
3571 *
3572 */
lsm6dsv32x_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)3573 int32_t lsm6dsv32x_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
3574 {
3575 lsm6dsv32x_fifo_ctrl1_t fifo_ctrl1;
3576 int32_t ret;
3577
3578 fifo_ctrl1.wtm = val;
3579 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
3580
3581 return ret;
3582 }
3583
3584 /**
3585 * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[get]
3586 *
3587 * @param ctx read / write interface definitions
3588 * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).
3589 * @retval interface status (MANDATORY: return 0 -> no Error)
3590 *
3591 */
lsm6dsv32x_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)3592 int32_t lsm6dsv32x_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
3593 {
3594 lsm6dsv32x_fifo_ctrl1_t fifo_ctrl1;
3595 int32_t ret;
3596
3597 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
3598 *val = fifo_ctrl1.wtm;
3599
3600 return ret;
3601 }
3602
3603 /**
3604 * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[set]
3605 *
3606 * @param ctx read / write interface definitions
3607 * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.
3608 * @retval interface status (MANDATORY: return 0 -> no Error)
3609 *
3610 */
lsm6dsv32x_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t * ctx,uint8_t val)3611 int32_t lsm6dsv32x_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
3612 {
3613 lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2;
3614 int32_t ret;
3615
3616 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3617 if (ret == 0)
3618 {
3619 fifo_ctrl2.xl_dualc_batch_from_fsm = val;
3620 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3621 }
3622
3623 return ret;
3624 }
3625
3626 /**
3627 * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[get]
3628 *
3629 * @param ctx read / write interface definitions
3630 * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.
3631 * @retval interface status (MANDATORY: return 0 -> no Error)
3632 *
3633 */
lsm6dsv32x_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)3634 int32_t lsm6dsv32x_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
3635 {
3636 lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2;
3637 int32_t ret;
3638
3639 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3640 *val = fifo_ctrl2.xl_dualc_batch_from_fsm;
3641
3642 return ret;
3643 }
3644
3645 /**
3646 * @brief It configures the compression algorithm to write non-compressed data at each rate.[set]
3647 *
3648 * @param ctx read / write interface definitions
3649 * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1,
3650 * @retval interface status (MANDATORY: return 0 -> no Error)
3651 *
3652 */
lsm6dsv32x_fifo_compress_algo_set(const stmdev_ctx_t * ctx,lsm6dsv32x_fifo_compress_algo_t val)3653 int32_t lsm6dsv32x_fifo_compress_algo_set(const stmdev_ctx_t *ctx,
3654 lsm6dsv32x_fifo_compress_algo_t val)
3655 {
3656 lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2;
3657 int32_t ret;
3658
3659 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3660 if (ret == 0)
3661 {
3662 fifo_ctrl2.uncompr_rate = (uint8_t)val & 0x03U;
3663 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3664 }
3665
3666 return ret;
3667 }
3668
3669 /**
3670 * @brief It configures the compression algorithm to write non-compressed data at each rate.[get]
3671 *
3672 * @param ctx read / write interface definitions
3673 * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1,
3674 * @retval interface status (MANDATORY: return 0 -> no Error)
3675 *
3676 */
lsm6dsv32x_fifo_compress_algo_get(const stmdev_ctx_t * ctx,lsm6dsv32x_fifo_compress_algo_t * val)3677 int32_t lsm6dsv32x_fifo_compress_algo_get(const stmdev_ctx_t *ctx,
3678 lsm6dsv32x_fifo_compress_algo_t *val)
3679 {
3680 lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2;
3681 int32_t ret;
3682
3683 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3684 if (ret != 0)
3685 {
3686 return ret;
3687 }
3688
3689 switch (fifo_ctrl2.uncompr_rate)
3690 {
3691 case LSM6DSV32X_CMP_DISABLE:
3692 *val = LSM6DSV32X_CMP_DISABLE;
3693 break;
3694
3695 case LSM6DSV32X_CMP_8_TO_1:
3696 *val = LSM6DSV32X_CMP_8_TO_1;
3697 break;
3698
3699 case LSM6DSV32X_CMP_16_TO_1:
3700 *val = LSM6DSV32X_CMP_16_TO_1;
3701 break;
3702
3703 case LSM6DSV32X_CMP_32_TO_1:
3704 *val = LSM6DSV32X_CMP_32_TO_1;
3705 break;
3706
3707 default:
3708 *val = LSM6DSV32X_CMP_DISABLE;
3709 break;
3710 }
3711 return ret;
3712 }
3713
3714 /**
3715 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
3716 *
3717 * @param ctx read / write interface definitions
3718 * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO.
3719 * @retval interface status (MANDATORY: return 0 -> no Error)
3720 *
3721 */
lsm6dsv32x_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t * ctx,uint8_t val)3722 int32_t lsm6dsv32x_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val)
3723 {
3724 lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2;
3725 int32_t ret;
3726
3727 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3728 if (ret == 0)
3729 {
3730 fifo_ctrl2.odr_chg_en = val;
3731 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3732 }
3733
3734 return ret;
3735 }
3736
3737 /**
3738 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
3739 *
3740 * @param ctx read / write interface definitions
3741 * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO.
3742 * @retval interface status (MANDATORY: return 0 -> no Error)
3743 *
3744 */
lsm6dsv32x_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t * ctx,uint8_t * val)3745 int32_t lsm6dsv32x_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx,
3746 uint8_t *val)
3747 {
3748 lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2;
3749 int32_t ret;
3750
3751 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3752 *val = fifo_ctrl2.odr_chg_en;
3753
3754 return ret;
3755 }
3756
3757 /**
3758 * @brief Enables/Disables compression algorithm runtime.[set]
3759 *
3760 * @param ctx read / write interface definitions
3761 * @param val Enables/Disables compression algorithm runtime.
3762 * @retval interface status (MANDATORY: return 0 -> no Error)
3763 *
3764 */
lsm6dsv32x_fifo_compress_algo_real_time_set(const stmdev_ctx_t * ctx,uint8_t val)3765 int32_t lsm6dsv32x_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx,
3766 uint8_t val)
3767 {
3768 lsm6dsv32x_emb_func_en_b_t emb_func_en_b;
3769 lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2;
3770
3771 int32_t ret;
3772
3773 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3774 fifo_ctrl2.fifo_compr_rt_en = val;
3775 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3776 if (ret != 0)
3777 {
3778 return ret;
3779 }
3780
3781 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
3782 if (ret != 0)
3783 {
3784 return ret;
3785 }
3786
3787 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
3788 emb_func_en_b.fifo_compr_en = val;
3789 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
3790 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
3791
3792 return ret;
3793 }
3794
3795 /**
3796 * @brief Enables/Disables compression algorithm runtime.[get]
3797 *
3798 * @param ctx read / write interface definitions
3799 * @param val Enables/Disables compression algorithm runtime.
3800 * @retval interface status (MANDATORY: return 0 -> no Error)
3801 *
3802 */
lsm6dsv32x_fifo_compress_algo_real_time_get(const stmdev_ctx_t * ctx,uint8_t * val)3803 int32_t lsm6dsv32x_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx,
3804 uint8_t *val)
3805 {
3806 lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2;
3807 int32_t ret;
3808
3809 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3810
3811 *val = fifo_ctrl2.fifo_compr_rt_en;
3812
3813 return ret;
3814 }
3815
3816 /**
3817 * @brief Sensing chain FIFO stop values memorization at threshold level.[set]
3818 *
3819 * @param ctx read / write interface definitions
3820 * @param val Sensing chain FIFO stop values memorization at threshold level.
3821 * @retval interface status (MANDATORY: return 0 -> no Error)
3822 *
3823 */
lsm6dsv32x_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)3824 int32_t lsm6dsv32x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
3825 {
3826 lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2;
3827 int32_t ret;
3828
3829 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3830 if (ret == 0)
3831 {
3832 fifo_ctrl2.stop_on_wtm = val;
3833 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3834 }
3835
3836 return ret;
3837 }
3838
3839 /**
3840 * @brief Sensing chain FIFO stop values memorization at threshold level.[get]
3841 *
3842 * @param ctx read / write interface definitions
3843 * @param val Sensing chain FIFO stop values memorization at threshold level.
3844 * @retval interface status (MANDATORY: return 0 -> no Error)
3845 *
3846 */
lsm6dsv32x_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)3847 int32_t lsm6dsv32x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val)
3848 {
3849 lsm6dsv32x_fifo_ctrl2_t fifo_ctrl2;
3850 int32_t ret;
3851
3852 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3853 *val = fifo_ctrl2.stop_on_wtm;
3854
3855 return ret;
3856 }
3857
3858 /**
3859 * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[set]
3860 *
3861 * @param ctx read / write interface definitions
3862 * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz,
3863 * @retval interface status (MANDATORY: return 0 -> no Error)
3864 *
3865 */
lsm6dsv32x_fifo_xl_batch_set(const stmdev_ctx_t * ctx,lsm6dsv32x_fifo_xl_batch_t val)3866 int32_t lsm6dsv32x_fifo_xl_batch_set(const stmdev_ctx_t *ctx,
3867 lsm6dsv32x_fifo_xl_batch_t val)
3868 {
3869 lsm6dsv32x_fifo_ctrl3_t fifo_ctrl3;
3870 int32_t ret;
3871
3872 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3873 if (ret == 0)
3874 {
3875 fifo_ctrl3.bdr_xl = (uint8_t)val & 0xFu;
3876 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3877 }
3878
3879 return ret;
3880 }
3881
3882 /**
3883 * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[get]
3884 *
3885 * @param ctx read / write interface definitions
3886 * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz,
3887 * @retval interface status (MANDATORY: return 0 -> no Error)
3888 *
3889 */
lsm6dsv32x_fifo_xl_batch_get(const stmdev_ctx_t * ctx,lsm6dsv32x_fifo_xl_batch_t * val)3890 int32_t lsm6dsv32x_fifo_xl_batch_get(const stmdev_ctx_t *ctx,
3891 lsm6dsv32x_fifo_xl_batch_t *val)
3892 {
3893 lsm6dsv32x_fifo_ctrl3_t fifo_ctrl3;
3894 int32_t ret;
3895
3896 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3897 if (ret != 0)
3898 {
3899 return ret;
3900 }
3901
3902 switch (fifo_ctrl3.bdr_xl)
3903 {
3904 case LSM6DSV32X_XL_NOT_BATCHED:
3905 *val = LSM6DSV32X_XL_NOT_BATCHED;
3906 break;
3907
3908 case LSM6DSV32X_XL_BATCHED_AT_1Hz875:
3909 *val = LSM6DSV32X_XL_BATCHED_AT_1Hz875;
3910 break;
3911
3912 case LSM6DSV32X_XL_BATCHED_AT_7Hz5:
3913 *val = LSM6DSV32X_XL_BATCHED_AT_7Hz5;
3914 break;
3915
3916 case LSM6DSV32X_XL_BATCHED_AT_15Hz:
3917 *val = LSM6DSV32X_XL_BATCHED_AT_15Hz;
3918 break;
3919
3920 case LSM6DSV32X_XL_BATCHED_AT_30Hz:
3921 *val = LSM6DSV32X_XL_BATCHED_AT_30Hz;
3922 break;
3923
3924 case LSM6DSV32X_XL_BATCHED_AT_60Hz:
3925 *val = LSM6DSV32X_XL_BATCHED_AT_60Hz;
3926 break;
3927
3928 case LSM6DSV32X_XL_BATCHED_AT_120Hz:
3929 *val = LSM6DSV32X_XL_BATCHED_AT_120Hz;
3930 break;
3931
3932 case LSM6DSV32X_XL_BATCHED_AT_240Hz:
3933 *val = LSM6DSV32X_XL_BATCHED_AT_240Hz;
3934 break;
3935
3936 case LSM6DSV32X_XL_BATCHED_AT_480Hz:
3937 *val = LSM6DSV32X_XL_BATCHED_AT_480Hz;
3938 break;
3939
3940 case LSM6DSV32X_XL_BATCHED_AT_960Hz:
3941 *val = LSM6DSV32X_XL_BATCHED_AT_960Hz;
3942 break;
3943
3944 case LSM6DSV32X_XL_BATCHED_AT_1920Hz:
3945 *val = LSM6DSV32X_XL_BATCHED_AT_1920Hz;
3946 break;
3947
3948 case LSM6DSV32X_XL_BATCHED_AT_3840Hz:
3949 *val = LSM6DSV32X_XL_BATCHED_AT_3840Hz;
3950 break;
3951
3952 case LSM6DSV32X_XL_BATCHED_AT_7680Hz:
3953 *val = LSM6DSV32X_XL_BATCHED_AT_7680Hz;
3954 break;
3955
3956 default:
3957 *val = LSM6DSV32X_XL_NOT_BATCHED;
3958 break;
3959 }
3960
3961 return ret;
3962 }
3963
3964 /**
3965 * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[set]
3966 *
3967 * @param ctx read / write interface definitions
3968 * @param val GY_NOT_BATCHED, GY_BATCHED_AT_1Hz875, GY_BATCHED_AT_7Hz5, GY_BATCHED_AT_15Hz, GY_BATCHED_AT_30Hz, GY_BATCHED_AT_60Hz, GY_BATCHED_AT_120Hz, GY_BATCHED_AT_240Hz, GY_BATCHED_AT_480Hz, GY_BATCHED_AT_960Hz, GY_BATCHED_AT_1920Hz, GY_BATCHED_AT_3840Hz, GY_BATCHED_AT_7680Hz,
3969 * @retval interface status (MANDATORY: return 0 -> no Error)
3970 *
3971 */
lsm6dsv32x_fifo_gy_batch_set(const stmdev_ctx_t * ctx,lsm6dsv32x_fifo_gy_batch_t val)3972 int32_t lsm6dsv32x_fifo_gy_batch_set(const stmdev_ctx_t *ctx,
3973 lsm6dsv32x_fifo_gy_batch_t val)
3974 {
3975 lsm6dsv32x_fifo_ctrl3_t fifo_ctrl3;
3976 int32_t ret;
3977
3978 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3979 if (ret == 0)
3980 {
3981 fifo_ctrl3.bdr_gy = (uint8_t)val & 0x0Fu;
3982 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3983 }
3984
3985 return ret;
3986 }
3987
3988 /**
3989 * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[get]
3990 *
3991 * @param ctx read / write interface definitions
3992 * @param val GY_NOT_BATCHED, GY_BATCHED_AT_1Hz875, GY_BATCHED_AT_7Hz5, GY_BATCHED_AT_15Hz, GY_BATCHED_AT_30Hz, GY_BATCHED_AT_60Hz, GY_BATCHED_AT_120Hz, GY_BATCHED_AT_240Hz, GY_BATCHED_AT_480Hz, GY_BATCHED_AT_960Hz, GY_BATCHED_AT_1920Hz, GY_BATCHED_AT_3840Hz, GY_BATCHED_AT_7680Hz,
3993 * @retval interface status (MANDATORY: return 0 -> no Error)
3994 *
3995 */
lsm6dsv32x_fifo_gy_batch_get(const stmdev_ctx_t * ctx,lsm6dsv32x_fifo_gy_batch_t * val)3996 int32_t lsm6dsv32x_fifo_gy_batch_get(const stmdev_ctx_t *ctx,
3997 lsm6dsv32x_fifo_gy_batch_t *val)
3998 {
3999 lsm6dsv32x_fifo_ctrl3_t fifo_ctrl3;
4000 int32_t ret;
4001
4002 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
4003 if (ret != 0)
4004 {
4005 return ret;
4006 }
4007
4008 switch (fifo_ctrl3.bdr_gy)
4009 {
4010 case LSM6DSV32X_GY_NOT_BATCHED:
4011 *val = LSM6DSV32X_GY_NOT_BATCHED;
4012 break;
4013
4014 case LSM6DSV32X_GY_BATCHED_AT_1Hz875:
4015 *val = LSM6DSV32X_GY_BATCHED_AT_1Hz875;
4016 break;
4017
4018 case LSM6DSV32X_GY_BATCHED_AT_7Hz5:
4019 *val = LSM6DSV32X_GY_BATCHED_AT_7Hz5;
4020 break;
4021
4022 case LSM6DSV32X_GY_BATCHED_AT_15Hz:
4023 *val = LSM6DSV32X_GY_BATCHED_AT_15Hz;
4024 break;
4025
4026 case LSM6DSV32X_GY_BATCHED_AT_30Hz:
4027 *val = LSM6DSV32X_GY_BATCHED_AT_30Hz;
4028 break;
4029
4030 case LSM6DSV32X_GY_BATCHED_AT_60Hz:
4031 *val = LSM6DSV32X_GY_BATCHED_AT_60Hz;
4032 break;
4033
4034 case LSM6DSV32X_GY_BATCHED_AT_120Hz:
4035 *val = LSM6DSV32X_GY_BATCHED_AT_120Hz;
4036 break;
4037
4038 case LSM6DSV32X_GY_BATCHED_AT_240Hz:
4039 *val = LSM6DSV32X_GY_BATCHED_AT_240Hz;
4040 break;
4041
4042 case LSM6DSV32X_GY_BATCHED_AT_480Hz:
4043 *val = LSM6DSV32X_GY_BATCHED_AT_480Hz;
4044 break;
4045
4046 case LSM6DSV32X_GY_BATCHED_AT_960Hz:
4047 *val = LSM6DSV32X_GY_BATCHED_AT_960Hz;
4048 break;
4049
4050 case LSM6DSV32X_GY_BATCHED_AT_1920Hz:
4051 *val = LSM6DSV32X_GY_BATCHED_AT_1920Hz;
4052 break;
4053
4054 case LSM6DSV32X_GY_BATCHED_AT_3840Hz:
4055 *val = LSM6DSV32X_GY_BATCHED_AT_3840Hz;
4056 break;
4057
4058 case LSM6DSV32X_GY_BATCHED_AT_7680Hz:
4059 *val = LSM6DSV32X_GY_BATCHED_AT_7680Hz;
4060 break;
4061
4062 default:
4063 *val = LSM6DSV32X_GY_NOT_BATCHED;
4064 break;
4065 }
4066 return ret;
4067 }
4068
4069
4070 /**
4071 * @brief FIFO mode selection.[set]
4072 *
4073 * @param ctx read / write interface definitions
4074 * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
4075 * @retval interface status (MANDATORY: return 0 -> no Error)
4076 *
4077 */
lsm6dsv32x_fifo_mode_set(const stmdev_ctx_t * ctx,lsm6dsv32x_fifo_mode_t val)4078 int32_t lsm6dsv32x_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_fifo_mode_t val)
4079 {
4080 lsm6dsv32x_fifo_ctrl4_t fifo_ctrl4;
4081 int32_t ret;
4082
4083 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4084 if (ret == 0)
4085 {
4086 fifo_ctrl4.fifo_mode = (uint8_t)val & 0x07U;
4087 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4088 }
4089
4090 return ret;
4091 }
4092
4093 /**
4094 * @brief FIFO mode selection.[get]
4095 *
4096 * @param ctx read / write interface definitions
4097 * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
4098 * @retval interface status (MANDATORY: return 0 -> no Error)
4099 *
4100 */
lsm6dsv32x_fifo_mode_get(const stmdev_ctx_t * ctx,lsm6dsv32x_fifo_mode_t * val)4101 int32_t lsm6dsv32x_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_fifo_mode_t *val)
4102 {
4103 lsm6dsv32x_fifo_ctrl4_t fifo_ctrl4;
4104 int32_t ret;
4105
4106 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4107 if (ret != 0)
4108 {
4109 return ret;
4110 }
4111
4112 switch (fifo_ctrl4.fifo_mode)
4113 {
4114 case LSM6DSV32X_BYPASS_MODE:
4115 *val = LSM6DSV32X_BYPASS_MODE;
4116 break;
4117
4118 case LSM6DSV32X_FIFO_MODE:
4119 *val = LSM6DSV32X_FIFO_MODE;
4120 break;
4121
4122 case LSM6DSV32X_STREAM_WTM_TO_FULL_MODE:
4123 *val = LSM6DSV32X_STREAM_WTM_TO_FULL_MODE;
4124 break;
4125
4126 case LSM6DSV32X_STREAM_TO_FIFO_MODE:
4127 *val = LSM6DSV32X_STREAM_TO_FIFO_MODE;
4128 break;
4129
4130 case LSM6DSV32X_BYPASS_TO_STREAM_MODE:
4131 *val = LSM6DSV32X_BYPASS_TO_STREAM_MODE;
4132 break;
4133
4134 case LSM6DSV32X_STREAM_MODE:
4135 *val = LSM6DSV32X_STREAM_MODE;
4136 break;
4137
4138 case LSM6DSV32X_BYPASS_TO_FIFO_MODE:
4139 *val = LSM6DSV32X_BYPASS_TO_FIFO_MODE;
4140 break;
4141
4142 default:
4143 *val = LSM6DSV32X_BYPASS_MODE;
4144 break;
4145 }
4146 return ret;
4147 }
4148
4149 /**
4150 * @brief Enables FIFO batching of EIS gyroscope output values.[set]
4151 *
4152 * @param ctx read / write interface definitions
4153 * @param val Enables FIFO batching of EIS gyroscope output values.
4154 * @retval interface status (MANDATORY: return 0 -> no Error)
4155 *
4156 */
lsm6dsv32x_fifo_gy_eis_batch_set(const stmdev_ctx_t * ctx,uint8_t val)4157 int32_t lsm6dsv32x_fifo_gy_eis_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
4158 {
4159 lsm6dsv32x_fifo_ctrl4_t fifo_ctrl4;
4160 int32_t ret;
4161
4162 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4163 if (ret == 0)
4164 {
4165 fifo_ctrl4.g_eis_fifo_en = val;
4166 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4167 }
4168
4169 return ret;
4170 }
4171
4172 /**
4173 * @brief Enables FIFO batching of EIS gyroscope output values.[get]
4174 *
4175 * @param ctx read / write interface definitions
4176 * @param val Enables FIFO batching of EIS gyroscope output values.
4177 * @retval interface status (MANDATORY: return 0 -> no Error)
4178 *
4179 */
lsm6dsv32x_fifo_gy_eis_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)4180 int32_t lsm6dsv32x_fifo_gy_eis_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
4181 {
4182 lsm6dsv32x_fifo_ctrl4_t fifo_ctrl4;
4183 int32_t ret;
4184
4185 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4186 *val = fifo_ctrl4.g_eis_fifo_en;
4187
4188 return ret;
4189 }
4190
4191 /**
4192 * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[set]
4193 *
4194 * @param ctx read / write interface definitions
4195 * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz,
4196 * @retval interface status (MANDATORY: return 0 -> no Error)
4197 *
4198 */
lsm6dsv32x_fifo_temp_batch_set(const stmdev_ctx_t * ctx,lsm6dsv32x_fifo_temp_batch_t val)4199 int32_t lsm6dsv32x_fifo_temp_batch_set(const stmdev_ctx_t *ctx,
4200 lsm6dsv32x_fifo_temp_batch_t val)
4201 {
4202 lsm6dsv32x_fifo_ctrl4_t fifo_ctrl4;
4203 int32_t ret;
4204
4205 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4206 if (ret == 0)
4207 {
4208 fifo_ctrl4.odr_t_batch = (uint8_t)val & 0x03U;
4209 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4210 }
4211
4212 return ret;
4213 }
4214
4215 /**
4216 * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[get]
4217 *
4218 * @param ctx read / write interface definitions
4219 * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz,
4220 * @retval interface status (MANDATORY: return 0 -> no Error)
4221 *
4222 */
lsm6dsv32x_fifo_temp_batch_get(const stmdev_ctx_t * ctx,lsm6dsv32x_fifo_temp_batch_t * val)4223 int32_t lsm6dsv32x_fifo_temp_batch_get(const stmdev_ctx_t *ctx,
4224 lsm6dsv32x_fifo_temp_batch_t *val)
4225 {
4226 lsm6dsv32x_fifo_ctrl4_t fifo_ctrl4;
4227 int32_t ret;
4228
4229 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4230 if (ret != 0)
4231 {
4232 return ret;
4233 }
4234
4235 switch (fifo_ctrl4.odr_t_batch)
4236 {
4237 case LSM6DSV32X_TEMP_NOT_BATCHED:
4238 *val = LSM6DSV32X_TEMP_NOT_BATCHED;
4239 break;
4240
4241 case LSM6DSV32X_TEMP_BATCHED_AT_1Hz875:
4242 *val = LSM6DSV32X_TEMP_BATCHED_AT_1Hz875;
4243 break;
4244
4245 case LSM6DSV32X_TEMP_BATCHED_AT_15Hz:
4246 *val = LSM6DSV32X_TEMP_BATCHED_AT_15Hz;
4247 break;
4248
4249 case LSM6DSV32X_TEMP_BATCHED_AT_60Hz:
4250 *val = LSM6DSV32X_TEMP_BATCHED_AT_60Hz;
4251 break;
4252
4253 default:
4254 *val = LSM6DSV32X_TEMP_NOT_BATCHED;
4255 break;
4256 }
4257 return ret;
4258 }
4259
4260 /**
4261 * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[set]
4262 *
4263 * @param ctx read / write interface definitions
4264 * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32,
4265 * @retval interface status (MANDATORY: return 0 -> no Error)
4266 *
4267 */
lsm6dsv32x_fifo_timestamp_batch_set(const stmdev_ctx_t * ctx,lsm6dsv32x_fifo_timestamp_batch_t val)4268 int32_t lsm6dsv32x_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx,
4269 lsm6dsv32x_fifo_timestamp_batch_t val)
4270 {
4271 lsm6dsv32x_fifo_ctrl4_t fifo_ctrl4;
4272 int32_t ret;
4273
4274 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4275 if (ret == 0)
4276 {
4277 fifo_ctrl4.dec_ts_batch = (uint8_t)val & 0x03U;
4278 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4279 }
4280
4281 return ret;
4282 }
4283
4284 /**
4285 * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[get]
4286 *
4287 * @param ctx read / write interface definitions
4288 * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32,
4289 * @retval interface status (MANDATORY: return 0 -> no Error)
4290 *
4291 */
lsm6dsv32x_fifo_timestamp_batch_get(const stmdev_ctx_t * ctx,lsm6dsv32x_fifo_timestamp_batch_t * val)4292 int32_t lsm6dsv32x_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx,
4293 lsm6dsv32x_fifo_timestamp_batch_t *val)
4294 {
4295 lsm6dsv32x_fifo_ctrl4_t fifo_ctrl4;
4296 int32_t ret;
4297
4298 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4299 if (ret != 0)
4300 {
4301 return ret;
4302 }
4303
4304 switch (fifo_ctrl4.dec_ts_batch)
4305 {
4306 case LSM6DSV32X_TMSTMP_NOT_BATCHED:
4307 *val = LSM6DSV32X_TMSTMP_NOT_BATCHED;
4308 break;
4309
4310 case LSM6DSV32X_TMSTMP_DEC_1:
4311 *val = LSM6DSV32X_TMSTMP_DEC_1;
4312 break;
4313
4314 case LSM6DSV32X_TMSTMP_DEC_8:
4315 *val = LSM6DSV32X_TMSTMP_DEC_8;
4316 break;
4317
4318 case LSM6DSV32X_TMSTMP_DEC_32:
4319 *val = LSM6DSV32X_TMSTMP_DEC_32;
4320 break;
4321
4322 default:
4323 *val = LSM6DSV32X_TMSTMP_NOT_BATCHED;
4324 break;
4325 }
4326
4327 return ret;
4328 }
4329
4330 /**
4331 * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[set]
4332 *
4333 * @param ctx read / write interface definitions
4334 * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.
4335 * @retval interface status (MANDATORY: return 0 -> no Error)
4336 *
4337 */
lsm6dsv32x_fifo_batch_counter_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)4338 int32_t lsm6dsv32x_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx,
4339 uint16_t val)
4340 {
4341 lsm6dsv32x_counter_bdr_reg1_t counter_bdr_reg1;
4342 lsm6dsv32x_counter_bdr_reg2_t counter_bdr_reg2;
4343 int32_t ret;
4344
4345 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
4346
4347 if (ret == 0)
4348 {
4349 counter_bdr_reg2.cnt_bdr_th = (uint8_t)val & 0xFFU;
4350 counter_bdr_reg1.cnt_bdr_th = (uint8_t)(val >> 8) & 0x3U;
4351 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
4352 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1);
4353 }
4354
4355 return ret;
4356 }
4357
4358 /**
4359 * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[get]
4360 *
4361 * @param ctx read / write interface definitions
4362 * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.
4363 * @retval interface status (MANDATORY: return 0 -> no Error)
4364 *
4365 */
lsm6dsv32x_fifo_batch_counter_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)4366 int32_t lsm6dsv32x_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx,
4367 uint16_t *val)
4368 {
4369 uint8_t buff[2];
4370 int32_t ret;
4371
4372 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_COUNTER_BDR_REG1, &buff[0], 2);
4373 if (ret != 0)
4374 {
4375 return ret;
4376 }
4377
4378 *val = (uint16_t)buff[0] & 0x3U;
4379 *val = (*val * 256U) + (uint16_t)buff[1];
4380
4381 return ret;
4382 }
4383
4384 /**
4385 * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[set]
4386 *
4387 * @param ctx read / write interface definitions
4388 * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT,
4389 * @retval interface status (MANDATORY: return 0 -> no Error)
4390 *
4391 */
lsm6dsv32x_fifo_batch_cnt_event_set(const stmdev_ctx_t * ctx,lsm6dsv32x_fifo_batch_cnt_event_t val)4392 int32_t lsm6dsv32x_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx,
4393 lsm6dsv32x_fifo_batch_cnt_event_t val)
4394 {
4395 lsm6dsv32x_counter_bdr_reg1_t counter_bdr_reg1;
4396 int32_t ret;
4397
4398 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
4399 if (ret == 0)
4400 {
4401 counter_bdr_reg1.trig_counter_bdr = (uint8_t)val & 0x03U;
4402 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
4403 }
4404
4405 return ret;
4406 }
4407
4408 /**
4409 * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[get]
4410 *
4411 * @param ctx read / write interface definitions
4412 * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT,
4413 * @retval interface status (MANDATORY: return 0 -> no Error)
4414 *
4415 */
lsm6dsv32x_fifo_batch_cnt_event_get(const stmdev_ctx_t * ctx,lsm6dsv32x_fifo_batch_cnt_event_t * val)4416 int32_t lsm6dsv32x_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx,
4417 lsm6dsv32x_fifo_batch_cnt_event_t *val)
4418 {
4419 lsm6dsv32x_counter_bdr_reg1_t counter_bdr_reg1;
4420 int32_t ret;
4421
4422 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
4423 if (ret != 0)
4424 {
4425 return ret;
4426 }
4427
4428 switch (counter_bdr_reg1.trig_counter_bdr)
4429 {
4430 case LSM6DSV32X_XL_BATCH_EVENT:
4431 *val = LSM6DSV32X_XL_BATCH_EVENT;
4432 break;
4433
4434 case LSM6DSV32X_GY_BATCH_EVENT:
4435 *val = LSM6DSV32X_GY_BATCH_EVENT;
4436 break;
4437
4438 case LSM6DSV32X_GY_EIS_BATCH_EVENT:
4439 *val = LSM6DSV32X_GY_EIS_BATCH_EVENT;
4440 break;
4441
4442 default:
4443 *val = LSM6DSV32X_XL_BATCH_EVENT;
4444 break;
4445 }
4446
4447 return ret;
4448 }
4449
lsm6dsv32x_fifo_status_get(const stmdev_ctx_t * ctx,lsm6dsv32x_fifo_status_t * val)4450 int32_t lsm6dsv32x_fifo_status_get(const stmdev_ctx_t *ctx,
4451 lsm6dsv32x_fifo_status_t *val)
4452 {
4453 uint8_t buff[2];
4454 lsm6dsv32x_fifo_status2_t status;
4455 int32_t ret;
4456
4457 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_STATUS1, (uint8_t *)&buff[0], 2);
4458 if (ret != 0)
4459 {
4460 return ret;
4461 }
4462
4463 bytecpy((uint8_t *)&status, &buff[1]);
4464
4465 val->fifo_bdr = status.counter_bdr_ia;
4466 val->fifo_ovr = status.fifo_ovr_ia;
4467 val->fifo_full = status.fifo_full_ia;
4468 val->fifo_th = status.fifo_wtm_ia;
4469
4470 val->fifo_level = (uint16_t)buff[1] & 0x01U;
4471 val->fifo_level = (val->fifo_level * 256U) + buff[0];
4472
4473 return ret;
4474 }
4475
4476
4477 /**
4478 * @brief FIFO data output[get]
4479 *
4480 * @param ctx read / write interface definitions
4481 * @param val lsm6dsv32x_fifo_out_raw_t
4482 * @retval interface status (MANDATORY: return 0 -> no Error)
4483 *
4484 */
lsm6dsv32x_fifo_out_raw_get(const stmdev_ctx_t * ctx,lsm6dsv32x_fifo_out_raw_t * val)4485 int32_t lsm6dsv32x_fifo_out_raw_get(const stmdev_ctx_t *ctx,
4486 lsm6dsv32x_fifo_out_raw_t *val)
4487 {
4488 lsm6dsv32x_fifo_data_out_tag_t fifo_data_out_tag;
4489 uint8_t buff[7];
4490 int32_t ret;
4491
4492 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FIFO_DATA_OUT_TAG, buff, 7);
4493 if (ret != 0)
4494 {
4495 return ret;
4496 }
4497
4498 bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]);
4499
4500 switch (fifo_data_out_tag.tag_sensor)
4501 {
4502 case LSM6DSV32X_FIFO_EMPTY:
4503 val->tag = LSM6DSV32X_FIFO_EMPTY;
4504 break;
4505
4506 case LSM6DSV32X_GY_NC_TAG:
4507 val->tag = LSM6DSV32X_GY_NC_TAG;
4508 break;
4509
4510 case LSM6DSV32X_XL_NC_TAG:
4511 val->tag = LSM6DSV32X_XL_NC_TAG;
4512 break;
4513
4514 case LSM6DSV32X_TIMESTAMP_TAG:
4515 val->tag = LSM6DSV32X_TIMESTAMP_TAG;
4516 break;
4517
4518 case LSM6DSV32X_TEMPERATURE_TAG:
4519 val->tag = LSM6DSV32X_TEMPERATURE_TAG;
4520 break;
4521
4522 case LSM6DSV32X_CFG_CHANGE_TAG:
4523 val->tag = LSM6DSV32X_CFG_CHANGE_TAG;
4524 break;
4525
4526 case LSM6DSV32X_XL_NC_T_2_TAG:
4527 val->tag = LSM6DSV32X_XL_NC_T_2_TAG;
4528 break;
4529
4530 case LSM6DSV32X_XL_NC_T_1_TAG:
4531 val->tag = LSM6DSV32X_XL_NC_T_1_TAG;
4532 break;
4533
4534 case LSM6DSV32X_XL_2XC_TAG:
4535 val->tag = LSM6DSV32X_XL_2XC_TAG;
4536 break;
4537
4538 case LSM6DSV32X_XL_3XC_TAG:
4539 val->tag = LSM6DSV32X_XL_3XC_TAG;
4540 break;
4541
4542 case LSM6DSV32X_GY_NC_T_2_TAG:
4543 val->tag = LSM6DSV32X_GY_NC_T_2_TAG;
4544 break;
4545
4546 case LSM6DSV32X_GY_NC_T_1_TAG:
4547 val->tag = LSM6DSV32X_GY_NC_T_1_TAG;
4548 break;
4549
4550 case LSM6DSV32X_GY_2XC_TAG:
4551 val->tag = LSM6DSV32X_GY_2XC_TAG;
4552 break;
4553
4554 case LSM6DSV32X_GY_3XC_TAG:
4555 val->tag = LSM6DSV32X_GY_3XC_TAG;
4556 break;
4557
4558 case LSM6DSV32X_SENSORHUB_SLAVE0_TAG:
4559 val->tag = LSM6DSV32X_SENSORHUB_SLAVE0_TAG;
4560 break;
4561
4562 case LSM6DSV32X_SENSORHUB_SLAVE1_TAG:
4563 val->tag = LSM6DSV32X_SENSORHUB_SLAVE1_TAG;
4564 break;
4565
4566 case LSM6DSV32X_SENSORHUB_SLAVE2_TAG:
4567 val->tag = LSM6DSV32X_SENSORHUB_SLAVE2_TAG;
4568 break;
4569
4570 case LSM6DSV32X_SENSORHUB_SLAVE3_TAG:
4571 val->tag = LSM6DSV32X_SENSORHUB_SLAVE3_TAG;
4572 break;
4573
4574 case LSM6DSV32X_STEP_COUNTER_TAG:
4575 val->tag = LSM6DSV32X_STEP_COUNTER_TAG;
4576 break;
4577
4578 case LSM6DSV32X_SFLP_GAME_ROTATION_VECTOR_TAG:
4579 val->tag = LSM6DSV32X_SFLP_GAME_ROTATION_VECTOR_TAG;
4580 break;
4581
4582 case LSM6DSV32X_SFLP_GYROSCOPE_BIAS_TAG:
4583 val->tag = LSM6DSV32X_SFLP_GYROSCOPE_BIAS_TAG;
4584 break;
4585
4586 case LSM6DSV32X_SFLP_GRAVITY_VECTOR_TAG:
4587 val->tag = LSM6DSV32X_SFLP_GRAVITY_VECTOR_TAG;
4588 break;
4589
4590 case LSM6DSV32X_SENSORHUB_NACK_TAG:
4591 val->tag = LSM6DSV32X_SENSORHUB_NACK_TAG;
4592 break;
4593
4594 case LSM6DSV32X_MLC_RESULT_TAG:
4595 val->tag = LSM6DSV32X_MLC_RESULT_TAG;
4596 break;
4597
4598 case LSM6DSV32X_MLC_FILTER:
4599 val->tag = LSM6DSV32X_MLC_FILTER;
4600 break;
4601
4602 case LSM6DSV32X_MLC_FEATURE:
4603 val->tag = LSM6DSV32X_MLC_FEATURE;
4604 break;
4605
4606 case LSM6DSV32X_XL_DUAL_CORE:
4607 val->tag = LSM6DSV32X_XL_DUAL_CORE;
4608 break;
4609
4610 case LSM6DSV32X_GY_ENHANCED_EIS:
4611 val->tag = LSM6DSV32X_GY_ENHANCED_EIS;
4612 break;
4613
4614 default:
4615 val->tag = LSM6DSV32X_FIFO_EMPTY;
4616 break;
4617 }
4618
4619 val->cnt = fifo_data_out_tag.tag_cnt;
4620
4621 val->data[0] = buff[1];
4622 val->data[1] = buff[2];
4623 val->data[2] = buff[3];
4624 val->data[3] = buff[4];
4625 val->data[4] = buff[5];
4626 val->data[5] = buff[6];
4627
4628 return ret;
4629 }
4630
4631 /**
4632 * @brief Batching in FIFO buffer of step counter value.[set]
4633 *
4634 * @param ctx read / write interface definitions
4635 * @param val Batching in FIFO buffer of step counter value.
4636 * @retval interface status (MANDATORY: return 0 -> no Error)
4637 *
4638 */
lsm6dsv32x_fifo_stpcnt_batch_set(const stmdev_ctx_t * ctx,uint8_t val)4639 int32_t lsm6dsv32x_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
4640 {
4641 lsm6dsv32x_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4642 int32_t ret;
4643
4644 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
4645 if (ret != 0)
4646 {
4647 return ret;
4648 }
4649
4650 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4651 emb_func_fifo_en_a.step_counter_fifo_en = val;
4652 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4653
4654 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
4655
4656 return ret;
4657 }
4658
4659 /**
4660 * @brief Batching in FIFO buffer of step counter value.[get]
4661 *
4662 * @param ctx read / write interface definitions
4663 * @param val Batching in FIFO buffer of step counter value.
4664 * @retval interface status (MANDATORY: return 0 -> no Error)
4665 *
4666 */
lsm6dsv32x_fifo_stpcnt_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)4667 int32_t lsm6dsv32x_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
4668 {
4669 lsm6dsv32x_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4670 int32_t ret;
4671
4672 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
4673 if (ret != 0)
4674 {
4675 return ret;
4676 }
4677
4678 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4679 *val = emb_func_fifo_en_a.step_counter_fifo_en;
4680
4681 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
4682
4683 return ret;
4684 }
4685
4686 /**
4687 * @brief Batching in FIFO buffer of machine learning core results.[set]
4688 *
4689 * @param ctx read / write interface definitions
4690 * @param val Batching in FIFO buffer of machine learning core results.
4691 * @retval interface status (MANDATORY: return 0 -> no Error)
4692 *
4693 */
lsm6dsv32x_fifo_mlc_batch_set(const stmdev_ctx_t * ctx,uint8_t val)4694 int32_t lsm6dsv32x_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
4695 {
4696 lsm6dsv32x_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4697 int32_t ret;
4698
4699 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
4700 if (ret != 0)
4701 {
4702 return ret;
4703 }
4704
4705 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4706 emb_func_fifo_en_a.mlc_fifo_en = val;
4707 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4708
4709 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
4710
4711 return ret;
4712 }
4713
4714 /**
4715 * @brief Batching in FIFO buffer of machine learning core results.[get]
4716 *
4717 * @param ctx read / write interface definitions
4718 * @param val Batching in FIFO buffer of machine learning core results.
4719 * @retval interface status (MANDATORY: return 0 -> no Error)
4720 *
4721 */
lsm6dsv32x_fifo_mlc_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)4722 int32_t lsm6dsv32x_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
4723 {
4724 lsm6dsv32x_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4725 int32_t ret;
4726
4727 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
4728 if (ret != 0)
4729 {
4730 return ret;
4731 }
4732
4733 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4734 *val = emb_func_fifo_en_a.mlc_fifo_en;
4735
4736 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
4737
4738 return ret;
4739 }
4740
4741 /**
4742 * @brief Enables batching in FIFO buffer of machine learning core filters and features.[set]
4743 *
4744 * @param ctx read / write interface definitions
4745 * @param val Enables batching in FIFO buffer of machine learning core filters and features.
4746 * @retval interface status (MANDATORY: return 0 -> no Error)
4747 *
4748 */
lsm6dsv32x_fifo_mlc_filt_batch_set(const stmdev_ctx_t * ctx,uint8_t val)4749 int32_t lsm6dsv32x_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
4750 {
4751 lsm6dsv32x_emb_func_fifo_en_b_t emb_func_fifo_en_b;
4752 int32_t ret;
4753
4754 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
4755 if (ret != 0)
4756 {
4757 return ret;
4758 }
4759
4760 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1);
4761 emb_func_fifo_en_b.mlc_filter_feature_fifo_en = val;
4762 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1);
4763
4764 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
4765
4766 return ret;
4767 }
4768
4769 /**
4770 * @brief Enables batching in FIFO buffer of machine learning core filters and features.[get]
4771 *
4772 * @param ctx read / write interface definitions
4773 * @param val Enables batching in FIFO buffer of machine learning core filters and features.
4774 * @retval interface status (MANDATORY: return 0 -> no Error)
4775 *
4776 */
lsm6dsv32x_fifo_mlc_filt_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)4777 int32_t lsm6dsv32x_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
4778 {
4779 lsm6dsv32x_emb_func_fifo_en_b_t emb_func_fifo_en_b;
4780 int32_t ret;
4781
4782 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
4783 if (ret != 0)
4784 {
4785 return ret;
4786 }
4787
4788 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1);
4789 *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en;
4790
4791 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
4792
4793 return ret;
4794 }
4795
4796 /**
4797 * @brief Enable FIFO data batching of slave idx.[set]
4798 *
4799 * @param ctx read / write interface definitions
4800 * @param val Enable FIFO data batching of slave idx.
4801 * @retval interface status (MANDATORY: return 0 -> no Error)
4802 *
4803 */
lsm6dsv32x_fifo_sh_batch_slave_set(const stmdev_ctx_t * ctx,uint8_t idx,uint8_t val)4804 int32_t lsm6dsv32x_fifo_sh_batch_slave_set(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t val)
4805 {
4806 lsm6dsv32x_slv0_config_t slv_config;
4807 int32_t ret;
4808
4809 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
4810 if (ret != 0)
4811 {
4812 return ret;
4813 }
4814
4815 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1);
4816 slv_config.batch_ext_sens_0_en = val;
4817 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1);
4818
4819 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
4820
4821 return ret;
4822 }
4823
4824 /**
4825 * @brief Enable FIFO data batching of slave idx.[get]
4826 *
4827 * @param ctx read / write interface definitions
4828 * @param val Enable FIFO data batching of slave idx.
4829 * @retval interface status (MANDATORY: return 0 -> no Error)
4830 *
4831 */
lsm6dsv32x_fifo_sh_batch_slave_get(const stmdev_ctx_t * ctx,uint8_t idx,uint8_t * val)4832 int32_t lsm6dsv32x_fifo_sh_batch_slave_get(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val)
4833 {
4834 lsm6dsv32x_slv0_config_t slv_config;
4835 int32_t ret;
4836
4837 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
4838 if (ret != 0)
4839 {
4840 return ret;
4841 }
4842
4843 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1);
4844 *val = slv_config.batch_ext_sens_0_en;
4845
4846 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
4847
4848 return ret;
4849 }
4850
4851 /**
4852 * @brief Batching in FIFO buffer of SFLP.[set]
4853 *
4854 * @param ctx read / write interface definitions
4855 * @param val Batching in FIFO buffer of SFLP values.
4856 * @retval interface status (MANDATORY: return 0 -> no Error)
4857 *
4858 */
lsm6dsv32x_fifo_sflp_batch_set(const stmdev_ctx_t * ctx,lsm6dsv32x_fifo_sflp_raw_t val)4859 int32_t lsm6dsv32x_fifo_sflp_batch_set(const stmdev_ctx_t *ctx,
4860 lsm6dsv32x_fifo_sflp_raw_t val)
4861 {
4862 lsm6dsv32x_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4863 int32_t ret;
4864
4865 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
4866 if (ret == 0)
4867 {
4868 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4869 emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation;
4870 emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity;
4871 emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias;
4872 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A,
4873 (uint8_t *)&emb_func_fifo_en_a, 1);
4874 }
4875
4876 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
4877
4878 return ret;
4879 }
4880
4881 /**
4882 * @brief Batching in FIFO buffer of SFLP.[get]
4883 *
4884 * @param ctx read / write interface definitions
4885 * @param val Batching in FIFO buffer of SFLP values.
4886 * @retval interface status (MANDATORY: return 0 -> no Error)
4887 *
4888 */
lsm6dsv32x_fifo_sflp_batch_get(const stmdev_ctx_t * ctx,lsm6dsv32x_fifo_sflp_raw_t * val)4889 int32_t lsm6dsv32x_fifo_sflp_batch_get(const stmdev_ctx_t *ctx,
4890 lsm6dsv32x_fifo_sflp_raw_t *val)
4891 {
4892 lsm6dsv32x_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4893 int32_t ret;
4894
4895 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
4896 if (ret == 0)
4897 {
4898 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4899
4900 val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en;
4901 val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en;
4902 val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en;
4903 }
4904
4905 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
4906
4907 return ret;
4908 }
4909
4910 /**
4911 * @}
4912 *
4913 */
4914
4915 /**
4916 * @defgroup Filters
4917 * @brief This section group all the functions concerning the
4918 * filters configuration
4919 * @{
4920 *
4921 */
4922
4923 /**
4924 * @brief Protocol anti-spike filters.[set]
4925 *
4926 * @param ctx read / write interface definitions
4927 * @param val AUTO, ALWAYS_ACTIVE,
4928 * @retval interface status (MANDATORY: return 0 -> no Error)
4929 *
4930 */
lsm6dsv32x_filt_anti_spike_set(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_anti_spike_t val)4931 int32_t lsm6dsv32x_filt_anti_spike_set(const stmdev_ctx_t *ctx,
4932 lsm6dsv32x_filt_anti_spike_t val)
4933 {
4934 lsm6dsv32x_if_cfg_t if_cfg;
4935 int32_t ret;
4936
4937 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1);
4938
4939 if (ret == 0)
4940 {
4941 if_cfg.asf_ctrl = (uint8_t)val & 0x01U;
4942 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1);
4943 }
4944
4945 return ret;
4946 }
4947
4948 /**
4949 * @brief Protocol anti-spike filters.[get]
4950 *
4951 * @param ctx read / write interface definitions
4952 * @param val AUTO, ALWAYS_ACTIVE,
4953 * @retval interface status (MANDATORY: return 0 -> no Error)
4954 *
4955 */
lsm6dsv32x_filt_anti_spike_get(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_anti_spike_t * val)4956 int32_t lsm6dsv32x_filt_anti_spike_get(const stmdev_ctx_t *ctx,
4957 lsm6dsv32x_filt_anti_spike_t *val)
4958 {
4959 lsm6dsv32x_if_cfg_t if_cfg;
4960 int32_t ret;
4961
4962 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1);
4963 if (ret != 0)
4964 {
4965 return ret;
4966 }
4967
4968 switch (if_cfg.asf_ctrl)
4969 {
4970 case LSM6DSV32X_AUTO:
4971 *val = LSM6DSV32X_AUTO;
4972 break;
4973
4974 case LSM6DSV32X_ALWAYS_ACTIVE:
4975 *val = LSM6DSV32X_ALWAYS_ACTIVE;
4976 break;
4977
4978 default:
4979 *val = LSM6DSV32X_AUTO;
4980 break;
4981 }
4982
4983 return ret;
4984 }
4985
4986 /**
4987 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set]
4988 *
4989 * @param ctx read / write interface definitions
4990 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
4991 * @retval interface status (MANDATORY: return 0 -> no Error)
4992 *
4993 */
lsm6dsv32x_filt_settling_mask_set(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_settling_mask_t val)4994 int32_t lsm6dsv32x_filt_settling_mask_set(const stmdev_ctx_t *ctx,
4995 lsm6dsv32x_filt_settling_mask_t val)
4996 {
4997 lsm6dsv32x_emb_func_cfg_t emb_func_cfg;
4998 lsm6dsv32x_ui_int_ois_t ui_int_ois;
4999 lsm6dsv32x_ctrl4_t ctrl4;
5000 int32_t ret;
5001
5002 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1);
5003 ctrl4.drdy_mask = val.drdy;
5004 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1);
5005 if (ret != 0)
5006 {
5007 return ret;
5008 }
5009
5010 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
5011 emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl;
5012 emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g;
5013 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
5014 if (ret != 0)
5015 {
5016 return ret;
5017 }
5018
5019 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1);
5020 ui_int_ois.drdy_mask_ois = val.ois_drdy;
5021 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1);
5022
5023 return ret;
5024 }
5025
5026 /**
5027 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get]
5028 *
5029 * @param ctx read / write interface definitions
5030 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
5031 * @retval interface status (MANDATORY: return 0 -> no Error)
5032 *
5033 */
lsm6dsv32x_filt_settling_mask_get(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_settling_mask_t * val)5034 int32_t lsm6dsv32x_filt_settling_mask_get(const stmdev_ctx_t *ctx,
5035 lsm6dsv32x_filt_settling_mask_t *val)
5036 {
5037 lsm6dsv32x_emb_func_cfg_t emb_func_cfg;
5038 lsm6dsv32x_ui_int_ois_t ui_int_ois;
5039 lsm6dsv32x_ctrl4_t ctrl4;
5040 int32_t ret;
5041
5042 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL4, (uint8_t *)&ctrl4, 1);
5043 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
5044 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1);
5045
5046 val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl;
5047 val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl;
5048 val->drdy = ctrl4.drdy_mask;
5049
5050 return ret;
5051 }
5052
5053 /**
5054 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set]
5055 *
5056 * @param ctx read / write interface definitions
5057 * @param val It masks DRDY and Interrupts RQ until filter settling ends from OIS interface.
5058 * @retval interface status (MANDATORY: return 0 -> no Error)
5059 *
5060 */
lsm6dsv32x_filt_ois_settling_mask_set(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_ois_settling_mask_t val)5061 int32_t lsm6dsv32x_filt_ois_settling_mask_set(const stmdev_ctx_t *ctx,
5062 lsm6dsv32x_filt_ois_settling_mask_t val)
5063 {
5064 lsm6dsv32x_spi2_int_ois_t spi2_int_ois;
5065 int32_t ret;
5066
5067 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
5068
5069 if (ret == 0)
5070 {
5071 spi2_int_ois.drdy_mask_ois = val.ois_drdy;
5072 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
5073 }
5074
5075 return ret;
5076 }
5077
5078 /**
5079 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get]
5080 *
5081 * @param ctx read / write interface definitions
5082 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
5083 * @retval interface status (MANDATORY: return 0 -> no Error)
5084 *
5085 */
lsm6dsv32x_filt_ois_settling_mask_get(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_ois_settling_mask_t * val)5086 int32_t lsm6dsv32x_filt_ois_settling_mask_get(const stmdev_ctx_t *ctx,
5087 lsm6dsv32x_filt_ois_settling_mask_t *val)
5088 {
5089
5090 lsm6dsv32x_spi2_int_ois_t spi2_int_ois;
5091 int32_t ret;
5092
5093 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
5094 val->ois_drdy = spi2_int_ois.drdy_mask_ois;
5095
5096 return ret;
5097 }
5098
5099 /**
5100 * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[set]
5101 *
5102 * @param ctx read / write interface definitions
5103 * @param val GY_ULTRA_LIGHT, GY_VERY_LIGHT, GY_LIGHT, GY_MEDIUM, GY_STRONG, GY_VERY_STRONG, GY_AGGRESSIVE, GY_XTREME,
5104 * @retval interface status (MANDATORY: return 0 -> no Error)
5105 *
5106 */
lsm6dsv32x_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_gy_lp1_bandwidth_t val)5107 int32_t lsm6dsv32x_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
5108 lsm6dsv32x_filt_gy_lp1_bandwidth_t val)
5109 {
5110 lsm6dsv32x_ctrl6_t ctrl6;
5111 int32_t ret;
5112
5113 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL6, (uint8_t *)&ctrl6, 1);
5114 if (ret == 0)
5115 {
5116 ctrl6.lpf1_g_bw = (uint8_t)val & 0x0Fu;
5117 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL6, (uint8_t *)&ctrl6, 1);
5118 }
5119
5120 return ret;
5121 }
5122
5123 /**
5124 * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[get]
5125 *
5126 * @param ctx read / write interface definitions
5127 * @param val GY_ULTRA_LIGHT, GY_VERY_LIGHT, GY_LIGHT, GY_MEDIUM, GY_STRONG, GY_VERY_STRONG, GY_AGGRESSIVE, GY_XTREME,
5128 * @retval interface status (MANDATORY: return 0 -> no Error)
5129 *
5130 */
lsm6dsv32x_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_gy_lp1_bandwidth_t * val)5131 int32_t lsm6dsv32x_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
5132 lsm6dsv32x_filt_gy_lp1_bandwidth_t *val)
5133 {
5134 lsm6dsv32x_ctrl6_t ctrl6;
5135 int32_t ret;
5136
5137 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL6, (uint8_t *)&ctrl6, 1);
5138 if (ret != 0)
5139 {
5140 return ret;
5141 }
5142
5143 switch (ctrl6.lpf1_g_bw)
5144 {
5145 case LSM6DSV32X_GY_ULTRA_LIGHT:
5146 *val = LSM6DSV32X_GY_ULTRA_LIGHT;
5147 break;
5148
5149 case LSM6DSV32X_GY_VERY_LIGHT:
5150 *val = LSM6DSV32X_GY_VERY_LIGHT;
5151 break;
5152
5153 case LSM6DSV32X_GY_LIGHT:
5154 *val = LSM6DSV32X_GY_LIGHT;
5155 break;
5156
5157 case LSM6DSV32X_GY_MEDIUM:
5158 *val = LSM6DSV32X_GY_MEDIUM;
5159 break;
5160
5161 case LSM6DSV32X_GY_STRONG:
5162 *val = LSM6DSV32X_GY_STRONG;
5163 break;
5164
5165 case LSM6DSV32X_GY_VERY_STRONG:
5166 *val = LSM6DSV32X_GY_VERY_STRONG;
5167 break;
5168
5169 case LSM6DSV32X_GY_AGGRESSIVE:
5170 *val = LSM6DSV32X_GY_AGGRESSIVE;
5171 break;
5172
5173 case LSM6DSV32X_GY_XTREME:
5174 *val = LSM6DSV32X_GY_XTREME;
5175 break;
5176
5177 default:
5178 *val = LSM6DSV32X_GY_ULTRA_LIGHT;
5179 break;
5180 }
5181
5182 return ret;
5183 }
5184
5185 /**
5186 * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[set]
5187 *
5188 * @param ctx read / write interface definitions
5189 * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.
5190 * @retval interface status (MANDATORY: return 0 -> no Error)
5191 *
5192 */
lsm6dsv32x_filt_gy_lp1_set(const stmdev_ctx_t * ctx,uint8_t val)5193 int32_t lsm6dsv32x_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val)
5194 {
5195 lsm6dsv32x_ctrl7_t ctrl7;
5196 int32_t ret;
5197
5198 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1);
5199 if (ret == 0)
5200 {
5201 ctrl7.lpf1_g_en = val;
5202 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1);
5203 }
5204
5205 return ret;
5206 }
5207
5208
5209 /**
5210 * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[get]
5211 *
5212 * @param ctx read / write interface definitions
5213 * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.
5214 * @retval interface status (MANDATORY: return 0 -> no Error)
5215 *
5216 */
lsm6dsv32x_filt_gy_lp1_get(const stmdev_ctx_t * ctx,uint8_t * val)5217 int32_t lsm6dsv32x_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val)
5218 {
5219 lsm6dsv32x_ctrl7_t ctrl7;
5220 int32_t ret;
5221
5222 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1);
5223 *val = ctrl7.lpf1_g_en;
5224
5225 return ret;
5226 }
5227
5228 /**
5229 * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[set]
5230 *
5231 * @param ctx read / write interface definitions
5232 * @param val XL_ULTRA_LIGHT, XL_VERY_LIGHT, XL_LIGHT, XL_MEDIUM, XL_STRONG, XL_VERY_STRONG, XL_AGGRESSIVE, XL_XTREME,
5233 * @retval interface status (MANDATORY: return 0 -> no Error)
5234 *
5235 */
lsm6dsv32x_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_xl_lp2_bandwidth_t val)5236 int32_t lsm6dsv32x_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx,
5237 lsm6dsv32x_filt_xl_lp2_bandwidth_t val)
5238 {
5239 lsm6dsv32x_ctrl8_t ctrl8;
5240 int32_t ret;
5241
5242 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL8, (uint8_t *)&ctrl8, 1);
5243 if (ret == 0)
5244 {
5245 ctrl8.hp_lpf2_xl_bw = (uint8_t)val & 0x07U;
5246 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL8, (uint8_t *)&ctrl8, 1);
5247 }
5248
5249 return ret;
5250 }
5251
5252 /**
5253 * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[get]
5254 *
5255 * @param ctx read / write interface definitions
5256 * @param val XL_ULTRA_LIGHT, XL_VERY_LIGHT, XL_LIGHT, XL_MEDIUM, XL_STRONG, XL_VERY_STRONG, XL_AGGRESSIVE, XL_XTREME,
5257 * @retval interface status (MANDATORY: return 0 -> no Error)
5258 *
5259 */
lsm6dsv32x_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_xl_lp2_bandwidth_t * val)5260 int32_t lsm6dsv32x_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx,
5261 lsm6dsv32x_filt_xl_lp2_bandwidth_t *val)
5262 {
5263 lsm6dsv32x_ctrl8_t ctrl8;
5264 int32_t ret;
5265
5266 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL8, (uint8_t *)&ctrl8, 1);
5267 if (ret != 0)
5268 {
5269 return ret;
5270 }
5271
5272 switch (ctrl8.hp_lpf2_xl_bw)
5273 {
5274 case LSM6DSV32X_XL_ULTRA_LIGHT:
5275 *val = LSM6DSV32X_XL_ULTRA_LIGHT;
5276 break;
5277
5278 case LSM6DSV32X_XL_VERY_LIGHT:
5279 *val = LSM6DSV32X_XL_VERY_LIGHT;
5280 break;
5281
5282 case LSM6DSV32X_XL_LIGHT:
5283 *val = LSM6DSV32X_XL_LIGHT;
5284 break;
5285
5286 case LSM6DSV32X_XL_MEDIUM:
5287 *val = LSM6DSV32X_XL_MEDIUM;
5288 break;
5289
5290 case LSM6DSV32X_XL_STRONG:
5291 *val = LSM6DSV32X_XL_STRONG;
5292 break;
5293
5294 case LSM6DSV32X_XL_VERY_STRONG:
5295 *val = LSM6DSV32X_XL_VERY_STRONG;
5296 break;
5297
5298 case LSM6DSV32X_XL_AGGRESSIVE:
5299 *val = LSM6DSV32X_XL_AGGRESSIVE;
5300 break;
5301
5302 case LSM6DSV32X_XL_XTREME:
5303 *val = LSM6DSV32X_XL_XTREME;
5304 break;
5305
5306 default:
5307 *val = LSM6DSV32X_XL_ULTRA_LIGHT;
5308 break;
5309 }
5310
5311 return ret;
5312 }
5313
5314 /**
5315 * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[set]
5316 *
5317 * @param ctx read / write interface definitions
5318 * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.
5319 * @retval interface status (MANDATORY: return 0 -> no Error)
5320 *
5321 */
lsm6dsv32x_filt_xl_lp2_set(const stmdev_ctx_t * ctx,uint8_t val)5322 int32_t lsm6dsv32x_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val)
5323 {
5324 lsm6dsv32x_ctrl9_t ctrl9;
5325 int32_t ret;
5326
5327 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1);
5328 if (ret == 0)
5329 {
5330 ctrl9.lpf2_xl_en = val;
5331 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1);
5332 }
5333
5334 return ret;
5335 }
5336
5337 /**
5338 * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[get]
5339 *
5340 * @param ctx read / write interface definitions
5341 * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.
5342 * @retval interface status (MANDATORY: return 0 -> no Error)
5343 *
5344 */
lsm6dsv32x_filt_xl_lp2_get(const stmdev_ctx_t * ctx,uint8_t * val)5345 int32_t lsm6dsv32x_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val)
5346 {
5347 lsm6dsv32x_ctrl9_t ctrl9;
5348 int32_t ret;
5349
5350 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1);
5351 *val = ctrl9.lpf2_xl_en;
5352
5353 return ret;
5354 }
5355
5356 /**
5357 * @brief Accelerometer slope filter / high-pass filter selection.[set]
5358 *
5359 * @param ctx read / write interface definitions
5360 * @param val Accelerometer slope filter / high-pass filter selection.
5361 * @retval interface status (MANDATORY: return 0 -> no Error)
5362 *
5363 */
lsm6dsv32x_filt_xl_hp_set(const stmdev_ctx_t * ctx,uint8_t val)5364 int32_t lsm6dsv32x_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val)
5365 {
5366 lsm6dsv32x_ctrl9_t ctrl9;
5367 int32_t ret;
5368
5369 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1);
5370 if (ret == 0)
5371 {
5372 ctrl9.hp_slope_xl_en = val;
5373 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1);
5374 }
5375
5376 return ret;
5377 }
5378
5379 /**
5380 * @brief Accelerometer slope filter / high-pass filter selection.[get]
5381 *
5382 * @param ctx read / write interface definitions
5383 * @param val Accelerometer slope filter / high-pass filter selection.
5384 * @retval interface status (MANDATORY: return 0 -> no Error)
5385 *
5386 */
lsm6dsv32x_filt_xl_hp_get(const stmdev_ctx_t * ctx,uint8_t * val)5387 int32_t lsm6dsv32x_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val)
5388 {
5389 lsm6dsv32x_ctrl9_t ctrl9;
5390 int32_t ret;
5391
5392 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1);
5393 *val = ctrl9.hp_slope_xl_en;
5394
5395 return ret;
5396 }
5397
5398 /**
5399 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[set]
5400 *
5401 * @param ctx read / write interface definitions
5402 * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.
5403 * @retval interface status (MANDATORY: return 0 -> no Error)
5404 *
5405 */
lsm6dsv32x_filt_xl_fast_settling_set(const stmdev_ctx_t * ctx,uint8_t val)5406 int32_t lsm6dsv32x_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val)
5407 {
5408 lsm6dsv32x_ctrl9_t ctrl9;
5409 int32_t ret;
5410
5411 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1);
5412 if (ret == 0)
5413 {
5414 ctrl9.xl_fastsettl_mode = val;
5415 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1);
5416 }
5417
5418 return ret;
5419 }
5420
5421 /**
5422 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[get]
5423 *
5424 * @param ctx read / write interface definitions
5425 * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.
5426 * @retval interface status (MANDATORY: return 0 -> no Error)
5427 *
5428 */
lsm6dsv32x_filt_xl_fast_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)5429 int32_t lsm6dsv32x_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val)
5430 {
5431 lsm6dsv32x_ctrl9_t ctrl9;
5432 int32_t ret;
5433
5434 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1);
5435 *val = ctrl9.xl_fastsettl_mode;
5436
5437 return ret;
5438 }
5439
5440 /**
5441 * @brief Accelerometer high-pass filter mode.[set]
5442 *
5443 * @param ctx read / write interface definitions
5444 * @param val HP_MD_NORMAL, HP_MD_REFERENCE,
5445 * @retval interface status (MANDATORY: return 0 -> no Error)
5446 *
5447 */
lsm6dsv32x_filt_xl_hp_mode_set(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_xl_hp_mode_t val)5448 int32_t lsm6dsv32x_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx,
5449 lsm6dsv32x_filt_xl_hp_mode_t val)
5450 {
5451 lsm6dsv32x_ctrl9_t ctrl9;
5452 int32_t ret;
5453
5454 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1);
5455 if (ret == 0)
5456 {
5457 ctrl9.hp_ref_mode_xl = (uint8_t)val & 0x01U;
5458 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1);
5459 }
5460
5461 return ret;
5462 }
5463
5464 /**
5465 * @brief Accelerometer high-pass filter mode.[get]
5466 *
5467 * @param ctx read / write interface definitions
5468 * @param val HP_MD_NORMAL, HP_MD_REFERENCE,
5469 * @retval interface status (MANDATORY: return 0 -> no Error)
5470 *
5471 */
lsm6dsv32x_filt_xl_hp_mode_get(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_xl_hp_mode_t * val)5472 int32_t lsm6dsv32x_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx,
5473 lsm6dsv32x_filt_xl_hp_mode_t *val)
5474 {
5475 lsm6dsv32x_ctrl9_t ctrl9;
5476 int32_t ret;
5477
5478 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL9, (uint8_t *)&ctrl9, 1);
5479 if (ret != 0)
5480 {
5481 return ret;
5482 }
5483
5484 switch (ctrl9.hp_ref_mode_xl)
5485 {
5486 case LSM6DSV32X_HP_MD_NORMAL:
5487 *val = LSM6DSV32X_HP_MD_NORMAL;
5488 break;
5489
5490 case LSM6DSV32X_HP_MD_REFERENCE:
5491 *val = LSM6DSV32X_HP_MD_REFERENCE;
5492 break;
5493
5494 default:
5495 *val = LSM6DSV32X_HP_MD_NORMAL;
5496 break;
5497 }
5498
5499 return ret;
5500 }
5501
5502 /**
5503 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[set]
5504 *
5505 * @param ctx read / write interface definitions
5506 * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, WK_FEED_LP_WITH_OFFSET,
5507 * @retval interface status (MANDATORY: return 0 -> no Error)
5508 *
5509 */
lsm6dsv32x_filt_wkup_act_feed_set(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_wkup_act_feed_t val)5510 int32_t lsm6dsv32x_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx,
5511 lsm6dsv32x_filt_wkup_act_feed_t val)
5512 {
5513 lsm6dsv32x_wake_up_ths_t wake_up_ths;
5514 lsm6dsv32x_tap_cfg0_t tap_cfg0;
5515 int32_t ret;
5516
5517 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
5518 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5519 if (ret != 0)
5520 {
5521 return ret;
5522 }
5523
5524 tap_cfg0.slope_fds = (uint8_t)val & 0x01U;
5525 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5526 if (ret != 0)
5527 {
5528 return ret;
5529 }
5530
5531 wake_up_ths.usr_off_on_wu = ((uint8_t)val & 0x02U) >> 1;
5532 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
5533
5534 return ret;
5535 }
5536
5537 /**
5538 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[get]
5539 *
5540 * @param ctx read / write interface definitions
5541 * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, WK_FEED_LP_WITH_OFFSET,
5542 * @retval interface status (MANDATORY: return 0 -> no Error)
5543 *
5544 */
lsm6dsv32x_filt_wkup_act_feed_get(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_wkup_act_feed_t * val)5545 int32_t lsm6dsv32x_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx,
5546 lsm6dsv32x_filt_wkup_act_feed_t *val)
5547 {
5548 lsm6dsv32x_wake_up_ths_t wake_up_ths;
5549 lsm6dsv32x_tap_cfg0_t tap_cfg0;
5550 int32_t ret;
5551
5552 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
5553 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5554 if (ret != 0)
5555 {
5556 return ret;
5557 }
5558
5559 switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds)
5560 {
5561 case LSM6DSV32X_WK_FEED_SLOPE:
5562 *val = LSM6DSV32X_WK_FEED_SLOPE;
5563 break;
5564
5565 case LSM6DSV32X_WK_FEED_HIGH_PASS:
5566 *val = LSM6DSV32X_WK_FEED_HIGH_PASS;
5567 break;
5568
5569 case LSM6DSV32X_WK_FEED_LP_WITH_OFFSET:
5570 *val = LSM6DSV32X_WK_FEED_LP_WITH_OFFSET;
5571 break;
5572
5573 default:
5574 *val = LSM6DSV32X_WK_FEED_SLOPE;
5575 break;
5576 }
5577
5578 return ret;
5579 }
5580
5581 /**
5582 * @brief Mask hw function triggers when xl is settling.[set]
5583 *
5584 * @param ctx read / write interface definitions
5585 * @param val 0 or 1,
5586 * @retval interface status (MANDATORY: return 0 -> no Error)
5587 *
5588 */
lsm6dsv32x_mask_trigger_xl_settl_set(const stmdev_ctx_t * ctx,uint8_t val)5589 int32_t lsm6dsv32x_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val)
5590 {
5591 lsm6dsv32x_tap_cfg0_t tap_cfg0;
5592 int32_t ret;
5593
5594 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5595
5596 if (ret == 0)
5597 {
5598 tap_cfg0.hw_func_mask_xl_settl = val & 0x01U;
5599 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5600 }
5601
5602 return ret;
5603 }
5604
5605 /**
5606 * @brief Mask hw function triggers when xl is settling.[get]
5607 *
5608 * @param ctx read / write interface definitions
5609 * @param val 0 or 1,
5610 * @retval interface status (MANDATORY: return 0 -> no Error)
5611 *
5612 */
lsm6dsv32x_mask_trigger_xl_settl_get(const stmdev_ctx_t * ctx,uint8_t * val)5613 int32_t lsm6dsv32x_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val)
5614 {
5615 lsm6dsv32x_tap_cfg0_t tap_cfg0;
5616 int32_t ret;
5617
5618 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5619 *val = tap_cfg0.hw_func_mask_xl_settl;
5620
5621 return ret;
5622 }
5623
5624 /**
5625 * @brief LPF2 filter on 6D (sixd) function selection.[set]
5626 *
5627 * @param ctx read / write interface definitions
5628 * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS,
5629 * @retval interface status (MANDATORY: return 0 -> no Error)
5630 *
5631 */
lsm6dsv32x_filt_sixd_feed_set(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_sixd_feed_t val)5632 int32_t lsm6dsv32x_filt_sixd_feed_set(const stmdev_ctx_t *ctx,
5633 lsm6dsv32x_filt_sixd_feed_t val)
5634 {
5635 lsm6dsv32x_tap_cfg0_t tap_cfg0;
5636 int32_t ret;
5637
5638 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5639
5640 if (ret == 0)
5641 {
5642 tap_cfg0.low_pass_on_6d = (uint8_t)val & 0x01U;
5643 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5644 }
5645
5646 return ret;
5647 }
5648
5649 /**
5650 * @brief LPF2 filter on 6D (sixd) function selection.[get]
5651 *
5652 * @param ctx read / write interface definitions
5653 * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS,
5654 * @retval interface status (MANDATORY: return 0 -> no Error)
5655 *
5656 */
lsm6dsv32x_filt_sixd_feed_get(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_sixd_feed_t * val)5657 int32_t lsm6dsv32x_filt_sixd_feed_get(const stmdev_ctx_t *ctx,
5658 lsm6dsv32x_filt_sixd_feed_t *val)
5659 {
5660 lsm6dsv32x_tap_cfg0_t tap_cfg0;
5661 int32_t ret;
5662
5663 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5664 if (ret != 0)
5665 {
5666 return ret;
5667 }
5668
5669 switch (tap_cfg0.low_pass_on_6d)
5670 {
5671 case LSM6DSV32X_SIXD_FEED_ODR_DIV_2:
5672 *val = LSM6DSV32X_SIXD_FEED_ODR_DIV_2;
5673 break;
5674
5675 case LSM6DSV32X_SIXD_FEED_LOW_PASS:
5676 *val = LSM6DSV32X_SIXD_FEED_LOW_PASS;
5677 break;
5678
5679 default:
5680 *val = LSM6DSV32X_SIXD_FEED_ODR_DIV_2;
5681 break;
5682 }
5683
5684 return ret;
5685 }
5686
5687 /**
5688 * @brief Gyroscope digital LPF_EIS filter bandwidth selection.[set]
5689 *
5690 * @param ctx read / write interface definitions
5691 * @param val EIS_LP_NORMAL, EIS_LP_LIGHT,
5692 * @retval interface status (MANDATORY: return 0 -> no Error)
5693 *
5694 */
lsm6dsv32x_filt_gy_eis_lp_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_gy_eis_lp_bandwidth_t val)5695 int32_t lsm6dsv32x_filt_gy_eis_lp_bandwidth_set(const stmdev_ctx_t *ctx,
5696 lsm6dsv32x_filt_gy_eis_lp_bandwidth_t val)
5697 {
5698 lsm6dsv32x_ctrl_eis_t ctrl_eis;
5699 int32_t ret;
5700
5701 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
5702
5703 if (ret == 0)
5704 {
5705 ctrl_eis.lpf_g_eis_bw = (uint8_t)val & 0x01U;
5706 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
5707 }
5708
5709 return ret;
5710 }
5711
5712 /**
5713 * @brief Gyroscope digital LPF_EIS filter bandwidth selection.[get]
5714 *
5715 * @param ctx read / write interface definitions
5716 * @param val EIS_LP_NORMAL, EIS_LP_LIGHT,
5717 * @retval interface status (MANDATORY: return 0 -> no Error)
5718 *
5719 */
lsm6dsv32x_filt_gy_eis_lp_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_gy_eis_lp_bandwidth_t * val)5720 int32_t lsm6dsv32x_filt_gy_eis_lp_bandwidth_get(const stmdev_ctx_t *ctx,
5721 lsm6dsv32x_filt_gy_eis_lp_bandwidth_t *val)
5722 {
5723 lsm6dsv32x_ctrl_eis_t ctrl_eis;
5724 int32_t ret;
5725
5726 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
5727 if (ret != 0)
5728 {
5729 return ret;
5730 }
5731
5732 switch (ctrl_eis.lpf_g_eis_bw)
5733 {
5734 case LSM6DSV32X_EIS_LP_NORMAL:
5735 *val = LSM6DSV32X_EIS_LP_NORMAL;
5736 break;
5737
5738 case LSM6DSV32X_EIS_LP_LIGHT:
5739 *val = LSM6DSV32X_EIS_LP_LIGHT;
5740 break;
5741
5742 default:
5743 *val = LSM6DSV32X_EIS_LP_NORMAL;
5744 break;
5745 }
5746
5747 return ret;
5748 }
5749
5750 /**
5751 * @brief Gyroscope OIS digital LPF1 filter bandwidth selection. This function works also on OIS interface (SPI2_CTRL2_OIS = UI_CTRL2_OIS).[set]
5752 *
5753 * @param ctx read / write interface definitions
5754 * @param val OIS_GY_LP_NORMAL, OIS_GY_LP_STRONG, OIS_GY_LP_AGGRESSIVE, OIS_GY_LP_LIGHT,
5755 * @retval interface status (MANDATORY: return 0 -> no Error)
5756 *
5757 */
lsm6dsv32x_filt_gy_ois_lp_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_gy_ois_lp_bandwidth_t val)5758 int32_t lsm6dsv32x_filt_gy_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx,
5759 lsm6dsv32x_filt_gy_ois_lp_bandwidth_t val)
5760 {
5761 lsm6dsv32x_ui_ctrl2_ois_t ui_ctrl2_ois;
5762 int32_t ret;
5763
5764 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
5765
5766 if (ret == 0)
5767 {
5768 ui_ctrl2_ois.lpf1_g_ois_bw = (uint8_t)val & 0x03U;
5769 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
5770 }
5771
5772 return ret;
5773 }
5774
5775 /**
5776 * @brief Gyroscope OIS digital LPF1 filter bandwidth selection. This function works also on OIS interface (SPI2_CTRL2_OIS = UI_CTRL2_OIS).[get]
5777 *
5778 * @param ctx read / write interface definitions
5779 * @param val OIS_GY_LP_NORMAL, OIS_GY_LP_STRONG, OIS_GY_LP_AGGRESSIVE, OIS_GY_LP_LIGHT,
5780 * @retval interface status (MANDATORY: return 0 -> no Error)
5781 *
5782 */
lsm6dsv32x_filt_gy_ois_lp_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_gy_ois_lp_bandwidth_t * val)5783 int32_t lsm6dsv32x_filt_gy_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx,
5784 lsm6dsv32x_filt_gy_ois_lp_bandwidth_t *val)
5785 {
5786
5787 lsm6dsv32x_ui_ctrl2_ois_t ui_ctrl2_ois;
5788 int32_t ret;
5789
5790 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
5791 if (ret != 0)
5792 {
5793 return ret;
5794 }
5795
5796 switch (ui_ctrl2_ois.lpf1_g_ois_bw)
5797 {
5798 case LSM6DSV32X_OIS_GY_LP_NORMAL:
5799 *val = LSM6DSV32X_OIS_GY_LP_NORMAL;
5800 break;
5801
5802 case LSM6DSV32X_OIS_GY_LP_STRONG:
5803 *val = LSM6DSV32X_OIS_GY_LP_STRONG;
5804 break;
5805
5806 case LSM6DSV32X_OIS_GY_LP_AGGRESSIVE:
5807 *val = LSM6DSV32X_OIS_GY_LP_AGGRESSIVE;
5808 break;
5809
5810 case LSM6DSV32X_OIS_GY_LP_LIGHT:
5811 *val = LSM6DSV32X_OIS_GY_LP_LIGHT;
5812 break;
5813
5814 default:
5815 *val = LSM6DSV32X_OIS_GY_LP_NORMAL;
5816 break;
5817 }
5818
5819 return ret;
5820 }
5821
5822 /**
5823 * @brief Selects accelerometer OIS channel bandwidth. This function works also on OIS interface (SPI2_CTRL3_OIS = UI_CTRL3_OIS).[set]
5824 *
5825 * @param ctx read / write interface definitions
5826 * @param val OIS_XL_LP_ULTRA_LIGHT, OIS_XL_LP_VERY_LIGHT, OIS_XL_LP_LIGHT, OIS_XL_LP_NORMAL, OIS_XL_LP_STRONG, OIS_XL_LP_VERY_STRONG, OIS_XL_LP_AGGRESSIVE, OIS_XL_LP_XTREME,
5827 * @retval interface status (MANDATORY: return 0 -> no Error)
5828 *
5829 */
lsm6dsv32x_filt_xl_ois_lp_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_xl_ois_lp_bandwidth_t val)5830 int32_t lsm6dsv32x_filt_xl_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx,
5831 lsm6dsv32x_filt_xl_ois_lp_bandwidth_t val)
5832 {
5833 lsm6dsv32x_ui_ctrl3_ois_t ui_ctrl3_ois;
5834 int32_t ret;
5835
5836 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
5837
5838 if (ret == 0)
5839 {
5840 ui_ctrl3_ois.lpf_xl_ois_bw = (uint8_t)val & 0x07U;
5841 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
5842 }
5843
5844 return ret;
5845 }
5846
5847 /**
5848 * @brief Selects accelerometer OIS channel bandwidth. This function works also on OIS interface (SPI2_CTRL3_OIS = UI_CTRL3_OIS).[get]
5849 *
5850 * @param ctx read / write interface definitions
5851 * @param val OIS_XL_LP_ULTRA_LIGHT, OIS_XL_LP_VERY_LIGHT, OIS_XL_LP_LIGHT, OIS_XL_LP_NORMAL, OIS_XL_LP_STRONG, OIS_XL_LP_VERY_STRONG, OIS_XL_LP_AGGRESSIVE, OIS_XL_LP_XTREME,
5852 * @retval interface status (MANDATORY: return 0 -> no Error)
5853 *
5854 */
lsm6dsv32x_filt_xl_ois_lp_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsv32x_filt_xl_ois_lp_bandwidth_t * val)5855 int32_t lsm6dsv32x_filt_xl_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx,
5856 lsm6dsv32x_filt_xl_ois_lp_bandwidth_t *val)
5857 {
5858 lsm6dsv32x_ui_ctrl3_ois_t ui_ctrl3_ois;
5859 int32_t ret;
5860
5861 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
5862 if (ret != 0)
5863 {
5864 return ret;
5865 }
5866
5867 switch (ui_ctrl3_ois.lpf_xl_ois_bw)
5868 {
5869 case LSM6DSV32X_OIS_XL_LP_ULTRA_LIGHT:
5870 *val = LSM6DSV32X_OIS_XL_LP_ULTRA_LIGHT;
5871 break;
5872
5873 case LSM6DSV32X_OIS_XL_LP_VERY_LIGHT:
5874 *val = LSM6DSV32X_OIS_XL_LP_VERY_LIGHT;
5875 break;
5876
5877 case LSM6DSV32X_OIS_XL_LP_LIGHT:
5878 *val = LSM6DSV32X_OIS_XL_LP_LIGHT;
5879 break;
5880
5881 case LSM6DSV32X_OIS_XL_LP_NORMAL:
5882 *val = LSM6DSV32X_OIS_XL_LP_NORMAL;
5883 break;
5884
5885 case LSM6DSV32X_OIS_XL_LP_STRONG:
5886 *val = LSM6DSV32X_OIS_XL_LP_STRONG;
5887 break;
5888
5889 case LSM6DSV32X_OIS_XL_LP_VERY_STRONG:
5890 *val = LSM6DSV32X_OIS_XL_LP_VERY_STRONG;
5891 break;
5892
5893 case LSM6DSV32X_OIS_XL_LP_AGGRESSIVE:
5894 *val = LSM6DSV32X_OIS_XL_LP_AGGRESSIVE;
5895 break;
5896
5897 case LSM6DSV32X_OIS_XL_LP_XTREME:
5898 *val = LSM6DSV32X_OIS_XL_LP_XTREME;
5899 break;
5900
5901 default:
5902 *val = LSM6DSV32X_OIS_XL_LP_ULTRA_LIGHT;
5903 break;
5904 }
5905
5906 return ret;
5907 }
5908
5909 /**
5910 * @}
5911 *
5912 */
5913
5914 /**
5915 * @defgroup Finite State Machine (FSM)
5916 * @brief This section groups all the functions that manage the
5917 * state_machine.
5918 * @{
5919 *
5920 */
5921
5922 /**
5923 * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[set]
5924 *
5925 * @param ctx read / write interface definitions
5926 * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG,
5927 * @retval interface status (MANDATORY: return 0 -> no Error)
5928 *
5929 */
lsm6dsv32x_fsm_permission_set(const stmdev_ctx_t * ctx,lsm6dsv32x_fsm_permission_t val)5930 int32_t lsm6dsv32x_fsm_permission_set(const stmdev_ctx_t *ctx,
5931 lsm6dsv32x_fsm_permission_t val)
5932 {
5933 lsm6dsv32x_func_cfg_access_t func_cfg_access;
5934 int32_t ret;
5935
5936 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
5937
5938 if (ret == 0)
5939 {
5940 func_cfg_access.fsm_wr_ctrl_en = (uint8_t)val & 0x01U;
5941 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
5942 }
5943
5944 return ret;
5945 }
5946
5947 /**
5948 * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[get]
5949 *
5950 * @param ctx read / write interface definitions
5951 * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG,
5952 * @retval interface status (MANDATORY: return 0 -> no Error)
5953 *
5954 */
lsm6dsv32x_fsm_permission_get(const stmdev_ctx_t * ctx,lsm6dsv32x_fsm_permission_t * val)5955 int32_t lsm6dsv32x_fsm_permission_get(const stmdev_ctx_t *ctx,
5956 lsm6dsv32x_fsm_permission_t *val)
5957 {
5958 lsm6dsv32x_func_cfg_access_t func_cfg_access;
5959 int32_t ret;
5960
5961 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
5962 if (ret != 0)
5963 {
5964 return ret;
5965 }
5966
5967 switch (func_cfg_access.fsm_wr_ctrl_en)
5968 {
5969 case LSM6DSV32X_PROTECT_CTRL_REGS:
5970 *val = LSM6DSV32X_PROTECT_CTRL_REGS;
5971 break;
5972
5973 case LSM6DSV32X_WRITE_CTRL_REG:
5974 *val = LSM6DSV32X_WRITE_CTRL_REG;
5975 break;
5976
5977 default:
5978 *val = LSM6DSV32X_PROTECT_CTRL_REGS;
5979 break;
5980 }
5981
5982 return ret;
5983 }
5984
5985 /**
5986 * @brief Get the FSM permission status
5987 *
5988 * @param ctx read / write interface definitions
5989 * @param val 0: All reg writable from std if - 1: some regs are under FSM control.
5990 * @retval interface status (MANDATORY: return 0 -> no Error)
5991 *
5992 */
lsm6dsv32x_fsm_permission_status(const stmdev_ctx_t * ctx,uint8_t * val)5993 int32_t lsm6dsv32x_fsm_permission_status(const stmdev_ctx_t *ctx, uint8_t *val)
5994 {
5995 lsm6dsv32x_ctrl_status_t ctrl_status;
5996 int32_t ret;
5997
5998 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL_STATUS, (uint8_t *)&ctrl_status, 1);
5999
6000 *val = ctrl_status.fsm_wr_ctrl_status;
6001
6002 return ret;
6003 }
6004
6005 /**
6006 * @brief Enable Finite State Machine (FSM) feature.[set]
6007 *
6008 * @param ctx read / write interface definitions
6009 * @param val Enable Finite State Machine (FSM) feature.
6010 * @retval interface status (MANDATORY: return 0 -> no Error)
6011 *
6012 */
lsm6dsv32x_fsm_mode_set(const stmdev_ctx_t * ctx,lsm6dsv32x_fsm_mode_t val)6013 int32_t lsm6dsv32x_fsm_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_fsm_mode_t val)
6014 {
6015 lsm6dsv32x_emb_func_en_b_t emb_func_en_b;
6016 lsm6dsv32x_fsm_enable_t fsm_enable;
6017 int32_t ret;
6018
6019 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
6020 if (ret != 0)
6021 {
6022 return ret;
6023 }
6024
6025 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
6026 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
6027 if (ret != 0)
6028 {
6029 goto exit;
6030 }
6031
6032 if ((val.fsm1_en | val.fsm2_en | val.fsm3_en | val.fsm4_en
6033 | val.fsm5_en | val.fsm6_en | val.fsm7_en | val.fsm8_en) == PROPERTY_ENABLE)
6034 {
6035 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
6036 }
6037 else
6038 {
6039 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
6040 }
6041
6042 fsm_enable.fsm1_en = val.fsm1_en;
6043 fsm_enable.fsm2_en = val.fsm2_en;
6044 fsm_enable.fsm3_en = val.fsm3_en;
6045 fsm_enable.fsm4_en = val.fsm4_en;
6046 fsm_enable.fsm5_en = val.fsm5_en;
6047 fsm_enable.fsm6_en = val.fsm6_en;
6048 fsm_enable.fsm7_en = val.fsm7_en;
6049 fsm_enable.fsm8_en = val.fsm8_en;
6050
6051 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
6052 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
6053
6054 exit:
6055 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
6056
6057 return ret;
6058 }
6059
6060 /**
6061 * @brief Enable Finite State Machine (FSM) feature.[get]
6062 *
6063 * @param ctx read / write interface definitions
6064 * @param val Enable Finite State Machine (FSM) feature.
6065 * @retval interface status (MANDATORY: return 0 -> no Error)
6066 *
6067 */
lsm6dsv32x_fsm_mode_get(const stmdev_ctx_t * ctx,lsm6dsv32x_fsm_mode_t * val)6068 int32_t lsm6dsv32x_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_fsm_mode_t *val)
6069 {
6070 lsm6dsv32x_fsm_enable_t fsm_enable;
6071 int32_t ret;
6072
6073 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
6074 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
6075 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
6076 if (ret != 0)
6077 {
6078 return ret;
6079 }
6080
6081 val->fsm1_en = fsm_enable.fsm1_en;
6082 val->fsm2_en = fsm_enable.fsm2_en;
6083 val->fsm3_en = fsm_enable.fsm3_en;
6084 val->fsm4_en = fsm_enable.fsm4_en;
6085 val->fsm5_en = fsm_enable.fsm5_en;
6086 val->fsm6_en = fsm_enable.fsm6_en;
6087 val->fsm7_en = fsm_enable.fsm7_en;
6088 val->fsm8_en = fsm_enable.fsm8_en;
6089
6090 return ret;
6091 }
6092
6093 /**
6094 * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[set]
6095 *
6096 * @param ctx read / write interface definitions
6097 * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).
6098 * @retval interface status (MANDATORY: return 0 -> no Error)
6099 *
6100 */
lsm6dsv32x_fsm_long_cnt_set(const stmdev_ctx_t * ctx,uint16_t val)6101 int32_t lsm6dsv32x_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val)
6102 {
6103 uint8_t buff[2];
6104 int32_t ret;
6105
6106 buff[1] = (uint8_t)(val / 256U);
6107 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6108
6109 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
6110 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2);
6111 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
6112
6113 return ret;
6114 }
6115
6116 /**
6117 * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[get]
6118 *
6119 * @param ctx read / write interface definitions
6120 * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).
6121 * @retval interface status (MANDATORY: return 0 -> no Error)
6122 *
6123 */
lsm6dsv32x_fsm_long_cnt_get(const stmdev_ctx_t * ctx,uint16_t * val)6124 int32_t lsm6dsv32x_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val)
6125 {
6126 uint8_t buff[2];
6127 int32_t ret;
6128
6129 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
6130 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FSM_LONG_COUNTER_L, &buff[0], 2);
6131 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
6132 if (ret != 0)
6133 {
6134 return ret;
6135 }
6136
6137 *val = buff[1];
6138 *val = (*val * 256U) + buff[0];
6139
6140 return ret;
6141 }
6142
6143 /**
6144 * @brief FSM output registers[get]
6145 *
6146 * @param ctx read / write interface definitions
6147 * @param val FSM output registers
6148 * @retval interface status (MANDATORY: return 0 -> no Error)
6149 *
6150 */
lsm6dsv32x_fsm_out_get(const stmdev_ctx_t * ctx,lsm6dsv32x_fsm_out_t * val)6151 int32_t lsm6dsv32x_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv32x_fsm_out_t *val)
6152 {
6153 int32_t ret;
6154
6155 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
6156 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FSM_OUTS1, (uint8_t *)val, 8);
6157 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
6158
6159 return ret;
6160 }
6161
6162 /**
6163 * @brief Finite State Machine Output Data Rate (ODR) configuration.[set]
6164 *
6165 * @param ctx read / write interface definitions
6166 * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz,
6167 * @retval interface status (MANDATORY: return 0 -> no Error)
6168 *
6169 */
lsm6dsv32x_fsm_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv32x_fsm_data_rate_t val)6170 int32_t lsm6dsv32x_fsm_data_rate_set(const stmdev_ctx_t *ctx,
6171 lsm6dsv32x_fsm_data_rate_t val)
6172 {
6173 lsm6dsv32x_fsm_odr_t fsm_odr;
6174 int32_t ret;
6175
6176 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
6177 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FSM_ODR, (uint8_t *)&fsm_odr, 1);
6178 if (ret != 0)
6179 {
6180 goto exit;
6181 }
6182
6183 fsm_odr.fsm_odr = (uint8_t)val & 0x07U;
6184 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FSM_ODR, (uint8_t *)&fsm_odr, 1);
6185
6186 exit:
6187 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
6188
6189 return ret;
6190 }
6191
6192 /**
6193 * @brief Finite State Machine Output Data Rate (ODR) configuration.[get]
6194 *
6195 * @param ctx read / write interface definitions
6196 * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz,
6197 * @retval interface status (MANDATORY: return 0 -> no Error)
6198 *
6199 */
lsm6dsv32x_fsm_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv32x_fsm_data_rate_t * val)6200 int32_t lsm6dsv32x_fsm_data_rate_get(const stmdev_ctx_t *ctx,
6201 lsm6dsv32x_fsm_data_rate_t *val)
6202 {
6203 lsm6dsv32x_fsm_odr_t fsm_odr;
6204 int32_t ret;
6205
6206 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
6207 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FSM_ODR, (uint8_t *)&fsm_odr, 1);
6208 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
6209 if (ret != 0)
6210 {
6211 return ret;
6212 }
6213
6214 switch (fsm_odr.fsm_odr)
6215 {
6216 case LSM6DSV32X_FSM_15Hz:
6217 *val = LSM6DSV32X_FSM_15Hz;
6218 break;
6219
6220 case LSM6DSV32X_FSM_30Hz:
6221 *val = LSM6DSV32X_FSM_30Hz;
6222 break;
6223
6224 case LSM6DSV32X_FSM_60Hz:
6225 *val = LSM6DSV32X_FSM_60Hz;
6226 break;
6227
6228 case LSM6DSV32X_FSM_120Hz:
6229 *val = LSM6DSV32X_FSM_120Hz;
6230 break;
6231
6232 case LSM6DSV32X_FSM_240Hz:
6233 *val = LSM6DSV32X_FSM_240Hz;
6234 break;
6235
6236 case LSM6DSV32X_FSM_480Hz:
6237 *val = LSM6DSV32X_FSM_480Hz;
6238 break;
6239
6240 case LSM6DSV32X_FSM_960Hz:
6241 *val = LSM6DSV32X_FSM_960Hz;
6242 break;
6243
6244 default:
6245 *val = LSM6DSV32X_FSM_15Hz;
6246 break;
6247 }
6248
6249 return ret;
6250 }
6251
6252 /*
6253 * Original conversion routines taken from: https://github.com/numpy/numpy
6254 *
6255 * uint16_t npy_floatbits_to_halfbits(uint32_t f);
6256 * uint16_t npy_float_to_half(float_t f);
6257 *
6258 * Released under BSD-3-Clause License
6259 */
6260
6261 #define NPY_HALF_GENERATE_OVERFLOW 0 /* do not trigger FP overflow */
6262 #define NPY_HALF_GENERATE_UNDERFLOW 0 /* do not trigger FP underflow */
6263 #ifndef NPY_HALF_ROUND_TIES_TO_EVEN
6264 #define NPY_HALF_ROUND_TIES_TO_EVEN 1
6265 #endif
6266
npy_floatbits_to_halfbits(uint32_t f)6267 static uint16_t npy_floatbits_to_halfbits(uint32_t f)
6268 {
6269 uint32_t f_exp, f_sig;
6270 uint16_t h_sgn, h_exp, h_sig;
6271
6272 h_sgn = (uint16_t)((f & 0x80000000u) >> 16);
6273 f_exp = (f & 0x7f800000u);
6274
6275 /* Exponent overflow/NaN converts to signed inf/NaN */
6276 if (f_exp >= 0x47800000u)
6277 {
6278 if (f_exp == 0x7f800000u)
6279 {
6280 /* Inf or NaN */
6281 f_sig = (f & 0x007fffffu);
6282 if (f_sig != 0U)
6283 {
6284 /* NaN - propagate the flag in the significand... */
6285 uint16_t ret = (uint16_t)(0x7c00u + (f_sig >> 13));
6286 /* ...but make sure it stays a NaN */
6287 if (ret == 0x7c00u)
6288 {
6289 ret++;
6290 }
6291 return h_sgn + ret;
6292 }
6293 else
6294 {
6295 /* signed inf */
6296 return (uint16_t)(h_sgn + 0x7c00u);
6297 }
6298 }
6299 else
6300 {
6301 /* overflow to signed inf */
6302 #if NPY_HALF_GENERATE_OVERFLOW
6303 npy_set_floatstatus_overflow();
6304 #endif
6305 return (uint16_t)(h_sgn + 0x7c00u);
6306 }
6307 }
6308
6309 /* Exponent underflow converts to a subnormal half or signed zero */
6310 if (f_exp <= 0x38000000u)
6311 {
6312 /*
6313 * Signed zeros, subnormal floats, and floats with small
6314 * exponents all convert to signed zero half-floats.
6315 */
6316 if (f_exp < 0x33000000u)
6317 {
6318 #if NPY_HALF_GENERATE_UNDERFLOW
6319 /* If f != 0, it underflowed to 0 */
6320 if ((f & 0x7fffffff) != 0)
6321 {
6322 npy_set_floatstatus_underflow();
6323 }
6324 #endif
6325 return h_sgn;
6326 }
6327 /* Make the subnormal significand */
6328 f_exp >>= 23;
6329 f_sig = (0x00800000u + (f & 0x007fffffu));
6330 #if NPY_HALF_GENERATE_UNDERFLOW
6331 /* If it's not exactly represented, it underflowed */
6332 if ((f_sig & (((uint32_t)1 << (126 - f_exp)) - 1)) != 0)
6333 {
6334 npy_set_floatstatus_underflow();
6335 }
6336 #endif
6337 /*
6338 * Usually the significand is shifted by 13. For subnormals an
6339 * additional shift needs to occur. This shift is one for the largest
6340 * exponent giving a subnormal `f_exp = 0x38000000 >> 23 = 112`, which
6341 * offsets the new first bit. At most the shift can be 1+10 bits.
6342 */
6343 f_sig >>= (113U - f_exp);
6344 /* Handle rounding by adding 1 to the bit beyond half precision */
6345 #if NPY_HALF_ROUND_TIES_TO_EVEN
6346 /*
6347 * If the last bit in the half significand is 0 (already even), and
6348 * the remaining bit pattern is 1000...0, then we do not add one
6349 * to the bit after the half significand. However, the (113 - f_exp)
6350 * shift can lose up to 11 bits, so the || checks them in the original.
6351 * In all other cases, we can just add one.
6352 */
6353 if (((f_sig & 0x00003fffu) != 0x00001000u) || (f & 0x000007ffu))
6354 {
6355 f_sig += 0x00001000u;
6356 }
6357 #else
6358 f_sig += 0x00001000u;
6359 #endif
6360 h_sig = (uint16_t)(f_sig >> 13);
6361 /*
6362 * If the rounding causes a bit to spill into h_exp, it will
6363 * increment h_exp from zero to one and h_sig will be zero.
6364 * This is the correct result.
6365 */
6366 return (uint16_t)(h_sgn + h_sig);
6367 }
6368
6369 /* Regular case with no overflow or underflow */
6370 h_exp = (uint16_t)((f_exp - 0x38000000u) >> 13);
6371 /* Handle rounding by adding 1 to the bit beyond half precision */
6372 f_sig = (f & 0x007fffffu);
6373 #if NPY_HALF_ROUND_TIES_TO_EVEN
6374 /*
6375 * If the last bit in the half significand is 0 (already even), and
6376 * the remaining bit pattern is 1000...0, then we do not add one
6377 * to the bit after the half significand. In all other cases, we do.
6378 */
6379 if ((f_sig & 0x00003fffu) != 0x00001000u)
6380 {
6381 f_sig += 0x00001000u;
6382 }
6383 #else
6384 f_sig += 0x00001000u;
6385 #endif
6386 h_sig = (uint16_t)(f_sig >> 13);
6387 /*
6388 * If the rounding causes a bit to spill into h_exp, it will
6389 * increment h_exp by one and h_sig will be zero. This is the
6390 * correct result. h_exp may increment to 15, at greatest, in
6391 * which case the result overflows to a signed inf.
6392 */
6393 #if NPY_HALF_GENERATE_OVERFLOW
6394 h_sig += h_exp;
6395 if (h_sig == 0x7c00u)
6396 {
6397 npy_set_floatstatus_overflow();
6398 }
6399 return h_sgn + h_sig;
6400 #else
6401 return h_sgn + h_exp + h_sig;
6402 #endif
6403 }
6404
npy_float_to_half(float_t f)6405 static uint16_t npy_float_to_half(float_t f)
6406 {
6407 union
6408 {
6409 float_t f;
6410 uint32_t fbits;
6411 } conv;
6412 conv.f = f;
6413 return npy_floatbits_to_halfbits(conv.fbits);
6414 }
6415
6416 /**
6417 * @brief SFLP GBIAS value. The register value is expressed as half-precision
6418 * floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent
6419 * bits; F: 10 fraction bits).[set]
6420 *
6421 * @param ctx read / write interface definitions
6422 * @param val GBIAS x/y/z val.
6423 * @retval interface status (MANDATORY: return 0 -> no Error)
6424 *
6425 */
lsm6dsv32x_sflp_game_gbias_set(const stmdev_ctx_t * ctx,lsm6dsv32x_sflp_gbias_t * val)6426 int32_t lsm6dsv32x_sflp_game_gbias_set(const stmdev_ctx_t *ctx,
6427 lsm6dsv32x_sflp_gbias_t *val)
6428 {
6429 lsm6dsv32x_sflp_data_rate_t sflp_odr;
6430 lsm6dsv32x_emb_func_exec_status_t emb_func_sts;
6431 lsm6dsv32x_data_ready_t drdy;
6432 lsm6dsv32x_xl_full_scale_t xl_fs;
6433 lsm6dsv32x_ctrl10_t ctrl10;
6434 uint8_t master_config;
6435 uint8_t emb_func_en_saved[2];
6436 uint8_t conf_saved[2];
6437 uint8_t reg_zero[2] = {0x0, 0x0};
6438 uint16_t gbias_hf[3];
6439 float_t k = 0.005f;
6440 int16_t xl_data[3];
6441 int32_t data_tmp;
6442 uint8_t *data_ptr = (uint8_t *)&data_tmp;
6443 uint8_t i, j;
6444 int32_t ret;
6445
6446 ret = lsm6dsv32x_sflp_data_rate_get(ctx, &sflp_odr);
6447 if (ret != 0)
6448 {
6449 return ret;
6450 }
6451
6452 /* Calculate k factor */
6453 switch (sflp_odr)
6454 {
6455 default:
6456 case LSM6DSV32X_SFLP_15Hz:
6457 k = 0.04f;
6458 break;
6459 case LSM6DSV32X_SFLP_30Hz:
6460 k = 0.02f;
6461 break;
6462 case LSM6DSV32X_SFLP_60Hz:
6463 k = 0.01f;
6464 break;
6465 case LSM6DSV32X_SFLP_120Hz:
6466 k = 0.005f;
6467 break;
6468 case LSM6DSV32X_SFLP_240Hz:
6469 k = 0.0025f;
6470 break;
6471 case LSM6DSV32X_SFLP_480Hz:
6472 k = 0.00125f;
6473 break;
6474 }
6475
6476 /* compute gbias as half precision float in order to be put in embedded advanced feature register */
6477 gbias_hf[0] = npy_float_to_half(val->gbias_x * (3.14159265358979323846f / 180.0f) / k);
6478 gbias_hf[1] = npy_float_to_half(val->gbias_y * (3.14159265358979323846f / 180.0f) / k);
6479 gbias_hf[2] = npy_float_to_half(val->gbias_z * (3.14159265358979323846f / 180.0f) / k);
6480
6481 /* Save sensor configuration and set high-performance mode (if the sensor is in power-down mode, turn it on) */
6482 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL1, conf_saved, 2);
6483 ret += lsm6dsv32x_xl_mode_set(ctx, LSM6DSV32X_XL_HIGH_PERFORMANCE_MD);
6484 ret += lsm6dsv32x_gy_mode_set(ctx, LSM6DSV32X_GY_HIGH_PERFORMANCE_MD);
6485 if (((uint8_t)conf_saved[0] & 0x0FU) == (uint8_t)LSM6DSV32X_ODR_OFF)
6486 {
6487 ret += lsm6dsv32x_xl_data_rate_set(ctx, LSM6DSV32X_ODR_AT_120Hz);
6488 }
6489
6490 /* Make sure to turn the sensor-hub master off */
6491 ret += lsm6dsv32x_sh_master_get(ctx, &master_config);
6492 ret += lsm6dsv32x_sh_master_set(ctx, 0);
6493
6494 /* disable algos */
6495 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
6496 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, emb_func_en_saved, 2);
6497 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, reg_zero, 2);
6498 do
6499 {
6500 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EXEC_STATUS,
6501 (uint8_t *)&emb_func_sts, 1);
6502 } while (emb_func_sts.emb_func_endop != 1U);
6503 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
6504
6505 // enable gbias setting
6506 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1);
6507 ctrl10.emb_func_debug = 1;
6508 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1);
6509
6510 /* enable algos */
6511 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
6512 emb_func_en_saved[0] |= 0x02U; /* force SFLP GAME en */
6513 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, emb_func_en_saved,
6514 2);
6515 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
6516
6517 ret += lsm6dsv32x_xl_full_scale_get(ctx, &xl_fs);
6518
6519 /* Read XL data */
6520 do
6521 {
6522 ret += lsm6dsv32x_flag_data_ready_get(ctx, &drdy);
6523 } while (drdy.drdy_xl != 1U);
6524 ret += lsm6dsv32x_acceleration_raw_get(ctx, xl_data);
6525
6526 /* force sflp initialization */
6527 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
6528 for (i = 0; i < 3U; i++)
6529 {
6530 j = 0;
6531 data_tmp = (int32_t)xl_data[i];
6532 data_tmp <<= xl_fs; // shift based on current fs
6533 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SENSOR_HUB_1 + 3U * i,
6534 &data_ptr[j++], 1);
6535 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SENSOR_HUB_2 + 3U * i,
6536 &data_ptr[j++], 1);
6537 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SENSOR_HUB_3 + 3U * i, &data_ptr[j],
6538 1);
6539 }
6540 for (i = 0; i < 3U; i++)
6541 {
6542 j = 0;
6543 data_tmp = 0;
6544 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SENSOR_HUB_10 + 3U * i,
6545 &data_ptr[j++], 1);
6546 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SENSOR_HUB_11 + 3U * i,
6547 &data_ptr[j++], 1);
6548 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SENSOR_HUB_12 + 3U * i, &data_ptr[j],
6549 1);
6550 }
6551 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
6552
6553 // wait end_op (and at least 30 us)
6554 ctx->mdelay(1);
6555 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
6556 do
6557 {
6558 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EXEC_STATUS,
6559 (uint8_t *)&emb_func_sts, 1);
6560 } while (emb_func_sts.emb_func_endop != 1U);
6561 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
6562
6563 /* write gbias in embedded advanced features registers */
6564 ret += lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_SFLP_GAME_GBIASX_L,
6565 (uint8_t *)gbias_hf, 6);
6566
6567 /* reload previous sensor configuration */
6568 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL1, conf_saved, 2);
6569
6570 // disable gbias setting
6571 ctrl10.emb_func_debug = 0;
6572 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL10, (uint8_t *)&ctrl10, 1);
6573
6574 /* reload previous master configuration */
6575 ret += lsm6dsv32x_sh_master_set(ctx, master_config);
6576
6577 return ret;
6578 }
6579
6580 /**
6581 * @brief External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).[set]
6582 *
6583 * @param ctx read / write interface definitions
6584 * @param val External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).
6585 * @retval interface status (MANDATORY: return 0 -> no Error)
6586 *
6587 */
lsm6dsv32x_fsm_ext_sens_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)6588 int32_t lsm6dsv32x_fsm_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val)
6589 {
6590 uint8_t buff[2];
6591 int32_t ret;
6592
6593 buff[1] = (uint8_t)(val / 256U);
6594 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6595 ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_FSM_EXT_SENSITIVITY_L, (uint8_t *)&buff[0], 2);
6596
6597 return ret;
6598 }
6599
6600 /**
6601 * @brief External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).[get]
6602 *
6603 * @param ctx read / write interface definitions
6604 * @param val External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).
6605 * @retval interface status (MANDATORY: return 0 -> no Error)
6606 *
6607 */
lsm6dsv32x_fsm_ext_sens_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)6608 int32_t lsm6dsv32x_fsm_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx,
6609 uint16_t *val)
6610 {
6611 uint8_t buff[2];
6612 int32_t ret;
6613
6614 ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_FSM_EXT_SENSITIVITY_L, &buff[0], 2);
6615 if (ret != 0)
6616 {
6617 return ret;
6618 }
6619
6620 *val = buff[1];
6621 *val = (*val * 256U) + buff[0];
6622
6623 return ret;
6624 }
6625
6626 /**
6627 * @brief External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set]
6628 *
6629 * @param ctx read / write interface definitions
6630 * @param val External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
6631 * @retval interface status (MANDATORY: return 0 -> no Error)
6632 *
6633 */
lsm6dsv32x_fsm_ext_sens_offset_set(const stmdev_ctx_t * ctx,lsm6dsv32x_xl_fsm_ext_sens_offset_t val)6634 int32_t lsm6dsv32x_fsm_ext_sens_offset_set(const stmdev_ctx_t *ctx,
6635 lsm6dsv32x_xl_fsm_ext_sens_offset_t val)
6636 {
6637 uint8_t buff[6];
6638 int32_t ret;
6639
6640 buff[1] = (uint8_t)(val.x / 256U);
6641 buff[0] = (uint8_t)(val.x - (buff[1] * 256U));
6642 buff[3] = (uint8_t)(val.y / 256U);
6643 buff[2] = (uint8_t)(val.y - (buff[3] * 256U));
6644 buff[5] = (uint8_t)(val.z / 256U);
6645 buff[4] = (uint8_t)(val.z - (buff[5] * 256U));
6646 ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_FSM_EXT_OFFX_L, (uint8_t *)&buff[0], 6);
6647
6648 return ret;
6649 }
6650
6651 /**
6652 * @brief External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get]
6653 *
6654 * @param ctx read / write interface definitions
6655 * @param val External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
6656 * @retval interface status (MANDATORY: return 0 -> no Error)
6657 *
6658 */
lsm6dsv32x_fsm_ext_sens_offset_get(const stmdev_ctx_t * ctx,lsm6dsv32x_xl_fsm_ext_sens_offset_t * val)6659 int32_t lsm6dsv32x_fsm_ext_sens_offset_get(const stmdev_ctx_t *ctx,
6660 lsm6dsv32x_xl_fsm_ext_sens_offset_t *val)
6661 {
6662 uint8_t buff[6];
6663 int32_t ret;
6664
6665 ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_FSM_EXT_OFFX_L, &buff[0], 6);
6666 if (ret != 0)
6667 {
6668 return ret;
6669 }
6670
6671 val->x = buff[1];
6672 val->x = (val->x * 256U) + buff[0];
6673 val->y = buff[3];
6674 val->y = (val->y * 256U) + buff[2];
6675 val->z = buff[5];
6676 val->z = (val->z * 256U) + buff[4];
6677
6678 return ret;
6679 }
6680
6681 /**
6682 * @brief External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set]
6683 *
6684 * @param ctx read / write interface definitions
6685 * @param val External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
6686 * @retval interface status (MANDATORY: return 0 -> no Error)
6687 *
6688 */
lsm6dsv32x_fsm_ext_sens_matrix_set(const stmdev_ctx_t * ctx,lsm6dsv32x_xl_fsm_ext_sens_matrix_t val)6689 int32_t lsm6dsv32x_fsm_ext_sens_matrix_set(const stmdev_ctx_t *ctx,
6690 lsm6dsv32x_xl_fsm_ext_sens_matrix_t val)
6691 {
6692 uint8_t buff[12];
6693 int32_t ret;
6694
6695 buff[1] = (uint8_t)(val.xx / 256U);
6696 buff[0] = (uint8_t)(val.xx - (buff[1] * 256U));
6697 buff[3] = (uint8_t)(val.xy / 256U);
6698 buff[2] = (uint8_t)(val.xy - (buff[3] * 256U));
6699 buff[5] = (uint8_t)(val.xz / 256U);
6700 buff[4] = (uint8_t)(val.xz - (buff[5] * 256U));
6701 buff[7] = (uint8_t)(val.yy / 256U);
6702 buff[6] = (uint8_t)(val.yy - (buff[7] * 256U));
6703 buff[9] = (uint8_t)(val.yz / 256U);
6704 buff[8] = (uint8_t)(val.yz - (buff[9] * 256U));
6705 buff[11] = (uint8_t)(val.zz / 256U);
6706 buff[10] = (uint8_t)(val.zz - (buff[11] * 256U));
6707 ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_FSM_EXT_MATRIX_XX_L, (uint8_t *)&buff[0], 12);
6708
6709 return ret;
6710 }
6711
6712 /**
6713 * @brief External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get]
6714 *
6715 * @param ctx read / write interface definitions
6716 * @param val External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
6717 * @retval interface status (MANDATORY: return 0 -> no Error)
6718 *
6719 */
lsm6dsv32x_fsm_ext_sens_matrix_get(const stmdev_ctx_t * ctx,lsm6dsv32x_xl_fsm_ext_sens_matrix_t * val)6720 int32_t lsm6dsv32x_fsm_ext_sens_matrix_get(const stmdev_ctx_t *ctx,
6721 lsm6dsv32x_xl_fsm_ext_sens_matrix_t *val)
6722 {
6723 uint8_t buff[12];
6724 int32_t ret;
6725
6726 ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_FSM_EXT_MATRIX_XX_L, &buff[0], 12);
6727 if (ret != 0)
6728 {
6729 return ret;
6730 }
6731
6732 val->xx = buff[1];
6733 val->xx = (val->xx * 256U) + buff[0];
6734 val->xy = buff[3];
6735 val->xy = (val->xy * 256U) + buff[2];
6736 val->xz = buff[5];
6737 val->xz = (val->xz * 256U) + buff[4];
6738 val->yy = buff[7];
6739 val->yy = (val->yy * 256U) + buff[6];
6740 val->yz = buff[9];
6741 val->yz = (val->yz * 256U) + buff[8];
6742 val->zz = buff[11];
6743 val->zz = (val->zz * 256U) + buff[10];
6744
6745 return ret;
6746 }
6747
6748 /**
6749 * @brief External sensor z-axis coordinates rotation.[set]
6750 *
6751 * @param ctx read / write interface definitions
6752 * @param val Z_EQ_Y, Z_EQ_MIN_Y, Z_EQ_X, Z_EQ_MIN_X, Z_EQ_MIN_Z, Z_EQ_Z,
6753 * @retval interface status (MANDATORY: return 0 -> no Error)
6754 *
6755 */
lsm6dsv32x_fsm_ext_sens_z_orient_set(const stmdev_ctx_t * ctx,lsm6dsv32x_fsm_ext_sens_z_orient_t val)6756 int32_t lsm6dsv32x_fsm_ext_sens_z_orient_set(const stmdev_ctx_t *ctx,
6757 lsm6dsv32x_fsm_ext_sens_z_orient_t val)
6758 {
6759 lsm6dsv32x_ext_cfg_a_t ext_cfg_a;
6760 int32_t ret;
6761
6762 ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6763 ext_cfg_a.ext_z_axis = (uint8_t)val & 0x07U;
6764 ret += lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6765
6766 return ret;
6767 }
6768
6769 /**
6770 * @brief External sensor z-axis coordinates rotation.[get]
6771 *
6772 * @param ctx read / write interface definitions
6773 * @param val Z_EQ_Y, Z_EQ_MIN_Y, Z_EQ_X, Z_EQ_MIN_X, Z_EQ_MIN_Z, Z_EQ_Z,
6774 * @retval interface status (MANDATORY: return 0 -> no Error)
6775 *
6776 */
lsm6dsv32x_fsm_ext_sens_z_orient_get(const stmdev_ctx_t * ctx,lsm6dsv32x_fsm_ext_sens_z_orient_t * val)6777 int32_t lsm6dsv32x_fsm_ext_sens_z_orient_get(const stmdev_ctx_t *ctx,
6778 lsm6dsv32x_fsm_ext_sens_z_orient_t *val)
6779 {
6780 lsm6dsv32x_ext_cfg_a_t ext_cfg_a;
6781 int32_t ret;
6782
6783 ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6784 if (ret != 0)
6785 {
6786 return ret;
6787 }
6788
6789 switch (ext_cfg_a.ext_z_axis)
6790 {
6791 case LSM6DSV32X_Z_EQ_Y:
6792 *val = LSM6DSV32X_Z_EQ_Y;
6793 break;
6794
6795 case LSM6DSV32X_Z_EQ_MIN_Y:
6796 *val = LSM6DSV32X_Z_EQ_MIN_Y;
6797 break;
6798
6799 case LSM6DSV32X_Z_EQ_X:
6800 *val = LSM6DSV32X_Z_EQ_X;
6801 break;
6802
6803 case LSM6DSV32X_Z_EQ_MIN_X:
6804 *val = LSM6DSV32X_Z_EQ_MIN_X;
6805 break;
6806
6807 case LSM6DSV32X_Z_EQ_MIN_Z:
6808 *val = LSM6DSV32X_Z_EQ_MIN_Z;
6809 break;
6810
6811 case LSM6DSV32X_Z_EQ_Z:
6812 *val = LSM6DSV32X_Z_EQ_Z;
6813 break;
6814
6815 default:
6816 *val = LSM6DSV32X_Z_EQ_Y;
6817 break;
6818 }
6819
6820 return ret;
6821 }
6822
6823 /**
6824 * @brief External sensor Y-axis coordinates rotation.[set]
6825 *
6826 * @param ctx read / write interface definitions
6827 * @param val Y_EQ_Y, Y_EQ_MIN_Y, Y_EQ_X, Y_EQ_MIN_X, Y_EQ_MIN_Z, Y_EQ_Z,
6828 * @retval interface status (MANDATORY: return 0 -> no Error)
6829 *
6830 */
lsm6dsv32x_fsm_ext_sens_y_orient_set(const stmdev_ctx_t * ctx,lsm6dsv32x_fsm_ext_sens_y_orient_t val)6831 int32_t lsm6dsv32x_fsm_ext_sens_y_orient_set(const stmdev_ctx_t *ctx,
6832 lsm6dsv32x_fsm_ext_sens_y_orient_t val)
6833 {
6834 lsm6dsv32x_ext_cfg_a_t ext_cfg_a;
6835 int32_t ret;
6836
6837 ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6838 if (ret == 0)
6839 {
6840 ext_cfg_a.ext_y_axis = (uint8_t)val & 0x7U;
6841 ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6842 }
6843
6844 return ret;
6845 }
6846
6847 /**
6848 * @brief External sensor Y-axis coordinates rotation.[get]
6849 *
6850 * @param ctx read / write interface definitions
6851 * @param val Y_EQ_Y, Y_EQ_MIN_Y, Y_EQ_X, Y_EQ_MIN_X, Y_EQ_MIN_Z, Y_EQ_Z,
6852 * @retval interface status (MANDATORY: return 0 -> no Error)
6853 *
6854 */
lsm6dsv32x_fsm_ext_sens_y_orient_get(const stmdev_ctx_t * ctx,lsm6dsv32x_fsm_ext_sens_y_orient_t * val)6855 int32_t lsm6dsv32x_fsm_ext_sens_y_orient_get(const stmdev_ctx_t *ctx,
6856 lsm6dsv32x_fsm_ext_sens_y_orient_t *val)
6857 {
6858 lsm6dsv32x_ext_cfg_a_t ext_cfg_a;
6859 int32_t ret;
6860
6861 ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6862 if (ret != 0)
6863 {
6864 return ret;
6865 }
6866
6867 switch (ext_cfg_a.ext_y_axis)
6868 {
6869 case LSM6DSV32X_Y_EQ_Y:
6870 *val = LSM6DSV32X_Y_EQ_Y;
6871 break;
6872
6873 case LSM6DSV32X_Y_EQ_MIN_Y:
6874 *val = LSM6DSV32X_Y_EQ_MIN_Y;
6875 break;
6876
6877 case LSM6DSV32X_Y_EQ_X:
6878 *val = LSM6DSV32X_Y_EQ_X;
6879 break;
6880
6881 case LSM6DSV32X_Y_EQ_MIN_X:
6882 *val = LSM6DSV32X_Y_EQ_MIN_X;
6883 break;
6884
6885 case LSM6DSV32X_Y_EQ_MIN_Z:
6886 *val = LSM6DSV32X_Y_EQ_MIN_Z;
6887 break;
6888
6889 case LSM6DSV32X_Y_EQ_Z:
6890 *val = LSM6DSV32X_Y_EQ_Z;
6891 break;
6892
6893 default:
6894 *val = LSM6DSV32X_Y_EQ_Y;
6895 break;
6896 }
6897
6898 return ret;
6899 }
6900
6901 /**
6902 * @brief External sensor X-axis coordinates rotation.[set]
6903 *
6904 * @param ctx read / write interface definitions
6905 * @param val X_EQ_Y, X_EQ_MIN_Y, X_EQ_X, X_EQ_MIN_X, X_EQ_MIN_Z, X_EQ_Z,
6906 * @retval interface status (MANDATORY: return 0 -> no Error)
6907 *
6908 */
lsm6dsv32x_fsm_ext_sens_x_orient_set(const stmdev_ctx_t * ctx,lsm6dsv32x_fsm_ext_sens_x_orient_t val)6909 int32_t lsm6dsv32x_fsm_ext_sens_x_orient_set(const stmdev_ctx_t *ctx,
6910 lsm6dsv32x_fsm_ext_sens_x_orient_t val)
6911 {
6912 lsm6dsv32x_ext_cfg_b_t ext_cfg_b;
6913 int32_t ret;
6914
6915 ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1);
6916 if (ret == 0)
6917 {
6918 ext_cfg_b.ext_x_axis = (uint8_t)val & 0x7U;
6919 ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1);
6920 }
6921
6922 return ret;
6923 }
6924
6925 /**
6926 * @brief External sensor X-axis coordinates rotation.[get]
6927 *
6928 * @param ctx read / write interface definitions
6929 * @param val X_EQ_Y, X_EQ_MIN_Y, X_EQ_X, X_EQ_MIN_X, X_EQ_MIN_Z, X_EQ_Z,
6930 * @retval interface status (MANDATORY: return 0 -> no Error)
6931 *
6932 */
lsm6dsv32x_fsm_ext_sens_x_orient_get(const stmdev_ctx_t * ctx,lsm6dsv32x_fsm_ext_sens_x_orient_t * val)6933 int32_t lsm6dsv32x_fsm_ext_sens_x_orient_get(const stmdev_ctx_t *ctx,
6934 lsm6dsv32x_fsm_ext_sens_x_orient_t *val)
6935 {
6936 lsm6dsv32x_ext_cfg_b_t ext_cfg_b;
6937 int32_t ret;
6938
6939 ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1);
6940 if (ret != 0)
6941 {
6942 return ret;
6943 }
6944
6945 switch (ext_cfg_b.ext_x_axis)
6946 {
6947 case LSM6DSV32X_X_EQ_Y:
6948 *val = LSM6DSV32X_X_EQ_Y;
6949 break;
6950
6951 case LSM6DSV32X_X_EQ_MIN_Y:
6952 *val = LSM6DSV32X_X_EQ_MIN_Y;
6953 break;
6954
6955 case LSM6DSV32X_X_EQ_X:
6956 *val = LSM6DSV32X_X_EQ_X;
6957 break;
6958
6959 case LSM6DSV32X_X_EQ_MIN_X:
6960 *val = LSM6DSV32X_X_EQ_MIN_X;
6961 break;
6962
6963 case LSM6DSV32X_X_EQ_MIN_Z:
6964 *val = LSM6DSV32X_X_EQ_MIN_Z;
6965 break;
6966
6967 case LSM6DSV32X_X_EQ_Z:
6968 *val = LSM6DSV32X_X_EQ_Z;
6969 break;
6970
6971 default:
6972 *val = LSM6DSV32X_X_EQ_Y;
6973 break;
6974 }
6975
6976 return ret;
6977 }
6978
6979 /**
6980 * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[set]
6981 *
6982 * @param ctx read / write interface definitions
6983 * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.
6984 * @retval interface status (MANDATORY: return 0 -> no Error)
6985 *
6986 */
lsm6dsv32x_fsm_long_cnt_timeout_set(const stmdev_ctx_t * ctx,uint16_t val)6987 int32_t lsm6dsv32x_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val)
6988 {
6989 uint8_t buff[2];
6990 int32_t ret;
6991
6992 buff[1] = (uint8_t)(val / 256U);
6993 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6994 ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_FSM_LC_TIMEOUT_L,
6995 (uint8_t *)&buff[0], 2);
6996
6997 return ret;
6998 }
6999
7000 /**
7001 * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[get]
7002 *
7003 * @param ctx read / write interface definitions
7004 * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.
7005 * @retval interface status (MANDATORY: return 0 -> no Error)
7006 *
7007 */
lsm6dsv32x_fsm_long_cnt_timeout_get(const stmdev_ctx_t * ctx,uint16_t * val)7008 int32_t lsm6dsv32x_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val)
7009 {
7010 uint8_t buff[2];
7011 int32_t ret;
7012
7013 ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_FSM_LC_TIMEOUT_L, &buff[0],
7014 2);
7015 if (ret != 0)
7016 {
7017 return ret;
7018 }
7019
7020 *val = buff[1];
7021 *val = (*val * 256U) + buff[0];
7022
7023 return ret;
7024 }
7025
7026 /**
7027 * @brief FSM number of programs.[set]
7028 *
7029 * @param ctx read / write interface definitions
7030 * @param val FSM number of programs.
7031 * @retval interface status (MANDATORY: return 0 -> no Error)
7032 *
7033 */
lsm6dsv32x_fsm_number_of_programs_set(const stmdev_ctx_t * ctx,uint8_t val)7034 int32_t lsm6dsv32x_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val)
7035 {
7036 lsm6dsv32x_fsm_programs_t fsm_programs;
7037 int32_t ret;
7038
7039 ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_FSM_PROGRAMS,
7040 (uint8_t *)&fsm_programs, 1);
7041 if (ret == 0)
7042 {
7043 fsm_programs.fsm_n_prog = val;
7044 ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_FSM_PROGRAMS,
7045 (uint8_t *)&fsm_programs, 1);
7046 }
7047
7048 return ret;
7049 }
7050
7051 /**
7052 * @brief FSM number of programs.[get]
7053 *
7054 * @param ctx read / write interface definitions
7055 * @param val FSM number of programs.
7056 * @retval interface status (MANDATORY: return 0 -> no Error)
7057 *
7058 */
lsm6dsv32x_fsm_number_of_programs_get(const stmdev_ctx_t * ctx,uint8_t * val)7059 int32_t lsm6dsv32x_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val)
7060 {
7061 lsm6dsv32x_fsm_programs_t fsm_programs;
7062 int32_t ret;
7063
7064 ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_FSM_PROGRAMS,
7065 (uint8_t *)&fsm_programs, 1);
7066 *val = fsm_programs.fsm_n_prog;
7067
7068 return ret;
7069 }
7070
7071 /**
7072 * @brief FSM start address. First available address is 0x35C.[set]
7073 *
7074 * @param ctx read / write interface definitions
7075 * @param val FSM start address. First available address is 0x35C.
7076 * @retval interface status (MANDATORY: return 0 -> no Error)
7077 *
7078 */
lsm6dsv32x_fsm_start_address_set(const stmdev_ctx_t * ctx,uint16_t val)7079 int32_t lsm6dsv32x_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val)
7080 {
7081 uint8_t buff[2];
7082 int32_t ret;
7083
7084 buff[1] = (uint8_t)(val / 256U);
7085 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7086 ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_FSM_START_ADD_L,
7087 (uint8_t *)&buff[0], 2);
7088
7089 return ret;
7090 }
7091
7092 /**
7093 * @brief FSM start address. First available address is 0x35C.[get]
7094 *
7095 * @param ctx read / write interface definitions
7096 * @param val FSM start address. First available address is 0x35C.
7097 * @retval interface status (MANDATORY: return 0 -> no Error)
7098 *
7099 */
lsm6dsv32x_fsm_start_address_get(const stmdev_ctx_t * ctx,uint16_t * val)7100 int32_t lsm6dsv32x_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val)
7101 {
7102 uint8_t buff[2];
7103 int32_t ret;
7104
7105 ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_FSM_START_ADD_L, &buff[0], 2);
7106 if (ret != 0)
7107 {
7108 return ret;
7109 }
7110
7111 *val = buff[1];
7112 *val = (*val * 256U) + buff[0];
7113
7114 return ret;
7115 }
7116
7117 /**
7118 * @}
7119 *
7120 */
7121
7122 /**
7123 * @defgroup Free fall
7124 * @brief This section group all the functions concerning the free
7125 * fall detection.
7126 * @{
7127 *
7128 */
7129
7130 /**
7131 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set]
7132 *
7133 * @param ctx read / write interface definitions
7134 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
7135 * @retval interface status (MANDATORY: return 0 -> no Error)
7136 *
7137 */
lsm6dsv32x_ff_time_windows_set(const stmdev_ctx_t * ctx,uint8_t val)7138 int32_t lsm6dsv32x_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val)
7139 {
7140 lsm6dsv32x_wake_up_dur_t wake_up_dur;
7141 lsm6dsv32x_free_fall_t free_fall;
7142 int32_t ret;
7143
7144 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
7145 wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
7146 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
7147 if (ret != 0)
7148 {
7149 return ret;
7150 }
7151
7152 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FREE_FALL, (uint8_t *)&free_fall, 1);
7153 free_fall.ff_dur = (uint8_t)val & 0x1FU;
7154 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FREE_FALL, (uint8_t *)&free_fall, 1);
7155
7156 return ret;
7157 }
7158
7159 /**
7160 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get]
7161 *
7162 * @param ctx read / write interface definitions
7163 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
7164 * @retval interface status (MANDATORY: return 0 -> no Error)
7165 *
7166 */
lsm6dsv32x_ff_time_windows_get(const stmdev_ctx_t * ctx,uint8_t * val)7167 int32_t lsm6dsv32x_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val)
7168 {
7169 lsm6dsv32x_wake_up_dur_t wake_up_dur;
7170 lsm6dsv32x_free_fall_t free_fall;
7171 int32_t ret;
7172
7173 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
7174 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FREE_FALL, (uint8_t *)&free_fall, 1);
7175
7176 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
7177
7178 return ret;
7179 }
7180
7181 /**
7182 * @brief Free fall threshold setting.[set]
7183 *
7184 * @param ctx read / write interface definitions
7185 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
7186 * @retval interface status (MANDATORY: return 0 -> no Error)
7187 *
7188 */
lsm6dsv32x_ff_thresholds_set(const stmdev_ctx_t * ctx,lsm6dsv32x_ff_thresholds_t val)7189 int32_t lsm6dsv32x_ff_thresholds_set(const stmdev_ctx_t *ctx,
7190 lsm6dsv32x_ff_thresholds_t val)
7191 {
7192 lsm6dsv32x_free_fall_t free_fall;
7193 int32_t ret;
7194
7195 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FREE_FALL, (uint8_t *)&free_fall, 1);
7196 if (ret == 0)
7197 {
7198 free_fall.ff_ths = (uint8_t)val & 0x7U;
7199 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FREE_FALL, (uint8_t *)&free_fall, 1);
7200 }
7201
7202 return ret;
7203 }
7204
7205 /**
7206 * @brief Free fall threshold setting.[get]
7207 *
7208 * @param ctx read / write interface definitions
7209 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
7210 * @retval interface status (MANDATORY: return 0 -> no Error)
7211 *
7212 */
lsm6dsv32x_ff_thresholds_get(const stmdev_ctx_t * ctx,lsm6dsv32x_ff_thresholds_t * val)7213 int32_t lsm6dsv32x_ff_thresholds_get(const stmdev_ctx_t *ctx,
7214 lsm6dsv32x_ff_thresholds_t *val)
7215 {
7216 lsm6dsv32x_free_fall_t free_fall;
7217 int32_t ret;
7218
7219 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FREE_FALL, (uint8_t *)&free_fall, 1);
7220 if (ret != 0)
7221 {
7222 return ret;
7223 }
7224
7225 switch (free_fall.ff_ths)
7226 {
7227 case LSM6DSV32X_156_mg:
7228 *val = LSM6DSV32X_156_mg;
7229 break;
7230
7231 case LSM6DSV32X_219_mg:
7232 *val = LSM6DSV32X_219_mg;
7233 break;
7234
7235 case LSM6DSV32X_250_mg:
7236 *val = LSM6DSV32X_250_mg;
7237 break;
7238
7239 case LSM6DSV32X_312_mg:
7240 *val = LSM6DSV32X_312_mg;
7241 break;
7242
7243 case LSM6DSV32X_344_mg:
7244 *val = LSM6DSV32X_344_mg;
7245 break;
7246
7247 case LSM6DSV32X_406_mg:
7248 *val = LSM6DSV32X_406_mg;
7249 break;
7250
7251 case LSM6DSV32X_469_mg:
7252 *val = LSM6DSV32X_469_mg;
7253 break;
7254
7255 case LSM6DSV32X_500_mg:
7256 *val = LSM6DSV32X_500_mg;
7257 break;
7258
7259 default:
7260 *val = LSM6DSV32X_156_mg;
7261 break;
7262 }
7263
7264 return ret;
7265 }
7266
7267 /**
7268 * @}
7269 *
7270 */
7271
7272 /**
7273 * @defgroup Machine Learning Core (MLC)
7274 * @brief This section group all the functions concerning the
7275 * usage of Machine Learning Core
7276 * @{
7277 *
7278 */
7279
7280 /**
7281 * @brief It enables Machine Learning Core feature (MLC).
7282 * When the Machine Learning Core is enabled the Finite State Machine (FSM)
7283 * programs are executed before executing the MLC algorithms.[set]
7284 *
7285 * @param ctx read / write interface definitions
7286 * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM,
7287 * @retval interface status (MANDATORY: return 0 -> no Error)
7288 *
7289 */
lsm6dsv32x_mlc_set(const stmdev_ctx_t * ctx,lsm6dsv32x_mlc_mode_t val)7290 int32_t lsm6dsv32x_mlc_set(const stmdev_ctx_t *ctx, lsm6dsv32x_mlc_mode_t val)
7291 {
7292 lsm6dsv32x_emb_func_en_b_t emb_en_b;
7293 lsm6dsv32x_emb_func_en_a_t emb_en_a;
7294 int32_t ret;
7295
7296 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
7297 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
7298 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
7299 if (ret != 0)
7300 {
7301 goto exit;
7302 }
7303
7304 switch (val)
7305 {
7306 case LSM6DSV32X_MLC_OFF:
7307 emb_en_a.mlc_before_fsm_en = 0;
7308 emb_en_b.mlc_en = 0;
7309 break;
7310 case LSM6DSV32X_MLC_ON:
7311 emb_en_a.mlc_before_fsm_en = 0;
7312 emb_en_b.mlc_en = 1;
7313 break;
7314 case LSM6DSV32X_MLC_ON_BEFORE_FSM:
7315 emb_en_a.mlc_before_fsm_en = 1;
7316 emb_en_b.mlc_en = 0;
7317 break;
7318 default:
7319 break;
7320 }
7321
7322 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
7323 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
7324
7325 exit:
7326 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
7327
7328 return ret;
7329 }
7330
7331 /**
7332 * @brief It enables Machine Learning Core feature (MLC).
7333 * When the Machine Learning Core is enabled the Finite State Machine (FSM)
7334 * programs are executed before executing the MLC algorithms.[get]
7335 *
7336 * @param ctx read / write interface definitions
7337 * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM,
7338 * @retval interface status (MANDATORY: return 0 -> no Error)
7339 *
7340 */
lsm6dsv32x_mlc_get(const stmdev_ctx_t * ctx,lsm6dsv32x_mlc_mode_t * val)7341 int32_t lsm6dsv32x_mlc_get(const stmdev_ctx_t *ctx, lsm6dsv32x_mlc_mode_t *val)
7342 {
7343 lsm6dsv32x_emb_func_en_b_t emb_en_b;
7344 lsm6dsv32x_emb_func_en_a_t emb_en_a;
7345 int32_t ret;
7346
7347 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
7348 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
7349 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
7350 if (ret != 0)
7351 {
7352 goto exit;
7353 }
7354
7355 if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U)
7356 {
7357 *val = LSM6DSV32X_MLC_OFF;
7358 }
7359 else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U)
7360 {
7361 *val = LSM6DSV32X_MLC_ON;
7362 }
7363 else if (emb_en_a.mlc_before_fsm_en == 1U)
7364 {
7365 *val = LSM6DSV32X_MLC_ON_BEFORE_FSM;
7366 }
7367 else
7368 {
7369 /* Do nothing */
7370 }
7371
7372 exit:
7373 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
7374
7375 return ret;
7376 }
7377
7378 /**
7379 * @brief Machine Learning Core Output Data Rate (ODR) configuration.[set]
7380 *
7381 * @param ctx read / write interface definitions
7382 * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz,
7383 * @retval interface status (MANDATORY: return 0 -> no Error)
7384 *
7385 */
lsm6dsv32x_mlc_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv32x_mlc_data_rate_t val)7386 int32_t lsm6dsv32x_mlc_data_rate_set(const stmdev_ctx_t *ctx,
7387 lsm6dsv32x_mlc_data_rate_t val)
7388 {
7389 lsm6dsv32x_mlc_odr_t mlc_odr;
7390 int32_t ret;
7391
7392 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
7393 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MLC_ODR, (uint8_t *)&mlc_odr, 1);
7394 if (ret != 0)
7395 {
7396 goto exit;
7397 }
7398
7399 mlc_odr.mlc_odr = (uint8_t)val & 0x07U;
7400 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MLC_ODR, (uint8_t *)&mlc_odr, 1);
7401
7402 exit:
7403 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
7404
7405 return ret;
7406 }
7407
7408 /**
7409 * @brief Machine Learning Core Output Data Rate (ODR) configuration.[get]
7410 *
7411 * @param ctx read / write interface definitions
7412 * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz,
7413 * @retval interface status (MANDATORY: return 0 -> no Error)
7414 *
7415 */
lsm6dsv32x_mlc_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv32x_mlc_data_rate_t * val)7416 int32_t lsm6dsv32x_mlc_data_rate_get(const stmdev_ctx_t *ctx,
7417 lsm6dsv32x_mlc_data_rate_t *val)
7418 {
7419 lsm6dsv32x_mlc_odr_t mlc_odr;
7420 int32_t ret;
7421
7422 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
7423 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MLC_ODR, (uint8_t *)&mlc_odr, 1);
7424 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
7425 if (ret != 0)
7426 {
7427 return ret;
7428 }
7429
7430 switch (mlc_odr.mlc_odr)
7431 {
7432 case LSM6DSV32X_MLC_15Hz:
7433 *val = LSM6DSV32X_MLC_15Hz;
7434 break;
7435
7436 case LSM6DSV32X_MLC_30Hz:
7437 *val = LSM6DSV32X_MLC_30Hz;
7438 break;
7439
7440 case LSM6DSV32X_MLC_60Hz:
7441 *val = LSM6DSV32X_MLC_60Hz;
7442 break;
7443
7444 case LSM6DSV32X_MLC_120Hz:
7445 *val = LSM6DSV32X_MLC_120Hz;
7446 break;
7447
7448 case LSM6DSV32X_MLC_240Hz:
7449 *val = LSM6DSV32X_MLC_240Hz;
7450 break;
7451
7452 case LSM6DSV32X_MLC_480Hz:
7453 *val = LSM6DSV32X_MLC_480Hz;
7454 break;
7455
7456 case LSM6DSV32X_MLC_960Hz:
7457 *val = LSM6DSV32X_MLC_960Hz;
7458 break;
7459
7460 default:
7461 *val = LSM6DSV32X_MLC_15Hz;
7462 break;
7463 }
7464
7465 return ret;
7466 }
7467
7468 /**
7469 * @brief Output value of all MLC decision trees.[get]
7470 *
7471 * @param ctx read / write interface definitions
7472 * @param val Output value of all MLC decision trees.
7473 * @retval interface status (MANDATORY: return 0 -> no Error)
7474 *
7475 */
lsm6dsv32x_mlc_out_get(const stmdev_ctx_t * ctx,lsm6dsv32x_mlc_out_t * val)7476 int32_t lsm6dsv32x_mlc_out_get(const stmdev_ctx_t *ctx, lsm6dsv32x_mlc_out_t *val)
7477 {
7478 int32_t ret;
7479
7480 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
7481 if (ret == 0)
7482 {
7483 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MLC1_SRC, (uint8_t *)val, 4);
7484 }
7485 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
7486
7487 return ret;
7488 }
7489
7490 /**
7491 * @brief External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB).[set]
7492 *
7493 * @param ctx read / write interface definitions
7494 * @param val External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB).
7495 * @retval interface status (MANDATORY: return 0 -> no Error)
7496 *
7497 */
lsm6dsv32x_mlc_ext_sens_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)7498 int32_t lsm6dsv32x_mlc_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val)
7499 {
7500 uint8_t buff[2];
7501 int32_t ret;
7502
7503 buff[1] = (uint8_t)(val / 256U);
7504 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7505
7506 ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_MLC_EXT_SENSITIVITY_L,
7507 (uint8_t *)&buff[0], 2);
7508
7509 return ret;
7510 }
7511
7512 /**
7513 * @brief External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB).[get]
7514 *
7515 * @param ctx read / write interface definitions
7516 * @param val External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB).
7517 * @retval interface status (MANDATORY: return 0 -> no Error)
7518 *
7519 */
lsm6dsv32x_mlc_ext_sens_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)7520 int32_t lsm6dsv32x_mlc_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx,
7521 uint16_t *val)
7522 {
7523 uint8_t buff[2];
7524 int32_t ret;
7525
7526 ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_MLC_EXT_SENSITIVITY_L,
7527 &buff[0], 2);
7528 if (ret != 0)
7529 {
7530 return ret;
7531 }
7532
7533 *val = buff[1];
7534 *val = (*val * 256U) + buff[0];
7535
7536 return ret;
7537 }
7538
7539 /**
7540 * @}
7541 *
7542 */
7543
7544 /**
7545 * @defgroup Optical Image Stabilization (OIS)
7546 * @brief This section groups all the functions concerning
7547 * Optical Image Stabilization (OIS).
7548 * @{
7549 *
7550 */
7551
7552 /**
7553 * @brief Enable the full control of OIS configurations from the UI (User Interface).[set]
7554 *
7555 * @param ctx read / write interface definitions
7556 * @param val OIS_CTRL_FROM_OIS, OIS_CTRL_FROM_UI,
7557 * @retval interface status (MANDATORY: return 0 -> no Error)
7558 *
7559 */
lsm6dsv32x_ois_ctrl_mode_set(const stmdev_ctx_t * ctx,lsm6dsv32x_ois_ctrl_mode_t val)7560 int32_t lsm6dsv32x_ois_ctrl_mode_set(const stmdev_ctx_t *ctx,
7561 lsm6dsv32x_ois_ctrl_mode_t val)
7562 {
7563 lsm6dsv32x_func_cfg_access_t func_cfg_access;
7564 int32_t ret;
7565
7566 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
7567 if (ret == 0)
7568 {
7569 func_cfg_access.ois_ctrl_from_ui = (uint8_t)val & 0x1U;
7570 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
7571 }
7572
7573 return ret;
7574 }
7575
7576 /**
7577 * @brief Enable the full control of OIS configurations from the UI (User Interface).[get]
7578 *
7579 * @param ctx read / write interface definitions
7580 * @param val OIS_CTRL_FROM_OIS, OIS_CTRL_FROM_UI,
7581 * @retval interface status (MANDATORY: return 0 -> no Error)
7582 *
7583 */
lsm6dsv32x_ois_ctrl_mode_get(const stmdev_ctx_t * ctx,lsm6dsv32x_ois_ctrl_mode_t * val)7584 int32_t lsm6dsv32x_ois_ctrl_mode_get(const stmdev_ctx_t *ctx,
7585 lsm6dsv32x_ois_ctrl_mode_t *val)
7586 {
7587 lsm6dsv32x_func_cfg_access_t func_cfg_access;
7588 int32_t ret;
7589
7590 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
7591 if (ret != 0)
7592 {
7593 return ret;
7594 }
7595
7596 switch (func_cfg_access.ois_ctrl_from_ui)
7597 {
7598 case LSM6DSV32X_OIS_CTRL_FROM_OIS:
7599 *val = LSM6DSV32X_OIS_CTRL_FROM_OIS;
7600 break;
7601
7602 case LSM6DSV32X_OIS_CTRL_FROM_UI:
7603 *val = LSM6DSV32X_OIS_CTRL_FROM_UI;
7604 break;
7605
7606 default:
7607 *val = LSM6DSV32X_OIS_CTRL_FROM_OIS;
7608 break;
7609 }
7610
7611 return ret;
7612 }
7613
7614 /**
7615 * @brief Resets the control registers of OIS from the UI (User Interface)[set]
7616 *
7617 * @param ctx read / write interface definitions
7618 * @param val Resets the control registers of OIS from the UI (User Interface)
7619 * @retval interface status (MANDATORY: return 0 -> no Error)
7620 *
7621 */
lsm6dsv32x_ois_reset_set(const stmdev_ctx_t * ctx,int8_t val)7622 int32_t lsm6dsv32x_ois_reset_set(const stmdev_ctx_t *ctx, int8_t val)
7623 {
7624 lsm6dsv32x_func_cfg_access_t func_cfg_access;
7625 int32_t ret;
7626
7627 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
7628 if (ret == 0)
7629 {
7630 func_cfg_access.spi2_reset = (uint8_t)val;
7631 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
7632 }
7633
7634 return ret;
7635 }
7636
7637 /**
7638 * @brief Resets the control registers of OIS from the UI (User Interface)[get]
7639 *
7640 * @param ctx read / write interface definitions
7641 * @param val Resets the control registers of OIS from the UI (User Interface)
7642 * @retval interface status (MANDATORY: return 0 -> no Error)
7643 *
7644 */
lsm6dsv32x_ois_reset_get(const stmdev_ctx_t * ctx,int8_t * val)7645 int32_t lsm6dsv32x_ois_reset_get(const stmdev_ctx_t *ctx, int8_t *val)
7646 {
7647 lsm6dsv32x_func_cfg_access_t func_cfg_access;
7648 int32_t ret;
7649
7650 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
7651 *val = (int8_t)func_cfg_access.spi2_reset;
7652
7653 return ret;
7654 }
7655
7656 /**
7657 * @brief Enable/disable pull up on OIS interface.[set]
7658 *
7659 * @param ctx read / write interface definitions
7660 * @param val Enable/disable pull up on OIS interface.
7661 * @retval interface status (MANDATORY: return 0 -> no Error)
7662 *
7663 */
lsm6dsv32x_ois_interface_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)7664 int32_t lsm6dsv32x_ois_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
7665 {
7666 lsm6dsv32x_pin_ctrl_t pin_ctrl;
7667 int32_t ret;
7668
7669 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7670 if (ret == 0)
7671 {
7672 pin_ctrl.ois_pu_dis = val;
7673 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7674 }
7675
7676 return ret;
7677 }
7678
7679 /**
7680 * @brief Enable/disable pull up on OIS interface.[get]
7681 *
7682 * @param ctx read / write interface definitions
7683 * @param val Enable/disable pull up on OIS interface.
7684 * @retval interface status (MANDATORY: return 0 -> no Error)
7685 *
7686 */
lsm6dsv32x_ois_interface_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)7687 int32_t lsm6dsv32x_ois_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
7688 {
7689 lsm6dsv32x_pin_ctrl_t pin_ctrl;
7690 int32_t ret;
7691
7692 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7693 *val = pin_ctrl.ois_pu_dis;
7694
7695 return ret;
7696 }
7697
7698 /**
7699 * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[set]
7700 *
7701 * @param ctx read / write interface definitions
7702 * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.
7703 * @retval interface status (MANDATORY: return 0 -> no Error)
7704 *
7705 */
lsm6dsv32x_ois_handshake_from_ui_set(const stmdev_ctx_t * ctx,lsm6dsv32x_ois_handshake_t val)7706 int32_t lsm6dsv32x_ois_handshake_from_ui_set(const stmdev_ctx_t *ctx,
7707 lsm6dsv32x_ois_handshake_t val)
7708 {
7709 lsm6dsv32x_ui_handshake_ctrl_t ui_handshake_ctrl;
7710 int32_t ret;
7711
7712 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1);
7713 if (ret == 0)
7714 {
7715 ui_handshake_ctrl.ui_shared_ack = val.ack;
7716 ui_handshake_ctrl.ui_shared_req = val.req;
7717 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1);
7718 }
7719
7720 return ret;
7721 }
7722
7723 /**
7724 * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[get]
7725 *
7726 * @param ctx read / write interface definitions
7727 * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.
7728 * @retval interface status (MANDATORY: return 0 -> no Error)
7729 *
7730 */
lsm6dsv32x_ois_handshake_from_ui_get(const stmdev_ctx_t * ctx,lsm6dsv32x_ois_handshake_t * val)7731 int32_t lsm6dsv32x_ois_handshake_from_ui_get(const stmdev_ctx_t *ctx,
7732 lsm6dsv32x_ois_handshake_t *val)
7733 {
7734 lsm6dsv32x_ui_handshake_ctrl_t ui_handshake_ctrl;
7735 int32_t ret;
7736
7737 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1);
7738 if (ret != 0)
7739 {
7740 return ret;
7741 }
7742
7743 val->ack = ui_handshake_ctrl.ui_shared_ack;
7744 val->req = ui_handshake_ctrl.ui_shared_req;
7745
7746 return ret;
7747 }
7748
7749 /**
7750 * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[set]
7751 *
7752 * @param ctx read / write interface definitions
7753 * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.
7754 * @retval interface status (MANDATORY: return 0 -> no Error)
7755 *
7756 */
lsm6dsv32x_ois_handshake_from_ois_set(const stmdev_ctx_t * ctx,lsm6dsv32x_ois_handshake_t val)7757 int32_t lsm6dsv32x_ois_handshake_from_ois_set(const stmdev_ctx_t *ctx,
7758 lsm6dsv32x_ois_handshake_t val)
7759 {
7760 lsm6dsv32x_spi2_handshake_ctrl_t spi2_handshake_ctrl;
7761 int32_t ret;
7762
7763 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1);
7764 if (ret == 0)
7765 {
7766 spi2_handshake_ctrl.spi2_shared_ack = val.ack;
7767 spi2_handshake_ctrl.spi2_shared_req = val.req;
7768 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1);
7769 }
7770
7771 return ret;
7772 }
7773
7774 /**
7775 * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[get]
7776 *
7777 * @param ctx read / write interface definitions
7778 * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.
7779 * @retval interface status (MANDATORY: return 0 -> no Error)
7780 *
7781 */
lsm6dsv32x_ois_handshake_from_ois_get(const stmdev_ctx_t * ctx,lsm6dsv32x_ois_handshake_t * val)7782 int32_t lsm6dsv32x_ois_handshake_from_ois_get(const stmdev_ctx_t *ctx,
7783 lsm6dsv32x_ois_handshake_t *val)
7784 {
7785 lsm6dsv32x_spi2_handshake_ctrl_t spi2_handshake_ctrl;
7786 int32_t ret;
7787
7788 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1);
7789 if (ret != 0)
7790 {
7791 return ret;
7792 }
7793
7794 val->ack = spi2_handshake_ctrl.spi2_shared_ack;
7795 val->req = spi2_handshake_ctrl.spi2_shared_req;
7796
7797 return ret;
7798 }
7799
7800 /**
7801 * @brief User interface (UI) / SPI2 (OIS) shared registers[set]
7802 *
7803 * @param ctx read / write interface definitions
7804 * @param val User interface (UI) / SPI2 (OIS) shared registers
7805 * @retval interface status (MANDATORY: return 0 -> no Error)
7806 *
7807 */
lsm6dsv32x_ois_shared_set(const stmdev_ctx_t * ctx,uint8_t val[6])7808 int32_t lsm6dsv32x_ois_shared_set(const stmdev_ctx_t *ctx, uint8_t val[6])
7809 {
7810 int32_t ret;
7811
7812 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_SPI2_SHARED_0, val, 6);
7813
7814 return ret;
7815 }
7816
7817 /**
7818 * @brief User interface (UI) / SPI2 (OIS) shared registers[get]
7819 *
7820 * @param ctx read / write interface definitions
7821 * @param val User interface (UI) / SPI2 (OIS) shared registers
7822 * @retval interface status (MANDATORY: return 0 -> no Error)
7823 *
7824 */
lsm6dsv32x_ois_shared_get(const stmdev_ctx_t * ctx,uint8_t val[6])7825 int32_t lsm6dsv32x_ois_shared_get(const stmdev_ctx_t *ctx, uint8_t val[6])
7826 {
7827 int32_t ret;
7828
7829 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_SPI2_SHARED_0, val, 6);
7830
7831 return ret;
7832 }
7833
7834 /**
7835 * @brief In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set]
7836 *
7837 * @param ctx read / write interface definitions
7838 * @param val In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data.
7839 * @retval interface status (MANDATORY: return 0 -> no Error)
7840 *
7841 */
lsm6dsv32x_ois_on_spi2_set(const stmdev_ctx_t * ctx,uint8_t val)7842 int32_t lsm6dsv32x_ois_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val)
7843 {
7844 lsm6dsv32x_ui_ctrl1_ois_t ui_ctrl1_ois;
7845 int32_t ret;
7846
7847 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7848 if (ret == 0)
7849 {
7850 ui_ctrl1_ois.spi2_read_en = val;
7851 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7852 }
7853
7854 return ret;
7855 }
7856
7857 /**
7858 * @brief In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[get]
7859 *
7860 * @param ctx read / write interface definitions
7861 * @param val In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data.
7862 * @retval interface status (MANDATORY: return 0 -> no Error)
7863 *
7864 */
lsm6dsv32x_ois_on_spi2_get(const stmdev_ctx_t * ctx,uint8_t * val)7865 int32_t lsm6dsv32x_ois_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val)
7866 {
7867 lsm6dsv32x_ui_ctrl1_ois_t ui_ctrl1_ois;
7868 int32_t ret;
7869
7870 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7871 *val = ui_ctrl1_ois.spi2_read_en;
7872
7873 return ret;
7874 }
7875
7876 /**
7877 * @brief Enables gyroscope/accelerometer OIS chain. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set]
7878 *
7879 * @param ctx read / write interface definitions
7880 * @param val Enables gyroscope/accelerometer OIS chain.
7881 * @retval interface status (MANDATORY: return 0 -> no Error)
7882 *
7883 */
lsm6dsv32x_ois_chain_set(const stmdev_ctx_t * ctx,lsm6dsv32x_ois_chain_t val)7884 int32_t lsm6dsv32x_ois_chain_set(const stmdev_ctx_t *ctx, lsm6dsv32x_ois_chain_t val)
7885 {
7886 lsm6dsv32x_ui_ctrl1_ois_t ui_ctrl1_ois;
7887 int32_t ret;
7888
7889 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7890 if (ret == 0)
7891 {
7892 ui_ctrl1_ois.ois_g_en = val.gy;
7893 ui_ctrl1_ois.ois_xl_en = val.xl;
7894 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7895 }
7896
7897 return ret;
7898 }
7899
7900 /**
7901 * @brief Enables gyroscope/accelerometer OIS chain.[get]
7902 *
7903 * @param ctx read / write interface definitions
7904 * @param val Enables gyroscope/accelerometer OIS chain.
7905 * @retval interface status (MANDATORY: return 0 -> no Error)
7906 *
7907 */
lsm6dsv32x_ois_chain_get(const stmdev_ctx_t * ctx,lsm6dsv32x_ois_chain_t * val)7908 int32_t lsm6dsv32x_ois_chain_get(const stmdev_ctx_t *ctx, lsm6dsv32x_ois_chain_t *val)
7909 {
7910 lsm6dsv32x_ui_ctrl1_ois_t ui_ctrl1_ois;
7911 int32_t ret;
7912
7913 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7914 if (ret != 0)
7915 {
7916 return ret;
7917 }
7918
7919 val->gy = ui_ctrl1_ois.ois_g_en;
7920 val->xl = ui_ctrl1_ois.ois_xl_en;
7921
7922 return ret;
7923 }
7924
7925 /**
7926 * @brief Gyroscope OIS full-scale selection[set]
7927 *
7928 * @param ctx read / write interface definitions
7929 * @param val OIS_125dps, OIS_250dps, OIS_500dps, OIS_1000dps, OIS_2000dps,
7930 * @retval interface status (MANDATORY: return 0 -> no Error)
7931 *
7932 */
lsm6dsv32x_ois_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv32x_ois_gy_full_scale_t val)7933 int32_t lsm6dsv32x_ois_gy_full_scale_set(const stmdev_ctx_t *ctx,
7934 lsm6dsv32x_ois_gy_full_scale_t val)
7935 {
7936 lsm6dsv32x_ui_ctrl2_ois_t ui_ctrl2_ois;
7937 int32_t ret;
7938
7939 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
7940 if (ret == 0)
7941 {
7942 ui_ctrl2_ois.fs_g_ois = (uint8_t)val & 0x03U;
7943 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
7944 }
7945
7946 return ret;
7947 }
7948
7949 /**
7950 * @brief Gyroscope OIS full-scale selection[get]
7951 *
7952 * @param ctx read / write interface definitions
7953 * @param val OIS_125dps, OIS_250dps, OIS_500dps, OIS_1000dps, OIS_2000dps,
7954 * @retval interface status (MANDATORY: return 0 -> no Error)
7955 *
7956 */
lsm6dsv32x_ois_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv32x_ois_gy_full_scale_t * val)7957 int32_t lsm6dsv32x_ois_gy_full_scale_get(const stmdev_ctx_t *ctx,
7958 lsm6dsv32x_ois_gy_full_scale_t *val)
7959 {
7960 lsm6dsv32x_ui_ctrl2_ois_t ui_ctrl2_ois;
7961 int32_t ret;
7962
7963 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
7964 if (ret != 0)
7965 {
7966 return ret;
7967 }
7968
7969 switch (ui_ctrl2_ois.fs_g_ois)
7970 {
7971 case LSM6DSV32X_OIS_125dps:
7972 *val = LSM6DSV32X_OIS_125dps;
7973 break;
7974
7975 case LSM6DSV32X_OIS_250dps:
7976 *val = LSM6DSV32X_OIS_250dps;
7977 break;
7978
7979 case LSM6DSV32X_OIS_500dps:
7980 *val = LSM6DSV32X_OIS_500dps;
7981 break;
7982
7983 case LSM6DSV32X_OIS_1000dps:
7984 *val = LSM6DSV32X_OIS_1000dps;
7985 break;
7986
7987 case LSM6DSV32X_OIS_2000dps:
7988 *val = LSM6DSV32X_OIS_2000dps;
7989 break;
7990
7991 default:
7992 *val = LSM6DSV32X_OIS_125dps;
7993 break;
7994 }
7995
7996 return ret;
7997 }
7998
7999 /**
8000 * @brief Selects accelerometer OIS channel full-scale.[set]
8001 *
8002 * @param ctx read / write interface definitions
8003 * @param val lsm6dsv32x_ois_xl_full_scale_t
8004 * @retval interface status (MANDATORY: return 0 -> no Error)
8005 *
8006 */
lsm6dsv32x_ois_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv32x_ois_xl_full_scale_t val)8007 int32_t lsm6dsv32x_ois_xl_full_scale_set(const stmdev_ctx_t *ctx,
8008 lsm6dsv32x_ois_xl_full_scale_t val)
8009 {
8010 lsm6dsv32x_ui_ctrl3_ois_t ui_ctrl3_ois;
8011 int32_t ret;
8012
8013 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
8014 if (ret == 0)
8015 {
8016 ui_ctrl3_ois.fs_xl_ois = (uint8_t)val & 0x3U;
8017 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
8018 }
8019
8020 return ret;
8021 }
8022
8023 /**
8024 * @brief Selects accelerometer OIS channel full-scale.[get]
8025 *
8026 * @param ctx read / write interface definitions
8027 * @param val lsm6dsv32x_ois_xl_full_scale_t
8028 * @retval interface status (MANDATORY: return 0 -> no Error)
8029 *
8030 */
lsm6dsv32x_ois_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv32x_ois_xl_full_scale_t * val)8031 int32_t lsm6dsv32x_ois_xl_full_scale_get(const stmdev_ctx_t *ctx,
8032 lsm6dsv32x_ois_xl_full_scale_t *val)
8033 {
8034 lsm6dsv32x_ui_ctrl3_ois_t ui_ctrl3_ois;
8035 int32_t ret;
8036
8037 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
8038 if (ret != 0)
8039 {
8040 return ret;
8041 }
8042
8043 switch (ui_ctrl3_ois.fs_xl_ois)
8044 {
8045
8046 case LSM6DSV32X_OIS_4g:
8047 *val = LSM6DSV32X_OIS_4g;
8048 break;
8049
8050 case LSM6DSV32X_OIS_8g:
8051 *val = LSM6DSV32X_OIS_8g;
8052 break;
8053
8054 case LSM6DSV32X_OIS_16g:
8055 *val = LSM6DSV32X_OIS_16g;
8056 break;
8057
8058 case LSM6DSV32X_OIS_32g:
8059 *val = LSM6DSV32X_OIS_32g;
8060 break;
8061
8062 default:
8063 *val = LSM6DSV32X_OIS_4g;
8064 break;
8065 }
8066
8067 return ret;
8068 }
8069
8070 /**
8071 * @}
8072 *
8073 */
8074
8075 /**
8076 * @defgroup Orientation 6D (and 4D)
8077 * @brief This section groups all the functions concerning six position
8078 * detection (6D).
8079 * @{
8080 *
8081 */
8082
8083 /**
8084 * @brief Threshold for 4D/6D function.[set]
8085 *
8086 * @param ctx read / write interface definitions
8087 * @param val DEG_80, DEG_70, DEG_60, DEG_50,
8088 * @retval interface status (MANDATORY: return 0 -> no Error)
8089 *
8090 */
lsm6dsv32x_6d_threshold_set(const stmdev_ctx_t * ctx,lsm6dsv32x_6d_threshold_t val)8091 int32_t lsm6dsv32x_6d_threshold_set(const stmdev_ctx_t *ctx,
8092 lsm6dsv32x_6d_threshold_t val)
8093 {
8094 lsm6dsv32x_tap_ths_6d_t tap_ths_6d;
8095 int32_t ret;
8096
8097 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
8098 if (ret == 0)
8099 {
8100 tap_ths_6d.sixd_ths = (uint8_t)val & 0x03U;
8101 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
8102 }
8103
8104 return ret;
8105 }
8106
8107 /**
8108 * @brief Threshold for 4D/6D function.[get]
8109 *
8110 * @param ctx read / write interface definitions
8111 * @param val DEG_80, DEG_70, DEG_60, DEG_50,
8112 * @retval interface status (MANDATORY: return 0 -> no Error)
8113 *
8114 */
lsm6dsv32x_6d_threshold_get(const stmdev_ctx_t * ctx,lsm6dsv32x_6d_threshold_t * val)8115 int32_t lsm6dsv32x_6d_threshold_get(const stmdev_ctx_t *ctx,
8116 lsm6dsv32x_6d_threshold_t *val)
8117 {
8118 lsm6dsv32x_tap_ths_6d_t tap_ths_6d;
8119 int32_t ret;
8120
8121 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
8122 if (ret != 0)
8123 {
8124 return ret;
8125 }
8126
8127 switch (tap_ths_6d.sixd_ths)
8128 {
8129 case LSM6DSV32X_DEG_80:
8130 *val = LSM6DSV32X_DEG_80;
8131 break;
8132
8133 case LSM6DSV32X_DEG_70:
8134 *val = LSM6DSV32X_DEG_70;
8135 break;
8136
8137 case LSM6DSV32X_DEG_60:
8138 *val = LSM6DSV32X_DEG_60;
8139 break;
8140
8141 case LSM6DSV32X_DEG_50:
8142 *val = LSM6DSV32X_DEG_50;
8143 break;
8144
8145 default:
8146 *val = LSM6DSV32X_DEG_80;
8147 break;
8148 }
8149
8150 return ret;
8151 }
8152
8153 /**
8154 * @brief 4D orientation detection enable. Z-axis position detection is disabled.[set]
8155 *
8156 * @param ctx read / write interface definitions
8157 * @param val 4D orientation detection enable. Z-axis position detection is disabled.
8158 * @retval interface status (MANDATORY: return 0 -> no Error)
8159 *
8160 */
lsm6dsv32x_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)8161 int32_t lsm6dsv32x_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
8162 {
8163 lsm6dsv32x_tap_ths_6d_t tap_ths_6d;
8164 int32_t ret;
8165
8166 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
8167 if (ret == 0)
8168 {
8169 tap_ths_6d.d4d_en = val;
8170 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
8171 }
8172
8173 return ret;
8174 }
8175
8176 /**
8177 * @brief 4D orientation detection enable. Z-axis position detection is disabled.[get]
8178 *
8179 * @param ctx read / write interface definitions
8180 * @param val 4D orientation detection enable. Z-axis position detection is disabled.
8181 * @retval interface status (MANDATORY: return 0 -> no Error)
8182 *
8183 */
lsm6dsv32x_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)8184 int32_t lsm6dsv32x_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
8185 {
8186 lsm6dsv32x_tap_ths_6d_t tap_ths_6d;
8187 int32_t ret;
8188
8189 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
8190 *val = tap_ths_6d.d4d_en;
8191
8192 return ret;
8193 }
8194
8195 /**
8196 * @}
8197 *
8198 */
8199
8200 /**
8201 * @defgroup AH_QVAR
8202 * @brief This section group all the functions concerning the
8203 * usage of AH_QVAR
8204 * @{
8205 *
8206 */
8207
8208 /**
8209 * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[set]
8210 *
8211 * @param ctx read / write interface definitions
8212 * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm,
8213 * @retval interface status (MANDATORY: return 0 -> no Error)
8214 *
8215 */
lsm6dsv32x_ah_qvar_zin_set(const stmdev_ctx_t * ctx,lsm6dsv32x_ah_qvar_zin_t val)8216 int32_t lsm6dsv32x_ah_qvar_zin_set(const stmdev_ctx_t *ctx,
8217 lsm6dsv32x_ah_qvar_zin_t val)
8218 {
8219 lsm6dsv32x_ctrl7_t ctrl7;
8220 int32_t ret;
8221
8222 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1);
8223 if (ret == 0)
8224 {
8225 ctrl7.ah_qvar_c_zin = (uint8_t)val & 0x03U;
8226 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1);
8227 }
8228
8229 return ret;
8230 }
8231
8232 /**
8233 * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[get]
8234 *
8235 * @param ctx read / write interface definitions
8236 * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm,
8237 * @retval interface status (MANDATORY: return 0 -> no Error)
8238 *
8239 */
lsm6dsv32x_ah_qvar_zin_get(const stmdev_ctx_t * ctx,lsm6dsv32x_ah_qvar_zin_t * val)8240 int32_t lsm6dsv32x_ah_qvar_zin_get(const stmdev_ctx_t *ctx,
8241 lsm6dsv32x_ah_qvar_zin_t *val)
8242 {
8243 lsm6dsv32x_ctrl7_t ctrl7;
8244 int32_t ret;
8245
8246 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1);
8247 if (ret != 0)
8248 {
8249 return ret;
8250 }
8251
8252 switch (ctrl7.ah_qvar_c_zin)
8253 {
8254 case LSM6DSV32X_2400MOhm:
8255 *val = LSM6DSV32X_2400MOhm;
8256 break;
8257
8258 case LSM6DSV32X_730MOhm:
8259 *val = LSM6DSV32X_730MOhm;
8260 break;
8261
8262 case LSM6DSV32X_300MOhm:
8263 *val = LSM6DSV32X_300MOhm;
8264 break;
8265
8266 case LSM6DSV32X_255MOhm:
8267 *val = LSM6DSV32X_255MOhm;
8268 break;
8269
8270 default:
8271 *val = LSM6DSV32X_2400MOhm;
8272 break;
8273 }
8274
8275 return ret;
8276 }
8277
8278 /**
8279 * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.[set]
8280 *
8281 * @param ctx read / write interface definitions
8282 * @param val Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.
8283 * @retval interface status (MANDATORY: return 0 -> no Error)
8284 *
8285 */
lsm6dsv32x_ah_qvar_mode_set(const stmdev_ctx_t * ctx,lsm6dsv32x_ah_qvar_mode_t val)8286 int32_t lsm6dsv32x_ah_qvar_mode_set(const stmdev_ctx_t *ctx,
8287 lsm6dsv32x_ah_qvar_mode_t val)
8288 {
8289 lsm6dsv32x_ctrl7_t ctrl7;
8290 int32_t ret;
8291
8292 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1);
8293 if (ret == 0)
8294 {
8295 ctrl7.ah_qvar_en = val.ah_qvar_en;
8296 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1);
8297 }
8298
8299 return ret;
8300 }
8301
8302 /**
8303 * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.[get]
8304 *
8305 * @param ctx read / write interface definitions
8306 * @param val Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.
8307 * @retval interface status (MANDATORY: return 0 -> no Error)
8308 *
8309 */
lsm6dsv32x_ah_qvar_mode_get(const stmdev_ctx_t * ctx,lsm6dsv32x_ah_qvar_mode_t * val)8310 int32_t lsm6dsv32x_ah_qvar_mode_get(const stmdev_ctx_t *ctx,
8311 lsm6dsv32x_ah_qvar_mode_t *val)
8312 {
8313 lsm6dsv32x_ctrl7_t ctrl7;
8314 int32_t ret;
8315
8316 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL7, (uint8_t *)&ctrl7, 1);
8317 val->ah_qvar_en = ctrl7.ah_qvar_en;
8318
8319 return ret;
8320 }
8321
8322 /**
8323 * @}
8324 *
8325 */
8326
8327 /**
8328 * @defgroup SenseWire (I3C)
8329 * @brief This section group all the functions concerning the
8330 * usage of SenseWire (I3C)
8331 * @{
8332 *
8333 */
8334
8335 /**
8336 * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[set]
8337 *
8338 * @param ctx read / write interface definitions
8339 * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST,
8340 * @retval interface status (MANDATORY: return 0 -> no Error)
8341 *
8342 */
lsm6dsv32x_i3c_reset_mode_set(const stmdev_ctx_t * ctx,lsm6dsv32x_i3c_reset_mode_t val)8343 int32_t lsm6dsv32x_i3c_reset_mode_set(const stmdev_ctx_t *ctx,
8344 lsm6dsv32x_i3c_reset_mode_t val)
8345 {
8346 lsm6dsv32x_pin_ctrl_t pin_ctrl;
8347 int32_t ret;
8348
8349 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8350 if (ret == 0)
8351 {
8352 pin_ctrl.ibhr_por_en = (uint8_t)val & 0x01U;
8353 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8354 }
8355
8356 return ret;
8357 }
8358
8359 /**
8360 * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[get]
8361 *
8362 * @param ctx read / write interface definitions
8363 * @param val SW_RST_DYN_ADDRESS_RST, I3C_GLOBAL_RST,
8364 * @retval interface status (MANDATORY: return 0 -> no Error)
8365 *
8366 */
lsm6dsv32x_i3c_reset_mode_get(const stmdev_ctx_t * ctx,lsm6dsv32x_i3c_reset_mode_t * val)8367 int32_t lsm6dsv32x_i3c_reset_mode_get(const stmdev_ctx_t *ctx,
8368 lsm6dsv32x_i3c_reset_mode_t *val)
8369 {
8370 lsm6dsv32x_pin_ctrl_t pin_ctrl;
8371 int32_t ret;
8372
8373 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8374 if (ret != 0)
8375 {
8376 return ret;
8377 }
8378
8379 switch (pin_ctrl.ibhr_por_en)
8380 {
8381 case LSM6DSV32X_SW_RST_DYN_ADDRESS_RST:
8382 *val = LSM6DSV32X_SW_RST_DYN_ADDRESS_RST;
8383 break;
8384
8385 case LSM6DSV32X_I3C_GLOBAL_RST:
8386 *val = LSM6DSV32X_I3C_GLOBAL_RST;
8387 break;
8388
8389 default:
8390 *val = LSM6DSV32X_SW_RST_DYN_ADDRESS_RST;
8391 break;
8392 }
8393
8394 return ret;
8395 }
8396
8397 /**
8398 * @brief Enable/Disable INT pin when I3C is used.[set]
8399 *
8400 * @param ctx read / write interface definitions
8401 * @param val 0: disabled, 1: enabled
8402 * @retval interface status (MANDATORY: return 0 -> no Error)
8403 *
8404 */
lsm6dsv32x_i3c_int_en_set(const stmdev_ctx_t * ctx,uint8_t val)8405 int32_t lsm6dsv32x_i3c_int_en_set(const stmdev_ctx_t *ctx, uint8_t val)
8406 {
8407 lsm6dsv32x_ctrl5_t ctrl5;
8408 int32_t ret;
8409
8410 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL5, (uint8_t *)&ctrl5, 1);
8411 if (ret == 0)
8412 {
8413 ctrl5.int_en_i3c = (uint8_t)val & 0x01U;
8414 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL5, (uint8_t *)&ctrl5, 1);
8415 }
8416
8417 return ret;
8418 }
8419
8420 /**
8421 * @brief Enable/Disable INT pin when I3C is used.[get]
8422 *
8423 * @param ctx read / write interface definitions
8424 * @param val 0: disabled, 1: enabled
8425 * @retval interface status (MANDATORY: return 0 -> no Error)
8426 *
8427 */
lsm6dsv32x_i3c_int_en_get(const stmdev_ctx_t * ctx,uint8_t * val)8428 int32_t lsm6dsv32x_i3c_int_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
8429 {
8430 lsm6dsv32x_ctrl5_t ctrl5;
8431 int32_t ret;
8432
8433 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL5, (uint8_t *)&ctrl5, 1);
8434 *val = ctrl5.int_en_i3c;
8435
8436 return ret;
8437 }
8438
8439 /**
8440 * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[set]
8441 *
8442 * @param ctx read / write interface definitions
8443 * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms,
8444 * @retval interface status (MANDATORY: return 0 -> no Error)
8445 *
8446 */
lsm6dsv32x_i3c_ibi_time_set(const stmdev_ctx_t * ctx,lsm6dsv32x_i3c_ibi_time_t val)8447 int32_t lsm6dsv32x_i3c_ibi_time_set(const stmdev_ctx_t *ctx,
8448 lsm6dsv32x_i3c_ibi_time_t val)
8449 {
8450 lsm6dsv32x_ctrl5_t ctrl5;
8451 int32_t ret;
8452
8453 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL5, (uint8_t *)&ctrl5, 1);
8454 if (ret == 0)
8455 {
8456 ctrl5.bus_act_sel = (uint8_t)val & 0x03U;
8457 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_CTRL5, (uint8_t *)&ctrl5, 1);
8458 }
8459
8460 return ret;
8461 }
8462
8463 /**
8464 * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[get]
8465 *
8466 * @param ctx read / write interface definitions
8467 * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms,
8468 * @retval interface status (MANDATORY: return 0 -> no Error)
8469 *
8470 */
lsm6dsv32x_i3c_ibi_time_get(const stmdev_ctx_t * ctx,lsm6dsv32x_i3c_ibi_time_t * val)8471 int32_t lsm6dsv32x_i3c_ibi_time_get(const stmdev_ctx_t *ctx,
8472 lsm6dsv32x_i3c_ibi_time_t *val)
8473 {
8474 lsm6dsv32x_ctrl5_t ctrl5;
8475 int32_t ret;
8476
8477 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_CTRL5, (uint8_t *)&ctrl5, 1);
8478 if (ret != 0)
8479 {
8480 return ret;
8481 }
8482
8483 switch (ctrl5.bus_act_sel)
8484 {
8485 case LSM6DSV32X_IBI_2us:
8486 *val = LSM6DSV32X_IBI_2us;
8487 break;
8488
8489 case LSM6DSV32X_IBI_50us:
8490 *val = LSM6DSV32X_IBI_50us;
8491 break;
8492
8493 case LSM6DSV32X_IBI_1ms:
8494 *val = LSM6DSV32X_IBI_1ms;
8495 break;
8496
8497 case LSM6DSV32X_IBI_25ms:
8498 *val = LSM6DSV32X_IBI_25ms;
8499 break;
8500
8501 default:
8502 *val = LSM6DSV32X_IBI_2us;
8503 break;
8504 }
8505
8506 return ret;
8507 }
8508
8509 /**
8510 * @}
8511 *
8512 */
8513
8514 /**
8515 * @defgroup Sensor hub
8516 * @brief This section groups all the functions that manage the
8517 * sensor hub.
8518 * @{
8519 *
8520 */
8521
8522 /**
8523 * @brief Sensor Hub master I2C pull-up enable.[set]
8524 *
8525 * @param ctx read / write interface definitions
8526 * @param val Sensor Hub master I2C pull-up enable.
8527 * @retval interface status (MANDATORY: return 0 -> no Error)
8528 *
8529 */
lsm6dsv32x_sh_master_interface_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)8530 int32_t lsm6dsv32x_sh_master_interface_pull_up_set(const stmdev_ctx_t *ctx,
8531 uint8_t val)
8532 {
8533 lsm6dsv32x_if_cfg_t if_cfg;
8534 int32_t ret;
8535
8536 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1);
8537 if (ret == 0)
8538 {
8539 if_cfg.shub_pu_en = val;
8540 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1);
8541 }
8542
8543 return ret;
8544 }
8545
8546 /**
8547 * @brief Sensor Hub master I2C pull-up enable.[get]
8548 *
8549 * @param ctx read / write interface definitions
8550 * @param val Sensor Hub master I2C pull-up enable.
8551 * @retval interface status (MANDATORY: return 0 -> no Error)
8552 *
8553 */
lsm6dsv32x_sh_master_interface_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)8554 int32_t lsm6dsv32x_sh_master_interface_pull_up_get(const stmdev_ctx_t *ctx,
8555 uint8_t *val)
8556 {
8557 lsm6dsv32x_if_cfg_t if_cfg;
8558 int32_t ret;
8559
8560 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1);
8561 *val = if_cfg.shub_pu_en;
8562
8563 return ret;
8564 }
8565
8566 /**
8567 * @brief Sensor hub output registers.[get]
8568 *
8569 * @param ctx read / write interface definitions
8570 * @param val Sensor hub output registers.
8571 * @retval interface status (MANDATORY: return 0 -> no Error)
8572 *
8573 */
lsm6dsv32x_sh_read_data_raw_get(const stmdev_ctx_t * ctx,uint8_t * val,uint8_t len)8574 int32_t lsm6dsv32x_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val,
8575 uint8_t len)
8576 {
8577 int32_t ret;
8578
8579 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
8580 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SENSOR_HUB_1, val, len);
8581 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
8582
8583 return ret;
8584 }
8585
8586 /**
8587 * @brief Number of external sensors to be read by the sensor hub.[set]
8588 *
8589 * @param ctx read / write interface definitions
8590 * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3,
8591 * @retval interface status (MANDATORY: return 0 -> no Error)
8592 *
8593 */
lsm6dsv32x_sh_slave_connected_set(const stmdev_ctx_t * ctx,lsm6dsv32x_sh_slave_connected_t val)8594 int32_t lsm6dsv32x_sh_slave_connected_set(const stmdev_ctx_t *ctx,
8595 lsm6dsv32x_sh_slave_connected_t val)
8596 {
8597 lsm6dsv32x_master_config_t master_config;
8598 int32_t ret;
8599
8600 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
8601 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8602 if (ret != 0)
8603 {
8604 goto exit;
8605 }
8606
8607 master_config.aux_sens_on = (uint8_t)val & 0x3U;
8608 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8609
8610 exit:
8611 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
8612
8613 return ret;
8614 }
8615
8616 /**
8617 * @brief Number of external sensors to be read by the sensor hub.[get]
8618 *
8619 * @param ctx read / write interface definitions
8620 * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3,
8621 * @retval interface status (MANDATORY: return 0 -> no Error)
8622 *
8623 */
lsm6dsv32x_sh_slave_connected_get(const stmdev_ctx_t * ctx,lsm6dsv32x_sh_slave_connected_t * val)8624 int32_t lsm6dsv32x_sh_slave_connected_get(const stmdev_ctx_t *ctx,
8625 lsm6dsv32x_sh_slave_connected_t *val)
8626 {
8627 lsm6dsv32x_master_config_t master_config;
8628 int32_t ret;
8629
8630 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
8631 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8632 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
8633 if (ret != 0)
8634 {
8635 return ret;
8636 }
8637
8638 switch (master_config.aux_sens_on)
8639 {
8640 case LSM6DSV32X_SLV_0:
8641 *val = LSM6DSV32X_SLV_0;
8642 break;
8643
8644 case LSM6DSV32X_SLV_0_1:
8645 *val = LSM6DSV32X_SLV_0_1;
8646 break;
8647
8648 case LSM6DSV32X_SLV_0_1_2:
8649 *val = LSM6DSV32X_SLV_0_1_2;
8650 break;
8651
8652 case LSM6DSV32X_SLV_0_1_2_3:
8653 *val = LSM6DSV32X_SLV_0_1_2_3;
8654 break;
8655
8656 default:
8657 *val = LSM6DSV32X_SLV_0;
8658 break;
8659 }
8660
8661 return ret;
8662 }
8663
8664 /**
8665 * @brief Sensor hub I2C master enable.[set]
8666 *
8667 * @param ctx read / write interface definitions
8668 * @param val Sensor hub I2C master enable.
8669 * @retval interface status (MANDATORY: return 0 -> no Error)
8670 *
8671 */
lsm6dsv32x_sh_master_set(const stmdev_ctx_t * ctx,uint8_t val)8672 int32_t lsm6dsv32x_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val)
8673 {
8674 lsm6dsv32x_master_config_t master_config;
8675 int32_t ret;
8676
8677 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
8678 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8679 if (ret != 0)
8680 {
8681 goto exit;
8682 }
8683
8684 master_config.master_on = val;
8685 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8686
8687 exit:
8688 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
8689
8690 return ret;
8691 }
8692
8693 /**
8694 * @brief Sensor hub I2C master enable.[get]
8695 *
8696 * @param ctx read / write interface definitions
8697 * @param val Sensor hub I2C master enable.
8698 * @retval interface status (MANDATORY: return 0 -> no Error)
8699 *
8700 */
lsm6dsv32x_sh_master_get(const stmdev_ctx_t * ctx,uint8_t * val)8701 int32_t lsm6dsv32x_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val)
8702 {
8703 lsm6dsv32x_master_config_t master_config;
8704 int32_t ret;
8705
8706 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
8707 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8708
8709 *val = master_config.master_on;
8710
8711 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
8712
8713 return ret;
8714 }
8715
8716 /**
8717 * @brief I2C interface pass-through.[set]
8718 *
8719 * @param ctx read / write interface definitions
8720 * @param val I2C interface pass-through.
8721 * @retval interface status (MANDATORY: return 0 -> no Error)
8722 *
8723 */
lsm6dsv32x_sh_pass_through_set(const stmdev_ctx_t * ctx,uint8_t val)8724 int32_t lsm6dsv32x_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val)
8725 {
8726 lsm6dsv32x_master_config_t master_config;
8727 int32_t ret;
8728
8729 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
8730 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8731 if (ret != 0)
8732 {
8733 goto exit;
8734 }
8735
8736 master_config.pass_through_mode = val;
8737 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8738
8739 exit:
8740 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
8741
8742 return ret;
8743 }
8744
8745 /**
8746 * @brief I2C interface pass-through.[get]
8747 *
8748 * @param ctx read / write interface definitions
8749 * @param val I2C interface pass-through.
8750 * @retval interface status (MANDATORY: return 0 -> no Error)
8751 *
8752 */
lsm6dsv32x_sh_pass_through_get(const stmdev_ctx_t * ctx,uint8_t * val)8753 int32_t lsm6dsv32x_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val)
8754 {
8755 lsm6dsv32x_master_config_t master_config;
8756 int32_t ret;
8757
8758 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
8759 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8760
8761 *val = master_config.pass_through_mode;
8762
8763 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
8764
8765 return ret;
8766 }
8767
8768 /**
8769 * @brief Sensor hub trigger signal selection.[set]
8770 *
8771 * @param ctx read / write interface definitions
8772 * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2,
8773 * @retval interface status (MANDATORY: return 0 -> no Error)
8774 *
8775 */
lsm6dsv32x_sh_syncro_mode_set(const stmdev_ctx_t * ctx,lsm6dsv32x_sh_syncro_mode_t val)8776 int32_t lsm6dsv32x_sh_syncro_mode_set(const stmdev_ctx_t *ctx,
8777 lsm6dsv32x_sh_syncro_mode_t val)
8778 {
8779 lsm6dsv32x_master_config_t master_config;
8780 int32_t ret;
8781
8782 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
8783 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8784 if (ret != 0)
8785 {
8786 goto exit;
8787 }
8788
8789 master_config.start_config = (uint8_t)val & 0x01U;
8790 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8791
8792 exit:
8793 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
8794
8795 return ret;
8796 }
8797
8798 /**
8799 * @brief Sensor hub trigger signal selection.[get]
8800 *
8801 * @param ctx read / write interface definitions
8802 * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2,
8803 * @retval interface status (MANDATORY: return 0 -> no Error)
8804 *
8805 */
lsm6dsv32x_sh_syncro_mode_get(const stmdev_ctx_t * ctx,lsm6dsv32x_sh_syncro_mode_t * val)8806 int32_t lsm6dsv32x_sh_syncro_mode_get(const stmdev_ctx_t *ctx,
8807 lsm6dsv32x_sh_syncro_mode_t *val)
8808 {
8809 lsm6dsv32x_master_config_t master_config;
8810 int32_t ret;
8811
8812 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
8813 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8814 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
8815 if (ret != 0)
8816 {
8817 return ret;
8818 }
8819
8820 switch (master_config.start_config)
8821 {
8822 case LSM6DSV32X_SH_TRG_XL_GY_DRDY:
8823 *val = LSM6DSV32X_SH_TRG_XL_GY_DRDY;
8824 break;
8825
8826 case LSM6DSV32X_SH_TRIG_INT2:
8827 *val = LSM6DSV32X_SH_TRIG_INT2;
8828 break;
8829
8830 default:
8831 *val = LSM6DSV32X_SH_TRG_XL_GY_DRDY;
8832 break;
8833 }
8834
8835 return ret;
8836 }
8837
8838 /**
8839 * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[set]
8840 *
8841 * @param ctx read / write interface definitions
8842 * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE,
8843 * @retval interface status (MANDATORY: return 0 -> no Error)
8844 *
8845 */
lsm6dsv32x_sh_write_mode_set(const stmdev_ctx_t * ctx,lsm6dsv32x_sh_write_mode_t val)8846 int32_t lsm6dsv32x_sh_write_mode_set(const stmdev_ctx_t *ctx,
8847 lsm6dsv32x_sh_write_mode_t val)
8848 {
8849 lsm6dsv32x_master_config_t master_config;
8850 int32_t ret;
8851
8852 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
8853 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8854 if (ret != 0)
8855 {
8856 goto exit;
8857 }
8858
8859 master_config.write_once = (uint8_t)val & 0x01U;
8860 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8861
8862 exit:
8863 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
8864
8865 return ret;
8866 }
8867
8868 /**
8869 * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[get]
8870 *
8871 * @param ctx read / write interface definitions
8872 * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE,
8873 * @retval interface status (MANDATORY: return 0 -> no Error)
8874 *
8875 */
lsm6dsv32x_sh_write_mode_get(const stmdev_ctx_t * ctx,lsm6dsv32x_sh_write_mode_t * val)8876 int32_t lsm6dsv32x_sh_write_mode_get(const stmdev_ctx_t *ctx,
8877 lsm6dsv32x_sh_write_mode_t *val)
8878 {
8879 lsm6dsv32x_master_config_t master_config;
8880 int32_t ret;
8881
8882 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
8883 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8884 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
8885 if (ret != 0)
8886 {
8887 return ret;
8888 }
8889
8890 switch (master_config.write_once)
8891 {
8892 case LSM6DSV32X_EACH_SH_CYCLE:
8893 *val = LSM6DSV32X_EACH_SH_CYCLE;
8894 break;
8895
8896 case LSM6DSV32X_ONLY_FIRST_CYCLE:
8897 *val = LSM6DSV32X_ONLY_FIRST_CYCLE;
8898 break;
8899
8900 default:
8901 *val = LSM6DSV32X_EACH_SH_CYCLE;
8902 break;
8903 }
8904
8905 return ret;
8906 }
8907
8908 /**
8909 * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[set]
8910 *
8911 * @param ctx read / write interface definitions
8912 * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.
8913 * @retval interface status (MANDATORY: return 0 -> no Error)
8914 *
8915 */
lsm6dsv32x_sh_reset_set(const stmdev_ctx_t * ctx,uint8_t val)8916 int32_t lsm6dsv32x_sh_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
8917 {
8918 lsm6dsv32x_master_config_t master_config;
8919 int32_t ret;
8920
8921 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
8922 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8923 if (ret != 0)
8924 {
8925 goto exit;
8926 }
8927
8928 master_config.rst_master_regs = val;
8929 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8930
8931 exit:
8932 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
8933
8934 return ret;
8935 }
8936
8937 /**
8938 * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[get]
8939 *
8940 * @param ctx read / write interface definitions
8941 * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.
8942 * @retval interface status (MANDATORY: return 0 -> no Error)
8943 *
8944 */
lsm6dsv32x_sh_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)8945 int32_t lsm6dsv32x_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
8946 {
8947 lsm6dsv32x_master_config_t master_config;
8948 int32_t ret;
8949
8950 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
8951 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8952
8953 *val = master_config.rst_master_regs;
8954
8955 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
8956
8957 return ret;
8958 }
8959
8960 /**
8961 * @brief Configure slave 0 for perform a write.[set]
8962 *
8963 * @param ctx read / write interface definitions
8964 * @param val a structure that contain
8965 * - uint8_t slv1_add; 8 bit i2c device address
8966 * - uint8_t slv1_subadd; 8 bit register device address
8967 * - uint8_t slv1_data; 8 bit data to write
8968 * @retval interface status (MANDATORY: return 0 -> no Error)
8969 *
8970 */
lsm6dsv32x_sh_cfg_write(const stmdev_ctx_t * ctx,lsm6dsv32x_sh_cfg_write_t * val)8971 int32_t lsm6dsv32x_sh_cfg_write(const stmdev_ctx_t *ctx,
8972 lsm6dsv32x_sh_cfg_write_t *val)
8973 {
8974 lsm6dsv32x_slv0_add_t reg;
8975 int32_t ret;
8976
8977 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
8978 if (ret != 0)
8979 {
8980 return ret;
8981 }
8982
8983 reg.slave0_add = val->slv0_add;
8984 reg.rw_0 = 0;
8985 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SLV0_ADD, (uint8_t *)®, 1);
8986 if (ret != 0)
8987 {
8988 goto exit;
8989 }
8990
8991 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SLV0_SUBADD,
8992 &(val->slv0_subadd), 1);
8993 if (ret != 0)
8994 {
8995 goto exit;
8996 }
8997
8998 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_DATAWRITE_SLV0,
8999 &(val->slv0_data), 1);
9000
9001 exit:
9002 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
9003
9004 return ret;
9005 }
9006
9007 /**
9008 * @brief Rate at which the master communicates.[set]
9009 *
9010 * @param ctx read / write interface definitions
9011 * @param val SH_15Hz, SH_30Hz, SH_60Hz, SH_120Hz, SH_240Hz, SH_480Hz,
9012 * @retval interface status (MANDATORY: return 0 -> no Error)
9013 *
9014 */
lsm6dsv32x_sh_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv32x_sh_data_rate_t val)9015 int32_t lsm6dsv32x_sh_data_rate_set(const stmdev_ctx_t *ctx,
9016 lsm6dsv32x_sh_data_rate_t val)
9017 {
9018 lsm6dsv32x_slv0_config_t slv0_config;
9019 int32_t ret;
9020
9021 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
9022 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1);
9023 if (ret != 0)
9024 {
9025 goto exit;
9026 }
9027
9028 slv0_config.shub_odr = (uint8_t)val & 0x07U;
9029 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1);
9030
9031 exit:
9032 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
9033
9034 return ret;
9035 }
9036
9037 /**
9038 * @brief Rate at which the master communicates.[get]
9039 *
9040 * @param ctx read / write interface definitions
9041 * @param val SH_15Hz, SH_30Hz, SH_60Hz, SH_120Hz, SH_240Hz, SH_480Hz,
9042 * @retval interface status (MANDATORY: return 0 -> no Error)
9043 *
9044 */
lsm6dsv32x_sh_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv32x_sh_data_rate_t * val)9045 int32_t lsm6dsv32x_sh_data_rate_get(const stmdev_ctx_t *ctx,
9046 lsm6dsv32x_sh_data_rate_t *val)
9047 {
9048 lsm6dsv32x_slv0_config_t slv0_config;
9049 int32_t ret;
9050
9051 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
9052 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1);
9053 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
9054 if (ret != 0)
9055 {
9056 return ret;
9057 }
9058
9059 switch (slv0_config.shub_odr)
9060 {
9061 case LSM6DSV32X_SH_15Hz:
9062 *val = LSM6DSV32X_SH_15Hz;
9063 break;
9064
9065 case LSM6DSV32X_SH_30Hz:
9066 *val = LSM6DSV32X_SH_30Hz;
9067 break;
9068
9069 case LSM6DSV32X_SH_60Hz:
9070 *val = LSM6DSV32X_SH_60Hz;
9071 break;
9072
9073 case LSM6DSV32X_SH_120Hz:
9074 *val = LSM6DSV32X_SH_120Hz;
9075 break;
9076
9077 case LSM6DSV32X_SH_240Hz:
9078 *val = LSM6DSV32X_SH_240Hz;
9079 break;
9080
9081 case LSM6DSV32X_SH_480Hz:
9082 *val = LSM6DSV32X_SH_480Hz;
9083 break;
9084
9085 default:
9086 *val = LSM6DSV32X_SH_15Hz;
9087 break;
9088 }
9089
9090 return ret;
9091 }
9092
9093 /**
9094 * @brief Configure slave idx for perform a read.[set]
9095 *
9096 * @param ctx read / write interface definitions
9097 * @param val Structure that contain
9098 * - uint8_t slv_add; 8 bit i2c device address
9099 * - uint8_t slv_subadd; 8 bit register device address
9100 * - uint8_t slv_len; num of bit to read
9101 * @retval interface status (MANDATORY: return 0 -> no Error)
9102 *
9103 */
lsm6dsv32x_sh_slv_cfg_read(const stmdev_ctx_t * ctx,uint8_t idx,lsm6dsv32x_sh_cfg_read_t * val)9104 int32_t lsm6dsv32x_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx,
9105 lsm6dsv32x_sh_cfg_read_t *val)
9106 {
9107 lsm6dsv32x_slv0_add_t slv_add;
9108 lsm6dsv32x_slv0_config_t slv_config;
9109 int32_t ret;
9110
9111 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_SENSOR_HUB_MEM_BANK);
9112 if (ret != 0)
9113 {
9114 return ret;
9115 }
9116
9117 slv_add.slave0_add = val->slv_add;
9118 slv_add.rw_0 = 1;
9119 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SLV0_ADD + idx * 3U,
9120 (uint8_t *)&slv_add, 1);
9121 if (ret != 0)
9122 {
9123 goto exit;
9124 }
9125
9126 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SLV0_SUBADD + idx * 3U,
9127 &(val->slv_subadd), 1);
9128 if (ret != 0)
9129 {
9130 goto exit;
9131 }
9132
9133 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SLV0_CONFIG + idx * 3U,
9134 (uint8_t *)&slv_config, 1);
9135 if (ret != 0)
9136 {
9137 goto exit;
9138 }
9139
9140 slv_config.slave0_numop = val->slv_len;
9141 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SLV0_CONFIG + idx * 3U,
9142 (uint8_t *)&slv_config, 1);
9143
9144 exit:
9145 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
9146
9147 return ret;
9148 }
9149
9150 /**
9151 * @brief Sensor hub source register.[get]
9152 *
9153 * @param ctx read / write interface definitions
9154 * @param val union of registers from STATUS_MASTER to
9155 * @retval interface status (MANDATORY: return 0 -> no Error)
9156 *
9157 */
lsm6dsv32x_sh_status_get(const stmdev_ctx_t * ctx,lsm6dsv32x_status_master_t * val)9158 int32_t lsm6dsv32x_sh_status_get(const stmdev_ctx_t *ctx,
9159 lsm6dsv32x_status_master_t *val)
9160 {
9161 int32_t ret;
9162
9163 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_STATUS_MASTER_MAINPAGE, (uint8_t *) val, 1);
9164
9165 return ret;
9166 }
9167
9168 /**
9169 * @}
9170 *
9171 */
9172
9173 /**
9174 * @defgroup Serial interfaces
9175 * @brief This section groups all the functions concerning
9176 * serial interfaces management (not auxiliary)
9177 * @{
9178 *
9179 */
9180
9181 /**
9182 * @brief Enables pull-up on SDO pin of UI (User Interface).[set]
9183 *
9184 * @param ctx read / write interface definitions
9185 * @param val Enables pull-up on SDO pin of UI (User Interface).
9186 * @retval interface status (MANDATORY: return 0 -> no Error)
9187 *
9188 */
lsm6dsv32x_ui_sdo_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)9189 int32_t lsm6dsv32x_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
9190 {
9191 lsm6dsv32x_pin_ctrl_t pin_ctrl;
9192 int32_t ret;
9193
9194 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
9195 if (ret == 0)
9196 {
9197 pin_ctrl.sdo_pu_en = val;
9198 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
9199 }
9200
9201 return ret;
9202 }
9203
9204 /**
9205 * @brief Enables pull-up on SDO pin of UI (User Interface).[get]
9206 *
9207 * @param ctx read / write interface definitions
9208 * @param val Enables pull-up on SDO pin of UI (User Interface).
9209 * @retval interface status (MANDATORY: return 0 -> no Error)
9210 *
9211 */
lsm6dsv32x_ui_sdo_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)9212 int32_t lsm6dsv32x_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
9213 {
9214 lsm6dsv32x_pin_ctrl_t pin_ctrl;
9215 int32_t ret;
9216
9217 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
9218 *val = pin_ctrl.sdo_pu_en;
9219
9220 return ret;
9221 }
9222
9223 /**
9224 * @brief Disables I2C and I3C on UI (User Interface).[set]
9225 *
9226 * @param ctx read / write interface definitions
9227 * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE,
9228 * @retval interface status (MANDATORY: return 0 -> no Error)
9229 *
9230 */
lsm6dsv32x_ui_i2c_i3c_mode_set(const stmdev_ctx_t * ctx,lsm6dsv32x_ui_i2c_i3c_mode_t val)9231 int32_t lsm6dsv32x_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx,
9232 lsm6dsv32x_ui_i2c_i3c_mode_t val)
9233 {
9234 lsm6dsv32x_if_cfg_t if_cfg;
9235 int32_t ret;
9236
9237 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1);
9238 if (ret == 0)
9239 {
9240 if_cfg.i2c_i3c_disable = (uint8_t)val & 0x1U;
9241 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1);
9242 }
9243
9244 return ret;
9245 }
9246
9247 /**
9248 * @brief Disables I2C and I3C on UI (User Interface).[get]
9249 *
9250 * @param ctx read / write interface definitions
9251 * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE,
9252 * @retval interface status (MANDATORY: return 0 -> no Error)
9253 *
9254 */
lsm6dsv32x_ui_i2c_i3c_mode_get(const stmdev_ctx_t * ctx,lsm6dsv32x_ui_i2c_i3c_mode_t * val)9255 int32_t lsm6dsv32x_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx,
9256 lsm6dsv32x_ui_i2c_i3c_mode_t *val)
9257 {
9258 lsm6dsv32x_if_cfg_t if_cfg;
9259 int32_t ret;
9260
9261 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1);
9262 if (ret != 0)
9263 {
9264 return ret;
9265 }
9266
9267 switch (if_cfg.i2c_i3c_disable)
9268 {
9269 case LSM6DSV32X_I2C_I3C_ENABLE:
9270 *val = LSM6DSV32X_I2C_I3C_ENABLE;
9271 break;
9272
9273 case LSM6DSV32X_I2C_I3C_DISABLE:
9274 *val = LSM6DSV32X_I2C_I3C_DISABLE;
9275 break;
9276
9277 default:
9278 *val = LSM6DSV32X_I2C_I3C_ENABLE;
9279 break;
9280 }
9281
9282 return ret;
9283 }
9284
9285 /**
9286 * @brief SPI Serial Interface Mode selection.[set]
9287 *
9288 * @param ctx read / write interface definitions
9289 * @param val SPI_4_WIRE, SPI_3_WIRE,
9290 * @retval interface status (MANDATORY: return 0 -> no Error)
9291 *
9292 */
lsm6dsv32x_spi_mode_set(const stmdev_ctx_t * ctx,lsm6dsv32x_spi_mode_t val)9293 int32_t lsm6dsv32x_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_spi_mode_t val)
9294 {
9295 lsm6dsv32x_if_cfg_t if_cfg;
9296 int32_t ret;
9297
9298 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1);
9299 if (ret == 0)
9300 {
9301 if_cfg.sim = (uint8_t)val & 0x01U;
9302 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1);
9303 }
9304
9305 return ret;
9306 }
9307
9308 /**
9309 * @brief SPI Serial Interface Mode selection.[get]
9310 *
9311 * @param ctx read / write interface definitions
9312 * @param val SPI_4_WIRE, SPI_3_WIRE,
9313 * @retval interface status (MANDATORY: return 0 -> no Error)
9314 *
9315 */
lsm6dsv32x_spi_mode_get(const stmdev_ctx_t * ctx,lsm6dsv32x_spi_mode_t * val)9316 int32_t lsm6dsv32x_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_spi_mode_t *val)
9317 {
9318 lsm6dsv32x_if_cfg_t if_cfg;
9319 int32_t ret;
9320
9321 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1);
9322 if (ret != 0)
9323 {
9324 return ret;
9325 }
9326
9327 switch (if_cfg.sim)
9328 {
9329 case LSM6DSV32X_SPI_4_WIRE:
9330 *val = LSM6DSV32X_SPI_4_WIRE;
9331 break;
9332
9333 case LSM6DSV32X_SPI_3_WIRE:
9334 *val = LSM6DSV32X_SPI_3_WIRE;
9335 break;
9336
9337 default:
9338 *val = LSM6DSV32X_SPI_4_WIRE;
9339 break;
9340 }
9341
9342 return ret;
9343 }
9344
9345 /**
9346 * @brief Enables pull-up on SDA pin.[set]
9347 *
9348 * @param ctx read / write interface definitions
9349 * @param val Enables pull-up on SDA pin.
9350 * @retval interface status (MANDATORY: return 0 -> no Error)
9351 *
9352 */
lsm6dsv32x_ui_sda_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)9353 int32_t lsm6dsv32x_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
9354 {
9355 lsm6dsv32x_if_cfg_t if_cfg;
9356 int32_t ret;
9357
9358 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1);
9359 if (ret == 0)
9360 {
9361 if_cfg.sda_pu_en = val;
9362 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1);
9363 }
9364
9365 return ret;
9366 }
9367
9368 /**
9369 * @brief Enables pull-up on SDA pin.[get]
9370 *
9371 * @param ctx read / write interface definitions
9372 * @param val Enables pull-up on SDA pin.
9373 * @retval interface status (MANDATORY: return 0 -> no Error)
9374 *
9375 */
lsm6dsv32x_ui_sda_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)9376 int32_t lsm6dsv32x_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
9377 {
9378 lsm6dsv32x_if_cfg_t if_cfg;
9379 int32_t ret;
9380
9381 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_IF_CFG, (uint8_t *)&if_cfg, 1);
9382 *val = if_cfg.sda_pu_en;
9383
9384 return ret;
9385 }
9386
9387 /**
9388 * @brief SPI2 (OIS Inteface) Serial Interface Mode selection. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set]
9389 *
9390 * @param ctx read / write interface definitions
9391 * @param val SPI2_4_WIRE, SPI2_3_WIRE,
9392 * @retval interface status (MANDATORY: return 0 -> no Error)
9393 *
9394 */
lsm6dsv32x_spi2_mode_set(const stmdev_ctx_t * ctx,lsm6dsv32x_spi2_mode_t val)9395 int32_t lsm6dsv32x_spi2_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_spi2_mode_t val)
9396 {
9397 lsm6dsv32x_ui_ctrl1_ois_t ui_ctrl1_ois;
9398 int32_t ret;
9399
9400 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
9401 if (ret == 0)
9402 {
9403 ui_ctrl1_ois.sim_ois = (uint8_t)val & 0x01U;
9404 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
9405 }
9406
9407 return ret;
9408 }
9409
9410 /**
9411 * @brief SPI2 (OIS Inteface) Serial Interface Mode selection. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[get]
9412 *
9413 * @param ctx read / write interface definitions
9414 * @param val SPI2_4_WIRE, SPI2_3_WIRE,
9415 * @retval interface status (MANDATORY: return 0 -> no Error)
9416 *
9417 */
lsm6dsv32x_spi2_mode_get(const stmdev_ctx_t * ctx,lsm6dsv32x_spi2_mode_t * val)9418 int32_t lsm6dsv32x_spi2_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_spi2_mode_t *val)
9419 {
9420 lsm6dsv32x_ui_ctrl1_ois_t ui_ctrl1_ois;
9421 int32_t ret;
9422
9423 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
9424 if (ret != 0)
9425 {
9426 return ret;
9427 }
9428
9429 switch (ui_ctrl1_ois.sim_ois)
9430 {
9431 case LSM6DSV32X_SPI2_4_WIRE:
9432 *val = LSM6DSV32X_SPI2_4_WIRE;
9433 break;
9434
9435 case LSM6DSV32X_SPI2_3_WIRE:
9436 *val = LSM6DSV32X_SPI2_3_WIRE;
9437 break;
9438
9439 default:
9440 *val = LSM6DSV32X_SPI2_4_WIRE;
9441 break;
9442 }
9443
9444 return ret;
9445 }
9446
9447 /**
9448 * @}
9449 *
9450 */
9451
9452 /**
9453 * @defgroup Significant motion detection
9454 * @brief This section groups all the functions that manage the
9455 * significant motion detection.
9456 * @{
9457 *
9458 */
9459
9460
9461 /**
9462 * @brief Enables significant motion detection function.[set]
9463 *
9464 * @param ctx read / write interface definitions
9465 * @param val Enables significant motion detection function.
9466 * @retval interface status (MANDATORY: return 0 -> no Error)
9467 *
9468 */
lsm6dsv32x_sigmot_mode_set(const stmdev_ctx_t * ctx,uint8_t val)9469 int32_t lsm6dsv32x_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
9470 {
9471 lsm6dsv32x_emb_func_en_a_t emb_func_en_a;
9472 int32_t ret;
9473
9474 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
9475 if (ret != 0)
9476 {
9477 return ret;
9478 }
9479
9480 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9481 emb_func_en_a.sign_motion_en = val;
9482 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9483
9484 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
9485
9486 return ret;
9487 }
9488
9489 /**
9490 * @brief Enables significant motion detection function.[get]
9491 *
9492 * @param ctx read / write interface definitions
9493 * @param val Enables significant motion detection function.
9494 * @retval interface status (MANDATORY: return 0 -> no Error)
9495 *
9496 */
lsm6dsv32x_sigmot_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)9497 int32_t lsm6dsv32x_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
9498 {
9499 lsm6dsv32x_emb_func_en_a_t emb_func_en_a;
9500 int32_t ret;
9501
9502 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
9503 if (ret != 0)
9504 {
9505 return ret;
9506 }
9507
9508 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9509 *val = emb_func_en_a.sign_motion_en;
9510
9511 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
9512
9513 return ret;
9514 }
9515
9516 /**
9517 * @}
9518 *
9519 */
9520
9521 /**
9522 * @defgroup Step Counter (Pedometer)
9523 * @brief This section groups all the functions that manage pedometer.
9524 * @{
9525 *
9526 */
9527
9528 /**
9529 * @brief Step counter mode[set]
9530 *
9531 * @param ctx read / write interface definitions
9532 * @param val Step counter mode
9533 * @retval interface status (MANDATORY: return 0 -> no Error)
9534 *
9535 */
lsm6dsv32x_stpcnt_mode_set(const stmdev_ctx_t * ctx,lsm6dsv32x_stpcnt_mode_t val)9536 int32_t lsm6dsv32x_stpcnt_mode_set(const stmdev_ctx_t *ctx,
9537 lsm6dsv32x_stpcnt_mode_t val)
9538 {
9539 lsm6dsv32x_emb_func_en_a_t emb_func_en_a;
9540 lsm6dsv32x_emb_func_en_b_t emb_func_en_b;
9541 lsm6dsv32x_pedo_cmd_reg_t pedo_cmd_reg;
9542 int32_t ret;
9543
9544 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
9545 if (ret != 0)
9546 {
9547 return ret;
9548 }
9549
9550 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9551 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
9552 if (ret != 0)
9553 {
9554 goto exit;
9555 }
9556
9557 if ((val.false_step_rej == PROPERTY_ENABLE)
9558 && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) ==
9559 PROPERTY_DISABLE))
9560 {
9561 emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE;
9562 }
9563
9564 emb_func_en_a.pedo_en = val.step_counter_enable;
9565 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9566
9567 exit:
9568 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
9569
9570 if (ret == 0)
9571 {
9572 ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_PEDO_CMD_REG,
9573 (uint8_t *)&pedo_cmd_reg, 1);
9574 pedo_cmd_reg.fp_rejection_en = val.false_step_rej;
9575 ret += lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_PEDO_CMD_REG,
9576 (uint8_t *)&pedo_cmd_reg, 1);
9577 }
9578
9579 return ret;
9580 }
9581
9582 /**
9583 * @brief Step counter mode[get]
9584 *
9585 * @param ctx read / write interface definitions
9586 * @param val false_step_rej, step_counter, step_detector,
9587 * @retval interface status (MANDATORY: return 0 -> no Error)
9588 *
9589 */
lsm6dsv32x_stpcnt_mode_get(const stmdev_ctx_t * ctx,lsm6dsv32x_stpcnt_mode_t * val)9590 int32_t lsm6dsv32x_stpcnt_mode_get(const stmdev_ctx_t *ctx,
9591 lsm6dsv32x_stpcnt_mode_t *val)
9592 {
9593 lsm6dsv32x_emb_func_en_a_t emb_func_en_a;
9594 lsm6dsv32x_pedo_cmd_reg_t pedo_cmd_reg;
9595 int32_t ret;
9596
9597 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
9598 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9599 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
9600 if (ret != 0)
9601 {
9602 return ret;
9603 }
9604
9605 ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_PEDO_CMD_REG,
9606 (uint8_t *)&pedo_cmd_reg, 1);
9607 if (ret != 0)
9608 {
9609 return ret;
9610 }
9611
9612 val->false_step_rej = pedo_cmd_reg.fp_rejection_en;
9613 val->step_counter_enable = emb_func_en_a.pedo_en;
9614
9615 return ret;
9616 }
9617
9618 /**
9619 * @brief Step counter output, number of detected steps.[get]
9620 *
9621 * @param ctx read / write interface definitions
9622 * @param val Step counter output, number of detected steps.
9623 * @retval interface status (MANDATORY: return 0 -> no Error)
9624 *
9625 */
lsm6dsv32x_stpcnt_steps_get(const stmdev_ctx_t * ctx,uint16_t * val)9626 int32_t lsm6dsv32x_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val)
9627 {
9628 uint8_t buff[2];
9629 int32_t ret;
9630
9631 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
9632 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_STEP_COUNTER_L, &buff[0], 2);
9633 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
9634 if (ret != 0)
9635 {
9636 return ret;
9637 }
9638
9639 *val = buff[1];
9640 *val = (*val * 256U) + buff[0];
9641
9642 return ret;
9643 }
9644
9645 /**
9646 * @brief Reset step counter.[set]
9647 *
9648 * @param ctx read / write interface definitions
9649 * @param val Reset step counter.
9650 * @retval interface status (MANDATORY: return 0 -> no Error)
9651 *
9652 */
lsm6dsv32x_stpcnt_rst_step_set(const stmdev_ctx_t * ctx,uint8_t val)9653 int32_t lsm6dsv32x_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val)
9654 {
9655 lsm6dsv32x_emb_func_src_t emb_func_src;
9656 int32_t ret;
9657
9658 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
9659 if (ret != 0)
9660 {
9661 return ret;
9662 }
9663
9664 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
9665 if (ret != 0)
9666 {
9667 goto exit;
9668 }
9669
9670 emb_func_src.pedo_rst_step = val;
9671 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
9672
9673 exit:
9674 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
9675
9676 return ret;
9677 }
9678
9679 /**
9680 * @brief Reset step counter.[get]
9681 *
9682 * @param ctx read / write interface definitions
9683 * @param val Reset step counter.
9684 * @retval interface status (MANDATORY: return 0 -> no Error)
9685 *
9686 */
lsm6dsv32x_stpcnt_rst_step_get(const stmdev_ctx_t * ctx,uint8_t * val)9687 int32_t lsm6dsv32x_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val)
9688 {
9689 lsm6dsv32x_emb_func_src_t emb_func_src;
9690 int32_t ret;
9691
9692 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
9693 if (ret != 0)
9694 {
9695 return ret;
9696 }
9697
9698 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
9699 *val = emb_func_src.pedo_rst_step;
9700
9701 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
9702
9703 return ret;
9704 }
9705
9706 /**
9707 * @brief Pedometer debounce configuration.[set]
9708 *
9709 * @param ctx read / write interface definitions
9710 * @param val Pedometer debounce configuration.
9711 * @retval interface status (MANDATORY: return 0 -> no Error)
9712 *
9713 */
lsm6dsv32x_stpcnt_debounce_set(const stmdev_ctx_t * ctx,uint8_t val)9714 int32_t lsm6dsv32x_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val)
9715 {
9716 lsm6dsv32x_pedo_deb_steps_conf_t pedo_deb_steps_conf;
9717 int32_t ret;
9718
9719 ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_PEDO_DEB_STEPS_CONF,
9720 (uint8_t *)&pedo_deb_steps_conf, 1);
9721 if (ret == 0)
9722 {
9723 pedo_deb_steps_conf.deb_step = val;
9724 ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_PEDO_DEB_STEPS_CONF,
9725 (uint8_t *)&pedo_deb_steps_conf, 1);
9726 }
9727
9728 return ret;
9729 }
9730
9731 /**
9732 * @brief Pedometer debounce configuration.[get]
9733 *
9734 * @param ctx read / write interface definitions
9735 * @param val Pedometer debounce configuration.
9736 * @retval interface status (MANDATORY: return 0 -> no Error)
9737 *
9738 */
lsm6dsv32x_stpcnt_debounce_get(const stmdev_ctx_t * ctx,uint8_t * val)9739 int32_t lsm6dsv32x_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val)
9740 {
9741 lsm6dsv32x_pedo_deb_steps_conf_t pedo_deb_steps_conf;
9742 int32_t ret;
9743
9744 ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_PEDO_DEB_STEPS_CONF,
9745 (uint8_t *)&pedo_deb_steps_conf, 1);
9746 *val = pedo_deb_steps_conf.deb_step;
9747
9748 return ret;
9749 }
9750
9751 /**
9752 * @brief Time period register for step detection on delta time.[set]
9753 *
9754 * @param ctx read / write interface definitions
9755 * @param val Time period register for step detection on delta time.
9756 * @retval interface status (MANDATORY: return 0 -> no Error)
9757 *
9758 */
lsm6dsv32x_stpcnt_period_set(const stmdev_ctx_t * ctx,uint16_t val)9759 int32_t lsm6dsv32x_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val)
9760 {
9761 uint8_t buff[2];
9762 int32_t ret;
9763
9764 buff[1] = (uint8_t)(val / 256U);
9765 buff[0] = (uint8_t)(val - (buff[1] * 256U));
9766 ret = lsm6dsv32x_ln_pg_write(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_PEDO_SC_DELTAT_L,
9767 (uint8_t *)&buff[0], 2);
9768
9769 return ret;
9770 }
9771
9772 /**
9773 * @brief Time period register for step detection on delta time.[get]
9774 *
9775 * @param ctx read / write interface definitions
9776 * @param val Time period register for step detection on delta time.
9777 * @retval interface status (MANDATORY: return 0 -> no Error)
9778 *
9779 */
lsm6dsv32x_stpcnt_period_get(const stmdev_ctx_t * ctx,uint16_t * val)9780 int32_t lsm6dsv32x_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val)
9781 {
9782 uint8_t buff[2];
9783 int32_t ret;
9784
9785 ret = lsm6dsv32x_ln_pg_read(ctx, LSM6DSV32X_EMB_ADV_PG_1 + LSM6DSV32X_PEDO_SC_DELTAT_L, &buff[0],
9786 2);
9787 if (ret != 0)
9788 {
9789 return ret;
9790 }
9791
9792 *val = buff[1];
9793 *val = (*val * 256U) + buff[0];
9794
9795 return ret;
9796 }
9797
9798 /**
9799 * @}
9800 *
9801 */
9802
9803 /**
9804 * @defgroup Sensor Fusion Low Power (SFLP)
9805 * @brief This section groups all the functions that manage pedometer.
9806 * @{
9807 *
9808 */
9809
9810 /**
9811 * @brief Enable SFLP Game Rotation Vector (6x).[set]
9812 *
9813 * @param ctx read / write interface definitions
9814 * @param val Enable/Disable game rotation value (0/1).
9815 * @retval interface status (MANDATORY: return 0 -> no Error)
9816 *
9817 */
lsm6dsv32x_sflp_game_rotation_set(const stmdev_ctx_t * ctx,uint8_t val)9818 int32_t lsm6dsv32x_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint8_t val)
9819 {
9820 lsm6dsv32x_emb_func_en_a_t emb_func_en_a;
9821 int32_t ret;
9822
9823 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
9824 if (ret != 0)
9825 {
9826 return ret;
9827 }
9828
9829 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9830 if (ret != 0)
9831 {
9832 goto exit;
9833 }
9834
9835 emb_func_en_a.sflp_game_en = val;
9836 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A,
9837 (uint8_t *)&emb_func_en_a, 1);
9838
9839 exit:
9840 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
9841
9842 return ret;
9843 }
9844
9845 /**
9846 * @brief Enable SFLP Game Rotation Vector (6x).[get]
9847 *
9848 * @param ctx read / write interface definitions
9849 * @param val Enable/Disable game rotation value (0/1).
9850 * @retval interface status (MANDATORY: return 0 -> no Error)
9851 *
9852 */
lsm6dsv32x_sflp_game_rotation_get(const stmdev_ctx_t * ctx,uint8_t * val)9853 int32_t lsm6dsv32x_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint8_t *val)
9854 {
9855 lsm6dsv32x_emb_func_en_a_t emb_func_en_a;
9856 int32_t ret;
9857
9858 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
9859 if (ret != 0)
9860 {
9861 return ret;
9862 }
9863
9864 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9865 *val = emb_func_en_a.sflp_game_en;
9866
9867 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
9868
9869 return ret;
9870 }
9871
9872 /**
9873 * @brief SFLP Data Rate (ODR) configuration.[set]
9874 *
9875 * @param ctx read / write interface definitions
9876 * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz
9877 * @retval interface status (MANDATORY: return 0 -> no Error)
9878 *
9879 */
lsm6dsv32x_sflp_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv32x_sflp_data_rate_t val)9880 int32_t lsm6dsv32x_sflp_data_rate_set(const stmdev_ctx_t *ctx,
9881 lsm6dsv32x_sflp_data_rate_t val)
9882 {
9883 lsm6dsv32x_sflp_odr_t sflp_odr;
9884 int32_t ret;
9885
9886 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
9887 if (ret != 0)
9888 {
9889 return ret;
9890 }
9891
9892 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
9893 if (ret != 0)
9894 {
9895 goto exit;
9896 }
9897
9898 sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U;
9899 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
9900
9901 exit:
9902 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
9903
9904 return ret;
9905 }
9906
9907 /**
9908 * @brief SFLP Data Rate (ODR) configuration.[get]
9909 *
9910 * @param ctx read / write interface definitions
9911 * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz
9912 * @retval interface status (MANDATORY: return 0 -> no Error)
9913 *
9914 */
lsm6dsv32x_sflp_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv32x_sflp_data_rate_t * val)9915 int32_t lsm6dsv32x_sflp_data_rate_get(const stmdev_ctx_t *ctx,
9916 lsm6dsv32x_sflp_data_rate_t *val)
9917 {
9918 lsm6dsv32x_sflp_odr_t sflp_odr;
9919 int32_t ret;
9920
9921 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
9922 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
9923 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
9924 if (ret != 0)
9925 {
9926 return ret;
9927 }
9928
9929 switch (sflp_odr.sflp_game_odr)
9930 {
9931 case LSM6DSV32X_SFLP_15Hz:
9932 *val = LSM6DSV32X_SFLP_15Hz;
9933 break;
9934
9935 case LSM6DSV32X_SFLP_30Hz:
9936 *val = LSM6DSV32X_SFLP_30Hz;
9937 break;
9938
9939 case LSM6DSV32X_SFLP_60Hz:
9940 *val = LSM6DSV32X_SFLP_60Hz;
9941 break;
9942
9943 case LSM6DSV32X_SFLP_120Hz:
9944 *val = LSM6DSV32X_SFLP_120Hz;
9945 break;
9946
9947 case LSM6DSV32X_SFLP_240Hz:
9948 *val = LSM6DSV32X_SFLP_240Hz;
9949 break;
9950
9951 case LSM6DSV32X_SFLP_480Hz:
9952 *val = LSM6DSV32X_SFLP_480Hz;
9953 break;
9954
9955 default:
9956 *val = LSM6DSV32X_SFLP_15Hz;
9957 break;
9958 }
9959
9960 return ret;
9961 }
9962
9963 /**
9964 * @}
9965 *
9966 */
9967
9968 /**
9969 * @defgroup Tap - Double Tap
9970 * @brief This section groups all the functions that manage the
9971 * tap and double tap event generation.
9972 * @{
9973 *
9974 */
9975
9976 /**
9977 * @brief Enable axis for Tap - Double Tap detection.[set]
9978 *
9979 * @param ctx read / write interface definitions
9980 * @param val Enable axis for Tap - Double Tap detection.
9981 * @retval interface status (MANDATORY: return 0 -> no Error)
9982 *
9983 */
lsm6dsv32x_tap_detection_set(const stmdev_ctx_t * ctx,lsm6dsv32x_tap_detection_t val)9984 int32_t lsm6dsv32x_tap_detection_set(const stmdev_ctx_t *ctx,
9985 lsm6dsv32x_tap_detection_t val)
9986 {
9987 lsm6dsv32x_tap_cfg0_t tap_cfg0;
9988 int32_t ret;
9989
9990 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
9991 if (ret == 0)
9992 {
9993 tap_cfg0.tap_x_en = val.tap_x_en;
9994 tap_cfg0.tap_y_en = val.tap_y_en;
9995 tap_cfg0.tap_z_en = val.tap_z_en;
9996 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
9997 }
9998
9999 return ret;
10000 }
10001
10002 /**
10003 * @brief Enable axis for Tap - Double Tap detection.[get]
10004 *
10005 * @param ctx read / write interface definitions
10006 * @param val Enable axis for Tap - Double Tap detection.
10007 * @retval interface status (MANDATORY: return 0 -> no Error)
10008 *
10009 */
lsm6dsv32x_tap_detection_get(const stmdev_ctx_t * ctx,lsm6dsv32x_tap_detection_t * val)10010 int32_t lsm6dsv32x_tap_detection_get(const stmdev_ctx_t *ctx,
10011 lsm6dsv32x_tap_detection_t *val)
10012 {
10013 lsm6dsv32x_tap_cfg0_t tap_cfg0;
10014 int32_t ret;
10015
10016 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
10017 if (ret != 0)
10018 {
10019 return ret;
10020 }
10021
10022 val->tap_x_en = tap_cfg0.tap_x_en;
10023 val->tap_y_en = tap_cfg0.tap_y_en;
10024 val->tap_z_en = tap_cfg0.tap_z_en;
10025
10026 return ret;
10027 }
10028
10029 /**
10030 * @brief axis Tap - Double Tap recognition thresholds.[set]
10031 *
10032 * @param ctx read / write interface definitions
10033 * @param val axis Tap - Double Tap recognition thresholds.
10034 * @retval interface status (MANDATORY: return 0 -> no Error)
10035 *
10036 */
lsm6dsv32x_tap_thresholds_set(const stmdev_ctx_t * ctx,lsm6dsv32x_tap_thresholds_t val)10037 int32_t lsm6dsv32x_tap_thresholds_set(const stmdev_ctx_t *ctx,
10038 lsm6dsv32x_tap_thresholds_t val)
10039 {
10040 lsm6dsv32x_tap_ths_6d_t tap_ths_6d;
10041 lsm6dsv32x_tap_cfg2_t tap_cfg2;
10042 lsm6dsv32x_tap_cfg1_t tap_cfg1;
10043 int32_t ret;
10044
10045 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
10046 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
10047 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
10048 if (ret != 0)
10049 {
10050 return ret;
10051 }
10052
10053 tap_cfg1.tap_ths_x = val.x;
10054 tap_cfg2.tap_ths_y = val.y;
10055 tap_ths_6d.tap_ths_z = val.z;
10056
10057 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
10058 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
10059 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
10060
10061 return ret;
10062 }
10063
10064 /**
10065 * @brief axis Tap - Double Tap recognition thresholds.[get]
10066 *
10067 * @param ctx read / write interface definitions
10068 * @param val axis Tap - Double Tap recognition thresholds.
10069 * @retval interface status (MANDATORY: return 0 -> no Error)
10070 *
10071 */
lsm6dsv32x_tap_thresholds_get(const stmdev_ctx_t * ctx,lsm6dsv32x_tap_thresholds_t * val)10072 int32_t lsm6dsv32x_tap_thresholds_get(const stmdev_ctx_t *ctx,
10073 lsm6dsv32x_tap_thresholds_t *val)
10074 {
10075 lsm6dsv32x_tap_ths_6d_t tap_ths_6d;
10076 lsm6dsv32x_tap_cfg2_t tap_cfg2;
10077 lsm6dsv32x_tap_cfg1_t tap_cfg1;
10078 int32_t ret;
10079
10080 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
10081 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
10082 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
10083 if (ret != 0)
10084 {
10085 return ret;
10086 }
10087
10088 val->x = tap_cfg1.tap_ths_x;
10089 val->y = tap_cfg2.tap_ths_y;
10090 val->z = tap_ths_6d.tap_ths_z;
10091
10092 return ret;
10093 }
10094
10095 /**
10096 * @brief Selection of axis priority for TAP detection.[set]
10097 *
10098 * @param ctx read / write interface definitions
10099 * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY ,
10100 * @retval interface status (MANDATORY: return 0 -> no Error)
10101 *
10102 */
lsm6dsv32x_tap_axis_priority_set(const stmdev_ctx_t * ctx,lsm6dsv32x_tap_axis_priority_t val)10103 int32_t lsm6dsv32x_tap_axis_priority_set(const stmdev_ctx_t *ctx,
10104 lsm6dsv32x_tap_axis_priority_t val)
10105 {
10106 lsm6dsv32x_tap_cfg1_t tap_cfg1;
10107 int32_t ret;
10108
10109 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
10110 if (ret == 0)
10111 {
10112 tap_cfg1.tap_priority = (uint8_t)val & 0x7U;
10113 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
10114 }
10115
10116 return ret;
10117 }
10118
10119 /**
10120 * @brief Selection of axis priority for TAP detection.[get]
10121 *
10122 * @param ctx read / write interface definitions
10123 * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY ,
10124 * @retval interface status (MANDATORY: return 0 -> no Error)
10125 *
10126 */
lsm6dsv32x_tap_axis_priority_get(const stmdev_ctx_t * ctx,lsm6dsv32x_tap_axis_priority_t * val)10127 int32_t lsm6dsv32x_tap_axis_priority_get(const stmdev_ctx_t *ctx,
10128 lsm6dsv32x_tap_axis_priority_t *val)
10129 {
10130 lsm6dsv32x_tap_cfg1_t tap_cfg1;
10131 int32_t ret;
10132
10133 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
10134 if (ret != 0)
10135 {
10136 return ret;
10137 }
10138
10139 switch (tap_cfg1.tap_priority)
10140 {
10141 case LSM6DSV32X_XYZ :
10142 *val = LSM6DSV32X_XYZ ;
10143 break;
10144
10145 case LSM6DSV32X_YXZ :
10146 *val = LSM6DSV32X_YXZ ;
10147 break;
10148
10149 case LSM6DSV32X_XZY:
10150 *val = LSM6DSV32X_XZY;
10151 break;
10152
10153 case LSM6DSV32X_ZYX :
10154 *val = LSM6DSV32X_ZYX ;
10155 break;
10156
10157 case LSM6DSV32X_YZX :
10158 *val = LSM6DSV32X_YZX ;
10159 break;
10160
10161 case LSM6DSV32X_ZXY :
10162 *val = LSM6DSV32X_ZXY ;
10163 break;
10164
10165 default:
10166 *val = LSM6DSV32X_XYZ ;
10167 break;
10168 }
10169
10170 return ret;
10171 }
10172
10173 /**
10174 * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[set]
10175 *
10176 * @param ctx read / write interface definitions
10177 * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.
10178 * @retval interface status (MANDATORY: return 0 -> no Error)
10179 *
10180 */
lsm6dsv32x_tap_time_windows_set(const stmdev_ctx_t * ctx,lsm6dsv32x_tap_time_windows_t val)10181 int32_t lsm6dsv32x_tap_time_windows_set(const stmdev_ctx_t *ctx,
10182 lsm6dsv32x_tap_time_windows_t val)
10183 {
10184 lsm6dsv32x_tap_dur_t tap_dur;
10185 int32_t ret;
10186
10187 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_DUR, (uint8_t *)&tap_dur, 1);
10188 if (ret == 0)
10189 {
10190 tap_dur.shock = val.shock;
10191 tap_dur.quiet = val.quiet;
10192 tap_dur.dur = val.tap_gap;
10193 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_TAP_DUR, (uint8_t *)&tap_dur, 1);
10194 }
10195
10196 return ret;
10197 }
10198
10199 /**
10200 * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[get]
10201 *
10202 * @param ctx read / write interface definitions
10203 * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.
10204 * @retval interface status (MANDATORY: return 0 -> no Error)
10205 *
10206 */
lsm6dsv32x_tap_time_windows_get(const stmdev_ctx_t * ctx,lsm6dsv32x_tap_time_windows_t * val)10207 int32_t lsm6dsv32x_tap_time_windows_get(const stmdev_ctx_t *ctx,
10208 lsm6dsv32x_tap_time_windows_t *val)
10209 {
10210 lsm6dsv32x_tap_dur_t tap_dur;
10211 int32_t ret;
10212
10213 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TAP_DUR, (uint8_t *)&tap_dur, 1);
10214 if (ret != 0)
10215 {
10216 return ret;
10217 }
10218
10219 val->shock = tap_dur.shock;
10220 val->quiet = tap_dur.quiet;
10221 val->tap_gap = tap_dur.dur;
10222
10223 return ret;
10224 }
10225
10226 /**
10227 * @brief Single/double-tap event enable.[set]
10228 *
10229 * @param ctx read / write interface definitions
10230 * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE,
10231 * @retval interface status (MANDATORY: return 0 -> no Error)
10232 *
10233 */
lsm6dsv32x_tap_mode_set(const stmdev_ctx_t * ctx,lsm6dsv32x_tap_mode_t val)10234 int32_t lsm6dsv32x_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_tap_mode_t val)
10235 {
10236 lsm6dsv32x_wake_up_ths_t wake_up_ths;
10237 int32_t ret;
10238
10239 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
10240 if (ret == 0)
10241 {
10242 wake_up_ths.single_double_tap = (uint8_t)val & 0x01U;
10243 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
10244 }
10245
10246 return ret;
10247 }
10248
10249 /**
10250 * @brief Single/double-tap event enable.[get]
10251 *
10252 * @param ctx read / write interface definitions
10253 * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE,
10254 * @retval interface status (MANDATORY: return 0 -> no Error)
10255 *
10256 */
lsm6dsv32x_tap_mode_get(const stmdev_ctx_t * ctx,lsm6dsv32x_tap_mode_t * val)10257 int32_t lsm6dsv32x_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_tap_mode_t *val)
10258 {
10259 lsm6dsv32x_wake_up_ths_t wake_up_ths;
10260 int32_t ret;
10261
10262 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
10263 if (ret != 0)
10264 {
10265 return ret;
10266 }
10267
10268 switch (wake_up_ths.single_double_tap)
10269 {
10270 case LSM6DSV32X_ONLY_SINGLE:
10271 *val = LSM6DSV32X_ONLY_SINGLE;
10272 break;
10273
10274 case LSM6DSV32X_BOTH_SINGLE_DOUBLE:
10275 *val = LSM6DSV32X_BOTH_SINGLE_DOUBLE;
10276 break;
10277
10278 default:
10279 *val = LSM6DSV32X_ONLY_SINGLE;
10280 break;
10281 }
10282
10283 return ret;
10284 }
10285
10286 /**
10287 * @}
10288 *
10289 */
10290
10291 /**
10292 * @defgroup Tilt detection
10293 * @brief This section groups all the functions that manage the tilt
10294 * event detection.
10295 * @{
10296 *
10297 */
10298
10299 /**
10300 * @brief Tilt calculation.[set]
10301 *
10302 * @param ctx read / write interface definitions
10303 * @param val Tilt calculation.
10304 * @retval interface status (MANDATORY: return 0 -> no Error)
10305 *
10306 */
lsm6dsv32x_tilt_mode_set(const stmdev_ctx_t * ctx,uint8_t val)10307 int32_t lsm6dsv32x_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
10308 {
10309 lsm6dsv32x_emb_func_en_a_t emb_func_en_a;
10310 int32_t ret;
10311
10312 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
10313 if (ret != 0)
10314 {
10315 return ret;
10316 }
10317
10318 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
10319 emb_func_en_a.tilt_en = val;
10320 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
10321
10322 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
10323
10324 return ret;
10325 }
10326
10327 /**
10328 * @brief Tilt calculation.[get]
10329 *
10330 * @param ctx read / write interface definitions
10331 * @param val Tilt calculation.
10332 * @retval interface status (MANDATORY: return 0 -> no Error)
10333 *
10334 */
lsm6dsv32x_tilt_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)10335 int32_t lsm6dsv32x_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
10336 {
10337 lsm6dsv32x_emb_func_en_a_t emb_func_en_a;
10338 int32_t ret;
10339
10340 ret = lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_EMBED_FUNC_MEM_BANK);
10341 if (ret != 0)
10342 {
10343 return ret;
10344 }
10345
10346 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
10347 *val = emb_func_en_a.tilt_en;
10348
10349 ret += lsm6dsv32x_mem_bank_set(ctx, LSM6DSV32X_MAIN_MEM_BANK);
10350
10351 return ret;
10352 }
10353
10354 /**
10355 * @}
10356 *
10357 */
10358
10359 /**
10360 * @defgroup Timestamp
10361 * @brief This section groups all the functions that manage the
10362 * timestamp generation.
10363 * @{
10364 *
10365 */
10366
10367 /**
10368 * @brief Timestamp data output.[get]
10369 *
10370 * @param ctx read / write interface definitions
10371 * @param val Timestamp data output.
10372 * @retval interface status (MANDATORY: return 0 -> no Error)
10373 *
10374 */
lsm6dsv32x_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)10375 int32_t lsm6dsv32x_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
10376 {
10377 uint8_t buff[4];
10378 int32_t ret;
10379
10380 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_TIMESTAMP0, &buff[0], 4);
10381 if (ret != 0)
10382 {
10383 return ret;
10384 }
10385
10386 *val = buff[3];
10387 *val = (*val * 256U) + buff[2];
10388 *val = (*val * 256U) + buff[1];
10389 *val = (*val * 256U) + buff[0];
10390
10391 return ret;
10392 }
10393
10394 /**
10395 * @brief Enables timestamp counter.[set]
10396 *
10397 * @param ctx read / write interface definitions
10398 * @param val Enables timestamp counter.
10399 * @retval interface status (MANDATORY: return 0 -> no Error)
10400 *
10401 */
lsm6dsv32x_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)10402 int32_t lsm6dsv32x_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
10403 {
10404 lsm6dsv32x_functions_enable_t functions_enable;
10405 int32_t ret;
10406
10407 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
10408 if (ret == 0)
10409 {
10410 functions_enable.timestamp_en = val;
10411 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
10412 }
10413
10414 return ret;
10415 }
10416
10417 /**
10418 * @brief Enables timestamp counter.[get]
10419 *
10420 * @param ctx read / write interface definitions
10421 * @param val Enables timestamp counter.
10422 * @retval interface status (MANDATORY: return 0 -> no Error)
10423 *
10424 */
lsm6dsv32x_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)10425 int32_t lsm6dsv32x_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
10426 {
10427 lsm6dsv32x_functions_enable_t functions_enable;
10428 int32_t ret;
10429
10430 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
10431 *val = functions_enable.timestamp_en;
10432
10433 return ret;
10434 }
10435
10436 /**
10437 * @}
10438 *
10439 */
10440
10441 /**
10442 * @defgroup Wake Up - Activity - Inactivity (Sleep)
10443 * @brief This section groups all the functions that manage the Wake Up
10444 * event generation.
10445 * @{
10446 *
10447 */
10448
10449 /**
10450 * @brief Enable activity/inactivity (sleep) function.[set]
10451 *
10452 * @param ctx read / write interface definitions
10453 * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN,
10454 * @retval interface status (MANDATORY: return 0 -> no Error)
10455 *
10456 */
lsm6dsv32x_act_mode_set(const stmdev_ctx_t * ctx,lsm6dsv32x_act_mode_t val)10457 int32_t lsm6dsv32x_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsv32x_act_mode_t val)
10458 {
10459 lsm6dsv32x_functions_enable_t functions_enable;
10460 int32_t ret;
10461
10462 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
10463 if (ret == 0)
10464 {
10465 functions_enable.inact_en = (uint8_t)val & 0x3U;
10466 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
10467 }
10468
10469 return ret;
10470 }
10471
10472 /**
10473 * @brief Enable activity/inactivity (sleep) function.[get]
10474 *
10475 * @param ctx read / write interface definitions
10476 * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN,
10477 * @retval interface status (MANDATORY: return 0 -> no Error)
10478 *
10479 */
lsm6dsv32x_act_mode_get(const stmdev_ctx_t * ctx,lsm6dsv32x_act_mode_t * val)10480 int32_t lsm6dsv32x_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsv32x_act_mode_t *val)
10481 {
10482 lsm6dsv32x_functions_enable_t functions_enable;
10483 int32_t ret;
10484
10485 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
10486 if (ret != 0)
10487 {
10488 return ret;
10489 }
10490
10491 switch (functions_enable.inact_en)
10492 {
10493 case LSM6DSV32X_XL_AND_GY_NOT_AFFECTED:
10494 *val = LSM6DSV32X_XL_AND_GY_NOT_AFFECTED;
10495 break;
10496
10497 case LSM6DSV32X_XL_LOW_POWER_GY_NOT_AFFECTED:
10498 *val = LSM6DSV32X_XL_LOW_POWER_GY_NOT_AFFECTED;
10499 break;
10500
10501 case LSM6DSV32X_XL_LOW_POWER_GY_SLEEP:
10502 *val = LSM6DSV32X_XL_LOW_POWER_GY_SLEEP;
10503 break;
10504
10505 case LSM6DSV32X_XL_LOW_POWER_GY_POWER_DOWN:
10506 *val = LSM6DSV32X_XL_LOW_POWER_GY_POWER_DOWN;
10507 break;
10508
10509 default:
10510 *val = LSM6DSV32X_XL_AND_GY_NOT_AFFECTED;
10511 break;
10512 }
10513
10514 return ret;
10515 }
10516
10517 /**
10518 * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[set]
10519 *
10520 * @param ctx read / write interface definitions
10521 * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE,
10522 * @retval interface status (MANDATORY: return 0 -> no Error)
10523 *
10524 */
lsm6dsv32x_act_from_sleep_to_act_dur_set(const stmdev_ctx_t * ctx,lsm6dsv32x_act_from_sleep_to_act_dur_t val)10525 int32_t lsm6dsv32x_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx,
10526 lsm6dsv32x_act_from_sleep_to_act_dur_t val)
10527 {
10528 lsm6dsv32x_inactivity_dur_t inactivity_dur;
10529 int32_t ret;
10530
10531 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10532 if (ret == 0)
10533 {
10534 inactivity_dur.inact_dur = (uint8_t)val & 0x3U;
10535 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10536 }
10537
10538 return ret;
10539 }
10540
10541 /**
10542 * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[get]
10543 *
10544 * @param ctx read / write interface definitions
10545 * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE,
10546 * @retval interface status (MANDATORY: return 0 -> no Error)
10547 *
10548 */
lsm6dsv32x_act_from_sleep_to_act_dur_get(const stmdev_ctx_t * ctx,lsm6dsv32x_act_from_sleep_to_act_dur_t * val)10549 int32_t lsm6dsv32x_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx,
10550 lsm6dsv32x_act_from_sleep_to_act_dur_t *val)
10551 {
10552 lsm6dsv32x_inactivity_dur_t inactivity_dur;
10553 int32_t ret;
10554
10555 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10556 if (ret != 0)
10557 {
10558 return ret;
10559 }
10560
10561 switch (inactivity_dur.inact_dur)
10562 {
10563 case LSM6DSV32X_SLEEP_TO_ACT_AT_1ST_SAMPLE:
10564 *val = LSM6DSV32X_SLEEP_TO_ACT_AT_1ST_SAMPLE;
10565 break;
10566
10567 case LSM6DSV32X_SLEEP_TO_ACT_AT_2ND_SAMPLE:
10568 *val = LSM6DSV32X_SLEEP_TO_ACT_AT_2ND_SAMPLE;
10569 break;
10570
10571 case LSM6DSV32X_SLEEP_TO_ACT_AT_3RD_SAMPLE:
10572 *val = LSM6DSV32X_SLEEP_TO_ACT_AT_3RD_SAMPLE;
10573 break;
10574
10575 case LSM6DSV32X_SLEEP_TO_ACT_AT_4th_SAMPLE:
10576 *val = LSM6DSV32X_SLEEP_TO_ACT_AT_4th_SAMPLE;
10577 break;
10578
10579 default:
10580 *val = LSM6DSV32X_SLEEP_TO_ACT_AT_1ST_SAMPLE;
10581 break;
10582 }
10583
10584 return ret;
10585 }
10586
10587 /**
10588 * @brief Selects the accelerometer data rate during Inactivity.[set]
10589 *
10590 * @param ctx read / write interface definitions
10591 * @param val 1Hz875, 15Hz, 30Hz, 60Hz,
10592 * @retval interface status (MANDATORY: return 0 -> no Error)
10593 *
10594 */
lsm6dsv32x_act_sleep_xl_odr_set(const stmdev_ctx_t * ctx,lsm6dsv32x_act_sleep_xl_odr_t val)10595 int32_t lsm6dsv32x_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx,
10596 lsm6dsv32x_act_sleep_xl_odr_t val)
10597 {
10598 lsm6dsv32x_inactivity_dur_t inactivity_dur;
10599 int32_t ret;
10600
10601 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10602 if (ret == 0)
10603 {
10604 inactivity_dur.xl_inact_odr = (uint8_t)val & 0x03U;
10605 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10606 }
10607
10608 return ret;
10609 }
10610
10611 /**
10612 * @brief Selects the accelerometer data rate during Inactivity.[get]
10613 *
10614 * @param ctx read / write interface definitions
10615 * @param val 1Hz875, 15Hz, 30Hz, 60Hz,
10616 * @retval interface status (MANDATORY: return 0 -> no Error)
10617 *
10618 */
lsm6dsv32x_act_sleep_xl_odr_get(const stmdev_ctx_t * ctx,lsm6dsv32x_act_sleep_xl_odr_t * val)10619 int32_t lsm6dsv32x_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx,
10620 lsm6dsv32x_act_sleep_xl_odr_t *val)
10621 {
10622 lsm6dsv32x_inactivity_dur_t inactivity_dur;
10623 int32_t ret;
10624
10625 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10626 if (ret != 0)
10627 {
10628 return ret;
10629 }
10630
10631 switch (inactivity_dur.xl_inact_odr)
10632 {
10633 case LSM6DSV32X_1Hz875:
10634 *val = LSM6DSV32X_1Hz875;
10635 break;
10636
10637 case LSM6DSV32X_15Hz:
10638 *val = LSM6DSV32X_15Hz;
10639 break;
10640
10641 case LSM6DSV32X_30Hz:
10642 *val = LSM6DSV32X_30Hz;
10643 break;
10644
10645 case LSM6DSV32X_60Hz:
10646 *val = LSM6DSV32X_60Hz;
10647 break;
10648
10649 default:
10650 *val = LSM6DSV32X_1Hz875;
10651 break;
10652 }
10653
10654 return ret;
10655 }
10656
10657 /**
10658 * @brief Wakeup and activity/inactivity threshold.[set]
10659 *
10660 * @param ctx read / write interface definitions
10661 * @param val Wakeup and activity/inactivity threshold.
10662 * @retval interface status (MANDATORY: return 0 -> no Error)
10663 *
10664 */
lsm6dsv32x_act_thresholds_set(const stmdev_ctx_t * ctx,lsm6dsv32x_act_thresholds_t * val)10665 int32_t lsm6dsv32x_act_thresholds_set(const stmdev_ctx_t *ctx,
10666 lsm6dsv32x_act_thresholds_t *val)
10667 {
10668 lsm6dsv32x_inactivity_ths_t inactivity_ths;
10669 lsm6dsv32x_inactivity_dur_t inactivity_dur;
10670 lsm6dsv32x_wake_up_ths_t wake_up_ths;
10671 lsm6dsv32x_wake_up_dur_t wake_up_dur;
10672 int32_t ret;
10673
10674 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10675 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
10676 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
10677 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
10678 if (ret != 0)
10679 {
10680 return ret;
10681 }
10682
10683 inactivity_dur.wu_inact_ths_w = val->inactivity_cfg.wu_inact_ths_w;
10684 inactivity_dur.xl_inact_odr = val->inactivity_cfg.xl_inact_odr;
10685 inactivity_dur.inact_dur = val->inactivity_cfg.inact_dur;
10686
10687 inactivity_ths.inact_ths = val->inactivity_ths;
10688 wake_up_ths.wk_ths = val->threshold;
10689 wake_up_dur.wake_dur = val->duration;
10690
10691 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10692 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
10693 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
10694 ret += lsm6dsv32x_write_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
10695
10696 return ret;
10697 }
10698
10699 /**
10700 * @brief Wakeup and activity/inactivity threshold.[get]
10701 *
10702 * @param ctx read / write interface definitions
10703 * @param val Wakeup and activity/inactivity threshold.
10704 * @retval interface status (MANDATORY: return 0 -> no Error)
10705 *
10706 */
lsm6dsv32x_act_thresholds_get(const stmdev_ctx_t * ctx,lsm6dsv32x_act_thresholds_t * val)10707 int32_t lsm6dsv32x_act_thresholds_get(const stmdev_ctx_t *ctx,
10708 lsm6dsv32x_act_thresholds_t *val)
10709 {
10710 lsm6dsv32x_inactivity_dur_t inactivity_dur;
10711 lsm6dsv32x_inactivity_ths_t inactivity_ths;
10712 lsm6dsv32x_wake_up_ths_t wake_up_ths;
10713 lsm6dsv32x_wake_up_dur_t wake_up_dur;
10714 int32_t ret;
10715
10716 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10717 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
10718 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
10719 ret += lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
10720 if (ret != 0)
10721 {
10722 return ret;
10723 }
10724
10725 val->inactivity_cfg.wu_inact_ths_w = inactivity_dur.wu_inact_ths_w;
10726 val->inactivity_cfg.xl_inact_odr = inactivity_dur.xl_inact_odr;
10727 val->inactivity_cfg.inact_dur = inactivity_dur.inact_dur;
10728
10729 val->inactivity_ths = inactivity_ths.inact_ths;
10730 val->threshold = wake_up_ths.wk_ths;
10731 val->duration = wake_up_dur.wake_dur;
10732
10733 return ret;
10734 }
10735
10736 /**
10737 * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [set]
10738 *
10739 * @param ctx read / write interface definitions
10740 * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time.
10741 * @retval interface status (MANDATORY: return 0 -> no Error)
10742 *
10743 */
lsm6dsv32x_act_wkup_time_windows_set(const stmdev_ctx_t * ctx,lsm6dsv32x_act_wkup_time_windows_t val)10744 int32_t lsm6dsv32x_act_wkup_time_windows_set(const stmdev_ctx_t *ctx,
10745 lsm6dsv32x_act_wkup_time_windows_t val)
10746 {
10747 lsm6dsv32x_wake_up_dur_t wake_up_dur;
10748 int32_t ret;
10749
10750 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
10751 if (ret == 0)
10752 {
10753 wake_up_dur.wake_dur = val.shock;
10754 wake_up_dur.sleep_dur = val.quiet;
10755 ret = lsm6dsv32x_write_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
10756 }
10757
10758 return ret;
10759 }
10760
10761 /**
10762 * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [get]
10763 *
10764 * @param ctx read / write interface definitions
10765 * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time.
10766 * @retval interface status (MANDATORY: return 0 -> no Error)
10767 *
10768 */
lsm6dsv32x_act_wkup_time_windows_get(const stmdev_ctx_t * ctx,lsm6dsv32x_act_wkup_time_windows_t * val)10769 int32_t lsm6dsv32x_act_wkup_time_windows_get(const stmdev_ctx_t *ctx,
10770 lsm6dsv32x_act_wkup_time_windows_t *val)
10771 {
10772 lsm6dsv32x_wake_up_dur_t wake_up_dur;
10773 int32_t ret;
10774
10775 ret = lsm6dsv32x_read_reg(ctx, LSM6DSV32X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
10776 if (ret != 0)
10777 {
10778 return ret;
10779 }
10780
10781 val->shock = wake_up_dur.wake_dur;
10782 val->quiet = wake_up_dur.sleep_dur;
10783
10784 return ret;
10785 }
10786
10787 /**
10788 * @}
10789 *
10790 */
10791
