1 /**
2 ******************************************************************************
3 * @file lsm6dsv16x_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSV16X driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dsv16x_reg.h"
21
22 /**
23 * @defgroup LSM6DSV16X
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dsv16x enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup Interfaces functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx communication interface handler.(ptr)
43 * @param reg first register address to read.
44 * @param data buffer for data read.(ptr)
45 * @param len number of consecutive register to read.
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6dsv16x_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dsv16x_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx communication interface handler.(ptr)
69 * @param reg first register address to write.
70 * @param data the buffer contains data to be written.(ptr)
71 * @param len number of consecutive register to write.
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lsm6dsv16x_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lsm6dsv16x_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup Private functions
98 * @brief Section collect all the utility functions needed by APIs.
99 * @{
100 *
101 */
102
bytecpy(uint8_t * target,uint8_t * source)103 static void bytecpy(uint8_t *target, uint8_t *source)
104 {
105 if ((target != NULL) && (source != NULL))
106 {
107 *target = *source;
108 }
109 }
110
111 /**
112 * @}
113 *
114 */
115
116 /**
117 * @defgroup Sensitivity
118 * @brief These functions convert raw-data into engineering units.
119 * @{
120 *
121 */
lsm6dsv16x_from_sflp_to_mg(int16_t lsb)122 float_t lsm6dsv16x_from_sflp_to_mg(int16_t lsb)
123 {
124 return ((float_t)lsb) * 0.061f;
125 }
126
lsm6dsv16x_from_fs2_to_mg(int16_t lsb)127 float_t lsm6dsv16x_from_fs2_to_mg(int16_t lsb)
128 {
129 return ((float_t)lsb) * 0.061f;
130 }
131
lsm6dsv16x_from_fs4_to_mg(int16_t lsb)132 float_t lsm6dsv16x_from_fs4_to_mg(int16_t lsb)
133 {
134 return ((float_t)lsb) * 0.122f;
135 }
136
lsm6dsv16x_from_fs8_to_mg(int16_t lsb)137 float_t lsm6dsv16x_from_fs8_to_mg(int16_t lsb)
138 {
139 return ((float_t)lsb) * 0.244f;
140 }
141
lsm6dsv16x_from_fs16_to_mg(int16_t lsb)142 float_t lsm6dsv16x_from_fs16_to_mg(int16_t lsb)
143 {
144 return ((float_t)lsb) * 0.488f;
145 }
146
lsm6dsv16x_from_fs125_to_mdps(int16_t lsb)147 float_t lsm6dsv16x_from_fs125_to_mdps(int16_t lsb)
148 {
149 return ((float_t)lsb) * 4.375f;
150 }
151
lsm6dsv16x_from_fs250_to_mdps(int16_t lsb)152 float_t lsm6dsv16x_from_fs250_to_mdps(int16_t lsb)
153 {
154 return ((float_t)lsb) * 8.750f;
155 }
156
lsm6dsv16x_from_fs500_to_mdps(int16_t lsb)157 float_t lsm6dsv16x_from_fs500_to_mdps(int16_t lsb)
158 {
159 return ((float_t)lsb) * 17.50f;
160 }
161
lsm6dsv16x_from_fs1000_to_mdps(int16_t lsb)162 float_t lsm6dsv16x_from_fs1000_to_mdps(int16_t lsb)
163 {
164 return ((float_t)lsb) * 35.0f;
165 }
166
lsm6dsv16x_from_fs2000_to_mdps(int16_t lsb)167 float_t lsm6dsv16x_from_fs2000_to_mdps(int16_t lsb)
168 {
169 return ((float_t)lsb) * 70.0f;
170 }
171
lsm6dsv16x_from_fs4000_to_mdps(int16_t lsb)172 float_t lsm6dsv16x_from_fs4000_to_mdps(int16_t lsb)
173 {
174 return ((float_t)lsb) * 140.0f;
175 }
176
lsm6dsv16x_from_lsb_to_celsius(int16_t lsb)177 float_t lsm6dsv16x_from_lsb_to_celsius(int16_t lsb)
178 {
179 return (((float_t)lsb / 256.0f) + 25.0f);
180 }
181
lsm6dsv16x_from_lsb_to_nsec(uint32_t lsb)182 float_t lsm6dsv16x_from_lsb_to_nsec(uint32_t lsb)
183 {
184 return ((float_t)lsb * 21750.0f);
185 }
186
lsm6dsv16x_from_lsb_to_mv(int16_t lsb)187 float_t lsm6dsv16x_from_lsb_to_mv(int16_t lsb)
188 {
189 return ((float_t)lsb) / 78.0f;
190 }
191
192 /*
193 * Original conversion routines taken from: https://github.com/numpy/numpy
194 *
195 * Converts from half-precision (16-bit) float number to single precision (32-bit).
196 *
197 * uint32_t static uint32_t ToFloatBits(uint16_t h);
198 * Released under BSD-3-Clause License
199 */
ToFloatBits(uint16_t h)200 static uint32_t ToFloatBits(uint16_t h)
201 {
202 uint16_t h_exp = (h & 0x7c00u);
203 uint32_t f_sgn = ((uint32_t)h & 0x8000u) << 16;
204 switch (h_exp)
205 {
206 case 0x0000u: // 0 or subnormal
207 {
208 uint16_t h_sig = (h & 0x03ffu);
209 // Signed zero
210 if (h_sig == 0)
211 {
212 return f_sgn;
213 }
214 // Subnormal
215 h_sig <<= 1;
216 while ((h_sig & 0x0400u) == 0)
217 {
218 h_sig <<= 1;
219 h_exp++;
220 }
221 uint32_t f_exp = ((uint32_t)(127 - 15 - h_exp)) << 23;
222 uint32_t f_sig = ((uint32_t)(h_sig & 0x03ffu)) << 13;
223 return f_sgn + f_exp + f_sig;
224 }
225 case 0x7c00u: // inf or NaN
226 // All-ones exponent and a copy of the significand
227 return f_sgn + 0x7f800000u + (((uint32_t)(h & 0x03ffu)) << 13);
228 default: // normalized
229 // Just need to adjust the exponent and shift
230 return f_sgn + (((uint32_t)(h & 0x7fffu) + 0x1c000u) << 13);
231 }
232 }
233
234 /**
235 * @brief Convert from 16-bit to 32-bit float number
236 *
237 * @param val Batching in FIFO buffer of SFLP values.
238 * @retval interface status (MANDATORY: return 0 -> no Error)
239 *
240 */
lsm6dsv16x_from_f16_to_f32(uint16_t val)241 uint32_t lsm6dsv16x_from_f16_to_f32(uint16_t val)
242 {
243 return ToFloatBits(val);
244 }
245
246 /**
247 * @}
248 *
249 */
250
251 /**
252 * @defgroup Accelerometer user offset correction
253 * @brief This section groups all the functions concerning the
254 * usage of Accelerometer user offset correction
255 * @{
256 *
257 */
258
259 /**
260 * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[set]
261 *
262 * @param ctx read / write interface definitions
263 * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path.
264 * @retval interface status (MANDATORY: return 0 -> no Error)
265 *
266 */
lsm6dsv16x_xl_offset_on_out_set(const stmdev_ctx_t * ctx,uint8_t val)267 int32_t lsm6dsv16x_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val)
268 {
269 lsm6dsv16x_ctrl9_t ctrl9;
270 int32_t ret;
271
272 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
273 if (ret == 0)
274 {
275 ctrl9.usr_off_on_out = val;
276 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
277 }
278
279 return ret;
280 }
281
282 /**
283 * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[get]
284 *
285 * @param ctx read / write interface definitions
286 * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path.
287 * @retval interface status (MANDATORY: return 0 -> no Error)
288 *
289 */
lsm6dsv16x_xl_offset_on_out_get(const stmdev_ctx_t * ctx,uint8_t * val)290 int32_t lsm6dsv16x_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val)
291 {
292 lsm6dsv16x_ctrl9_t ctrl9;
293 int32_t ret;
294
295 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
296 *val = ctrl9.usr_off_on_out;
297
298 return ret;
299 }
300
301 /**
302 * @brief Accelerometer user offset correction values in mg.[set]
303 *
304 * @param ctx read / write interface definitions
305 * @param val Accelerometer user offset correction values in mg.
306 * @retval interface status (MANDATORY: return 0 -> no Error)
307 *
308 */
lsm6dsv16x_xl_offset_mg_set(const stmdev_ctx_t * ctx,lsm6dsv16x_xl_offset_mg_t val)309 int32_t lsm6dsv16x_xl_offset_mg_set(const stmdev_ctx_t *ctx,
310 lsm6dsv16x_xl_offset_mg_t val)
311 {
312 lsm6dsv16x_z_ofs_usr_t z_ofs_usr;
313 lsm6dsv16x_y_ofs_usr_t y_ofs_usr;
314 lsm6dsv16x_x_ofs_usr_t x_ofs_usr;
315 lsm6dsv16x_ctrl9_t ctrl9;
316 int32_t ret;
317 float_t tmp;
318
319 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
320 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
321 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
322 if (ret != 0)
323 {
324 return ret;
325 }
326
327
328 if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) &&
329 (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) &&
330 (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f)))
331 {
332 ctrl9.usr_off_w = 0;
333
334 tmp = val.z_mg / 0.0078125f;
335 z_ofs_usr.z_ofs_usr = (uint8_t)tmp;
336
337 tmp = val.y_mg / 0.0078125f;
338 y_ofs_usr.y_ofs_usr = (uint8_t)tmp;
339
340 tmp = val.x_mg / 0.0078125f;
341 x_ofs_usr.x_ofs_usr = (uint8_t)tmp;
342 }
343 else if ((val.x_mg < (0.125f * 127.0f)) && (val.x_mg > (0.125f * -127.0f)) &&
344 (val.y_mg < (0.125f * 127.0f)) && (val.y_mg > (0.125f * -127.0f)) &&
345 (val.z_mg < (0.125f * 127.0f)) && (val.z_mg > (0.125f * -127.0f)))
346 {
347 ctrl9.usr_off_w = 1;
348
349 tmp = val.z_mg / 0.125f;
350 z_ofs_usr.z_ofs_usr = (uint8_t)tmp;
351
352 tmp = val.y_mg / 0.125f;
353 y_ofs_usr.y_ofs_usr = (uint8_t)tmp;
354
355 tmp = val.x_mg / 0.125f;
356 x_ofs_usr.x_ofs_usr = (uint8_t)tmp;
357 }
358 else // out of limit
359 {
360 ctrl9.usr_off_w = 1;
361 z_ofs_usr.z_ofs_usr = 0xFFU;
362 y_ofs_usr.y_ofs_usr = 0xFFU;
363 x_ofs_usr.x_ofs_usr = 0xFFU;
364 }
365
366 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
367 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
368 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
369 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
370
371 return ret;
372 }
373
374 /**
375 * @brief Accelerometer user offset correction values in mg.[get]
376 *
377 * @param ctx read / write interface definitions
378 * @param val Accelerometer user offset correction values in mg.
379 * @retval interface status (MANDATORY: return 0 -> no Error)
380 *
381 */
lsm6dsv16x_xl_offset_mg_get(const stmdev_ctx_t * ctx,lsm6dsv16x_xl_offset_mg_t * val)382 int32_t lsm6dsv16x_xl_offset_mg_get(const stmdev_ctx_t *ctx,
383 lsm6dsv16x_xl_offset_mg_t *val)
384 {
385 lsm6dsv16x_z_ofs_usr_t z_ofs_usr;
386 lsm6dsv16x_y_ofs_usr_t y_ofs_usr;
387 lsm6dsv16x_x_ofs_usr_t x_ofs_usr;
388 lsm6dsv16x_ctrl9_t ctrl9;
389 int32_t ret;
390
391 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
392 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
393 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
394 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
395 if (ret != 0)
396 {
397 return ret;
398 }
399
400 if (ctrl9.usr_off_w == PROPERTY_DISABLE)
401 {
402 val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.0078125f);
403 val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.0078125f);
404 val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.0078125f);
405 }
406 else
407 {
408 val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.125f);
409 val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.125f);
410 val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.125f);
411 }
412
413 return ret;
414 }
415
416 /**
417 * @}
418 *
419 */
420
421 /**
422 * @brief Reset of the device.[set]
423 *
424 * @param ctx read / write interface definitions
425 * @param val Reset of the device.
426 * @retval interface status (MANDATORY: return 0 -> no Error)
427 *
428 */
lsm6dsv16x_reset_set(const stmdev_ctx_t * ctx,lsm6dsv16x_reset_t val)429 int32_t lsm6dsv16x_reset_set(const stmdev_ctx_t *ctx, lsm6dsv16x_reset_t val)
430 {
431 lsm6dsv16x_func_cfg_access_t func_cfg_access;
432 lsm6dsv16x_ctrl3_t ctrl3;
433 int32_t ret;
434
435 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1);
436 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
437 if (ret != 0)
438 {
439 return ret;
440 }
441
442 ctrl3.boot = ((uint8_t)val & 0x04U) >> 2;
443 ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1;
444 func_cfg_access.sw_por = (uint8_t)val & 0x01U;
445
446 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1);
447 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
448
449 return ret;
450 }
451
452 /**
453 * @brief Global reset of the device.[get]
454 *
455 * @param ctx read / write interface definitions
456 * @param val Global reset of the device.
457 * @retval interface status (MANDATORY: return 0 -> no Error)
458 *
459 */
lsm6dsv16x_reset_get(const stmdev_ctx_t * ctx,lsm6dsv16x_reset_t * val)460 int32_t lsm6dsv16x_reset_get(const stmdev_ctx_t *ctx, lsm6dsv16x_reset_t *val)
461 {
462 lsm6dsv16x_func_cfg_access_t func_cfg_access;
463 lsm6dsv16x_ctrl3_t ctrl3;
464 int32_t ret;
465
466 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1);
467 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
468 if (ret != 0)
469 {
470 return ret;
471 }
472
473 switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por)
474 {
475 case LSM6DSV16X_READY:
476 *val = LSM6DSV16X_READY;
477 break;
478
479 case LSM6DSV16X_GLOBAL_RST:
480 *val = LSM6DSV16X_GLOBAL_RST;
481 break;
482
483 case LSM6DSV16X_RESTORE_CAL_PARAM:
484 *val = LSM6DSV16X_RESTORE_CAL_PARAM;
485 break;
486
487 case LSM6DSV16X_RESTORE_CTRL_REGS:
488 *val = LSM6DSV16X_RESTORE_CTRL_REGS;
489 break;
490
491 default:
492 *val = LSM6DSV16X_GLOBAL_RST;
493 break;
494 }
495
496 return ret;
497 }
498
499 /**
500 * @brief Change memory bank.[set]
501 *
502 * @param ctx read / write interface definitions
503 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK,
504 * @retval interface status (MANDATORY: return 0 -> no Error)
505 *
506 */
lsm6dsv16x_mem_bank_set(const stmdev_ctx_t * ctx,lsm6dsv16x_mem_bank_t val)507 int32_t lsm6dsv16x_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t val)
508 {
509 lsm6dsv16x_func_cfg_access_t func_cfg_access;
510 int32_t ret;
511
512 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
513 if (ret != 0)
514 {
515 return ret;
516 }
517
518 func_cfg_access.shub_reg_access = ((uint8_t)val & 0x02U) >> 1;
519 func_cfg_access.emb_func_reg_access = (uint8_t)val & 0x01U;
520 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
521
522 return ret;
523 }
524
525 /**
526 * @brief Change memory bank.[get]
527 *
528 * @param ctx read / write interface definitions
529 * @param val MAIN_MEM_BANK, SENSOR_HUB_MEM_BANK, EMBED_FUNC_MEM_BANK,
530 * @retval interface status (MANDATORY: return 0 -> no Error)
531 *
532 */
lsm6dsv16x_mem_bank_get(const stmdev_ctx_t * ctx,lsm6dsv16x_mem_bank_t * val)533 int32_t lsm6dsv16x_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsv16x_mem_bank_t *val)
534 {
535 lsm6dsv16x_func_cfg_access_t func_cfg_access;
536 int32_t ret;
537
538 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
539 if (ret != 0)
540 {
541 return ret;
542 }
543
544 switch ((func_cfg_access.shub_reg_access << 1) + func_cfg_access.emb_func_reg_access)
545 {
546 case LSM6DSV16X_MAIN_MEM_BANK:
547 *val = LSM6DSV16X_MAIN_MEM_BANK;
548 break;
549
550 case LSM6DSV16X_EMBED_FUNC_MEM_BANK:
551 *val = LSM6DSV16X_EMBED_FUNC_MEM_BANK;
552 break;
553
554 case LSM6DSV16X_SENSOR_HUB_MEM_BANK:
555 *val = LSM6DSV16X_SENSOR_HUB_MEM_BANK;
556 break;
557
558 default:
559 *val = LSM6DSV16X_MAIN_MEM_BANK;
560 break;
561 }
562
563 return ret;
564 }
565
566 /**
567 * @brief Device ID.[get] THis function works also for OIS
568 * (WHO_AM_I and SPI2_WHO_AM_I have same address)
569 *
570 * @param ctx read / write interface definitions
571 * @param val Device ID.
572 * @retval interface status (MANDATORY: return 0 -> no Error)
573 *
574 */
lsm6dsv16x_device_id_get(const stmdev_ctx_t * ctx,uint8_t * val)575 int32_t lsm6dsv16x_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val)
576 {
577 int32_t ret;
578
579 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WHO_AM_I, val, 1);
580
581 return ret;
582 }
583
584 /**
585 * @brief Accelerometer output data rate (ODR) selection.[set]
586 *
587 * @param ctx read / write interface definitions
588 * @param val lsm6dsv16x_data_rate_t enum
589 * @retval interface status (MANDATORY: return 0 -> no Error)
590 *
591 */
lsm6dsv16x_xl_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv16x_data_rate_t val)592 int32_t lsm6dsv16x_xl_data_rate_set(const stmdev_ctx_t *ctx,
593 lsm6dsv16x_data_rate_t val)
594 {
595 lsm6dsv16x_ctrl1_t ctrl1;
596 lsm6dsv16x_haodr_cfg_t haodr;
597 uint8_t sel;
598 int32_t ret;
599
600 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1);
601 if (ret != 0)
602 {
603 return ret;
604 }
605
606 ctrl1.odr_xl = (uint8_t)val & 0x0Fu;
607 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1);
608 if (ret != 0)
609 {
610 return ret;
611 }
612
613 sel = ((uint8_t)val >> 4) & 0xFU;
614 if (sel != 0U)
615 {
616 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1);
617 haodr.haodr_sel = sel;
618 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1);
619 }
620
621 return ret;
622 }
623
624 /**
625 * @brief Accelerometer output data rate (ODR) selection.[get]
626 *
627 * @param ctx read / write interface definitions
628 * @param val lsm6dsv16x_data_rate_t enum
629 * @retval interface status (MANDATORY: return 0 -> no Error)
630 *
631 */
lsm6dsv16x_xl_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv16x_data_rate_t * val)632 int32_t lsm6dsv16x_xl_data_rate_get(const stmdev_ctx_t *ctx,
633 lsm6dsv16x_data_rate_t *val)
634 {
635 lsm6dsv16x_ctrl1_t ctrl1;
636 lsm6dsv16x_haodr_cfg_t haodr;
637 uint8_t sel;
638 int32_t ret;
639
640 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1);
641 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1);
642 if (ret != 0)
643 {
644 return ret;
645 }
646
647 sel = haodr.haodr_sel;
648
649 switch (ctrl1.odr_xl)
650 {
651 case LSM6DSV16X_ODR_OFF:
652 *val = LSM6DSV16X_ODR_OFF;
653 break;
654
655 case LSM6DSV16X_ODR_AT_1Hz875:
656 *val = LSM6DSV16X_ODR_AT_1Hz875;
657 break;
658
659 case LSM6DSV16X_ODR_AT_7Hz5:
660 *val = LSM6DSV16X_ODR_AT_7Hz5;
661 break;
662
663 case LSM6DSV16X_ODR_AT_15Hz:
664 switch (sel)
665 {
666 default:
667 case 0:
668 *val = LSM6DSV16X_ODR_AT_15Hz;
669 break;
670 case 1:
671 *val = LSM6DSV16X_ODR_HA01_AT_15Hz625;
672 break;
673 case 2:
674 *val = LSM6DSV16X_ODR_HA02_AT_12Hz5;
675 break;
676 }
677 break;
678
679 case LSM6DSV16X_ODR_AT_30Hz:
680 switch (sel)
681 {
682 default:
683 case 0:
684 *val = LSM6DSV16X_ODR_AT_30Hz;
685 break;
686 case 1:
687 *val = LSM6DSV16X_ODR_HA01_AT_31Hz25;
688 break;
689 case 2:
690 *val = LSM6DSV16X_ODR_HA02_AT_25Hz;
691 break;
692 }
693 break;
694
695 case LSM6DSV16X_ODR_AT_60Hz:
696 switch (sel)
697 {
698 default:
699 case 0:
700 *val = LSM6DSV16X_ODR_AT_60Hz;
701 break;
702 case 1:
703 *val = LSM6DSV16X_ODR_HA01_AT_62Hz5;
704 break;
705 case 2:
706 *val = LSM6DSV16X_ODR_HA02_AT_50Hz;
707 break;
708 }
709 break;
710
711 case LSM6DSV16X_ODR_AT_120Hz:
712 switch (sel)
713 {
714 default:
715 case 0:
716 *val = LSM6DSV16X_ODR_AT_120Hz;
717 break;
718 case 1:
719 *val = LSM6DSV16X_ODR_HA01_AT_125Hz;
720 break;
721 case 2:
722 *val = LSM6DSV16X_ODR_HA02_AT_100Hz;
723 break;
724 }
725 break;
726
727 case LSM6DSV16X_ODR_AT_240Hz:
728 switch (sel)
729 {
730 default:
731 case 0:
732 *val = LSM6DSV16X_ODR_AT_240Hz;
733 break;
734 case 1:
735 *val = LSM6DSV16X_ODR_HA01_AT_250Hz;
736 break;
737 case 2:
738 *val = LSM6DSV16X_ODR_HA02_AT_200Hz;
739 break;
740 }
741 break;
742
743 case LSM6DSV16X_ODR_AT_480Hz:
744 switch (sel)
745 {
746 default:
747 case 0:
748 *val = LSM6DSV16X_ODR_AT_480Hz;
749 break;
750 case 1:
751 *val = LSM6DSV16X_ODR_HA01_AT_500Hz;
752 break;
753 case 2:
754 *val = LSM6DSV16X_ODR_HA02_AT_400Hz;
755 break;
756 }
757 break;
758
759 case LSM6DSV16X_ODR_AT_960Hz:
760 switch (sel)
761 {
762 default:
763 case 0:
764 *val = LSM6DSV16X_ODR_AT_960Hz;
765 break;
766 case 1:
767 *val = LSM6DSV16X_ODR_HA01_AT_1000Hz;
768 break;
769 case 2:
770 *val = LSM6DSV16X_ODR_HA02_AT_800Hz;
771 break;
772 }
773 break;
774
775 case LSM6DSV16X_ODR_AT_1920Hz:
776 switch (sel)
777 {
778 default:
779 case 0:
780 *val = LSM6DSV16X_ODR_AT_1920Hz;
781 break;
782 case 1:
783 *val = LSM6DSV16X_ODR_HA01_AT_2000Hz;
784 break;
785 case 2:
786 *val = LSM6DSV16X_ODR_HA02_AT_1600Hz;
787 break;
788 }
789 break;
790
791 case LSM6DSV16X_ODR_AT_3840Hz:
792 switch (sel)
793 {
794 default:
795 case 0:
796 *val = LSM6DSV16X_ODR_AT_3840Hz;
797 break;
798 case 1:
799 *val = LSM6DSV16X_ODR_HA01_AT_4000Hz;
800 break;
801 case 2:
802 *val = LSM6DSV16X_ODR_HA02_AT_3200Hz;
803 break;
804 }
805 break;
806
807 case LSM6DSV16X_ODR_AT_7680Hz:
808 switch (sel)
809 {
810 default:
811 case 0:
812 *val = LSM6DSV16X_ODR_AT_7680Hz;
813 break;
814 case 1:
815 *val = LSM6DSV16X_ODR_HA01_AT_8000Hz;
816 break;
817 case 2:
818 *val = LSM6DSV16X_ODR_HA02_AT_6400Hz;
819 break;
820 }
821 break;
822
823 default:
824 *val = LSM6DSV16X_ODR_OFF;
825 break;
826 }
827
828 return ret;
829 }
830
831 /**
832 * @brief Accelerometer operating mode selection.[set]
833 *
834 * @param ctx read / write interface definitions
835 * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURACY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD,
836 * @retval interface status (MANDATORY: return 0 -> no Error)
837 *
838 */
lsm6dsv16x_xl_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16x_xl_mode_t val)839 int32_t lsm6dsv16x_xl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t val)
840 {
841 lsm6dsv16x_ctrl1_t ctrl1;
842 int32_t ret;
843
844 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1);
845
846 if (ret == 0)
847 {
848 ctrl1.op_mode_xl = (uint8_t)val & 0x07U;
849 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1);
850 }
851
852 return ret;
853 }
854
855 /**
856 * @brief Accelerometer operating mode selection.[get]
857 *
858 * @param ctx read / write interface definitions
859 * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURACY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD,
860 * @retval interface status (MANDATORY: return 0 -> no Error)
861 *
862 */
lsm6dsv16x_xl_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16x_xl_mode_t * val)863 int32_t lsm6dsv16x_xl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_xl_mode_t *val)
864 {
865 lsm6dsv16x_ctrl1_t ctrl1;
866 int32_t ret;
867
868 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL1, (uint8_t *)&ctrl1, 1);
869 if (ret != 0)
870 {
871 return ret;
872 }
873
874 switch (ctrl1.op_mode_xl)
875 {
876 case LSM6DSV16X_XL_HIGH_PERFORMANCE_MD:
877 *val = LSM6DSV16X_XL_HIGH_PERFORMANCE_MD;
878 break;
879
880 case LSM6DSV16X_XL_HIGH_ACCURACY_ODR_MD:
881 *val = LSM6DSV16X_XL_HIGH_ACCURACY_ODR_MD;
882 break;
883
884 case LSM6DSV16X_XL_ODR_TRIGGERED_MD:
885 *val = LSM6DSV16X_XL_ODR_TRIGGERED_MD;
886 break;
887
888 case LSM6DSV16X_XL_LOW_POWER_2_AVG_MD:
889 *val = LSM6DSV16X_XL_LOW_POWER_2_AVG_MD;
890 break;
891
892 case LSM6DSV16X_XL_LOW_POWER_4_AVG_MD:
893 *val = LSM6DSV16X_XL_LOW_POWER_4_AVG_MD;
894 break;
895
896 case LSM6DSV16X_XL_LOW_POWER_8_AVG_MD:
897 *val = LSM6DSV16X_XL_LOW_POWER_8_AVG_MD;
898 break;
899
900 case LSM6DSV16X_XL_NORMAL_MD:
901 *val = LSM6DSV16X_XL_NORMAL_MD;
902 break;
903
904 default:
905 *val = LSM6DSV16X_XL_HIGH_PERFORMANCE_MD;
906 break;
907 }
908
909 return ret;
910 }
911
912 /**
913 * @brief Gyroscope output data rate (ODR) selection.[set]
914 *
915 * @param ctx read / write interface definitions
916 * @param val lsm6dsv16x_data_rate_t enum
917 * @retval interface status (MANDATORY: return 0 -> no Error)
918 *
919 */
lsm6dsv16x_gy_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv16x_data_rate_t val)920 int32_t lsm6dsv16x_gy_data_rate_set(const stmdev_ctx_t *ctx,
921 lsm6dsv16x_data_rate_t val)
922 {
923 lsm6dsv16x_ctrl2_t ctrl2;
924 lsm6dsv16x_haodr_cfg_t haodr;
925 uint8_t sel;
926 int32_t ret;
927
928 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1);
929
930 ctrl2.odr_g = (uint8_t)val & 0x0Fu;
931 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1);
932 if (ret != 0)
933 {
934 return ret;
935 }
936
937 sel = ((uint8_t)val >> 4) & 0xFU;
938 if (sel != 0U)
939 {
940 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1);
941 haodr.haodr_sel = sel;
942 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1);
943 }
944
945 return ret;
946 }
947
948 /**
949 * @brief Gyroscope output data rate (ODR) selection.[get]
950 *
951 * @param ctx read / write interface definitions
952 * @param val lsm6dsv16x_data_rate_t enum
953 * @retval interface status (MANDATORY: return 0 -> no Error)
954 *
955 */
lsm6dsv16x_gy_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv16x_data_rate_t * val)956 int32_t lsm6dsv16x_gy_data_rate_get(const stmdev_ctx_t *ctx,
957 lsm6dsv16x_data_rate_t *val)
958 {
959 lsm6dsv16x_ctrl2_t ctrl2;
960 lsm6dsv16x_haodr_cfg_t haodr;
961 uint8_t sel;
962 int32_t ret;
963
964 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1);
965 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_HAODR_CFG, (uint8_t *)&haodr, 1);
966 if (ret != 0)
967 {
968 return ret;
969 }
970
971 sel = haodr.haodr_sel;
972
973 switch (ctrl2.odr_g)
974 {
975 case LSM6DSV16X_ODR_OFF:
976 *val = LSM6DSV16X_ODR_OFF;
977 break;
978
979 case LSM6DSV16X_ODR_AT_1Hz875:
980 *val = LSM6DSV16X_ODR_AT_1Hz875;
981 break;
982
983 case LSM6DSV16X_ODR_AT_7Hz5:
984 *val = LSM6DSV16X_ODR_AT_7Hz5;
985 break;
986
987 case LSM6DSV16X_ODR_AT_15Hz:
988 switch (sel)
989 {
990 default:
991 case 0:
992 *val = LSM6DSV16X_ODR_AT_15Hz;
993 break;
994 case 1:
995 *val = LSM6DSV16X_ODR_HA01_AT_15Hz625;
996 break;
997 case 2:
998 *val = LSM6DSV16X_ODR_HA02_AT_12Hz5;
999 break;
1000 }
1001 break;
1002
1003 case LSM6DSV16X_ODR_AT_30Hz:
1004 switch (sel)
1005 {
1006 default:
1007 case 0:
1008 *val = LSM6DSV16X_ODR_AT_30Hz;
1009 break;
1010 case 1:
1011 *val = LSM6DSV16X_ODR_HA01_AT_31Hz25;
1012 break;
1013 case 2:
1014 *val = LSM6DSV16X_ODR_HA02_AT_25Hz;
1015 break;
1016 }
1017 break;
1018
1019 case LSM6DSV16X_ODR_AT_60Hz:
1020 switch (sel)
1021 {
1022 default:
1023 case 0:
1024 *val = LSM6DSV16X_ODR_AT_60Hz;
1025 break;
1026 case 1:
1027 *val = LSM6DSV16X_ODR_HA01_AT_62Hz5;
1028 break;
1029 case 2:
1030 *val = LSM6DSV16X_ODR_HA02_AT_50Hz;
1031 break;
1032 }
1033 break;
1034
1035 case LSM6DSV16X_ODR_AT_120Hz:
1036 switch (sel)
1037 {
1038 default:
1039 case 0:
1040 *val = LSM6DSV16X_ODR_AT_120Hz;
1041 break;
1042 case 1:
1043 *val = LSM6DSV16X_ODR_HA01_AT_125Hz;
1044 break;
1045 case 2:
1046 *val = LSM6DSV16X_ODR_HA02_AT_100Hz;
1047 break;
1048 }
1049 break;
1050
1051 case LSM6DSV16X_ODR_AT_240Hz:
1052 switch (sel)
1053 {
1054 default:
1055 case 0:
1056 *val = LSM6DSV16X_ODR_AT_240Hz;
1057 break;
1058 case 1:
1059 *val = LSM6DSV16X_ODR_HA01_AT_250Hz;
1060 break;
1061 case 2:
1062 *val = LSM6DSV16X_ODR_HA02_AT_200Hz;
1063 break;
1064 }
1065 break;
1066
1067 case LSM6DSV16X_ODR_AT_480Hz:
1068 switch (sel)
1069 {
1070 default:
1071 case 0:
1072 *val = LSM6DSV16X_ODR_AT_480Hz;
1073 break;
1074 case 1:
1075 *val = LSM6DSV16X_ODR_HA01_AT_500Hz;
1076 break;
1077 case 2:
1078 *val = LSM6DSV16X_ODR_HA02_AT_400Hz;
1079 break;
1080 }
1081 break;
1082
1083 case LSM6DSV16X_ODR_AT_960Hz:
1084 switch (sel)
1085 {
1086 default:
1087 case 0:
1088 *val = LSM6DSV16X_ODR_AT_960Hz;
1089 break;
1090 case 1:
1091 *val = LSM6DSV16X_ODR_HA01_AT_1000Hz;
1092 break;
1093 case 2:
1094 *val = LSM6DSV16X_ODR_HA02_AT_800Hz;
1095 break;
1096 }
1097 break;
1098
1099 case LSM6DSV16X_ODR_AT_1920Hz:
1100 switch (sel)
1101 {
1102 default:
1103 case 0:
1104 *val = LSM6DSV16X_ODR_AT_1920Hz;
1105 break;
1106 case 1:
1107 *val = LSM6DSV16X_ODR_HA01_AT_2000Hz;
1108 break;
1109 case 2:
1110 *val = LSM6DSV16X_ODR_HA02_AT_1600Hz;
1111 break;
1112 }
1113 break;
1114
1115 case LSM6DSV16X_ODR_AT_3840Hz:
1116 switch (sel)
1117 {
1118 default:
1119 case 0:
1120 *val = LSM6DSV16X_ODR_AT_3840Hz;
1121 break;
1122 case 1:
1123 *val = LSM6DSV16X_ODR_HA01_AT_4000Hz;
1124 break;
1125 case 2:
1126 *val = LSM6DSV16X_ODR_HA02_AT_3200Hz;
1127 break;
1128 }
1129 break;
1130
1131 case LSM6DSV16X_ODR_AT_7680Hz:
1132 switch (sel)
1133 {
1134 default:
1135 case 0:
1136 *val = LSM6DSV16X_ODR_AT_7680Hz;
1137 break;
1138 case 1:
1139 *val = LSM6DSV16X_ODR_HA01_AT_8000Hz;
1140 break;
1141 case 2:
1142 *val = LSM6DSV16X_ODR_HA02_AT_6400Hz;
1143 break;
1144 }
1145 break;
1146
1147 default:
1148 *val = LSM6DSV16X_ODR_OFF;
1149 break;
1150 }
1151
1152 return ret;
1153 }
1154
1155 /**
1156 * @brief Gyroscope operating mode selection.[set]
1157 *
1158 * @param ctx read / write interface definitions
1159 * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURACY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD,
1160 * @retval interface status (MANDATORY: return 0 -> no Error)
1161 *
1162 */
lsm6dsv16x_gy_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16x_gy_mode_t val)1163 int32_t lsm6dsv16x_gy_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t val)
1164 {
1165 lsm6dsv16x_ctrl2_t ctrl2;
1166 int32_t ret;
1167
1168 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1);
1169 if (ret == 0)
1170 {
1171 ctrl2.op_mode_g = (uint8_t)val & 0x07U;
1172 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1);
1173 }
1174
1175 return ret;
1176 }
1177
1178 /**
1179 * @brief Gyroscope operating mode selection.[get]
1180 *
1181 * @param ctx read / write interface definitions
1182 * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURACY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD,
1183 * @retval interface status (MANDATORY: return 0 -> no Error)
1184 *
1185 */
lsm6dsv16x_gy_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16x_gy_mode_t * val)1186 int32_t lsm6dsv16x_gy_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_gy_mode_t *val)
1187 {
1188 lsm6dsv16x_ctrl2_t ctrl2;
1189 int32_t ret;
1190
1191 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL2, (uint8_t *)&ctrl2, 1);
1192 if (ret != 0)
1193 {
1194 return ret;
1195 }
1196
1197 switch (ctrl2.op_mode_g)
1198 {
1199 case LSM6DSV16X_GY_HIGH_PERFORMANCE_MD:
1200 *val = LSM6DSV16X_GY_HIGH_PERFORMANCE_MD;
1201 break;
1202
1203 case LSM6DSV16X_GY_HIGH_ACCURACY_ODR_MD:
1204 *val = LSM6DSV16X_GY_HIGH_ACCURACY_ODR_MD;
1205 break;
1206
1207 case LSM6DSV16X_GY_SLEEP_MD:
1208 *val = LSM6DSV16X_GY_SLEEP_MD;
1209 break;
1210
1211 case LSM6DSV16X_GY_LOW_POWER_MD:
1212 *val = LSM6DSV16X_GY_LOW_POWER_MD;
1213 break;
1214
1215 default:
1216 *val = LSM6DSV16X_GY_HIGH_PERFORMANCE_MD;
1217 break;
1218 }
1219
1220 return ret;
1221 }
1222
1223 /**
1224 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set]
1225 *
1226 * @param ctx read / write interface definitions
1227 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
1228 * @retval interface status (MANDATORY: return 0 -> no Error)
1229 *
1230 */
lsm6dsv16x_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)1231 int32_t lsm6dsv16x_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
1232 {
1233 lsm6dsv16x_ctrl3_t ctrl3;
1234 int32_t ret;
1235
1236 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1);
1237 if (ret == 0)
1238 {
1239 ctrl3.if_inc = val;
1240 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1);
1241 }
1242
1243 return ret;
1244 }
1245
1246 /**
1247 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get]
1248 *
1249 * @param ctx read / write interface definitions
1250 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
1251 * @retval interface status (MANDATORY: return 0 -> no Error)
1252 *
1253 */
lsm6dsv16x_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)1254 int32_t lsm6dsv16x_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
1255 {
1256 lsm6dsv16x_ctrl3_t ctrl3;
1257 int32_t ret;
1258
1259 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1);
1260 *val = ctrl3.if_inc;
1261
1262 return ret;
1263 }
1264
1265 /**
1266 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set]
1267 *
1268 * @param ctx read / write interface definitions
1269 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
1270 * @retval interface status (MANDATORY: return 0 -> no Error)
1271 *
1272 */
lsm6dsv16x_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)1273 int32_t lsm6dsv16x_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
1274 {
1275 lsm6dsv16x_ctrl3_t ctrl3;
1276 int32_t ret;
1277
1278 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1);
1279
1280 if (ret == 0)
1281 {
1282 ctrl3.bdu = val;
1283 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1);
1284 }
1285
1286 return ret;
1287 }
1288
1289 /**
1290 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get]
1291 *
1292 * @param ctx read / write interface definitions
1293 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
1294 * @retval interface status (MANDATORY: return 0 -> no Error)
1295 *
1296 */
lsm6dsv16x_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)1297 int32_t lsm6dsv16x_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
1298 {
1299 lsm6dsv16x_ctrl3_t ctrl3;
1300 int32_t ret;
1301
1302 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL3, (uint8_t *)&ctrl3, 1);
1303 *val = ctrl3.bdu;
1304
1305 return ret;
1306 }
1307
1308 /**
1309 * @brief Configure ODR trigger. [set]
1310 *
1311 * @param ctx read / write interface definitions
1312 * @param val number of data in the reference period.
1313 * @retval interface status (MANDATORY: return 0 -> no Error)
1314 *
1315 */
lsm6dsv16x_odr_trig_cfg_set(const stmdev_ctx_t * ctx,uint8_t val)1316 int32_t lsm6dsv16x_odr_trig_cfg_set(const stmdev_ctx_t *ctx, uint8_t val)
1317 {
1318 lsm6dsv16x_odr_trig_cfg_t odr_trig;
1319 int32_t ret;
1320
1321 if (val >= 1U && val <= 3U)
1322 {
1323 return -1;
1324 }
1325
1326 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1);
1327
1328 if (ret == 0)
1329 {
1330 odr_trig.odr_trig_nodr = val;
1331 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1);
1332 }
1333
1334 return ret;
1335 }
1336
1337 /**
1338 * @brief Configure ODR trigger. [get]
1339 *
1340 * @param ctx read / write interface definitions
1341 * @param val number of data in the reference period.
1342 * @retval interface status (MANDATORY: return 0 -> no Error)
1343 *
1344 */
lsm6dsv16x_odr_trig_cfg_get(const stmdev_ctx_t * ctx,uint8_t * val)1345 int32_t lsm6dsv16x_odr_trig_cfg_get(const stmdev_ctx_t *ctx, uint8_t *val)
1346 {
1347 lsm6dsv16x_odr_trig_cfg_t odr_trig;
1348 int32_t ret;
1349
1350 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_ODR_TRIG_CFG, (uint8_t *)&odr_trig, 1);
1351 *val = odr_trig.odr_trig_nodr;
1352
1353 return ret;
1354 }
1355
1356 /**
1357 * @brief Enables pulsed data-ready mode (~75 us).[set]
1358 *
1359 * @param ctx read / write interface definitions
1360 * @param val DRDY_LATCHED, DRDY_PULSED,
1361 * @retval interface status (MANDATORY: return 0 -> no Error)
1362 *
1363 */
lsm6dsv16x_data_ready_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16x_data_ready_mode_t val)1364 int32_t lsm6dsv16x_data_ready_mode_set(const stmdev_ctx_t *ctx,
1365 lsm6dsv16x_data_ready_mode_t val)
1366 {
1367 lsm6dsv16x_ctrl4_t ctrl4;
1368 int32_t ret;
1369
1370 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
1371
1372 if (ret == 0)
1373 {
1374 ctrl4.drdy_pulsed = (uint8_t)val & 0x1U;
1375 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
1376 }
1377
1378 return ret;
1379 }
1380
1381 /**
1382 * @brief Enables pulsed data-ready mode (~75 us).[get]
1383 *
1384 * @param ctx read / write interface definitions
1385 * @param val DRDY_LATCHED, DRDY_PULSED,
1386 * @retval interface status (MANDATORY: return 0 -> no Error)
1387 *
1388 */
lsm6dsv16x_data_ready_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16x_data_ready_mode_t * val)1389 int32_t lsm6dsv16x_data_ready_mode_get(const stmdev_ctx_t *ctx,
1390 lsm6dsv16x_data_ready_mode_t *val)
1391 {
1392 lsm6dsv16x_ctrl4_t ctrl4;
1393 int32_t ret;
1394
1395 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
1396
1397 switch (ctrl4.drdy_pulsed)
1398 {
1399 case LSM6DSV16X_DRDY_LATCHED:
1400 *val = LSM6DSV16X_DRDY_LATCHED;
1401 break;
1402
1403 case LSM6DSV16X_DRDY_PULSED:
1404 *val = LSM6DSV16X_DRDY_PULSED;
1405 break;
1406
1407 default:
1408 *val = LSM6DSV16X_DRDY_LATCHED;
1409 break;
1410 }
1411
1412 return ret;
1413 }
1414
1415 /**
1416 * @brief Enables interrupt.[set]
1417 *
1418 * @param ctx read / write interface definitions
1419 * @param val enable/disable, latched/pulsed
1420 * @retval interface status (MANDATORY: return 0 -> no Error)
1421 *
1422 */
lsm6dsv16x_interrupt_enable_set(const stmdev_ctx_t * ctx,lsm6dsv16x_interrupt_mode_t val)1423 int32_t lsm6dsv16x_interrupt_enable_set(const stmdev_ctx_t *ctx,
1424 lsm6dsv16x_interrupt_mode_t val)
1425 {
1426 lsm6dsv16x_tap_cfg0_t cfg;
1427 lsm6dsv16x_functions_enable_t func;
1428 int32_t ret;
1429
1430 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1);
1431 func.interrupts_enable = val.enable;
1432 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1);
1433 if (ret != 0)
1434 {
1435 return ret;
1436 }
1437
1438 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&cfg, 1);
1439 cfg.lir = val.lir;
1440 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&cfg, 1);
1441
1442 return ret;
1443 }
1444
1445 /**
1446 * @brief Enables latched interrupt mode.[get]
1447 *
1448 * @param ctx read / write interface definitions
1449 * @param val enable/disable, latched/pulsed
1450 * @retval interface status (MANDATORY: return 0 -> no Error)
1451 *
1452 */
lsm6dsv16x_interrupt_enable_get(const stmdev_ctx_t * ctx,lsm6dsv16x_interrupt_mode_t * val)1453 int32_t lsm6dsv16x_interrupt_enable_get(const stmdev_ctx_t *ctx,
1454 lsm6dsv16x_interrupt_mode_t *val)
1455 {
1456 lsm6dsv16x_tap_cfg0_t cfg;
1457 lsm6dsv16x_functions_enable_t func;
1458 int32_t ret;
1459
1460 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&func, 1);
1461 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&cfg, 1);
1462 if (ret != 0)
1463 {
1464 return ret;
1465 }
1466
1467 val->enable = func.interrupts_enable;
1468 val->lir = cfg.lir;
1469
1470 return ret;
1471 }
1472
1473 /**
1474 * @brief Gyroscope full-scale selection[set]
1475 *
1476 * @param ctx read / write interface definitions
1477 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
1478 * @retval interface status (MANDATORY: return 0 -> no Error)
1479 *
1480 */
lsm6dsv16x_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv16x_gy_full_scale_t val)1481 int32_t lsm6dsv16x_gy_full_scale_set(const stmdev_ctx_t *ctx,
1482 lsm6dsv16x_gy_full_scale_t val)
1483 {
1484 lsm6dsv16x_ctrl6_t ctrl6;
1485 int32_t ret;
1486
1487 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1);
1488
1489 if (ret == 0)
1490 {
1491 ctrl6.fs_g = (uint8_t)val & 0xfu;
1492 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1);
1493 }
1494
1495 return ret;
1496 }
1497
1498 /**
1499 * @brief Gyroscope full-scale selection[get]
1500 *
1501 * @param ctx read / write interface definitions
1502 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
1503 * @retval interface status (MANDATORY: return 0 -> no Error)
1504 *
1505 */
lsm6dsv16x_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv16x_gy_full_scale_t * val)1506 int32_t lsm6dsv16x_gy_full_scale_get(const stmdev_ctx_t *ctx,
1507 lsm6dsv16x_gy_full_scale_t *val)
1508 {
1509 lsm6dsv16x_ctrl6_t ctrl6;
1510 int32_t ret;
1511
1512 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1);
1513 if (ret != 0)
1514 {
1515 return ret;
1516 }
1517
1518 switch (ctrl6.fs_g)
1519 {
1520 case LSM6DSV16X_125dps:
1521 *val = LSM6DSV16X_125dps;
1522 break;
1523
1524 case LSM6DSV16X_250dps:
1525 *val = LSM6DSV16X_250dps;
1526 break;
1527
1528 case LSM6DSV16X_500dps:
1529 *val = LSM6DSV16X_500dps;
1530 break;
1531
1532 case LSM6DSV16X_1000dps:
1533 *val = LSM6DSV16X_1000dps;
1534 break;
1535
1536 case LSM6DSV16X_2000dps:
1537 *val = LSM6DSV16X_2000dps;
1538 break;
1539
1540 case LSM6DSV16X_4000dps:
1541 *val = LSM6DSV16X_4000dps;
1542 break;
1543
1544 default:
1545 *val = LSM6DSV16X_125dps;
1546 break;
1547 }
1548
1549 return ret;
1550 }
1551
1552 /**
1553 * @brief Accelerometer full-scale selection.[set]
1554 *
1555 * @param ctx read / write interface definitions
1556 * @param val lsm6dsv16x_xl_full_scale_t
1557 * @retval interface status (MANDATORY: return 0 -> no Error)
1558 *
1559 */
lsm6dsv16x_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv16x_xl_full_scale_t val)1560 int32_t lsm6dsv16x_xl_full_scale_set(const stmdev_ctx_t *ctx,
1561 lsm6dsv16x_xl_full_scale_t val)
1562 {
1563 lsm6dsv16x_ctrl8_t ctrl8;
1564 int32_t ret;
1565
1566 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1);
1567
1568 if (ret == 0)
1569 {
1570 ctrl8.fs_xl = (uint8_t)val & 0x3U;
1571 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1);
1572 }
1573
1574 return ret;
1575 }
1576
1577 /**
1578 * @brief Accelerometer full-scale selection.[get]
1579 *
1580 * @param ctx read / write interface definitions
1581 * @param val lsm6dsv16x_xl_full_scale_t
1582 * @retval interface status (MANDATORY: return 0 -> no Error)
1583 *
1584 */
lsm6dsv16x_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv16x_xl_full_scale_t * val)1585 int32_t lsm6dsv16x_xl_full_scale_get(const stmdev_ctx_t *ctx,
1586 lsm6dsv16x_xl_full_scale_t *val)
1587 {
1588 lsm6dsv16x_ctrl8_t ctrl8;
1589 int32_t ret;
1590
1591 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1);
1592 if (ret != 0)
1593 {
1594 return ret;
1595 }
1596
1597 switch (ctrl8.fs_xl)
1598 {
1599 case LSM6DSV16X_2g:
1600 *val = LSM6DSV16X_2g;
1601 break;
1602
1603 case LSM6DSV16X_4g:
1604 *val = LSM6DSV16X_4g;
1605 break;
1606
1607 case LSM6DSV16X_8g:
1608 *val = LSM6DSV16X_8g;
1609 break;
1610
1611 case LSM6DSV16X_16g:
1612 *val = LSM6DSV16X_16g;
1613 break;
1614
1615 default:
1616 *val = LSM6DSV16X_2g;
1617 break;
1618 }
1619
1620 return ret;
1621 }
1622
1623 /**
1624 * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[set]
1625 *
1626 * @param ctx read / write interface definitions
1627 * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.
1628 * @retval interface status (MANDATORY: return 0 -> no Error)
1629 *
1630 */
lsm6dsv16x_xl_dual_channel_set(const stmdev_ctx_t * ctx,uint8_t val)1631 int32_t lsm6dsv16x_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val)
1632 {
1633 lsm6dsv16x_ctrl8_t ctrl8;
1634 int32_t ret;
1635
1636 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1);
1637
1638 if (ret == 0)
1639 {
1640 ctrl8.xl_dualc_en = val;
1641 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1);
1642 }
1643
1644 return ret;
1645 }
1646
1647 /**
1648 * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[get]
1649 *
1650 * @param ctx read / write interface definitions
1651 * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.
1652 * @retval interface status (MANDATORY: return 0 -> no Error)
1653 *
1654 */
lsm6dsv16x_xl_dual_channel_get(const stmdev_ctx_t * ctx,uint8_t * val)1655 int32_t lsm6dsv16x_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val)
1656 {
1657 lsm6dsv16x_ctrl8_t ctrl8;
1658 int32_t ret;
1659
1660 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1);
1661 *val = ctrl8.xl_dualc_en;
1662
1663 return ret;
1664 }
1665
1666 /**
1667 * @brief Accelerometer self-test selection.[set]
1668 *
1669 * @param ctx read / write interface definitions
1670 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1671 * @retval interface status (MANDATORY: return 0 -> no Error)
1672 *
1673 */
lsm6dsv16x_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6dsv16x_xl_self_test_t val)1674 int32_t lsm6dsv16x_xl_self_test_set(const stmdev_ctx_t *ctx,
1675 lsm6dsv16x_xl_self_test_t val)
1676 {
1677 lsm6dsv16x_ctrl10_t ctrl10;
1678 int32_t ret;
1679
1680 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
1681
1682 if (ret == 0)
1683 {
1684 ctrl10.st_xl = (uint8_t)val & 0x3U;
1685 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
1686 }
1687
1688 return ret;
1689 }
1690
1691 /**
1692 * @brief Accelerometer self-test selection.[get]
1693 *
1694 * @param ctx read / write interface definitions
1695 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1696 * @retval interface status (MANDATORY: return 0 -> no Error)
1697 *
1698 */
lsm6dsv16x_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6dsv16x_xl_self_test_t * val)1699 int32_t lsm6dsv16x_xl_self_test_get(const stmdev_ctx_t *ctx,
1700 lsm6dsv16x_xl_self_test_t *val)
1701 {
1702 lsm6dsv16x_ctrl10_t ctrl10;
1703 int32_t ret;
1704
1705 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
1706 if (ret != 0)
1707 {
1708 return ret;
1709 }
1710
1711 switch (ctrl10.st_xl)
1712 {
1713 case LSM6DSV16X_XL_ST_DISABLE:
1714 *val = LSM6DSV16X_XL_ST_DISABLE;
1715 break;
1716
1717 case LSM6DSV16X_XL_ST_POSITIVE:
1718 *val = LSM6DSV16X_XL_ST_POSITIVE;
1719 break;
1720
1721 case LSM6DSV16X_XL_ST_NEGATIVE:
1722 *val = LSM6DSV16X_XL_ST_NEGATIVE;
1723 break;
1724
1725 default:
1726 *val = LSM6DSV16X_XL_ST_DISABLE;
1727 break;
1728 }
1729
1730 return ret;
1731 }
1732
1733 /**
1734 * @brief Gyroscope self-test selection.[set]
1735 *
1736 * @param ctx read / write interface definitions
1737 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1738 * @retval interface status (MANDATORY: return 0 -> no Error)
1739 *
1740 */
lsm6dsv16x_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dsv16x_gy_self_test_t val)1741 int32_t lsm6dsv16x_gy_self_test_set(const stmdev_ctx_t *ctx,
1742 lsm6dsv16x_gy_self_test_t val)
1743 {
1744 lsm6dsv16x_ctrl10_t ctrl10;
1745 int32_t ret;
1746
1747 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
1748
1749 if (ret == 0)
1750 {
1751 ctrl10.st_g = (uint8_t)val & 0x3U;
1752 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
1753 }
1754
1755 return ret;
1756 }
1757
1758 /**
1759 * @brief Gyroscope self-test selection.[get]
1760 *
1761 * @param ctx read / write interface definitions
1762 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1763 * @retval interface status (MANDATORY: return 0 -> no Error)
1764 *
1765 */
lsm6dsv16x_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dsv16x_gy_self_test_t * val)1766 int32_t lsm6dsv16x_gy_self_test_get(const stmdev_ctx_t *ctx,
1767 lsm6dsv16x_gy_self_test_t *val)
1768 {
1769 lsm6dsv16x_ctrl10_t ctrl10;
1770 int32_t ret;
1771
1772 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
1773 if (ret != 0)
1774 {
1775 return ret;
1776 }
1777
1778 switch (ctrl10.st_g)
1779 {
1780 case LSM6DSV16X_GY_ST_DISABLE:
1781 *val = LSM6DSV16X_GY_ST_DISABLE;
1782 break;
1783
1784 case LSM6DSV16X_GY_ST_POSITIVE:
1785 *val = LSM6DSV16X_GY_ST_POSITIVE;
1786 break;
1787
1788 case LSM6DSV16X_GY_ST_NEGATIVE:
1789 *val = LSM6DSV16X_GY_ST_NEGATIVE;
1790 break;
1791
1792 default:
1793 *val = LSM6DSV16X_GY_ST_DISABLE;
1794 break;
1795 }
1796
1797 return ret;
1798 }
1799
1800 /**
1801 * @brief SPI2 Accelerometer self-test selection.[set]
1802 *
1803 * @param ctx read / write interface definitions
1804 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1805 * @retval interface status (MANDATORY: return 0 -> no Error)
1806 *
1807 */
lsm6dsv16x_ois_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6dsv16x_ois_xl_self_test_t val)1808 int32_t lsm6dsv16x_ois_xl_self_test_set(const stmdev_ctx_t *ctx,
1809 lsm6dsv16x_ois_xl_self_test_t val)
1810 {
1811 lsm6dsv16x_spi2_int_ois_t spi2_int_ois;
1812 int32_t ret;
1813
1814 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1815
1816 if (ret == 0)
1817 {
1818 spi2_int_ois.st_xl_ois = ((uint8_t)val & 0x3U);
1819 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1820 }
1821
1822 return ret;
1823 }
1824
1825 /**
1826 * @brief SPI2 Accelerometer self-test selection.[get]
1827 *
1828 * @param ctx read / write interface definitions
1829 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1830 * @retval interface status (MANDATORY: return 0 -> no Error)
1831 *
1832 */
lsm6dsv16x_ois_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6dsv16x_ois_xl_self_test_t * val)1833 int32_t lsm6dsv16x_ois_xl_self_test_get(const stmdev_ctx_t *ctx,
1834 lsm6dsv16x_ois_xl_self_test_t *val)
1835 {
1836 lsm6dsv16x_spi2_int_ois_t spi2_int_ois;
1837 int32_t ret;
1838
1839 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1840 if (ret != 0)
1841 {
1842 return ret;
1843 }
1844
1845 switch (spi2_int_ois.st_xl_ois)
1846 {
1847 case LSM6DSV16X_OIS_XL_ST_DISABLE:
1848 *val = LSM6DSV16X_OIS_XL_ST_DISABLE;
1849 break;
1850
1851 case LSM6DSV16X_OIS_XL_ST_POSITIVE:
1852 *val = LSM6DSV16X_OIS_XL_ST_POSITIVE;
1853 break;
1854
1855 case LSM6DSV16X_OIS_XL_ST_NEGATIVE:
1856 *val = LSM6DSV16X_OIS_XL_ST_NEGATIVE;
1857 break;
1858
1859 default:
1860 *val = LSM6DSV16X_OIS_XL_ST_DISABLE;
1861 break;
1862 }
1863
1864 return ret;
1865 }
1866
1867 /**
1868 * @brief SPI2 Accelerometer self-test selection.[set]
1869 *
1870 * @param ctx read / write interface definitions
1871 * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, LSM6DSV16X_OIS_GY_ST_CLAMP_POS, LSM6DSV16X_OIS_GY_ST_CLAMP_NEG
1872 * @retval interface status (MANDATORY: return 0 -> no Error)
1873 *
1874 */
lsm6dsv16x_ois_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dsv16x_ois_gy_self_test_t val)1875 int32_t lsm6dsv16x_ois_gy_self_test_set(const stmdev_ctx_t *ctx,
1876 lsm6dsv16x_ois_gy_self_test_t val)
1877 {
1878 lsm6dsv16x_spi2_int_ois_t spi2_int_ois;
1879 int32_t ret;
1880
1881 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1882
1883 if (ret == 0)
1884 {
1885 spi2_int_ois.st_g_ois = ((uint8_t)val & 0x3U);
1886 spi2_int_ois.st_ois_clampdis = ((uint8_t)val & 0x04U) >> 2;
1887 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1888 }
1889
1890 return ret;
1891 }
1892
1893 /**
1894 * @brief SPI2 Accelerometer self-test selection.[get]
1895 *
1896 * @param ctx read / write interface definitions
1897 * @param val GY_ST_DISABLE, GY_ST_POSITIVE, GY_ST_NEGATIVE, LSM6DSV16X_OIS_GY_ST_CLAMP_POS, LSM6DSV16X_OIS_GY_ST_CLAMP_NEG
1898 * @retval interface status (MANDATORY: return 0 -> no Error)
1899 *
1900 */
lsm6dsv16x_ois_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dsv16x_ois_gy_self_test_t * val)1901 int32_t lsm6dsv16x_ois_gy_self_test_get(const stmdev_ctx_t *ctx,
1902 lsm6dsv16x_ois_gy_self_test_t *val)
1903 {
1904 lsm6dsv16x_spi2_int_ois_t spi2_int_ois;
1905 int32_t ret;
1906
1907 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
1908 if (ret != 0)
1909 {
1910 return ret;
1911 }
1912
1913 switch (spi2_int_ois.st_g_ois)
1914 {
1915 case LSM6DSV16X_OIS_GY_ST_DISABLE:
1916 *val = LSM6DSV16X_OIS_GY_ST_DISABLE;
1917 break;
1918
1919 case LSM6DSV16X_OIS_GY_ST_POSITIVE:
1920 *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV16X_OIS_GY_ST_CLAMP_POS :
1921 LSM6DSV16X_OIS_GY_ST_POSITIVE;
1922 break;
1923
1924 case LSM6DSV16X_OIS_GY_ST_NEGATIVE:
1925 *val = (spi2_int_ois.st_ois_clampdis == 1U) ? LSM6DSV16X_OIS_GY_ST_CLAMP_NEG :
1926 LSM6DSV16X_OIS_GY_ST_NEGATIVE;
1927 break;
1928
1929 default:
1930 *val = LSM6DSV16X_OIS_GY_ST_DISABLE;
1931 break;
1932 }
1933
1934 return ret;
1935 }
1936
1937 /**
1938 * @defgroup interrupt_pins
1939 * @brief This section groups all the functions that manage
1940 * interrupt pins
1941 * @{
1942 *
1943 */
1944
1945 /**
1946 * @brief Select the signal that need to route on int1 pad[set]
1947 *
1948 * @param ctx Read / write interface definitions.(ptr)
1949 * @param val the signals to route on int1 pin.
1950 * @retval Interface status (MANDATORY: return 0 -> no Error).
1951 *
1952 */
lsm6dsv16x_pin_int1_route_set(const stmdev_ctx_t * ctx,lsm6dsv16x_pin_int_route_t * val)1953 int32_t lsm6dsv16x_pin_int1_route_set(const stmdev_ctx_t *ctx,
1954 lsm6dsv16x_pin_int_route_t *val)
1955 {
1956 lsm6dsv16x_int1_ctrl_t int1_ctrl;
1957 lsm6dsv16x_md1_cfg_t md1_cfg;
1958 int32_t ret;
1959
1960 /* not available on INT1 */
1961 if (val->drdy_temp == 1)
1962 {
1963 return -1;
1964 }
1965
1966 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
1967 if (ret != 0)
1968 {
1969 return ret;
1970 }
1971
1972 int1_ctrl.int1_drdy_xl = val->drdy_xl;
1973 int1_ctrl.int1_drdy_g = val->drdy_g;
1974 int1_ctrl.int1_fifo_th = val->fifo_th;
1975 int1_ctrl.int1_fifo_ovr = val->fifo_ovr;
1976 int1_ctrl.int1_fifo_full = val->fifo_full;
1977 int1_ctrl.int1_cnt_bdr = val->cnt_bdr;
1978
1979 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
1980 if (ret != 0)
1981 {
1982 return ret;
1983 }
1984
1985 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MD1_CFG, (uint8_t *)&md1_cfg, 1);
1986 if (ret != 0)
1987 {
1988 return ret;
1989 }
1990
1991 md1_cfg.int1_shub = val->shub;
1992 md1_cfg.int1_emb_func = val->emb_func;
1993 md1_cfg.int1_6d = val->sixd;
1994 md1_cfg.int1_single_tap = val->single_tap;
1995 md1_cfg.int1_double_tap = val->double_tap;
1996 md1_cfg.int1_wu = val->wakeup;
1997 md1_cfg.int1_ff = val->freefall;
1998 md1_cfg.int1_sleep_change = val->sleep_change;
1999
2000 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MD1_CFG, (uint8_t *)&md1_cfg, 1);
2001
2002 return ret;
2003 }
2004
2005 /**
2006 * @brief Select the signal that need to route on int1 pad.[get]
2007 *
2008 * @param ctx Read / write interface definitions.(ptr)
2009 * @param val the signals that are routed on int1 pin.(ptr)
2010 * @retval Interface status (MANDATORY: return 0 -> no Error).
2011 *
2012 */
lsm6dsv16x_pin_int1_route_get(const stmdev_ctx_t * ctx,lsm6dsv16x_pin_int_route_t * val)2013 int32_t lsm6dsv16x_pin_int1_route_get(const stmdev_ctx_t *ctx,
2014 lsm6dsv16x_pin_int_route_t *val)
2015 {
2016 lsm6dsv16x_int1_ctrl_t int1_ctrl;
2017 lsm6dsv16x_md1_cfg_t md1_cfg;
2018 int32_t ret;
2019
2020 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
2021 if (ret != 0)
2022 {
2023 return ret;
2024 }
2025
2026 val->drdy_xl = int1_ctrl.int1_drdy_xl;
2027 val->drdy_g = int1_ctrl.int1_drdy_g;
2028 val->fifo_th = int1_ctrl.int1_fifo_th;
2029 val->fifo_ovr = int1_ctrl.int1_fifo_ovr;
2030 val->fifo_full = int1_ctrl.int1_fifo_full;
2031 val->cnt_bdr = int1_ctrl.int1_cnt_bdr;
2032
2033 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MD1_CFG, (uint8_t *)&md1_cfg, 1);
2034 if (ret != 0)
2035 {
2036 return ret;
2037 }
2038
2039 val->shub = md1_cfg.int1_shub;
2040 val->emb_func = md1_cfg.int1_emb_func;
2041 val->sixd = md1_cfg.int1_6d;
2042 val->single_tap = md1_cfg.int1_single_tap;
2043 val->double_tap = md1_cfg.int1_double_tap;
2044 val->wakeup = md1_cfg.int1_wu;
2045 val->freefall = md1_cfg.int1_ff;
2046 val->sleep_change = md1_cfg.int1_sleep_change;
2047
2048 return ret;
2049 }
2050
2051 /**
2052 * @brief Select the signal that need to route on int2 pad[set]
2053 *
2054 * @param ctx Read / write interface definitions.(ptr)
2055 * @param val the signals to route on int2 pin.
2056 * @retval Interface status (MANDATORY: return 0 -> no Error).
2057 *
2058 */
lsm6dsv16x_pin_int2_route_set(const stmdev_ctx_t * ctx,lsm6dsv16x_pin_int_route_t * val)2059 int32_t lsm6dsv16x_pin_int2_route_set(const stmdev_ctx_t *ctx,
2060 lsm6dsv16x_pin_int_route_t *val)
2061 {
2062 lsm6dsv16x_int2_ctrl_t int2_ctrl;
2063 lsm6dsv16x_ctrl4_t ctrl4;
2064 lsm6dsv16x_ctrl7_t ctrl7;
2065 lsm6dsv16x_md2_cfg_t md2_cfg;
2066 int32_t ret;
2067
2068 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2069 if (ret != 0)
2070 {
2071 return ret;
2072 }
2073
2074 int2_ctrl.int2_drdy_xl = val->drdy_xl;
2075 int2_ctrl.int2_drdy_g = val->drdy_g;
2076 int2_ctrl.int2_fifo_th = val->fifo_th;
2077 int2_ctrl.int2_fifo_ovr = val->fifo_ovr;
2078 int2_ctrl.int2_fifo_full = val->fifo_full;
2079 int2_ctrl.int2_cnt_bdr = val->cnt_bdr;
2080 int2_ctrl.int2_drdy_g_eis = val->drdy_g_eis;
2081 int2_ctrl.int2_emb_func_endop = val->emb_func_endop;
2082
2083 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2084 if (ret != 0)
2085 {
2086 return ret;
2087 }
2088
2089 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
2090 ctrl4.int2_drdy_temp = val->drdy_temp;
2091 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
2092 if (ret != 0)
2093 {
2094 return ret;
2095 }
2096
2097 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
2098 ctrl7.int2_drdy_ah_qvar = val->drdy_ah_qvar;
2099 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
2100 if (ret != 0)
2101 {
2102 return ret;
2103 }
2104
2105 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2106 if (ret != 0)
2107 {
2108 return ret;
2109 }
2110
2111 md2_cfg.int2_timestamp = val->timestamp;
2112 md2_cfg.int2_emb_func = val->emb_func;
2113 md2_cfg.int2_6d = val->sixd;
2114 md2_cfg.int2_single_tap = val->single_tap;
2115 md2_cfg.int2_double_tap = val->double_tap;
2116 md2_cfg.int2_wu = val->wakeup;
2117 md2_cfg.int2_ff = val->freefall;
2118 md2_cfg.int2_sleep_change = val->sleep_change;
2119
2120 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2121
2122 return ret;
2123 }
2124
2125 /**
2126 * @brief Select the signal that need to route on int2 pad.[get]
2127 *
2128 * @param ctx Read / write interface definitions.(ptr)
2129 * @param val the signals that are routed on int2 pin.(ptr)
2130 * @retval Interface status (MANDATORY: return 0 -> no Error).
2131 *
2132 */
lsm6dsv16x_pin_int2_route_get(const stmdev_ctx_t * ctx,lsm6dsv16x_pin_int_route_t * val)2133 int32_t lsm6dsv16x_pin_int2_route_get(const stmdev_ctx_t *ctx,
2134 lsm6dsv16x_pin_int_route_t *val)
2135 {
2136 lsm6dsv16x_int2_ctrl_t int2_ctrl;
2137 lsm6dsv16x_ctrl4_t ctrl4;
2138 lsm6dsv16x_ctrl7_t ctrl7;
2139 lsm6dsv16x_md2_cfg_t md2_cfg;
2140 int32_t ret;
2141
2142 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2143 if (ret != 0)
2144 {
2145 return ret;
2146 }
2147
2148 val->drdy_xl = int2_ctrl.int2_drdy_xl;
2149 val->drdy_g = int2_ctrl.int2_drdy_g;
2150 val->fifo_th = int2_ctrl.int2_fifo_th;
2151 val->fifo_ovr = int2_ctrl.int2_fifo_ovr;
2152 val->fifo_full = int2_ctrl.int2_fifo_full;
2153 val->cnt_bdr = int2_ctrl.int2_cnt_bdr;
2154 val->drdy_g_eis = int2_ctrl.int2_drdy_g_eis;
2155 val->emb_func_endop = int2_ctrl.int2_emb_func_endop;
2156
2157 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
2158 if (ret != 0)
2159 {
2160 return ret;
2161 }
2162
2163 val->drdy_temp = ctrl4.int2_drdy_temp;
2164
2165 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
2166 if (ret != 0)
2167 {
2168 return ret;
2169 }
2170
2171 val->drdy_ah_qvar = ctrl7.int2_drdy_ah_qvar;
2172
2173 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2174 if (ret != 0)
2175 {
2176 return ret;
2177 }
2178
2179 val->timestamp = md2_cfg.int2_timestamp;
2180 val->emb_func = md2_cfg.int2_emb_func;
2181 val->sixd = md2_cfg.int2_6d;
2182 val->single_tap = md2_cfg.int2_single_tap;
2183 val->double_tap = md2_cfg.int2_double_tap;
2184 val->wakeup = md2_cfg.int2_wu;
2185 val->freefall = md2_cfg.int2_ff;
2186 val->sleep_change = md2_cfg.int2_sleep_change;
2187
2188 return ret;
2189 }
2190
2191 /**
2192 * @brief routes embedded func interrupt signals on INT 1 pin.[set]
2193 *
2194 * @param ctx read / write interface definitions
2195 * @param val routes embedded func interrupt signals on INT 1 pin.
2196 * @retval interface status (MANDATORY: return 0 -> no Error)
2197 *
2198 */
lsm6dsv16x_emb_pin_int1_route_set(const stmdev_ctx_t * ctx,const lsm6dsv16x_emb_pin_int_route_t * val)2199 int32_t lsm6dsv16x_emb_pin_int1_route_set(const stmdev_ctx_t *ctx,
2200 const lsm6dsv16x_emb_pin_int_route_t *val)
2201 {
2202 lsm6dsv16x_emb_func_int1_t emb_func_int1;
2203 lsm6dsv16x_md1_cfg_t md1_cfg;
2204 int32_t ret;
2205
2206 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
2207 if (ret == 0)
2208 {
2209 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
2210 }
2211
2212 if (ret == 0)
2213 {
2214 emb_func_int1.int1_tilt = val->tilt;
2215 emb_func_int1.int1_sig_mot = val->sig_mot;
2216 emb_func_int1.int1_step_detector = val->step_det;
2217 emb_func_int1.int1_fsm_lc = val->fsm_lc;
2218
2219 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
2220 }
2221 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
2222
2223 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MD1_CFG, (uint8_t *)&md1_cfg, 1);
2224 if (ret == 0)
2225 {
2226 md1_cfg.int1_emb_func = 1;
2227 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MD1_CFG, (uint8_t *)&md1_cfg, 1);
2228 }
2229
2230 return ret;
2231 }
2232
2233 /**
2234 * @brief routes embedded func interrupt signals on INT 1 pin.[get]
2235 *
2236 * @param ctx read / write interface definitions
2237 * @param val routes embedded func interrupt signals on INT 1 pin.
2238 * @retval interface status (MANDATORY: return 0 -> no Error)
2239 *
2240 */
lsm6dsv16x_emb_pin_int1_route_get(const stmdev_ctx_t * ctx,lsm6dsv16x_emb_pin_int_route_t * val)2241 int32_t lsm6dsv16x_emb_pin_int1_route_get(const stmdev_ctx_t *ctx,
2242 lsm6dsv16x_emb_pin_int_route_t *val)
2243 {
2244 lsm6dsv16x_emb_func_int1_t emb_func_int1;
2245 int32_t ret;
2246
2247 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
2248 if (ret == 0)
2249 {
2250 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
2251 }
2252
2253 if (ret == 0)
2254 {
2255 val->tilt = emb_func_int1.int1_tilt;
2256 val->sig_mot = emb_func_int1.int1_sig_mot;
2257 val->step_det = emb_func_int1.int1_step_detector;
2258 val->fsm_lc = emb_func_int1.int1_fsm_lc;
2259 }
2260 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
2261
2262 return ret;
2263 }
2264
2265 /**
2266 * @brief routes embedded func interrupt signals on INT 2 pin.[set]
2267 *
2268 * @param ctx read / write interface definitions
2269 * @param val routes embedded func interrupt signals on INT 2 pin.
2270 * @retval interface status (MANDATORY: return 0 -> no Error)
2271 *
2272 */
lsm6dsv16x_emb_pin_int2_route_set(const stmdev_ctx_t * ctx,const lsm6dsv16x_emb_pin_int_route_t * val)2273 int32_t lsm6dsv16x_emb_pin_int2_route_set(const stmdev_ctx_t *ctx,
2274 const lsm6dsv16x_emb_pin_int_route_t *val)
2275 {
2276 lsm6dsv16x_emb_func_int2_t emb_func_int2;
2277 lsm6dsv16x_md2_cfg_t md2_cfg;
2278 int32_t ret;
2279
2280 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
2281 if (ret == 0)
2282 {
2283 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
2284 }
2285
2286 if (ret == 0)
2287 {
2288 emb_func_int2.int2_tilt = val->tilt;
2289 emb_func_int2.int2_sig_mot = val->sig_mot;
2290 emb_func_int2.int2_step_detector = val->step_det;
2291 emb_func_int2.int2_fsm_lc = val->fsm_lc;
2292
2293 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
2294 }
2295 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
2296
2297 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2298 if (ret == 0)
2299 {
2300 md2_cfg.int2_emb_func = 1;
2301 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2302 }
2303
2304 return ret;
2305 }
2306
2307 /**
2308 * @brief routes embedded func interrupt signals on INT 2 pin.[get]
2309 *
2310 * @param ctx read / write interface definitions
2311 * @param val routes embedded func interrupt signals on INT 2 pin.
2312 * @retval interface status (MANDATORY: return 0 -> no Error)
2313 *
2314 */
lsm6dsv16x_emb_pin_int2_route_get(const stmdev_ctx_t * ctx,lsm6dsv16x_emb_pin_int_route_t * val)2315 int32_t lsm6dsv16x_emb_pin_int2_route_get(const stmdev_ctx_t *ctx,
2316 lsm6dsv16x_emb_pin_int_route_t *val)
2317 {
2318 lsm6dsv16x_emb_func_int2_t emb_func_int2;
2319 int32_t ret;
2320
2321 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
2322 if (ret == 0)
2323 {
2324 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
2325 }
2326
2327 if (ret == 0)
2328 {
2329 val->tilt = emb_func_int2.int2_tilt;
2330 val->sig_mot = emb_func_int2.int2_sig_mot;
2331 val->step_det = emb_func_int2.int2_step_detector;
2332 val->fsm_lc = emb_func_int2.int2_fsm_lc;
2333 }
2334 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
2335
2336 return ret;
2337 }
2338
2339 /**
2340 * @brief Embedded Interrupt configuration mode.[set]
2341 *
2342 * @param ctx read / write interface definitions
2343 * @param val INT_PULSED, INT_LATCHED
2344 * @retval interface status (MANDATORY: return 0 -> no Error)
2345 *
2346 */
lsm6dsv16x_embedded_int_cfg_set(const stmdev_ctx_t * ctx,lsm6dsv16x_embedded_int_config_t val)2347 int32_t lsm6dsv16x_embedded_int_cfg_set(const stmdev_ctx_t *ctx,
2348 lsm6dsv16x_embedded_int_config_t val)
2349 {
2350 lsm6dsv16x_page_rw_t page_rw;
2351 int32_t ret;
2352
2353 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
2354 if (ret == 0)
2355 {
2356 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1);
2357
2358 switch (val)
2359 {
2360 case LSM6DSV16X_INT_LATCH_DISABLE:
2361 page_rw.emb_func_lir = 0;
2362 break;
2363
2364 case LSM6DSV16X_INT_LATCH_ENABLE:
2365 default:
2366 page_rw.emb_func_lir = 1;
2367 break;
2368 }
2369
2370 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1);
2371 }
2372
2373 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
2374
2375 return ret;
2376 }
2377
2378 /**
2379 * @brief Interrupt configuration mode.[get]
2380 *
2381 * @param ctx read / write interface definitions
2382 * @param val INT_DISABLED, INT_PULSED, INT_LATCHED
2383 * @retval interface status (MANDATORY: return 0 -> no Error)
2384 *
2385 */
lsm6dsv16x_embedded_int_cfg_get(const stmdev_ctx_t * ctx,lsm6dsv16x_embedded_int_config_t * val)2386 int32_t lsm6dsv16x_embedded_int_cfg_get(const stmdev_ctx_t *ctx,
2387 lsm6dsv16x_embedded_int_config_t *val)
2388 {
2389 lsm6dsv16x_page_rw_t page_rw;
2390 int32_t ret;
2391
2392 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
2393 if (ret == 0)
2394 {
2395 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1);
2396
2397 if (page_rw.emb_func_lir == 0U)
2398 {
2399 *val = LSM6DSV16X_INT_LATCH_DISABLE;
2400 }
2401 else
2402 {
2403 *val = LSM6DSV16X_INT_LATCH_ENABLE;
2404 }
2405 }
2406
2407 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
2408
2409 return ret;
2410 }
2411
2412 /**
2413 * @brief Get the status of embedded functions.[get]
2414 *
2415 * @param ctx read / write interface definitions
2416 * @param val lsm6dsv16x_embedded_status_t ptr
2417 * @retval interface status (MANDATORY: return 0 -> no Error)
2418 *
2419 */
lsm6dsv16x_embedded_status_get(const stmdev_ctx_t * ctx,lsm6dsv16x_embedded_status_t * val)2420 int32_t lsm6dsv16x_embedded_status_get(const stmdev_ctx_t *ctx,
2421 lsm6dsv16x_embedded_status_t *val)
2422 {
2423 lsm6dsv16x_emb_func_status_mainpage_t emb_func_status;
2424 lsm6dsv16x_emb_func_src_t emb_func_src;
2425 int32_t ret;
2426
2427 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_STATUS_MAINPAGE, (uint8_t *)&emb_func_status, 1);
2428 if (ret != 0)
2429 {
2430 return ret;
2431 }
2432
2433 val->step_detector = emb_func_status.is_step_det;
2434 val->tilt = emb_func_status.is_tilt;
2435 val->sig_mot = emb_func_status.is_sigmot;
2436 val->fsm_lc = emb_func_status.is_fsm_lc;
2437
2438 /* embedded func */
2439 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
2440 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
2441 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
2442 if (ret != 0)
2443 {
2444 return ret;
2445 }
2446
2447 val->step_count_inc = emb_func_src.stepcounter_bit_set;
2448 val->step_count_overflow = emb_func_src.step_overflow;
2449 val->step_on_delta_time = emb_func_src.step_count_delta_ia;
2450 val->step_detector = emb_func_src.step_detected;
2451
2452 return ret;
2453 }
2454
2455 /**
2456 * @}
2457 *
2458 */
2459
2460 /**
2461 * @brief Get the status of all the interrupt sources.[get]
2462 *
2463 * @param ctx read / write interface definitions
2464 * @param val Get the status of all the interrupt sources.
2465 * @retval interface status (MANDATORY: return 0 -> no Error)
2466 *
2467 */
lsm6dsv16x_all_sources_get(const stmdev_ctx_t * ctx,lsm6dsv16x_all_sources_t * val)2468 int32_t lsm6dsv16x_all_sources_get(const stmdev_ctx_t *ctx,
2469 lsm6dsv16x_all_sources_t *val)
2470 {
2471 lsm6dsv16x_emb_func_status_mainpage_t emb_func_status_mainpage;
2472 lsm6dsv16x_emb_func_exec_status_t emb_func_exec_status;
2473 lsm6dsv16x_fsm_status_mainpage_t fsm_status_mainpage;
2474 lsm6dsv16x_mlc_status_mainpage_t mlc_status_mainpage;
2475 lsm6dsv16x_functions_enable_t functions_enable;
2476 lsm6dsv16x_emb_func_src_t emb_func_src;
2477 lsm6dsv16x_fifo_status2_t fifo_status2;
2478 lsm6dsv16x_all_int_src_t all_int_src;
2479 lsm6dsv16x_wake_up_src_t wake_up_src;
2480 lsm6dsv16x_status_reg_t status_reg;
2481 lsm6dsv16x_d6d_src_t d6d_src;
2482 lsm6dsv16x_tap_src_t tap_src;
2483 lsm6dsv16x_ui_status_reg_ois_t status_reg_ois;
2484 lsm6dsv16x_status_master_t status_shub;
2485 uint8_t buff[8];
2486 int32_t ret;
2487
2488 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
2489 functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE;
2490 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
2491 if (ret != 0)
2492 {
2493 return ret;
2494 }
2495
2496 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_STATUS1, (uint8_t *)&buff, 4);
2497 if (ret != 0)
2498 {
2499 return ret;
2500 }
2501
2502 bytecpy((uint8_t *)&fifo_status2, &buff[1]);
2503 bytecpy((uint8_t *)&all_int_src, &buff[2]);
2504 bytecpy((uint8_t *)&status_reg, &buff[3]);
2505
2506 val->fifo_ovr = fifo_status2.fifo_ovr_ia;
2507 val->fifo_bdr = fifo_status2.counter_bdr_ia;
2508 val->fifo_full = fifo_status2.fifo_full_ia;
2509 val->fifo_th = fifo_status2.fifo_wtm_ia;
2510
2511 val->free_fall = all_int_src.ff_ia;
2512 val->wake_up = all_int_src.wu_ia;
2513 val->six_d = all_int_src.d6d_ia;
2514
2515 val->drdy_xl = status_reg.xlda;
2516 val->drdy_gy = status_reg.gda;
2517 val->drdy_temp = status_reg.tda;
2518 val->drdy_ah_qvar = status_reg.ah_qvarda;
2519 val->drdy_eis = status_reg.gda_eis;
2520 val->drdy_ois = status_reg.ois_drdy;
2521 val->timestamp = status_reg.timestamp_endcount;
2522
2523 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
2524 functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE;
2525 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
2526 if (ret != 0)
2527 {
2528 return ret;
2529 }
2530
2531 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_STATUS_REG_OIS, (uint8_t *)&buff, 8);
2532 if (ret != 0)
2533 {
2534 return ret;
2535 }
2536
2537 bytecpy((uint8_t *)&status_reg_ois, &buff[0]);
2538 bytecpy((uint8_t *)&wake_up_src, &buff[1]);
2539 bytecpy((uint8_t *)&tap_src, &buff[2]);
2540 bytecpy((uint8_t *)&d6d_src, &buff[3]);
2541 bytecpy((uint8_t *)&emb_func_status_mainpage, &buff[5]);
2542 bytecpy((uint8_t *)&fsm_status_mainpage, &buff[6]);
2543 bytecpy((uint8_t *)&mlc_status_mainpage, &buff[7]);
2544
2545 val->gy_settling = status_reg_ois.gyro_settling;
2546 val->sleep_change = wake_up_src.sleep_change_ia;
2547 val->wake_up_x = wake_up_src.x_wu;
2548 val->wake_up_y = wake_up_src.y_wu;
2549 val->wake_up_z = wake_up_src.z_wu;
2550 val->sleep_state = wake_up_src.sleep_state;
2551
2552 val->tap_x = tap_src.x_tap;
2553 val->tap_y = tap_src.y_tap;
2554 val->tap_z = tap_src.z_tap;
2555 val->tap_sign = tap_src.tap_sign;
2556 val->double_tap = tap_src.double_tap;
2557 val->single_tap = tap_src.single_tap;
2558
2559 val->six_d_zl = d6d_src.zl;
2560 val->six_d_zh = d6d_src.zh;
2561 val->six_d_yl = d6d_src.yl;
2562 val->six_d_yh = d6d_src.yh;
2563 val->six_d_xl = d6d_src.xl;
2564 val->six_d_xh = d6d_src.xh;
2565
2566 val->step_detector = emb_func_status_mainpage.is_step_det;
2567 val->tilt = emb_func_status_mainpage.is_tilt;
2568 val->sig_mot = emb_func_status_mainpage.is_sigmot;
2569 val->fsm_lc = emb_func_status_mainpage.is_fsm_lc;
2570
2571 val->fsm1 = fsm_status_mainpage.is_fsm1;
2572 val->fsm2 = fsm_status_mainpage.is_fsm2;
2573 val->fsm3 = fsm_status_mainpage.is_fsm3;
2574 val->fsm4 = fsm_status_mainpage.is_fsm4;
2575 val->fsm5 = fsm_status_mainpage.is_fsm5;
2576 val->fsm6 = fsm_status_mainpage.is_fsm6;
2577 val->fsm7 = fsm_status_mainpage.is_fsm7;
2578 val->fsm8 = fsm_status_mainpage.is_fsm8;
2579
2580 val->mlc1 = mlc_status_mainpage.is_mlc1;
2581 val->mlc2 = mlc_status_mainpage.is_mlc2;
2582 val->mlc3 = mlc_status_mainpage.is_mlc3;
2583 val->mlc4 = mlc_status_mainpage.is_mlc4;
2584
2585 /* embedded func */
2586 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
2587 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status,
2588 1);
2589 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
2590 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
2591 if (ret != 0)
2592 {
2593 return ret;
2594 }
2595
2596 val->emb_func_stand_by = emb_func_exec_status.emb_func_endop;
2597 val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr;
2598 val->step_count_inc = emb_func_src.stepcounter_bit_set;
2599 val->step_count_overflow = emb_func_src.step_overflow;
2600 val->step_on_delta_time = emb_func_src.step_count_delta_ia;
2601
2602 val->step_detector = emb_func_src.step_detected;
2603
2604 /* sensor hub */
2605 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_STATUS_MASTER_MAINPAGE, (uint8_t *)&status_shub, 1);
2606 if (ret != 0)
2607 {
2608 return ret;
2609 }
2610
2611 val->sh_endop = status_shub.sens_hub_endop;
2612 val->sh_wr_once = status_shub.wr_once_done;
2613 val->sh_slave3_nack = status_shub.slave3_nack;
2614 val->sh_slave2_nack = status_shub.slave2_nack;
2615 val->sh_slave1_nack = status_shub.slave1_nack;
2616 val->sh_slave0_nack = status_shub.slave0_nack;
2617
2618 return ret;
2619 }
2620
lsm6dsv16x_flag_data_ready_get(const stmdev_ctx_t * ctx,lsm6dsv16x_data_ready_t * val)2621 int32_t lsm6dsv16x_flag_data_ready_get(const stmdev_ctx_t *ctx,
2622 lsm6dsv16x_data_ready_t *val)
2623 {
2624 lsm6dsv16x_status_reg_t status;
2625 int32_t ret;
2626
2627 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_STATUS_REG, (uint8_t *)&status, 1);
2628 if (ret != 0)
2629 {
2630 return ret;
2631 }
2632
2633 val->drdy_xl = status.xlda;
2634 val->drdy_gy = status.gda;
2635 val->drdy_temp = status.tda;
2636
2637 return ret;
2638 }
2639
2640 /**
2641 * @brief Mask status bit reset[set]
2642 *
2643 * @param ctx read / write interface definitions
2644 * @param val Mask to prevent status bit being reset
2645 * @retval interface status (MANDATORY: return 0 -> no Error)
2646 *
2647 */
lsm6dsv16x_int_ack_mask_set(const stmdev_ctx_t * ctx,uint8_t val)2648 int32_t lsm6dsv16x_int_ack_mask_set(const stmdev_ctx_t *ctx, uint8_t val)
2649 {
2650 int32_t ret;
2651
2652 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INT_ACK_MASK, &val, 1);
2653
2654 return ret;
2655 }
2656
2657 /**
2658 * @brief Mask status bit reset[get]
2659 *
2660 * @param ctx read / write interface definitions
2661 * @param val Mask to prevent status bit being reset
2662 * @retval interface status (MANDATORY: return 0 -> no Error)
2663 *
2664 */
lsm6dsv16x_int_ack_mask_get(const stmdev_ctx_t * ctx,uint8_t * val)2665 int32_t lsm6dsv16x_int_ack_mask_get(const stmdev_ctx_t *ctx, uint8_t *val)
2666 {
2667 int32_t ret;
2668
2669 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INT_ACK_MASK, val, 1);
2670
2671 return ret;
2672 }
2673
2674 /**
2675 * @brief Temperature data output register[get]
2676 *
2677 * @param ctx read / write interface definitions
2678 * @param val Temperature data output register
2679 * @retval interface status (MANDATORY: return 0 -> no Error)
2680 *
2681 */
lsm6dsv16x_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2682 int32_t lsm6dsv16x_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2683 {
2684 uint8_t buff[2];
2685 int32_t ret;
2686
2687 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_OUT_TEMP_L, &buff[0], 2);
2688 if (ret != 0)
2689 {
2690 return ret;
2691 }
2692
2693 *val = (int16_t)buff[1];
2694 *val = (*val * 256) + (int16_t)buff[0];
2695
2696 return ret;
2697 }
2698
2699 /**
2700 * @brief Angular rate sensor.[get]
2701 *
2702 * @param ctx read / write interface definitions
2703 * @param val Angular rate sensor.
2704 * @retval interface status (MANDATORY: return 0 -> no Error)
2705 *
2706 */
lsm6dsv16x_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2707 int32_t lsm6dsv16x_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2708 {
2709 uint8_t buff[6];
2710 int32_t ret;
2711
2712 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_OUTX_L_G, &buff[0], 6);
2713 if (ret != 0)
2714 {
2715 return ret;
2716 }
2717
2718 val[0] = (int16_t)buff[1];
2719 val[0] = (val[0] * 256) + (int16_t)buff[0];
2720 val[1] = (int16_t)buff[3];
2721 val[1] = (val[1] * 256) + (int16_t)buff[2];
2722 val[2] = (int16_t)buff[5];
2723 val[2] = (val[2] * 256) + (int16_t)buff[4];
2724
2725 return ret;
2726 }
2727
2728 /**
2729 * @brief Angular rate sensor.[get]
2730 *
2731 * @param ctx read / write interface definitions
2732 * @param val OIS Angular rate sensor (thru SPI2).
2733 * @retval interface status (MANDATORY: return 0 -> no Error)
2734 *
2735 */
lsm6dsv16x_ois_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2736 int32_t lsm6dsv16x_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2737 {
2738 uint8_t buff[6];
2739 int32_t ret;
2740
2741 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_OUTX_L_G_OIS, &buff[0], 6);
2742 if (ret != 0)
2743 {
2744 return ret;
2745 }
2746
2747 val[0] = (int16_t)buff[1];
2748 val[0] = (*val * 256) + (int16_t)buff[0];
2749 val[1] = (int16_t)buff[3];
2750 val[1] = (*val * 256) + (int16_t)buff[2];
2751 val[2] = (int16_t)buff[5];
2752 val[2] = (*val * 256) + (int16_t)buff[4];
2753
2754 return ret;
2755 }
2756
2757 /**
2758 * @brief Angular rate sensor for OIS gyro or the EIS gyro channel.[get]
2759 *
2760 * @param ctx read / write interface definitions
2761 * @param val Angular rate sensor for OIS gyro or the EIS gyro channel.
2762 * @retval interface status (MANDATORY: return 0 -> no Error)
2763 *
2764 */
lsm6dsv16x_ois_eis_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2765 int32_t lsm6dsv16x_ois_eis_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2766 {
2767 uint8_t buff[6];
2768 int32_t ret;
2769
2770 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_OUTX_L_G_OIS_EIS, &buff[0], 6);
2771 if (ret != 0)
2772 {
2773 return ret;
2774 }
2775
2776 val[0] = (int16_t)buff[1];
2777 val[0] = (*val * 256) + (int16_t)buff[0];
2778 val[1] = (int16_t)buff[3];
2779 val[1] = (*val * 256) + (int16_t)buff[2];
2780 val[2] = (int16_t)buff[5];
2781 val[2] = (*val * 256) + (int16_t)buff[4];
2782
2783 return ret;
2784 }
2785
2786 /**
2787 * @brief Linear acceleration sensor.[get]
2788 *
2789 * @param ctx read / write interface definitions
2790 * @param val Linear acceleration sensor.
2791 * @retval interface status (MANDATORY: return 0 -> no Error)
2792 *
2793 */
lsm6dsv16x_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2794 int32_t lsm6dsv16x_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2795 {
2796 uint8_t buff[6];
2797 int32_t ret;
2798
2799 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_OUTX_L_A, &buff[0], 6);
2800 if (ret != 0)
2801 {
2802 return ret;
2803 }
2804
2805 val[0] = (int16_t)buff[1];
2806 val[0] = (val[0] * 256) + (int16_t)buff[0];
2807 val[1] = (int16_t)buff[3];
2808 val[1] = (val[1] * 256) + (int16_t)buff[2];
2809 val[2] = (int16_t)buff[5];
2810 val[2] = (val[2] * 256) + (int16_t)buff[4];
2811
2812 return ret;
2813 }
2814
2815 /**
2816 * @brief Linear acceleration sensor for Dual channel mode.[get]
2817 *
2818 * @param ctx read / write interface definitions
2819 * @param val Linear acceleration sensor or Dual channel mode.
2820 * @retval interface status (MANDATORY: return 0 -> no Error)
2821 *
2822 */
lsm6dsv16x_dual_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2823 int32_t lsm6dsv16x_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2824 {
2825 uint8_t buff[6];
2826 int32_t ret;
2827
2828 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_OUTX_L_A_OIS_DUALC, &buff[0], 6);
2829 if (ret != 0)
2830 {
2831 return ret;
2832 }
2833
2834 val[0] = (int16_t)buff[1];
2835 val[0] = (val[0] * 256) + (int16_t)buff[0];
2836 val[1] = (int16_t)buff[3];
2837 val[1] = (val[1] * 256) + (int16_t)buff[2];
2838 val[2] = (int16_t)buff[5];
2839 val[2] = (val[2] * 256) + (int16_t)buff[4];
2840
2841 return ret;
2842 }
2843
2844 /**
2845 * @brief ah_qvar data output register.[get]
2846 *
2847 * @param ctx read / write interface definitions
2848 * @param val ah_qvar data output register.
2849 * @retval interface status (MANDATORY: return 0 -> no Error)
2850 *
2851 */
lsm6dsv16x_ah_qvar_raw_get(const stmdev_ctx_t * ctx,int16_t * val)2852 int32_t lsm6dsv16x_ah_qvar_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
2853 {
2854 uint8_t buff[2];
2855 int32_t ret;
2856
2857 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_AH_QVAR_OUT_L, &buff[0], 2);
2858 if (ret != 0)
2859 {
2860 return ret;
2861 }
2862
2863 *val = (int16_t)buff[1];
2864 *val = (*val * 256) + (int16_t)buff[0];
2865
2866 return ret;
2867 }
2868
2869 /**
2870 * @brief Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.[get]
2871 *
2872 * @param ctx read / write interface definitions
2873 * @param val Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.
2874 * @retval interface status (MANDATORY: return 0 -> no Error)
2875 *
2876 */
lsm6dsv16x_odr_cal_reg_get(const stmdev_ctx_t * ctx,int8_t * val)2877 int32_t lsm6dsv16x_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val)
2878 {
2879 lsm6dsv16x_internal_freq_t internal_freq;
2880 int32_t ret;
2881
2882 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1);
2883 *val = (int8_t)internal_freq.freq_fine;
2884
2885 return ret;
2886 }
2887
2888 /**
2889 * @brief Write buffer in a page.[set]
2890 *
2891 * @param ctx read / write interface definitions
2892 * @param val Write buffer in a page.
2893 * @retval interface status (MANDATORY: return 0 -> no Error)
2894 *
2895 */
lsm6dsv16x_ln_pg_write(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)2896 int32_t lsm6dsv16x_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address,
2897 uint8_t *buf, uint8_t len)
2898 {
2899 lsm6dsv16x_page_address_t page_address;
2900 lsm6dsv16x_page_sel_t page_sel;
2901 lsm6dsv16x_page_rw_t page_rw;
2902 uint8_t msb;
2903 uint8_t lsb;
2904 int32_t ret;
2905 uint8_t i ;
2906
2907 msb = ((uint8_t)(address >> 8) & 0x0FU);
2908 lsb = (uint8_t)address & 0xFFU;
2909
2910 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
2911 if (ret != 0)
2912 {
2913 return ret;
2914 }
2915
2916 /* set page write */
2917 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1);
2918 page_rw.page_read = PROPERTY_DISABLE;
2919 page_rw.page_write = PROPERTY_ENABLE;
2920 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1);
2921 if (ret != 0)
2922 {
2923 goto exit;
2924 }
2925
2926 /* select page */
2927 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2928 page_sel.page_sel = msb;
2929 page_sel.not_used0 = 1; // Default value
2930 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2931 if (ret != 0)
2932 {
2933 goto exit;
2934 }
2935
2936 /* set page addr */
2937 page_address.page_addr = lsb;
2938 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_ADDRESS,
2939 (uint8_t *)&page_address, 1);
2940 if (ret != 0)
2941 {
2942 goto exit;
2943 }
2944
2945 for (i = 0; ((i < len) && (ret == 0)); i++)
2946 {
2947 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_VALUE, &buf[i], 1);
2948 if (ret != 0)
2949 {
2950 goto exit;
2951 }
2952
2953 lsb++;
2954
2955 /* Check if page wrap */
2956 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
2957 {
2958 msb++;
2959 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2960 if (ret != 0)
2961 {
2962 goto exit;
2963 }
2964
2965 page_sel.page_sel = msb;
2966 page_sel.not_used0 = 1; // Default value
2967 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2968 if (ret != 0)
2969 {
2970 goto exit;
2971 }
2972 }
2973 }
2974
2975 page_sel.page_sel = 0;
2976 page_sel.not_used0 = 1;// Default value
2977 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
2978 if (ret != 0)
2979 {
2980 goto exit;
2981 }
2982
2983 /* unset page write */
2984 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1);
2985 page_rw.page_read = PROPERTY_DISABLE;
2986 page_rw.page_write = PROPERTY_DISABLE;
2987 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1);
2988
2989 exit:
2990 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
2991
2992 return ret;
2993 }
2994
2995 /**
2996 * @defgroup Common
2997 * @brief This section groups common useful functions.
2998 * @{/
2999 *
3000 */
3001
3002 /**
3003 * @brief Read buffer in a page.[set]
3004 *
3005 * @param ctx read / write interface definitions
3006 * @param val Write buffer in a page.
3007 * @retval interface status (MANDATORY: return 0 -> no Error)
3008 *
3009 */
lsm6dsv16x_ln_pg_read(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)3010 int32_t lsm6dsv16x_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf,
3011 uint8_t len)
3012 {
3013 lsm6dsv16x_page_address_t page_address;
3014 lsm6dsv16x_page_sel_t page_sel;
3015 lsm6dsv16x_page_rw_t page_rw;
3016 uint8_t msb;
3017 uint8_t lsb;
3018 int32_t ret;
3019 uint8_t i ;
3020
3021 msb = ((uint8_t)(address >> 8) & 0x0FU);
3022 lsb = (uint8_t)address & 0xFFU;
3023
3024 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
3025 if (ret != 0)
3026 {
3027 return ret;
3028 }
3029
3030 /* set page write */
3031 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1);
3032 page_rw.page_read = PROPERTY_ENABLE;
3033 page_rw.page_write = PROPERTY_DISABLE;
3034 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1);
3035 if (ret != 0)
3036 {
3037 goto exit;
3038 }
3039
3040 /* select page */
3041 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
3042 page_sel.page_sel = msb;
3043 page_sel.not_used0 = 1; // Default value
3044 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
3045 if (ret != 0)
3046 {
3047 goto exit;
3048 }
3049
3050 /* set page addr */
3051 page_address.page_addr = lsb;
3052 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_ADDRESS,
3053 (uint8_t *)&page_address, 1);
3054 if (ret != 0)
3055 {
3056 goto exit;
3057 }
3058
3059 for (i = 0; ((i < len) && (ret == 0)); i++)
3060 {
3061 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_VALUE, &buf[i], 1);
3062 if (ret != 0)
3063 {
3064 goto exit;
3065 }
3066
3067 lsb++;
3068
3069 /* Check if page wrap */
3070 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
3071 {
3072 msb++;
3073 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
3074 if (ret != 0)
3075 {
3076 goto exit;
3077 }
3078
3079 page_sel.page_sel = msb;
3080 page_sel.not_used0 = 1; // Default value
3081 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
3082 if (ret != 0)
3083 {
3084 goto exit;
3085 }
3086 }
3087 }
3088
3089 page_sel.page_sel = 0;
3090 page_sel.not_used0 = 1;// Default value
3091 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_SEL, (uint8_t *)&page_sel, 1);
3092 if (ret != 0)
3093 {
3094 goto exit;
3095 }
3096
3097 /* unset page write */
3098 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1);
3099 page_rw.page_read = PROPERTY_DISABLE;
3100 page_rw.page_write = PROPERTY_DISABLE;
3101 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PAGE_RW, (uint8_t *)&page_rw, 1);
3102
3103 exit:
3104 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
3105
3106 return ret;
3107 }
3108
3109 /**
3110 * @brief Enable debug mode for embedded functions [set]
3111 *
3112 * @param ctx read / write interface definitions
3113 * @param val 0, 1
3114 * @retval interface status (MANDATORY: return 0 -> no Error)
3115 *
3116 */
lsm6dsv16x_emb_function_dbg_set(const stmdev_ctx_t * ctx,uint8_t val)3117 int32_t lsm6dsv16x_emb_function_dbg_set(const stmdev_ctx_t *ctx, uint8_t val)
3118 {
3119 lsm6dsv16x_ctrl10_t ctrl10;
3120 int32_t ret;
3121
3122 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
3123
3124 if (ret == 0)
3125 {
3126 ctrl10.emb_func_debug = val;
3127 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
3128 }
3129
3130 return ret;
3131 }
3132
3133 /**
3134 * @brief Enable debug mode for embedded functions [get]
3135 *
3136 * @param ctx read / write interface definitions
3137 * @param val 0, 1
3138 * @retval interface status (MANDATORY: return 0 -> no Error)
3139 *
3140 */
lsm6dsv16x_emb_function_dbg_get(const stmdev_ctx_t * ctx,uint8_t * val)3141 int32_t lsm6dsv16x_emb_function_dbg_get(const stmdev_ctx_t *ctx, uint8_t *val)
3142 {
3143 lsm6dsv16x_ctrl10_t ctrl10;
3144 int32_t ret;
3145
3146 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
3147 if (ret != 0)
3148 {
3149 return ret;
3150 }
3151
3152 *val = ctrl10.emb_func_debug;
3153
3154 return ret;
3155 }
3156
3157 /**
3158 * @}
3159 *
3160 */
3161
3162 /**
3163 * @defgroup Data ENable (DEN)
3164 * @brief This section groups all the functions concerning
3165 * DEN functionality.
3166 * @{
3167 *
3168 */
3169
3170 /**
3171 * @brief It changes the polarity of INT2 pin input trigger for data enable (DEN) or embedded functions.[set]
3172 *
3173 * @param ctx read / write interface definitions
3174 * @param val DEN_ACT_LOW, DEN_ACT_HIGH,
3175 * @retval interface status (MANDATORY: return 0 -> no Error)
3176 *
3177 */
lsm6dsv16x_den_polarity_set(const stmdev_ctx_t * ctx,lsm6dsv16x_den_polarity_t val)3178 int32_t lsm6dsv16x_den_polarity_set(const stmdev_ctx_t *ctx,
3179 lsm6dsv16x_den_polarity_t val)
3180 {
3181 lsm6dsv16x_ctrl4_t ctrl4;
3182 int32_t ret;
3183
3184 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
3185
3186 if (ret == 0)
3187 {
3188 ctrl4.int2_in_lh = (uint8_t)val & 0x1U;
3189 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
3190 }
3191
3192 return ret;
3193 }
3194
3195 /**
3196 * @brief It changes the polarity of INT2 pin input trigger for data enable (DEN) or embedded functions.[get]
3197 *
3198 * @param ctx read / write interface definitions
3199 * @param val DEN_ACT_LOW, DEN_ACT_HIGH,
3200 * @retval interface status (MANDATORY: return 0 -> no Error)
3201 *
3202 */
lsm6dsv16x_den_polarity_get(const stmdev_ctx_t * ctx,lsm6dsv16x_den_polarity_t * val)3203 int32_t lsm6dsv16x_den_polarity_get(const stmdev_ctx_t *ctx,
3204 lsm6dsv16x_den_polarity_t *val)
3205 {
3206 lsm6dsv16x_ctrl4_t ctrl4;
3207 int32_t ret;
3208
3209 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
3210 if (ret != 0)
3211 {
3212 return ret;
3213 }
3214
3215 switch (ctrl4.int2_in_lh)
3216 {
3217 case LSM6DSV16X_DEN_ACT_LOW:
3218 *val = LSM6DSV16X_DEN_ACT_LOW;
3219 break;
3220
3221 case LSM6DSV16X_DEN_ACT_HIGH:
3222 *val = LSM6DSV16X_DEN_ACT_HIGH;
3223 break;
3224
3225 default:
3226 *val = LSM6DSV16X_DEN_ACT_LOW;
3227 break;
3228 }
3229
3230 return ret;
3231 }
3232
3233 /**
3234 * @brief Data ENable (DEN) configuration.[set]
3235 *
3236 * @param ctx read / write interface definitions
3237 * @param val Data ENable (DEN) configuration.
3238 * @retval interface status (MANDATORY: return 0 -> no Error)
3239 *
3240 */
lsm6dsv16x_den_conf_set(const stmdev_ctx_t * ctx,lsm6dsv16x_den_conf_t val)3241 int32_t lsm6dsv16x_den_conf_set(const stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t val)
3242 {
3243 lsm6dsv16x_den_t den;
3244 int32_t ret;
3245
3246 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_DEN, (uint8_t *)&den, 1);
3247 if (ret != 0)
3248 {
3249 return ret;
3250 }
3251
3252 den.den_z = val.den_z;
3253 den.den_y = val.den_y;
3254 den.den_x = val.den_x;
3255
3256 den.lvl2_en = (uint8_t)val.mode & 0x1U;
3257 den.lvl1_en = ((uint8_t)val.mode & 0x2U) >> 1;
3258
3259 if (val.stamp_in_gy_data == PROPERTY_ENABLE && val.stamp_in_xl_data == PROPERTY_ENABLE)
3260 {
3261 den.den_xl_g = PROPERTY_DISABLE;
3262 den.den_xl_en = PROPERTY_ENABLE;
3263 }
3264 else if (val.stamp_in_gy_data == PROPERTY_ENABLE && val.stamp_in_xl_data == PROPERTY_DISABLE)
3265 {
3266 den.den_xl_g = PROPERTY_DISABLE;
3267 den.den_xl_en = PROPERTY_DISABLE;
3268 }
3269 else if (val.stamp_in_gy_data == PROPERTY_DISABLE && val.stamp_in_xl_data == PROPERTY_ENABLE)
3270 {
3271 den.den_xl_g = PROPERTY_ENABLE;
3272 den.den_xl_en = PROPERTY_DISABLE;
3273 }
3274 else
3275 {
3276 den.den_xl_g = PROPERTY_DISABLE;
3277 den.den_xl_en = PROPERTY_DISABLE;
3278 den.den_z = PROPERTY_DISABLE;
3279 den.den_y = PROPERTY_DISABLE;
3280 den.den_x = PROPERTY_DISABLE;
3281 den.lvl2_en = PROPERTY_DISABLE;
3282 den.lvl1_en = PROPERTY_DISABLE;
3283 }
3284
3285 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_DEN, (uint8_t *)&den, 1);
3286
3287 return ret;
3288 }
3289
3290
3291 /**
3292 * @brief Data ENable (DEN) configuration.[get]
3293 *
3294 * @param ctx read / write interface definitions
3295 * @param val Data ENable (DEN) configuration.
3296 * @retval interface status (MANDATORY: return 0 -> no Error)
3297 *
3298 */
lsm6dsv16x_den_conf_get(const stmdev_ctx_t * ctx,lsm6dsv16x_den_conf_t * val)3299 int32_t lsm6dsv16x_den_conf_get(const stmdev_ctx_t *ctx, lsm6dsv16x_den_conf_t *val)
3300 {
3301 lsm6dsv16x_den_t den;
3302 int32_t ret;
3303
3304 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_DEN, (uint8_t *)&den, 1);
3305 if (ret != 0)
3306 {
3307 return ret;
3308 }
3309
3310 val->den_z = den.den_z;
3311 val->den_y = den.den_y;
3312 val->den_x = den.den_x;
3313
3314 if ((den.den_x | den.den_y | den.den_z) == PROPERTY_ENABLE)
3315 {
3316 if (den.den_xl_g == PROPERTY_DISABLE && den.den_xl_en == PROPERTY_ENABLE)
3317 {
3318 val->stamp_in_gy_data = PROPERTY_ENABLE;
3319 val->stamp_in_xl_data = PROPERTY_ENABLE;
3320 }
3321 else if (den.den_xl_g == PROPERTY_DISABLE && den.den_xl_en == PROPERTY_DISABLE)
3322 {
3323 val->stamp_in_gy_data = PROPERTY_ENABLE;
3324 val->stamp_in_xl_data = PROPERTY_DISABLE;
3325 }
3326 else // ( (den.den_xl_g & !den.den_xl_en) == PROPERTY_ENABLE )
3327 {
3328 val->stamp_in_gy_data = PROPERTY_DISABLE;
3329 val->stamp_in_xl_data = PROPERTY_ENABLE;
3330 }
3331 }
3332 else
3333 {
3334 val->stamp_in_gy_data = PROPERTY_DISABLE;
3335 val->stamp_in_xl_data = PROPERTY_DISABLE;
3336 }
3337
3338 switch ((den.lvl1_en << 1) + den.lvl2_en)
3339 {
3340 case LSM6DSV16X_LEVEL_TRIGGER:
3341 val->mode = LSM6DSV16X_LEVEL_TRIGGER;
3342 break;
3343
3344 case LSM6DSV16X_LEVEL_LATCHED:
3345 val->mode = LSM6DSV16X_LEVEL_LATCHED;
3346 break;
3347
3348 default:
3349 val->mode = LSM6DSV16X_DEN_NOT_DEFINED;
3350 break;
3351 }
3352
3353 return ret;
3354 }
3355
3356 /**
3357 * @}
3358 *
3359 */
3360
3361 /**
3362 * @defgroup Electronic Image Stabilization (EIS)
3363 * @brief Electronic Image Stabilization (EIS)
3364 * @{/
3365 *
3366 */
3367
3368 /**
3369 * @brief Gyroscope full-scale selection for EIS channel. WARNING: 4000dps will be available only if also User Interface chain is set to 4000dps[set]
3370 *
3371 * @param ctx read / write interface definitions
3372 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
3373 * @retval interface status (MANDATORY: return 0 -> no Error)
3374 *
3375 */
lsm6dsv16x_eis_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv16x_eis_gy_full_scale_t val)3376 int32_t lsm6dsv16x_eis_gy_full_scale_set(const stmdev_ctx_t *ctx,
3377 lsm6dsv16x_eis_gy_full_scale_t val)
3378 {
3379 lsm6dsv16x_ctrl_eis_t ctrl_eis;
3380 int32_t ret;
3381
3382 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3383
3384 if (ret == 0)
3385 {
3386 ctrl_eis.fs_g_eis = (uint8_t)val & 0x7U;
3387 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3388 }
3389
3390 return ret;
3391 }
3392
3393 /**
3394 * @brief Gyroscope full-scale selection for EIS channel. WARNING: 4000dps will be available only if also User Interface chain is set to 4000dps[get]
3395 *
3396 * @param ctx read / write interface definitions
3397 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps
3398 * @retval interface status (MANDATORY: return 0 -> no Error)
3399 *
3400 */
lsm6dsv16x_eis_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv16x_eis_gy_full_scale_t * val)3401 int32_t lsm6dsv16x_eis_gy_full_scale_get(const stmdev_ctx_t *ctx,
3402 lsm6dsv16x_eis_gy_full_scale_t *val)
3403 {
3404 lsm6dsv16x_ctrl_eis_t ctrl_eis;
3405 int32_t ret;
3406
3407 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3408 if (ret != 0)
3409 {
3410 return ret;
3411 }
3412
3413 switch (ctrl_eis.fs_g_eis)
3414 {
3415 case LSM6DSV16X_EIS_125dps:
3416 *val = LSM6DSV16X_EIS_125dps;
3417 break;
3418
3419 case LSM6DSV16X_EIS_250dps:
3420 *val = LSM6DSV16X_EIS_250dps;
3421 break;
3422
3423 case LSM6DSV16X_EIS_500dps:
3424 *val = LSM6DSV16X_EIS_500dps;
3425 break;
3426
3427 case LSM6DSV16X_EIS_1000dps:
3428 *val = LSM6DSV16X_EIS_1000dps;
3429 break;
3430
3431 case LSM6DSV16X_EIS_2000dps:
3432 *val = LSM6DSV16X_EIS_2000dps;
3433 break;
3434
3435 default:
3436 *val = LSM6DSV16X_EIS_125dps;
3437 break;
3438 }
3439 return ret;
3440 }
3441
3442 /**
3443 * @brief Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).[set]
3444 *
3445 * @param ctx read / write interface definitions
3446 * @param val Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).
3447 * @retval interface status (MANDATORY: return 0 -> no Error)
3448 *
3449 */
lsm6dsv16x_eis_gy_on_spi2_set(const stmdev_ctx_t * ctx,uint8_t val)3450 int32_t lsm6dsv16x_eis_gy_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val)
3451 {
3452 lsm6dsv16x_ctrl_eis_t ctrl_eis;
3453 int32_t ret;
3454
3455 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3456
3457 if (ret == 0)
3458 {
3459 ctrl_eis.g_eis_on_g_ois_out_reg = val;
3460 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3461 }
3462
3463 return ret;
3464 }
3465
3466 /**
3467 * @brief Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).[get]
3468 *
3469 * @param ctx read / write interface definitions
3470 * @param val Enables routing of gyroscope EIS outputs on SPI2 (OIS interface). The gyroscope data on SPI2 (OIS interface) cannot be read from User Interface (UI).
3471 * @retval interface status (MANDATORY: return 0 -> no Error)
3472 *
3473 */
lsm6dsv16x_eis_gy_on_spi2_get(const stmdev_ctx_t * ctx,uint8_t * val)3474 int32_t lsm6dsv16x_eis_gy_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val)
3475 {
3476 lsm6dsv16x_ctrl_eis_t ctrl_eis;
3477 int32_t ret;
3478
3479 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3480 *val = ctrl_eis.g_eis_on_g_ois_out_reg;
3481
3482 return ret;
3483 }
3484
3485 /**
3486 * @brief Enables and selects the ODR of the gyroscope EIS channel.[set]
3487 *
3488 * @param ctx read / write interface definitions
3489 * @param val EIS_1920Hz, EIS_960Hz,
3490 * @retval interface status (MANDATORY: return 0 -> no Error)
3491 *
3492 */
lsm6dsv16x_gy_eis_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv16x_gy_eis_data_rate_t val)3493 int32_t lsm6dsv16x_gy_eis_data_rate_set(const stmdev_ctx_t *ctx,
3494 lsm6dsv16x_gy_eis_data_rate_t val)
3495 {
3496 lsm6dsv16x_ctrl_eis_t ctrl_eis;
3497 int32_t ret;
3498
3499 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3500
3501 if (ret == 0)
3502 {
3503 ctrl_eis.odr_g_eis = (uint8_t)val & 0x03U;
3504 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3505 }
3506
3507 return ret;
3508 }
3509
3510 /**
3511 * @brief Enables and selects the ODR of the gyroscope EIS channel.[get]
3512 *
3513 * @param ctx read / write interface definitions
3514 * @param val EIS_1920Hz, EIS_960Hz,
3515 * @retval interface status (MANDATORY: return 0 -> no Error)
3516 *
3517 */
lsm6dsv16x_gy_eis_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv16x_gy_eis_data_rate_t * val)3518 int32_t lsm6dsv16x_gy_eis_data_rate_get(const stmdev_ctx_t *ctx,
3519 lsm6dsv16x_gy_eis_data_rate_t *val)
3520 {
3521 lsm6dsv16x_ctrl_eis_t ctrl_eis;
3522 int32_t ret;
3523
3524 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
3525 if (ret != 0)
3526 {
3527 return ret;
3528 }
3529
3530 switch (ctrl_eis.odr_g_eis)
3531 {
3532 case LSM6DSV16X_EIS_ODR_OFF:
3533 *val = LSM6DSV16X_EIS_ODR_OFF;
3534 break;
3535
3536 case LSM6DSV16X_EIS_1920Hz:
3537 *val = LSM6DSV16X_EIS_1920Hz;
3538 break;
3539
3540 case LSM6DSV16X_EIS_960Hz:
3541 *val = LSM6DSV16X_EIS_960Hz;
3542 break;
3543
3544 default:
3545 *val = LSM6DSV16X_EIS_1920Hz;
3546 break;
3547 }
3548
3549 return ret;
3550 }
3551
3552 /**
3553 * @}
3554 *
3555 */
3556
3557 /**
3558 * @defgroup FIFO
3559 * @brief This section group all the functions concerning the FIFO usage
3560 * @{
3561 *
3562 */
3563
3564 /**
3565 * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[set]
3566 *
3567 * @param ctx read / write interface definitions
3568 * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).
3569 * @retval interface status (MANDATORY: return 0 -> no Error)
3570 *
3571 */
lsm6dsv16x_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)3572 int32_t lsm6dsv16x_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
3573 {
3574 lsm6dsv16x_fifo_ctrl1_t fifo_ctrl1;
3575 int32_t ret;
3576
3577 fifo_ctrl1.wtm = val;
3578 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
3579
3580 return ret;
3581 }
3582
3583 /**
3584 * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[get]
3585 *
3586 * @param ctx read / write interface definitions
3587 * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).
3588 * @retval interface status (MANDATORY: return 0 -> no Error)
3589 *
3590 */
lsm6dsv16x_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)3591 int32_t lsm6dsv16x_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
3592 {
3593 lsm6dsv16x_fifo_ctrl1_t fifo_ctrl1;
3594 int32_t ret;
3595
3596 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
3597 *val = fifo_ctrl1.wtm;
3598
3599 return ret;
3600 }
3601
3602 /**
3603 * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[set]
3604 *
3605 * @param ctx read / write interface definitions
3606 * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.
3607 * @retval interface status (MANDATORY: return 0 -> no Error)
3608 *
3609 */
lsm6dsv16x_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t * ctx,uint8_t val)3610 int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
3611 {
3612 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3613 int32_t ret;
3614
3615 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3616 if (ret == 0)
3617 {
3618 fifo_ctrl2.xl_dualc_batch_from_fsm = val;
3619 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3620 }
3621
3622 return ret;
3623 }
3624
3625 /**
3626 * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[get]
3627 *
3628 * @param ctx read / write interface definitions
3629 * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.
3630 * @retval interface status (MANDATORY: return 0 -> no Error)
3631 *
3632 */
lsm6dsv16x_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)3633 int32_t lsm6dsv16x_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
3634 {
3635 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3636 int32_t ret;
3637
3638 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3639 *val = fifo_ctrl2.xl_dualc_batch_from_fsm;
3640
3641 return ret;
3642 }
3643
3644 /**
3645 * @brief It configures the compression algorithm to write non-compressed data at each rate.[set]
3646 *
3647 * @param ctx read / write interface definitions
3648 * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1,
3649 * @retval interface status (MANDATORY: return 0 -> no Error)
3650 *
3651 */
lsm6dsv16x_fifo_compress_algo_set(const stmdev_ctx_t * ctx,lsm6dsv16x_fifo_compress_algo_t val)3652 int32_t lsm6dsv16x_fifo_compress_algo_set(const stmdev_ctx_t *ctx,
3653 lsm6dsv16x_fifo_compress_algo_t val)
3654 {
3655 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3656 int32_t ret;
3657
3658 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3659 if (ret == 0)
3660 {
3661 fifo_ctrl2.uncompr_rate = (uint8_t)val & 0x03U;
3662 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3663 }
3664
3665 return ret;
3666 }
3667
3668 /**
3669 * @brief It configures the compression algorithm to write non-compressed data at each rate.[get]
3670 *
3671 * @param ctx read / write interface definitions
3672 * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1,
3673 * @retval interface status (MANDATORY: return 0 -> no Error)
3674 *
3675 */
lsm6dsv16x_fifo_compress_algo_get(const stmdev_ctx_t * ctx,lsm6dsv16x_fifo_compress_algo_t * val)3676 int32_t lsm6dsv16x_fifo_compress_algo_get(const stmdev_ctx_t *ctx,
3677 lsm6dsv16x_fifo_compress_algo_t *val)
3678 {
3679 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3680 int32_t ret;
3681
3682 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3683 if (ret != 0)
3684 {
3685 return ret;
3686 }
3687
3688 switch (fifo_ctrl2.uncompr_rate)
3689 {
3690 case LSM6DSV16X_CMP_DISABLE:
3691 *val = LSM6DSV16X_CMP_DISABLE;
3692 break;
3693
3694 case LSM6DSV16X_CMP_8_TO_1:
3695 *val = LSM6DSV16X_CMP_8_TO_1;
3696 break;
3697
3698 case LSM6DSV16X_CMP_16_TO_1:
3699 *val = LSM6DSV16X_CMP_16_TO_1;
3700 break;
3701
3702 case LSM6DSV16X_CMP_32_TO_1:
3703 *val = LSM6DSV16X_CMP_32_TO_1;
3704 break;
3705
3706 default:
3707 *val = LSM6DSV16X_CMP_DISABLE;
3708 break;
3709 }
3710 return ret;
3711 }
3712
3713 /**
3714 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
3715 *
3716 * @param ctx read / write interface definitions
3717 * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO.
3718 * @retval interface status (MANDATORY: return 0 -> no Error)
3719 *
3720 */
lsm6dsv16x_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t * ctx,uint8_t val)3721 int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, uint8_t val)
3722 {
3723 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3724 int32_t ret;
3725
3726 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3727 if (ret == 0)
3728 {
3729 fifo_ctrl2.odr_chg_en = val;
3730 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3731 }
3732
3733 return ret;
3734 }
3735
3736 /**
3737 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
3738 *
3739 * @param ctx read / write interface definitions
3740 * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO.
3741 * @retval interface status (MANDATORY: return 0 -> no Error)
3742 *
3743 */
lsm6dsv16x_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t * ctx,uint8_t * val)3744 int32_t lsm6dsv16x_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx,
3745 uint8_t *val)
3746 {
3747 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3748 int32_t ret;
3749
3750 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3751 *val = fifo_ctrl2.odr_chg_en;
3752
3753 return ret;
3754 }
3755
3756 /**
3757 * @brief Enables/Disables compression algorithm runtime.[set]
3758 *
3759 * @param ctx read / write interface definitions
3760 * @param val Enables/Disables compression algorithm runtime.
3761 * @retval interface status (MANDATORY: return 0 -> no Error)
3762 *
3763 */
lsm6dsv16x_fifo_compress_algo_real_time_set(const stmdev_ctx_t * ctx,uint8_t val)3764 int32_t lsm6dsv16x_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx,
3765 uint8_t val)
3766 {
3767 lsm6dsv16x_emb_func_en_b_t emb_func_en_b;
3768 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3769
3770 int32_t ret;
3771
3772 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3773 fifo_ctrl2.fifo_compr_rt_en = val;
3774 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3775 if (ret != 0)
3776 {
3777 return ret;
3778 }
3779
3780 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
3781 if (ret != 0)
3782 {
3783 return ret;
3784 }
3785
3786 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
3787 emb_func_en_b.fifo_compr_en = val;
3788 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
3789 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
3790
3791 return ret;
3792 }
3793
3794 /**
3795 * @brief Enables/Disables compression algorithm runtime.[get]
3796 *
3797 * @param ctx read / write interface definitions
3798 * @param val Enables/Disables compression algorithm runtime.
3799 * @retval interface status (MANDATORY: return 0 -> no Error)
3800 *
3801 */
lsm6dsv16x_fifo_compress_algo_real_time_get(const stmdev_ctx_t * ctx,uint8_t * val)3802 int32_t lsm6dsv16x_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx,
3803 uint8_t *val)
3804 {
3805 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3806 int32_t ret;
3807
3808 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3809
3810 *val = fifo_ctrl2.fifo_compr_rt_en;
3811
3812 return ret;
3813 }
3814
3815 /**
3816 * @brief Sensing chain FIFO stop values memorization at threshold level.[set]
3817 *
3818 * @param ctx read / write interface definitions
3819 * @param val Sensing chain FIFO stop values memorization at threshold level.
3820 * @retval interface status (MANDATORY: return 0 -> no Error)
3821 *
3822 */
lsm6dsv16x_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)3823 int32_t lsm6dsv16x_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
3824 {
3825 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3826 int32_t ret;
3827
3828 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3829 if (ret == 0)
3830 {
3831 fifo_ctrl2.stop_on_wtm = val;
3832 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3833 }
3834
3835 return ret;
3836 }
3837
3838 /**
3839 * @brief Sensing chain FIFO stop values memorization at threshold level.[get]
3840 *
3841 * @param ctx read / write interface definitions
3842 * @param val Sensing chain FIFO stop values memorization at threshold level.
3843 * @retval interface status (MANDATORY: return 0 -> no Error)
3844 *
3845 */
lsm6dsv16x_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)3846 int32_t lsm6dsv16x_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val)
3847 {
3848 lsm6dsv16x_fifo_ctrl2_t fifo_ctrl2;
3849 int32_t ret;
3850
3851 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
3852 *val = fifo_ctrl2.stop_on_wtm;
3853
3854 return ret;
3855 }
3856
3857 /**
3858 * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[set]
3859 *
3860 * @param ctx read / write interface definitions
3861 * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz,
3862 * @retval interface status (MANDATORY: return 0 -> no Error)
3863 *
3864 */
lsm6dsv16x_fifo_xl_batch_set(const stmdev_ctx_t * ctx,lsm6dsv16x_fifo_xl_batch_t val)3865 int32_t lsm6dsv16x_fifo_xl_batch_set(const stmdev_ctx_t *ctx,
3866 lsm6dsv16x_fifo_xl_batch_t val)
3867 {
3868 lsm6dsv16x_fifo_ctrl3_t fifo_ctrl3;
3869 int32_t ret;
3870
3871 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3872 if (ret == 0)
3873 {
3874 fifo_ctrl3.bdr_xl = (uint8_t)val & 0xFu;
3875 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3876 }
3877
3878 return ret;
3879 }
3880
3881 /**
3882 * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[get]
3883 *
3884 * @param ctx read / write interface definitions
3885 * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz,
3886 * @retval interface status (MANDATORY: return 0 -> no Error)
3887 *
3888 */
lsm6dsv16x_fifo_xl_batch_get(const stmdev_ctx_t * ctx,lsm6dsv16x_fifo_xl_batch_t * val)3889 int32_t lsm6dsv16x_fifo_xl_batch_get(const stmdev_ctx_t *ctx,
3890 lsm6dsv16x_fifo_xl_batch_t *val)
3891 {
3892 lsm6dsv16x_fifo_ctrl3_t fifo_ctrl3;
3893 int32_t ret;
3894
3895 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3896 if (ret != 0)
3897 {
3898 return ret;
3899 }
3900
3901 switch (fifo_ctrl3.bdr_xl)
3902 {
3903 case LSM6DSV16X_XL_NOT_BATCHED:
3904 *val = LSM6DSV16X_XL_NOT_BATCHED;
3905 break;
3906
3907 case LSM6DSV16X_XL_BATCHED_AT_1Hz875:
3908 *val = LSM6DSV16X_XL_BATCHED_AT_1Hz875;
3909 break;
3910
3911 case LSM6DSV16X_XL_BATCHED_AT_7Hz5:
3912 *val = LSM6DSV16X_XL_BATCHED_AT_7Hz5;
3913 break;
3914
3915 case LSM6DSV16X_XL_BATCHED_AT_15Hz:
3916 *val = LSM6DSV16X_XL_BATCHED_AT_15Hz;
3917 break;
3918
3919 case LSM6DSV16X_XL_BATCHED_AT_30Hz:
3920 *val = LSM6DSV16X_XL_BATCHED_AT_30Hz;
3921 break;
3922
3923 case LSM6DSV16X_XL_BATCHED_AT_60Hz:
3924 *val = LSM6DSV16X_XL_BATCHED_AT_60Hz;
3925 break;
3926
3927 case LSM6DSV16X_XL_BATCHED_AT_120Hz:
3928 *val = LSM6DSV16X_XL_BATCHED_AT_120Hz;
3929 break;
3930
3931 case LSM6DSV16X_XL_BATCHED_AT_240Hz:
3932 *val = LSM6DSV16X_XL_BATCHED_AT_240Hz;
3933 break;
3934
3935 case LSM6DSV16X_XL_BATCHED_AT_480Hz:
3936 *val = LSM6DSV16X_XL_BATCHED_AT_480Hz;
3937 break;
3938
3939 case LSM6DSV16X_XL_BATCHED_AT_960Hz:
3940 *val = LSM6DSV16X_XL_BATCHED_AT_960Hz;
3941 break;
3942
3943 case LSM6DSV16X_XL_BATCHED_AT_1920Hz:
3944 *val = LSM6DSV16X_XL_BATCHED_AT_1920Hz;
3945 break;
3946
3947 case LSM6DSV16X_XL_BATCHED_AT_3840Hz:
3948 *val = LSM6DSV16X_XL_BATCHED_AT_3840Hz;
3949 break;
3950
3951 case LSM6DSV16X_XL_BATCHED_AT_7680Hz:
3952 *val = LSM6DSV16X_XL_BATCHED_AT_7680Hz;
3953 break;
3954
3955 default:
3956 *val = LSM6DSV16X_XL_NOT_BATCHED;
3957 break;
3958 }
3959
3960 return ret;
3961 }
3962
3963 /**
3964 * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[set]
3965 *
3966 * @param ctx read / write interface definitions
3967 * @param val GY_NOT_BATCHED, GY_BATCHED_AT_1Hz875, GY_BATCHED_AT_7Hz5, GY_BATCHED_AT_15Hz, GY_BATCHED_AT_30Hz, GY_BATCHED_AT_60Hz, GY_BATCHED_AT_120Hz, GY_BATCHED_AT_240Hz, GY_BATCHED_AT_480Hz, GY_BATCHED_AT_960Hz, GY_BATCHED_AT_1920Hz, GY_BATCHED_AT_3840Hz, GY_BATCHED_AT_7680Hz,
3968 * @retval interface status (MANDATORY: return 0 -> no Error)
3969 *
3970 */
lsm6dsv16x_fifo_gy_batch_set(const stmdev_ctx_t * ctx,lsm6dsv16x_fifo_gy_batch_t val)3971 int32_t lsm6dsv16x_fifo_gy_batch_set(const stmdev_ctx_t *ctx,
3972 lsm6dsv16x_fifo_gy_batch_t val)
3973 {
3974 lsm6dsv16x_fifo_ctrl3_t fifo_ctrl3;
3975 int32_t ret;
3976
3977 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3978 if (ret == 0)
3979 {
3980 fifo_ctrl3.bdr_gy = (uint8_t)val & 0x0Fu;
3981 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
3982 }
3983
3984 return ret;
3985 }
3986
3987 /**
3988 * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[get]
3989 *
3990 * @param ctx read / write interface definitions
3991 * @param val GY_NOT_BATCHED, GY_BATCHED_AT_1Hz875, GY_BATCHED_AT_7Hz5, GY_BATCHED_AT_15Hz, GY_BATCHED_AT_30Hz, GY_BATCHED_AT_60Hz, GY_BATCHED_AT_120Hz, GY_BATCHED_AT_240Hz, GY_BATCHED_AT_480Hz, GY_BATCHED_AT_960Hz, GY_BATCHED_AT_1920Hz, GY_BATCHED_AT_3840Hz, GY_BATCHED_AT_7680Hz,
3992 * @retval interface status (MANDATORY: return 0 -> no Error)
3993 *
3994 */
lsm6dsv16x_fifo_gy_batch_get(const stmdev_ctx_t * ctx,lsm6dsv16x_fifo_gy_batch_t * val)3995 int32_t lsm6dsv16x_fifo_gy_batch_get(const stmdev_ctx_t *ctx,
3996 lsm6dsv16x_fifo_gy_batch_t *val)
3997 {
3998 lsm6dsv16x_fifo_ctrl3_t fifo_ctrl3;
3999 int32_t ret;
4000
4001 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
4002 if (ret != 0)
4003 {
4004 return ret;
4005 }
4006
4007 switch (fifo_ctrl3.bdr_gy)
4008 {
4009 case LSM6DSV16X_GY_NOT_BATCHED:
4010 *val = LSM6DSV16X_GY_NOT_BATCHED;
4011 break;
4012
4013 case LSM6DSV16X_GY_BATCHED_AT_1Hz875:
4014 *val = LSM6DSV16X_GY_BATCHED_AT_1Hz875;
4015 break;
4016
4017 case LSM6DSV16X_GY_BATCHED_AT_7Hz5:
4018 *val = LSM6DSV16X_GY_BATCHED_AT_7Hz5;
4019 break;
4020
4021 case LSM6DSV16X_GY_BATCHED_AT_15Hz:
4022 *val = LSM6DSV16X_GY_BATCHED_AT_15Hz;
4023 break;
4024
4025 case LSM6DSV16X_GY_BATCHED_AT_30Hz:
4026 *val = LSM6DSV16X_GY_BATCHED_AT_30Hz;
4027 break;
4028
4029 case LSM6DSV16X_GY_BATCHED_AT_60Hz:
4030 *val = LSM6DSV16X_GY_BATCHED_AT_60Hz;
4031 break;
4032
4033 case LSM6DSV16X_GY_BATCHED_AT_120Hz:
4034 *val = LSM6DSV16X_GY_BATCHED_AT_120Hz;
4035 break;
4036
4037 case LSM6DSV16X_GY_BATCHED_AT_240Hz:
4038 *val = LSM6DSV16X_GY_BATCHED_AT_240Hz;
4039 break;
4040
4041 case LSM6DSV16X_GY_BATCHED_AT_480Hz:
4042 *val = LSM6DSV16X_GY_BATCHED_AT_480Hz;
4043 break;
4044
4045 case LSM6DSV16X_GY_BATCHED_AT_960Hz:
4046 *val = LSM6DSV16X_GY_BATCHED_AT_960Hz;
4047 break;
4048
4049 case LSM6DSV16X_GY_BATCHED_AT_1920Hz:
4050 *val = LSM6DSV16X_GY_BATCHED_AT_1920Hz;
4051 break;
4052
4053 case LSM6DSV16X_GY_BATCHED_AT_3840Hz:
4054 *val = LSM6DSV16X_GY_BATCHED_AT_3840Hz;
4055 break;
4056
4057 case LSM6DSV16X_GY_BATCHED_AT_7680Hz:
4058 *val = LSM6DSV16X_GY_BATCHED_AT_7680Hz;
4059 break;
4060
4061 default:
4062 *val = LSM6DSV16X_GY_NOT_BATCHED;
4063 break;
4064 }
4065 return ret;
4066 }
4067
4068
4069 /**
4070 * @brief FIFO mode selection.[set]
4071 *
4072 * @param ctx read / write interface definitions
4073 * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
4074 * @retval interface status (MANDATORY: return 0 -> no Error)
4075 *
4076 */
lsm6dsv16x_fifo_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16x_fifo_mode_t val)4077 int32_t lsm6dsv16x_fifo_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_mode_t val)
4078 {
4079 lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4;
4080 int32_t ret;
4081
4082 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4083 if (ret == 0)
4084 {
4085 fifo_ctrl4.fifo_mode = (uint8_t)val & 0x07U;
4086 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4087 }
4088
4089 return ret;
4090 }
4091
4092 /**
4093 * @brief FIFO mode selection.[get]
4094 *
4095 * @param ctx read / write interface definitions
4096 * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
4097 * @retval interface status (MANDATORY: return 0 -> no Error)
4098 *
4099 */
lsm6dsv16x_fifo_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16x_fifo_mode_t * val)4100 int32_t lsm6dsv16x_fifo_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fifo_mode_t *val)
4101 {
4102 lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4;
4103 int32_t ret;
4104
4105 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4106 if (ret != 0)
4107 {
4108 return ret;
4109 }
4110
4111 switch (fifo_ctrl4.fifo_mode)
4112 {
4113 case LSM6DSV16X_BYPASS_MODE:
4114 *val = LSM6DSV16X_BYPASS_MODE;
4115 break;
4116
4117 case LSM6DSV16X_FIFO_MODE:
4118 *val = LSM6DSV16X_FIFO_MODE;
4119 break;
4120
4121 case LSM6DSV16X_STREAM_WTM_TO_FULL_MODE:
4122 *val = LSM6DSV16X_STREAM_WTM_TO_FULL_MODE;
4123 break;
4124
4125 case LSM6DSV16X_STREAM_TO_FIFO_MODE:
4126 *val = LSM6DSV16X_STREAM_TO_FIFO_MODE;
4127 break;
4128
4129 case LSM6DSV16X_BYPASS_TO_STREAM_MODE:
4130 *val = LSM6DSV16X_BYPASS_TO_STREAM_MODE;
4131 break;
4132
4133 case LSM6DSV16X_STREAM_MODE:
4134 *val = LSM6DSV16X_STREAM_MODE;
4135 break;
4136
4137 case LSM6DSV16X_BYPASS_TO_FIFO_MODE:
4138 *val = LSM6DSV16X_BYPASS_TO_FIFO_MODE;
4139 break;
4140
4141 default:
4142 *val = LSM6DSV16X_BYPASS_MODE;
4143 break;
4144 }
4145 return ret;
4146 }
4147
4148 /**
4149 * @brief Enables FIFO batching of EIS gyroscope output values.[set]
4150 *
4151 * @param ctx read / write interface definitions
4152 * @param val Enables FIFO batching of EIS gyroscope output values.
4153 * @retval interface status (MANDATORY: return 0 -> no Error)
4154 *
4155 */
lsm6dsv16x_fifo_gy_eis_batch_set(const stmdev_ctx_t * ctx,uint8_t val)4156 int32_t lsm6dsv16x_fifo_gy_eis_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
4157 {
4158 lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4;
4159 int32_t ret;
4160
4161 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4162 if (ret == 0)
4163 {
4164 fifo_ctrl4.g_eis_fifo_en = val;
4165 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4166 }
4167
4168 return ret;
4169 }
4170
4171 /**
4172 * @brief Enables FIFO batching of EIS gyroscope output values.[get]
4173 *
4174 * @param ctx read / write interface definitions
4175 * @param val Enables FIFO batching of EIS gyroscope output values.
4176 * @retval interface status (MANDATORY: return 0 -> no Error)
4177 *
4178 */
lsm6dsv16x_fifo_gy_eis_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)4179 int32_t lsm6dsv16x_fifo_gy_eis_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
4180 {
4181 lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4;
4182 int32_t ret;
4183
4184 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4185 *val = fifo_ctrl4.g_eis_fifo_en;
4186
4187 return ret;
4188 }
4189
4190 /**
4191 * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[set]
4192 *
4193 * @param ctx read / write interface definitions
4194 * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz,
4195 * @retval interface status (MANDATORY: return 0 -> no Error)
4196 *
4197 */
lsm6dsv16x_fifo_temp_batch_set(const stmdev_ctx_t * ctx,lsm6dsv16x_fifo_temp_batch_t val)4198 int32_t lsm6dsv16x_fifo_temp_batch_set(const stmdev_ctx_t *ctx,
4199 lsm6dsv16x_fifo_temp_batch_t val)
4200 {
4201 lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4;
4202 int32_t ret;
4203
4204 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4205 if (ret == 0)
4206 {
4207 fifo_ctrl4.odr_t_batch = (uint8_t)val & 0x03U;
4208 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4209 }
4210
4211 return ret;
4212 }
4213
4214 /**
4215 * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[get]
4216 *
4217 * @param ctx read / write interface definitions
4218 * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz,
4219 * @retval interface status (MANDATORY: return 0 -> no Error)
4220 *
4221 */
lsm6dsv16x_fifo_temp_batch_get(const stmdev_ctx_t * ctx,lsm6dsv16x_fifo_temp_batch_t * val)4222 int32_t lsm6dsv16x_fifo_temp_batch_get(const stmdev_ctx_t *ctx,
4223 lsm6dsv16x_fifo_temp_batch_t *val)
4224 {
4225 lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4;
4226 int32_t ret;
4227
4228 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4229 if (ret != 0)
4230 {
4231 return ret;
4232 }
4233
4234 switch (fifo_ctrl4.odr_t_batch)
4235 {
4236 case LSM6DSV16X_TEMP_NOT_BATCHED:
4237 *val = LSM6DSV16X_TEMP_NOT_BATCHED;
4238 break;
4239
4240 case LSM6DSV16X_TEMP_BATCHED_AT_1Hz875:
4241 *val = LSM6DSV16X_TEMP_BATCHED_AT_1Hz875;
4242 break;
4243
4244 case LSM6DSV16X_TEMP_BATCHED_AT_15Hz:
4245 *val = LSM6DSV16X_TEMP_BATCHED_AT_15Hz;
4246 break;
4247
4248 case LSM6DSV16X_TEMP_BATCHED_AT_60Hz:
4249 *val = LSM6DSV16X_TEMP_BATCHED_AT_60Hz;
4250 break;
4251
4252 default:
4253 *val = LSM6DSV16X_TEMP_NOT_BATCHED;
4254 break;
4255 }
4256 return ret;
4257 }
4258
4259 /**
4260 * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[set]
4261 *
4262 * @param ctx read / write interface definitions
4263 * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32,
4264 * @retval interface status (MANDATORY: return 0 -> no Error)
4265 *
4266 */
lsm6dsv16x_fifo_timestamp_batch_set(const stmdev_ctx_t * ctx,lsm6dsv16x_fifo_timestamp_batch_t val)4267 int32_t lsm6dsv16x_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx,
4268 lsm6dsv16x_fifo_timestamp_batch_t val)
4269 {
4270 lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4;
4271 int32_t ret;
4272
4273 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4274 if (ret == 0)
4275 {
4276 fifo_ctrl4.dec_ts_batch = (uint8_t)val & 0x03U;
4277 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4278 }
4279
4280 return ret;
4281 }
4282
4283 /**
4284 * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[get]
4285 *
4286 * @param ctx read / write interface definitions
4287 * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32,
4288 * @retval interface status (MANDATORY: return 0 -> no Error)
4289 *
4290 */
lsm6dsv16x_fifo_timestamp_batch_get(const stmdev_ctx_t * ctx,lsm6dsv16x_fifo_timestamp_batch_t * val)4291 int32_t lsm6dsv16x_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx,
4292 lsm6dsv16x_fifo_timestamp_batch_t *val)
4293 {
4294 lsm6dsv16x_fifo_ctrl4_t fifo_ctrl4;
4295 int32_t ret;
4296
4297 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
4298 if (ret != 0)
4299 {
4300 return ret;
4301 }
4302
4303 switch (fifo_ctrl4.dec_ts_batch)
4304 {
4305 case LSM6DSV16X_TMSTMP_NOT_BATCHED:
4306 *val = LSM6DSV16X_TMSTMP_NOT_BATCHED;
4307 break;
4308
4309 case LSM6DSV16X_TMSTMP_DEC_1:
4310 *val = LSM6DSV16X_TMSTMP_DEC_1;
4311 break;
4312
4313 case LSM6DSV16X_TMSTMP_DEC_8:
4314 *val = LSM6DSV16X_TMSTMP_DEC_8;
4315 break;
4316
4317 case LSM6DSV16X_TMSTMP_DEC_32:
4318 *val = LSM6DSV16X_TMSTMP_DEC_32;
4319 break;
4320
4321 default:
4322 *val = LSM6DSV16X_TMSTMP_NOT_BATCHED;
4323 break;
4324 }
4325
4326 return ret;
4327 }
4328
4329 /**
4330 * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[set]
4331 *
4332 * @param ctx read / write interface definitions
4333 * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.
4334 * @retval interface status (MANDATORY: return 0 -> no Error)
4335 *
4336 */
lsm6dsv16x_fifo_batch_counter_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)4337 int32_t lsm6dsv16x_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx,
4338 uint16_t val)
4339 {
4340 lsm6dsv16x_counter_bdr_reg1_t counter_bdr_reg1;
4341 lsm6dsv16x_counter_bdr_reg2_t counter_bdr_reg2;
4342 int32_t ret;
4343
4344 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
4345
4346 if (ret == 0)
4347 {
4348 counter_bdr_reg2.cnt_bdr_th = (uint8_t)val & 0xFFU;
4349 counter_bdr_reg1.cnt_bdr_th = (uint8_t)(val >> 8) & 0x3U;
4350 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
4351 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1);
4352 }
4353
4354 return ret;
4355 }
4356
4357 /**
4358 * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[get]
4359 *
4360 * @param ctx read / write interface definitions
4361 * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.
4362 * @retval interface status (MANDATORY: return 0 -> no Error)
4363 *
4364 */
lsm6dsv16x_fifo_batch_counter_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)4365 int32_t lsm6dsv16x_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx,
4366 uint16_t *val)
4367 {
4368 uint8_t buff[2];
4369 int32_t ret;
4370
4371 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, &buff[0], 2);
4372 if (ret != 0)
4373 {
4374 return ret;
4375 }
4376
4377 *val = (uint16_t)buff[0] & 0x3U;
4378 *val = (*val * 256U) + (uint16_t)buff[1];
4379
4380 return ret;
4381 }
4382
4383 /**
4384 * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[set]
4385 *
4386 * @param ctx read / write interface definitions
4387 * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT,
4388 * @retval interface status (MANDATORY: return 0 -> no Error)
4389 *
4390 */
lsm6dsv16x_fifo_batch_cnt_event_set(const stmdev_ctx_t * ctx,lsm6dsv16x_fifo_batch_cnt_event_t val)4391 int32_t lsm6dsv16x_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx,
4392 lsm6dsv16x_fifo_batch_cnt_event_t val)
4393 {
4394 lsm6dsv16x_counter_bdr_reg1_t counter_bdr_reg1;
4395 int32_t ret;
4396
4397 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
4398 if (ret == 0)
4399 {
4400 counter_bdr_reg1.trig_counter_bdr = (uint8_t)val & 0x03U;
4401 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
4402 }
4403
4404 return ret;
4405 }
4406
4407 /**
4408 * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[get]
4409 *
4410 * @param ctx read / write interface definitions
4411 * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT,
4412 * @retval interface status (MANDATORY: return 0 -> no Error)
4413 *
4414 */
lsm6dsv16x_fifo_batch_cnt_event_get(const stmdev_ctx_t * ctx,lsm6dsv16x_fifo_batch_cnt_event_t * val)4415 int32_t lsm6dsv16x_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx,
4416 lsm6dsv16x_fifo_batch_cnt_event_t *val)
4417 {
4418 lsm6dsv16x_counter_bdr_reg1_t counter_bdr_reg1;
4419 int32_t ret;
4420
4421 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
4422 if (ret != 0)
4423 {
4424 return ret;
4425 }
4426
4427 switch (counter_bdr_reg1.trig_counter_bdr)
4428 {
4429 case LSM6DSV16X_XL_BATCH_EVENT:
4430 *val = LSM6DSV16X_XL_BATCH_EVENT;
4431 break;
4432
4433 case LSM6DSV16X_GY_BATCH_EVENT:
4434 *val = LSM6DSV16X_GY_BATCH_EVENT;
4435 break;
4436
4437 case LSM6DSV16X_GY_EIS_BATCH_EVENT:
4438 *val = LSM6DSV16X_GY_EIS_BATCH_EVENT;
4439 break;
4440
4441 default:
4442 *val = LSM6DSV16X_XL_BATCH_EVENT;
4443 break;
4444 }
4445
4446 return ret;
4447 }
4448
lsm6dsv16x_fifo_status_get(const stmdev_ctx_t * ctx,lsm6dsv16x_fifo_status_t * val)4449 int32_t lsm6dsv16x_fifo_status_get(const stmdev_ctx_t *ctx,
4450 lsm6dsv16x_fifo_status_t *val)
4451 {
4452 uint8_t buff[2];
4453 lsm6dsv16x_fifo_status2_t status;
4454 int32_t ret;
4455
4456 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_STATUS1, (uint8_t *)&buff[0], 2);
4457 if (ret != 0)
4458 {
4459 return ret;
4460 }
4461
4462 bytecpy((uint8_t *)&status, &buff[1]);
4463
4464 val->fifo_bdr = status.counter_bdr_ia;
4465 val->fifo_ovr = status.fifo_ovr_ia;
4466 val->fifo_full = status.fifo_full_ia;
4467 val->fifo_th = status.fifo_wtm_ia;
4468
4469 val->fifo_level = (uint16_t)buff[1] & 0x01U;
4470 val->fifo_level = (val->fifo_level * 256U) + buff[0];
4471
4472 return ret;
4473 }
4474
4475
4476 /**
4477 * @brief FIFO data output[get]
4478 *
4479 * @param ctx read / write interface definitions
4480 * @param val lsm6dsv16x_fifo_out_raw_t
4481 * @retval interface status (MANDATORY: return 0 -> no Error)
4482 *
4483 */
lsm6dsv16x_fifo_out_raw_get(const stmdev_ctx_t * ctx,lsm6dsv16x_fifo_out_raw_t * val)4484 int32_t lsm6dsv16x_fifo_out_raw_get(const stmdev_ctx_t *ctx,
4485 lsm6dsv16x_fifo_out_raw_t *val)
4486 {
4487 lsm6dsv16x_fifo_data_out_tag_t fifo_data_out_tag;
4488 uint8_t buff[7];
4489 int32_t ret;
4490
4491 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FIFO_DATA_OUT_TAG, buff, 7);
4492 if (ret != 0)
4493 {
4494 return ret;
4495 }
4496
4497 bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]);
4498
4499 switch (fifo_data_out_tag.tag_sensor)
4500 {
4501 case LSM6DSV16X_FIFO_EMPTY:
4502 val->tag = LSM6DSV16X_FIFO_EMPTY;
4503 break;
4504
4505 case LSM6DSV16X_GY_NC_TAG:
4506 val->tag = LSM6DSV16X_GY_NC_TAG;
4507 break;
4508
4509 case LSM6DSV16X_XL_NC_TAG:
4510 val->tag = LSM6DSV16X_XL_NC_TAG;
4511 break;
4512
4513 case LSM6DSV16X_TIMESTAMP_TAG:
4514 val->tag = LSM6DSV16X_TIMESTAMP_TAG;
4515 break;
4516
4517 case LSM6DSV16X_TEMPERATURE_TAG:
4518 val->tag = LSM6DSV16X_TEMPERATURE_TAG;
4519 break;
4520
4521 case LSM6DSV16X_CFG_CHANGE_TAG:
4522 val->tag = LSM6DSV16X_CFG_CHANGE_TAG;
4523 break;
4524
4525 case LSM6DSV16X_XL_NC_T_2_TAG:
4526 val->tag = LSM6DSV16X_XL_NC_T_2_TAG;
4527 break;
4528
4529 case LSM6DSV16X_XL_NC_T_1_TAG:
4530 val->tag = LSM6DSV16X_XL_NC_T_1_TAG;
4531 break;
4532
4533 case LSM6DSV16X_XL_2XC_TAG:
4534 val->tag = LSM6DSV16X_XL_2XC_TAG;
4535 break;
4536
4537 case LSM6DSV16X_XL_3XC_TAG:
4538 val->tag = LSM6DSV16X_XL_3XC_TAG;
4539 break;
4540
4541 case LSM6DSV16X_GY_NC_T_2_TAG:
4542 val->tag = LSM6DSV16X_GY_NC_T_2_TAG;
4543 break;
4544
4545 case LSM6DSV16X_GY_NC_T_1_TAG:
4546 val->tag = LSM6DSV16X_GY_NC_T_1_TAG;
4547 break;
4548
4549 case LSM6DSV16X_GY_2XC_TAG:
4550 val->tag = LSM6DSV16X_GY_2XC_TAG;
4551 break;
4552
4553 case LSM6DSV16X_GY_3XC_TAG:
4554 val->tag = LSM6DSV16X_GY_3XC_TAG;
4555 break;
4556
4557 case LSM6DSV16X_SENSORHUB_SLAVE0_TAG:
4558 val->tag = LSM6DSV16X_SENSORHUB_SLAVE0_TAG;
4559 break;
4560
4561 case LSM6DSV16X_SENSORHUB_SLAVE1_TAG:
4562 val->tag = LSM6DSV16X_SENSORHUB_SLAVE1_TAG;
4563 break;
4564
4565 case LSM6DSV16X_SENSORHUB_SLAVE2_TAG:
4566 val->tag = LSM6DSV16X_SENSORHUB_SLAVE2_TAG;
4567 break;
4568
4569 case LSM6DSV16X_SENSORHUB_SLAVE3_TAG:
4570 val->tag = LSM6DSV16X_SENSORHUB_SLAVE3_TAG;
4571 break;
4572
4573 case LSM6DSV16X_STEP_COUNTER_TAG:
4574 val->tag = LSM6DSV16X_STEP_COUNTER_TAG;
4575 break;
4576
4577 case LSM6DSV16X_SFLP_GAME_ROTATION_VECTOR_TAG:
4578 val->tag = LSM6DSV16X_SFLP_GAME_ROTATION_VECTOR_TAG;
4579 break;
4580
4581 case LSM6DSV16X_SFLP_GYROSCOPE_BIAS_TAG:
4582 val->tag = LSM6DSV16X_SFLP_GYROSCOPE_BIAS_TAG;
4583 break;
4584
4585 case LSM6DSV16X_SFLP_GRAVITY_VECTOR_TAG:
4586 val->tag = LSM6DSV16X_SFLP_GRAVITY_VECTOR_TAG;
4587 break;
4588
4589 case LSM6DSV16X_SENSORHUB_NACK_TAG:
4590 val->tag = LSM6DSV16X_SENSORHUB_NACK_TAG;
4591 break;
4592
4593 case LSM6DSV16X_MLC_RESULT_TAG:
4594 val->tag = LSM6DSV16X_MLC_RESULT_TAG;
4595 break;
4596
4597 case LSM6DSV16X_MLC_FILTER:
4598 val->tag = LSM6DSV16X_MLC_FILTER;
4599 break;
4600
4601 case LSM6DSV16X_MLC_FEATURE:
4602 val->tag = LSM6DSV16X_MLC_FEATURE;
4603 break;
4604
4605 case LSM6DSV16X_XL_DUAL_CORE:
4606 val->tag = LSM6DSV16X_XL_DUAL_CORE;
4607 break;
4608
4609 case LSM6DSV16X_GY_ENHANCED_EIS:
4610 val->tag = LSM6DSV16X_GY_ENHANCED_EIS;
4611 break;
4612
4613 default:
4614 val->tag = LSM6DSV16X_FIFO_EMPTY;
4615 break;
4616 }
4617
4618 val->cnt = fifo_data_out_tag.tag_cnt;
4619
4620 val->data[0] = buff[1];
4621 val->data[1] = buff[2];
4622 val->data[2] = buff[3];
4623 val->data[3] = buff[4];
4624 val->data[4] = buff[5];
4625 val->data[5] = buff[6];
4626
4627 return ret;
4628 }
4629
4630 /**
4631 * @brief Batching in FIFO buffer of step counter value.[set]
4632 *
4633 * @param ctx read / write interface definitions
4634 * @param val Batching in FIFO buffer of step counter value.
4635 * @retval interface status (MANDATORY: return 0 -> no Error)
4636 *
4637 */
lsm6dsv16x_fifo_stpcnt_batch_set(const stmdev_ctx_t * ctx,uint8_t val)4638 int32_t lsm6dsv16x_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
4639 {
4640 lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4641 int32_t ret;
4642
4643 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
4644 if (ret != 0)
4645 {
4646 return ret;
4647 }
4648
4649 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4650 emb_func_fifo_en_a.step_counter_fifo_en = val;
4651 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4652
4653 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4654
4655 return ret;
4656 }
4657
4658 /**
4659 * @brief Batching in FIFO buffer of step counter value.[get]
4660 *
4661 * @param ctx read / write interface definitions
4662 * @param val Batching in FIFO buffer of step counter value.
4663 * @retval interface status (MANDATORY: return 0 -> no Error)
4664 *
4665 */
lsm6dsv16x_fifo_stpcnt_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)4666 int32_t lsm6dsv16x_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
4667 {
4668 lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4669 int32_t ret;
4670
4671 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
4672 if (ret != 0)
4673 {
4674 return ret;
4675 }
4676
4677 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4678 *val = emb_func_fifo_en_a.step_counter_fifo_en;
4679
4680 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4681
4682 return ret;
4683 }
4684
4685 /**
4686 * @brief Batching in FIFO buffer of machine learning core results.[set]
4687 *
4688 * @param ctx read / write interface definitions
4689 * @param val Batching in FIFO buffer of machine learning core results.
4690 * @retval interface status (MANDATORY: return 0 -> no Error)
4691 *
4692 */
lsm6dsv16x_fifo_mlc_batch_set(const stmdev_ctx_t * ctx,uint8_t val)4693 int32_t lsm6dsv16x_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
4694 {
4695 lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4696 int32_t ret;
4697
4698 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
4699 if (ret != 0)
4700 {
4701 return ret;
4702 }
4703
4704 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4705 emb_func_fifo_en_a.mlc_fifo_en = val;
4706 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4707
4708 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4709
4710 return ret;
4711 }
4712
4713 /**
4714 * @brief Batching in FIFO buffer of machine learning core results.[get]
4715 *
4716 * @param ctx read / write interface definitions
4717 * @param val Batching in FIFO buffer of machine learning core results.
4718 * @retval interface status (MANDATORY: return 0 -> no Error)
4719 *
4720 */
lsm6dsv16x_fifo_mlc_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)4721 int32_t lsm6dsv16x_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
4722 {
4723 lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4724 int32_t ret;
4725
4726 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
4727 if (ret != 0)
4728 {
4729 return ret;
4730 }
4731
4732 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4733 *val = emb_func_fifo_en_a.mlc_fifo_en;
4734
4735 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4736
4737 return ret;
4738 }
4739
4740 /**
4741 * @brief Enables batching in FIFO buffer of machine learning core filters and features.[set]
4742 *
4743 * @param ctx read / write interface definitions
4744 * @param val Enables batching in FIFO buffer of machine learning core filters and features.
4745 * @retval interface status (MANDATORY: return 0 -> no Error)
4746 *
4747 */
lsm6dsv16x_fifo_mlc_filt_batch_set(const stmdev_ctx_t * ctx,uint8_t val)4748 int32_t lsm6dsv16x_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
4749 {
4750 lsm6dsv16x_emb_func_fifo_en_b_t emb_func_fifo_en_b;
4751 int32_t ret;
4752
4753 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
4754 if (ret != 0)
4755 {
4756 return ret;
4757 }
4758
4759 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1);
4760 emb_func_fifo_en_b.mlc_filter_feature_fifo_en = val;
4761 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1);
4762
4763 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4764
4765 return ret;
4766 }
4767
4768 /**
4769 * @brief Enables batching in FIFO buffer of machine learning core filters and features.[get]
4770 *
4771 * @param ctx read / write interface definitions
4772 * @param val Enables batching in FIFO buffer of machine learning core filters and features.
4773 * @retval interface status (MANDATORY: return 0 -> no Error)
4774 *
4775 */
lsm6dsv16x_fifo_mlc_filt_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)4776 int32_t lsm6dsv16x_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
4777 {
4778 lsm6dsv16x_emb_func_fifo_en_b_t emb_func_fifo_en_b;
4779 int32_t ret;
4780
4781 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
4782 if (ret != 0)
4783 {
4784 return ret;
4785 }
4786
4787 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1);
4788 *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en;
4789
4790 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4791
4792 return ret;
4793 }
4794
4795 /**
4796 * @brief Enable FIFO data batching of slave idx.[set]
4797 *
4798 * @param ctx read / write interface definitions
4799 * @param val Enable FIFO data batching of slave idx.
4800 * @retval interface status (MANDATORY: return 0 -> no Error)
4801 *
4802 */
lsm6dsv16x_fifo_sh_batch_slave_set(const stmdev_ctx_t * ctx,uint8_t idx,uint8_t val)4803 int32_t lsm6dsv16x_fifo_sh_batch_slave_set(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t val)
4804 {
4805 lsm6dsv16x_slv0_config_t slv_config;
4806 int32_t ret;
4807
4808 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
4809 if (ret != 0)
4810 {
4811 return ret;
4812 }
4813
4814 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1);
4815 slv_config.batch_ext_sens_0_en = val;
4816 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1);
4817
4818 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4819
4820 return ret;
4821 }
4822
4823 /**
4824 * @brief Enable FIFO data batching of slave idx.[get]
4825 *
4826 * @param ctx read / write interface definitions
4827 * @param val Enable FIFO data batching of slave idx.
4828 * @retval interface status (MANDATORY: return 0 -> no Error)
4829 *
4830 */
lsm6dsv16x_fifo_sh_batch_slave_get(const stmdev_ctx_t * ctx,uint8_t idx,uint8_t * val)4831 int32_t lsm6dsv16x_fifo_sh_batch_slave_get(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val)
4832 {
4833 lsm6dsv16x_slv0_config_t slv_config;
4834 int32_t ret;
4835
4836 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
4837 if (ret != 0)
4838 {
4839 return ret;
4840 }
4841
4842 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx * 3U, (uint8_t *)&slv_config, 1);
4843 *val = slv_config.batch_ext_sens_0_en;
4844
4845 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4846
4847 return ret;
4848 }
4849
4850 /**
4851 * @brief Batching in FIFO buffer of SFLP.[set]
4852 *
4853 * @param ctx read / write interface definitions
4854 * @param val Batching in FIFO buffer of SFLP values.
4855 * @retval interface status (MANDATORY: return 0 -> no Error)
4856 *
4857 */
lsm6dsv16x_fifo_sflp_batch_set(const stmdev_ctx_t * ctx,lsm6dsv16x_fifo_sflp_raw_t val)4858 int32_t lsm6dsv16x_fifo_sflp_batch_set(const stmdev_ctx_t *ctx,
4859 lsm6dsv16x_fifo_sflp_raw_t val)
4860 {
4861 lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4862 int32_t ret;
4863
4864 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
4865 if (ret == 0)
4866 {
4867 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4868 emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation;
4869 emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity;
4870 emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias;
4871 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A,
4872 (uint8_t *)&emb_func_fifo_en_a, 1);
4873 }
4874
4875 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4876
4877 return ret;
4878 }
4879
4880 /**
4881 * @brief Batching in FIFO buffer of SFLP.[get]
4882 *
4883 * @param ctx read / write interface definitions
4884 * @param val Batching in FIFO buffer of SFLP values.
4885 * @retval interface status (MANDATORY: return 0 -> no Error)
4886 *
4887 */
lsm6dsv16x_fifo_sflp_batch_get(const stmdev_ctx_t * ctx,lsm6dsv16x_fifo_sflp_raw_t * val)4888 int32_t lsm6dsv16x_fifo_sflp_batch_get(const stmdev_ctx_t *ctx,
4889 lsm6dsv16x_fifo_sflp_raw_t *val)
4890 {
4891 lsm6dsv16x_emb_func_fifo_en_a_t emb_func_fifo_en_a;
4892 int32_t ret;
4893
4894 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
4895 if (ret == 0)
4896 {
4897 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
4898
4899 val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en;
4900 val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en;
4901 val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en;
4902 }
4903
4904 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
4905
4906 return ret;
4907 }
4908
4909 /**
4910 * @}
4911 *
4912 */
4913
4914 /**
4915 * @defgroup Filters
4916 * @brief This section group all the functions concerning the
4917 * filters configuration
4918 * @{
4919 *
4920 */
4921
4922 /**
4923 * @brief Protocol anti-spike filters.[set]
4924 *
4925 * @param ctx read / write interface definitions
4926 * @param val AUTO, ALWAYS_ACTIVE,
4927 * @retval interface status (MANDATORY: return 0 -> no Error)
4928 *
4929 */
lsm6dsv16x_filt_anti_spike_set(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_anti_spike_t val)4930 int32_t lsm6dsv16x_filt_anti_spike_set(const stmdev_ctx_t *ctx,
4931 lsm6dsv16x_filt_anti_spike_t val)
4932 {
4933 lsm6dsv16x_if_cfg_t if_cfg;
4934 int32_t ret;
4935
4936 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
4937
4938 if (ret == 0)
4939 {
4940 if_cfg.asf_ctrl = (uint8_t)val & 0x01U;
4941 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
4942 }
4943
4944 return ret;
4945 }
4946
4947 /**
4948 * @brief Protocol anti-spike filters.[get]
4949 *
4950 * @param ctx read / write interface definitions
4951 * @param val AUTO, ALWAYS_ACTIVE,
4952 * @retval interface status (MANDATORY: return 0 -> no Error)
4953 *
4954 */
lsm6dsv16x_filt_anti_spike_get(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_anti_spike_t * val)4955 int32_t lsm6dsv16x_filt_anti_spike_get(const stmdev_ctx_t *ctx,
4956 lsm6dsv16x_filt_anti_spike_t *val)
4957 {
4958 lsm6dsv16x_if_cfg_t if_cfg;
4959 int32_t ret;
4960
4961 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
4962 if (ret != 0)
4963 {
4964 return ret;
4965 }
4966
4967 switch (if_cfg.asf_ctrl)
4968 {
4969 case LSM6DSV16X_AUTO:
4970 *val = LSM6DSV16X_AUTO;
4971 break;
4972
4973 case LSM6DSV16X_ALWAYS_ACTIVE:
4974 *val = LSM6DSV16X_ALWAYS_ACTIVE;
4975 break;
4976
4977 default:
4978 *val = LSM6DSV16X_AUTO;
4979 break;
4980 }
4981
4982 return ret;
4983 }
4984
4985 /**
4986 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set]
4987 *
4988 * @param ctx read / write interface definitions
4989 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
4990 * @retval interface status (MANDATORY: return 0 -> no Error)
4991 *
4992 */
lsm6dsv16x_filt_settling_mask_set(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_settling_mask_t val)4993 int32_t lsm6dsv16x_filt_settling_mask_set(const stmdev_ctx_t *ctx,
4994 lsm6dsv16x_filt_settling_mask_t val)
4995 {
4996 lsm6dsv16x_emb_func_cfg_t emb_func_cfg;
4997 lsm6dsv16x_ui_int_ois_t ui_int_ois;
4998 lsm6dsv16x_ctrl4_t ctrl4;
4999 int32_t ret;
5000
5001 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
5002 ctrl4.drdy_mask = val.drdy;
5003 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
5004 if (ret != 0)
5005 {
5006 return ret;
5007 }
5008
5009 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
5010 emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl;
5011 emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g;
5012 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
5013 if (ret != 0)
5014 {
5015 return ret;
5016 }
5017
5018 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1);
5019 ui_int_ois.drdy_mask_ois = val.ois_drdy;
5020 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1);
5021
5022 return ret;
5023 }
5024
5025 /**
5026 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get]
5027 *
5028 * @param ctx read / write interface definitions
5029 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
5030 * @retval interface status (MANDATORY: return 0 -> no Error)
5031 *
5032 */
lsm6dsv16x_filt_settling_mask_get(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_settling_mask_t * val)5033 int32_t lsm6dsv16x_filt_settling_mask_get(const stmdev_ctx_t *ctx,
5034 lsm6dsv16x_filt_settling_mask_t *val)
5035 {
5036 lsm6dsv16x_emb_func_cfg_t emb_func_cfg;
5037 lsm6dsv16x_ui_int_ois_t ui_int_ois;
5038 lsm6dsv16x_ctrl4_t ctrl4;
5039 int32_t ret;
5040
5041 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL4, (uint8_t *)&ctrl4, 1);
5042 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
5043 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_INT_OIS, (uint8_t *)&ui_int_ois, 1);
5044
5045 val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl;
5046 val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl;
5047 val->drdy = ctrl4.drdy_mask;
5048
5049 return ret;
5050 }
5051
5052 /**
5053 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set]
5054 *
5055 * @param ctx read / write interface definitions
5056 * @param val It masks DRDY and Interrupts RQ until filter settling ends from OIS interface.
5057 * @retval interface status (MANDATORY: return 0 -> no Error)
5058 *
5059 */
lsm6dsv16x_filt_ois_settling_mask_set(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_ois_settling_mask_t val)5060 int32_t lsm6dsv16x_filt_ois_settling_mask_set(const stmdev_ctx_t *ctx,
5061 lsm6dsv16x_filt_ois_settling_mask_t val)
5062 {
5063 lsm6dsv16x_spi2_int_ois_t spi2_int_ois;
5064 int32_t ret;
5065
5066 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
5067
5068 if (ret == 0)
5069 {
5070 spi2_int_ois.drdy_mask_ois = val.ois_drdy;
5071 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
5072 }
5073
5074 return ret;
5075 }
5076
5077 /**
5078 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get]
5079 *
5080 * @param ctx read / write interface definitions
5081 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
5082 * @retval interface status (MANDATORY: return 0 -> no Error)
5083 *
5084 */
lsm6dsv16x_filt_ois_settling_mask_get(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_ois_settling_mask_t * val)5085 int32_t lsm6dsv16x_filt_ois_settling_mask_get(const stmdev_ctx_t *ctx,
5086 lsm6dsv16x_filt_ois_settling_mask_t *val)
5087 {
5088
5089 lsm6dsv16x_spi2_int_ois_t spi2_int_ois;
5090 int32_t ret;
5091
5092 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_INT_OIS, (uint8_t *)&spi2_int_ois, 1);
5093 val->ois_drdy = spi2_int_ois.drdy_mask_ois;
5094
5095 return ret;
5096 }
5097
5098 /**
5099 * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[set]
5100 *
5101 * @param ctx read / write interface definitions
5102 * @param val GY_ULTRA_LIGHT, GY_VERY_LIGHT, GY_LIGHT, GY_MEDIUM, GY_STRONG, GY_VERY_STRONG, GY_AGGRESSIVE, GY_XTREME,
5103 * @retval interface status (MANDATORY: return 0 -> no Error)
5104 *
5105 */
lsm6dsv16x_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_gy_lp1_bandwidth_t val)5106 int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
5107 lsm6dsv16x_filt_gy_lp1_bandwidth_t val)
5108 {
5109 lsm6dsv16x_ctrl6_t ctrl6;
5110 int32_t ret;
5111
5112 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1);
5113 if (ret == 0)
5114 {
5115 ctrl6.lpf1_g_bw = (uint8_t)val & 0x0Fu;
5116 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1);
5117 }
5118
5119 return ret;
5120 }
5121
5122 /**
5123 * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[get]
5124 *
5125 * @param ctx read / write interface definitions
5126 * @param val GY_ULTRA_LIGHT, GY_VERY_LIGHT, GY_LIGHT, GY_MEDIUM, GY_STRONG, GY_VERY_STRONG, GY_AGGRESSIVE, GY_XTREME,
5127 * @retval interface status (MANDATORY: return 0 -> no Error)
5128 *
5129 */
lsm6dsv16x_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_gy_lp1_bandwidth_t * val)5130 int32_t lsm6dsv16x_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
5131 lsm6dsv16x_filt_gy_lp1_bandwidth_t *val)
5132 {
5133 lsm6dsv16x_ctrl6_t ctrl6;
5134 int32_t ret;
5135
5136 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL6, (uint8_t *)&ctrl6, 1);
5137 if (ret != 0)
5138 {
5139 return ret;
5140 }
5141
5142 switch (ctrl6.lpf1_g_bw)
5143 {
5144 case LSM6DSV16X_GY_ULTRA_LIGHT:
5145 *val = LSM6DSV16X_GY_ULTRA_LIGHT;
5146 break;
5147
5148 case LSM6DSV16X_GY_VERY_LIGHT:
5149 *val = LSM6DSV16X_GY_VERY_LIGHT;
5150 break;
5151
5152 case LSM6DSV16X_GY_LIGHT:
5153 *val = LSM6DSV16X_GY_LIGHT;
5154 break;
5155
5156 case LSM6DSV16X_GY_MEDIUM:
5157 *val = LSM6DSV16X_GY_MEDIUM;
5158 break;
5159
5160 case LSM6DSV16X_GY_STRONG:
5161 *val = LSM6DSV16X_GY_STRONG;
5162 break;
5163
5164 case LSM6DSV16X_GY_VERY_STRONG:
5165 *val = LSM6DSV16X_GY_VERY_STRONG;
5166 break;
5167
5168 case LSM6DSV16X_GY_AGGRESSIVE:
5169 *val = LSM6DSV16X_GY_AGGRESSIVE;
5170 break;
5171
5172 case LSM6DSV16X_GY_XTREME:
5173 *val = LSM6DSV16X_GY_XTREME;
5174 break;
5175
5176 default:
5177 *val = LSM6DSV16X_GY_ULTRA_LIGHT;
5178 break;
5179 }
5180
5181 return ret;
5182 }
5183
5184 /**
5185 * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[set]
5186 *
5187 * @param ctx read / write interface definitions
5188 * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.
5189 * @retval interface status (MANDATORY: return 0 -> no Error)
5190 *
5191 */
lsm6dsv16x_filt_gy_lp1_set(const stmdev_ctx_t * ctx,uint8_t val)5192 int32_t lsm6dsv16x_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val)
5193 {
5194 lsm6dsv16x_ctrl7_t ctrl7;
5195 int32_t ret;
5196
5197 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
5198 if (ret == 0)
5199 {
5200 ctrl7.lpf1_g_en = val;
5201 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
5202 }
5203
5204 return ret;
5205 }
5206
5207
5208 /**
5209 * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[get]
5210 *
5211 * @param ctx read / write interface definitions
5212 * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.
5213 * @retval interface status (MANDATORY: return 0 -> no Error)
5214 *
5215 */
lsm6dsv16x_filt_gy_lp1_get(const stmdev_ctx_t * ctx,uint8_t * val)5216 int32_t lsm6dsv16x_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val)
5217 {
5218 lsm6dsv16x_ctrl7_t ctrl7;
5219 int32_t ret;
5220
5221 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
5222 *val = ctrl7.lpf1_g_en;
5223
5224 return ret;
5225 }
5226
5227 /**
5228 * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[set]
5229 *
5230 * @param ctx read / write interface definitions
5231 * @param val XL_ULTRA_LIGHT, XL_VERY_LIGHT, XL_LIGHT, XL_MEDIUM, XL_STRONG, XL_VERY_STRONG, XL_AGGRESSIVE, XL_XTREME,
5232 * @retval interface status (MANDATORY: return 0 -> no Error)
5233 *
5234 */
lsm6dsv16x_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_xl_lp2_bandwidth_t val)5235 int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx,
5236 lsm6dsv16x_filt_xl_lp2_bandwidth_t val)
5237 {
5238 lsm6dsv16x_ctrl8_t ctrl8;
5239 int32_t ret;
5240
5241 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1);
5242 if (ret == 0)
5243 {
5244 ctrl8.hp_lpf2_xl_bw = (uint8_t)val & 0x07U;
5245 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1);
5246 }
5247
5248 return ret;
5249 }
5250
5251 /**
5252 * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[get]
5253 *
5254 * @param ctx read / write interface definitions
5255 * @param val XL_ULTRA_LIGHT, XL_VERY_LIGHT, XL_LIGHT, XL_MEDIUM, XL_STRONG, XL_VERY_STRONG, XL_AGGRESSIVE, XL_XTREME,
5256 * @retval interface status (MANDATORY: return 0 -> no Error)
5257 *
5258 */
lsm6dsv16x_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_xl_lp2_bandwidth_t * val)5259 int32_t lsm6dsv16x_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx,
5260 lsm6dsv16x_filt_xl_lp2_bandwidth_t *val)
5261 {
5262 lsm6dsv16x_ctrl8_t ctrl8;
5263 int32_t ret;
5264
5265 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL8, (uint8_t *)&ctrl8, 1);
5266 if (ret != 0)
5267 {
5268 return ret;
5269 }
5270
5271 switch (ctrl8.hp_lpf2_xl_bw)
5272 {
5273 case LSM6DSV16X_XL_ULTRA_LIGHT:
5274 *val = LSM6DSV16X_XL_ULTRA_LIGHT;
5275 break;
5276
5277 case LSM6DSV16X_XL_VERY_LIGHT:
5278 *val = LSM6DSV16X_XL_VERY_LIGHT;
5279 break;
5280
5281 case LSM6DSV16X_XL_LIGHT:
5282 *val = LSM6DSV16X_XL_LIGHT;
5283 break;
5284
5285 case LSM6DSV16X_XL_MEDIUM:
5286 *val = LSM6DSV16X_XL_MEDIUM;
5287 break;
5288
5289 case LSM6DSV16X_XL_STRONG:
5290 *val = LSM6DSV16X_XL_STRONG;
5291 break;
5292
5293 case LSM6DSV16X_XL_VERY_STRONG:
5294 *val = LSM6DSV16X_XL_VERY_STRONG;
5295 break;
5296
5297 case LSM6DSV16X_XL_AGGRESSIVE:
5298 *val = LSM6DSV16X_XL_AGGRESSIVE;
5299 break;
5300
5301 case LSM6DSV16X_XL_XTREME:
5302 *val = LSM6DSV16X_XL_XTREME;
5303 break;
5304
5305 default:
5306 *val = LSM6DSV16X_XL_ULTRA_LIGHT;
5307 break;
5308 }
5309
5310 return ret;
5311 }
5312
5313 /**
5314 * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[set]
5315 *
5316 * @param ctx read / write interface definitions
5317 * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.
5318 * @retval interface status (MANDATORY: return 0 -> no Error)
5319 *
5320 */
lsm6dsv16x_filt_xl_lp2_set(const stmdev_ctx_t * ctx,uint8_t val)5321 int32_t lsm6dsv16x_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val)
5322 {
5323 lsm6dsv16x_ctrl9_t ctrl9;
5324 int32_t ret;
5325
5326 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
5327 if (ret == 0)
5328 {
5329 ctrl9.lpf2_xl_en = val;
5330 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
5331 }
5332
5333 return ret;
5334 }
5335
5336 /**
5337 * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[get]
5338 *
5339 * @param ctx read / write interface definitions
5340 * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.
5341 * @retval interface status (MANDATORY: return 0 -> no Error)
5342 *
5343 */
lsm6dsv16x_filt_xl_lp2_get(const stmdev_ctx_t * ctx,uint8_t * val)5344 int32_t lsm6dsv16x_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val)
5345 {
5346 lsm6dsv16x_ctrl9_t ctrl9;
5347 int32_t ret;
5348
5349 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
5350 *val = ctrl9.lpf2_xl_en;
5351
5352 return ret;
5353 }
5354
5355 /**
5356 * @brief Accelerometer slope filter / high-pass filter selection.[set]
5357 *
5358 * @param ctx read / write interface definitions
5359 * @param val Accelerometer slope filter / high-pass filter selection.
5360 * @retval interface status (MANDATORY: return 0 -> no Error)
5361 *
5362 */
lsm6dsv16x_filt_xl_hp_set(const stmdev_ctx_t * ctx,uint8_t val)5363 int32_t lsm6dsv16x_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val)
5364 {
5365 lsm6dsv16x_ctrl9_t ctrl9;
5366 int32_t ret;
5367
5368 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
5369 if (ret == 0)
5370 {
5371 ctrl9.hp_slope_xl_en = val;
5372 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
5373 }
5374
5375 return ret;
5376 }
5377
5378 /**
5379 * @brief Accelerometer slope filter / high-pass filter selection.[get]
5380 *
5381 * @param ctx read / write interface definitions
5382 * @param val Accelerometer slope filter / high-pass filter selection.
5383 * @retval interface status (MANDATORY: return 0 -> no Error)
5384 *
5385 */
lsm6dsv16x_filt_xl_hp_get(const stmdev_ctx_t * ctx,uint8_t * val)5386 int32_t lsm6dsv16x_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val)
5387 {
5388 lsm6dsv16x_ctrl9_t ctrl9;
5389 int32_t ret;
5390
5391 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
5392 *val = ctrl9.hp_slope_xl_en;
5393
5394 return ret;
5395 }
5396
5397 /**
5398 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[set]
5399 *
5400 * @param ctx read / write interface definitions
5401 * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.
5402 * @retval interface status (MANDATORY: return 0 -> no Error)
5403 *
5404 */
lsm6dsv16x_filt_xl_fast_settling_set(const stmdev_ctx_t * ctx,uint8_t val)5405 int32_t lsm6dsv16x_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val)
5406 {
5407 lsm6dsv16x_ctrl9_t ctrl9;
5408 int32_t ret;
5409
5410 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
5411 if (ret == 0)
5412 {
5413 ctrl9.xl_fastsettl_mode = val;
5414 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
5415 }
5416
5417 return ret;
5418 }
5419
5420 /**
5421 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[get]
5422 *
5423 * @param ctx read / write interface definitions
5424 * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.
5425 * @retval interface status (MANDATORY: return 0 -> no Error)
5426 *
5427 */
lsm6dsv16x_filt_xl_fast_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)5428 int32_t lsm6dsv16x_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val)
5429 {
5430 lsm6dsv16x_ctrl9_t ctrl9;
5431 int32_t ret;
5432
5433 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
5434 *val = ctrl9.xl_fastsettl_mode;
5435
5436 return ret;
5437 }
5438
5439 /**
5440 * @brief Accelerometer high-pass filter mode.[set]
5441 *
5442 * @param ctx read / write interface definitions
5443 * @param val HP_MD_NORMAL, HP_MD_REFERENCE,
5444 * @retval interface status (MANDATORY: return 0 -> no Error)
5445 *
5446 */
lsm6dsv16x_filt_xl_hp_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_xl_hp_mode_t val)5447 int32_t lsm6dsv16x_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx,
5448 lsm6dsv16x_filt_xl_hp_mode_t val)
5449 {
5450 lsm6dsv16x_ctrl9_t ctrl9;
5451 int32_t ret;
5452
5453 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
5454 if (ret == 0)
5455 {
5456 ctrl9.hp_ref_mode_xl = (uint8_t)val & 0x01U;
5457 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
5458 }
5459
5460 return ret;
5461 }
5462
5463 /**
5464 * @brief Accelerometer high-pass filter mode.[get]
5465 *
5466 * @param ctx read / write interface definitions
5467 * @param val HP_MD_NORMAL, HP_MD_REFERENCE,
5468 * @retval interface status (MANDATORY: return 0 -> no Error)
5469 *
5470 */
lsm6dsv16x_filt_xl_hp_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_xl_hp_mode_t * val)5471 int32_t lsm6dsv16x_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx,
5472 lsm6dsv16x_filt_xl_hp_mode_t *val)
5473 {
5474 lsm6dsv16x_ctrl9_t ctrl9;
5475 int32_t ret;
5476
5477 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL9, (uint8_t *)&ctrl9, 1);
5478 if (ret != 0)
5479 {
5480 return ret;
5481 }
5482
5483 switch (ctrl9.hp_ref_mode_xl)
5484 {
5485 case LSM6DSV16X_HP_MD_NORMAL:
5486 *val = LSM6DSV16X_HP_MD_NORMAL;
5487 break;
5488
5489 case LSM6DSV16X_HP_MD_REFERENCE:
5490 *val = LSM6DSV16X_HP_MD_REFERENCE;
5491 break;
5492
5493 default:
5494 *val = LSM6DSV16X_HP_MD_NORMAL;
5495 break;
5496 }
5497
5498 return ret;
5499 }
5500
5501 /**
5502 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[set]
5503 *
5504 * @param ctx read / write interface definitions
5505 * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, WK_FEED_LP_WITH_OFFSET,
5506 * @retval interface status (MANDATORY: return 0 -> no Error)
5507 *
5508 */
lsm6dsv16x_filt_wkup_act_feed_set(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_wkup_act_feed_t val)5509 int32_t lsm6dsv16x_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx,
5510 lsm6dsv16x_filt_wkup_act_feed_t val)
5511 {
5512 lsm6dsv16x_wake_up_ths_t wake_up_ths;
5513 lsm6dsv16x_tap_cfg0_t tap_cfg0;
5514 int32_t ret;
5515
5516 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
5517 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5518 if (ret != 0)
5519 {
5520 return ret;
5521 }
5522
5523 tap_cfg0.slope_fds = (uint8_t)val & 0x01U;
5524 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5525 if (ret != 0)
5526 {
5527 return ret;
5528 }
5529
5530 wake_up_ths.usr_off_on_wu = ((uint8_t)val & 0x02U) >> 1;
5531 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
5532
5533 return ret;
5534 }
5535
5536 /**
5537 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[get]
5538 *
5539 * @param ctx read / write interface definitions
5540 * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS, WK_FEED_LP_WITH_OFFSET,
5541 * @retval interface status (MANDATORY: return 0 -> no Error)
5542 *
5543 */
lsm6dsv16x_filt_wkup_act_feed_get(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_wkup_act_feed_t * val)5544 int32_t lsm6dsv16x_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx,
5545 lsm6dsv16x_filt_wkup_act_feed_t *val)
5546 {
5547 lsm6dsv16x_wake_up_ths_t wake_up_ths;
5548 lsm6dsv16x_tap_cfg0_t tap_cfg0;
5549 int32_t ret;
5550
5551 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
5552 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5553 if (ret != 0)
5554 {
5555 return ret;
5556 }
5557
5558 switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds)
5559 {
5560 case LSM6DSV16X_WK_FEED_SLOPE:
5561 *val = LSM6DSV16X_WK_FEED_SLOPE;
5562 break;
5563
5564 case LSM6DSV16X_WK_FEED_HIGH_PASS:
5565 *val = LSM6DSV16X_WK_FEED_HIGH_PASS;
5566 break;
5567
5568 case LSM6DSV16X_WK_FEED_LP_WITH_OFFSET:
5569 *val = LSM6DSV16X_WK_FEED_LP_WITH_OFFSET;
5570 break;
5571
5572 default:
5573 *val = LSM6DSV16X_WK_FEED_SLOPE;
5574 break;
5575 }
5576
5577 return ret;
5578 }
5579
5580 /**
5581 * @brief Mask hw function triggers when xl is settling.[set]
5582 *
5583 * @param ctx read / write interface definitions
5584 * @param val 0 or 1,
5585 * @retval interface status (MANDATORY: return 0 -> no Error)
5586 *
5587 */
lsm6dsv16x_mask_trigger_xl_settl_set(const stmdev_ctx_t * ctx,uint8_t val)5588 int32_t lsm6dsv16x_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val)
5589 {
5590 lsm6dsv16x_tap_cfg0_t tap_cfg0;
5591 int32_t ret;
5592
5593 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5594
5595 if (ret == 0)
5596 {
5597 tap_cfg0.hw_func_mask_xl_settl = val & 0x01U;
5598 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5599 }
5600
5601 return ret;
5602 }
5603
5604 /**
5605 * @brief Mask hw function triggers when xl is settling.[get]
5606 *
5607 * @param ctx read / write interface definitions
5608 * @param val 0 or 1,
5609 * @retval interface status (MANDATORY: return 0 -> no Error)
5610 *
5611 */
lsm6dsv16x_mask_trigger_xl_settl_get(const stmdev_ctx_t * ctx,uint8_t * val)5612 int32_t lsm6dsv16x_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val)
5613 {
5614 lsm6dsv16x_tap_cfg0_t tap_cfg0;
5615 int32_t ret;
5616
5617 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5618 *val = tap_cfg0.hw_func_mask_xl_settl;
5619
5620 return ret;
5621 }
5622
5623 /**
5624 * @brief LPF2 filter on 6D (sixd) function selection.[set]
5625 *
5626 * @param ctx read / write interface definitions
5627 * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS,
5628 * @retval interface status (MANDATORY: return 0 -> no Error)
5629 *
5630 */
lsm6dsv16x_filt_sixd_feed_set(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_sixd_feed_t val)5631 int32_t lsm6dsv16x_filt_sixd_feed_set(const stmdev_ctx_t *ctx,
5632 lsm6dsv16x_filt_sixd_feed_t val)
5633 {
5634 lsm6dsv16x_tap_cfg0_t tap_cfg0;
5635 int32_t ret;
5636
5637 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5638
5639 if (ret == 0)
5640 {
5641 tap_cfg0.low_pass_on_6d = (uint8_t)val & 0x01U;
5642 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5643 }
5644
5645 return ret;
5646 }
5647
5648 /**
5649 * @brief LPF2 filter on 6D (sixd) function selection.[get]
5650 *
5651 * @param ctx read / write interface definitions
5652 * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS,
5653 * @retval interface status (MANDATORY: return 0 -> no Error)
5654 *
5655 */
lsm6dsv16x_filt_sixd_feed_get(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_sixd_feed_t * val)5656 int32_t lsm6dsv16x_filt_sixd_feed_get(const stmdev_ctx_t *ctx,
5657 lsm6dsv16x_filt_sixd_feed_t *val)
5658 {
5659 lsm6dsv16x_tap_cfg0_t tap_cfg0;
5660 int32_t ret;
5661
5662 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5663 if (ret != 0)
5664 {
5665 return ret;
5666 }
5667
5668 switch (tap_cfg0.low_pass_on_6d)
5669 {
5670 case LSM6DSV16X_SIXD_FEED_ODR_DIV_2:
5671 *val = LSM6DSV16X_SIXD_FEED_ODR_DIV_2;
5672 break;
5673
5674 case LSM6DSV16X_SIXD_FEED_LOW_PASS:
5675 *val = LSM6DSV16X_SIXD_FEED_LOW_PASS;
5676 break;
5677
5678 default:
5679 *val = LSM6DSV16X_SIXD_FEED_ODR_DIV_2;
5680 break;
5681 }
5682
5683 return ret;
5684 }
5685
5686 /**
5687 * @brief Gyroscope digital LPF_EIS filter bandwidth selection.[set]
5688 *
5689 * @param ctx read / write interface definitions
5690 * @param val EIS_LP_NORMAL, EIS_LP_LIGHT,
5691 * @retval interface status (MANDATORY: return 0 -> no Error)
5692 *
5693 */
lsm6dsv16x_filt_gy_eis_lp_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_gy_eis_lp_bandwidth_t val)5694 int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_set(const stmdev_ctx_t *ctx,
5695 lsm6dsv16x_filt_gy_eis_lp_bandwidth_t val)
5696 {
5697 lsm6dsv16x_ctrl_eis_t ctrl_eis;
5698 int32_t ret;
5699
5700 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
5701
5702 if (ret == 0)
5703 {
5704 ctrl_eis.lpf_g_eis_bw = (uint8_t)val & 0x01U;
5705 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
5706 }
5707
5708 return ret;
5709 }
5710
5711 /**
5712 * @brief Gyroscope digital LPF_EIS filter bandwidth selection.[get]
5713 *
5714 * @param ctx read / write interface definitions
5715 * @param val EIS_LP_NORMAL, EIS_LP_LIGHT,
5716 * @retval interface status (MANDATORY: return 0 -> no Error)
5717 *
5718 */
lsm6dsv16x_filt_gy_eis_lp_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_gy_eis_lp_bandwidth_t * val)5719 int32_t lsm6dsv16x_filt_gy_eis_lp_bandwidth_get(const stmdev_ctx_t *ctx,
5720 lsm6dsv16x_filt_gy_eis_lp_bandwidth_t *val)
5721 {
5722 lsm6dsv16x_ctrl_eis_t ctrl_eis;
5723 int32_t ret;
5724
5725 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_EIS, (uint8_t *)&ctrl_eis, 1);
5726 if (ret != 0)
5727 {
5728 return ret;
5729 }
5730
5731 switch (ctrl_eis.lpf_g_eis_bw)
5732 {
5733 case LSM6DSV16X_EIS_LP_NORMAL:
5734 *val = LSM6DSV16X_EIS_LP_NORMAL;
5735 break;
5736
5737 case LSM6DSV16X_EIS_LP_LIGHT:
5738 *val = LSM6DSV16X_EIS_LP_LIGHT;
5739 break;
5740
5741 default:
5742 *val = LSM6DSV16X_EIS_LP_NORMAL;
5743 break;
5744 }
5745
5746 return ret;
5747 }
5748
5749 /**
5750 * @brief Gyroscope OIS digital LPF1 filter bandwidth selection. This function works also on OIS interface (SPI2_CTRL2_OIS = UI_CTRL2_OIS).[set]
5751 *
5752 * @param ctx read / write interface definitions
5753 * @param val OIS_GY_LP_NORMAL, OIS_GY_LP_STRONG, OIS_GY_LP_AGGRESSIVE, OIS_GY_LP_LIGHT,
5754 * @retval interface status (MANDATORY: return 0 -> no Error)
5755 *
5756 */
lsm6dsv16x_filt_gy_ois_lp_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_gy_ois_lp_bandwidth_t val)5757 int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx,
5758 lsm6dsv16x_filt_gy_ois_lp_bandwidth_t val)
5759 {
5760 lsm6dsv16x_ui_ctrl2_ois_t ui_ctrl2_ois;
5761 int32_t ret;
5762
5763 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
5764
5765 if (ret == 0)
5766 {
5767 ui_ctrl2_ois.lpf1_g_ois_bw = (uint8_t)val & 0x03U;
5768 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
5769 }
5770
5771 return ret;
5772 }
5773
5774 /**
5775 * @brief Gyroscope OIS digital LPF1 filter bandwidth selection. This function works also on OIS interface (SPI2_CTRL2_OIS = UI_CTRL2_OIS).[get]
5776 *
5777 * @param ctx read / write interface definitions
5778 * @param val OIS_GY_LP_NORMAL, OIS_GY_LP_STRONG, OIS_GY_LP_AGGRESSIVE, OIS_GY_LP_LIGHT,
5779 * @retval interface status (MANDATORY: return 0 -> no Error)
5780 *
5781 */
lsm6dsv16x_filt_gy_ois_lp_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_gy_ois_lp_bandwidth_t * val)5782 int32_t lsm6dsv16x_filt_gy_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx,
5783 lsm6dsv16x_filt_gy_ois_lp_bandwidth_t *val)
5784 {
5785
5786 lsm6dsv16x_ui_ctrl2_ois_t ui_ctrl2_ois;
5787 int32_t ret;
5788
5789 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
5790 if (ret != 0)
5791 {
5792 return ret;
5793 }
5794
5795 switch (ui_ctrl2_ois.lpf1_g_ois_bw)
5796 {
5797 case LSM6DSV16X_OIS_GY_LP_NORMAL:
5798 *val = LSM6DSV16X_OIS_GY_LP_NORMAL;
5799 break;
5800
5801 case LSM6DSV16X_OIS_GY_LP_STRONG:
5802 *val = LSM6DSV16X_OIS_GY_LP_STRONG;
5803 break;
5804
5805 case LSM6DSV16X_OIS_GY_LP_AGGRESSIVE:
5806 *val = LSM6DSV16X_OIS_GY_LP_AGGRESSIVE;
5807 break;
5808
5809 case LSM6DSV16X_OIS_GY_LP_LIGHT:
5810 *val = LSM6DSV16X_OIS_GY_LP_LIGHT;
5811 break;
5812
5813 default:
5814 *val = LSM6DSV16X_OIS_GY_LP_NORMAL;
5815 break;
5816 }
5817
5818 return ret;
5819 }
5820
5821 /**
5822 * @brief Selects accelerometer OIS channel bandwidth. This function works also on OIS interface (SPI2_CTRL3_OIS = UI_CTRL3_OIS).[set]
5823 *
5824 * @param ctx read / write interface definitions
5825 * @param val OIS_XL_LP_ULTRA_LIGHT, OIS_XL_LP_VERY_LIGHT, OIS_XL_LP_LIGHT, OIS_XL_LP_NORMAL, OIS_XL_LP_STRONG, OIS_XL_LP_VERY_STRONG, OIS_XL_LP_AGGRESSIVE, OIS_XL_LP_XTREME,
5826 * @retval interface status (MANDATORY: return 0 -> no Error)
5827 *
5828 */
lsm6dsv16x_filt_xl_ois_lp_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_xl_ois_lp_bandwidth_t val)5829 int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_set(const stmdev_ctx_t *ctx,
5830 lsm6dsv16x_filt_xl_ois_lp_bandwidth_t val)
5831 {
5832 lsm6dsv16x_ui_ctrl3_ois_t ui_ctrl3_ois;
5833 int32_t ret;
5834
5835 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
5836
5837 if (ret == 0)
5838 {
5839 ui_ctrl3_ois.lpf_xl_ois_bw = (uint8_t)val & 0x07U;
5840 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
5841 }
5842
5843 return ret;
5844 }
5845
5846 /**
5847 * @brief Selects accelerometer OIS channel bandwidth. This function works also on OIS interface (SPI2_CTRL3_OIS = UI_CTRL3_OIS).[get]
5848 *
5849 * @param ctx read / write interface definitions
5850 * @param val OIS_XL_LP_ULTRA_LIGHT, OIS_XL_LP_VERY_LIGHT, OIS_XL_LP_LIGHT, OIS_XL_LP_NORMAL, OIS_XL_LP_STRONG, OIS_XL_LP_VERY_STRONG, OIS_XL_LP_AGGRESSIVE, OIS_XL_LP_XTREME,
5851 * @retval interface status (MANDATORY: return 0 -> no Error)
5852 *
5853 */
lsm6dsv16x_filt_xl_ois_lp_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsv16x_filt_xl_ois_lp_bandwidth_t * val)5854 int32_t lsm6dsv16x_filt_xl_ois_lp_bandwidth_get(const stmdev_ctx_t *ctx,
5855 lsm6dsv16x_filt_xl_ois_lp_bandwidth_t *val)
5856 {
5857 lsm6dsv16x_ui_ctrl3_ois_t ui_ctrl3_ois;
5858 int32_t ret;
5859
5860 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
5861 if (ret != 0)
5862 {
5863 return ret;
5864 }
5865
5866 switch (ui_ctrl3_ois.lpf_xl_ois_bw)
5867 {
5868 case LSM6DSV16X_OIS_XL_LP_ULTRA_LIGHT:
5869 *val = LSM6DSV16X_OIS_XL_LP_ULTRA_LIGHT;
5870 break;
5871
5872 case LSM6DSV16X_OIS_XL_LP_VERY_LIGHT:
5873 *val = LSM6DSV16X_OIS_XL_LP_VERY_LIGHT;
5874 break;
5875
5876 case LSM6DSV16X_OIS_XL_LP_LIGHT:
5877 *val = LSM6DSV16X_OIS_XL_LP_LIGHT;
5878 break;
5879
5880 case LSM6DSV16X_OIS_XL_LP_NORMAL:
5881 *val = LSM6DSV16X_OIS_XL_LP_NORMAL;
5882 break;
5883
5884 case LSM6DSV16X_OIS_XL_LP_STRONG:
5885 *val = LSM6DSV16X_OIS_XL_LP_STRONG;
5886 break;
5887
5888 case LSM6DSV16X_OIS_XL_LP_VERY_STRONG:
5889 *val = LSM6DSV16X_OIS_XL_LP_VERY_STRONG;
5890 break;
5891
5892 case LSM6DSV16X_OIS_XL_LP_AGGRESSIVE:
5893 *val = LSM6DSV16X_OIS_XL_LP_AGGRESSIVE;
5894 break;
5895
5896 case LSM6DSV16X_OIS_XL_LP_XTREME:
5897 *val = LSM6DSV16X_OIS_XL_LP_XTREME;
5898 break;
5899
5900 default:
5901 *val = LSM6DSV16X_OIS_XL_LP_ULTRA_LIGHT;
5902 break;
5903 }
5904
5905 return ret;
5906 }
5907
5908 /**
5909 * @}
5910 *
5911 */
5912
5913 /**
5914 * @defgroup Finite State Machine (FSM)
5915 * @brief This section groups all the functions that manage the
5916 * state_machine.
5917 * @{
5918 *
5919 */
5920
5921 /**
5922 * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[set]
5923 *
5924 * @param ctx read / write interface definitions
5925 * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG,
5926 * @retval interface status (MANDATORY: return 0 -> no Error)
5927 *
5928 */
lsm6dsv16x_fsm_permission_set(const stmdev_ctx_t * ctx,lsm6dsv16x_fsm_permission_t val)5929 int32_t lsm6dsv16x_fsm_permission_set(const stmdev_ctx_t *ctx,
5930 lsm6dsv16x_fsm_permission_t val)
5931 {
5932 lsm6dsv16x_func_cfg_access_t func_cfg_access;
5933 int32_t ret;
5934
5935 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
5936
5937 if (ret == 0)
5938 {
5939 func_cfg_access.fsm_wr_ctrl_en = (uint8_t)val & 0x01U;
5940 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
5941 }
5942
5943 return ret;
5944 }
5945
5946 /**
5947 * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[get]
5948 *
5949 * @param ctx read / write interface definitions
5950 * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG,
5951 * @retval interface status (MANDATORY: return 0 -> no Error)
5952 *
5953 */
lsm6dsv16x_fsm_permission_get(const stmdev_ctx_t * ctx,lsm6dsv16x_fsm_permission_t * val)5954 int32_t lsm6dsv16x_fsm_permission_get(const stmdev_ctx_t *ctx,
5955 lsm6dsv16x_fsm_permission_t *val)
5956 {
5957 lsm6dsv16x_func_cfg_access_t func_cfg_access;
5958 int32_t ret;
5959
5960 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
5961 if (ret != 0)
5962 {
5963 return ret;
5964 }
5965
5966 switch (func_cfg_access.fsm_wr_ctrl_en)
5967 {
5968 case LSM6DSV16X_PROTECT_CTRL_REGS:
5969 *val = LSM6DSV16X_PROTECT_CTRL_REGS;
5970 break;
5971
5972 case LSM6DSV16X_WRITE_CTRL_REG:
5973 *val = LSM6DSV16X_WRITE_CTRL_REG;
5974 break;
5975
5976 default:
5977 *val = LSM6DSV16X_PROTECT_CTRL_REGS;
5978 break;
5979 }
5980
5981 return ret;
5982 }
5983
5984 /**
5985 * @brief Get the FSM permission status
5986 *
5987 * @param ctx read / write interface definitions
5988 * @param val 0: All reg writable from std if - 1: some regs are under FSM control.
5989 * @retval interface status (MANDATORY: return 0 -> no Error)
5990 *
5991 */
lsm6dsv16x_fsm_permission_status(const stmdev_ctx_t * ctx,uint8_t * val)5992 int32_t lsm6dsv16x_fsm_permission_status(const stmdev_ctx_t *ctx, uint8_t *val)
5993 {
5994 lsm6dsv16x_ctrl_status_t ctrl_status;
5995 int32_t ret;
5996
5997 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL_STATUS, (uint8_t *)&ctrl_status, 1);
5998
5999 *val = ctrl_status.fsm_wr_ctrl_status;
6000
6001 return ret;
6002 }
6003
6004 /**
6005 * @brief Enable Finite State Machine (FSM) feature.[set]
6006 *
6007 * @param ctx read / write interface definitions
6008 * @param val Enable Finite State Machine (FSM) feature.
6009 * @retval interface status (MANDATORY: return 0 -> no Error)
6010 *
6011 */
lsm6dsv16x_fsm_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16x_fsm_mode_t val)6012 int32_t lsm6dsv16x_fsm_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t val)
6013 {
6014 lsm6dsv16x_emb_func_en_b_t emb_func_en_b;
6015 lsm6dsv16x_fsm_enable_t fsm_enable;
6016 int32_t ret;
6017
6018 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
6019 if (ret != 0)
6020 {
6021 return ret;
6022 }
6023
6024 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
6025 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
6026 if (ret != 0)
6027 {
6028 goto exit;
6029 }
6030
6031 if ((val.fsm1_en | val.fsm2_en | val.fsm3_en | val.fsm4_en
6032 | val.fsm5_en | val.fsm6_en | val.fsm7_en | val.fsm8_en) == PROPERTY_ENABLE)
6033 {
6034 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
6035 }
6036 else
6037 {
6038 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
6039 }
6040
6041 fsm_enable.fsm1_en = val.fsm1_en;
6042 fsm_enable.fsm2_en = val.fsm2_en;
6043 fsm_enable.fsm3_en = val.fsm3_en;
6044 fsm_enable.fsm4_en = val.fsm4_en;
6045 fsm_enable.fsm5_en = val.fsm5_en;
6046 fsm_enable.fsm6_en = val.fsm6_en;
6047 fsm_enable.fsm7_en = val.fsm7_en;
6048 fsm_enable.fsm8_en = val.fsm8_en;
6049
6050 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
6051 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
6052
6053 exit:
6054 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
6055
6056 return ret;
6057 }
6058
6059 /**
6060 * @brief Enable Finite State Machine (FSM) feature.[get]
6061 *
6062 * @param ctx read / write interface definitions
6063 * @param val Enable Finite State Machine (FSM) feature.
6064 * @retval interface status (MANDATORY: return 0 -> no Error)
6065 *
6066 */
lsm6dsv16x_fsm_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16x_fsm_mode_t * val)6067 int32_t lsm6dsv16x_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_mode_t *val)
6068 {
6069 lsm6dsv16x_fsm_enable_t fsm_enable;
6070 int32_t ret;
6071
6072 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
6073 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
6074 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
6075 if (ret != 0)
6076 {
6077 return ret;
6078 }
6079
6080 val->fsm1_en = fsm_enable.fsm1_en;
6081 val->fsm2_en = fsm_enable.fsm2_en;
6082 val->fsm3_en = fsm_enable.fsm3_en;
6083 val->fsm4_en = fsm_enable.fsm4_en;
6084 val->fsm5_en = fsm_enable.fsm5_en;
6085 val->fsm6_en = fsm_enable.fsm6_en;
6086 val->fsm7_en = fsm_enable.fsm7_en;
6087 val->fsm8_en = fsm_enable.fsm8_en;
6088
6089 return ret;
6090 }
6091
6092 /**
6093 * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[set]
6094 *
6095 * @param ctx read / write interface definitions
6096 * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).
6097 * @retval interface status (MANDATORY: return 0 -> no Error)
6098 *
6099 */
lsm6dsv16x_fsm_long_cnt_set(const stmdev_ctx_t * ctx,uint16_t val)6100 int32_t lsm6dsv16x_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val)
6101 {
6102 uint8_t buff[2];
6103 int32_t ret;
6104
6105 buff[1] = (uint8_t)(val / 256U);
6106 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6107
6108 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
6109 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2);
6110 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
6111
6112 return ret;
6113 }
6114
6115 /**
6116 * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[get]
6117 *
6118 * @param ctx read / write interface definitions
6119 * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).
6120 * @retval interface status (MANDATORY: return 0 -> no Error)
6121 *
6122 */
lsm6dsv16x_fsm_long_cnt_get(const stmdev_ctx_t * ctx,uint16_t * val)6123 int32_t lsm6dsv16x_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val)
6124 {
6125 uint8_t buff[2];
6126 int32_t ret;
6127
6128 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
6129 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_LONG_COUNTER_L, &buff[0], 2);
6130 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
6131 if (ret != 0)
6132 {
6133 return ret;
6134 }
6135
6136 *val = buff[1];
6137 *val = (*val * 256U) + buff[0];
6138
6139 return ret;
6140 }
6141
6142 /**
6143 * @brief FSM output registers[get]
6144 *
6145 * @param ctx read / write interface definitions
6146 * @param val FSM output registers
6147 * @retval interface status (MANDATORY: return 0 -> no Error)
6148 *
6149 */
lsm6dsv16x_fsm_out_get(const stmdev_ctx_t * ctx,lsm6dsv16x_fsm_out_t * val)6150 int32_t lsm6dsv16x_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv16x_fsm_out_t *val)
6151 {
6152 int32_t ret;
6153
6154 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
6155 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_OUTS1, (uint8_t *)val, 8);
6156 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
6157
6158 return ret;
6159 }
6160
6161 /**
6162 * @brief Finite State Machine Output Data Rate (ODR) configuration.[set]
6163 *
6164 * @param ctx read / write interface definitions
6165 * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz,
6166 * @retval interface status (MANDATORY: return 0 -> no Error)
6167 *
6168 */
lsm6dsv16x_fsm_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv16x_fsm_data_rate_t val)6169 int32_t lsm6dsv16x_fsm_data_rate_set(const stmdev_ctx_t *ctx,
6170 lsm6dsv16x_fsm_data_rate_t val)
6171 {
6172 lsm6dsv16x_fsm_odr_t fsm_odr;
6173 int32_t ret;
6174
6175 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
6176 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_ODR, (uint8_t *)&fsm_odr, 1);
6177 if (ret != 0)
6178 {
6179 goto exit;
6180 }
6181
6182 fsm_odr.fsm_odr = (uint8_t)val & 0x07U;
6183 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FSM_ODR, (uint8_t *)&fsm_odr, 1);
6184
6185 exit:
6186 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
6187
6188 return ret;
6189 }
6190
6191 /**
6192 * @brief Finite State Machine Output Data Rate (ODR) configuration.[get]
6193 *
6194 * @param ctx read / write interface definitions
6195 * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz,
6196 * @retval interface status (MANDATORY: return 0 -> no Error)
6197 *
6198 */
lsm6dsv16x_fsm_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv16x_fsm_data_rate_t * val)6199 int32_t lsm6dsv16x_fsm_data_rate_get(const stmdev_ctx_t *ctx,
6200 lsm6dsv16x_fsm_data_rate_t *val)
6201 {
6202 lsm6dsv16x_fsm_odr_t fsm_odr;
6203 int32_t ret;
6204
6205 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
6206 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FSM_ODR, (uint8_t *)&fsm_odr, 1);
6207 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
6208 if (ret != 0)
6209 {
6210 return ret;
6211 }
6212
6213 switch (fsm_odr.fsm_odr)
6214 {
6215 case LSM6DSV16X_FSM_15Hz:
6216 *val = LSM6DSV16X_FSM_15Hz;
6217 break;
6218
6219 case LSM6DSV16X_FSM_30Hz:
6220 *val = LSM6DSV16X_FSM_30Hz;
6221 break;
6222
6223 case LSM6DSV16X_FSM_60Hz:
6224 *val = LSM6DSV16X_FSM_60Hz;
6225 break;
6226
6227 case LSM6DSV16X_FSM_120Hz:
6228 *val = LSM6DSV16X_FSM_120Hz;
6229 break;
6230
6231 case LSM6DSV16X_FSM_240Hz:
6232 *val = LSM6DSV16X_FSM_240Hz;
6233 break;
6234
6235 case LSM6DSV16X_FSM_480Hz:
6236 *val = LSM6DSV16X_FSM_480Hz;
6237 break;
6238
6239 case LSM6DSV16X_FSM_960Hz:
6240 *val = LSM6DSV16X_FSM_960Hz;
6241 break;
6242
6243 default:
6244 *val = LSM6DSV16X_FSM_15Hz;
6245 break;
6246 }
6247
6248 return ret;
6249 }
6250
6251 /*
6252 * Original conversion routines taken from: https://github.com/numpy/numpy
6253 *
6254 * uint16_t npy_floatbits_to_halfbits(uint32_t f);
6255 * uint16_t npy_float_to_half(float_t f);
6256 *
6257 * Released under BSD-3-Clause License
6258 */
6259
6260 #define NPY_HALF_GENERATE_OVERFLOW 0 /* do not trigger FP overflow */
6261 #define NPY_HALF_GENERATE_UNDERFLOW 0 /* do not trigger FP underflow */
6262 #ifndef NPY_HALF_ROUND_TIES_TO_EVEN
6263 #define NPY_HALF_ROUND_TIES_TO_EVEN 1
6264 #endif
6265
npy_floatbits_to_halfbits(uint32_t f)6266 static uint16_t npy_floatbits_to_halfbits(uint32_t f)
6267 {
6268 uint32_t f_exp, f_sig;
6269 uint16_t h_sgn, h_exp, h_sig;
6270
6271 h_sgn = (uint16_t)((f & 0x80000000u) >> 16);
6272 f_exp = (f & 0x7f800000u);
6273
6274 /* Exponent overflow/NaN converts to signed inf/NaN */
6275 if (f_exp >= 0x47800000u)
6276 {
6277 if (f_exp == 0x7f800000u)
6278 {
6279 /* Inf or NaN */
6280 f_sig = (f & 0x007fffffu);
6281 if (f_sig != 0U)
6282 {
6283 /* NaN - propagate the flag in the significand... */
6284 uint16_t ret = (uint16_t)(0x7c00u + (f_sig >> 13));
6285 /* ...but make sure it stays a NaN */
6286 if (ret == 0x7c00u)
6287 {
6288 ret++;
6289 }
6290 return h_sgn + ret;
6291 }
6292 else
6293 {
6294 /* signed inf */
6295 return (uint16_t)(h_sgn + 0x7c00u);
6296 }
6297 }
6298 else
6299 {
6300 /* overflow to signed inf */
6301 #if NPY_HALF_GENERATE_OVERFLOW
6302 npy_set_floatstatus_overflow();
6303 #endif
6304 return (uint16_t)(h_sgn + 0x7c00u);
6305 }
6306 }
6307
6308 /* Exponent underflow converts to a subnormal half or signed zero */
6309 if (f_exp <= 0x38000000u)
6310 {
6311 /*
6312 * Signed zeros, subnormal floats, and floats with small
6313 * exponents all convert to signed zero half-floats.
6314 */
6315 if (f_exp < 0x33000000u)
6316 {
6317 #if NPY_HALF_GENERATE_UNDERFLOW
6318 /* If f != 0, it underflowed to 0 */
6319 if ((f & 0x7fffffff) != 0)
6320 {
6321 npy_set_floatstatus_underflow();
6322 }
6323 #endif
6324 return h_sgn;
6325 }
6326 /* Make the subnormal significand */
6327 f_exp >>= 23;
6328 f_sig = (0x00800000u + (f & 0x007fffffu));
6329 #if NPY_HALF_GENERATE_UNDERFLOW
6330 /* If it's not exactly represented, it underflowed */
6331 if ((f_sig & (((uint32_t)1 << (126 - f_exp)) - 1)) != 0)
6332 {
6333 npy_set_floatstatus_underflow();
6334 }
6335 #endif
6336 /*
6337 * Usually the significand is shifted by 13. For subnormals an
6338 * additional shift needs to occur. This shift is one for the largest
6339 * exponent giving a subnormal `f_exp = 0x38000000 >> 23 = 112`, which
6340 * offsets the new first bit. At most the shift can be 1+10 bits.
6341 */
6342 f_sig >>= (113U - f_exp);
6343 /* Handle rounding by adding 1 to the bit beyond half precision */
6344 #if NPY_HALF_ROUND_TIES_TO_EVEN
6345 /*
6346 * If the last bit in the half significand is 0 (already even), and
6347 * the remaining bit pattern is 1000...0, then we do not add one
6348 * to the bit after the half significand. However, the (113 - f_exp)
6349 * shift can lose up to 11 bits, so the || checks them in the original.
6350 * In all other cases, we can just add one.
6351 */
6352 if (((f_sig & 0x00003fffu) != 0x00001000u) || (f & 0x000007ffu))
6353 {
6354 f_sig += 0x00001000u;
6355 }
6356 #else
6357 f_sig += 0x00001000u;
6358 #endif
6359 h_sig = (uint16_t)(f_sig >> 13);
6360 /*
6361 * If the rounding causes a bit to spill into h_exp, it will
6362 * increment h_exp from zero to one and h_sig will be zero.
6363 * This is the correct result.
6364 */
6365 return (uint16_t)(h_sgn + h_sig);
6366 }
6367
6368 /* Regular case with no overflow or underflow */
6369 h_exp = (uint16_t)((f_exp - 0x38000000u) >> 13);
6370 /* Handle rounding by adding 1 to the bit beyond half precision */
6371 f_sig = (f & 0x007fffffu);
6372 #if NPY_HALF_ROUND_TIES_TO_EVEN
6373 /*
6374 * If the last bit in the half significand is 0 (already even), and
6375 * the remaining bit pattern is 1000...0, then we do not add one
6376 * to the bit after the half significand. In all other cases, we do.
6377 */
6378 if ((f_sig & 0x00003fffu) != 0x00001000u)
6379 {
6380 f_sig += 0x00001000u;
6381 }
6382 #else
6383 f_sig += 0x00001000u;
6384 #endif
6385 h_sig = (uint16_t)(f_sig >> 13);
6386 /*
6387 * If the rounding causes a bit to spill into h_exp, it will
6388 * increment h_exp by one and h_sig will be zero. This is the
6389 * correct result. h_exp may increment to 15, at greatest, in
6390 * which case the result overflows to a signed inf.
6391 */
6392 #if NPY_HALF_GENERATE_OVERFLOW
6393 h_sig += h_exp;
6394 if (h_sig == 0x7c00u)
6395 {
6396 npy_set_floatstatus_overflow();
6397 }
6398 return h_sgn + h_sig;
6399 #else
6400 return h_sgn + h_exp + h_sig;
6401 #endif
6402 }
6403
npy_float_to_half(float_t f)6404 static uint16_t npy_float_to_half(float_t f)
6405 {
6406 union
6407 {
6408 float_t f;
6409 uint32_t fbits;
6410 } conv;
6411 conv.f = f;
6412 return npy_floatbits_to_halfbits(conv.fbits);
6413 }
6414
6415 /**
6416 * @brief SFLP GBIAS value. The register value is expressed as half-precision
6417 * floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent
6418 * bits; F: 10 fraction bits).[set]
6419 *
6420 * @param ctx read / write interface definitions
6421 * @param val GBIAS x/y/z val.
6422 * @retval interface status (MANDATORY: return 0 -> no Error)
6423 *
6424 */
lsm6dsv16x_sflp_game_gbias_set(const stmdev_ctx_t * ctx,lsm6dsv16x_sflp_gbias_t * val)6425 int32_t lsm6dsv16x_sflp_game_gbias_set(const stmdev_ctx_t *ctx,
6426 lsm6dsv16x_sflp_gbias_t *val)
6427 {
6428 lsm6dsv16x_sflp_data_rate_t sflp_odr;
6429 lsm6dsv16x_emb_func_exec_status_t emb_func_sts;
6430 lsm6dsv16x_data_ready_t drdy;
6431 lsm6dsv16x_xl_full_scale_t xl_fs;
6432 lsm6dsv16x_ctrl10_t ctrl10;
6433 uint8_t master_config;
6434 uint8_t emb_func_en_saved[2];
6435 uint8_t conf_saved[2];
6436 uint8_t reg_zero[2] = {0x0, 0x0};
6437 uint16_t gbias_hf[3];
6438 float_t k = 0.005f;
6439 int16_t xl_data[3];
6440 int32_t data_tmp;
6441 uint8_t *data_ptr = (uint8_t *)&data_tmp;
6442 uint8_t i, j;
6443 int32_t ret;
6444
6445 ret = lsm6dsv16x_sflp_data_rate_get(ctx, &sflp_odr);
6446 if (ret != 0)
6447 {
6448 return ret;
6449 }
6450
6451 /* Calculate k factor */
6452 switch (sflp_odr)
6453 {
6454 default:
6455 case LSM6DSV16X_SFLP_15Hz:
6456 k = 0.04f;
6457 break;
6458 case LSM6DSV16X_SFLP_30Hz:
6459 k = 0.02f;
6460 break;
6461 case LSM6DSV16X_SFLP_60Hz:
6462 k = 0.01f;
6463 break;
6464 case LSM6DSV16X_SFLP_120Hz:
6465 k = 0.005f;
6466 break;
6467 case LSM6DSV16X_SFLP_240Hz:
6468 k = 0.0025f;
6469 break;
6470 case LSM6DSV16X_SFLP_480Hz:
6471 k = 0.00125f;
6472 break;
6473 }
6474
6475 /* compute gbias as half precision float in order to be put in embedded advanced feature register */
6476 gbias_hf[0] = npy_float_to_half(val->gbias_x * (3.14159265358979323846f / 180.0f) / k);
6477 gbias_hf[1] = npy_float_to_half(val->gbias_y * (3.14159265358979323846f / 180.0f) / k);
6478 gbias_hf[2] = npy_float_to_half(val->gbias_z * (3.14159265358979323846f / 180.0f) / k);
6479
6480 /* Save sensor configuration and set high-performance mode (if the sensor is in power-down mode, turn it on) */
6481 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL1, conf_saved, 2);
6482 ret += lsm6dsv16x_xl_mode_set(ctx, LSM6DSV16X_XL_HIGH_PERFORMANCE_MD);
6483 ret += lsm6dsv16x_gy_mode_set(ctx, LSM6DSV16X_GY_HIGH_PERFORMANCE_MD);
6484 if (((uint8_t)conf_saved[0] & 0x0FU) == (uint8_t)LSM6DSV16X_ODR_OFF)
6485 {
6486 ret += lsm6dsv16x_xl_data_rate_set(ctx, LSM6DSV16X_ODR_AT_120Hz);
6487 }
6488
6489 /* Make sure to turn the sensor-hub master off */
6490 ret += lsm6dsv16x_sh_master_get(ctx, &master_config);
6491 ret += lsm6dsv16x_sh_master_set(ctx, 0);
6492
6493 /* disable algos */
6494 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
6495 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, emb_func_en_saved, 2);
6496 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, reg_zero, 2);
6497 do
6498 {
6499 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EXEC_STATUS,
6500 (uint8_t *)&emb_func_sts, 1);
6501 } while (emb_func_sts.emb_func_endop != 1U);
6502 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
6503
6504 // enable gbias setting
6505 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
6506 ctrl10.emb_func_debug = 1;
6507 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
6508
6509 /* enable algos */
6510 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
6511 emb_func_en_saved[0] |= 0x02U; /* force SFLP GAME en */
6512 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, emb_func_en_saved,
6513 2);
6514 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
6515
6516 ret += lsm6dsv16x_xl_full_scale_get(ctx, &xl_fs);
6517
6518 /* Read XL data */
6519 do
6520 {
6521 ret += lsm6dsv16x_flag_data_ready_get(ctx, &drdy);
6522 } while (drdy.drdy_xl != 1U);
6523 ret += lsm6dsv16x_acceleration_raw_get(ctx, xl_data);
6524
6525 /* force sflp initialization */
6526 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
6527 for (i = 0; i < 3U; i++)
6528 {
6529 j = 0;
6530 data_tmp = (int32_t)xl_data[i];
6531 data_tmp <<= xl_fs; // shift based on current fs
6532 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SENSOR_HUB_1 + 3U * i,
6533 &data_ptr[j++], 1);
6534 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SENSOR_HUB_2 + 3U * i,
6535 &data_ptr[j++], 1);
6536 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SENSOR_HUB_3 + 3U * i, &data_ptr[j],
6537 1);
6538 }
6539 for (i = 0; i < 3U; i++)
6540 {
6541 j = 0;
6542 data_tmp = 0;
6543 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SENSOR_HUB_10 + 3U * i,
6544 &data_ptr[j++], 1);
6545 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SENSOR_HUB_11 + 3U * i,
6546 &data_ptr[j++], 1);
6547 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SENSOR_HUB_12 + 3U * i, &data_ptr[j],
6548 1);
6549 }
6550 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
6551
6552 // wait end_op (and at least 30 us)
6553 ctx->mdelay(1);
6554 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
6555 do
6556 {
6557 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EXEC_STATUS,
6558 (uint8_t *)&emb_func_sts, 1);
6559 } while (emb_func_sts.emb_func_endop != 1U);
6560 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
6561
6562 /* write gbias in embedded advanced features registers */
6563 ret += lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_SFLP_GAME_GBIASX_L,
6564 (uint8_t *)gbias_hf, 6);
6565
6566 /* reload previous sensor configuration */
6567 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL1, conf_saved, 2);
6568
6569 // disable gbias setting
6570 ctrl10.emb_func_debug = 0;
6571 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL10, (uint8_t *)&ctrl10, 1);
6572
6573 /* reload previous master configuration */
6574 ret += lsm6dsv16x_sh_master_set(ctx, master_config);
6575
6576 return ret;
6577 }
6578
6579 /**
6580 * @brief External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).[set]
6581 *
6582 * @param ctx read / write interface definitions
6583 * @param val External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).
6584 * @retval interface status (MANDATORY: return 0 -> no Error)
6585 *
6586 */
lsm6dsv16x_fsm_ext_sens_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)6587 int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val)
6588 {
6589 uint8_t buff[2];
6590 int32_t ret;
6591
6592 buff[1] = (uint8_t)(val / 256U);
6593 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6594 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_FSM_EXT_SENSITIVITY_L, (uint8_t *)&buff[0], 2);
6595
6596 return ret;
6597 }
6598
6599 /**
6600 * @brief External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).[get]
6601 *
6602 * @param ctx read / write interface definitions
6603 * @param val External sensor sensitivity value register for the Finite State Machine (r/w). This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits). Default value is 0x1624 (when using an external magnetometer this value corresponds to 0.0015 gauss/LSB).
6604 * @retval interface status (MANDATORY: return 0 -> no Error)
6605 *
6606 */
lsm6dsv16x_fsm_ext_sens_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)6607 int32_t lsm6dsv16x_fsm_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx,
6608 uint16_t *val)
6609 {
6610 uint8_t buff[2];
6611 int32_t ret;
6612
6613 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_FSM_EXT_SENSITIVITY_L, &buff[0], 2);
6614 if (ret != 0)
6615 {
6616 return ret;
6617 }
6618
6619 *val = buff[1];
6620 *val = (*val * 256U) + buff[0];
6621
6622 return ret;
6623 }
6624
6625 /**
6626 * @brief External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set]
6627 *
6628 * @param ctx read / write interface definitions
6629 * @param val External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
6630 * @retval interface status (MANDATORY: return 0 -> no Error)
6631 *
6632 */
lsm6dsv16x_fsm_ext_sens_offset_set(const stmdev_ctx_t * ctx,lsm6dsv16x_xl_fsm_ext_sens_offset_t val)6633 int32_t lsm6dsv16x_fsm_ext_sens_offset_set(const stmdev_ctx_t *ctx,
6634 lsm6dsv16x_xl_fsm_ext_sens_offset_t val)
6635 {
6636 uint8_t buff[6];
6637 int32_t ret;
6638
6639 buff[1] = (uint8_t)(val.x / 256U);
6640 buff[0] = (uint8_t)(val.x - (buff[1] * 256U));
6641 buff[3] = (uint8_t)(val.y / 256U);
6642 buff[2] = (uint8_t)(val.y - (buff[3] * 256U));
6643 buff[5] = (uint8_t)(val.z / 256U);
6644 buff[4] = (uint8_t)(val.z - (buff[5] * 256U));
6645 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_FSM_EXT_OFFX_L, (uint8_t *)&buff[0], 6);
6646
6647 return ret;
6648 }
6649
6650 /**
6651 * @brief External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get]
6652 *
6653 * @param ctx read / write interface definitions
6654 * @param val External sensor offsets (X,Y,Z). The values are expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
6655 * @retval interface status (MANDATORY: return 0 -> no Error)
6656 *
6657 */
lsm6dsv16x_fsm_ext_sens_offset_get(const stmdev_ctx_t * ctx,lsm6dsv16x_xl_fsm_ext_sens_offset_t * val)6658 int32_t lsm6dsv16x_fsm_ext_sens_offset_get(const stmdev_ctx_t *ctx,
6659 lsm6dsv16x_xl_fsm_ext_sens_offset_t *val)
6660 {
6661 uint8_t buff[6];
6662 int32_t ret;
6663
6664 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_FSM_EXT_OFFX_L, &buff[0], 6);
6665 if (ret != 0)
6666 {
6667 return ret;
6668 }
6669
6670 val->x = buff[1];
6671 val->x = (val->x * 256U) + buff[0];
6672 val->y = buff[3];
6673 val->y = (val->y * 256U) + buff[2];
6674 val->z = buff[5];
6675 val->z = (val->z * 256U) + buff[4];
6676
6677 return ret;
6678 }
6679
6680 /**
6681 * @brief External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set]
6682 *
6683 * @param ctx read / write interface definitions
6684 * @param val External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
6685 * @retval interface status (MANDATORY: return 0 -> no Error)
6686 *
6687 */
lsm6dsv16x_fsm_ext_sens_matrix_set(const stmdev_ctx_t * ctx,lsm6dsv16x_xl_fsm_ext_sens_matrix_t val)6688 int32_t lsm6dsv16x_fsm_ext_sens_matrix_set(const stmdev_ctx_t *ctx,
6689 lsm6dsv16x_xl_fsm_ext_sens_matrix_t val)
6690 {
6691 uint8_t buff[12];
6692 int32_t ret;
6693
6694 buff[1] = (uint8_t)(val.xx / 256U);
6695 buff[0] = (uint8_t)(val.xx - (buff[1] * 256U));
6696 buff[3] = (uint8_t)(val.xy / 256U);
6697 buff[2] = (uint8_t)(val.xy - (buff[3] * 256U));
6698 buff[5] = (uint8_t)(val.xz / 256U);
6699 buff[4] = (uint8_t)(val.xz - (buff[5] * 256U));
6700 buff[7] = (uint8_t)(val.yy / 256U);
6701 buff[6] = (uint8_t)(val.yy - (buff[7] * 256U));
6702 buff[9] = (uint8_t)(val.yz / 256U);
6703 buff[8] = (uint8_t)(val.yz - (buff[9] * 256U));
6704 buff[11] = (uint8_t)(val.zz / 256U);
6705 buff[10] = (uint8_t)(val.zz - (buff[11] * 256U));
6706 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_FSM_EXT_MATRIX_XX_L, (uint8_t *)&buff[0], 12);
6707
6708 return ret;
6709 }
6710
6711 /**
6712 * @brief External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get]
6713 *
6714 * @param ctx read / write interface definitions
6715 * @param val External sensor transformation matrix. The value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
6716 * @retval interface status (MANDATORY: return 0 -> no Error)
6717 *
6718 */
lsm6dsv16x_fsm_ext_sens_matrix_get(const stmdev_ctx_t * ctx,lsm6dsv16x_xl_fsm_ext_sens_matrix_t * val)6719 int32_t lsm6dsv16x_fsm_ext_sens_matrix_get(const stmdev_ctx_t *ctx,
6720 lsm6dsv16x_xl_fsm_ext_sens_matrix_t *val)
6721 {
6722 uint8_t buff[12];
6723 int32_t ret;
6724
6725 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_FSM_EXT_MATRIX_XX_L, &buff[0], 12);
6726 if (ret != 0)
6727 {
6728 return ret;
6729 }
6730
6731 val->xx = buff[1];
6732 val->xx = (val->xx * 256U) + buff[0];
6733 val->xy = buff[3];
6734 val->xy = (val->xy * 256U) + buff[2];
6735 val->xz = buff[5];
6736 val->xz = (val->xz * 256U) + buff[4];
6737 val->yy = buff[7];
6738 val->yy = (val->yy * 256U) + buff[6];
6739 val->yz = buff[9];
6740 val->yz = (val->yz * 256U) + buff[8];
6741 val->zz = buff[11];
6742 val->zz = (val->zz * 256U) + buff[10];
6743
6744 return ret;
6745 }
6746
6747 /**
6748 * @brief External sensor z-axis coordinates rotation.[set]
6749 *
6750 * @param ctx read / write interface definitions
6751 * @param val Z_EQ_Y, Z_EQ_MIN_Y, Z_EQ_X, Z_EQ_MIN_X, Z_EQ_MIN_Z, Z_EQ_Z,
6752 * @retval interface status (MANDATORY: return 0 -> no Error)
6753 *
6754 */
lsm6dsv16x_fsm_ext_sens_z_orient_set(const stmdev_ctx_t * ctx,lsm6dsv16x_fsm_ext_sens_z_orient_t val)6755 int32_t lsm6dsv16x_fsm_ext_sens_z_orient_set(const stmdev_ctx_t *ctx,
6756 lsm6dsv16x_fsm_ext_sens_z_orient_t val)
6757 {
6758 lsm6dsv16x_ext_cfg_a_t ext_cfg_a;
6759 int32_t ret;
6760
6761 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6762 ext_cfg_a.ext_z_axis = (uint8_t)val & 0x07U;
6763 ret += lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6764
6765 return ret;
6766 }
6767
6768 /**
6769 * @brief External sensor z-axis coordinates rotation.[get]
6770 *
6771 * @param ctx read / write interface definitions
6772 * @param val Z_EQ_Y, Z_EQ_MIN_Y, Z_EQ_X, Z_EQ_MIN_X, Z_EQ_MIN_Z, Z_EQ_Z,
6773 * @retval interface status (MANDATORY: return 0 -> no Error)
6774 *
6775 */
lsm6dsv16x_fsm_ext_sens_z_orient_get(const stmdev_ctx_t * ctx,lsm6dsv16x_fsm_ext_sens_z_orient_t * val)6776 int32_t lsm6dsv16x_fsm_ext_sens_z_orient_get(const stmdev_ctx_t *ctx,
6777 lsm6dsv16x_fsm_ext_sens_z_orient_t *val)
6778 {
6779 lsm6dsv16x_ext_cfg_a_t ext_cfg_a;
6780 int32_t ret;
6781
6782 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6783 if (ret != 0)
6784 {
6785 return ret;
6786 }
6787
6788 switch (ext_cfg_a.ext_z_axis)
6789 {
6790 case LSM6DSV16X_Z_EQ_Y:
6791 *val = LSM6DSV16X_Z_EQ_Y;
6792 break;
6793
6794 case LSM6DSV16X_Z_EQ_MIN_Y:
6795 *val = LSM6DSV16X_Z_EQ_MIN_Y;
6796 break;
6797
6798 case LSM6DSV16X_Z_EQ_X:
6799 *val = LSM6DSV16X_Z_EQ_X;
6800 break;
6801
6802 case LSM6DSV16X_Z_EQ_MIN_X:
6803 *val = LSM6DSV16X_Z_EQ_MIN_X;
6804 break;
6805
6806 case LSM6DSV16X_Z_EQ_MIN_Z:
6807 *val = LSM6DSV16X_Z_EQ_MIN_Z;
6808 break;
6809
6810 case LSM6DSV16X_Z_EQ_Z:
6811 *val = LSM6DSV16X_Z_EQ_Z;
6812 break;
6813
6814 default:
6815 *val = LSM6DSV16X_Z_EQ_Y;
6816 break;
6817 }
6818
6819 return ret;
6820 }
6821
6822 /**
6823 * @brief External sensor Y-axis coordinates rotation.[set]
6824 *
6825 * @param ctx read / write interface definitions
6826 * @param val Y_EQ_Y, Y_EQ_MIN_Y, Y_EQ_X, Y_EQ_MIN_X, Y_EQ_MIN_Z, Y_EQ_Z,
6827 * @retval interface status (MANDATORY: return 0 -> no Error)
6828 *
6829 */
lsm6dsv16x_fsm_ext_sens_y_orient_set(const stmdev_ctx_t * ctx,lsm6dsv16x_fsm_ext_sens_y_orient_t val)6830 int32_t lsm6dsv16x_fsm_ext_sens_y_orient_set(const stmdev_ctx_t *ctx,
6831 lsm6dsv16x_fsm_ext_sens_y_orient_t val)
6832 {
6833 lsm6dsv16x_ext_cfg_a_t ext_cfg_a;
6834 int32_t ret;
6835
6836 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6837 if (ret == 0)
6838 {
6839 ext_cfg_a.ext_y_axis = (uint8_t)val & 0x7U;
6840 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6841 }
6842
6843 return ret;
6844 }
6845
6846 /**
6847 * @brief External sensor Y-axis coordinates rotation.[get]
6848 *
6849 * @param ctx read / write interface definitions
6850 * @param val Y_EQ_Y, Y_EQ_MIN_Y, Y_EQ_X, Y_EQ_MIN_X, Y_EQ_MIN_Z, Y_EQ_Z,
6851 * @retval interface status (MANDATORY: return 0 -> no Error)
6852 *
6853 */
lsm6dsv16x_fsm_ext_sens_y_orient_get(const stmdev_ctx_t * ctx,lsm6dsv16x_fsm_ext_sens_y_orient_t * val)6854 int32_t lsm6dsv16x_fsm_ext_sens_y_orient_get(const stmdev_ctx_t *ctx,
6855 lsm6dsv16x_fsm_ext_sens_y_orient_t *val)
6856 {
6857 lsm6dsv16x_ext_cfg_a_t ext_cfg_a;
6858 int32_t ret;
6859
6860 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_A, (uint8_t *)&ext_cfg_a, 1);
6861 if (ret != 0)
6862 {
6863 return ret;
6864 }
6865
6866 switch (ext_cfg_a.ext_y_axis)
6867 {
6868 case LSM6DSV16X_Y_EQ_Y:
6869 *val = LSM6DSV16X_Y_EQ_Y;
6870 break;
6871
6872 case LSM6DSV16X_Y_EQ_MIN_Y:
6873 *val = LSM6DSV16X_Y_EQ_MIN_Y;
6874 break;
6875
6876 case LSM6DSV16X_Y_EQ_X:
6877 *val = LSM6DSV16X_Y_EQ_X;
6878 break;
6879
6880 case LSM6DSV16X_Y_EQ_MIN_X:
6881 *val = LSM6DSV16X_Y_EQ_MIN_X;
6882 break;
6883
6884 case LSM6DSV16X_Y_EQ_MIN_Z:
6885 *val = LSM6DSV16X_Y_EQ_MIN_Z;
6886 break;
6887
6888 case LSM6DSV16X_Y_EQ_Z:
6889 *val = LSM6DSV16X_Y_EQ_Z;
6890 break;
6891
6892 default:
6893 *val = LSM6DSV16X_Y_EQ_Y;
6894 break;
6895 }
6896
6897 return ret;
6898 }
6899
6900 /**
6901 * @brief External sensor X-axis coordinates rotation.[set]
6902 *
6903 * @param ctx read / write interface definitions
6904 * @param val X_EQ_Y, X_EQ_MIN_Y, X_EQ_X, X_EQ_MIN_X, X_EQ_MIN_Z, X_EQ_Z,
6905 * @retval interface status (MANDATORY: return 0 -> no Error)
6906 *
6907 */
lsm6dsv16x_fsm_ext_sens_x_orient_set(const stmdev_ctx_t * ctx,lsm6dsv16x_fsm_ext_sens_x_orient_t val)6908 int32_t lsm6dsv16x_fsm_ext_sens_x_orient_set(const stmdev_ctx_t *ctx,
6909 lsm6dsv16x_fsm_ext_sens_x_orient_t val)
6910 {
6911 lsm6dsv16x_ext_cfg_b_t ext_cfg_b;
6912 int32_t ret;
6913
6914 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1);
6915 if (ret == 0)
6916 {
6917 ext_cfg_b.ext_x_axis = (uint8_t)val & 0x7U;
6918 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1);
6919 }
6920
6921 return ret;
6922 }
6923
6924 /**
6925 * @brief External sensor X-axis coordinates rotation.[get]
6926 *
6927 * @param ctx read / write interface definitions
6928 * @param val X_EQ_Y, X_EQ_MIN_Y, X_EQ_X, X_EQ_MIN_X, X_EQ_MIN_Z, X_EQ_Z,
6929 * @retval interface status (MANDATORY: return 0 -> no Error)
6930 *
6931 */
lsm6dsv16x_fsm_ext_sens_x_orient_get(const stmdev_ctx_t * ctx,lsm6dsv16x_fsm_ext_sens_x_orient_t * val)6932 int32_t lsm6dsv16x_fsm_ext_sens_x_orient_get(const stmdev_ctx_t *ctx,
6933 lsm6dsv16x_fsm_ext_sens_x_orient_t *val)
6934 {
6935 lsm6dsv16x_ext_cfg_b_t ext_cfg_b;
6936 int32_t ret;
6937
6938 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EXT_CFG_B, (uint8_t *)&ext_cfg_b, 1);
6939 if (ret != 0)
6940 {
6941 return ret;
6942 }
6943
6944 switch (ext_cfg_b.ext_x_axis)
6945 {
6946 case LSM6DSV16X_X_EQ_Y:
6947 *val = LSM6DSV16X_X_EQ_Y;
6948 break;
6949
6950 case LSM6DSV16X_X_EQ_MIN_Y:
6951 *val = LSM6DSV16X_X_EQ_MIN_Y;
6952 break;
6953
6954 case LSM6DSV16X_X_EQ_X:
6955 *val = LSM6DSV16X_X_EQ_X;
6956 break;
6957
6958 case LSM6DSV16X_X_EQ_MIN_X:
6959 *val = LSM6DSV16X_X_EQ_MIN_X;
6960 break;
6961
6962 case LSM6DSV16X_X_EQ_MIN_Z:
6963 *val = LSM6DSV16X_X_EQ_MIN_Z;
6964 break;
6965
6966 case LSM6DSV16X_X_EQ_Z:
6967 *val = LSM6DSV16X_X_EQ_Z;
6968 break;
6969
6970 default:
6971 *val = LSM6DSV16X_X_EQ_Y;
6972 break;
6973 }
6974
6975 return ret;
6976 }
6977
6978 /**
6979 * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[set]
6980 *
6981 * @param ctx read / write interface definitions
6982 * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.
6983 * @retval interface status (MANDATORY: return 0 -> no Error)
6984 *
6985 */
lsm6dsv16x_fsm_long_cnt_timeout_set(const stmdev_ctx_t * ctx,uint16_t val)6986 int32_t lsm6dsv16x_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val)
6987 {
6988 uint8_t buff[2];
6989 int32_t ret;
6990
6991 buff[1] = (uint8_t)(val / 256U);
6992 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6993 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_LC_TIMEOUT_L,
6994 (uint8_t *)&buff[0], 2);
6995
6996 return ret;
6997 }
6998
6999 /**
7000 * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[get]
7001 *
7002 * @param ctx read / write interface definitions
7003 * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.
7004 * @retval interface status (MANDATORY: return 0 -> no Error)
7005 *
7006 */
lsm6dsv16x_fsm_long_cnt_timeout_get(const stmdev_ctx_t * ctx,uint16_t * val)7007 int32_t lsm6dsv16x_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val)
7008 {
7009 uint8_t buff[2];
7010 int32_t ret;
7011
7012 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_LC_TIMEOUT_L, &buff[0],
7013 2);
7014 if (ret != 0)
7015 {
7016 return ret;
7017 }
7018
7019 *val = buff[1];
7020 *val = (*val * 256U) + buff[0];
7021
7022 return ret;
7023 }
7024
7025 /**
7026 * @brief FSM number of programs.[set]
7027 *
7028 * @param ctx read / write interface definitions
7029 * @param val FSM number of programs.
7030 * @retval interface status (MANDATORY: return 0 -> no Error)
7031 *
7032 */
lsm6dsv16x_fsm_number_of_programs_set(const stmdev_ctx_t * ctx,uint8_t val)7033 int32_t lsm6dsv16x_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val)
7034 {
7035 lsm6dsv16x_fsm_programs_t fsm_programs;
7036 int32_t ret;
7037
7038 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_PROGRAMS,
7039 (uint8_t *)&fsm_programs, 1);
7040 if (ret == 0)
7041 {
7042 fsm_programs.fsm_n_prog = val;
7043 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_PROGRAMS,
7044 (uint8_t *)&fsm_programs, 1);
7045 }
7046
7047 return ret;
7048 }
7049
7050 /**
7051 * @brief FSM number of programs.[get]
7052 *
7053 * @param ctx read / write interface definitions
7054 * @param val FSM number of programs.
7055 * @retval interface status (MANDATORY: return 0 -> no Error)
7056 *
7057 */
lsm6dsv16x_fsm_number_of_programs_get(const stmdev_ctx_t * ctx,uint8_t * val)7058 int32_t lsm6dsv16x_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val)
7059 {
7060 lsm6dsv16x_fsm_programs_t fsm_programs;
7061 int32_t ret;
7062
7063 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_PROGRAMS,
7064 (uint8_t *)&fsm_programs, 1);
7065 *val = fsm_programs.fsm_n_prog;
7066
7067 return ret;
7068 }
7069
7070 /**
7071 * @brief FSM start address. First available address is 0x35C.[set]
7072 *
7073 * @param ctx read / write interface definitions
7074 * @param val FSM start address. First available address is 0x35C.
7075 * @retval interface status (MANDATORY: return 0 -> no Error)
7076 *
7077 */
lsm6dsv16x_fsm_start_address_set(const stmdev_ctx_t * ctx,uint16_t val)7078 int32_t lsm6dsv16x_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val)
7079 {
7080 uint8_t buff[2];
7081 int32_t ret;
7082
7083 buff[1] = (uint8_t)(val / 256U);
7084 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7085 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_START_ADD_L,
7086 (uint8_t *)&buff[0], 2);
7087
7088 return ret;
7089 }
7090
7091 /**
7092 * @brief FSM start address. First available address is 0x35C.[get]
7093 *
7094 * @param ctx read / write interface definitions
7095 * @param val FSM start address. First available address is 0x35C.
7096 * @retval interface status (MANDATORY: return 0 -> no Error)
7097 *
7098 */
lsm6dsv16x_fsm_start_address_get(const stmdev_ctx_t * ctx,uint16_t * val)7099 int32_t lsm6dsv16x_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val)
7100 {
7101 uint8_t buff[2];
7102 int32_t ret;
7103
7104 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_FSM_START_ADD_L, &buff[0], 2);
7105 if (ret != 0)
7106 {
7107 return ret;
7108 }
7109
7110 *val = buff[1];
7111 *val = (*val * 256U) + buff[0];
7112
7113 return ret;
7114 }
7115
7116 /**
7117 * @}
7118 *
7119 */
7120
7121 /**
7122 * @defgroup Free fall
7123 * @brief This section group all the functions concerning the free
7124 * fall detection.
7125 * @{
7126 *
7127 */
7128
7129 /**
7130 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set]
7131 *
7132 * @param ctx read / write interface definitions
7133 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
7134 * @retval interface status (MANDATORY: return 0 -> no Error)
7135 *
7136 */
lsm6dsv16x_ff_time_windows_set(const stmdev_ctx_t * ctx,uint8_t val)7137 int32_t lsm6dsv16x_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val)
7138 {
7139 lsm6dsv16x_wake_up_dur_t wake_up_dur;
7140 lsm6dsv16x_free_fall_t free_fall;
7141 int32_t ret;
7142
7143 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
7144 wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
7145 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
7146 if (ret != 0)
7147 {
7148 return ret;
7149 }
7150
7151 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1);
7152 free_fall.ff_dur = (uint8_t)val & 0x1FU;
7153 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1);
7154
7155 return ret;
7156 }
7157
7158 /**
7159 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get]
7160 *
7161 * @param ctx read / write interface definitions
7162 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
7163 * @retval interface status (MANDATORY: return 0 -> no Error)
7164 *
7165 */
lsm6dsv16x_ff_time_windows_get(const stmdev_ctx_t * ctx,uint8_t * val)7166 int32_t lsm6dsv16x_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val)
7167 {
7168 lsm6dsv16x_wake_up_dur_t wake_up_dur;
7169 lsm6dsv16x_free_fall_t free_fall;
7170 int32_t ret;
7171
7172 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
7173 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1);
7174
7175 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
7176
7177 return ret;
7178 }
7179
7180 /**
7181 * @brief Free fall threshold setting.[set]
7182 *
7183 * @param ctx read / write interface definitions
7184 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
7185 * @retval interface status (MANDATORY: return 0 -> no Error)
7186 *
7187 */
lsm6dsv16x_ff_thresholds_set(const stmdev_ctx_t * ctx,lsm6dsv16x_ff_thresholds_t val)7188 int32_t lsm6dsv16x_ff_thresholds_set(const stmdev_ctx_t *ctx,
7189 lsm6dsv16x_ff_thresholds_t val)
7190 {
7191 lsm6dsv16x_free_fall_t free_fall;
7192 int32_t ret;
7193
7194 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1);
7195 if (ret == 0)
7196 {
7197 free_fall.ff_ths = (uint8_t)val & 0x7U;
7198 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1);
7199 }
7200
7201 return ret;
7202 }
7203
7204 /**
7205 * @brief Free fall threshold setting.[get]
7206 *
7207 * @param ctx read / write interface definitions
7208 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
7209 * @retval interface status (MANDATORY: return 0 -> no Error)
7210 *
7211 */
lsm6dsv16x_ff_thresholds_get(const stmdev_ctx_t * ctx,lsm6dsv16x_ff_thresholds_t * val)7212 int32_t lsm6dsv16x_ff_thresholds_get(const stmdev_ctx_t *ctx,
7213 lsm6dsv16x_ff_thresholds_t *val)
7214 {
7215 lsm6dsv16x_free_fall_t free_fall;
7216 int32_t ret;
7217
7218 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FREE_FALL, (uint8_t *)&free_fall, 1);
7219 if (ret != 0)
7220 {
7221 return ret;
7222 }
7223
7224 switch (free_fall.ff_ths)
7225 {
7226 case LSM6DSV16X_156_mg:
7227 *val = LSM6DSV16X_156_mg;
7228 break;
7229
7230 case LSM6DSV16X_219_mg:
7231 *val = LSM6DSV16X_219_mg;
7232 break;
7233
7234 case LSM6DSV16X_250_mg:
7235 *val = LSM6DSV16X_250_mg;
7236 break;
7237
7238 case LSM6DSV16X_312_mg:
7239 *val = LSM6DSV16X_312_mg;
7240 break;
7241
7242 case LSM6DSV16X_344_mg:
7243 *val = LSM6DSV16X_344_mg;
7244 break;
7245
7246 case LSM6DSV16X_406_mg:
7247 *val = LSM6DSV16X_406_mg;
7248 break;
7249
7250 case LSM6DSV16X_469_mg:
7251 *val = LSM6DSV16X_469_mg;
7252 break;
7253
7254 case LSM6DSV16X_500_mg:
7255 *val = LSM6DSV16X_500_mg;
7256 break;
7257
7258 default:
7259 *val = LSM6DSV16X_156_mg;
7260 break;
7261 }
7262
7263 return ret;
7264 }
7265
7266 /**
7267 * @}
7268 *
7269 */
7270
7271 /**
7272 * @defgroup Machine Learning Core (MLC)
7273 * @brief This section group all the functions concerning the
7274 * usage of Machine Learning Core
7275 * @{
7276 *
7277 */
7278
7279 /**
7280 * @brief It enables Machine Learning Core feature (MLC).
7281 * When the Machine Learning Core is enabled the Finite State Machine (FSM)
7282 * programs are executed before executing the MLC algorithms.[set]
7283 *
7284 * @param ctx read / write interface definitions
7285 * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM,
7286 * @retval interface status (MANDATORY: return 0 -> no Error)
7287 *
7288 */
lsm6dsv16x_mlc_set(const stmdev_ctx_t * ctx,lsm6dsv16x_mlc_mode_t val)7289 int32_t lsm6dsv16x_mlc_set(const stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t val)
7290 {
7291 lsm6dsv16x_emb_func_en_b_t emb_en_b;
7292 lsm6dsv16x_emb_func_en_a_t emb_en_a;
7293 int32_t ret;
7294
7295 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
7296 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
7297 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
7298 if (ret != 0)
7299 {
7300 goto exit;
7301 }
7302
7303 switch (val)
7304 {
7305 case LSM6DSV16X_MLC_OFF:
7306 emb_en_a.mlc_before_fsm_en = 0;
7307 emb_en_b.mlc_en = 0;
7308 break;
7309 case LSM6DSV16X_MLC_ON:
7310 emb_en_a.mlc_before_fsm_en = 0;
7311 emb_en_b.mlc_en = 1;
7312 break;
7313 case LSM6DSV16X_MLC_ON_BEFORE_FSM:
7314 emb_en_a.mlc_before_fsm_en = 1;
7315 emb_en_b.mlc_en = 0;
7316 break;
7317 default:
7318 break;
7319 }
7320
7321 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
7322 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
7323
7324 exit:
7325 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
7326
7327 return ret;
7328 }
7329
7330 /**
7331 * @brief It enables Machine Learning Core feature (MLC).
7332 * When the Machine Learning Core is enabled the Finite State Machine (FSM)
7333 * programs are executed before executing the MLC algorithms.[get]
7334 *
7335 * @param ctx read / write interface definitions
7336 * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM,
7337 * @retval interface status (MANDATORY: return 0 -> no Error)
7338 *
7339 */
lsm6dsv16x_mlc_get(const stmdev_ctx_t * ctx,lsm6dsv16x_mlc_mode_t * val)7340 int32_t lsm6dsv16x_mlc_get(const stmdev_ctx_t *ctx, lsm6dsv16x_mlc_mode_t *val)
7341 {
7342 lsm6dsv16x_emb_func_en_b_t emb_en_b;
7343 lsm6dsv16x_emb_func_en_a_t emb_en_a;
7344 int32_t ret;
7345
7346 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
7347 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
7348 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
7349 if (ret != 0)
7350 {
7351 goto exit;
7352 }
7353
7354 if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U)
7355 {
7356 *val = LSM6DSV16X_MLC_OFF;
7357 }
7358 else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U)
7359 {
7360 *val = LSM6DSV16X_MLC_ON;
7361 }
7362 else if (emb_en_a.mlc_before_fsm_en == 1U)
7363 {
7364 *val = LSM6DSV16X_MLC_ON_BEFORE_FSM;
7365 }
7366 else
7367 {
7368 /* Do nothing */
7369 }
7370
7371 exit:
7372 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
7373
7374 return ret;
7375 }
7376
7377 /**
7378 * @brief Machine Learning Core Output Data Rate (ODR) configuration.[set]
7379 *
7380 * @param ctx read / write interface definitions
7381 * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz,
7382 * @retval interface status (MANDATORY: return 0 -> no Error)
7383 *
7384 */
lsm6dsv16x_mlc_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv16x_mlc_data_rate_t val)7385 int32_t lsm6dsv16x_mlc_data_rate_set(const stmdev_ctx_t *ctx,
7386 lsm6dsv16x_mlc_data_rate_t val)
7387 {
7388 lsm6dsv16x_mlc_odr_t mlc_odr;
7389 int32_t ret;
7390
7391 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
7392 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MLC_ODR, (uint8_t *)&mlc_odr, 1);
7393 if (ret != 0)
7394 {
7395 goto exit;
7396 }
7397
7398 mlc_odr.mlc_odr = (uint8_t)val & 0x07U;
7399 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MLC_ODR, (uint8_t *)&mlc_odr, 1);
7400
7401 exit:
7402 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
7403
7404 return ret;
7405 }
7406
7407 /**
7408 * @brief Machine Learning Core Output Data Rate (ODR) configuration.[get]
7409 *
7410 * @param ctx read / write interface definitions
7411 * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz,
7412 * @retval interface status (MANDATORY: return 0 -> no Error)
7413 *
7414 */
lsm6dsv16x_mlc_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv16x_mlc_data_rate_t * val)7415 int32_t lsm6dsv16x_mlc_data_rate_get(const stmdev_ctx_t *ctx,
7416 lsm6dsv16x_mlc_data_rate_t *val)
7417 {
7418 lsm6dsv16x_mlc_odr_t mlc_odr;
7419 int32_t ret;
7420
7421 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
7422 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MLC_ODR, (uint8_t *)&mlc_odr, 1);
7423 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
7424 if (ret != 0)
7425 {
7426 return ret;
7427 }
7428
7429 switch (mlc_odr.mlc_odr)
7430 {
7431 case LSM6DSV16X_MLC_15Hz:
7432 *val = LSM6DSV16X_MLC_15Hz;
7433 break;
7434
7435 case LSM6DSV16X_MLC_30Hz:
7436 *val = LSM6DSV16X_MLC_30Hz;
7437 break;
7438
7439 case LSM6DSV16X_MLC_60Hz:
7440 *val = LSM6DSV16X_MLC_60Hz;
7441 break;
7442
7443 case LSM6DSV16X_MLC_120Hz:
7444 *val = LSM6DSV16X_MLC_120Hz;
7445 break;
7446
7447 case LSM6DSV16X_MLC_240Hz:
7448 *val = LSM6DSV16X_MLC_240Hz;
7449 break;
7450
7451 case LSM6DSV16X_MLC_480Hz:
7452 *val = LSM6DSV16X_MLC_480Hz;
7453 break;
7454
7455 case LSM6DSV16X_MLC_960Hz:
7456 *val = LSM6DSV16X_MLC_960Hz;
7457 break;
7458
7459 default:
7460 *val = LSM6DSV16X_MLC_15Hz;
7461 break;
7462 }
7463
7464 return ret;
7465 }
7466
7467 /**
7468 * @brief Output value of all MLC decision trees.[get]
7469 *
7470 * @param ctx read / write interface definitions
7471 * @param val Output value of all MLC decision trees.
7472 * @retval interface status (MANDATORY: return 0 -> no Error)
7473 *
7474 */
lsm6dsv16x_mlc_out_get(const stmdev_ctx_t * ctx,lsm6dsv16x_mlc_out_t * val)7475 int32_t lsm6dsv16x_mlc_out_get(const stmdev_ctx_t *ctx, lsm6dsv16x_mlc_out_t *val)
7476 {
7477 int32_t ret;
7478
7479 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
7480 if (ret == 0)
7481 {
7482 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MLC1_SRC, (uint8_t *)val, 4);
7483 }
7484 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
7485
7486 return ret;
7487 }
7488
7489 /**
7490 * @brief External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB).[set]
7491 *
7492 * @param ctx read / write interface definitions
7493 * @param val External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB).
7494 * @retval interface status (MANDATORY: return 0 -> no Error)
7495 *
7496 */
lsm6dsv16x_mlc_ext_sens_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)7497 int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val)
7498 {
7499 uint8_t buff[2];
7500 int32_t ret;
7501
7502 buff[1] = (uint8_t)(val / 256U);
7503 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7504
7505 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_MLC_EXT_SENSITIVITY_L,
7506 (uint8_t *)&buff[0], 2);
7507
7508 return ret;
7509 }
7510
7511 /**
7512 * @brief External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB).[get]
7513 *
7514 * @param ctx read / write interface definitions
7515 * @param val External sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the external sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).Default value is 0x3C00 (when using an external magnetometer this value corresponds to 1 gauss/LSB).
7516 * @retval interface status (MANDATORY: return 0 -> no Error)
7517 *
7518 */
lsm6dsv16x_mlc_ext_sens_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)7519 int32_t lsm6dsv16x_mlc_ext_sens_sensitivity_get(const stmdev_ctx_t *ctx,
7520 uint16_t *val)
7521 {
7522 uint8_t buff[2];
7523 int32_t ret;
7524
7525 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_MLC_EXT_SENSITIVITY_L,
7526 &buff[0], 2);
7527 if (ret != 0)
7528 {
7529 return ret;
7530 }
7531
7532 *val = buff[1];
7533 *val = (*val * 256U) + buff[0];
7534
7535 return ret;
7536 }
7537
7538 /**
7539 * @}
7540 *
7541 */
7542
7543 /**
7544 * @defgroup Optical Image Stabilization (OIS)
7545 * @brief This section groups all the functions concerning
7546 * Optical Image Stabilization (OIS).
7547 * @{
7548 *
7549 */
7550
7551 /**
7552 * @brief Enable the full control of OIS configurations from the UI (User Interface).[set]
7553 *
7554 * @param ctx read / write interface definitions
7555 * @param val OIS_CTRL_FROM_OIS, OIS_CTRL_FROM_UI,
7556 * @retval interface status (MANDATORY: return 0 -> no Error)
7557 *
7558 */
lsm6dsv16x_ois_ctrl_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16x_ois_ctrl_mode_t val)7559 int32_t lsm6dsv16x_ois_ctrl_mode_set(const stmdev_ctx_t *ctx,
7560 lsm6dsv16x_ois_ctrl_mode_t val)
7561 {
7562 lsm6dsv16x_func_cfg_access_t func_cfg_access;
7563 int32_t ret;
7564
7565 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
7566 if (ret == 0)
7567 {
7568 func_cfg_access.ois_ctrl_from_ui = (uint8_t)val & 0x1U;
7569 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
7570 }
7571
7572 return ret;
7573 }
7574
7575 /**
7576 * @brief Enable the full control of OIS configurations from the UI (User Interface).[get]
7577 *
7578 * @param ctx read / write interface definitions
7579 * @param val OIS_CTRL_FROM_OIS, OIS_CTRL_FROM_UI,
7580 * @retval interface status (MANDATORY: return 0 -> no Error)
7581 *
7582 */
lsm6dsv16x_ois_ctrl_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16x_ois_ctrl_mode_t * val)7583 int32_t lsm6dsv16x_ois_ctrl_mode_get(const stmdev_ctx_t *ctx,
7584 lsm6dsv16x_ois_ctrl_mode_t *val)
7585 {
7586 lsm6dsv16x_func_cfg_access_t func_cfg_access;
7587 int32_t ret;
7588
7589 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
7590 if (ret != 0)
7591 {
7592 return ret;
7593 }
7594
7595 switch (func_cfg_access.ois_ctrl_from_ui)
7596 {
7597 case LSM6DSV16X_OIS_CTRL_FROM_OIS:
7598 *val = LSM6DSV16X_OIS_CTRL_FROM_OIS;
7599 break;
7600
7601 case LSM6DSV16X_OIS_CTRL_FROM_UI:
7602 *val = LSM6DSV16X_OIS_CTRL_FROM_UI;
7603 break;
7604
7605 default:
7606 *val = LSM6DSV16X_OIS_CTRL_FROM_OIS;
7607 break;
7608 }
7609
7610 return ret;
7611 }
7612
7613 /**
7614 * @brief Resets the control registers of OIS from the UI (User Interface)[set]
7615 *
7616 * @param ctx read / write interface definitions
7617 * @param val Resets the control registers of OIS from the UI (User Interface)
7618 * @retval interface status (MANDATORY: return 0 -> no Error)
7619 *
7620 */
lsm6dsv16x_ois_reset_set(const stmdev_ctx_t * ctx,int8_t val)7621 int32_t lsm6dsv16x_ois_reset_set(const stmdev_ctx_t *ctx, int8_t val)
7622 {
7623 lsm6dsv16x_func_cfg_access_t func_cfg_access;
7624 int32_t ret;
7625
7626 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
7627 if (ret == 0)
7628 {
7629 func_cfg_access.spi2_reset = (uint8_t)val;
7630 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
7631 }
7632
7633 return ret;
7634 }
7635
7636 /**
7637 * @brief Resets the control registers of OIS from the UI (User Interface)[get]
7638 *
7639 * @param ctx read / write interface definitions
7640 * @param val Resets the control registers of OIS from the UI (User Interface)
7641 * @retval interface status (MANDATORY: return 0 -> no Error)
7642 *
7643 */
lsm6dsv16x_ois_reset_get(const stmdev_ctx_t * ctx,int8_t * val)7644 int32_t lsm6dsv16x_ois_reset_get(const stmdev_ctx_t *ctx, int8_t *val)
7645 {
7646 lsm6dsv16x_func_cfg_access_t func_cfg_access;
7647 int32_t ret;
7648
7649 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
7650 *val = (int8_t)func_cfg_access.spi2_reset;
7651
7652 return ret;
7653 }
7654
7655 /**
7656 * @brief Enable/disable pull up on OIS interface.[set]
7657 *
7658 * @param ctx read / write interface definitions
7659 * @param val Enable/disable pull up on OIS interface.
7660 * @retval interface status (MANDATORY: return 0 -> no Error)
7661 *
7662 */
lsm6dsv16x_ois_interface_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)7663 int32_t lsm6dsv16x_ois_interface_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
7664 {
7665 lsm6dsv16x_pin_ctrl_t pin_ctrl;
7666 int32_t ret;
7667
7668 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7669 if (ret == 0)
7670 {
7671 pin_ctrl.ois_pu_dis = val;
7672 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7673 }
7674
7675 return ret;
7676 }
7677
7678 /**
7679 * @brief Enable/disable pull up on OIS interface.[get]
7680 *
7681 * @param ctx read / write interface definitions
7682 * @param val Enable/disable pull up on OIS interface.
7683 * @retval interface status (MANDATORY: return 0 -> no Error)
7684 *
7685 */
lsm6dsv16x_ois_interface_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)7686 int32_t lsm6dsv16x_ois_interface_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
7687 {
7688 lsm6dsv16x_pin_ctrl_t pin_ctrl;
7689 int32_t ret;
7690
7691 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7692 *val = pin_ctrl.ois_pu_dis;
7693
7694 return ret;
7695 }
7696
7697 /**
7698 * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[set]
7699 *
7700 * @param ctx read / write interface definitions
7701 * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.
7702 * @retval interface status (MANDATORY: return 0 -> no Error)
7703 *
7704 */
lsm6dsv16x_ois_handshake_from_ui_set(const stmdev_ctx_t * ctx,lsm6dsv16x_ois_handshake_t val)7705 int32_t lsm6dsv16x_ois_handshake_from_ui_set(const stmdev_ctx_t *ctx,
7706 lsm6dsv16x_ois_handshake_t val)
7707 {
7708 lsm6dsv16x_ui_handshake_ctrl_t ui_handshake_ctrl;
7709 int32_t ret;
7710
7711 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1);
7712 if (ret == 0)
7713 {
7714 ui_handshake_ctrl.ui_shared_ack = val.ack;
7715 ui_handshake_ctrl.ui_shared_req = val.req;
7716 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1);
7717 }
7718
7719 return ret;
7720 }
7721
7722 /**
7723 * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[get]
7724 *
7725 * @param ctx read / write interface definitions
7726 * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.
7727 * @retval interface status (MANDATORY: return 0 -> no Error)
7728 *
7729 */
lsm6dsv16x_ois_handshake_from_ui_get(const stmdev_ctx_t * ctx,lsm6dsv16x_ois_handshake_t * val)7730 int32_t lsm6dsv16x_ois_handshake_from_ui_get(const stmdev_ctx_t *ctx,
7731 lsm6dsv16x_ois_handshake_t *val)
7732 {
7733 lsm6dsv16x_ui_handshake_ctrl_t ui_handshake_ctrl;
7734 int32_t ret;
7735
7736 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_HANDSHAKE_CTRL, (uint8_t *)&ui_handshake_ctrl, 1);
7737 if (ret != 0)
7738 {
7739 return ret;
7740 }
7741
7742 val->ack = ui_handshake_ctrl.ui_shared_ack;
7743 val->req = ui_handshake_ctrl.ui_shared_req;
7744
7745 return ret;
7746 }
7747
7748 /**
7749 * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[set]
7750 *
7751 * @param ctx read / write interface definitions
7752 * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.
7753 * @retval interface status (MANDATORY: return 0 -> no Error)
7754 *
7755 */
lsm6dsv16x_ois_handshake_from_ois_set(const stmdev_ctx_t * ctx,lsm6dsv16x_ois_handshake_t val)7756 int32_t lsm6dsv16x_ois_handshake_from_ois_set(const stmdev_ctx_t *ctx,
7757 lsm6dsv16x_ois_handshake_t val)
7758 {
7759 lsm6dsv16x_spi2_handshake_ctrl_t spi2_handshake_ctrl;
7760 int32_t ret;
7761
7762 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1);
7763 if (ret == 0)
7764 {
7765 spi2_handshake_ctrl.spi2_shared_ack = val.ack;
7766 spi2_handshake_ctrl.spi2_shared_req = val.req;
7767 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1);
7768 }
7769
7770 return ret;
7771 }
7772
7773 /**
7774 * @brief Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.[get]
7775 *
7776 * @param ctx read / write interface definitions
7777 * @param val Handshake for (User Interface) UI / (OIS interface) SPI2 shared registers. ACK: This bit acknowledges the handshake. If the secondary interface is not accessing the shared registers, this bit is set to 1 by the device and the R/W operation on the UI_SPI2_SHARED registers is allowed on the primary interface. REQ: This bit is used by the primary interface master to request access to the UI_SPI2_SHARED registers. When the R/W operation is finished, the master must reset this bit.
7778 * @retval interface status (MANDATORY: return 0 -> no Error)
7779 *
7780 */
lsm6dsv16x_ois_handshake_from_ois_get(const stmdev_ctx_t * ctx,lsm6dsv16x_ois_handshake_t * val)7781 int32_t lsm6dsv16x_ois_handshake_from_ois_get(const stmdev_ctx_t *ctx,
7782 lsm6dsv16x_ois_handshake_t *val)
7783 {
7784 lsm6dsv16x_spi2_handshake_ctrl_t spi2_handshake_ctrl;
7785 int32_t ret;
7786
7787 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SPI2_HANDSHAKE_CTRL, (uint8_t *)&spi2_handshake_ctrl, 1);
7788 if (ret != 0)
7789 {
7790 return ret;
7791 }
7792
7793 val->ack = spi2_handshake_ctrl.spi2_shared_ack;
7794 val->req = spi2_handshake_ctrl.spi2_shared_req;
7795
7796 return ret;
7797 }
7798
7799 /**
7800 * @brief User interface (UI) / SPI2 (OIS) shared registers[set]
7801 *
7802 * @param ctx read / write interface definitions
7803 * @param val User interface (UI) / SPI2 (OIS) shared registers
7804 * @retval interface status (MANDATORY: return 0 -> no Error)
7805 *
7806 */
lsm6dsv16x_ois_shared_set(const stmdev_ctx_t * ctx,uint8_t val[6])7807 int32_t lsm6dsv16x_ois_shared_set(const stmdev_ctx_t *ctx, uint8_t val[6])
7808 {
7809 int32_t ret;
7810
7811 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_SPI2_SHARED_0, val, 6);
7812
7813 return ret;
7814 }
7815
7816 /**
7817 * @brief User interface (UI) / SPI2 (OIS) shared registers[get]
7818 *
7819 * @param ctx read / write interface definitions
7820 * @param val User interface (UI) / SPI2 (OIS) shared registers
7821 * @retval interface status (MANDATORY: return 0 -> no Error)
7822 *
7823 */
lsm6dsv16x_ois_shared_get(const stmdev_ctx_t * ctx,uint8_t val[6])7824 int32_t lsm6dsv16x_ois_shared_get(const stmdev_ctx_t *ctx, uint8_t val[6])
7825 {
7826 int32_t ret;
7827
7828 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_SPI2_SHARED_0, val, 6);
7829
7830 return ret;
7831 }
7832
7833 /**
7834 * @brief In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set]
7835 *
7836 * @param ctx read / write interface definitions
7837 * @param val In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data.
7838 * @retval interface status (MANDATORY: return 0 -> no Error)
7839 *
7840 */
lsm6dsv16x_ois_on_spi2_set(const stmdev_ctx_t * ctx,uint8_t val)7841 int32_t lsm6dsv16x_ois_on_spi2_set(const stmdev_ctx_t *ctx, uint8_t val)
7842 {
7843 lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois;
7844 int32_t ret;
7845
7846 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7847 if (ret == 0)
7848 {
7849 ui_ctrl1_ois.spi2_read_en = val;
7850 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7851 }
7852
7853 return ret;
7854 }
7855
7856 /**
7857 * @brief In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[get]
7858 *
7859 * @param ctx read / write interface definitions
7860 * @param val In User Interface (UI) full control mode, enables SPI2 (OIS Interface) for reading OIS data.
7861 * @retval interface status (MANDATORY: return 0 -> no Error)
7862 *
7863 */
lsm6dsv16x_ois_on_spi2_get(const stmdev_ctx_t * ctx,uint8_t * val)7864 int32_t lsm6dsv16x_ois_on_spi2_get(const stmdev_ctx_t *ctx, uint8_t *val)
7865 {
7866 lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois;
7867 int32_t ret;
7868
7869 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7870 *val = ui_ctrl1_ois.spi2_read_en;
7871
7872 return ret;
7873 }
7874
7875 /**
7876 * @brief Enables gyroscope/accelerometer OIS chain. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set]
7877 *
7878 * @param ctx read / write interface definitions
7879 * @param val Enables gyroscope/accelerometer OIS chain.
7880 * @retval interface status (MANDATORY: return 0 -> no Error)
7881 *
7882 */
lsm6dsv16x_ois_chain_set(const stmdev_ctx_t * ctx,lsm6dsv16x_ois_chain_t val)7883 int32_t lsm6dsv16x_ois_chain_set(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_chain_t val)
7884 {
7885 lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois;
7886 int32_t ret;
7887
7888 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7889 if (ret == 0)
7890 {
7891 ui_ctrl1_ois.ois_g_en = val.gy;
7892 ui_ctrl1_ois.ois_xl_en = val.xl;
7893 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7894 }
7895
7896 return ret;
7897 }
7898
7899 /**
7900 * @brief Enables gyroscope/accelerometer OIS chain.[get]
7901 *
7902 * @param ctx read / write interface definitions
7903 * @param val Enables gyroscope/accelerometer OIS chain.
7904 * @retval interface status (MANDATORY: return 0 -> no Error)
7905 *
7906 */
lsm6dsv16x_ois_chain_get(const stmdev_ctx_t * ctx,lsm6dsv16x_ois_chain_t * val)7907 int32_t lsm6dsv16x_ois_chain_get(const stmdev_ctx_t *ctx, lsm6dsv16x_ois_chain_t *val)
7908 {
7909 lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois;
7910 int32_t ret;
7911
7912 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
7913 if (ret != 0)
7914 {
7915 return ret;
7916 }
7917
7918 val->gy = ui_ctrl1_ois.ois_g_en;
7919 val->xl = ui_ctrl1_ois.ois_xl_en;
7920
7921 return ret;
7922 }
7923
7924 /**
7925 * @brief Gyroscope OIS full-scale selection[set]
7926 *
7927 * @param ctx read / write interface definitions
7928 * @param val OIS_125dps, OIS_250dps, OIS_500dps, OIS_1000dps, OIS_2000dps,
7929 * @retval interface status (MANDATORY: return 0 -> no Error)
7930 *
7931 */
lsm6dsv16x_ois_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv16x_ois_gy_full_scale_t val)7932 int32_t lsm6dsv16x_ois_gy_full_scale_set(const stmdev_ctx_t *ctx,
7933 lsm6dsv16x_ois_gy_full_scale_t val)
7934 {
7935 lsm6dsv16x_ui_ctrl2_ois_t ui_ctrl2_ois;
7936 int32_t ret;
7937
7938 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
7939 if (ret == 0)
7940 {
7941 ui_ctrl2_ois.fs_g_ois = (uint8_t)val & 0x03U;
7942 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
7943 }
7944
7945 return ret;
7946 }
7947
7948 /**
7949 * @brief Gyroscope OIS full-scale selection[get]
7950 *
7951 * @param ctx read / write interface definitions
7952 * @param val OIS_125dps, OIS_250dps, OIS_500dps, OIS_1000dps, OIS_2000dps,
7953 * @retval interface status (MANDATORY: return 0 -> no Error)
7954 *
7955 */
lsm6dsv16x_ois_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv16x_ois_gy_full_scale_t * val)7956 int32_t lsm6dsv16x_ois_gy_full_scale_get(const stmdev_ctx_t *ctx,
7957 lsm6dsv16x_ois_gy_full_scale_t *val)
7958 {
7959 lsm6dsv16x_ui_ctrl2_ois_t ui_ctrl2_ois;
7960 int32_t ret;
7961
7962 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL2_OIS, (uint8_t *)&ui_ctrl2_ois, 1);
7963 if (ret != 0)
7964 {
7965 return ret;
7966 }
7967
7968 switch (ui_ctrl2_ois.fs_g_ois)
7969 {
7970 case LSM6DSV16X_OIS_125dps:
7971 *val = LSM6DSV16X_OIS_125dps;
7972 break;
7973
7974 case LSM6DSV16X_OIS_250dps:
7975 *val = LSM6DSV16X_OIS_250dps;
7976 break;
7977
7978 case LSM6DSV16X_OIS_500dps:
7979 *val = LSM6DSV16X_OIS_500dps;
7980 break;
7981
7982 case LSM6DSV16X_OIS_1000dps:
7983 *val = LSM6DSV16X_OIS_1000dps;
7984 break;
7985
7986 case LSM6DSV16X_OIS_2000dps:
7987 *val = LSM6DSV16X_OIS_2000dps;
7988 break;
7989
7990 default:
7991 *val = LSM6DSV16X_OIS_125dps;
7992 break;
7993 }
7994
7995 return ret;
7996 }
7997
7998 /**
7999 * @brief Selects accelerometer OIS channel full-scale.[set]
8000 *
8001 * @param ctx read / write interface definitions
8002 * @param val lsm6dsv16x_ois_xl_full_scale_t
8003 * @retval interface status (MANDATORY: return 0 -> no Error)
8004 *
8005 */
lsm6dsv16x_ois_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv16x_ois_xl_full_scale_t val)8006 int32_t lsm6dsv16x_ois_xl_full_scale_set(const stmdev_ctx_t *ctx,
8007 lsm6dsv16x_ois_xl_full_scale_t val)
8008 {
8009 lsm6dsv16x_ui_ctrl3_ois_t ui_ctrl3_ois;
8010 int32_t ret;
8011
8012 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
8013 if (ret == 0)
8014 {
8015 ui_ctrl3_ois.fs_xl_ois = (uint8_t)val & 0x3U;
8016 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
8017 }
8018
8019 return ret;
8020 }
8021
8022 /**
8023 * @brief Selects accelerometer OIS channel full-scale.[get]
8024 *
8025 * @param ctx read / write interface definitions
8026 * @param val lsm6dsv16x_ois_xl_full_scale_t
8027 * @retval interface status (MANDATORY: return 0 -> no Error)
8028 *
8029 */
lsm6dsv16x_ois_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv16x_ois_xl_full_scale_t * val)8030 int32_t lsm6dsv16x_ois_xl_full_scale_get(const stmdev_ctx_t *ctx,
8031 lsm6dsv16x_ois_xl_full_scale_t *val)
8032 {
8033 lsm6dsv16x_ui_ctrl3_ois_t ui_ctrl3_ois;
8034 int32_t ret;
8035
8036 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL3_OIS, (uint8_t *)&ui_ctrl3_ois, 1);
8037 if (ret != 0)
8038 {
8039 return ret;
8040 }
8041
8042 switch (ui_ctrl3_ois.fs_xl_ois)
8043 {
8044 case LSM6DSV16X_OIS_2g:
8045 *val = LSM6DSV16X_OIS_2g;
8046 break;
8047
8048 case LSM6DSV16X_OIS_4g:
8049 *val = LSM6DSV16X_OIS_4g;
8050 break;
8051
8052 case LSM6DSV16X_OIS_8g:
8053 *val = LSM6DSV16X_OIS_8g;
8054 break;
8055
8056 case LSM6DSV16X_OIS_16g:
8057 *val = LSM6DSV16X_OIS_16g;
8058 break;
8059
8060 default:
8061 *val = LSM6DSV16X_OIS_2g;
8062 break;
8063 }
8064
8065 return ret;
8066 }
8067
8068 /**
8069 * @}
8070 *
8071 */
8072
8073 /**
8074 * @defgroup Orientation 6D (and 4D)
8075 * @brief This section groups all the functions concerning six position
8076 * detection (6D).
8077 * @{
8078 *
8079 */
8080
8081 /**
8082 * @brief Threshold for 4D/6D function.[set]
8083 *
8084 * @param ctx read / write interface definitions
8085 * @param val DEG_80, DEG_70, DEG_60, DEG_50,
8086 * @retval interface status (MANDATORY: return 0 -> no Error)
8087 *
8088 */
lsm6dsv16x_6d_threshold_set(const stmdev_ctx_t * ctx,lsm6dsv16x_6d_threshold_t val)8089 int32_t lsm6dsv16x_6d_threshold_set(const stmdev_ctx_t *ctx,
8090 lsm6dsv16x_6d_threshold_t val)
8091 {
8092 lsm6dsv16x_tap_ths_6d_t tap_ths_6d;
8093 int32_t ret;
8094
8095 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
8096 if (ret == 0)
8097 {
8098 tap_ths_6d.sixd_ths = (uint8_t)val & 0x03U;
8099 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
8100 }
8101
8102 return ret;
8103 }
8104
8105 /**
8106 * @brief Threshold for 4D/6D function.[get]
8107 *
8108 * @param ctx read / write interface definitions
8109 * @param val DEG_80, DEG_70, DEG_60, DEG_50,
8110 * @retval interface status (MANDATORY: return 0 -> no Error)
8111 *
8112 */
lsm6dsv16x_6d_threshold_get(const stmdev_ctx_t * ctx,lsm6dsv16x_6d_threshold_t * val)8113 int32_t lsm6dsv16x_6d_threshold_get(const stmdev_ctx_t *ctx,
8114 lsm6dsv16x_6d_threshold_t *val)
8115 {
8116 lsm6dsv16x_tap_ths_6d_t tap_ths_6d;
8117 int32_t ret;
8118
8119 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
8120 if (ret != 0)
8121 {
8122 return ret;
8123 }
8124
8125 switch (tap_ths_6d.sixd_ths)
8126 {
8127 case LSM6DSV16X_DEG_80:
8128 *val = LSM6DSV16X_DEG_80;
8129 break;
8130
8131 case LSM6DSV16X_DEG_70:
8132 *val = LSM6DSV16X_DEG_70;
8133 break;
8134
8135 case LSM6DSV16X_DEG_60:
8136 *val = LSM6DSV16X_DEG_60;
8137 break;
8138
8139 case LSM6DSV16X_DEG_50:
8140 *val = LSM6DSV16X_DEG_50;
8141 break;
8142
8143 default:
8144 *val = LSM6DSV16X_DEG_80;
8145 break;
8146 }
8147
8148 return ret;
8149 }
8150
8151 /**
8152 * @brief 4D orientation detection enable. Z-axis position detection is disabled.[set]
8153 *
8154 * @param ctx read / write interface definitions
8155 * @param val 4D orientation detection enable. Z-axis position detection is disabled.
8156 * @retval interface status (MANDATORY: return 0 -> no Error)
8157 *
8158 */
lsm6dsv16x_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)8159 int32_t lsm6dsv16x_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
8160 {
8161 lsm6dsv16x_tap_ths_6d_t tap_ths_6d;
8162 int32_t ret;
8163
8164 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
8165 if (ret == 0)
8166 {
8167 tap_ths_6d.d4d_en = val;
8168 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
8169 }
8170
8171 return ret;
8172 }
8173
8174 /**
8175 * @brief 4D orientation detection enable. Z-axis position detection is disabled.[get]
8176 *
8177 * @param ctx read / write interface definitions
8178 * @param val 4D orientation detection enable. Z-axis position detection is disabled.
8179 * @retval interface status (MANDATORY: return 0 -> no Error)
8180 *
8181 */
lsm6dsv16x_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)8182 int32_t lsm6dsv16x_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
8183 {
8184 lsm6dsv16x_tap_ths_6d_t tap_ths_6d;
8185 int32_t ret;
8186
8187 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
8188 *val = tap_ths_6d.d4d_en;
8189
8190 return ret;
8191 }
8192
8193 /**
8194 * @}
8195 *
8196 */
8197
8198 /**
8199 * @defgroup AH_QVAR
8200 * @brief This section group all the functions concerning the
8201 * usage of AH_QVAR
8202 * @{
8203 *
8204 */
8205
8206 /**
8207 * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[set]
8208 *
8209 * @param ctx read / write interface definitions
8210 * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm,
8211 * @retval interface status (MANDATORY: return 0 -> no Error)
8212 *
8213 */
lsm6dsv16x_ah_qvar_zin_set(const stmdev_ctx_t * ctx,lsm6dsv16x_ah_qvar_zin_t val)8214 int32_t lsm6dsv16x_ah_qvar_zin_set(const stmdev_ctx_t *ctx,
8215 lsm6dsv16x_ah_qvar_zin_t val)
8216 {
8217 lsm6dsv16x_ctrl7_t ctrl7;
8218 int32_t ret;
8219
8220 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
8221 if (ret == 0)
8222 {
8223 ctrl7.ah_qvar_c_zin = (uint8_t)val & 0x03U;
8224 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
8225 }
8226
8227 return ret;
8228 }
8229
8230 /**
8231 * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[get]
8232 *
8233 * @param ctx read / write interface definitions
8234 * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm,
8235 * @retval interface status (MANDATORY: return 0 -> no Error)
8236 *
8237 */
lsm6dsv16x_ah_qvar_zin_get(const stmdev_ctx_t * ctx,lsm6dsv16x_ah_qvar_zin_t * val)8238 int32_t lsm6dsv16x_ah_qvar_zin_get(const stmdev_ctx_t *ctx,
8239 lsm6dsv16x_ah_qvar_zin_t *val)
8240 {
8241 lsm6dsv16x_ctrl7_t ctrl7;
8242 int32_t ret;
8243
8244 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
8245 if (ret != 0)
8246 {
8247 return ret;
8248 }
8249
8250 switch (ctrl7.ah_qvar_c_zin)
8251 {
8252 case LSM6DSV16X_2400MOhm:
8253 *val = LSM6DSV16X_2400MOhm;
8254 break;
8255
8256 case LSM6DSV16X_730MOhm:
8257 *val = LSM6DSV16X_730MOhm;
8258 break;
8259
8260 case LSM6DSV16X_300MOhm:
8261 *val = LSM6DSV16X_300MOhm;
8262 break;
8263
8264 case LSM6DSV16X_255MOhm:
8265 *val = LSM6DSV16X_255MOhm;
8266 break;
8267
8268 default:
8269 *val = LSM6DSV16X_2400MOhm;
8270 break;
8271 }
8272
8273 return ret;
8274 }
8275
8276 /**
8277 * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.[set]
8278 *
8279 * @param ctx read / write interface definitions
8280 * @param val Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.
8281 * @retval interface status (MANDATORY: return 0 -> no Error)
8282 *
8283 */
lsm6dsv16x_ah_qvar_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16x_ah_qvar_mode_t val)8284 int32_t lsm6dsv16x_ah_qvar_mode_set(const stmdev_ctx_t *ctx,
8285 lsm6dsv16x_ah_qvar_mode_t val)
8286 {
8287 lsm6dsv16x_ctrl7_t ctrl7;
8288 int32_t ret;
8289
8290 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
8291 if (ret == 0)
8292 {
8293 ctrl7.ah_qvar_en = val.ah_qvar_en;
8294 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
8295 }
8296
8297 return ret;
8298 }
8299
8300 /**
8301 * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.[get]
8302 *
8303 * @param ctx read / write interface definitions
8304 * @param val Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/AH1/Qvar1 and SCx/AH2/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.
8305 * @retval interface status (MANDATORY: return 0 -> no Error)
8306 *
8307 */
lsm6dsv16x_ah_qvar_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16x_ah_qvar_mode_t * val)8308 int32_t lsm6dsv16x_ah_qvar_mode_get(const stmdev_ctx_t *ctx,
8309 lsm6dsv16x_ah_qvar_mode_t *val)
8310 {
8311 lsm6dsv16x_ctrl7_t ctrl7;
8312 int32_t ret;
8313
8314 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL7, (uint8_t *)&ctrl7, 1);
8315 val->ah_qvar_en = ctrl7.ah_qvar_en;
8316
8317 return ret;
8318 }
8319
8320 /**
8321 * @}
8322 *
8323 */
8324
8325 /**
8326 * @defgroup SenseWire (I3C)
8327 * @brief This section group all the functions concerning the
8328 * usage of SenseWire (I3C)
8329 * @{
8330 *
8331 */
8332
8333 /**
8334 * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[set]
8335 *
8336 * @param ctx read / write interface definitions
8337 * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST,
8338 * @retval interface status (MANDATORY: return 0 -> no Error)
8339 *
8340 */
lsm6dsv16x_i3c_reset_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16x_i3c_reset_mode_t val)8341 int32_t lsm6dsv16x_i3c_reset_mode_set(const stmdev_ctx_t *ctx,
8342 lsm6dsv16x_i3c_reset_mode_t val)
8343 {
8344 lsm6dsv16x_pin_ctrl_t pin_ctrl;
8345 int32_t ret;
8346
8347 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8348 if (ret == 0)
8349 {
8350 pin_ctrl.ibhr_por_en = (uint8_t)val & 0x01U;
8351 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8352 }
8353
8354 return ret;
8355 }
8356
8357 /**
8358 * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[get]
8359 *
8360 * @param ctx read / write interface definitions
8361 * @param val SW_RST_DYN_ADDRESS_RST, I3C_GLOBAL_RST,
8362 * @retval interface status (MANDATORY: return 0 -> no Error)
8363 *
8364 */
lsm6dsv16x_i3c_reset_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16x_i3c_reset_mode_t * val)8365 int32_t lsm6dsv16x_i3c_reset_mode_get(const stmdev_ctx_t *ctx,
8366 lsm6dsv16x_i3c_reset_mode_t *val)
8367 {
8368 lsm6dsv16x_pin_ctrl_t pin_ctrl;
8369 int32_t ret;
8370
8371 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8372 if (ret != 0)
8373 {
8374 return ret;
8375 }
8376
8377 switch (pin_ctrl.ibhr_por_en)
8378 {
8379 case LSM6DSV16X_SW_RST_DYN_ADDRESS_RST:
8380 *val = LSM6DSV16X_SW_RST_DYN_ADDRESS_RST;
8381 break;
8382
8383 case LSM6DSV16X_I3C_GLOBAL_RST:
8384 *val = LSM6DSV16X_I3C_GLOBAL_RST;
8385 break;
8386
8387 default:
8388 *val = LSM6DSV16X_SW_RST_DYN_ADDRESS_RST;
8389 break;
8390 }
8391
8392 return ret;
8393 }
8394
8395 /**
8396 * @brief Enable/Disable INT pin when I3C is used.[set]
8397 *
8398 * @param ctx read / write interface definitions
8399 * @param val 0: disabled, 1: enabled
8400 * @retval interface status (MANDATORY: return 0 -> no Error)
8401 *
8402 */
lsm6dsv16x_i3c_int_en_set(const stmdev_ctx_t * ctx,uint8_t val)8403 int32_t lsm6dsv16x_i3c_int_en_set(const stmdev_ctx_t *ctx, uint8_t val)
8404 {
8405 lsm6dsv16x_ctrl5_t ctrl5;
8406 int32_t ret;
8407
8408 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL5, (uint8_t *)&ctrl5, 1);
8409 if (ret == 0)
8410 {
8411 ctrl5.int_en_i3c = (uint8_t)val & 0x01U;
8412 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL5, (uint8_t *)&ctrl5, 1);
8413 }
8414
8415 return ret;
8416 }
8417
8418 /**
8419 * @brief Enable/Disable INT pin when I3C is used.[get]
8420 *
8421 * @param ctx read / write interface definitions
8422 * @param val 0: disabled, 1: enabled
8423 * @retval interface status (MANDATORY: return 0 -> no Error)
8424 *
8425 */
lsm6dsv16x_i3c_int_en_get(const stmdev_ctx_t * ctx,uint8_t * val)8426 int32_t lsm6dsv16x_i3c_int_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
8427 {
8428 lsm6dsv16x_ctrl5_t ctrl5;
8429 int32_t ret;
8430
8431 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL5, (uint8_t *)&ctrl5, 1);
8432 *val = ctrl5.int_en_i3c;
8433
8434 return ret;
8435 }
8436
8437 /**
8438 * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[set]
8439 *
8440 * @param ctx read / write interface definitions
8441 * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms,
8442 * @retval interface status (MANDATORY: return 0 -> no Error)
8443 *
8444 */
lsm6dsv16x_i3c_ibi_time_set(const stmdev_ctx_t * ctx,lsm6dsv16x_i3c_ibi_time_t val)8445 int32_t lsm6dsv16x_i3c_ibi_time_set(const stmdev_ctx_t *ctx,
8446 lsm6dsv16x_i3c_ibi_time_t val)
8447 {
8448 lsm6dsv16x_ctrl5_t ctrl5;
8449 int32_t ret;
8450
8451 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL5, (uint8_t *)&ctrl5, 1);
8452 if (ret == 0)
8453 {
8454 ctrl5.bus_act_sel = (uint8_t)val & 0x03U;
8455 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_CTRL5, (uint8_t *)&ctrl5, 1);
8456 }
8457
8458 return ret;
8459 }
8460
8461 /**
8462 * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[get]
8463 *
8464 * @param ctx read / write interface definitions
8465 * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms,
8466 * @retval interface status (MANDATORY: return 0 -> no Error)
8467 *
8468 */
lsm6dsv16x_i3c_ibi_time_get(const stmdev_ctx_t * ctx,lsm6dsv16x_i3c_ibi_time_t * val)8469 int32_t lsm6dsv16x_i3c_ibi_time_get(const stmdev_ctx_t *ctx,
8470 lsm6dsv16x_i3c_ibi_time_t *val)
8471 {
8472 lsm6dsv16x_ctrl5_t ctrl5;
8473 int32_t ret;
8474
8475 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_CTRL5, (uint8_t *)&ctrl5, 1);
8476 if (ret != 0)
8477 {
8478 return ret;
8479 }
8480
8481 switch (ctrl5.bus_act_sel)
8482 {
8483 case LSM6DSV16X_IBI_2us:
8484 *val = LSM6DSV16X_IBI_2us;
8485 break;
8486
8487 case LSM6DSV16X_IBI_50us:
8488 *val = LSM6DSV16X_IBI_50us;
8489 break;
8490
8491 case LSM6DSV16X_IBI_1ms:
8492 *val = LSM6DSV16X_IBI_1ms;
8493 break;
8494
8495 case LSM6DSV16X_IBI_25ms:
8496 *val = LSM6DSV16X_IBI_25ms;
8497 break;
8498
8499 default:
8500 *val = LSM6DSV16X_IBI_2us;
8501 break;
8502 }
8503
8504 return ret;
8505 }
8506
8507 /**
8508 * @}
8509 *
8510 */
8511
8512 /**
8513 * @defgroup Sensor hub
8514 * @brief This section groups all the functions that manage the
8515 * sensor hub.
8516 * @{
8517 *
8518 */
8519
8520 /**
8521 * @brief Sensor Hub master I2C pull-up enable.[set]
8522 *
8523 * @param ctx read / write interface definitions
8524 * @param val Sensor Hub master I2C pull-up enable.
8525 * @retval interface status (MANDATORY: return 0 -> no Error)
8526 *
8527 */
lsm6dsv16x_sh_master_interface_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)8528 int32_t lsm6dsv16x_sh_master_interface_pull_up_set(const stmdev_ctx_t *ctx,
8529 uint8_t val)
8530 {
8531 lsm6dsv16x_if_cfg_t if_cfg;
8532 int32_t ret;
8533
8534 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
8535 if (ret == 0)
8536 {
8537 if_cfg.shub_pu_en = val;
8538 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
8539 }
8540
8541 return ret;
8542 }
8543
8544 /**
8545 * @brief Sensor Hub master I2C pull-up enable.[get]
8546 *
8547 * @param ctx read / write interface definitions
8548 * @param val Sensor Hub master I2C pull-up enable.
8549 * @retval interface status (MANDATORY: return 0 -> no Error)
8550 *
8551 */
lsm6dsv16x_sh_master_interface_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)8552 int32_t lsm6dsv16x_sh_master_interface_pull_up_get(const stmdev_ctx_t *ctx,
8553 uint8_t *val)
8554 {
8555 lsm6dsv16x_if_cfg_t if_cfg;
8556 int32_t ret;
8557
8558 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
8559 *val = if_cfg.shub_pu_en;
8560
8561 return ret;
8562 }
8563
8564 /**
8565 * @brief Sensor hub output registers.[get]
8566 *
8567 * @param ctx read / write interface definitions
8568 * @param val Sensor hub output registers.
8569 * @retval interface status (MANDATORY: return 0 -> no Error)
8570 *
8571 */
lsm6dsv16x_sh_read_data_raw_get(const stmdev_ctx_t * ctx,uint8_t * val,uint8_t len)8572 int32_t lsm6dsv16x_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val,
8573 uint8_t len)
8574 {
8575 int32_t ret;
8576
8577 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8578 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SENSOR_HUB_1, val, len);
8579 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8580
8581 return ret;
8582 }
8583
8584 /**
8585 * @brief Number of external sensors to be read by the sensor hub.[set]
8586 *
8587 * @param ctx read / write interface definitions
8588 * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3,
8589 * @retval interface status (MANDATORY: return 0 -> no Error)
8590 *
8591 */
lsm6dsv16x_sh_slave_connected_set(const stmdev_ctx_t * ctx,lsm6dsv16x_sh_slave_connected_t val)8592 int32_t lsm6dsv16x_sh_slave_connected_set(const stmdev_ctx_t *ctx,
8593 lsm6dsv16x_sh_slave_connected_t val)
8594 {
8595 lsm6dsv16x_master_config_t master_config;
8596 int32_t ret;
8597
8598 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8599 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8600 if (ret != 0)
8601 {
8602 goto exit;
8603 }
8604
8605 master_config.aux_sens_on = (uint8_t)val & 0x3U;
8606 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8607
8608 exit:
8609 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8610
8611 return ret;
8612 }
8613
8614 /**
8615 * @brief Number of external sensors to be read by the sensor hub.[get]
8616 *
8617 * @param ctx read / write interface definitions
8618 * @param val SLV_0, SLV_0_1, SLV_0_1_2, SLV_0_1_2_3,
8619 * @retval interface status (MANDATORY: return 0 -> no Error)
8620 *
8621 */
lsm6dsv16x_sh_slave_connected_get(const stmdev_ctx_t * ctx,lsm6dsv16x_sh_slave_connected_t * val)8622 int32_t lsm6dsv16x_sh_slave_connected_get(const stmdev_ctx_t *ctx,
8623 lsm6dsv16x_sh_slave_connected_t *val)
8624 {
8625 lsm6dsv16x_master_config_t master_config;
8626 int32_t ret;
8627
8628 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8629 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8630 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8631 if (ret != 0)
8632 {
8633 return ret;
8634 }
8635
8636 switch (master_config.aux_sens_on)
8637 {
8638 case LSM6DSV16X_SLV_0:
8639 *val = LSM6DSV16X_SLV_0;
8640 break;
8641
8642 case LSM6DSV16X_SLV_0_1:
8643 *val = LSM6DSV16X_SLV_0_1;
8644 break;
8645
8646 case LSM6DSV16X_SLV_0_1_2:
8647 *val = LSM6DSV16X_SLV_0_1_2;
8648 break;
8649
8650 case LSM6DSV16X_SLV_0_1_2_3:
8651 *val = LSM6DSV16X_SLV_0_1_2_3;
8652 break;
8653
8654 default:
8655 *val = LSM6DSV16X_SLV_0;
8656 break;
8657 }
8658
8659 return ret;
8660 }
8661
8662 /**
8663 * @brief Sensor hub I2C master enable.[set]
8664 *
8665 * @param ctx read / write interface definitions
8666 * @param val Sensor hub I2C master enable.
8667 * @retval interface status (MANDATORY: return 0 -> no Error)
8668 *
8669 */
lsm6dsv16x_sh_master_set(const stmdev_ctx_t * ctx,uint8_t val)8670 int32_t lsm6dsv16x_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val)
8671 {
8672 lsm6dsv16x_master_config_t master_config;
8673 int32_t ret;
8674
8675 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8676 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8677 if (ret != 0)
8678 {
8679 goto exit;
8680 }
8681
8682 master_config.master_on = val;
8683 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8684
8685 exit:
8686 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8687
8688 return ret;
8689 }
8690
8691 /**
8692 * @brief Sensor hub I2C master enable.[get]
8693 *
8694 * @param ctx read / write interface definitions
8695 * @param val Sensor hub I2C master enable.
8696 * @retval interface status (MANDATORY: return 0 -> no Error)
8697 *
8698 */
lsm6dsv16x_sh_master_get(const stmdev_ctx_t * ctx,uint8_t * val)8699 int32_t lsm6dsv16x_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val)
8700 {
8701 lsm6dsv16x_master_config_t master_config;
8702 int32_t ret;
8703
8704 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8705 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8706
8707 *val = master_config.master_on;
8708
8709 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8710
8711 return ret;
8712 }
8713
8714 /**
8715 * @brief I2C interface pass-through.[set]
8716 *
8717 * @param ctx read / write interface definitions
8718 * @param val I2C interface pass-through.
8719 * @retval interface status (MANDATORY: return 0 -> no Error)
8720 *
8721 */
lsm6dsv16x_sh_pass_through_set(const stmdev_ctx_t * ctx,uint8_t val)8722 int32_t lsm6dsv16x_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val)
8723 {
8724 lsm6dsv16x_master_config_t master_config;
8725 int32_t ret;
8726
8727 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8728 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8729 if (ret != 0)
8730 {
8731 goto exit;
8732 }
8733
8734 master_config.pass_through_mode = val;
8735 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8736
8737 exit:
8738 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8739
8740 return ret;
8741 }
8742
8743 /**
8744 * @brief I2C interface pass-through.[get]
8745 *
8746 * @param ctx read / write interface definitions
8747 * @param val I2C interface pass-through.
8748 * @retval interface status (MANDATORY: return 0 -> no Error)
8749 *
8750 */
lsm6dsv16x_sh_pass_through_get(const stmdev_ctx_t * ctx,uint8_t * val)8751 int32_t lsm6dsv16x_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val)
8752 {
8753 lsm6dsv16x_master_config_t master_config;
8754 int32_t ret;
8755
8756 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8757 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8758
8759 *val = master_config.pass_through_mode;
8760
8761 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8762
8763 return ret;
8764 }
8765
8766 /**
8767 * @brief Sensor hub trigger signal selection.[set]
8768 *
8769 * @param ctx read / write interface definitions
8770 * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2,
8771 * @retval interface status (MANDATORY: return 0 -> no Error)
8772 *
8773 */
lsm6dsv16x_sh_syncro_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16x_sh_syncro_mode_t val)8774 int32_t lsm6dsv16x_sh_syncro_mode_set(const stmdev_ctx_t *ctx,
8775 lsm6dsv16x_sh_syncro_mode_t val)
8776 {
8777 lsm6dsv16x_master_config_t master_config;
8778 int32_t ret;
8779
8780 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8781 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8782 if (ret != 0)
8783 {
8784 goto exit;
8785 }
8786
8787 master_config.start_config = (uint8_t)val & 0x01U;
8788 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8789
8790 exit:
8791 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8792
8793 return ret;
8794 }
8795
8796 /**
8797 * @brief Sensor hub trigger signal selection.[get]
8798 *
8799 * @param ctx read / write interface definitions
8800 * @param val SH_TRG_XL_GY_DRDY, SH_TRIG_INT2,
8801 * @retval interface status (MANDATORY: return 0 -> no Error)
8802 *
8803 */
lsm6dsv16x_sh_syncro_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16x_sh_syncro_mode_t * val)8804 int32_t lsm6dsv16x_sh_syncro_mode_get(const stmdev_ctx_t *ctx,
8805 lsm6dsv16x_sh_syncro_mode_t *val)
8806 {
8807 lsm6dsv16x_master_config_t master_config;
8808 int32_t ret;
8809
8810 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8811 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8812 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8813 if (ret != 0)
8814 {
8815 return ret;
8816 }
8817
8818 switch (master_config.start_config)
8819 {
8820 case LSM6DSV16X_SH_TRG_XL_GY_DRDY:
8821 *val = LSM6DSV16X_SH_TRG_XL_GY_DRDY;
8822 break;
8823
8824 case LSM6DSV16X_SH_TRIG_INT2:
8825 *val = LSM6DSV16X_SH_TRIG_INT2;
8826 break;
8827
8828 default:
8829 *val = LSM6DSV16X_SH_TRG_XL_GY_DRDY;
8830 break;
8831 }
8832
8833 return ret;
8834 }
8835
8836 /**
8837 * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[set]
8838 *
8839 * @param ctx read / write interface definitions
8840 * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE,
8841 * @retval interface status (MANDATORY: return 0 -> no Error)
8842 *
8843 */
lsm6dsv16x_sh_write_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16x_sh_write_mode_t val)8844 int32_t lsm6dsv16x_sh_write_mode_set(const stmdev_ctx_t *ctx,
8845 lsm6dsv16x_sh_write_mode_t val)
8846 {
8847 lsm6dsv16x_master_config_t master_config;
8848 int32_t ret;
8849
8850 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8851 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8852 if (ret != 0)
8853 {
8854 goto exit;
8855 }
8856
8857 master_config.write_once = (uint8_t)val & 0x01U;
8858 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8859
8860 exit:
8861 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8862
8863 return ret;
8864 }
8865
8866 /**
8867 * @brief Slave 0 write operation is performed only at the first sensor hub cycle.[get]
8868 *
8869 * @param ctx read / write interface definitions
8870 * @param val EACH_SH_CYCLE, ONLY_FIRST_CYCLE,
8871 * @retval interface status (MANDATORY: return 0 -> no Error)
8872 *
8873 */
lsm6dsv16x_sh_write_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16x_sh_write_mode_t * val)8874 int32_t lsm6dsv16x_sh_write_mode_get(const stmdev_ctx_t *ctx,
8875 lsm6dsv16x_sh_write_mode_t *val)
8876 {
8877 lsm6dsv16x_master_config_t master_config;
8878 int32_t ret;
8879
8880 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8881 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8882 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8883 if (ret != 0)
8884 {
8885 return ret;
8886 }
8887
8888 switch (master_config.write_once)
8889 {
8890 case LSM6DSV16X_EACH_SH_CYCLE:
8891 *val = LSM6DSV16X_EACH_SH_CYCLE;
8892 break;
8893
8894 case LSM6DSV16X_ONLY_FIRST_CYCLE:
8895 *val = LSM6DSV16X_ONLY_FIRST_CYCLE;
8896 break;
8897
8898 default:
8899 *val = LSM6DSV16X_EACH_SH_CYCLE;
8900 break;
8901 }
8902
8903 return ret;
8904 }
8905
8906 /**
8907 * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[set]
8908 *
8909 * @param ctx read / write interface definitions
8910 * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.
8911 * @retval interface status (MANDATORY: return 0 -> no Error)
8912 *
8913 */
lsm6dsv16x_sh_reset_set(const stmdev_ctx_t * ctx,uint8_t val)8914 int32_t lsm6dsv16x_sh_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
8915 {
8916 lsm6dsv16x_master_config_t master_config;
8917 int32_t ret;
8918
8919 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8920 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8921 if (ret != 0)
8922 {
8923 goto exit;
8924 }
8925
8926 master_config.rst_master_regs = val;
8927 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8928
8929 exit:
8930 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8931
8932 return ret;
8933 }
8934
8935 /**
8936 * @brief Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.[get]
8937 *
8938 * @param ctx read / write interface definitions
8939 * @param val Reset Master logic and output registers. Must be set to ‘1’ and then set it to ‘0’.
8940 * @retval interface status (MANDATORY: return 0 -> no Error)
8941 *
8942 */
lsm6dsv16x_sh_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)8943 int32_t lsm6dsv16x_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
8944 {
8945 lsm6dsv16x_master_config_t master_config;
8946 int32_t ret;
8947
8948 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8949 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_MASTER_CONFIG, (uint8_t *)&master_config, 1);
8950
8951 *val = master_config.rst_master_regs;
8952
8953 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
8954
8955 return ret;
8956 }
8957
8958 /**
8959 * @brief Configure slave 0 for perform a write.[set]
8960 *
8961 * @param ctx read / write interface definitions
8962 * @param val a structure that contain
8963 * - uint8_t slv1_add; 8 bit i2c device address
8964 * - uint8_t slv1_subadd; 8 bit register device address
8965 * - uint8_t slv1_data; 8 bit data to write
8966 * @retval interface status (MANDATORY: return 0 -> no Error)
8967 *
8968 */
lsm6dsv16x_sh_cfg_write(const stmdev_ctx_t * ctx,lsm6dsv16x_sh_cfg_write_t * val)8969 int32_t lsm6dsv16x_sh_cfg_write(const stmdev_ctx_t *ctx,
8970 lsm6dsv16x_sh_cfg_write_t *val)
8971 {
8972 lsm6dsv16x_slv0_add_t reg;
8973 int32_t ret;
8974
8975 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
8976 if (ret != 0)
8977 {
8978 return ret;
8979 }
8980
8981 reg.slave0_add = val->slv0_add;
8982 reg.rw_0 = 0;
8983 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_ADD, (uint8_t *)®, 1);
8984 if (ret != 0)
8985 {
8986 goto exit;
8987 }
8988
8989 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_SUBADD,
8990 &(val->slv0_subadd), 1);
8991 if (ret != 0)
8992 {
8993 goto exit;
8994 }
8995
8996 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_DATAWRITE_SLV0,
8997 &(val->slv0_data), 1);
8998
8999 exit:
9000 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
9001
9002 return ret;
9003 }
9004
9005 /**
9006 * @brief Rate at which the master communicates.[set]
9007 *
9008 * @param ctx read / write interface definitions
9009 * @param val SH_15Hz, SH_30Hz, SH_60Hz, SH_120Hz, SH_240Hz, SH_480Hz,
9010 * @retval interface status (MANDATORY: return 0 -> no Error)
9011 *
9012 */
lsm6dsv16x_sh_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv16x_sh_data_rate_t val)9013 int32_t lsm6dsv16x_sh_data_rate_set(const stmdev_ctx_t *ctx,
9014 lsm6dsv16x_sh_data_rate_t val)
9015 {
9016 lsm6dsv16x_slv0_config_t slv0_config;
9017 int32_t ret;
9018
9019 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
9020 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1);
9021 if (ret != 0)
9022 {
9023 goto exit;
9024 }
9025
9026 slv0_config.shub_odr = (uint8_t)val & 0x07U;
9027 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1);
9028
9029 exit:
9030 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
9031
9032 return ret;
9033 }
9034
9035 /**
9036 * @brief Rate at which the master communicates.[get]
9037 *
9038 * @param ctx read / write interface definitions
9039 * @param val SH_15Hz, SH_30Hz, SH_60Hz, SH_120Hz, SH_240Hz, SH_480Hz,
9040 * @retval interface status (MANDATORY: return 0 -> no Error)
9041 *
9042 */
lsm6dsv16x_sh_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv16x_sh_data_rate_t * val)9043 int32_t lsm6dsv16x_sh_data_rate_get(const stmdev_ctx_t *ctx,
9044 lsm6dsv16x_sh_data_rate_t *val)
9045 {
9046 lsm6dsv16x_slv0_config_t slv0_config;
9047 int32_t ret;
9048
9049 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
9050 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG, (uint8_t *)&slv0_config, 1);
9051 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
9052 if (ret != 0)
9053 {
9054 return ret;
9055 }
9056
9057 switch (slv0_config.shub_odr)
9058 {
9059 case LSM6DSV16X_SH_15Hz:
9060 *val = LSM6DSV16X_SH_15Hz;
9061 break;
9062
9063 case LSM6DSV16X_SH_30Hz:
9064 *val = LSM6DSV16X_SH_30Hz;
9065 break;
9066
9067 case LSM6DSV16X_SH_60Hz:
9068 *val = LSM6DSV16X_SH_60Hz;
9069 break;
9070
9071 case LSM6DSV16X_SH_120Hz:
9072 *val = LSM6DSV16X_SH_120Hz;
9073 break;
9074
9075 case LSM6DSV16X_SH_240Hz:
9076 *val = LSM6DSV16X_SH_240Hz;
9077 break;
9078
9079 case LSM6DSV16X_SH_480Hz:
9080 *val = LSM6DSV16X_SH_480Hz;
9081 break;
9082
9083 default:
9084 *val = LSM6DSV16X_SH_15Hz;
9085 break;
9086 }
9087
9088 return ret;
9089 }
9090
9091 /**
9092 * @brief Configure slave idx for perform a read.[set]
9093 *
9094 * @param ctx read / write interface definitions
9095 * @param val Structure that contain
9096 * - uint8_t slv_add; 8 bit i2c device address
9097 * - uint8_t slv_subadd; 8 bit register device address
9098 * - uint8_t slv_len; num of bit to read
9099 * @retval interface status (MANDATORY: return 0 -> no Error)
9100 *
9101 */
lsm6dsv16x_sh_slv_cfg_read(const stmdev_ctx_t * ctx,uint8_t idx,lsm6dsv16x_sh_cfg_read_t * val)9102 int32_t lsm6dsv16x_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx,
9103 lsm6dsv16x_sh_cfg_read_t *val)
9104 {
9105 lsm6dsv16x_slv0_add_t slv_add;
9106 lsm6dsv16x_slv0_config_t slv_config;
9107 int32_t ret;
9108
9109 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_SENSOR_HUB_MEM_BANK);
9110 if (ret != 0)
9111 {
9112 return ret;
9113 }
9114
9115 slv_add.slave0_add = val->slv_add;
9116 slv_add.rw_0 = 1;
9117 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_ADD + idx * 3U,
9118 (uint8_t *)&slv_add, 1);
9119 if (ret != 0)
9120 {
9121 goto exit;
9122 }
9123
9124 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_SUBADD + idx * 3U,
9125 &(val->slv_subadd), 1);
9126 if (ret != 0)
9127 {
9128 goto exit;
9129 }
9130
9131 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx * 3U,
9132 (uint8_t *)&slv_config, 1);
9133 if (ret != 0)
9134 {
9135 goto exit;
9136 }
9137
9138 slv_config.slave0_numop = val->slv_len;
9139 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SLV0_CONFIG + idx * 3U,
9140 (uint8_t *)&slv_config, 1);
9141
9142 exit:
9143 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
9144
9145 return ret;
9146 }
9147
9148 /**
9149 * @brief Sensor hub source register.[get]
9150 *
9151 * @param ctx read / write interface definitions
9152 * @param val union of registers from STATUS_MASTER to
9153 * @retval interface status (MANDATORY: return 0 -> no Error)
9154 *
9155 */
lsm6dsv16x_sh_status_get(const stmdev_ctx_t * ctx,lsm6dsv16x_status_master_t * val)9156 int32_t lsm6dsv16x_sh_status_get(const stmdev_ctx_t *ctx,
9157 lsm6dsv16x_status_master_t *val)
9158 {
9159 int32_t ret;
9160
9161 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_STATUS_MASTER_MAINPAGE, (uint8_t *) val, 1);
9162
9163 return ret;
9164 }
9165
9166 /**
9167 * @}
9168 *
9169 */
9170
9171 /**
9172 * @defgroup Serial interfaces
9173 * @brief This section groups all the functions concerning
9174 * serial interfaces management (not auxiliary)
9175 * @{
9176 *
9177 */
9178
9179 /**
9180 * @brief Enables pull-up on SDO pin of UI (User Interface).[set]
9181 *
9182 * @param ctx read / write interface definitions
9183 * @param val Enables pull-up on SDO pin of UI (User Interface).
9184 * @retval interface status (MANDATORY: return 0 -> no Error)
9185 *
9186 */
lsm6dsv16x_ui_sdo_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)9187 int32_t lsm6dsv16x_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
9188 {
9189 lsm6dsv16x_pin_ctrl_t pin_ctrl;
9190 int32_t ret;
9191
9192 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
9193 if (ret == 0)
9194 {
9195 pin_ctrl.sdo_pu_en = val;
9196 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
9197 }
9198
9199 return ret;
9200 }
9201
9202 /**
9203 * @brief Enables pull-up on SDO pin of UI (User Interface).[get]
9204 *
9205 * @param ctx read / write interface definitions
9206 * @param val Enables pull-up on SDO pin of UI (User Interface).
9207 * @retval interface status (MANDATORY: return 0 -> no Error)
9208 *
9209 */
lsm6dsv16x_ui_sdo_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)9210 int32_t lsm6dsv16x_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
9211 {
9212 lsm6dsv16x_pin_ctrl_t pin_ctrl;
9213 int32_t ret;
9214
9215 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
9216 *val = pin_ctrl.sdo_pu_en;
9217
9218 return ret;
9219 }
9220
9221 /**
9222 * @brief Disables I2C and I3C on UI (User Interface).[set]
9223 *
9224 * @param ctx read / write interface definitions
9225 * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE,
9226 * @retval interface status (MANDATORY: return 0 -> no Error)
9227 *
9228 */
lsm6dsv16x_ui_i2c_i3c_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16x_ui_i2c_i3c_mode_t val)9229 int32_t lsm6dsv16x_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx,
9230 lsm6dsv16x_ui_i2c_i3c_mode_t val)
9231 {
9232 lsm6dsv16x_if_cfg_t if_cfg;
9233 int32_t ret;
9234
9235 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
9236 if (ret == 0)
9237 {
9238 if_cfg.i2c_i3c_disable = (uint8_t)val & 0x1U;
9239 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
9240 }
9241
9242 return ret;
9243 }
9244
9245 /**
9246 * @brief Disables I2C and I3C on UI (User Interface).[get]
9247 *
9248 * @param ctx read / write interface definitions
9249 * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE,
9250 * @retval interface status (MANDATORY: return 0 -> no Error)
9251 *
9252 */
lsm6dsv16x_ui_i2c_i3c_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16x_ui_i2c_i3c_mode_t * val)9253 int32_t lsm6dsv16x_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx,
9254 lsm6dsv16x_ui_i2c_i3c_mode_t *val)
9255 {
9256 lsm6dsv16x_if_cfg_t if_cfg;
9257 int32_t ret;
9258
9259 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
9260 if (ret != 0)
9261 {
9262 return ret;
9263 }
9264
9265 switch (if_cfg.i2c_i3c_disable)
9266 {
9267 case LSM6DSV16X_I2C_I3C_ENABLE:
9268 *val = LSM6DSV16X_I2C_I3C_ENABLE;
9269 break;
9270
9271 case LSM6DSV16X_I2C_I3C_DISABLE:
9272 *val = LSM6DSV16X_I2C_I3C_DISABLE;
9273 break;
9274
9275 default:
9276 *val = LSM6DSV16X_I2C_I3C_ENABLE;
9277 break;
9278 }
9279
9280 return ret;
9281 }
9282
9283 /**
9284 * @brief SPI Serial Interface Mode selection.[set]
9285 *
9286 * @param ctx read / write interface definitions
9287 * @param val SPI_4_WIRE, SPI_3_WIRE,
9288 * @retval interface status (MANDATORY: return 0 -> no Error)
9289 *
9290 */
lsm6dsv16x_spi_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16x_spi_mode_t val)9291 int32_t lsm6dsv16x_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t val)
9292 {
9293 lsm6dsv16x_if_cfg_t if_cfg;
9294 int32_t ret;
9295
9296 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
9297 if (ret == 0)
9298 {
9299 if_cfg.sim = (uint8_t)val & 0x01U;
9300 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
9301 }
9302
9303 return ret;
9304 }
9305
9306 /**
9307 * @brief SPI Serial Interface Mode selection.[get]
9308 *
9309 * @param ctx read / write interface definitions
9310 * @param val SPI_4_WIRE, SPI_3_WIRE,
9311 * @retval interface status (MANDATORY: return 0 -> no Error)
9312 *
9313 */
lsm6dsv16x_spi_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16x_spi_mode_t * val)9314 int32_t lsm6dsv16x_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_spi_mode_t *val)
9315 {
9316 lsm6dsv16x_if_cfg_t if_cfg;
9317 int32_t ret;
9318
9319 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
9320 if (ret != 0)
9321 {
9322 return ret;
9323 }
9324
9325 switch (if_cfg.sim)
9326 {
9327 case LSM6DSV16X_SPI_4_WIRE:
9328 *val = LSM6DSV16X_SPI_4_WIRE;
9329 break;
9330
9331 case LSM6DSV16X_SPI_3_WIRE:
9332 *val = LSM6DSV16X_SPI_3_WIRE;
9333 break;
9334
9335 default:
9336 *val = LSM6DSV16X_SPI_4_WIRE;
9337 break;
9338 }
9339
9340 return ret;
9341 }
9342
9343 /**
9344 * @brief Enables pull-up on SDA pin.[set]
9345 *
9346 * @param ctx read / write interface definitions
9347 * @param val Enables pull-up on SDA pin.
9348 * @retval interface status (MANDATORY: return 0 -> no Error)
9349 *
9350 */
lsm6dsv16x_ui_sda_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)9351 int32_t lsm6dsv16x_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
9352 {
9353 lsm6dsv16x_if_cfg_t if_cfg;
9354 int32_t ret;
9355
9356 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
9357 if (ret == 0)
9358 {
9359 if_cfg.sda_pu_en = val;
9360 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
9361 }
9362
9363 return ret;
9364 }
9365
9366 /**
9367 * @brief Enables pull-up on SDA pin.[get]
9368 *
9369 * @param ctx read / write interface definitions
9370 * @param val Enables pull-up on SDA pin.
9371 * @retval interface status (MANDATORY: return 0 -> no Error)
9372 *
9373 */
lsm6dsv16x_ui_sda_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)9374 int32_t lsm6dsv16x_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
9375 {
9376 lsm6dsv16x_if_cfg_t if_cfg;
9377 int32_t ret;
9378
9379 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_IF_CFG, (uint8_t *)&if_cfg, 1);
9380 *val = if_cfg.sda_pu_en;
9381
9382 return ret;
9383 }
9384
9385 /**
9386 * @brief SPI2 (OIS Inteface) Serial Interface Mode selection. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[set]
9387 *
9388 * @param ctx read / write interface definitions
9389 * @param val SPI2_4_WIRE, SPI2_3_WIRE,
9390 * @retval interface status (MANDATORY: return 0 -> no Error)
9391 *
9392 */
lsm6dsv16x_spi2_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16x_spi2_mode_t val)9393 int32_t lsm6dsv16x_spi2_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_spi2_mode_t val)
9394 {
9395 lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois;
9396 int32_t ret;
9397
9398 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
9399 if (ret == 0)
9400 {
9401 ui_ctrl1_ois.sim_ois = (uint8_t)val & 0x01U;
9402 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
9403 }
9404
9405 return ret;
9406 }
9407
9408 /**
9409 * @brief SPI2 (OIS Inteface) Serial Interface Mode selection. This function works also on OIS (UI_CTRL1_OIS = SPI2_CTRL1_OIS).[get]
9410 *
9411 * @param ctx read / write interface definitions
9412 * @param val SPI2_4_WIRE, SPI2_3_WIRE,
9413 * @retval interface status (MANDATORY: return 0 -> no Error)
9414 *
9415 */
lsm6dsv16x_spi2_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16x_spi2_mode_t * val)9416 int32_t lsm6dsv16x_spi2_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_spi2_mode_t *val)
9417 {
9418 lsm6dsv16x_ui_ctrl1_ois_t ui_ctrl1_ois;
9419 int32_t ret;
9420
9421 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_UI_CTRL1_OIS, (uint8_t *)&ui_ctrl1_ois, 1);
9422 if (ret != 0)
9423 {
9424 return ret;
9425 }
9426
9427 switch (ui_ctrl1_ois.sim_ois)
9428 {
9429 case LSM6DSV16X_SPI2_4_WIRE:
9430 *val = LSM6DSV16X_SPI2_4_WIRE;
9431 break;
9432
9433 case LSM6DSV16X_SPI2_3_WIRE:
9434 *val = LSM6DSV16X_SPI2_3_WIRE;
9435 break;
9436
9437 default:
9438 *val = LSM6DSV16X_SPI2_4_WIRE;
9439 break;
9440 }
9441
9442 return ret;
9443 }
9444
9445 /**
9446 * @}
9447 *
9448 */
9449
9450 /**
9451 * @defgroup Significant motion detection
9452 * @brief This section groups all the functions that manage the
9453 * significant motion detection.
9454 * @{
9455 *
9456 */
9457
9458
9459 /**
9460 * @brief Enables significant motion detection function.[set]
9461 *
9462 * @param ctx read / write interface definitions
9463 * @param val Enables significant motion detection function.
9464 * @retval interface status (MANDATORY: return 0 -> no Error)
9465 *
9466 */
lsm6dsv16x_sigmot_mode_set(const stmdev_ctx_t * ctx,uint8_t val)9467 int32_t lsm6dsv16x_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
9468 {
9469 lsm6dsv16x_emb_func_en_a_t emb_func_en_a;
9470 int32_t ret;
9471
9472 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
9473 if (ret != 0)
9474 {
9475 return ret;
9476 }
9477
9478 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9479 emb_func_en_a.sign_motion_en = val;
9480 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9481
9482 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
9483
9484 return ret;
9485 }
9486
9487 /**
9488 * @brief Enables significant motion detection function.[get]
9489 *
9490 * @param ctx read / write interface definitions
9491 * @param val Enables significant motion detection function.
9492 * @retval interface status (MANDATORY: return 0 -> no Error)
9493 *
9494 */
lsm6dsv16x_sigmot_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)9495 int32_t lsm6dsv16x_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
9496 {
9497 lsm6dsv16x_emb_func_en_a_t emb_func_en_a;
9498 int32_t ret;
9499
9500 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
9501 if (ret != 0)
9502 {
9503 return ret;
9504 }
9505
9506 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9507 *val = emb_func_en_a.sign_motion_en;
9508
9509 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
9510
9511 return ret;
9512 }
9513
9514 /**
9515 * @}
9516 *
9517 */
9518
9519 /**
9520 * @defgroup Step Counter (Pedometer)
9521 * @brief This section groups all the functions that manage pedometer.
9522 * @{
9523 *
9524 */
9525
9526 /**
9527 * @brief Step counter mode[set]
9528 *
9529 * @param ctx read / write interface definitions
9530 * @param val Step counter mode
9531 * @retval interface status (MANDATORY: return 0 -> no Error)
9532 *
9533 */
lsm6dsv16x_stpcnt_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16x_stpcnt_mode_t val)9534 int32_t lsm6dsv16x_stpcnt_mode_set(const stmdev_ctx_t *ctx,
9535 lsm6dsv16x_stpcnt_mode_t val)
9536 {
9537 lsm6dsv16x_emb_func_en_a_t emb_func_en_a;
9538 lsm6dsv16x_emb_func_en_b_t emb_func_en_b;
9539 lsm6dsv16x_pedo_cmd_reg_t pedo_cmd_reg;
9540 int32_t ret;
9541
9542 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
9543 if (ret != 0)
9544 {
9545 return ret;
9546 }
9547
9548 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9549 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
9550 if (ret != 0)
9551 {
9552 goto exit;
9553 }
9554
9555 if ((val.false_step_rej == PROPERTY_ENABLE)
9556 && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) ==
9557 PROPERTY_DISABLE))
9558 {
9559 emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE;
9560 }
9561
9562 emb_func_en_a.pedo_en = val.step_counter_enable;
9563 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9564
9565 exit:
9566 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
9567
9568 if (ret == 0)
9569 {
9570 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_CMD_REG,
9571 (uint8_t *)&pedo_cmd_reg, 1);
9572 pedo_cmd_reg.fp_rejection_en = val.false_step_rej;
9573 ret += lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_CMD_REG,
9574 (uint8_t *)&pedo_cmd_reg, 1);
9575 }
9576
9577 return ret;
9578 }
9579
9580 /**
9581 * @brief Step counter mode[get]
9582 *
9583 * @param ctx read / write interface definitions
9584 * @param val false_step_rej, step_counter, step_detector,
9585 * @retval interface status (MANDATORY: return 0 -> no Error)
9586 *
9587 */
lsm6dsv16x_stpcnt_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16x_stpcnt_mode_t * val)9588 int32_t lsm6dsv16x_stpcnt_mode_get(const stmdev_ctx_t *ctx,
9589 lsm6dsv16x_stpcnt_mode_t *val)
9590 {
9591 lsm6dsv16x_emb_func_en_a_t emb_func_en_a;
9592 lsm6dsv16x_pedo_cmd_reg_t pedo_cmd_reg;
9593 int32_t ret;
9594
9595 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
9596 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9597 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
9598 if (ret != 0)
9599 {
9600 return ret;
9601 }
9602
9603 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_CMD_REG,
9604 (uint8_t *)&pedo_cmd_reg, 1);
9605 if (ret != 0)
9606 {
9607 return ret;
9608 }
9609
9610 val->false_step_rej = pedo_cmd_reg.fp_rejection_en;
9611 val->step_counter_enable = emb_func_en_a.pedo_en;
9612
9613 return ret;
9614 }
9615
9616 /**
9617 * @brief Step counter output, number of detected steps.[get]
9618 *
9619 * @param ctx read / write interface definitions
9620 * @param val Step counter output, number of detected steps.
9621 * @retval interface status (MANDATORY: return 0 -> no Error)
9622 *
9623 */
lsm6dsv16x_stpcnt_steps_get(const stmdev_ctx_t * ctx,uint16_t * val)9624 int32_t lsm6dsv16x_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val)
9625 {
9626 uint8_t buff[2];
9627 int32_t ret;
9628
9629 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
9630 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_STEP_COUNTER_L, &buff[0], 2);
9631 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
9632 if (ret != 0)
9633 {
9634 return ret;
9635 }
9636
9637 *val = buff[1];
9638 *val = (*val * 256U) + buff[0];
9639
9640 return ret;
9641 }
9642
9643 /**
9644 * @brief Reset step counter.[set]
9645 *
9646 * @param ctx read / write interface definitions
9647 * @param val Reset step counter.
9648 * @retval interface status (MANDATORY: return 0 -> no Error)
9649 *
9650 */
lsm6dsv16x_stpcnt_rst_step_set(const stmdev_ctx_t * ctx,uint8_t val)9651 int32_t lsm6dsv16x_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val)
9652 {
9653 lsm6dsv16x_emb_func_src_t emb_func_src;
9654 int32_t ret;
9655
9656 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
9657 if (ret != 0)
9658 {
9659 return ret;
9660 }
9661
9662 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
9663 if (ret != 0)
9664 {
9665 goto exit;
9666 }
9667
9668 emb_func_src.pedo_rst_step = val;
9669 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
9670
9671 exit:
9672 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
9673
9674 return ret;
9675 }
9676
9677 /**
9678 * @brief Reset step counter.[get]
9679 *
9680 * @param ctx read / write interface definitions
9681 * @param val Reset step counter.
9682 * @retval interface status (MANDATORY: return 0 -> no Error)
9683 *
9684 */
lsm6dsv16x_stpcnt_rst_step_get(const stmdev_ctx_t * ctx,uint8_t * val)9685 int32_t lsm6dsv16x_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val)
9686 {
9687 lsm6dsv16x_emb_func_src_t emb_func_src;
9688 int32_t ret;
9689
9690 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
9691 if (ret != 0)
9692 {
9693 return ret;
9694 }
9695
9696 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
9697 *val = emb_func_src.pedo_rst_step;
9698
9699 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
9700
9701 return ret;
9702 }
9703
9704 /**
9705 * @brief Pedometer debounce configuration.[set]
9706 *
9707 * @param ctx read / write interface definitions
9708 * @param val Pedometer debounce configuration.
9709 * @retval interface status (MANDATORY: return 0 -> no Error)
9710 *
9711 */
lsm6dsv16x_stpcnt_debounce_set(const stmdev_ctx_t * ctx,uint8_t val)9712 int32_t lsm6dsv16x_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val)
9713 {
9714 lsm6dsv16x_pedo_deb_steps_conf_t pedo_deb_steps_conf;
9715 int32_t ret;
9716
9717 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_DEB_STEPS_CONF,
9718 (uint8_t *)&pedo_deb_steps_conf, 1);
9719 if (ret == 0)
9720 {
9721 pedo_deb_steps_conf.deb_step = val;
9722 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_DEB_STEPS_CONF,
9723 (uint8_t *)&pedo_deb_steps_conf, 1);
9724 }
9725
9726 return ret;
9727 }
9728
9729 /**
9730 * @brief Pedometer debounce configuration.[get]
9731 *
9732 * @param ctx read / write interface definitions
9733 * @param val Pedometer debounce configuration.
9734 * @retval interface status (MANDATORY: return 0 -> no Error)
9735 *
9736 */
lsm6dsv16x_stpcnt_debounce_get(const stmdev_ctx_t * ctx,uint8_t * val)9737 int32_t lsm6dsv16x_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val)
9738 {
9739 lsm6dsv16x_pedo_deb_steps_conf_t pedo_deb_steps_conf;
9740 int32_t ret;
9741
9742 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_DEB_STEPS_CONF,
9743 (uint8_t *)&pedo_deb_steps_conf, 1);
9744 *val = pedo_deb_steps_conf.deb_step;
9745
9746 return ret;
9747 }
9748
9749 /**
9750 * @brief Time period register for step detection on delta time.[set]
9751 *
9752 * @param ctx read / write interface definitions
9753 * @param val Time period register for step detection on delta time.
9754 * @retval interface status (MANDATORY: return 0 -> no Error)
9755 *
9756 */
lsm6dsv16x_stpcnt_period_set(const stmdev_ctx_t * ctx,uint16_t val)9757 int32_t lsm6dsv16x_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val)
9758 {
9759 uint8_t buff[2];
9760 int32_t ret;
9761
9762 buff[1] = (uint8_t)(val / 256U);
9763 buff[0] = (uint8_t)(val - (buff[1] * 256U));
9764 ret = lsm6dsv16x_ln_pg_write(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_SC_DELTAT_L,
9765 (uint8_t *)&buff[0], 2);
9766
9767 return ret;
9768 }
9769
9770 /**
9771 * @brief Time period register for step detection on delta time.[get]
9772 *
9773 * @param ctx read / write interface definitions
9774 * @param val Time period register for step detection on delta time.
9775 * @retval interface status (MANDATORY: return 0 -> no Error)
9776 *
9777 */
lsm6dsv16x_stpcnt_period_get(const stmdev_ctx_t * ctx,uint16_t * val)9778 int32_t lsm6dsv16x_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val)
9779 {
9780 uint8_t buff[2];
9781 int32_t ret;
9782
9783 ret = lsm6dsv16x_ln_pg_read(ctx, LSM6DSV16X_EMB_ADV_PG_1 + LSM6DSV16X_PEDO_SC_DELTAT_L, &buff[0],
9784 2);
9785 if (ret != 0)
9786 {
9787 return ret;
9788 }
9789
9790 *val = buff[1];
9791 *val = (*val * 256U) + buff[0];
9792
9793 return ret;
9794 }
9795
9796 /**
9797 * @}
9798 *
9799 */
9800
9801 /**
9802 * @defgroup Sensor Fusion Low Power (SFLP)
9803 * @brief This section groups all the functions that manage pedometer.
9804 * @{
9805 *
9806 */
9807
9808 /**
9809 * @brief Enable SFLP Game Rotation Vector (6x).[set]
9810 *
9811 * @param ctx read / write interface definitions
9812 * @param val Enable/Disable game rotation value (0/1).
9813 * @retval interface status (MANDATORY: return 0 -> no Error)
9814 *
9815 */
lsm6dsv16x_sflp_game_rotation_set(const stmdev_ctx_t * ctx,uint8_t val)9816 int32_t lsm6dsv16x_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint8_t val)
9817 {
9818 lsm6dsv16x_emb_func_en_a_t emb_func_en_a;
9819 int32_t ret;
9820
9821 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
9822 if (ret != 0)
9823 {
9824 return ret;
9825 }
9826
9827 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9828 if (ret != 0)
9829 {
9830 goto exit;
9831 }
9832
9833 emb_func_en_a.sflp_game_en = val;
9834 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A,
9835 (uint8_t *)&emb_func_en_a, 1);
9836
9837 exit:
9838 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
9839
9840 return ret;
9841 }
9842
9843 /**
9844 * @brief Enable SFLP Game Rotation Vector (6x).[get]
9845 *
9846 * @param ctx read / write interface definitions
9847 * @param val Enable/Disable game rotation value (0/1).
9848 * @retval interface status (MANDATORY: return 0 -> no Error)
9849 *
9850 */
lsm6dsv16x_sflp_game_rotation_get(const stmdev_ctx_t * ctx,uint8_t * val)9851 int32_t lsm6dsv16x_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint8_t *val)
9852 {
9853 lsm6dsv16x_emb_func_en_a_t emb_func_en_a;
9854 int32_t ret;
9855
9856 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
9857 if (ret != 0)
9858 {
9859 return ret;
9860 }
9861
9862 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
9863 *val = emb_func_en_a.sflp_game_en;
9864
9865 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
9866
9867 return ret;
9868 }
9869
9870 /**
9871 * @brief SFLP Data Rate (ODR) configuration.[set]
9872 *
9873 * @param ctx read / write interface definitions
9874 * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz
9875 * @retval interface status (MANDATORY: return 0 -> no Error)
9876 *
9877 */
lsm6dsv16x_sflp_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv16x_sflp_data_rate_t val)9878 int32_t lsm6dsv16x_sflp_data_rate_set(const stmdev_ctx_t *ctx,
9879 lsm6dsv16x_sflp_data_rate_t val)
9880 {
9881 lsm6dsv16x_sflp_odr_t sflp_odr;
9882 int32_t ret;
9883
9884 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
9885 if (ret != 0)
9886 {
9887 return ret;
9888 }
9889
9890 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
9891 if (ret != 0)
9892 {
9893 goto exit;
9894 }
9895
9896 sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U;
9897 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
9898
9899 exit:
9900 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
9901
9902 return ret;
9903 }
9904
9905 /**
9906 * @brief SFLP Data Rate (ODR) configuration.[get]
9907 *
9908 * @param ctx read / write interface definitions
9909 * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz
9910 * @retval interface status (MANDATORY: return 0 -> no Error)
9911 *
9912 */
lsm6dsv16x_sflp_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv16x_sflp_data_rate_t * val)9913 int32_t lsm6dsv16x_sflp_data_rate_get(const stmdev_ctx_t *ctx,
9914 lsm6dsv16x_sflp_data_rate_t *val)
9915 {
9916 lsm6dsv16x_sflp_odr_t sflp_odr;
9917 int32_t ret;
9918
9919 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
9920 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
9921 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
9922 if (ret != 0)
9923 {
9924 return ret;
9925 }
9926
9927 switch (sflp_odr.sflp_game_odr)
9928 {
9929 case LSM6DSV16X_SFLP_15Hz:
9930 *val = LSM6DSV16X_SFLP_15Hz;
9931 break;
9932
9933 case LSM6DSV16X_SFLP_30Hz:
9934 *val = LSM6DSV16X_SFLP_30Hz;
9935 break;
9936
9937 case LSM6DSV16X_SFLP_60Hz:
9938 *val = LSM6DSV16X_SFLP_60Hz;
9939 break;
9940
9941 case LSM6DSV16X_SFLP_120Hz:
9942 *val = LSM6DSV16X_SFLP_120Hz;
9943 break;
9944
9945 case LSM6DSV16X_SFLP_240Hz:
9946 *val = LSM6DSV16X_SFLP_240Hz;
9947 break;
9948
9949 case LSM6DSV16X_SFLP_480Hz:
9950 *val = LSM6DSV16X_SFLP_480Hz;
9951 break;
9952
9953 default:
9954 *val = LSM6DSV16X_SFLP_15Hz;
9955 break;
9956 }
9957
9958 return ret;
9959 }
9960
9961 /**
9962 * @}
9963 *
9964 */
9965
9966 /**
9967 * @defgroup Tap - Double Tap
9968 * @brief This section groups all the functions that manage the
9969 * tap and double tap event generation.
9970 * @{
9971 *
9972 */
9973
9974 /**
9975 * @brief Enable axis for Tap - Double Tap detection.[set]
9976 *
9977 * @param ctx read / write interface definitions
9978 * @param val Enable axis for Tap - Double Tap detection.
9979 * @retval interface status (MANDATORY: return 0 -> no Error)
9980 *
9981 */
lsm6dsv16x_tap_detection_set(const stmdev_ctx_t * ctx,lsm6dsv16x_tap_detection_t val)9982 int32_t lsm6dsv16x_tap_detection_set(const stmdev_ctx_t *ctx,
9983 lsm6dsv16x_tap_detection_t val)
9984 {
9985 lsm6dsv16x_tap_cfg0_t tap_cfg0;
9986 int32_t ret;
9987
9988 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
9989 if (ret == 0)
9990 {
9991 tap_cfg0.tap_x_en = val.tap_x_en;
9992 tap_cfg0.tap_y_en = val.tap_y_en;
9993 tap_cfg0.tap_z_en = val.tap_z_en;
9994 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
9995 }
9996
9997 return ret;
9998 }
9999
10000 /**
10001 * @brief Enable axis for Tap - Double Tap detection.[get]
10002 *
10003 * @param ctx read / write interface definitions
10004 * @param val Enable axis for Tap - Double Tap detection.
10005 * @retval interface status (MANDATORY: return 0 -> no Error)
10006 *
10007 */
lsm6dsv16x_tap_detection_get(const stmdev_ctx_t * ctx,lsm6dsv16x_tap_detection_t * val)10008 int32_t lsm6dsv16x_tap_detection_get(const stmdev_ctx_t *ctx,
10009 lsm6dsv16x_tap_detection_t *val)
10010 {
10011 lsm6dsv16x_tap_cfg0_t tap_cfg0;
10012 int32_t ret;
10013
10014 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
10015 if (ret != 0)
10016 {
10017 return ret;
10018 }
10019
10020 val->tap_x_en = tap_cfg0.tap_x_en;
10021 val->tap_y_en = tap_cfg0.tap_y_en;
10022 val->tap_z_en = tap_cfg0.tap_z_en;
10023
10024 return ret;
10025 }
10026
10027 /**
10028 * @brief axis Tap - Double Tap recognition thresholds.[set]
10029 *
10030 * @param ctx read / write interface definitions
10031 * @param val axis Tap - Double Tap recognition thresholds.
10032 * @retval interface status (MANDATORY: return 0 -> no Error)
10033 *
10034 */
lsm6dsv16x_tap_thresholds_set(const stmdev_ctx_t * ctx,lsm6dsv16x_tap_thresholds_t val)10035 int32_t lsm6dsv16x_tap_thresholds_set(const stmdev_ctx_t *ctx,
10036 lsm6dsv16x_tap_thresholds_t val)
10037 {
10038 lsm6dsv16x_tap_ths_6d_t tap_ths_6d;
10039 lsm6dsv16x_tap_cfg2_t tap_cfg2;
10040 lsm6dsv16x_tap_cfg1_t tap_cfg1;
10041 int32_t ret;
10042
10043 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
10044 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
10045 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
10046 if (ret != 0)
10047 {
10048 return ret;
10049 }
10050
10051 tap_cfg1.tap_ths_x = val.x;
10052 tap_cfg2.tap_ths_y = val.y;
10053 tap_ths_6d.tap_ths_z = val.z;
10054
10055 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
10056 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
10057 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
10058
10059 return ret;
10060 }
10061
10062 /**
10063 * @brief axis Tap - Double Tap recognition thresholds.[get]
10064 *
10065 * @param ctx read / write interface definitions
10066 * @param val axis Tap - Double Tap recognition thresholds.
10067 * @retval interface status (MANDATORY: return 0 -> no Error)
10068 *
10069 */
lsm6dsv16x_tap_thresholds_get(const stmdev_ctx_t * ctx,lsm6dsv16x_tap_thresholds_t * val)10070 int32_t lsm6dsv16x_tap_thresholds_get(const stmdev_ctx_t *ctx,
10071 lsm6dsv16x_tap_thresholds_t *val)
10072 {
10073 lsm6dsv16x_tap_ths_6d_t tap_ths_6d;
10074 lsm6dsv16x_tap_cfg2_t tap_cfg2;
10075 lsm6dsv16x_tap_cfg1_t tap_cfg1;
10076 int32_t ret;
10077
10078 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
10079 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
10080 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
10081 if (ret != 0)
10082 {
10083 return ret;
10084 }
10085
10086 val->x = tap_cfg1.tap_ths_x;
10087 val->y = tap_cfg2.tap_ths_y;
10088 val->z = tap_ths_6d.tap_ths_z;
10089
10090 return ret;
10091 }
10092
10093 /**
10094 * @brief Selection of axis priority for TAP detection.[set]
10095 *
10096 * @param ctx read / write interface definitions
10097 * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY ,
10098 * @retval interface status (MANDATORY: return 0 -> no Error)
10099 *
10100 */
lsm6dsv16x_tap_axis_priority_set(const stmdev_ctx_t * ctx,lsm6dsv16x_tap_axis_priority_t val)10101 int32_t lsm6dsv16x_tap_axis_priority_set(const stmdev_ctx_t *ctx,
10102 lsm6dsv16x_tap_axis_priority_t val)
10103 {
10104 lsm6dsv16x_tap_cfg1_t tap_cfg1;
10105 int32_t ret;
10106
10107 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
10108 if (ret == 0)
10109 {
10110 tap_cfg1.tap_priority = (uint8_t)val & 0x7U;
10111 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
10112 }
10113
10114 return ret;
10115 }
10116
10117 /**
10118 * @brief Selection of axis priority for TAP detection.[get]
10119 *
10120 * @param ctx read / write interface definitions
10121 * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY ,
10122 * @retval interface status (MANDATORY: return 0 -> no Error)
10123 *
10124 */
lsm6dsv16x_tap_axis_priority_get(const stmdev_ctx_t * ctx,lsm6dsv16x_tap_axis_priority_t * val)10125 int32_t lsm6dsv16x_tap_axis_priority_get(const stmdev_ctx_t *ctx,
10126 lsm6dsv16x_tap_axis_priority_t *val)
10127 {
10128 lsm6dsv16x_tap_cfg1_t tap_cfg1;
10129 int32_t ret;
10130
10131 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
10132 if (ret != 0)
10133 {
10134 return ret;
10135 }
10136
10137 switch (tap_cfg1.tap_priority)
10138 {
10139 case LSM6DSV16X_XYZ :
10140 *val = LSM6DSV16X_XYZ ;
10141 break;
10142
10143 case LSM6DSV16X_YXZ :
10144 *val = LSM6DSV16X_YXZ ;
10145 break;
10146
10147 case LSM6DSV16X_XZY:
10148 *val = LSM6DSV16X_XZY;
10149 break;
10150
10151 case LSM6DSV16X_ZYX :
10152 *val = LSM6DSV16X_ZYX ;
10153 break;
10154
10155 case LSM6DSV16X_YZX :
10156 *val = LSM6DSV16X_YZX ;
10157 break;
10158
10159 case LSM6DSV16X_ZXY :
10160 *val = LSM6DSV16X_ZXY ;
10161 break;
10162
10163 default:
10164 *val = LSM6DSV16X_XYZ ;
10165 break;
10166 }
10167
10168 return ret;
10169 }
10170
10171 /**
10172 * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[set]
10173 *
10174 * @param ctx read / write interface definitions
10175 * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.
10176 * @retval interface status (MANDATORY: return 0 -> no Error)
10177 *
10178 */
lsm6dsv16x_tap_time_windows_set(const stmdev_ctx_t * ctx,lsm6dsv16x_tap_time_windows_t val)10179 int32_t lsm6dsv16x_tap_time_windows_set(const stmdev_ctx_t *ctx,
10180 lsm6dsv16x_tap_time_windows_t val)
10181 {
10182 lsm6dsv16x_tap_dur_t tap_dur;
10183 int32_t ret;
10184
10185 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_DUR, (uint8_t *)&tap_dur, 1);
10186 if (ret == 0)
10187 {
10188 tap_dur.shock = val.shock;
10189 tap_dur.quiet = val.quiet;
10190 tap_dur.dur = val.tap_gap;
10191 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_TAP_DUR, (uint8_t *)&tap_dur, 1);
10192 }
10193
10194 return ret;
10195 }
10196
10197 /**
10198 * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[get]
10199 *
10200 * @param ctx read / write interface definitions
10201 * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.
10202 * @retval interface status (MANDATORY: return 0 -> no Error)
10203 *
10204 */
lsm6dsv16x_tap_time_windows_get(const stmdev_ctx_t * ctx,lsm6dsv16x_tap_time_windows_t * val)10205 int32_t lsm6dsv16x_tap_time_windows_get(const stmdev_ctx_t *ctx,
10206 lsm6dsv16x_tap_time_windows_t *val)
10207 {
10208 lsm6dsv16x_tap_dur_t tap_dur;
10209 int32_t ret;
10210
10211 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TAP_DUR, (uint8_t *)&tap_dur, 1);
10212 if (ret != 0)
10213 {
10214 return ret;
10215 }
10216
10217 val->shock = tap_dur.shock;
10218 val->quiet = tap_dur.quiet;
10219 val->tap_gap = tap_dur.dur;
10220
10221 return ret;
10222 }
10223
10224 /**
10225 * @brief Single/double-tap event enable.[set]
10226 *
10227 * @param ctx read / write interface definitions
10228 * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE,
10229 * @retval interface status (MANDATORY: return 0 -> no Error)
10230 *
10231 */
lsm6dsv16x_tap_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16x_tap_mode_t val)10232 int32_t lsm6dsv16x_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t val)
10233 {
10234 lsm6dsv16x_wake_up_ths_t wake_up_ths;
10235 int32_t ret;
10236
10237 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
10238 if (ret == 0)
10239 {
10240 wake_up_ths.single_double_tap = (uint8_t)val & 0x01U;
10241 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
10242 }
10243
10244 return ret;
10245 }
10246
10247 /**
10248 * @brief Single/double-tap event enable.[get]
10249 *
10250 * @param ctx read / write interface definitions
10251 * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE,
10252 * @retval interface status (MANDATORY: return 0 -> no Error)
10253 *
10254 */
lsm6dsv16x_tap_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16x_tap_mode_t * val)10255 int32_t lsm6dsv16x_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_tap_mode_t *val)
10256 {
10257 lsm6dsv16x_wake_up_ths_t wake_up_ths;
10258 int32_t ret;
10259
10260 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
10261 if (ret != 0)
10262 {
10263 return ret;
10264 }
10265
10266 switch (wake_up_ths.single_double_tap)
10267 {
10268 case LSM6DSV16X_ONLY_SINGLE:
10269 *val = LSM6DSV16X_ONLY_SINGLE;
10270 break;
10271
10272 case LSM6DSV16X_BOTH_SINGLE_DOUBLE:
10273 *val = LSM6DSV16X_BOTH_SINGLE_DOUBLE;
10274 break;
10275
10276 default:
10277 *val = LSM6DSV16X_ONLY_SINGLE;
10278 break;
10279 }
10280
10281 return ret;
10282 }
10283
10284 /**
10285 * @}
10286 *
10287 */
10288
10289 /**
10290 * @defgroup Tilt detection
10291 * @brief This section groups all the functions that manage the tilt
10292 * event detection.
10293 * @{
10294 *
10295 */
10296
10297 /**
10298 * @brief Tilt calculation.[set]
10299 *
10300 * @param ctx read / write interface definitions
10301 * @param val Tilt calculation.
10302 * @retval interface status (MANDATORY: return 0 -> no Error)
10303 *
10304 */
lsm6dsv16x_tilt_mode_set(const stmdev_ctx_t * ctx,uint8_t val)10305 int32_t lsm6dsv16x_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
10306 {
10307 lsm6dsv16x_emb_func_en_a_t emb_func_en_a;
10308 int32_t ret;
10309
10310 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
10311 if (ret != 0)
10312 {
10313 return ret;
10314 }
10315
10316 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
10317 emb_func_en_a.tilt_en = val;
10318 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
10319
10320 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
10321
10322 return ret;
10323 }
10324
10325 /**
10326 * @brief Tilt calculation.[get]
10327 *
10328 * @param ctx read / write interface definitions
10329 * @param val Tilt calculation.
10330 * @retval interface status (MANDATORY: return 0 -> no Error)
10331 *
10332 */
lsm6dsv16x_tilt_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)10333 int32_t lsm6dsv16x_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
10334 {
10335 lsm6dsv16x_emb_func_en_a_t emb_func_en_a;
10336 int32_t ret;
10337
10338 ret = lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_EMBED_FUNC_MEM_BANK);
10339 if (ret != 0)
10340 {
10341 return ret;
10342 }
10343
10344 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
10345 *val = emb_func_en_a.tilt_en;
10346
10347 ret += lsm6dsv16x_mem_bank_set(ctx, LSM6DSV16X_MAIN_MEM_BANK);
10348
10349 return ret;
10350 }
10351
10352 /**
10353 * @}
10354 *
10355 */
10356
10357 /**
10358 * @defgroup Timestamp
10359 * @brief This section groups all the functions that manage the
10360 * timestamp generation.
10361 * @{
10362 *
10363 */
10364
10365 /**
10366 * @brief Timestamp data output.[get]
10367 *
10368 * @param ctx read / write interface definitions
10369 * @param val Timestamp data output.
10370 * @retval interface status (MANDATORY: return 0 -> no Error)
10371 *
10372 */
lsm6dsv16x_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)10373 int32_t lsm6dsv16x_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
10374 {
10375 uint8_t buff[4];
10376 int32_t ret;
10377
10378 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_TIMESTAMP0, &buff[0], 4);
10379 if (ret != 0)
10380 {
10381 return ret;
10382 }
10383
10384 *val = buff[3];
10385 *val = (*val * 256U) + buff[2];
10386 *val = (*val * 256U) + buff[1];
10387 *val = (*val * 256U) + buff[0];
10388
10389 return ret;
10390 }
10391
10392 /**
10393 * @brief Enables timestamp counter.[set]
10394 *
10395 * @param ctx read / write interface definitions
10396 * @param val Enables timestamp counter.
10397 * @retval interface status (MANDATORY: return 0 -> no Error)
10398 *
10399 */
lsm6dsv16x_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)10400 int32_t lsm6dsv16x_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
10401 {
10402 lsm6dsv16x_functions_enable_t functions_enable;
10403 int32_t ret;
10404
10405 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
10406 if (ret == 0)
10407 {
10408 functions_enable.timestamp_en = val;
10409 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
10410 }
10411
10412 return ret;
10413 }
10414
10415 /**
10416 * @brief Enables timestamp counter.[get]
10417 *
10418 * @param ctx read / write interface definitions
10419 * @param val Enables timestamp counter.
10420 * @retval interface status (MANDATORY: return 0 -> no Error)
10421 *
10422 */
lsm6dsv16x_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)10423 int32_t lsm6dsv16x_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
10424 {
10425 lsm6dsv16x_functions_enable_t functions_enable;
10426 int32_t ret;
10427
10428 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
10429 *val = functions_enable.timestamp_en;
10430
10431 return ret;
10432 }
10433
10434 /**
10435 * @}
10436 *
10437 */
10438
10439 /**
10440 * @defgroup Wake Up - Activity - Inactivity (Sleep)
10441 * @brief This section groups all the functions that manage the Wake Up
10442 * event generation.
10443 * @{
10444 *
10445 */
10446
10447 /**
10448 * @brief Enable activity/inactivity (sleep) function.[set]
10449 *
10450 * @param ctx read / write interface definitions
10451 * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN,
10452 * @retval interface status (MANDATORY: return 0 -> no Error)
10453 *
10454 */
lsm6dsv16x_act_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16x_act_mode_t val)10455 int32_t lsm6dsv16x_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t val)
10456 {
10457 lsm6dsv16x_functions_enable_t functions_enable;
10458 int32_t ret;
10459
10460 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
10461 if (ret == 0)
10462 {
10463 functions_enable.inact_en = (uint8_t)val & 0x3U;
10464 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
10465 }
10466
10467 return ret;
10468 }
10469
10470 /**
10471 * @brief Enable activity/inactivity (sleep) function.[get]
10472 *
10473 * @param ctx read / write interface definitions
10474 * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN,
10475 * @retval interface status (MANDATORY: return 0 -> no Error)
10476 *
10477 */
lsm6dsv16x_act_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16x_act_mode_t * val)10478 int32_t lsm6dsv16x_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16x_act_mode_t *val)
10479 {
10480 lsm6dsv16x_functions_enable_t functions_enable;
10481 int32_t ret;
10482
10483 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
10484 if (ret != 0)
10485 {
10486 return ret;
10487 }
10488
10489 switch (functions_enable.inact_en)
10490 {
10491 case LSM6DSV16X_XL_AND_GY_NOT_AFFECTED:
10492 *val = LSM6DSV16X_XL_AND_GY_NOT_AFFECTED;
10493 break;
10494
10495 case LSM6DSV16X_XL_LOW_POWER_GY_NOT_AFFECTED:
10496 *val = LSM6DSV16X_XL_LOW_POWER_GY_NOT_AFFECTED;
10497 break;
10498
10499 case LSM6DSV16X_XL_LOW_POWER_GY_SLEEP:
10500 *val = LSM6DSV16X_XL_LOW_POWER_GY_SLEEP;
10501 break;
10502
10503 case LSM6DSV16X_XL_LOW_POWER_GY_POWER_DOWN:
10504 *val = LSM6DSV16X_XL_LOW_POWER_GY_POWER_DOWN;
10505 break;
10506
10507 default:
10508 *val = LSM6DSV16X_XL_AND_GY_NOT_AFFECTED;
10509 break;
10510 }
10511
10512 return ret;
10513 }
10514
10515 /**
10516 * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[set]
10517 *
10518 * @param ctx read / write interface definitions
10519 * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE,
10520 * @retval interface status (MANDATORY: return 0 -> no Error)
10521 *
10522 */
lsm6dsv16x_act_from_sleep_to_act_dur_set(const stmdev_ctx_t * ctx,lsm6dsv16x_act_from_sleep_to_act_dur_t val)10523 int32_t lsm6dsv16x_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx,
10524 lsm6dsv16x_act_from_sleep_to_act_dur_t val)
10525 {
10526 lsm6dsv16x_inactivity_dur_t inactivity_dur;
10527 int32_t ret;
10528
10529 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10530 if (ret == 0)
10531 {
10532 inactivity_dur.inact_dur = (uint8_t)val & 0x3U;
10533 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10534 }
10535
10536 return ret;
10537 }
10538
10539 /**
10540 * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[get]
10541 *
10542 * @param ctx read / write interface definitions
10543 * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE,
10544 * @retval interface status (MANDATORY: return 0 -> no Error)
10545 *
10546 */
lsm6dsv16x_act_from_sleep_to_act_dur_get(const stmdev_ctx_t * ctx,lsm6dsv16x_act_from_sleep_to_act_dur_t * val)10547 int32_t lsm6dsv16x_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx,
10548 lsm6dsv16x_act_from_sleep_to_act_dur_t *val)
10549 {
10550 lsm6dsv16x_inactivity_dur_t inactivity_dur;
10551 int32_t ret;
10552
10553 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10554 if (ret != 0)
10555 {
10556 return ret;
10557 }
10558
10559 switch (inactivity_dur.inact_dur)
10560 {
10561 case LSM6DSV16X_SLEEP_TO_ACT_AT_1ST_SAMPLE:
10562 *val = LSM6DSV16X_SLEEP_TO_ACT_AT_1ST_SAMPLE;
10563 break;
10564
10565 case LSM6DSV16X_SLEEP_TO_ACT_AT_2ND_SAMPLE:
10566 *val = LSM6DSV16X_SLEEP_TO_ACT_AT_2ND_SAMPLE;
10567 break;
10568
10569 case LSM6DSV16X_SLEEP_TO_ACT_AT_3RD_SAMPLE:
10570 *val = LSM6DSV16X_SLEEP_TO_ACT_AT_3RD_SAMPLE;
10571 break;
10572
10573 case LSM6DSV16X_SLEEP_TO_ACT_AT_4th_SAMPLE:
10574 *val = LSM6DSV16X_SLEEP_TO_ACT_AT_4th_SAMPLE;
10575 break;
10576
10577 default:
10578 *val = LSM6DSV16X_SLEEP_TO_ACT_AT_1ST_SAMPLE;
10579 break;
10580 }
10581
10582 return ret;
10583 }
10584
10585 /**
10586 * @brief Selects the accelerometer data rate during Inactivity.[set]
10587 *
10588 * @param ctx read / write interface definitions
10589 * @param val 1Hz875, 15Hz, 30Hz, 60Hz,
10590 * @retval interface status (MANDATORY: return 0 -> no Error)
10591 *
10592 */
lsm6dsv16x_act_sleep_xl_odr_set(const stmdev_ctx_t * ctx,lsm6dsv16x_act_sleep_xl_odr_t val)10593 int32_t lsm6dsv16x_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx,
10594 lsm6dsv16x_act_sleep_xl_odr_t val)
10595 {
10596 lsm6dsv16x_inactivity_dur_t inactivity_dur;
10597 int32_t ret;
10598
10599 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10600 if (ret == 0)
10601 {
10602 inactivity_dur.xl_inact_odr = (uint8_t)val & 0x03U;
10603 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10604 }
10605
10606 return ret;
10607 }
10608
10609 /**
10610 * @brief Selects the accelerometer data rate during Inactivity.[get]
10611 *
10612 * @param ctx read / write interface definitions
10613 * @param val 1Hz875, 15Hz, 30Hz, 60Hz,
10614 * @retval interface status (MANDATORY: return 0 -> no Error)
10615 *
10616 */
lsm6dsv16x_act_sleep_xl_odr_get(const stmdev_ctx_t * ctx,lsm6dsv16x_act_sleep_xl_odr_t * val)10617 int32_t lsm6dsv16x_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx,
10618 lsm6dsv16x_act_sleep_xl_odr_t *val)
10619 {
10620 lsm6dsv16x_inactivity_dur_t inactivity_dur;
10621 int32_t ret;
10622
10623 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10624 if (ret != 0)
10625 {
10626 return ret;
10627 }
10628
10629 switch (inactivity_dur.xl_inact_odr)
10630 {
10631 case LSM6DSV16X_1Hz875:
10632 *val = LSM6DSV16X_1Hz875;
10633 break;
10634
10635 case LSM6DSV16X_15Hz:
10636 *val = LSM6DSV16X_15Hz;
10637 break;
10638
10639 case LSM6DSV16X_30Hz:
10640 *val = LSM6DSV16X_30Hz;
10641 break;
10642
10643 case LSM6DSV16X_60Hz:
10644 *val = LSM6DSV16X_60Hz;
10645 break;
10646
10647 default:
10648 *val = LSM6DSV16X_1Hz875;
10649 break;
10650 }
10651
10652 return ret;
10653 }
10654
10655 /**
10656 * @brief Wakeup and activity/inactivity threshold.[set]
10657 *
10658 * @param ctx read / write interface definitions
10659 * @param val Wakeup and activity/inactivity threshold.
10660 * @retval interface status (MANDATORY: return 0 -> no Error)
10661 *
10662 */
lsm6dsv16x_act_thresholds_set(const stmdev_ctx_t * ctx,lsm6dsv16x_act_thresholds_t * val)10663 int32_t lsm6dsv16x_act_thresholds_set(const stmdev_ctx_t *ctx,
10664 lsm6dsv16x_act_thresholds_t *val)
10665 {
10666 lsm6dsv16x_inactivity_ths_t inactivity_ths;
10667 lsm6dsv16x_inactivity_dur_t inactivity_dur;
10668 lsm6dsv16x_wake_up_ths_t wake_up_ths;
10669 lsm6dsv16x_wake_up_dur_t wake_up_dur;
10670 int32_t ret;
10671
10672 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10673 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
10674 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
10675 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
10676 if (ret != 0)
10677 {
10678 return ret;
10679 }
10680
10681 inactivity_dur.wu_inact_ths_w = val->inactivity_cfg.wu_inact_ths_w;
10682 inactivity_dur.xl_inact_odr = val->inactivity_cfg.xl_inact_odr;
10683 inactivity_dur.inact_dur = val->inactivity_cfg.inact_dur;
10684
10685 inactivity_ths.inact_ths = val->inactivity_ths;
10686 wake_up_ths.wk_ths = val->threshold;
10687 wake_up_dur.wake_dur = val->duration;
10688
10689 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10690 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
10691 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
10692 ret += lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
10693
10694 return ret;
10695 }
10696
10697 /**
10698 * @brief Wakeup and activity/inactivity threshold.[get]
10699 *
10700 * @param ctx read / write interface definitions
10701 * @param val Wakeup and activity/inactivity threshold.
10702 * @retval interface status (MANDATORY: return 0 -> no Error)
10703 *
10704 */
lsm6dsv16x_act_thresholds_get(const stmdev_ctx_t * ctx,lsm6dsv16x_act_thresholds_t * val)10705 int32_t lsm6dsv16x_act_thresholds_get(const stmdev_ctx_t *ctx,
10706 lsm6dsv16x_act_thresholds_t *val)
10707 {
10708 lsm6dsv16x_inactivity_dur_t inactivity_dur;
10709 lsm6dsv16x_inactivity_ths_t inactivity_ths;
10710 lsm6dsv16x_wake_up_ths_t wake_up_ths;
10711 lsm6dsv16x_wake_up_dur_t wake_up_dur;
10712 int32_t ret;
10713
10714 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
10715 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
10716 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
10717 ret += lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
10718 if (ret != 0)
10719 {
10720 return ret;
10721 }
10722
10723 val->inactivity_cfg.wu_inact_ths_w = inactivity_dur.wu_inact_ths_w;
10724 val->inactivity_cfg.xl_inact_odr = inactivity_dur.xl_inact_odr;
10725 val->inactivity_cfg.inact_dur = inactivity_dur.inact_dur;
10726
10727 val->inactivity_ths = inactivity_ths.inact_ths;
10728 val->threshold = wake_up_ths.wk_ths;
10729 val->duration = wake_up_dur.wake_dur;
10730
10731 return ret;
10732 }
10733
10734 /**
10735 * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [set]
10736 *
10737 * @param ctx read / write interface definitions
10738 * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time.
10739 * @retval interface status (MANDATORY: return 0 -> no Error)
10740 *
10741 */
lsm6dsv16x_act_wkup_time_windows_set(const stmdev_ctx_t * ctx,lsm6dsv16x_act_wkup_time_windows_t val)10742 int32_t lsm6dsv16x_act_wkup_time_windows_set(const stmdev_ctx_t *ctx,
10743 lsm6dsv16x_act_wkup_time_windows_t val)
10744 {
10745 lsm6dsv16x_wake_up_dur_t wake_up_dur;
10746 int32_t ret;
10747
10748 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
10749 if (ret == 0)
10750 {
10751 wake_up_dur.wake_dur = val.shock;
10752 wake_up_dur.sleep_dur = val.quiet;
10753 ret = lsm6dsv16x_write_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
10754 }
10755
10756 return ret;
10757 }
10758
10759 /**
10760 * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [get]
10761 *
10762 * @param ctx read / write interface definitions
10763 * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time.
10764 * @retval interface status (MANDATORY: return 0 -> no Error)
10765 *
10766 */
lsm6dsv16x_act_wkup_time_windows_get(const stmdev_ctx_t * ctx,lsm6dsv16x_act_wkup_time_windows_t * val)10767 int32_t lsm6dsv16x_act_wkup_time_windows_get(const stmdev_ctx_t *ctx,
10768 lsm6dsv16x_act_wkup_time_windows_t *val)
10769 {
10770 lsm6dsv16x_wake_up_dur_t wake_up_dur;
10771 int32_t ret;
10772
10773 ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
10774 if (ret != 0)
10775 {
10776 return ret;
10777 }
10778
10779 val->shock = wake_up_dur.wake_dur;
10780 val->quiet = wake_up_dur.sleep_dur;
10781
10782 return ret;
10783 }
10784
10785 /**
10786 * @}
10787 *
10788 */
10789
