1 /**
2 ******************************************************************************
3 * @file lsm6dsv16bx_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSV16BX driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dsv16bx_reg.h"
21
22 /**
23 * @defgroup LSM6DSV16BX
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dsv16bx enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup Interfaces functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx communication interface handler.(ptr)
43 * @param reg first register address to read.
44 * @param data buffer for data read.(ptr)
45 * @param len number of consecutive register to read.
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6dsv16bx_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dsv16bx_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 ret = ctx->read_reg(ctx->handle, reg, data, len);
56
57 return ret;
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx communication interface handler.(ptr)
64 * @param reg first register address to write.
65 * @param data the buffer contains data to be written.(ptr)
66 * @param len number of consecutive register to write.
67 * @retval interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
lsm6dsv16bx_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak lsm6dsv16bx_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
71 uint8_t *data,
72 uint16_t len)
73 {
74 int32_t ret;
75
76 ret = ctx->write_reg(ctx->handle, reg, data, len);
77
78 return ret;
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup Private functions
88 * @brief Section collect all the utility functions needed by APIs.
89 * @{
90 *
91 */
92
bytecpy(uint8_t * target,uint8_t * source)93 static void bytecpy(uint8_t *target, uint8_t *source)
94 {
95 if ((target != NULL) && (source != NULL))
96 {
97 *target = *source;
98 }
99 }
100
101 /**
102 * @}
103 *
104 */
105
106 /**
107 * @defgroup Sensitivity
108 * @brief These functions convert raw-data into engineering units.
109 * @{
110 *
111 */
lsm6dsv16bx_from_sflp_to_mg(int16_t lsb)112 float_t lsm6dsv16bx_from_sflp_to_mg(int16_t lsb)
113 {
114 return ((float_t)lsb) * 0.061f;
115 }
116
lsm6dsv16bx_from_fs2_to_mg(int16_t lsb)117 float_t lsm6dsv16bx_from_fs2_to_mg(int16_t lsb)
118 {
119 return ((float_t)lsb) * 0.061f;
120 }
121
lsm6dsv16bx_from_fs4_to_mg(int16_t lsb)122 float_t lsm6dsv16bx_from_fs4_to_mg(int16_t lsb)
123 {
124 return ((float_t)lsb) * 0.122f;
125 }
126
lsm6dsv16bx_from_fs8_to_mg(int16_t lsb)127 float_t lsm6dsv16bx_from_fs8_to_mg(int16_t lsb)
128 {
129 return ((float_t)lsb) * 0.244f;
130 }
131
lsm6dsv16bx_from_fs16_to_mg(int16_t lsb)132 float_t lsm6dsv16bx_from_fs16_to_mg(int16_t lsb)
133 {
134 return ((float_t)lsb) * 0.488f;
135 }
136
lsm6dsv16bx_from_fs125_to_mdps(int16_t lsb)137 float_t lsm6dsv16bx_from_fs125_to_mdps(int16_t lsb)
138 {
139 return ((float_t)lsb) * 4.375f;
140 }
141
lsm6dsv16bx_from_fs250_to_mdps(int16_t lsb)142 float_t lsm6dsv16bx_from_fs250_to_mdps(int16_t lsb)
143 {
144 return ((float_t)lsb) * 8.750f;
145 }
146
lsm6dsv16bx_from_fs500_to_mdps(int16_t lsb)147 float_t lsm6dsv16bx_from_fs500_to_mdps(int16_t lsb)
148 {
149 return ((float_t)lsb) * 17.50f;
150 }
151
lsm6dsv16bx_from_fs1000_to_mdps(int16_t lsb)152 float_t lsm6dsv16bx_from_fs1000_to_mdps(int16_t lsb)
153 {
154 return ((float_t)lsb) * 35.0f;
155 }
156
lsm6dsv16bx_from_fs2000_to_mdps(int16_t lsb)157 float_t lsm6dsv16bx_from_fs2000_to_mdps(int16_t lsb)
158 {
159 return ((float_t)lsb) * 70.0f;
160 }
161
lsm6dsv16bx_from_fs4000_to_mdps(int16_t lsb)162 float_t lsm6dsv16bx_from_fs4000_to_mdps(int16_t lsb)
163 {
164 return ((float_t)lsb) * 140.0f;
165 }
166
lsm6dsv16bx_from_lsb_to_celsius(int16_t lsb)167 float_t lsm6dsv16bx_from_lsb_to_celsius(int16_t lsb)
168 {
169 return (((float_t)lsb / 256.0f) + 25.0f);
170 }
171
lsm6dsv16bx_from_lsb_to_nsec(uint32_t lsb)172 uint64_t lsm6dsv16bx_from_lsb_to_nsec(uint32_t lsb)
173 {
174 return ((uint64_t)lsb * 21750);
175 }
176
177 /**
178 * @}
179 *
180 */
181
182 /**
183 * @defgroup Common
184 * @brief This section groups common useful functions.
185 *
186 */
187
188 /**
189 * @brief Reset of the device.[set]
190 *
191 * @param ctx read / write interface definitions
192 * @param val Reset of the device.
193 * @retval interface status (MANDATORY: return 0 -> no Error)
194 *
195 */
lsm6dsv16bx_reset_set(stmdev_ctx_t * ctx,lsm6dsv16bx_reset_t val)196 int32_t lsm6dsv16bx_reset_set(stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t val)
197 {
198 lsm6dsv16bx_func_cfg_access_t func_cfg_access;
199 lsm6dsv16bx_ctrl3_t ctrl3;
200 int32_t ret;
201
202 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1);
203 if (ret == 0)
204 {
205 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
206 }
207
208 ctrl3.boot = ((uint8_t)val & 0x04U) >> 2;
209 ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1;
210 func_cfg_access.sw_por = (uint8_t)val & 0x01U;
211
212 if (ret == 0)
213 {
214 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1);
215 }
216 if (ret == 0)
217 {
218 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
219 }
220
221 return ret;
222 }
223
224 /**
225 * @brief Global reset of the device.[get]
226 *
227 * @param ctx read / write interface definitions
228 * @param val Global reset of the device.
229 * @retval interface status (MANDATORY: return 0 -> no Error)
230 *
231 */
lsm6dsv16bx_reset_get(stmdev_ctx_t * ctx,lsm6dsv16bx_reset_t * val)232 int32_t lsm6dsv16bx_reset_get(stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t *val)
233 {
234 lsm6dsv16bx_func_cfg_access_t func_cfg_access;
235 lsm6dsv16bx_ctrl3_t ctrl3;
236 int32_t ret;
237
238 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1);
239 if (ret == 0)
240 {
241 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
242 }
243
244 switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por)
245 {
246 case LSM6DSV16BX_READY:
247 *val = LSM6DSV16BX_READY;
248 break;
249
250 case LSM6DSV16BX_GLOBAL_RST:
251 *val = LSM6DSV16BX_GLOBAL_RST;
252 break;
253
254 case LSM6DSV16BX_RESTORE_CAL_PARAM:
255 *val = LSM6DSV16BX_RESTORE_CAL_PARAM;
256 break;
257
258 case LSM6DSV16BX_RESTORE_CTRL_REGS:
259 *val = LSM6DSV16BX_RESTORE_CTRL_REGS;
260 break;
261
262 default:
263 *val = LSM6DSV16BX_GLOBAL_RST;
264 break;
265 }
266 return ret;
267 }
268
269 /**
270 * @brief Change memory bank.[set]
271 *
272 * @param ctx read / write interface definitions
273 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK,
274 * @retval interface status (MANDATORY: return 0 -> no Error)
275 *
276 */
lsm6dsv16bx_mem_bank_set(stmdev_ctx_t * ctx,lsm6dsv16bx_mem_bank_t val)277 int32_t lsm6dsv16bx_mem_bank_set(stmdev_ctx_t *ctx, lsm6dsv16bx_mem_bank_t val)
278 {
279 lsm6dsv16bx_func_cfg_access_t func_cfg_access;
280 int32_t ret;
281
282 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
283 if (ret == 0)
284 {
285 func_cfg_access.emb_func_reg_access = (uint8_t)val & 0x01U;
286 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
287 }
288
289 return ret;
290 }
291
292 /**
293 * @brief Change memory bank.[get]
294 *
295 * @param ctx read / write interface definitions
296 * @param val MAIN_MEM_BANK, SENSOR_HUB_MEM_BANK, EMBED_FUNC_MEM_BANK,
297 * @retval interface status (MANDATORY: return 0 -> no Error)
298 *
299 */
lsm6dsv16bx_mem_bank_get(stmdev_ctx_t * ctx,lsm6dsv16bx_mem_bank_t * val)300 int32_t lsm6dsv16bx_mem_bank_get(stmdev_ctx_t *ctx, lsm6dsv16bx_mem_bank_t *val)
301 {
302 lsm6dsv16bx_func_cfg_access_t func_cfg_access;
303 int32_t ret;
304
305 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
306
307 switch (func_cfg_access.emb_func_reg_access)
308 {
309 case LSM6DSV16BX_MAIN_MEM_BANK:
310 *val = LSM6DSV16BX_MAIN_MEM_BANK;
311 break;
312
313 case LSM6DSV16BX_EMBED_FUNC_MEM_BANK:
314 *val = LSM6DSV16BX_EMBED_FUNC_MEM_BANK;
315 break;
316
317 default:
318 *val = LSM6DSV16BX_MAIN_MEM_BANK;
319 break;
320 }
321 return ret;
322 }
323
324 /**
325 * @brief Device ID.[get]
326 *
327 * @param ctx read / write interface definitions
328 * @param val Device ID.
329 * @retval interface status (MANDATORY: return 0 -> no Error)
330 *
331 */
lsm6dsv16bx_device_id_get(stmdev_ctx_t * ctx,uint8_t * val)332 int32_t lsm6dsv16bx_device_id_get(stmdev_ctx_t *ctx, uint8_t *val)
333 {
334 lsm6dsv16bx_who_am_i_t who_am_i;
335 int32_t ret;
336
337 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WHO_AM_I, (uint8_t *)&who_am_i, 1);
338 *val = who_am_i.id;
339
340 return ret;
341 }
342
343 /**
344 * @brief Accelerometer output data rate (ODR) selection.[set]
345 *
346 * @param ctx read / write interface definitions
347 * @param val XL_ODR_OFF, XL_ODR_AT_1Hz875, XL_ODR_AT_7Hz5, XL_ODR_AT_15Hz, XL_ODR_AT_30Hz, XL_ODR_AT_60Hz, XL_ODR_AT_120Hz, XL_ODR_AT_240Hz, XL_ODR_AT_480Hz, XL_ODR_AT_960Hz, XL_ODR_AT_1920Hz, XL_ODR_AT_3840Hz, XL_ODR_AT_7680Hz,
348 * @retval interface status (MANDATORY: return 0 -> no Error)
349 *
350 */
lsm6dsv16bx_xl_data_rate_set(stmdev_ctx_t * ctx,lsm6dsv16bx_xl_data_rate_t val)351 int32_t lsm6dsv16bx_xl_data_rate_set(stmdev_ctx_t *ctx,
352 lsm6dsv16bx_xl_data_rate_t val)
353 {
354 lsm6dsv16bx_ctrl1_t ctrl1;
355 int32_t ret;
356
357 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1);
358 if (ret == 0)
359 {
360 ctrl1.odr_xl = (uint8_t)val & 0xFU;
361 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1);
362 }
363
364 return ret;
365 }
366
367 /**
368 * @brief Accelerometer output data rate (ODR) selection.[get]
369 *
370 * @param ctx read / write interface definitions
371 * @param val XL_ODR_OFF, XL_ODR_AT_1Hz875, XL_ODR_AT_7Hz5, XL_ODR_AT_15Hz, XL_ODR_AT_30Hz, XL_ODR_AT_60Hz, XL_ODR_AT_120Hz, XL_ODR_AT_240Hz, XL_ODR_AT_480Hz, XL_ODR_AT_960Hz, XL_ODR_AT_1920Hz, XL_ODR_AT_3840Hz, XL_ODR_AT_7680Hz,
372 * @retval interface status (MANDATORY: return 0 -> no Error)
373 *
374 */
lsm6dsv16bx_xl_data_rate_get(stmdev_ctx_t * ctx,lsm6dsv16bx_xl_data_rate_t * val)375 int32_t lsm6dsv16bx_xl_data_rate_get(stmdev_ctx_t *ctx,
376 lsm6dsv16bx_xl_data_rate_t *val)
377 {
378 lsm6dsv16bx_ctrl1_t ctrl1;
379 int32_t ret;
380
381 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1);
382
383 switch (ctrl1.odr_xl)
384 {
385 case LSM6DSV16BX_XL_ODR_OFF:
386 *val = LSM6DSV16BX_XL_ODR_OFF;
387 break;
388
389 case LSM6DSV16BX_XL_ODR_AT_1Hz875:
390 *val = LSM6DSV16BX_XL_ODR_AT_1Hz875;
391 break;
392
393 case LSM6DSV16BX_XL_ODR_AT_7Hz5:
394 *val = LSM6DSV16BX_XL_ODR_AT_7Hz5;
395 break;
396
397 case LSM6DSV16BX_XL_ODR_AT_15Hz:
398 *val = LSM6DSV16BX_XL_ODR_AT_15Hz;
399 break;
400
401 case LSM6DSV16BX_XL_ODR_AT_30Hz:
402 *val = LSM6DSV16BX_XL_ODR_AT_30Hz;
403 break;
404
405 case LSM6DSV16BX_XL_ODR_AT_60Hz:
406 *val = LSM6DSV16BX_XL_ODR_AT_60Hz;
407 break;
408
409 case LSM6DSV16BX_XL_ODR_AT_120Hz:
410 *val = LSM6DSV16BX_XL_ODR_AT_120Hz;
411 break;
412
413 case LSM6DSV16BX_XL_ODR_AT_240Hz:
414 *val = LSM6DSV16BX_XL_ODR_AT_240Hz;
415 break;
416
417 case LSM6DSV16BX_XL_ODR_AT_480Hz:
418 *val = LSM6DSV16BX_XL_ODR_AT_480Hz;
419 break;
420
421 case LSM6DSV16BX_XL_ODR_AT_960Hz:
422 *val = LSM6DSV16BX_XL_ODR_AT_960Hz;
423 break;
424
425 case LSM6DSV16BX_XL_ODR_AT_1920Hz:
426 *val = LSM6DSV16BX_XL_ODR_AT_1920Hz;
427 break;
428
429 case LSM6DSV16BX_XL_ODR_AT_3840Hz:
430 *val = LSM6DSV16BX_XL_ODR_AT_3840Hz;
431 break;
432
433 case LSM6DSV16BX_XL_ODR_AT_7680Hz:
434 *val = LSM6DSV16BX_XL_ODR_AT_7680Hz;
435 break;
436
437 default:
438 *val = LSM6DSV16BX_XL_ODR_OFF;
439 break;
440 }
441 return ret;
442 }
443
444 /**
445 * @brief Accelerometer operating mode selection.[set]
446 *
447 * @param ctx read / write interface definitions
448 * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURANCY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD,
449 * @retval interface status (MANDATORY: return 0 -> no Error)
450 *
451 */
lsm6dsv16bx_xl_mode_set(stmdev_ctx_t * ctx,lsm6dsv16bx_xl_mode_t val)452 int32_t lsm6dsv16bx_xl_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t val)
453 {
454 lsm6dsv16bx_ctrl1_t ctrl1;
455 int32_t ret;
456
457 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1);
458
459 if (ret == 0)
460 {
461 ctrl1.op_mode_xl = (uint8_t)val & 0x07U;
462 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1);
463 }
464
465 return ret;
466 }
467
468 /**
469 * @brief Accelerometer operating mode selection.[get]
470 *
471 * @param ctx read / write interface definitions
472 * @param val XL_HIGH_PERFORMANCE_MD, XL_HIGH_ACCURANCY_ODR_MD, XL_LOW_POWER_2_AVG_MD, XL_LOW_POWER_4_AVG_MD, XL_LOW_POWER_8_AVG_MD, XL_NORMAL_MD,
473 * @retval interface status (MANDATORY: return 0 -> no Error)
474 *
475 */
lsm6dsv16bx_xl_mode_get(stmdev_ctx_t * ctx,lsm6dsv16bx_xl_mode_t * val)476 int32_t lsm6dsv16bx_xl_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t *val)
477 {
478 lsm6dsv16bx_ctrl1_t ctrl1;
479 int32_t ret;
480
481 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1);
482
483 switch (ctrl1.op_mode_xl)
484 {
485 case LSM6DSV16BX_XL_HIGH_PERFORMANCE_MD:
486 *val = LSM6DSV16BX_XL_HIGH_PERFORMANCE_MD;
487 break;
488
489 case LSM6DSV16BX_XL_HIGH_ACCURANCY_ODR_MD:
490 *val = LSM6DSV16BX_XL_HIGH_ACCURANCY_ODR_MD;
491 break;
492
493 case LSM6DSV16BX_XL_LOW_POWER_2_AVG_MD:
494 *val = LSM6DSV16BX_XL_LOW_POWER_2_AVG_MD;
495 break;
496
497 case LSM6DSV16BX_XL_LOW_POWER_4_AVG_MD:
498 *val = LSM6DSV16BX_XL_LOW_POWER_4_AVG_MD;
499 break;
500
501 case LSM6DSV16BX_XL_LOW_POWER_8_AVG_MD:
502 *val = LSM6DSV16BX_XL_LOW_POWER_8_AVG_MD;
503 break;
504
505 case LSM6DSV16BX_XL_NORMAL_MD:
506 *val = LSM6DSV16BX_XL_NORMAL_MD;
507 break;
508
509 default:
510 *val = LSM6DSV16BX_XL_HIGH_PERFORMANCE_MD;
511 break;
512 }
513 return ret;
514 }
515
516 /**
517 * @brief Gyroscope output data rate (ODR) selection.[set]
518 *
519 * @param ctx read / write interface definitions
520 * @param val GY_ODR_OFF, GY_ODR_AT_7Hz5, GY_ODR_AT_15Hz, GY_ODR_AT_30Hz, GY_ODR_AT_60Hz, GY_ODR_AT_120Hz, GY_ODR_AT_240Hz, GY_ODR_AT_480Hz, GY_ODR_AT_960Hz, GY_ODR_AT_1920Hz, GY_ODR_AT_3840Hz, GY_ODR_AT_7680Hz,
521 * @retval interface status (MANDATORY: return 0 -> no Error)
522 *
523 */
lsm6dsv16bx_gy_data_rate_set(stmdev_ctx_t * ctx,lsm6dsv16bx_gy_data_rate_t val)524 int32_t lsm6dsv16bx_gy_data_rate_set(stmdev_ctx_t *ctx,
525 lsm6dsv16bx_gy_data_rate_t val)
526 {
527 lsm6dsv16bx_ctrl2_t ctrl2;
528 int32_t ret;
529
530 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1);
531
532 if (ret == 0)
533 {
534 ctrl2.odr_g = (uint8_t)val & 0xFU;
535 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1);
536 }
537
538 return ret;
539 }
540
541 /**
542 * @brief Gyroscope output data rate (ODR) selection.[get]
543 *
544 * @param ctx read / write interface definitions
545 * @param val GY_ODR_OFF, GY_ODR_AT_7Hz5, GY_ODR_AT_15Hz, GY_ODR_AT_30Hz, GY_ODR_AT_60Hz, GY_ODR_AT_120Hz, GY_ODR_AT_240Hz, GY_ODR_AT_480Hz, GY_ODR_AT_960Hz, GY_ODR_AT_1920Hz, GY_ODR_AT_3840Hz, GY_ODR_AT_7680Hz,
546 * @retval interface status (MANDATORY: return 0 -> no Error)
547 *
548 */
lsm6dsv16bx_gy_data_rate_get(stmdev_ctx_t * ctx,lsm6dsv16bx_gy_data_rate_t * val)549 int32_t lsm6dsv16bx_gy_data_rate_get(stmdev_ctx_t *ctx,
550 lsm6dsv16bx_gy_data_rate_t *val)
551 {
552 lsm6dsv16bx_ctrl2_t ctrl2;
553 int32_t ret;
554
555 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1);
556
557 switch (ctrl2.odr_g)
558 {
559 case LSM6DSV16BX_GY_ODR_OFF:
560 *val = LSM6DSV16BX_GY_ODR_OFF;
561 break;
562
563 case LSM6DSV16BX_GY_ODR_AT_7Hz5:
564 *val = LSM6DSV16BX_GY_ODR_AT_7Hz5;
565 break;
566
567 case LSM6DSV16BX_GY_ODR_AT_15Hz:
568 *val = LSM6DSV16BX_GY_ODR_AT_15Hz;
569 break;
570
571 case LSM6DSV16BX_GY_ODR_AT_30Hz:
572 *val = LSM6DSV16BX_GY_ODR_AT_30Hz;
573 break;
574
575 case LSM6DSV16BX_GY_ODR_AT_60Hz:
576 *val = LSM6DSV16BX_GY_ODR_AT_60Hz;
577 break;
578
579 case LSM6DSV16BX_GY_ODR_AT_120Hz:
580 *val = LSM6DSV16BX_GY_ODR_AT_120Hz;
581 break;
582
583 case LSM6DSV16BX_GY_ODR_AT_240Hz:
584 *val = LSM6DSV16BX_GY_ODR_AT_240Hz;
585 break;
586
587 case LSM6DSV16BX_GY_ODR_AT_480Hz:
588 *val = LSM6DSV16BX_GY_ODR_AT_480Hz;
589 break;
590
591 case LSM6DSV16BX_GY_ODR_AT_960Hz:
592 *val = LSM6DSV16BX_GY_ODR_AT_960Hz;
593 break;
594
595 case LSM6DSV16BX_GY_ODR_AT_1920Hz:
596 *val = LSM6DSV16BX_GY_ODR_AT_1920Hz;
597 break;
598
599 case LSM6DSV16BX_GY_ODR_AT_3840Hz:
600 *val = LSM6DSV16BX_GY_ODR_AT_3840Hz;
601 break;
602
603 case LSM6DSV16BX_GY_ODR_AT_7680Hz:
604 *val = LSM6DSV16BX_GY_ODR_AT_7680Hz;
605 break;
606
607 default:
608 *val = LSM6DSV16BX_GY_ODR_OFF;
609 break;
610 }
611 return ret;
612 }
613
614 /**
615 * @brief Gyroscope operating mode selection.[set]
616 *
617 * @param ctx read / write interface definitions
618 * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURANCY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD,
619 * @retval interface status (MANDATORY: return 0 -> no Error)
620 *
621 */
lsm6dsv16bx_gy_mode_set(stmdev_ctx_t * ctx,lsm6dsv16bx_gy_mode_t val)622 int32_t lsm6dsv16bx_gy_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t val)
623 {
624 lsm6dsv16bx_ctrl2_t ctrl2;
625 int32_t ret;
626
627 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1);
628 if (ret == 0)
629 {
630 ctrl2.op_mode_g = (uint8_t)val & 0x07U;
631 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1);
632 }
633
634 return ret;
635 }
636
637 /**
638 * @brief Gyroscope operating mode selection.[get]
639 *
640 * @param ctx read / write interface definitions
641 * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURANCY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD,
642 * @retval interface status (MANDATORY: return 0 -> no Error)
643 *
644 */
lsm6dsv16bx_gy_mode_get(stmdev_ctx_t * ctx,lsm6dsv16bx_gy_mode_t * val)645 int32_t lsm6dsv16bx_gy_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t *val)
646 {
647 lsm6dsv16bx_ctrl2_t ctrl2;
648 int32_t ret;
649
650 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1);
651 switch (ctrl2.op_mode_g)
652 {
653 case LSM6DSV16BX_GY_HIGH_PERFORMANCE_MD:
654 *val = LSM6DSV16BX_GY_HIGH_PERFORMANCE_MD;
655 break;
656
657 case LSM6DSV16BX_GY_HIGH_ACCURANCY_ODR_MD:
658 *val = LSM6DSV16BX_GY_HIGH_ACCURANCY_ODR_MD;
659 break;
660
661 case LSM6DSV16BX_GY_SLEEP_MD:
662 *val = LSM6DSV16BX_GY_SLEEP_MD;
663 break;
664
665 case LSM6DSV16BX_GY_LOW_POWER_MD:
666 *val = LSM6DSV16BX_GY_LOW_POWER_MD;
667 break;
668
669 default:
670 *val = LSM6DSV16BX_GY_HIGH_PERFORMANCE_MD;
671 break;
672 }
673 return ret;
674 }
675
676 /**
677 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set]
678 *
679 * @param ctx read / write interface definitions
680 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
681 * @retval interface status (MANDATORY: return 0 -> no Error)
682 *
683 */
lsm6dsv16bx_auto_increment_set(stmdev_ctx_t * ctx,uint8_t val)684 int32_t lsm6dsv16bx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
685 {
686 lsm6dsv16bx_ctrl3_t ctrl3;
687 int32_t ret;
688
689 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1);
690 if (ret == 0)
691 {
692 ctrl3.if_inc = val;
693 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1);
694 }
695
696 return ret;
697 }
698
699 /**
700 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get]
701 *
702 * @param ctx read / write interface definitions
703 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
704 * @retval interface status (MANDATORY: return 0 -> no Error)
705 *
706 */
lsm6dsv16bx_auto_increment_get(stmdev_ctx_t * ctx,uint8_t * val)707 int32_t lsm6dsv16bx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
708 {
709 lsm6dsv16bx_ctrl3_t ctrl3;
710 int32_t ret;
711
712 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1);
713 *val = ctrl3.if_inc;
714
715
716 return ret;
717 }
718
719 /**
720 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set]
721 *
722 * @param ctx read / write interface definitions
723 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
724 * @retval interface status (MANDATORY: return 0 -> no Error)
725 *
726 */
lsm6dsv16bx_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)727 int32_t lsm6dsv16bx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
728 {
729 lsm6dsv16bx_ctrl3_t ctrl3;
730 int32_t ret;
731
732 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1);
733
734 if (ret == 0)
735 {
736 ctrl3.bdu = val;
737 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1);
738 }
739
740 return ret;
741 }
742
743 /**
744 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get]
745 *
746 * @param ctx read / write interface definitions
747 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
748 * @retval interface status (MANDATORY: return 0 -> no Error)
749 *
750 */
lsm6dsv16bx_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)751 int32_t lsm6dsv16bx_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
752 {
753 lsm6dsv16bx_ctrl3_t ctrl3;
754 int32_t ret;
755
756 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1);
757 *val = ctrl3.bdu;
758
759 return ret;
760 }
761
762 /**
763 * @brief Enables pulsed data-ready mode (~75 us).[set]
764 *
765 * @param ctx read / write interface definitions
766 * @param val DRDY_LATCHED, DRDY_PULSED,
767 * @retval interface status (MANDATORY: return 0 -> no Error)
768 *
769 */
lsm6dsv16bx_data_ready_mode_set(stmdev_ctx_t * ctx,lsm6dsv16bx_data_ready_mode_t val)770 int32_t lsm6dsv16bx_data_ready_mode_set(stmdev_ctx_t *ctx,
771 lsm6dsv16bx_data_ready_mode_t val)
772 {
773 lsm6dsv16bx_ctrl4_t ctrl4;
774 int32_t ret;
775
776 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
777
778 if (ret == 0)
779 {
780 ctrl4.drdy_pulsed = (uint8_t)val & 0x1U;
781 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
782 }
783
784 return ret;
785 }
786
787 /**
788 * @brief Enables pulsed data-ready mode (~75 us).[get]
789 *
790 * @param ctx read / write interface definitions
791 * @param val DRDY_LATCHED, DRDY_PULSED,
792 * @retval interface status (MANDATORY: return 0 -> no Error)
793 *
794 */
lsm6dsv16bx_data_ready_mode_get(stmdev_ctx_t * ctx,lsm6dsv16bx_data_ready_mode_t * val)795 int32_t lsm6dsv16bx_data_ready_mode_get(stmdev_ctx_t *ctx,
796 lsm6dsv16bx_data_ready_mode_t *val)
797 {
798 lsm6dsv16bx_ctrl4_t ctrl4;
799 int32_t ret;
800
801 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
802
803 switch (ctrl4.drdy_pulsed)
804 {
805 case LSM6DSV16BX_DRDY_LATCHED:
806 *val = LSM6DSV16BX_DRDY_LATCHED;
807 break;
808
809 case LSM6DSV16BX_DRDY_PULSED:
810 *val = LSM6DSV16BX_DRDY_PULSED;
811 break;
812
813 default:
814 *val = LSM6DSV16BX_DRDY_LATCHED;
815 break;
816 }
817 return ret;
818 }
819
820 /**
821 * @brief Gyroscope full-scale selection[set]
822 *
823 * @param ctx read / write interface definitions
824 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
825 * @retval interface status (MANDATORY: return 0 -> no Error)
826 *
827 */
lsm6dsv16bx_gy_full_scale_set(stmdev_ctx_t * ctx,lsm6dsv16bx_gy_full_scale_t val)828 int32_t lsm6dsv16bx_gy_full_scale_set(stmdev_ctx_t *ctx,
829 lsm6dsv16bx_gy_full_scale_t val)
830 {
831 lsm6dsv16bx_ctrl6_t ctrl6;
832 int32_t ret;
833
834 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1);
835
836 if (ret == 0)
837 {
838 ctrl6.fs_g = (uint8_t)val & 0xFU;
839 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1);
840 }
841
842 return ret;
843 }
844
845 /**
846 * @brief Gyroscope full-scale selection[get]
847 *
848 * @param ctx read / write interface definitions
849 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
850 * @retval interface status (MANDATORY: return 0 -> no Error)
851 *
852 */
lsm6dsv16bx_gy_full_scale_get(stmdev_ctx_t * ctx,lsm6dsv16bx_gy_full_scale_t * val)853 int32_t lsm6dsv16bx_gy_full_scale_get(stmdev_ctx_t *ctx,
854 lsm6dsv16bx_gy_full_scale_t *val)
855 {
856 lsm6dsv16bx_ctrl6_t ctrl6;
857 int32_t ret;
858
859 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1);
860
861 switch (ctrl6.fs_g)
862 {
863 case LSM6DSV16BX_125dps:
864 *val = LSM6DSV16BX_125dps;
865 break;
866
867 case LSM6DSV16BX_250dps:
868 *val = LSM6DSV16BX_250dps;
869 break;
870
871 case LSM6DSV16BX_500dps:
872 *val = LSM6DSV16BX_500dps;
873 break;
874
875 case LSM6DSV16BX_1000dps:
876 *val = LSM6DSV16BX_1000dps;
877 break;
878
879 case LSM6DSV16BX_2000dps:
880 *val = LSM6DSV16BX_2000dps;
881 break;
882
883 case LSM6DSV16BX_4000dps:
884 *val = LSM6DSV16BX_4000dps;
885 break;
886
887 default:
888 *val = LSM6DSV16BX_125dps;
889 break;
890 }
891 return ret;
892 }
893
894 /**
895 * @brief Accelerometer full-scale selection.[set]
896 *
897 * @param ctx read / write interface definitions
898 * @param val 2g, 4g, 8g, 16g,
899 * @retval interface status (MANDATORY: return 0 -> no Error)
900 *
901 */
lsm6dsv16bx_xl_full_scale_set(stmdev_ctx_t * ctx,lsm6dsv16bx_xl_full_scale_t val)902 int32_t lsm6dsv16bx_xl_full_scale_set(stmdev_ctx_t *ctx,
903 lsm6dsv16bx_xl_full_scale_t val)
904 {
905 lsm6dsv16bx_ctrl8_t ctrl8;
906 int32_t ret;
907
908 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
909
910 if (ret == 0)
911 {
912 ctrl8.fs_xl = (uint8_t)val & 0x3U;
913 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
914 }
915
916 return ret;
917 }
918
919 /**
920 * @brief Accelerometer full-scale selection.[get]
921 *
922 * @param ctx read / write interface definitions
923 * @param val 2g, 4g, 8g, 16g,
924 * @retval interface status (MANDATORY: return 0 -> no Error)
925 *
926 */
lsm6dsv16bx_xl_full_scale_get(stmdev_ctx_t * ctx,lsm6dsv16bx_xl_full_scale_t * val)927 int32_t lsm6dsv16bx_xl_full_scale_get(stmdev_ctx_t *ctx,
928 lsm6dsv16bx_xl_full_scale_t *val)
929 {
930 lsm6dsv16bx_ctrl8_t ctrl8;
931 int32_t ret;
932
933 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
934
935 switch (ctrl8.fs_xl)
936 {
937 case LSM6DSV16BX_2g:
938 *val = LSM6DSV16BX_2g;
939 break;
940
941 case LSM6DSV16BX_4g:
942 *val = LSM6DSV16BX_4g;
943 break;
944
945 case LSM6DSV16BX_8g:
946 *val = LSM6DSV16BX_8g;
947 break;
948
949 case LSM6DSV16BX_16g:
950 *val = LSM6DSV16BX_16g;
951 break;
952
953 default:
954 *val = LSM6DSV16BX_2g;
955 break;
956 }
957 return ret;
958 }
959
960 /**
961 * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[set]
962 *
963 * @param ctx read / write interface definitions
964 * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.
965 * @retval interface status (MANDATORY: return 0 -> no Error)
966 *
967 */
lsm6dsv16bx_xl_dual_channel_set(stmdev_ctx_t * ctx,uint8_t val)968 int32_t lsm6dsv16bx_xl_dual_channel_set(stmdev_ctx_t *ctx, uint8_t val)
969 {
970 lsm6dsv16bx_ctrl8_t ctrl8;
971 int32_t ret;
972
973 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
974
975 if (ret == 0)
976 {
977 ctrl8.xl_dualc_en = val;
978 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
979 }
980
981 return ret;
982 }
983
984 /**
985 * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[get]
986 *
987 * @param ctx read / write interface definitions
988 * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.
989 * @retval interface status (MANDATORY: return 0 -> no Error)
990 *
991 */
lsm6dsv16bx_xl_dual_channel_get(stmdev_ctx_t * ctx,uint8_t * val)992 int32_t lsm6dsv16bx_xl_dual_channel_get(stmdev_ctx_t *ctx, uint8_t *val)
993 {
994 lsm6dsv16bx_ctrl8_t ctrl8;
995 int32_t ret;
996
997 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
998 *val = ctrl8.xl_dualc_en;
999
1000 return ret;
1001 }
1002
1003 /**
1004 * @brief Accelerometer self-test selection.[set]
1005 *
1006 * @param ctx read / write interface definitions
1007 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1008 * @retval interface status (MANDATORY: return 0 -> no Error)
1009 *
1010 */
lsm6dsv16bx_xl_self_test_set(stmdev_ctx_t * ctx,lsm6dsv16bx_xl_self_test_t val)1011 int32_t lsm6dsv16bx_xl_self_test_set(stmdev_ctx_t *ctx,
1012 lsm6dsv16bx_xl_self_test_t val)
1013 {
1014 lsm6dsv16bx_ctrl10_t ctrl10;
1015 int32_t ret;
1016
1017 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
1018
1019 if (ret == 0)
1020 {
1021 ctrl10.st_xl = (uint8_t)val & 0x3U;
1022 ctrl10.xl_st_offset = ((uint8_t)val & 0x04U) >> 2;
1023 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
1024 }
1025
1026 return ret;
1027 }
1028
1029 /**
1030 * @brief Accelerometer self-test selection.[get]
1031 *
1032 * @param ctx read / write interface definitions
1033 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1034 * @retval interface status (MANDATORY: return 0 -> no Error)
1035 *
1036 */
lsm6dsv16bx_xl_self_test_get(stmdev_ctx_t * ctx,lsm6dsv16bx_xl_self_test_t * val)1037 int32_t lsm6dsv16bx_xl_self_test_get(stmdev_ctx_t *ctx,
1038 lsm6dsv16bx_xl_self_test_t *val)
1039 {
1040 lsm6dsv16bx_ctrl10_t ctrl10;
1041 int32_t ret;
1042
1043 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
1044
1045 //switch (ctrl10.xl_st_offset)
1046 switch (ctrl10.st_xl)
1047 {
1048 case LSM6DSV16BX_XL_ST_DISABLE:
1049 *val = LSM6DSV16BX_XL_ST_DISABLE;
1050 break;
1051
1052 case LSM6DSV16BX_XL_ST_POSITIVE:
1053 *val = LSM6DSV16BX_XL_ST_POSITIVE;
1054 break;
1055
1056 case LSM6DSV16BX_XL_ST_NEGATIVE:
1057 *val = LSM6DSV16BX_XL_ST_NEGATIVE;
1058 break;
1059
1060 default:
1061 *val = LSM6DSV16BX_XL_ST_DISABLE;
1062 break;
1063 }
1064 return ret;
1065 }
1066
1067 /**
1068 * @brief Gyroscope self-test selection.[set]
1069 *
1070 * @param ctx read / write interface definitions
1071 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1072 * @retval interface status (MANDATORY: return 0 -> no Error)
1073 *
1074 */
lsm6dsv16bx_gy_self_test_set(stmdev_ctx_t * ctx,lsm6dsv16bx_gy_self_test_t val)1075 int32_t lsm6dsv16bx_gy_self_test_set(stmdev_ctx_t *ctx,
1076 lsm6dsv16bx_gy_self_test_t val)
1077 {
1078 lsm6dsv16bx_ctrl10_t ctrl10;
1079 int32_t ret;
1080
1081 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
1082
1083 if (ret == 0)
1084 {
1085 ctrl10.st_g = (uint8_t)val & 0x3U;
1086 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
1087 }
1088
1089 return ret;
1090 }
1091
1092 /**
1093 * @brief Gyroscope self-test selection.[get]
1094 *
1095 * @param ctx read / write interface definitions
1096 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1097 * @retval interface status (MANDATORY: return 0 -> no Error)
1098 *
1099 */
lsm6dsv16bx_gy_self_test_get(stmdev_ctx_t * ctx,lsm6dsv16bx_gy_self_test_t * val)1100 int32_t lsm6dsv16bx_gy_self_test_get(stmdev_ctx_t *ctx,
1101 lsm6dsv16bx_gy_self_test_t *val)
1102 {
1103 lsm6dsv16bx_ctrl10_t ctrl10;
1104 int32_t ret;
1105
1106 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
1107
1108 switch (ctrl10.st_g)
1109 {
1110 case LSM6DSV16BX_GY_ST_DISABLE:
1111 *val = LSM6DSV16BX_GY_ST_DISABLE;
1112 break;
1113
1114 case LSM6DSV16BX_GY_ST_POSITIVE:
1115 *val = LSM6DSV16BX_GY_ST_POSITIVE;
1116 break;
1117
1118 case LSM6DSV16BX_GY_ST_NEGATIVE:
1119 *val = LSM6DSV16BX_GY_ST_NEGATIVE;
1120 break;
1121
1122 default:
1123 *val = LSM6DSV16BX_GY_ST_DISABLE;
1124 break;
1125 }
1126 return ret;
1127 }
1128
1129 /**
1130 * @brief Get the status of all the interrupt sources.[get]
1131 *
1132 * @param ctx read / write interface definitions
1133 * @param val Get the status of all the interrupt sources.
1134 * @retval interface status (MANDATORY: return 0 -> no Error)
1135 *
1136 */
lsm6dsv16bx_all_sources_get(stmdev_ctx_t * ctx,lsm6dsv16bx_all_sources_t * val)1137 int32_t lsm6dsv16bx_all_sources_get(stmdev_ctx_t *ctx,
1138 lsm6dsv16bx_all_sources_t *val)
1139 {
1140 lsm6dsv16bx_emb_func_status_mainpage_t emb_func_status_mainpage;
1141 lsm6dsv16bx_emb_func_exec_status_t emb_func_exec_status;
1142 lsm6dsv16bx_fsm_status_mainpage_t fsm_status_mainpage;
1143 lsm6dsv16bx_mlc_status_mainpage_t mlc_status_mainpage;
1144 lsm6dsv16bx_functions_enable_t functions_enable;
1145 lsm6dsv16bx_emb_func_src_t emb_func_src;
1146 lsm6dsv16bx_fifo_status2_t fifo_status2;
1147 lsm6dsv16bx_all_int_src_t all_int_src;
1148 lsm6dsv16bx_wake_up_src_t wake_up_src;
1149 lsm6dsv16bx_status_reg_t status_reg;
1150 lsm6dsv16bx_d6d_src_t d6d_src;
1151 lsm6dsv16bx_tap_src_t tap_src;
1152 uint8_t buff[7];
1153 int32_t ret;
1154
1155 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1156 if (ret == 0)
1157 {
1158 functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE;
1159 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1160 }
1161
1162 if (ret == 0)
1163 {
1164 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_STATUS1, (uint8_t *)&buff, 4);
1165 }
1166 bytecpy((uint8_t *)&fifo_status2, &buff[1]);
1167 bytecpy((uint8_t *)&all_int_src, &buff[2]);
1168 bytecpy((uint8_t *)&status_reg, &buff[3]);
1169
1170 val->fifo_ovr = fifo_status2.fifo_ovr_ia;
1171 val->fifo_bdr = fifo_status2.counter_bdr_ia;
1172 val->fifo_full = fifo_status2.fifo_full_ia;
1173 val->fifo_th = fifo_status2.fifo_wtm_ia;
1174
1175 val->free_fall = all_int_src.ff_ia;
1176 val->wake_up = all_int_src.wu_ia;
1177 val->six_d = all_int_src.d6d_ia;
1178
1179 val->drdy_xl = status_reg.xlda;
1180 val->drdy_gy = status_reg.gda;
1181 val->drdy_temp = status_reg.tda;
1182 val->drdy_ah_qvar = status_reg.ah_qvarda;
1183 val->timestamp = status_reg.timestamp_endcount;
1184
1185 if (ret == 0)
1186 {
1187 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1188 }
1189 if (ret == 0)
1190 {
1191 functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE;
1192 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1193 }
1194
1195 if (ret == 0)
1196 {
1197 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_SRC, (uint8_t *)&buff, 7);
1198 }
1199
1200 if (ret == 0)
1201 {
1202 bytecpy((uint8_t *)&wake_up_src, &buff[0]);
1203 bytecpy((uint8_t *)&tap_src, &buff[1]);
1204 bytecpy((uint8_t *)&d6d_src, &buff[2]);
1205 bytecpy((uint8_t *)&emb_func_status_mainpage, &buff[4]);
1206 bytecpy((uint8_t *)&fsm_status_mainpage, &buff[5]);
1207 bytecpy((uint8_t *)&mlc_status_mainpage, &buff[6]);
1208
1209 val->sleep_change = wake_up_src.sleep_change_ia;
1210 val->wake_up_x = wake_up_src.x_wu;
1211 val->wake_up_y = wake_up_src.y_wu;
1212 val->wake_up_z = wake_up_src.z_wu;
1213 val->sleep_state = wake_up_src.sleep_state;
1214
1215 val->tap_x = tap_src.x_tap;
1216 val->tap_y = tap_src.y_tap;
1217 val->tap_z = tap_src.z_tap;
1218 val->tap_sign = tap_src.tap_sign;
1219 val->double_tap = tap_src.double_tap;
1220 val->single_tap = tap_src.single_tap;
1221
1222 val->six_d_zl = d6d_src.zl;
1223 val->six_d_zh = d6d_src.zh;
1224 val->six_d_yl = d6d_src.yl;
1225 val->six_d_yh = d6d_src.yh;
1226 val->six_d_xl = d6d_src.xl;
1227 val->six_d_xh = d6d_src.xh;
1228
1229 val->step_detector = emb_func_status_mainpage.is_step_det;
1230 val->tilt = emb_func_status_mainpage.is_tilt;
1231 val->sig_mot = emb_func_status_mainpage.is_sigmot;
1232 val->fsm_lc = emb_func_status_mainpage.is_fsm_lc;
1233
1234 val->fsm1 = fsm_status_mainpage.is_fsm1;
1235 val->fsm2 = fsm_status_mainpage.is_fsm2;
1236 val->fsm3 = fsm_status_mainpage.is_fsm3;
1237 val->fsm4 = fsm_status_mainpage.is_fsm4;
1238 val->fsm5 = fsm_status_mainpage.is_fsm5;
1239 val->fsm6 = fsm_status_mainpage.is_fsm6;
1240 val->fsm7 = fsm_status_mainpage.is_fsm7;
1241 val->fsm8 = fsm_status_mainpage.is_fsm8;
1242
1243 val->mlc1 = mlc_status_mainpage.is_mlc1;
1244 val->mlc2 = mlc_status_mainpage.is_mlc2;
1245 val->mlc3 = mlc_status_mainpage.is_mlc3;
1246 val->mlc4 = mlc_status_mainpage.is_mlc4;
1247 }
1248
1249
1250 if (ret == 0)
1251 {
1252 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
1253 }
1254 if (ret == 0)
1255 {
1256 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status, 1);
1257 }
1258 if (ret == 0)
1259 {
1260 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
1261 }
1262
1263 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
1264
1265 val->emb_func_stand_by = emb_func_exec_status.emb_func_endop;
1266 val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr;
1267 val->step_count_inc = emb_func_src.stepcounter_bit_set;
1268 val->step_count_overflow = emb_func_src.step_overflow;
1269 val->step_on_delta_time = emb_func_src.step_count_delta_ia;
1270
1271 val->step_detector = emb_func_src.step_detected;
1272
1273 return ret;
1274 }
1275
lsm6dsv16bx_flag_data_ready_get(stmdev_ctx_t * ctx,lsm6dsv16bx_data_ready_t * val)1276 int32_t lsm6dsv16bx_flag_data_ready_get(stmdev_ctx_t *ctx,
1277 lsm6dsv16bx_data_ready_t *val)
1278 {
1279 lsm6dsv16bx_status_reg_t status;
1280 int32_t ret;
1281
1282 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_STATUS_REG, (uint8_t *)&status, 1);
1283 val->drdy_xl = status.xlda;
1284 val->drdy_gy = status.gda;
1285 val->drdy_temp = status.tda;
1286
1287 return ret;
1288 }
1289
1290 /**
1291 * @brief Temperature data output register[get]
1292 *
1293 * @param ctx read / write interface definitions
1294 * @param val Temperature data output register
1295 * @retval interface status (MANDATORY: return 0 -> no Error)
1296 *
1297 */
lsm6dsv16bx_temperature_raw_get(stmdev_ctx_t * ctx,int16_t * val)1298 int32_t lsm6dsv16bx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1299 {
1300 uint8_t buff[2];
1301 int32_t ret;
1302
1303 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_OUT_TEMP_L, &buff[0], 2);
1304 *val = (int16_t)buff[1];
1305 *val = (*val * 256) + (int16_t)buff[0];
1306
1307 return ret;
1308 }
1309
1310 /**
1311 * @brief Angular rate sensor.[get]
1312 *
1313 * @param ctx read / write interface definitions
1314 * @param val Angular rate sensor.
1315 * @retval interface status (MANDATORY: return 0 -> no Error)
1316 *
1317 */
lsm6dsv16bx_angular_rate_raw_get(stmdev_ctx_t * ctx,int16_t * val)1318 int32_t lsm6dsv16bx_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1319 {
1320 uint8_t buff[6];
1321 int32_t ret;
1322
1323 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_OUTX_L_G, &buff[0], 6);
1324 val[0] = (int16_t)buff[1];
1325 val[0] = (val[0] * 256) + (int16_t)buff[0];
1326 val[1] = (int16_t)buff[3];
1327 val[1] = (val[1] * 256) + (int16_t)buff[2];
1328 val[2] = (int16_t)buff[5];
1329 val[2] = (val[2] * 256) + (int16_t)buff[4];
1330
1331 return ret;
1332 }
1333
1334 /**
1335 * @brief Linear acceleration sensor.[get]
1336 *
1337 * @param ctx read / write interface definitions
1338 * @param val Linear acceleration sensor.
1339 * @retval interface status (MANDATORY: return 0 -> no Error)
1340 *
1341 */
lsm6dsv16bx_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)1342 int32_t lsm6dsv16bx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1343 {
1344 uint8_t buff[6];
1345 int32_t ret;
1346
1347 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_OUTZ_L_A, &buff[0], 6);
1348 val[2] = (int16_t)buff[1];
1349 val[2] = (val[2] * 256) + (int16_t)buff[0];
1350 val[1] = (int16_t)buff[3];
1351 val[1] = (val[1] * 256) + (int16_t)buff[2];
1352 val[0] = (int16_t)buff[5];
1353 val[0] = (val[0] * 256) + (int16_t)buff[4];
1354
1355 return ret;
1356 }
1357
1358 /**
1359 * @brief Linear acceleration sensor for Dual channel mode.[get]
1360 *
1361 * @param ctx read / write interface definitions
1362 * @param val Linear acceleration sensor or Dual channel mode.
1363 * @retval interface status (MANDATORY: return 0 -> no Error)
1364 *
1365 */
lsm6dsv16bx_dual_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)1366 int32_t lsm6dsv16bx_dual_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1367 {
1368 uint8_t buff[6];
1369 int32_t ret;
1370
1371 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_UI_OUTZ_L_A_OIS_DUALC, &buff[0], 6);
1372 val[2] = (int16_t)buff[1];
1373 val[2] = (val[2] * 256) + (int16_t)buff[0];
1374 val[1] = (int16_t)buff[3];
1375 val[1] = (val[1] * 256) + (int16_t)buff[2];
1376 val[0] = (int16_t)buff[5];
1377 val[0] = (val[0] * 256) + (int16_t)buff[4];
1378
1379 return ret;
1380 }
1381
1382 /**
1383 * @brief Qvar data output register.[get]
1384 *
1385 * @param ctx read / write interface definitions
1386 * @param val Qvar data output register.
1387 * @retval interface status (MANDATORY: return 0 -> no Error)
1388 *
1389 */
lsm6dsv16bx_ah_qvar_raw_get(stmdev_ctx_t * ctx,int16_t * val)1390 int32_t lsm6dsv16bx_ah_qvar_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1391 {
1392 uint8_t buff[2];
1393 int32_t ret;
1394
1395 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_AH_QVAR_OUT_L, &buff[0], 2);
1396 *val = (int16_t)buff[1];
1397 *val = (*val * 256) + (int16_t)buff[0];
1398
1399 return ret;
1400 }
1401
1402 /**
1403 * @brief Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.[get]
1404 *
1405 * @param ctx read / write interface definitions
1406 * @param val Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.
1407 * @retval interface status (MANDATORY: return 0 -> no Error)
1408 *
1409 */
lsm6dsv16bx_odr_cal_reg_get(stmdev_ctx_t * ctx,int8_t * val)1410 int32_t lsm6dsv16bx_odr_cal_reg_get(stmdev_ctx_t *ctx, int8_t *val)
1411 {
1412 lsm6dsv16bx_internal_freq_t internal_freq;
1413 int32_t ret;
1414
1415 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1);
1416 *val = (int8_t)internal_freq.freq_fine;
1417
1418 return ret;
1419 }
1420
1421 /**
1422 * @brief Enable accelerometer axis.[set]
1423 *
1424 * @param ctx read / write interface definitions
1425 * @param val Enable accelerometer axis.
1426 * @retval interface status (MANDATORY: return 0 -> no Error)
1427 *
1428 */
lsm6dsv16bx_xl_axis_set(stmdev_ctx_t * ctx,lsm6dsv16bx_xl_axis_t val)1429 int32_t lsm6dsv16bx_xl_axis_set(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_axis_t val)
1430 {
1431 lsm6dsv16bx_tdm_cfg1_t tdm_cfg1;
1432 int32_t ret;
1433
1434 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
1435 if (ret == 0)
1436 {
1437 tdm_cfg1.tdm_xl_z_en = val.z;
1438 tdm_cfg1.tdm_xl_y_en = val.y;
1439 tdm_cfg1.tdm_xl_x_en = val.x;
1440 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
1441 }
1442
1443 return ret;
1444 }
1445
1446 /**
1447 * @brief Enable accelerometer axis.[get]
1448 *
1449 * @param ctx read / write interface definitions
1450 * @param val Enable accelerometer axis.
1451 * @retval interface status (MANDATORY: return 0 -> no Error)
1452 *
1453 */
lsm6dsv16bx_xl_axis_get(stmdev_ctx_t * ctx,lsm6dsv16bx_xl_axis_t * val)1454 int32_t lsm6dsv16bx_xl_axis_get(stmdev_ctx_t *ctx, lsm6dsv16bx_xl_axis_t *val)
1455 {
1456 lsm6dsv16bx_tdm_cfg1_t tdm_cfg1;
1457 int32_t ret;
1458
1459 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
1460 val->x = tdm_cfg1.tdm_xl_x_en;
1461 val->y = tdm_cfg1.tdm_xl_y_en;
1462 val->z = tdm_cfg1.tdm_xl_z_en;
1463
1464 return ret;
1465 }
1466
1467 /**
1468 * @brief Write buffer in a page.[set]
1469 *
1470 * @param ctx read / write interface definitions
1471 * @param val Write buffer in a page.
1472 * @retval interface status (MANDATORY: return 0 -> no Error)
1473 *
1474 */
lsm6dsv16bx_ln_pg_write(stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1475 int32_t lsm6dsv16bx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
1476 uint8_t *buf, uint8_t len)
1477 {
1478 lsm6dsv16bx_page_address_t page_address;
1479 lsm6dsv16bx_page_sel_t page_sel;
1480 lsm6dsv16bx_page_rw_t page_rw;
1481 uint8_t msb;
1482 uint8_t lsb;
1483 int32_t ret;
1484 uint8_t i ;
1485
1486 msb = ((uint8_t)(address >> 8) & 0x0FU);
1487 lsb = (uint8_t)address & 0xFFU;
1488
1489 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
1490
1491 /* set page write */
1492 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1493 page_rw.page_read = PROPERTY_DISABLE;
1494 page_rw.page_write = PROPERTY_ENABLE;
1495 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1496
1497 /* select page */
1498 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, 1);
1499 page_sel.page_sel = msb;
1500 page_sel.not_used0 = 1; // Default value
1501 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel,
1502 1);
1503
1504 /* set page addr */
1505 page_address.page_addr = lsb;
1506 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_ADDRESS,
1507 (uint8_t *)&page_address, 1);
1508
1509 for (i = 0; ((i < len) && (ret == 0)); i++)
1510 {
1511 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_VALUE, &buf[i], 1);
1512 lsb++;
1513
1514 /* Check if page wrap */
1515 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
1516 {
1517 msb++;
1518 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, 1);
1519
1520 if (ret == 0)
1521 {
1522 page_sel.page_sel = msb;
1523 page_sel.not_used0 = 1; // Default value
1524 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel,
1525 1);
1526 }
1527 }
1528 }
1529
1530 page_sel.page_sel = 0;
1531 page_sel.not_used0 = 1;// Default value
1532 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel,
1533 1);
1534
1535 /* unset page write */
1536 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1537 page_rw.page_read = PROPERTY_DISABLE;
1538 page_rw.page_write = PROPERTY_DISABLE;
1539 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1540
1541 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
1542
1543 return ret;
1544 }
1545
1546 /**
1547 * @brief Read buffer in a page.[set]
1548 *
1549 * @param ctx read / write interface definitions
1550 * @param val Write buffer in a page.
1551 * @retval interface status (MANDATORY: return 0 -> no Error)
1552 *
1553 */
lsm6dsv16bx_ln_pg_read(stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1554 int32_t lsm6dsv16bx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address,
1555 uint8_t *buf, uint8_t len)
1556 {
1557 lsm6dsv16bx_page_address_t page_address;
1558 lsm6dsv16bx_page_sel_t page_sel;
1559 lsm6dsv16bx_page_rw_t page_rw;
1560 uint8_t msb;
1561 uint8_t lsb;
1562 int32_t ret;
1563 uint8_t i ;
1564
1565 msb = ((uint8_t)(address >> 8) & 0x0FU);
1566 lsb = (uint8_t)address & 0xFFU;
1567
1568 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
1569
1570 /* set page write */
1571 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1572 page_rw.page_read = PROPERTY_ENABLE;
1573 page_rw.page_write = PROPERTY_DISABLE;
1574 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1575
1576 /* select page */
1577 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, 1);
1578 page_sel.page_sel = msb;
1579 page_sel.not_used0 = 1; // Default value
1580 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel,
1581 1);
1582
1583 /* set page addr */
1584 page_address.page_addr = lsb;
1585 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_ADDRESS,
1586 (uint8_t *)&page_address, 1);
1587
1588 for (i = 0; ((i < len) && (ret == 0)); i++)
1589 {
1590 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_VALUE, &buf[i], 1);
1591 lsb++;
1592
1593 /* Check if page wrap */
1594 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
1595 {
1596 msb++;
1597 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, 1);
1598
1599 if (ret == 0)
1600 {
1601 page_sel.page_sel = msb;
1602 page_sel.not_used0 = 1; // Default value
1603 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel,
1604 1);
1605 }
1606 }
1607 }
1608
1609 page_sel.page_sel = 0;
1610 page_sel.not_used0 = 1;// Default value
1611 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel,
1612 1);
1613
1614 /* unset page write */
1615 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1616 page_rw.page_read = PROPERTY_DISABLE;
1617 page_rw.page_write = PROPERTY_DISABLE;
1618 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1619
1620 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
1621
1622 return ret;
1623 }
1624
1625 /**
1626 * @}
1627 *
1628 */
1629
1630 /**
1631 * @defgroup Timestamp
1632 * @brief This section groups all the functions that manage the
1633 * timestamp generation.
1634 * @{
1635 *
1636 */
1637
1638 /**
1639 * @brief Enables timestamp counter.[set]
1640 *
1641 * @param ctx read / write interface definitions
1642 * @param val Enables timestamp counter.
1643 * @retval interface status (MANDATORY: return 0 -> no Error)
1644 *
1645 */
lsm6dsv16bx_timestamp_set(stmdev_ctx_t * ctx,uint8_t val)1646 int32_t lsm6dsv16bx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
1647 {
1648 lsm6dsv16bx_functions_enable_t functions_enable;
1649 int32_t ret;
1650
1651 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1652 if (ret == 0)
1653 {
1654 functions_enable.timestamp_en = val;
1655 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1656 }
1657
1658 return ret;
1659 }
1660
1661 /**
1662 * @brief Enables timestamp counter.[get]
1663 *
1664 * @param ctx read / write interface definitions
1665 * @param val Enables timestamp counter.
1666 * @retval interface status (MANDATORY: return 0 -> no Error)
1667 *
1668 */
lsm6dsv16bx_timestamp_get(stmdev_ctx_t * ctx,uint8_t * val)1669 int32_t lsm6dsv16bx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
1670 {
1671 lsm6dsv16bx_functions_enable_t functions_enable;
1672 int32_t ret;
1673
1674 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1675 *val = functions_enable.timestamp_en;
1676
1677 return ret;
1678 }
1679
1680 /**
1681 * @brief Timestamp data output.[get]
1682 *
1683 * @param ctx read / write interface definitions
1684 * @param val Timestamp data output.
1685 * @retval interface status (MANDATORY: return 0 -> no Error)
1686 *
1687 */
lsm6dsv16bx_timestamp_raw_get(stmdev_ctx_t * ctx,uint32_t * val)1688 int32_t lsm6dsv16bx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
1689 {
1690 uint8_t buff[4];
1691 int32_t ret;
1692
1693 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TIMESTAMP0, &buff[0], 4);
1694 *val = buff[3];
1695 *val = (*val * 256U) + buff[2];
1696 *val = (*val * 256U) + buff[1];
1697 *val = (*val * 256U) + buff[0];
1698
1699 return ret;
1700 }
1701
1702 /**
1703 * @}
1704 *
1705 */
1706
1707 /**
1708 * @defgroup Filters
1709 * @brief This section group all the functions concerning the
1710 * filters configuration
1711 * @{
1712 *
1713 */
1714
1715 /**
1716 * @brief Protocol anti-spike filters.[set]
1717 *
1718 * @param ctx read / write interface definitions
1719 * @param val AUTO, ALWAYS_ACTIVE,
1720 * @retval interface status (MANDATORY: return 0 -> no Error)
1721 *
1722 */
lsm6dsv16bx_filt_anti_spike_set(stmdev_ctx_t * ctx,lsm6dsv16bx_filt_anti_spike_t val)1723 int32_t lsm6dsv16bx_filt_anti_spike_set(stmdev_ctx_t *ctx,
1724 lsm6dsv16bx_filt_anti_spike_t val)
1725 {
1726 lsm6dsv16bx_if_cfg_t if_cfg;
1727 int32_t ret;
1728
1729 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
1730
1731 if (ret == 0)
1732 {
1733 if_cfg.asf_ctrl = (uint8_t)val & 0x01U;
1734 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
1735 }
1736
1737 return ret;
1738 }
1739
1740 /**
1741 * @brief Protocol anti-spike filters.[get]
1742 *
1743 * @param ctx read / write interface definitions
1744 * @param val AUTO, ALWAYS_ACTIVE,
1745 * @retval interface status (MANDATORY: return 0 -> no Error)
1746 *
1747 */
lsm6dsv16bx_filt_anti_spike_get(stmdev_ctx_t * ctx,lsm6dsv16bx_filt_anti_spike_t * val)1748 int32_t lsm6dsv16bx_filt_anti_spike_get(stmdev_ctx_t *ctx,
1749 lsm6dsv16bx_filt_anti_spike_t *val)
1750 {
1751 lsm6dsv16bx_if_cfg_t if_cfg;
1752 int32_t ret;
1753
1754 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
1755 switch (if_cfg.asf_ctrl)
1756 {
1757 case LSM6DSV16BX_AUTO:
1758 *val = LSM6DSV16BX_AUTO;
1759 break;
1760
1761 case LSM6DSV16BX_ALWAYS_ACTIVE:
1762 *val = LSM6DSV16BX_ALWAYS_ACTIVE;
1763 break;
1764
1765 default:
1766 *val = LSM6DSV16BX_AUTO;
1767 break;
1768 }
1769 return ret;
1770 }
1771
1772 /**
1773 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set]
1774 *
1775 * @param ctx read / write interface definitions
1776 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
1777 * @retval interface status (MANDATORY: return 0 -> no Error)
1778 *
1779 */
lsm6dsv16bx_filt_settling_mask_set(stmdev_ctx_t * ctx,lsm6dsv16bx_filt_settling_mask_t val)1780 int32_t lsm6dsv16bx_filt_settling_mask_set(stmdev_ctx_t *ctx,
1781 lsm6dsv16bx_filt_settling_mask_t val)
1782 {
1783 lsm6dsv16bx_emb_func_cfg_t emb_func_cfg;
1784 lsm6dsv16bx_tdm_cfg2_t tdm_cfg2;
1785 lsm6dsv16bx_ctrl4_t ctrl4;
1786 int32_t ret;
1787
1788 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
1789
1790 if (ret == 0)
1791 {
1792 ctrl4.drdy_mask = val.drdy;
1793
1794 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
1795 }
1796
1797 if (ret == 0)
1798 {
1799 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
1800 }
1801
1802 if (ret == 0)
1803 {
1804 emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl;
1805 emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g;
1806 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
1807 }
1808
1809 if (ret == 0)
1810 {
1811 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
1812 }
1813
1814 if (ret == 0)
1815 {
1816 tdm_cfg2.tdm_data_mask = val.tdm_excep_code;
1817 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
1818 }
1819
1820 return ret;
1821 }
1822
1823 /**
1824 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get]
1825 *
1826 * @param ctx read / write interface definitions
1827 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
1828 * @retval interface status (MANDATORY: return 0 -> no Error)
1829 *
1830 */
lsm6dsv16bx_filt_settling_mask_get(stmdev_ctx_t * ctx,lsm6dsv16bx_filt_settling_mask_t * val)1831 int32_t lsm6dsv16bx_filt_settling_mask_get(stmdev_ctx_t *ctx,
1832 lsm6dsv16bx_filt_settling_mask_t *val)
1833 {
1834 lsm6dsv16bx_emb_func_cfg_t emb_func_cfg;
1835 lsm6dsv16bx_tdm_cfg2_t tdm_cfg2;
1836 lsm6dsv16bx_ctrl4_t ctrl4;
1837 int32_t ret;
1838
1839 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
1840 if (ret == 0)
1841 {
1842 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
1843 }
1844 if (ret == 0)
1845 {
1846 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
1847 }
1848
1849 val->drdy = ctrl4.drdy_mask;
1850 val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl;
1851 val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl;
1852 val->tdm_excep_code = tdm_cfg2.tdm_data_mask;
1853
1854 return ret;
1855 }
1856
1857 /**
1858 * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[set]
1859 *
1860 * @param ctx read / write interface definitions
1861 * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME,
1862 * @retval interface status (MANDATORY: return 0 -> no Error)
1863 *
1864 */
lsm6dsv16bx_filt_gy_lp1_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsv16bx_filt_gy_lp1_bandwidth_t val)1865 int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
1866 lsm6dsv16bx_filt_gy_lp1_bandwidth_t val)
1867 {
1868 lsm6dsv16bx_ctrl6_t ctrl6;
1869 int32_t ret;
1870
1871 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1);
1872 if (ret == 0)
1873 {
1874 ctrl6.lpf1_g_bw = (uint8_t)val & 0x7U;
1875 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1);
1876 }
1877
1878 return ret;
1879 }
1880
1881 /**
1882 * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[get]
1883 *
1884 * @param ctx read / write interface definitions
1885 * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME,
1886 * @retval interface status (MANDATORY: return 0 -> no Error)
1887 *
1888 */
lsm6dsv16bx_filt_gy_lp1_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsv16bx_filt_gy_lp1_bandwidth_t * val)1889 int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
1890 lsm6dsv16bx_filt_gy_lp1_bandwidth_t *val)
1891 {
1892 lsm6dsv16bx_ctrl6_t ctrl6;
1893 int32_t ret;
1894
1895 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1);
1896
1897 switch (ctrl6.lpf1_g_bw)
1898 {
1899 case LSM6DSV16BX_GY_ULTRA_LIGHT:
1900 *val = LSM6DSV16BX_GY_ULTRA_LIGHT;
1901 break;
1902
1903 case LSM6DSV16BX_GY_VERY_LIGHT:
1904 *val = LSM6DSV16BX_GY_VERY_LIGHT;
1905 break;
1906
1907 case LSM6DSV16BX_GY_LIGHT:
1908 *val = LSM6DSV16BX_GY_LIGHT;
1909 break;
1910
1911 case LSM6DSV16BX_GY_MEDIUM:
1912 *val = LSM6DSV16BX_GY_MEDIUM;
1913 break;
1914
1915 case LSM6DSV16BX_GY_STRONG:
1916 *val = LSM6DSV16BX_GY_STRONG;
1917 break;
1918
1919 case LSM6DSV16BX_GY_VERY_STRONG:
1920 *val = LSM6DSV16BX_GY_VERY_STRONG;
1921 break;
1922
1923 case LSM6DSV16BX_GY_AGGRESSIVE:
1924 *val = LSM6DSV16BX_GY_AGGRESSIVE;
1925 break;
1926
1927 case LSM6DSV16BX_GY_XTREME:
1928 *val = LSM6DSV16BX_GY_XTREME;
1929 break;
1930
1931 default:
1932 *val = LSM6DSV16BX_GY_ULTRA_LIGHT;
1933 break;
1934 }
1935 return ret;
1936 }
1937
1938 /**
1939 * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[set]
1940 *
1941 * @param ctx read / write interface definitions
1942 * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.
1943 * @retval interface status (MANDATORY: return 0 -> no Error)
1944 *
1945 */
lsm6dsv16bx_filt_gy_lp1_set(stmdev_ctx_t * ctx,uint8_t val)1946 int32_t lsm6dsv16bx_filt_gy_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
1947 {
1948 lsm6dsv16bx_ctrl7_t ctrl7;
1949 int32_t ret;
1950
1951 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
1952
1953 if (ret == 0)
1954 {
1955 ctrl7.lpf1_g_en = val;
1956 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
1957 }
1958
1959 return ret;
1960 }
1961
1962 /**
1963 * @brief It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.[get]
1964 *
1965 * @param ctx read / write interface definitions
1966 * @param val It enables gyroscope digital LPF1 filter. If the OIS chain is disabled, the bandwidth can be selected through LPF1_G_BW.
1967 * @retval interface status (MANDATORY: return 0 -> no Error)
1968 *
1969 */
lsm6dsv16bx_filt_gy_lp1_get(stmdev_ctx_t * ctx,uint8_t * val)1970 int32_t lsm6dsv16bx_filt_gy_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
1971 {
1972 lsm6dsv16bx_ctrl7_t ctrl7;
1973 int32_t ret;
1974
1975 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
1976 *val = ctrl7.lpf1_g_en;
1977
1978 return ret;
1979 }
1980
1981 /**
1982 * @brief Qvar filter configuration.[set]
1983 *
1984 * @param ctx read / write interface definitions
1985 * @param val Qvar filter configuration.
1986 * @retval interface status (MANDATORY: return 0 -> no Error)
1987 *
1988 */
lsm6dsv16bx_filt_ah_qvar_conf_set(stmdev_ctx_t * ctx,lsm6dsv16bx_filt_ah_qvar_conf_t val)1989 int32_t lsm6dsv16bx_filt_ah_qvar_conf_set(stmdev_ctx_t *ctx,
1990 lsm6dsv16bx_filt_ah_qvar_conf_t val)
1991 {
1992 lsm6dsv16bx_ctrl9_t ctrl9;
1993 lsm6dsv16bx_ctrl8_t ctrl8;
1994 int32_t ret;
1995
1996 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
1997 if (ret == 0)
1998 {
1999 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2000 }
2001
2002 ctrl8.ah_qvar_hpf = val.hpf;
2003 ctrl9.ah_qvar_lpf = val.lpf;
2004
2005 if (ret == 0)
2006 {
2007 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
2008 }
2009 if (ret == 0)
2010 {
2011 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2012 }
2013
2014 return ret;
2015 }
2016
2017 /**
2018 * @brief Qvar filter configuration.[get]
2019 *
2020 * @param ctx read / write interface definitions
2021 * @param val Qvar filter configuration.
2022 * @retval interface status (MANDATORY: return 0 -> no Error)
2023 *
2024 */
lsm6dsv16bx_filt_ah_qvar_conf_get(stmdev_ctx_t * ctx,lsm6dsv16bx_filt_ah_qvar_conf_t * val)2025 int32_t lsm6dsv16bx_filt_ah_qvar_conf_get(stmdev_ctx_t *ctx,
2026 lsm6dsv16bx_filt_ah_qvar_conf_t *val)
2027 {
2028 lsm6dsv16bx_ctrl8_t ctrl8;
2029 lsm6dsv16bx_ctrl9_t ctrl9;
2030 int32_t ret;
2031
2032 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
2033 if (ret == 0)
2034 {
2035 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2036 }
2037
2038 val->lpf = ctrl9.ah_qvar_lpf;
2039 val->hpf = ctrl8.ah_qvar_hpf;
2040
2041 return ret;
2042 }
2043
2044 /**
2045 * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[set]
2046 *
2047 * @param ctx read / write interface definitions
2048 * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME,
2049 * @retval interface status (MANDATORY: return 0 -> no Error)
2050 *
2051 */
lsm6dsv16bx_filt_xl_lp2_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsv16bx_filt_xl_lp2_bandwidth_t val)2052 int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx,
2053 lsm6dsv16bx_filt_xl_lp2_bandwidth_t val)
2054 {
2055 lsm6dsv16bx_ctrl8_t ctrl8;
2056 int32_t ret;
2057
2058 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
2059 if (ret == 0)
2060 {
2061 ctrl8.hp_lpf2_xl_bw = (uint8_t)val & 0x7U;
2062 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
2063 }
2064
2065 return ret;
2066 }
2067
2068 /**
2069 * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[get]
2070 *
2071 * @param ctx read / write interface definitions
2072 * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME,
2073 * @retval interface status (MANDATORY: return 0 -> no Error)
2074 *
2075 */
lsm6dsv16bx_filt_xl_lp2_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsv16bx_filt_xl_lp2_bandwidth_t * val)2076 int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx,
2077 lsm6dsv16bx_filt_xl_lp2_bandwidth_t *val)
2078 {
2079 lsm6dsv16bx_ctrl8_t ctrl8;
2080 int32_t ret;
2081
2082 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
2083 switch (ctrl8.hp_lpf2_xl_bw)
2084 {
2085 case LSM6DSV16BX_XL_ULTRA_LIGHT:
2086 *val = LSM6DSV16BX_XL_ULTRA_LIGHT;
2087 break;
2088
2089 case LSM6DSV16BX_XL_VERY_LIGHT:
2090 *val = LSM6DSV16BX_XL_VERY_LIGHT;
2091 break;
2092
2093 case LSM6DSV16BX_XL_LIGHT:
2094 *val = LSM6DSV16BX_XL_LIGHT;
2095 break;
2096
2097 case LSM6DSV16BX_XL_MEDIUM:
2098 *val = LSM6DSV16BX_XL_MEDIUM;
2099 break;
2100
2101 case LSM6DSV16BX_XL_STRONG:
2102 *val = LSM6DSV16BX_XL_STRONG;
2103 break;
2104
2105 case LSM6DSV16BX_XL_VERY_STRONG:
2106 *val = LSM6DSV16BX_XL_VERY_STRONG;
2107 break;
2108
2109 case LSM6DSV16BX_XL_AGGRESSIVE:
2110 *val = LSM6DSV16BX_XL_AGGRESSIVE;
2111 break;
2112
2113 case LSM6DSV16BX_XL_XTREME:
2114 *val = LSM6DSV16BX_XL_XTREME;
2115 break;
2116
2117 default:
2118 *val = LSM6DSV16BX_XL_ULTRA_LIGHT;
2119 break;
2120 }
2121 return ret;
2122 }
2123
2124 /**
2125 * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[set]
2126 *
2127 * @param ctx read / write interface definitions
2128 * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.
2129 * @retval interface status (MANDATORY: return 0 -> no Error)
2130 *
2131 */
lsm6dsv16bx_filt_xl_lp2_set(stmdev_ctx_t * ctx,uint8_t val)2132 int32_t lsm6dsv16bx_filt_xl_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
2133 {
2134 lsm6dsv16bx_ctrl9_t ctrl9;
2135 int32_t ret;
2136
2137 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2138 if (ret == 0)
2139 {
2140 ctrl9.lpf2_xl_en = val;
2141 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2142 }
2143
2144 return ret;
2145 }
2146
2147 /**
2148 * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[get]
2149 *
2150 * @param ctx read / write interface definitions
2151 * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.
2152 * @retval interface status (MANDATORY: return 0 -> no Error)
2153 *
2154 */
lsm6dsv16bx_filt_xl_lp2_get(stmdev_ctx_t * ctx,uint8_t * val)2155 int32_t lsm6dsv16bx_filt_xl_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
2156 {
2157 lsm6dsv16bx_ctrl9_t ctrl9;
2158 int32_t ret;
2159
2160 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2161 *val = ctrl9.lpf2_xl_en;
2162
2163 return ret;
2164 }
2165
2166 /**
2167 * @brief Accelerometer slope filter / high-pass filter selection.[set]
2168 *
2169 * @param ctx read / write interface definitions
2170 * @param val Accelerometer slope filter / high-pass filter selection.
2171 * @retval interface status (MANDATORY: return 0 -> no Error)
2172 *
2173 */
lsm6dsv16bx_filt_xl_hp_set(stmdev_ctx_t * ctx,uint8_t val)2174 int32_t lsm6dsv16bx_filt_xl_hp_set(stmdev_ctx_t *ctx, uint8_t val)
2175 {
2176 lsm6dsv16bx_ctrl9_t ctrl9;
2177 int32_t ret;
2178
2179 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2180 if (ret == 0)
2181 {
2182 ctrl9.hp_slope_xl_en = val;
2183 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2184 }
2185
2186 return ret;
2187 }
2188
2189 /**
2190 * @brief Accelerometer slope filter / high-pass filter selection.[get]
2191 *
2192 * @param ctx read / write interface definitions
2193 * @param val Accelerometer slope filter / high-pass filter selection.
2194 * @retval interface status (MANDATORY: return 0 -> no Error)
2195 *
2196 */
lsm6dsv16bx_filt_xl_hp_get(stmdev_ctx_t * ctx,uint8_t * val)2197 int32_t lsm6dsv16bx_filt_xl_hp_get(stmdev_ctx_t *ctx, uint8_t *val)
2198 {
2199 lsm6dsv16bx_ctrl9_t ctrl9;
2200 int32_t ret;
2201
2202 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2203 *val = ctrl9.hp_slope_xl_en;
2204
2205 return ret;
2206 }
2207
2208 /**
2209 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[set]
2210 *
2211 * @param ctx read / write interface definitions
2212 * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.
2213 * @retval interface status (MANDATORY: return 0 -> no Error)
2214 *
2215 */
lsm6dsv16bx_filt_xl_fast_settling_set(stmdev_ctx_t * ctx,uint8_t val)2216 int32_t lsm6dsv16bx_filt_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
2217 {
2218 lsm6dsv16bx_ctrl9_t ctrl9;
2219 int32_t ret;
2220
2221 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2222 if (ret == 0)
2223 {
2224 ctrl9.xl_fastsettl_mode = val;
2225 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2226 }
2227
2228 return ret;
2229 }
2230
2231 /**
2232 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[get]
2233 *
2234 * @param ctx read / write interface definitions
2235 * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.
2236 * @retval interface status (MANDATORY: return 0 -> no Error)
2237 *
2238 */
lsm6dsv16bx_filt_xl_fast_settling_get(stmdev_ctx_t * ctx,uint8_t * val)2239 int32_t lsm6dsv16bx_filt_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
2240 {
2241 lsm6dsv16bx_ctrl9_t ctrl9;
2242 int32_t ret;
2243
2244 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2245 *val = ctrl9.xl_fastsettl_mode;
2246
2247 return ret;
2248 }
2249
2250 /**
2251 * @brief Accelerometer high-pass filter mode.[set]
2252 *
2253 * @param ctx read / write interface definitions
2254 * @param val HP_MD_NORMAL, HP_MD_REFERENCE,
2255 * @retval interface status (MANDATORY: return 0 -> no Error)
2256 *
2257 */
lsm6dsv16bx_filt_xl_hp_mode_set(stmdev_ctx_t * ctx,lsm6dsv16bx_filt_xl_hp_mode_t val)2258 int32_t lsm6dsv16bx_filt_xl_hp_mode_set(stmdev_ctx_t *ctx,
2259 lsm6dsv16bx_filt_xl_hp_mode_t val)
2260 {
2261 lsm6dsv16bx_ctrl9_t ctrl9;
2262 int32_t ret;
2263
2264 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2265 if (ret == 0)
2266 {
2267 ctrl9.hp_ref_mode_xl = (uint8_t)val & 0x01U;
2268 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2269 }
2270
2271 return ret;
2272 }
2273
2274 /**
2275 * @brief Accelerometer high-pass filter mode.[get]
2276 *
2277 * @param ctx read / write interface definitions
2278 * @param val HP_MD_NORMAL, HP_MD_REFERENCE,
2279 * @retval interface status (MANDATORY: return 0 -> no Error)
2280 *
2281 */
lsm6dsv16bx_filt_xl_hp_mode_get(stmdev_ctx_t * ctx,lsm6dsv16bx_filt_xl_hp_mode_t * val)2282 int32_t lsm6dsv16bx_filt_xl_hp_mode_get(stmdev_ctx_t *ctx,
2283 lsm6dsv16bx_filt_xl_hp_mode_t *val)
2284 {
2285 lsm6dsv16bx_ctrl9_t ctrl9;
2286 int32_t ret;
2287
2288 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2289 switch (ctrl9.hp_ref_mode_xl)
2290 {
2291 case LSM6DSV16BX_HP_MD_NORMAL:
2292 *val = LSM6DSV16BX_HP_MD_NORMAL;
2293 break;
2294
2295 case LSM6DSV16BX_HP_MD_REFERENCE:
2296 *val = LSM6DSV16BX_HP_MD_REFERENCE;
2297 break;
2298
2299 default:
2300 *val = LSM6DSV16BX_HP_MD_NORMAL;
2301 break;
2302 }
2303 return ret;
2304 }
2305
2306 /**
2307 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[set]
2308 *
2309 * @param ctx read / write interface definitions
2310 * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS,
2311 * @retval interface status (MANDATORY: return 0 -> no Error)
2312 *
2313 */
lsm6dsv16bx_filt_wkup_act_feed_set(stmdev_ctx_t * ctx,lsm6dsv16bx_filt_wkup_act_feed_t val)2314 int32_t lsm6dsv16bx_filt_wkup_act_feed_set(stmdev_ctx_t *ctx,
2315 lsm6dsv16bx_filt_wkup_act_feed_t val)
2316 {
2317 lsm6dsv16bx_wake_up_ths_t wake_up_ths;
2318 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
2319 int32_t ret;
2320
2321 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2322 if (ret == 0)
2323 {
2324 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
2325 }
2326
2327 tap_cfg0.slope_fds = (uint8_t)val & 0x01U;
2328 wake_up_ths.usr_off_on_wu = ((uint8_t)val & 0x02U) >> 1;
2329
2330 if (ret == 0)
2331 {
2332
2333 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2334 }
2335 if (ret == 0)
2336 {
2337
2338 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
2339 }
2340
2341 return ret;
2342 }
2343
2344 /**
2345 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[get]
2346 *
2347 * @param ctx read / write interface definitions
2348 * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS,
2349 * @retval interface status (MANDATORY: return 0 -> no Error)
2350 *
2351 */
lsm6dsv16bx_filt_wkup_act_feed_get(stmdev_ctx_t * ctx,lsm6dsv16bx_filt_wkup_act_feed_t * val)2352 int32_t lsm6dsv16bx_filt_wkup_act_feed_get(stmdev_ctx_t *ctx,
2353 lsm6dsv16bx_filt_wkup_act_feed_t *val)
2354 {
2355 lsm6dsv16bx_wake_up_ths_t wake_up_ths;
2356 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
2357 int32_t ret;
2358
2359 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
2360 if (ret == 0)
2361 {
2362 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2363 }
2364
2365 switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds)
2366 {
2367 case LSM6DSV16BX_WK_FEED_SLOPE:
2368 *val = LSM6DSV16BX_WK_FEED_SLOPE;
2369 break;
2370
2371 case LSM6DSV16BX_WK_FEED_HIGH_PASS:
2372 *val = LSM6DSV16BX_WK_FEED_HIGH_PASS;
2373 break;
2374
2375 case LSM6DSV16BX_WK_FEED_LP_WITH_OFFSET:
2376 *val = LSM6DSV16BX_WK_FEED_LP_WITH_OFFSET;
2377 break;
2378
2379 default:
2380 *val = LSM6DSV16BX_WK_FEED_SLOPE;
2381 break;
2382 }
2383 return ret;
2384 }
2385
2386 /**
2387 * @brief Mask hw function triggers when xl is settling.[set]
2388 *
2389 * @param ctx read / write interface definitions
2390 * @param val 0 or 1,
2391 * @retval interface status (MANDATORY: return 0 -> no Error)
2392 *
2393 */
lsm6dsv16bx_mask_trigger_xl_settl_set(stmdev_ctx_t * ctx,uint8_t val)2394 int32_t lsm6dsv16bx_mask_trigger_xl_settl_set(stmdev_ctx_t *ctx, uint8_t val)
2395 {
2396 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
2397 int32_t ret;
2398
2399 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2400
2401 if (ret == 0)
2402 {
2403 tap_cfg0.hw_func_mask_xl_settl = val & 0x01U;
2404 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2405 }
2406
2407 return ret;
2408 }
2409
2410 /**
2411 * @brief Mask hw function triggers when xl is settling.[get]
2412 *
2413 * @param ctx read / write interface definitions
2414 * @param val 0 or 1,
2415 * @retval interface status (MANDATORY: return 0 -> no Error)
2416 *
2417 */
lsm6dsv16bx_mask_trigger_xl_settl_get(stmdev_ctx_t * ctx,uint8_t * val)2418 int32_t lsm6dsv16bx_mask_trigger_xl_settl_get(stmdev_ctx_t *ctx, uint8_t *val)
2419 {
2420 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
2421 int32_t ret;
2422
2423 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2424 *val = tap_cfg0.hw_func_mask_xl_settl;
2425
2426 return ret;
2427 }
2428
2429
2430 /**
2431 * @brief LPF2 filter on 6D (sixd) function selection.[set]
2432 *
2433 * @param ctx read / write interface definitions
2434 * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS,
2435 * @retval interface status (MANDATORY: return 0 -> no Error)
2436 *
2437 */
lsm6dsv16bx_filt_sixd_feed_set(stmdev_ctx_t * ctx,lsm6dsv16bx_filt_sixd_feed_t val)2438 int32_t lsm6dsv16bx_filt_sixd_feed_set(stmdev_ctx_t *ctx,
2439 lsm6dsv16bx_filt_sixd_feed_t val)
2440 {
2441 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
2442 int32_t ret;
2443
2444 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2445 if (ret == 0)
2446 {
2447 tap_cfg0.low_pass_on_6d = (uint8_t)val & 0x01U;
2448 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2449 }
2450
2451 return ret;
2452 }
2453
2454 /**
2455 * @brief LPF2 filter on 6D (sixd) function selection.[get]
2456 *
2457 * @param ctx read / write interface definitions
2458 * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS,
2459 * @retval interface status (MANDATORY: return 0 -> no Error)
2460 *
2461 */
lsm6dsv16bx_filt_sixd_feed_get(stmdev_ctx_t * ctx,lsm6dsv16bx_filt_sixd_feed_t * val)2462 int32_t lsm6dsv16bx_filt_sixd_feed_get(stmdev_ctx_t *ctx,
2463 lsm6dsv16bx_filt_sixd_feed_t *val)
2464 {
2465 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
2466 int32_t ret;
2467
2468 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2469 switch (tap_cfg0.low_pass_on_6d)
2470 {
2471 case LSM6DSV16BX_SIXD_FEED_ODR_DIV_2:
2472 *val = LSM6DSV16BX_SIXD_FEED_ODR_DIV_2;
2473 break;
2474
2475 case LSM6DSV16BX_SIXD_FEED_LOW_PASS:
2476 *val = LSM6DSV16BX_SIXD_FEED_LOW_PASS;
2477 break;
2478
2479 default:
2480 *val = LSM6DSV16BX_SIXD_FEED_ODR_DIV_2;
2481 break;
2482 }
2483 return ret;
2484 }
2485
2486 /**
2487 * @}
2488 *
2489 */
2490
2491 /**
2492 * @defgroup Serial interfaces
2493 * @brief This section groups all the functions concerning
2494 * serial interfaces management (not auxiliary)
2495 * @{
2496 *
2497 */
2498
2499 /**
2500 * @brief Enables pull-up on SDO pin of UI (User Interface).[set]
2501 *
2502 * @param ctx read / write interface definitions
2503 * @param val Enables pull-up on SDO pin of UI (User Interface).
2504 * @retval interface status (MANDATORY: return 0 -> no Error)
2505 *
2506 */
lsm6dsv16bx_ui_sdo_pull_up_set(stmdev_ctx_t * ctx,uint8_t val)2507 int32_t lsm6dsv16bx_ui_sdo_pull_up_set(stmdev_ctx_t *ctx, uint8_t val)
2508 {
2509 lsm6dsv16bx_pin_ctrl_t pin_ctrl;
2510 int32_t ret;
2511
2512 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2513 if (ret == 0)
2514 {
2515 pin_ctrl.sdo_pu_en = val;
2516 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2517 }
2518
2519 return ret;
2520 }
2521
2522 /**
2523 * @brief Enables pull-up on SDO pin of UI (User Interface).[get]
2524 *
2525 * @param ctx read / write interface definitions
2526 * @param val Enables pull-up on SDO pin of UI (User Interface).
2527 * @retval interface status (MANDATORY: return 0 -> no Error)
2528 *
2529 */
lsm6dsv16bx_ui_sdo_pull_up_get(stmdev_ctx_t * ctx,uint8_t * val)2530 int32_t lsm6dsv16bx_ui_sdo_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val)
2531 {
2532 lsm6dsv16bx_pin_ctrl_t pin_ctrl;
2533 int32_t ret;
2534
2535 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2536 *val = pin_ctrl.sdo_pu_en;
2537
2538 return ret;
2539 }
2540
2541 /**
2542 * @brief Disables I2C and I3C on UI (User Interface).[set]
2543 *
2544 * @param ctx read / write interface definitions
2545 * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE,
2546 * @retval interface status (MANDATORY: return 0 -> no Error)
2547 *
2548 */
lsm6dsv16bx_ui_i2c_i3c_mode_set(stmdev_ctx_t * ctx,lsm6dsv16bx_ui_i2c_i3c_mode_t val)2549 int32_t lsm6dsv16bx_ui_i2c_i3c_mode_set(stmdev_ctx_t *ctx,
2550 lsm6dsv16bx_ui_i2c_i3c_mode_t val)
2551 {
2552 lsm6dsv16bx_if_cfg_t if_cfg;
2553 int32_t ret;
2554
2555 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2556 if (ret == 0)
2557 {
2558 if_cfg.i2c_i3c_disable = (uint8_t)val & 0x01U;
2559 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2560 }
2561
2562 return ret;
2563 }
2564
2565 /**
2566 * @brief Disables I2C and I3C on UI (User Interface).[get]
2567 *
2568 * @param ctx read / write interface definitions
2569 * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE,
2570 * @retval interface status (MANDATORY: return 0 -> no Error)
2571 *
2572 */
lsm6dsv16bx_ui_i2c_i3c_mode_get(stmdev_ctx_t * ctx,lsm6dsv16bx_ui_i2c_i3c_mode_t * val)2573 int32_t lsm6dsv16bx_ui_i2c_i3c_mode_get(stmdev_ctx_t *ctx,
2574 lsm6dsv16bx_ui_i2c_i3c_mode_t *val)
2575 {
2576 lsm6dsv16bx_if_cfg_t if_cfg;
2577 int32_t ret;
2578
2579 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2580 switch (if_cfg.i2c_i3c_disable)
2581 {
2582 case LSM6DSV16BX_I2C_I3C_ENABLE:
2583 *val = LSM6DSV16BX_I2C_I3C_ENABLE;
2584 break;
2585
2586 case LSM6DSV16BX_I2C_I3C_DISABLE:
2587 *val = LSM6DSV16BX_I2C_I3C_DISABLE;
2588 break;
2589
2590 default:
2591 *val = LSM6DSV16BX_I2C_I3C_ENABLE;
2592 break;
2593 }
2594 return ret;
2595 }
2596
2597 /**
2598 * @brief SPI Serial Interface Mode selection.[set]
2599 *
2600 * @param ctx read / write interface definitions
2601 * @param val SPI_4_WIRE, SPI_3_WIRE,
2602 * @retval interface status (MANDATORY: return 0 -> no Error)
2603 *
2604 */
lsm6dsv16bx_spi_mode_set(stmdev_ctx_t * ctx,lsm6dsv16bx_spi_mode_t val)2605 int32_t lsm6dsv16bx_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_spi_mode_t val)
2606 {
2607 lsm6dsv16bx_if_cfg_t if_cfg;
2608 int32_t ret;
2609
2610 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2611 if (ret == 0)
2612 {
2613 if_cfg.sim = (uint8_t)val & 0x01U;
2614 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2615 }
2616
2617 return ret;
2618 }
2619
2620 /**
2621 * @brief SPI Serial Interface Mode selection.[get]
2622 *
2623 * @param ctx read / write interface definitions
2624 * @param val SPI_4_WIRE, SPI_3_WIRE,
2625 * @retval interface status (MANDATORY: return 0 -> no Error)
2626 *
2627 */
lsm6dsv16bx_spi_mode_get(stmdev_ctx_t * ctx,lsm6dsv16bx_spi_mode_t * val)2628 int32_t lsm6dsv16bx_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_spi_mode_t *val)
2629 {
2630 lsm6dsv16bx_if_cfg_t if_cfg;
2631 int32_t ret;
2632
2633 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2634 switch (if_cfg.sim)
2635 {
2636 case LSM6DSV16BX_SPI_4_WIRE:
2637 *val = LSM6DSV16BX_SPI_4_WIRE;
2638 break;
2639
2640 case LSM6DSV16BX_SPI_3_WIRE:
2641 *val = LSM6DSV16BX_SPI_3_WIRE;
2642 break;
2643
2644 default:
2645 *val = LSM6DSV16BX_SPI_4_WIRE;
2646 break;
2647 }
2648 return ret;
2649 }
2650
2651 /**
2652 * @brief Enables pull-up on SDA pin.[set]
2653 *
2654 * @param ctx read / write interface definitions
2655 * @param val Enables pull-up on SDA pin.
2656 * @retval interface status (MANDATORY: return 0 -> no Error)
2657 *
2658 */
lsm6dsv16bx_ui_sda_pull_up_set(stmdev_ctx_t * ctx,uint8_t val)2659 int32_t lsm6dsv16bx_ui_sda_pull_up_set(stmdev_ctx_t *ctx, uint8_t val)
2660 {
2661 lsm6dsv16bx_if_cfg_t if_cfg;
2662 int32_t ret;
2663
2664 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2665 if (ret == 0)
2666 {
2667 if_cfg.sda_pu_en = (uint8_t)val & 0x01U;
2668 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2669 }
2670
2671 return ret;
2672 }
2673
2674 /**
2675 * @brief Enables pull-up on SDA pin.[get]
2676 *
2677 * @param ctx read / write interface definitions
2678 * @param val Enables pull-up on SDA pin.
2679 * @retval interface status (MANDATORY: return 0 -> no Error)
2680 *
2681 */
lsm6dsv16bx_ui_sda_pull_up_get(stmdev_ctx_t * ctx,uint8_t * val)2682 int32_t lsm6dsv16bx_ui_sda_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val)
2683 {
2684 lsm6dsv16bx_if_cfg_t if_cfg;
2685 int32_t ret;
2686
2687 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2688 *val = if_cfg.sda_pu_en;
2689
2690 return ret;
2691 }
2692
2693 /**
2694 * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[set]
2695 *
2696 * @param ctx read / write interface definitions
2697 * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms,
2698 * @retval interface status (MANDATORY: return 0 -> no Error)
2699 *
2700 */
lsm6dsv16bx_i3c_ibi_time_set(stmdev_ctx_t * ctx,lsm6dsv16bx_i3c_ibi_time_t val)2701 int32_t lsm6dsv16bx_i3c_ibi_time_set(stmdev_ctx_t *ctx,
2702 lsm6dsv16bx_i3c_ibi_time_t val)
2703 {
2704 lsm6dsv16bx_ctrl5_t ctrl5;
2705 int32_t ret;
2706
2707 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1);
2708 if (ret == 0)
2709 {
2710 ctrl5.bus_act_sel = (uint8_t)val & 0x03U;
2711 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1);
2712 }
2713
2714 return ret;
2715 }
2716
2717 /**
2718 * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[get]
2719 *
2720 * @param ctx read / write interface definitions
2721 * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms,
2722 * @retval interface status (MANDATORY: return 0 -> no Error)
2723 *
2724 */
lsm6dsv16bx_i3c_ibi_time_get(stmdev_ctx_t * ctx,lsm6dsv16bx_i3c_ibi_time_t * val)2725 int32_t lsm6dsv16bx_i3c_ibi_time_get(stmdev_ctx_t *ctx,
2726 lsm6dsv16bx_i3c_ibi_time_t *val)
2727 {
2728 lsm6dsv16bx_ctrl5_t ctrl5;
2729 int32_t ret;
2730
2731 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1);
2732 switch (ctrl5.bus_act_sel)
2733 {
2734 case LSM6DSV16BX_IBI_2us:
2735 *val = LSM6DSV16BX_IBI_2us;
2736 break;
2737
2738 case LSM6DSV16BX_IBI_50us:
2739 *val = LSM6DSV16BX_IBI_50us;
2740 break;
2741
2742 case LSM6DSV16BX_IBI_1ms:
2743 *val = LSM6DSV16BX_IBI_1ms;
2744 break;
2745
2746 case LSM6DSV16BX_IBI_25ms:
2747 *val = LSM6DSV16BX_IBI_25ms;
2748 break;
2749
2750 default:
2751 *val = LSM6DSV16BX_IBI_2us;
2752 break;
2753 }
2754 return ret;
2755 }
2756
2757 /**
2758 * @}
2759 *
2760 */
2761
2762 /**
2763 * @defgroup Interrupt pins
2764 * @brief This section groups all the functions that manage interrupt pins
2765 * @{
2766 *
2767 */
2768
2769 /**
2770 * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[set]
2771 *
2772 * @param ctx read / write interface definitions
2773 * @param val PUSH_PULL, OPEN_DRAIN,
2774 * @retval interface status (MANDATORY: return 0 -> no Error)
2775 *
2776 */
lsm6dsv16bx_int_pin_mode_set(stmdev_ctx_t * ctx,lsm6dsv16bx_int_pin_mode_t val)2777 int32_t lsm6dsv16bx_int_pin_mode_set(stmdev_ctx_t *ctx,
2778 lsm6dsv16bx_int_pin_mode_t val)
2779 {
2780 lsm6dsv16bx_if_cfg_t if_cfg;
2781 int32_t ret;
2782
2783 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2784 if (ret == 0)
2785 {
2786 if_cfg.pp_od = (uint8_t)val & 0x01U;
2787 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2788 }
2789
2790 return ret;
2791 }
2792
2793 /**
2794 * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[get]
2795 *
2796 * @param ctx read / write interface definitions
2797 * @param val PUSH_PULL, OPEN_DRAIN,
2798 * @retval interface status (MANDATORY: return 0 -> no Error)
2799 *
2800 */
lsm6dsv16bx_int_pin_mode_get(stmdev_ctx_t * ctx,lsm6dsv16bx_int_pin_mode_t * val)2801 int32_t lsm6dsv16bx_int_pin_mode_get(stmdev_ctx_t *ctx,
2802 lsm6dsv16bx_int_pin_mode_t *val)
2803 {
2804 lsm6dsv16bx_if_cfg_t if_cfg;
2805 int32_t ret;
2806
2807 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2808 switch (if_cfg.pp_od)
2809 {
2810 case LSM6DSV16BX_PUSH_PULL:
2811 *val = LSM6DSV16BX_PUSH_PULL;
2812 break;
2813
2814 case LSM6DSV16BX_OPEN_DRAIN:
2815 *val = LSM6DSV16BX_OPEN_DRAIN;
2816 break;
2817
2818 default:
2819 *val = LSM6DSV16BX_PUSH_PULL;
2820 break;
2821 }
2822 return ret;
2823 }
2824
2825 /**
2826 * @brief Interrupt activation level.[set]
2827 *
2828 * @param ctx read / write interface definitions
2829 * @param val ACTIVE_HIGH, ACTIVE_LOW,
2830 * @retval interface status (MANDATORY: return 0 -> no Error)
2831 *
2832 */
lsm6dsv16bx_pin_polarity_set(stmdev_ctx_t * ctx,lsm6dsv16bx_pin_polarity_t val)2833 int32_t lsm6dsv16bx_pin_polarity_set(stmdev_ctx_t *ctx,
2834 lsm6dsv16bx_pin_polarity_t val)
2835 {
2836 lsm6dsv16bx_if_cfg_t if_cfg;
2837 int32_t ret;
2838
2839 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2840 if (ret == 0)
2841 {
2842 if_cfg.h_lactive = (uint8_t)val & 0x01U;
2843 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2844 }
2845
2846 return ret;
2847 }
2848
2849 /**
2850 * @brief Interrupt activation level.[get]
2851 *
2852 * @param ctx read / write interface definitions
2853 * @param val ACTIVE_HIGH, ACTIVE_LOW,
2854 * @retval interface status (MANDATORY: return 0 -> no Error)
2855 *
2856 */
lsm6dsv16bx_pin_polarity_get(stmdev_ctx_t * ctx,lsm6dsv16bx_pin_polarity_t * val)2857 int32_t lsm6dsv16bx_pin_polarity_get(stmdev_ctx_t *ctx,
2858 lsm6dsv16bx_pin_polarity_t *val)
2859 {
2860 lsm6dsv16bx_if_cfg_t if_cfg;
2861 int32_t ret;
2862
2863 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2864 switch (if_cfg.h_lactive)
2865 {
2866 case LSM6DSV16BX_ACTIVE_HIGH:
2867 *val = LSM6DSV16BX_ACTIVE_HIGH;
2868 break;
2869
2870 case LSM6DSV16BX_ACTIVE_LOW:
2871 *val = LSM6DSV16BX_ACTIVE_LOW;
2872 break;
2873
2874 default:
2875 *val = LSM6DSV16BX_ACTIVE_HIGH;
2876 break;
2877 }
2878 return ret;
2879 }
2880
2881 /**
2882 * @brief It routes interrupt signals on INT 1 pin.[set]
2883 *
2884 * @param ctx read / write interface definitions
2885 * @param val It routes interrupt signals on INT 1 pin.
2886 * @retval interface status (MANDATORY: return 0 -> no Error)
2887 *
2888 */
lsm6dsv16bx_pin_int1_route_set(stmdev_ctx_t * ctx,lsm6dsv16bx_pin_int1_route_t val)2889 int32_t lsm6dsv16bx_pin_int1_route_set(stmdev_ctx_t *ctx,
2890 lsm6dsv16bx_pin_int1_route_t val)
2891 {
2892 lsm6dsv16bx_functions_enable_t functions_enable;
2893 lsm6dsv16bx_pin_int2_route_t pin_int2_route;
2894 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
2895 lsm6dsv16bx_emb_func_int1_t emb_func_int1;
2896 lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg;
2897 lsm6dsv16bx_int2_ctrl_t int2_ctrl;
2898 lsm6dsv16bx_int1_ctrl_t int1_ctrl;
2899 lsm6dsv16bx_fsm_int1_t fsm_int1;
2900 lsm6dsv16bx_mlc_int1_t mlc_int1;
2901 lsm6dsv16bx_md1_cfg_t md1_cfg;
2902 lsm6dsv16bx_md2_cfg_t md2_cfg;
2903 lsm6dsv16bx_ctrl4_t ctrl4;
2904 int32_t ret;
2905
2906 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
2907 if (ret == 0)
2908 {
2909 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
2910 }
2911 if (ret == 0)
2912 {
2913 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_INT1, (uint8_t *)&fsm_int1, 1);
2914 }
2915 if (ret == 0)
2916 {
2917 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_INT1, (uint8_t *)&mlc_int1, 1);
2918 }
2919
2920 if (ret == 0)
2921 {
2922 emb_func_int1.int1_step_detector = val.step_detector;
2923 emb_func_int1.int1_tilt = val.tilt;
2924 emb_func_int1.int1_sig_mot = val.sig_mot;
2925 emb_func_int1.int1_fsm_lc = val.fsm_lc;
2926 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
2927 }
2928 if (ret == 0)
2929 {
2930 fsm_int1.int1_fsm1 = val.fsm1;
2931 fsm_int1.int1_fsm2 = val.fsm2;
2932 fsm_int1.int1_fsm3 = val.fsm3;
2933 fsm_int1.int1_fsm4 = val.fsm4;
2934 fsm_int1.int1_fsm5 = val.fsm5;
2935 fsm_int1.int1_fsm6 = val.fsm6;
2936 fsm_int1.int1_fsm7 = val.fsm7;
2937 fsm_int1.int1_fsm8 = val.fsm8;
2938 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FSM_INT1, (uint8_t *)&fsm_int1, 1);
2939 }
2940 if (ret == 0)
2941 {
2942 mlc_int1.int1_mlc1 = val.mlc1;
2943 mlc_int1.int1_mlc2 = val.mlc2;
2944 mlc_int1.int1_mlc3 = val.mlc3;
2945 mlc_int1.int1_mlc4 = val.mlc4;
2946 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_MLC_INT1, (uint8_t *)&mlc_int1, 1);
2947 }
2948
2949 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
2950
2951 if (ret == 0)
2952 {
2953 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
2954 }
2955 if (ret == 0)
2956 {
2957 if ((val.emb_func_stand_by | val.timestamp) != PROPERTY_DISABLE)
2958 {
2959 ctrl4.int2_on_int1 = PROPERTY_ENABLE;
2960 }
2961 else
2962 {
2963 ctrl4.int2_on_int1 = PROPERTY_DISABLE;
2964 }
2965 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
2966 }
2967
2968 if (ret == 0)
2969 {
2970 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2971 }
2972
2973 if (ret == 0)
2974 {
2975 int2_ctrl.int2_emb_func_endop = val.emb_func_stand_by;
2976 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2977 }
2978
2979
2980 if (ret == 0)
2981 {
2982 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2983 }
2984
2985 if (ret == 0)
2986 {
2987 md2_cfg.int2_timestamp = val.timestamp;
2988 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2989 }
2990
2991 if (ret == 0)
2992 {
2993 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
2994 }
2995
2996 if (ret == 0)
2997 {
2998 inactivity_dur.sleep_status_on_int = val.sleep_status;
2999 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3000 }
3001
3002
3003 if (ret == 0)
3004 {
3005 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
3006 }
3007
3008 if (ret == 0)
3009 {
3010 int1_ctrl.int1_drdy_xl = val.drdy_xl;
3011 int1_ctrl.int1_drdy_g = val.drdy_gy;
3012 int1_ctrl.int1_fifo_th = val.fifo_th;
3013 int1_ctrl.int1_fifo_ovr = val.fifo_ovr;
3014 int1_ctrl.int1_fifo_full = val.fifo_full;
3015 int1_ctrl.int1_cnt_bdr = val.fifo_bdr;
3016 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
3017 }
3018
3019 if (ret == 0)
3020 {
3021 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3022 }
3023
3024 if (ret == 0)
3025 {
3026 if ((emb_func_int1.int1_fsm_lc
3027 | emb_func_int1.int1_sig_mot
3028 | emb_func_int1.int1_step_detector
3029 | emb_func_int1.int1_tilt
3030 | fsm_int1.int1_fsm1
3031 | fsm_int1.int1_fsm2
3032 | fsm_int1.int1_fsm3
3033 | fsm_int1.int1_fsm4
3034 | fsm_int1.int1_fsm5
3035 | fsm_int1.int1_fsm6
3036 | fsm_int1.int1_fsm7
3037 | fsm_int1.int1_fsm8
3038 | mlc_int1.int1_mlc1
3039 | mlc_int1.int1_mlc2
3040 | mlc_int1.int1_mlc3
3041 | mlc_int1.int1_mlc4) != PROPERTY_DISABLE)
3042 {
3043 md1_cfg.int1_emb_func = PROPERTY_ENABLE;
3044 }
3045 else
3046 {
3047 md1_cfg.int1_emb_func = PROPERTY_DISABLE;
3048 }
3049 md1_cfg.int1_6d = val.six_d;
3050 md1_cfg.int1_double_tap = val.double_tap;
3051 md1_cfg.int1_ff = val.free_fall;
3052 md1_cfg.int1_wu = val.wake_up;
3053 md1_cfg.int1_single_tap = val.single_tap;
3054 if ((val.sleep_status | val.sleep_change) != PROPERTY_DISABLE)
3055 {
3056 md1_cfg.int1_sleep_change = PROPERTY_ENABLE;
3057 }
3058 else
3059 {
3060 md1_cfg.int1_sleep_change = PROPERTY_DISABLE;
3061 }
3062 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3063 }
3064
3065 if (ret == 0)
3066 {
3067 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3068 }
3069
3070 if (ret == 0)
3071 {
3072 pedo_cmd_reg.carry_count_en = val.step_count_overflow;
3073 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3074 }
3075
3076
3077 if (ret == 0)
3078 {
3079 ret = lsm6dsv16bx_pin_int2_route_get(ctx, &pin_int2_route);
3080 }
3081
3082 if (ret == 0)
3083 {
3084 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3085 }
3086 if (ret == 0)
3087 {
3088 if ((pin_int2_route.six_d
3089 | pin_int2_route.double_tap
3090 | pin_int2_route.free_fall
3091 | pin_int2_route.wake_up
3092 | pin_int2_route.single_tap
3093 | pin_int2_route.sleep_status
3094 | pin_int2_route.sleep_change
3095 | val.six_d
3096 | val.double_tap
3097 | val.free_fall
3098 | val.wake_up
3099 | val.single_tap
3100 | val.sleep_status
3101 | val.sleep_change) != PROPERTY_DISABLE)
3102 {
3103 functions_enable.interrupts_enable = PROPERTY_ENABLE;
3104 }
3105
3106 else
3107 {
3108 functions_enable.interrupts_enable = PROPERTY_DISABLE;
3109 }
3110
3111 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3112 }
3113
3114 return ret;
3115 }
3116
3117 /**
3118 * @brief It routes interrupt signals on INT 1 pin.[get]
3119 *
3120 * @param ctx read / write interface definitions
3121 * @param val It routes interrupt signals on INT 1 pin.
3122 * @retval interface status (MANDATORY: return 0 -> no Error)
3123 *
3124 */
lsm6dsv16bx_pin_int1_route_get(stmdev_ctx_t * ctx,lsm6dsv16bx_pin_int1_route_t * val)3125 int32_t lsm6dsv16bx_pin_int1_route_get(stmdev_ctx_t *ctx,
3126 lsm6dsv16bx_pin_int1_route_t *val)
3127 {
3128 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
3129 lsm6dsv16bx_emb_func_int1_t emb_func_int1;
3130 lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg;
3131 lsm6dsv16bx_int1_ctrl_t int1_ctrl;
3132 lsm6dsv16bx_int2_ctrl_t int2_ctrl;
3133 lsm6dsv16bx_fsm_int1_t fsm_int1;
3134 lsm6dsv16bx_mlc_int1_t mlc_int1;
3135 lsm6dsv16bx_md1_cfg_t md1_cfg;
3136 lsm6dsv16bx_md2_cfg_t md2_cfg;
3137 lsm6dsv16bx_ctrl4_t ctrl4;
3138 int32_t ret;
3139
3140
3141 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
3142 if (ctrl4.int2_on_int1 == PROPERTY_ENABLE)
3143 {
3144 if (ret == 0)
3145 {
3146 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3147 val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop;
3148 }
3149 if (ret == 0)
3150 {
3151 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3152 val->timestamp = md2_cfg.int2_timestamp;
3153 }
3154 }
3155
3156 if (ret == 0)
3157 {
3158 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3159 val->sleep_status = inactivity_dur.sleep_status_on_int;
3160 }
3161
3162
3163 if (ret == 0)
3164 {
3165 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
3166 val->drdy_xl = int1_ctrl.int1_drdy_xl;
3167 val->drdy_gy = int1_ctrl.int1_drdy_g;
3168 val->fifo_th = int1_ctrl.int1_fifo_th;
3169 val->fifo_ovr = int1_ctrl.int1_fifo_ovr;
3170 val->fifo_full = int1_ctrl.int1_fifo_full;
3171 val->fifo_bdr = int1_ctrl.int1_cnt_bdr;
3172 }
3173
3174
3175 if (ret == 0)
3176 {
3177 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3178 val->six_d = md1_cfg.int1_6d;
3179 val->double_tap = md1_cfg.int1_double_tap;
3180 val->free_fall = md1_cfg.int1_ff;
3181 val->wake_up = md1_cfg.int1_wu;
3182 val->single_tap = md1_cfg.int1_single_tap;
3183 val->sleep_change = md1_cfg.int1_sleep_change;
3184 }
3185
3186 if (ret == 0)
3187 {
3188 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
3189 }
3190 if (ret == 0)
3191 {
3192 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
3193 val->step_detector = emb_func_int1.int1_step_detector;
3194 val->tilt = emb_func_int1.int1_tilt;
3195 val->sig_mot = emb_func_int1.int1_sig_mot;
3196 val->fsm_lc = emb_func_int1.int1_fsm_lc;
3197 }
3198 if (ret == 0)
3199 {
3200 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_INT1, (uint8_t *)&fsm_int1, 1);
3201 val->fsm1 = fsm_int1.int1_fsm1;
3202 val->fsm2 = fsm_int1.int1_fsm2;
3203 val->fsm3 = fsm_int1.int1_fsm3;
3204 val->fsm4 = fsm_int1.int1_fsm4;
3205 val->fsm5 = fsm_int1.int1_fsm5;
3206 val->fsm6 = fsm_int1.int1_fsm6;
3207 val->fsm7 = fsm_int1.int1_fsm7;
3208 val->fsm8 = fsm_int1.int1_fsm8;
3209 }
3210 if (ret == 0)
3211 {
3212 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_INT1, (uint8_t *)&mlc_int1, 1);
3213 val->mlc1 = mlc_int1.int1_mlc1;
3214 val->mlc2 = mlc_int1.int1_mlc2;
3215 val->mlc3 = mlc_int1.int1_mlc3;
3216 val->mlc4 = mlc_int1.int1_mlc4;
3217 }
3218
3219 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
3220
3221 if (ret == 0)
3222 {
3223 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3224 val->step_count_overflow = pedo_cmd_reg.carry_count_en;
3225 }
3226
3227 return ret;
3228 }
3229
3230
3231 /**
3232 * @brief It routes interrupt signals on INT 2 pin.[set]
3233 *
3234 * @param ctx read / write interface definitions
3235 * @param val It routes interrupt signals on INT 2 pin.
3236 * @retval interface status (MANDATORY: return 0 -> no Error)
3237 *
3238 */
lsm6dsv16bx_pin_int2_route_set(stmdev_ctx_t * ctx,lsm6dsv16bx_pin_int2_route_t val)3239 int32_t lsm6dsv16bx_pin_int2_route_set(stmdev_ctx_t *ctx,
3240 lsm6dsv16bx_pin_int2_route_t val)
3241 {
3242 lsm6dsv16bx_functions_enable_t functions_enable;
3243 lsm6dsv16bx_pin_int1_route_t pin_int1_route;
3244 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
3245 lsm6dsv16bx_emb_func_int2_t emb_func_int2;
3246 lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg;
3247 lsm6dsv16bx_int2_ctrl_t int2_ctrl;
3248 lsm6dsv16bx_fsm_int2_t fsm_int2;
3249 lsm6dsv16bx_mlc_int2_t mlc_int2;
3250 lsm6dsv16bx_md2_cfg_t md2_cfg;
3251 lsm6dsv16bx_ctrl4_t ctrl4;
3252 int32_t ret;
3253
3254
3255 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
3256 if (ret == 0)
3257 {
3258 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
3259 }
3260 if (ret == 0)
3261 {
3262 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_INT2, (uint8_t *)&fsm_int2, 1);
3263 }
3264 if (ret == 0)
3265 {
3266 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_INT2, (uint8_t *)&mlc_int2, 1);
3267 }
3268
3269 if (ret == 0)
3270 {
3271 emb_func_int2.int2_step_detector = val.step_detector;
3272 emb_func_int2.int2_tilt = val.tilt;
3273 emb_func_int2.int2_sig_mot = val.sig_mot;
3274 emb_func_int2.int2_fsm_lc = val.fsm_lc;
3275 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
3276 }
3277 if (ret == 0)
3278 {
3279 fsm_int2.int2_fsm1 = val.fsm1;
3280 fsm_int2.int2_fsm2 = val.fsm2;
3281 fsm_int2.int2_fsm3 = val.fsm3;
3282 fsm_int2.int2_fsm4 = val.fsm4;
3283 fsm_int2.int2_fsm5 = val.fsm5;
3284 fsm_int2.int2_fsm6 = val.fsm6;
3285 fsm_int2.int2_fsm7 = val.fsm7;
3286 fsm_int2.int2_fsm8 = val.fsm8;
3287 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FSM_INT2, (uint8_t *)&fsm_int2, 1);
3288 }
3289 if (ret == 0)
3290 {
3291 mlc_int2.int2_mlc1 = val.mlc1;
3292 mlc_int2.int2_mlc2 = val.mlc2;
3293 mlc_int2.int2_mlc3 = val.mlc3;
3294 mlc_int2.int2_mlc4 = val.mlc4;
3295 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_MLC_INT2, (uint8_t *)&mlc_int2, 1);
3296 }
3297
3298 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
3299
3300 if (ret == 0)
3301 {
3302 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
3303 }
3304 if (ret == 0)
3305 {
3306 if ((val.emb_func_stand_by | val.timestamp) != PROPERTY_DISABLE)
3307 {
3308 ctrl4.int2_on_int1 = PROPERTY_DISABLE;
3309 }
3310 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
3311 }
3312
3313 if (ret == 0)
3314 {
3315 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3316 }
3317
3318 if (ret == 0)
3319 {
3320 inactivity_dur.sleep_status_on_int = val.sleep_status;
3321 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3322 }
3323
3324 if (ret == 0)
3325 {
3326 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3327 }
3328
3329 if (ret == 0)
3330 {
3331 int2_ctrl.int2_drdy_xl = val.drdy_xl;
3332 int2_ctrl.int2_drdy_g = val.drdy_gy;
3333 int2_ctrl.int2_fifo_th = val.fifo_th;
3334 int2_ctrl.int2_fifo_ovr = val.fifo_ovr;
3335 int2_ctrl.int2_fifo_full = val.fifo_full;
3336 int2_ctrl.int2_cnt_bdr = val.fifo_bdr;
3337 int2_ctrl.int2_emb_func_endop = val.emb_func_stand_by;
3338 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3339 }
3340
3341 if (ret == 0)
3342 {
3343 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3344 }
3345
3346 if (ret == 0)
3347 {
3348 if ((emb_func_int2.int2_fsm_lc
3349 | emb_func_int2.int2_sig_mot
3350 | emb_func_int2.int2_step_detector
3351 | emb_func_int2.int2_tilt
3352 | fsm_int2.int2_fsm1
3353 | fsm_int2.int2_fsm2
3354 | fsm_int2.int2_fsm3
3355 | fsm_int2.int2_fsm4
3356 | fsm_int2.int2_fsm5
3357 | fsm_int2.int2_fsm6
3358 | fsm_int2.int2_fsm7
3359 | fsm_int2.int2_fsm8
3360 | mlc_int2.int2_mlc1
3361 | mlc_int2.int2_mlc2
3362 | mlc_int2.int2_mlc3
3363 | mlc_int2.int2_mlc4) != PROPERTY_DISABLE)
3364 {
3365 md2_cfg.int2_emb_func = PROPERTY_ENABLE;
3366 }
3367 else
3368 {
3369 md2_cfg.int2_emb_func = PROPERTY_DISABLE;
3370 }
3371 md2_cfg.int2_6d = val.six_d;
3372 md2_cfg.int2_double_tap = val.double_tap;
3373 md2_cfg.int2_ff = val.free_fall;
3374 md2_cfg.int2_wu = val.wake_up;
3375 md2_cfg.int2_single_tap = val.single_tap;
3376 md2_cfg.int2_timestamp = val.timestamp;
3377 if ((val.sleep_status | val.sleep_change) != PROPERTY_DISABLE)
3378 {
3379 md2_cfg.int2_sleep_change = PROPERTY_ENABLE;
3380 }
3381 else
3382 {
3383 md2_cfg.int2_sleep_change = PROPERTY_DISABLE;
3384 }
3385 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3386 }
3387
3388 if (ret == 0)
3389 {
3390 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3391 }
3392
3393 if (ret == 0)
3394 {
3395 pedo_cmd_reg.carry_count_en = val.step_count_overflow;
3396 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3397 }
3398
3399
3400 if (ret == 0)
3401 {
3402 ret = lsm6dsv16bx_pin_int1_route_get(ctx, &pin_int1_route);
3403 }
3404
3405 if (ret == 0)
3406 {
3407 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3408 }
3409 if (ret == 0)
3410 {
3411 if ((pin_int1_route.six_d
3412 | pin_int1_route.double_tap
3413 | pin_int1_route.free_fall
3414 | pin_int1_route.wake_up
3415 | pin_int1_route.single_tap
3416 | pin_int1_route.sleep_status
3417 | pin_int1_route.sleep_change
3418 | val.six_d
3419 | val.double_tap
3420 | val.free_fall
3421 | val.wake_up
3422 | val.single_tap
3423 | val.sleep_status
3424 | val.sleep_change) != PROPERTY_DISABLE)
3425 {
3426 functions_enable.interrupts_enable = PROPERTY_ENABLE;
3427 }
3428
3429 else
3430 {
3431 functions_enable.interrupts_enable = PROPERTY_DISABLE;
3432 }
3433
3434 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3435 }
3436
3437 return ret;
3438 }
3439
3440 /**
3441 * @brief It routes interrupt signals on INT 2 pin.[get]
3442 *
3443 * @param ctx read / write interface definitions
3444 * @param val It routes interrupt signals on INT 2 pin.
3445 * @retval interface status (MANDATORY: return 0 -> no Error)
3446 *
3447 */
lsm6dsv16bx_pin_int2_route_get(stmdev_ctx_t * ctx,lsm6dsv16bx_pin_int2_route_t * val)3448 int32_t lsm6dsv16bx_pin_int2_route_get(stmdev_ctx_t *ctx,
3449 lsm6dsv16bx_pin_int2_route_t *val)
3450 {
3451 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
3452 lsm6dsv16bx_emb_func_int2_t emb_func_int2;
3453 lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg;
3454 lsm6dsv16bx_int2_ctrl_t int2_ctrl;
3455 lsm6dsv16bx_fsm_int2_t fsm_int2;
3456 lsm6dsv16bx_mlc_int2_t mlc_int2;
3457 lsm6dsv16bx_md2_cfg_t md2_cfg;
3458 lsm6dsv16bx_ctrl4_t ctrl4;
3459 int32_t ret;
3460
3461
3462 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
3463 if (ctrl4.int2_on_int1 == PROPERTY_DISABLE)
3464 {
3465 if (ret == 0)
3466 {
3467 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3468 val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop;
3469 }
3470 if (ret == 0)
3471 {
3472 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3473 val->timestamp = md2_cfg.int2_timestamp;
3474 }
3475 }
3476
3477 if (ret == 0)
3478 {
3479 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3480 val->sleep_status = inactivity_dur.sleep_status_on_int;
3481 }
3482
3483
3484 if (ret == 0)
3485 {
3486 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3487 val->drdy_xl = int2_ctrl.int2_drdy_xl;
3488 val->drdy_gy = int2_ctrl.int2_drdy_g;
3489 val->fifo_th = int2_ctrl.int2_fifo_th;
3490 val->fifo_ovr = int2_ctrl.int2_fifo_ovr;
3491 val->fifo_full = int2_ctrl.int2_fifo_full;
3492 val->fifo_bdr = int2_ctrl.int2_cnt_bdr;
3493 }
3494
3495
3496 if (ret == 0)
3497 {
3498 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3499 val->six_d = md2_cfg.int2_6d;
3500 val->double_tap = md2_cfg.int2_double_tap;
3501 val->free_fall = md2_cfg.int2_ff;
3502 val->wake_up = md2_cfg.int2_wu;
3503 val->single_tap = md2_cfg.int2_single_tap;
3504 val->sleep_change = md2_cfg.int2_sleep_change;
3505 }
3506
3507 if (ret == 0)
3508 {
3509 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
3510 }
3511 if (ret == 0)
3512 {
3513 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
3514 val->step_detector = emb_func_int2.int2_step_detector;
3515 val->tilt = emb_func_int2.int2_tilt;
3516 val->sig_mot = emb_func_int2.int2_sig_mot;
3517 val->fsm_lc = emb_func_int2.int2_fsm_lc;
3518 }
3519 if (ret == 0)
3520 {
3521 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_INT2, (uint8_t *)&fsm_int2, 1);
3522 val->fsm1 = fsm_int2.int2_fsm1;
3523 val->fsm2 = fsm_int2.int2_fsm2;
3524 val->fsm3 = fsm_int2.int2_fsm3;
3525 val->fsm4 = fsm_int2.int2_fsm4;
3526 val->fsm5 = fsm_int2.int2_fsm5;
3527 val->fsm6 = fsm_int2.int2_fsm6;
3528 val->fsm7 = fsm_int2.int2_fsm7;
3529 val->fsm8 = fsm_int2.int2_fsm8;
3530 }
3531 if (ret == 0)
3532 {
3533 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_INT2, (uint8_t *)&mlc_int2, 1);
3534 val->mlc1 = mlc_int2.int2_mlc1;
3535 val->mlc2 = mlc_int2.int2_mlc2;
3536 val->mlc3 = mlc_int2.int2_mlc3;
3537 val->mlc4 = mlc_int2.int2_mlc4;
3538 }
3539
3540 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
3541
3542 if (ret == 0)
3543 {
3544 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3545 val->step_count_overflow = pedo_cmd_reg.carry_count_en;
3546 }
3547
3548 return ret;
3549 }
3550
3551 /**
3552 * @brief Enables INT pin when I3C is enabled.[set]
3553 *
3554 * @param ctx read / write interface definitions
3555 * @param val Enables INT pin when I3C is enabled.
3556 * @retval interface status (MANDATORY: return 0 -> no Error)
3557 *
3558 */
lsm6dsv16bx_pin_int_en_when_i2c_set(stmdev_ctx_t * ctx,uint8_t val)3559 int32_t lsm6dsv16bx_pin_int_en_when_i2c_set(stmdev_ctx_t *ctx, uint8_t val)
3560 {
3561 lsm6dsv16bx_ctrl5_t ctrl5;
3562 int32_t ret;
3563
3564 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1);
3565 if (ret == 0)
3566 {
3567 ctrl5.int_en_i3c = val;
3568 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1);
3569 }
3570
3571 return ret;
3572 }
3573
3574 /**
3575 * @brief Enables INT pin when I3C is enabled.[get]
3576 *
3577 * @param ctx read / write interface definitions
3578 * @param val Enables INT pin when I3C is enabled.
3579 * @retval interface status (MANDATORY: return 0 -> no Error)
3580 *
3581 */
lsm6dsv16bx_pin_int_en_when_i2c_get(stmdev_ctx_t * ctx,uint8_t * val)3582 int32_t lsm6dsv16bx_pin_int_en_when_i2c_get(stmdev_ctx_t *ctx, uint8_t *val)
3583 {
3584 lsm6dsv16bx_ctrl5_t ctrl5;
3585 int32_t ret;
3586
3587 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1);
3588 *val = ctrl5.int_en_i3c;
3589
3590 return ret;
3591 }
3592
3593 /**
3594 * @brief Interrupt notification mode.[set]
3595 *
3596 * @param ctx read / write interface definitions
3597 * @param val ALL_INT_PULSED, BASE_LATCHED_EMB_PULSED, BASE_PULSED_EMB_LATCHED, ALL_INT_LATCHED,
3598 * @retval interface status (MANDATORY: return 0 -> no Error)
3599 *
3600 */
lsm6dsv16bx_int_notification_set(stmdev_ctx_t * ctx,lsm6dsv16bx_int_notification_t val)3601 int32_t lsm6dsv16bx_int_notification_set(stmdev_ctx_t *ctx,
3602 lsm6dsv16bx_int_notification_t val)
3603 {
3604 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
3605 lsm6dsv16bx_page_rw_t page_rw;
3606 int32_t ret;
3607
3608 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3609 if (ret == 0)
3610 {
3611 tap_cfg0.lir = (uint8_t)val & 0x01U;
3612 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3613 }
3614
3615 if (ret == 0)
3616 {
3617 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
3618 }
3619 if (ret == 0)
3620 {
3621 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
3622 }
3623
3624 if (ret == 0)
3625 {
3626 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
3627 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
3628 }
3629
3630 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
3631
3632 return ret;
3633 }
3634
3635 /**
3636 * @brief Interrupt notification mode.[get]
3637 *
3638 * @param ctx read / write interface definitions
3639 * @param val ALL_INT_PULSED, BASE_LATCHED_EMB_PULSED, BASE_PULSED_EMB_LATCHED, ALL_INT_LATCHED,
3640 * @retval interface status (MANDATORY: return 0 -> no Error)
3641 *
3642 */
lsm6dsv16bx_int_notification_get(stmdev_ctx_t * ctx,lsm6dsv16bx_int_notification_t * val)3643 int32_t lsm6dsv16bx_int_notification_get(stmdev_ctx_t *ctx,
3644 lsm6dsv16bx_int_notification_t *val)
3645 {
3646 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
3647 lsm6dsv16bx_page_rw_t page_rw;
3648 int32_t ret;
3649
3650 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3651 if (ret == 0)
3652 {
3653 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
3654 }
3655 if (ret == 0)
3656 {
3657 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
3658 }
3659
3660 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
3661
3662 switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir)
3663 {
3664 case LSM6DSV16BX_ALL_INT_PULSED:
3665 *val = LSM6DSV16BX_ALL_INT_PULSED;
3666 break;
3667
3668 case LSM6DSV16BX_BASE_LATCHED_EMB_PULSED:
3669 *val = LSM6DSV16BX_BASE_LATCHED_EMB_PULSED;
3670 break;
3671
3672 case LSM6DSV16BX_BASE_PULSED_EMB_LATCHED:
3673 *val = LSM6DSV16BX_BASE_PULSED_EMB_LATCHED;
3674 break;
3675
3676 case LSM6DSV16BX_ALL_INT_LATCHED:
3677 *val = LSM6DSV16BX_ALL_INT_LATCHED;
3678 break;
3679
3680 default:
3681 *val = LSM6DSV16BX_ALL_INT_PULSED;
3682 break;
3683 }
3684 return ret;
3685 }
3686
3687 /**
3688 * @}
3689 *
3690 */
3691
3692 /**
3693 * @defgroup Wake Up event and Activity / Inactivity detection
3694 * @brief This section groups all the functions that manage the Wake Up
3695 * event generation.
3696 * @{
3697 *
3698 */
3699
3700 /**
3701 * @brief Enable activity/inactivity (sleep) function.[set]
3702 *
3703 * @param ctx read / write interface definitions
3704 * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN,
3705 * @retval interface status (MANDATORY: return 0 -> no Error)
3706 *
3707 */
lsm6dsv16bx_act_mode_set(stmdev_ctx_t * ctx,lsm6dsv16bx_act_mode_t val)3708 int32_t lsm6dsv16bx_act_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_act_mode_t val)
3709 {
3710 lsm6dsv16bx_functions_enable_t functions_enable;
3711 int32_t ret;
3712
3713 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3714 if (ret == 0)
3715 {
3716 functions_enable.inact_en = (uint8_t)val & 0x03U;
3717 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3718 }
3719
3720 return ret;
3721 }
3722
3723 /**
3724 * @brief Enable activity/inactivity (sleep) function.[get]
3725 *
3726 * @param ctx read / write interface definitions
3727 * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN,
3728 * @retval interface status (MANDATORY: return 0 -> no Error)
3729 *
3730 */
lsm6dsv16bx_act_mode_get(stmdev_ctx_t * ctx,lsm6dsv16bx_act_mode_t * val)3731 int32_t lsm6dsv16bx_act_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_act_mode_t *val)
3732 {
3733 lsm6dsv16bx_functions_enable_t functions_enable;
3734 int32_t ret;
3735
3736 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3737 switch (functions_enable.inact_en)
3738 {
3739 case LSM6DSV16BX_XL_AND_GY_NOT_AFFECTED:
3740 *val = LSM6DSV16BX_XL_AND_GY_NOT_AFFECTED;
3741 break;
3742
3743 case LSM6DSV16BX_XL_LOW_POWER_GY_NOT_AFFECTED:
3744 *val = LSM6DSV16BX_XL_LOW_POWER_GY_NOT_AFFECTED;
3745 break;
3746
3747 case LSM6DSV16BX_XL_LOW_POWER_GY_SLEEP:
3748 *val = LSM6DSV16BX_XL_LOW_POWER_GY_SLEEP;
3749 break;
3750
3751 case LSM6DSV16BX_XL_LOW_POWER_GY_POWER_DOWN:
3752 *val = LSM6DSV16BX_XL_LOW_POWER_GY_POWER_DOWN;
3753 break;
3754
3755 default:
3756 *val = LSM6DSV16BX_XL_AND_GY_NOT_AFFECTED;
3757 break;
3758 }
3759 return ret;
3760 }
3761
3762 /**
3763 * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[set]
3764 *
3765 * @param ctx read / write interface definitions
3766 * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE,
3767 * @retval interface status (MANDATORY: return 0 -> no Error)
3768 *
3769 */
lsm6dsv16bx_act_from_sleep_to_act_dur_set(stmdev_ctx_t * ctx,lsm6dsv16bx_act_from_sleep_to_act_dur_t val)3770 int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_set(stmdev_ctx_t *ctx,
3771 lsm6dsv16bx_act_from_sleep_to_act_dur_t val)
3772 {
3773 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
3774 int32_t ret;
3775
3776 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3777 if (ret == 0)
3778 {
3779 inactivity_dur.inact_dur = (uint8_t)val & 0x3U;
3780 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3781 }
3782
3783 return ret;
3784 }
3785
3786 /**
3787 * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[get]
3788 *
3789 * @param ctx read / write interface definitions
3790 * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE,
3791 * @retval interface status (MANDATORY: return 0 -> no Error)
3792 *
3793 */
lsm6dsv16bx_act_from_sleep_to_act_dur_get(stmdev_ctx_t * ctx,lsm6dsv16bx_act_from_sleep_to_act_dur_t * val)3794 int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_get(stmdev_ctx_t *ctx,
3795 lsm6dsv16bx_act_from_sleep_to_act_dur_t *val)
3796 {
3797 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
3798 int32_t ret;
3799
3800 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3801 switch (inactivity_dur.inact_dur)
3802 {
3803 case LSM6DSV16BX_SLEEP_TO_ACT_AT_1ST_SAMPLE:
3804 *val = LSM6DSV16BX_SLEEP_TO_ACT_AT_1ST_SAMPLE;
3805 break;
3806
3807 case LSM6DSV16BX_SLEEP_TO_ACT_AT_2ND_SAMPLE:
3808 *val = LSM6DSV16BX_SLEEP_TO_ACT_AT_2ND_SAMPLE;
3809 break;
3810
3811 case LSM6DSV16BX_SLEEP_TO_ACT_AT_3RD_SAMPLE:
3812 *val = LSM6DSV16BX_SLEEP_TO_ACT_AT_3RD_SAMPLE;
3813 break;
3814
3815 case LSM6DSV16BX_SLEEP_TO_ACT_AT_4th_SAMPLE:
3816 *val = LSM6DSV16BX_SLEEP_TO_ACT_AT_4th_SAMPLE;
3817 break;
3818
3819 default:
3820 *val = LSM6DSV16BX_SLEEP_TO_ACT_AT_1ST_SAMPLE;
3821 break;
3822 }
3823 return ret;
3824 }
3825
3826 /**
3827 * @brief Selects the accelerometer data rate during Inactivity.[set]
3828 *
3829 * @param ctx read / write interface definitions
3830 * @param val 1Hz875, 15Hz, 30Hz, 60Hz,
3831 * @retval interface status (MANDATORY: return 0 -> no Error)
3832 *
3833 */
lsm6dsv16bx_act_sleep_xl_odr_set(stmdev_ctx_t * ctx,lsm6dsv16bx_act_sleep_xl_odr_t val)3834 int32_t lsm6dsv16bx_act_sleep_xl_odr_set(stmdev_ctx_t *ctx,
3835 lsm6dsv16bx_act_sleep_xl_odr_t val)
3836 {
3837 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
3838 int32_t ret;
3839
3840 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3841 if (ret == 0)
3842 {
3843 inactivity_dur.xl_inact_odr = (uint8_t)val & 0x03U;
3844 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3845 }
3846
3847 return ret;
3848 }
3849
3850 /**
3851 * @brief Selects the accelerometer data rate during Inactivity.[get]
3852 *
3853 * @param ctx read / write interface definitions
3854 * @param val 1Hz875, 15Hz, 30Hz, 60Hz,
3855 * @retval interface status (MANDATORY: return 0 -> no Error)
3856 *
3857 */
lsm6dsv16bx_act_sleep_xl_odr_get(stmdev_ctx_t * ctx,lsm6dsv16bx_act_sleep_xl_odr_t * val)3858 int32_t lsm6dsv16bx_act_sleep_xl_odr_get(stmdev_ctx_t *ctx,
3859 lsm6dsv16bx_act_sleep_xl_odr_t *val)
3860 {
3861 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
3862 int32_t ret;
3863
3864 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3865 switch (inactivity_dur.xl_inact_odr)
3866 {
3867 case LSM6DSV16BX_1Hz875:
3868 *val = LSM6DSV16BX_1Hz875;
3869 break;
3870
3871 case LSM6DSV16BX_15Hz:
3872 *val = LSM6DSV16BX_15Hz;
3873 break;
3874
3875 case LSM6DSV16BX_30Hz:
3876 *val = LSM6DSV16BX_30Hz;
3877 break;
3878
3879 case LSM6DSV16BX_60Hz:
3880 *val = LSM6DSV16BX_60Hz;
3881 break;
3882
3883 default:
3884 *val = LSM6DSV16BX_1Hz875;
3885 break;
3886 }
3887 return ret;
3888 }
3889
3890 /**
3891 * @brief Wakeup and activity/inactivity threshold.[set]
3892 *
3893 * @param ctx read / write interface definitions
3894 * @param val Wakeup and activity/inactivity threshold.
3895 * @retval interface status (MANDATORY: return 0 -> no Error)
3896 *
3897 */
lsm6dsv16bx_act_thresholds_set(stmdev_ctx_t * ctx,lsm6dsv16bx_act_thresholds_t val)3898 int32_t lsm6dsv16bx_act_thresholds_set(stmdev_ctx_t *ctx,
3899 lsm6dsv16bx_act_thresholds_t val)
3900 {
3901 lsm6dsv16bx_inactivity_ths_t inactivity_ths;
3902 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
3903 lsm6dsv16bx_wake_up_ths_t wake_up_ths;
3904 int32_t ret;
3905 float_t tmp;
3906
3907 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3908 if (ret == 0)
3909 {
3910 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
3911 }
3912
3913 if (ret == 0)
3914 {
3915 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
3916 }
3917
3918 if ((val.wk_ths_mg < (uint32_t)(7.8125f * 63.0f))
3919 && (val.inact_ths_mg < (uint32_t)(7.8125f * 63.0f)))
3920 {
3921 inactivity_dur.wu_inact_ths_w = 0;
3922
3923 tmp = (float_t)val.inact_ths_mg / 7.8125f;
3924 inactivity_ths.inact_ths = (uint8_t)tmp;
3925
3926 tmp = (float_t)val.wk_ths_mg / 7.8125f;
3927 wake_up_ths.wk_ths = (uint8_t)tmp;
3928 }
3929 else if ((val.wk_ths_mg < (uint32_t)(15.625f * 63.0f))
3930 && (val.inact_ths_mg < (uint32_t)(15.625f * 63.0f)))
3931 {
3932 inactivity_dur.wu_inact_ths_w = 1;
3933
3934 tmp = (float_t)val.inact_ths_mg / 15.625f;
3935 inactivity_ths.inact_ths = (uint8_t)tmp;
3936
3937 tmp = (float_t)val.wk_ths_mg / 15.625f;
3938 wake_up_ths.wk_ths = (uint8_t)tmp;
3939 }
3940 else if ((val.wk_ths_mg < (uint32_t)(31.25f * 63.0f))
3941 && (val.inact_ths_mg < (uint32_t)(31.25f * 63.0f)))
3942 {
3943 inactivity_dur.wu_inact_ths_w = 2;
3944
3945 tmp = (float_t)val.inact_ths_mg / 31.25f;
3946 inactivity_ths.inact_ths = (uint8_t)tmp;
3947
3948 tmp = (float_t)val.wk_ths_mg / 31.25f;
3949 wake_up_ths.wk_ths = (uint8_t)tmp;
3950 }
3951 else if ((val.wk_ths_mg < (uint32_t)(62.5f * 63.0f))
3952 && (val.inact_ths_mg < (uint32_t)(62.5f * 63.0f)))
3953 {
3954 inactivity_dur.wu_inact_ths_w = 3;
3955
3956 tmp = (float_t)val.inact_ths_mg / 62.5f;
3957 inactivity_ths.inact_ths = (uint8_t)tmp;
3958
3959 tmp = (float_t)val.wk_ths_mg / 62.5f;
3960 wake_up_ths.wk_ths = (uint8_t)tmp;
3961 }
3962 else if ((val.wk_ths_mg < (uint32_t)(125.0f * 63.0f))
3963 && (val.inact_ths_mg < (uint32_t)(125.0f * 63.0f)))
3964 {
3965 inactivity_dur.wu_inact_ths_w = 4;
3966
3967 tmp = (float_t)val.inact_ths_mg / 125.0f;
3968 inactivity_ths.inact_ths = (uint8_t)tmp;
3969
3970 tmp = (float_t)val.wk_ths_mg / 125.0f;
3971 wake_up_ths.wk_ths = (uint8_t)tmp;
3972 }
3973 else if ((val.wk_ths_mg < (uint32_t)(250.0f * 63.0f))
3974 && (val.inact_ths_mg < (uint32_t)(250.0f * 63.0f)))
3975 {
3976 inactivity_dur.wu_inact_ths_w = 5;
3977
3978 tmp = (float_t)val.inact_ths_mg / 250.0f;
3979 inactivity_ths.inact_ths = (uint8_t)tmp;
3980
3981 tmp = (float_t)val.wk_ths_mg / 250.0f;
3982 wake_up_ths.wk_ths = (uint8_t)tmp;
3983 }
3984 else // out of limit
3985 {
3986 inactivity_dur.wu_inact_ths_w = 5;
3987 inactivity_ths.inact_ths = 0x3FU;
3988 wake_up_ths.wk_ths = 0x3FU;
3989 }
3990
3991 if (ret == 0)
3992 {
3993 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3994 }
3995 if (ret == 0)
3996 {
3997
3998 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
3999 }
4000 if (ret == 0)
4001 {
4002
4003 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4004 }
4005
4006 return ret;
4007 }
4008
4009 /**
4010 * @brief Wakeup and activity/inactivity threshold.[get]
4011 *
4012 * @param ctx read / write interface definitions
4013 * @param val Wakeup and activity/inactivity threshold.
4014 * @retval interface status (MANDATORY: return 0 -> no Error)
4015 *
4016 */
lsm6dsv16bx_act_thresholds_get(stmdev_ctx_t * ctx,lsm6dsv16bx_act_thresholds_t * val)4017 int32_t lsm6dsv16bx_act_thresholds_get(stmdev_ctx_t *ctx,
4018 lsm6dsv16bx_act_thresholds_t *val)
4019 {
4020 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
4021 lsm6dsv16bx_inactivity_ths_t inactivity_ths;
4022 lsm6dsv16bx_wake_up_ths_t wake_up_ths;
4023 int32_t ret;
4024 float_t tmp;
4025
4026 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
4027 if (ret == 0)
4028 {
4029 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
4030 }
4031 if (ret == 0)
4032 {
4033 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4034 }
4035
4036 switch (inactivity_dur.wu_inact_ths_w)
4037 {
4038 case 0:
4039 tmp = (float_t)wake_up_ths.wk_ths * 7.8125f;
4040 val->wk_ths_mg = (uint32_t)tmp;
4041
4042 tmp = (float_t)inactivity_ths.inact_ths * 7.8125f;
4043 val->inact_ths_mg = (uint32_t)tmp;
4044 break;
4045
4046 case 1:
4047 tmp = (float_t)wake_up_ths.wk_ths * 15.625f;
4048 val->wk_ths_mg = (uint32_t)tmp;
4049
4050 tmp = (float_t)inactivity_ths.inact_ths * 15.625f;
4051 val->inact_ths_mg = (uint32_t)tmp;
4052 break;
4053
4054 case 2:
4055 tmp = (float_t)wake_up_ths.wk_ths * 31.25f;
4056 val->wk_ths_mg = (uint32_t)tmp;
4057
4058 tmp = (float_t)inactivity_ths.inact_ths * 31.25f;
4059 val->inact_ths_mg = (uint32_t)tmp;
4060 break;
4061
4062 case 3:
4063 tmp = (float_t)wake_up_ths.wk_ths * 62.5f;
4064 val->wk_ths_mg = (uint32_t)tmp;
4065
4066 tmp = (float_t)inactivity_ths.inact_ths * 62.5f;
4067 val->inact_ths_mg = (uint32_t)tmp;
4068 break;
4069
4070 case 4:
4071 tmp = (float_t)wake_up_ths.wk_ths * 125.0f;
4072 val->wk_ths_mg = (uint32_t)tmp;
4073
4074 tmp = (float_t)inactivity_ths.inact_ths * 125.0f;
4075 val->inact_ths_mg = (uint32_t)tmp;
4076 break;
4077
4078 default:
4079 tmp = (float_t)wake_up_ths.wk_ths * 250.0f;
4080 val->wk_ths_mg = (uint32_t)tmp;
4081
4082 tmp = (float_t)inactivity_ths.inact_ths * 250.0f;
4083 val->inact_ths_mg = (uint32_t)tmp;
4084 break;
4085 }
4086
4087 return ret;
4088 }
4089
4090 /**
4091 * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [set]
4092 *
4093 * @param ctx read / write interface definitions
4094 * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time.
4095 * @retval interface status (MANDATORY: return 0 -> no Error)
4096 *
4097 */
lsm6dsv16bx_act_wkup_time_windows_set(stmdev_ctx_t * ctx,lsm6dsv16bx_act_wkup_time_windows_t val)4098 int32_t lsm6dsv16bx_act_wkup_time_windows_set(stmdev_ctx_t *ctx,
4099 lsm6dsv16bx_act_wkup_time_windows_t val)
4100 {
4101 lsm6dsv16bx_wake_up_dur_t wake_up_dur;
4102 int32_t ret;
4103
4104 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4105 if (ret == 0)
4106 {
4107 wake_up_dur.wake_dur = val.shock;
4108 wake_up_dur.sleep_dur = val.quiet;
4109 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4110 }
4111
4112 return ret;
4113 }
4114
4115 /**
4116 * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [get]
4117 *
4118 * @param ctx read / write interface definitions
4119 * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time.
4120 * @retval interface status (MANDATORY: return 0 -> no Error)
4121 *
4122 */
lsm6dsv16bx_act_wkup_time_windows_get(stmdev_ctx_t * ctx,lsm6dsv16bx_act_wkup_time_windows_t * val)4123 int32_t lsm6dsv16bx_act_wkup_time_windows_get(stmdev_ctx_t *ctx,
4124 lsm6dsv16bx_act_wkup_time_windows_t *val)
4125 {
4126 lsm6dsv16bx_wake_up_dur_t wake_up_dur;
4127 int32_t ret;
4128
4129 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4130 val->shock = wake_up_dur.wake_dur;
4131 val->quiet = wake_up_dur.sleep_dur;
4132
4133 return ret;
4134 }
4135
4136 /**
4137 * @}
4138 *
4139 */
4140
4141 /**
4142 * @defgroup Tap Generator
4143 * @brief This section groups all the functions that manage the
4144 * tap and double tap event generation.
4145 * @{
4146 *
4147 */
4148
4149 /**
4150 * @brief Enable axis for Tap - Double Tap detection.[set]
4151 *
4152 * @param ctx read / write interface definitions
4153 * @param val Enable axis for Tap - Double Tap detection.
4154 * @retval interface status (MANDATORY: return 0 -> no Error)
4155 *
4156 */
lsm6dsv16bx_tap_detection_set(stmdev_ctx_t * ctx,lsm6dsv16bx_tap_detection_t val)4157 int32_t lsm6dsv16bx_tap_detection_set(stmdev_ctx_t *ctx,
4158 lsm6dsv16bx_tap_detection_t val)
4159 {
4160 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
4161 int32_t ret;
4162
4163 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4164 if (ret == 0)
4165 {
4166 tap_cfg0.tap_x_en = val.tap_x_en;
4167 tap_cfg0.tap_y_en = val.tap_y_en;
4168 tap_cfg0.tap_z_en = val.tap_z_en;
4169 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4170 }
4171
4172 return ret;
4173 }
4174
4175 /**
4176 * @brief Enable axis for Tap - Double Tap detection.[get]
4177 *
4178 * @param ctx read / write interface definitions
4179 * @param val Enable axis for Tap - Double Tap detection.
4180 * @retval interface status (MANDATORY: return 0 -> no Error)
4181 *
4182 */
lsm6dsv16bx_tap_detection_get(stmdev_ctx_t * ctx,lsm6dsv16bx_tap_detection_t * val)4183 int32_t lsm6dsv16bx_tap_detection_get(stmdev_ctx_t *ctx,
4184 lsm6dsv16bx_tap_detection_t *val)
4185 {
4186 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
4187 int32_t ret;
4188
4189 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4190 val->tap_x_en = tap_cfg0.tap_x_en;
4191 val->tap_y_en = tap_cfg0.tap_y_en;
4192 val->tap_z_en = tap_cfg0.tap_z_en;
4193
4194 return ret;
4195 }
4196
4197 /**
4198 * @brief axis Tap - Double Tap recognition thresholds.[set]
4199 *
4200 * @param ctx read / write interface definitions
4201 * @param val axis Tap - Double Tap recognition thresholds.
4202 * @retval interface status (MANDATORY: return 0 -> no Error)
4203 *
4204 */
lsm6dsv16bx_tap_thresholds_set(stmdev_ctx_t * ctx,lsm6dsv16bx_tap_thresholds_t val)4205 int32_t lsm6dsv16bx_tap_thresholds_set(stmdev_ctx_t *ctx,
4206 lsm6dsv16bx_tap_thresholds_t val)
4207 {
4208 lsm6dsv16bx_tap_ths_6d_t tap_ths_6d;
4209 lsm6dsv16bx_tap_cfg2_t tap_cfg2;
4210 lsm6dsv16bx_tap_cfg1_t tap_cfg1;
4211 int32_t ret;
4212
4213 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4214 if (ret == 0)
4215 {
4216 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
4217 }
4218 if (ret == 0)
4219 {
4220 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4221 }
4222
4223 tap_cfg1.tap_ths_z = val.z;
4224 tap_cfg2.tap_ths_y = val.y;
4225 tap_ths_6d.tap_ths_x = val.x;
4226
4227 if (ret == 0)
4228 {
4229 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4230 }
4231 if (ret == 0)
4232 {
4233 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
4234 }
4235 if (ret == 0)
4236 {
4237 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4238 }
4239
4240 return ret;
4241 }
4242
4243 /**
4244 * @brief axis Tap - Double Tap recognition thresholds.[get]
4245 *
4246 * @param ctx read / write interface definitions
4247 * @param val axis Tap - Double Tap recognition thresholds.
4248 * @retval interface status (MANDATORY: return 0 -> no Error)
4249 *
4250 */
lsm6dsv16bx_tap_thresholds_get(stmdev_ctx_t * ctx,lsm6dsv16bx_tap_thresholds_t * val)4251 int32_t lsm6dsv16bx_tap_thresholds_get(stmdev_ctx_t *ctx,
4252 lsm6dsv16bx_tap_thresholds_t *val)
4253 {
4254 lsm6dsv16bx_tap_ths_6d_t tap_ths_6d;
4255 lsm6dsv16bx_tap_cfg2_t tap_cfg2;
4256 lsm6dsv16bx_tap_cfg1_t tap_cfg1;
4257 int32_t ret;
4258
4259 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4260 if (ret == 0)
4261 {
4262 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
4263 }
4264 if (ret == 0)
4265 {
4266 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4267 }
4268
4269 val->z = tap_cfg1.tap_ths_z;
4270 val->y = tap_cfg2.tap_ths_y;
4271 val->x = tap_ths_6d.tap_ths_x;
4272
4273 return ret;
4274 }
4275
4276 /**
4277 * @brief Selection of axis priority for TAP detection.[set]
4278 *
4279 * @param ctx read / write interface definitions
4280 * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY ,
4281 * @retval interface status (MANDATORY: return 0 -> no Error)
4282 *
4283 */
lsm6dsv16bx_tap_axis_priority_set(stmdev_ctx_t * ctx,lsm6dsv16bx_tap_axis_priority_t val)4284 int32_t lsm6dsv16bx_tap_axis_priority_set(stmdev_ctx_t *ctx,
4285 lsm6dsv16bx_tap_axis_priority_t val)
4286 {
4287 lsm6dsv16bx_tap_cfg1_t tap_cfg1;
4288 int32_t ret;
4289
4290 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4291 if (ret == 0)
4292 {
4293 tap_cfg1.tap_priority = (uint8_t)val & 0x07U;
4294 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4295 }
4296
4297 return ret;
4298 }
4299
4300 /**
4301 * @brief Selection of axis priority for TAP detection.[get]
4302 *
4303 * @param ctx read / write interface definitions
4304 * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY ,
4305 * @retval interface status (MANDATORY: return 0 -> no Error)
4306 *
4307 */
lsm6dsv16bx_tap_axis_priority_get(stmdev_ctx_t * ctx,lsm6dsv16bx_tap_axis_priority_t * val)4308 int32_t lsm6dsv16bx_tap_axis_priority_get(stmdev_ctx_t *ctx,
4309 lsm6dsv16bx_tap_axis_priority_t *val)
4310 {
4311 lsm6dsv16bx_tap_cfg1_t tap_cfg1;
4312 int32_t ret;
4313
4314 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4315 switch (tap_cfg1.tap_priority)
4316 {
4317 case LSM6DSV16BX_XYZ :
4318 *val = LSM6DSV16BX_XYZ ;
4319 break;
4320
4321 case LSM6DSV16BX_YXZ :
4322 *val = LSM6DSV16BX_YXZ ;
4323 break;
4324
4325 case LSM6DSV16BX_XZY:
4326 *val = LSM6DSV16BX_XZY;
4327 break;
4328
4329 case LSM6DSV16BX_ZYX :
4330 *val = LSM6DSV16BX_ZYX ;
4331 break;
4332
4333 case LSM6DSV16BX_YZX :
4334 *val = LSM6DSV16BX_YZX ;
4335 break;
4336
4337 case LSM6DSV16BX_ZXY :
4338 *val = LSM6DSV16BX_ZXY ;
4339 break;
4340
4341 default:
4342 *val = LSM6DSV16BX_XYZ ;
4343 break;
4344 }
4345 return ret;
4346 }
4347
4348
4349 /**
4350 * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[set]
4351 *
4352 * @param ctx read / write interface definitions
4353 * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.
4354 * @retval interface status (MANDATORY: return 0 -> no Error)
4355 *
4356 */
lsm6dsv16bx_tap_time_windows_set(stmdev_ctx_t * ctx,lsm6dsv16bx_tap_time_windows_t val)4357 int32_t lsm6dsv16bx_tap_time_windows_set(stmdev_ctx_t *ctx,
4358 lsm6dsv16bx_tap_time_windows_t val)
4359 {
4360 lsm6dsv16bx_tap_dur_t tap_dur;
4361 int32_t ret;
4362
4363 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_DUR, (uint8_t *)&tap_dur, 1);
4364 if (ret == 0)
4365 {
4366 tap_dur.shock = val.shock;
4367 tap_dur.quiet = val.quiet;
4368 tap_dur.dur = val.tap_gap;
4369 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_DUR, (uint8_t *)&tap_dur, 1);
4370 }
4371
4372 return ret;
4373 }
4374
4375 /**
4376 * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[get]
4377 *
4378 * @param ctx read / write interface definitions
4379 * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.
4380 * @retval interface status (MANDATORY: return 0 -> no Error)
4381 *
4382 */
lsm6dsv16bx_tap_time_windows_get(stmdev_ctx_t * ctx,lsm6dsv16bx_tap_time_windows_t * val)4383 int32_t lsm6dsv16bx_tap_time_windows_get(stmdev_ctx_t *ctx,
4384 lsm6dsv16bx_tap_time_windows_t *val)
4385 {
4386 lsm6dsv16bx_tap_dur_t tap_dur;
4387 int32_t ret;
4388
4389 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_DUR, (uint8_t *)&tap_dur, 1);
4390 val->shock = tap_dur.shock;
4391 val->quiet = tap_dur.quiet;
4392 val->tap_gap = tap_dur.dur;
4393
4394 return ret;
4395 }
4396
4397 /**
4398 * @brief Single/double-tap event enable.[set]
4399 *
4400 * @param ctx read / write interface definitions
4401 * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE,
4402 * @retval interface status (MANDATORY: return 0 -> no Error)
4403 *
4404 */
lsm6dsv16bx_tap_mode_set(stmdev_ctx_t * ctx,lsm6dsv16bx_tap_mode_t val)4405 int32_t lsm6dsv16bx_tap_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_tap_mode_t val)
4406 {
4407 lsm6dsv16bx_wake_up_ths_t wake_up_ths;
4408 int32_t ret;
4409
4410 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4411 if (ret == 0)
4412 {
4413 wake_up_ths.single_double_tap = (uint8_t)val & 0x01U;
4414 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4415 }
4416
4417 return ret;
4418 }
4419
4420 /**
4421 * @brief Single/double-tap event enable.[get]
4422 *
4423 * @param ctx read / write interface definitions
4424 * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE,
4425 * @retval interface status (MANDATORY: return 0 -> no Error)
4426 *
4427 */
lsm6dsv16bx_tap_mode_get(stmdev_ctx_t * ctx,lsm6dsv16bx_tap_mode_t * val)4428 int32_t lsm6dsv16bx_tap_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_tap_mode_t *val)
4429 {
4430 lsm6dsv16bx_wake_up_ths_t wake_up_ths;
4431 int32_t ret;
4432
4433 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4434 switch (wake_up_ths.single_double_tap)
4435 {
4436 case LSM6DSV16BX_ONLY_SINGLE:
4437 *val = LSM6DSV16BX_ONLY_SINGLE;
4438 break;
4439
4440 case LSM6DSV16BX_BOTH_SINGLE_DOUBLE:
4441 *val = LSM6DSV16BX_BOTH_SINGLE_DOUBLE;
4442 break;
4443
4444 default:
4445 *val = LSM6DSV16BX_ONLY_SINGLE;
4446 break;
4447 }
4448 return ret;
4449 }
4450
4451 /**
4452 * @}
4453 *
4454 */
4455
4456 /**
4457 * @defgroup Six position detection (6D)
4458 * @brief This section groups all the functions concerning six position
4459 * detection (6D).
4460 * @{
4461 *
4462 */
4463
4464 /**
4465 * @brief Threshold for 4D/6D function.[set]
4466 *
4467 * @param ctx read / write interface definitions
4468 * @param val DEG_80, DEG_70, DEG_60, DEG_50,
4469 * @retval interface status (MANDATORY: return 0 -> no Error)
4470 *
4471 */
lsm6dsv16bx_6d_threshold_set(stmdev_ctx_t * ctx,lsm6dsv16bx_6d_threshold_t val)4472 int32_t lsm6dsv16bx_6d_threshold_set(stmdev_ctx_t *ctx,
4473 lsm6dsv16bx_6d_threshold_t val)
4474 {
4475 lsm6dsv16bx_tap_ths_6d_t tap_ths_6d;
4476 int32_t ret;
4477
4478 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4479 if (ret == 0)
4480 {
4481 tap_ths_6d.sixd_ths = (uint8_t)val & 0x03U;
4482 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4483 }
4484
4485 return ret;
4486 }
4487
4488 /**
4489 * @brief Threshold for 4D/6D function.[get]
4490 *
4491 * @param ctx read / write interface definitions
4492 * @param val DEG_80, DEG_70, DEG_60, DEG_50,
4493 * @retval interface status (MANDATORY: return 0 -> no Error)
4494 *
4495 */
lsm6dsv16bx_6d_threshold_get(stmdev_ctx_t * ctx,lsm6dsv16bx_6d_threshold_t * val)4496 int32_t lsm6dsv16bx_6d_threshold_get(stmdev_ctx_t *ctx,
4497 lsm6dsv16bx_6d_threshold_t *val)
4498 {
4499 lsm6dsv16bx_tap_ths_6d_t tap_ths_6d;
4500 int32_t ret;
4501
4502 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4503 switch (tap_ths_6d.sixd_ths)
4504 {
4505 case LSM6DSV16BX_DEG_80:
4506 *val = LSM6DSV16BX_DEG_80;
4507 break;
4508
4509 case LSM6DSV16BX_DEG_70:
4510 *val = LSM6DSV16BX_DEG_70;
4511 break;
4512
4513 case LSM6DSV16BX_DEG_60:
4514 *val = LSM6DSV16BX_DEG_60;
4515 break;
4516
4517 case LSM6DSV16BX_DEG_50:
4518 *val = LSM6DSV16BX_DEG_50;
4519 break;
4520
4521 default:
4522 *val = LSM6DSV16BX_DEG_80;
4523 break;
4524 }
4525 return ret;
4526 }
4527
4528 /**
4529 * @}
4530 *
4531 */
4532
4533 /**
4534 * @defgroup Free fall
4535 * @brief This section group all the functions concerning the free
4536 * fall detection.
4537 * @{
4538 *
4539 */
4540
4541 /**
4542 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set]
4543 *
4544 * @param ctx read / write interface definitions
4545 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
4546 * @retval interface status (MANDATORY: return 0 -> no Error)
4547 *
4548 */
lsm6dsv16bx_ff_time_windows_set(stmdev_ctx_t * ctx,uint8_t val)4549 int32_t lsm6dsv16bx_ff_time_windows_set(stmdev_ctx_t *ctx, uint8_t val)
4550 {
4551 lsm6dsv16bx_wake_up_dur_t wake_up_dur;
4552 lsm6dsv16bx_free_fall_t free_fall;
4553 int32_t ret;
4554
4555 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4556 if (ret == 0)
4557 {
4558 wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
4559 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4560 }
4561 if (ret == 0)
4562 {
4563 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1);
4564 }
4565
4566 if (ret == 0)
4567 {
4568 free_fall.ff_dur = (uint8_t)val & 0x1FU;
4569 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1);
4570 }
4571
4572 return ret;
4573 }
4574
4575 /**
4576 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get]
4577 *
4578 * @param ctx read / write interface definitions
4579 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
4580 * @retval interface status (MANDATORY: return 0 -> no Error)
4581 *
4582 */
lsm6dsv16bx_ff_time_windows_get(stmdev_ctx_t * ctx,uint8_t * val)4583 int32_t lsm6dsv16bx_ff_time_windows_get(stmdev_ctx_t *ctx, uint8_t *val)
4584 {
4585 lsm6dsv16bx_wake_up_dur_t wake_up_dur;
4586 lsm6dsv16bx_free_fall_t free_fall;
4587 int32_t ret;
4588
4589 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4590 if (ret == 0)
4591 {
4592 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1);
4593 }
4594
4595 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
4596
4597 return ret;
4598 }
4599
4600 /**
4601 * @brief Free fall threshold setting.[set]
4602 *
4603 * @param ctx read / write interface definitions
4604 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
4605 * @retval interface status (MANDATORY: return 0 -> no Error)
4606 *
4607 */
lsm6dsv16bx_ff_thresholds_set(stmdev_ctx_t * ctx,lsm6dsv16bx_ff_thresholds_t val)4608 int32_t lsm6dsv16bx_ff_thresholds_set(stmdev_ctx_t *ctx,
4609 lsm6dsv16bx_ff_thresholds_t val)
4610 {
4611 lsm6dsv16bx_free_fall_t free_fall;
4612 int32_t ret;
4613
4614 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1);
4615 if (ret == 0)
4616 {
4617 free_fall.ff_ths = (uint8_t)val & 0x7U;
4618 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1);
4619 }
4620
4621 return ret;
4622 }
4623
4624 /**
4625 * @brief Free fall threshold setting.[get]
4626 *
4627 * @param ctx read / write interface definitions
4628 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
4629 * @retval interface status (MANDATORY: return 0 -> no Error)
4630 *
4631 */
lsm6dsv16bx_ff_thresholds_get(stmdev_ctx_t * ctx,lsm6dsv16bx_ff_thresholds_t * val)4632 int32_t lsm6dsv16bx_ff_thresholds_get(stmdev_ctx_t *ctx,
4633 lsm6dsv16bx_ff_thresholds_t *val)
4634 {
4635 lsm6dsv16bx_free_fall_t free_fall;
4636 int32_t ret;
4637
4638 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1);
4639
4640 switch (free_fall.ff_ths)
4641 {
4642 case LSM6DSV16BX_156_mg:
4643 *val = LSM6DSV16BX_156_mg;
4644 break;
4645
4646 case LSM6DSV16BX_219_mg:
4647 *val = LSM6DSV16BX_219_mg;
4648 break;
4649
4650 case LSM6DSV16BX_250_mg:
4651 *val = LSM6DSV16BX_250_mg;
4652 break;
4653
4654 case LSM6DSV16BX_312_mg:
4655 *val = LSM6DSV16BX_312_mg;
4656 break;
4657
4658 case LSM6DSV16BX_344_mg:
4659 *val = LSM6DSV16BX_344_mg;
4660 break;
4661
4662 case LSM6DSV16BX_406_mg:
4663 *val = LSM6DSV16BX_406_mg;
4664 break;
4665
4666 case LSM6DSV16BX_469_mg:
4667 *val = LSM6DSV16BX_469_mg;
4668 break;
4669
4670 case LSM6DSV16BX_500_mg:
4671 *val = LSM6DSV16BX_500_mg;
4672 break;
4673
4674 default:
4675 *val = LSM6DSV16BX_156_mg;
4676 break;
4677 }
4678 return ret;
4679 }
4680
4681 /**
4682 * @}
4683 *
4684 */
4685
4686 /**
4687 * @defgroup FIFO
4688 * @brief This section group all the functions concerning the fifo usage
4689 * @{
4690 *
4691 */
4692
4693 /**
4694 * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[set]
4695 *
4696 * @param ctx read / write interface definitions
4697 * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).
4698 * @retval interface status (MANDATORY: return 0 -> no Error)
4699 *
4700 */
lsm6dsv16bx_fifo_watermark_set(stmdev_ctx_t * ctx,uint8_t val)4701 int32_t lsm6dsv16bx_fifo_watermark_set(stmdev_ctx_t *ctx, uint8_t val)
4702 {
4703 lsm6dsv16bx_fifo_ctrl1_t fifo_ctrl1;
4704 int32_t ret;
4705
4706 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
4707
4708 if (ret == 0)
4709 {
4710 fifo_ctrl1.wtm = val;
4711 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
4712 }
4713
4714 return ret;
4715 }
4716
4717 /**
4718 * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[get]
4719 *
4720 * @param ctx read / write interface definitions
4721 * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).
4722 * @retval interface status (MANDATORY: return 0 -> no Error)
4723 *
4724 */
lsm6dsv16bx_fifo_watermark_get(stmdev_ctx_t * ctx,uint8_t * val)4725 int32_t lsm6dsv16bx_fifo_watermark_get(stmdev_ctx_t *ctx, uint8_t *val)
4726 {
4727 lsm6dsv16bx_fifo_ctrl1_t fifo_ctrl1;
4728 int32_t ret;
4729
4730 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
4731 *val = fifo_ctrl1.wtm;
4732
4733 return ret;
4734 }
4735
4736 /**
4737 * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[set]
4738 *
4739 * @param ctx read / write interface definitions
4740 * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.
4741 * @retval interface status (MANDATORY: return 0 -> no Error)
4742 *
4743 */
lsm6dsv16bx_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t * ctx,uint8_t val)4744 int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_set(stmdev_ctx_t *ctx, uint8_t val)
4745 {
4746 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
4747 int32_t ret;
4748
4749 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4750 if (ret == 0)
4751 {
4752 fifo_ctrl2.xl_dualc_batch_from_fsm = val;
4753 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4754 }
4755
4756 return ret;
4757 }
4758
4759 /**
4760 * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[get]
4761 *
4762 * @param ctx read / write interface definitions
4763 * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.
4764 * @retval interface status (MANDATORY: return 0 -> no Error)
4765 *
4766 */
lsm6dsv16bx_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t * ctx,uint8_t * val)4767 int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
4768 {
4769 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
4770 int32_t ret;
4771
4772 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4773 *val = fifo_ctrl2.xl_dualc_batch_from_fsm;
4774
4775 return ret;
4776 }
4777
4778 /**
4779 * @brief It configures the compression algorithm to write non-compressed data at each rate.[set]
4780 *
4781 * @param ctx read / write interface definitions
4782 * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1,
4783 * @retval interface status (MANDATORY: return 0 -> no Error)
4784 *
4785 */
lsm6dsv16bx_fifo_compress_algo_set(stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_compress_algo_t val)4786 int32_t lsm6dsv16bx_fifo_compress_algo_set(stmdev_ctx_t *ctx,
4787 lsm6dsv16bx_fifo_compress_algo_t val)
4788 {
4789 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
4790 int32_t ret;
4791
4792 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4793 if (ret == 0)
4794 {
4795 fifo_ctrl2.uncompr_rate = (uint8_t)val & 0x03U;
4796 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4797 }
4798
4799 return ret;
4800 }
4801
4802 /**
4803 * @brief It configures the compression algorithm to write non-compressed data at each rate.[get]
4804 *
4805 * @param ctx read / write interface definitions
4806 * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1,
4807 * @retval interface status (MANDATORY: return 0 -> no Error)
4808 *
4809 */
lsm6dsv16bx_fifo_compress_algo_get(stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_compress_algo_t * val)4810 int32_t lsm6dsv16bx_fifo_compress_algo_get(stmdev_ctx_t *ctx,
4811 lsm6dsv16bx_fifo_compress_algo_t *val)
4812 {
4813 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
4814 int32_t ret;
4815
4816 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4817
4818 switch (fifo_ctrl2.uncompr_rate)
4819 {
4820 case LSM6DSV16BX_CMP_DISABLE:
4821 *val = LSM6DSV16BX_CMP_DISABLE;
4822 break;
4823
4824 case LSM6DSV16BX_CMP_8_TO_1:
4825 *val = LSM6DSV16BX_CMP_8_TO_1;
4826 break;
4827
4828 case LSM6DSV16BX_CMP_16_TO_1:
4829 *val = LSM6DSV16BX_CMP_16_TO_1;
4830 break;
4831
4832 case LSM6DSV16BX_CMP_32_TO_1:
4833 *val = LSM6DSV16BX_CMP_32_TO_1;
4834 break;
4835
4836 default:
4837 *val = LSM6DSV16BX_CMP_DISABLE;
4838 break;
4839 }
4840 return ret;
4841 }
4842
4843 /**
4844 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
4845 *
4846 * @param ctx read / write interface definitions
4847 * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO.
4848 * @retval interface status (MANDATORY: return 0 -> no Error)
4849 *
4850 */
lsm6dsv16bx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t * ctx,uint8_t val)4851 int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
4852 uint8_t val)
4853 {
4854 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
4855 int32_t ret;
4856
4857 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4858 if (ret == 0)
4859 {
4860 fifo_ctrl2.odr_chg_en = val;
4861 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4862 }
4863
4864 return ret;
4865 }
4866
4867 /**
4868 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
4869 *
4870 * @param ctx read / write interface definitions
4871 * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO.
4872 * @retval interface status (MANDATORY: return 0 -> no Error)
4873 *
4874 */
lsm6dsv16bx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t * ctx,uint8_t * val)4875 int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
4876 uint8_t *val)
4877 {
4878 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
4879 int32_t ret;
4880
4881 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4882 *val = fifo_ctrl2.odr_chg_en;
4883
4884 return ret;
4885 }
4886
4887 /**
4888 * @brief Enables/Disables compression algorithm runtime.[set]
4889 *
4890 * @param ctx read / write interface definitions
4891 * @param val Enables/Disables compression algorithm runtime.
4892 * @retval interface status (MANDATORY: return 0 -> no Error)
4893 *
4894 */
lsm6dsv16bx_fifo_compress_algo_real_time_set(stmdev_ctx_t * ctx,uint8_t val)4895 int32_t lsm6dsv16bx_fifo_compress_algo_real_time_set(stmdev_ctx_t *ctx,
4896 uint8_t val)
4897 {
4898 lsm6dsv16bx_emb_func_en_b_t emb_func_en_b;
4899 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
4900
4901 int32_t ret;
4902
4903 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4904 if (ret == 0)
4905 {
4906 fifo_ctrl2.fifo_compr_rt_en = val;
4907 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4908 }
4909
4910 if (ret == 0)
4911 {
4912 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
4913 }
4914 if (ret == 0)
4915 {
4916 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
4917 }
4918 if (ret == 0)
4919 {
4920 emb_func_en_b.fifo_compr_en = val;
4921 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
4922 }
4923
4924 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
4925
4926 return ret;
4927 }
4928
4929 /**
4930 * @brief Enables/Disables compression algorithm runtime.[get]
4931 *
4932 * @param ctx read / write interface definitions
4933 * @param val Enables/Disables compression algorithm runtime.
4934 * @retval interface status (MANDATORY: return 0 -> no Error)
4935 *
4936 */
lsm6dsv16bx_fifo_compress_algo_real_time_get(stmdev_ctx_t * ctx,uint8_t * val)4937 int32_t lsm6dsv16bx_fifo_compress_algo_real_time_get(stmdev_ctx_t *ctx,
4938 uint8_t *val)
4939 {
4940 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
4941 int32_t ret;
4942
4943 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4944
4945 *val = fifo_ctrl2.fifo_compr_rt_en;
4946
4947 return ret;
4948 }
4949
4950 /**
4951 * @brief Sensing chain FIFO stop values memorization at threshold level.[set]
4952 *
4953 * @param ctx read / write interface definitions
4954 * @param val Sensing chain FIFO stop values memorization at threshold level.
4955 * @retval interface status (MANDATORY: return 0 -> no Error)
4956 *
4957 */
lsm6dsv16bx_fifo_stop_on_wtm_set(stmdev_ctx_t * ctx,uint8_t val)4958 int32_t lsm6dsv16bx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
4959 {
4960 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
4961 int32_t ret;
4962
4963 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4964 if (ret == 0)
4965 {
4966 fifo_ctrl2.stop_on_wtm = val;
4967 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4968 }
4969
4970 return ret;
4971 }
4972
4973 /**
4974 * @brief Sensing chain FIFO stop values memorization at threshold level.[get]
4975 *
4976 * @param ctx read / write interface definitions
4977 * @param val Sensing chain FIFO stop values memorization at threshold level.
4978 * @retval interface status (MANDATORY: return 0 -> no Error)
4979 *
4980 */
lsm6dsv16bx_fifo_stop_on_wtm_get(stmdev_ctx_t * ctx,uint8_t * val)4981 int32_t lsm6dsv16bx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
4982 {
4983 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
4984 int32_t ret;
4985
4986 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4987 *val = fifo_ctrl2.stop_on_wtm;
4988
4989 return ret;
4990 }
4991
4992 /**
4993 * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[set]
4994 *
4995 * @param ctx read / write interface definitions
4996 * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz,
4997 * @retval interface status (MANDATORY: return 0 -> no Error)
4998 *
4999 */
lsm6dsv16bx_fifo_xl_batch_set(stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_xl_batch_t val)5000 int32_t lsm6dsv16bx_fifo_xl_batch_set(stmdev_ctx_t *ctx,
5001 lsm6dsv16bx_fifo_xl_batch_t val)
5002 {
5003 lsm6dsv16bx_fifo_ctrl3_t fifo_ctrl3;
5004 int32_t ret;
5005
5006 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
5007 if (ret == 0)
5008 {
5009 fifo_ctrl3.bdr_xl = (uint8_t)val & 0xFU;
5010 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
5011 }
5012
5013 return ret;
5014 }
5015
5016 /**
5017 * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[get]
5018 *
5019 * @param ctx read / write interface definitions
5020 * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz,
5021 * @retval interface status (MANDATORY: return 0 -> no Error)
5022 *
5023 */
lsm6dsv16bx_fifo_xl_batch_get(stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_xl_batch_t * val)5024 int32_t lsm6dsv16bx_fifo_xl_batch_get(stmdev_ctx_t *ctx,
5025 lsm6dsv16bx_fifo_xl_batch_t *val)
5026 {
5027 lsm6dsv16bx_fifo_ctrl3_t fifo_ctrl3;
5028 int32_t ret;
5029
5030 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
5031 switch (fifo_ctrl3.bdr_xl)
5032 {
5033 case LSM6DSV16BX_XL_NOT_BATCHED:
5034 *val = LSM6DSV16BX_XL_NOT_BATCHED;
5035 break;
5036
5037 case LSM6DSV16BX_XL_BATCHED_AT_1Hz875:
5038 *val = LSM6DSV16BX_XL_BATCHED_AT_1Hz875;
5039 break;
5040
5041 case LSM6DSV16BX_XL_BATCHED_AT_7Hz5:
5042 *val = LSM6DSV16BX_XL_BATCHED_AT_7Hz5;
5043 break;
5044
5045 case LSM6DSV16BX_XL_BATCHED_AT_15Hz:
5046 *val = LSM6DSV16BX_XL_BATCHED_AT_15Hz;
5047 break;
5048
5049 case LSM6DSV16BX_XL_BATCHED_AT_30Hz:
5050 *val = LSM6DSV16BX_XL_BATCHED_AT_30Hz;
5051 break;
5052
5053 case LSM6DSV16BX_XL_BATCHED_AT_60Hz:
5054 *val = LSM6DSV16BX_XL_BATCHED_AT_60Hz;
5055 break;
5056
5057 case LSM6DSV16BX_XL_BATCHED_AT_120Hz:
5058 *val = LSM6DSV16BX_XL_BATCHED_AT_120Hz;
5059 break;
5060
5061 case LSM6DSV16BX_XL_BATCHED_AT_240Hz:
5062 *val = LSM6DSV16BX_XL_BATCHED_AT_240Hz;
5063 break;
5064
5065 case LSM6DSV16BX_XL_BATCHED_AT_480Hz:
5066 *val = LSM6DSV16BX_XL_BATCHED_AT_480Hz;
5067 break;
5068
5069 case LSM6DSV16BX_XL_BATCHED_AT_960Hz:
5070 *val = LSM6DSV16BX_XL_BATCHED_AT_960Hz;
5071 break;
5072
5073 case LSM6DSV16BX_XL_BATCHED_AT_1920Hz:
5074 *val = LSM6DSV16BX_XL_BATCHED_AT_1920Hz;
5075 break;
5076
5077 case LSM6DSV16BX_XL_BATCHED_AT_3840Hz:
5078 *val = LSM6DSV16BX_XL_BATCHED_AT_3840Hz;
5079 break;
5080
5081 case LSM6DSV16BX_XL_BATCHED_AT_7680Hz:
5082 *val = LSM6DSV16BX_XL_BATCHED_AT_7680Hz;
5083 break;
5084
5085 default:
5086 *val = LSM6DSV16BX_XL_NOT_BATCHED;
5087 break;
5088 }
5089 return ret;
5090 }
5091
5092 /**
5093 * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[set]
5094 *
5095 * @param ctx read / write interface definitions
5096 * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz,
5097 * @retval interface status (MANDATORY: return 0 -> no Error)
5098 *
5099 */
lsm6dsv16bx_fifo_gy_batch_set(stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_gy_batch_t val)5100 int32_t lsm6dsv16bx_fifo_gy_batch_set(stmdev_ctx_t *ctx,
5101 lsm6dsv16bx_fifo_gy_batch_t val)
5102 {
5103 lsm6dsv16bx_fifo_ctrl3_t fifo_ctrl3;
5104 int32_t ret;
5105
5106 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
5107 if (ret == 0)
5108 {
5109 fifo_ctrl3.bdr_gy = (uint8_t)val & 0xFU;
5110 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
5111 }
5112
5113 return ret;
5114 }
5115
5116 /**
5117 * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[get]
5118 *
5119 * @param ctx read / write interface definitions
5120 * @param val XL_NOT_BATCHED, XL_BATCHED_AT_1Hz875, XL_BATCHED_AT_7Hz5, XL_BATCHED_AT_15Hz, XL_BATCHED_AT_30Hz, XL_BATCHED_AT_60Hz, XL_BATCHED_AT_120Hz, XL_BATCHED_AT_240Hz, XL_BATCHED_AT_480Hz, XL_BATCHED_AT_960Hz, XL_BATCHED_AT_1920Hz, XL_BATCHED_AT_3840Hz, XL_BATCHED_AT_7680Hz,
5121 * @retval interface status (MANDATORY: return 0 -> no Error)
5122 *
5123 */
lsm6dsv16bx_fifo_gy_batch_get(stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_gy_batch_t * val)5124 int32_t lsm6dsv16bx_fifo_gy_batch_get(stmdev_ctx_t *ctx,
5125 lsm6dsv16bx_fifo_gy_batch_t *val)
5126 {
5127 lsm6dsv16bx_fifo_ctrl3_t fifo_ctrl3;
5128 int32_t ret;
5129
5130 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
5131 switch (fifo_ctrl3.bdr_gy)
5132 {
5133 case LSM6DSV16BX_GY_NOT_BATCHED:
5134 *val = LSM6DSV16BX_GY_NOT_BATCHED;
5135 break;
5136
5137 case LSM6DSV16BX_GY_BATCHED_AT_1Hz875:
5138 *val = LSM6DSV16BX_GY_BATCHED_AT_1Hz875;
5139 break;
5140
5141 case LSM6DSV16BX_GY_BATCHED_AT_7Hz5:
5142 *val = LSM6DSV16BX_GY_BATCHED_AT_7Hz5;
5143 break;
5144
5145 case LSM6DSV16BX_GY_BATCHED_AT_15Hz:
5146 *val = LSM6DSV16BX_GY_BATCHED_AT_15Hz;
5147 break;
5148
5149 case LSM6DSV16BX_GY_BATCHED_AT_30Hz:
5150 *val = LSM6DSV16BX_GY_BATCHED_AT_30Hz;
5151 break;
5152
5153 case LSM6DSV16BX_GY_BATCHED_AT_60Hz:
5154 *val = LSM6DSV16BX_GY_BATCHED_AT_60Hz;
5155 break;
5156
5157 case LSM6DSV16BX_GY_BATCHED_AT_120Hz:
5158 *val = LSM6DSV16BX_GY_BATCHED_AT_120Hz;
5159 break;
5160
5161 case LSM6DSV16BX_GY_BATCHED_AT_240Hz:
5162 *val = LSM6DSV16BX_GY_BATCHED_AT_240Hz;
5163 break;
5164
5165 case LSM6DSV16BX_GY_BATCHED_AT_480Hz:
5166 *val = LSM6DSV16BX_GY_BATCHED_AT_480Hz;
5167 break;
5168
5169 case LSM6DSV16BX_GY_BATCHED_AT_960Hz:
5170 *val = LSM6DSV16BX_GY_BATCHED_AT_960Hz;
5171 break;
5172
5173 case LSM6DSV16BX_GY_BATCHED_AT_1920Hz:
5174 *val = LSM6DSV16BX_GY_BATCHED_AT_1920Hz;
5175 break;
5176
5177 case LSM6DSV16BX_GY_BATCHED_AT_3840Hz:
5178 *val = LSM6DSV16BX_GY_BATCHED_AT_3840Hz;
5179 break;
5180
5181 case LSM6DSV16BX_GY_BATCHED_AT_7680Hz:
5182 *val = LSM6DSV16BX_GY_BATCHED_AT_7680Hz;
5183 break;
5184
5185 default:
5186 *val = LSM6DSV16BX_GY_NOT_BATCHED;
5187 break;
5188 }
5189 return ret;
5190 }
5191
5192 /**
5193 * @brief FIFO mode selection.[set]
5194 *
5195 * @param ctx read / write interface definitions
5196 * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
5197 * @retval interface status (MANDATORY: return 0 -> no Error)
5198 *
5199 */
lsm6dsv16bx_fifo_mode_set(stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_mode_t val)5200 int32_t lsm6dsv16bx_fifo_mode_set(stmdev_ctx_t *ctx,
5201 lsm6dsv16bx_fifo_mode_t val)
5202 {
5203 lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4;
5204 int32_t ret;
5205
5206 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5207 if (ret == 0)
5208 {
5209 fifo_ctrl4.fifo_mode = (uint8_t)val & 0x07U;
5210 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5211 }
5212
5213 return ret;
5214 }
5215
5216 /**
5217 * @brief FIFO mode selection.[get]
5218 *
5219 * @param ctx read / write interface definitions
5220 * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
5221 * @retval interface status (MANDATORY: return 0 -> no Error)
5222 *
5223 */
lsm6dsv16bx_fifo_mode_get(stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_mode_t * val)5224 int32_t lsm6dsv16bx_fifo_mode_get(stmdev_ctx_t *ctx,
5225 lsm6dsv16bx_fifo_mode_t *val)
5226 {
5227 lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4;
5228 int32_t ret;
5229
5230 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5231 switch (fifo_ctrl4.fifo_mode)
5232 {
5233 case LSM6DSV16BX_BYPASS_MODE:
5234 *val = LSM6DSV16BX_BYPASS_MODE;
5235 break;
5236
5237 case LSM6DSV16BX_FIFO_MODE:
5238 *val = LSM6DSV16BX_FIFO_MODE;
5239 break;
5240
5241 case LSM6DSV16BX_STREAM_WTM_TO_FULL_MODE:
5242 *val = LSM6DSV16BX_STREAM_WTM_TO_FULL_MODE;
5243 break;
5244
5245 case LSM6DSV16BX_STREAM_TO_FIFO_MODE:
5246 *val = LSM6DSV16BX_STREAM_TO_FIFO_MODE;
5247 break;
5248
5249 case LSM6DSV16BX_BYPASS_TO_STREAM_MODE:
5250 *val = LSM6DSV16BX_BYPASS_TO_STREAM_MODE;
5251 break;
5252
5253 case LSM6DSV16BX_STREAM_MODE:
5254 *val = LSM6DSV16BX_STREAM_MODE;
5255 break;
5256
5257 case LSM6DSV16BX_BYPASS_TO_FIFO_MODE:
5258 *val = LSM6DSV16BX_BYPASS_TO_FIFO_MODE;
5259 break;
5260
5261 default:
5262 *val = LSM6DSV16BX_BYPASS_MODE;
5263 break;
5264 }
5265 return ret;
5266 }
5267
5268 /**
5269 * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[set]
5270 *
5271 * @param ctx read / write interface definitions
5272 * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz,
5273 * @retval interface status (MANDATORY: return 0 -> no Error)
5274 *
5275 */
lsm6dsv16bx_fifo_temp_batch_set(stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_temp_batch_t val)5276 int32_t lsm6dsv16bx_fifo_temp_batch_set(stmdev_ctx_t *ctx,
5277 lsm6dsv16bx_fifo_temp_batch_t val)
5278 {
5279 lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4;
5280 int32_t ret;
5281
5282 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5283 if (ret == 0)
5284 {
5285 fifo_ctrl4.odr_t_batch = (uint8_t)val & 0x03U;
5286 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5287 }
5288
5289 return ret;
5290 }
5291
5292 /**
5293 * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[get]
5294 *
5295 * @param ctx read / write interface definitions
5296 * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz,
5297 * @retval interface status (MANDATORY: return 0 -> no Error)
5298 *
5299 */
lsm6dsv16bx_fifo_temp_batch_get(stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_temp_batch_t * val)5300 int32_t lsm6dsv16bx_fifo_temp_batch_get(stmdev_ctx_t *ctx,
5301 lsm6dsv16bx_fifo_temp_batch_t *val)
5302 {
5303 lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4;
5304 int32_t ret;
5305
5306 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5307 switch (fifo_ctrl4.odr_t_batch)
5308 {
5309 case LSM6DSV16BX_TEMP_NOT_BATCHED:
5310 *val = LSM6DSV16BX_TEMP_NOT_BATCHED;
5311 break;
5312
5313 case LSM6DSV16BX_TEMP_BATCHED_AT_1Hz875:
5314 *val = LSM6DSV16BX_TEMP_BATCHED_AT_1Hz875;
5315 break;
5316
5317 case LSM6DSV16BX_TEMP_BATCHED_AT_15Hz:
5318 *val = LSM6DSV16BX_TEMP_BATCHED_AT_15Hz;
5319 break;
5320
5321 case LSM6DSV16BX_TEMP_BATCHED_AT_60Hz:
5322 *val = LSM6DSV16BX_TEMP_BATCHED_AT_60Hz;
5323 break;
5324
5325 default:
5326 *val = LSM6DSV16BX_TEMP_NOT_BATCHED;
5327 break;
5328 }
5329 return ret;
5330 }
5331
5332 /**
5333 * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[set]
5334 *
5335 * @param ctx read / write interface definitions
5336 * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32,
5337 * @retval interface status (MANDATORY: return 0 -> no Error)
5338 *
5339 */
lsm6dsv16bx_fifo_timestamp_batch_set(stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_timestamp_batch_t val)5340 int32_t lsm6dsv16bx_fifo_timestamp_batch_set(stmdev_ctx_t *ctx,
5341 lsm6dsv16bx_fifo_timestamp_batch_t val)
5342 {
5343 lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4;
5344 int32_t ret;
5345
5346 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5347 if (ret == 0)
5348 {
5349 fifo_ctrl4.dec_ts_batch = (uint8_t)val & 0x3U;
5350 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5351 }
5352
5353 return ret;
5354 }
5355
5356 /**
5357 * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[get]
5358 *
5359 * @param ctx read / write interface definitions
5360 * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32,
5361 * @retval interface status (MANDATORY: return 0 -> no Error)
5362 *
5363 */
lsm6dsv16bx_fifo_timestamp_batch_get(stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_timestamp_batch_t * val)5364 int32_t lsm6dsv16bx_fifo_timestamp_batch_get(stmdev_ctx_t *ctx,
5365 lsm6dsv16bx_fifo_timestamp_batch_t *val)
5366 {
5367 lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4;
5368 int32_t ret;
5369
5370 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5371 switch (fifo_ctrl4.dec_ts_batch)
5372 {
5373 case LSM6DSV16BX_TMSTMP_NOT_BATCHED:
5374 *val = LSM6DSV16BX_TMSTMP_NOT_BATCHED;
5375 break;
5376
5377 case LSM6DSV16BX_TMSTMP_DEC_1:
5378 *val = LSM6DSV16BX_TMSTMP_DEC_1;
5379 break;
5380
5381 case LSM6DSV16BX_TMSTMP_DEC_8:
5382 *val = LSM6DSV16BX_TMSTMP_DEC_8;
5383 break;
5384
5385 case LSM6DSV16BX_TMSTMP_DEC_32:
5386 *val = LSM6DSV16BX_TMSTMP_DEC_32;
5387 break;
5388
5389 default:
5390 *val = LSM6DSV16BX_TMSTMP_NOT_BATCHED;
5391 break;
5392 }
5393 return ret;
5394 }
5395
5396 /**
5397 * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[set]
5398 *
5399 * @param ctx read / write interface definitions
5400 * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.
5401 * @retval interface status (MANDATORY: return 0 -> no Error)
5402 *
5403 */
lsm6dsv16bx_fifo_batch_counter_threshold_set(stmdev_ctx_t * ctx,uint16_t val)5404 int32_t lsm6dsv16bx_fifo_batch_counter_threshold_set(stmdev_ctx_t *ctx,
5405 uint16_t val)
5406 {
5407 uint8_t buff[2];
5408 int32_t ret;
5409
5410 buff[1] = (uint8_t)(val / 256U);
5411 buff[0] = (uint8_t)(val - (buff[1] * 256U));
5412 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&buff[0], 2);
5413
5414 return ret;
5415 }
5416
5417 /**
5418 * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[get]
5419 *
5420 * @param ctx read / write interface definitions
5421 * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.
5422 * @retval interface status (MANDATORY: return 0 -> no Error)
5423 *
5424 */
lsm6dsv16bx_fifo_batch_counter_threshold_get(stmdev_ctx_t * ctx,uint16_t * val)5425 int32_t lsm6dsv16bx_fifo_batch_counter_threshold_get(stmdev_ctx_t *ctx,
5426 uint16_t *val)
5427 {
5428 uint8_t buff[2];
5429 int32_t ret;
5430
5431 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, &buff[0], 2);
5432 *val = buff[1];
5433 *val = (*val * 256U) + buff[0];
5434
5435 return ret;
5436 }
5437
5438 /**
5439 * @brief Enables AH_QVAR batching in FIFO.[set]
5440 *
5441 * @param ctx read / write interface definitions
5442 * @param val Enables AH_QVAR batching in FIFO.
5443 * @retval interface status (MANDATORY: return 0 -> no Error)
5444 *
5445 */
lsm6dsv16bx_fifo_batch_ah_qvar_set(stmdev_ctx_t * ctx,uint8_t val)5446 int32_t lsm6dsv16bx_fifo_batch_ah_qvar_set(stmdev_ctx_t *ctx, uint8_t val)
5447 {
5448 lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1;
5449 int32_t ret;
5450
5451 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5452 if (ret == 0)
5453 {
5454 counter_bdr_reg1.ah_qvar_batch_en = val;
5455 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5456 }
5457
5458 return ret;
5459 }
5460
5461 /**
5462 * @brief Enables AH_QVAR batching in FIFO.[get]
5463 *
5464 * @param ctx read / write interface definitions
5465 * @param val Enables AH_QVAR batching in FIFO.
5466 * @retval interface status (MANDATORY: return 0 -> no Error)
5467 *
5468 */
lsm6dsv16bx_fifo_batch_ah_qvar_get(stmdev_ctx_t * ctx,uint8_t * val)5469 int32_t lsm6dsv16bx_fifo_batch_ah_qvar_get(stmdev_ctx_t *ctx, uint8_t *val)
5470 {
5471 lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1;
5472 int32_t ret;
5473
5474 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5475 *val = counter_bdr_reg1.ah_qvar_batch_en;
5476
5477 return ret;
5478 }
5479
5480 /**
5481 * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[set]
5482 *
5483 * @param ctx read / write interface definitions
5484 * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT,
5485 * @retval interface status (MANDATORY: return 0 -> no Error)
5486 *
5487 */
lsm6dsv16bx_fifo_batch_cnt_event_set(stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_batch_cnt_event_t val)5488 int32_t lsm6dsv16bx_fifo_batch_cnt_event_set(stmdev_ctx_t *ctx,
5489 lsm6dsv16bx_fifo_batch_cnt_event_t val)
5490 {
5491 lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1;
5492 int32_t ret;
5493
5494 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5495
5496 if (ret == 0)
5497 {
5498 counter_bdr_reg1.trig_counter_bdr = (uint8_t)val & 0x03U;
5499 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5500 }
5501
5502 return ret;
5503 }
5504
5505 /**
5506 * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope and EIS gyroscope.[get]
5507 *
5508 * @param ctx read / write interface definitions
5509 * @param val XL_BATCH_EVENT, GY_BATCH_EVENT, GY_EIS_BATCH_EVENT,
5510 * @retval interface status (MANDATORY: return 0 -> no Error)
5511 *
5512 */
lsm6dsv16bx_fifo_batch_cnt_event_get(stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_batch_cnt_event_t * val)5513 int32_t lsm6dsv16bx_fifo_batch_cnt_event_get(stmdev_ctx_t *ctx,
5514 lsm6dsv16bx_fifo_batch_cnt_event_t *val)
5515 {
5516 lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1;
5517 int32_t ret;
5518
5519 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5520 switch (counter_bdr_reg1.trig_counter_bdr)
5521 {
5522 case LSM6DSV16BX_XL_BATCH_EVENT:
5523 *val = LSM6DSV16BX_XL_BATCH_EVENT;
5524 break;
5525
5526 case LSM6DSV16BX_GY_BATCH_EVENT:
5527 *val = LSM6DSV16BX_GY_BATCH_EVENT;
5528 break;
5529
5530 case LSM6DSV16BX_GY_EIS_BATCH_EVENT:
5531 *val = LSM6DSV16BX_GY_EIS_BATCH_EVENT;
5532 break;
5533
5534 default:
5535 *val = LSM6DSV16BX_XL_BATCH_EVENT;
5536 break;
5537 }
5538 return ret;
5539 }
5540
5541 /**
5542 * @brief Batching in FIFO buffer of SFLP.[set]
5543 *
5544 * @param ctx read / write interface definitions
5545 * @param val Batching in FIFO buffer of SFLP values.
5546 * @retval interface status (MANDATORY: return 0 -> no Error)
5547 *
5548 */
lsm6dsv16bx_fifo_sflp_batch_set(stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_sflp_raw_t val)5549 int32_t lsm6dsv16bx_fifo_sflp_batch_set(stmdev_ctx_t *ctx,
5550 lsm6dsv16bx_fifo_sflp_raw_t val)
5551 {
5552 lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5553 int32_t ret;
5554
5555 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
5556 if (ret == 0)
5557 {
5558 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5559 emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation;
5560 emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity;
5561 emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias;
5562 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A,
5563 (uint8_t *)&emb_func_fifo_en_a, 1);
5564 }
5565
5566 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
5567
5568 return ret;
5569 }
5570
5571 /**
5572 * @brief Batching in FIFO buffer of SFLP.[get]
5573 *
5574 * @param ctx read / write interface definitions
5575 * @param val Batching in FIFO buffer of SFLP values.
5576 * @retval interface status (MANDATORY: return 0 -> no Error)
5577 *
5578 */
lsm6dsv16bx_fifo_sflp_batch_get(stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_sflp_raw_t * val)5579 int32_t lsm6dsv16bx_fifo_sflp_batch_get(stmdev_ctx_t *ctx,
5580 lsm6dsv16bx_fifo_sflp_raw_t *val)
5581 {
5582 lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5583 int32_t ret;
5584
5585 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
5586 if (ret == 0)
5587 {
5588 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5589
5590 val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en;
5591 val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en;
5592 val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en;
5593 }
5594
5595 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
5596
5597 return ret;
5598 }
5599
5600 /**
5601 * @brief Status of FIFO.[get]
5602 *
5603 * @param ctx read / write interface definitions
5604 * @param val Status of FIFO (level and flags).
5605 * @retval interface status (MANDATORY: return 0 -> no Error)
5606 *
5607 */
lsm6dsv16bx_fifo_status_get(stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_status_t * val)5608 int32_t lsm6dsv16bx_fifo_status_get(stmdev_ctx_t *ctx,
5609 lsm6dsv16bx_fifo_status_t *val)
5610 {
5611 uint8_t buff[2];
5612 lsm6dsv16bx_fifo_status2_t status;
5613 int32_t ret;
5614
5615 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_STATUS1, (uint8_t *)&buff[0], 2);
5616 bytecpy((uint8_t *)&status, &buff[1]);
5617
5618 val->fifo_bdr = status.counter_bdr_ia;
5619 val->fifo_ovr = status.fifo_ovr_ia;
5620 val->fifo_full = status.fifo_full_ia;
5621 val->fifo_th = status.fifo_wtm_ia;
5622
5623 val->fifo_level = (uint16_t)buff[1] & 0x01U;
5624 val->fifo_level = (val->fifo_level * 256U) + buff[0];
5625
5626 return ret;
5627 }
5628
5629 /**
5630 * @brief FIFO data output[get]
5631 *
5632 * @param ctx read / write interface definitions
5633 * @param val FIFO_EMPTY, GY_NC_TAG, XL_NC_TAG, TIMESTAMP_TAG,
5634 TEMPERATURE_TAG, CFG_CHANGE_TAG, XL_NC_T_2_TAG,
5635 XL_NC_T_1_TAG, XL_2XC_TAG, XL_3XC_TAG, GY_NC_T_2_TAG,
5636 GY_NC_T_1_TAG, GY_2XC_TAG, GY_3XC_TAG, STEP_COUNTER_TAG,
5637 SFLP_GAME_ROTATION_VECTOR_TAG, SFLP_GYROSCOPE_BIAS_TAG,
5638 SFLP_GRAVITY_VECTOR_TAG, MLC_RESULT_TAG,
5639 MLC_FILTER, MLC_FEATURE, XL_DUAL_CORE, AH_QVAR,
5640 * @retval interface status (MANDATORY: return 0 -> no Error)
5641 *
5642 */
lsm6dsv16bx_fifo_out_raw_get(stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_out_raw_t * val)5643 int32_t lsm6dsv16bx_fifo_out_raw_get(stmdev_ctx_t *ctx,
5644 lsm6dsv16bx_fifo_out_raw_t *val)
5645 {
5646 lsm6dsv16bx_fifo_data_out_tag_t fifo_data_out_tag;
5647 uint8_t buff[7];
5648 int32_t ret;
5649
5650 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_DATA_OUT_TAG, buff, 7);
5651 bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]);
5652
5653 switch (fifo_data_out_tag.tag_sensor)
5654 {
5655 case LSM6DSV16BX_FIFO_EMPTY:
5656 val->tag = LSM6DSV16BX_FIFO_EMPTY;
5657 break;
5658
5659 case LSM6DSV16BX_GY_NC_TAG:
5660 val->tag = LSM6DSV16BX_GY_NC_TAG;
5661 break;
5662
5663 case LSM6DSV16BX_XL_NC_TAG:
5664 val->tag = LSM6DSV16BX_XL_NC_TAG;
5665 break;
5666
5667 case LSM6DSV16BX_TIMESTAMP_TAG:
5668 val->tag = LSM6DSV16BX_TIMESTAMP_TAG;
5669 break;
5670
5671 case LSM6DSV16BX_TEMPERATURE_TAG:
5672 val->tag = LSM6DSV16BX_TEMPERATURE_TAG;
5673 break;
5674
5675 case LSM6DSV16BX_CFG_CHANGE_TAG:
5676 val->tag = LSM6DSV16BX_CFG_CHANGE_TAG;
5677 break;
5678
5679 case LSM6DSV16BX_XL_NC_T_2_TAG:
5680 val->tag = LSM6DSV16BX_XL_NC_T_2_TAG;
5681 break;
5682
5683 case LSM6DSV16BX_XL_NC_T_1_TAG:
5684 val->tag = LSM6DSV16BX_XL_NC_T_1_TAG;
5685 break;
5686
5687 case LSM6DSV16BX_XL_2XC_TAG:
5688 val->tag = LSM6DSV16BX_XL_2XC_TAG;
5689 break;
5690
5691 case LSM6DSV16BX_XL_3XC_TAG:
5692 val->tag = LSM6DSV16BX_XL_3XC_TAG;
5693 break;
5694
5695 case LSM6DSV16BX_GY_NC_T_2_TAG:
5696 val->tag = LSM6DSV16BX_GY_NC_T_2_TAG;
5697 break;
5698
5699 case LSM6DSV16BX_GY_NC_T_1_TAG:
5700 val->tag = LSM6DSV16BX_GY_NC_T_1_TAG;
5701 break;
5702
5703 case LSM6DSV16BX_GY_2XC_TAG:
5704 val->tag = LSM6DSV16BX_GY_2XC_TAG;
5705 break;
5706
5707 case LSM6DSV16BX_GY_3XC_TAG:
5708 val->tag = LSM6DSV16BX_GY_3XC_TAG;
5709 break;
5710
5711 case LSM6DSV16BX_STEP_COUNTER_TAG:
5712 val->tag = LSM6DSV16BX_STEP_COUNTER_TAG;
5713 break;
5714
5715 case LSM6DSV16BX_MLC_RESULT_TAG:
5716 val->tag = LSM6DSV16BX_MLC_RESULT_TAG;
5717 break;
5718
5719 case LSM6DSV16BX_SFLP_GAME_ROTATION_VECTOR_TAG:
5720 val->tag = LSM6DSV16BX_SFLP_GAME_ROTATION_VECTOR_TAG;
5721 break;
5722
5723 case LSM6DSV16BX_SFLP_GYROSCOPE_BIAS_TAG:
5724 val->tag = LSM6DSV16BX_SFLP_GYROSCOPE_BIAS_TAG;
5725 break;
5726
5727 case LSM6DSV16BX_SFLP_GRAVITY_VECTOR_TAG:
5728 val->tag = LSM6DSV16BX_SFLP_GRAVITY_VECTOR_TAG;
5729 break;
5730
5731 case LSM6DSV16BX_MLC_FILTER:
5732 val->tag = LSM6DSV16BX_MLC_FILTER;
5733 break;
5734
5735 case LSM6DSV16BX_MLC_FEATURE:
5736 val->tag = LSM6DSV16BX_MLC_FEATURE;
5737 break;
5738
5739 case LSM6DSV16BX_XL_DUAL_CORE:
5740 val->tag = LSM6DSV16BX_XL_DUAL_CORE;
5741 break;
5742
5743 case LSM6DSV16BX_AH_QVAR:
5744 val->tag = LSM6DSV16BX_AH_QVAR;
5745 break;
5746
5747 default:
5748 val->tag = LSM6DSV16BX_FIFO_EMPTY;
5749 break;
5750 }
5751
5752 val->cnt = fifo_data_out_tag.tag_cnt;
5753
5754 val->data[0] = buff[1];
5755 val->data[1] = buff[2];
5756 val->data[2] = buff[3];
5757 val->data[3] = buff[4];
5758 val->data[4] = buff[5];
5759 val->data[5] = buff[6];
5760
5761 return ret;
5762 }
5763
5764 /**
5765 * @brief Batching in FIFO buffer of step counter value.[set]
5766 *
5767 * @param ctx read / write interface definitions
5768 * @param val Batching in FIFO buffer of step counter value.
5769 * @retval interface status (MANDATORY: return 0 -> no Error)
5770 *
5771 */
lsm6dsv16bx_fifo_stpcnt_batch_set(stmdev_ctx_t * ctx,uint8_t val)5772 int32_t lsm6dsv16bx_fifo_stpcnt_batch_set(stmdev_ctx_t *ctx, uint8_t val)
5773 {
5774 lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5775 int32_t ret;
5776
5777 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
5778 if (ret == 0)
5779 {
5780 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5781 }
5782
5783 if (ret == 0)
5784 {
5785 emb_func_fifo_en_a.step_counter_fifo_en = val;
5786 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5787 }
5788
5789 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
5790
5791 return ret;
5792 }
5793
5794 /**
5795 * @brief Batching in FIFO buffer of step counter value.[get]
5796 *
5797 * @param ctx read / write interface definitions
5798 * @param val Batching in FIFO buffer of step counter value.
5799 * @retval interface status (MANDATORY: return 0 -> no Error)
5800 *
5801 */
lsm6dsv16bx_fifo_stpcnt_batch_get(stmdev_ctx_t * ctx,uint8_t * val)5802 int32_t lsm6dsv16bx_fifo_stpcnt_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
5803 {
5804 lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5805 int32_t ret;
5806
5807 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
5808 if (ret == 0)
5809 {
5810 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5811 }
5812
5813 *val = emb_func_fifo_en_a.step_counter_fifo_en;
5814
5815 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
5816
5817
5818 return ret;
5819 }
5820
5821 /**
5822 * @brief Batching in FIFO buffer of machine learning core results.[set]
5823 *
5824 * @param ctx read / write interface definitions
5825 * @param val Batching in FIFO buffer of machine learning core results.
5826 * @retval interface status (MANDATORY: return 0 -> no Error)
5827 *
5828 */
lsm6dsv16bx_fifo_mlc_batch_set(stmdev_ctx_t * ctx,uint8_t val)5829 int32_t lsm6dsv16bx_fifo_mlc_batch_set(stmdev_ctx_t *ctx, uint8_t val)
5830 {
5831 lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5832 int32_t ret;
5833
5834 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
5835 if (ret == 0)
5836 {
5837 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5838 }
5839
5840 if (ret == 0)
5841 {
5842 emb_func_fifo_en_a.mlc_fifo_en = val;
5843 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5844 }
5845
5846 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
5847
5848 return ret;
5849 }
5850
5851 /**
5852 * @brief Batching in FIFO buffer of machine learning core results.[get]
5853 *
5854 * @param ctx read / write interface definitions
5855 * @param val Batching in FIFO buffer of machine learning core results.
5856 * @retval interface status (MANDATORY: return 0 -> no Error)
5857 *
5858 */
lsm6dsv16bx_fifo_mlc_batch_get(stmdev_ctx_t * ctx,uint8_t * val)5859 int32_t lsm6dsv16bx_fifo_mlc_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
5860 {
5861 lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5862 int32_t ret;
5863
5864 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
5865 if (ret == 0)
5866 {
5867 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5868 }
5869
5870 *val = emb_func_fifo_en_a.mlc_fifo_en;
5871
5872 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
5873
5874 return ret;
5875 }
5876
5877 /**
5878 * @brief Enables batching in FIFO buffer of machine learning core filters and features.[set]
5879 *
5880 * @param ctx read / write interface definitions
5881 * @param val Enables batching in FIFO buffer of machine learning core filters and features.
5882 * @retval interface status (MANDATORY: return 0 -> no Error)
5883 *
5884 */
lsm6dsv16bx_fifo_mlc_filt_batch_set(stmdev_ctx_t * ctx,uint8_t val)5885 int32_t lsm6dsv16bx_fifo_mlc_filt_batch_set(stmdev_ctx_t *ctx, uint8_t val)
5886 {
5887 lsm6dsv16bx_emb_func_fifo_en_b_t emb_func_fifo_en_b;
5888 int32_t ret;
5889
5890 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
5891 if (ret == 0)
5892 {
5893 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1);
5894 }
5895
5896 if (ret == 0)
5897 {
5898 emb_func_fifo_en_b.mlc_filter_feature_fifo_en = val;
5899 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1);
5900 }
5901
5902 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
5903
5904 return ret;
5905 }
5906
5907 /**
5908 * @brief Enables batching in FIFO buffer of machine learning core filters and features.[get]
5909 *
5910 * @param ctx read / write interface definitions
5911 * @param val Enables batching in FIFO buffer of machine learning core filters and features.
5912 * @retval interface status (MANDATORY: return 0 -> no Error)
5913 *
5914 */
lsm6dsv16bx_fifo_mlc_filt_batch_get(stmdev_ctx_t * ctx,uint8_t * val)5915 int32_t lsm6dsv16bx_fifo_mlc_filt_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
5916 {
5917 lsm6dsv16bx_emb_func_fifo_en_b_t emb_func_fifo_en_b;
5918 int32_t ret;
5919
5920 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
5921 if (ret == 0)
5922 {
5923 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1);
5924 }
5925
5926 *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en;
5927
5928 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
5929
5930 return ret;
5931 }
5932
5933 /**
5934 * @}
5935 *
5936 */
5937
5938 /**
5939 * @defgroup Step Counter
5940 * @brief This section groups all the functions that manage pedometer.
5941 * @{
5942 *
5943 */
5944
5945 /**
5946 * @brief Step counter mode[set]
5947 *
5948 * @param ctx read / write interface definitions
5949 * @param val false_step_rej, step_counter, step_detector,
5950 * @retval interface status (MANDATORY: return 0 -> no Error)
5951 *
5952 */
lsm6dsv16bx_stpcnt_mode_set(stmdev_ctx_t * ctx,lsm6dsv16bx_stpcnt_mode_t val)5953 int32_t lsm6dsv16bx_stpcnt_mode_set(stmdev_ctx_t *ctx,
5954 lsm6dsv16bx_stpcnt_mode_t val)
5955 {
5956 lsm6dsv16bx_emb_func_en_a_t emb_func_en_a;
5957 lsm6dsv16bx_emb_func_en_b_t emb_func_en_b;
5958 lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg;
5959 int32_t ret;
5960
5961 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
5962 if (ret == 0)
5963 {
5964 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
5965 }
5966 if (ret == 0)
5967 {
5968 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
5969 }
5970 if ((val.false_step_rej == PROPERTY_ENABLE)
5971 && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) ==
5972 PROPERTY_DISABLE))
5973 {
5974 emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE;
5975 }
5976 if (ret == 0)
5977 {
5978 emb_func_en_a.pedo_en = val.step_counter_enable;
5979 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
5980 }
5981
5982 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
5983
5984 if (ret == 0)
5985 {
5986 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
5987 }
5988 if (ret == 0)
5989 {
5990 pedo_cmd_reg.fp_rejection_en = val.false_step_rej;
5991 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
5992 }
5993
5994 return ret;
5995 }
5996
5997 /**
5998 * @brief Step counter mode[get]
5999 *
6000 * @param ctx read / write interface definitions
6001 * @param val false_step_rej, step_counter, step_detector,
6002 * @retval interface status (MANDATORY: return 0 -> no Error)
6003 *
6004 */
lsm6dsv16bx_stpcnt_mode_get(stmdev_ctx_t * ctx,lsm6dsv16bx_stpcnt_mode_t * val)6005 int32_t lsm6dsv16bx_stpcnt_mode_get(stmdev_ctx_t *ctx,
6006 lsm6dsv16bx_stpcnt_mode_t *val)
6007 {
6008 lsm6dsv16bx_emb_func_en_a_t emb_func_en_a;
6009 lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg;
6010 int32_t ret;
6011
6012 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6013 if (ret == 0)
6014 {
6015 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6016 }
6017
6018 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6019
6020 if (ret == 0)
6021 {
6022 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
6023 }
6024 val->false_step_rej = pedo_cmd_reg.fp_rejection_en;
6025 val->step_counter_enable = emb_func_en_a.pedo_en;
6026
6027 return ret;
6028 }
6029
6030 /**
6031 * @brief Step counter output, number of detected steps.[get]
6032 *
6033 * @param ctx read / write interface definitions
6034 * @param val Step counter output, number of detected steps.
6035 * @retval interface status (MANDATORY: return 0 -> no Error)
6036 *
6037 */
lsm6dsv16bx_stpcnt_steps_get(stmdev_ctx_t * ctx,uint16_t * val)6038 int32_t lsm6dsv16bx_stpcnt_steps_get(stmdev_ctx_t *ctx, uint16_t *val)
6039 {
6040 uint8_t buff[2];
6041 int32_t ret;
6042
6043 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6044 if (ret == 0)
6045 {
6046 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_STEP_COUNTER_L, &buff[0], 2);
6047 }
6048
6049 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6050
6051 *val = buff[1];
6052 *val = (*val * 256U) + buff[0];
6053
6054 return ret;
6055 }
6056
6057 /**
6058 * @brief Reset step counter.[set]
6059 *
6060 * @param ctx read / write interface definitions
6061 * @param val Reset step counter.
6062 * @retval interface status (MANDATORY: return 0 -> no Error)
6063 *
6064 */
lsm6dsv16bx_stpcnt_rst_step_set(stmdev_ctx_t * ctx,uint8_t val)6065 int32_t lsm6dsv16bx_stpcnt_rst_step_set(stmdev_ctx_t *ctx, uint8_t val)
6066 {
6067 lsm6dsv16bx_emb_func_src_t emb_func_src;
6068 int32_t ret;
6069
6070 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6071 if (ret == 0)
6072 {
6073 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
6074 }
6075
6076 if (ret == 0)
6077 {
6078 emb_func_src.pedo_rst_step = val;
6079 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
6080 }
6081
6082 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6083
6084 return ret;
6085 }
6086
6087 /**
6088 * @brief Reset step counter.[get]
6089 *
6090 * @param ctx read / write interface definitions
6091 * @param val Reset step counter.
6092 * @retval interface status (MANDATORY: return 0 -> no Error)
6093 *
6094 */
lsm6dsv16bx_stpcnt_rst_step_get(stmdev_ctx_t * ctx,uint8_t * val)6095 int32_t lsm6dsv16bx_stpcnt_rst_step_get(stmdev_ctx_t *ctx, uint8_t *val)
6096 {
6097 lsm6dsv16bx_emb_func_src_t emb_func_src;
6098 int32_t ret;
6099
6100 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6101 if (ret == 0)
6102 {
6103 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
6104 }
6105
6106 *val = emb_func_src.pedo_rst_step;
6107
6108 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6109
6110 return ret;
6111 }
6112
6113 /**
6114 * @brief Pedometer debounce configuration.[set]
6115 *
6116 * @param ctx read / write interface definitions
6117 * @param val Pedometer debounce configuration.
6118 * @retval interface status (MANDATORY: return 0 -> no Error)
6119 *
6120 */
lsm6dsv16bx_stpcnt_debounce_set(stmdev_ctx_t * ctx,uint8_t val)6121 int32_t lsm6dsv16bx_stpcnt_debounce_set(stmdev_ctx_t *ctx, uint8_t val)
6122 {
6123 lsm6dsv16bx_pedo_deb_steps_conf_t pedo_deb_steps_conf;
6124 int32_t ret;
6125
6126 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1);
6127 if (ret == 0)
6128 {
6129 pedo_deb_steps_conf.deb_step = val;
6130 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1);
6131 }
6132
6133 return ret;
6134 }
6135
6136 /**
6137 * @brief Pedometer debounce configuration.[get]
6138 *
6139 * @param ctx read / write interface definitions
6140 * @param val Pedometer debounce configuration.
6141 * @retval interface status (MANDATORY: return 0 -> no Error)
6142 *
6143 */
lsm6dsv16bx_stpcnt_debounce_get(stmdev_ctx_t * ctx,uint8_t * val)6144 int32_t lsm6dsv16bx_stpcnt_debounce_get(stmdev_ctx_t *ctx, uint8_t *val)
6145 {
6146 lsm6dsv16bx_pedo_deb_steps_conf_t pedo_deb_steps_conf;
6147 int32_t ret;
6148
6149 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf, 1);
6150 *val = pedo_deb_steps_conf.deb_step;
6151
6152 return ret;
6153 }
6154
6155 /**
6156 * @brief Time period register for step detection on delta time.[set]
6157 *
6158 * @param ctx read / write interface definitions
6159 * @param val Time period register for step detection on delta time.
6160 * @retval interface status (MANDATORY: return 0 -> no Error)
6161 *
6162 */
lsm6dsv16bx_stpcnt_period_set(stmdev_ctx_t * ctx,uint16_t val)6163 int32_t lsm6dsv16bx_stpcnt_period_set(stmdev_ctx_t *ctx, uint16_t val)
6164 {
6165 uint8_t buff[2];
6166 int32_t ret;
6167
6168 buff[1] = (uint8_t)(val / 256U);
6169 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6170
6171 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_PEDO_SC_DELTAT_L, (uint8_t *)&buff[0], 2);
6172
6173 return ret;
6174 }
6175
6176 /**
6177 * @brief Time period register for step detection on delta time.[get]
6178 *
6179 * @param ctx read / write interface definitions
6180 * @param val Time period register for step detection on delta time.
6181 * @retval interface status (MANDATORY: return 0 -> no Error)
6182 *
6183 */
lsm6dsv16bx_stpcnt_period_get(stmdev_ctx_t * ctx,uint16_t * val)6184 int32_t lsm6dsv16bx_stpcnt_period_get(stmdev_ctx_t *ctx, uint16_t *val)
6185 {
6186 uint8_t buff[2];
6187 int32_t ret;
6188
6189 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_SC_DELTAT_L, &buff[0], 2);
6190 *val = buff[1];
6191 *val = (*val * 256U) + buff[0];
6192
6193 return ret;
6194 }
6195
6196 /**
6197 * @}
6198 *
6199 */
6200
6201 /**
6202 * @defgroup Significant motion
6203 * @brief This section groups all the functions that manage the
6204 * significant motion detection.
6205 * @{
6206 *
6207 */
6208
6209 /**
6210 * @brief Enables significant motion detection function.[set]
6211 *
6212 * @param ctx read / write interface definitions
6213 * @param val Enables significant motion detection function.
6214 * @retval interface status (MANDATORY: return 0 -> no Error)
6215 *
6216 */
lsm6dsv16bx_sigmot_mode_set(stmdev_ctx_t * ctx,uint8_t val)6217 int32_t lsm6dsv16bx_sigmot_mode_set(stmdev_ctx_t *ctx, uint8_t val)
6218 {
6219 lsm6dsv16bx_emb_func_en_a_t emb_func_en_a;
6220 int32_t ret;
6221
6222 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6223 if (ret == 0)
6224 {
6225 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6226 }
6227 if (ret == 0)
6228 {
6229 emb_func_en_a.sign_motion_en = val;
6230 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6231 }
6232
6233 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6234
6235
6236 return ret;
6237 }
6238
6239 /**
6240 * @brief Enables significant motion detection function.[get]
6241 *
6242 * @param ctx read / write interface definitions
6243 * @param val Enables significant motion detection function.
6244 * @retval interface status (MANDATORY: return 0 -> no Error)
6245 *
6246 */
lsm6dsv16bx_sigmot_mode_get(stmdev_ctx_t * ctx,uint8_t * val)6247 int32_t lsm6dsv16bx_sigmot_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
6248 {
6249 lsm6dsv16bx_emb_func_en_a_t emb_func_en_a;
6250 int32_t ret;
6251
6252 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6253 if (ret == 0)
6254 {
6255 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6256 }
6257 *val = emb_func_en_a.sign_motion_en;
6258
6259 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6260
6261
6262 return ret;
6263 }
6264
6265 /**
6266 * @}
6267 *
6268 */
6269
6270 /**
6271 * @defgroup Tilt detection
6272 * @brief This section groups all the functions that manage the tilt
6273 * event detection.
6274 * @{
6275 *
6276 */
6277
6278 /**
6279 * @brief Tilt calculation.[set]
6280 *
6281 * @param ctx read / write interface definitions
6282 * @param val Tilt calculation.
6283 * @retval interface status (MANDATORY: return 0 -> no Error)
6284 *
6285 */
lsm6dsv16bx_tilt_mode_set(stmdev_ctx_t * ctx,uint8_t val)6286 int32_t lsm6dsv16bx_tilt_mode_set(stmdev_ctx_t *ctx, uint8_t val)
6287 {
6288 lsm6dsv16bx_emb_func_en_a_t emb_func_en_a;
6289 int32_t ret;
6290
6291 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6292 if (ret == 0)
6293 {
6294 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6295 }
6296 if (ret == 0)
6297 {
6298 emb_func_en_a.tilt_en = val;
6299 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6300 }
6301
6302 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6303
6304 return ret;
6305 }
6306
6307 /**
6308 * @brief Tilt calculation.[get]
6309 *
6310 * @param ctx read / write interface definitions
6311 * @param val Tilt calculation.
6312 * @retval interface status (MANDATORY: return 0 -> no Error)
6313 *
6314 */
lsm6dsv16bx_tilt_mode_get(stmdev_ctx_t * ctx,uint8_t * val)6315 int32_t lsm6dsv16bx_tilt_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
6316 {
6317 lsm6dsv16bx_emb_func_en_a_t emb_func_en_a;
6318 int32_t ret;
6319
6320 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6321 if (ret == 0)
6322 {
6323 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6324 }
6325 *val = emb_func_en_a.tilt_en;
6326
6327 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6328
6329 return ret;
6330 }
6331
6332 /**
6333 * @}
6334 *
6335 */
6336
6337 /**
6338 * @defgroup Sensor Fusion Low Power (SFLP)
6339 * @brief This section groups all the functions that manage pedometer.
6340 * @{
6341 *
6342 */
6343
6344 /**
6345 * @brief Enable SFLP Game Rotation Vector (6x).[set]
6346 *
6347 * @param ctx read / write interface definitions
6348 * @param val Enable/Disable game rotation value (0/1).
6349 * @retval interface status (MANDATORY: return 0 -> no Error)
6350 *
6351 */
lsm6dsv16bx_sflp_game_rotation_set(stmdev_ctx_t * ctx,uint16_t val)6352 int32_t lsm6dsv16bx_sflp_game_rotation_set(stmdev_ctx_t *ctx, uint16_t val)
6353 {
6354 lsm6dsv16bx_emb_func_en_a_t emb_func_en_a;
6355 int32_t ret;
6356
6357 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6358 if (ret == 0)
6359 {
6360 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6361 emb_func_en_a.sflp_game_en = val;
6362 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A,
6363 (uint8_t *)&emb_func_en_a, 1);
6364 }
6365
6366 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6367
6368 return ret;
6369 }
6370
6371 /**
6372 * @brief Enable SFLP Game Rotation Vector (6x).[get]
6373 *
6374 * @param ctx read / write interface definitions
6375 * @param val Enable/Disable game rotation value (0/1).
6376 * @retval interface status (MANDATORY: return 0 -> no Error)
6377 *
6378 */
lsm6dsv16bx_sflp_game_rotation_get(stmdev_ctx_t * ctx,uint16_t * val)6379 int32_t lsm6dsv16bx_sflp_game_rotation_get(stmdev_ctx_t *ctx, uint16_t *val)
6380 {
6381 lsm6dsv16bx_emb_func_en_a_t emb_func_en_a;
6382 int32_t ret;
6383
6384 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6385 if (ret == 0)
6386 {
6387 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6388 *val = emb_func_en_a.sflp_game_en;
6389 }
6390
6391 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6392
6393 return ret;
6394 }
6395
6396 /**
6397 * @brief SFLP Data Rate (ODR) configuration.[set]
6398 *
6399 * @param ctx read / write interface definitions
6400 * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz
6401 * @retval interface status (MANDATORY: return 0 -> no Error)
6402 *
6403 */
lsm6dsv16bx_sflp_data_rate_set(stmdev_ctx_t * ctx,lsm6dsv16bx_sflp_data_rate_t val)6404 int32_t lsm6dsv16bx_sflp_data_rate_set(stmdev_ctx_t *ctx,
6405 lsm6dsv16bx_sflp_data_rate_t val)
6406 {
6407 lsm6dsv16bx_sflp_odr_t sflp_odr;
6408 int32_t ret;
6409
6410 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6411 if (ret == 0)
6412 {
6413 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
6414 sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U;
6415 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_SFLP_ODR, (uint8_t *)&sflp_odr,
6416 1);
6417 }
6418
6419 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6420
6421 return ret;
6422 }
6423
6424 /**
6425 * @brief SFLP Data Rate (ODR) configuration.[get]
6426 *
6427 * @param ctx read / write interface definitions
6428 * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz
6429 * @retval interface status (MANDATORY: return 0 -> no Error)
6430 *
6431 */
lsm6dsv16bx_sflp_data_rate_get(stmdev_ctx_t * ctx,lsm6dsv16bx_sflp_data_rate_t * val)6432 int32_t lsm6dsv16bx_sflp_data_rate_get(stmdev_ctx_t *ctx,
6433 lsm6dsv16bx_sflp_data_rate_t *val)
6434 {
6435 lsm6dsv16bx_sflp_odr_t sflp_odr;
6436 int32_t ret;
6437
6438 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6439 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
6440 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6441
6442 switch (sflp_odr.sflp_game_odr)
6443 {
6444 case LSM6DSV16BX_SFLP_15Hz:
6445 *val = LSM6DSV16BX_SFLP_15Hz;
6446 break;
6447
6448 case LSM6DSV16BX_SFLP_30Hz:
6449 *val = LSM6DSV16BX_SFLP_30Hz;
6450 break;
6451
6452 case LSM6DSV16BX_SFLP_60Hz:
6453 *val = LSM6DSV16BX_SFLP_60Hz;
6454 break;
6455
6456 case LSM6DSV16BX_SFLP_120Hz:
6457 *val = LSM6DSV16BX_SFLP_120Hz;
6458 break;
6459
6460 case LSM6DSV16BX_SFLP_240Hz:
6461 *val = LSM6DSV16BX_SFLP_240Hz;
6462 break;
6463
6464 case LSM6DSV16BX_SFLP_480Hz:
6465 *val = LSM6DSV16BX_SFLP_480Hz;
6466 break;
6467
6468 default:
6469 *val = LSM6DSV16BX_SFLP_15Hz;
6470 break;
6471 }
6472 return ret;
6473 }
6474
6475 /*
6476 * Original conversion routines taken from: https://github.com/numpy/numpy
6477 *
6478 * uint16_t npy_floatbits_to_halfbits(uint32_t f);
6479 * uint16_t npy_float_to_half(float_t f);
6480 *
6481 * Released under BSD-3-Clause License
6482 */
npy_floatbits_to_halfbits(uint32_t f)6483 static uint16_t npy_floatbits_to_halfbits(uint32_t f)
6484 {
6485 uint32_t f_exp, f_sig;
6486 uint16_t h_sgn, h_exp, h_sig;
6487
6488 h_sgn = (uint16_t)((f & 0x80000000u) >> 16);
6489 f_exp = (f & 0x7f800000u);
6490
6491 /* Exponent overflow/NaN converts to signed inf/NaN */
6492 if (f_exp >= 0x47800000u)
6493 {
6494 if (f_exp == 0x7f800000u)
6495 {
6496 /* Inf or NaN */
6497 f_sig = (f & 0x007fffffu);
6498 if (f_sig != 0)
6499 {
6500 /* NaN - propagate the flag in the significand... */
6501 uint16_t ret = (uint16_t)(0x7c00u + (f_sig >> 13));
6502 /* ...but make sure it stays a NaN */
6503 if (ret == 0x7c00u)
6504 {
6505 ret++;
6506 }
6507 return h_sgn + ret;
6508 }
6509 else
6510 {
6511 /* signed inf */
6512 return (uint16_t)(h_sgn + 0x7c00u);
6513 }
6514 }
6515 else
6516 {
6517 /* overflow to signed inf */
6518 #if NPY_HALF_GENERATE_OVERFLOW
6519 npy_set_floatstatus_overflow();
6520 #endif
6521 return (uint16_t)(h_sgn + 0x7c00u);
6522 }
6523 }
6524
6525 /* Exponent underflow converts to a subnormal half or signed zero */
6526 if (f_exp <= 0x38000000u)
6527 {
6528 /*
6529 * Signed zeros, subnormal floats, and floats with small
6530 * exponents all convert to signed zero half-floats.
6531 */
6532 if (f_exp < 0x33000000u)
6533 {
6534 #if NPY_HALF_GENERATE_UNDERFLOW
6535 /* If f != 0, it underflowed to 0 */
6536 if ((f & 0x7fffffff) != 0)
6537 {
6538 npy_set_floatstatus_underflow();
6539 }
6540 #endif
6541 return h_sgn;
6542 }
6543 /* Make the subnormal significand */
6544 f_exp >>= 23;
6545 f_sig = (0x00800000u + (f & 0x007fffffu));
6546 #if NPY_HALF_GENERATE_UNDERFLOW
6547 /* If it's not exactly represented, it underflowed */
6548 if ((f_sig & (((uint32_t)1 << (126 - f_exp)) - 1)) != 0)
6549 {
6550 npy_set_floatstatus_underflow();
6551 }
6552 #endif
6553 /*
6554 * Usually the significand is shifted by 13. For subnormals an
6555 * additional shift needs to occur. This shift is one for the largest
6556 * exponent giving a subnormal `f_exp = 0x38000000 >> 23 = 112`, which
6557 * offsets the new first bit. At most the shift can be 1+10 bits.
6558 */
6559 f_sig >>= (113 - f_exp);
6560 /* Handle rounding by adding 1 to the bit beyond half precision */
6561 #if NPY_HALF_ROUND_TIES_TO_EVEN
6562 /*
6563 * If the last bit in the half significand is 0 (already even), and
6564 * the remaining bit pattern is 1000...0, then we do not add one
6565 * to the bit after the half significand. However, the (113 - f_exp)
6566 * shift can lose up to 11 bits, so the || checks them in the original.
6567 * In all other cases, we can just add one.
6568 */
6569 if (((f_sig & 0x00003fffu) != 0x00001000u) || (f & 0x000007ffu))
6570 {
6571 f_sig += 0x00001000u;
6572 }
6573 #else
6574 f_sig += 0x00001000u;
6575 #endif
6576 h_sig = (uint16_t)(f_sig >> 13);
6577 /*
6578 * If the rounding causes a bit to spill into h_exp, it will
6579 * increment h_exp from zero to one and h_sig will be zero.
6580 * This is the correct result.
6581 */
6582 return (uint16_t)(h_sgn + h_sig);
6583 }
6584
6585 /* Regular case with no overflow or underflow */
6586 h_exp = (uint16_t)((f_exp - 0x38000000u) >> 13);
6587 /* Handle rounding by adding 1 to the bit beyond half precision */
6588 f_sig = (f & 0x007fffffu);
6589 #if NPY_HALF_ROUND_TIES_TO_EVEN
6590 /*
6591 * If the last bit in the half significand is 0 (already even), and
6592 * the remaining bit pattern is 1000...0, then we do not add one
6593 * to the bit after the half significand. In all other cases, we do.
6594 */
6595 if ((f_sig & 0x00003fffu) != 0x00001000u)
6596 {
6597 f_sig += 0x00001000u;
6598 }
6599 #else
6600 f_sig += 0x00001000u;
6601 #endif
6602 h_sig = (uint16_t)(f_sig >> 13);
6603 /*
6604 * If the rounding causes a bit to spill into h_exp, it will
6605 * increment h_exp by one and h_sig will be zero. This is the
6606 * correct result. h_exp may increment to 15, at greatest, in
6607 * which case the result overflows to a signed inf.
6608 */
6609 #if NPY_HALF_GENERATE_OVERFLOW
6610 h_sig += h_exp;
6611 if (h_sig == 0x7c00u)
6612 {
6613 npy_set_floatstatus_overflow();
6614 }
6615 return h_sgn + h_sig;
6616 #else
6617 return h_sgn + h_exp + h_sig;
6618 #endif
6619 }
6620
npy_float_to_half(float_t f)6621 static uint16_t npy_float_to_half(float_t f)
6622 {
6623 union
6624 {
6625 float_t f;
6626 uint32_t fbits;
6627 } conv;
6628 conv.f = f;
6629 return npy_floatbits_to_halfbits(conv.fbits);
6630 }
6631
6632 /**
6633 * @brief SFLP GBIAS value. The register value is expressed as half-precision
6634 * floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent
6635 * bits; F: 10 fraction bits).[set]
6636 *
6637 * @param ctx read / write interface definitions
6638 * @param val GBIAS x/y/z val.
6639 * @retval interface status (MANDATORY: return 0 -> no Error)
6640 *
6641 */
lsm6dsv16bx_sflp_game_gbias_set(stmdev_ctx_t * ctx,lsm6dsv16bx_sflp_gbias_t * val)6642 int32_t lsm6dsv16bx_sflp_game_gbias_set(stmdev_ctx_t *ctx,
6643 lsm6dsv16bx_sflp_gbias_t *val)
6644 {
6645 lsm6dsv16bx_sflp_data_rate_t sflp_odr;
6646 lsm6dsv16bx_emb_func_exec_status_t emb_func_sts;
6647 lsm6dsv16bx_data_ready_t drdy;
6648 lsm6dsv16bx_xl_full_scale_t xl_fs;
6649 lsm6dsv16bx_ctrl10_t ctrl10;
6650 uint8_t master_config;
6651 uint8_t emb_func_en_saved[2];
6652 uint8_t conf_saved[2];
6653 uint8_t reg_zero[2] = {0x0, 0x0};
6654 uint16_t gbias_hf[3];
6655 float_t k = 0.005f;
6656 int16_t xl_data[3];
6657 int32_t data_tmp;
6658 uint8_t *data_ptr = (uint8_t *)&data_tmp;
6659 uint8_t i, j;
6660 int32_t ret;
6661
6662 ret = lsm6dsv16bx_sflp_data_rate_get(ctx, &sflp_odr);
6663 if (ret != 0)
6664 {
6665 return ret;
6666 }
6667
6668 /* Calculate k factor */
6669 switch (sflp_odr)
6670 {
6671 case LSM6DSV16BX_SFLP_15Hz:
6672 k = 0.04f;
6673 break;
6674 case LSM6DSV16BX_SFLP_30Hz:
6675 k = 0.02f;
6676 break;
6677 case LSM6DSV16BX_SFLP_60Hz:
6678 k = 0.01f;
6679 break;
6680 case LSM6DSV16BX_SFLP_120Hz:
6681 k = 0.005f;
6682 break;
6683 case LSM6DSV16BX_SFLP_240Hz:
6684 k = 0.0025f;
6685 break;
6686 case LSM6DSV16BX_SFLP_480Hz:
6687 k = 0.00125f;
6688 break;
6689 }
6690
6691 /* compute gbias as half precision float in order to be put in embedded advanced feature register */
6692 gbias_hf[0] = npy_float_to_half(val->gbias_x * (3.14159265358979323846f / 180.0f) / k);
6693 gbias_hf[1] = npy_float_to_half(val->gbias_y * (3.14159265358979323846f / 180.0f) / k);
6694 gbias_hf[2] = npy_float_to_half(val->gbias_z * (3.14159265358979323846f / 180.0f) / k);
6695
6696 /* Save sensor configuration and set high-performance mode (if the sensor is in power-down mode, turn it on) */
6697 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL1, conf_saved, 2);
6698 ret += lsm6dsv16bx_xl_mode_set(ctx, LSM6DSV16BX_XL_HIGH_PERFORMANCE_MD);
6699 ret += lsm6dsv16bx_gy_mode_set(ctx, LSM6DSV16BX_GY_HIGH_PERFORMANCE_MD);
6700 if ((conf_saved[0] & 0x0FU) == LSM6DSV16BX_XL_ODR_OFF)
6701 {
6702 ret += lsm6dsv16bx_xl_data_rate_set(ctx, LSM6DSV16BX_XL_ODR_AT_120Hz);
6703 }
6704
6705 /* disable algos */
6706 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6707 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, emb_func_en_saved,
6708 2);
6709 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, reg_zero, 2);
6710 do
6711 {
6712 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EXEC_STATUS,
6713 (uint8_t *)&emb_func_sts, 1);
6714 } while (emb_func_sts.emb_func_endop != 1);
6715 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6716
6717 // enable gbias setting
6718 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
6719 ctrl10.emb_func_debug = 1;
6720 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
6721
6722 /* enable algos */
6723 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6724 emb_func_en_saved[0] |= 0x02; /* force SFLP GAME en */
6725 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, emb_func_en_saved,
6726 2);
6727 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6728
6729 ret += lsm6dsv16bx_xl_full_scale_get(ctx, &xl_fs);
6730
6731 /* Read XL data */
6732 do
6733 {
6734 ret += lsm6dsv16bx_flag_data_ready_get(ctx, &drdy);
6735 } while (drdy.drdy_xl != 1);
6736 ret += lsm6dsv16bx_acceleration_raw_get(ctx, xl_data);
6737
6738 /* force sflp initialization */
6739 master_config = 0x40;
6740 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, &master_config,
6741 1);
6742 for (i = 0; i < 3; i++)
6743 {
6744 j = 0;
6745 data_tmp = (int32_t)xl_data[i];
6746 data_tmp <<= xl_fs; // shift based on current fs
6747 ret += lsm6dsv16bx_write_reg(ctx, 0x02 + 3 * i, &data_ptr[j++], 1);
6748 ret += lsm6dsv16bx_write_reg(ctx, 0x03 + 3 * i, &data_ptr[j++], 1);
6749 ret += lsm6dsv16bx_write_reg(ctx, 0x04 + 3 * i, &data_ptr[j], 1);
6750 }
6751 for (i = 0; i < 3; i++)
6752 {
6753 j = 0;
6754 data_tmp = 0;
6755 ret += lsm6dsv16bx_write_reg(ctx, 0x0B + 3 * i, &data_ptr[j++], 1);
6756 ret += lsm6dsv16bx_write_reg(ctx, 0x0C + 3 * i, &data_ptr[j++], 1);
6757 ret += lsm6dsv16bx_write_reg(ctx, 0x0D + 3 * i, &data_ptr[j], 1);
6758 }
6759 master_config = 0x00;
6760 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, &master_config,
6761 1);
6762
6763 // wait end_op (and at least 30 us)
6764 ctx->mdelay(1);
6765 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6766 do
6767 {
6768 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EXEC_STATUS,
6769 (uint8_t *)&emb_func_sts, 1);
6770 } while (emb_func_sts.emb_func_endop != 1);
6771 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6772
6773 /* write gbias in embedded advanced features registers */
6774 ret += lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_SFLP_GAME_GBIASX_L,
6775 (uint8_t *)gbias_hf, 6);
6776
6777 /* reload previous sensor configuration */
6778 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL1, conf_saved, 2);
6779
6780 // disable gbias setting
6781 ctrl10.emb_func_debug = 0;
6782 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
6783
6784 return ret;
6785 }
6786
6787 /**
6788 * @brief SFLP initial configuration [set]
6789 *
6790 * @param ctx read / write interface definitions
6791 * @retval interface status (MANDATORY: return 0 -> no Error)
6792 *
6793 */
lsm6dsv16bx_sflp_configure(stmdev_ctx_t * ctx)6794 int32_t lsm6dsv16bx_sflp_configure(stmdev_ctx_t *ctx)
6795 {
6796 uint8_t val = 0x50;
6797 int32_t ret;
6798
6799 ret = lsm6dsv16bx_ln_pg_write(ctx, 0xD2, &val, 1);
6800
6801 return ret;
6802 }
6803
6804 /**
6805 * @}
6806 *
6807 */
6808
6809 /**
6810 * @defgroup Finite State Machine (FSM)
6811 * @brief This section groups all the functions that manage the
6812 * state_machine.
6813 * @{
6814 *
6815 */
6816
6817 /**
6818 * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[set]
6819 *
6820 * @param ctx read / write interface definitions
6821 * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG,
6822 * @retval interface status (MANDATORY: return 0 -> no Error)
6823 *
6824 */
lsm6dsv16bx_fsm_permission_set(stmdev_ctx_t * ctx,lsm6dsv16bx_fsm_permission_t val)6825 int32_t lsm6dsv16bx_fsm_permission_set(stmdev_ctx_t *ctx,
6826 lsm6dsv16bx_fsm_permission_t val)
6827 {
6828 lsm6dsv16bx_func_cfg_access_t func_cfg_access;
6829 int32_t ret;
6830
6831 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
6832 if (ret == 0)
6833 {
6834 func_cfg_access.fsm_wr_ctrl_en = (uint8_t)val & 0x01U;
6835 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
6836 }
6837
6838 return ret;
6839 }
6840
6841 /**
6842 * @brief Return the status of the CTRL registers permission (standard interface vs FSM).[get]
6843 *
6844 * @param ctx read / write interface definitions
6845 * @param val 0: all FSM regs are under std_if control, 1: some regs are under FSM control.
6846 * @retval interface status (MANDATORY: return 0 -> no Error)
6847 *
6848 */
lsm6dsv16bx_fsm_permission_status_get(stmdev_ctx_t * ctx,lsm6dsv16bx_fsm_permission_status_t * val)6849 int32_t lsm6dsv16bx_fsm_permission_status_get(stmdev_ctx_t *ctx,
6850 lsm6dsv16bx_fsm_permission_status_t *val)
6851 {
6852 lsm6dsv16bx_ctrl_status_t status;
6853 int32_t ret;
6854
6855 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL_STATUS, (uint8_t *)&status, 1);
6856 *val = (status.fsm_wr_ctrl_status == 0) ? LSM6DSV16BX_STD_IF_CONTROL : LSM6DSV16BX_FSM_CONTROL;
6857
6858 return ret;
6859 }
6860
6861 /**
6862 * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[get]
6863 *
6864 * @param ctx read / write interface definitions
6865 * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG,
6866 * @retval interface status (MANDATORY: return 0 -> no Error)
6867 *
6868 */
lsm6dsv16bx_fsm_permission_get(stmdev_ctx_t * ctx,lsm6dsv16bx_fsm_permission_t * val)6869 int32_t lsm6dsv16bx_fsm_permission_get(stmdev_ctx_t *ctx,
6870 lsm6dsv16bx_fsm_permission_t *val)
6871 {
6872 lsm6dsv16bx_func_cfg_access_t func_cfg_access;
6873 int32_t ret;
6874
6875 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
6876 switch (func_cfg_access.fsm_wr_ctrl_en)
6877 {
6878 case LSM6DSV16BX_PROTECT_CTRL_REGS:
6879 *val = LSM6DSV16BX_PROTECT_CTRL_REGS;
6880 break;
6881
6882 case LSM6DSV16BX_WRITE_CTRL_REG:
6883 *val = LSM6DSV16BX_WRITE_CTRL_REG;
6884 break;
6885
6886 default:
6887 *val = LSM6DSV16BX_PROTECT_CTRL_REGS;
6888 break;
6889 }
6890 return ret;
6891 }
6892
6893 /**
6894 * @brief Get the FSM permission status
6895 *
6896 * @param ctx read / write interface definitions
6897 * @param val 0: All reg writable from std if - 1: some regs are under FSM control.
6898 * @retval interface status (MANDATORY: return 0 -> no Error)
6899 *
6900 */
lsm6dsv16bx_fsm_permission_status(stmdev_ctx_t * ctx,uint8_t * val)6901 int32_t lsm6dsv16bx_fsm_permission_status(stmdev_ctx_t *ctx, uint8_t *val)
6902 {
6903 lsm6dsv16bx_ctrl_status_t ctrl_status;
6904 int32_t ret;
6905
6906 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL_STATUS, (uint8_t *)&ctrl_status, 1);
6907
6908 *val = ctrl_status.fsm_wr_ctrl_status;
6909
6910 return ret;
6911 }
6912
6913 /**
6914 * @brief Enable Finite State Machine (FSM) feature.[set]
6915 *
6916 * @param ctx read / write interface definitions
6917 * @param val Enable Finite State Machine (FSM) feature.
6918 * @retval interface status (MANDATORY: return 0 -> no Error)
6919 *
6920 */
lsm6dsv16bx_fsm_mode_set(stmdev_ctx_t * ctx,lsm6dsv16bx_fsm_mode_t val)6921 int32_t lsm6dsv16bx_fsm_mode_set(stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_mode_t val)
6922 {
6923 lsm6dsv16bx_emb_func_en_b_t emb_func_en_b;
6924 lsm6dsv16bx_fsm_enable_t fsm_enable;
6925 int32_t ret;
6926
6927 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6928 if (ret == 0)
6929 {
6930 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
6931 }
6932 if (ret == 0)
6933 {
6934 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
6935 }
6936 if ((val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en
6937 | val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en) == PROPERTY_ENABLE)
6938 {
6939 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
6940 }
6941 else
6942 {
6943 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
6944 }
6945 if (ret == 0)
6946 {
6947 fsm_enable.fsm1_en = val.fsm1_en;
6948 fsm_enable.fsm2_en = val.fsm2_en;
6949 fsm_enable.fsm3_en = val.fsm3_en;
6950 fsm_enable.fsm4_en = val.fsm4_en;
6951 fsm_enable.fsm5_en = val.fsm5_en;
6952 fsm_enable.fsm6_en = val.fsm6_en;
6953 fsm_enable.fsm7_en = val.fsm7_en;
6954 fsm_enable.fsm8_en = val.fsm8_en;
6955 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
6956 }
6957 if (ret == 0)
6958 {
6959 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
6960 }
6961
6962 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6963
6964 return ret;
6965 }
6966
6967 /**
6968 * @brief Enable Finite State Machine (FSM) feature.[get]
6969 *
6970 * @param ctx read / write interface definitions
6971 * @param val Enable Finite State Machine (FSM) feature.
6972 * @retval interface status (MANDATORY: return 0 -> no Error)
6973 *
6974 */
lsm6dsv16bx_fsm_mode_get(stmdev_ctx_t * ctx,lsm6dsv16bx_fsm_mode_t * val)6975 int32_t lsm6dsv16bx_fsm_mode_get(stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_mode_t *val)
6976 {
6977 lsm6dsv16bx_fsm_enable_t fsm_enable;
6978 int32_t ret;
6979
6980 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6981 if (ret == 0)
6982 {
6983 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
6984 }
6985
6986 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6987
6988 val->fsm1_en = fsm_enable.fsm1_en;
6989 val->fsm2_en = fsm_enable.fsm2_en;
6990 val->fsm3_en = fsm_enable.fsm3_en;
6991 val->fsm4_en = fsm_enable.fsm4_en;
6992 val->fsm5_en = fsm_enable.fsm5_en;
6993 val->fsm6_en = fsm_enable.fsm6_en;
6994 val->fsm7_en = fsm_enable.fsm7_en;
6995 val->fsm8_en = fsm_enable.fsm8_en;
6996
6997 return ret;
6998 }
6999
7000 /**
7001 * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[set]
7002 *
7003 * @param ctx read / write interface definitions
7004 * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).
7005 * @retval interface status (MANDATORY: return 0 -> no Error)
7006 *
7007 */
lsm6dsv16bx_fsm_long_cnt_set(stmdev_ctx_t * ctx,uint16_t val)7008 int32_t lsm6dsv16bx_fsm_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
7009 {
7010 uint8_t buff[2];
7011 int32_t ret;
7012
7013 buff[1] = (uint8_t)(val / 256U);
7014 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7015
7016 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7017 if (ret == 0)
7018 {
7019 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2);
7020 }
7021
7022 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7023
7024 return ret;
7025 }
7026
7027 /**
7028 * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[get]
7029 *
7030 * @param ctx read / write interface definitions
7031 * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).
7032 * @retval interface status (MANDATORY: return 0 -> no Error)
7033 *
7034 */
lsm6dsv16bx_fsm_long_cnt_get(stmdev_ctx_t * ctx,uint16_t * val)7035 int32_t lsm6dsv16bx_fsm_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
7036 {
7037 uint8_t buff[2];
7038 int32_t ret;
7039
7040 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7041 if (ret == 0)
7042 {
7043 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_LONG_COUNTER_L, &buff[0], 2);
7044 }
7045
7046 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7047
7048 *val = buff[1];
7049 *val = (*val * 256U) + buff[0];
7050
7051 return ret;
7052 }
7053
7054 /**
7055 * @brief FSM output registers[get]
7056 *
7057 * @param ctx read / write interface definitions
7058 * @param val FSM output registers
7059 * @retval interface status (MANDATORY: return 0 -> no Error)
7060 *
7061 */
lsm6dsv16bx_fsm_out_get(stmdev_ctx_t * ctx,lsm6dsv16bx_fsm_out_t * val)7062 int32_t lsm6dsv16bx_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_out_t *val)
7063 {
7064 int32_t ret;
7065
7066 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7067 if (ret == 0)
7068 {
7069 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_OUTS1, (uint8_t *)val, 8);
7070 }
7071
7072 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7073
7074 return ret;
7075 }
7076
7077 /**
7078 * @brief Finite State Machine Output Data Rate (ODR) configuration.[set]
7079 *
7080 * @param ctx read / write interface definitions
7081 * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz,
7082 * @retval interface status (MANDATORY: return 0 -> no Error)
7083 *
7084 */
lsm6dsv16bx_fsm_data_rate_set(stmdev_ctx_t * ctx,lsm6dsv16bx_fsm_data_rate_t val)7085 int32_t lsm6dsv16bx_fsm_data_rate_set(stmdev_ctx_t *ctx,
7086 lsm6dsv16bx_fsm_data_rate_t val)
7087 {
7088 lsm6dsv16bx_fsm_odr_t fsm_odr;
7089 int32_t ret;
7090
7091 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7092 if (ret == 0)
7093 {
7094 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_ODR, (uint8_t *)&fsm_odr, 1);
7095 }
7096
7097 if (ret == 0)
7098 {
7099 fsm_odr.fsm_odr = (uint8_t)val & 0x07U;
7100 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FSM_ODR, (uint8_t *)&fsm_odr, 1);
7101 }
7102
7103 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7104
7105 return ret;
7106 }
7107
7108 /**
7109 * @brief Finite State Machine Output Data Rate (ODR) configuration.[get]
7110 *
7111 * @param ctx read / write interface definitions
7112 * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz,
7113 * @retval interface status (MANDATORY: return 0 -> no Error)
7114 *
7115 */
lsm6dsv16bx_fsm_data_rate_get(stmdev_ctx_t * ctx,lsm6dsv16bx_fsm_data_rate_t * val)7116 int32_t lsm6dsv16bx_fsm_data_rate_get(stmdev_ctx_t *ctx,
7117 lsm6dsv16bx_fsm_data_rate_t *val)
7118 {
7119 lsm6dsv16bx_fsm_odr_t fsm_odr;
7120 int32_t ret;
7121
7122 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7123 if (ret == 0)
7124 {
7125 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_ODR, (uint8_t *)&fsm_odr, 1);
7126 }
7127
7128 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7129
7130 switch (fsm_odr.fsm_odr)
7131 {
7132 case LSM6DSV16BX_FSM_15Hz:
7133 *val = LSM6DSV16BX_FSM_15Hz;
7134 break;
7135
7136 case LSM6DSV16BX_FSM_30Hz:
7137 *val = LSM6DSV16BX_FSM_30Hz;
7138 break;
7139
7140 case LSM6DSV16BX_FSM_60Hz:
7141 *val = LSM6DSV16BX_FSM_60Hz;
7142 break;
7143
7144 case LSM6DSV16BX_FSM_120Hz:
7145 *val = LSM6DSV16BX_FSM_120Hz;
7146 break;
7147
7148 case LSM6DSV16BX_FSM_240Hz:
7149 *val = LSM6DSV16BX_FSM_240Hz;
7150 break;
7151
7152 case LSM6DSV16BX_FSM_480Hz:
7153 *val = LSM6DSV16BX_FSM_480Hz;
7154 break;
7155
7156 case LSM6DSV16BX_FSM_960Hz:
7157 *val = LSM6DSV16BX_FSM_960Hz;
7158 break;
7159
7160 default:
7161 *val = LSM6DSV16BX_FSM_15Hz;
7162 break;
7163 }
7164 return ret;
7165 }
7166
7167 /**
7168 * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[set]
7169 *
7170 * @param ctx read / write interface definitions
7171 * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.
7172 * @retval interface status (MANDATORY: return 0 -> no Error)
7173 *
7174 */
lsm6dsv16bx_fsm_long_cnt_timeout_set(stmdev_ctx_t * ctx,uint16_t val)7175 int32_t lsm6dsv16bx_fsm_long_cnt_timeout_set(stmdev_ctx_t *ctx, uint16_t val)
7176 {
7177 uint8_t buff[2];
7178 int32_t ret;
7179
7180 buff[1] = (uint8_t)(val / 256U);
7181 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7182 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_FSM_LC_TIMEOUT_L, (uint8_t *)&buff[0], 2);
7183
7184 return ret;
7185 }
7186
7187 /**
7188 * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[get]
7189 *
7190 * @param ctx read / write interface definitions
7191 * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.
7192 * @retval interface status (MANDATORY: return 0 -> no Error)
7193 *
7194 */
lsm6dsv16bx_fsm_long_cnt_timeout_get(stmdev_ctx_t * ctx,uint16_t * val)7195 int32_t lsm6dsv16bx_fsm_long_cnt_timeout_get(stmdev_ctx_t *ctx, uint16_t *val)
7196 {
7197 uint8_t buff[2];
7198 int32_t ret;
7199
7200 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_FSM_LC_TIMEOUT_L, &buff[0], 2);
7201 *val = buff[1];
7202 *val = (*val * 256U) + buff[0];
7203
7204 return ret;
7205 }
7206
7207 /**
7208 * @brief FSM number of programs.[set]
7209 *
7210 * @param ctx read / write interface definitions
7211 * @param val FSM number of programs.
7212 * @retval interface status (MANDATORY: return 0 -> no Error)
7213 *
7214 */
lsm6dsv16bx_fsm_number_of_programs_set(stmdev_ctx_t * ctx,uint8_t val)7215 int32_t lsm6dsv16bx_fsm_number_of_programs_set(stmdev_ctx_t *ctx, uint8_t val)
7216 {
7217 lsm6dsv16bx_fsm_programs_t fsm_programs;
7218 int32_t ret;
7219
7220 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1);
7221 if (ret == 0)
7222 {
7223 fsm_programs.fsm_n_prog = val;
7224 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1);
7225 }
7226
7227 return ret;
7228 }
7229
7230 /**
7231 * @brief FSM number of programs.[get]
7232 *
7233 * @param ctx read / write interface definitions
7234 * @param val FSM number of programs.
7235 * @retval interface status (MANDATORY: return 0 -> no Error)
7236 *
7237 */
lsm6dsv16bx_fsm_number_of_programs_get(stmdev_ctx_t * ctx,uint8_t * val)7238 int32_t lsm6dsv16bx_fsm_number_of_programs_get(stmdev_ctx_t *ctx, uint8_t *val)
7239 {
7240 lsm6dsv16bx_fsm_programs_t fsm_programs;
7241 int32_t ret;
7242
7243 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1);
7244 *val = fsm_programs.fsm_n_prog;
7245
7246
7247 return ret;
7248 }
7249
7250 /**
7251 * @brief FSM start address. First available address is 0x35C.[set]
7252 *
7253 * @param ctx read / write interface definitions
7254 * @param val FSM start address. First available address is 0x35C.
7255 * @retval interface status (MANDATORY: return 0 -> no Error)
7256 *
7257 */
lsm6dsv16bx_fsm_start_address_set(stmdev_ctx_t * ctx,uint16_t val)7258 int32_t lsm6dsv16bx_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val)
7259 {
7260 uint8_t buff[2];
7261 int32_t ret;
7262
7263 buff[1] = (uint8_t)(val / 256U);
7264 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7265 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_FSM_START_ADD_L, (uint8_t *)&buff[0], 2);
7266
7267 return ret;
7268 }
7269
7270 /**
7271 * @brief FSM start address. First available address is 0x35C.[get]
7272 *
7273 * @param ctx read / write interface definitions
7274 * @param val FSM start address. First available address is 0x35C.
7275 * @retval interface status (MANDATORY: return 0 -> no Error)
7276 *
7277 */
lsm6dsv16bx_fsm_start_address_get(stmdev_ctx_t * ctx,uint16_t * val)7278 int32_t lsm6dsv16bx_fsm_start_address_get(stmdev_ctx_t *ctx, uint16_t *val)
7279 {
7280 uint8_t buff[2];
7281 int32_t ret;
7282
7283 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_FSM_START_ADD_L, &buff[0], 2);
7284 *val = buff[1];
7285 *val = (*val * 256U) + buff[0];
7286
7287 return ret;
7288 }
7289
7290 /**
7291 * @}
7292 *
7293 */
7294
7295 /**
7296 * @addtogroup Machine Learning Core
7297 * @brief This section group all the functions concerning the
7298 * usage of Machine Learning Core
7299 * @{
7300 *
7301 */
7302
7303 /**
7304 * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[set]
7305 *
7306 * @param ctx read / write interface definitions
7307 * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM,
7308 * @retval interface status (MANDATORY: return 0 -> no Error)
7309 *
7310 */
lsm6dsv16bx_mlc_set(stmdev_ctx_t * ctx,lsm6dsv16bx_mlc_mode_t val)7311 int32_t lsm6dsv16bx_mlc_set(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t val)
7312 {
7313 lsm6dsv16bx_emb_func_en_b_t emb_en_b;
7314 lsm6dsv16bx_emb_func_en_a_t emb_en_a;
7315 int32_t ret;
7316
7317 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7318
7319 if (ret == 0)
7320 {
7321 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
7322 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
7323
7324 switch(val)
7325 {
7326 case LSM6DSV16BX_MLC_OFF:
7327 emb_en_a.mlc_before_fsm_en = 0;
7328 emb_en_b.mlc_en = 0;
7329 break;
7330 case LSM6DSV16BX_MLC_ON:
7331 emb_en_a.mlc_before_fsm_en = 0;
7332 emb_en_b.mlc_en = 1;
7333 break;
7334 case LSM6DSV16BX_MLC_ON_BEFORE_FSM:
7335 emb_en_a.mlc_before_fsm_en = 1;
7336 emb_en_b.mlc_en = 0;
7337 break;
7338 default:
7339 break;
7340 }
7341
7342 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
7343 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
7344 }
7345
7346 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7347
7348 return ret;
7349 }
7350
7351 /**
7352 * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[get]
7353 *
7354 * @param ctx read / write interface definitions
7355 * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM,
7356 * @retval interface status (MANDATORY: return 0 -> no Error)
7357 *
7358 */
lsm6dsv16bx_mlc_get(stmdev_ctx_t * ctx,lsm6dsv16bx_mlc_mode_t * val)7359 int32_t lsm6dsv16bx_mlc_get(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t *val)
7360 {
7361 lsm6dsv16bx_emb_func_en_b_t emb_en_b;
7362 lsm6dsv16bx_emb_func_en_a_t emb_en_a;
7363 int32_t ret;
7364
7365 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7366
7367 if (ret == 0)
7368 {
7369 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
7370 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
7371
7372 if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U)
7373 {
7374 *val = LSM6DSV16BX_MLC_OFF;
7375 }
7376 else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U)
7377 {
7378 *val = LSM6DSV16BX_MLC_ON;
7379 }
7380 else if (emb_en_a.mlc_before_fsm_en == 1U)
7381 {
7382 *val = LSM6DSV16BX_MLC_ON_BEFORE_FSM;
7383 }
7384 else
7385 {
7386 /* Do nothing */
7387 }
7388 }
7389
7390 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7391
7392 return ret;
7393 }
7394
7395 /**
7396 * @brief Machine Learning Core Output Data Rate (ODR) configuration.[set]
7397 *
7398 * @param ctx read / write interface definitions
7399 * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz,
7400 * @retval interface status (MANDATORY: return 0 -> no Error)
7401 *
7402 */
lsm6dsv16bx_mlc_data_rate_set(stmdev_ctx_t * ctx,lsm6dsv16bx_mlc_data_rate_t val)7403 int32_t lsm6dsv16bx_mlc_data_rate_set(stmdev_ctx_t *ctx,
7404 lsm6dsv16bx_mlc_data_rate_t val)
7405 {
7406 lsm6dsv16bx_mlc_odr_t mlc_odr;
7407 int32_t ret;
7408
7409 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7410 if (ret == 0)
7411 {
7412 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_ODR, (uint8_t *)&mlc_odr, 1);
7413 }
7414
7415 if (ret == 0)
7416 {
7417 mlc_odr.mlc_odr = (uint8_t)val & 0x07U;
7418 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_MLC_ODR, (uint8_t *)&mlc_odr, 1);
7419 }
7420
7421 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7422
7423 return ret;
7424 }
7425
7426 /**
7427 * @brief Machine Learning Core Output Data Rate (ODR) configuration.[get]
7428 *
7429 * @param ctx read / write interface definitions
7430 * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz,
7431 * @retval interface status (MANDATORY: return 0 -> no Error)
7432 *
7433 */
lsm6dsv16bx_mlc_data_rate_get(stmdev_ctx_t * ctx,lsm6dsv16bx_mlc_data_rate_t * val)7434 int32_t lsm6dsv16bx_mlc_data_rate_get(stmdev_ctx_t *ctx,
7435 lsm6dsv16bx_mlc_data_rate_t *val)
7436 {
7437 lsm6dsv16bx_mlc_odr_t mlc_odr;
7438 int32_t ret;
7439
7440 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7441 if (ret == 0)
7442 {
7443 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_ODR, (uint8_t *)&mlc_odr, 1);
7444 }
7445
7446 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7447
7448 switch (mlc_odr.mlc_odr)
7449 {
7450 case LSM6DSV16BX_MLC_15Hz:
7451 *val = LSM6DSV16BX_MLC_15Hz;
7452 break;
7453
7454 case LSM6DSV16BX_MLC_30Hz:
7455 *val = LSM6DSV16BX_MLC_30Hz;
7456 break;
7457
7458 case LSM6DSV16BX_MLC_60Hz:
7459 *val = LSM6DSV16BX_MLC_60Hz;
7460 break;
7461
7462 case LSM6DSV16BX_MLC_120Hz:
7463 *val = LSM6DSV16BX_MLC_120Hz;
7464 break;
7465
7466 case LSM6DSV16BX_MLC_240Hz:
7467 *val = LSM6DSV16BX_MLC_240Hz;
7468 break;
7469
7470 case LSM6DSV16BX_MLC_480Hz:
7471 *val = LSM6DSV16BX_MLC_480Hz;
7472 break;
7473
7474 case LSM6DSV16BX_MLC_960Hz:
7475 *val = LSM6DSV16BX_MLC_960Hz;
7476 break;
7477
7478 default:
7479 *val = LSM6DSV16BX_MLC_15Hz;
7480 break;
7481 }
7482 return ret;
7483 }
7484
7485 /**
7486 * @brief Output value of all MLC decision trees.[get]
7487 *
7488 * @param ctx read / write interface definitions
7489 * @param val Output value of all MLC decision trees.
7490 * @retval interface status (MANDATORY: return 0 -> no Error)
7491 *
7492 */
lsm6dsv16bx_mlc_out_get(stmdev_ctx_t * ctx,lsm6dsv16bx_mlc_out_t * val)7493 int32_t lsm6dsv16bx_mlc_out_get(stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_out_t *val)
7494 {
7495 int32_t ret;
7496
7497 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7498 if (ret == 0)
7499 {
7500 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC1_SRC, (uint8_t *)&val, 4);
7501 }
7502
7503 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7504 return ret;
7505 }
7506
7507 /**
7508 * @brief Qvar sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set]
7509 *
7510 * @param ctx read / write interface definitions
7511 * @param val Qvar sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
7512 * @retval interface status (MANDATORY: return 0 -> no Error)
7513 *
7514 */
lsm6dsv16bx_mlc_qvar_sensitivity_set(stmdev_ctx_t * ctx,uint16_t val)7515 int32_t lsm6dsv16bx_mlc_qvar_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val)
7516 {
7517 uint8_t buff[2];
7518 int32_t ret;
7519
7520 buff[1] = (uint8_t)(val / 256U);
7521 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7522 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_MLC_QVAR_SENSITIVITY_L, (uint8_t *)&buff[0], 2);
7523
7524 return ret;
7525 }
7526
7527 /**
7528 * @brief Qvar sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get]
7529 *
7530 * @param ctx read / write interface definitions
7531 * @param val Qvar sensor sensitivity value register for the Machine Learning Core. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
7532 * @retval interface status (MANDATORY: return 0 -> no Error)
7533 *
7534 */
lsm6dsv16bx_mlc_qvar_sensitivity_get(stmdev_ctx_t * ctx,uint16_t * val)7535 int32_t lsm6dsv16bx_mlc_qvar_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val)
7536 {
7537 uint8_t buff[2];
7538 int32_t ret;
7539
7540 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_MLC_QVAR_SENSITIVITY_L, &buff[0], 2);
7541 *val = buff[1];
7542 *val = (*val * 256U) + buff[0];
7543
7544 return ret;
7545 }
7546
7547 /**
7548 * @}
7549 *
7550 */
7551
7552 /**
7553 * @addtogroup Accelerometer user offset correction
7554 * @brief This section group all the functions concerning the
7555 * usage of Accelerometer user offset correction
7556 * @{
7557 *
7558 */
7559
7560 /**
7561 * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[set]
7562 *
7563 * @param ctx read / write interface definitions
7564 * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path.
7565 * @retval interface status (MANDATORY: return 0 -> no Error)
7566 *
7567 */
lsm6dsv16bx_xl_offset_on_out_set(stmdev_ctx_t * ctx,uint8_t val)7568 int32_t lsm6dsv16bx_xl_offset_on_out_set(stmdev_ctx_t *ctx, uint8_t val)
7569 {
7570 lsm6dsv16bx_ctrl9_t ctrl9;
7571 int32_t ret;
7572
7573 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
7574 if (ret == 0)
7575 {
7576 ctrl9.usr_off_on_out = val;
7577 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
7578 }
7579
7580 return ret;
7581 }
7582
7583 /**
7584 * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[get]
7585 *
7586 * @param ctx read / write interface definitions
7587 * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path.
7588 * @retval interface status (MANDATORY: return 0 -> no Error)
7589 *
7590 */
lsm6dsv16bx_xl_offset_on_out_get(stmdev_ctx_t * ctx,uint8_t * val)7591 int32_t lsm6dsv16bx_xl_offset_on_out_get(stmdev_ctx_t *ctx, uint8_t *val)
7592 {
7593 lsm6dsv16bx_ctrl9_t ctrl9;
7594 int32_t ret;
7595
7596 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
7597 *val = ctrl9.usr_off_on_out;
7598
7599 return ret;
7600 }
7601
7602 /**
7603 * @brief Accelerometer user offset correction values in mg.[set]
7604 *
7605 * @param ctx read / write interface definitions
7606 * @param val Accelerometer user offset correction values in mg.
7607 * @retval interface status (MANDATORY: return 0 -> no Error)
7608 *
7609 */
lsm6dsv16bx_xl_offset_mg_set(stmdev_ctx_t * ctx,lsm6dsv16bxxl_offset_mg_t val)7610 int32_t lsm6dsv16bx_xl_offset_mg_set(stmdev_ctx_t *ctx,
7611 lsm6dsv16bxxl_offset_mg_t val)
7612 {
7613 lsm6dsv16bx_z_ofs_usr_t z_ofs_usr;
7614 lsm6dsv16bx_y_ofs_usr_t y_ofs_usr;
7615 lsm6dsv16bx_x_ofs_usr_t x_ofs_usr;
7616 lsm6dsv16bx_ctrl9_t ctrl9;
7617 int32_t ret;
7618 float_t tmp;
7619
7620 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
7621 if (ret == 0)
7622 {
7623 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
7624 }
7625 if (ret == 0)
7626 {
7627 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
7628 }
7629 if (ret == 0)
7630 {
7631 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
7632 }
7633
7634
7635 if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) &&
7636 (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) &&
7637 (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f)))
7638 {
7639 ctrl9.usr_off_w = 0;
7640
7641 tmp = val.z_mg / 0.0078125f;
7642 z_ofs_usr.z_ofs_usr = (uint8_t)tmp;
7643
7644 tmp = val.y_mg / 0.0078125f;
7645 y_ofs_usr.y_ofs_usr = (uint8_t)tmp;
7646
7647 tmp = val.x_mg / 0.0078125f;
7648 x_ofs_usr.x_ofs_usr = (uint8_t)tmp;
7649 }
7650 else if ((val.x_mg < (0.125f * 127.0f)) && (val.x_mg > (0.125f * -127.0f)) &&
7651 (val.y_mg < (0.125f * 127.0f)) && (val.y_mg > (0.125f * -127.0f)) &&
7652 (val.z_mg < (0.125f * 127.0f)) && (val.z_mg > (0.125f * -127.0f)))
7653 {
7654 ctrl9.usr_off_w = 1;
7655
7656 tmp = val.z_mg / 0.125f;
7657 z_ofs_usr.z_ofs_usr = (uint8_t)tmp;
7658
7659 tmp = val.y_mg / 0.125f;
7660 y_ofs_usr.y_ofs_usr = (uint8_t)tmp;
7661
7662 tmp = val.x_mg / 0.125f;
7663 x_ofs_usr.x_ofs_usr = (uint8_t)tmp;
7664 }
7665 else // out of limit
7666 {
7667 ctrl9.usr_off_w = 1;
7668 z_ofs_usr.z_ofs_usr = 0xFFU;
7669 y_ofs_usr.y_ofs_usr = 0xFFU;
7670 x_ofs_usr.x_ofs_usr = 0xFFU;
7671 }
7672
7673 if (ret == 0)
7674 {
7675 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
7676 }
7677 if (ret == 0)
7678 {
7679 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
7680 }
7681 if (ret == 0)
7682 {
7683 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
7684 }
7685 if (ret == 0)
7686 {
7687 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
7688 }
7689 return ret;
7690 }
7691
7692 /**
7693 * @brief Accelerometer user offset correction values in mg.[get]
7694 *
7695 * @param ctx read / write interface definitions
7696 * @param val Accelerometer user offset correction values in mg.
7697 * @retval interface status (MANDATORY: return 0 -> no Error)
7698 *
7699 */
lsm6dsv16bx_xl_offset_mg_get(stmdev_ctx_t * ctx,lsm6dsv16bxxl_offset_mg_t * val)7700 int32_t lsm6dsv16bx_xl_offset_mg_get(stmdev_ctx_t *ctx,
7701 lsm6dsv16bxxl_offset_mg_t *val)
7702 {
7703 lsm6dsv16bx_z_ofs_usr_t z_ofs_usr;
7704 lsm6dsv16bx_y_ofs_usr_t y_ofs_usr;
7705 lsm6dsv16bx_x_ofs_usr_t x_ofs_usr;
7706 lsm6dsv16bx_ctrl9_t ctrl9;
7707 int32_t ret;
7708
7709 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
7710 if (ret == 0)
7711 {
7712 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
7713 }
7714 if (ret == 0)
7715 {
7716 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
7717 }
7718 if (ret == 0)
7719 {
7720 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
7721 }
7722
7723 if (ctrl9.usr_off_w == PROPERTY_DISABLE)
7724 {
7725 val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.0078125f);
7726 val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.0078125f);
7727 val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.0078125f);
7728 }
7729 else
7730 {
7731 val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.125f);
7732 val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.125f);
7733 val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.125f);
7734 }
7735
7736 return ret;
7737 }
7738
7739 /**
7740 * @}
7741 *
7742 */
7743
7744 /**
7745 * @addtogroup AH_QVAR
7746 * @brief This section group all the functions concerning the
7747 * usage of AH_QVAR
7748 * @{
7749 *
7750 */
7751
7752 /**
7753 * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/Qvar1 and SCx/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.[set]
7754 *
7755 * @param ctx read / write interface definitions
7756 * @param val Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/Qvar1 and SCx/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.
7757 * @retval interface status (MANDATORY: return 0 -> no Error)
7758 *
7759 */
lsm6dsv16bx_ah_qvar_mode_set(stmdev_ctx_t * ctx,lsm6dsv16bx_ah_qvar_mode_t val)7760 int32_t lsm6dsv16bx_ah_qvar_mode_set(stmdev_ctx_t *ctx,
7761 lsm6dsv16bx_ah_qvar_mode_t val)
7762 {
7763 lsm6dsv16bx_ctrl10_t ctrl10;
7764 lsm6dsv16bx_ctrl7_t ctrl7;
7765 int32_t ret;
7766
7767 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
7768 if (ret == 0)
7769 {
7770 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
7771 }
7772
7773 if (ret == 0)
7774 {
7775 if ((val.ah_qvar1_en | val.ah_qvar2_en) == PROPERTY_ENABLE)
7776 {
7777 ctrl7.ah_qvar_en = PROPERTY_ENABLE;
7778 }
7779 else
7780 {
7781 ctrl7.ah_qvar_en = PROPERTY_DISABLE;
7782 }
7783 ctrl7.ah_qvar1_en = val.ah_qvar1_en;
7784 ctrl7.ah_qvar2_en = val.ah_qvar2_en;
7785 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
7786 }
7787 if (ret == 0)
7788 {
7789 ctrl10.ah_qvar_sw = val.swaps;
7790 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
7791 }
7792 return ret;
7793 }
7794
7795 /**
7796 * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/Qvar1 and SCx/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.[get]
7797 *
7798 * @param ctx read / write interface definitions
7799 * @param val Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are connected to the SDx/Qvar1 and SCx/Qvar2 pins. Before setting this bit to 1, the accelerometer and gyroscope sensor have to be configured in power-down mode.
7800 * @retval interface status (MANDATORY: return 0 -> no Error)
7801 *
7802 */
lsm6dsv16bx_ah_qvar_mode_get(stmdev_ctx_t * ctx,lsm6dsv16bx_ah_qvar_mode_t * val)7803 int32_t lsm6dsv16bx_ah_qvar_mode_get(stmdev_ctx_t *ctx,
7804 lsm6dsv16bx_ah_qvar_mode_t *val)
7805 {
7806 lsm6dsv16bx_ctrl10_t ctrl10;
7807 lsm6dsv16bx_ctrl7_t ctrl7;
7808 int32_t ret;
7809
7810 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
7811 if (ret == 0)
7812 {
7813 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
7814 }
7815
7816 val->ah_qvar1_en = ctrl7.ah_qvar1_en;
7817 val->ah_qvar2_en = ctrl7.ah_qvar2_en;
7818 val->swaps = ctrl10.ah_qvar_sw;
7819
7820 return ret;
7821 }
7822
7823 /**
7824 * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[set]
7825 *
7826 * @param ctx read / write interface definitions
7827 * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm,
7828 * @retval interface status (MANDATORY: return 0 -> no Error)
7829 *
7830 */
lsm6dsv16bx_ah_qvar_zin_set(stmdev_ctx_t * ctx,lsm6dsv16bx_ah_qvar_zin_t val)7831 int32_t lsm6dsv16bx_ah_qvar_zin_set(stmdev_ctx_t *ctx,
7832 lsm6dsv16bx_ah_qvar_zin_t val)
7833 {
7834 lsm6dsv16bx_ctrl7_t ctrl7;
7835 int32_t ret;
7836
7837 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
7838 if (ret == 0)
7839 {
7840 ctrl7.ah_qvar_c_zin = (uint8_t)val & 0x03U;
7841 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
7842 }
7843
7844 return ret;
7845 }
7846
7847 /**
7848 * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[get]
7849 *
7850 * @param ctx read / write interface definitions
7851 * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm,
7852 * @retval interface status (MANDATORY: return 0 -> no Error)
7853 *
7854 */
lsm6dsv16bx_ah_qvar_zin_get(stmdev_ctx_t * ctx,lsm6dsv16bx_ah_qvar_zin_t * val)7855 int32_t lsm6dsv16bx_ah_qvar_zin_get(stmdev_ctx_t *ctx,
7856 lsm6dsv16bx_ah_qvar_zin_t *val)
7857 {
7858 lsm6dsv16bx_ctrl7_t ctrl7;
7859 int32_t ret;
7860
7861 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
7862 switch (ctrl7.ah_qvar_c_zin)
7863 {
7864 case LSM6DSV16BX_2400MOhm:
7865 *val = LSM6DSV16BX_2400MOhm;
7866 break;
7867
7868 case LSM6DSV16BX_730MOhm:
7869 *val = LSM6DSV16BX_730MOhm;
7870 break;
7871
7872 case LSM6DSV16BX_300MOhm:
7873 *val = LSM6DSV16BX_300MOhm;
7874 break;
7875
7876 case LSM6DSV16BX_255MOhm:
7877 *val = LSM6DSV16BX_255MOhm;
7878 break;
7879
7880 default:
7881 *val = LSM6DSV16BX_2400MOhm;
7882 break;
7883 }
7884 return ret;
7885 }
7886
7887 /**
7888 * @brief Qvar sensor sensitivity value register for the Finite State Machine. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set]
7889 *
7890 * @param ctx read / write interface definitions
7891 * @param val Qvar sensor sensitivity value register for the Finite State Machine. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
7892 * @retval interface status (MANDATORY: return 0 -> no Error)
7893 *
7894 */
lsm6dsv16bx_fsm_qvar_sensitivity_set(stmdev_ctx_t * ctx,uint16_t val)7895 int32_t lsm6dsv16bx_fsm_qvar_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val)
7896 {
7897 uint8_t buff[2];
7898 int32_t ret;
7899
7900 buff[1] = (uint8_t)(val / 256U);
7901 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7902 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_FSM_QVAR_SENSITIVITY_L, (uint8_t *)&buff[0], 2);
7903
7904 return ret;
7905 }
7906
7907 /**
7908 * @brief Qvar sensor sensitivity value register for the Finite State Machine. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get]
7909 *
7910 * @param ctx read / write interface definitions
7911 * @param val Qvar sensor sensitivity value register for the Finite State Machine. This register corresponds to the conversion value of the Qvar sensor. The register value is expressed as half-precision floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).
7912 * @retval interface status (MANDATORY: return 0 -> no Error)
7913 *
7914 */
lsm6dsv16bx_fsm_qvar_sensitivity_get(stmdev_ctx_t * ctx,uint16_t * val)7915 int32_t lsm6dsv16bx_fsm_qvar_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val)
7916 {
7917 uint8_t buff[2];
7918 int32_t ret;
7919
7920 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_FSM_QVAR_SENSITIVITY_L, &buff[0], 2);
7921 *val = buff[1];
7922 *val = (*val * 256U) + buff[0];
7923
7924 return ret;
7925 }
7926
7927 /**
7928 * @}
7929 *
7930 */
7931
7932 /**
7933 * @addtogroup SenseWire (I3C)
7934 * @brief This section group all the functions concerning the
7935 * usage of SenseWire (I3C)
7936 * @{
7937 *
7938 */
7939
7940 /**
7941 * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[set]
7942 *
7943 * @param ctx read / write interface definitions
7944 * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST_,
7945 * @retval interface status (MANDATORY: return 0 -> no Error)
7946 *
7947 */
lsm6dsv16bx_i3c_reset_mode_set(stmdev_ctx_t * ctx,lsm6dsv16bx_i3c_reset_mode_t val)7948 int32_t lsm6dsv16bx_i3c_reset_mode_set(stmdev_ctx_t *ctx,
7949 lsm6dsv16bx_i3c_reset_mode_t val)
7950 {
7951 lsm6dsv16bx_pin_ctrl_t pin_ctrl;
7952 int32_t ret;
7953
7954 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7955 if (ret == 0)
7956 {
7957 pin_ctrl.ibhr_por_en = (uint8_t)val & 0x01U;
7958 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7959 }
7960
7961 return ret;
7962 }
7963
7964 /**
7965 * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[get]
7966 *
7967 * @param ctx read / write interface definitions
7968 * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST_,
7969 * @retval interface status (MANDATORY: return 0 -> no Error)
7970 *
7971 */
lsm6dsv16bx_i3c_reset_mode_get(stmdev_ctx_t * ctx,lsm6dsv16bx_i3c_reset_mode_t * val)7972 int32_t lsm6dsv16bx_i3c_reset_mode_get(stmdev_ctx_t *ctx,
7973 lsm6dsv16bx_i3c_reset_mode_t *val)
7974 {
7975 lsm6dsv16bx_pin_ctrl_t pin_ctrl;
7976 int32_t ret;
7977
7978 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7979 switch (pin_ctrl.ibhr_por_en)
7980 {
7981 case LSM6DSV16BX_SW_RST_DYN_ADDRESS_RST:
7982 *val = LSM6DSV16BX_SW_RST_DYN_ADDRESS_RST;
7983 break;
7984
7985 case LSM6DSV16BX_I3C_GLOBAL_RST:
7986 *val = LSM6DSV16BX_I3C_GLOBAL_RST;
7987 break;
7988
7989 default:
7990 *val = LSM6DSV16BX_SW_RST_DYN_ADDRESS_RST;
7991 break;
7992 }
7993 return ret;
7994 }
7995
7996 /**
7997 * @}
7998 *
7999 */
8000
8001 /**
8002 * @addtogroup Time-Division Multiplexing (TDM)
8003 * @brief This section group all the functions concerning the
8004 * usage of Time-Division Multiplexing (TDM)
8005 * @{
8006 *
8007 */
8008
8009 /**
8010 * @brief Disables pull-up on WCLK pin.[set]
8011 *
8012 * @param ctx read / write interface definitions
8013 * @param val Disables pull-up on WCLK pin.
8014 * @retval interface status (MANDATORY: return 0 -> no Error)
8015 *
8016 */
lsm6dsv16bx_tdm_dis_wclk_pull_up_set(stmdev_ctx_t * ctx,uint8_t val)8017 int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_set(stmdev_ctx_t *ctx, uint8_t val)
8018 {
8019 lsm6dsv16bx_pin_ctrl_t pin_ctrl;
8020 int32_t ret;
8021
8022 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8023 if (ret == 0)
8024 {
8025 pin_ctrl.tdm_wclk_pu_dis = val;
8026 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8027 }
8028
8029 return ret;
8030 }
8031
8032 /**
8033 * @brief Disables pull-up on WCLK pin.[get]
8034 *
8035 * @param ctx read / write interface definitions
8036 * @param val Disables pull-up on WCLK pin.
8037 * @retval interface status (MANDATORY: return 0 -> no Error)
8038 *
8039 */
lsm6dsv16bx_tdm_dis_wclk_pull_up_get(stmdev_ctx_t * ctx,uint8_t * val)8040 int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val)
8041 {
8042 lsm6dsv16bx_pin_ctrl_t pin_ctrl;
8043 int32_t ret;
8044
8045 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8046 *val = pin_ctrl.tdm_wclk_pu_dis;
8047
8048 return ret;
8049 }
8050
8051 /**
8052 * @brief Enables pull-up on TDMout pin.[set]
8053 *
8054 * @param ctx read / write interface definitions
8055 * @param val Enables pull-up on TDMout pin.
8056 * @retval interface status (MANDATORY: return 0 -> no Error)
8057 *
8058 */
lsm6dsv16bx_tdm_tdmout_pull_up_set(stmdev_ctx_t * ctx,uint8_t val)8059 int32_t lsm6dsv16bx_tdm_tdmout_pull_up_set(stmdev_ctx_t *ctx, uint8_t val)
8060 {
8061 lsm6dsv16bx_if_cfg_t if_cfg;
8062 int32_t ret;
8063
8064 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
8065 if (ret == 0)
8066 {
8067 if_cfg.tdm_out_pu_en = val;
8068 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
8069 }
8070
8071 return ret;
8072 }
8073
8074 /**
8075 * @brief Enables pull-up on TDMout pin.[get]
8076 *
8077 * @param ctx read / write interface definitions
8078 * @param val Enables pull-up on TDMout pin.
8079 * @retval interface status (MANDATORY: return 0 -> no Error)
8080 *
8081 */
lsm6dsv16bx_tdm_tdmout_pull_up_get(stmdev_ctx_t * ctx,uint8_t * val)8082 int32_t lsm6dsv16bx_tdm_tdmout_pull_up_get(stmdev_ctx_t *ctx, uint8_t *val)
8083 {
8084 lsm6dsv16bx_if_cfg_t if_cfg;
8085 int32_t ret;
8086
8087 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
8088 *val = if_cfg.tdm_out_pu_en;
8089
8090 return ret;
8091 }
8092
8093 /**
8094 * @brief WCLK and BCLK frequencies.[set]
8095 *
8096 * @param ctx read / write interface definitions
8097 * @param val WCLK_8kHZ_1024kHz, WCLK_16kHZ_2048kHz, WCLK_8kHZ_2048kHz, WCLK_16kHZ_1024kHz,
8098 * @retval interface status (MANDATORY: return 0 -> no Error)
8099 *
8100 */
lsm6dsv16bx_tdm_wclk_bclk_set(stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_wclk_bclk_t val)8101 int32_t lsm6dsv16bx_tdm_wclk_bclk_set(stmdev_ctx_t *ctx,
8102 lsm6dsv16bx_tdm_wclk_bclk_t val)
8103 {
8104 lsm6dsv16bx_tdm_cfg0_t tdm_cfg0;
8105 int32_t ret;
8106
8107 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8108 if (ret == 0)
8109 {
8110 tdm_cfg0.tdm_wclk_bclk_sel = ((uint8_t)val & 0x4U) >> 2;
8111 tdm_cfg0.tdm_wclk = (uint8_t)val & 0x3U;
8112 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8113 }
8114
8115 return ret;
8116 }
8117
8118 /**
8119 * @brief WCLK and BCLK frequencies.[get]
8120 *
8121 * @param ctx read / write interface definitions
8122 * @param val WCLK_8kHZ_1024kHz, WCLK_16kHZ_2048kHz, WCLK_8kHZ_2048kHz, WCLK_16kHZ_1024kHz,
8123 * @retval interface status (MANDATORY: return 0 -> no Error)
8124 *
8125 */
lsm6dsv16bx_tdm_wclk_bclk_get(stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_wclk_bclk_t * val)8126 int32_t lsm6dsv16bx_tdm_wclk_bclk_get(stmdev_ctx_t *ctx,
8127 lsm6dsv16bx_tdm_wclk_bclk_t *val)
8128 {
8129 lsm6dsv16bx_tdm_cfg0_t tdm_cfg0;
8130 int32_t ret;
8131
8132 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8133 switch ((tdm_cfg0.tdm_wclk_bclk_sel << 2) + tdm_cfg0.tdm_wclk)
8134 {
8135 case LSM6DSV16BX_WCLK_16kHZ_BCLK_2048kHz:
8136 *val = LSM6DSV16BX_WCLK_16kHZ_BCLK_2048kHz;
8137 break;
8138
8139 case LSM6DSV16BX_WCLK_8kHZ_BCLK_2048kHz:
8140 *val = LSM6DSV16BX_WCLK_8kHZ_BCLK_2048kHz;
8141 break;
8142
8143 default:
8144 *val = LSM6DSV16BX_WCLK_8kHZ_BCLK_2048kHz;
8145 break;
8146 }
8147 return ret;
8148 }
8149
8150 /**
8151 * @brief Selection of TDM slot for transmission.[set]
8152 *
8153 * @param ctx read / write interface definitions
8154 * @param val SLOT_012, SLOT_456,
8155 * @retval interface status (MANDATORY: return 0 -> no Error)
8156 *
8157 */
lsm6dsv16bx_tdm_slot_set(stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_slot_t val)8158 int32_t lsm6dsv16bx_tdm_slot_set(stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_slot_t val)
8159 {
8160 lsm6dsv16bx_tdm_cfg0_t tdm_cfg0;
8161 int32_t ret;
8162
8163 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8164 if (ret == 0)
8165 {
8166 tdm_cfg0.tdm_slot_sel = (uint8_t)val & 0x01U;
8167 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8168 }
8169
8170 return ret;
8171 }
8172
8173 /**
8174 * @brief Selection of TDM slot for transmission.[get]
8175 *
8176 * @param ctx read / write interface definitions
8177 * @param val SLOT_012, SLOT_456,
8178 * @retval interface status (MANDATORY: return 0 -> no Error)
8179 *
8180 */
lsm6dsv16bx_tdm_slot_get(stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_slot_t * val)8181 int32_t lsm6dsv16bx_tdm_slot_get(stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_slot_t *val)
8182 {
8183 lsm6dsv16bx_tdm_cfg0_t tdm_cfg0;
8184 int32_t ret;
8185
8186 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8187 switch (tdm_cfg0.tdm_slot_sel)
8188 {
8189 case LSM6DSV16BX_SLOT_012:
8190 *val = LSM6DSV16BX_SLOT_012;
8191 break;
8192
8193 case LSM6DSV16BX_SLOT_456:
8194 *val = LSM6DSV16BX_SLOT_456;
8195 break;
8196
8197 default:
8198 *val = LSM6DSV16BX_SLOT_012;
8199 break;
8200 }
8201 return ret;
8202 }
8203
8204 /**
8205 * @brief BCLK edge selection for TDM interface.[set]
8206 *
8207 * @param ctx read / write interface definitions
8208 * @param val BCLK_RISING, BCLK_FALLING,
8209 * @retval interface status (MANDATORY: return 0 -> no Error)
8210 *
8211 */
lsm6dsv16bx_tdm_bclk_edge_set(stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_bclk_edge_t val)8212 int32_t lsm6dsv16bx_tdm_bclk_edge_set(stmdev_ctx_t *ctx,
8213 lsm6dsv16bx_tdm_bclk_edge_t val)
8214 {
8215 lsm6dsv16bx_tdm_cfg0_t tdm_cfg0;
8216 int32_t ret;
8217
8218 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8219 if (ret == 0)
8220 {
8221 tdm_cfg0.tdm_bclk_edge_sel = (uint8_t)val & 0x01U;
8222 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8223 }
8224
8225 return ret;
8226 }
8227
8228 /**
8229 * @brief BCLK edge selection for TDM interface.[get]
8230 *
8231 * @param ctx read / write interface definitions
8232 * @param val BCLK_RISING, BCLK_FALLING,
8233 * @retval interface status (MANDATORY: return 0 -> no Error)
8234 *
8235 */
lsm6dsv16bx_tdm_bclk_edge_get(stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_bclk_edge_t * val)8236 int32_t lsm6dsv16bx_tdm_bclk_edge_get(stmdev_ctx_t *ctx,
8237 lsm6dsv16bx_tdm_bclk_edge_t *val)
8238 {
8239 lsm6dsv16bx_tdm_cfg0_t tdm_cfg0;
8240 int32_t ret;
8241
8242 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8243 switch (tdm_cfg0.tdm_bclk_edge_sel)
8244 {
8245 case LSM6DSV16BX_BCLK_RISING:
8246 *val = LSM6DSV16BX_BCLK_RISING;
8247 break;
8248
8249 case LSM6DSV16BX_BCLK_FALLING:
8250 *val = LSM6DSV16BX_BCLK_FALLING;
8251 break;
8252
8253 default:
8254 *val = LSM6DSV16BX_BCLK_RISING;
8255 break;
8256 }
8257 return ret;
8258 }
8259
8260 /**
8261 * @brief Enables TDM delayed configuration.[set]
8262 *
8263 * @param ctx read / write interface definitions
8264 * @param val Enables TDM delayed configuration.
8265 * @retval interface status (MANDATORY: return 0 -> no Error)
8266 *
8267 */
lsm6dsv16bx_tdm_delayed_conf_set(stmdev_ctx_t * ctx,uint8_t val)8268 int32_t lsm6dsv16bx_tdm_delayed_conf_set(stmdev_ctx_t *ctx, uint8_t val)
8269 {
8270 lsm6dsv16bx_tdm_cfg0_t tdm_cfg0;
8271 int32_t ret;
8272
8273 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8274 if (ret == 0)
8275 {
8276 tdm_cfg0.tdm_delayed_cfg = val;
8277 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8278 }
8279
8280 return ret;
8281 }
8282
8283 /**
8284 * @brief Enables TDM delayed configuration.[get]
8285 *
8286 * @param ctx read / write interface definitions
8287 * @param val Enables TDM delayed configuration.
8288 * @retval interface status (MANDATORY: return 0 -> no Error)
8289 *
8290 */
lsm6dsv16bx_tdm_delayed_conf_get(stmdev_ctx_t * ctx,uint8_t * val)8291 int32_t lsm6dsv16bx_tdm_delayed_conf_get(stmdev_ctx_t *ctx, uint8_t *val)
8292 {
8293 lsm6dsv16bx_tdm_cfg0_t tdm_cfg0;
8294 int32_t ret;
8295
8296 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8297 *val = tdm_cfg0.tdm_delayed_cfg;
8298
8299 return ret;
8300 }
8301
8302
8303 /**
8304 * @brief Selects order of transmission of TDM axes.[set]
8305 *
8306 * @param ctx read / write interface definitions
8307 * @param val TDM_ORDER_ZYX, TDM_ORDER_XZY, TDM_ORDER_XYZ,
8308 * @retval interface status (MANDATORY: return 0 -> no Error)
8309 *
8310 */
lsm6dsv16bx_tdm_axis_order_set(stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_axis_order_t val)8311 int32_t lsm6dsv16bx_tdm_axis_order_set(stmdev_ctx_t *ctx,
8312 lsm6dsv16bx_tdm_axis_order_t val)
8313 {
8314 lsm6dsv16bx_tdm_cfg1_t tdm_cfg1;
8315 int32_t ret;
8316
8317 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
8318 if (ret == 0)
8319 {
8320 tdm_cfg1.tdm_axes_ord_sel = (uint8_t)val & 0x03U;
8321 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
8322 }
8323
8324 return ret;
8325 }
8326
8327 /**
8328 * @brief Selects order of transmission of TDM axes.[get]
8329 *
8330 * @param ctx read / write interface definitions
8331 * @param val TDM_ORDER_ZYX, TDM_ORDER_XZY, TDM_ORDER_XYZ,
8332 * @retval interface status (MANDATORY: return 0 -> no Error)
8333 *
8334 */
lsm6dsv16bx_tdm_axis_order_get(stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_axis_order_t * val)8335 int32_t lsm6dsv16bx_tdm_axis_order_get(stmdev_ctx_t *ctx,
8336 lsm6dsv16bx_tdm_axis_order_t *val)
8337 {
8338 lsm6dsv16bx_tdm_cfg1_t tdm_cfg1;
8339 int32_t ret;
8340
8341 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
8342 switch (tdm_cfg1.tdm_axes_ord_sel)
8343 {
8344 case LSM6DSV16BX_TDM_ORDER_ZYX:
8345 *val = LSM6DSV16BX_TDM_ORDER_ZYX;
8346 break;
8347
8348 case LSM6DSV16BX_TDM_ORDER_XZY:
8349 *val = LSM6DSV16BX_TDM_ORDER_XZY;
8350 break;
8351
8352 case LSM6DSV16BX_TDM_ORDER_XYZ:
8353 *val = LSM6DSV16BX_TDM_ORDER_XYZ;
8354 break;
8355
8356 default:
8357 *val = LSM6DSV16BX_TDM_ORDER_ZYX;
8358 break;
8359 }
8360 return ret;
8361 }
8362
8363 /**
8364 * @brief TDM channel accelerometer full-scale selection.[set]
8365 *
8366 * @param ctx read / write interface definitions
8367 * @param val TDM_2g, TDM_4g, TDM_8g,
8368 * @retval interface status (MANDATORY: return 0 -> no Error)
8369 *
8370 */
lsm6dsv16bx_tdm_xl_full_scale_set(stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_xl_full_scale_t val)8371 int32_t lsm6dsv16bx_tdm_xl_full_scale_set(stmdev_ctx_t *ctx,
8372 lsm6dsv16bx_tdm_xl_full_scale_t val)
8373 {
8374 lsm6dsv16bx_tdm_cfg2_t tdm_cfg2;
8375 int32_t ret;
8376
8377 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
8378 if (ret == 0)
8379 {
8380 tdm_cfg2.tdm_fs_xl = (uint8_t)val & 0x3U;
8381 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
8382 }
8383
8384 return ret;
8385 }
8386
8387 /**
8388 * @brief TDM channel accelerometer full-scale selection.[get]
8389 *
8390 * @param ctx read / write interface definitions
8391 * @param val TDM_2g, TDM_4g, TDM_8g,
8392 * @retval interface status (MANDATORY: return 0 -> no Error)
8393 *
8394 */
lsm6dsv16bx_tdm_xl_full_scale_get(stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_xl_full_scale_t * val)8395 int32_t lsm6dsv16bx_tdm_xl_full_scale_get(stmdev_ctx_t *ctx,
8396 lsm6dsv16bx_tdm_xl_full_scale_t *val)
8397 {
8398 lsm6dsv16bx_tdm_cfg2_t tdm_cfg2;
8399 int32_t ret;
8400
8401 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
8402 switch (tdm_cfg2.tdm_fs_xl)
8403 {
8404 case LSM6DSV16BX_TDM_2g:
8405 *val = LSM6DSV16BX_TDM_2g;
8406 break;
8407
8408 case LSM6DSV16BX_TDM_4g:
8409 *val = LSM6DSV16BX_TDM_4g;
8410 break;
8411
8412 case LSM6DSV16BX_TDM_8g:
8413 *val = LSM6DSV16BX_TDM_8g;
8414 break;
8415
8416 default:
8417 *val = LSM6DSV16BX_TDM_2g;
8418 break;
8419 }
8420 return ret;
8421 }
8422
8423 /**
8424 * @}
8425 *
8426 */
8427
8428 /**
8429 * @}
8430 *
8431 */
8432
8433 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
8434
