1 /**
2 ******************************************************************************
3 * @file lsm6dsv16bx_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSV16BX driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dsv16bx_reg.h"
21
22 /**
23 * @defgroup LSM6DSV16BX
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dsv16bx enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup Interfaces functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx communication interface handler.(ptr)
43 * @param reg first register address to read.
44 * @param data buffer for data read.(ptr)
45 * @param len number of consecutive register to read.
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6dsv16bx_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dsv16bx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx communication interface handler.(ptr)
69 * @param reg first register address to write.
70 * @param data the buffer contains data to be written.(ptr)
71 * @param len number of consecutive register to write.
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lsm6dsv16bx_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lsm6dsv16bx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup Private functions
98 * @brief Section collect all the utility functions needed by APIs.
99 * @{
100 *
101 */
102
bytecpy(uint8_t * target,uint8_t * source)103 static void bytecpy(uint8_t *target, uint8_t *source)
104 {
105 if ((target != NULL) && (source != NULL))
106 {
107 *target = *source;
108 }
109 }
110
111 /**
112 * @}
113 *
114 */
115
116 /**
117 * @defgroup Sensitivity
118 * @brief These functions convert raw-data into engineering units.
119 * @{
120 *
121 */
lsm6dsv16bx_from_sflp_to_mg(int16_t lsb)122 float_t lsm6dsv16bx_from_sflp_to_mg(int16_t lsb)
123 {
124 return ((float_t)lsb) * 0.061f;
125 }
126
lsm6dsv16bx_from_fs2_to_mg(int16_t lsb)127 float_t lsm6dsv16bx_from_fs2_to_mg(int16_t lsb)
128 {
129 return ((float_t)lsb) * 0.061f;
130 }
131
lsm6dsv16bx_from_fs4_to_mg(int16_t lsb)132 float_t lsm6dsv16bx_from_fs4_to_mg(int16_t lsb)
133 {
134 return ((float_t)lsb) * 0.122f;
135 }
136
lsm6dsv16bx_from_fs8_to_mg(int16_t lsb)137 float_t lsm6dsv16bx_from_fs8_to_mg(int16_t lsb)
138 {
139 return ((float_t)lsb) * 0.244f;
140 }
141
lsm6dsv16bx_from_fs16_to_mg(int16_t lsb)142 float_t lsm6dsv16bx_from_fs16_to_mg(int16_t lsb)
143 {
144 return ((float_t)lsb) * 0.488f;
145 }
146
lsm6dsv16bx_from_fs125_to_mdps(int16_t lsb)147 float_t lsm6dsv16bx_from_fs125_to_mdps(int16_t lsb)
148 {
149 return ((float_t)lsb) * 4.375f;
150 }
151
lsm6dsv16bx_from_fs250_to_mdps(int16_t lsb)152 float_t lsm6dsv16bx_from_fs250_to_mdps(int16_t lsb)
153 {
154 return ((float_t)lsb) * 8.750f;
155 }
156
lsm6dsv16bx_from_fs500_to_mdps(int16_t lsb)157 float_t lsm6dsv16bx_from_fs500_to_mdps(int16_t lsb)
158 {
159 return ((float_t)lsb) * 17.50f;
160 }
161
lsm6dsv16bx_from_fs1000_to_mdps(int16_t lsb)162 float_t lsm6dsv16bx_from_fs1000_to_mdps(int16_t lsb)
163 {
164 return ((float_t)lsb) * 35.0f;
165 }
166
lsm6dsv16bx_from_fs2000_to_mdps(int16_t lsb)167 float_t lsm6dsv16bx_from_fs2000_to_mdps(int16_t lsb)
168 {
169 return ((float_t)lsb) * 70.0f;
170 }
171
lsm6dsv16bx_from_fs4000_to_mdps(int16_t lsb)172 float_t lsm6dsv16bx_from_fs4000_to_mdps(int16_t lsb)
173 {
174 return ((float_t)lsb) * 140.0f;
175 }
176
lsm6dsv16bx_from_lsb_to_celsius(int16_t lsb)177 float_t lsm6dsv16bx_from_lsb_to_celsius(int16_t lsb)
178 {
179 return (((float_t)lsb / 256.0f) + 25.0f);
180 }
181
lsm6dsv16bx_from_lsb_to_nsec(uint32_t lsb)182 uint64_t lsm6dsv16bx_from_lsb_to_nsec(uint32_t lsb)
183 {
184 return ((uint64_t)lsb * 21750);
185 }
186
lsm6dsv16bx_from_lsb_to_mv(int16_t lsb)187 float_t lsm6dsv16bx_from_lsb_to_mv(int16_t lsb)
188 {
189 return ((float_t)lsb) / 78.0f;
190 }
191
192 /**
193 * @}
194 *
195 */
196
197 /**
198 * @defgroup Common
199 * @brief This section groups common useful functions.
200 *
201 */
202
203 /**
204 * @brief Reset of the device.[set]
205 *
206 * @param ctx read / write interface definitions
207 * @param val Reset of the device.
208 * @retval interface status (MANDATORY: return 0 -> no Error)
209 *
210 */
lsm6dsv16bx_reset_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_reset_t val)211 int32_t lsm6dsv16bx_reset_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t val)
212 {
213 lsm6dsv16bx_func_cfg_access_t func_cfg_access;
214 lsm6dsv16bx_ctrl3_t ctrl3;
215 int32_t ret;
216
217 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1);
218 if (ret == 0)
219 {
220 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
221 }
222
223 ctrl3.boot = ((uint8_t)val & 0x04U) >> 2;
224 ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1;
225 func_cfg_access.sw_por = (uint8_t)val & 0x01U;
226
227 if (ret == 0)
228 {
229 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1);
230 }
231 if (ret == 0)
232 {
233 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
234 }
235
236 return ret;
237 }
238
239 /**
240 * @brief Global reset of the device.[get]
241 *
242 * @param ctx read / write interface definitions
243 * @param val Global reset of the device.
244 * @retval interface status (MANDATORY: return 0 -> no Error)
245 *
246 */
lsm6dsv16bx_reset_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_reset_t * val)247 int32_t lsm6dsv16bx_reset_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_reset_t *val)
248 {
249 lsm6dsv16bx_func_cfg_access_t func_cfg_access;
250 lsm6dsv16bx_ctrl3_t ctrl3;
251 int32_t ret;
252
253 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1);
254 if (ret == 0)
255 {
256 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
257 }
258
259 switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por)
260 {
261 case LSM6DSV16BX_READY:
262 *val = LSM6DSV16BX_READY;
263 break;
264
265 case LSM6DSV16BX_GLOBAL_RST:
266 *val = LSM6DSV16BX_GLOBAL_RST;
267 break;
268
269 case LSM6DSV16BX_RESTORE_CAL_PARAM:
270 *val = LSM6DSV16BX_RESTORE_CAL_PARAM;
271 break;
272
273 case LSM6DSV16BX_RESTORE_CTRL_REGS:
274 *val = LSM6DSV16BX_RESTORE_CTRL_REGS;
275 break;
276
277 default:
278 *val = LSM6DSV16BX_GLOBAL_RST;
279 break;
280 }
281 return ret;
282 }
283
284 /**
285 * @brief Change memory bank.[set]
286 *
287 * @param ctx read / write interface definitions
288 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK,
289 * @retval interface status (MANDATORY: return 0 -> no Error)
290 *
291 */
lsm6dsv16bx_mem_bank_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_mem_bank_t val)292 int32_t lsm6dsv16bx_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_mem_bank_t val)
293 {
294 lsm6dsv16bx_func_cfg_access_t func_cfg_access;
295 int32_t ret;
296
297 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
298 if (ret == 0)
299 {
300 func_cfg_access.emb_func_reg_access = (uint8_t)val & 0x01U;
301 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
302 }
303
304 return ret;
305 }
306
307 /**
308 * @brief Change memory bank.[get]
309 *
310 * @param ctx read / write interface definitions
311 * @param val MAIN_MEM_BANK, SENSOR_HUB_MEM_BANK, EMBED_FUNC_MEM_BANK,
312 * @retval interface status (MANDATORY: return 0 -> no Error)
313 *
314 */
lsm6dsv16bx_mem_bank_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_mem_bank_t * val)315 int32_t lsm6dsv16bx_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_mem_bank_t *val)
316 {
317 lsm6dsv16bx_func_cfg_access_t func_cfg_access;
318 int32_t ret;
319
320 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
321
322 switch (func_cfg_access.emb_func_reg_access)
323 {
324 case LSM6DSV16BX_MAIN_MEM_BANK:
325 *val = LSM6DSV16BX_MAIN_MEM_BANK;
326 break;
327
328 case LSM6DSV16BX_EMBED_FUNC_MEM_BANK:
329 *val = LSM6DSV16BX_EMBED_FUNC_MEM_BANK;
330 break;
331
332 default:
333 *val = LSM6DSV16BX_MAIN_MEM_BANK;
334 break;
335 }
336 return ret;
337 }
338
339 /**
340 * @brief Device ID.[get]
341 *
342 * @param ctx read / write interface definitions
343 * @param val Device ID.
344 * @retval interface status (MANDATORY: return 0 -> no Error)
345 *
346 */
lsm6dsv16bx_device_id_get(const stmdev_ctx_t * ctx,uint8_t * val)347 int32_t lsm6dsv16bx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val)
348 {
349 lsm6dsv16bx_who_am_i_t who_am_i;
350 int32_t ret;
351
352 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WHO_AM_I, (uint8_t *)&who_am_i, 1);
353 *val = who_am_i.id;
354
355 return ret;
356 }
357
358 /**
359 * @brief Accelerometer output data rate (ODR) selection.[set]
360 *
361 * @param ctx read / write interface definitions
362 * @param val lsm6dsv16bx_xl_data_rate_t enum
363 * @retval interface status (MANDATORY: return 0 -> no Error)
364 *
365 */
lsm6dsv16bx_xl_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_xl_data_rate_t val)366 int32_t lsm6dsv16bx_xl_data_rate_set(const stmdev_ctx_t *ctx,
367 lsm6dsv16bx_xl_data_rate_t val)
368 {
369 lsm6dsv16bx_ctrl1_t ctrl1;
370 int32_t ret;
371
372 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1);
373 if (ret == 0)
374 {
375 ctrl1.odr_xl = (uint8_t)val & 0xFU;
376 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1);
377 }
378
379 return ret;
380 }
381
382 /**
383 * @brief Accelerometer output data rate (ODR) selection.[get]
384 *
385 * @param ctx read / write interface definitions
386 * @param val lsm6dsv16bx_xl_data_rate_t enum
387 * @retval interface status (MANDATORY: return 0 -> no Error)
388 *
389 */
lsm6dsv16bx_xl_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_xl_data_rate_t * val)390 int32_t lsm6dsv16bx_xl_data_rate_get(const stmdev_ctx_t *ctx,
391 lsm6dsv16bx_xl_data_rate_t *val)
392 {
393 lsm6dsv16bx_ctrl1_t ctrl1;
394 int32_t ret;
395
396 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1);
397
398 switch (ctrl1.odr_xl)
399 {
400 case LSM6DSV16BX_XL_ODR_OFF:
401 *val = LSM6DSV16BX_XL_ODR_OFF;
402 break;
403
404 case LSM6DSV16BX_XL_ODR_AT_1Hz875:
405 *val = LSM6DSV16BX_XL_ODR_AT_1Hz875;
406 break;
407
408 case LSM6DSV16BX_XL_ODR_AT_7Hz5:
409 *val = LSM6DSV16BX_XL_ODR_AT_7Hz5;
410 break;
411
412 case LSM6DSV16BX_XL_ODR_AT_15Hz:
413 *val = LSM6DSV16BX_XL_ODR_AT_15Hz;
414 break;
415
416 case LSM6DSV16BX_XL_ODR_AT_30Hz:
417 *val = LSM6DSV16BX_XL_ODR_AT_30Hz;
418 break;
419
420 case LSM6DSV16BX_XL_ODR_AT_60Hz:
421 *val = LSM6DSV16BX_XL_ODR_AT_60Hz;
422 break;
423
424 case LSM6DSV16BX_XL_ODR_AT_120Hz:
425 *val = LSM6DSV16BX_XL_ODR_AT_120Hz;
426 break;
427
428 case LSM6DSV16BX_XL_ODR_AT_240Hz:
429 *val = LSM6DSV16BX_XL_ODR_AT_240Hz;
430 break;
431
432 case LSM6DSV16BX_XL_ODR_AT_480Hz:
433 *val = LSM6DSV16BX_XL_ODR_AT_480Hz;
434 break;
435
436 case LSM6DSV16BX_XL_ODR_AT_960Hz:
437 *val = LSM6DSV16BX_XL_ODR_AT_960Hz;
438 break;
439
440 case LSM6DSV16BX_XL_ODR_AT_1920Hz:
441 *val = LSM6DSV16BX_XL_ODR_AT_1920Hz;
442 break;
443
444 case LSM6DSV16BX_XL_ODR_AT_3840Hz:
445 *val = LSM6DSV16BX_XL_ODR_AT_3840Hz;
446 break;
447
448 case LSM6DSV16BX_XL_ODR_AT_7680Hz:
449 *val = LSM6DSV16BX_XL_ODR_AT_7680Hz;
450 break;
451
452 default:
453 *val = LSM6DSV16BX_XL_ODR_OFF;
454 break;
455 }
456 return ret;
457 }
458
459 /**
460 * @brief Accelerometer operating mode selection.[set]
461 *
462 * @param ctx read / write interface definitions
463 * @param val lsm6dsv16bx_xl_mode_t struct
464 * @retval interface status (MANDATORY: return 0 -> no Error)
465 *
466 */
lsm6dsv16bx_xl_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_xl_mode_t val)467 int32_t lsm6dsv16bx_xl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t val)
468 {
469 lsm6dsv16bx_ctrl1_t ctrl1;
470 int32_t ret;
471
472 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1);
473
474 if (ret == 0)
475 {
476 ctrl1.op_mode_xl = (uint8_t)val & 0x07U;
477 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1);
478 }
479
480 return ret;
481 }
482
483 /**
484 * @brief Accelerometer operating mode selection.[get]
485 *
486 * @param ctx read / write interface definitions
487 * @param val lsm6dsv16bx_xl_mode_t struct
488 * @retval interface status (MANDATORY: return 0 -> no Error)
489 *
490 */
lsm6dsv16bx_xl_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_xl_mode_t * val)491 int32_t lsm6dsv16bx_xl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_xl_mode_t *val)
492 {
493 lsm6dsv16bx_ctrl1_t ctrl1;
494 int32_t ret;
495
496 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL1, (uint8_t *)&ctrl1, 1);
497
498 switch (ctrl1.op_mode_xl)
499 {
500 case LSM6DSV16BX_XL_HIGH_PERFORMANCE_MD:
501 *val = LSM6DSV16BX_XL_HIGH_PERFORMANCE_MD;
502 break;
503
504 case LSM6DSV16BX_XL_HIGH_PERFORMANCE_TDM_MD:
505 *val = LSM6DSV16BX_XL_HIGH_PERFORMANCE_TDM_MD;
506 break;
507
508 case LSM6DSV16BX_XL_LOW_POWER_2_AVG_MD:
509 *val = LSM6DSV16BX_XL_LOW_POWER_2_AVG_MD;
510 break;
511
512 case LSM6DSV16BX_XL_LOW_POWER_4_AVG_MD:
513 *val = LSM6DSV16BX_XL_LOW_POWER_4_AVG_MD;
514 break;
515
516 case LSM6DSV16BX_XL_LOW_POWER_8_AVG_MD:
517 *val = LSM6DSV16BX_XL_LOW_POWER_8_AVG_MD;
518 break;
519
520 default:
521 *val = LSM6DSV16BX_XL_HIGH_PERFORMANCE_MD;
522 break;
523 }
524 return ret;
525 }
526
527 /**
528 * @brief Gyroscope output data rate (ODR) selection.[set]
529 *
530 * @param ctx read / write interface definitions
531 * @param val lsm6dsv16bx_gy_data_rate_t enum
532 * @retval interface status (MANDATORY: return 0 -> no Error)
533 *
534 */
lsm6dsv16bx_gy_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_gy_data_rate_t val)535 int32_t lsm6dsv16bx_gy_data_rate_set(const stmdev_ctx_t *ctx,
536 lsm6dsv16bx_gy_data_rate_t val)
537 {
538 lsm6dsv16bx_ctrl2_t ctrl2;
539 int32_t ret;
540
541 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1);
542
543 if (ret == 0)
544 {
545 ctrl2.odr_g = (uint8_t)val & 0xFU;
546 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1);
547 }
548
549 return ret;
550 }
551
552 /**
553 * @brief Gyroscope output data rate (ODR) selection.[get]
554 *
555 * @param ctx read / write interface definitions
556 * @param val lsm6dsv16bx_gy_data_rate_t enum
557 * @retval interface status (MANDATORY: return 0 -> no Error)
558 *
559 */
lsm6dsv16bx_gy_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_gy_data_rate_t * val)560 int32_t lsm6dsv16bx_gy_data_rate_get(const stmdev_ctx_t *ctx,
561 lsm6dsv16bx_gy_data_rate_t *val)
562 {
563 lsm6dsv16bx_ctrl2_t ctrl2;
564 int32_t ret;
565
566 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1);
567
568 switch (ctrl2.odr_g)
569 {
570 case LSM6DSV16BX_GY_ODR_OFF:
571 *val = LSM6DSV16BX_GY_ODR_OFF;
572 break;
573
574 case LSM6DSV16BX_GY_ODR_AT_7Hz5:
575 *val = LSM6DSV16BX_GY_ODR_AT_7Hz5;
576 break;
577
578 case LSM6DSV16BX_GY_ODR_AT_15Hz:
579 *val = LSM6DSV16BX_GY_ODR_AT_15Hz;
580 break;
581
582 case LSM6DSV16BX_GY_ODR_AT_30Hz:
583 *val = LSM6DSV16BX_GY_ODR_AT_30Hz;
584 break;
585
586 case LSM6DSV16BX_GY_ODR_AT_60Hz:
587 *val = LSM6DSV16BX_GY_ODR_AT_60Hz;
588 break;
589
590 case LSM6DSV16BX_GY_ODR_AT_120Hz:
591 *val = LSM6DSV16BX_GY_ODR_AT_120Hz;
592 break;
593
594 case LSM6DSV16BX_GY_ODR_AT_240Hz:
595 *val = LSM6DSV16BX_GY_ODR_AT_240Hz;
596 break;
597
598 case LSM6DSV16BX_GY_ODR_AT_480Hz:
599 *val = LSM6DSV16BX_GY_ODR_AT_480Hz;
600 break;
601
602 case LSM6DSV16BX_GY_ODR_AT_960Hz:
603 *val = LSM6DSV16BX_GY_ODR_AT_960Hz;
604 break;
605
606 case LSM6DSV16BX_GY_ODR_AT_1920Hz:
607 *val = LSM6DSV16BX_GY_ODR_AT_1920Hz;
608 break;
609
610 case LSM6DSV16BX_GY_ODR_AT_3840Hz:
611 *val = LSM6DSV16BX_GY_ODR_AT_3840Hz;
612 break;
613
614 case LSM6DSV16BX_GY_ODR_AT_7680Hz:
615 *val = LSM6DSV16BX_GY_ODR_AT_7680Hz;
616 break;
617
618 default:
619 *val = LSM6DSV16BX_GY_ODR_OFF;
620 break;
621 }
622 return ret;
623 }
624
625 /**
626 * @brief Gyroscope operating mode selection.[set]
627 *
628 * @param ctx read / write interface definitions
629 * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURANCY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD,
630 * @retval interface status (MANDATORY: return 0 -> no Error)
631 *
632 */
lsm6dsv16bx_gy_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_gy_mode_t val)633 int32_t lsm6dsv16bx_gy_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t val)
634 {
635 lsm6dsv16bx_ctrl2_t ctrl2;
636 int32_t ret;
637
638 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1);
639 if (ret == 0)
640 {
641 ctrl2.op_mode_g = (uint8_t)val & 0x07U;
642 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1);
643 }
644
645 return ret;
646 }
647
648 /**
649 * @brief Gyroscope operating mode selection.[get]
650 *
651 * @param ctx read / write interface definitions
652 * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURANCY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD,
653 * @retval interface status (MANDATORY: return 0 -> no Error)
654 *
655 */
lsm6dsv16bx_gy_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_gy_mode_t * val)656 int32_t lsm6dsv16bx_gy_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_gy_mode_t *val)
657 {
658 lsm6dsv16bx_ctrl2_t ctrl2;
659 int32_t ret;
660
661 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL2, (uint8_t *)&ctrl2, 1);
662 switch (ctrl2.op_mode_g)
663 {
664 case LSM6DSV16BX_GY_HIGH_PERFORMANCE_MD:
665 *val = LSM6DSV16BX_GY_HIGH_PERFORMANCE_MD;
666 break;
667
668 case LSM6DSV16BX_GY_SLEEP_MD:
669 *val = LSM6DSV16BX_GY_SLEEP_MD;
670 break;
671
672 case LSM6DSV16BX_GY_LOW_POWER_MD:
673 *val = LSM6DSV16BX_GY_LOW_POWER_MD;
674 break;
675
676 default:
677 *val = LSM6DSV16BX_GY_HIGH_PERFORMANCE_MD;
678 break;
679 }
680 return ret;
681 }
682
683 /**
684 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set]
685 *
686 * @param ctx read / write interface definitions
687 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
688 * @retval interface status (MANDATORY: return 0 -> no Error)
689 *
690 */
lsm6dsv16bx_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)691 int32_t lsm6dsv16bx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
692 {
693 lsm6dsv16bx_ctrl3_t ctrl3;
694 int32_t ret;
695
696 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1);
697 if (ret == 0)
698 {
699 ctrl3.if_inc = val;
700 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1);
701 }
702
703 return ret;
704 }
705
706 /**
707 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get]
708 *
709 * @param ctx read / write interface definitions
710 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
711 * @retval interface status (MANDATORY: return 0 -> no Error)
712 *
713 */
lsm6dsv16bx_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)714 int32_t lsm6dsv16bx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
715 {
716 lsm6dsv16bx_ctrl3_t ctrl3;
717 int32_t ret;
718
719 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1);
720 *val = ctrl3.if_inc;
721
722
723 return ret;
724 }
725
726 /**
727 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set]
728 *
729 * @param ctx read / write interface definitions
730 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
731 * @retval interface status (MANDATORY: return 0 -> no Error)
732 *
733 */
lsm6dsv16bx_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)734 int32_t lsm6dsv16bx_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
735 {
736 lsm6dsv16bx_ctrl3_t ctrl3;
737 int32_t ret;
738
739 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1);
740
741 if (ret == 0)
742 {
743 ctrl3.bdu = val;
744 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1);
745 }
746
747 return ret;
748 }
749
750 /**
751 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get]
752 *
753 * @param ctx read / write interface definitions
754 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
755 * @retval interface status (MANDATORY: return 0 -> no Error)
756 *
757 */
lsm6dsv16bx_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)758 int32_t lsm6dsv16bx_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
759 {
760 lsm6dsv16bx_ctrl3_t ctrl3;
761 int32_t ret;
762
763 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL3, (uint8_t *)&ctrl3, 1);
764 *val = ctrl3.bdu;
765
766 return ret;
767 }
768
769 /**
770 * @brief Enables pulsed data-ready mode (~75 us).[set]
771 *
772 * @param ctx read / write interface definitions
773 * @param val DRDY_LATCHED, DRDY_PULSED,
774 * @retval interface status (MANDATORY: return 0 -> no Error)
775 *
776 */
lsm6dsv16bx_data_ready_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_data_ready_mode_t val)777 int32_t lsm6dsv16bx_data_ready_mode_set(const stmdev_ctx_t *ctx,
778 lsm6dsv16bx_data_ready_mode_t val)
779 {
780 lsm6dsv16bx_ctrl4_t ctrl4;
781 int32_t ret;
782
783 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
784
785 if (ret == 0)
786 {
787 ctrl4.drdy_pulsed = (uint8_t)val & 0x1U;
788 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
789 }
790
791 return ret;
792 }
793
794 /**
795 * @brief Enables pulsed data-ready mode (~75 us).[get]
796 *
797 * @param ctx read / write interface definitions
798 * @param val DRDY_LATCHED, DRDY_PULSED,
799 * @retval interface status (MANDATORY: return 0 -> no Error)
800 *
801 */
lsm6dsv16bx_data_ready_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_data_ready_mode_t * val)802 int32_t lsm6dsv16bx_data_ready_mode_get(const stmdev_ctx_t *ctx,
803 lsm6dsv16bx_data_ready_mode_t *val)
804 {
805 lsm6dsv16bx_ctrl4_t ctrl4;
806 int32_t ret;
807
808 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
809
810 switch (ctrl4.drdy_pulsed)
811 {
812 case LSM6DSV16BX_DRDY_LATCHED:
813 *val = LSM6DSV16BX_DRDY_LATCHED;
814 break;
815
816 case LSM6DSV16BX_DRDY_PULSED:
817 *val = LSM6DSV16BX_DRDY_PULSED;
818 break;
819
820 default:
821 *val = LSM6DSV16BX_DRDY_LATCHED;
822 break;
823 }
824 return ret;
825 }
826
827 /**
828 * @brief Gyroscope full-scale selection[set]
829 *
830 * @param ctx read / write interface definitions
831 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
832 * @retval interface status (MANDATORY: return 0 -> no Error)
833 *
834 */
lsm6dsv16bx_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_gy_full_scale_t val)835 int32_t lsm6dsv16bx_gy_full_scale_set(const stmdev_ctx_t *ctx,
836 lsm6dsv16bx_gy_full_scale_t val)
837 {
838 lsm6dsv16bx_ctrl6_t ctrl6;
839 int32_t ret;
840
841 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1);
842
843 if (ret == 0)
844 {
845 ctrl6.fs_g = (uint8_t)val & 0xFU;
846 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1);
847 }
848
849 return ret;
850 }
851
852 /**
853 * @brief Gyroscope full-scale selection[get]
854 *
855 * @param ctx read / write interface definitions
856 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
857 * @retval interface status (MANDATORY: return 0 -> no Error)
858 *
859 */
lsm6dsv16bx_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_gy_full_scale_t * val)860 int32_t lsm6dsv16bx_gy_full_scale_get(const stmdev_ctx_t *ctx,
861 lsm6dsv16bx_gy_full_scale_t *val)
862 {
863 lsm6dsv16bx_ctrl6_t ctrl6;
864 int32_t ret;
865
866 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1);
867
868 switch (ctrl6.fs_g)
869 {
870 case LSM6DSV16BX_125dps:
871 *val = LSM6DSV16BX_125dps;
872 break;
873
874 case LSM6DSV16BX_250dps:
875 *val = LSM6DSV16BX_250dps;
876 break;
877
878 case LSM6DSV16BX_500dps:
879 *val = LSM6DSV16BX_500dps;
880 break;
881
882 case LSM6DSV16BX_1000dps:
883 *val = LSM6DSV16BX_1000dps;
884 break;
885
886 case LSM6DSV16BX_2000dps:
887 *val = LSM6DSV16BX_2000dps;
888 break;
889
890 case LSM6DSV16BX_4000dps:
891 *val = LSM6DSV16BX_4000dps;
892 break;
893
894 default:
895 *val = LSM6DSV16BX_125dps;
896 break;
897 }
898 return ret;
899 }
900
901 /**
902 * @brief Accelerometer full-scale selection.[set]
903 *
904 * @param ctx read / write interface definitions
905 * @param val 2g, 4g, 8g, 16g,
906 * @retval interface status (MANDATORY: return 0 -> no Error)
907 *
908 */
lsm6dsv16bx_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_xl_full_scale_t val)909 int32_t lsm6dsv16bx_xl_full_scale_set(const stmdev_ctx_t *ctx,
910 lsm6dsv16bx_xl_full_scale_t val)
911 {
912 lsm6dsv16bx_ctrl8_t ctrl8;
913 int32_t ret;
914
915 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
916
917 if (ret == 0)
918 {
919 ctrl8.fs_xl = (uint8_t)val & 0x3U;
920 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
921 }
922
923 return ret;
924 }
925
926 /**
927 * @brief Accelerometer full-scale selection.[get]
928 *
929 * @param ctx read / write interface definitions
930 * @param val 2g, 4g, 8g, 16g,
931 * @retval interface status (MANDATORY: return 0 -> no Error)
932 *
933 */
lsm6dsv16bx_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_xl_full_scale_t * val)934 int32_t lsm6dsv16bx_xl_full_scale_get(const stmdev_ctx_t *ctx,
935 lsm6dsv16bx_xl_full_scale_t *val)
936 {
937 lsm6dsv16bx_ctrl8_t ctrl8;
938 int32_t ret;
939
940 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
941
942 switch (ctrl8.fs_xl)
943 {
944 case LSM6DSV16BX_2g:
945 *val = LSM6DSV16BX_2g;
946 break;
947
948 case LSM6DSV16BX_4g:
949 *val = LSM6DSV16BX_4g;
950 break;
951
952 case LSM6DSV16BX_8g:
953 *val = LSM6DSV16BX_8g;
954 break;
955
956 case LSM6DSV16BX_16g:
957 *val = LSM6DSV16BX_16g;
958 break;
959
960 default:
961 *val = LSM6DSV16BX_2g;
962 break;
963 }
964 return ret;
965 }
966
967 /**
968 * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[set]
969 *
970 * @param ctx read / write interface definitions
971 * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.
972 * @retval interface status (MANDATORY: return 0 -> no Error)
973 *
974 */
lsm6dsv16bx_xl_dual_channel_set(const stmdev_ctx_t * ctx,uint8_t val)975 int32_t lsm6dsv16bx_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val)
976 {
977 lsm6dsv16bx_ctrl8_t ctrl8;
978 int32_t ret;
979
980 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
981
982 if (ret == 0)
983 {
984 ctrl8.xl_dualc_en = val;
985 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
986 }
987
988 return ret;
989 }
990
991 /**
992 * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[get]
993 *
994 * @param ctx read / write interface definitions
995 * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.
996 * @retval interface status (MANDATORY: return 0 -> no Error)
997 *
998 */
lsm6dsv16bx_xl_dual_channel_get(const stmdev_ctx_t * ctx,uint8_t * val)999 int32_t lsm6dsv16bx_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val)
1000 {
1001 lsm6dsv16bx_ctrl8_t ctrl8;
1002 int32_t ret;
1003
1004 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
1005 *val = ctrl8.xl_dualc_en;
1006
1007 return ret;
1008 }
1009
1010 /**
1011 * @brief Accelerometer self-test selection.[set]
1012 *
1013 * @param ctx read / write interface definitions
1014 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1015 * @retval interface status (MANDATORY: return 0 -> no Error)
1016 *
1017 */
lsm6dsv16bx_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_xl_self_test_t val)1018 int32_t lsm6dsv16bx_xl_self_test_set(const stmdev_ctx_t *ctx,
1019 lsm6dsv16bx_xl_self_test_t val)
1020 {
1021 lsm6dsv16bx_ctrl10_t ctrl10;
1022 int32_t ret;
1023
1024 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
1025
1026 if (ret == 0)
1027 {
1028 ctrl10.st_xl = (uint8_t)val & 0x3U;
1029 ctrl10.xl_st_offset = ((uint8_t)val & 0x04U) >> 2;
1030 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
1031 }
1032
1033 return ret;
1034 }
1035
1036 /**
1037 * @brief Accelerometer self-test selection.[get]
1038 *
1039 * @param ctx read / write interface definitions
1040 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1041 * @retval interface status (MANDATORY: return 0 -> no Error)
1042 *
1043 */
lsm6dsv16bx_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_xl_self_test_t * val)1044 int32_t lsm6dsv16bx_xl_self_test_get(const stmdev_ctx_t *ctx,
1045 lsm6dsv16bx_xl_self_test_t *val)
1046 {
1047 lsm6dsv16bx_ctrl10_t ctrl10;
1048 int32_t ret;
1049
1050 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
1051
1052 //switch (ctrl10.xl_st_offset)
1053 switch (ctrl10.st_xl)
1054 {
1055 case LSM6DSV16BX_XL_ST_DISABLE:
1056 *val = LSM6DSV16BX_XL_ST_DISABLE;
1057 break;
1058
1059 case LSM6DSV16BX_XL_ST_POSITIVE:
1060 *val = LSM6DSV16BX_XL_ST_POSITIVE;
1061 break;
1062
1063 case LSM6DSV16BX_XL_ST_NEGATIVE:
1064 *val = LSM6DSV16BX_XL_ST_NEGATIVE;
1065 break;
1066
1067 default:
1068 *val = LSM6DSV16BX_XL_ST_DISABLE;
1069 break;
1070 }
1071 return ret;
1072 }
1073
1074 /**
1075 * @brief Gyroscope self-test selection.[set]
1076 *
1077 * @param ctx read / write interface definitions
1078 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1079 * @retval interface status (MANDATORY: return 0 -> no Error)
1080 *
1081 */
lsm6dsv16bx_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_gy_self_test_t val)1082 int32_t lsm6dsv16bx_gy_self_test_set(const stmdev_ctx_t *ctx,
1083 lsm6dsv16bx_gy_self_test_t val)
1084 {
1085 lsm6dsv16bx_ctrl10_t ctrl10;
1086 int32_t ret;
1087
1088 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
1089
1090 if (ret == 0)
1091 {
1092 ctrl10.st_g = (uint8_t)val & 0x3U;
1093 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
1094 }
1095
1096 return ret;
1097 }
1098
1099 /**
1100 * @brief Gyroscope self-test selection.[get]
1101 *
1102 * @param ctx read / write interface definitions
1103 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1104 * @retval interface status (MANDATORY: return 0 -> no Error)
1105 *
1106 */
lsm6dsv16bx_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_gy_self_test_t * val)1107 int32_t lsm6dsv16bx_gy_self_test_get(const stmdev_ctx_t *ctx,
1108 lsm6dsv16bx_gy_self_test_t *val)
1109 {
1110 lsm6dsv16bx_ctrl10_t ctrl10;
1111 int32_t ret;
1112
1113 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
1114
1115 switch (ctrl10.st_g)
1116 {
1117 case LSM6DSV16BX_GY_ST_DISABLE:
1118 *val = LSM6DSV16BX_GY_ST_DISABLE;
1119 break;
1120
1121 case LSM6DSV16BX_GY_ST_POSITIVE:
1122 *val = LSM6DSV16BX_GY_ST_POSITIVE;
1123 break;
1124
1125 case LSM6DSV16BX_GY_ST_NEGATIVE:
1126 *val = LSM6DSV16BX_GY_ST_NEGATIVE;
1127 break;
1128
1129 default:
1130 *val = LSM6DSV16BX_GY_ST_DISABLE;
1131 break;
1132 }
1133 return ret;
1134 }
1135
1136 /**
1137 * @brief Get the status of all the interrupt sources.[get]
1138 *
1139 * @param ctx read / write interface definitions
1140 * @param val Get the status of all the interrupt sources.
1141 * @retval interface status (MANDATORY: return 0 -> no Error)
1142 *
1143 */
lsm6dsv16bx_all_sources_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_all_sources_t * val)1144 int32_t lsm6dsv16bx_all_sources_get(const stmdev_ctx_t *ctx,
1145 lsm6dsv16bx_all_sources_t *val)
1146 {
1147 lsm6dsv16bx_emb_func_status_mainpage_t emb_func_status_mainpage;
1148 lsm6dsv16bx_emb_func_exec_status_t emb_func_exec_status;
1149 lsm6dsv16bx_fsm_status_mainpage_t fsm_status_mainpage;
1150 lsm6dsv16bx_mlc_status_mainpage_t mlc_status_mainpage;
1151 lsm6dsv16bx_functions_enable_t functions_enable;
1152 lsm6dsv16bx_emb_func_src_t emb_func_src;
1153 lsm6dsv16bx_fifo_status2_t fifo_status2;
1154 lsm6dsv16bx_all_int_src_t all_int_src;
1155 lsm6dsv16bx_wake_up_src_t wake_up_src;
1156 lsm6dsv16bx_status_reg_t status_reg;
1157 lsm6dsv16bx_d6d_src_t d6d_src;
1158 lsm6dsv16bx_tap_src_t tap_src;
1159 uint8_t buff[7];
1160 int32_t ret;
1161
1162 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1163 if (ret == 0)
1164 {
1165 functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE;
1166 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1167 }
1168
1169 if (ret == 0)
1170 {
1171 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_STATUS1, (uint8_t *)&buff, 4);
1172 }
1173 bytecpy((uint8_t *)&fifo_status2, &buff[1]);
1174 bytecpy((uint8_t *)&all_int_src, &buff[2]);
1175 bytecpy((uint8_t *)&status_reg, &buff[3]);
1176
1177 val->fifo_ovr = fifo_status2.fifo_ovr_ia;
1178 val->fifo_bdr = fifo_status2.counter_bdr_ia;
1179 val->fifo_full = fifo_status2.fifo_full_ia;
1180 val->fifo_th = fifo_status2.fifo_wtm_ia;
1181
1182 val->free_fall = all_int_src.ff_ia;
1183 val->wake_up = all_int_src.wu_ia;
1184 val->six_d = all_int_src.d6d_ia;
1185
1186 val->drdy_xl = status_reg.xlda;
1187 val->drdy_gy = status_reg.gda;
1188 val->drdy_temp = status_reg.tda;
1189 val->drdy_ah_qvar = status_reg.ah_qvarda;
1190 val->timestamp = status_reg.timestamp_endcount;
1191
1192 if (ret == 0)
1193 {
1194 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1195 }
1196 if (ret == 0)
1197 {
1198 functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE;
1199 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1200 }
1201
1202 if (ret == 0)
1203 {
1204 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_SRC, (uint8_t *)&buff, 7);
1205 }
1206
1207 if (ret == 0)
1208 {
1209 bytecpy((uint8_t *)&wake_up_src, &buff[0]);
1210 bytecpy((uint8_t *)&tap_src, &buff[1]);
1211 bytecpy((uint8_t *)&d6d_src, &buff[2]);
1212 bytecpy((uint8_t *)&emb_func_status_mainpage, &buff[4]);
1213 bytecpy((uint8_t *)&fsm_status_mainpage, &buff[5]);
1214 bytecpy((uint8_t *)&mlc_status_mainpage, &buff[6]);
1215
1216 val->sleep_change = wake_up_src.sleep_change_ia;
1217 val->wake_up_x = wake_up_src.x_wu;
1218 val->wake_up_y = wake_up_src.y_wu;
1219 val->wake_up_z = wake_up_src.z_wu;
1220 val->sleep_state = wake_up_src.sleep_state;
1221
1222 val->tap_x = tap_src.x_tap;
1223 val->tap_y = tap_src.y_tap;
1224 val->tap_z = tap_src.z_tap;
1225 val->tap_sign = tap_src.tap_sign;
1226 val->double_tap = tap_src.double_tap;
1227 val->single_tap = tap_src.single_tap;
1228
1229 val->six_d_zl = d6d_src.zl;
1230 val->six_d_zh = d6d_src.zh;
1231 val->six_d_yl = d6d_src.yl;
1232 val->six_d_yh = d6d_src.yh;
1233 val->six_d_xl = d6d_src.xl;
1234 val->six_d_xh = d6d_src.xh;
1235
1236 val->step_detector = emb_func_status_mainpage.is_step_det;
1237 val->tilt = emb_func_status_mainpage.is_tilt;
1238 val->sig_mot = emb_func_status_mainpage.is_sigmot;
1239 val->fsm_lc = emb_func_status_mainpage.is_fsm_lc;
1240
1241 val->fsm1 = fsm_status_mainpage.is_fsm1;
1242 val->fsm2 = fsm_status_mainpage.is_fsm2;
1243 val->fsm3 = fsm_status_mainpage.is_fsm3;
1244 val->fsm4 = fsm_status_mainpage.is_fsm4;
1245 val->fsm5 = fsm_status_mainpage.is_fsm5;
1246 val->fsm6 = fsm_status_mainpage.is_fsm6;
1247 val->fsm7 = fsm_status_mainpage.is_fsm7;
1248 val->fsm8 = fsm_status_mainpage.is_fsm8;
1249
1250 val->mlc1 = mlc_status_mainpage.is_mlc1;
1251 val->mlc2 = mlc_status_mainpage.is_mlc2;
1252 val->mlc3 = mlc_status_mainpage.is_mlc3;
1253 val->mlc4 = mlc_status_mainpage.is_mlc4;
1254 }
1255
1256
1257 if (ret == 0)
1258 {
1259 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
1260 }
1261 if (ret == 0)
1262 {
1263 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status,
1264 1);
1265 }
1266 if (ret == 0)
1267 {
1268 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
1269 }
1270
1271 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
1272
1273 val->emb_func_stand_by = emb_func_exec_status.emb_func_endop;
1274 val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr;
1275 val->step_count_inc = emb_func_src.stepcounter_bit_set;
1276 val->step_count_overflow = emb_func_src.step_overflow;
1277 val->step_on_delta_time = emb_func_src.step_count_delta_ia;
1278
1279 val->step_detector = emb_func_src.step_detected;
1280
1281 return ret;
1282 }
1283
lsm6dsv16bx_flag_data_ready_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_data_ready_t * val)1284 int32_t lsm6dsv16bx_flag_data_ready_get(const stmdev_ctx_t *ctx,
1285 lsm6dsv16bx_data_ready_t *val)
1286 {
1287 lsm6dsv16bx_status_reg_t status;
1288 int32_t ret;
1289
1290 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_STATUS_REG, (uint8_t *)&status, 1);
1291 val->drdy_xl = status.xlda;
1292 val->drdy_gy = status.gda;
1293 val->drdy_temp = status.tda;
1294 val->drdy_ah_qvar = status.ah_qvarda;
1295
1296 return ret;
1297 }
1298
1299 /**
1300 * @brief Temperature data output register[get]
1301 *
1302 * @param ctx read / write interface definitions
1303 * @param val Temperature data output register
1304 * @retval interface status (MANDATORY: return 0 -> no Error)
1305 *
1306 */
lsm6dsv16bx_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1307 int32_t lsm6dsv16bx_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1308 {
1309 uint8_t buff[2];
1310 int32_t ret;
1311
1312 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_OUT_TEMP_L, &buff[0], 2);
1313 *val = (int16_t)buff[1];
1314 *val = (*val * 256) + (int16_t)buff[0];
1315
1316 return ret;
1317 }
1318
1319 /**
1320 * @brief Angular rate sensor.[get]
1321 *
1322 * @param ctx read / write interface definitions
1323 * @param val Angular rate sensor.
1324 * @retval interface status (MANDATORY: return 0 -> no Error)
1325 *
1326 */
lsm6dsv16bx_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1327 int32_t lsm6dsv16bx_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1328 {
1329 uint8_t buff[6];
1330 int32_t ret;
1331
1332 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_OUTX_L_G, &buff[0], 6);
1333 val[0] = (int16_t)buff[1];
1334 val[0] = (val[0] * 256) + (int16_t)buff[0];
1335 val[1] = (int16_t)buff[3];
1336 val[1] = (val[1] * 256) + (int16_t)buff[2];
1337 val[2] = (int16_t)buff[5];
1338 val[2] = (val[2] * 256) + (int16_t)buff[4];
1339
1340 return ret;
1341 }
1342
1343 /**
1344 * @brief Linear acceleration sensor.[get]
1345 *
1346 * @param ctx read / write interface definitions
1347 * @param val Linear acceleration sensor.
1348 * @retval interface status (MANDATORY: return 0 -> no Error)
1349 *
1350 */
lsm6dsv16bx_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1351 int32_t lsm6dsv16bx_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1352 {
1353 uint8_t buff[6];
1354 int32_t ret;
1355
1356 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_OUTZ_L_A, &buff[0], 6);
1357 val[2] = (int16_t)buff[1];
1358 val[2] = (val[2] * 256) + (int16_t)buff[0];
1359 val[1] = (int16_t)buff[3];
1360 val[1] = (val[1] * 256) + (int16_t)buff[2];
1361 val[0] = (int16_t)buff[5];
1362 val[0] = (val[0] * 256) + (int16_t)buff[4];
1363
1364 return ret;
1365 }
1366
1367 /**
1368 * @brief Linear acceleration sensor for Dual channel mode.[get]
1369 *
1370 * @param ctx read / write interface definitions
1371 * @param val Linear acceleration sensor or Dual channel mode.
1372 * @retval interface status (MANDATORY: return 0 -> no Error)
1373 *
1374 */
lsm6dsv16bx_dual_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1375 int32_t lsm6dsv16bx_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1376 {
1377 uint8_t buff[6];
1378 int32_t ret;
1379
1380 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_UI_OUTZ_L_A_DUALC, &buff[0], 6);
1381 val[2] = (int16_t)buff[1];
1382 val[2] = (val[2] * 256) + (int16_t)buff[0];
1383 val[1] = (int16_t)buff[3];
1384 val[1] = (val[1] * 256) + (int16_t)buff[2];
1385 val[0] = (int16_t)buff[5];
1386 val[0] = (val[0] * 256) + (int16_t)buff[4];
1387
1388 return ret;
1389 }
1390
1391 /**
1392 * @brief Qvar data output register.[get]
1393 *
1394 * @param ctx read / write interface definitions
1395 * @param val Qvar data output register.
1396 * @retval interface status (MANDATORY: return 0 -> no Error)
1397 *
1398 */
lsm6dsv16bx_ah_qvar_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1399 int32_t lsm6dsv16bx_ah_qvar_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1400 {
1401 uint8_t buff[2];
1402 int32_t ret;
1403
1404 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_AH_QVAR_OUT_L, &buff[0], 2);
1405 *val = (int16_t)buff[1];
1406 *val = (*val * 256) + (int16_t)buff[0];
1407
1408 return ret;
1409 }
1410
1411 /**
1412 * @brief Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.[get]
1413 *
1414 * @param ctx read / write interface definitions
1415 * @param val Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.
1416 * @retval interface status (MANDATORY: return 0 -> no Error)
1417 *
1418 */
lsm6dsv16bx_odr_cal_reg_get(const stmdev_ctx_t * ctx,int8_t * val)1419 int32_t lsm6dsv16bx_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val)
1420 {
1421 lsm6dsv16bx_internal_freq_t internal_freq;
1422 int32_t ret;
1423
1424 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1);
1425 *val = (int8_t)internal_freq.freq_fine;
1426
1427 return ret;
1428 }
1429
1430 /**
1431 * @brief Enable accelerometer axis.[set]
1432 *
1433 * @param ctx read / write interface definitions
1434 * @param val Enable accelerometer axis.
1435 * @retval interface status (MANDATORY: return 0 -> no Error)
1436 *
1437 */
lsm6dsv16bx_tdm_xl_axis_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_xl_axis_t val)1438 int32_t lsm6dsv16bx_tdm_xl_axis_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_xl_axis_t val)
1439 {
1440 lsm6dsv16bx_tdm_cfg1_t tdm_cfg1;
1441 int32_t ret;
1442
1443 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
1444 if (ret == 0)
1445 {
1446 tdm_cfg1.tdm_xl_z_en = val.z;
1447 tdm_cfg1.tdm_xl_y_en = val.y;
1448 tdm_cfg1.tdm_xl_x_en = val.x;
1449 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
1450 }
1451
1452 return ret;
1453 }
1454
1455 /**
1456 * @brief Enable accelerometer axis.[get]
1457 *
1458 * @param ctx read / write interface definitions
1459 * @param val Enable accelerometer axis.
1460 * @retval interface status (MANDATORY: return 0 -> no Error)
1461 *
1462 */
lsm6dsv16bx_tdm_xl_axis_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_xl_axis_t * val)1463 int32_t lsm6dsv16bx_tdm_xl_axis_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_xl_axis_t *val)
1464 {
1465 lsm6dsv16bx_tdm_cfg1_t tdm_cfg1;
1466 int32_t ret;
1467
1468 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
1469 val->x = tdm_cfg1.tdm_xl_x_en;
1470 val->y = tdm_cfg1.tdm_xl_y_en;
1471 val->z = tdm_cfg1.tdm_xl_z_en;
1472
1473 return ret;
1474 }
1475
1476 /**
1477 * @brief Write buffer in a page.[set]
1478 *
1479 * @param ctx read / write interface definitions
1480 * @param val Write buffer in a page.
1481 * @retval interface status (MANDATORY: return 0 -> no Error)
1482 *
1483 */
lsm6dsv16bx_ln_pg_write(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1484 int32_t lsm6dsv16bx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address,
1485 uint8_t *buf, uint8_t len)
1486 {
1487 lsm6dsv16bx_page_address_t page_address;
1488 lsm6dsv16bx_page_sel_t page_sel;
1489 lsm6dsv16bx_page_rw_t page_rw;
1490 uint8_t msb;
1491 uint8_t lsb;
1492 int32_t ret;
1493 uint8_t i ;
1494
1495 msb = ((uint8_t)(address >> 8) & 0x0FU);
1496 lsb = (uint8_t)address & 0xFFU;
1497
1498 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
1499
1500 /* set page write */
1501 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1502 page_rw.page_read = PROPERTY_DISABLE;
1503 page_rw.page_write = PROPERTY_ENABLE;
1504 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1505
1506 /* select page */
1507 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, 1);
1508 page_sel.page_sel = msb;
1509 page_sel.not_used0 = 1; // Default value
1510 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel,
1511 1);
1512
1513 /* set page addr */
1514 page_address.page_addr = lsb;
1515 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_ADDRESS,
1516 (uint8_t *)&page_address, 1);
1517
1518 for (i = 0; ((i < len) && (ret == 0)); i++)
1519 {
1520 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_VALUE, &buf[i], 1);
1521 lsb++;
1522
1523 /* Check if page wrap */
1524 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
1525 {
1526 msb++;
1527 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, 1);
1528
1529 if (ret == 0)
1530 {
1531 page_sel.page_sel = msb;
1532 page_sel.not_used0 = 1; // Default value
1533 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel,
1534 1);
1535 }
1536 }
1537 }
1538
1539 page_sel.page_sel = 0;
1540 page_sel.not_used0 = 1;// Default value
1541 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel,
1542 1);
1543
1544 /* unset page write */
1545 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1546 page_rw.page_read = PROPERTY_DISABLE;
1547 page_rw.page_write = PROPERTY_DISABLE;
1548 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1549
1550 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
1551
1552 return ret;
1553 }
1554
1555 /**
1556 * @brief Read buffer in a page.[set]
1557 *
1558 * @param ctx read / write interface definitions
1559 * @param val Write buffer in a page.
1560 * @retval interface status (MANDATORY: return 0 -> no Error)
1561 *
1562 */
lsm6dsv16bx_ln_pg_read(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1563 int32_t lsm6dsv16bx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address,
1564 uint8_t *buf, uint8_t len)
1565 {
1566 lsm6dsv16bx_page_address_t page_address;
1567 lsm6dsv16bx_page_sel_t page_sel;
1568 lsm6dsv16bx_page_rw_t page_rw;
1569 uint8_t msb;
1570 uint8_t lsb;
1571 int32_t ret;
1572 uint8_t i ;
1573
1574 msb = ((uint8_t)(address >> 8) & 0x0FU);
1575 lsb = (uint8_t)address & 0xFFU;
1576
1577 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
1578
1579 /* set page write */
1580 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1581 page_rw.page_read = PROPERTY_ENABLE;
1582 page_rw.page_write = PROPERTY_DISABLE;
1583 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1584
1585 /* select page */
1586 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, 1);
1587 page_sel.page_sel = msb;
1588 page_sel.not_used0 = 1; // Default value
1589 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel,
1590 1);
1591
1592 /* set page addr */
1593 page_address.page_addr = lsb;
1594 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_ADDRESS,
1595 (uint8_t *)&page_address, 1);
1596
1597 for (i = 0; ((i < len) && (ret == 0)); i++)
1598 {
1599 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_VALUE, &buf[i], 1);
1600 lsb++;
1601
1602 /* Check if page wrap */
1603 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
1604 {
1605 msb++;
1606 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel, 1);
1607
1608 if (ret == 0)
1609 {
1610 page_sel.page_sel = msb;
1611 page_sel.not_used0 = 1; // Default value
1612 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel,
1613 1);
1614 }
1615 }
1616 }
1617
1618 page_sel.page_sel = 0;
1619 page_sel.not_used0 = 1;// Default value
1620 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_SEL, (uint8_t *)&page_sel,
1621 1);
1622
1623 /* unset page write */
1624 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1625 page_rw.page_read = PROPERTY_DISABLE;
1626 page_rw.page_write = PROPERTY_DISABLE;
1627 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
1628
1629 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
1630
1631 return ret;
1632 }
1633
1634 /**
1635 * @}
1636 *
1637 */
1638
1639 /**
1640 * @defgroup Timestamp
1641 * @brief This section groups all the functions that manage the
1642 * timestamp generation.
1643 * @{
1644 *
1645 */
1646
1647 /**
1648 * @brief Enables timestamp counter.[set]
1649 *
1650 * @param ctx read / write interface definitions
1651 * @param val Enables timestamp counter.
1652 * @retval interface status (MANDATORY: return 0 -> no Error)
1653 *
1654 */
lsm6dsv16bx_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)1655 int32_t lsm6dsv16bx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
1656 {
1657 lsm6dsv16bx_functions_enable_t functions_enable;
1658 int32_t ret;
1659
1660 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1661 if (ret == 0)
1662 {
1663 functions_enable.timestamp_en = val;
1664 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1665 }
1666
1667 return ret;
1668 }
1669
1670 /**
1671 * @brief Enables timestamp counter.[get]
1672 *
1673 * @param ctx read / write interface definitions
1674 * @param val Enables timestamp counter.
1675 * @retval interface status (MANDATORY: return 0 -> no Error)
1676 *
1677 */
lsm6dsv16bx_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)1678 int32_t lsm6dsv16bx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
1679 {
1680 lsm6dsv16bx_functions_enable_t functions_enable;
1681 int32_t ret;
1682
1683 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1684 *val = functions_enable.timestamp_en;
1685
1686 return ret;
1687 }
1688
1689 /**
1690 * @brief Timestamp data output.[get]
1691 *
1692 * @param ctx read / write interface definitions
1693 * @param val Timestamp data output.
1694 * @retval interface status (MANDATORY: return 0 -> no Error)
1695 *
1696 */
lsm6dsv16bx_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)1697 int32_t lsm6dsv16bx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
1698 {
1699 uint8_t buff[4];
1700 int32_t ret;
1701
1702 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TIMESTAMP0, &buff[0], 4);
1703 *val = buff[3];
1704 *val = (*val * 256U) + buff[2];
1705 *val = (*val * 256U) + buff[1];
1706 *val = (*val * 256U) + buff[0];
1707
1708 return ret;
1709 }
1710
1711 /**
1712 * @}
1713 *
1714 */
1715
1716 /**
1717 * @defgroup Filters
1718 * @brief This section group all the functions concerning the
1719 * filters configuration
1720 * @{
1721 *
1722 */
1723
1724 /**
1725 * @brief Protocol anti-spike filters.[set]
1726 *
1727 * @param ctx read / write interface definitions
1728 * @param val AUTO, ALWAYS_ACTIVE,
1729 * @retval interface status (MANDATORY: return 0 -> no Error)
1730 *
1731 */
lsm6dsv16bx_filt_anti_spike_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_filt_anti_spike_t val)1732 int32_t lsm6dsv16bx_filt_anti_spike_set(const stmdev_ctx_t *ctx,
1733 lsm6dsv16bx_filt_anti_spike_t val)
1734 {
1735 lsm6dsv16bx_if_cfg_t if_cfg;
1736 int32_t ret;
1737
1738 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
1739
1740 if (ret == 0)
1741 {
1742 if_cfg.asf_ctrl = (uint8_t)val & 0x01U;
1743 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
1744 }
1745
1746 return ret;
1747 }
1748
1749 /**
1750 * @brief Protocol anti-spike filters.[get]
1751 *
1752 * @param ctx read / write interface definitions
1753 * @param val AUTO, ALWAYS_ACTIVE,
1754 * @retval interface status (MANDATORY: return 0 -> no Error)
1755 *
1756 */
lsm6dsv16bx_filt_anti_spike_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_filt_anti_spike_t * val)1757 int32_t lsm6dsv16bx_filt_anti_spike_get(const stmdev_ctx_t *ctx,
1758 lsm6dsv16bx_filt_anti_spike_t *val)
1759 {
1760 lsm6dsv16bx_if_cfg_t if_cfg;
1761 int32_t ret;
1762
1763 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
1764 switch (if_cfg.asf_ctrl)
1765 {
1766 case LSM6DSV16BX_AUTO:
1767 *val = LSM6DSV16BX_AUTO;
1768 break;
1769
1770 case LSM6DSV16BX_ALWAYS_ACTIVE:
1771 *val = LSM6DSV16BX_ALWAYS_ACTIVE;
1772 break;
1773
1774 default:
1775 *val = LSM6DSV16BX_AUTO;
1776 break;
1777 }
1778 return ret;
1779 }
1780
1781 /**
1782 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set]
1783 *
1784 * @param ctx read / write interface definitions
1785 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
1786 * @retval interface status (MANDATORY: return 0 -> no Error)
1787 *
1788 */
lsm6dsv16bx_filt_settling_mask_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_filt_settling_mask_t val)1789 int32_t lsm6dsv16bx_filt_settling_mask_set(const stmdev_ctx_t *ctx,
1790 lsm6dsv16bx_filt_settling_mask_t val)
1791 {
1792 lsm6dsv16bx_emb_func_cfg_t emb_func_cfg;
1793 lsm6dsv16bx_tdm_cfg2_t tdm_cfg2;
1794 lsm6dsv16bx_ctrl4_t ctrl4;
1795 int32_t ret;
1796
1797 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
1798
1799 if (ret == 0)
1800 {
1801 ctrl4.drdy_mask = val.drdy;
1802
1803 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
1804 }
1805
1806 if (ret == 0)
1807 {
1808 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
1809 }
1810
1811 if (ret == 0)
1812 {
1813 emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl;
1814 emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g;
1815 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
1816 }
1817
1818 if (ret == 0)
1819 {
1820 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
1821 }
1822
1823 if (ret == 0)
1824 {
1825 tdm_cfg2.tdm_data_mask = val.tdm_excep_code;
1826 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
1827 }
1828
1829 return ret;
1830 }
1831
1832 /**
1833 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get]
1834 *
1835 * @param ctx read / write interface definitions
1836 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
1837 * @retval interface status (MANDATORY: return 0 -> no Error)
1838 *
1839 */
lsm6dsv16bx_filt_settling_mask_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_filt_settling_mask_t * val)1840 int32_t lsm6dsv16bx_filt_settling_mask_get(const stmdev_ctx_t *ctx,
1841 lsm6dsv16bx_filt_settling_mask_t *val)
1842 {
1843 lsm6dsv16bx_emb_func_cfg_t emb_func_cfg;
1844 lsm6dsv16bx_tdm_cfg2_t tdm_cfg2;
1845 lsm6dsv16bx_ctrl4_t ctrl4;
1846 int32_t ret;
1847
1848 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
1849 if (ret == 0)
1850 {
1851 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
1852 }
1853 if (ret == 0)
1854 {
1855 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
1856 }
1857
1858 val->drdy = ctrl4.drdy_mask;
1859 val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl;
1860 val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl;
1861 val->tdm_excep_code = tdm_cfg2.tdm_data_mask;
1862
1863 return ret;
1864 }
1865
1866 /**
1867 * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[set]
1868 *
1869 * @param ctx read / write interface definitions
1870 * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME,
1871 * @retval interface status (MANDATORY: return 0 -> no Error)
1872 *
1873 */
lsm6dsv16bx_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_filt_gy_lp1_bandwidth_t val)1874 int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
1875 lsm6dsv16bx_filt_gy_lp1_bandwidth_t val)
1876 {
1877 lsm6dsv16bx_ctrl6_t ctrl6;
1878 int32_t ret;
1879
1880 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1);
1881 if (ret == 0)
1882 {
1883 ctrl6.lpf1_g_bw = (uint8_t)val & 0x7U;
1884 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1);
1885 }
1886
1887 return ret;
1888 }
1889
1890 /**
1891 * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[get]
1892 *
1893 * @param ctx read / write interface definitions
1894 * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME,
1895 * @retval interface status (MANDATORY: return 0 -> no Error)
1896 *
1897 */
lsm6dsv16bx_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_filt_gy_lp1_bandwidth_t * val)1898 int32_t lsm6dsv16bx_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
1899 lsm6dsv16bx_filt_gy_lp1_bandwidth_t *val)
1900 {
1901 lsm6dsv16bx_ctrl6_t ctrl6;
1902 int32_t ret;
1903
1904 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL6, (uint8_t *)&ctrl6, 1);
1905
1906 switch (ctrl6.lpf1_g_bw)
1907 {
1908 case LSM6DSV16BX_GY_ULTRA_LIGHT:
1909 *val = LSM6DSV16BX_GY_ULTRA_LIGHT;
1910 break;
1911
1912 case LSM6DSV16BX_GY_VERY_LIGHT:
1913 *val = LSM6DSV16BX_GY_VERY_LIGHT;
1914 break;
1915
1916 case LSM6DSV16BX_GY_LIGHT:
1917 *val = LSM6DSV16BX_GY_LIGHT;
1918 break;
1919
1920 case LSM6DSV16BX_GY_MEDIUM:
1921 *val = LSM6DSV16BX_GY_MEDIUM;
1922 break;
1923
1924 case LSM6DSV16BX_GY_STRONG:
1925 *val = LSM6DSV16BX_GY_STRONG;
1926 break;
1927
1928 case LSM6DSV16BX_GY_VERY_STRONG:
1929 *val = LSM6DSV16BX_GY_VERY_STRONG;
1930 break;
1931
1932 case LSM6DSV16BX_GY_AGGRESSIVE:
1933 *val = LSM6DSV16BX_GY_AGGRESSIVE;
1934 break;
1935
1936 case LSM6DSV16BX_GY_XTREME:
1937 *val = LSM6DSV16BX_GY_XTREME;
1938 break;
1939
1940 default:
1941 *val = LSM6DSV16BX_GY_ULTRA_LIGHT;
1942 break;
1943 }
1944 return ret;
1945 }
1946
1947 /**
1948 * @brief It enables gyroscope digital LPF1 filter.[set]
1949 *
1950 * @param ctx read / write interface definitions
1951 * @param val It enables gyroscope digital LPF1 filter.
1952 * @retval interface status (MANDATORY: return 0 -> no Error)
1953 *
1954 */
lsm6dsv16bx_filt_gy_lp1_set(const stmdev_ctx_t * ctx,uint8_t val)1955 int32_t lsm6dsv16bx_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val)
1956 {
1957 lsm6dsv16bx_ctrl7_t ctrl7;
1958 int32_t ret;
1959
1960 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
1961
1962 if (ret == 0)
1963 {
1964 ctrl7.lpf1_g_en = val;
1965 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
1966 }
1967
1968 return ret;
1969 }
1970
1971 /**
1972 * @brief It enables gyroscope digital LPF1 filter.[get]
1973 *
1974 * @param ctx read / write interface definitions
1975 * @param val It enables gyroscope digital LPF1 filter.
1976 * @retval interface status (MANDATORY: return 0 -> no Error)
1977 *
1978 */
lsm6dsv16bx_filt_gy_lp1_get(const stmdev_ctx_t * ctx,uint8_t * val)1979 int32_t lsm6dsv16bx_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val)
1980 {
1981 lsm6dsv16bx_ctrl7_t ctrl7;
1982 int32_t ret;
1983
1984 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
1985 *val = ctrl7.lpf1_g_en;
1986
1987 return ret;
1988 }
1989
1990 /**
1991 * @brief Qvar filter configuration.[set]
1992 *
1993 * @param ctx read / write interface definitions
1994 * @param val Qvar filter configuration.
1995 * @retval interface status (MANDATORY: return 0 -> no Error)
1996 *
1997 */
lsm6dsv16bx_filt_ah_qvar_conf_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_filt_ah_qvar_conf_t val)1998 int32_t lsm6dsv16bx_filt_ah_qvar_conf_set(const stmdev_ctx_t *ctx,
1999 lsm6dsv16bx_filt_ah_qvar_conf_t val)
2000 {
2001 lsm6dsv16bx_ctrl9_t ctrl9;
2002 lsm6dsv16bx_ctrl8_t ctrl8;
2003 int32_t ret;
2004
2005 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
2006 if (ret == 0)
2007 {
2008 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2009 }
2010
2011 ctrl8.ah_qvar_hpf = val.hpf;
2012 ctrl9.ah_qvar_lpf = val.lpf;
2013
2014 if (ret == 0)
2015 {
2016 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
2017 }
2018 if (ret == 0)
2019 {
2020 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2021 }
2022
2023 return ret;
2024 }
2025
2026 /**
2027 * @brief Qvar filter configuration.[get]
2028 *
2029 * @param ctx read / write interface definitions
2030 * @param val Qvar filter configuration.
2031 * @retval interface status (MANDATORY: return 0 -> no Error)
2032 *
2033 */
lsm6dsv16bx_filt_ah_qvar_conf_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_filt_ah_qvar_conf_t * val)2034 int32_t lsm6dsv16bx_filt_ah_qvar_conf_get(const stmdev_ctx_t *ctx,
2035 lsm6dsv16bx_filt_ah_qvar_conf_t *val)
2036 {
2037 lsm6dsv16bx_ctrl8_t ctrl8;
2038 lsm6dsv16bx_ctrl9_t ctrl9;
2039 int32_t ret;
2040
2041 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
2042 if (ret == 0)
2043 {
2044 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2045 }
2046
2047 val->lpf = ctrl9.ah_qvar_lpf;
2048 val->hpf = ctrl8.ah_qvar_hpf;
2049
2050 return ret;
2051 }
2052
2053 /**
2054 * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[set]
2055 *
2056 * @param ctx read / write interface definitions
2057 * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME,
2058 * @retval interface status (MANDATORY: return 0 -> no Error)
2059 *
2060 */
lsm6dsv16bx_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_filt_xl_lp2_bandwidth_t val)2061 int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx,
2062 lsm6dsv16bx_filt_xl_lp2_bandwidth_t val)
2063 {
2064 lsm6dsv16bx_ctrl8_t ctrl8;
2065 int32_t ret;
2066
2067 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
2068 if (ret == 0)
2069 {
2070 ctrl8.hp_lpf2_xl_bw = (uint8_t)val & 0x7U;
2071 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
2072 }
2073
2074 return ret;
2075 }
2076
2077 /**
2078 * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[get]
2079 *
2080 * @param ctx read / write interface definitions
2081 * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME,
2082 * @retval interface status (MANDATORY: return 0 -> no Error)
2083 *
2084 */
lsm6dsv16bx_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_filt_xl_lp2_bandwidth_t * val)2085 int32_t lsm6dsv16bx_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx,
2086 lsm6dsv16bx_filt_xl_lp2_bandwidth_t *val)
2087 {
2088 lsm6dsv16bx_ctrl8_t ctrl8;
2089 int32_t ret;
2090
2091 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL8, (uint8_t *)&ctrl8, 1);
2092 switch (ctrl8.hp_lpf2_xl_bw)
2093 {
2094 case LSM6DSV16BX_XL_ULTRA_LIGHT:
2095 *val = LSM6DSV16BX_XL_ULTRA_LIGHT;
2096 break;
2097
2098 case LSM6DSV16BX_XL_VERY_LIGHT:
2099 *val = LSM6DSV16BX_XL_VERY_LIGHT;
2100 break;
2101
2102 case LSM6DSV16BX_XL_LIGHT:
2103 *val = LSM6DSV16BX_XL_LIGHT;
2104 break;
2105
2106 case LSM6DSV16BX_XL_MEDIUM:
2107 *val = LSM6DSV16BX_XL_MEDIUM;
2108 break;
2109
2110 case LSM6DSV16BX_XL_STRONG:
2111 *val = LSM6DSV16BX_XL_STRONG;
2112 break;
2113
2114 case LSM6DSV16BX_XL_VERY_STRONG:
2115 *val = LSM6DSV16BX_XL_VERY_STRONG;
2116 break;
2117
2118 case LSM6DSV16BX_XL_AGGRESSIVE:
2119 *val = LSM6DSV16BX_XL_AGGRESSIVE;
2120 break;
2121
2122 case LSM6DSV16BX_XL_XTREME:
2123 *val = LSM6DSV16BX_XL_XTREME;
2124 break;
2125
2126 default:
2127 *val = LSM6DSV16BX_XL_ULTRA_LIGHT;
2128 break;
2129 }
2130 return ret;
2131 }
2132
2133 /**
2134 * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[set]
2135 *
2136 * @param ctx read / write interface definitions
2137 * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.
2138 * @retval interface status (MANDATORY: return 0 -> no Error)
2139 *
2140 */
lsm6dsv16bx_filt_xl_lp2_set(const stmdev_ctx_t * ctx,uint8_t val)2141 int32_t lsm6dsv16bx_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val)
2142 {
2143 lsm6dsv16bx_ctrl9_t ctrl9;
2144 int32_t ret;
2145
2146 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2147 if (ret == 0)
2148 {
2149 ctrl9.lpf2_xl_en = val;
2150 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2151 }
2152
2153 return ret;
2154 }
2155
2156 /**
2157 * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[get]
2158 *
2159 * @param ctx read / write interface definitions
2160 * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.
2161 * @retval interface status (MANDATORY: return 0 -> no Error)
2162 *
2163 */
lsm6dsv16bx_filt_xl_lp2_get(const stmdev_ctx_t * ctx,uint8_t * val)2164 int32_t lsm6dsv16bx_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val)
2165 {
2166 lsm6dsv16bx_ctrl9_t ctrl9;
2167 int32_t ret;
2168
2169 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2170 *val = ctrl9.lpf2_xl_en;
2171
2172 return ret;
2173 }
2174
2175 /**
2176 * @brief Accelerometer slope filter / high-pass filter selection.[set]
2177 *
2178 * @param ctx read / write interface definitions
2179 * @param val Accelerometer slope filter / high-pass filter selection.
2180 * @retval interface status (MANDATORY: return 0 -> no Error)
2181 *
2182 */
lsm6dsv16bx_filt_xl_hp_set(const stmdev_ctx_t * ctx,uint8_t val)2183 int32_t lsm6dsv16bx_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val)
2184 {
2185 lsm6dsv16bx_ctrl9_t ctrl9;
2186 int32_t ret;
2187
2188 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2189 if (ret == 0)
2190 {
2191 ctrl9.hp_slope_xl_en = val;
2192 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2193 }
2194
2195 return ret;
2196 }
2197
2198 /**
2199 * @brief Accelerometer slope filter / high-pass filter selection.[get]
2200 *
2201 * @param ctx read / write interface definitions
2202 * @param val Accelerometer slope filter / high-pass filter selection.
2203 * @retval interface status (MANDATORY: return 0 -> no Error)
2204 *
2205 */
lsm6dsv16bx_filt_xl_hp_get(const stmdev_ctx_t * ctx,uint8_t * val)2206 int32_t lsm6dsv16bx_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val)
2207 {
2208 lsm6dsv16bx_ctrl9_t ctrl9;
2209 int32_t ret;
2210
2211 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2212 *val = ctrl9.hp_slope_xl_en;
2213
2214 return ret;
2215 }
2216
2217 /**
2218 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[set]
2219 *
2220 * @param ctx read / write interface definitions
2221 * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.
2222 * @retval interface status (MANDATORY: return 0 -> no Error)
2223 *
2224 */
lsm6dsv16bx_filt_xl_fast_settling_set(const stmdev_ctx_t * ctx,uint8_t val)2225 int32_t lsm6dsv16bx_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val)
2226 {
2227 lsm6dsv16bx_ctrl9_t ctrl9;
2228 int32_t ret;
2229
2230 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2231 if (ret == 0)
2232 {
2233 ctrl9.xl_fastsettl_mode = val;
2234 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2235 }
2236
2237 return ret;
2238 }
2239
2240 /**
2241 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[get]
2242 *
2243 * @param ctx read / write interface definitions
2244 * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.
2245 * @retval interface status (MANDATORY: return 0 -> no Error)
2246 *
2247 */
lsm6dsv16bx_filt_xl_fast_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)2248 int32_t lsm6dsv16bx_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val)
2249 {
2250 lsm6dsv16bx_ctrl9_t ctrl9;
2251 int32_t ret;
2252
2253 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2254 *val = ctrl9.xl_fastsettl_mode;
2255
2256 return ret;
2257 }
2258
2259 /**
2260 * @brief Accelerometer high-pass filter mode.[set]
2261 *
2262 * @param ctx read / write interface definitions
2263 * @param val HP_MD_NORMAL, HP_MD_REFERENCE,
2264 * @retval interface status (MANDATORY: return 0 -> no Error)
2265 *
2266 */
lsm6dsv16bx_filt_xl_hp_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_filt_xl_hp_mode_t val)2267 int32_t lsm6dsv16bx_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx,
2268 lsm6dsv16bx_filt_xl_hp_mode_t val)
2269 {
2270 lsm6dsv16bx_ctrl9_t ctrl9;
2271 int32_t ret;
2272
2273 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2274 if (ret == 0)
2275 {
2276 ctrl9.hp_ref_mode_xl = (uint8_t)val & 0x01U;
2277 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2278 }
2279
2280 return ret;
2281 }
2282
2283 /**
2284 * @brief Accelerometer high-pass filter mode.[get]
2285 *
2286 * @param ctx read / write interface definitions
2287 * @param val HP_MD_NORMAL, HP_MD_REFERENCE,
2288 * @retval interface status (MANDATORY: return 0 -> no Error)
2289 *
2290 */
lsm6dsv16bx_filt_xl_hp_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_filt_xl_hp_mode_t * val)2291 int32_t lsm6dsv16bx_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx,
2292 lsm6dsv16bx_filt_xl_hp_mode_t *val)
2293 {
2294 lsm6dsv16bx_ctrl9_t ctrl9;
2295 int32_t ret;
2296
2297 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
2298 switch (ctrl9.hp_ref_mode_xl)
2299 {
2300 case LSM6DSV16BX_HP_MD_NORMAL:
2301 *val = LSM6DSV16BX_HP_MD_NORMAL;
2302 break;
2303
2304 case LSM6DSV16BX_HP_MD_REFERENCE:
2305 *val = LSM6DSV16BX_HP_MD_REFERENCE;
2306 break;
2307
2308 default:
2309 *val = LSM6DSV16BX_HP_MD_NORMAL;
2310 break;
2311 }
2312 return ret;
2313 }
2314
2315 /**
2316 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[set]
2317 *
2318 * @param ctx read / write interface definitions
2319 * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS,
2320 * @retval interface status (MANDATORY: return 0 -> no Error)
2321 *
2322 */
lsm6dsv16bx_filt_wkup_act_feed_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_filt_wkup_act_feed_t val)2323 int32_t lsm6dsv16bx_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx,
2324 lsm6dsv16bx_filt_wkup_act_feed_t val)
2325 {
2326 lsm6dsv16bx_wake_up_ths_t wake_up_ths;
2327 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
2328 int32_t ret;
2329
2330 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2331 if (ret == 0)
2332 {
2333 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
2334 }
2335
2336 tap_cfg0.slope_fds = (uint8_t)val & 0x01U;
2337 wake_up_ths.usr_off_on_wu = ((uint8_t)val & 0x02U) >> 1;
2338
2339 if (ret == 0)
2340 {
2341
2342 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2343 }
2344 if (ret == 0)
2345 {
2346
2347 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
2348 }
2349
2350 return ret;
2351 }
2352
2353 /**
2354 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[get]
2355 *
2356 * @param ctx read / write interface definitions
2357 * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS,
2358 * @retval interface status (MANDATORY: return 0 -> no Error)
2359 *
2360 */
lsm6dsv16bx_filt_wkup_act_feed_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_filt_wkup_act_feed_t * val)2361 int32_t lsm6dsv16bx_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx,
2362 lsm6dsv16bx_filt_wkup_act_feed_t *val)
2363 {
2364 lsm6dsv16bx_wake_up_ths_t wake_up_ths;
2365 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
2366 int32_t ret;
2367
2368 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
2369 if (ret == 0)
2370 {
2371 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2372 }
2373
2374 switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds)
2375 {
2376 case LSM6DSV16BX_WK_FEED_SLOPE:
2377 *val = LSM6DSV16BX_WK_FEED_SLOPE;
2378 break;
2379
2380 case LSM6DSV16BX_WK_FEED_HIGH_PASS:
2381 *val = LSM6DSV16BX_WK_FEED_HIGH_PASS;
2382 break;
2383
2384 case LSM6DSV16BX_WK_FEED_LP_WITH_OFFSET:
2385 *val = LSM6DSV16BX_WK_FEED_LP_WITH_OFFSET;
2386 break;
2387
2388 default:
2389 *val = LSM6DSV16BX_WK_FEED_SLOPE;
2390 break;
2391 }
2392 return ret;
2393 }
2394
2395 /**
2396 * @brief Mask hw function triggers when xl is settling.[set]
2397 *
2398 * @param ctx read / write interface definitions
2399 * @param val 0 or 1,
2400 * @retval interface status (MANDATORY: return 0 -> no Error)
2401 *
2402 */
lsm6dsv16bx_mask_trigger_xl_settl_set(const stmdev_ctx_t * ctx,uint8_t val)2403 int32_t lsm6dsv16bx_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val)
2404 {
2405 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
2406 int32_t ret;
2407
2408 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2409
2410 if (ret == 0)
2411 {
2412 tap_cfg0.hw_func_mask_xl_settl = val & 0x01U;
2413 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2414 }
2415
2416 return ret;
2417 }
2418
2419 /**
2420 * @brief Mask hw function triggers when xl is settling.[get]
2421 *
2422 * @param ctx read / write interface definitions
2423 * @param val 0 or 1,
2424 * @retval interface status (MANDATORY: return 0 -> no Error)
2425 *
2426 */
lsm6dsv16bx_mask_trigger_xl_settl_get(const stmdev_ctx_t * ctx,uint8_t * val)2427 int32_t lsm6dsv16bx_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val)
2428 {
2429 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
2430 int32_t ret;
2431
2432 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2433 *val = tap_cfg0.hw_func_mask_xl_settl;
2434
2435 return ret;
2436 }
2437
2438
2439 /**
2440 * @brief LPF2 filter on 6D (sixd) function selection.[set]
2441 *
2442 * @param ctx read / write interface definitions
2443 * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS,
2444 * @retval interface status (MANDATORY: return 0 -> no Error)
2445 *
2446 */
lsm6dsv16bx_filt_sixd_feed_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_filt_sixd_feed_t val)2447 int32_t lsm6dsv16bx_filt_sixd_feed_set(const stmdev_ctx_t *ctx,
2448 lsm6dsv16bx_filt_sixd_feed_t val)
2449 {
2450 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
2451 int32_t ret;
2452
2453 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2454 if (ret == 0)
2455 {
2456 tap_cfg0.low_pass_on_6d = (uint8_t)val & 0x01U;
2457 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2458 }
2459
2460 return ret;
2461 }
2462
2463 /**
2464 * @brief LPF2 filter on 6D (sixd) function selection.[get]
2465 *
2466 * @param ctx read / write interface definitions
2467 * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS,
2468 * @retval interface status (MANDATORY: return 0 -> no Error)
2469 *
2470 */
lsm6dsv16bx_filt_sixd_feed_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_filt_sixd_feed_t * val)2471 int32_t lsm6dsv16bx_filt_sixd_feed_get(const stmdev_ctx_t *ctx,
2472 lsm6dsv16bx_filt_sixd_feed_t *val)
2473 {
2474 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
2475 int32_t ret;
2476
2477 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2478 switch (tap_cfg0.low_pass_on_6d)
2479 {
2480 case LSM6DSV16BX_SIXD_FEED_ODR_DIV_2:
2481 *val = LSM6DSV16BX_SIXD_FEED_ODR_DIV_2;
2482 break;
2483
2484 case LSM6DSV16BX_SIXD_FEED_LOW_PASS:
2485 *val = LSM6DSV16BX_SIXD_FEED_LOW_PASS;
2486 break;
2487
2488 default:
2489 *val = LSM6DSV16BX_SIXD_FEED_ODR_DIV_2;
2490 break;
2491 }
2492 return ret;
2493 }
2494
2495 /**
2496 * @}
2497 *
2498 */
2499
2500 /**
2501 * @defgroup Serial interfaces
2502 * @brief This section groups all the functions concerning
2503 * serial interfaces management (not auxiliary)
2504 * @{
2505 *
2506 */
2507
2508 /**
2509 * @brief Enables pull-up on SDO pin of UI (User Interface).[set]
2510 *
2511 * @param ctx read / write interface definitions
2512 * @param val Enables pull-up on SDO pin of UI (User Interface).
2513 * @retval interface status (MANDATORY: return 0 -> no Error)
2514 *
2515 */
lsm6dsv16bx_ui_sdo_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)2516 int32_t lsm6dsv16bx_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
2517 {
2518 lsm6dsv16bx_pin_ctrl_t pin_ctrl;
2519 int32_t ret;
2520
2521 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2522 if (ret == 0)
2523 {
2524 pin_ctrl.sdo_pu_en = val;
2525 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2526 }
2527
2528 return ret;
2529 }
2530
2531 /**
2532 * @brief Enables pull-up on SDO pin of UI (User Interface).[get]
2533 *
2534 * @param ctx read / write interface definitions
2535 * @param val Enables pull-up on SDO pin of UI (User Interface).
2536 * @retval interface status (MANDATORY: return 0 -> no Error)
2537 *
2538 */
lsm6dsv16bx_ui_sdo_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)2539 int32_t lsm6dsv16bx_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
2540 {
2541 lsm6dsv16bx_pin_ctrl_t pin_ctrl;
2542 int32_t ret;
2543
2544 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2545 *val = pin_ctrl.sdo_pu_en;
2546
2547 return ret;
2548 }
2549
2550 /**
2551 * @brief Disables I2C and I3C on UI (User Interface).[set]
2552 *
2553 * @param ctx read / write interface definitions
2554 * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE,
2555 * @retval interface status (MANDATORY: return 0 -> no Error)
2556 *
2557 */
lsm6dsv16bx_ui_i2c_i3c_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_ui_i2c_i3c_mode_t val)2558 int32_t lsm6dsv16bx_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx,
2559 lsm6dsv16bx_ui_i2c_i3c_mode_t val)
2560 {
2561 lsm6dsv16bx_if_cfg_t if_cfg;
2562 int32_t ret;
2563
2564 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2565 if (ret == 0)
2566 {
2567 if_cfg.i2c_i3c_disable = (uint8_t)val & 0x01U;
2568 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2569 }
2570
2571 return ret;
2572 }
2573
2574 /**
2575 * @brief Disables I2C and I3C on UI (User Interface).[get]
2576 *
2577 * @param ctx read / write interface definitions
2578 * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE,
2579 * @retval interface status (MANDATORY: return 0 -> no Error)
2580 *
2581 */
lsm6dsv16bx_ui_i2c_i3c_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_ui_i2c_i3c_mode_t * val)2582 int32_t lsm6dsv16bx_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx,
2583 lsm6dsv16bx_ui_i2c_i3c_mode_t *val)
2584 {
2585 lsm6dsv16bx_if_cfg_t if_cfg;
2586 int32_t ret;
2587
2588 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2589 switch (if_cfg.i2c_i3c_disable)
2590 {
2591 case LSM6DSV16BX_I2C_I3C_ENABLE:
2592 *val = LSM6DSV16BX_I2C_I3C_ENABLE;
2593 break;
2594
2595 case LSM6DSV16BX_I2C_I3C_DISABLE:
2596 *val = LSM6DSV16BX_I2C_I3C_DISABLE;
2597 break;
2598
2599 default:
2600 *val = LSM6DSV16BX_I2C_I3C_ENABLE;
2601 break;
2602 }
2603 return ret;
2604 }
2605
2606 /**
2607 * @brief SPI Serial Interface Mode selection.[set]
2608 *
2609 * @param ctx read / write interface definitions
2610 * @param val SPI_4_WIRE, SPI_3_WIRE,
2611 * @retval interface status (MANDATORY: return 0 -> no Error)
2612 *
2613 */
lsm6dsv16bx_spi_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_spi_mode_t val)2614 int32_t lsm6dsv16bx_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_spi_mode_t val)
2615 {
2616 lsm6dsv16bx_if_cfg_t if_cfg;
2617 int32_t ret;
2618
2619 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2620 if (ret == 0)
2621 {
2622 if_cfg.sim = (uint8_t)val & 0x01U;
2623 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2624 }
2625
2626 return ret;
2627 }
2628
2629 /**
2630 * @brief SPI Serial Interface Mode selection.[get]
2631 *
2632 * @param ctx read / write interface definitions
2633 * @param val SPI_4_WIRE, SPI_3_WIRE,
2634 * @retval interface status (MANDATORY: return 0 -> no Error)
2635 *
2636 */
lsm6dsv16bx_spi_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_spi_mode_t * val)2637 int32_t lsm6dsv16bx_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_spi_mode_t *val)
2638 {
2639 lsm6dsv16bx_if_cfg_t if_cfg;
2640 int32_t ret;
2641
2642 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2643 switch (if_cfg.sim)
2644 {
2645 case LSM6DSV16BX_SPI_4_WIRE:
2646 *val = LSM6DSV16BX_SPI_4_WIRE;
2647 break;
2648
2649 case LSM6DSV16BX_SPI_3_WIRE:
2650 *val = LSM6DSV16BX_SPI_3_WIRE;
2651 break;
2652
2653 default:
2654 *val = LSM6DSV16BX_SPI_4_WIRE;
2655 break;
2656 }
2657 return ret;
2658 }
2659
2660 /**
2661 * @brief Enables pull-up on SDA pin.[set]
2662 *
2663 * @param ctx read / write interface definitions
2664 * @param val Enables pull-up on SDA pin.
2665 * @retval interface status (MANDATORY: return 0 -> no Error)
2666 *
2667 */
lsm6dsv16bx_ui_sda_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)2668 int32_t lsm6dsv16bx_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
2669 {
2670 lsm6dsv16bx_if_cfg_t if_cfg;
2671 int32_t ret;
2672
2673 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2674 if (ret == 0)
2675 {
2676 if_cfg.sda_pu_en = (uint8_t)val & 0x01U;
2677 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2678 }
2679
2680 return ret;
2681 }
2682
2683 /**
2684 * @brief Enables pull-up on SDA pin.[get]
2685 *
2686 * @param ctx read / write interface definitions
2687 * @param val Enables pull-up on SDA pin.
2688 * @retval interface status (MANDATORY: return 0 -> no Error)
2689 *
2690 */
lsm6dsv16bx_ui_sda_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)2691 int32_t lsm6dsv16bx_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
2692 {
2693 lsm6dsv16bx_if_cfg_t if_cfg;
2694 int32_t ret;
2695
2696 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2697 *val = if_cfg.sda_pu_en;
2698
2699 return ret;
2700 }
2701
2702 /**
2703 * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[set]
2704 *
2705 * @param ctx read / write interface definitions
2706 * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms,
2707 * @retval interface status (MANDATORY: return 0 -> no Error)
2708 *
2709 */
lsm6dsv16bx_i3c_ibi_time_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_i3c_ibi_time_t val)2710 int32_t lsm6dsv16bx_i3c_ibi_time_set(const stmdev_ctx_t *ctx,
2711 lsm6dsv16bx_i3c_ibi_time_t val)
2712 {
2713 lsm6dsv16bx_ctrl5_t ctrl5;
2714 int32_t ret;
2715
2716 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1);
2717 if (ret == 0)
2718 {
2719 ctrl5.bus_act_sel = (uint8_t)val & 0x03U;
2720 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1);
2721 }
2722
2723 return ret;
2724 }
2725
2726 /**
2727 * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[get]
2728 *
2729 * @param ctx read / write interface definitions
2730 * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms,
2731 * @retval interface status (MANDATORY: return 0 -> no Error)
2732 *
2733 */
lsm6dsv16bx_i3c_ibi_time_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_i3c_ibi_time_t * val)2734 int32_t lsm6dsv16bx_i3c_ibi_time_get(const stmdev_ctx_t *ctx,
2735 lsm6dsv16bx_i3c_ibi_time_t *val)
2736 {
2737 lsm6dsv16bx_ctrl5_t ctrl5;
2738 int32_t ret;
2739
2740 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1);
2741 switch (ctrl5.bus_act_sel)
2742 {
2743 case LSM6DSV16BX_IBI_2us:
2744 *val = LSM6DSV16BX_IBI_2us;
2745 break;
2746
2747 case LSM6DSV16BX_IBI_50us:
2748 *val = LSM6DSV16BX_IBI_50us;
2749 break;
2750
2751 case LSM6DSV16BX_IBI_1ms:
2752 *val = LSM6DSV16BX_IBI_1ms;
2753 break;
2754
2755 case LSM6DSV16BX_IBI_25ms:
2756 *val = LSM6DSV16BX_IBI_25ms;
2757 break;
2758
2759 default:
2760 *val = LSM6DSV16BX_IBI_2us;
2761 break;
2762 }
2763 return ret;
2764 }
2765
2766 /**
2767 * @}
2768 *
2769 */
2770
2771 /**
2772 * @defgroup Interrupt pins
2773 * @brief This section groups all the functions that manage interrupt pins
2774 * @{
2775 *
2776 */
2777
2778 /**
2779 * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[set]
2780 *
2781 * @param ctx read / write interface definitions
2782 * @param val PUSH_PULL, OPEN_DRAIN,
2783 * @retval interface status (MANDATORY: return 0 -> no Error)
2784 *
2785 */
lsm6dsv16bx_int_pin_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_int_pin_mode_t val)2786 int32_t lsm6dsv16bx_int_pin_mode_set(const stmdev_ctx_t *ctx,
2787 lsm6dsv16bx_int_pin_mode_t val)
2788 {
2789 lsm6dsv16bx_if_cfg_t if_cfg;
2790 int32_t ret;
2791
2792 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2793 if (ret == 0)
2794 {
2795 if_cfg.pp_od = (uint8_t)val & 0x01U;
2796 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2797 }
2798
2799 return ret;
2800 }
2801
2802 /**
2803 * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[get]
2804 *
2805 * @param ctx read / write interface definitions
2806 * @param val PUSH_PULL, OPEN_DRAIN,
2807 * @retval interface status (MANDATORY: return 0 -> no Error)
2808 *
2809 */
lsm6dsv16bx_int_pin_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_int_pin_mode_t * val)2810 int32_t lsm6dsv16bx_int_pin_mode_get(const stmdev_ctx_t *ctx,
2811 lsm6dsv16bx_int_pin_mode_t *val)
2812 {
2813 lsm6dsv16bx_if_cfg_t if_cfg;
2814 int32_t ret;
2815
2816 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2817 switch (if_cfg.pp_od)
2818 {
2819 case LSM6DSV16BX_PUSH_PULL:
2820 *val = LSM6DSV16BX_PUSH_PULL;
2821 break;
2822
2823 case LSM6DSV16BX_OPEN_DRAIN:
2824 *val = LSM6DSV16BX_OPEN_DRAIN;
2825 break;
2826
2827 default:
2828 *val = LSM6DSV16BX_PUSH_PULL;
2829 break;
2830 }
2831 return ret;
2832 }
2833
2834 /**
2835 * @brief Interrupt activation level.[set]
2836 *
2837 * @param ctx read / write interface definitions
2838 * @param val ACTIVE_HIGH, ACTIVE_LOW,
2839 * @retval interface status (MANDATORY: return 0 -> no Error)
2840 *
2841 */
lsm6dsv16bx_pin_polarity_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_pin_polarity_t val)2842 int32_t lsm6dsv16bx_pin_polarity_set(const stmdev_ctx_t *ctx,
2843 lsm6dsv16bx_pin_polarity_t val)
2844 {
2845 lsm6dsv16bx_if_cfg_t if_cfg;
2846 int32_t ret;
2847
2848 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2849 if (ret == 0)
2850 {
2851 if_cfg.h_lactive = (uint8_t)val & 0x01U;
2852 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2853 }
2854
2855 return ret;
2856 }
2857
2858 /**
2859 * @brief Interrupt activation level.[get]
2860 *
2861 * @param ctx read / write interface definitions
2862 * @param val ACTIVE_HIGH, ACTIVE_LOW,
2863 * @retval interface status (MANDATORY: return 0 -> no Error)
2864 *
2865 */
lsm6dsv16bx_pin_polarity_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_pin_polarity_t * val)2866 int32_t lsm6dsv16bx_pin_polarity_get(const stmdev_ctx_t *ctx,
2867 lsm6dsv16bx_pin_polarity_t *val)
2868 {
2869 lsm6dsv16bx_if_cfg_t if_cfg;
2870 int32_t ret;
2871
2872 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
2873 switch (if_cfg.h_lactive)
2874 {
2875 case LSM6DSV16BX_ACTIVE_HIGH:
2876 *val = LSM6DSV16BX_ACTIVE_HIGH;
2877 break;
2878
2879 case LSM6DSV16BX_ACTIVE_LOW:
2880 *val = LSM6DSV16BX_ACTIVE_LOW;
2881 break;
2882
2883 default:
2884 *val = LSM6DSV16BX_ACTIVE_HIGH;
2885 break;
2886 }
2887 return ret;
2888 }
2889
2890 /**
2891 * @brief It routes interrupt signals on INT 1 pin.[set]
2892 *
2893 * @param ctx read / write interface definitions
2894 * @param val It routes interrupt signals on INT 1 pin.
2895 * @retval interface status (MANDATORY: return 0 -> no Error)
2896 *
2897 */
lsm6dsv16bx_pin_int1_route_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_pin_int_route_t val)2898 int32_t lsm6dsv16bx_pin_int1_route_set(const stmdev_ctx_t *ctx,
2899 lsm6dsv16bx_pin_int_route_t val)
2900 {
2901 lsm6dsv16bx_functions_enable_t functions_enable;
2902 lsm6dsv16bx_pin_int_route_t pin_int2_route;
2903 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
2904 lsm6dsv16bx_emb_func_int1_t emb_func_int1;
2905 lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg;
2906 lsm6dsv16bx_int2_ctrl_t int2_ctrl;
2907 lsm6dsv16bx_int1_ctrl_t int1_ctrl;
2908 lsm6dsv16bx_fsm_int1_t fsm_int1;
2909 lsm6dsv16bx_mlc_int1_t mlc_int1;
2910 lsm6dsv16bx_md1_cfg_t md1_cfg;
2911 lsm6dsv16bx_md2_cfg_t md2_cfg;
2912 lsm6dsv16bx_ctrl4_t ctrl4;
2913 int32_t ret;
2914
2915 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
2916 if (ret == 0)
2917 {
2918 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
2919 }
2920 if (ret == 0)
2921 {
2922 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_INT1, (uint8_t *)&fsm_int1, 1);
2923 }
2924 if (ret == 0)
2925 {
2926 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_INT1, (uint8_t *)&mlc_int1, 1);
2927 }
2928
2929 if (ret == 0)
2930 {
2931 emb_func_int1.int1_step_detector = val.step_detector;
2932 emb_func_int1.int1_tilt = val.tilt;
2933 emb_func_int1.int1_sig_mot = val.sig_mot;
2934 emb_func_int1.int1_fsm_lc = val.fsm_lc;
2935 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
2936 }
2937 if (ret == 0)
2938 {
2939 fsm_int1.int1_fsm1 = val.fsm1;
2940 fsm_int1.int1_fsm2 = val.fsm2;
2941 fsm_int1.int1_fsm3 = val.fsm3;
2942 fsm_int1.int1_fsm4 = val.fsm4;
2943 fsm_int1.int1_fsm5 = val.fsm5;
2944 fsm_int1.int1_fsm6 = val.fsm6;
2945 fsm_int1.int1_fsm7 = val.fsm7;
2946 fsm_int1.int1_fsm8 = val.fsm8;
2947 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FSM_INT1, (uint8_t *)&fsm_int1, 1);
2948 }
2949 if (ret == 0)
2950 {
2951 mlc_int1.int1_mlc1 = val.mlc1;
2952 mlc_int1.int1_mlc2 = val.mlc2;
2953 mlc_int1.int1_mlc3 = val.mlc3;
2954 mlc_int1.int1_mlc4 = val.mlc4;
2955 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_MLC_INT1, (uint8_t *)&mlc_int1, 1);
2956 }
2957
2958 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
2959
2960 if (ret == 0)
2961 {
2962 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
2963 }
2964 if (ret == 0)
2965 {
2966 if ((val.emb_func_stand_by | val.timestamp) != PROPERTY_DISABLE)
2967 {
2968 ctrl4.int2_on_int1 = PROPERTY_ENABLE;
2969 }
2970 else
2971 {
2972 ctrl4.int2_on_int1 = PROPERTY_DISABLE;
2973 }
2974 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
2975 }
2976
2977 if (ret == 0)
2978 {
2979 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2980 }
2981
2982 if (ret == 0)
2983 {
2984 int2_ctrl.int2_emb_func_endop = val.emb_func_stand_by;
2985 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2986 }
2987
2988
2989 if (ret == 0)
2990 {
2991 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2992 }
2993
2994 if (ret == 0)
2995 {
2996 md2_cfg.int2_timestamp = val.timestamp;
2997 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2998 }
2999
3000 if (ret == 0)
3001 {
3002 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3003 }
3004
3005 if (ret == 0)
3006 {
3007 inactivity_dur.sleep_status_on_int = val.sleep_status;
3008 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3009 }
3010
3011
3012 if (ret == 0)
3013 {
3014 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
3015 }
3016
3017 if (ret == 0)
3018 {
3019 int1_ctrl.int1_drdy_xl = val.drdy_xl;
3020 int1_ctrl.int1_drdy_g = val.drdy_gy;
3021 int1_ctrl.int1_fifo_th = val.fifo_th;
3022 int1_ctrl.int1_fifo_ovr = val.fifo_ovr;
3023 int1_ctrl.int1_fifo_full = val.fifo_full;
3024 int1_ctrl.int1_cnt_bdr = val.fifo_bdr;
3025 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
3026 }
3027
3028 if (ret == 0)
3029 {
3030 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3031 }
3032
3033 if (ret == 0)
3034 {
3035 if ((emb_func_int1.int1_fsm_lc
3036 | emb_func_int1.int1_sig_mot
3037 | emb_func_int1.int1_step_detector
3038 | emb_func_int1.int1_tilt
3039 | fsm_int1.int1_fsm1
3040 | fsm_int1.int1_fsm2
3041 | fsm_int1.int1_fsm3
3042 | fsm_int1.int1_fsm4
3043 | fsm_int1.int1_fsm5
3044 | fsm_int1.int1_fsm6
3045 | fsm_int1.int1_fsm7
3046 | fsm_int1.int1_fsm8
3047 | mlc_int1.int1_mlc1
3048 | mlc_int1.int1_mlc2
3049 | mlc_int1.int1_mlc3
3050 | mlc_int1.int1_mlc4) != PROPERTY_DISABLE)
3051 {
3052 md1_cfg.int1_emb_func = PROPERTY_ENABLE;
3053 }
3054 else
3055 {
3056 md1_cfg.int1_emb_func = PROPERTY_DISABLE;
3057 }
3058 md1_cfg.int1_6d = val.six_d;
3059 md1_cfg.int1_double_tap = val.double_tap;
3060 md1_cfg.int1_ff = val.free_fall;
3061 md1_cfg.int1_wu = val.wake_up;
3062 md1_cfg.int1_single_tap = val.single_tap;
3063 if ((val.sleep_status | val.sleep_change) != PROPERTY_DISABLE)
3064 {
3065 md1_cfg.int1_sleep_change = PROPERTY_ENABLE;
3066 }
3067 else
3068 {
3069 md1_cfg.int1_sleep_change = PROPERTY_DISABLE;
3070 }
3071 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3072 }
3073
3074 if (ret == 0)
3075 {
3076 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3077 }
3078
3079 if (ret == 0)
3080 {
3081 pedo_cmd_reg.carry_count_en = val.step_count_overflow;
3082 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3083 }
3084
3085
3086 if (ret == 0)
3087 {
3088 ret = lsm6dsv16bx_pin_int2_route_get(ctx, &pin_int2_route);
3089 }
3090
3091 if (ret == 0)
3092 {
3093 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3094 }
3095 if (ret == 0)
3096 {
3097 if ((pin_int2_route.six_d
3098 | pin_int2_route.double_tap
3099 | pin_int2_route.free_fall
3100 | pin_int2_route.wake_up
3101 | pin_int2_route.single_tap
3102 | pin_int2_route.sleep_status
3103 | pin_int2_route.sleep_change
3104 | val.six_d
3105 | val.double_tap
3106 | val.free_fall
3107 | val.wake_up
3108 | val.single_tap
3109 | val.sleep_status
3110 | val.sleep_change) != PROPERTY_DISABLE)
3111 {
3112 functions_enable.interrupts_enable = PROPERTY_ENABLE;
3113 }
3114
3115 else
3116 {
3117 functions_enable.interrupts_enable = PROPERTY_DISABLE;
3118 }
3119
3120 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3121 }
3122
3123 return ret;
3124 }
3125
3126 /**
3127 * @brief It routes interrupt signals on INT 1 pin.[get]
3128 *
3129 * @param ctx read / write interface definitions
3130 * @param val It routes interrupt signals on INT 1 pin.
3131 * @retval interface status (MANDATORY: return 0 -> no Error)
3132 *
3133 */
lsm6dsv16bx_pin_int1_route_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_pin_int_route_t * val)3134 int32_t lsm6dsv16bx_pin_int1_route_get(const stmdev_ctx_t *ctx,
3135 lsm6dsv16bx_pin_int_route_t *val)
3136 {
3137 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
3138 lsm6dsv16bx_emb_func_int1_t emb_func_int1;
3139 lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg;
3140 lsm6dsv16bx_int1_ctrl_t int1_ctrl;
3141 lsm6dsv16bx_int2_ctrl_t int2_ctrl;
3142 lsm6dsv16bx_fsm_int1_t fsm_int1;
3143 lsm6dsv16bx_mlc_int1_t mlc_int1;
3144 lsm6dsv16bx_md1_cfg_t md1_cfg;
3145 lsm6dsv16bx_md2_cfg_t md2_cfg;
3146 lsm6dsv16bx_ctrl4_t ctrl4;
3147 int32_t ret;
3148
3149
3150 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
3151 if (ctrl4.int2_on_int1 == PROPERTY_ENABLE)
3152 {
3153 if (ret == 0)
3154 {
3155 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3156 val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop;
3157 }
3158 if (ret == 0)
3159 {
3160 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3161 val->timestamp = md2_cfg.int2_timestamp;
3162 }
3163 }
3164
3165 if (ret == 0)
3166 {
3167 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3168 val->sleep_status = inactivity_dur.sleep_status_on_int;
3169 }
3170
3171
3172 if (ret == 0)
3173 {
3174 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
3175 val->drdy_xl = int1_ctrl.int1_drdy_xl;
3176 val->drdy_gy = int1_ctrl.int1_drdy_g;
3177 val->fifo_th = int1_ctrl.int1_fifo_th;
3178 val->fifo_ovr = int1_ctrl.int1_fifo_ovr;
3179 val->fifo_full = int1_ctrl.int1_fifo_full;
3180 val->fifo_bdr = int1_ctrl.int1_cnt_bdr;
3181 }
3182
3183
3184 if (ret == 0)
3185 {
3186 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3187 val->six_d = md1_cfg.int1_6d;
3188 val->double_tap = md1_cfg.int1_double_tap;
3189 val->free_fall = md1_cfg.int1_ff;
3190 val->wake_up = md1_cfg.int1_wu;
3191 val->single_tap = md1_cfg.int1_single_tap;
3192 val->sleep_change = md1_cfg.int1_sleep_change;
3193 }
3194
3195 if (ret == 0)
3196 {
3197 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
3198 }
3199 if (ret == 0)
3200 {
3201 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
3202 val->step_detector = emb_func_int1.int1_step_detector;
3203 val->tilt = emb_func_int1.int1_tilt;
3204 val->sig_mot = emb_func_int1.int1_sig_mot;
3205 val->fsm_lc = emb_func_int1.int1_fsm_lc;
3206 }
3207 if (ret == 0)
3208 {
3209 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_INT1, (uint8_t *)&fsm_int1, 1);
3210 val->fsm1 = fsm_int1.int1_fsm1;
3211 val->fsm2 = fsm_int1.int1_fsm2;
3212 val->fsm3 = fsm_int1.int1_fsm3;
3213 val->fsm4 = fsm_int1.int1_fsm4;
3214 val->fsm5 = fsm_int1.int1_fsm5;
3215 val->fsm6 = fsm_int1.int1_fsm6;
3216 val->fsm7 = fsm_int1.int1_fsm7;
3217 val->fsm8 = fsm_int1.int1_fsm8;
3218 }
3219 if (ret == 0)
3220 {
3221 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_INT1, (uint8_t *)&mlc_int1, 1);
3222 val->mlc1 = mlc_int1.int1_mlc1;
3223 val->mlc2 = mlc_int1.int1_mlc2;
3224 val->mlc3 = mlc_int1.int1_mlc3;
3225 val->mlc4 = mlc_int1.int1_mlc4;
3226 }
3227
3228 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
3229
3230 if (ret == 0)
3231 {
3232 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3233 val->step_count_overflow = pedo_cmd_reg.carry_count_en;
3234 }
3235
3236 return ret;
3237 }
3238
3239
3240 /**
3241 * @brief It routes interrupt signals on INT 2 pin.[set]
3242 *
3243 * @param ctx read / write interface definitions
3244 * @param val It routes interrupt signals on INT 2 pin.
3245 * @retval interface status (MANDATORY: return 0 -> no Error)
3246 *
3247 */
lsm6dsv16bx_pin_int2_route_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_pin_int_route_t val)3248 int32_t lsm6dsv16bx_pin_int2_route_set(const stmdev_ctx_t *ctx,
3249 lsm6dsv16bx_pin_int_route_t val)
3250 {
3251 lsm6dsv16bx_functions_enable_t functions_enable;
3252 lsm6dsv16bx_pin_int_route_t pin_int1_route;
3253 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
3254 lsm6dsv16bx_emb_func_int2_t emb_func_int2;
3255 lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg;
3256 lsm6dsv16bx_int2_ctrl_t int2_ctrl;
3257 lsm6dsv16bx_fsm_int2_t fsm_int2;
3258 lsm6dsv16bx_mlc_int2_t mlc_int2;
3259 lsm6dsv16bx_ctrl7_t ctrl7;
3260 lsm6dsv16bx_md2_cfg_t md2_cfg;
3261 lsm6dsv16bx_ctrl4_t ctrl4;
3262 int32_t ret;
3263
3264
3265 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
3266 if (ret == 0)
3267 {
3268 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
3269 }
3270 if (ret == 0)
3271 {
3272 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_INT2, (uint8_t *)&fsm_int2, 1);
3273 }
3274 if (ret == 0)
3275 {
3276 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_INT2, (uint8_t *)&mlc_int2, 1);
3277 }
3278
3279 if (ret == 0)
3280 {
3281 emb_func_int2.int2_step_detector = val.step_detector;
3282 emb_func_int2.int2_tilt = val.tilt;
3283 emb_func_int2.int2_sig_mot = val.sig_mot;
3284 emb_func_int2.int2_fsm_lc = val.fsm_lc;
3285 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
3286 }
3287 if (ret == 0)
3288 {
3289 fsm_int2.int2_fsm1 = val.fsm1;
3290 fsm_int2.int2_fsm2 = val.fsm2;
3291 fsm_int2.int2_fsm3 = val.fsm3;
3292 fsm_int2.int2_fsm4 = val.fsm4;
3293 fsm_int2.int2_fsm5 = val.fsm5;
3294 fsm_int2.int2_fsm6 = val.fsm6;
3295 fsm_int2.int2_fsm7 = val.fsm7;
3296 fsm_int2.int2_fsm8 = val.fsm8;
3297 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FSM_INT2, (uint8_t *)&fsm_int2, 1);
3298 }
3299 if (ret == 0)
3300 {
3301 mlc_int2.int2_mlc1 = val.mlc1;
3302 mlc_int2.int2_mlc2 = val.mlc2;
3303 mlc_int2.int2_mlc3 = val.mlc3;
3304 mlc_int2.int2_mlc4 = val.mlc4;
3305 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_MLC_INT2, (uint8_t *)&mlc_int2, 1);
3306 }
3307
3308 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
3309
3310 if (ret == 0)
3311 {
3312 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
3313 }
3314 if (ret == 0)
3315 {
3316 if ((val.emb_func_stand_by | val.timestamp) != PROPERTY_DISABLE)
3317 {
3318 ctrl4.int2_on_int1 = PROPERTY_DISABLE;
3319 }
3320 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
3321 }
3322
3323 if (ret == 0)
3324 {
3325 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3326 }
3327
3328 if (ret == 0)
3329 {
3330 inactivity_dur.sleep_status_on_int = val.sleep_status;
3331 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3332 }
3333
3334 if (ret == 0)
3335 {
3336 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3337 }
3338
3339 if (ret == 0)
3340 {
3341 int2_ctrl.int2_drdy_xl = val.drdy_xl;
3342 int2_ctrl.int2_drdy_g = val.drdy_gy;
3343 int2_ctrl.int2_fifo_th = val.fifo_th;
3344 int2_ctrl.int2_fifo_ovr = val.fifo_ovr;
3345 int2_ctrl.int2_fifo_full = val.fifo_full;
3346 int2_ctrl.int2_cnt_bdr = val.fifo_bdr;
3347 int2_ctrl.int2_emb_func_endop = val.emb_func_stand_by;
3348 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3349 }
3350
3351 if (ret == 0)
3352 {
3353 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
3354 ctrl7.int2_drdy_ah_qvar = val.drdy_ah_qvar;
3355 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
3356 }
3357
3358 if (ret == 0)
3359 {
3360 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3361 }
3362
3363 if (ret == 0)
3364 {
3365 if ((emb_func_int2.int2_fsm_lc
3366 | emb_func_int2.int2_sig_mot
3367 | emb_func_int2.int2_step_detector
3368 | emb_func_int2.int2_tilt
3369 | fsm_int2.int2_fsm1
3370 | fsm_int2.int2_fsm2
3371 | fsm_int2.int2_fsm3
3372 | fsm_int2.int2_fsm4
3373 | fsm_int2.int2_fsm5
3374 | fsm_int2.int2_fsm6
3375 | fsm_int2.int2_fsm7
3376 | fsm_int2.int2_fsm8
3377 | mlc_int2.int2_mlc1
3378 | mlc_int2.int2_mlc2
3379 | mlc_int2.int2_mlc3
3380 | mlc_int2.int2_mlc4) != PROPERTY_DISABLE)
3381 {
3382 md2_cfg.int2_emb_func = PROPERTY_ENABLE;
3383 }
3384 else
3385 {
3386 md2_cfg.int2_emb_func = PROPERTY_DISABLE;
3387 }
3388 md2_cfg.int2_6d = val.six_d;
3389 md2_cfg.int2_double_tap = val.double_tap;
3390 md2_cfg.int2_ff = val.free_fall;
3391 md2_cfg.int2_wu = val.wake_up;
3392 md2_cfg.int2_single_tap = val.single_tap;
3393 md2_cfg.int2_timestamp = val.timestamp;
3394 if ((val.sleep_status | val.sleep_change) != PROPERTY_DISABLE)
3395 {
3396 md2_cfg.int2_sleep_change = PROPERTY_ENABLE;
3397 }
3398 else
3399 {
3400 md2_cfg.int2_sleep_change = PROPERTY_DISABLE;
3401 }
3402 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3403 }
3404
3405 if (ret == 0)
3406 {
3407 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3408 }
3409
3410 if (ret == 0)
3411 {
3412 pedo_cmd_reg.carry_count_en = val.step_count_overflow;
3413 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3414 }
3415
3416
3417 if (ret == 0)
3418 {
3419 ret = lsm6dsv16bx_pin_int1_route_get(ctx, &pin_int1_route);
3420 }
3421
3422 if (ret == 0)
3423 {
3424 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3425 }
3426 if (ret == 0)
3427 {
3428 if ((pin_int1_route.six_d
3429 | pin_int1_route.double_tap
3430 | pin_int1_route.free_fall
3431 | pin_int1_route.wake_up
3432 | pin_int1_route.single_tap
3433 | pin_int1_route.sleep_status
3434 | pin_int1_route.sleep_change
3435 | val.six_d
3436 | val.double_tap
3437 | val.free_fall
3438 | val.wake_up
3439 | val.single_tap
3440 | val.sleep_status
3441 | val.sleep_change) != PROPERTY_DISABLE)
3442 {
3443 functions_enable.interrupts_enable = PROPERTY_ENABLE;
3444 }
3445
3446 else
3447 {
3448 functions_enable.interrupts_enable = PROPERTY_DISABLE;
3449 }
3450
3451 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3452 }
3453
3454 return ret;
3455 }
3456
3457 /**
3458 * @brief It routes interrupt signals on INT 2 pin.[get]
3459 *
3460 * @param ctx read / write interface definitions
3461 * @param val It routes interrupt signals on INT 2 pin.
3462 * @retval interface status (MANDATORY: return 0 -> no Error)
3463 *
3464 */
lsm6dsv16bx_pin_int2_route_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_pin_int_route_t * val)3465 int32_t lsm6dsv16bx_pin_int2_route_get(const stmdev_ctx_t *ctx,
3466 lsm6dsv16bx_pin_int_route_t *val)
3467 {
3468 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
3469 lsm6dsv16bx_emb_func_int2_t emb_func_int2;
3470 lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg;
3471 lsm6dsv16bx_int2_ctrl_t int2_ctrl;
3472 lsm6dsv16bx_fsm_int2_t fsm_int2;
3473 lsm6dsv16bx_mlc_int2_t mlc_int2;
3474 lsm6dsv16bx_ctrl7_t ctrl7;
3475 lsm6dsv16bx_md2_cfg_t md2_cfg;
3476 lsm6dsv16bx_ctrl4_t ctrl4;
3477 int32_t ret;
3478
3479
3480 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL4, (uint8_t *)&ctrl4, 1);
3481 if (ctrl4.int2_on_int1 == PROPERTY_DISABLE)
3482 {
3483 if (ret == 0)
3484 {
3485 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3486 val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop;
3487 }
3488 if (ret == 0)
3489 {
3490 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3491 val->timestamp = md2_cfg.int2_timestamp;
3492 }
3493 }
3494
3495 if (ret == 0)
3496 {
3497 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3498 val->sleep_status = inactivity_dur.sleep_status_on_int;
3499 }
3500
3501
3502 if (ret == 0)
3503 {
3504 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3505 val->drdy_xl = int2_ctrl.int2_drdy_xl;
3506 val->drdy_gy = int2_ctrl.int2_drdy_g;
3507 val->fifo_th = int2_ctrl.int2_fifo_th;
3508 val->fifo_ovr = int2_ctrl.int2_fifo_ovr;
3509 val->fifo_full = int2_ctrl.int2_fifo_full;
3510 val->fifo_bdr = int2_ctrl.int2_cnt_bdr;
3511 }
3512
3513 if (ret == 0)
3514 {
3515 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
3516 val->drdy_ah_qvar = ctrl7.int2_drdy_ah_qvar;
3517 }
3518
3519 if (ret == 0)
3520 {
3521 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3522 val->six_d = md2_cfg.int2_6d;
3523 val->double_tap = md2_cfg.int2_double_tap;
3524 val->free_fall = md2_cfg.int2_ff;
3525 val->wake_up = md2_cfg.int2_wu;
3526 val->single_tap = md2_cfg.int2_single_tap;
3527 val->sleep_change = md2_cfg.int2_sleep_change;
3528 }
3529
3530 if (ret == 0)
3531 {
3532 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
3533 }
3534 if (ret == 0)
3535 {
3536 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
3537 val->step_detector = emb_func_int2.int2_step_detector;
3538 val->tilt = emb_func_int2.int2_tilt;
3539 val->sig_mot = emb_func_int2.int2_sig_mot;
3540 val->fsm_lc = emb_func_int2.int2_fsm_lc;
3541 }
3542 if (ret == 0)
3543 {
3544 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_INT2, (uint8_t *)&fsm_int2, 1);
3545 val->fsm1 = fsm_int2.int2_fsm1;
3546 val->fsm2 = fsm_int2.int2_fsm2;
3547 val->fsm3 = fsm_int2.int2_fsm3;
3548 val->fsm4 = fsm_int2.int2_fsm4;
3549 val->fsm5 = fsm_int2.int2_fsm5;
3550 val->fsm6 = fsm_int2.int2_fsm6;
3551 val->fsm7 = fsm_int2.int2_fsm7;
3552 val->fsm8 = fsm_int2.int2_fsm8;
3553 }
3554 if (ret == 0)
3555 {
3556 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_INT2, (uint8_t *)&mlc_int2, 1);
3557 val->mlc1 = mlc_int2.int2_mlc1;
3558 val->mlc2 = mlc_int2.int2_mlc2;
3559 val->mlc3 = mlc_int2.int2_mlc3;
3560 val->mlc4 = mlc_int2.int2_mlc4;
3561 }
3562
3563 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
3564
3565 if (ret == 0)
3566 {
3567 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3568 val->step_count_overflow = pedo_cmd_reg.carry_count_en;
3569 }
3570
3571 return ret;
3572 }
3573
3574 /**
3575 * @brief Enables INT pin when I3C is enabled.[set]
3576 *
3577 * @param ctx read / write interface definitions
3578 * @param val Enables INT pin when I3C is enabled.
3579 * @retval interface status (MANDATORY: return 0 -> no Error)
3580 *
3581 */
lsm6dsv16bx_pin_int_en_when_i2c_set(const stmdev_ctx_t * ctx,uint8_t val)3582 int32_t lsm6dsv16bx_pin_int_en_when_i2c_set(const stmdev_ctx_t *ctx, uint8_t val)
3583 {
3584 lsm6dsv16bx_ctrl5_t ctrl5;
3585 int32_t ret;
3586
3587 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1);
3588 if (ret == 0)
3589 {
3590 ctrl5.int_en_i3c = val;
3591 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1);
3592 }
3593
3594 return ret;
3595 }
3596
3597 /**
3598 * @brief Enables INT pin when I3C is enabled.[get]
3599 *
3600 * @param ctx read / write interface definitions
3601 * @param val Enables INT pin when I3C is enabled.
3602 * @retval interface status (MANDATORY: return 0 -> no Error)
3603 *
3604 */
lsm6dsv16bx_pin_int_en_when_i2c_get(const stmdev_ctx_t * ctx,uint8_t * val)3605 int32_t lsm6dsv16bx_pin_int_en_when_i2c_get(const stmdev_ctx_t *ctx, uint8_t *val)
3606 {
3607 lsm6dsv16bx_ctrl5_t ctrl5;
3608 int32_t ret;
3609
3610 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL5, (uint8_t *)&ctrl5, 1);
3611 *val = ctrl5.int_en_i3c;
3612
3613 return ret;
3614 }
3615
3616 /**
3617 * @brief Interrupt notification mode.[set]
3618 *
3619 * @param ctx read / write interface definitions
3620 * @param val ALL_INT_PULSED, BASE_LATCHED_EMB_PULSED, BASE_PULSED_EMB_LATCHED, ALL_INT_LATCHED,
3621 * @retval interface status (MANDATORY: return 0 -> no Error)
3622 *
3623 */
lsm6dsv16bx_int_notification_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_int_notification_t val)3624 int32_t lsm6dsv16bx_int_notification_set(const stmdev_ctx_t *ctx,
3625 lsm6dsv16bx_int_notification_t val)
3626 {
3627 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
3628 lsm6dsv16bx_page_rw_t page_rw;
3629 int32_t ret;
3630
3631 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3632 if (ret == 0)
3633 {
3634 tap_cfg0.lir = (uint8_t)val & 0x01U;
3635 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3636 }
3637
3638 if (ret == 0)
3639 {
3640 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
3641 }
3642 if (ret == 0)
3643 {
3644 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
3645 }
3646
3647 if (ret == 0)
3648 {
3649 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
3650 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
3651 }
3652
3653 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
3654
3655 return ret;
3656 }
3657
3658 /**
3659 * @brief Interrupt notification mode.[get]
3660 *
3661 * @param ctx read / write interface definitions
3662 * @param val ALL_INT_PULSED, BASE_LATCHED_EMB_PULSED, BASE_PULSED_EMB_LATCHED, ALL_INT_LATCHED,
3663 * @retval interface status (MANDATORY: return 0 -> no Error)
3664 *
3665 */
lsm6dsv16bx_int_notification_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_int_notification_t * val)3666 int32_t lsm6dsv16bx_int_notification_get(const stmdev_ctx_t *ctx,
3667 lsm6dsv16bx_int_notification_t *val)
3668 {
3669 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
3670 lsm6dsv16bx_page_rw_t page_rw;
3671 int32_t ret;
3672
3673 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3674 if (ret == 0)
3675 {
3676 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
3677 }
3678 if (ret == 0)
3679 {
3680 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PAGE_RW, (uint8_t *)&page_rw, 1);
3681 }
3682
3683 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
3684
3685 switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir)
3686 {
3687 case LSM6DSV16BX_ALL_INT_PULSED:
3688 *val = LSM6DSV16BX_ALL_INT_PULSED;
3689 break;
3690
3691 case LSM6DSV16BX_BASE_LATCHED_EMB_PULSED:
3692 *val = LSM6DSV16BX_BASE_LATCHED_EMB_PULSED;
3693 break;
3694
3695 case LSM6DSV16BX_BASE_PULSED_EMB_LATCHED:
3696 *val = LSM6DSV16BX_BASE_PULSED_EMB_LATCHED;
3697 break;
3698
3699 case LSM6DSV16BX_ALL_INT_LATCHED:
3700 *val = LSM6DSV16BX_ALL_INT_LATCHED;
3701 break;
3702
3703 default:
3704 *val = LSM6DSV16BX_ALL_INT_PULSED;
3705 break;
3706 }
3707 return ret;
3708 }
3709
3710 /**
3711 * @}
3712 *
3713 */
3714
3715 /**
3716 * @defgroup Wake Up event and Activity / Inactivity detection
3717 * @brief This section groups all the functions that manage the Wake Up
3718 * event generation.
3719 * @{
3720 *
3721 */
3722
3723 /**
3724 * @brief Enable activity/inactivity (sleep) function.[set]
3725 *
3726 * @param ctx read / write interface definitions
3727 * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN,
3728 * @retval interface status (MANDATORY: return 0 -> no Error)
3729 *
3730 */
lsm6dsv16bx_act_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_act_mode_t val)3731 int32_t lsm6dsv16bx_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_mode_t val)
3732 {
3733 lsm6dsv16bx_functions_enable_t functions_enable;
3734 int32_t ret;
3735
3736 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3737 if (ret == 0)
3738 {
3739 functions_enable.inact_en = (uint8_t)val & 0x03U;
3740 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3741 }
3742
3743 return ret;
3744 }
3745
3746 /**
3747 * @brief Enable activity/inactivity (sleep) function.[get]
3748 *
3749 * @param ctx read / write interface definitions
3750 * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN,
3751 * @retval interface status (MANDATORY: return 0 -> no Error)
3752 *
3753 */
lsm6dsv16bx_act_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_act_mode_t * val)3754 int32_t lsm6dsv16bx_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_act_mode_t *val)
3755 {
3756 lsm6dsv16bx_functions_enable_t functions_enable;
3757 int32_t ret;
3758
3759 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3760 switch (functions_enable.inact_en)
3761 {
3762 case LSM6DSV16BX_XL_AND_GY_NOT_AFFECTED:
3763 *val = LSM6DSV16BX_XL_AND_GY_NOT_AFFECTED;
3764 break;
3765
3766 case LSM6DSV16BX_XL_LOW_POWER_GY_NOT_AFFECTED:
3767 *val = LSM6DSV16BX_XL_LOW_POWER_GY_NOT_AFFECTED;
3768 break;
3769
3770 case LSM6DSV16BX_XL_LOW_POWER_GY_SLEEP:
3771 *val = LSM6DSV16BX_XL_LOW_POWER_GY_SLEEP;
3772 break;
3773
3774 case LSM6DSV16BX_XL_LOW_POWER_GY_POWER_DOWN:
3775 *val = LSM6DSV16BX_XL_LOW_POWER_GY_POWER_DOWN;
3776 break;
3777
3778 default:
3779 *val = LSM6DSV16BX_XL_AND_GY_NOT_AFFECTED;
3780 break;
3781 }
3782 return ret;
3783 }
3784
3785 /**
3786 * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[set]
3787 *
3788 * @param ctx read / write interface definitions
3789 * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE,
3790 * @retval interface status (MANDATORY: return 0 -> no Error)
3791 *
3792 */
lsm6dsv16bx_act_from_sleep_to_act_dur_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_act_from_sleep_to_act_dur_t val)3793 int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx,
3794 lsm6dsv16bx_act_from_sleep_to_act_dur_t val)
3795 {
3796 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
3797 int32_t ret;
3798
3799 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3800 if (ret == 0)
3801 {
3802 inactivity_dur.inact_dur = (uint8_t)val & 0x3U;
3803 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3804 }
3805
3806 return ret;
3807 }
3808
3809 /**
3810 * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[get]
3811 *
3812 * @param ctx read / write interface definitions
3813 * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE,
3814 * @retval interface status (MANDATORY: return 0 -> no Error)
3815 *
3816 */
lsm6dsv16bx_act_from_sleep_to_act_dur_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_act_from_sleep_to_act_dur_t * val)3817 int32_t lsm6dsv16bx_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx,
3818 lsm6dsv16bx_act_from_sleep_to_act_dur_t *val)
3819 {
3820 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
3821 int32_t ret;
3822
3823 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3824 switch (inactivity_dur.inact_dur)
3825 {
3826 case LSM6DSV16BX_SLEEP_TO_ACT_AT_1ST_SAMPLE:
3827 *val = LSM6DSV16BX_SLEEP_TO_ACT_AT_1ST_SAMPLE;
3828 break;
3829
3830 case LSM6DSV16BX_SLEEP_TO_ACT_AT_2ND_SAMPLE:
3831 *val = LSM6DSV16BX_SLEEP_TO_ACT_AT_2ND_SAMPLE;
3832 break;
3833
3834 case LSM6DSV16BX_SLEEP_TO_ACT_AT_3RD_SAMPLE:
3835 *val = LSM6DSV16BX_SLEEP_TO_ACT_AT_3RD_SAMPLE;
3836 break;
3837
3838 case LSM6DSV16BX_SLEEP_TO_ACT_AT_4th_SAMPLE:
3839 *val = LSM6DSV16BX_SLEEP_TO_ACT_AT_4th_SAMPLE;
3840 break;
3841
3842 default:
3843 *val = LSM6DSV16BX_SLEEP_TO_ACT_AT_1ST_SAMPLE;
3844 break;
3845 }
3846 return ret;
3847 }
3848
3849 /**
3850 * @brief Selects the accelerometer data rate during Inactivity.[set]
3851 *
3852 * @param ctx read / write interface definitions
3853 * @param val 1Hz875, 15Hz, 30Hz, 60Hz,
3854 * @retval interface status (MANDATORY: return 0 -> no Error)
3855 *
3856 */
lsm6dsv16bx_act_sleep_xl_odr_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_act_sleep_xl_odr_t val)3857 int32_t lsm6dsv16bx_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx,
3858 lsm6dsv16bx_act_sleep_xl_odr_t val)
3859 {
3860 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
3861 int32_t ret;
3862
3863 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3864 if (ret == 0)
3865 {
3866 inactivity_dur.xl_inact_odr = (uint8_t)val & 0x03U;
3867 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3868 }
3869
3870 return ret;
3871 }
3872
3873 /**
3874 * @brief Selects the accelerometer data rate during Inactivity.[get]
3875 *
3876 * @param ctx read / write interface definitions
3877 * @param val 1Hz875, 15Hz, 30Hz, 60Hz,
3878 * @retval interface status (MANDATORY: return 0 -> no Error)
3879 *
3880 */
lsm6dsv16bx_act_sleep_xl_odr_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_act_sleep_xl_odr_t * val)3881 int32_t lsm6dsv16bx_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx,
3882 lsm6dsv16bx_act_sleep_xl_odr_t *val)
3883 {
3884 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
3885 int32_t ret;
3886
3887 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3888 switch (inactivity_dur.xl_inact_odr)
3889 {
3890 case LSM6DSV16BX_1Hz875:
3891 *val = LSM6DSV16BX_1Hz875;
3892 break;
3893
3894 case LSM6DSV16BX_15Hz:
3895 *val = LSM6DSV16BX_15Hz;
3896 break;
3897
3898 case LSM6DSV16BX_30Hz:
3899 *val = LSM6DSV16BX_30Hz;
3900 break;
3901
3902 case LSM6DSV16BX_60Hz:
3903 *val = LSM6DSV16BX_60Hz;
3904 break;
3905
3906 default:
3907 *val = LSM6DSV16BX_1Hz875;
3908 break;
3909 }
3910 return ret;
3911 }
3912
3913 /**
3914 * @brief Wakeup and activity/inactivity threshold.[set]
3915 *
3916 * @param ctx read / write interface definitions
3917 * @param val Wakeup and activity/inactivity threshold.
3918 * @retval interface status (MANDATORY: return 0 -> no Error)
3919 *
3920 */
lsm6dsv16bx_act_thresholds_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_act_thresholds_t val)3921 int32_t lsm6dsv16bx_act_thresholds_set(const stmdev_ctx_t *ctx,
3922 lsm6dsv16bx_act_thresholds_t val)
3923 {
3924 lsm6dsv16bx_inactivity_ths_t inactivity_ths;
3925 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
3926 lsm6dsv16bx_wake_up_ths_t wake_up_ths;
3927 int32_t ret;
3928 float_t tmp;
3929
3930 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3931 if (ret == 0)
3932 {
3933 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
3934 }
3935
3936 if (ret == 0)
3937 {
3938 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
3939 }
3940
3941 if ((val.wk_ths_mg < (uint32_t)(7.8125f * 63.0f))
3942 && (val.inact_ths_mg < (uint32_t)(7.8125f * 63.0f)))
3943 {
3944 inactivity_dur.wu_inact_ths_w = 0;
3945
3946 tmp = (float_t)val.inact_ths_mg / 7.8125f;
3947 inactivity_ths.inact_ths = (uint8_t)tmp;
3948
3949 tmp = (float_t)val.wk_ths_mg / 7.8125f;
3950 wake_up_ths.wk_ths = (uint8_t)tmp;
3951 }
3952 else if ((val.wk_ths_mg < (uint32_t)(15.625f * 63.0f))
3953 && (val.inact_ths_mg < (uint32_t)(15.625f * 63.0f)))
3954 {
3955 inactivity_dur.wu_inact_ths_w = 1;
3956
3957 tmp = (float_t)val.inact_ths_mg / 15.625f;
3958 inactivity_ths.inact_ths = (uint8_t)tmp;
3959
3960 tmp = (float_t)val.wk_ths_mg / 15.625f;
3961 wake_up_ths.wk_ths = (uint8_t)tmp;
3962 }
3963 else if ((val.wk_ths_mg < (uint32_t)(31.25f * 63.0f))
3964 && (val.inact_ths_mg < (uint32_t)(31.25f * 63.0f)))
3965 {
3966 inactivity_dur.wu_inact_ths_w = 2;
3967
3968 tmp = (float_t)val.inact_ths_mg / 31.25f;
3969 inactivity_ths.inact_ths = (uint8_t)tmp;
3970
3971 tmp = (float_t)val.wk_ths_mg / 31.25f;
3972 wake_up_ths.wk_ths = (uint8_t)tmp;
3973 }
3974 else if ((val.wk_ths_mg < (uint32_t)(62.5f * 63.0f))
3975 && (val.inact_ths_mg < (uint32_t)(62.5f * 63.0f)))
3976 {
3977 inactivity_dur.wu_inact_ths_w = 3;
3978
3979 tmp = (float_t)val.inact_ths_mg / 62.5f;
3980 inactivity_ths.inact_ths = (uint8_t)tmp;
3981
3982 tmp = (float_t)val.wk_ths_mg / 62.5f;
3983 wake_up_ths.wk_ths = (uint8_t)tmp;
3984 }
3985 else if ((val.wk_ths_mg < (uint32_t)(125.0f * 63.0f))
3986 && (val.inact_ths_mg < (uint32_t)(125.0f * 63.0f)))
3987 {
3988 inactivity_dur.wu_inact_ths_w = 4;
3989
3990 tmp = (float_t)val.inact_ths_mg / 125.0f;
3991 inactivity_ths.inact_ths = (uint8_t)tmp;
3992
3993 tmp = (float_t)val.wk_ths_mg / 125.0f;
3994 wake_up_ths.wk_ths = (uint8_t)tmp;
3995 }
3996 else if ((val.wk_ths_mg < (uint32_t)(250.0f * 63.0f))
3997 && (val.inact_ths_mg < (uint32_t)(250.0f * 63.0f)))
3998 {
3999 inactivity_dur.wu_inact_ths_w = 5;
4000
4001 tmp = (float_t)val.inact_ths_mg / 250.0f;
4002 inactivity_ths.inact_ths = (uint8_t)tmp;
4003
4004 tmp = (float_t)val.wk_ths_mg / 250.0f;
4005 wake_up_ths.wk_ths = (uint8_t)tmp;
4006 }
4007 else // out of limit
4008 {
4009 inactivity_dur.wu_inact_ths_w = 5;
4010 inactivity_ths.inact_ths = 0x3FU;
4011 wake_up_ths.wk_ths = 0x3FU;
4012 }
4013
4014 if (ret == 0)
4015 {
4016 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
4017 }
4018 if (ret == 0)
4019 {
4020
4021 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
4022 }
4023 if (ret == 0)
4024 {
4025
4026 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4027 }
4028
4029 return ret;
4030 }
4031
4032 /**
4033 * @brief Wakeup and activity/inactivity threshold.[get]
4034 *
4035 * @param ctx read / write interface definitions
4036 * @param val Wakeup and activity/inactivity threshold.
4037 * @retval interface status (MANDATORY: return 0 -> no Error)
4038 *
4039 */
lsm6dsv16bx_act_thresholds_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_act_thresholds_t * val)4040 int32_t lsm6dsv16bx_act_thresholds_get(const stmdev_ctx_t *ctx,
4041 lsm6dsv16bx_act_thresholds_t *val)
4042 {
4043 lsm6dsv16bx_inactivity_dur_t inactivity_dur;
4044 lsm6dsv16bx_inactivity_ths_t inactivity_ths;
4045 lsm6dsv16bx_wake_up_ths_t wake_up_ths;
4046 int32_t ret;
4047 float_t tmp;
4048
4049 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
4050 if (ret == 0)
4051 {
4052 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
4053 }
4054 if (ret == 0)
4055 {
4056 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4057 }
4058
4059 switch (inactivity_dur.wu_inact_ths_w)
4060 {
4061 case 0:
4062 tmp = (float_t)wake_up_ths.wk_ths * 7.8125f;
4063 val->wk_ths_mg = (uint32_t)tmp;
4064
4065 tmp = (float_t)inactivity_ths.inact_ths * 7.8125f;
4066 val->inact_ths_mg = (uint32_t)tmp;
4067 break;
4068
4069 case 1:
4070 tmp = (float_t)wake_up_ths.wk_ths * 15.625f;
4071 val->wk_ths_mg = (uint32_t)tmp;
4072
4073 tmp = (float_t)inactivity_ths.inact_ths * 15.625f;
4074 val->inact_ths_mg = (uint32_t)tmp;
4075 break;
4076
4077 case 2:
4078 tmp = (float_t)wake_up_ths.wk_ths * 31.25f;
4079 val->wk_ths_mg = (uint32_t)tmp;
4080
4081 tmp = (float_t)inactivity_ths.inact_ths * 31.25f;
4082 val->inact_ths_mg = (uint32_t)tmp;
4083 break;
4084
4085 case 3:
4086 tmp = (float_t)wake_up_ths.wk_ths * 62.5f;
4087 val->wk_ths_mg = (uint32_t)tmp;
4088
4089 tmp = (float_t)inactivity_ths.inact_ths * 62.5f;
4090 val->inact_ths_mg = (uint32_t)tmp;
4091 break;
4092
4093 case 4:
4094 tmp = (float_t)wake_up_ths.wk_ths * 125.0f;
4095 val->wk_ths_mg = (uint32_t)tmp;
4096
4097 tmp = (float_t)inactivity_ths.inact_ths * 125.0f;
4098 val->inact_ths_mg = (uint32_t)tmp;
4099 break;
4100
4101 default:
4102 tmp = (float_t)wake_up_ths.wk_ths * 250.0f;
4103 val->wk_ths_mg = (uint32_t)tmp;
4104
4105 tmp = (float_t)inactivity_ths.inact_ths * 250.0f;
4106 val->inact_ths_mg = (uint32_t)tmp;
4107 break;
4108 }
4109
4110 return ret;
4111 }
4112
4113 /**
4114 * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [set]
4115 *
4116 * @param ctx read / write interface definitions
4117 * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time.
4118 * @retval interface status (MANDATORY: return 0 -> no Error)
4119 *
4120 */
lsm6dsv16bx_act_wkup_time_windows_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_act_wkup_time_windows_t val)4121 int32_t lsm6dsv16bx_act_wkup_time_windows_set(const stmdev_ctx_t *ctx,
4122 lsm6dsv16bx_act_wkup_time_windows_t val)
4123 {
4124 lsm6dsv16bx_wake_up_dur_t wake_up_dur;
4125 int32_t ret;
4126
4127 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4128 if (ret == 0)
4129 {
4130 wake_up_dur.wake_dur = val.shock;
4131 wake_up_dur.sleep_dur = val.quiet;
4132 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4133 }
4134
4135 return ret;
4136 }
4137
4138 /**
4139 * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [get]
4140 *
4141 * @param ctx read / write interface definitions
4142 * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time.
4143 * @retval interface status (MANDATORY: return 0 -> no Error)
4144 *
4145 */
lsm6dsv16bx_act_wkup_time_windows_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_act_wkup_time_windows_t * val)4146 int32_t lsm6dsv16bx_act_wkup_time_windows_get(const stmdev_ctx_t *ctx,
4147 lsm6dsv16bx_act_wkup_time_windows_t *val)
4148 {
4149 lsm6dsv16bx_wake_up_dur_t wake_up_dur;
4150 int32_t ret;
4151
4152 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4153 val->shock = wake_up_dur.wake_dur;
4154 val->quiet = wake_up_dur.sleep_dur;
4155
4156 return ret;
4157 }
4158
4159 /**
4160 * @}
4161 *
4162 */
4163
4164 /**
4165 * @defgroup Tap Generator
4166 * @brief This section groups all the functions that manage the
4167 * tap and double tap event generation.
4168 * @{
4169 *
4170 */
4171
4172 /**
4173 * @brief Enable axis for Tap - Double Tap detection.[set]
4174 *
4175 * @param ctx read / write interface definitions
4176 * @param val Enable axis for Tap - Double Tap detection.
4177 * @retval interface status (MANDATORY: return 0 -> no Error)
4178 *
4179 */
lsm6dsv16bx_tap_detection_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_tap_detection_t val)4180 int32_t lsm6dsv16bx_tap_detection_set(const stmdev_ctx_t *ctx,
4181 lsm6dsv16bx_tap_detection_t val)
4182 {
4183 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
4184 int32_t ret;
4185
4186 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4187 if (ret == 0)
4188 {
4189 tap_cfg0.tap_x_en = val.tap_x_en;
4190 tap_cfg0.tap_y_en = val.tap_y_en;
4191 tap_cfg0.tap_z_en = val.tap_z_en;
4192 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4193 }
4194
4195 return ret;
4196 }
4197
4198 /**
4199 * @brief Enable axis for Tap - Double Tap detection.[get]
4200 *
4201 * @param ctx read / write interface definitions
4202 * @param val Enable axis for Tap - Double Tap detection.
4203 * @retval interface status (MANDATORY: return 0 -> no Error)
4204 *
4205 */
lsm6dsv16bx_tap_detection_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_tap_detection_t * val)4206 int32_t lsm6dsv16bx_tap_detection_get(const stmdev_ctx_t *ctx,
4207 lsm6dsv16bx_tap_detection_t *val)
4208 {
4209 lsm6dsv16bx_tap_cfg0_t tap_cfg0;
4210 int32_t ret;
4211
4212 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4213 val->tap_x_en = tap_cfg0.tap_x_en;
4214 val->tap_y_en = tap_cfg0.tap_y_en;
4215 val->tap_z_en = tap_cfg0.tap_z_en;
4216
4217 return ret;
4218 }
4219
4220 /**
4221 * @brief axis Tap - Double Tap recognition thresholds.[set]
4222 *
4223 * @param ctx read / write interface definitions
4224 * @param val axis Tap - Double Tap recognition thresholds.
4225 * @retval interface status (MANDATORY: return 0 -> no Error)
4226 *
4227 */
lsm6dsv16bx_tap_thresholds_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_tap_thresholds_t val)4228 int32_t lsm6dsv16bx_tap_thresholds_set(const stmdev_ctx_t *ctx,
4229 lsm6dsv16bx_tap_thresholds_t val)
4230 {
4231 lsm6dsv16bx_tap_ths_6d_t tap_ths_6d;
4232 lsm6dsv16bx_tap_cfg2_t tap_cfg2;
4233 lsm6dsv16bx_tap_cfg1_t tap_cfg1;
4234 int32_t ret;
4235
4236 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4237 if (ret == 0)
4238 {
4239 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
4240 }
4241 if (ret == 0)
4242 {
4243 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4244 }
4245
4246 tap_cfg1.tap_ths_z = val.z;
4247 tap_cfg2.tap_ths_y = val.y;
4248 tap_ths_6d.tap_ths_x = val.x;
4249
4250 if (ret == 0)
4251 {
4252 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4253 }
4254 if (ret == 0)
4255 {
4256 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
4257 }
4258 if (ret == 0)
4259 {
4260 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4261 }
4262
4263 return ret;
4264 }
4265
4266 /**
4267 * @brief axis Tap - Double Tap recognition thresholds.[get]
4268 *
4269 * @param ctx read / write interface definitions
4270 * @param val axis Tap - Double Tap recognition thresholds.
4271 * @retval interface status (MANDATORY: return 0 -> no Error)
4272 *
4273 */
lsm6dsv16bx_tap_thresholds_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_tap_thresholds_t * val)4274 int32_t lsm6dsv16bx_tap_thresholds_get(const stmdev_ctx_t *ctx,
4275 lsm6dsv16bx_tap_thresholds_t *val)
4276 {
4277 lsm6dsv16bx_tap_ths_6d_t tap_ths_6d;
4278 lsm6dsv16bx_tap_cfg2_t tap_cfg2;
4279 lsm6dsv16bx_tap_cfg1_t tap_cfg1;
4280 int32_t ret;
4281
4282 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4283 if (ret == 0)
4284 {
4285 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
4286 }
4287 if (ret == 0)
4288 {
4289 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4290 }
4291
4292 val->z = tap_cfg1.tap_ths_z;
4293 val->y = tap_cfg2.tap_ths_y;
4294 val->x = tap_ths_6d.tap_ths_x;
4295
4296 return ret;
4297 }
4298
4299 /**
4300 * @brief Selection of axis priority for TAP detection.[set]
4301 *
4302 * @param ctx read / write interface definitions
4303 * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY ,
4304 * @retval interface status (MANDATORY: return 0 -> no Error)
4305 *
4306 */
lsm6dsv16bx_tap_axis_priority_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_tap_axis_priority_t val)4307 int32_t lsm6dsv16bx_tap_axis_priority_set(const stmdev_ctx_t *ctx,
4308 lsm6dsv16bx_tap_axis_priority_t val)
4309 {
4310 lsm6dsv16bx_tap_cfg1_t tap_cfg1;
4311 int32_t ret;
4312
4313 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4314 if (ret == 0)
4315 {
4316 tap_cfg1.tap_priority = (uint8_t)val & 0x07U;
4317 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4318 }
4319
4320 return ret;
4321 }
4322
4323 /**
4324 * @brief Selection of axis priority for TAP detection.[get]
4325 *
4326 * @param ctx read / write interface definitions
4327 * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY ,
4328 * @retval interface status (MANDATORY: return 0 -> no Error)
4329 *
4330 */
lsm6dsv16bx_tap_axis_priority_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_tap_axis_priority_t * val)4331 int32_t lsm6dsv16bx_tap_axis_priority_get(const stmdev_ctx_t *ctx,
4332 lsm6dsv16bx_tap_axis_priority_t *val)
4333 {
4334 lsm6dsv16bx_tap_cfg1_t tap_cfg1;
4335 int32_t ret;
4336
4337 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4338 switch (tap_cfg1.tap_priority)
4339 {
4340 case LSM6DSV16BX_XYZ :
4341 *val = LSM6DSV16BX_XYZ ;
4342 break;
4343
4344 case LSM6DSV16BX_YXZ :
4345 *val = LSM6DSV16BX_YXZ ;
4346 break;
4347
4348 case LSM6DSV16BX_XZY:
4349 *val = LSM6DSV16BX_XZY;
4350 break;
4351
4352 case LSM6DSV16BX_ZYX :
4353 *val = LSM6DSV16BX_ZYX ;
4354 break;
4355
4356 case LSM6DSV16BX_YZX :
4357 *val = LSM6DSV16BX_YZX ;
4358 break;
4359
4360 case LSM6DSV16BX_ZXY :
4361 *val = LSM6DSV16BX_ZXY ;
4362 break;
4363
4364 default:
4365 *val = LSM6DSV16BX_XYZ ;
4366 break;
4367 }
4368 return ret;
4369 }
4370
4371
4372 /**
4373 * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[set]
4374 *
4375 * @param ctx read / write interface definitions
4376 * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.
4377 * @retval interface status (MANDATORY: return 0 -> no Error)
4378 *
4379 */
lsm6dsv16bx_tap_time_windows_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_tap_time_windows_t val)4380 int32_t lsm6dsv16bx_tap_time_windows_set(const stmdev_ctx_t *ctx,
4381 lsm6dsv16bx_tap_time_windows_t val)
4382 {
4383 lsm6dsv16bx_tap_dur_t tap_dur;
4384 int32_t ret;
4385
4386 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_DUR, (uint8_t *)&tap_dur, 1);
4387 if (ret == 0)
4388 {
4389 tap_dur.shock = val.shock;
4390 tap_dur.quiet = val.quiet;
4391 tap_dur.dur = val.tap_gap;
4392 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_DUR, (uint8_t *)&tap_dur, 1);
4393 }
4394
4395 return ret;
4396 }
4397
4398 /**
4399 * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[get]
4400 *
4401 * @param ctx read / write interface definitions
4402 * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.
4403 * @retval interface status (MANDATORY: return 0 -> no Error)
4404 *
4405 */
lsm6dsv16bx_tap_time_windows_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_tap_time_windows_t * val)4406 int32_t lsm6dsv16bx_tap_time_windows_get(const stmdev_ctx_t *ctx,
4407 lsm6dsv16bx_tap_time_windows_t *val)
4408 {
4409 lsm6dsv16bx_tap_dur_t tap_dur;
4410 int32_t ret;
4411
4412 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_DUR, (uint8_t *)&tap_dur, 1);
4413 val->shock = tap_dur.shock;
4414 val->quiet = tap_dur.quiet;
4415 val->tap_gap = tap_dur.dur;
4416
4417 return ret;
4418 }
4419
4420 /**
4421 * @brief Single/double-tap event enable.[set]
4422 *
4423 * @param ctx read / write interface definitions
4424 * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE,
4425 * @retval interface status (MANDATORY: return 0 -> no Error)
4426 *
4427 */
lsm6dsv16bx_tap_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_tap_mode_t val)4428 int32_t lsm6dsv16bx_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_mode_t val)
4429 {
4430 lsm6dsv16bx_wake_up_ths_t wake_up_ths;
4431 int32_t ret;
4432
4433 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4434 if (ret == 0)
4435 {
4436 wake_up_ths.single_double_tap = (uint8_t)val & 0x01U;
4437 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4438 }
4439
4440 return ret;
4441 }
4442
4443 /**
4444 * @brief Single/double-tap event enable.[get]
4445 *
4446 * @param ctx read / write interface definitions
4447 * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE,
4448 * @retval interface status (MANDATORY: return 0 -> no Error)
4449 *
4450 */
lsm6dsv16bx_tap_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_tap_mode_t * val)4451 int32_t lsm6dsv16bx_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tap_mode_t *val)
4452 {
4453 lsm6dsv16bx_wake_up_ths_t wake_up_ths;
4454 int32_t ret;
4455
4456 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4457 switch (wake_up_ths.single_double_tap)
4458 {
4459 case LSM6DSV16BX_ONLY_SINGLE:
4460 *val = LSM6DSV16BX_ONLY_SINGLE;
4461 break;
4462
4463 case LSM6DSV16BX_BOTH_SINGLE_DOUBLE:
4464 *val = LSM6DSV16BX_BOTH_SINGLE_DOUBLE;
4465 break;
4466
4467 default:
4468 *val = LSM6DSV16BX_ONLY_SINGLE;
4469 break;
4470 }
4471 return ret;
4472 }
4473
4474 /**
4475 * @}
4476 *
4477 */
4478
4479 /**
4480 * @defgroup Six position detection (6D)
4481 * @brief This section groups all the functions concerning six position
4482 * detection (6D).
4483 * @{
4484 *
4485 */
4486
4487 /**
4488 * @brief Threshold for 4D/6D function.[set]
4489 *
4490 * @param ctx read / write interface definitions
4491 * @param val DEG_80, DEG_70, DEG_60, DEG_50,
4492 * @retval interface status (MANDATORY: return 0 -> no Error)
4493 *
4494 */
lsm6dsv16bx_6d_threshold_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_6d_threshold_t val)4495 int32_t lsm6dsv16bx_6d_threshold_set(const stmdev_ctx_t *ctx,
4496 lsm6dsv16bx_6d_threshold_t val)
4497 {
4498 lsm6dsv16bx_tap_ths_6d_t tap_ths_6d;
4499 int32_t ret;
4500
4501 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4502 if (ret == 0)
4503 {
4504 tap_ths_6d.sixd_ths = (uint8_t)val & 0x03U;
4505 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4506 }
4507
4508 return ret;
4509 }
4510
4511 /**
4512 * @brief Threshold for 4D/6D function.[get]
4513 *
4514 * @param ctx read / write interface definitions
4515 * @param val DEG_80, DEG_70, DEG_60, DEG_50,
4516 * @retval interface status (MANDATORY: return 0 -> no Error)
4517 *
4518 */
lsm6dsv16bx_6d_threshold_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_6d_threshold_t * val)4519 int32_t lsm6dsv16bx_6d_threshold_get(const stmdev_ctx_t *ctx,
4520 lsm6dsv16bx_6d_threshold_t *val)
4521 {
4522 lsm6dsv16bx_tap_ths_6d_t tap_ths_6d;
4523 int32_t ret;
4524
4525 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4526 switch (tap_ths_6d.sixd_ths)
4527 {
4528 case LSM6DSV16BX_DEG_80:
4529 *val = LSM6DSV16BX_DEG_80;
4530 break;
4531
4532 case LSM6DSV16BX_DEG_70:
4533 *val = LSM6DSV16BX_DEG_70;
4534 break;
4535
4536 case LSM6DSV16BX_DEG_60:
4537 *val = LSM6DSV16BX_DEG_60;
4538 break;
4539
4540 case LSM6DSV16BX_DEG_50:
4541 *val = LSM6DSV16BX_DEG_50;
4542 break;
4543
4544 default:
4545 *val = LSM6DSV16BX_DEG_80;
4546 break;
4547 }
4548 return ret;
4549 }
4550
4551 /**
4552 * @}
4553 *
4554 */
4555
4556 /**
4557 * @defgroup Free fall
4558 * @brief This section group all the functions concerning the free
4559 * fall detection.
4560 * @{
4561 *
4562 */
4563
4564 /**
4565 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set]
4566 *
4567 * @param ctx read / write interface definitions
4568 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
4569 * @retval interface status (MANDATORY: return 0 -> no Error)
4570 *
4571 */
lsm6dsv16bx_ff_time_windows_set(const stmdev_ctx_t * ctx,uint8_t val)4572 int32_t lsm6dsv16bx_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val)
4573 {
4574 lsm6dsv16bx_wake_up_dur_t wake_up_dur;
4575 lsm6dsv16bx_free_fall_t free_fall;
4576 int32_t ret;
4577
4578 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4579 if (ret == 0)
4580 {
4581 wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
4582 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4583 }
4584 if (ret == 0)
4585 {
4586 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1);
4587 }
4588
4589 if (ret == 0)
4590 {
4591 free_fall.ff_dur = (uint8_t)val & 0x1FU;
4592 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1);
4593 }
4594
4595 return ret;
4596 }
4597
4598 /**
4599 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get]
4600 *
4601 * @param ctx read / write interface definitions
4602 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
4603 * @retval interface status (MANDATORY: return 0 -> no Error)
4604 *
4605 */
lsm6dsv16bx_ff_time_windows_get(const stmdev_ctx_t * ctx,uint8_t * val)4606 int32_t lsm6dsv16bx_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val)
4607 {
4608 lsm6dsv16bx_wake_up_dur_t wake_up_dur;
4609 lsm6dsv16bx_free_fall_t free_fall;
4610 int32_t ret;
4611
4612 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4613 if (ret == 0)
4614 {
4615 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1);
4616 }
4617
4618 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
4619
4620 return ret;
4621 }
4622
4623 /**
4624 * @brief Free fall threshold setting.[set]
4625 *
4626 * @param ctx read / write interface definitions
4627 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
4628 * @retval interface status (MANDATORY: return 0 -> no Error)
4629 *
4630 */
lsm6dsv16bx_ff_thresholds_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_ff_thresholds_t val)4631 int32_t lsm6dsv16bx_ff_thresholds_set(const stmdev_ctx_t *ctx,
4632 lsm6dsv16bx_ff_thresholds_t val)
4633 {
4634 lsm6dsv16bx_free_fall_t free_fall;
4635 int32_t ret;
4636
4637 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1);
4638 if (ret == 0)
4639 {
4640 free_fall.ff_ths = (uint8_t)val & 0x7U;
4641 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1);
4642 }
4643
4644 return ret;
4645 }
4646
4647 /**
4648 * @brief Free fall threshold setting.[get]
4649 *
4650 * @param ctx read / write interface definitions
4651 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
4652 * @retval interface status (MANDATORY: return 0 -> no Error)
4653 *
4654 */
lsm6dsv16bx_ff_thresholds_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_ff_thresholds_t * val)4655 int32_t lsm6dsv16bx_ff_thresholds_get(const stmdev_ctx_t *ctx,
4656 lsm6dsv16bx_ff_thresholds_t *val)
4657 {
4658 lsm6dsv16bx_free_fall_t free_fall;
4659 int32_t ret;
4660
4661 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FREE_FALL, (uint8_t *)&free_fall, 1);
4662
4663 switch (free_fall.ff_ths)
4664 {
4665 case LSM6DSV16BX_156_mg:
4666 *val = LSM6DSV16BX_156_mg;
4667 break;
4668
4669 case LSM6DSV16BX_219_mg:
4670 *val = LSM6DSV16BX_219_mg;
4671 break;
4672
4673 case LSM6DSV16BX_250_mg:
4674 *val = LSM6DSV16BX_250_mg;
4675 break;
4676
4677 case LSM6DSV16BX_312_mg:
4678 *val = LSM6DSV16BX_312_mg;
4679 break;
4680
4681 case LSM6DSV16BX_344_mg:
4682 *val = LSM6DSV16BX_344_mg;
4683 break;
4684
4685 case LSM6DSV16BX_406_mg:
4686 *val = LSM6DSV16BX_406_mg;
4687 break;
4688
4689 case LSM6DSV16BX_469_mg:
4690 *val = LSM6DSV16BX_469_mg;
4691 break;
4692
4693 case LSM6DSV16BX_500_mg:
4694 *val = LSM6DSV16BX_500_mg;
4695 break;
4696
4697 default:
4698 *val = LSM6DSV16BX_156_mg;
4699 break;
4700 }
4701 return ret;
4702 }
4703
4704 /**
4705 * @}
4706 *
4707 */
4708
4709 /**
4710 * @defgroup FIFO
4711 * @brief This section group all the functions concerning the fifo usage
4712 * @{
4713 *
4714 */
4715
4716 /**
4717 * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[set]
4718 *
4719 * @param ctx read / write interface definitions
4720 * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).
4721 * @retval interface status (MANDATORY: return 0 -> no Error)
4722 *
4723 */
lsm6dsv16bx_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)4724 int32_t lsm6dsv16bx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
4725 {
4726 lsm6dsv16bx_fifo_ctrl1_t fifo_ctrl1;
4727 int32_t ret;
4728
4729 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
4730
4731 if (ret == 0)
4732 {
4733 fifo_ctrl1.wtm = val;
4734 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
4735 }
4736
4737 return ret;
4738 }
4739
4740 /**
4741 * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[get]
4742 *
4743 * @param ctx read / write interface definitions
4744 * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).
4745 * @retval interface status (MANDATORY: return 0 -> no Error)
4746 *
4747 */
lsm6dsv16bx_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)4748 int32_t lsm6dsv16bx_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
4749 {
4750 lsm6dsv16bx_fifo_ctrl1_t fifo_ctrl1;
4751 int32_t ret;
4752
4753 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
4754 *val = fifo_ctrl1.wtm;
4755
4756 return ret;
4757 }
4758
4759 /**
4760 * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[set]
4761 *
4762 * @param ctx read / write interface definitions
4763 * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.
4764 * @retval interface status (MANDATORY: return 0 -> no Error)
4765 *
4766 */
lsm6dsv16bx_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t * ctx,uint8_t val)4767 int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
4768 {
4769 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
4770 int32_t ret;
4771
4772 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4773 if (ret == 0)
4774 {
4775 fifo_ctrl2.xl_dualc_batch_from_fsm = val;
4776 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4777 }
4778
4779 return ret;
4780 }
4781
4782 /**
4783 * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[get]
4784 *
4785 * @param ctx read / write interface definitions
4786 * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.
4787 * @retval interface status (MANDATORY: return 0 -> no Error)
4788 *
4789 */
lsm6dsv16bx_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)4790 int32_t lsm6dsv16bx_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
4791 {
4792 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
4793 int32_t ret;
4794
4795 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4796 *val = fifo_ctrl2.xl_dualc_batch_from_fsm;
4797
4798 return ret;
4799 }
4800
4801 /**
4802 * @brief It configures the compression algorithm to write non-compressed data at each rate.[set]
4803 *
4804 * @param ctx read / write interface definitions
4805 * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1,
4806 * @retval interface status (MANDATORY: return 0 -> no Error)
4807 *
4808 */
lsm6dsv16bx_fifo_compress_algo_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_compress_algo_t val)4809 int32_t lsm6dsv16bx_fifo_compress_algo_set(const stmdev_ctx_t *ctx,
4810 lsm6dsv16bx_fifo_compress_algo_t val)
4811 {
4812 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
4813 int32_t ret;
4814
4815 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4816 if (ret == 0)
4817 {
4818 fifo_ctrl2.uncompr_rate = (uint8_t)val & 0x03U;
4819 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4820 }
4821
4822 return ret;
4823 }
4824
4825 /**
4826 * @brief It configures the compression algorithm to write non-compressed data at each rate.[get]
4827 *
4828 * @param ctx read / write interface definitions
4829 * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1,
4830 * @retval interface status (MANDATORY: return 0 -> no Error)
4831 *
4832 */
lsm6dsv16bx_fifo_compress_algo_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_compress_algo_t * val)4833 int32_t lsm6dsv16bx_fifo_compress_algo_get(const stmdev_ctx_t *ctx,
4834 lsm6dsv16bx_fifo_compress_algo_t *val)
4835 {
4836 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
4837 int32_t ret;
4838
4839 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4840
4841 switch (fifo_ctrl2.uncompr_rate)
4842 {
4843 case LSM6DSV16BX_CMP_DISABLE:
4844 *val = LSM6DSV16BX_CMP_DISABLE;
4845 break;
4846
4847 case LSM6DSV16BX_CMP_8_TO_1:
4848 *val = LSM6DSV16BX_CMP_8_TO_1;
4849 break;
4850
4851 case LSM6DSV16BX_CMP_16_TO_1:
4852 *val = LSM6DSV16BX_CMP_16_TO_1;
4853 break;
4854
4855 case LSM6DSV16BX_CMP_32_TO_1:
4856 *val = LSM6DSV16BX_CMP_32_TO_1;
4857 break;
4858
4859 default:
4860 *val = LSM6DSV16BX_CMP_DISABLE;
4861 break;
4862 }
4863 return ret;
4864 }
4865
4866 /**
4867 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
4868 *
4869 * @param ctx read / write interface definitions
4870 * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO.
4871 * @retval interface status (MANDATORY: return 0 -> no Error)
4872 *
4873 */
lsm6dsv16bx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t * ctx,uint8_t val)4874 int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx,
4875 uint8_t val)
4876 {
4877 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
4878 int32_t ret;
4879
4880 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4881 if (ret == 0)
4882 {
4883 fifo_ctrl2.odr_chg_en = val;
4884 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4885 }
4886
4887 return ret;
4888 }
4889
4890 /**
4891 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
4892 *
4893 * @param ctx read / write interface definitions
4894 * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO.
4895 * @retval interface status (MANDATORY: return 0 -> no Error)
4896 *
4897 */
lsm6dsv16bx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t * ctx,uint8_t * val)4898 int32_t lsm6dsv16bx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx,
4899 uint8_t *val)
4900 {
4901 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
4902 int32_t ret;
4903
4904 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4905 *val = fifo_ctrl2.odr_chg_en;
4906
4907 return ret;
4908 }
4909
4910 /**
4911 * @brief Enables/Disables compression algorithm runtime.[set]
4912 *
4913 * @param ctx read / write interface definitions
4914 * @param val Enables/Disables compression algorithm runtime.
4915 * @retval interface status (MANDATORY: return 0 -> no Error)
4916 *
4917 */
lsm6dsv16bx_fifo_compress_algo_real_time_set(const stmdev_ctx_t * ctx,uint8_t val)4918 int32_t lsm6dsv16bx_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx,
4919 uint8_t val)
4920 {
4921 lsm6dsv16bx_emb_func_en_b_t emb_func_en_b;
4922 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
4923
4924 int32_t ret;
4925
4926 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4927 if (ret == 0)
4928 {
4929 fifo_ctrl2.fifo_compr_rt_en = val;
4930 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4931 }
4932
4933 if (ret == 0)
4934 {
4935 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
4936 }
4937 if (ret == 0)
4938 {
4939 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
4940 }
4941 if (ret == 0)
4942 {
4943 emb_func_en_b.fifo_compr_en = val;
4944 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
4945 }
4946
4947 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
4948
4949 return ret;
4950 }
4951
4952 /**
4953 * @brief Enables/Disables compression algorithm runtime.[get]
4954 *
4955 * @param ctx read / write interface definitions
4956 * @param val Enables/Disables compression algorithm runtime.
4957 * @retval interface status (MANDATORY: return 0 -> no Error)
4958 *
4959 */
lsm6dsv16bx_fifo_compress_algo_real_time_get(const stmdev_ctx_t * ctx,uint8_t * val)4960 int32_t lsm6dsv16bx_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx,
4961 uint8_t *val)
4962 {
4963 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
4964 int32_t ret;
4965
4966 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4967
4968 *val = fifo_ctrl2.fifo_compr_rt_en;
4969
4970 return ret;
4971 }
4972
4973 /**
4974 * @brief Sensing chain FIFO stop values memorization at threshold level.[set]
4975 *
4976 * @param ctx read / write interface definitions
4977 * @param val Sensing chain FIFO stop values memorization at threshold level.
4978 * @retval interface status (MANDATORY: return 0 -> no Error)
4979 *
4980 */
lsm6dsv16bx_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)4981 int32_t lsm6dsv16bx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
4982 {
4983 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
4984 int32_t ret;
4985
4986 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4987 if (ret == 0)
4988 {
4989 fifo_ctrl2.stop_on_wtm = val;
4990 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4991 }
4992
4993 return ret;
4994 }
4995
4996 /**
4997 * @brief Sensing chain FIFO stop values memorization at threshold level.[get]
4998 *
4999 * @param ctx read / write interface definitions
5000 * @param val Sensing chain FIFO stop values memorization at threshold level.
5001 * @retval interface status (MANDATORY: return 0 -> no Error)
5002 *
5003 */
lsm6dsv16bx_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)5004 int32_t lsm6dsv16bx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val)
5005 {
5006 lsm6dsv16bx_fifo_ctrl2_t fifo_ctrl2;
5007 int32_t ret;
5008
5009 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
5010 *val = fifo_ctrl2.stop_on_wtm;
5011
5012 return ret;
5013 }
5014
5015 /**
5016 * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[set]
5017 *
5018 * @param ctx read / write interface definitions
5019 * @param val lsm6dsv16bx_fifo_xl_batch_t enum
5020 * @retval interface status (MANDATORY: return 0 -> no Error)
5021 *
5022 */
lsm6dsv16bx_fifo_xl_batch_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_xl_batch_t val)5023 int32_t lsm6dsv16bx_fifo_xl_batch_set(const stmdev_ctx_t *ctx,
5024 lsm6dsv16bx_fifo_xl_batch_t val)
5025 {
5026 lsm6dsv16bx_fifo_ctrl3_t fifo_ctrl3;
5027 int32_t ret;
5028
5029 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
5030 if (ret == 0)
5031 {
5032 fifo_ctrl3.bdr_xl = (uint8_t)val & 0xFU;
5033 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
5034 }
5035
5036 return ret;
5037 }
5038
5039 /**
5040 * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[get]
5041 *
5042 * @param ctx read / write interface definitions
5043 * @param val lsm6dsv16bx_fifo_xl_batch_t enum
5044 * @retval interface status (MANDATORY: return 0 -> no Error)
5045 *
5046 */
lsm6dsv16bx_fifo_xl_batch_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_xl_batch_t * val)5047 int32_t lsm6dsv16bx_fifo_xl_batch_get(const stmdev_ctx_t *ctx,
5048 lsm6dsv16bx_fifo_xl_batch_t *val)
5049 {
5050 lsm6dsv16bx_fifo_ctrl3_t fifo_ctrl3;
5051 int32_t ret;
5052
5053 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
5054 switch (fifo_ctrl3.bdr_xl)
5055 {
5056 case LSM6DSV16BX_XL_NOT_BATCHED:
5057 *val = LSM6DSV16BX_XL_NOT_BATCHED;
5058 break;
5059
5060 case LSM6DSV16BX_XL_BATCHED_AT_1Hz875:
5061 *val = LSM6DSV16BX_XL_BATCHED_AT_1Hz875;
5062 break;
5063
5064 case LSM6DSV16BX_XL_BATCHED_AT_7Hz5:
5065 *val = LSM6DSV16BX_XL_BATCHED_AT_7Hz5;
5066 break;
5067
5068 case LSM6DSV16BX_XL_BATCHED_AT_15Hz:
5069 *val = LSM6DSV16BX_XL_BATCHED_AT_15Hz;
5070 break;
5071
5072 case LSM6DSV16BX_XL_BATCHED_AT_30Hz:
5073 *val = LSM6DSV16BX_XL_BATCHED_AT_30Hz;
5074 break;
5075
5076 case LSM6DSV16BX_XL_BATCHED_AT_60Hz:
5077 *val = LSM6DSV16BX_XL_BATCHED_AT_60Hz;
5078 break;
5079
5080 case LSM6DSV16BX_XL_BATCHED_AT_120Hz:
5081 *val = LSM6DSV16BX_XL_BATCHED_AT_120Hz;
5082 break;
5083
5084 case LSM6DSV16BX_XL_BATCHED_AT_240Hz:
5085 *val = LSM6DSV16BX_XL_BATCHED_AT_240Hz;
5086 break;
5087
5088 case LSM6DSV16BX_XL_BATCHED_AT_480Hz:
5089 *val = LSM6DSV16BX_XL_BATCHED_AT_480Hz;
5090 break;
5091
5092 case LSM6DSV16BX_XL_BATCHED_AT_960Hz:
5093 *val = LSM6DSV16BX_XL_BATCHED_AT_960Hz;
5094 break;
5095
5096 case LSM6DSV16BX_XL_BATCHED_AT_1920Hz:
5097 *val = LSM6DSV16BX_XL_BATCHED_AT_1920Hz;
5098 break;
5099
5100 case LSM6DSV16BX_XL_BATCHED_AT_3840Hz:
5101 *val = LSM6DSV16BX_XL_BATCHED_AT_3840Hz;
5102 break;
5103
5104 case LSM6DSV16BX_XL_BATCHED_AT_7680Hz:
5105 *val = LSM6DSV16BX_XL_BATCHED_AT_7680Hz;
5106 break;
5107
5108 default:
5109 *val = LSM6DSV16BX_XL_NOT_BATCHED;
5110 break;
5111 }
5112 return ret;
5113 }
5114
5115 /**
5116 * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[set]
5117 *
5118 * @param ctx read / write interface definitions
5119 * @param val lsm6dsv16bx_fifo_gy_batch_t enum
5120 * @retval interface status (MANDATORY: return 0 -> no Error)
5121 *
5122 */
lsm6dsv16bx_fifo_gy_batch_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_gy_batch_t val)5123 int32_t lsm6dsv16bx_fifo_gy_batch_set(const stmdev_ctx_t *ctx,
5124 lsm6dsv16bx_fifo_gy_batch_t val)
5125 {
5126 lsm6dsv16bx_fifo_ctrl3_t fifo_ctrl3;
5127 int32_t ret;
5128
5129 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
5130 if (ret == 0)
5131 {
5132 fifo_ctrl3.bdr_gy = (uint8_t)val & 0xFU;
5133 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
5134 }
5135
5136 return ret;
5137 }
5138
5139 /**
5140 * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[get]
5141 *
5142 * @param ctx read / write interface definitions
5143 * @param val lsm6dsv16bx_fifo_gy_batch_t enum
5144 * @retval interface status (MANDATORY: return 0 -> no Error)
5145 *
5146 */
lsm6dsv16bx_fifo_gy_batch_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_gy_batch_t * val)5147 int32_t lsm6dsv16bx_fifo_gy_batch_get(const stmdev_ctx_t *ctx,
5148 lsm6dsv16bx_fifo_gy_batch_t *val)
5149 {
5150 lsm6dsv16bx_fifo_ctrl3_t fifo_ctrl3;
5151 int32_t ret;
5152
5153 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
5154 switch (fifo_ctrl3.bdr_gy)
5155 {
5156 case LSM6DSV16BX_GY_NOT_BATCHED:
5157 *val = LSM6DSV16BX_GY_NOT_BATCHED;
5158 break;
5159
5160 case LSM6DSV16BX_GY_BATCHED_AT_1Hz875:
5161 *val = LSM6DSV16BX_GY_BATCHED_AT_1Hz875;
5162 break;
5163
5164 case LSM6DSV16BX_GY_BATCHED_AT_7Hz5:
5165 *val = LSM6DSV16BX_GY_BATCHED_AT_7Hz5;
5166 break;
5167
5168 case LSM6DSV16BX_GY_BATCHED_AT_15Hz:
5169 *val = LSM6DSV16BX_GY_BATCHED_AT_15Hz;
5170 break;
5171
5172 case LSM6DSV16BX_GY_BATCHED_AT_30Hz:
5173 *val = LSM6DSV16BX_GY_BATCHED_AT_30Hz;
5174 break;
5175
5176 case LSM6DSV16BX_GY_BATCHED_AT_60Hz:
5177 *val = LSM6DSV16BX_GY_BATCHED_AT_60Hz;
5178 break;
5179
5180 case LSM6DSV16BX_GY_BATCHED_AT_120Hz:
5181 *val = LSM6DSV16BX_GY_BATCHED_AT_120Hz;
5182 break;
5183
5184 case LSM6DSV16BX_GY_BATCHED_AT_240Hz:
5185 *val = LSM6DSV16BX_GY_BATCHED_AT_240Hz;
5186 break;
5187
5188 case LSM6DSV16BX_GY_BATCHED_AT_480Hz:
5189 *val = LSM6DSV16BX_GY_BATCHED_AT_480Hz;
5190 break;
5191
5192 case LSM6DSV16BX_GY_BATCHED_AT_960Hz:
5193 *val = LSM6DSV16BX_GY_BATCHED_AT_960Hz;
5194 break;
5195
5196 case LSM6DSV16BX_GY_BATCHED_AT_1920Hz:
5197 *val = LSM6DSV16BX_GY_BATCHED_AT_1920Hz;
5198 break;
5199
5200 case LSM6DSV16BX_GY_BATCHED_AT_3840Hz:
5201 *val = LSM6DSV16BX_GY_BATCHED_AT_3840Hz;
5202 break;
5203
5204 case LSM6DSV16BX_GY_BATCHED_AT_7680Hz:
5205 *val = LSM6DSV16BX_GY_BATCHED_AT_7680Hz;
5206 break;
5207
5208 default:
5209 *val = LSM6DSV16BX_GY_NOT_BATCHED;
5210 break;
5211 }
5212 return ret;
5213 }
5214
5215 /**
5216 * @brief FIFO mode selection.[set]
5217 *
5218 * @param ctx read / write interface definitions
5219 * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
5220 * @retval interface status (MANDATORY: return 0 -> no Error)
5221 *
5222 */
lsm6dsv16bx_fifo_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_mode_t val)5223 int32_t lsm6dsv16bx_fifo_mode_set(const stmdev_ctx_t *ctx,
5224 lsm6dsv16bx_fifo_mode_t val)
5225 {
5226 lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4;
5227 int32_t ret;
5228
5229 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5230 if (ret == 0)
5231 {
5232 fifo_ctrl4.fifo_mode = (uint8_t)val & 0x07U;
5233 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5234 }
5235
5236 return ret;
5237 }
5238
5239 /**
5240 * @brief FIFO mode selection.[get]
5241 *
5242 * @param ctx read / write interface definitions
5243 * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
5244 * @retval interface status (MANDATORY: return 0 -> no Error)
5245 *
5246 */
lsm6dsv16bx_fifo_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_mode_t * val)5247 int32_t lsm6dsv16bx_fifo_mode_get(const stmdev_ctx_t *ctx,
5248 lsm6dsv16bx_fifo_mode_t *val)
5249 {
5250 lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4;
5251 int32_t ret;
5252
5253 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5254 switch (fifo_ctrl4.fifo_mode)
5255 {
5256 case LSM6DSV16BX_BYPASS_MODE:
5257 *val = LSM6DSV16BX_BYPASS_MODE;
5258 break;
5259
5260 case LSM6DSV16BX_FIFO_MODE:
5261 *val = LSM6DSV16BX_FIFO_MODE;
5262 break;
5263
5264 case LSM6DSV16BX_STREAM_WTM_TO_FULL_MODE:
5265 *val = LSM6DSV16BX_STREAM_WTM_TO_FULL_MODE;
5266 break;
5267
5268 case LSM6DSV16BX_STREAM_TO_FIFO_MODE:
5269 *val = LSM6DSV16BX_STREAM_TO_FIFO_MODE;
5270 break;
5271
5272 case LSM6DSV16BX_BYPASS_TO_STREAM_MODE:
5273 *val = LSM6DSV16BX_BYPASS_TO_STREAM_MODE;
5274 break;
5275
5276 case LSM6DSV16BX_STREAM_MODE:
5277 *val = LSM6DSV16BX_STREAM_MODE;
5278 break;
5279
5280 case LSM6DSV16BX_BYPASS_TO_FIFO_MODE:
5281 *val = LSM6DSV16BX_BYPASS_TO_FIFO_MODE;
5282 break;
5283
5284 default:
5285 *val = LSM6DSV16BX_BYPASS_MODE;
5286 break;
5287 }
5288 return ret;
5289 }
5290
5291 /**
5292 * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[set]
5293 *
5294 * @param ctx read / write interface definitions
5295 * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz,
5296 * @retval interface status (MANDATORY: return 0 -> no Error)
5297 *
5298 */
lsm6dsv16bx_fifo_temp_batch_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_temp_batch_t val)5299 int32_t lsm6dsv16bx_fifo_temp_batch_set(const stmdev_ctx_t *ctx,
5300 lsm6dsv16bx_fifo_temp_batch_t val)
5301 {
5302 lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4;
5303 int32_t ret;
5304
5305 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5306 if (ret == 0)
5307 {
5308 fifo_ctrl4.odr_t_batch = (uint8_t)val & 0x03U;
5309 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5310 }
5311
5312 return ret;
5313 }
5314
5315 /**
5316 * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[get]
5317 *
5318 * @param ctx read / write interface definitions
5319 * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz,
5320 * @retval interface status (MANDATORY: return 0 -> no Error)
5321 *
5322 */
lsm6dsv16bx_fifo_temp_batch_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_temp_batch_t * val)5323 int32_t lsm6dsv16bx_fifo_temp_batch_get(const stmdev_ctx_t *ctx,
5324 lsm6dsv16bx_fifo_temp_batch_t *val)
5325 {
5326 lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4;
5327 int32_t ret;
5328
5329 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5330 switch (fifo_ctrl4.odr_t_batch)
5331 {
5332 case LSM6DSV16BX_TEMP_NOT_BATCHED:
5333 *val = LSM6DSV16BX_TEMP_NOT_BATCHED;
5334 break;
5335
5336 case LSM6DSV16BX_TEMP_BATCHED_AT_1Hz875:
5337 *val = LSM6DSV16BX_TEMP_BATCHED_AT_1Hz875;
5338 break;
5339
5340 case LSM6DSV16BX_TEMP_BATCHED_AT_15Hz:
5341 *val = LSM6DSV16BX_TEMP_BATCHED_AT_15Hz;
5342 break;
5343
5344 case LSM6DSV16BX_TEMP_BATCHED_AT_60Hz:
5345 *val = LSM6DSV16BX_TEMP_BATCHED_AT_60Hz;
5346 break;
5347
5348 default:
5349 *val = LSM6DSV16BX_TEMP_NOT_BATCHED;
5350 break;
5351 }
5352 return ret;
5353 }
5354
5355 /**
5356 * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[set]
5357 *
5358 * @param ctx read / write interface definitions
5359 * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32,
5360 * @retval interface status (MANDATORY: return 0 -> no Error)
5361 *
5362 */
lsm6dsv16bx_fifo_timestamp_batch_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_timestamp_batch_t val)5363 int32_t lsm6dsv16bx_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx,
5364 lsm6dsv16bx_fifo_timestamp_batch_t val)
5365 {
5366 lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4;
5367 int32_t ret;
5368
5369 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5370 if (ret == 0)
5371 {
5372 fifo_ctrl4.dec_ts_batch = (uint8_t)val & 0x3U;
5373 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5374 }
5375
5376 return ret;
5377 }
5378
5379 /**
5380 * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[get]
5381 *
5382 * @param ctx read / write interface definitions
5383 * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32,
5384 * @retval interface status (MANDATORY: return 0 -> no Error)
5385 *
5386 */
lsm6dsv16bx_fifo_timestamp_batch_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_timestamp_batch_t * val)5387 int32_t lsm6dsv16bx_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx,
5388 lsm6dsv16bx_fifo_timestamp_batch_t *val)
5389 {
5390 lsm6dsv16bx_fifo_ctrl4_t fifo_ctrl4;
5391 int32_t ret;
5392
5393 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5394 switch (fifo_ctrl4.dec_ts_batch)
5395 {
5396 case LSM6DSV16BX_TMSTMP_NOT_BATCHED:
5397 *val = LSM6DSV16BX_TMSTMP_NOT_BATCHED;
5398 break;
5399
5400 case LSM6DSV16BX_TMSTMP_DEC_1:
5401 *val = LSM6DSV16BX_TMSTMP_DEC_1;
5402 break;
5403
5404 case LSM6DSV16BX_TMSTMP_DEC_8:
5405 *val = LSM6DSV16BX_TMSTMP_DEC_8;
5406 break;
5407
5408 case LSM6DSV16BX_TMSTMP_DEC_32:
5409 *val = LSM6DSV16BX_TMSTMP_DEC_32;
5410 break;
5411
5412 default:
5413 *val = LSM6DSV16BX_TMSTMP_NOT_BATCHED;
5414 break;
5415 }
5416 return ret;
5417 }
5418
5419 /**
5420 * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[set]
5421 *
5422 * @param ctx read / write interface definitions
5423 * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.
5424 * @retval interface status (MANDATORY: return 0 -> no Error)
5425 *
5426 */
lsm6dsv16bx_fifo_batch_counter_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)5427 int32_t lsm6dsv16bx_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx,
5428 uint16_t val)
5429 {
5430 lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1;
5431 lsm6dsv16bx_counter_bdr_reg2_t counter_bdr_reg2;
5432 int32_t ret;
5433
5434 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5435
5436 if (ret == 0)
5437 {
5438 counter_bdr_reg2.cnt_bdr_th = (uint8_t)val & 0xFFU;
5439 counter_bdr_reg1.cnt_bdr_th = (uint8_t)(val >> 8) & 0x3U;
5440 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5441 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1);
5442 }
5443
5444 return ret;
5445 }
5446
5447 /**
5448 * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[get]
5449 *
5450 * @param ctx read / write interface definitions
5451 * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.
5452 * @retval interface status (MANDATORY: return 0 -> no Error)
5453 *
5454 */
lsm6dsv16bx_fifo_batch_counter_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)5455 int32_t lsm6dsv16bx_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx,
5456 uint16_t *val)
5457 {
5458 uint8_t buff[2];
5459 int32_t ret;
5460
5461 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, &buff[0], 2);
5462 *val = (uint16_t)buff[0] & 0x3U;
5463 *val = (*val * 256U) + (uint16_t)buff[1];
5464
5465 return ret;
5466 }
5467
5468 /**
5469 * @brief Enables AH_QVAR batching in FIFO.[set]
5470 *
5471 * @param ctx read / write interface definitions
5472 * @param val Enables AH_QVAR batching in FIFO.
5473 * @retval interface status (MANDATORY: return 0 -> no Error)
5474 *
5475 */
lsm6dsv16bx_fifo_batch_ah_qvar_set(const stmdev_ctx_t * ctx,uint8_t val)5476 int32_t lsm6dsv16bx_fifo_batch_ah_qvar_set(const stmdev_ctx_t *ctx, uint8_t val)
5477 {
5478 lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1;
5479 int32_t ret;
5480
5481 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5482 if (ret == 0)
5483 {
5484 counter_bdr_reg1.ah_qvar_batch_en = val;
5485 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5486 }
5487
5488 return ret;
5489 }
5490
5491 /**
5492 * @brief Enables AH_QVAR batching in FIFO.[get]
5493 *
5494 * @param ctx read / write interface definitions
5495 * @param val Enables AH_QVAR batching in FIFO.
5496 * @retval interface status (MANDATORY: return 0 -> no Error)
5497 *
5498 */
lsm6dsv16bx_fifo_batch_ah_qvar_get(const stmdev_ctx_t * ctx,uint8_t * val)5499 int32_t lsm6dsv16bx_fifo_batch_ah_qvar_get(const stmdev_ctx_t *ctx, uint8_t *val)
5500 {
5501 lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1;
5502 int32_t ret;
5503
5504 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5505 *val = counter_bdr_reg1.ah_qvar_batch_en;
5506
5507 return ret;
5508 }
5509
5510 /**
5511 * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope.[set]
5512 *
5513 * @param ctx read / write interface definitions
5514 * @param val XL_BATCH_EVENT, GY_BATCH_EVENT
5515 * @retval interface status (MANDATORY: return 0 -> no Error)
5516 *
5517 */
lsm6dsv16bx_fifo_batch_cnt_event_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_batch_cnt_event_t val)5518 int32_t lsm6dsv16bx_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx,
5519 lsm6dsv16bx_fifo_batch_cnt_event_t val)
5520 {
5521 lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1;
5522 int32_t ret;
5523
5524 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5525
5526 if (ret == 0)
5527 {
5528 counter_bdr_reg1.trig_counter_bdr = (uint8_t)val & 0x03U;
5529 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5530 }
5531
5532 return ret;
5533 }
5534
5535 /**
5536 * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope.[get]
5537 *
5538 * @param ctx read / write interface definitions
5539 * @param val XL_BATCH_EVENT, GY_BATCH_EVENT
5540 * @retval interface status (MANDATORY: return 0 -> no Error)
5541 *
5542 */
lsm6dsv16bx_fifo_batch_cnt_event_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_batch_cnt_event_t * val)5543 int32_t lsm6dsv16bx_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx,
5544 lsm6dsv16bx_fifo_batch_cnt_event_t *val)
5545 {
5546 lsm6dsv16bx_counter_bdr_reg1_t counter_bdr_reg1;
5547 int32_t ret;
5548
5549 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5550 switch (counter_bdr_reg1.trig_counter_bdr)
5551 {
5552 case LSM6DSV16BX_XL_BATCH_EVENT:
5553 *val = LSM6DSV16BX_XL_BATCH_EVENT;
5554 break;
5555
5556 case LSM6DSV16BX_GY_BATCH_EVENT:
5557 *val = LSM6DSV16BX_GY_BATCH_EVENT;
5558 break;
5559
5560 default:
5561 *val = LSM6DSV16BX_XL_BATCH_EVENT;
5562 break;
5563 }
5564 return ret;
5565 }
5566
5567 /**
5568 * @brief Batching in FIFO buffer of SFLP.[set]
5569 *
5570 * @param ctx read / write interface definitions
5571 * @param val Batching in FIFO buffer of SFLP values.
5572 * @retval interface status (MANDATORY: return 0 -> no Error)
5573 *
5574 */
lsm6dsv16bx_fifo_sflp_batch_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_sflp_raw_t val)5575 int32_t lsm6dsv16bx_fifo_sflp_batch_set(const stmdev_ctx_t *ctx,
5576 lsm6dsv16bx_fifo_sflp_raw_t val)
5577 {
5578 lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5579 int32_t ret;
5580
5581 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
5582 if (ret == 0)
5583 {
5584 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5585 emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation;
5586 emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity;
5587 emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias;
5588 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A,
5589 (uint8_t *)&emb_func_fifo_en_a, 1);
5590 }
5591
5592 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
5593
5594 return ret;
5595 }
5596
5597 /**
5598 * @brief Batching in FIFO buffer of SFLP.[get]
5599 *
5600 * @param ctx read / write interface definitions
5601 * @param val Batching in FIFO buffer of SFLP values.
5602 * @retval interface status (MANDATORY: return 0 -> no Error)
5603 *
5604 */
lsm6dsv16bx_fifo_sflp_batch_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_sflp_raw_t * val)5605 int32_t lsm6dsv16bx_fifo_sflp_batch_get(const stmdev_ctx_t *ctx,
5606 lsm6dsv16bx_fifo_sflp_raw_t *val)
5607 {
5608 lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5609 int32_t ret;
5610
5611 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
5612 if (ret == 0)
5613 {
5614 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5615
5616 val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en;
5617 val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en;
5618 val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en;
5619 }
5620
5621 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
5622
5623 return ret;
5624 }
5625
5626 /**
5627 * @brief Status of FIFO.[get]
5628 *
5629 * @param ctx read / write interface definitions
5630 * @param val Status of FIFO (level and flags).
5631 * @retval interface status (MANDATORY: return 0 -> no Error)
5632 *
5633 */
lsm6dsv16bx_fifo_status_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_status_t * val)5634 int32_t lsm6dsv16bx_fifo_status_get(const stmdev_ctx_t *ctx,
5635 lsm6dsv16bx_fifo_status_t *val)
5636 {
5637 uint8_t buff[2];
5638 lsm6dsv16bx_fifo_status2_t status;
5639 int32_t ret;
5640
5641 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_STATUS1, (uint8_t *)&buff[0], 2);
5642 bytecpy((uint8_t *)&status, &buff[1]);
5643
5644 val->fifo_bdr = status.counter_bdr_ia;
5645 val->fifo_ovr = status.fifo_ovr_ia;
5646 val->fifo_full = status.fifo_full_ia;
5647 val->fifo_th = status.fifo_wtm_ia;
5648
5649 val->fifo_level = (uint16_t)buff[1] & 0x01U;
5650 val->fifo_level = (val->fifo_level * 256U) + buff[0];
5651
5652 return ret;
5653 }
5654
5655 /**
5656 * @brief FIFO data output[get]
5657 *
5658 * @param ctx read / write interface definitions
5659 * @param val lsm6dsv16bx_fifo_out_raw_t enum
5660 * @retval interface status (MANDATORY: return 0 -> no Error)
5661 *
5662 */
lsm6dsv16bx_fifo_out_raw_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_fifo_out_raw_t * val)5663 int32_t lsm6dsv16bx_fifo_out_raw_get(const stmdev_ctx_t *ctx,
5664 lsm6dsv16bx_fifo_out_raw_t *val)
5665 {
5666 lsm6dsv16bx_fifo_data_out_tag_t fifo_data_out_tag;
5667 uint8_t buff[7];
5668 int32_t ret;
5669
5670 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FIFO_DATA_OUT_TAG, buff, 7);
5671 bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]);
5672
5673 switch (fifo_data_out_tag.tag_sensor)
5674 {
5675 case LSM6DSV16BX_FIFO_EMPTY:
5676 val->tag = LSM6DSV16BX_FIFO_EMPTY;
5677 break;
5678
5679 case LSM6DSV16BX_GY_NC_TAG:
5680 val->tag = LSM6DSV16BX_GY_NC_TAG;
5681 break;
5682
5683 case LSM6DSV16BX_XL_NC_TAG:
5684 val->tag = LSM6DSV16BX_XL_NC_TAG;
5685 break;
5686
5687 case LSM6DSV16BX_TIMESTAMP_TAG:
5688 val->tag = LSM6DSV16BX_TIMESTAMP_TAG;
5689 break;
5690
5691 case LSM6DSV16BX_TEMPERATURE_TAG:
5692 val->tag = LSM6DSV16BX_TEMPERATURE_TAG;
5693 break;
5694
5695 case LSM6DSV16BX_CFG_CHANGE_TAG:
5696 val->tag = LSM6DSV16BX_CFG_CHANGE_TAG;
5697 break;
5698
5699 case LSM6DSV16BX_XL_NC_T_2_TAG:
5700 val->tag = LSM6DSV16BX_XL_NC_T_2_TAG;
5701 break;
5702
5703 case LSM6DSV16BX_XL_NC_T_1_TAG:
5704 val->tag = LSM6DSV16BX_XL_NC_T_1_TAG;
5705 break;
5706
5707 case LSM6DSV16BX_XL_2XC_TAG:
5708 val->tag = LSM6DSV16BX_XL_2XC_TAG;
5709 break;
5710
5711 case LSM6DSV16BX_XL_3XC_TAG:
5712 val->tag = LSM6DSV16BX_XL_3XC_TAG;
5713 break;
5714
5715 case LSM6DSV16BX_GY_NC_T_2_TAG:
5716 val->tag = LSM6DSV16BX_GY_NC_T_2_TAG;
5717 break;
5718
5719 case LSM6DSV16BX_GY_NC_T_1_TAG:
5720 val->tag = LSM6DSV16BX_GY_NC_T_1_TAG;
5721 break;
5722
5723 case LSM6DSV16BX_GY_2XC_TAG:
5724 val->tag = LSM6DSV16BX_GY_2XC_TAG;
5725 break;
5726
5727 case LSM6DSV16BX_GY_3XC_TAG:
5728 val->tag = LSM6DSV16BX_GY_3XC_TAG;
5729 break;
5730
5731 case LSM6DSV16BX_STEP_COUNTER_TAG:
5732 val->tag = LSM6DSV16BX_STEP_COUNTER_TAG;
5733 break;
5734
5735 case LSM6DSV16BX_MLC_RESULT_TAG:
5736 val->tag = LSM6DSV16BX_MLC_RESULT_TAG;
5737 break;
5738
5739 case LSM6DSV16BX_SFLP_GAME_ROTATION_VECTOR_TAG:
5740 val->tag = LSM6DSV16BX_SFLP_GAME_ROTATION_VECTOR_TAG;
5741 break;
5742
5743 case LSM6DSV16BX_SFLP_GYROSCOPE_BIAS_TAG:
5744 val->tag = LSM6DSV16BX_SFLP_GYROSCOPE_BIAS_TAG;
5745 break;
5746
5747 case LSM6DSV16BX_SFLP_GRAVITY_VECTOR_TAG:
5748 val->tag = LSM6DSV16BX_SFLP_GRAVITY_VECTOR_TAG;
5749 break;
5750
5751 case LSM6DSV16BX_MLC_FILTER:
5752 val->tag = LSM6DSV16BX_MLC_FILTER;
5753 break;
5754
5755 case LSM6DSV16BX_MLC_FEATURE:
5756 val->tag = LSM6DSV16BX_MLC_FEATURE;
5757 break;
5758
5759 case LSM6DSV16BX_XL_DUAL_CORE:
5760 val->tag = LSM6DSV16BX_XL_DUAL_CORE;
5761 break;
5762
5763 case LSM6DSV16BX_AH_QVAR:
5764 val->tag = LSM6DSV16BX_AH_QVAR;
5765 break;
5766
5767 default:
5768 val->tag = LSM6DSV16BX_FIFO_EMPTY;
5769 break;
5770 }
5771
5772 val->cnt = fifo_data_out_tag.tag_cnt;
5773
5774 val->data[0] = buff[1];
5775 val->data[1] = buff[2];
5776 val->data[2] = buff[3];
5777 val->data[3] = buff[4];
5778 val->data[4] = buff[5];
5779 val->data[5] = buff[6];
5780
5781 return ret;
5782 }
5783
5784 /**
5785 * @brief Batching in FIFO buffer of step counter value.[set]
5786 *
5787 * @param ctx read / write interface definitions
5788 * @param val Batching in FIFO buffer of step counter value.
5789 * @retval interface status (MANDATORY: return 0 -> no Error)
5790 *
5791 */
lsm6dsv16bx_fifo_stpcnt_batch_set(const stmdev_ctx_t * ctx,uint8_t val)5792 int32_t lsm6dsv16bx_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
5793 {
5794 lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5795 int32_t ret;
5796
5797 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
5798 if (ret == 0)
5799 {
5800 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5801 }
5802
5803 if (ret == 0)
5804 {
5805 emb_func_fifo_en_a.step_counter_fifo_en = val;
5806 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5807 }
5808
5809 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
5810
5811 return ret;
5812 }
5813
5814 /**
5815 * @brief Batching in FIFO buffer of step counter value.[get]
5816 *
5817 * @param ctx read / write interface definitions
5818 * @param val Batching in FIFO buffer of step counter value.
5819 * @retval interface status (MANDATORY: return 0 -> no Error)
5820 *
5821 */
lsm6dsv16bx_fifo_stpcnt_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)5822 int32_t lsm6dsv16bx_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
5823 {
5824 lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5825 int32_t ret;
5826
5827 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
5828 if (ret == 0)
5829 {
5830 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5831 }
5832
5833 *val = emb_func_fifo_en_a.step_counter_fifo_en;
5834
5835 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
5836
5837
5838 return ret;
5839 }
5840
5841 /**
5842 * @brief Batching in FIFO buffer of machine learning core results.[set]
5843 *
5844 * @param ctx read / write interface definitions
5845 * @param val Batching in FIFO buffer of machine learning core results.
5846 * @retval interface status (MANDATORY: return 0 -> no Error)
5847 *
5848 */
lsm6dsv16bx_fifo_mlc_batch_set(const stmdev_ctx_t * ctx,uint8_t val)5849 int32_t lsm6dsv16bx_fifo_mlc_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
5850 {
5851 lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5852 int32_t ret;
5853
5854 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
5855 if (ret == 0)
5856 {
5857 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5858 }
5859
5860 if (ret == 0)
5861 {
5862 emb_func_fifo_en_a.mlc_fifo_en = val;
5863 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5864 }
5865
5866 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
5867
5868 return ret;
5869 }
5870
5871 /**
5872 * @brief Batching in FIFO buffer of machine learning core results.[get]
5873 *
5874 * @param ctx read / write interface definitions
5875 * @param val Batching in FIFO buffer of machine learning core results.
5876 * @retval interface status (MANDATORY: return 0 -> no Error)
5877 *
5878 */
lsm6dsv16bx_fifo_mlc_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)5879 int32_t lsm6dsv16bx_fifo_mlc_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
5880 {
5881 lsm6dsv16bx_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5882 int32_t ret;
5883
5884 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
5885 if (ret == 0)
5886 {
5887 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5888 }
5889
5890 *val = emb_func_fifo_en_a.mlc_fifo_en;
5891
5892 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
5893
5894 return ret;
5895 }
5896
5897 /**
5898 * @brief Enables batching in FIFO buffer of machine learning core filters and features.[set]
5899 *
5900 * @param ctx read / write interface definitions
5901 * @param val Enables batching in FIFO buffer of machine learning core filters and features.
5902 * @retval interface status (MANDATORY: return 0 -> no Error)
5903 *
5904 */
lsm6dsv16bx_fifo_mlc_filt_batch_set(const stmdev_ctx_t * ctx,uint8_t val)5905 int32_t lsm6dsv16bx_fifo_mlc_filt_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
5906 {
5907 lsm6dsv16bx_emb_func_fifo_en_b_t emb_func_fifo_en_b;
5908 int32_t ret;
5909
5910 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
5911 if (ret == 0)
5912 {
5913 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1);
5914 }
5915
5916 if (ret == 0)
5917 {
5918 emb_func_fifo_en_b.mlc_filter_feature_fifo_en = val;
5919 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1);
5920 }
5921
5922 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
5923
5924 return ret;
5925 }
5926
5927 /**
5928 * @brief Enables batching in FIFO buffer of machine learning core filters and features.[get]
5929 *
5930 * @param ctx read / write interface definitions
5931 * @param val Enables batching in FIFO buffer of machine learning core filters and features.
5932 * @retval interface status (MANDATORY: return 0 -> no Error)
5933 *
5934 */
lsm6dsv16bx_fifo_mlc_filt_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)5935 int32_t lsm6dsv16bx_fifo_mlc_filt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
5936 {
5937 lsm6dsv16bx_emb_func_fifo_en_b_t emb_func_fifo_en_b;
5938 int32_t ret;
5939
5940 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
5941 if (ret == 0)
5942 {
5943 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_FIFO_EN_B, (uint8_t *)&emb_func_fifo_en_b, 1);
5944 }
5945
5946 *val = emb_func_fifo_en_b.mlc_filter_feature_fifo_en;
5947
5948 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
5949
5950 return ret;
5951 }
5952
5953 /**
5954 * @}
5955 *
5956 */
5957
5958 /**
5959 * @defgroup Step Counter
5960 * @brief This section groups all the functions that manage pedometer.
5961 * @{
5962 *
5963 */
5964
5965 /**
5966 * @brief Step counter mode[set]
5967 *
5968 * @param ctx read / write interface definitions
5969 * @param val false_step_rej, step_counter, step_detector,
5970 * @retval interface status (MANDATORY: return 0 -> no Error)
5971 *
5972 */
lsm6dsv16bx_stpcnt_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_stpcnt_mode_t val)5973 int32_t lsm6dsv16bx_stpcnt_mode_set(const stmdev_ctx_t *ctx,
5974 lsm6dsv16bx_stpcnt_mode_t val)
5975 {
5976 lsm6dsv16bx_emb_func_en_a_t emb_func_en_a;
5977 lsm6dsv16bx_emb_func_en_b_t emb_func_en_b;
5978 lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg;
5979 int32_t ret;
5980
5981 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
5982 if (ret == 0)
5983 {
5984 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
5985 }
5986 if (ret == 0)
5987 {
5988 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
5989 }
5990 if ((val.false_step_rej == PROPERTY_ENABLE)
5991 && ((emb_func_en_a.mlc_before_fsm_en & emb_func_en_b.mlc_en) ==
5992 PROPERTY_DISABLE))
5993 {
5994 emb_func_en_a.mlc_before_fsm_en = PROPERTY_ENABLE;
5995 }
5996 if (ret == 0)
5997 {
5998 emb_func_en_a.pedo_en = val.step_counter_enable;
5999 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6000 }
6001
6002 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6003
6004 if (ret == 0)
6005 {
6006 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
6007 }
6008 if (ret == 0)
6009 {
6010 pedo_cmd_reg.fp_rejection_en = val.false_step_rej;
6011 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
6012 }
6013
6014 return ret;
6015 }
6016
6017 /**
6018 * @brief Step counter mode[get]
6019 *
6020 * @param ctx read / write interface definitions
6021 * @param val false_step_rej, step_counter, step_detector,
6022 * @retval interface status (MANDATORY: return 0 -> no Error)
6023 *
6024 */
lsm6dsv16bx_stpcnt_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_stpcnt_mode_t * val)6025 int32_t lsm6dsv16bx_stpcnt_mode_get(const stmdev_ctx_t *ctx,
6026 lsm6dsv16bx_stpcnt_mode_t *val)
6027 {
6028 lsm6dsv16bx_emb_func_en_a_t emb_func_en_a;
6029 lsm6dsv16bx_pedo_cmd_reg_t pedo_cmd_reg;
6030 int32_t ret;
6031
6032 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6033 if (ret == 0)
6034 {
6035 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6036 }
6037
6038 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6039
6040 if (ret == 0)
6041 {
6042 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
6043 }
6044 val->false_step_rej = pedo_cmd_reg.fp_rejection_en;
6045 val->step_counter_enable = emb_func_en_a.pedo_en;
6046
6047 return ret;
6048 }
6049
6050 /**
6051 * @brief Step counter output, number of detected steps.[get]
6052 *
6053 * @param ctx read / write interface definitions
6054 * @param val Step counter output, number of detected steps.
6055 * @retval interface status (MANDATORY: return 0 -> no Error)
6056 *
6057 */
lsm6dsv16bx_stpcnt_steps_get(const stmdev_ctx_t * ctx,uint16_t * val)6058 int32_t lsm6dsv16bx_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val)
6059 {
6060 uint8_t buff[2];
6061 int32_t ret;
6062
6063 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6064 if (ret == 0)
6065 {
6066 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_STEP_COUNTER_L, &buff[0], 2);
6067 }
6068
6069 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6070
6071 *val = buff[1];
6072 *val = (*val * 256U) + buff[0];
6073
6074 return ret;
6075 }
6076
6077 /**
6078 * @brief Reset step counter.[set]
6079 *
6080 * @param ctx read / write interface definitions
6081 * @param val Reset step counter.
6082 * @retval interface status (MANDATORY: return 0 -> no Error)
6083 *
6084 */
lsm6dsv16bx_stpcnt_rst_step_set(const stmdev_ctx_t * ctx,uint8_t val)6085 int32_t lsm6dsv16bx_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val)
6086 {
6087 lsm6dsv16bx_emb_func_src_t emb_func_src;
6088 int32_t ret;
6089
6090 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6091 if (ret == 0)
6092 {
6093 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
6094 }
6095
6096 if (ret == 0)
6097 {
6098 emb_func_src.pedo_rst_step = val;
6099 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
6100 }
6101
6102 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6103
6104 return ret;
6105 }
6106
6107 /**
6108 * @brief Reset step counter.[get]
6109 *
6110 * @param ctx read / write interface definitions
6111 * @param val Reset step counter.
6112 * @retval interface status (MANDATORY: return 0 -> no Error)
6113 *
6114 */
lsm6dsv16bx_stpcnt_rst_step_get(const stmdev_ctx_t * ctx,uint8_t * val)6115 int32_t lsm6dsv16bx_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val)
6116 {
6117 lsm6dsv16bx_emb_func_src_t emb_func_src;
6118 int32_t ret;
6119
6120 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6121 if (ret == 0)
6122 {
6123 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
6124 }
6125
6126 *val = emb_func_src.pedo_rst_step;
6127
6128 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6129
6130 return ret;
6131 }
6132
6133 /**
6134 * @brief Pedometer debounce configuration.[set]
6135 *
6136 * @param ctx read / write interface definitions
6137 * @param val Pedometer debounce configuration.
6138 * @retval interface status (MANDATORY: return 0 -> no Error)
6139 *
6140 */
lsm6dsv16bx_stpcnt_debounce_set(const stmdev_ctx_t * ctx,uint8_t val)6141 int32_t lsm6dsv16bx_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val)
6142 {
6143 lsm6dsv16bx_pedo_deb_steps_conf_t pedo_deb_steps_conf;
6144 int32_t ret;
6145
6146 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf,
6147 1);
6148 if (ret == 0)
6149 {
6150 pedo_deb_steps_conf.deb_step = val;
6151 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf,
6152 1);
6153 }
6154
6155 return ret;
6156 }
6157
6158 /**
6159 * @brief Pedometer debounce configuration.[get]
6160 *
6161 * @param ctx read / write interface definitions
6162 * @param val Pedometer debounce configuration.
6163 * @retval interface status (MANDATORY: return 0 -> no Error)
6164 *
6165 */
lsm6dsv16bx_stpcnt_debounce_get(const stmdev_ctx_t * ctx,uint8_t * val)6166 int32_t lsm6dsv16bx_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val)
6167 {
6168 lsm6dsv16bx_pedo_deb_steps_conf_t pedo_deb_steps_conf;
6169 int32_t ret;
6170
6171 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf,
6172 1);
6173 *val = pedo_deb_steps_conf.deb_step;
6174
6175 return ret;
6176 }
6177
6178 /**
6179 * @brief Time period register for step detection on delta time.[set]
6180 *
6181 * @param ctx read / write interface definitions
6182 * @param val Time period register for step detection on delta time.
6183 * @retval interface status (MANDATORY: return 0 -> no Error)
6184 *
6185 */
lsm6dsv16bx_stpcnt_period_set(const stmdev_ctx_t * ctx,uint16_t val)6186 int32_t lsm6dsv16bx_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val)
6187 {
6188 uint8_t buff[2];
6189 int32_t ret;
6190
6191 buff[1] = (uint8_t)(val / 256U);
6192 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6193
6194 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_PEDO_SC_DELTAT_L, (uint8_t *)&buff[0], 2);
6195
6196 return ret;
6197 }
6198
6199 /**
6200 * @brief Time period register for step detection on delta time.[get]
6201 *
6202 * @param ctx read / write interface definitions
6203 * @param val Time period register for step detection on delta time.
6204 * @retval interface status (MANDATORY: return 0 -> no Error)
6205 *
6206 */
lsm6dsv16bx_stpcnt_period_get(const stmdev_ctx_t * ctx,uint16_t * val)6207 int32_t lsm6dsv16bx_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val)
6208 {
6209 uint8_t buff[2];
6210 int32_t ret;
6211
6212 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_PEDO_SC_DELTAT_L, &buff[0], 2);
6213 *val = buff[1];
6214 *val = (*val * 256U) + buff[0];
6215
6216 return ret;
6217 }
6218
6219 /**
6220 * @}
6221 *
6222 */
6223
6224 /**
6225 * @defgroup Significant motion
6226 * @brief This section groups all the functions that manage the
6227 * significant motion detection.
6228 * @{
6229 *
6230 */
6231
6232 /**
6233 * @brief Enables significant motion detection function.[set]
6234 *
6235 * @param ctx read / write interface definitions
6236 * @param val Enables significant motion detection function.
6237 * @retval interface status (MANDATORY: return 0 -> no Error)
6238 *
6239 */
lsm6dsv16bx_sigmot_mode_set(const stmdev_ctx_t * ctx,uint8_t val)6240 int32_t lsm6dsv16bx_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
6241 {
6242 lsm6dsv16bx_emb_func_en_a_t emb_func_en_a;
6243 int32_t ret;
6244
6245 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6246 if (ret == 0)
6247 {
6248 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6249 }
6250 if (ret == 0)
6251 {
6252 emb_func_en_a.sign_motion_en = val;
6253 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6254 }
6255
6256 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6257
6258
6259 return ret;
6260 }
6261
6262 /**
6263 * @brief Enables significant motion detection function.[get]
6264 *
6265 * @param ctx read / write interface definitions
6266 * @param val Enables significant motion detection function.
6267 * @retval interface status (MANDATORY: return 0 -> no Error)
6268 *
6269 */
lsm6dsv16bx_sigmot_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)6270 int32_t lsm6dsv16bx_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
6271 {
6272 lsm6dsv16bx_emb_func_en_a_t emb_func_en_a;
6273 int32_t ret;
6274
6275 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6276 if (ret == 0)
6277 {
6278 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6279 }
6280 *val = emb_func_en_a.sign_motion_en;
6281
6282 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6283
6284
6285 return ret;
6286 }
6287
6288 /**
6289 * @}
6290 *
6291 */
6292
6293 /**
6294 * @defgroup Tilt detection
6295 * @brief This section groups all the functions that manage the tilt
6296 * event detection.
6297 * @{
6298 *
6299 */
6300
6301 /**
6302 * @brief Tilt calculation.[set]
6303 *
6304 * @param ctx read / write interface definitions
6305 * @param val Tilt calculation.
6306 * @retval interface status (MANDATORY: return 0 -> no Error)
6307 *
6308 */
lsm6dsv16bx_tilt_mode_set(const stmdev_ctx_t * ctx,uint8_t val)6309 int32_t lsm6dsv16bx_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
6310 {
6311 lsm6dsv16bx_emb_func_en_a_t emb_func_en_a;
6312 int32_t ret;
6313
6314 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6315 if (ret == 0)
6316 {
6317 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6318 }
6319 if (ret == 0)
6320 {
6321 emb_func_en_a.tilt_en = val;
6322 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6323 }
6324
6325 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6326
6327 return ret;
6328 }
6329
6330 /**
6331 * @brief Tilt calculation.[get]
6332 *
6333 * @param ctx read / write interface definitions
6334 * @param val Tilt calculation.
6335 * @retval interface status (MANDATORY: return 0 -> no Error)
6336 *
6337 */
lsm6dsv16bx_tilt_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)6338 int32_t lsm6dsv16bx_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
6339 {
6340 lsm6dsv16bx_emb_func_en_a_t emb_func_en_a;
6341 int32_t ret;
6342
6343 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6344 if (ret == 0)
6345 {
6346 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6347 }
6348 *val = emb_func_en_a.tilt_en;
6349
6350 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6351
6352 return ret;
6353 }
6354
6355 /**
6356 * @}
6357 *
6358 */
6359
6360 /**
6361 * @defgroup Sensor Fusion Low Power (SFLP)
6362 * @brief This section groups all the functions that manage pedometer.
6363 * @{
6364 *
6365 */
6366
6367 /**
6368 * @brief Enable SFLP Game Rotation Vector (6x).[set]
6369 *
6370 * @param ctx read / write interface definitions
6371 * @param val Enable/Disable game rotation value (0/1).
6372 * @retval interface status (MANDATORY: return 0 -> no Error)
6373 *
6374 */
lsm6dsv16bx_sflp_game_rotation_set(const stmdev_ctx_t * ctx,uint16_t val)6375 int32_t lsm6dsv16bx_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint16_t val)
6376 {
6377 lsm6dsv16bx_emb_func_en_a_t emb_func_en_a;
6378 int32_t ret;
6379
6380 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6381 if (ret == 0)
6382 {
6383 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6384 emb_func_en_a.sflp_game_en = val;
6385 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A,
6386 (uint8_t *)&emb_func_en_a, 1);
6387 }
6388
6389 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6390
6391 return ret;
6392 }
6393
6394 /**
6395 * @brief Enable SFLP Game Rotation Vector (6x).[get]
6396 *
6397 * @param ctx read / write interface definitions
6398 * @param val Enable/Disable game rotation value (0/1).
6399 * @retval interface status (MANDATORY: return 0 -> no Error)
6400 *
6401 */
lsm6dsv16bx_sflp_game_rotation_get(const stmdev_ctx_t * ctx,uint16_t * val)6402 int32_t lsm6dsv16bx_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint16_t *val)
6403 {
6404 lsm6dsv16bx_emb_func_en_a_t emb_func_en_a;
6405 int32_t ret;
6406
6407 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6408 if (ret == 0)
6409 {
6410 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6411 *val = emb_func_en_a.sflp_game_en;
6412 }
6413
6414 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6415
6416 return ret;
6417 }
6418
6419 /**
6420 * @brief SFLP Data Rate (ODR) configuration.[set]
6421 *
6422 * @param ctx read / write interface definitions
6423 * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz
6424 * @retval interface status (MANDATORY: return 0 -> no Error)
6425 *
6426 */
lsm6dsv16bx_sflp_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_sflp_data_rate_t val)6427 int32_t lsm6dsv16bx_sflp_data_rate_set(const stmdev_ctx_t *ctx,
6428 lsm6dsv16bx_sflp_data_rate_t val)
6429 {
6430 lsm6dsv16bx_sflp_odr_t sflp_odr;
6431 int32_t ret;
6432
6433 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6434 if (ret == 0)
6435 {
6436 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
6437 sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U;
6438 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_SFLP_ODR, (uint8_t *)&sflp_odr,
6439 1);
6440 }
6441
6442 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6443
6444 return ret;
6445 }
6446
6447 /**
6448 * @brief SFLP Data Rate (ODR) configuration.[get]
6449 *
6450 * @param ctx read / write interface definitions
6451 * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz
6452 * @retval interface status (MANDATORY: return 0 -> no Error)
6453 *
6454 */
lsm6dsv16bx_sflp_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_sflp_data_rate_t * val)6455 int32_t lsm6dsv16bx_sflp_data_rate_get(const stmdev_ctx_t *ctx,
6456 lsm6dsv16bx_sflp_data_rate_t *val)
6457 {
6458 lsm6dsv16bx_sflp_odr_t sflp_odr;
6459 int32_t ret;
6460
6461 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6462 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
6463 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6464
6465 switch (sflp_odr.sflp_game_odr)
6466 {
6467 case LSM6DSV16BX_SFLP_15Hz:
6468 *val = LSM6DSV16BX_SFLP_15Hz;
6469 break;
6470
6471 case LSM6DSV16BX_SFLP_30Hz:
6472 *val = LSM6DSV16BX_SFLP_30Hz;
6473 break;
6474
6475 case LSM6DSV16BX_SFLP_60Hz:
6476 *val = LSM6DSV16BX_SFLP_60Hz;
6477 break;
6478
6479 case LSM6DSV16BX_SFLP_120Hz:
6480 *val = LSM6DSV16BX_SFLP_120Hz;
6481 break;
6482
6483 case LSM6DSV16BX_SFLP_240Hz:
6484 *val = LSM6DSV16BX_SFLP_240Hz;
6485 break;
6486
6487 case LSM6DSV16BX_SFLP_480Hz:
6488 *val = LSM6DSV16BX_SFLP_480Hz;
6489 break;
6490
6491 default:
6492 *val = LSM6DSV16BX_SFLP_15Hz;
6493 break;
6494 }
6495 return ret;
6496 }
6497
6498 /*
6499 * Original conversion routines taken from: https://github.com/numpy/numpy
6500 *
6501 * uint16_t npy_floatbits_to_halfbits(uint32_t f);
6502 * uint16_t npy_float_to_half(float_t f);
6503 *
6504 * Released under BSD-3-Clause License
6505 */
6506
6507 #define NPY_HALF_GENERATE_OVERFLOW 0 /* do not trigger FP overflow */
6508 #define NPY_HALF_GENERATE_UNDERFLOW 0 /* do not trigger FP underflow */
6509 #ifndef NPY_HALF_ROUND_TIES_TO_EVEN
6510 #define NPY_HALF_ROUND_TIES_TO_EVEN 1
6511 #endif
6512
npy_floatbits_to_halfbits(uint32_t f)6513 static uint16_t npy_floatbits_to_halfbits(uint32_t f)
6514 {
6515 uint32_t f_exp, f_sig;
6516 uint16_t h_sgn, h_exp, h_sig;
6517
6518 h_sgn = (uint16_t)((f & 0x80000000u) >> 16);
6519 f_exp = (f & 0x7f800000u);
6520
6521 /* Exponent overflow/NaN converts to signed inf/NaN */
6522 if (f_exp >= 0x47800000u)
6523 {
6524 if (f_exp == 0x7f800000u)
6525 {
6526 /* Inf or NaN */
6527 f_sig = (f & 0x007fffffu);
6528 if (f_sig != 0)
6529 {
6530 /* NaN - propagate the flag in the significand... */
6531 uint16_t ret = (uint16_t)(0x7c00u + (f_sig >> 13));
6532 /* ...but make sure it stays a NaN */
6533 if (ret == 0x7c00u)
6534 {
6535 ret++;
6536 }
6537 return h_sgn + ret;
6538 }
6539 else
6540 {
6541 /* signed inf */
6542 return (uint16_t)(h_sgn + 0x7c00u);
6543 }
6544 }
6545 else
6546 {
6547 /* overflow to signed inf */
6548 #if NPY_HALF_GENERATE_OVERFLOW
6549 npy_set_floatstatus_overflow();
6550 #endif
6551 return (uint16_t)(h_sgn + 0x7c00u);
6552 }
6553 }
6554
6555 /* Exponent underflow converts to a subnormal half or signed zero */
6556 if (f_exp <= 0x38000000u)
6557 {
6558 /*
6559 * Signed zeros, subnormal floats, and floats with small
6560 * exponents all convert to signed zero half-floats.
6561 */
6562 if (f_exp < 0x33000000u)
6563 {
6564 #if NPY_HALF_GENERATE_UNDERFLOW
6565 /* If f != 0, it underflowed to 0 */
6566 if ((f & 0x7fffffff) != 0)
6567 {
6568 npy_set_floatstatus_underflow();
6569 }
6570 #endif
6571 return h_sgn;
6572 }
6573 /* Make the subnormal significand */
6574 f_exp >>= 23;
6575 f_sig = (0x00800000u + (f & 0x007fffffu));
6576 #if NPY_HALF_GENERATE_UNDERFLOW
6577 /* If it's not exactly represented, it underflowed */
6578 if ((f_sig & (((uint32_t)1 << (126 - f_exp)) - 1)) != 0)
6579 {
6580 npy_set_floatstatus_underflow();
6581 }
6582 #endif
6583 /*
6584 * Usually the significand is shifted by 13. For subnormals an
6585 * additional shift needs to occur. This shift is one for the largest
6586 * exponent giving a subnormal `f_exp = 0x38000000 >> 23 = 112`, which
6587 * offsets the new first bit. At most the shift can be 1+10 bits.
6588 */
6589 f_sig >>= (113 - f_exp);
6590 /* Handle rounding by adding 1 to the bit beyond half precision */
6591 #if NPY_HALF_ROUND_TIES_TO_EVEN
6592 /*
6593 * If the last bit in the half significand is 0 (already even), and
6594 * the remaining bit pattern is 1000...0, then we do not add one
6595 * to the bit after the half significand. However, the (113 - f_exp)
6596 * shift can lose up to 11 bits, so the || checks them in the original.
6597 * In all other cases, we can just add one.
6598 */
6599 if (((f_sig & 0x00003fffu) != 0x00001000u) || (f & 0x000007ffu))
6600 {
6601 f_sig += 0x00001000u;
6602 }
6603 #else
6604 f_sig += 0x00001000u;
6605 #endif
6606 h_sig = (uint16_t)(f_sig >> 13);
6607 /*
6608 * If the rounding causes a bit to spill into h_exp, it will
6609 * increment h_exp from zero to one and h_sig will be zero.
6610 * This is the correct result.
6611 */
6612 return (uint16_t)(h_sgn + h_sig);
6613 }
6614
6615 /* Regular case with no overflow or underflow */
6616 h_exp = (uint16_t)((f_exp - 0x38000000u) >> 13);
6617 /* Handle rounding by adding 1 to the bit beyond half precision */
6618 f_sig = (f & 0x007fffffu);
6619 #if NPY_HALF_ROUND_TIES_TO_EVEN
6620 /*
6621 * If the last bit in the half significand is 0 (already even), and
6622 * the remaining bit pattern is 1000...0, then we do not add one
6623 * to the bit after the half significand. In all other cases, we do.
6624 */
6625 if ((f_sig & 0x00003fffu) != 0x00001000u)
6626 {
6627 f_sig += 0x00001000u;
6628 }
6629 #else
6630 f_sig += 0x00001000u;
6631 #endif
6632 h_sig = (uint16_t)(f_sig >> 13);
6633 /*
6634 * If the rounding causes a bit to spill into h_exp, it will
6635 * increment h_exp by one and h_sig will be zero. This is the
6636 * correct result. h_exp may increment to 15, at greatest, in
6637 * which case the result overflows to a signed inf.
6638 */
6639 #if NPY_HALF_GENERATE_OVERFLOW
6640 h_sig += h_exp;
6641 if (h_sig == 0x7c00u)
6642 {
6643 npy_set_floatstatus_overflow();
6644 }
6645 return h_sgn + h_sig;
6646 #else
6647 return h_sgn + h_exp + h_sig;
6648 #endif
6649 }
6650
npy_float_to_half(float_t f)6651 static uint16_t npy_float_to_half(float_t f)
6652 {
6653 union
6654 {
6655 float_t f;
6656 uint32_t fbits;
6657 } conv;
6658 conv.f = f;
6659 return npy_floatbits_to_halfbits(conv.fbits);
6660 }
6661
6662 /**
6663 * @brief SFLP GBIAS value. The register value is expressed as half-precision
6664 * floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent
6665 * bits; F: 10 fraction bits).[set]
6666 *
6667 * @param ctx read / write interface definitions
6668 * @param val GBIAS x/y/z val.
6669 * @retval interface status (MANDATORY: return 0 -> no Error)
6670 *
6671 */
lsm6dsv16bx_sflp_game_gbias_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_sflp_gbias_t * val)6672 int32_t lsm6dsv16bx_sflp_game_gbias_set(const stmdev_ctx_t *ctx,
6673 lsm6dsv16bx_sflp_gbias_t *val)
6674 {
6675 lsm6dsv16bx_sflp_data_rate_t sflp_odr;
6676 lsm6dsv16bx_emb_func_exec_status_t emb_func_sts;
6677 lsm6dsv16bx_data_ready_t drdy;
6678 lsm6dsv16bx_xl_full_scale_t xl_fs;
6679 lsm6dsv16bx_ctrl10_t ctrl10;
6680 uint8_t master_config;
6681 uint8_t emb_func_en_saved[2];
6682 uint8_t conf_saved[2];
6683 uint8_t reg_zero[2] = {0x0, 0x0};
6684 uint16_t gbias_hf[3];
6685 float_t k = 0.005f;
6686 int16_t xl_data[3];
6687 int32_t data_tmp;
6688 uint8_t *data_ptr = (uint8_t *)&data_tmp;
6689 uint8_t i, j;
6690 int32_t ret;
6691
6692 ret = lsm6dsv16bx_sflp_data_rate_get(ctx, &sflp_odr);
6693 if (ret != 0)
6694 {
6695 return ret;
6696 }
6697
6698 /* Calculate k factor */
6699 switch (sflp_odr)
6700 {
6701 case LSM6DSV16BX_SFLP_15Hz:
6702 k = 0.04f;
6703 break;
6704 case LSM6DSV16BX_SFLP_30Hz:
6705 k = 0.02f;
6706 break;
6707 case LSM6DSV16BX_SFLP_60Hz:
6708 k = 0.01f;
6709 break;
6710 case LSM6DSV16BX_SFLP_120Hz:
6711 k = 0.005f;
6712 break;
6713 case LSM6DSV16BX_SFLP_240Hz:
6714 k = 0.0025f;
6715 break;
6716 case LSM6DSV16BX_SFLP_480Hz:
6717 k = 0.00125f;
6718 break;
6719 }
6720
6721 /* compute gbias as half precision float in order to be put in embedded advanced feature register */
6722 gbias_hf[0] = npy_float_to_half(val->gbias_x * (3.14159265358979323846f / 180.0f) / k);
6723 gbias_hf[1] = npy_float_to_half(val->gbias_y * (3.14159265358979323846f / 180.0f) / k);
6724 gbias_hf[2] = npy_float_to_half(val->gbias_z * (3.14159265358979323846f / 180.0f) / k);
6725
6726 /* Save sensor configuration and set high-performance mode (if the sensor is in power-down mode, turn it on) */
6727 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL1, conf_saved, 2);
6728 ret += lsm6dsv16bx_xl_mode_set(ctx, LSM6DSV16BX_XL_HIGH_PERFORMANCE_MD);
6729 ret += lsm6dsv16bx_gy_mode_set(ctx, LSM6DSV16BX_GY_HIGH_PERFORMANCE_MD);
6730 if ((conf_saved[0] & 0x0FU) == LSM6DSV16BX_XL_ODR_OFF)
6731 {
6732 ret += lsm6dsv16bx_xl_data_rate_set(ctx, LSM6DSV16BX_XL_ODR_AT_120Hz);
6733 }
6734
6735 /* disable algos */
6736 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6737 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, emb_func_en_saved,
6738 2);
6739 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, reg_zero, 2);
6740 do
6741 {
6742 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EXEC_STATUS,
6743 (uint8_t *)&emb_func_sts, 1);
6744 } while (emb_func_sts.emb_func_endop != 1);
6745 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6746
6747 // enable gbias setting
6748 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
6749 ctrl10.emb_func_debug = 1;
6750 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
6751
6752 /* enable algos */
6753 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6754 emb_func_en_saved[0] |= 0x02; /* force SFLP GAME en */
6755 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, emb_func_en_saved,
6756 2);
6757 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6758
6759 ret += lsm6dsv16bx_xl_full_scale_get(ctx, &xl_fs);
6760
6761 /* Read XL data */
6762 do
6763 {
6764 ret += lsm6dsv16bx_flag_data_ready_get(ctx, &drdy);
6765 } while (drdy.drdy_xl != 1);
6766 ret += lsm6dsv16bx_acceleration_raw_get(ctx, xl_data);
6767
6768 /* force sflp initialization */
6769 master_config = 0x40;
6770 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, &master_config,
6771 1);
6772 for (i = 0; i < 3; i++)
6773 {
6774 j = 0;
6775 data_tmp = (int32_t)xl_data[i];
6776 data_tmp <<= xl_fs; // shift based on current fs
6777 ret += lsm6dsv16bx_write_reg(ctx, 0x02 + 3 * i, &data_ptr[j++], 1);
6778 ret += lsm6dsv16bx_write_reg(ctx, 0x03 + 3 * i, &data_ptr[j++], 1);
6779 ret += lsm6dsv16bx_write_reg(ctx, 0x04 + 3 * i, &data_ptr[j], 1);
6780 }
6781 for (i = 0; i < 3; i++)
6782 {
6783 j = 0;
6784 data_tmp = 0;
6785 ret += lsm6dsv16bx_write_reg(ctx, 0x0B + 3 * i, &data_ptr[j++], 1);
6786 ret += lsm6dsv16bx_write_reg(ctx, 0x0C + 3 * i, &data_ptr[j++], 1);
6787 ret += lsm6dsv16bx_write_reg(ctx, 0x0D + 3 * i, &data_ptr[j], 1);
6788 }
6789 master_config = 0x00;
6790 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, &master_config,
6791 1);
6792
6793 // wait end_op (and at least 30 us)
6794 ctx->mdelay(1);
6795 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6796 do
6797 {
6798 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EXEC_STATUS,
6799 (uint8_t *)&emb_func_sts, 1);
6800 } while (emb_func_sts.emb_func_endop != 1);
6801 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6802
6803 /* write gbias in embedded advanced features registers */
6804 ret += lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_SFLP_GAME_GBIASX_L,
6805 (uint8_t *)gbias_hf, 6);
6806
6807 /* reload previous sensor configuration */
6808 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL1, conf_saved, 2);
6809
6810 // disable gbias setting
6811 ctrl10.emb_func_debug = 0;
6812 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
6813
6814 return ret;
6815 }
6816
6817 /**
6818 * @brief SFLP initial configuration [set]
6819 *
6820 * @param ctx read / write interface definitions
6821 * @retval interface status (MANDATORY: return 0 -> no Error)
6822 *
6823 */
lsm6dsv16bx_sflp_configure(const stmdev_ctx_t * ctx)6824 int32_t lsm6dsv16bx_sflp_configure(const stmdev_ctx_t *ctx)
6825 {
6826 uint8_t val = 0x50;
6827 int32_t ret;
6828
6829 ret = lsm6dsv16bx_ln_pg_write(ctx, 0xD2, &val, 1);
6830
6831 return ret;
6832 }
6833
6834 /**
6835 * @}
6836 *
6837 */
6838
6839 /**
6840 * @defgroup Finite State Machine (FSM)
6841 * @brief This section groups all the functions that manage the
6842 * state_machine.
6843 * @{
6844 *
6845 */
6846
6847 /**
6848 * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[set]
6849 *
6850 * @param ctx read / write interface definitions
6851 * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG,
6852 * @retval interface status (MANDATORY: return 0 -> no Error)
6853 *
6854 */
lsm6dsv16bx_fsm_permission_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_fsm_permission_t val)6855 int32_t lsm6dsv16bx_fsm_permission_set(const stmdev_ctx_t *ctx,
6856 lsm6dsv16bx_fsm_permission_t val)
6857 {
6858 lsm6dsv16bx_func_cfg_access_t func_cfg_access;
6859 int32_t ret;
6860
6861 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
6862 if (ret == 0)
6863 {
6864 func_cfg_access.fsm_wr_ctrl_en = (uint8_t)val & 0x01U;
6865 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
6866 }
6867
6868 return ret;
6869 }
6870
6871 /**
6872 * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[get]
6873 *
6874 * @param ctx read / write interface definitions
6875 * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG,
6876 * @retval interface status (MANDATORY: return 0 -> no Error)
6877 *
6878 */
lsm6dsv16bx_fsm_permission_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_fsm_permission_t * val)6879 int32_t lsm6dsv16bx_fsm_permission_get(const stmdev_ctx_t *ctx,
6880 lsm6dsv16bx_fsm_permission_t *val)
6881 {
6882 lsm6dsv16bx_func_cfg_access_t func_cfg_access;
6883 int32_t ret;
6884
6885 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
6886 switch (func_cfg_access.fsm_wr_ctrl_en)
6887 {
6888 case LSM6DSV16BX_PROTECT_CTRL_REGS:
6889 *val = LSM6DSV16BX_PROTECT_CTRL_REGS;
6890 break;
6891
6892 case LSM6DSV16BX_WRITE_CTRL_REG:
6893 *val = LSM6DSV16BX_WRITE_CTRL_REG;
6894 break;
6895
6896 default:
6897 *val = LSM6DSV16BX_PROTECT_CTRL_REGS;
6898 break;
6899 }
6900 return ret;
6901 }
6902
6903 /**
6904 * @brief Return the status of the CTRL registers permission (standard interface vs FSM).[get]
6905 *
6906 * @param ctx read / write interface definitions
6907 * @param val 0: all FSM regs are under std_if control, 1: some regs are under FSM control.
6908 * @retval interface status (MANDATORY: return 0 -> no Error)
6909 *
6910 */
lsm6dsv16bx_fsm_permission_status(const stmdev_ctx_t * ctx,lsm6dsv16bx_fsm_permission_status_t * val)6911 int32_t lsm6dsv16bx_fsm_permission_status(const stmdev_ctx_t *ctx,
6912 lsm6dsv16bx_fsm_permission_status_t *val)
6913 {
6914 lsm6dsv16bx_ctrl_status_t status;
6915 int32_t ret;
6916
6917 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL_STATUS, (uint8_t *)&status, 1);
6918 *val = (status.fsm_wr_ctrl_status == 0) ? LSM6DSV16BX_STD_IF_CONTROL : LSM6DSV16BX_FSM_CONTROL;
6919
6920 return ret;
6921 }
6922
6923 /**
6924 * @brief Enable Finite State Machine (FSM) feature.[set]
6925 *
6926 * @param ctx read / write interface definitions
6927 * @param val Enable Finite State Machine (FSM) feature.
6928 * @retval interface status (MANDATORY: return 0 -> no Error)
6929 *
6930 */
lsm6dsv16bx_fsm_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_fsm_mode_t val)6931 int32_t lsm6dsv16bx_fsm_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_mode_t val)
6932 {
6933 lsm6dsv16bx_emb_func_en_b_t emb_func_en_b;
6934 lsm6dsv16bx_fsm_enable_t fsm_enable;
6935 int32_t ret;
6936
6937 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6938 if (ret == 0)
6939 {
6940 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
6941 }
6942 if (ret == 0)
6943 {
6944 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
6945 }
6946 if ((val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en
6947 | val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en) == PROPERTY_ENABLE)
6948 {
6949 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
6950 }
6951 else
6952 {
6953 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
6954 }
6955 if (ret == 0)
6956 {
6957 fsm_enable.fsm1_en = val.fsm1_en;
6958 fsm_enable.fsm2_en = val.fsm2_en;
6959 fsm_enable.fsm3_en = val.fsm3_en;
6960 fsm_enable.fsm4_en = val.fsm4_en;
6961 fsm_enable.fsm5_en = val.fsm5_en;
6962 fsm_enable.fsm6_en = val.fsm6_en;
6963 fsm_enable.fsm7_en = val.fsm7_en;
6964 fsm_enable.fsm8_en = val.fsm8_en;
6965 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
6966 }
6967 if (ret == 0)
6968 {
6969 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
6970 }
6971
6972 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6973
6974 return ret;
6975 }
6976
6977 /**
6978 * @brief Enable Finite State Machine (FSM) feature.[get]
6979 *
6980 * @param ctx read / write interface definitions
6981 * @param val Enable Finite State Machine (FSM) feature.
6982 * @retval interface status (MANDATORY: return 0 -> no Error)
6983 *
6984 */
lsm6dsv16bx_fsm_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_fsm_mode_t * val)6985 int32_t lsm6dsv16bx_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_mode_t *val)
6986 {
6987 lsm6dsv16bx_fsm_enable_t fsm_enable;
6988 int32_t ret;
6989
6990 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
6991 if (ret == 0)
6992 {
6993 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
6994 }
6995
6996 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
6997
6998 val->fsm1_en = fsm_enable.fsm1_en;
6999 val->fsm2_en = fsm_enable.fsm2_en;
7000 val->fsm3_en = fsm_enable.fsm3_en;
7001 val->fsm4_en = fsm_enable.fsm4_en;
7002 val->fsm5_en = fsm_enable.fsm5_en;
7003 val->fsm6_en = fsm_enable.fsm6_en;
7004 val->fsm7_en = fsm_enable.fsm7_en;
7005 val->fsm8_en = fsm_enable.fsm8_en;
7006
7007 return ret;
7008 }
7009
7010 /**
7011 * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[set]
7012 *
7013 * @param ctx read / write interface definitions
7014 * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).
7015 * @retval interface status (MANDATORY: return 0 -> no Error)
7016 *
7017 */
lsm6dsv16bx_fsm_long_cnt_set(const stmdev_ctx_t * ctx,uint16_t val)7018 int32_t lsm6dsv16bx_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val)
7019 {
7020 uint8_t buff[2];
7021 int32_t ret;
7022
7023 buff[1] = (uint8_t)(val / 256U);
7024 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7025
7026 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7027 if (ret == 0)
7028 {
7029 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2);
7030 }
7031
7032 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7033
7034 return ret;
7035 }
7036
7037 /**
7038 * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[get]
7039 *
7040 * @param ctx read / write interface definitions
7041 * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).
7042 * @retval interface status (MANDATORY: return 0 -> no Error)
7043 *
7044 */
lsm6dsv16bx_fsm_long_cnt_get(const stmdev_ctx_t * ctx,uint16_t * val)7045 int32_t lsm6dsv16bx_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val)
7046 {
7047 uint8_t buff[2];
7048 int32_t ret;
7049
7050 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7051 if (ret == 0)
7052 {
7053 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_LONG_COUNTER_L, &buff[0], 2);
7054 }
7055
7056 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7057
7058 *val = buff[1];
7059 *val = (*val * 256U) + buff[0];
7060
7061 return ret;
7062 }
7063
7064 /**
7065 * @brief FSM output registers[get]
7066 *
7067 * @param ctx read / write interface definitions
7068 * @param val FSM output registers
7069 * @retval interface status (MANDATORY: return 0 -> no Error)
7070 *
7071 */
lsm6dsv16bx_fsm_out_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_fsm_out_t * val)7072 int32_t lsm6dsv16bx_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_fsm_out_t *val)
7073 {
7074 int32_t ret;
7075
7076 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7077 if (ret == 0)
7078 {
7079 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_OUTS1, (uint8_t *)val, 8);
7080 }
7081
7082 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7083
7084 return ret;
7085 }
7086
7087 /**
7088 * @brief Finite State Machine Output Data Rate (ODR) configuration.[set]
7089 *
7090 * @param ctx read / write interface definitions
7091 * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz,
7092 * @retval interface status (MANDATORY: return 0 -> no Error)
7093 *
7094 */
lsm6dsv16bx_fsm_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_fsm_data_rate_t val)7095 int32_t lsm6dsv16bx_fsm_data_rate_set(const stmdev_ctx_t *ctx,
7096 lsm6dsv16bx_fsm_data_rate_t val)
7097 {
7098 lsm6dsv16bx_fsm_odr_t fsm_odr;
7099 int32_t ret;
7100
7101 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7102 if (ret == 0)
7103 {
7104 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_ODR, (uint8_t *)&fsm_odr, 1);
7105 }
7106
7107 if (ret == 0)
7108 {
7109 fsm_odr.fsm_odr = (uint8_t)val & 0x07U;
7110 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_FSM_ODR, (uint8_t *)&fsm_odr, 1);
7111 }
7112
7113 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7114
7115 return ret;
7116 }
7117
7118 /**
7119 * @brief Finite State Machine Output Data Rate (ODR) configuration.[get]
7120 *
7121 * @param ctx read / write interface definitions
7122 * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz,
7123 * @retval interface status (MANDATORY: return 0 -> no Error)
7124 *
7125 */
lsm6dsv16bx_fsm_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_fsm_data_rate_t * val)7126 int32_t lsm6dsv16bx_fsm_data_rate_get(const stmdev_ctx_t *ctx,
7127 lsm6dsv16bx_fsm_data_rate_t *val)
7128 {
7129 lsm6dsv16bx_fsm_odr_t fsm_odr;
7130 int32_t ret;
7131
7132 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7133 if (ret == 0)
7134 {
7135 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_FSM_ODR, (uint8_t *)&fsm_odr, 1);
7136 }
7137
7138 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7139
7140 switch (fsm_odr.fsm_odr)
7141 {
7142 case LSM6DSV16BX_FSM_15Hz:
7143 *val = LSM6DSV16BX_FSM_15Hz;
7144 break;
7145
7146 case LSM6DSV16BX_FSM_30Hz:
7147 *val = LSM6DSV16BX_FSM_30Hz;
7148 break;
7149
7150 case LSM6DSV16BX_FSM_60Hz:
7151 *val = LSM6DSV16BX_FSM_60Hz;
7152 break;
7153
7154 case LSM6DSV16BX_FSM_120Hz:
7155 *val = LSM6DSV16BX_FSM_120Hz;
7156 break;
7157
7158 case LSM6DSV16BX_FSM_240Hz:
7159 *val = LSM6DSV16BX_FSM_240Hz;
7160 break;
7161
7162 case LSM6DSV16BX_FSM_480Hz:
7163 *val = LSM6DSV16BX_FSM_480Hz;
7164 break;
7165
7166 case LSM6DSV16BX_FSM_960Hz:
7167 *val = LSM6DSV16BX_FSM_960Hz;
7168 break;
7169
7170 default:
7171 *val = LSM6DSV16BX_FSM_15Hz;
7172 break;
7173 }
7174 return ret;
7175 }
7176
7177 /**
7178 * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[set]
7179 *
7180 * @param ctx read / write interface definitions
7181 * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.
7182 * @retval interface status (MANDATORY: return 0 -> no Error)
7183 *
7184 */
lsm6dsv16bx_fsm_long_cnt_timeout_set(const stmdev_ctx_t * ctx,uint16_t val)7185 int32_t lsm6dsv16bx_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val)
7186 {
7187 uint8_t buff[2];
7188 int32_t ret;
7189
7190 buff[1] = (uint8_t)(val / 256U);
7191 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7192 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_FSM_LC_TIMEOUT_L, (uint8_t *)&buff[0], 2);
7193
7194 return ret;
7195 }
7196
7197 /**
7198 * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[get]
7199 *
7200 * @param ctx read / write interface definitions
7201 * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.
7202 * @retval interface status (MANDATORY: return 0 -> no Error)
7203 *
7204 */
lsm6dsv16bx_fsm_long_cnt_timeout_get(const stmdev_ctx_t * ctx,uint16_t * val)7205 int32_t lsm6dsv16bx_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val)
7206 {
7207 uint8_t buff[2];
7208 int32_t ret;
7209
7210 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_FSM_LC_TIMEOUT_L, &buff[0], 2);
7211 *val = buff[1];
7212 *val = (*val * 256U) + buff[0];
7213
7214 return ret;
7215 }
7216
7217 /**
7218 * @brief FSM number of programs.[set]
7219 *
7220 * @param ctx read / write interface definitions
7221 * @param val FSM number of programs.
7222 * @retval interface status (MANDATORY: return 0 -> no Error)
7223 *
7224 */
lsm6dsv16bx_fsm_number_of_programs_set(const stmdev_ctx_t * ctx,uint8_t val)7225 int32_t lsm6dsv16bx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val)
7226 {
7227 lsm6dsv16bx_fsm_programs_t fsm_programs;
7228 int32_t ret;
7229
7230 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1);
7231 if (ret == 0)
7232 {
7233 fsm_programs.fsm_n_prog = val;
7234 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1);
7235 }
7236
7237 return ret;
7238 }
7239
7240 /**
7241 * @brief FSM number of programs.[get]
7242 *
7243 * @param ctx read / write interface definitions
7244 * @param val FSM number of programs.
7245 * @retval interface status (MANDATORY: return 0 -> no Error)
7246 *
7247 */
lsm6dsv16bx_fsm_number_of_programs_get(const stmdev_ctx_t * ctx,uint8_t * val)7248 int32_t lsm6dsv16bx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val)
7249 {
7250 lsm6dsv16bx_fsm_programs_t fsm_programs;
7251 int32_t ret;
7252
7253 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1);
7254 *val = fsm_programs.fsm_n_prog;
7255
7256
7257 return ret;
7258 }
7259
7260 /**
7261 * @brief FSM start address. First available address is 0x35C.[set]
7262 *
7263 * @param ctx read / write interface definitions
7264 * @param val FSM start address. First available address is 0x35C.
7265 * @retval interface status (MANDATORY: return 0 -> no Error)
7266 *
7267 */
lsm6dsv16bx_fsm_start_address_set(const stmdev_ctx_t * ctx,uint16_t val)7268 int32_t lsm6dsv16bx_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val)
7269 {
7270 uint8_t buff[2];
7271 int32_t ret;
7272
7273 buff[1] = (uint8_t)(val / 256U);
7274 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7275 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_FSM_START_ADD_L, (uint8_t *)&buff[0], 2);
7276
7277 return ret;
7278 }
7279
7280 /**
7281 * @brief FSM start address. First available address is 0x35C.[get]
7282 *
7283 * @param ctx read / write interface definitions
7284 * @param val FSM start address. First available address is 0x35C.
7285 * @retval interface status (MANDATORY: return 0 -> no Error)
7286 *
7287 */
lsm6dsv16bx_fsm_start_address_get(const stmdev_ctx_t * ctx,uint16_t * val)7288 int32_t lsm6dsv16bx_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val)
7289 {
7290 uint8_t buff[2];
7291 int32_t ret;
7292
7293 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_FSM_START_ADD_L, &buff[0], 2);
7294 *val = buff[1];
7295 *val = (*val * 256U) + buff[0];
7296
7297 return ret;
7298 }
7299
7300 /**
7301 * @}
7302 *
7303 */
7304
7305 /**
7306 * @addtogroup Machine Learning Core
7307 * @brief This section group all the functions concerning the
7308 * usage of Machine Learning Core
7309 * @{
7310 *
7311 */
7312
7313 /**
7314 * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[set]
7315 *
7316 * @param ctx read / write interface definitions
7317 * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM,
7318 * @retval interface status (MANDATORY: return 0 -> no Error)
7319 *
7320 */
lsm6dsv16bx_mlc_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_mlc_mode_t val)7321 int32_t lsm6dsv16bx_mlc_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t val)
7322 {
7323 lsm6dsv16bx_emb_func_en_b_t emb_en_b;
7324 lsm6dsv16bx_emb_func_en_a_t emb_en_a;
7325 int32_t ret;
7326
7327 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7328
7329 if (ret == 0)
7330 {
7331 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
7332 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
7333
7334 switch (val)
7335 {
7336 case LSM6DSV16BX_MLC_OFF:
7337 emb_en_a.mlc_before_fsm_en = 0;
7338 emb_en_b.mlc_en = 0;
7339 break;
7340 case LSM6DSV16BX_MLC_ON:
7341 emb_en_a.mlc_before_fsm_en = 0;
7342 emb_en_b.mlc_en = 1;
7343 break;
7344 case LSM6DSV16BX_MLC_ON_BEFORE_FSM:
7345 emb_en_a.mlc_before_fsm_en = 1;
7346 emb_en_b.mlc_en = 0;
7347 break;
7348 default:
7349 break;
7350 }
7351
7352 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
7353 ret += lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
7354 }
7355
7356 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7357
7358 return ret;
7359 }
7360
7361 /**
7362 * @brief It enables Machine Learning Core feature (MLC). When the Machine Learning Core is enabled the Finite State Machine (FSM) programs are executed before executing the MLC algorithms.[get]
7363 *
7364 * @param ctx read / write interface definitions
7365 * @param val MLC_OFF, MLC_ON, MLC_BEFORE_FSM,
7366 * @retval interface status (MANDATORY: return 0 -> no Error)
7367 *
7368 */
lsm6dsv16bx_mlc_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_mlc_mode_t * val)7369 int32_t lsm6dsv16bx_mlc_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_mode_t *val)
7370 {
7371 lsm6dsv16bx_emb_func_en_b_t emb_en_b;
7372 lsm6dsv16bx_emb_func_en_a_t emb_en_a;
7373 int32_t ret;
7374
7375 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7376
7377 if (ret == 0)
7378 {
7379 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_A, (uint8_t *)&emb_en_a, 1);
7380 ret += lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_EMB_FUNC_EN_B, (uint8_t *)&emb_en_b, 1);
7381
7382 if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 0U)
7383 {
7384 *val = LSM6DSV16BX_MLC_OFF;
7385 }
7386 else if (emb_en_a.mlc_before_fsm_en == 0U && emb_en_b.mlc_en == 1U)
7387 {
7388 *val = LSM6DSV16BX_MLC_ON;
7389 }
7390 else if (emb_en_a.mlc_before_fsm_en == 1U)
7391 {
7392 *val = LSM6DSV16BX_MLC_ON_BEFORE_FSM;
7393 }
7394 else
7395 {
7396 /* Do nothing */
7397 }
7398 }
7399
7400 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7401
7402 return ret;
7403 }
7404
7405 /**
7406 * @brief Machine Learning Core Output Data Rate (ODR) configuration.[set]
7407 *
7408 * @param ctx read / write interface definitions
7409 * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz,
7410 * @retval interface status (MANDATORY: return 0 -> no Error)
7411 *
7412 */
lsm6dsv16bx_mlc_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_mlc_data_rate_t val)7413 int32_t lsm6dsv16bx_mlc_data_rate_set(const stmdev_ctx_t *ctx,
7414 lsm6dsv16bx_mlc_data_rate_t val)
7415 {
7416 lsm6dsv16bx_mlc_odr_t mlc_odr;
7417 int32_t ret;
7418
7419 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7420 if (ret == 0)
7421 {
7422 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_ODR, (uint8_t *)&mlc_odr, 1);
7423 }
7424
7425 if (ret == 0)
7426 {
7427 mlc_odr.mlc_odr = (uint8_t)val & 0x07U;
7428 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_MLC_ODR, (uint8_t *)&mlc_odr, 1);
7429 }
7430
7431 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7432
7433 return ret;
7434 }
7435
7436 /**
7437 * @brief Machine Learning Core Output Data Rate (ODR) configuration.[get]
7438 *
7439 * @param ctx read / write interface definitions
7440 * @param val MLC_15Hz, MLC_30Hz, MLC_60Hz, MLC_120Hz, MLC_240Hz, MLC_480Hz, MLC_960Hz,
7441 * @retval interface status (MANDATORY: return 0 -> no Error)
7442 *
7443 */
lsm6dsv16bx_mlc_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_mlc_data_rate_t * val)7444 int32_t lsm6dsv16bx_mlc_data_rate_get(const stmdev_ctx_t *ctx,
7445 lsm6dsv16bx_mlc_data_rate_t *val)
7446 {
7447 lsm6dsv16bx_mlc_odr_t mlc_odr;
7448 int32_t ret;
7449
7450 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7451 if (ret == 0)
7452 {
7453 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC_ODR, (uint8_t *)&mlc_odr, 1);
7454 }
7455
7456 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7457
7458 switch (mlc_odr.mlc_odr)
7459 {
7460 case LSM6DSV16BX_MLC_15Hz:
7461 *val = LSM6DSV16BX_MLC_15Hz;
7462 break;
7463
7464 case LSM6DSV16BX_MLC_30Hz:
7465 *val = LSM6DSV16BX_MLC_30Hz;
7466 break;
7467
7468 case LSM6DSV16BX_MLC_60Hz:
7469 *val = LSM6DSV16BX_MLC_60Hz;
7470 break;
7471
7472 case LSM6DSV16BX_MLC_120Hz:
7473 *val = LSM6DSV16BX_MLC_120Hz;
7474 break;
7475
7476 case LSM6DSV16BX_MLC_240Hz:
7477 *val = LSM6DSV16BX_MLC_240Hz;
7478 break;
7479
7480 case LSM6DSV16BX_MLC_480Hz:
7481 *val = LSM6DSV16BX_MLC_480Hz;
7482 break;
7483
7484 case LSM6DSV16BX_MLC_960Hz:
7485 *val = LSM6DSV16BX_MLC_960Hz;
7486 break;
7487
7488 default:
7489 *val = LSM6DSV16BX_MLC_15Hz;
7490 break;
7491 }
7492 return ret;
7493 }
7494
7495 /**
7496 * @brief Output value of all MLC decision trees.[get]
7497 *
7498 * @param ctx read / write interface definitions
7499 * @param val Output value of all MLC decision trees.
7500 * @retval interface status (MANDATORY: return 0 -> no Error)
7501 *
7502 */
lsm6dsv16bx_mlc_out_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_mlc_out_t * val)7503 int32_t lsm6dsv16bx_mlc_out_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_mlc_out_t *val)
7504 {
7505 int32_t ret;
7506
7507 ret = lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_EMBED_FUNC_MEM_BANK);
7508 if (ret == 0)
7509 {
7510 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_MLC1_SRC, (uint8_t *)val, 4);
7511 }
7512
7513 ret += lsm6dsv16bx_mem_bank_set(ctx, LSM6DSV16BX_MAIN_MEM_BANK);
7514 return ret;
7515 }
7516
7517 /**
7518 * @brief Qvar sensor sensitivity value register for the Machine Learning Core.
7519 * This register corresponds to the conversion value of the Qvar sensor.
7520 * The register value is expressed as half-precision floating-point format:
7521 * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set]
7522 *
7523 * @param ctx read / write interface definitions
7524 * @param val Qvar sensor sensitivity value register for the Machine Learning Core.
7525 * @retval interface status (MANDATORY: return 0 -> no Error)
7526 *
7527 */
lsm6dsv16bx_mlc_qvar_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)7528 int32_t lsm6dsv16bx_mlc_qvar_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val)
7529 {
7530 uint8_t buff[2];
7531 int32_t ret;
7532
7533 buff[1] = (uint8_t)(val / 256U);
7534 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7535 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_MLC_QVAR_SENSITIVITY_L, (uint8_t *)&buff[0], 2);
7536
7537 return ret;
7538 }
7539
7540 /**
7541 * @brief Qvar sensor sensitivity value register for the Machine Learning Core.
7542 * This register corresponds to the conversion value of the Qvar sensor.
7543 * The register value is expressed as half-precision floating-point format:
7544 * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get]
7545 *
7546 * @param ctx read / write interface definitions
7547 * @param val Qvar sensor sensitivity value register for the Machine Learning Core.
7548 * @retval interface status (MANDATORY: return 0 -> no Error)
7549 *
7550 */
lsm6dsv16bx_mlc_qvar_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)7551 int32_t lsm6dsv16bx_mlc_qvar_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val)
7552 {
7553 uint8_t buff[2];
7554 int32_t ret;
7555
7556 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_MLC_QVAR_SENSITIVITY_L, &buff[0], 2);
7557 *val = buff[1];
7558 *val = (*val * 256U) + buff[0];
7559
7560 return ret;
7561 }
7562
7563 /**
7564 * @}
7565 *
7566 */
7567
7568 /**
7569 * @addtogroup Accelerometer user offset correction
7570 * @brief This section group all the functions concerning the
7571 * usage of Accelerometer user offset correction
7572 * @{
7573 *
7574 */
7575
7576 /**
7577 * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[set]
7578 *
7579 * @param ctx read / write interface definitions
7580 * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path.
7581 * @retval interface status (MANDATORY: return 0 -> no Error)
7582 *
7583 */
lsm6dsv16bx_xl_offset_on_out_set(const stmdev_ctx_t * ctx,uint8_t val)7584 int32_t lsm6dsv16bx_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val)
7585 {
7586 lsm6dsv16bx_ctrl9_t ctrl9;
7587 int32_t ret;
7588
7589 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
7590 if (ret == 0)
7591 {
7592 ctrl9.usr_off_on_out = val;
7593 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
7594 }
7595
7596 return ret;
7597 }
7598
7599 /**
7600 * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[get]
7601 *
7602 * @param ctx read / write interface definitions
7603 * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path.
7604 * @retval interface status (MANDATORY: return 0 -> no Error)
7605 *
7606 */
lsm6dsv16bx_xl_offset_on_out_get(const stmdev_ctx_t * ctx,uint8_t * val)7607 int32_t lsm6dsv16bx_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val)
7608 {
7609 lsm6dsv16bx_ctrl9_t ctrl9;
7610 int32_t ret;
7611
7612 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
7613 *val = ctrl9.usr_off_on_out;
7614
7615 return ret;
7616 }
7617
7618 /**
7619 * @brief Accelerometer user offset correction values in mg.[set]
7620 *
7621 * @param ctx read / write interface definitions
7622 * @param val Accelerometer user offset correction values in mg.
7623 * @retval interface status (MANDATORY: return 0 -> no Error)
7624 *
7625 */
lsm6dsv16bx_xl_offset_mg_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_xl_offset_mg_t val)7626 int32_t lsm6dsv16bx_xl_offset_mg_set(const stmdev_ctx_t *ctx,
7627 lsm6dsv16bx_xl_offset_mg_t val)
7628 {
7629 lsm6dsv16bx_z_ofs_usr_t z_ofs_usr;
7630 lsm6dsv16bx_y_ofs_usr_t y_ofs_usr;
7631 lsm6dsv16bx_x_ofs_usr_t x_ofs_usr;
7632 lsm6dsv16bx_ctrl9_t ctrl9;
7633 int32_t ret;
7634 float_t tmp;
7635
7636 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
7637 if (ret == 0)
7638 {
7639 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
7640 }
7641 if (ret == 0)
7642 {
7643 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
7644 }
7645 if (ret == 0)
7646 {
7647 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
7648 }
7649
7650
7651 if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) &&
7652 (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) &&
7653 (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f)))
7654 {
7655 ctrl9.usr_off_w = 0;
7656
7657 tmp = val.z_mg / 0.0078125f;
7658 z_ofs_usr.z_ofs_usr = (uint8_t)tmp;
7659
7660 tmp = val.y_mg / 0.0078125f;
7661 y_ofs_usr.y_ofs_usr = (uint8_t)tmp;
7662
7663 tmp = val.x_mg / 0.0078125f;
7664 x_ofs_usr.x_ofs_usr = (uint8_t)tmp;
7665 }
7666 else if ((val.x_mg < (0.125f * 127.0f)) && (val.x_mg > (0.125f * -127.0f)) &&
7667 (val.y_mg < (0.125f * 127.0f)) && (val.y_mg > (0.125f * -127.0f)) &&
7668 (val.z_mg < (0.125f * 127.0f)) && (val.z_mg > (0.125f * -127.0f)))
7669 {
7670 ctrl9.usr_off_w = 1;
7671
7672 tmp = val.z_mg / 0.125f;
7673 z_ofs_usr.z_ofs_usr = (uint8_t)tmp;
7674
7675 tmp = val.y_mg / 0.125f;
7676 y_ofs_usr.y_ofs_usr = (uint8_t)tmp;
7677
7678 tmp = val.x_mg / 0.125f;
7679 x_ofs_usr.x_ofs_usr = (uint8_t)tmp;
7680 }
7681 else // out of limit
7682 {
7683 ctrl9.usr_off_w = 1;
7684 z_ofs_usr.z_ofs_usr = 0xFFU;
7685 y_ofs_usr.y_ofs_usr = 0xFFU;
7686 x_ofs_usr.x_ofs_usr = 0xFFU;
7687 }
7688
7689 if (ret == 0)
7690 {
7691 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
7692 }
7693 if (ret == 0)
7694 {
7695 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
7696 }
7697 if (ret == 0)
7698 {
7699 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
7700 }
7701 if (ret == 0)
7702 {
7703 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
7704 }
7705 return ret;
7706 }
7707
7708 /**
7709 * @brief Accelerometer user offset correction values in mg.[get]
7710 *
7711 * @param ctx read / write interface definitions
7712 * @param val Accelerometer user offset correction values in mg.
7713 * @retval interface status (MANDATORY: return 0 -> no Error)
7714 *
7715 */
lsm6dsv16bx_xl_offset_mg_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_xl_offset_mg_t * val)7716 int32_t lsm6dsv16bx_xl_offset_mg_get(const stmdev_ctx_t *ctx,
7717 lsm6dsv16bx_xl_offset_mg_t *val)
7718 {
7719 lsm6dsv16bx_z_ofs_usr_t z_ofs_usr;
7720 lsm6dsv16bx_y_ofs_usr_t y_ofs_usr;
7721 lsm6dsv16bx_x_ofs_usr_t x_ofs_usr;
7722 lsm6dsv16bx_ctrl9_t ctrl9;
7723 int32_t ret;
7724
7725 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL9, (uint8_t *)&ctrl9, 1);
7726 if (ret == 0)
7727 {
7728 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
7729 }
7730 if (ret == 0)
7731 {
7732 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
7733 }
7734 if (ret == 0)
7735 {
7736 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
7737 }
7738
7739 if (ctrl9.usr_off_w == PROPERTY_DISABLE)
7740 {
7741 val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.0078125f);
7742 val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.0078125f);
7743 val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.0078125f);
7744 }
7745 else
7746 {
7747 val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.125f);
7748 val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.125f);
7749 val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.125f);
7750 }
7751
7752 return ret;
7753 }
7754
7755 /**
7756 * @}
7757 *
7758 */
7759
7760 /**
7761 * @addtogroup AH_QVAR
7762 * @brief This section group all the functions concerning the
7763 * usage of AH_QVAR
7764 * @{
7765 *
7766 */
7767
7768 /**
7769 * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are
7770 * connected to the AH1/Qvar1 and AH1/Qvar2 pins. Before setting this bit to 1,
7771 * the accelerometer and gyroscope sensor have to be configured in power-down mode.[set]
7772 *
7773 * @param ctx read / write interface definitions
7774 * @param val 1: Enables AH_QVAR chain, 0: Disable the AH_QVAR chain
7775 * @retval interface status (MANDATORY: return 0 -> no Error)
7776 *
7777 */
lsm6dsv16bx_ah_qvar_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_ah_qvar_mode_t val)7778 int32_t lsm6dsv16bx_ah_qvar_mode_set(const stmdev_ctx_t *ctx,
7779 lsm6dsv16bx_ah_qvar_mode_t val)
7780 {
7781 lsm6dsv16bx_ctrl10_t ctrl10;
7782 lsm6dsv16bx_ctrl7_t ctrl7;
7783 int32_t ret;
7784
7785 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
7786 if (ret == 0)
7787 {
7788 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
7789 }
7790
7791 if (ret == 0)
7792 {
7793 if ((val.ah_qvar1_en | val.ah_qvar2_en) == PROPERTY_ENABLE)
7794 {
7795 ctrl7.ah_qvar_en = PROPERTY_ENABLE;
7796 }
7797 else
7798 {
7799 ctrl7.ah_qvar_en = PROPERTY_DISABLE;
7800 }
7801 ctrl7.ah_qvar1_en = val.ah_qvar1_en;
7802 ctrl7.ah_qvar2_en = val.ah_qvar2_en;
7803 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
7804 }
7805 if (ret == 0)
7806 {
7807 ctrl10.ah_qvar_sw = val.swaps;
7808 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
7809 }
7810 return ret;
7811 }
7812
7813 /**
7814 * @brief Enables AH_QVAR chain. When this bit is set to ‘1’, the AH_QVAR buffers are
7815 * connected to the AH1/Qvar1 and AH1/Qvar2 pins. Before setting this bit to 1,
7816 * the accelerometer and gyroscope sensor have to be configured in power-down mode.[get]
7817 *
7818 * @param ctx read / write interface definitions
7819 * @param val 1: Enables AH_QVAR chain, 0: Disable the AH_QVAR chain
7820 * @retval interface status (MANDATORY: return 0 -> no Error)
7821 *
7822 */
lsm6dsv16bx_ah_qvar_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_ah_qvar_mode_t * val)7823 int32_t lsm6dsv16bx_ah_qvar_mode_get(const stmdev_ctx_t *ctx,
7824 lsm6dsv16bx_ah_qvar_mode_t *val)
7825 {
7826 lsm6dsv16bx_ctrl10_t ctrl10;
7827 lsm6dsv16bx_ctrl7_t ctrl7;
7828 int32_t ret;
7829
7830 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
7831 if (ret == 0)
7832 {
7833 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL10, (uint8_t *)&ctrl10, 1);
7834 }
7835
7836 val->ah_qvar1_en = ctrl7.ah_qvar1_en;
7837 val->ah_qvar2_en = ctrl7.ah_qvar2_en;
7838 val->swaps = ctrl10.ah_qvar_sw;
7839
7840 return ret;
7841 }
7842
7843 /**
7844 * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[set]
7845 *
7846 * @param ctx read / write interface definitions
7847 * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm,
7848 * @retval interface status (MANDATORY: return 0 -> no Error)
7849 *
7850 */
lsm6dsv16bx_ah_qvar_zin_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_ah_qvar_zin_t val)7851 int32_t lsm6dsv16bx_ah_qvar_zin_set(const stmdev_ctx_t *ctx,
7852 lsm6dsv16bx_ah_qvar_zin_t val)
7853 {
7854 lsm6dsv16bx_ctrl7_t ctrl7;
7855 int32_t ret;
7856
7857 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
7858 if (ret == 0)
7859 {
7860 ctrl7.ah_qvar_c_zin = (uint8_t)val & 0x03U;
7861 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
7862 }
7863
7864 return ret;
7865 }
7866
7867 /**
7868 * @brief Configures the equivalent input impedance of the AH_QVAR buffers.[get]
7869 *
7870 * @param ctx read / write interface definitions
7871 * @param val 2400MOhm, 730MOhm, 300MOhm, 255MOhm,
7872 * @retval interface status (MANDATORY: return 0 -> no Error)
7873 *
7874 */
lsm6dsv16bx_ah_qvar_zin_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_ah_qvar_zin_t * val)7875 int32_t lsm6dsv16bx_ah_qvar_zin_get(const stmdev_ctx_t *ctx,
7876 lsm6dsv16bx_ah_qvar_zin_t *val)
7877 {
7878 lsm6dsv16bx_ctrl7_t ctrl7;
7879 int32_t ret;
7880
7881 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_CTRL7, (uint8_t *)&ctrl7, 1);
7882 switch (ctrl7.ah_qvar_c_zin)
7883 {
7884 case LSM6DSV16BX_2400MOhm:
7885 *val = LSM6DSV16BX_2400MOhm;
7886 break;
7887
7888 case LSM6DSV16BX_730MOhm:
7889 *val = LSM6DSV16BX_730MOhm;
7890 break;
7891
7892 case LSM6DSV16BX_300MOhm:
7893 *val = LSM6DSV16BX_300MOhm;
7894 break;
7895
7896 case LSM6DSV16BX_255MOhm:
7897 *val = LSM6DSV16BX_255MOhm;
7898 break;
7899
7900 default:
7901 *val = LSM6DSV16BX_2400MOhm;
7902 break;
7903 }
7904 return ret;
7905 }
7906
7907 /**
7908 * @brief Qvar sensor sensitivity value register for the Finite State Machine.
7909 * This register corresponds to the conversion value of the Qvar sensor.
7910 * The register value is expressed as half-precision floating-point format:
7911 * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[set]
7912 *
7913 * @param ctx read / write interface definitions
7914 * @param val Qvar sensor sensitivity value register for the Finite State Machine.
7915 * @retval interface status (MANDATORY: return 0 -> no Error)
7916 *
7917 */
lsm6dsv16bx_fsm_qvar_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)7918 int32_t lsm6dsv16bx_fsm_qvar_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val)
7919 {
7920 uint8_t buff[2];
7921 int32_t ret;
7922
7923 buff[1] = (uint8_t)(val / 256U);
7924 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7925 ret = lsm6dsv16bx_ln_pg_write(ctx, LSM6DSV16BX_FSM_QVAR_SENSITIVITY_L, (uint8_t *)&buff[0], 2);
7926
7927 return ret;
7928 }
7929
7930 /**
7931 * @brief Qvar sensor sensitivity value register for the Finite State Machine.
7932 * This register corresponds to the conversion value of the Qvar sensor.
7933 * The register value is expressed as half-precision floating-point format:
7934 * SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent bits; F: 10 fraction bits).[get]
7935 *
7936 * @param ctx read / write interface definitions
7937 * @param val Qvar sensor sensitivity value register for the Finite State Machine.
7938 * @retval interface status (MANDATORY: return 0 -> no Error)
7939 *
7940 */
lsm6dsv16bx_fsm_qvar_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)7941 int32_t lsm6dsv16bx_fsm_qvar_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val)
7942 {
7943 uint8_t buff[2];
7944 int32_t ret;
7945
7946 ret = lsm6dsv16bx_ln_pg_read(ctx, LSM6DSV16BX_FSM_QVAR_SENSITIVITY_L, &buff[0], 2);
7947 *val = buff[1];
7948 *val = (*val * 256U) + buff[0];
7949
7950 return ret;
7951 }
7952
7953 /**
7954 * @}
7955 *
7956 */
7957
7958 /**
7959 * @addtogroup SenseWire (I3C)
7960 * @brief This section group all the functions concerning the
7961 * usage of SenseWire (I3C)
7962 * @{
7963 *
7964 */
7965
7966 /**
7967 * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[set]
7968 *
7969 * @param ctx read / write interface definitions
7970 * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST_,
7971 * @retval interface status (MANDATORY: return 0 -> no Error)
7972 *
7973 */
lsm6dsv16bx_i3c_reset_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_i3c_reset_mode_t val)7974 int32_t lsm6dsv16bx_i3c_reset_mode_set(const stmdev_ctx_t *ctx,
7975 lsm6dsv16bx_i3c_reset_mode_t val)
7976 {
7977 lsm6dsv16bx_pin_ctrl_t pin_ctrl;
7978 int32_t ret;
7979
7980 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7981 if (ret == 0)
7982 {
7983 pin_ctrl.ibhr_por_en = (uint8_t)val & 0x01U;
7984 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7985 }
7986
7987 return ret;
7988 }
7989
7990 /**
7991 * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[get]
7992 *
7993 * @param ctx read / write interface definitions
7994 * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST_,
7995 * @retval interface status (MANDATORY: return 0 -> no Error)
7996 *
7997 */
lsm6dsv16bx_i3c_reset_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_i3c_reset_mode_t * val)7998 int32_t lsm6dsv16bx_i3c_reset_mode_get(const stmdev_ctx_t *ctx,
7999 lsm6dsv16bx_i3c_reset_mode_t *val)
8000 {
8001 lsm6dsv16bx_pin_ctrl_t pin_ctrl;
8002 int32_t ret;
8003
8004 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8005 switch (pin_ctrl.ibhr_por_en)
8006 {
8007 case LSM6DSV16BX_SW_RST_DYN_ADDRESS_RST:
8008 *val = LSM6DSV16BX_SW_RST_DYN_ADDRESS_RST;
8009 break;
8010
8011 case LSM6DSV16BX_I3C_GLOBAL_RST:
8012 *val = LSM6DSV16BX_I3C_GLOBAL_RST;
8013 break;
8014
8015 default:
8016 *val = LSM6DSV16BX_SW_RST_DYN_ADDRESS_RST;
8017 break;
8018 }
8019 return ret;
8020 }
8021
8022 /**
8023 * @}
8024 *
8025 */
8026
8027 /**
8028 * @addtogroup Time-Division Multiplexing (TDM)
8029 * @brief This section group all the functions concerning the
8030 * usage of Time-Division Multiplexing (TDM)
8031 * @{
8032 *
8033 */
8034
8035 /**
8036 * @brief Disables pull-up on WCLK pin.[set]
8037 *
8038 * @param ctx read / write interface definitions
8039 * @param val Disables pull-up on WCLK pin.
8040 * @retval interface status (MANDATORY: return 0 -> no Error)
8041 *
8042 */
lsm6dsv16bx_tdm_dis_wclk_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)8043 int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
8044 {
8045 lsm6dsv16bx_pin_ctrl_t pin_ctrl;
8046 int32_t ret;
8047
8048 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8049 if (ret == 0)
8050 {
8051 pin_ctrl.tdm_wclk_pu_dis = val;
8052 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8053 }
8054
8055 return ret;
8056 }
8057
8058 /**
8059 * @brief Disables pull-up on WCLK pin.[get]
8060 *
8061 * @param ctx read / write interface definitions
8062 * @param val Disables pull-up on WCLK pin.
8063 * @retval interface status (MANDATORY: return 0 -> no Error)
8064 *
8065 */
lsm6dsv16bx_tdm_dis_wclk_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)8066 int32_t lsm6dsv16bx_tdm_dis_wclk_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
8067 {
8068 lsm6dsv16bx_pin_ctrl_t pin_ctrl;
8069 int32_t ret;
8070
8071 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
8072 *val = pin_ctrl.tdm_wclk_pu_dis;
8073
8074 return ret;
8075 }
8076
8077 /**
8078 * @brief Enables pull-up on TDMout pin.[set]
8079 *
8080 * @param ctx read / write interface definitions
8081 * @param val Enables pull-up on TDMout pin.
8082 * @retval interface status (MANDATORY: return 0 -> no Error)
8083 *
8084 */
lsm6dsv16bx_tdm_tdmout_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)8085 int32_t lsm6dsv16bx_tdm_tdmout_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
8086 {
8087 lsm6dsv16bx_if_cfg_t if_cfg;
8088 int32_t ret;
8089
8090 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
8091 if (ret == 0)
8092 {
8093 if_cfg.tdm_out_pu_en = val;
8094 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
8095 }
8096
8097 return ret;
8098 }
8099
8100 /**
8101 * @brief Enables pull-up on TDMout pin.[get]
8102 *
8103 * @param ctx read / write interface definitions
8104 * @param val Enables pull-up on TDMout pin.
8105 * @retval interface status (MANDATORY: return 0 -> no Error)
8106 *
8107 */
lsm6dsv16bx_tdm_tdmout_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)8108 int32_t lsm6dsv16bx_tdm_tdmout_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
8109 {
8110 lsm6dsv16bx_if_cfg_t if_cfg;
8111 int32_t ret;
8112
8113 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_IF_CFG, (uint8_t *)&if_cfg, 1);
8114 *val = if_cfg.tdm_out_pu_en;
8115
8116 return ret;
8117 }
8118
8119 /**
8120 * @brief WCLK and BCLK frequencies.[set]
8121 *
8122 * @param ctx read / write interface definitions
8123 * @param val WCLK_8kHZ_1024kHz, WCLK_16kHZ_2048kHz, WCLK_8kHZ_2048kHz, WCLK_16kHZ_1024kHz,
8124 * @retval interface status (MANDATORY: return 0 -> no Error)
8125 *
8126 */
lsm6dsv16bx_tdm_wclk_bclk_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_wclk_bclk_t val)8127 int32_t lsm6dsv16bx_tdm_wclk_bclk_set(const stmdev_ctx_t *ctx,
8128 lsm6dsv16bx_tdm_wclk_bclk_t val)
8129 {
8130 lsm6dsv16bx_tdm_cfg0_t tdm_cfg0;
8131 int32_t ret;
8132
8133 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8134 if (ret == 0)
8135 {
8136 tdm_cfg0.tdm_wclk_bclk_sel = ((uint8_t)val & 0x4U) >> 2;
8137 tdm_cfg0.tdm_wclk = (uint8_t)val & 0x3U;
8138 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8139 }
8140
8141 return ret;
8142 }
8143
8144 /**
8145 * @brief WCLK and BCLK frequencies.[get]
8146 *
8147 * @param ctx read / write interface definitions
8148 * @param val WCLK_8kHZ_1024kHz, WCLK_16kHZ_2048kHz, WCLK_8kHZ_2048kHz, WCLK_16kHZ_1024kHz,
8149 * @retval interface status (MANDATORY: return 0 -> no Error)
8150 *
8151 */
lsm6dsv16bx_tdm_wclk_bclk_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_wclk_bclk_t * val)8152 int32_t lsm6dsv16bx_tdm_wclk_bclk_get(const stmdev_ctx_t *ctx,
8153 lsm6dsv16bx_tdm_wclk_bclk_t *val)
8154 {
8155 lsm6dsv16bx_tdm_cfg0_t tdm_cfg0;
8156 int32_t ret;
8157
8158 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8159 switch ((tdm_cfg0.tdm_wclk_bclk_sel << 2) + tdm_cfg0.tdm_wclk)
8160 {
8161 case LSM6DSV16BX_WCLK_16kHZ_BCLK_2048kHz:
8162 *val = LSM6DSV16BX_WCLK_16kHZ_BCLK_2048kHz;
8163 break;
8164
8165 case LSM6DSV16BX_WCLK_8kHZ_BCLK_2048kHz:
8166 *val = LSM6DSV16BX_WCLK_8kHZ_BCLK_2048kHz;
8167 break;
8168
8169 default:
8170 *val = LSM6DSV16BX_WCLK_8kHZ_BCLK_2048kHz;
8171 break;
8172 }
8173 return ret;
8174 }
8175
8176 /**
8177 * @brief Selection of TDM slot for transmission.[set]
8178 *
8179 * @param ctx read / write interface definitions
8180 * @param val SLOT_012, SLOT_456,
8181 * @retval interface status (MANDATORY: return 0 -> no Error)
8182 *
8183 */
lsm6dsv16bx_tdm_slot_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_slot_t val)8184 int32_t lsm6dsv16bx_tdm_slot_set(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_slot_t val)
8185 {
8186 lsm6dsv16bx_tdm_cfg0_t tdm_cfg0;
8187 int32_t ret;
8188
8189 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8190 if (ret == 0)
8191 {
8192 tdm_cfg0.tdm_slot_sel = (uint8_t)val & 0x01U;
8193 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8194 }
8195
8196 return ret;
8197 }
8198
8199 /**
8200 * @brief Selection of TDM slot for transmission.[get]
8201 *
8202 * @param ctx read / write interface definitions
8203 * @param val SLOT_012, SLOT_456,
8204 * @retval interface status (MANDATORY: return 0 -> no Error)
8205 *
8206 */
lsm6dsv16bx_tdm_slot_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_slot_t * val)8207 int32_t lsm6dsv16bx_tdm_slot_get(const stmdev_ctx_t *ctx, lsm6dsv16bx_tdm_slot_t *val)
8208 {
8209 lsm6dsv16bx_tdm_cfg0_t tdm_cfg0;
8210 int32_t ret;
8211
8212 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8213 switch (tdm_cfg0.tdm_slot_sel)
8214 {
8215 case LSM6DSV16BX_SLOT_012:
8216 *val = LSM6DSV16BX_SLOT_012;
8217 break;
8218
8219 case LSM6DSV16BX_SLOT_456:
8220 *val = LSM6DSV16BX_SLOT_456;
8221 break;
8222
8223 default:
8224 *val = LSM6DSV16BX_SLOT_012;
8225 break;
8226 }
8227 return ret;
8228 }
8229
8230 /**
8231 * @brief BCLK edge selection for TDM interface.[set]
8232 *
8233 * @param ctx read / write interface definitions
8234 * @param val BCLK_RISING, BCLK_FALLING,
8235 * @retval interface status (MANDATORY: return 0 -> no Error)
8236 *
8237 */
lsm6dsv16bx_tdm_bclk_edge_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_bclk_edge_t val)8238 int32_t lsm6dsv16bx_tdm_bclk_edge_set(const stmdev_ctx_t *ctx,
8239 lsm6dsv16bx_tdm_bclk_edge_t val)
8240 {
8241 lsm6dsv16bx_tdm_cfg0_t tdm_cfg0;
8242 int32_t ret;
8243
8244 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8245 if (ret == 0)
8246 {
8247 tdm_cfg0.tdm_bclk_edge_sel = (uint8_t)val & 0x01U;
8248 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8249 }
8250
8251 return ret;
8252 }
8253
8254 /**
8255 * @brief BCLK edge selection for TDM interface.[get]
8256 *
8257 * @param ctx read / write interface definitions
8258 * @param val BCLK_RISING, BCLK_FALLING,
8259 * @retval interface status (MANDATORY: return 0 -> no Error)
8260 *
8261 */
lsm6dsv16bx_tdm_bclk_edge_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_bclk_edge_t * val)8262 int32_t lsm6dsv16bx_tdm_bclk_edge_get(const stmdev_ctx_t *ctx,
8263 lsm6dsv16bx_tdm_bclk_edge_t *val)
8264 {
8265 lsm6dsv16bx_tdm_cfg0_t tdm_cfg0;
8266 int32_t ret;
8267
8268 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8269 switch (tdm_cfg0.tdm_bclk_edge_sel)
8270 {
8271 case LSM6DSV16BX_BCLK_RISING:
8272 *val = LSM6DSV16BX_BCLK_RISING;
8273 break;
8274
8275 case LSM6DSV16BX_BCLK_FALLING:
8276 *val = LSM6DSV16BX_BCLK_FALLING;
8277 break;
8278
8279 default:
8280 *val = LSM6DSV16BX_BCLK_RISING;
8281 break;
8282 }
8283 return ret;
8284 }
8285
8286 /**
8287 * @brief Enables TDM delayed configuration.[set]
8288 *
8289 * @param ctx read / write interface definitions
8290 * @param val Enables TDM delayed configuration.
8291 * @retval interface status (MANDATORY: return 0 -> no Error)
8292 *
8293 */
lsm6dsv16bx_tdm_delayed_conf_set(const stmdev_ctx_t * ctx,uint8_t val)8294 int32_t lsm6dsv16bx_tdm_delayed_conf_set(const stmdev_ctx_t *ctx, uint8_t val)
8295 {
8296 lsm6dsv16bx_tdm_cfg0_t tdm_cfg0;
8297 int32_t ret;
8298
8299 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8300 if (ret == 0)
8301 {
8302 tdm_cfg0.tdm_delayed_cfg = val;
8303 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8304 }
8305
8306 return ret;
8307 }
8308
8309 /**
8310 * @brief Enables TDM delayed configuration.[get]
8311 *
8312 * @param ctx read / write interface definitions
8313 * @param val Enables TDM delayed configuration.
8314 * @retval interface status (MANDATORY: return 0 -> no Error)
8315 *
8316 */
lsm6dsv16bx_tdm_delayed_conf_get(const stmdev_ctx_t * ctx,uint8_t * val)8317 int32_t lsm6dsv16bx_tdm_delayed_conf_get(const stmdev_ctx_t *ctx, uint8_t *val)
8318 {
8319 lsm6dsv16bx_tdm_cfg0_t tdm_cfg0;
8320 int32_t ret;
8321
8322 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
8323 *val = tdm_cfg0.tdm_delayed_cfg;
8324
8325 return ret;
8326 }
8327
8328
8329 /**
8330 * @brief Selects order of transmission of TDM axes.[set]
8331 *
8332 * @param ctx read / write interface definitions
8333 * @param val TDM_ORDER_ZYX, TDM_ORDER_XZY, TDM_ORDER_XYZ,
8334 * @retval interface status (MANDATORY: return 0 -> no Error)
8335 *
8336 */
lsm6dsv16bx_tdm_axis_order_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_axis_order_t val)8337 int32_t lsm6dsv16bx_tdm_axis_order_set(const stmdev_ctx_t *ctx,
8338 lsm6dsv16bx_tdm_axis_order_t val)
8339 {
8340 lsm6dsv16bx_tdm_cfg1_t tdm_cfg1;
8341 int32_t ret;
8342
8343 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
8344 if (ret == 0)
8345 {
8346 tdm_cfg1.tdm_axes_ord_sel = (uint8_t)val & 0x03U;
8347 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
8348 }
8349
8350 return ret;
8351 }
8352
8353 /**
8354 * @brief Selects order of transmission of TDM axes.[get]
8355 *
8356 * @param ctx read / write interface definitions
8357 * @param val TDM_ORDER_ZYX, TDM_ORDER_XZY, TDM_ORDER_XYZ,
8358 * @retval interface status (MANDATORY: return 0 -> no Error)
8359 *
8360 */
lsm6dsv16bx_tdm_axis_order_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_axis_order_t * val)8361 int32_t lsm6dsv16bx_tdm_axis_order_get(const stmdev_ctx_t *ctx,
8362 lsm6dsv16bx_tdm_axis_order_t *val)
8363 {
8364 lsm6dsv16bx_tdm_cfg1_t tdm_cfg1;
8365 int32_t ret;
8366
8367 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
8368 switch (tdm_cfg1.tdm_axes_ord_sel)
8369 {
8370 case LSM6DSV16BX_TDM_ORDER_ZYX:
8371 *val = LSM6DSV16BX_TDM_ORDER_ZYX;
8372 break;
8373
8374 case LSM6DSV16BX_TDM_ORDER_XZY:
8375 *val = LSM6DSV16BX_TDM_ORDER_XZY;
8376 break;
8377
8378 case LSM6DSV16BX_TDM_ORDER_XYZ:
8379 *val = LSM6DSV16BX_TDM_ORDER_XYZ;
8380 break;
8381
8382 default:
8383 *val = LSM6DSV16BX_TDM_ORDER_ZYX;
8384 break;
8385 }
8386 return ret;
8387 }
8388
8389 /**
8390 * @brief TDM channel accelerometer full-scale selection.[set]
8391 *
8392 * @param ctx read / write interface definitions
8393 * @param val TDM_2g, TDM_4g, TDM_8g,
8394 * @retval interface status (MANDATORY: return 0 -> no Error)
8395 *
8396 */
lsm6dsv16bx_tdm_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_xl_full_scale_t val)8397 int32_t lsm6dsv16bx_tdm_xl_full_scale_set(const stmdev_ctx_t *ctx,
8398 lsm6dsv16bx_tdm_xl_full_scale_t val)
8399 {
8400 lsm6dsv16bx_tdm_cfg2_t tdm_cfg2;
8401 int32_t ret;
8402
8403 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
8404 if (ret == 0)
8405 {
8406 tdm_cfg2.tdm_fs_xl = (uint8_t)val & 0x3U;
8407 ret = lsm6dsv16bx_write_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
8408 }
8409
8410 return ret;
8411 }
8412
8413 /**
8414 * @brief TDM channel accelerometer full-scale selection.[get]
8415 *
8416 * @param ctx read / write interface definitions
8417 * @param val TDM_2g, TDM_4g, TDM_8g,
8418 * @retval interface status (MANDATORY: return 0 -> no Error)
8419 *
8420 */
lsm6dsv16bx_tdm_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv16bx_tdm_xl_full_scale_t * val)8421 int32_t lsm6dsv16bx_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx,
8422 lsm6dsv16bx_tdm_xl_full_scale_t *val)
8423 {
8424 lsm6dsv16bx_tdm_cfg2_t tdm_cfg2;
8425 int32_t ret;
8426
8427 ret = lsm6dsv16bx_read_reg(ctx, LSM6DSV16BX_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
8428 switch (tdm_cfg2.tdm_fs_xl)
8429 {
8430 case LSM6DSV16BX_TDM_2g:
8431 *val = LSM6DSV16BX_TDM_2g;
8432 break;
8433
8434 case LSM6DSV16BX_TDM_4g:
8435 *val = LSM6DSV16BX_TDM_4g;
8436 break;
8437
8438 case LSM6DSV16BX_TDM_8g:
8439 *val = LSM6DSV16BX_TDM_8g;
8440 break;
8441
8442 default:
8443 *val = LSM6DSV16BX_TDM_2g;
8444 break;
8445 }
8446 return ret;
8447 }
8448
8449 /**
8450 * @}
8451 *
8452 */
8453
8454 /**
8455 * @}
8456 *
8457 */
8458
8459 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
8460
