1 /** 2 ****************************************************************************** 3 * @file lsm6dsv16b_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm6dsv16b_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2024 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM6DSV16B_REGS_H 23 #define LSM6DSV16B_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM6DSV16B 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup LSM6DSV16B_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format if SA0=0 -> D5 if SA0=1 -> D7 **/ 172 #define LSM6DSV16B_I2C_ADD_L 0xD5U 173 #define LSM6DSV16B_I2C_ADD_H 0xD7U 174 175 /** Device Identification (Who am I) **/ 176 #define LSM6DSV16B_ID 0x71U 177 178 /** 179 * @} 180 * 181 */ 182 183 /** @defgroup bitfields page main 184 * @{ 185 * 186 */ 187 188 #define LSM6DSV16B_FUNC_CFG_ACCESS 0x1U 189 typedef struct 190 { 191 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 192 uint8_t not_used0 : 2; 193 uint8_t sw_por : 1; 194 uint8_t fsm_wr_ctrl_en : 1; 195 uint8_t not_used1 : 3; 196 uint8_t emb_func_reg_access : 1; 197 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 198 uint8_t emb_func_reg_access : 1; 199 uint8_t not_used1 : 3; 200 uint8_t fsm_wr_ctrl_en : 1; 201 uint8_t sw_por : 1; 202 uint8_t not_used0 : 2; 203 #endif /* DRV_BYTE_ORDER */ 204 } lsm6dsv16b_func_cfg_access_t; 205 206 #define LSM6DSV16B_PIN_CTRL 0x2U 207 typedef struct 208 { 209 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 210 uint8_t not_used0 : 5; 211 uint8_t ibhr_por_en : 1; 212 uint8_t sdo_pu_en : 1; 213 uint8_t tdm_wclk_pu_dis : 1; 214 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 215 uint8_t tdm_wclk_pu_dis : 1; 216 uint8_t sdo_pu_en : 1; 217 uint8_t ibhr_por_en : 1; 218 uint8_t not_used0 : 5; 219 #endif /* DRV_BYTE_ORDER */ 220 } lsm6dsv16b_pin_ctrl_t; 221 222 #define LSM6DSV16B_IF_CFG 0x3U 223 typedef struct 224 { 225 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 226 uint8_t i2c_i3c_disable : 1; 227 uint8_t not_used0 : 1; 228 uint8_t sim : 1; 229 uint8_t pp_od : 1; 230 uint8_t h_lactive : 1; 231 uint8_t asf_ctrl : 1; 232 uint8_t tdm_out_pu_en : 1; 233 uint8_t sda_pu_en : 1; 234 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 235 uint8_t sda_pu_en : 1; 236 uint8_t tdm_out_pu_en : 1; 237 uint8_t asf_ctrl : 1; 238 uint8_t h_lactive : 1; 239 uint8_t pp_od : 1; 240 uint8_t sim : 1; 241 uint8_t not_used0 : 1; 242 uint8_t i2c_i3c_disable : 1; 243 #endif /* DRV_BYTE_ORDER */ 244 } lsm6dsv16b_if_cfg_t; 245 246 #define LSM6DSV16B_FIFO_CTRL1 0x7U 247 typedef struct 248 { 249 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 250 uint8_t wtm : 8; 251 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 252 uint8_t wtm : 8; 253 #endif /* DRV_BYTE_ORDER */ 254 } lsm6dsv16b_fifo_ctrl1_t; 255 256 #define LSM6DSV16B_FIFO_CTRL2 0x8U 257 typedef struct 258 { 259 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 260 uint8_t xl_dualc_batch_from_fsm : 1; 261 uint8_t uncompr_rate : 2; 262 uint8_t not_used0 : 1; 263 uint8_t odr_chg_en : 1; 264 uint8_t not_used1 : 1; 265 uint8_t fifo_compr_rt_en : 1; 266 uint8_t stop_on_wtm : 1; 267 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 268 uint8_t stop_on_wtm : 1; 269 uint8_t fifo_compr_rt_en : 1; 270 uint8_t not_used1 : 1; 271 uint8_t odr_chg_en : 1; 272 uint8_t not_used0 : 1; 273 uint8_t uncompr_rate : 2; 274 uint8_t xl_dualc_batch_from_fsm : 1; 275 #endif /* DRV_BYTE_ORDER */ 276 } lsm6dsv16b_fifo_ctrl2_t; 277 278 #define LSM6DSV16B_FIFO_CTRL3 0x9U 279 typedef struct 280 { 281 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 282 uint8_t bdr_xl : 4; 283 uint8_t bdr_gy : 4; 284 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 285 uint8_t bdr_gy : 4; 286 uint8_t bdr_xl : 4; 287 #endif /* DRV_BYTE_ORDER */ 288 } lsm6dsv16b_fifo_ctrl3_t; 289 290 #define LSM6DSV16B_FIFO_CTRL4 0x0AU 291 typedef struct 292 { 293 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 294 uint8_t fifo_mode : 3; 295 uint8_t not_used0 : 1; 296 uint8_t odr_t_batch : 2; 297 uint8_t dec_ts_batch : 2; 298 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 299 uint8_t dec_ts_batch : 2; 300 uint8_t odr_t_batch : 2; 301 uint8_t not_used0 : 1; 302 uint8_t fifo_mode : 3; 303 #endif /* DRV_BYTE_ORDER */ 304 } lsm6dsv16b_fifo_ctrl4_t; 305 306 #define LSM6DSV16B_COUNTER_BDR_REG1 0x0BU 307 typedef struct 308 { 309 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 310 uint8_t cnt_bdr_th : 2; 311 uint8_t not_used0 : 3; 312 uint8_t trig_counter_bdr : 2; 313 uint8_t not_used1 : 1; 314 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 315 uint8_t not_used1 : 1; 316 uint8_t trig_counter_bdr : 2; 317 uint8_t not_used0 : 3; 318 uint8_t cnt_bdr_th : 2; 319 #endif /* DRV_BYTE_ORDER */ 320 } lsm6dsv16b_counter_bdr_reg1_t; 321 322 #define LSM6DSV16B_COUNTER_BDR_REG2 0x0CU 323 typedef struct 324 { 325 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 326 uint8_t cnt_bdr_th : 8; 327 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 328 uint8_t cnt_bdr_th : 8; 329 #endif /* DRV_BYTE_ORDER */ 330 } lsm6dsv16b_counter_bdr_reg2_t; 331 332 #define LSM6DSV16B_INT1_CTRL 0x0DU 333 typedef struct 334 { 335 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 336 uint8_t int1_drdy_xl : 1; 337 uint8_t int1_drdy_g : 1; 338 uint8_t not_used0 : 1; 339 uint8_t int1_fifo_th : 1; 340 uint8_t int1_fifo_ovr : 1; 341 uint8_t int1_fifo_full : 1; 342 uint8_t int1_cnt_bdr : 1; 343 uint8_t not_used1 : 1; 344 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 345 uint8_t not_used1 : 1; 346 uint8_t int1_cnt_bdr : 1; 347 uint8_t int1_fifo_full : 1; 348 uint8_t int1_fifo_ovr : 1; 349 uint8_t int1_fifo_th : 1; 350 uint8_t not_used0 : 1; 351 uint8_t int1_drdy_g : 1; 352 uint8_t int1_drdy_xl : 1; 353 #endif /* DRV_BYTE_ORDER */ 354 } lsm6dsv16b_int1_ctrl_t; 355 356 #define LSM6DSV16B_INT2_CTRL 0x0EU 357 typedef struct 358 { 359 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 360 uint8_t int2_drdy_xl : 1; 361 uint8_t int2_drdy_g : 1; 362 uint8_t not_used0 : 1; 363 uint8_t int2_fifo_th : 1; 364 uint8_t int2_fifo_ovr : 1; 365 uint8_t int2_fifo_full : 1; 366 uint8_t int2_cnt_bdr : 1; 367 uint8_t int2_emb_func_endop : 1; 368 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 369 uint8_t int2_emb_func_endop : 1; 370 uint8_t int2_cnt_bdr : 1; 371 uint8_t int2_fifo_full : 1; 372 uint8_t int2_fifo_ovr : 1; 373 uint8_t int2_fifo_th : 1; 374 uint8_t not_used0 : 1; 375 uint8_t int2_drdy_g : 1; 376 uint8_t int2_drdy_xl : 1; 377 #endif /* DRV_BYTE_ORDER */ 378 } lsm6dsv16b_int2_ctrl_t; 379 380 #define LSM6DSV16B_WHO_AM_I 0x0FU 381 typedef struct 382 { 383 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 384 uint8_t id : 8; 385 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 386 uint8_t id : 8; 387 #endif /* DRV_BYTE_ORDER */ 388 } lsm6dsv16b_who_am_i_t; 389 390 #define LSM6DSV16B_CTRL1 0x10U 391 typedef struct 392 { 393 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 394 uint8_t odr_xl : 4; 395 uint8_t op_mode_xl : 3; 396 uint8_t not_used0 : 1; 397 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 398 uint8_t not_used0 : 1; 399 uint8_t op_mode_xl : 3; 400 uint8_t odr_xl : 4; 401 #endif /* DRV_BYTE_ORDER */ 402 } lsm6dsv16b_ctrl1_t; 403 404 #define LSM6DSV16B_CTRL2 0x11U 405 typedef struct 406 { 407 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 408 uint8_t odr_g : 4; 409 uint8_t op_mode_g : 3; 410 uint8_t not_used0 : 1; 411 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 412 uint8_t not_used0 : 1; 413 uint8_t op_mode_g : 3; 414 uint8_t odr_g : 4; 415 #endif /* DRV_BYTE_ORDER */ 416 } lsm6dsv16b_ctrl2_t; 417 418 #define LSM6DSV16B_CTRL3 0x12U 419 typedef struct 420 { 421 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 422 uint8_t sw_reset : 1; 423 uint8_t not_used0 : 1; 424 uint8_t if_inc : 1; 425 uint8_t not_used1 : 3; 426 uint8_t bdu : 1; 427 uint8_t boot : 1; 428 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 429 uint8_t boot : 1; 430 uint8_t bdu : 1; 431 uint8_t not_used1 : 3; 432 uint8_t if_inc : 1; 433 uint8_t not_used0 : 1; 434 uint8_t sw_reset : 1; 435 #endif /* DRV_BYTE_ORDER */ 436 } lsm6dsv16b_ctrl3_t; 437 438 #define LSM6DSV16B_CTRL4 0x13U 439 typedef struct 440 { 441 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 442 uint8_t not_used1 : 1; 443 uint8_t drdy_pulsed : 1; 444 uint8_t int2_drdy_temp : 1; 445 uint8_t drdy_mask : 1; 446 uint8_t int2_on_int1 : 1; 447 uint8_t not_used0 : 3; 448 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 449 uint8_t not_used0 : 3; 450 uint8_t int2_on_int1 : 1; 451 uint8_t drdy_mask : 1; 452 uint8_t int2_drdy_temp : 1; 453 uint8_t drdy_pulsed : 1; 454 uint8_t not_used1 : 1; 455 #endif /* DRV_BYTE_ORDER */ 456 } lsm6dsv16b_ctrl4_t; 457 458 #define LSM6DSV16B_CTRL5 0x14U 459 typedef struct 460 { 461 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 462 uint8_t int_en_i3c : 1; 463 uint8_t bus_act_sel : 2; 464 uint8_t not_used0 : 5; 465 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 466 uint8_t not_used0 : 5; 467 uint8_t bus_act_sel : 2; 468 uint8_t int_en_i3c : 1; 469 #endif /* DRV_BYTE_ORDER */ 470 } lsm6dsv16b_ctrl5_t; 471 472 #define LSM6DSV16B_CTRL6 0x15U 473 typedef struct 474 { 475 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 476 uint8_t fs_g : 4; 477 uint8_t lpf1_g_bw : 3; 478 uint8_t not_used0 : 1; 479 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 480 uint8_t not_used0 : 1; 481 uint8_t lpf1_g_bw : 3; 482 uint8_t fs_g : 4; 483 #endif /* DRV_BYTE_ORDER */ 484 } lsm6dsv16b_ctrl6_t; 485 486 #define LSM6DSV16B_CTRL7 0x16U 487 typedef struct 488 { 489 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 490 uint8_t lpf1_g_en : 1; 491 uint8_t not_used0 : 7; 492 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 493 uint8_t not_used0 : 7; 494 uint8_t lpf1_g_en : 1; 495 #endif /* DRV_BYTE_ORDER */ 496 } lsm6dsv16b_ctrl7_t; 497 498 #define LSM6DSV16B_CTRL8 0x17U 499 typedef struct 500 { 501 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 502 uint8_t fs_xl : 2; 503 uint8_t not_used0 : 1; 504 uint8_t xl_dualc_en : 1; 505 uint8_t not_used1 : 1; 506 uint8_t hp_lpf2_xl_bw : 3; 507 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 508 uint8_t hp_lpf2_xl_bw : 3; 509 uint8_t not_used1 : 1; 510 uint8_t xl_dualc_en : 1; 511 uint8_t not_used0 : 1; 512 uint8_t fs_xl : 2; 513 #endif /* DRV_BYTE_ORDER */ 514 } lsm6dsv16b_ctrl8_t; 515 516 #define LSM6DSV16B_CTRL9 0x18U 517 typedef struct 518 { 519 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 520 uint8_t usr_off_on_out : 1; 521 uint8_t usr_off_w : 1; 522 uint8_t not_used0 : 1; 523 uint8_t lpf2_xl_en : 1; 524 uint8_t hp_slope_xl_en : 1; 525 uint8_t xl_fastsettl_mode : 1; 526 uint8_t hp_ref_mode_xl : 1; 527 uint8_t not_used1 : 1; 528 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 529 uint8_t not_used1 : 1; 530 uint8_t hp_ref_mode_xl : 1; 531 uint8_t xl_fastsettl_mode : 1; 532 uint8_t hp_slope_xl_en : 1; 533 uint8_t lpf2_xl_en : 1; 534 uint8_t not_used0 : 1; 535 uint8_t usr_off_w : 1; 536 uint8_t usr_off_on_out : 1; 537 #endif /* DRV_BYTE_ORDER */ 538 } lsm6dsv16b_ctrl9_t; 539 540 #define LSM6DSV16B_CTRL10 0x19U 541 typedef struct 542 { 543 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 544 uint8_t st_xl : 2; 545 uint8_t st_g : 2; 546 uint8_t xl_st_offset : 1; 547 uint8_t not_used1 : 1; 548 uint8_t emb_func_debug : 1; 549 uint8_t not_used0 : 1; 550 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 551 uint8_t not_used0 : 1; 552 uint8_t emb_func_debug : 1; 553 uint8_t not_used1 : 1; 554 uint8_t xl_st_offset : 1; 555 uint8_t st_g : 2; 556 uint8_t st_xl : 2; 557 #endif /* DRV_BYTE_ORDER */ 558 } lsm6dsv16b_ctrl10_t; 559 560 #define LSM6DSV16B_CTRL_STATUS 0x1AU 561 typedef struct 562 { 563 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 564 uint8_t not_used0 : 2; 565 uint8_t fsm_wr_ctrl_status : 1; 566 uint8_t not_used1 : 5; 567 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 568 uint8_t not_used1 : 5; 569 uint8_t fsm_wr_ctrl_status : 1; 570 uint8_t not_used0 : 2; 571 #endif /* DRV_BYTE_ORDER */ 572 } lsm6dsv16b_ctrl_status_t; 573 574 #define LSM6DSV16B_FIFO_STATUS1 0x1BU 575 typedef struct 576 { 577 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 578 uint8_t diff_fifo : 8; 579 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 580 uint8_t diff_fifo : 8; 581 #endif /* DRV_BYTE_ORDER */ 582 } lsm6dsv16b_fifo_status1_t; 583 584 #define LSM6DSV16B_FIFO_STATUS2 0x1CU 585 typedef struct 586 { 587 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 588 uint8_t diff_fifo : 1; 589 uint8_t not_used0 : 2; 590 uint8_t fifo_ovr_latched : 1; 591 uint8_t counter_bdr_ia : 1; 592 uint8_t fifo_full_ia : 1; 593 uint8_t fifo_ovr_ia : 1; 594 uint8_t fifo_wtm_ia : 1; 595 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 596 uint8_t fifo_wtm_ia : 1; 597 uint8_t fifo_ovr_ia : 1; 598 uint8_t fifo_full_ia : 1; 599 uint8_t counter_bdr_ia : 1; 600 uint8_t fifo_ovr_latched : 1; 601 uint8_t not_used0 : 2; 602 uint8_t diff_fifo : 1; 603 #endif /* DRV_BYTE_ORDER */ 604 } lsm6dsv16b_fifo_status2_t; 605 606 #define LSM6DSV16B_ALL_INT_SRC 0x1DU 607 typedef struct 608 { 609 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 610 uint8_t ff_ia : 1; 611 uint8_t wu_ia : 1; 612 uint8_t tap_ia : 1; 613 uint8_t not_used0 : 1; 614 uint8_t d6d_ia : 1; 615 uint8_t sleep_change_ia : 1; 616 uint8_t not_used1 : 1; 617 uint8_t emb_func_ia : 1; 618 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 619 uint8_t emb_func_ia : 1; 620 uint8_t not_used1 : 1; 621 uint8_t sleep_change_ia : 1; 622 uint8_t d6d_ia : 1; 623 uint8_t not_used0 : 1; 624 uint8_t tap_ia : 1; 625 uint8_t wu_ia : 1; 626 uint8_t ff_ia : 1; 627 #endif /* DRV_BYTE_ORDER */ 628 } lsm6dsv16b_all_int_src_t; 629 630 #define LSM6DSV16B_STATUS_REG 0x1EU 631 typedef struct 632 { 633 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 634 uint8_t xlda : 1; 635 uint8_t gda : 1; 636 uint8_t tda : 1; 637 uint8_t not_used0 : 4; 638 uint8_t timestamp_endcount : 1; 639 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 640 uint8_t timestamp_endcount : 1; 641 uint8_t not_used0 : 4; 642 uint8_t tda : 1; 643 uint8_t gda : 1; 644 uint8_t xlda : 1; 645 #endif /* DRV_BYTE_ORDER */ 646 } lsm6dsv16b_status_reg_t; 647 648 #define LSM6DSV16B_OUT_TEMP_L 0x20U 649 typedef struct 650 { 651 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 652 uint8_t temp : 8; 653 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 654 uint8_t temp : 8; 655 #endif /* DRV_BYTE_ORDER */ 656 } lsm6dsv16b_out_temp_l_t; 657 658 #define LSM6DSV16B_OUT_TEMP_H 0x21U 659 typedef struct 660 { 661 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 662 uint8_t temp : 8; 663 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 664 uint8_t temp : 8; 665 #endif /* DRV_BYTE_ORDER */ 666 } lsm6dsv16b_out_temp_h_t; 667 668 #define LSM6DSV16B_OUTX_L_G 0x22U 669 typedef struct 670 { 671 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 672 uint8_t outx_g : 8; 673 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 674 uint8_t outx_g : 8; 675 #endif /* DRV_BYTE_ORDER */ 676 } lsm6dsv16b_outx_l_g_t; 677 678 #define LSM6DSV16B_OUTX_H_G 0x23U 679 typedef struct 680 { 681 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 682 uint8_t outx_g : 8; 683 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 684 uint8_t outx_g : 8; 685 #endif /* DRV_BYTE_ORDER */ 686 } lsm6dsv16b_outx_h_g_t; 687 688 #define LSM6DSV16B_OUTY_L_G 0x24U 689 typedef struct 690 { 691 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 692 uint8_t outy_g : 8; 693 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 694 uint8_t outy_g : 8; 695 #endif /* DRV_BYTE_ORDER */ 696 } lsm6dsv16b_outy_l_g_t; 697 698 #define LSM6DSV16B_OUTY_H_G 0x25U 699 typedef struct 700 { 701 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 702 uint8_t outy_g : 8; 703 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 704 uint8_t outy_g : 8; 705 #endif /* DRV_BYTE_ORDER */ 706 } lsm6dsv16b_outy_h_g_t; 707 708 #define LSM6DSV16B_OUTZ_L_G 0x26U 709 typedef struct 710 { 711 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 712 uint8_t outz_g : 8; 713 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 714 uint8_t outz_g : 8; 715 #endif /* DRV_BYTE_ORDER */ 716 } lsm6dsv16b_outz_l_g_t; 717 718 #define LSM6DSV16B_OUTZ_H_G 0x27U 719 typedef struct 720 { 721 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 722 uint8_t outz_g : 8; 723 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 724 uint8_t outz_g : 8; 725 #endif /* DRV_BYTE_ORDER */ 726 } lsm6dsv16b_outz_h_g_t; 727 728 #define LSM6DSV16B_OUTZ_L_A 0x28U 729 typedef struct 730 { 731 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 732 uint8_t outz_a : 8; 733 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 734 uint8_t outz_a : 8; 735 #endif /* DRV_BYTE_ORDER */ 736 } lsm6dsv16b_outz_l_a_t; 737 738 #define LSM6DSV16B_OUTZ_H_A 0x29U 739 typedef struct 740 { 741 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 742 uint8_t outz_a : 8; 743 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 744 uint8_t outz_a : 8; 745 #endif /* DRV_BYTE_ORDER */ 746 } lsm6dsv16b_outz_h_a_t; 747 748 #define LSM6DSV16B_OUTY_L_A 0x2AU 749 typedef struct 750 { 751 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 752 uint8_t outy_a : 8; 753 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 754 uint8_t outy_a : 8; 755 #endif /* DRV_BYTE_ORDER */ 756 } lsm6dsv16b_outy_l_a_t; 757 758 #define LSM6DSV16B_OUTY_H_A 0x2BU 759 typedef struct 760 { 761 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 762 uint8_t outy_a : 8; 763 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 764 uint8_t outy_a : 8; 765 #endif /* DRV_BYTE_ORDER */ 766 } lsm6dsv16b_outy_h_a_t; 767 768 #define LSM6DSV16B_OUTX_L_A 0x2CU 769 typedef struct 770 { 771 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 772 uint8_t outx_a : 8; 773 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 774 uint8_t outx_a : 8; 775 #endif /* DRV_BYTE_ORDER */ 776 } lsm6dsv16b_outx_l_a_t; 777 778 #define LSM6DSV16B_OUTX_H_A 0x2DU 779 typedef struct 780 { 781 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 782 uint8_t outx_a : 8; 783 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 784 uint8_t outx_a : 8; 785 #endif /* DRV_BYTE_ORDER */ 786 } lsm6dsv16b_outx_h_a_t; 787 788 #define LSM6DSV16B_UI_OUTZ_L_A_DUALC 0x34U 789 typedef struct 790 { 791 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 792 uint8_t ui_outz_a_dualc : 8; 793 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 794 uint8_t ui_outz_a_dualc : 8; 795 #endif /* DRV_BYTE_ORDER */ 796 } lsm6dsv16b_ui_outz_l_a_dualc_t; 797 798 #define LSM6DSV16B_UI_OUTZ_H_A_DUALC 0x35U 799 typedef struct 800 { 801 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 802 uint8_t ui_outz_a_dualc : 8; 803 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 804 uint8_t ui_outz_a_dualc : 8; 805 #endif /* DRV_BYTE_ORDER */ 806 } lsm6dsv16b_ui_outz_h_a_dualc_t; 807 808 #define LSM6DSV16B_UI_OUTY_L_A_DUALC 0x36U 809 typedef struct 810 { 811 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 812 uint8_t ui_outy_a_dualc : 8; 813 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 814 uint8_t ui_outy_a_dualc : 8; 815 #endif /* DRV_BYTE_ORDER */ 816 } lsm6dsv16b_ui_outy_l_a_dualc_t; 817 818 #define LSM6DSV16B_UI_OUTY_H_A_DUALC 0x37U 819 typedef struct 820 { 821 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 822 uint8_t ui_outy_a_dualc : 8; 823 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 824 uint8_t ui_outy_a_dualc : 8; 825 #endif /* DRV_BYTE_ORDER */ 826 } lsm6dsv16b_ui_outy_h_a_dualc_t; 827 828 #define LSM6DSV16B_UI_OUTX_L_A_DUALC 0x38U 829 typedef struct 830 { 831 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 832 uint8_t ui_outx_a_dualc : 8; 833 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 834 uint8_t ui_outx_a_dualc : 8; 835 #endif /* DRV_BYTE_ORDER */ 836 } lsm6dsv16b_ui_outx_l_a_dualc_t; 837 838 #define LSM6DSV16B_UI_OUTX_H_A_DUALC 0x39U 839 typedef struct 840 { 841 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 842 uint8_t ui_outx_a_dualc : 8; 843 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 844 uint8_t ui_outx_a_dualc : 8; 845 #endif /* DRV_BYTE_ORDER */ 846 } lsm6dsv16b_ui_outx_h_a_dualc_t; 847 848 #define LSM6DSV16B_TIMESTAMP0 0x40U 849 typedef struct 850 { 851 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 852 uint8_t timestamp : 8; 853 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 854 uint8_t timestamp : 8; 855 #endif /* DRV_BYTE_ORDER */ 856 } lsm6dsv16b_timestamp0_t; 857 858 #define LSM6DSV16B_TIMESTAMP1 0x41U 859 typedef struct 860 { 861 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 862 uint8_t timestamp : 8; 863 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 864 uint8_t timestamp : 8; 865 #endif /* DRV_BYTE_ORDER */ 866 } lsm6dsv16b_timestamp1_t; 867 868 #define LSM6DSV16B_TIMESTAMP2 0x42U 869 typedef struct 870 { 871 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 872 uint8_t timestamp : 8; 873 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 874 uint8_t timestamp : 8; 875 #endif /* DRV_BYTE_ORDER */ 876 } lsm6dsv16b_timestamp2_t; 877 878 #define LSM6DSV16B_TIMESTAMP3 0x43U 879 typedef struct 880 { 881 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 882 uint8_t timestamp : 8; 883 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 884 uint8_t timestamp : 8; 885 #endif /* DRV_BYTE_ORDER */ 886 } lsm6dsv16b_timestamp3_t; 887 888 #define LSM6DSV16B_WAKE_UP_SRC 0x45U 889 typedef struct 890 { 891 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 892 uint8_t x_wu : 1; 893 uint8_t y_wu : 1; 894 uint8_t z_wu : 1; 895 uint8_t wu_ia : 1; 896 uint8_t sleep_state : 1; 897 uint8_t ff_ia : 1; 898 uint8_t sleep_change_ia : 1; 899 uint8_t not_used0 : 1; 900 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 901 uint8_t not_used0 : 1; 902 uint8_t sleep_change_ia : 1; 903 uint8_t ff_ia : 1; 904 uint8_t sleep_state : 1; 905 uint8_t wu_ia : 1; 906 uint8_t z_wu : 1; 907 uint8_t y_wu : 1; 908 uint8_t x_wu : 1; 909 #endif /* DRV_BYTE_ORDER */ 910 } lsm6dsv16b_wake_up_src_t; 911 912 #define LSM6DSV16B_TAP_SRC 0x46U 913 typedef struct 914 { 915 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 916 uint8_t x_tap : 1; 917 uint8_t y_tap : 1; 918 uint8_t z_tap : 1; 919 uint8_t tap_sign : 1; 920 uint8_t not_used0 : 1; 921 uint8_t double_tap : 1; 922 uint8_t single_tap : 1; 923 uint8_t tap_ia : 1; 924 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 925 uint8_t tap_ia : 1; 926 uint8_t single_tap : 1; 927 uint8_t double_tap : 1; 928 uint8_t not_used0 : 1; 929 uint8_t tap_sign : 1; 930 uint8_t z_tap : 1; 931 uint8_t y_tap : 1; 932 uint8_t x_tap : 1; 933 #endif /* DRV_BYTE_ORDER */ 934 } lsm6dsv16b_tap_src_t; 935 936 #define LSM6DSV16B_D6D_SRC 0x47U 937 typedef struct 938 { 939 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 940 uint8_t zl : 1; 941 uint8_t zh : 1; 942 uint8_t yl : 1; 943 uint8_t yh : 1; 944 uint8_t xl : 1; 945 uint8_t xh : 1; 946 uint8_t d6d_ia : 1; 947 uint8_t not_used0 : 1; 948 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 949 uint8_t not_used0 : 1; 950 uint8_t d6d_ia : 1; 951 uint8_t xh : 1; 952 uint8_t xl : 1; 953 uint8_t yh : 1; 954 uint8_t yl : 1; 955 uint8_t zh : 1; 956 uint8_t zl : 1; 957 #endif /* DRV_BYTE_ORDER */ 958 } lsm6dsv16b_d6d_src_t; 959 960 #define LSM6DSV16B_EMB_FUNC_STATUS_MAINPAGE 0x49U 961 typedef struct 962 { 963 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 964 uint8_t not_used0 : 3; 965 uint8_t is_step_det : 1; 966 uint8_t is_tilt : 1; 967 uint8_t is_sigmot : 1; 968 uint8_t not_used1 : 1; 969 uint8_t is_fsm_lc : 1; 970 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 971 uint8_t is_fsm_lc : 1; 972 uint8_t not_used1 : 1; 973 uint8_t is_sigmot : 1; 974 uint8_t is_tilt : 1; 975 uint8_t is_step_det : 1; 976 uint8_t not_used0 : 3; 977 #endif /* DRV_BYTE_ORDER */ 978 } lsm6dsv16b_emb_func_status_mainpage_t; 979 980 #define LSM6DSV16B_FSM_STATUS_MAINPAGE 0x4AU 981 typedef struct 982 { 983 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 984 uint8_t is_fsm1 : 1; 985 uint8_t is_fsm2 : 1; 986 uint8_t is_fsm3 : 1; 987 uint8_t is_fsm4 : 1; 988 uint8_t is_fsm5 : 1; 989 uint8_t is_fsm6 : 1; 990 uint8_t is_fsm7 : 1; 991 uint8_t is_fsm8 : 1; 992 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 993 uint8_t is_fsm8 : 1; 994 uint8_t is_fsm7 : 1; 995 uint8_t is_fsm6 : 1; 996 uint8_t is_fsm5 : 1; 997 uint8_t is_fsm4 : 1; 998 uint8_t is_fsm3 : 1; 999 uint8_t is_fsm2 : 1; 1000 uint8_t is_fsm1 : 1; 1001 #endif /* DRV_BYTE_ORDER */ 1002 } lsm6dsv16b_fsm_status_mainpage_t; 1003 1004 #define LSM6DSV16B_INTERNAL_FREQ 0x4FU 1005 typedef struct 1006 { 1007 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1008 uint8_t freq_fine : 8; 1009 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1010 uint8_t freq_fine : 8; 1011 #endif /* DRV_BYTE_ORDER */ 1012 } lsm6dsv16b_internal_freq_t; 1013 1014 #define LSM6DSV16B_FUNCTIONS_ENABLE 0x50U 1015 typedef struct 1016 { 1017 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1018 uint8_t inact_en : 2; 1019 uint8_t not_used0 : 1; 1020 uint8_t dis_rst_lir_all_int : 1; 1021 uint8_t not_used1 : 2; 1022 uint8_t timestamp_en : 1; 1023 uint8_t interrupts_enable : 1; 1024 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1025 uint8_t interrupts_enable : 1; 1026 uint8_t timestamp_en : 1; 1027 uint8_t not_used1 : 2; 1028 uint8_t dis_rst_lir_all_int : 1; 1029 uint8_t not_used0 : 1; 1030 uint8_t inact_en : 2; 1031 #endif /* DRV_BYTE_ORDER */ 1032 } lsm6dsv16b_functions_enable_t; 1033 1034 #define LSM6DSV16B_INACTIVITY_DUR 0x54U 1035 typedef struct 1036 { 1037 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1038 uint8_t inact_dur : 2; 1039 uint8_t xl_inact_odr : 2; 1040 uint8_t wu_inact_ths_w : 3; 1041 uint8_t sleep_status_on_int : 1; 1042 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1043 uint8_t sleep_status_on_int : 1; 1044 uint8_t wu_inact_ths_w : 3; 1045 uint8_t xl_inact_odr : 2; 1046 uint8_t inact_dur : 2; 1047 #endif /* DRV_BYTE_ORDER */ 1048 } lsm6dsv16b_inactivity_dur_t; 1049 1050 #define LSM6DSV16B_INACTIVITY_THS 0x55U 1051 typedef struct 1052 { 1053 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1054 uint8_t inact_ths : 6; 1055 uint8_t not_used0 : 2; 1056 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1057 uint8_t not_used0 : 2; 1058 uint8_t inact_ths : 6; 1059 #endif /* DRV_BYTE_ORDER */ 1060 } lsm6dsv16b_inactivity_ths_t; 1061 1062 #define LSM6DSV16B_TAP_CFG0 0x56U 1063 typedef struct 1064 { 1065 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1066 uint8_t lir : 1; 1067 uint8_t tap_x_en : 1; 1068 uint8_t tap_y_en : 1; 1069 uint8_t tap_z_en : 1; 1070 uint8_t slope_fds : 1; 1071 uint8_t hw_func_mask_xl_settl : 1; 1072 uint8_t low_pass_on_6d : 1; 1073 uint8_t not_used1 : 1; 1074 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1075 uint8_t not_used1 : 1; 1076 uint8_t low_pass_on_6d : 1; 1077 uint8_t hw_func_mask_xl_settl : 1; 1078 uint8_t slope_fds : 1; 1079 uint8_t tap_z_en : 1; 1080 uint8_t tap_y_en : 1; 1081 uint8_t tap_x_en : 1; 1082 uint8_t lir : 1; 1083 #endif /* DRV_BYTE_ORDER */ 1084 } lsm6dsv16b_tap_cfg0_t; 1085 1086 #define LSM6DSV16B_TAP_CFG1 0x57U 1087 typedef struct 1088 { 1089 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1090 uint8_t tap_ths_z : 5; 1091 uint8_t tap_priority : 3; 1092 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1093 uint8_t tap_priority : 3; 1094 uint8_t tap_ths_z : 5; 1095 #endif /* DRV_BYTE_ORDER */ 1096 } lsm6dsv16b_tap_cfg1_t; 1097 1098 #define LSM6DSV16B_TAP_CFG2 0x58U 1099 typedef struct 1100 { 1101 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1102 uint8_t tap_ths_y : 5; 1103 uint8_t not_used0 : 3; 1104 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1105 uint8_t not_used0 : 3; 1106 uint8_t tap_ths_y : 5; 1107 #endif /* DRV_BYTE_ORDER */ 1108 } lsm6dsv16b_tap_cfg2_t; 1109 1110 #define LSM6DSV16B_TAP_THS_6D 0x59U 1111 typedef struct 1112 { 1113 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1114 uint8_t tap_ths_x : 5; 1115 uint8_t sixd_ths : 2; 1116 uint8_t not_used0 : 1; 1117 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1118 uint8_t not_used0 : 1; 1119 uint8_t sixd_ths : 2; 1120 uint8_t tap_ths_x : 5; 1121 #endif /* DRV_BYTE_ORDER */ 1122 } lsm6dsv16b_tap_ths_6d_t; 1123 1124 #define LSM6DSV16B_TAP_DUR 0x5AU 1125 typedef struct 1126 { 1127 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1128 uint8_t shock : 2; 1129 uint8_t quiet : 2; 1130 uint8_t dur : 4; 1131 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1132 uint8_t dur : 4; 1133 uint8_t quiet : 2; 1134 uint8_t shock : 2; 1135 #endif /* DRV_BYTE_ORDER */ 1136 } lsm6dsv16b_tap_dur_t; 1137 1138 #define LSM6DSV16B_WAKE_UP_THS 0x5BU 1139 typedef struct 1140 { 1141 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1142 uint8_t wk_ths : 6; 1143 uint8_t usr_off_on_wu : 1; 1144 uint8_t single_double_tap : 1; 1145 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1146 uint8_t single_double_tap : 1; 1147 uint8_t usr_off_on_wu : 1; 1148 uint8_t wk_ths : 6; 1149 #endif /* DRV_BYTE_ORDER */ 1150 } lsm6dsv16b_wake_up_ths_t; 1151 1152 #define LSM6DSV16B_WAKE_UP_DUR 0x5CU 1153 typedef struct 1154 { 1155 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1156 uint8_t sleep_dur : 4; 1157 uint8_t not_used0 : 1; 1158 uint8_t wake_dur : 2; 1159 uint8_t ff_dur : 1; 1160 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1161 uint8_t ff_dur : 1; 1162 uint8_t wake_dur : 2; 1163 uint8_t not_used0 : 1; 1164 uint8_t sleep_dur : 4; 1165 #endif /* DRV_BYTE_ORDER */ 1166 } lsm6dsv16b_wake_up_dur_t; 1167 1168 #define LSM6DSV16B_FREE_FALL 0x5DU 1169 typedef struct 1170 { 1171 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1172 uint8_t ff_ths : 3; 1173 uint8_t ff_dur : 5; 1174 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1175 uint8_t ff_dur : 5; 1176 uint8_t ff_ths : 3; 1177 #endif /* DRV_BYTE_ORDER */ 1178 } lsm6dsv16b_free_fall_t; 1179 1180 #define LSM6DSV16B_MD1_CFG 0x5EU 1181 typedef struct 1182 { 1183 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1184 uint8_t not_used0 : 1; 1185 uint8_t int1_emb_func : 1; 1186 uint8_t int1_6d : 1; 1187 uint8_t int1_double_tap : 1; 1188 uint8_t int1_ff : 1; 1189 uint8_t int1_wu : 1; 1190 uint8_t int1_single_tap : 1; 1191 uint8_t int1_sleep_change : 1; 1192 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1193 uint8_t int1_sleep_change : 1; 1194 uint8_t int1_single_tap : 1; 1195 uint8_t int1_wu : 1; 1196 uint8_t int1_ff : 1; 1197 uint8_t int1_double_tap : 1; 1198 uint8_t int1_6d : 1; 1199 uint8_t int1_emb_func : 1; 1200 uint8_t not_used0 : 1; 1201 #endif /* DRV_BYTE_ORDER */ 1202 } lsm6dsv16b_md1_cfg_t; 1203 1204 #define LSM6DSV16B_MD2_CFG 0x5FU 1205 typedef struct 1206 { 1207 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1208 uint8_t int2_timestamp : 1; 1209 uint8_t int2_emb_func : 1; 1210 uint8_t int2_6d : 1; 1211 uint8_t int2_double_tap : 1; 1212 uint8_t int2_ff : 1; 1213 uint8_t int2_wu : 1; 1214 uint8_t int2_single_tap : 1; 1215 uint8_t int2_sleep_change : 1; 1216 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1217 uint8_t int2_sleep_change : 1; 1218 uint8_t int2_single_tap : 1; 1219 uint8_t int2_wu : 1; 1220 uint8_t int2_ff : 1; 1221 uint8_t int2_double_tap : 1; 1222 uint8_t int2_6d : 1; 1223 uint8_t int2_emb_func : 1; 1224 uint8_t int2_timestamp : 1; 1225 #endif /* DRV_BYTE_ORDER */ 1226 } lsm6dsv16b_md2_cfg_t; 1227 1228 #define LSM6DSV16B_EMB_FUNC_CFG 0x63U 1229 typedef struct 1230 { 1231 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1232 uint8_t not_used0 : 3; 1233 uint8_t emb_func_disable : 1; 1234 uint8_t emb_func_irq_mask_xl_settl : 1; 1235 uint8_t emb_func_irq_mask_g_settl : 1; 1236 uint8_t not_used1 : 1; 1237 uint8_t xl_dualc_batch_from_if : 1; 1238 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1239 uint8_t xl_dualc_batch_from_if : 1; 1240 uint8_t not_used1 : 1; 1241 uint8_t emb_func_irq_mask_g_settl : 1; 1242 uint8_t emb_func_irq_mask_xl_settl : 1; 1243 uint8_t emb_func_disable : 1; 1244 uint8_t not_used0 : 3; 1245 #endif /* DRV_BYTE_ORDER */ 1246 } lsm6dsv16b_emb_func_cfg_t; 1247 1248 #define LSM6DSV16B_TDM_CFG0 0x6CU 1249 typedef struct 1250 { 1251 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1252 uint8_t tdm_wclk_bclk_sel : 1; 1253 uint8_t tdm_wclk : 2; 1254 uint8_t not_used0 : 1; 1255 uint8_t tdm_slot_sel : 1; 1256 uint8_t tdm_bclk_edge_sel : 1; 1257 uint8_t tdm_delayed_cfg : 1; 1258 uint8_t not_used1 : 1; 1259 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1260 uint8_t not_used1 : 1; 1261 uint8_t tdm_delayed_cfg : 1; 1262 uint8_t tdm_bclk_edge_sel : 1; 1263 uint8_t tdm_slot_sel : 1; 1264 uint8_t not_used0 : 1; 1265 uint8_t tdm_wclk : 2; 1266 uint8_t tdm_wclk_bclk_sel : 1; 1267 #endif /* DRV_BYTE_ORDER */ 1268 } lsm6dsv16b_tdm_cfg0_t; 1269 1270 #define LSM6DSV16B_TDM_CFG1 0x6DU 1271 typedef struct 1272 { 1273 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1274 uint8_t not_used0 : 3; 1275 uint8_t tdm_axes_ord_sel : 2; 1276 uint8_t tdm_xl_z_en : 1; 1277 uint8_t tdm_xl_y_en : 1; 1278 uint8_t tdm_xl_x_en : 1; 1279 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1280 uint8_t tdm_xl_x_en : 1; 1281 uint8_t tdm_xl_y_en : 1; 1282 uint8_t tdm_xl_z_en : 1; 1283 uint8_t tdm_axes_ord_sel : 2; 1284 uint8_t not_used0 : 3; 1285 #endif /* DRV_BYTE_ORDER */ 1286 } lsm6dsv16b_tdm_cfg1_t; 1287 1288 #define LSM6DSV16B_TDM_CFG2 0x6EU 1289 typedef struct 1290 { 1291 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1292 uint8_t tdm_fs_xl : 2; 1293 uint8_t not_used0 : 1; 1294 uint8_t tdm_data_mask : 1; 1295 uint8_t not_used1 : 4; 1296 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1297 uint8_t not_used1 : 4; 1298 uint8_t tdm_data_mask : 1; 1299 uint8_t not_used0 : 1; 1300 uint8_t tdm_fs_xl : 2; 1301 #endif /* DRV_BYTE_ORDER */ 1302 } lsm6dsv16b_tdm_cfg2_t; 1303 1304 #define LSM6DSV16B_Z_OFS_USR 0x73U 1305 typedef struct 1306 { 1307 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1308 uint8_t z_ofs_usr : 8; 1309 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1310 uint8_t z_ofs_usr : 8; 1311 #endif /* DRV_BYTE_ORDER */ 1312 } lsm6dsv16b_z_ofs_usr_t; 1313 1314 #define LSM6DSV16B_Y_OFS_USR 0x74U 1315 typedef struct 1316 { 1317 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1318 uint8_t y_ofs_usr : 8; 1319 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1320 uint8_t y_ofs_usr : 8; 1321 #endif /* DRV_BYTE_ORDER */ 1322 } lsm6dsv16b_y_ofs_usr_t; 1323 1324 #define LSM6DSV16B_X_OFS_USR 0x75U 1325 typedef struct 1326 { 1327 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1328 uint8_t x_ofs_usr : 8; 1329 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1330 uint8_t x_ofs_usr : 8; 1331 #endif /* DRV_BYTE_ORDER */ 1332 } lsm6dsv16b_x_ofs_usr_t; 1333 1334 #define LSM6DSV16B_FIFO_DATA_OUT_TAG 0x78U 1335 typedef struct 1336 { 1337 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1338 uint8_t not_used0 : 1; 1339 uint8_t tag_cnt : 2; 1340 uint8_t tag_sensor : 5; 1341 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1342 uint8_t tag_sensor : 5; 1343 uint8_t tag_cnt : 2; 1344 uint8_t not_used0 : 1; 1345 #endif /* DRV_BYTE_ORDER */ 1346 } lsm6dsv16b_fifo_data_out_tag_t; 1347 1348 #define LSM6DSV16B_FIFO_DATA_OUT_BYTE_0 0x79U 1349 typedef struct 1350 { 1351 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1352 uint8_t fifo_data_out : 8; 1353 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1354 uint8_t fifo_data_out : 8; 1355 #endif /* DRV_BYTE_ORDER */ 1356 } lsm6dsv16b_fifo_data_out_byte_0_t; 1357 1358 #define LSM6DSV16B_FIFO_DATA_OUT_BYTE_1 0x7AU 1359 typedef struct 1360 { 1361 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1362 uint8_t fifo_data_out : 8; 1363 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1364 uint8_t fifo_data_out : 8; 1365 #endif /* DRV_BYTE_ORDER */ 1366 } lsm6dsv16b_fifo_data_out_byte_1_t; 1367 1368 #define LSM6DSV16B_FIFO_DATA_OUT_BYTE_2 0x7BU 1369 typedef struct 1370 { 1371 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1372 uint8_t fifo_data_out : 8; 1373 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1374 uint8_t fifo_data_out : 8; 1375 #endif /* DRV_BYTE_ORDER */ 1376 } lsm6dsv16b_fifo_data_out_byte_2_t; 1377 1378 #define LSM6DSV16B_FIFO_DATA_OUT_BYTE_3 0x7CU 1379 typedef struct 1380 { 1381 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1382 uint8_t fifo_data_out : 8; 1383 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1384 uint8_t fifo_data_out : 8; 1385 #endif /* DRV_BYTE_ORDER */ 1386 } lsm6dsv16b_fifo_data_out_byte_3_t; 1387 1388 #define LSM6DSV16B_FIFO_DATA_OUT_BYTE_4 0x7DU 1389 typedef struct 1390 { 1391 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1392 uint8_t fifo_data_out : 8; 1393 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1394 uint8_t fifo_data_out : 8; 1395 #endif /* DRV_BYTE_ORDER */ 1396 } lsm6dsv16b_fifo_data_out_byte_4_t; 1397 1398 #define LSM6DSV16B_FIFO_DATA_OUT_BYTE_5 0x7EU 1399 typedef struct 1400 { 1401 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1402 uint8_t fifo_data_out : 8; 1403 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1404 uint8_t fifo_data_out : 8; 1405 #endif /* DRV_BYTE_ORDER */ 1406 } lsm6dsv16b_fifo_data_out_byte_5_t; 1407 1408 /** 1409 * @} 1410 * 1411 */ 1412 1413 /** @defgroup bitfields page embedded 1414 * @{ 1415 * 1416 */ 1417 1418 #define LSM6DSV16B_PAGE_SEL 0x2U 1419 typedef struct 1420 { 1421 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1422 uint8_t not_used0 : 4; 1423 uint8_t page_sel : 4; 1424 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1425 uint8_t page_sel : 4; 1426 uint8_t not_used0 : 4; 1427 #endif /* DRV_BYTE_ORDER */ 1428 } lsm6dsv16b_page_sel_t; 1429 1430 #define LSM6DSV16B_EMB_FUNC_EN_A 0x4U 1431 typedef struct 1432 { 1433 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1434 uint8_t not_used2 : 1; 1435 uint8_t sflp_game_en : 1; 1436 uint8_t not_used0 : 1; 1437 uint8_t pedo_en : 1; 1438 uint8_t tilt_en : 1; 1439 uint8_t sign_motion_en : 1; 1440 uint8_t not_used1 : 2; 1441 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1442 uint8_t not_used1 : 2; 1443 uint8_t sign_motion_en : 1; 1444 uint8_t tilt_en : 1; 1445 uint8_t pedo_en : 1; 1446 uint8_t not_used0 : 1; 1447 uint8_t sflp_game_en : 1; 1448 uint8_t not_used2 : 1; 1449 #endif /* DRV_BYTE_ORDER */ 1450 } lsm6dsv16b_emb_func_en_a_t; 1451 1452 #define LSM6DSV16B_EMB_FUNC_EN_B 0x5U 1453 typedef struct 1454 { 1455 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1456 uint8_t fsm_en : 1; 1457 uint8_t not_used0 : 2; 1458 uint8_t fifo_compr_en : 1; 1459 uint8_t not_used1 : 4; 1460 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1461 uint8_t not_used1 : 4; 1462 uint8_t fifo_compr_en : 1; 1463 uint8_t not_used0 : 2; 1464 uint8_t fsm_en : 1; 1465 #endif /* DRV_BYTE_ORDER */ 1466 } lsm6dsv16b_emb_func_en_b_t; 1467 1468 #define LSM6DSV16B_EMB_FUNC_EXEC_STATUS 0x7U 1469 typedef struct 1470 { 1471 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1472 uint8_t emb_func_endop : 1; 1473 uint8_t emb_func_exec_ovr : 1; 1474 uint8_t not_used0 : 6; 1475 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1476 uint8_t not_used0 : 6; 1477 uint8_t emb_func_exec_ovr : 1; 1478 uint8_t emb_func_endop : 1; 1479 #endif /* DRV_BYTE_ORDER */ 1480 } lsm6dsv16b_emb_func_exec_status_t; 1481 1482 #define LSM6DSV16B_PAGE_ADDRESS 0x8U 1483 typedef struct 1484 { 1485 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1486 uint8_t page_addr : 8; 1487 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1488 uint8_t page_addr : 8; 1489 #endif /* DRV_BYTE_ORDER */ 1490 } lsm6dsv16b_page_address_t; 1491 1492 #define LSM6DSV16B_PAGE_VALUE 0x9U 1493 typedef struct 1494 { 1495 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1496 uint8_t page_value : 8; 1497 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1498 uint8_t page_value : 8; 1499 #endif /* DRV_BYTE_ORDER */ 1500 } lsm6dsv16b_page_value_t; 1501 1502 #define LSM6DSV16B_EMB_FUNC_INT1 0x0AU 1503 typedef struct 1504 { 1505 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1506 uint8_t not_used0 : 3; 1507 uint8_t int1_step_detector : 1; 1508 uint8_t int1_tilt : 1; 1509 uint8_t int1_sig_mot : 1; 1510 uint8_t not_used1 : 1; 1511 uint8_t int1_fsm_lc : 1; 1512 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1513 uint8_t int1_fsm_lc : 1; 1514 uint8_t not_used1 : 1; 1515 uint8_t int1_sig_mot : 1; 1516 uint8_t int1_tilt : 1; 1517 uint8_t int1_step_detector : 1; 1518 uint8_t not_used0 : 3; 1519 #endif /* DRV_BYTE_ORDER */ 1520 } lsm6dsv16b_emb_func_int1_t; 1521 1522 #define LSM6DSV16B_FSM_INT1 0x0BU 1523 typedef struct 1524 { 1525 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1526 uint8_t int1_fsm1 : 1; 1527 uint8_t int1_fsm2 : 1; 1528 uint8_t int1_fsm3 : 1; 1529 uint8_t int1_fsm4 : 1; 1530 uint8_t int1_fsm5 : 1; 1531 uint8_t int1_fsm6 : 1; 1532 uint8_t int1_fsm7 : 1; 1533 uint8_t int1_fsm8 : 1; 1534 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1535 uint8_t int1_fsm8 : 1; 1536 uint8_t int1_fsm7 : 1; 1537 uint8_t int1_fsm6 : 1; 1538 uint8_t int1_fsm5 : 1; 1539 uint8_t int1_fsm4 : 1; 1540 uint8_t int1_fsm3 : 1; 1541 uint8_t int1_fsm2 : 1; 1542 uint8_t int1_fsm1 : 1; 1543 #endif /* DRV_BYTE_ORDER */ 1544 } lsm6dsv16b_fsm_int1_t; 1545 1546 #define LSM6DSV16B_EMB_FUNC_INT2 0x0EU 1547 typedef struct 1548 { 1549 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1550 uint8_t not_used0 : 3; 1551 uint8_t int2_step_detector : 1; 1552 uint8_t int2_tilt : 1; 1553 uint8_t int2_sig_mot : 1; 1554 uint8_t not_used1 : 1; 1555 uint8_t int2_fsm_lc : 1; 1556 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1557 uint8_t int2_fsm_lc : 1; 1558 uint8_t not_used1 : 1; 1559 uint8_t int2_sig_mot : 1; 1560 uint8_t int2_tilt : 1; 1561 uint8_t int2_step_detector : 1; 1562 uint8_t not_used0 : 3; 1563 #endif /* DRV_BYTE_ORDER */ 1564 } lsm6dsv16b_emb_func_int2_t; 1565 1566 #define LSM6DSV16B_FSM_INT2 0x0FU 1567 typedef struct 1568 { 1569 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1570 uint8_t int2_fsm1 : 1; 1571 uint8_t int2_fsm2 : 1; 1572 uint8_t int2_fsm3 : 1; 1573 uint8_t int2_fsm4 : 1; 1574 uint8_t int2_fsm5 : 1; 1575 uint8_t int2_fsm6 : 1; 1576 uint8_t int2_fsm7 : 1; 1577 uint8_t int2_fsm8 : 1; 1578 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1579 uint8_t int2_fsm8 : 1; 1580 uint8_t int2_fsm7 : 1; 1581 uint8_t int2_fsm6 : 1; 1582 uint8_t int2_fsm5 : 1; 1583 uint8_t int2_fsm4 : 1; 1584 uint8_t int2_fsm3 : 1; 1585 uint8_t int2_fsm2 : 1; 1586 uint8_t int2_fsm1 : 1; 1587 #endif /* DRV_BYTE_ORDER */ 1588 } lsm6dsv16b_fsm_int2_t; 1589 1590 #define LSM6DSV16B_EMB_FUNC_STATUS 0x12U 1591 typedef struct 1592 { 1593 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1594 uint8_t not_used0 : 3; 1595 uint8_t is_step_det : 1; 1596 uint8_t is_tilt : 1; 1597 uint8_t is_sigmot : 1; 1598 uint8_t not_used1 : 1; 1599 uint8_t is_fsm_lc : 1; 1600 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1601 uint8_t is_fsm_lc : 1; 1602 uint8_t not_used1 : 1; 1603 uint8_t is_sigmot : 1; 1604 uint8_t is_tilt : 1; 1605 uint8_t is_step_det : 1; 1606 uint8_t not_used0 : 3; 1607 #endif /* DRV_BYTE_ORDER */ 1608 } lsm6dsv16b_emb_func_status_t; 1609 1610 #define LSM6DSV16B_FSM_STATUS 0x13U 1611 typedef struct 1612 { 1613 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1614 uint8_t is_fsm1 : 1; 1615 uint8_t is_fsm2 : 1; 1616 uint8_t is_fsm3 : 1; 1617 uint8_t is_fsm4 : 1; 1618 uint8_t is_fsm5 : 1; 1619 uint8_t is_fsm6 : 1; 1620 uint8_t is_fsm7 : 1; 1621 uint8_t is_fsm8 : 1; 1622 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1623 uint8_t is_fsm8 : 1; 1624 uint8_t is_fsm7 : 1; 1625 uint8_t is_fsm6 : 1; 1626 uint8_t is_fsm5 : 1; 1627 uint8_t is_fsm4 : 1; 1628 uint8_t is_fsm3 : 1; 1629 uint8_t is_fsm2 : 1; 1630 uint8_t is_fsm1 : 1; 1631 #endif /* DRV_BYTE_ORDER */ 1632 } lsm6dsv16b_fsm_status_t; 1633 1634 #define LSM6DSV16B_PAGE_RW 0x17U 1635 typedef struct 1636 { 1637 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1638 uint8_t not_used0 : 5; 1639 uint8_t page_read : 1; 1640 uint8_t page_write : 1; 1641 uint8_t emb_func_lir : 1; 1642 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1643 uint8_t emb_func_lir : 1; 1644 uint8_t page_write : 1; 1645 uint8_t page_read : 1; 1646 uint8_t not_used0 : 5; 1647 #endif /* DRV_BYTE_ORDER */ 1648 } lsm6dsv16b_page_rw_t; 1649 1650 #define LSM6DSV16B_EMB_FUNC_FIFO_EN_A 0x44U 1651 typedef struct 1652 { 1653 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1654 uint8_t not_used0 : 1; 1655 uint8_t sflp_game_fifo_en : 1; 1656 uint8_t not_used1 : 2; 1657 uint8_t sflp_gravity_fifo_en : 1; 1658 uint8_t sflp_gbias_fifo_en : 1; 1659 uint8_t step_counter_fifo_en : 1; 1660 uint8_t not_used2 : 1; 1661 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1662 uint8_t not_used2 : 1; 1663 uint8_t step_counter_fifo_en : 1; 1664 uint8_t sflp_gbias_fifo_en : 1; 1665 uint8_t sflp_gravity_fifo_en : 1; 1666 uint8_t not_used1 : 2; 1667 uint8_t sflp_game_fifo_en : 1; 1668 uint8_t not_used0 : 1; 1669 #endif /* DRV_BYTE_ORDER */ 1670 } lsm6dsv16b_emb_func_fifo_en_a_t; 1671 1672 #define LSM6DSV16B_FSM_ENABLE 0x46U 1673 typedef struct 1674 { 1675 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1676 uint8_t fsm1_en : 1; 1677 uint8_t fsm2_en : 1; 1678 uint8_t fsm3_en : 1; 1679 uint8_t fsm4_en : 1; 1680 uint8_t fsm5_en : 1; 1681 uint8_t fsm6_en : 1; 1682 uint8_t fsm7_en : 1; 1683 uint8_t fsm8_en : 1; 1684 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1685 uint8_t fsm8_en : 1; 1686 uint8_t fsm7_en : 1; 1687 uint8_t fsm6_en : 1; 1688 uint8_t fsm5_en : 1; 1689 uint8_t fsm4_en : 1; 1690 uint8_t fsm3_en : 1; 1691 uint8_t fsm2_en : 1; 1692 uint8_t fsm1_en : 1; 1693 #endif /* DRV_BYTE_ORDER */ 1694 } lsm6dsv16b_fsm_enable_t; 1695 1696 #define LSM6DSV16B_FSM_LONG_COUNTER_L 0x48U 1697 typedef struct 1698 { 1699 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1700 uint8_t fsm_lc : 8; 1701 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1702 uint8_t fsm_lc : 8; 1703 #endif /* DRV_BYTE_ORDER */ 1704 } lsm6dsv16b_fsm_long_counter_l_t; 1705 1706 #define LSM6DSV16B_FSM_LONG_COUNTER_H 0x49U 1707 typedef struct 1708 { 1709 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1710 uint8_t fsm_lc : 8; 1711 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1712 uint8_t fsm_lc : 8; 1713 #endif /* DRV_BYTE_ORDER */ 1714 } lsm6dsv16b_fsm_long_counter_h_t; 1715 1716 #define LSM6DSV16B_INT_ACK_MASK 0x4BU 1717 typedef struct 1718 { 1719 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1720 uint8_t iack_mask : 8; 1721 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1722 uint8_t iack_mask : 8; 1723 #endif /* DRV_BYTE_ORDER */ 1724 } lsm6dsv16b_int_ack_mask_t; 1725 1726 #define LSM6DSV16B_FSM_OUTS1 0x4CU 1727 typedef struct 1728 { 1729 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1730 uint8_t fsm1_n_v : 1; 1731 uint8_t fsm1_p_v : 1; 1732 uint8_t fsm1_n_3 : 1; 1733 uint8_t fsm1_p_3 : 1; 1734 uint8_t fsm1_n_2 : 1; 1735 uint8_t fsm1_p_2 : 1; 1736 uint8_t fsm1_n_1 : 1; 1737 uint8_t fsm1_p_1 : 1; 1738 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1739 uint8_t fsm1_p_1 : 1; 1740 uint8_t fsm1_n_1 : 1; 1741 uint8_t fsm1_p_2 : 1; 1742 uint8_t fsm1_n_2 : 1; 1743 uint8_t fsm1_p_3 : 1; 1744 uint8_t fsm1_n_3 : 1; 1745 uint8_t fsm1_p_v : 1; 1746 uint8_t fsm1_n_v : 1; 1747 #endif /* DRV_BYTE_ORDER */ 1748 } lsm6dsv16b_fsm_outs1_t; 1749 1750 #define LSM6DSV16B_FSM_OUTS2 0x4DU 1751 typedef struct 1752 { 1753 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1754 uint8_t fsm2_n_v : 1; 1755 uint8_t fsm2_p_v : 1; 1756 uint8_t fsm2_n_3 : 1; 1757 uint8_t fsm2_p_3 : 1; 1758 uint8_t fsm2_n_2 : 1; 1759 uint8_t fsm2_p_2 : 1; 1760 uint8_t fsm2_n_1 : 1; 1761 uint8_t fsm2_p_1 : 1; 1762 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1763 uint8_t fsm2_p_1 : 1; 1764 uint8_t fsm2_n_1 : 1; 1765 uint8_t fsm2_p_2 : 1; 1766 uint8_t fsm2_n_2 : 1; 1767 uint8_t fsm2_p_3 : 1; 1768 uint8_t fsm2_n_3 : 1; 1769 uint8_t fsm2_p_v : 1; 1770 uint8_t fsm2_n_v : 1; 1771 #endif /* DRV_BYTE_ORDER */ 1772 } lsm6dsv16b_fsm_outs2_t; 1773 1774 #define LSM6DSV16B_FSM_OUTS3 0x4EU 1775 typedef struct 1776 { 1777 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1778 uint8_t fsm3_n_v : 1; 1779 uint8_t fsm3_p_v : 1; 1780 uint8_t fsm3_n_3 : 1; 1781 uint8_t fsm3_p_3 : 1; 1782 uint8_t fsm3_n_2 : 1; 1783 uint8_t fsm3_p_2 : 1; 1784 uint8_t fsm3_n_1 : 1; 1785 uint8_t fsm3_p_1 : 1; 1786 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1787 uint8_t fsm3_p_1 : 1; 1788 uint8_t fsm3_n_1 : 1; 1789 uint8_t fsm3_p_2 : 1; 1790 uint8_t fsm3_n_2 : 1; 1791 uint8_t fsm3_p_3 : 1; 1792 uint8_t fsm3_n_3 : 1; 1793 uint8_t fsm3_p_v : 1; 1794 uint8_t fsm3_n_v : 1; 1795 #endif /* DRV_BYTE_ORDER */ 1796 } lsm6dsv16b_fsm_outs3_t; 1797 1798 #define LSM6DSV16B_FSM_OUTS4 0x4FU 1799 typedef struct 1800 { 1801 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1802 uint8_t fsm4_n_v : 1; 1803 uint8_t fsm4_p_v : 1; 1804 uint8_t fsm4_n_3 : 1; 1805 uint8_t fsm4_p_3 : 1; 1806 uint8_t fsm4_n_2 : 1; 1807 uint8_t fsm4_p_2 : 1; 1808 uint8_t fsm4_n_1 : 1; 1809 uint8_t fsm4_p_1 : 1; 1810 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1811 uint8_t fsm4_p_1 : 1; 1812 uint8_t fsm4_n_1 : 1; 1813 uint8_t fsm4_p_2 : 1; 1814 uint8_t fsm4_n_2 : 1; 1815 uint8_t fsm4_p_3 : 1; 1816 uint8_t fsm4_n_3 : 1; 1817 uint8_t fsm4_p_v : 1; 1818 uint8_t fsm4_n_v : 1; 1819 #endif /* DRV_BYTE_ORDER */ 1820 } lsm6dsv16b_fsm_outs4_t; 1821 1822 #define LSM6DSV16B_FSM_OUTS5 0x50U 1823 typedef struct 1824 { 1825 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1826 uint8_t fsm5_n_v : 1; 1827 uint8_t fsm5_p_v : 1; 1828 uint8_t fsm5_n_3 : 1; 1829 uint8_t fsm5_p_3 : 1; 1830 uint8_t fsm5_n_2 : 1; 1831 uint8_t fsm5_p_2 : 1; 1832 uint8_t fsm5_n_1 : 1; 1833 uint8_t fsm5_p_1 : 1; 1834 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1835 uint8_t fsm5_p_1 : 1; 1836 uint8_t fsm5_n_1 : 1; 1837 uint8_t fsm5_p_2 : 1; 1838 uint8_t fsm5_n_2 : 1; 1839 uint8_t fsm5_p_3 : 1; 1840 uint8_t fsm5_n_3 : 1; 1841 uint8_t fsm5_p_v : 1; 1842 uint8_t fsm5_n_v : 1; 1843 #endif /* DRV_BYTE_ORDER */ 1844 } lsm6dsv16b_fsm_outs5_t; 1845 1846 #define LSM6DSV16B_FSM_OUTS6 0x51U 1847 typedef struct 1848 { 1849 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1850 uint8_t fsm6_n_v : 1; 1851 uint8_t fsm6_p_v : 1; 1852 uint8_t fsm6_n_3 : 1; 1853 uint8_t fsm6_p_3 : 1; 1854 uint8_t fsm6_n_2 : 1; 1855 uint8_t fsm6_p_2 : 1; 1856 uint8_t fsm6_n_1 : 1; 1857 uint8_t fsm6_p_1 : 1; 1858 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1859 uint8_t fsm6_p_1 : 1; 1860 uint8_t fsm6_n_1 : 1; 1861 uint8_t fsm6_p_2 : 1; 1862 uint8_t fsm6_n_2 : 1; 1863 uint8_t fsm6_p_3 : 1; 1864 uint8_t fsm6_n_3 : 1; 1865 uint8_t fsm6_p_v : 1; 1866 uint8_t fsm6_n_v : 1; 1867 #endif /* DRV_BYTE_ORDER */ 1868 } lsm6dsv16b_fsm_outs6_t; 1869 1870 #define LSM6DSV16B_FSM_OUTS7 0x52U 1871 typedef struct 1872 { 1873 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1874 uint8_t fsm7_n_v : 1; 1875 uint8_t fsm7_p_v : 1; 1876 uint8_t fsm7_n_3 : 1; 1877 uint8_t fsm7_p_3 : 1; 1878 uint8_t fsm7_n_2 : 1; 1879 uint8_t fsm7_p_2 : 1; 1880 uint8_t fsm7_n_1 : 1; 1881 uint8_t fsm7_p_1 : 1; 1882 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1883 uint8_t fsm7_p_1 : 1; 1884 uint8_t fsm7_n_1 : 1; 1885 uint8_t fsm7_p_2 : 1; 1886 uint8_t fsm7_n_2 : 1; 1887 uint8_t fsm7_p_3 : 1; 1888 uint8_t fsm7_n_3 : 1; 1889 uint8_t fsm7_p_v : 1; 1890 uint8_t fsm7_n_v : 1; 1891 #endif /* DRV_BYTE_ORDER */ 1892 } lsm6dsv16b_fsm_outs7_t; 1893 1894 #define LSM6DSV16B_FSM_OUTS8 0x53U 1895 typedef struct 1896 { 1897 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1898 uint8_t fsm8_n_v : 1; 1899 uint8_t fsm8_p_v : 1; 1900 uint8_t fsm8_n_3 : 1; 1901 uint8_t fsm8_p_3 : 1; 1902 uint8_t fsm8_n_2 : 1; 1903 uint8_t fsm8_p_2 : 1; 1904 uint8_t fsm8_n_1 : 1; 1905 uint8_t fsm8_p_1 : 1; 1906 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1907 uint8_t fsm8_p_1 : 1; 1908 uint8_t fsm8_n_1 : 1; 1909 uint8_t fsm8_p_2 : 1; 1910 uint8_t fsm8_n_2 : 1; 1911 uint8_t fsm8_p_3 : 1; 1912 uint8_t fsm8_n_3 : 1; 1913 uint8_t fsm8_p_v : 1; 1914 uint8_t fsm8_n_v : 1; 1915 #endif /* DRV_BYTE_ORDER */ 1916 } lsm6dsv16b_fsm_outs8_t; 1917 1918 #define LSM6DSV16B_SFLP_ODR 0x5EU 1919 typedef struct 1920 { 1921 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1922 uint8_t not_used0 : 3; 1923 uint8_t sflp_game_odr : 3; 1924 uint8_t not_used1 : 2; 1925 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1926 uint8_t not_used1 : 2; 1927 uint8_t sflp_game_odr : 3; 1928 uint8_t not_used0 : 3; 1929 #endif /* DRV_BYTE_ORDER */ 1930 } lsm6dsv16b_sflp_odr_t; 1931 1932 #define LSM6DSV16B_FSM_ODR 0x5FU 1933 typedef struct 1934 { 1935 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1936 uint8_t not_used0 : 3; 1937 uint8_t fsm_odr : 3; 1938 uint8_t not_used1 : 2; 1939 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1940 uint8_t not_used1 : 2; 1941 uint8_t fsm_odr : 3; 1942 uint8_t not_used0 : 3; 1943 #endif /* DRV_BYTE_ORDER */ 1944 } lsm6dsv16b_fsm_odr_t; 1945 1946 #define LSM6DSV16B_STEP_COUNTER_L 0x62U 1947 typedef struct 1948 { 1949 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1950 uint8_t step : 8; 1951 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1952 uint8_t step : 8; 1953 #endif /* DRV_BYTE_ORDER */ 1954 } lsm6dsv16b_step_counter_l_t; 1955 1956 #define LSM6DSV16B_STEP_COUNTER_H 0x63U 1957 typedef struct 1958 { 1959 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1960 uint8_t step : 8; 1961 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1962 uint8_t step : 8; 1963 #endif /* DRV_BYTE_ORDER */ 1964 } lsm6dsv16b_step_counter_h_t; 1965 1966 #define LSM6DSV16B_EMB_FUNC_SRC 0x64U 1967 typedef struct 1968 { 1969 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1970 uint8_t not_used0 : 2; 1971 uint8_t stepcounter_bit_set : 1; 1972 uint8_t step_overflow : 1; 1973 uint8_t step_count_delta_ia : 1; 1974 uint8_t step_detected : 1; 1975 uint8_t not_used1 : 1; 1976 uint8_t pedo_rst_step : 1; 1977 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1978 uint8_t pedo_rst_step : 1; 1979 uint8_t not_used1 : 1; 1980 uint8_t step_detected : 1; 1981 uint8_t step_count_delta_ia : 1; 1982 uint8_t step_overflow : 1; 1983 uint8_t stepcounter_bit_set : 1; 1984 uint8_t not_used0 : 2; 1985 #endif /* DRV_BYTE_ORDER */ 1986 } lsm6dsv16b_emb_func_src_t; 1987 1988 #define LSM6DSV16B_EMB_FUNC_INIT_A 0x66U 1989 typedef struct 1990 { 1991 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1992 uint8_t not_used0 : 1; 1993 uint8_t sflp_game_init : 1; 1994 uint8_t not_used2 : 1; 1995 uint8_t step_det_init : 1; 1996 uint8_t tilt_init : 1; 1997 uint8_t sig_mot_init : 1; 1998 uint8_t not_used1 : 2; 1999 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2000 uint8_t not_used1 : 2; 2001 uint8_t not_used1 : 1; 2002 uint8_t sig_mot_init : 1; 2003 uint8_t tilt_init : 1; 2004 uint8_t step_det_init : 1; 2005 uint8_t not_used2 : 1; 2006 uint8_t sflp_game_init : 1; 2007 uint8_t not_used0 : 1; 2008 #endif /* DRV_BYTE_ORDER */ 2009 } lsm6dsv16b_emb_func_init_a_t; 2010 2011 #define LSM6DSV16B_EMB_FUNC_INIT_B 0x67U 2012 typedef struct 2013 { 2014 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2015 uint8_t fsm_init : 1; 2016 uint8_t not_used0 : 2; 2017 uint8_t fifo_compr_init : 1; 2018 uint8_t not_used1 : 4; 2019 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2020 uint8_t not_used1 : 4; 2021 uint8_t fifo_compr_init : 1; 2022 uint8_t not_used0 : 2; 2023 uint8_t fsm_init : 1; 2024 #endif /* DRV_BYTE_ORDER */ 2025 } lsm6dsv16b_emb_func_init_b_t; 2026 2027 /** 2028 * @} 2029 * 2030 */ 2031 2032 /** @defgroup bitfields page pg0_emb_adv 2033 * @{ 2034 * 2035 */ 2036 #define LSM6DSV16B_EMB_ADV_PG_0 0x000 2037 2038 #define LSM6DSV16B_SFLP_GAME_GBIASX_L 0x6EU 2039 typedef struct 2040 { 2041 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2042 uint8_t gbiasx : 8; 2043 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2044 uint8_t gbiasx : 8; 2045 #endif /* DRV_BYTE_ORDER */ 2046 } lsm6dsv16b_sflp_game_gbiasx_l_t; 2047 2048 #define LSM6DSV16B_SFLP_GAME_GBIASX_H 0x6FU 2049 typedef struct 2050 { 2051 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2052 uint8_t gbiasx : 8; 2053 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2054 uint8_t gbiasx : 8; 2055 #endif /* DRV_BYTE_ORDER */ 2056 } lsm6dsv16b_sflp_game_gbiasx_h_t; 2057 2058 #define LSM6DSV16B_SFLP_GAME_GBIASY_L 0x70U 2059 typedef struct 2060 { 2061 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2062 uint8_t gbiasy : 8; 2063 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2064 uint8_t gbiasy : 8; 2065 #endif /* DRV_BYTE_ORDER */ 2066 } lsm6dsv16b_sflp_game_gbiasy_l_t; 2067 2068 #define LSM6DSV16B_SFLP_GAME_GBIASY_H 0x71U 2069 typedef struct 2070 { 2071 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2072 uint8_t gbiasy : 8; 2073 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2074 uint8_t gbiasy : 8; 2075 #endif /* DRV_BYTE_ORDER */ 2076 } lsm6dsv16b_sflp_game_gbiasy_h_t; 2077 2078 #define LSM6DSV16B_SFLP_GAME_GBIASZ_L 0x72U 2079 typedef struct 2080 { 2081 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2082 uint8_t gbiasz : 8; 2083 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2084 uint8_t gbiasz : 8; 2085 #endif /* DRV_BYTE_ORDER */ 2086 } lsm6dsv16b_sflp_game_gbiasz_l_t; 2087 2088 #define LSM6DSV16B_SFLP_GAME_GBIASZ_H 0x73U 2089 typedef struct 2090 { 2091 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2092 uint8_t gbiasz : 8; 2093 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2094 uint8_t gbiasz : 8; 2095 #endif /* DRV_BYTE_ORDER */ 2096 } lsm6dsv16b_sflp_game_gbiasz_h_t; 2097 2098 /** 2099 * @} 2100 * 2101 */ 2102 2103 /** @defgroup bitfields page pg1_emb_adv 2104 * @{ 2105 * 2106 */ 2107 2108 #define LSM6DSV16B_EMB_ADV_PG_1 0x001 2109 2110 #define LSM6DSV16B_FSM_LC_TIMEOUT_L 0x17AU 2111 typedef struct 2112 { 2113 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2114 uint8_t fsm_lc_timeout : 8; 2115 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2116 uint8_t fsm_lc_timeout : 8; 2117 #endif /* DRV_BYTE_ORDER */ 2118 } lsm6dsv16b_fsm_lc_timeout_l_t; 2119 2120 #define LSM6DSV16B_FSM_LC_TIMEOUT_H 0x17BU 2121 typedef struct 2122 { 2123 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2124 uint8_t fsm_lc_timeout : 8; 2125 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2126 uint8_t fsm_lc_timeout : 8; 2127 #endif /* DRV_BYTE_ORDER */ 2128 } lsm6dsv16b_fsm_lc_timeout_h_t; 2129 2130 #define LSM6DSV16B_FSM_PROGRAMS 0x17CU 2131 typedef struct 2132 { 2133 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2134 uint8_t fsm_n_prog : 8; 2135 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2136 uint8_t fsm_n_prog : 8; 2137 #endif /* DRV_BYTE_ORDER */ 2138 } lsm6dsv16b_fsm_programs_t; 2139 2140 #define LSM6DSV16B_FSM_START_ADD_L 0x17EU 2141 typedef struct 2142 { 2143 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2144 uint8_t fsm_start : 8; 2145 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2146 uint8_t fsm_start : 8; 2147 #endif /* DRV_BYTE_ORDER */ 2148 } lsm6dsv16b_fsm_start_add_l_t; 2149 2150 #define LSM6DSV16B_FSM_START_ADD_H 0x17FU 2151 typedef struct 2152 { 2153 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2154 uint8_t fsm_start : 8; 2155 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2156 uint8_t fsm_start : 8; 2157 #endif /* DRV_BYTE_ORDER */ 2158 } lsm6dsv16b_fsm_start_add_h_t; 2159 2160 #define LSM6DSV16B_PEDO_CMD_REG 0x183U 2161 typedef struct 2162 { 2163 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2164 uint8_t not_used0 : 2; 2165 uint8_t fp_rejection_en : 1; 2166 uint8_t carry_count_en : 1; 2167 uint8_t not_used1 : 4; 2168 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2169 uint8_t not_used1 : 4; 2170 uint8_t carry_count_en : 1; 2171 uint8_t fp_rejection_en : 1; 2172 uint8_t not_used0 : 2; 2173 #endif /* DRV_BYTE_ORDER */ 2174 } lsm6dsv16b_pedo_cmd_reg_t; 2175 2176 #define LSM6DSV16B_PEDO_DEB_STEPS_CONF 0x184U 2177 typedef struct 2178 { 2179 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2180 uint8_t deb_step : 8; 2181 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2182 uint8_t deb_step : 8; 2183 #endif /* DRV_BYTE_ORDER */ 2184 } lsm6dsv16b_pedo_deb_steps_conf_t; 2185 2186 #define LSM6DSV16B_PEDO_SC_DELTAT_L 0x1D0U 2187 typedef struct 2188 { 2189 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2190 uint8_t pd_sc : 8; 2191 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2192 uint8_t pd_sc : 8; 2193 #endif /* DRV_BYTE_ORDER */ 2194 } lsm6dsv16b_pedo_sc_deltat_l_t; 2195 2196 #define LSM6DSV16B_PEDO_SC_DELTAT_H 0x1D1U 2197 typedef struct 2198 { 2199 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 2200 uint8_t pd_sc : 8; 2201 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 2202 uint8_t pd_sc : 8; 2203 #endif /* DRV_BYTE_ORDER */ 2204 } lsm6dsv16b_pedo_sc_deltat_h_t; 2205 2206 /** 2207 * @} 2208 * 2209 */ 2210 2211 #define LSM6DSV16B_START_FSM_ADD 0x035CU 2212 2213 /** 2214 * @defgroup LSM6DSV16B_Register_Union 2215 * @brief These unions group all the registers having a bit-field 2216 * description. 2217 * These unions are useful but it's not needed by the driver. 2218 * 2219 * REMOVING this unions you are compliant with: 2220 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 2221 * 2222 * @{ 2223 * 2224 */ 2225 typedef union 2226 { 2227 lsm6dsv16b_func_cfg_access_t func_cfg_access; 2228 lsm6dsv16b_pin_ctrl_t pin_ctrl; 2229 lsm6dsv16b_if_cfg_t if_cfg; 2230 lsm6dsv16b_fifo_ctrl1_t fifo_ctrl1; 2231 lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2; 2232 lsm6dsv16b_fifo_ctrl3_t fifo_ctrl3; 2233 lsm6dsv16b_fifo_ctrl4_t fifo_ctrl4; 2234 lsm6dsv16b_counter_bdr_reg1_t counter_bdr_reg1; 2235 lsm6dsv16b_counter_bdr_reg2_t counter_bdr_reg2; 2236 lsm6dsv16b_int1_ctrl_t int1_ctrl; 2237 lsm6dsv16b_int2_ctrl_t int2_ctrl; 2238 lsm6dsv16b_who_am_i_t who_am_i; 2239 lsm6dsv16b_ctrl1_t ctrl1; 2240 lsm6dsv16b_ctrl2_t ctrl2; 2241 lsm6dsv16b_ctrl3_t ctrl3; 2242 lsm6dsv16b_ctrl4_t ctrl4; 2243 lsm6dsv16b_ctrl5_t ctrl5; 2244 lsm6dsv16b_ctrl6_t ctrl6; 2245 lsm6dsv16b_ctrl7_t ctrl7; 2246 lsm6dsv16b_ctrl8_t ctrl8; 2247 lsm6dsv16b_ctrl9_t ctrl9; 2248 lsm6dsv16b_ctrl10_t ctrl10; 2249 lsm6dsv16b_fifo_status1_t fifo_status1; 2250 lsm6dsv16b_fifo_status2_t fifo_status2; 2251 lsm6dsv16b_all_int_src_t all_int_src; 2252 lsm6dsv16b_status_reg_t status_reg; 2253 lsm6dsv16b_out_temp_l_t out_temp_l; 2254 lsm6dsv16b_out_temp_h_t out_temp_h; 2255 lsm6dsv16b_outx_l_g_t outx_l_g; 2256 lsm6dsv16b_outx_h_g_t outx_h_g; 2257 lsm6dsv16b_outy_l_g_t outy_l_g; 2258 lsm6dsv16b_outy_h_g_t outy_h_g; 2259 lsm6dsv16b_outz_l_g_t outz_l_g; 2260 lsm6dsv16b_outz_h_g_t outz_h_g; 2261 lsm6dsv16b_outz_l_a_t outz_l_a; 2262 lsm6dsv16b_outz_h_a_t outz_h_a; 2263 lsm6dsv16b_outy_l_a_t outy_l_a; 2264 lsm6dsv16b_outy_h_a_t outy_h_a; 2265 lsm6dsv16b_outx_l_a_t outx_l_a; 2266 lsm6dsv16b_outx_h_a_t outx_h_a; 2267 lsm6dsv16b_ui_outz_l_a_dualc_t ui_outz_l_a_dualc; 2268 lsm6dsv16b_ui_outz_h_a_dualc_t ui_outz_h_a_dualc; 2269 lsm6dsv16b_ui_outy_l_a_dualc_t ui_outy_l_a_dualc; 2270 lsm6dsv16b_ui_outy_h_a_dualc_t ui_outy_h_a_dualc; 2271 lsm6dsv16b_ui_outx_l_a_dualc_t ui_outx_l_a_dualc; 2272 lsm6dsv16b_ui_outx_h_a_dualc_t ui_outx_h_a_dualc; 2273 lsm6dsv16b_timestamp0_t timestamp0; 2274 lsm6dsv16b_timestamp1_t timestamp1; 2275 lsm6dsv16b_timestamp2_t timestamp2; 2276 lsm6dsv16b_timestamp3_t timestamp3; 2277 lsm6dsv16b_wake_up_src_t wake_up_src; 2278 lsm6dsv16b_tap_src_t tap_src; 2279 lsm6dsv16b_d6d_src_t d6d_src; 2280 lsm6dsv16b_emb_func_status_mainpage_t emb_func_status_mainpage; 2281 lsm6dsv16b_fsm_status_mainpage_t fsm_status_mainpage; 2282 lsm6dsv16b_internal_freq_t internal_freq; 2283 lsm6dsv16b_functions_enable_t functions_enable; 2284 lsm6dsv16b_inactivity_dur_t inactivity_dur; 2285 lsm6dsv16b_inactivity_ths_t inactivity_ths; 2286 lsm6dsv16b_tap_cfg0_t tap_cfg0; 2287 lsm6dsv16b_tap_cfg1_t tap_cfg1; 2288 lsm6dsv16b_tap_cfg2_t tap_cfg2; 2289 lsm6dsv16b_tap_ths_6d_t tap_ths_6d; 2290 lsm6dsv16b_tap_dur_t int_dur2; 2291 lsm6dsv16b_wake_up_ths_t wake_up_ths; 2292 lsm6dsv16b_wake_up_dur_t wake_up_dur; 2293 lsm6dsv16b_free_fall_t free_fall; 2294 lsm6dsv16b_md1_cfg_t md1_cfg; 2295 lsm6dsv16b_md2_cfg_t md2_cfg; 2296 lsm6dsv16b_emb_func_cfg_t emb_func_cfg; 2297 lsm6dsv16b_tdm_cfg0_t tdm_cfg0; 2298 lsm6dsv16b_tdm_cfg1_t tdm_cfg1; 2299 lsm6dsv16b_tdm_cfg2_t tdm_cfg2; 2300 lsm6dsv16b_z_ofs_usr_t z_ofs_usr; 2301 lsm6dsv16b_y_ofs_usr_t y_ofs_usr; 2302 lsm6dsv16b_x_ofs_usr_t x_ofs_usr; 2303 lsm6dsv16b_fifo_data_out_tag_t fifo_data_out_tag; 2304 lsm6dsv16b_fifo_data_out_byte_0_t fifo_data_out_byte_0; 2305 lsm6dsv16b_fifo_data_out_byte_1_t fifo_data_out_byte_1; 2306 lsm6dsv16b_fifo_data_out_byte_2_t fifo_data_out_byte_2; 2307 lsm6dsv16b_fifo_data_out_byte_3_t fifo_data_out_byte_3; 2308 lsm6dsv16b_fifo_data_out_byte_4_t fifo_data_out_byte_4; 2309 lsm6dsv16b_fifo_data_out_byte_5_t fifo_data_out_byte_5; 2310 lsm6dsv16b_page_sel_t page_sel; 2311 lsm6dsv16b_emb_func_en_a_t emb_func_en_a; 2312 lsm6dsv16b_emb_func_en_b_t emb_func_en_b; 2313 lsm6dsv16b_emb_func_exec_status_t emb_func_exec_status; 2314 lsm6dsv16b_page_address_t page_address; 2315 lsm6dsv16b_page_value_t page_value; 2316 lsm6dsv16b_emb_func_int1_t emb_func_int1; 2317 lsm6dsv16b_fsm_int1_t fsm_int1; 2318 lsm6dsv16b_emb_func_int2_t emb_func_int2; 2319 lsm6dsv16b_fsm_int2_t fsm_int2; 2320 lsm6dsv16b_emb_func_status_t emb_func_status; 2321 lsm6dsv16b_fsm_status_t fsm_status; 2322 lsm6dsv16b_page_rw_t page_rw; 2323 lsm6dsv16b_emb_func_fifo_en_a_t emb_func_fifo_en_a; 2324 lsm6dsv16b_fsm_enable_t fsm_enable; 2325 lsm6dsv16b_fsm_long_counter_l_t fsm_long_counter_l; 2326 lsm6dsv16b_fsm_long_counter_h_t fsm_long_counter_h; 2327 lsm6dsv16b_fsm_outs1_t fsm_outs1; 2328 lsm6dsv16b_fsm_outs2_t fsm_outs2; 2329 lsm6dsv16b_fsm_outs3_t fsm_outs3; 2330 lsm6dsv16b_fsm_outs4_t fsm_outs4; 2331 lsm6dsv16b_fsm_outs5_t fsm_outs5; 2332 lsm6dsv16b_fsm_outs6_t fsm_outs6; 2333 lsm6dsv16b_fsm_outs7_t fsm_outs7; 2334 lsm6dsv16b_fsm_outs8_t fsm_outs8; 2335 lsm6dsv16b_fsm_odr_t fsm_odr; 2336 lsm6dsv16b_step_counter_l_t step_counter_l; 2337 lsm6dsv16b_step_counter_h_t step_counter_h; 2338 lsm6dsv16b_emb_func_src_t emb_func_src; 2339 lsm6dsv16b_emb_func_init_a_t emb_func_init_a; 2340 lsm6dsv16b_emb_func_init_b_t emb_func_init_b; 2341 lsm6dsv16b_fsm_lc_timeout_l_t fsm_lc_timeout_l; 2342 lsm6dsv16b_fsm_lc_timeout_h_t fsm_lc_timeout_h; 2343 lsm6dsv16b_fsm_programs_t fsm_programs; 2344 lsm6dsv16b_fsm_start_add_l_t fsm_start_add_l; 2345 lsm6dsv16b_fsm_start_add_h_t fsm_start_add_h; 2346 lsm6dsv16b_pedo_cmd_reg_t pedo_cmd_reg; 2347 lsm6dsv16b_pedo_deb_steps_conf_t pedo_deb_steps_conf; 2348 lsm6dsv16b_pedo_sc_deltat_l_t pedo_sc_deltat_l; 2349 lsm6dsv16b_pedo_sc_deltat_h_t pedo_sc_deltat_h; 2350 bitwise_t bitwise; 2351 uint8_t byte; 2352 } lsm6dsv16b_reg_t; 2353 2354 2355 /** 2356 * @} 2357 * 2358 */ 2359 2360 #ifndef __weak 2361 #define __weak __attribute__((weak)) 2362 #endif /* __weak */ 2363 2364 /* 2365 * These are the basic platform dependent I/O routines to read 2366 * and write device registers connected on a standard bus. 2367 * The driver keeps offering a default implementation based on function 2368 * pointers to read/write routines for backward compatibility. 2369 * The __weak directive allows the final application to overwrite 2370 * them with a custom implementation. 2371 */ 2372 2373 int32_t lsm6dsv16b_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 2374 uint8_t *data, 2375 uint16_t len); 2376 int32_t lsm6dsv16b_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 2377 uint8_t *data, 2378 uint16_t len); 2379 2380 float_t lsm6dsv16b_from_sflp_to_mg(int16_t lsb); 2381 float_t lsm6dsv16b_from_fs2_to_mg(int16_t lsb); 2382 float_t lsm6dsv16b_from_fs4_to_mg(int16_t lsb); 2383 float_t lsm6dsv16b_from_fs8_to_mg(int16_t lsb); 2384 float_t lsm6dsv16b_from_fs16_to_mg(int16_t lsb); 2385 2386 float_t lsm6dsv16b_from_fs125_to_mdps(int16_t lsb); 2387 float_t lsm6dsv16b_from_fs500_to_mdps(int16_t lsb); 2388 float_t lsm6dsv16b_from_fs250_to_mdps(int16_t lsb); 2389 float_t lsm6dsv16b_from_fs1000_to_mdps(int16_t lsb); 2390 float_t lsm6dsv16b_from_fs2000_to_mdps(int16_t lsb); 2391 float_t lsm6dsv16b_from_fs4000_to_mdps(int16_t lsb); 2392 2393 float_t lsm6dsv16b_from_lsb_to_celsius(int16_t lsb); 2394 2395 uint64_t lsm6dsv16b_from_lsb_to_nsec(uint32_t lsb); 2396 2397 float_t lsm6dsv16b_from_lsb_to_mv(int16_t lsb); 2398 2399 typedef enum 2400 { 2401 LSM6DSV16B_READY = 0x0, 2402 LSM6DSV16B_GLOBAL_RST = 0x1, 2403 LSM6DSV16B_RESTORE_CAL_PARAM = 0x2, 2404 LSM6DSV16B_RESTORE_CTRL_REGS = 0x4, 2405 } lsm6dsv16b_reset_t; 2406 int32_t lsm6dsv16b_reset_set(const stmdev_ctx_t *ctx, lsm6dsv16b_reset_t val); 2407 int32_t lsm6dsv16b_reset_get(const stmdev_ctx_t *ctx, lsm6dsv16b_reset_t *val); 2408 2409 typedef enum 2410 { 2411 LSM6DSV16B_MAIN_MEM_BANK = 0x0, 2412 LSM6DSV16B_EMBED_FUNC_MEM_BANK = 0x1, 2413 } lsm6dsv16b_mem_bank_t; 2414 int32_t lsm6dsv16b_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsv16b_mem_bank_t val); 2415 int32_t lsm6dsv16b_mem_bank_get(const stmdev_ctx_t *ctx, 2416 lsm6dsv16b_mem_bank_t *val); 2417 2418 int32_t lsm6dsv16b_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); 2419 2420 typedef enum 2421 { 2422 LSM6DSV16B_XL_ODR_OFF = 0x0, 2423 LSM6DSV16B_XL_ODR_AT_1Hz875 = 0x1, 2424 LSM6DSV16B_XL_ODR_AT_7Hz5 = 0x2, 2425 LSM6DSV16B_XL_ODR_AT_15Hz = 0x3, 2426 LSM6DSV16B_XL_ODR_AT_30Hz = 0x4, 2427 LSM6DSV16B_XL_ODR_AT_60Hz = 0x5, 2428 LSM6DSV16B_XL_ODR_AT_120Hz = 0x6, 2429 LSM6DSV16B_XL_ODR_AT_240Hz = 0x7, 2430 LSM6DSV16B_XL_ODR_AT_480Hz = 0x8, 2431 LSM6DSV16B_XL_ODR_AT_960Hz = 0x9, 2432 LSM6DSV16B_XL_ODR_AT_1920Hz = 0xA, 2433 LSM6DSV16B_XL_ODR_AT_3840Hz = 0xB, 2434 LSM6DSV16B_XL_ODR_AT_7680Hz = 0xC, 2435 } lsm6dsv16b_xl_data_rate_t; 2436 int32_t lsm6dsv16b_xl_data_rate_set(const stmdev_ctx_t *ctx, 2437 lsm6dsv16b_xl_data_rate_t val); 2438 int32_t lsm6dsv16b_xl_data_rate_get(const stmdev_ctx_t *ctx, 2439 lsm6dsv16b_xl_data_rate_t *val); 2440 2441 typedef enum 2442 { 2443 LSM6DSV16B_XL_HIGH_PERFORMANCE_MD = 0x0, 2444 LSM6DSV16B_XL_HIGH_PERFORMANCE_TDM_MD = 0x2, 2445 LSM6DSV16B_XL_LOW_POWER_2_AVG_MD = 0x4, 2446 LSM6DSV16B_XL_LOW_POWER_4_AVG_MD = 0x5, 2447 LSM6DSV16B_XL_LOW_POWER_8_AVG_MD = 0x6, 2448 } lsm6dsv16b_xl_mode_t; 2449 int32_t lsm6dsv16b_xl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_xl_mode_t val); 2450 int32_t lsm6dsv16b_xl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_xl_mode_t *val); 2451 2452 typedef enum 2453 { 2454 LSM6DSV16B_GY_ODR_OFF = 0x0, 2455 LSM6DSV16B_GY_ODR_AT_7Hz5 = 0x2, 2456 LSM6DSV16B_GY_ODR_AT_15Hz = 0x3, 2457 LSM6DSV16B_GY_ODR_AT_30Hz = 0x4, 2458 LSM6DSV16B_GY_ODR_AT_60Hz = 0x5, 2459 LSM6DSV16B_GY_ODR_AT_120Hz = 0x6, 2460 LSM6DSV16B_GY_ODR_AT_240Hz = 0x7, 2461 LSM6DSV16B_GY_ODR_AT_480Hz = 0x8, 2462 LSM6DSV16B_GY_ODR_AT_960Hz = 0x9, 2463 LSM6DSV16B_GY_ODR_AT_1920Hz = 0xa, 2464 LSM6DSV16B_GY_ODR_AT_3840Hz = 0xb, 2465 LSM6DSV16B_GY_ODR_AT_7680Hz = 0xc, 2466 } lsm6dsv16b_gy_data_rate_t; 2467 int32_t lsm6dsv16b_gy_data_rate_set(const stmdev_ctx_t *ctx, 2468 lsm6dsv16b_gy_data_rate_t val); 2469 int32_t lsm6dsv16b_gy_data_rate_get(const stmdev_ctx_t *ctx, 2470 lsm6dsv16b_gy_data_rate_t *val); 2471 2472 typedef enum 2473 { 2474 LSM6DSV16B_GY_HIGH_PERFORMANCE_MD = 0x0, 2475 LSM6DSV16B_GY_SLEEP_MD = 0x4, 2476 LSM6DSV16B_GY_LOW_POWER_MD = 0x5, 2477 } lsm6dsv16b_gy_mode_t; 2478 int32_t lsm6dsv16b_gy_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_gy_mode_t val); 2479 int32_t lsm6dsv16b_gy_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_gy_mode_t *val); 2480 2481 int32_t lsm6dsv16b_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 2482 int32_t lsm6dsv16b_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 2483 2484 int32_t lsm6dsv16b_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); 2485 int32_t lsm6dsv16b_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val); 2486 2487 typedef enum 2488 { 2489 LSM6DSV16B_DRDY_LATCHED = 0x0, 2490 LSM6DSV16B_DRDY_PULSED = 0x1, 2491 } lsm6dsv16b_data_ready_mode_t; 2492 int32_t lsm6dsv16b_data_ready_mode_set(const stmdev_ctx_t *ctx, 2493 lsm6dsv16b_data_ready_mode_t val); 2494 int32_t lsm6dsv16b_data_ready_mode_get(const stmdev_ctx_t *ctx, 2495 lsm6dsv16b_data_ready_mode_t *val); 2496 2497 typedef enum 2498 { 2499 LSM6DSV16B_125dps = 0x0, 2500 LSM6DSV16B_250dps = 0x1, 2501 LSM6DSV16B_500dps = 0x2, 2502 LSM6DSV16B_1000dps = 0x3, 2503 LSM6DSV16B_2000dps = 0x4, 2504 LSM6DSV16B_4000dps = 0xc, 2505 } lsm6dsv16b_gy_full_scale_t; 2506 int32_t lsm6dsv16b_gy_full_scale_set(const stmdev_ctx_t *ctx, 2507 lsm6dsv16b_gy_full_scale_t val); 2508 int32_t lsm6dsv16b_gy_full_scale_get(const stmdev_ctx_t *ctx, 2509 lsm6dsv16b_gy_full_scale_t *val); 2510 2511 typedef enum 2512 { 2513 LSM6DSV16B_2g = 0x0, 2514 LSM6DSV16B_4g = 0x1, 2515 LSM6DSV16B_8g = 0x2, 2516 LSM6DSV16B_16g = 0x3, 2517 } lsm6dsv16b_xl_full_scale_t; 2518 int32_t lsm6dsv16b_xl_full_scale_set(const stmdev_ctx_t *ctx, 2519 lsm6dsv16b_xl_full_scale_t val); 2520 int32_t lsm6dsv16b_xl_full_scale_get(const stmdev_ctx_t *ctx, 2521 lsm6dsv16b_xl_full_scale_t *val); 2522 2523 int32_t lsm6dsv16b_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val); 2524 int32_t lsm6dsv16b_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val); 2525 2526 typedef enum 2527 { 2528 LSM6DSV16B_XL_ST_DISABLE = 0x0, 2529 LSM6DSV16B_XL_ST_POSITIVE = 0x1, 2530 LSM6DSV16B_XL_ST_NEGATIVE = 0x2, 2531 LSM6DSV16B_XL_ST_OFFSET_POS = 0x5, 2532 LSM6DSV16B_XL_ST_OFFSET_NEG = 0x6, 2533 } lsm6dsv16b_xl_self_test_t; 2534 int32_t lsm6dsv16b_xl_self_test_set(const stmdev_ctx_t *ctx, 2535 lsm6dsv16b_xl_self_test_t val); 2536 int32_t lsm6dsv16b_xl_self_test_get(const stmdev_ctx_t *ctx, 2537 lsm6dsv16b_xl_self_test_t *val); 2538 2539 typedef enum 2540 { 2541 LSM6DSV16B_GY_ST_DISABLE = 0x0, 2542 LSM6DSV16B_GY_ST_POSITIVE = 0x1, 2543 LSM6DSV16B_GY_ST_NEGATIVE = 0x2, 2544 } lsm6dsv16b_gy_self_test_t; 2545 int32_t lsm6dsv16b_gy_self_test_set(const stmdev_ctx_t *ctx, 2546 lsm6dsv16b_gy_self_test_t val); 2547 int32_t lsm6dsv16b_gy_self_test_get(const stmdev_ctx_t *ctx, 2548 lsm6dsv16b_gy_self_test_t *val); 2549 2550 typedef struct 2551 { 2552 uint8_t drdy_xl : 1; 2553 uint8_t drdy_gy : 1; 2554 uint8_t drdy_temp : 1; 2555 uint8_t gy_settling : 1; 2556 uint8_t den_flag : 1; 2557 uint8_t timestamp : 1; 2558 uint8_t free_fall : 1; 2559 uint8_t wake_up : 1; 2560 uint8_t wake_up_z : 1; 2561 uint8_t wake_up_y : 1; 2562 uint8_t wake_up_x : 1; 2563 uint8_t single_tap : 1; 2564 uint8_t double_tap : 1; 2565 uint8_t tap_z : 1; 2566 uint8_t tap_y : 1; 2567 uint8_t tap_x : 1; 2568 uint8_t tap_sign : 1; 2569 uint8_t six_d : 1; 2570 uint8_t six_d_xl : 1; 2571 uint8_t six_d_xh : 1; 2572 uint8_t six_d_yl : 1; 2573 uint8_t six_d_yh : 1; 2574 uint8_t six_d_zl : 1; 2575 uint8_t six_d_zh : 1; 2576 uint8_t sleep_change : 1; 2577 uint8_t sleep_state : 1; 2578 uint8_t step_detector : 1; 2579 uint8_t step_count_inc : 1; 2580 uint8_t step_count_overflow : 1; 2581 uint8_t step_on_delta_time : 1; 2582 uint8_t emb_func_stand_by : 1; 2583 uint8_t emb_func_time_exceed: 1; 2584 uint8_t tilt : 1; 2585 uint8_t sig_mot : 1; 2586 uint8_t fsm_lc : 1; 2587 uint8_t fsm1 : 1; 2588 uint8_t fsm2 : 1; 2589 uint8_t fsm3 : 1; 2590 uint8_t fsm4 : 1; 2591 uint8_t fsm5 : 1; 2592 uint8_t fsm6 : 1; 2593 uint8_t fsm7 : 1; 2594 uint8_t fsm8 : 1; 2595 uint8_t fifo_bdr : 1; 2596 uint8_t fifo_full : 1; 2597 uint8_t fifo_ovr : 1; 2598 uint8_t fifo_th : 1; 2599 } lsm6dsv16b_all_sources_t; 2600 int32_t lsm6dsv16b_all_sources_get(const stmdev_ctx_t *ctx, 2601 lsm6dsv16b_all_sources_t *val); 2602 2603 typedef struct 2604 { 2605 uint8_t drdy_xl : 1; 2606 uint8_t drdy_gy : 1; 2607 uint8_t drdy_temp : 1; 2608 } lsm6dsv16b_data_ready_t; 2609 int32_t lsm6dsv16b_flag_data_ready_get(const stmdev_ctx_t *ctx, 2610 lsm6dsv16b_data_ready_t *val); 2611 2612 int32_t lsm6dsv16b_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 2613 2614 int32_t lsm6dsv16b_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 2615 2616 int32_t lsm6dsv16b_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 2617 2618 int32_t lsm6dsv16b_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 2619 2620 int32_t lsm6dsv16b_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, 2621 int16_t *val); 2622 2623 int32_t lsm6dsv16b_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val); 2624 2625 typedef struct 2626 { 2627 uint8_t x : 1; 2628 uint8_t y : 1; 2629 uint8_t z : 1; 2630 } lsm6dsv16b_tdm_xl_axis_t; 2631 int32_t lsm6dsv16b_tdm_xl_axis_set(const stmdev_ctx_t *ctx, lsm6dsv16b_tdm_xl_axis_t val); 2632 int32_t lsm6dsv16b_tdm_xl_axis_get(const stmdev_ctx_t *ctx, lsm6dsv16b_tdm_xl_axis_t *val); 2633 2634 int32_t lsm6dsv16b_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, 2635 uint8_t *buf, uint8_t len); 2636 int32_t lsm6dsv16b_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, 2637 uint8_t *buf, uint8_t len); 2638 2639 int32_t lsm6dsv16b_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); 2640 int32_t lsm6dsv16b_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); 2641 2642 int32_t lsm6dsv16b_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); 2643 2644 typedef enum 2645 { 2646 LSM6DSV16B_AUTO = 0x0, 2647 LSM6DSV16B_ALWAYS_ACTIVE = 0x1, 2648 } lsm6dsv16b_filt_anti_spike_t; 2649 int32_t lsm6dsv16b_filt_anti_spike_set(const stmdev_ctx_t *ctx, 2650 lsm6dsv16b_filt_anti_spike_t val); 2651 int32_t lsm6dsv16b_filt_anti_spike_get(const stmdev_ctx_t *ctx, 2652 lsm6dsv16b_filt_anti_spike_t *val); 2653 2654 typedef struct 2655 { 2656 uint8_t drdy : 1; 2657 uint8_t irq_xl : 1; 2658 uint8_t irq_g : 1; 2659 uint8_t tdm_excep_code : 1; 2660 } lsm6dsv16b_filt_settling_mask_t; 2661 int32_t lsm6dsv16b_filt_settling_mask_set(const stmdev_ctx_t *ctx, 2662 lsm6dsv16b_filt_settling_mask_t val); 2663 int32_t lsm6dsv16b_filt_settling_mask_get(const stmdev_ctx_t *ctx, 2664 lsm6dsv16b_filt_settling_mask_t *val); 2665 2666 typedef enum 2667 { 2668 LSM6DSV16B_GY_ULTRA_LIGHT = 0x0, 2669 LSM6DSV16B_GY_VERY_LIGHT = 0x1, 2670 LSM6DSV16B_GY_LIGHT = 0x2, 2671 LSM6DSV16B_GY_MEDIUM = 0x3, 2672 LSM6DSV16B_GY_STRONG = 0x4, 2673 LSM6DSV16B_GY_VERY_STRONG = 0x5, 2674 LSM6DSV16B_GY_AGGRESSIVE = 0x6, 2675 LSM6DSV16B_GY_XTREME = 0x7, 2676 } lsm6dsv16b_filt_gy_lp1_bandwidth_t; 2677 int32_t lsm6dsv16b_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx, 2678 lsm6dsv16b_filt_gy_lp1_bandwidth_t val); 2679 int32_t lsm6dsv16b_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx, 2680 lsm6dsv16b_filt_gy_lp1_bandwidth_t *val); 2681 2682 int32_t lsm6dsv16b_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val); 2683 int32_t lsm6dsv16b_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val); 2684 2685 typedef enum 2686 { 2687 LSM6DSV16B_XL_ULTRA_LIGHT = 0x0, 2688 LSM6DSV16B_XL_VERY_LIGHT = 0x1, 2689 LSM6DSV16B_XL_LIGHT = 0x2, 2690 LSM6DSV16B_XL_MEDIUM = 0x3, 2691 LSM6DSV16B_XL_STRONG = 0x4, 2692 LSM6DSV16B_XL_VERY_STRONG = 0x5, 2693 LSM6DSV16B_XL_AGGRESSIVE = 0x6, 2694 LSM6DSV16B_XL_XTREME = 0x7, 2695 } lsm6dsv16b_filt_xl_lp2_bandwidth_t; 2696 int32_t lsm6dsv16b_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx, 2697 lsm6dsv16b_filt_xl_lp2_bandwidth_t val); 2698 int32_t lsm6dsv16b_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx, 2699 lsm6dsv16b_filt_xl_lp2_bandwidth_t *val); 2700 2701 int32_t lsm6dsv16b_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val); 2702 int32_t lsm6dsv16b_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val); 2703 2704 int32_t lsm6dsv16b_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val); 2705 int32_t lsm6dsv16b_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val); 2706 2707 int32_t lsm6dsv16b_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val); 2708 int32_t lsm6dsv16b_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val); 2709 2710 typedef enum 2711 { 2712 LSM6DSV16B_HP_MD_NORMAL = 0x0, 2713 LSM6DSV16B_HP_MD_REFERENCE = 0x1, 2714 } lsm6dsv16b_filt_xl_hp_mode_t; 2715 int32_t lsm6dsv16b_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx, 2716 lsm6dsv16b_filt_xl_hp_mode_t val); 2717 int32_t lsm6dsv16b_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx, 2718 lsm6dsv16b_filt_xl_hp_mode_t *val); 2719 2720 typedef enum 2721 { 2722 LSM6DSV16B_WK_FEED_SLOPE = 0x0, 2723 LSM6DSV16B_WK_FEED_HIGH_PASS = 0x1, 2724 LSM6DSV16B_WK_FEED_LP_WITH_OFFSET = 0x2, 2725 } lsm6dsv16b_filt_wkup_act_feed_t; 2726 int32_t lsm6dsv16b_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx, 2727 lsm6dsv16b_filt_wkup_act_feed_t val); 2728 int32_t lsm6dsv16b_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx, 2729 lsm6dsv16b_filt_wkup_act_feed_t *val); 2730 2731 int32_t lsm6dsv16b_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val); 2732 int32_t lsm6dsv16b_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val); 2733 2734 typedef enum 2735 { 2736 LSM6DSV16B_SIXD_FEED_ODR_DIV_2 = 0x0, 2737 LSM6DSV16B_SIXD_FEED_LOW_PASS = 0x1, 2738 } lsm6dsv16b_filt_sixd_feed_t; 2739 int32_t lsm6dsv16b_filt_sixd_feed_set(const stmdev_ctx_t *ctx, 2740 lsm6dsv16b_filt_sixd_feed_t val); 2741 int32_t lsm6dsv16b_filt_sixd_feed_get(const stmdev_ctx_t *ctx, 2742 lsm6dsv16b_filt_sixd_feed_t *val); 2743 2744 int32_t lsm6dsv16b_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); 2745 int32_t lsm6dsv16b_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); 2746 2747 typedef enum 2748 { 2749 LSM6DSV16B_I2C_I3C_ENABLE = 0x0, 2750 LSM6DSV16B_I2C_I3C_DISABLE = 0x1, 2751 } lsm6dsv16b_ui_i2c_i3c_mode_t; 2752 int32_t lsm6dsv16b_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx, 2753 lsm6dsv16b_ui_i2c_i3c_mode_t val); 2754 int32_t lsm6dsv16b_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx, 2755 lsm6dsv16b_ui_i2c_i3c_mode_t *val); 2756 2757 typedef enum 2758 { 2759 LSM6DSV16B_SPI_4_WIRE = 0x0, 2760 LSM6DSV16B_SPI_3_WIRE = 0x1, 2761 } lsm6dsv16b_spi_mode_t; 2762 int32_t lsm6dsv16b_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_spi_mode_t val); 2763 int32_t lsm6dsv16b_spi_mode_get(const stmdev_ctx_t *ctx, 2764 lsm6dsv16b_spi_mode_t *val); 2765 2766 int32_t lsm6dsv16b_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); 2767 int32_t lsm6dsv16b_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); 2768 2769 typedef enum 2770 { 2771 LSM6DSV16B_IBI_2us = 0x0, 2772 LSM6DSV16B_IBI_50us = 0x1, 2773 LSM6DSV16B_IBI_1ms = 0x2, 2774 LSM6DSV16B_IBI_25ms = 0x3, 2775 } lsm6dsv16b_i3c_ibi_time_t; 2776 int32_t lsm6dsv16b_i3c_ibi_time_set(const stmdev_ctx_t *ctx, 2777 lsm6dsv16b_i3c_ibi_time_t val); 2778 int32_t lsm6dsv16b_i3c_ibi_time_get(const stmdev_ctx_t *ctx, 2779 lsm6dsv16b_i3c_ibi_time_t *val); 2780 2781 typedef enum 2782 { 2783 LSM6DSV16B_PUSH_PULL = 0x0, 2784 LSM6DSV16B_OPEN_DRAIN = 0x1, 2785 } lsm6dsv16b_int_pin_mode_t; 2786 int32_t lsm6dsv16b_int_pin_mode_set(const stmdev_ctx_t *ctx, 2787 lsm6dsv16b_int_pin_mode_t val); 2788 int32_t lsm6dsv16b_int_pin_mode_get(const stmdev_ctx_t *ctx, 2789 lsm6dsv16b_int_pin_mode_t *val); 2790 2791 typedef enum 2792 { 2793 LSM6DSV16B_ACTIVE_HIGH = 0x0, 2794 LSM6DSV16B_ACTIVE_LOW = 0x1, 2795 } lsm6dsv16b_pin_polarity_t; 2796 int32_t lsm6dsv16b_pin_polarity_set(const stmdev_ctx_t *ctx, 2797 lsm6dsv16b_pin_polarity_t val); 2798 int32_t lsm6dsv16b_pin_polarity_get(const stmdev_ctx_t *ctx, 2799 lsm6dsv16b_pin_polarity_t *val); 2800 2801 typedef struct 2802 { 2803 uint8_t boot : 1; 2804 uint8_t drdy_xl : 1; 2805 uint8_t drdy_gy : 1; 2806 uint8_t drdy_temp : 1; 2807 uint8_t fifo_th : 1; 2808 uint8_t fifo_ovr : 1; 2809 uint8_t fifo_full : 1; 2810 uint8_t fifo_bdr : 1; 2811 uint8_t den_flag : 1; 2812 uint8_t timestamp : 1; // impact on int2 signals 2813 uint8_t six_d : 1; 2814 uint8_t double_tap : 1; 2815 uint8_t free_fall : 1; 2816 uint8_t wake_up : 1; 2817 uint8_t single_tap : 1; 2818 uint8_t sleep_change : 1; 2819 uint8_t sleep_status : 1; 2820 uint8_t step_detector : 1; 2821 uint8_t step_count_overflow : 1; 2822 uint8_t tilt : 1; 2823 uint8_t sig_mot : 1; 2824 uint8_t emb_func_stand_by : 1; // impact on int2 signals 2825 uint8_t fsm_lc : 1; 2826 uint8_t fsm1 : 1; 2827 uint8_t fsm2 : 1; 2828 uint8_t fsm3 : 1; 2829 uint8_t fsm4 : 1; 2830 uint8_t fsm5 : 1; 2831 uint8_t fsm6 : 1; 2832 uint8_t fsm7 : 1; 2833 uint8_t fsm8 : 1; 2834 } lsm6dsv16b_pin_int_route_t; 2835 int32_t lsm6dsv16b_pin_int1_route_set(const stmdev_ctx_t *ctx, 2836 lsm6dsv16b_pin_int_route_t val); 2837 int32_t lsm6dsv16b_pin_int1_route_get(const stmdev_ctx_t *ctx, 2838 lsm6dsv16b_pin_int_route_t *val); 2839 int32_t lsm6dsv16b_pin_int2_route_set(const stmdev_ctx_t *ctx, 2840 lsm6dsv16b_pin_int_route_t val); 2841 int32_t lsm6dsv16b_pin_int2_route_get(const stmdev_ctx_t *ctx, 2842 lsm6dsv16b_pin_int_route_t *val); 2843 2844 int32_t lsm6dsv16b_pin_int_en_when_i2c_set(const stmdev_ctx_t *ctx, uint8_t val); 2845 int32_t lsm6dsv16b_pin_int_en_when_i2c_get(const stmdev_ctx_t *ctx, uint8_t *val); 2846 2847 typedef enum 2848 { 2849 LSM6DSV16B_ALL_INT_PULSED = 0x0, 2850 LSM6DSV16B_BASE_LATCHED_EMB_PULSED = 0x1, 2851 LSM6DSV16B_BASE_PULSED_EMB_LATCHED = 0x2, 2852 LSM6DSV16B_ALL_INT_LATCHED = 0x3, 2853 } lsm6dsv16b_int_notification_t; 2854 int32_t lsm6dsv16b_int_notification_set(const stmdev_ctx_t *ctx, 2855 lsm6dsv16b_int_notification_t val); 2856 int32_t lsm6dsv16b_int_notification_get(const stmdev_ctx_t *ctx, 2857 lsm6dsv16b_int_notification_t *val); 2858 2859 typedef enum 2860 { 2861 LSM6DSV16B_XL_AND_GY_NOT_AFFECTED = 0x0, 2862 LSM6DSV16B_XL_LOW_POWER_GY_NOT_AFFECTED = 0x1, 2863 LSM6DSV16B_XL_LOW_POWER_GY_SLEEP = 0x2, 2864 LSM6DSV16B_XL_LOW_POWER_GY_POWER_DOWN = 0x3, 2865 } lsm6dsv16b_act_mode_t; 2866 int32_t lsm6dsv16b_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_act_mode_t val); 2867 int32_t lsm6dsv16b_act_mode_get(const stmdev_ctx_t *ctx, 2868 lsm6dsv16b_act_mode_t *val); 2869 2870 typedef enum 2871 { 2872 LSM6DSV16B_SLEEP_TO_ACT_AT_1ST_SAMPLE = 0x0, 2873 LSM6DSV16B_SLEEP_TO_ACT_AT_2ND_SAMPLE = 0x1, 2874 LSM6DSV16B_SLEEP_TO_ACT_AT_3RD_SAMPLE = 0x2, 2875 LSM6DSV16B_SLEEP_TO_ACT_AT_4th_SAMPLE = 0x3, 2876 } lsm6dsv16b_act_from_sleep_to_act_dur_t; 2877 int32_t lsm6dsv16b_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx, 2878 lsm6dsv16b_act_from_sleep_to_act_dur_t val); 2879 int32_t lsm6dsv16b_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx, 2880 lsm6dsv16b_act_from_sleep_to_act_dur_t *val); 2881 2882 typedef enum 2883 { 2884 LSM6DSV16B_1Hz875 = 0x0, 2885 LSM6DSV16B_15Hz = 0x1, 2886 LSM6DSV16B_30Hz = 0x2, 2887 LSM6DSV16B_60Hz = 0x3, 2888 } lsm6dsv16b_act_sleep_xl_odr_t; 2889 int32_t lsm6dsv16b_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx, 2890 lsm6dsv16b_act_sleep_xl_odr_t val); 2891 int32_t lsm6dsv16b_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx, 2892 lsm6dsv16b_act_sleep_xl_odr_t *val); 2893 2894 typedef struct 2895 { 2896 uint32_t wk_ths_mg; 2897 uint32_t inact_ths_mg; 2898 } lsm6dsv16b_act_thresholds_t; 2899 int32_t lsm6dsv16b_act_thresholds_set(const stmdev_ctx_t *ctx, 2900 lsm6dsv16b_act_thresholds_t val); 2901 int32_t lsm6dsv16b_act_thresholds_get(const stmdev_ctx_t *ctx, 2902 lsm6dsv16b_act_thresholds_t *val); 2903 2904 typedef struct 2905 { 2906 uint8_t shock : 2; 2907 uint8_t quiet : 4; 2908 } lsm6dsv16b_act_wkup_time_windows_t; 2909 int32_t lsm6dsv16b_act_wkup_time_windows_set(const stmdev_ctx_t *ctx, 2910 lsm6dsv16b_act_wkup_time_windows_t val); 2911 int32_t lsm6dsv16b_act_wkup_time_windows_get(const stmdev_ctx_t *ctx, 2912 lsm6dsv16b_act_wkup_time_windows_t *val); 2913 2914 typedef struct 2915 { 2916 uint8_t tap_x_en : 1; 2917 uint8_t tap_y_en : 1; 2918 uint8_t tap_z_en : 1; 2919 } lsm6dsv16b_tap_detection_t; 2920 int32_t lsm6dsv16b_tap_detection_set(const stmdev_ctx_t *ctx, 2921 lsm6dsv16b_tap_detection_t val); 2922 int32_t lsm6dsv16b_tap_detection_get(const stmdev_ctx_t *ctx, 2923 lsm6dsv16b_tap_detection_t *val); 2924 2925 typedef struct 2926 { 2927 uint8_t x : 1; 2928 uint8_t y : 1; 2929 uint8_t z : 1; 2930 } lsm6dsv16b_tap_thresholds_t; 2931 int32_t lsm6dsv16b_tap_thresholds_set(const stmdev_ctx_t *ctx, 2932 lsm6dsv16b_tap_thresholds_t val); 2933 int32_t lsm6dsv16b_tap_thresholds_get(const stmdev_ctx_t *ctx, 2934 lsm6dsv16b_tap_thresholds_t *val); 2935 2936 2937 typedef enum 2938 { 2939 LSM6DSV16B_XYZ = 0x3, 2940 LSM6DSV16B_YXZ = 0x5, 2941 LSM6DSV16B_XZY = 0x6, 2942 LSM6DSV16B_ZYX = 0x0, 2943 LSM6DSV16B_YZX = 0x1, 2944 LSM6DSV16B_ZXY = 0x2, 2945 } lsm6dsv16b_tap_axis_priority_t; 2946 int32_t lsm6dsv16b_tap_axis_priority_set(const stmdev_ctx_t *ctx, 2947 lsm6dsv16b_tap_axis_priority_t val); 2948 int32_t lsm6dsv16b_tap_axis_priority_get(const stmdev_ctx_t *ctx, 2949 lsm6dsv16b_tap_axis_priority_t *val); 2950 2951 typedef struct 2952 { 2953 uint8_t shock : 1; 2954 uint8_t quiet : 1; 2955 uint8_t tap_gap : 1; 2956 } lsm6dsv16b_tap_time_windows_t; 2957 int32_t lsm6dsv16b_tap_time_windows_set(const stmdev_ctx_t *ctx, 2958 lsm6dsv16b_tap_time_windows_t val); 2959 int32_t lsm6dsv16b_tap_time_windows_get(const stmdev_ctx_t *ctx, 2960 lsm6dsv16b_tap_time_windows_t *val); 2961 2962 typedef enum 2963 { 2964 LSM6DSV16B_ONLY_SINGLE = 0x0, 2965 LSM6DSV16B_BOTH_SINGLE_DOUBLE = 0x1, 2966 } lsm6dsv16b_tap_mode_t; 2967 int32_t lsm6dsv16b_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_tap_mode_t val); 2968 int32_t lsm6dsv16b_tap_mode_get(const stmdev_ctx_t *ctx, 2969 lsm6dsv16b_tap_mode_t *val); 2970 2971 typedef enum 2972 { 2973 LSM6DSV16B_DEG_80 = 0x0, 2974 LSM6DSV16B_DEG_70 = 0x1, 2975 LSM6DSV16B_DEG_60 = 0x2, 2976 LSM6DSV16B_DEG_50 = 0x3, 2977 } lsm6dsv16b_6d_threshold_t; 2978 int32_t lsm6dsv16b_6d_threshold_set(const stmdev_ctx_t *ctx, 2979 lsm6dsv16b_6d_threshold_t val); 2980 int32_t lsm6dsv16b_6d_threshold_get(const stmdev_ctx_t *ctx, 2981 lsm6dsv16b_6d_threshold_t *val); 2982 2983 int32_t lsm6dsv16b_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val); 2984 int32_t lsm6dsv16b_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val); 2985 2986 typedef enum 2987 { 2988 LSM6DSV16B_156_mg = 0x0, 2989 LSM6DSV16B_219_mg = 0x1, 2990 LSM6DSV16B_250_mg = 0x2, 2991 LSM6DSV16B_312_mg = 0x3, 2992 LSM6DSV16B_344_mg = 0x4, 2993 LSM6DSV16B_406_mg = 0x5, 2994 LSM6DSV16B_469_mg = 0x6, 2995 LSM6DSV16B_500_mg = 0x7, 2996 } lsm6dsv16b_ff_thresholds_t; 2997 int32_t lsm6dsv16b_ff_thresholds_set(const stmdev_ctx_t *ctx, 2998 lsm6dsv16b_ff_thresholds_t val); 2999 int32_t lsm6dsv16b_ff_thresholds_get(const stmdev_ctx_t *ctx, 3000 lsm6dsv16b_ff_thresholds_t *val); 3001 3002 int32_t lsm6dsv16b_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val); 3003 int32_t lsm6dsv16b_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val); 3004 3005 int32_t lsm6dsv16b_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val); 3006 int32_t lsm6dsv16b_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); 3007 3008 typedef enum 3009 { 3010 LSM6DSV16B_CMP_DISABLE = 0x0, 3011 LSM6DSV16B_CMP_8_TO_1 = 0x1, 3012 LSM6DSV16B_CMP_16_TO_1 = 0x2, 3013 LSM6DSV16B_CMP_32_TO_1 = 0x3, 3014 } lsm6dsv16b_fifo_compress_algo_t; 3015 int32_t lsm6dsv16b_fifo_compress_algo_set(const stmdev_ctx_t *ctx, 3016 lsm6dsv16b_fifo_compress_algo_t val); 3017 int32_t lsm6dsv16b_fifo_compress_algo_get(const stmdev_ctx_t *ctx, 3018 lsm6dsv16b_fifo_compress_algo_t *val); 3019 3020 int32_t lsm6dsv16b_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx, 3021 uint8_t val); 3022 int32_t lsm6dsv16b_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx, 3023 uint8_t *val); 3024 3025 int32_t lsm6dsv16b_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx, 3026 uint8_t val); 3027 int32_t lsm6dsv16b_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx, 3028 uint8_t *val); 3029 3030 int32_t lsm6dsv16b_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val); 3031 int32_t lsm6dsv16b_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val); 3032 3033 typedef enum 3034 { 3035 LSM6DSV16B_XL_NOT_BATCHED = 0x0, 3036 LSM6DSV16B_XL_BATCHED_AT_1Hz875 = 0x1, 3037 LSM6DSV16B_XL_BATCHED_AT_7Hz5 = 0x2, 3038 LSM6DSV16B_XL_BATCHED_AT_15Hz = 0x3, 3039 LSM6DSV16B_XL_BATCHED_AT_30Hz = 0x4, 3040 LSM6DSV16B_XL_BATCHED_AT_60Hz = 0x5, 3041 LSM6DSV16B_XL_BATCHED_AT_120Hz = 0x6, 3042 LSM6DSV16B_XL_BATCHED_AT_240Hz = 0x7, 3043 LSM6DSV16B_XL_BATCHED_AT_480Hz = 0x8, 3044 LSM6DSV16B_XL_BATCHED_AT_960Hz = 0x9, 3045 LSM6DSV16B_XL_BATCHED_AT_1920Hz = 0xA, 3046 LSM6DSV16B_XL_BATCHED_AT_3840Hz = 0xB, 3047 LSM6DSV16B_XL_BATCHED_AT_7680Hz = 0xC, 3048 } lsm6dsv16b_fifo_xl_batch_t; 3049 int32_t lsm6dsv16b_fifo_xl_batch_set(const stmdev_ctx_t *ctx, 3050 lsm6dsv16b_fifo_xl_batch_t val); 3051 int32_t lsm6dsv16b_fifo_xl_batch_get(const stmdev_ctx_t *ctx, 3052 lsm6dsv16b_fifo_xl_batch_t *val); 3053 3054 typedef enum 3055 { 3056 LSM6DSV16B_GY_NOT_BATCHED = 0x0, 3057 LSM6DSV16B_GY_BATCHED_AT_1Hz875 = 0x1, 3058 LSM6DSV16B_GY_BATCHED_AT_7Hz5 = 0x2, 3059 LSM6DSV16B_GY_BATCHED_AT_15Hz = 0x3, 3060 LSM6DSV16B_GY_BATCHED_AT_30Hz = 0x4, 3061 LSM6DSV16B_GY_BATCHED_AT_60Hz = 0x5, 3062 LSM6DSV16B_GY_BATCHED_AT_120Hz = 0x6, 3063 LSM6DSV16B_GY_BATCHED_AT_240Hz = 0x7, 3064 LSM6DSV16B_GY_BATCHED_AT_480Hz = 0x8, 3065 LSM6DSV16B_GY_BATCHED_AT_960Hz = 0x9, 3066 LSM6DSV16B_GY_BATCHED_AT_1920Hz = 0xa, 3067 LSM6DSV16B_GY_BATCHED_AT_3840Hz = 0xb, 3068 LSM6DSV16B_GY_BATCHED_AT_7680Hz = 0xc, 3069 } lsm6dsv16b_fifo_gy_batch_t; 3070 int32_t lsm6dsv16b_fifo_gy_batch_set(const stmdev_ctx_t *ctx, 3071 lsm6dsv16b_fifo_gy_batch_t val); 3072 int32_t lsm6dsv16b_fifo_gy_batch_get(const stmdev_ctx_t *ctx, 3073 lsm6dsv16b_fifo_gy_batch_t *val); 3074 3075 typedef enum 3076 { 3077 LSM6DSV16B_BYPASS_MODE = 0x0, 3078 LSM6DSV16B_FIFO_MODE = 0x1, 3079 LSM6DSV16B_STREAM_WTM_TO_FULL_MODE = 0x2, 3080 LSM6DSV16B_STREAM_TO_FIFO_MODE = 0x3, 3081 LSM6DSV16B_BYPASS_TO_STREAM_MODE = 0x4, 3082 LSM6DSV16B_STREAM_MODE = 0x6, 3083 LSM6DSV16B_BYPASS_TO_FIFO_MODE = 0x7, 3084 } lsm6dsv16b_fifo_mode_t; 3085 int32_t lsm6dsv16b_fifo_mode_set(const stmdev_ctx_t *ctx, 3086 lsm6dsv16b_fifo_mode_t val); 3087 int32_t lsm6dsv16b_fifo_mode_get(const stmdev_ctx_t *ctx, 3088 lsm6dsv16b_fifo_mode_t *val); 3089 3090 typedef enum 3091 { 3092 LSM6DSV16B_TEMP_NOT_BATCHED = 0x0, 3093 LSM6DSV16B_TEMP_BATCHED_AT_1Hz875 = 0x1, 3094 LSM6DSV16B_TEMP_BATCHED_AT_15Hz = 0x2, 3095 LSM6DSV16B_TEMP_BATCHED_AT_60Hz = 0x3, 3096 } lsm6dsv16b_fifo_temp_batch_t; 3097 int32_t lsm6dsv16b_fifo_temp_batch_set(const stmdev_ctx_t *ctx, 3098 lsm6dsv16b_fifo_temp_batch_t val); 3099 int32_t lsm6dsv16b_fifo_temp_batch_get(const stmdev_ctx_t *ctx, 3100 lsm6dsv16b_fifo_temp_batch_t *val); 3101 3102 typedef enum 3103 { 3104 LSM6DSV16B_TMSTMP_NOT_BATCHED = 0x0, 3105 LSM6DSV16B_TMSTMP_DEC_1 = 0x1, 3106 LSM6DSV16B_TMSTMP_DEC_8 = 0x2, 3107 LSM6DSV16B_TMSTMP_DEC_32 = 0x3, 3108 } lsm6dsv16b_fifo_timestamp_batch_t; 3109 int32_t lsm6dsv16b_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx, 3110 lsm6dsv16b_fifo_timestamp_batch_t val); 3111 int32_t lsm6dsv16b_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx, 3112 lsm6dsv16b_fifo_timestamp_batch_t *val); 3113 3114 int32_t lsm6dsv16b_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx, 3115 uint16_t val); 3116 int32_t lsm6dsv16b_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx, 3117 uint16_t *val); 3118 3119 typedef enum 3120 { 3121 LSM6DSV16B_XL_BATCH_EVENT = 0x0, 3122 LSM6DSV16B_GY_BATCH_EVENT = 0x1, 3123 } lsm6dsv16b_fifo_batch_cnt_event_t; 3124 int32_t lsm6dsv16b_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx, 3125 lsm6dsv16b_fifo_batch_cnt_event_t val); 3126 int32_t lsm6dsv16b_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx, 3127 lsm6dsv16b_fifo_batch_cnt_event_t *val); 3128 3129 typedef struct 3130 { 3131 uint8_t game_rotation : 1; 3132 uint8_t gravity : 1; 3133 uint8_t gbias : 1; 3134 } lsm6dsv16b_fifo_sflp_raw_t; 3135 int32_t lsm6dsv16b_fifo_sflp_batch_set(const stmdev_ctx_t *ctx, 3136 lsm6dsv16b_fifo_sflp_raw_t val); 3137 int32_t lsm6dsv16b_fifo_sflp_batch_get(const stmdev_ctx_t *ctx, 3138 lsm6dsv16b_fifo_sflp_raw_t *val); 3139 3140 typedef struct 3141 { 3142 uint16_t fifo_level : 9; 3143 uint8_t fifo_bdr : 1; 3144 uint8_t fifo_full : 1; 3145 uint8_t fifo_ovr : 1; 3146 uint8_t fifo_th : 1; 3147 } lsm6dsv16b_fifo_status_t; 3148 3149 int32_t lsm6dsv16b_fifo_status_get(const stmdev_ctx_t *ctx, 3150 lsm6dsv16b_fifo_status_t *val); 3151 3152 typedef struct 3153 { 3154 enum 3155 { 3156 LSM6DSV16B_FIFO_EMPTY = 0x0, 3157 LSM6DSV16B_GY_NC_TAG = 0x1, 3158 LSM6DSV16B_XL_NC_TAG = 0x2, 3159 LSM6DSV16B_TEMPERATURE_TAG = 0x3, 3160 LSM6DSV16B_TIMESTAMP_TAG = 0x4, 3161 LSM6DSV16B_CFG_CHANGE_TAG = 0x5, 3162 LSM6DSV16B_XL_NC_T_2_TAG = 0x6, 3163 LSM6DSV16B_XL_NC_T_1_TAG = 0x7, 3164 LSM6DSV16B_XL_2XC_TAG = 0x8, 3165 LSM6DSV16B_XL_3XC_TAG = 0x9, 3166 LSM6DSV16B_GY_NC_T_2_TAG = 0xA, 3167 LSM6DSV16B_GY_NC_T_1_TAG = 0xB, 3168 LSM6DSV16B_GY_2XC_TAG = 0xC, 3169 LSM6DSV16B_GY_3XC_TAG = 0xD, 3170 LSM6DSV16B_STEP_COUNTER_TAG = 0x12, 3171 LSM6DSV16B_SFLP_GAME_ROTATION_VECTOR_TAG = 0x13, 3172 LSM6DSV16B_SFLP_GYROSCOPE_BIAS_TAG = 0x16, 3173 LSM6DSV16B_SFLP_GRAVITY_VECTOR_TAG = 0x17, 3174 LSM6DSV16B_XL_DUAL_CORE = 0x1D, 3175 } tag; 3176 uint8_t cnt; 3177 uint8_t data[6]; 3178 } lsm6dsv16b_fifo_out_raw_t; 3179 int32_t lsm6dsv16b_fifo_out_raw_get(const stmdev_ctx_t *ctx, 3180 lsm6dsv16b_fifo_out_raw_t *val); 3181 3182 int32_t lsm6dsv16b_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val); 3183 int32_t lsm6dsv16b_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val); 3184 3185 typedef struct 3186 { 3187 uint8_t step_counter_enable : 1; 3188 uint8_t false_step_rej : 1; 3189 } lsm6dsv16b_stpcnt_mode_t; 3190 int32_t lsm6dsv16b_stpcnt_mode_set(const stmdev_ctx_t *ctx, 3191 lsm6dsv16b_stpcnt_mode_t val); 3192 int32_t lsm6dsv16b_stpcnt_mode_get(const stmdev_ctx_t *ctx, 3193 lsm6dsv16b_stpcnt_mode_t *val); 3194 3195 int32_t lsm6dsv16b_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); 3196 3197 int32_t lsm6dsv16b_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val); 3198 int32_t lsm6dsv16b_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val); 3199 3200 int32_t lsm6dsv16b_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val); 3201 int32_t lsm6dsv16b_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val); 3202 3203 int32_t lsm6dsv16b_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val); 3204 int32_t lsm6dsv16b_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val); 3205 3206 int32_t lsm6dsv16b_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 3207 int32_t lsm6dsv16b_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 3208 3209 int32_t lsm6dsv16b_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 3210 int32_t lsm6dsv16b_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 3211 3212 int32_t lsm6dsv16b_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint16_t val); 3213 int32_t lsm6dsv16b_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint16_t *val); 3214 3215 typedef struct 3216 { 3217 float_t gbias_x; /* dps */ 3218 float_t gbias_y; /* dps */ 3219 float_t gbias_z; /* dps */ 3220 } lsm6dsv16b_sflp_gbias_t; 3221 int32_t lsm6dsv16b_sflp_game_gbias_set(const stmdev_ctx_t *ctx, 3222 lsm6dsv16b_sflp_gbias_t *val); 3223 3224 int32_t lsm6dsv16b_sflp_configure(const stmdev_ctx_t *ctx); 3225 3226 typedef enum 3227 { 3228 LSM6DSV16B_SFLP_15Hz = 0x0, 3229 LSM6DSV16B_SFLP_30Hz = 0x1, 3230 LSM6DSV16B_SFLP_60Hz = 0x2, 3231 LSM6DSV16B_SFLP_120Hz = 0x3, 3232 LSM6DSV16B_SFLP_240Hz = 0x4, 3233 LSM6DSV16B_SFLP_480Hz = 0x5, 3234 } lsm6dsv16b_sflp_data_rate_t; 3235 int32_t lsm6dsv16b_sflp_data_rate_set(const stmdev_ctx_t *ctx, 3236 lsm6dsv16b_sflp_data_rate_t val); 3237 int32_t lsm6dsv16b_sflp_data_rate_get(const stmdev_ctx_t *ctx, 3238 lsm6dsv16b_sflp_data_rate_t *val); 3239 3240 typedef enum 3241 { 3242 LSM6DSV16B_PROTECT_CTRL_REGS = 0x0, 3243 LSM6DSV16B_WRITE_CTRL_REG = 0x1, 3244 } lsm6dsv16b_fsm_permission_t; 3245 int32_t lsm6dsv16b_fsm_permission_set(const stmdev_ctx_t *ctx, 3246 lsm6dsv16b_fsm_permission_t val); 3247 int32_t lsm6dsv16b_fsm_permission_get(const stmdev_ctx_t *ctx, 3248 lsm6dsv16b_fsm_permission_t *val); 3249 3250 typedef enum 3251 { 3252 LSM6DSV16B_STD_IF_CONTROL = 0x0, 3253 LSM6DSV16B_FSM_CONTROL = 0x1, 3254 } lsm6dsv16b_fsm_permission_status_t; 3255 int32_t lsm6dsv16b_fsm_permission_status(const stmdev_ctx_t *ctx, 3256 lsm6dsv16b_fsm_permission_status_t *val); 3257 3258 typedef struct 3259 { 3260 uint8_t fsm1_en : 1; 3261 uint8_t fsm2_en : 1; 3262 uint8_t fsm3_en : 1; 3263 uint8_t fsm4_en : 1; 3264 uint8_t fsm5_en : 1; 3265 uint8_t fsm6_en : 1; 3266 uint8_t fsm7_en : 1; 3267 uint8_t fsm8_en : 1; 3268 } lsm6dsv16b_fsm_mode_t; 3269 int32_t lsm6dsv16b_fsm_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_fsm_mode_t val); 3270 int32_t lsm6dsv16b_fsm_mode_get(const stmdev_ctx_t *ctx, 3271 lsm6dsv16b_fsm_mode_t *val); 3272 3273 int32_t lsm6dsv16b_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); 3274 int32_t lsm6dsv16b_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); 3275 3276 typedef struct 3277 { 3278 uint8_t fsm_outs1; 3279 uint8_t fsm_outs2; 3280 uint8_t fsm_outs3; 3281 uint8_t fsm_outs4; 3282 uint8_t fsm_outs5; 3283 uint8_t fsm_outs6; 3284 uint8_t fsm_outs7; 3285 uint8_t fsm_outs8; 3286 } lsm6dsv16b_fsm_out_t; 3287 int32_t lsm6dsv16b_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv16b_fsm_out_t *val); 3288 3289 typedef enum 3290 { 3291 LSM6DSV16B_FSM_15Hz = 0x0, 3292 LSM6DSV16B_FSM_30Hz = 0x1, 3293 LSM6DSV16B_FSM_60Hz = 0x2, 3294 LSM6DSV16B_FSM_120Hz = 0x3, 3295 LSM6DSV16B_FSM_240Hz = 0x4, 3296 LSM6DSV16B_FSM_480Hz = 0x5, 3297 LSM6DSV16B_FSM_960Hz = 0x6, 3298 } lsm6dsv16b_fsm_data_rate_t; 3299 int32_t lsm6dsv16b_fsm_data_rate_set(const stmdev_ctx_t *ctx, 3300 lsm6dsv16b_fsm_data_rate_t val); 3301 int32_t lsm6dsv16b_fsm_data_rate_get(const stmdev_ctx_t *ctx, 3302 lsm6dsv16b_fsm_data_rate_t *val); 3303 3304 int32_t lsm6dsv16b_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val); 3305 int32_t lsm6dsv16b_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val); 3306 3307 int32_t lsm6dsv16b_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val); 3308 int32_t lsm6dsv16b_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val); 3309 3310 int32_t lsm6dsv16b_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val); 3311 int32_t lsm6dsv16b_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val); 3312 3313 int32_t lsm6dsv16b_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val); 3314 int32_t lsm6dsv16b_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val); 3315 3316 typedef struct 3317 { 3318 float_t z_mg; 3319 float_t y_mg; 3320 float_t x_mg; 3321 } lsm6dsv16b_xl_offset_mg_t; 3322 int32_t lsm6dsv16b_xl_offset_mg_set(const stmdev_ctx_t *ctx, 3323 lsm6dsv16b_xl_offset_mg_t val); 3324 int32_t lsm6dsv16b_xl_offset_mg_get(const stmdev_ctx_t *ctx, 3325 lsm6dsv16b_xl_offset_mg_t *val); 3326 3327 typedef enum 3328 { 3329 LSM6DSV16B_SW_RST_DYN_ADDRESS_RST = 0x0, 3330 LSM6DSV16B_I3C_GLOBAL_RST = 0x1, 3331 } lsm6dsv16b_i3c_reset_mode_t; 3332 int32_t lsm6dsv16b_i3c_reset_mode_set(const stmdev_ctx_t *ctx, 3333 lsm6dsv16b_i3c_reset_mode_t val); 3334 int32_t lsm6dsv16b_i3c_reset_mode_get(const stmdev_ctx_t *ctx, 3335 lsm6dsv16b_i3c_reset_mode_t *val); 3336 3337 int32_t lsm6dsv16b_tdm_dis_wclk_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); 3338 int32_t lsm6dsv16b_tdm_dis_wclk_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); 3339 3340 int32_t lsm6dsv16b_tdm_tdmout_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val); 3341 int32_t lsm6dsv16b_tdm_tdmout_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val); 3342 3343 typedef enum 3344 { 3345 LSM6DSV16B_WCLK_16kHZ_BCLK_2048kHz = 0x1, 3346 LSM6DSV16B_WCLK_8kHZ_BCLK_2048kHz = 0x4, 3347 } lsm6dsv16b_tdm_wclk_bclk_t; 3348 int32_t lsm6dsv16b_tdm_wclk_bclk_set(const stmdev_ctx_t *ctx, 3349 lsm6dsv16b_tdm_wclk_bclk_t val); 3350 int32_t lsm6dsv16b_tdm_wclk_bclk_get(const stmdev_ctx_t *ctx, 3351 lsm6dsv16b_tdm_wclk_bclk_t *val); 3352 3353 typedef enum 3354 { 3355 LSM6DSV16B_SLOT_012 = 0x0, 3356 LSM6DSV16B_SLOT_456 = 0x1, 3357 } lsm6dsv16b_tdm_slot_t; 3358 int32_t lsm6dsv16b_tdm_slot_set(const stmdev_ctx_t *ctx, lsm6dsv16b_tdm_slot_t val); 3359 int32_t lsm6dsv16b_tdm_slot_get(const stmdev_ctx_t *ctx, 3360 lsm6dsv16b_tdm_slot_t *val); 3361 3362 typedef enum 3363 { 3364 LSM6DSV16B_BCLK_RISING = 0x0, 3365 LSM6DSV16B_BCLK_FALLING = 0x1, 3366 } lsm6dsv16b_tdm_bclk_edge_t; 3367 int32_t lsm6dsv16b_tdm_bclk_edge_set(const stmdev_ctx_t *ctx, 3368 lsm6dsv16b_tdm_bclk_edge_t val); 3369 int32_t lsm6dsv16b_tdm_bclk_edge_get(const stmdev_ctx_t *ctx, 3370 lsm6dsv16b_tdm_bclk_edge_t *val); 3371 3372 int32_t lsm6dsv16b_tdm_delayed_conf_set(const stmdev_ctx_t *ctx, uint8_t val); 3373 int32_t lsm6dsv16b_tdm_delayed_conf_get(const stmdev_ctx_t *ctx, uint8_t *val); 3374 3375 typedef enum 3376 { 3377 LSM6DSV16B_TDM_ORDER_ZYX = 0x0, 3378 LSM6DSV16B_TDM_ORDER_XZY = 0x1, 3379 LSM6DSV16B_TDM_ORDER_XYZ = 0x2, 3380 } lsm6dsv16b_tdm_axis_order_t; 3381 int32_t lsm6dsv16b_tdm_axis_order_set(const stmdev_ctx_t *ctx, 3382 lsm6dsv16b_tdm_axis_order_t val); 3383 int32_t lsm6dsv16b_tdm_axis_order_get(const stmdev_ctx_t *ctx, 3384 lsm6dsv16b_tdm_axis_order_t *val); 3385 3386 typedef enum 3387 { 3388 LSM6DSV16B_TDM_2g = 0x0, 3389 LSM6DSV16B_TDM_4g = 0x1, 3390 LSM6DSV16B_TDM_8g = 0x2, 3391 } lsm6dsv16b_tdm_xl_full_scale_t; 3392 int32_t lsm6dsv16b_tdm_xl_full_scale_set(const stmdev_ctx_t *ctx, 3393 lsm6dsv16b_tdm_xl_full_scale_t val); 3394 int32_t lsm6dsv16b_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx, 3395 lsm6dsv16b_tdm_xl_full_scale_t *val); 3396 3397 /** 3398 * @} 3399 * 3400 */ 3401 3402 #ifdef __cplusplus 3403 } 3404 #endif 3405 3406 #endif /*LSM6DSV16B_DRIVER_H */ 3407 3408 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 3409
