1 /**
2 ******************************************************************************
3 * @file lsm6dsv16b_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSV16B driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2024 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dsv16b_reg.h"
21
22 /**
23 * @defgroup LSM6DSV16B
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dsv16b enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup Interfaces functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx communication interface handler.(ptr)
43 * @param reg first register address to read.
44 * @param data buffer for data read.(ptr)
45 * @param len number of consecutive register to read.
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6dsv16b_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dsv16b_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx communication interface handler.(ptr)
69 * @param reg first register address to write.
70 * @param data the buffer contains data to be written.(ptr)
71 * @param len number of consecutive register to write.
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lsm6dsv16b_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lsm6dsv16b_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup Private functions
98 * @brief Section collect all the utility functions needed by APIs.
99 * @{
100 *
101 */
102
bytecpy(uint8_t * target,uint8_t * source)103 static void bytecpy(uint8_t *target, uint8_t *source)
104 {
105 if ((target != NULL) && (source != NULL))
106 {
107 *target = *source;
108 }
109 }
110
111 /**
112 * @}
113 *
114 */
115
116 /**
117 * @defgroup Sensitivity
118 * @brief These functions convert raw-data into engineering units.
119 * @{
120 *
121 */
lsm6dsv16b_from_sflp_to_mg(int16_t lsb)122 float_t lsm6dsv16b_from_sflp_to_mg(int16_t lsb)
123 {
124 return ((float_t)lsb) * 0.061f;
125 }
126
lsm6dsv16b_from_fs2_to_mg(int16_t lsb)127 float_t lsm6dsv16b_from_fs2_to_mg(int16_t lsb)
128 {
129 return ((float_t)lsb) * 0.061f;
130 }
131
lsm6dsv16b_from_fs4_to_mg(int16_t lsb)132 float_t lsm6dsv16b_from_fs4_to_mg(int16_t lsb)
133 {
134 return ((float_t)lsb) * 0.122f;
135 }
136
lsm6dsv16b_from_fs8_to_mg(int16_t lsb)137 float_t lsm6dsv16b_from_fs8_to_mg(int16_t lsb)
138 {
139 return ((float_t)lsb) * 0.244f;
140 }
141
lsm6dsv16b_from_fs16_to_mg(int16_t lsb)142 float_t lsm6dsv16b_from_fs16_to_mg(int16_t lsb)
143 {
144 return ((float_t)lsb) * 0.488f;
145 }
146
lsm6dsv16b_from_fs125_to_mdps(int16_t lsb)147 float_t lsm6dsv16b_from_fs125_to_mdps(int16_t lsb)
148 {
149 return ((float_t)lsb) * 4.375f;
150 }
151
lsm6dsv16b_from_fs250_to_mdps(int16_t lsb)152 float_t lsm6dsv16b_from_fs250_to_mdps(int16_t lsb)
153 {
154 return ((float_t)lsb) * 8.750f;
155 }
156
lsm6dsv16b_from_fs500_to_mdps(int16_t lsb)157 float_t lsm6dsv16b_from_fs500_to_mdps(int16_t lsb)
158 {
159 return ((float_t)lsb) * 17.50f;
160 }
161
lsm6dsv16b_from_fs1000_to_mdps(int16_t lsb)162 float_t lsm6dsv16b_from_fs1000_to_mdps(int16_t lsb)
163 {
164 return ((float_t)lsb) * 35.0f;
165 }
166
lsm6dsv16b_from_fs2000_to_mdps(int16_t lsb)167 float_t lsm6dsv16b_from_fs2000_to_mdps(int16_t lsb)
168 {
169 return ((float_t)lsb) * 70.0f;
170 }
171
lsm6dsv16b_from_fs4000_to_mdps(int16_t lsb)172 float_t lsm6dsv16b_from_fs4000_to_mdps(int16_t lsb)
173 {
174 return ((float_t)lsb) * 140.0f;
175 }
176
lsm6dsv16b_from_lsb_to_celsius(int16_t lsb)177 float_t lsm6dsv16b_from_lsb_to_celsius(int16_t lsb)
178 {
179 return (((float_t)lsb / 256.0f) + 25.0f);
180 }
181
lsm6dsv16b_from_lsb_to_nsec(uint32_t lsb)182 uint64_t lsm6dsv16b_from_lsb_to_nsec(uint32_t lsb)
183 {
184 return ((uint64_t)lsb * 21750);
185 }
186
lsm6dsv16b_from_lsb_to_mv(int16_t lsb)187 float_t lsm6dsv16b_from_lsb_to_mv(int16_t lsb)
188 {
189 return ((float_t)lsb) / 78.0f;
190 }
191
192 /**
193 * @}
194 *
195 */
196
197 /**
198 * @defgroup Common
199 * @brief This section groups common useful functions.
200 *
201 */
202
203 /**
204 * @brief Reset of the device.[set]
205 *
206 * @param ctx read / write interface definitions
207 * @param val Reset of the device.
208 * @retval interface status (MANDATORY: return 0 -> no Error)
209 *
210 */
lsm6dsv16b_reset_set(const stmdev_ctx_t * ctx,lsm6dsv16b_reset_t val)211 int32_t lsm6dsv16b_reset_set(const stmdev_ctx_t *ctx, lsm6dsv16b_reset_t val)
212 {
213 lsm6dsv16b_func_cfg_access_t func_cfg_access;
214 lsm6dsv16b_ctrl3_t ctrl3;
215 int32_t ret;
216
217 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1);
218 if (ret == 0)
219 {
220 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
221 }
222
223 ctrl3.boot = ((uint8_t)val & 0x04U) >> 2;
224 ctrl3.sw_reset = ((uint8_t)val & 0x02U) >> 1;
225 func_cfg_access.sw_por = (uint8_t)val & 0x01U;
226
227 if (ret == 0)
228 {
229 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1);
230 }
231 if (ret == 0)
232 {
233 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
234 }
235
236 return ret;
237 }
238
239 /**
240 * @brief Global reset of the device.[get]
241 *
242 * @param ctx read / write interface definitions
243 * @param val Global reset of the device.
244 * @retval interface status (MANDATORY: return 0 -> no Error)
245 *
246 */
lsm6dsv16b_reset_get(const stmdev_ctx_t * ctx,lsm6dsv16b_reset_t * val)247 int32_t lsm6dsv16b_reset_get(const stmdev_ctx_t *ctx, lsm6dsv16b_reset_t *val)
248 {
249 lsm6dsv16b_func_cfg_access_t func_cfg_access;
250 lsm6dsv16b_ctrl3_t ctrl3;
251 int32_t ret;
252
253 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1);
254 if (ret == 0)
255 {
256 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
257 }
258
259 switch ((ctrl3.sw_reset << 2) + (ctrl3.boot << 1) + func_cfg_access.sw_por)
260 {
261 case LSM6DSV16B_READY:
262 *val = LSM6DSV16B_READY;
263 break;
264
265 case LSM6DSV16B_GLOBAL_RST:
266 *val = LSM6DSV16B_GLOBAL_RST;
267 break;
268
269 case LSM6DSV16B_RESTORE_CAL_PARAM:
270 *val = LSM6DSV16B_RESTORE_CAL_PARAM;
271 break;
272
273 case LSM6DSV16B_RESTORE_CTRL_REGS:
274 *val = LSM6DSV16B_RESTORE_CTRL_REGS;
275 break;
276
277 default:
278 *val = LSM6DSV16B_GLOBAL_RST;
279 break;
280 }
281 return ret;
282 }
283
284 /**
285 * @brief Change memory bank.[set]
286 *
287 * @param ctx read / write interface definitions
288 * @param val MAIN_MEM_BANK, EMBED_FUNC_MEM_BANK,
289 * @retval interface status (MANDATORY: return 0 -> no Error)
290 *
291 */
lsm6dsv16b_mem_bank_set(const stmdev_ctx_t * ctx,lsm6dsv16b_mem_bank_t val)292 int32_t lsm6dsv16b_mem_bank_set(const stmdev_ctx_t *ctx, lsm6dsv16b_mem_bank_t val)
293 {
294 lsm6dsv16b_func_cfg_access_t func_cfg_access;
295 int32_t ret;
296
297 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
298 if (ret == 0)
299 {
300 func_cfg_access.emb_func_reg_access = (uint8_t)val & 0x01U;
301 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
302 }
303
304 return ret;
305 }
306
307 /**
308 * @brief Change memory bank.[get]
309 *
310 * @param ctx read / write interface definitions
311 * @param val MAIN_MEM_BANK, SENSOR_HUB_MEM_BANK, EMBED_FUNC_MEM_BANK,
312 * @retval interface status (MANDATORY: return 0 -> no Error)
313 *
314 */
lsm6dsv16b_mem_bank_get(const stmdev_ctx_t * ctx,lsm6dsv16b_mem_bank_t * val)315 int32_t lsm6dsv16b_mem_bank_get(const stmdev_ctx_t *ctx, lsm6dsv16b_mem_bank_t *val)
316 {
317 lsm6dsv16b_func_cfg_access_t func_cfg_access;
318 int32_t ret;
319
320 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
321
322 switch (func_cfg_access.emb_func_reg_access)
323 {
324 case LSM6DSV16B_MAIN_MEM_BANK:
325 *val = LSM6DSV16B_MAIN_MEM_BANK;
326 break;
327
328 case LSM6DSV16B_EMBED_FUNC_MEM_BANK:
329 *val = LSM6DSV16B_EMBED_FUNC_MEM_BANK;
330 break;
331
332 default:
333 *val = LSM6DSV16B_MAIN_MEM_BANK;
334 break;
335 }
336 return ret;
337 }
338
339 /**
340 * @brief Device ID.[get]
341 *
342 * @param ctx read / write interface definitions
343 * @param val Device ID.
344 * @retval interface status (MANDATORY: return 0 -> no Error)
345 *
346 */
lsm6dsv16b_device_id_get(const stmdev_ctx_t * ctx,uint8_t * val)347 int32_t lsm6dsv16b_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val)
348 {
349 lsm6dsv16b_who_am_i_t who_am_i;
350 int32_t ret;
351
352 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WHO_AM_I, (uint8_t *)&who_am_i, 1);
353 *val = who_am_i.id;
354
355 return ret;
356 }
357
358 /**
359 * @brief Accelerometer output data rate (ODR) selection.[set]
360 *
361 * @param ctx read / write interface definitions
362 * @param val lsm6dsv16b_xl_data_rate_t enum
363 * @retval interface status (MANDATORY: return 0 -> no Error)
364 *
365 */
lsm6dsv16b_xl_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv16b_xl_data_rate_t val)366 int32_t lsm6dsv16b_xl_data_rate_set(const stmdev_ctx_t *ctx,
367 lsm6dsv16b_xl_data_rate_t val)
368 {
369 lsm6dsv16b_ctrl1_t ctrl1;
370 int32_t ret;
371
372 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL1, (uint8_t *)&ctrl1, 1);
373 if (ret == 0)
374 {
375 ctrl1.odr_xl = (uint8_t)val & 0xFU;
376 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL1, (uint8_t *)&ctrl1, 1);
377 }
378
379 return ret;
380 }
381
382 /**
383 * @brief Accelerometer output data rate (ODR) selection.[get]
384 *
385 * @param ctx read / write interface definitions
386 * @param val lsm6dsv16b_xl_data_rate_t enum
387 * @retval interface status (MANDATORY: return 0 -> no Error)
388 *
389 */
lsm6dsv16b_xl_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv16b_xl_data_rate_t * val)390 int32_t lsm6dsv16b_xl_data_rate_get(const stmdev_ctx_t *ctx,
391 lsm6dsv16b_xl_data_rate_t *val)
392 {
393 lsm6dsv16b_ctrl1_t ctrl1;
394 int32_t ret;
395
396 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL1, (uint8_t *)&ctrl1, 1);
397
398 switch (ctrl1.odr_xl)
399 {
400 case LSM6DSV16B_XL_ODR_OFF:
401 *val = LSM6DSV16B_XL_ODR_OFF;
402 break;
403
404 case LSM6DSV16B_XL_ODR_AT_1Hz875:
405 *val = LSM6DSV16B_XL_ODR_AT_1Hz875;
406 break;
407
408 case LSM6DSV16B_XL_ODR_AT_7Hz5:
409 *val = LSM6DSV16B_XL_ODR_AT_7Hz5;
410 break;
411
412 case LSM6DSV16B_XL_ODR_AT_15Hz:
413 *val = LSM6DSV16B_XL_ODR_AT_15Hz;
414 break;
415
416 case LSM6DSV16B_XL_ODR_AT_30Hz:
417 *val = LSM6DSV16B_XL_ODR_AT_30Hz;
418 break;
419
420 case LSM6DSV16B_XL_ODR_AT_60Hz:
421 *val = LSM6DSV16B_XL_ODR_AT_60Hz;
422 break;
423
424 case LSM6DSV16B_XL_ODR_AT_120Hz:
425 *val = LSM6DSV16B_XL_ODR_AT_120Hz;
426 break;
427
428 case LSM6DSV16B_XL_ODR_AT_240Hz:
429 *val = LSM6DSV16B_XL_ODR_AT_240Hz;
430 break;
431
432 case LSM6DSV16B_XL_ODR_AT_480Hz:
433 *val = LSM6DSV16B_XL_ODR_AT_480Hz;
434 break;
435
436 case LSM6DSV16B_XL_ODR_AT_960Hz:
437 *val = LSM6DSV16B_XL_ODR_AT_960Hz;
438 break;
439
440 case LSM6DSV16B_XL_ODR_AT_1920Hz:
441 *val = LSM6DSV16B_XL_ODR_AT_1920Hz;
442 break;
443
444 case LSM6DSV16B_XL_ODR_AT_3840Hz:
445 *val = LSM6DSV16B_XL_ODR_AT_3840Hz;
446 break;
447
448 case LSM6DSV16B_XL_ODR_AT_7680Hz:
449 *val = LSM6DSV16B_XL_ODR_AT_7680Hz;
450 break;
451
452 default:
453 *val = LSM6DSV16B_XL_ODR_OFF;
454 break;
455 }
456 return ret;
457 }
458
459 /**
460 * @brief Accelerometer operating mode selection.[set]
461 *
462 * @param ctx read / write interface definitions
463 * @param val lsm6dsv16b_xl_mode_t struct
464 * @retval interface status (MANDATORY: return 0 -> no Error)
465 *
466 */
lsm6dsv16b_xl_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16b_xl_mode_t val)467 int32_t lsm6dsv16b_xl_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_xl_mode_t val)
468 {
469 lsm6dsv16b_ctrl1_t ctrl1;
470 int32_t ret;
471
472 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL1, (uint8_t *)&ctrl1, 1);
473
474 if (ret == 0)
475 {
476 ctrl1.op_mode_xl = (uint8_t)val & 0x07U;
477 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL1, (uint8_t *)&ctrl1, 1);
478 }
479
480 return ret;
481 }
482
483 /**
484 * @brief Accelerometer operating mode selection.[get]
485 *
486 * @param ctx read / write interface definitions
487 * @param val lsm6dsv16b_xl_mode_t struct
488 * @retval interface status (MANDATORY: return 0 -> no Error)
489 *
490 */
lsm6dsv16b_xl_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16b_xl_mode_t * val)491 int32_t lsm6dsv16b_xl_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_xl_mode_t *val)
492 {
493 lsm6dsv16b_ctrl1_t ctrl1;
494 int32_t ret;
495
496 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL1, (uint8_t *)&ctrl1, 1);
497
498 switch (ctrl1.op_mode_xl)
499 {
500 case LSM6DSV16B_XL_HIGH_PERFORMANCE_MD:
501 *val = LSM6DSV16B_XL_HIGH_PERFORMANCE_MD;
502 break;
503
504 case LSM6DSV16B_XL_HIGH_PERFORMANCE_TDM_MD:
505 *val = LSM6DSV16B_XL_HIGH_PERFORMANCE_TDM_MD;
506 break;
507
508 case LSM6DSV16B_XL_LOW_POWER_2_AVG_MD:
509 *val = LSM6DSV16B_XL_LOW_POWER_2_AVG_MD;
510 break;
511
512 case LSM6DSV16B_XL_LOW_POWER_4_AVG_MD:
513 *val = LSM6DSV16B_XL_LOW_POWER_4_AVG_MD;
514 break;
515
516 case LSM6DSV16B_XL_LOW_POWER_8_AVG_MD:
517 *val = LSM6DSV16B_XL_LOW_POWER_8_AVG_MD;
518 break;
519
520 default:
521 *val = LSM6DSV16B_XL_HIGH_PERFORMANCE_MD;
522 break;
523 }
524 return ret;
525 }
526
527 /**
528 * @brief Gyroscope output data rate (ODR) selection.[set]
529 *
530 * @param ctx read / write interface definitions
531 * @param val lsm6dsv16b_gy_data_rate_t enum
532 * @retval interface status (MANDATORY: return 0 -> no Error)
533 *
534 */
lsm6dsv16b_gy_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv16b_gy_data_rate_t val)535 int32_t lsm6dsv16b_gy_data_rate_set(const stmdev_ctx_t *ctx,
536 lsm6dsv16b_gy_data_rate_t val)
537 {
538 lsm6dsv16b_ctrl2_t ctrl2;
539 int32_t ret;
540
541 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL2, (uint8_t *)&ctrl2, 1);
542
543 if (ret == 0)
544 {
545 ctrl2.odr_g = (uint8_t)val & 0xFU;
546 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL2, (uint8_t *)&ctrl2, 1);
547 }
548
549 return ret;
550 }
551
552 /**
553 * @brief Gyroscope output data rate (ODR) selection.[get]
554 *
555 * @param ctx read / write interface definitions
556 * @param val lsm6dsv16b_gy_data_rate_t enum
557 * @retval interface status (MANDATORY: return 0 -> no Error)
558 *
559 */
lsm6dsv16b_gy_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv16b_gy_data_rate_t * val)560 int32_t lsm6dsv16b_gy_data_rate_get(const stmdev_ctx_t *ctx,
561 lsm6dsv16b_gy_data_rate_t *val)
562 {
563 lsm6dsv16b_ctrl2_t ctrl2;
564 int32_t ret;
565
566 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL2, (uint8_t *)&ctrl2, 1);
567
568 switch (ctrl2.odr_g)
569 {
570 case LSM6DSV16B_GY_ODR_OFF:
571 *val = LSM6DSV16B_GY_ODR_OFF;
572 break;
573
574 case LSM6DSV16B_GY_ODR_AT_7Hz5:
575 *val = LSM6DSV16B_GY_ODR_AT_7Hz5;
576 break;
577
578 case LSM6DSV16B_GY_ODR_AT_15Hz:
579 *val = LSM6DSV16B_GY_ODR_AT_15Hz;
580 break;
581
582 case LSM6DSV16B_GY_ODR_AT_30Hz:
583 *val = LSM6DSV16B_GY_ODR_AT_30Hz;
584 break;
585
586 case LSM6DSV16B_GY_ODR_AT_60Hz:
587 *val = LSM6DSV16B_GY_ODR_AT_60Hz;
588 break;
589
590 case LSM6DSV16B_GY_ODR_AT_120Hz:
591 *val = LSM6DSV16B_GY_ODR_AT_120Hz;
592 break;
593
594 case LSM6DSV16B_GY_ODR_AT_240Hz:
595 *val = LSM6DSV16B_GY_ODR_AT_240Hz;
596 break;
597
598 case LSM6DSV16B_GY_ODR_AT_480Hz:
599 *val = LSM6DSV16B_GY_ODR_AT_480Hz;
600 break;
601
602 case LSM6DSV16B_GY_ODR_AT_960Hz:
603 *val = LSM6DSV16B_GY_ODR_AT_960Hz;
604 break;
605
606 case LSM6DSV16B_GY_ODR_AT_1920Hz:
607 *val = LSM6DSV16B_GY_ODR_AT_1920Hz;
608 break;
609
610 case LSM6DSV16B_GY_ODR_AT_3840Hz:
611 *val = LSM6DSV16B_GY_ODR_AT_3840Hz;
612 break;
613
614 case LSM6DSV16B_GY_ODR_AT_7680Hz:
615 *val = LSM6DSV16B_GY_ODR_AT_7680Hz;
616 break;
617
618 default:
619 *val = LSM6DSV16B_GY_ODR_OFF;
620 break;
621 }
622 return ret;
623 }
624
625 /**
626 * @brief Gyroscope operating mode selection.[set]
627 *
628 * @param ctx read / write interface definitions
629 * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURANCY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD,
630 * @retval interface status (MANDATORY: return 0 -> no Error)
631 *
632 */
lsm6dsv16b_gy_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16b_gy_mode_t val)633 int32_t lsm6dsv16b_gy_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_gy_mode_t val)
634 {
635 lsm6dsv16b_ctrl2_t ctrl2;
636 int32_t ret;
637
638 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL2, (uint8_t *)&ctrl2, 1);
639 if (ret == 0)
640 {
641 ctrl2.op_mode_g = (uint8_t)val & 0x07U;
642 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL2, (uint8_t *)&ctrl2, 1);
643 }
644
645 return ret;
646 }
647
648 /**
649 * @brief Gyroscope operating mode selection.[get]
650 *
651 * @param ctx read / write interface definitions
652 * @param val GY_HIGH_PERFORMANCE_MD, GY_HIGH_ACCURANCY_ODR_MD, GY_SLEEP_MD, GY_LOW_POWER_MD,
653 * @retval interface status (MANDATORY: return 0 -> no Error)
654 *
655 */
lsm6dsv16b_gy_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16b_gy_mode_t * val)656 int32_t lsm6dsv16b_gy_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_gy_mode_t *val)
657 {
658 lsm6dsv16b_ctrl2_t ctrl2;
659 int32_t ret;
660
661 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL2, (uint8_t *)&ctrl2, 1);
662 switch (ctrl2.op_mode_g)
663 {
664 case LSM6DSV16B_GY_HIGH_PERFORMANCE_MD:
665 *val = LSM6DSV16B_GY_HIGH_PERFORMANCE_MD;
666 break;
667
668 case LSM6DSV16B_GY_SLEEP_MD:
669 *val = LSM6DSV16B_GY_SLEEP_MD;
670 break;
671
672 case LSM6DSV16B_GY_LOW_POWER_MD:
673 *val = LSM6DSV16B_GY_LOW_POWER_MD;
674 break;
675
676 default:
677 *val = LSM6DSV16B_GY_HIGH_PERFORMANCE_MD;
678 break;
679 }
680 return ret;
681 }
682
683 /**
684 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[set]
685 *
686 * @param ctx read / write interface definitions
687 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
688 * @retval interface status (MANDATORY: return 0 -> no Error)
689 *
690 */
lsm6dsv16b_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)691 int32_t lsm6dsv16b_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
692 {
693 lsm6dsv16b_ctrl3_t ctrl3;
694 int32_t ret;
695
696 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1);
697 if (ret == 0)
698 {
699 ctrl3.if_inc = val;
700 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1);
701 }
702
703 return ret;
704 }
705
706 /**
707 * @brief Register address automatically incremented during a multiple byte access with a serial interface (enable by default).[get]
708 *
709 * @param ctx read / write interface definitions
710 * @param val Register address automatically incremented during a multiple byte access with a serial interface (enable by default).
711 * @retval interface status (MANDATORY: return 0 -> no Error)
712 *
713 */
lsm6dsv16b_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)714 int32_t lsm6dsv16b_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
715 {
716 lsm6dsv16b_ctrl3_t ctrl3;
717 int32_t ret;
718
719 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1);
720 *val = ctrl3.if_inc;
721
722
723 return ret;
724 }
725
726 /**
727 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [set]
728 *
729 * @param ctx read / write interface definitions
730 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
731 * @retval interface status (MANDATORY: return 0 -> no Error)
732 *
733 */
lsm6dsv16b_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)734 int32_t lsm6dsv16b_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
735 {
736 lsm6dsv16b_ctrl3_t ctrl3;
737 int32_t ret;
738
739 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1);
740
741 if (ret == 0)
742 {
743 ctrl3.bdu = val;
744 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1);
745 }
746
747 return ret;
748 }
749
750 /**
751 * @brief Block Data Update (BDU): output registers are not updated until LSB and MSB have been read). [get]
752 *
753 * @param ctx read / write interface definitions
754 * @param val Block Data Update (BDU): output registers are not updated until LSB and MSB have been read).
755 * @retval interface status (MANDATORY: return 0 -> no Error)
756 *
757 */
lsm6dsv16b_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)758 int32_t lsm6dsv16b_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
759 {
760 lsm6dsv16b_ctrl3_t ctrl3;
761 int32_t ret;
762
763 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL3, (uint8_t *)&ctrl3, 1);
764 *val = ctrl3.bdu;
765
766 return ret;
767 }
768
769 /**
770 * @brief Enables pulsed data-ready mode (~75 us).[set]
771 *
772 * @param ctx read / write interface definitions
773 * @param val DRDY_LATCHED, DRDY_PULSED,
774 * @retval interface status (MANDATORY: return 0 -> no Error)
775 *
776 */
lsm6dsv16b_data_ready_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16b_data_ready_mode_t val)777 int32_t lsm6dsv16b_data_ready_mode_set(const stmdev_ctx_t *ctx,
778 lsm6dsv16b_data_ready_mode_t val)
779 {
780 lsm6dsv16b_ctrl4_t ctrl4;
781 int32_t ret;
782
783 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1);
784
785 if (ret == 0)
786 {
787 ctrl4.drdy_pulsed = (uint8_t)val & 0x1U;
788 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1);
789 }
790
791 return ret;
792 }
793
794 /**
795 * @brief Enables pulsed data-ready mode (~75 us).[get]
796 *
797 * @param ctx read / write interface definitions
798 * @param val DRDY_LATCHED, DRDY_PULSED,
799 * @retval interface status (MANDATORY: return 0 -> no Error)
800 *
801 */
lsm6dsv16b_data_ready_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16b_data_ready_mode_t * val)802 int32_t lsm6dsv16b_data_ready_mode_get(const stmdev_ctx_t *ctx,
803 lsm6dsv16b_data_ready_mode_t *val)
804 {
805 lsm6dsv16b_ctrl4_t ctrl4;
806 int32_t ret;
807
808 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1);
809
810 switch (ctrl4.drdy_pulsed)
811 {
812 case LSM6DSV16B_DRDY_LATCHED:
813 *val = LSM6DSV16B_DRDY_LATCHED;
814 break;
815
816 case LSM6DSV16B_DRDY_PULSED:
817 *val = LSM6DSV16B_DRDY_PULSED;
818 break;
819
820 default:
821 *val = LSM6DSV16B_DRDY_LATCHED;
822 break;
823 }
824 return ret;
825 }
826
827 /**
828 * @brief Gyroscope full-scale selection[set]
829 *
830 * @param ctx read / write interface definitions
831 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
832 * @retval interface status (MANDATORY: return 0 -> no Error)
833 *
834 */
lsm6dsv16b_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv16b_gy_full_scale_t val)835 int32_t lsm6dsv16b_gy_full_scale_set(const stmdev_ctx_t *ctx,
836 lsm6dsv16b_gy_full_scale_t val)
837 {
838 lsm6dsv16b_ctrl6_t ctrl6;
839 int32_t ret;
840
841 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL6, (uint8_t *)&ctrl6, 1);
842
843 if (ret == 0)
844 {
845 ctrl6.fs_g = (uint8_t)val & 0xFU;
846 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL6, (uint8_t *)&ctrl6, 1);
847 }
848
849 return ret;
850 }
851
852 /**
853 * @brief Gyroscope full-scale selection[get]
854 *
855 * @param ctx read / write interface definitions
856 * @param val 125dps, 250dps, 500dps, 1000dps, 2000dps, 4000dps,
857 * @retval interface status (MANDATORY: return 0 -> no Error)
858 *
859 */
lsm6dsv16b_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv16b_gy_full_scale_t * val)860 int32_t lsm6dsv16b_gy_full_scale_get(const stmdev_ctx_t *ctx,
861 lsm6dsv16b_gy_full_scale_t *val)
862 {
863 lsm6dsv16b_ctrl6_t ctrl6;
864 int32_t ret;
865
866 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL6, (uint8_t *)&ctrl6, 1);
867
868 switch (ctrl6.fs_g)
869 {
870 case LSM6DSV16B_125dps:
871 *val = LSM6DSV16B_125dps;
872 break;
873
874 case LSM6DSV16B_250dps:
875 *val = LSM6DSV16B_250dps;
876 break;
877
878 case LSM6DSV16B_500dps:
879 *val = LSM6DSV16B_500dps;
880 break;
881
882 case LSM6DSV16B_1000dps:
883 *val = LSM6DSV16B_1000dps;
884 break;
885
886 case LSM6DSV16B_2000dps:
887 *val = LSM6DSV16B_2000dps;
888 break;
889
890 case LSM6DSV16B_4000dps:
891 *val = LSM6DSV16B_4000dps;
892 break;
893
894 default:
895 *val = LSM6DSV16B_125dps;
896 break;
897 }
898 return ret;
899 }
900
901 /**
902 * @brief Accelerometer full-scale selection.[set]
903 *
904 * @param ctx read / write interface definitions
905 * @param val 2g, 4g, 8g, 16g,
906 * @retval interface status (MANDATORY: return 0 -> no Error)
907 *
908 */
lsm6dsv16b_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv16b_xl_full_scale_t val)909 int32_t lsm6dsv16b_xl_full_scale_set(const stmdev_ctx_t *ctx,
910 lsm6dsv16b_xl_full_scale_t val)
911 {
912 lsm6dsv16b_ctrl8_t ctrl8;
913 int32_t ret;
914
915 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1);
916
917 if (ret == 0)
918 {
919 ctrl8.fs_xl = (uint8_t)val & 0x3U;
920 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1);
921 }
922
923 return ret;
924 }
925
926 /**
927 * @brief Accelerometer full-scale selection.[get]
928 *
929 * @param ctx read / write interface definitions
930 * @param val 2g, 4g, 8g, 16g,
931 * @retval interface status (MANDATORY: return 0 -> no Error)
932 *
933 */
lsm6dsv16b_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv16b_xl_full_scale_t * val)934 int32_t lsm6dsv16b_xl_full_scale_get(const stmdev_ctx_t *ctx,
935 lsm6dsv16b_xl_full_scale_t *val)
936 {
937 lsm6dsv16b_ctrl8_t ctrl8;
938 int32_t ret;
939
940 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1);
941
942 switch (ctrl8.fs_xl)
943 {
944 case LSM6DSV16B_2g:
945 *val = LSM6DSV16B_2g;
946 break;
947
948 case LSM6DSV16B_4g:
949 *val = LSM6DSV16B_4g;
950 break;
951
952 case LSM6DSV16B_8g:
953 *val = LSM6DSV16B_8g;
954 break;
955
956 case LSM6DSV16B_16g:
957 *val = LSM6DSV16B_16g;
958 break;
959
960 default:
961 *val = LSM6DSV16B_2g;
962 break;
963 }
964 return ret;
965 }
966
967 /**
968 * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[set]
969 *
970 * @param ctx read / write interface definitions
971 * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.
972 * @retval interface status (MANDATORY: return 0 -> no Error)
973 *
974 */
lsm6dsv16b_xl_dual_channel_set(const stmdev_ctx_t * ctx,uint8_t val)975 int32_t lsm6dsv16b_xl_dual_channel_set(const stmdev_ctx_t *ctx, uint8_t val)
976 {
977 lsm6dsv16b_ctrl8_t ctrl8;
978 int32_t ret;
979
980 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1);
981
982 if (ret == 0)
983 {
984 ctrl8.xl_dualc_en = val;
985 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1);
986 }
987
988 return ret;
989 }
990
991 /**
992 * @brief It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.[get]
993 *
994 * @param ctx read / write interface definitions
995 * @param val It enables the accelerometer Dual channel mode: data with selected full scale and data with maximum full scale are sent simultaneously to two different set of output registers.
996 * @retval interface status (MANDATORY: return 0 -> no Error)
997 *
998 */
lsm6dsv16b_xl_dual_channel_get(const stmdev_ctx_t * ctx,uint8_t * val)999 int32_t lsm6dsv16b_xl_dual_channel_get(const stmdev_ctx_t *ctx, uint8_t *val)
1000 {
1001 lsm6dsv16b_ctrl8_t ctrl8;
1002 int32_t ret;
1003
1004 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1);
1005 *val = ctrl8.xl_dualc_en;
1006
1007 return ret;
1008 }
1009
1010 /**
1011 * @brief Accelerometer self-test selection.[set]
1012 *
1013 * @param ctx read / write interface definitions
1014 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1015 * @retval interface status (MANDATORY: return 0 -> no Error)
1016 *
1017 */
lsm6dsv16b_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6dsv16b_xl_self_test_t val)1018 int32_t lsm6dsv16b_xl_self_test_set(const stmdev_ctx_t *ctx,
1019 lsm6dsv16b_xl_self_test_t val)
1020 {
1021 lsm6dsv16b_ctrl10_t ctrl10;
1022 int32_t ret;
1023
1024 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1);
1025
1026 if (ret == 0)
1027 {
1028 ctrl10.st_xl = (uint8_t)val & 0x3U;
1029 ctrl10.xl_st_offset = ((uint8_t)val & 0x04U) >> 2;
1030 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1);
1031 }
1032
1033 return ret;
1034 }
1035
1036 /**
1037 * @brief Accelerometer self-test selection.[get]
1038 *
1039 * @param ctx read / write interface definitions
1040 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1041 * @retval interface status (MANDATORY: return 0 -> no Error)
1042 *
1043 */
lsm6dsv16b_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6dsv16b_xl_self_test_t * val)1044 int32_t lsm6dsv16b_xl_self_test_get(const stmdev_ctx_t *ctx,
1045 lsm6dsv16b_xl_self_test_t *val)
1046 {
1047 lsm6dsv16b_ctrl10_t ctrl10;
1048 int32_t ret;
1049
1050 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1);
1051
1052 //switch (ctrl10.xl_st_offset)
1053 switch (ctrl10.st_xl)
1054 {
1055 case LSM6DSV16B_XL_ST_DISABLE:
1056 *val = LSM6DSV16B_XL_ST_DISABLE;
1057 break;
1058
1059 case LSM6DSV16B_XL_ST_POSITIVE:
1060 *val = LSM6DSV16B_XL_ST_POSITIVE;
1061 break;
1062
1063 case LSM6DSV16B_XL_ST_NEGATIVE:
1064 *val = LSM6DSV16B_XL_ST_NEGATIVE;
1065 break;
1066
1067 default:
1068 *val = LSM6DSV16B_XL_ST_DISABLE;
1069 break;
1070 }
1071 return ret;
1072 }
1073
1074 /**
1075 * @brief Gyroscope self-test selection.[set]
1076 *
1077 * @param ctx read / write interface definitions
1078 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1079 * @retval interface status (MANDATORY: return 0 -> no Error)
1080 *
1081 */
lsm6dsv16b_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dsv16b_gy_self_test_t val)1082 int32_t lsm6dsv16b_gy_self_test_set(const stmdev_ctx_t *ctx,
1083 lsm6dsv16b_gy_self_test_t val)
1084 {
1085 lsm6dsv16b_ctrl10_t ctrl10;
1086 int32_t ret;
1087
1088 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1);
1089
1090 if (ret == 0)
1091 {
1092 ctrl10.st_g = (uint8_t)val & 0x3U;
1093 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1);
1094 }
1095
1096 return ret;
1097 }
1098
1099 /**
1100 * @brief Gyroscope self-test selection.[get]
1101 *
1102 * @param ctx read / write interface definitions
1103 * @param val XL_ST_DISABLE, XL_ST_POSITIVE, XL_ST_NEGATIVE,
1104 * @retval interface status (MANDATORY: return 0 -> no Error)
1105 *
1106 */
lsm6dsv16b_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dsv16b_gy_self_test_t * val)1107 int32_t lsm6dsv16b_gy_self_test_get(const stmdev_ctx_t *ctx,
1108 lsm6dsv16b_gy_self_test_t *val)
1109 {
1110 lsm6dsv16b_ctrl10_t ctrl10;
1111 int32_t ret;
1112
1113 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1);
1114
1115 switch (ctrl10.st_g)
1116 {
1117 case LSM6DSV16B_GY_ST_DISABLE:
1118 *val = LSM6DSV16B_GY_ST_DISABLE;
1119 break;
1120
1121 case LSM6DSV16B_GY_ST_POSITIVE:
1122 *val = LSM6DSV16B_GY_ST_POSITIVE;
1123 break;
1124
1125 case LSM6DSV16B_GY_ST_NEGATIVE:
1126 *val = LSM6DSV16B_GY_ST_NEGATIVE;
1127 break;
1128
1129 default:
1130 *val = LSM6DSV16B_GY_ST_DISABLE;
1131 break;
1132 }
1133 return ret;
1134 }
1135
1136 /**
1137 * @brief Get the status of all the interrupt sources.[get]
1138 *
1139 * @param ctx read / write interface definitions
1140 * @param val Get the status of all the interrupt sources.
1141 * @retval interface status (MANDATORY: return 0 -> no Error)
1142 *
1143 */
lsm6dsv16b_all_sources_get(const stmdev_ctx_t * ctx,lsm6dsv16b_all_sources_t * val)1144 int32_t lsm6dsv16b_all_sources_get(const stmdev_ctx_t *ctx,
1145 lsm6dsv16b_all_sources_t *val)
1146 {
1147 lsm6dsv16b_emb_func_status_mainpage_t emb_func_status_mainpage;
1148 lsm6dsv16b_emb_func_exec_status_t emb_func_exec_status;
1149 lsm6dsv16b_fsm_status_mainpage_t fsm_status_mainpage;
1150 lsm6dsv16b_functions_enable_t functions_enable;
1151 lsm6dsv16b_emb_func_src_t emb_func_src;
1152 lsm6dsv16b_fifo_status2_t fifo_status2;
1153 lsm6dsv16b_all_int_src_t all_int_src;
1154 lsm6dsv16b_wake_up_src_t wake_up_src;
1155 lsm6dsv16b_status_reg_t status_reg;
1156 lsm6dsv16b_d6d_src_t d6d_src;
1157 lsm6dsv16b_tap_src_t tap_src;
1158 uint8_t buff[6];
1159 int32_t ret;
1160
1161 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1162 if (ret == 0)
1163 {
1164 functions_enable.dis_rst_lir_all_int = PROPERTY_ENABLE;
1165 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1166 }
1167
1168 if (ret == 0)
1169 {
1170 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_STATUS1, (uint8_t *)&buff, 4);
1171 }
1172 bytecpy((uint8_t *)&fifo_status2, &buff[1]);
1173 bytecpy((uint8_t *)&all_int_src, &buff[2]);
1174 bytecpy((uint8_t *)&status_reg, &buff[3]);
1175
1176 val->fifo_ovr = fifo_status2.fifo_ovr_ia;
1177 val->fifo_bdr = fifo_status2.counter_bdr_ia;
1178 val->fifo_full = fifo_status2.fifo_full_ia;
1179 val->fifo_th = fifo_status2.fifo_wtm_ia;
1180
1181 val->free_fall = all_int_src.ff_ia;
1182 val->wake_up = all_int_src.wu_ia;
1183 val->six_d = all_int_src.d6d_ia;
1184
1185 val->drdy_xl = status_reg.xlda;
1186 val->drdy_gy = status_reg.gda;
1187 val->drdy_temp = status_reg.tda;
1188 val->timestamp = status_reg.timestamp_endcount;
1189
1190 if (ret == 0)
1191 {
1192 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1193 }
1194 if (ret == 0)
1195 {
1196 functions_enable.dis_rst_lir_all_int = PROPERTY_DISABLE;
1197 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1198 }
1199
1200 if (ret == 0)
1201 {
1202 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_SRC, (uint8_t *)&buff, 6);
1203 }
1204
1205 if (ret == 0)
1206 {
1207 bytecpy((uint8_t *)&wake_up_src, &buff[0]);
1208 bytecpy((uint8_t *)&tap_src, &buff[1]);
1209 bytecpy((uint8_t *)&d6d_src, &buff[2]);
1210 bytecpy((uint8_t *)&emb_func_status_mainpage, &buff[4]);
1211 bytecpy((uint8_t *)&fsm_status_mainpage, &buff[5]);
1212
1213 val->sleep_change = wake_up_src.sleep_change_ia;
1214 val->wake_up_x = wake_up_src.x_wu;
1215 val->wake_up_y = wake_up_src.y_wu;
1216 val->wake_up_z = wake_up_src.z_wu;
1217 val->sleep_state = wake_up_src.sleep_state;
1218
1219 val->tap_x = tap_src.x_tap;
1220 val->tap_y = tap_src.y_tap;
1221 val->tap_z = tap_src.z_tap;
1222 val->tap_sign = tap_src.tap_sign;
1223 val->double_tap = tap_src.double_tap;
1224 val->single_tap = tap_src.single_tap;
1225
1226 val->six_d_zl = d6d_src.zl;
1227 val->six_d_zh = d6d_src.zh;
1228 val->six_d_yl = d6d_src.yl;
1229 val->six_d_yh = d6d_src.yh;
1230 val->six_d_xl = d6d_src.xl;
1231 val->six_d_xh = d6d_src.xh;
1232
1233 val->step_detector = emb_func_status_mainpage.is_step_det;
1234 val->tilt = emb_func_status_mainpage.is_tilt;
1235 val->sig_mot = emb_func_status_mainpage.is_sigmot;
1236 val->fsm_lc = emb_func_status_mainpage.is_fsm_lc;
1237
1238 val->fsm1 = fsm_status_mainpage.is_fsm1;
1239 val->fsm2 = fsm_status_mainpage.is_fsm2;
1240 val->fsm3 = fsm_status_mainpage.is_fsm3;
1241 val->fsm4 = fsm_status_mainpage.is_fsm4;
1242 val->fsm5 = fsm_status_mainpage.is_fsm5;
1243 val->fsm6 = fsm_status_mainpage.is_fsm6;
1244 val->fsm7 = fsm_status_mainpage.is_fsm7;
1245 val->fsm8 = fsm_status_mainpage.is_fsm8;
1246
1247 }
1248
1249
1250 if (ret == 0)
1251 {
1252 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
1253 }
1254 if (ret == 0)
1255 {
1256 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EXEC_STATUS, (uint8_t *)&emb_func_exec_status,
1257 1);
1258 }
1259 if (ret == 0)
1260 {
1261 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
1262 }
1263
1264 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
1265
1266 val->emb_func_stand_by = emb_func_exec_status.emb_func_endop;
1267 val->emb_func_time_exceed = emb_func_exec_status.emb_func_exec_ovr;
1268 val->step_count_inc = emb_func_src.stepcounter_bit_set;
1269 val->step_count_overflow = emb_func_src.step_overflow;
1270 val->step_on_delta_time = emb_func_src.step_count_delta_ia;
1271
1272 val->step_detector = emb_func_src.step_detected;
1273
1274 return ret;
1275 }
1276
lsm6dsv16b_flag_data_ready_get(const stmdev_ctx_t * ctx,lsm6dsv16b_data_ready_t * val)1277 int32_t lsm6dsv16b_flag_data_ready_get(const stmdev_ctx_t *ctx,
1278 lsm6dsv16b_data_ready_t *val)
1279 {
1280 lsm6dsv16b_status_reg_t status;
1281 int32_t ret;
1282
1283 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_STATUS_REG, (uint8_t *)&status, 1);
1284 val->drdy_xl = status.xlda;
1285 val->drdy_gy = status.gda;
1286 val->drdy_temp = status.tda;
1287
1288 return ret;
1289 }
1290
1291 /**
1292 * @brief Temperature data output register[get]
1293 *
1294 * @param ctx read / write interface definitions
1295 * @param val Temperature data output register
1296 * @retval interface status (MANDATORY: return 0 -> no Error)
1297 *
1298 */
lsm6dsv16b_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1299 int32_t lsm6dsv16b_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1300 {
1301 uint8_t buff[2];
1302 int32_t ret;
1303
1304 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_OUT_TEMP_L, &buff[0], 2);
1305 *val = (int16_t)buff[1];
1306 *val = (*val * 256) + (int16_t)buff[0];
1307
1308 return ret;
1309 }
1310
1311 /**
1312 * @brief Angular rate sensor.[get]
1313 *
1314 * @param ctx read / write interface definitions
1315 * @param val Angular rate sensor.
1316 * @retval interface status (MANDATORY: return 0 -> no Error)
1317 *
1318 */
lsm6dsv16b_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1319 int32_t lsm6dsv16b_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1320 {
1321 uint8_t buff[6];
1322 int32_t ret;
1323
1324 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_OUTX_L_G, &buff[0], 6);
1325 val[0] = (int16_t)buff[1];
1326 val[0] = (val[0] * 256) + (int16_t)buff[0];
1327 val[1] = (int16_t)buff[3];
1328 val[1] = (val[1] * 256) + (int16_t)buff[2];
1329 val[2] = (int16_t)buff[5];
1330 val[2] = (val[2] * 256) + (int16_t)buff[4];
1331
1332 return ret;
1333 }
1334
1335 /**
1336 * @brief Linear acceleration sensor.[get]
1337 *
1338 * @param ctx read / write interface definitions
1339 * @param val Linear acceleration sensor.
1340 * @retval interface status (MANDATORY: return 0 -> no Error)
1341 *
1342 */
lsm6dsv16b_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1343 int32_t lsm6dsv16b_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1344 {
1345 uint8_t buff[6];
1346 int32_t ret;
1347
1348 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_OUTZ_L_A, &buff[0], 6);
1349 val[2] = (int16_t)buff[1];
1350 val[2] = (val[2] * 256) + (int16_t)buff[0];
1351 val[1] = (int16_t)buff[3];
1352 val[1] = (val[1] * 256) + (int16_t)buff[2];
1353 val[0] = (int16_t)buff[5];
1354 val[0] = (val[0] * 256) + (int16_t)buff[4];
1355
1356 return ret;
1357 }
1358
1359 /**
1360 * @brief Linear acceleration sensor for Dual channel mode.[get]
1361 *
1362 * @param ctx read / write interface definitions
1363 * @param val Linear acceleration sensor or Dual channel mode.
1364 * @retval interface status (MANDATORY: return 0 -> no Error)
1365 *
1366 */
lsm6dsv16b_dual_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1367 int32_t lsm6dsv16b_dual_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1368 {
1369 uint8_t buff[6];
1370 int32_t ret;
1371
1372 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_UI_OUTZ_L_A_DUALC, &buff[0], 6);
1373 val[2] = (int16_t)buff[1];
1374 val[2] = (val[2] * 256) + (int16_t)buff[0];
1375 val[1] = (int16_t)buff[3];
1376 val[1] = (val[1] * 256) + (int16_t)buff[2];
1377 val[0] = (int16_t)buff[5];
1378 val[0] = (val[0] * 256) + (int16_t)buff[4];
1379
1380 return ret;
1381 }
1382
1383 /**
1384 * @brief Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.[get]
1385 *
1386 * @param ctx read / write interface definitions
1387 * @param val Difference in percentage of the effective ODR (and timestamp rate) with respect to the typical. Step: 0.13%. 8-bit format, 2's complement.
1388 * @retval interface status (MANDATORY: return 0 -> no Error)
1389 *
1390 */
lsm6dsv16b_odr_cal_reg_get(const stmdev_ctx_t * ctx,int8_t * val)1391 int32_t lsm6dsv16b_odr_cal_reg_get(const stmdev_ctx_t *ctx, int8_t *val)
1392 {
1393 lsm6dsv16b_internal_freq_t internal_freq;
1394 int32_t ret;
1395
1396 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INTERNAL_FREQ, (uint8_t *)&internal_freq, 1);
1397 *val = (int8_t)internal_freq.freq_fine;
1398
1399 return ret;
1400 }
1401
1402 /**
1403 * @brief Enable accelerometer axis.[set]
1404 *
1405 * @param ctx read / write interface definitions
1406 * @param val Enable accelerometer axis.
1407 * @retval interface status (MANDATORY: return 0 -> no Error)
1408 *
1409 */
lsm6dsv16b_tdm_xl_axis_set(const stmdev_ctx_t * ctx,lsm6dsv16b_tdm_xl_axis_t val)1410 int32_t lsm6dsv16b_tdm_xl_axis_set(const stmdev_ctx_t *ctx, lsm6dsv16b_tdm_xl_axis_t val)
1411 {
1412 lsm6dsv16b_tdm_cfg1_t tdm_cfg1;
1413 int32_t ret;
1414
1415 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
1416 if (ret == 0)
1417 {
1418 tdm_cfg1.tdm_xl_z_en = val.z;
1419 tdm_cfg1.tdm_xl_y_en = val.y;
1420 tdm_cfg1.tdm_xl_x_en = val.x;
1421 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
1422 }
1423
1424 return ret;
1425 }
1426
1427 /**
1428 * @brief Enable accelerometer axis.[get]
1429 *
1430 * @param ctx read / write interface definitions
1431 * @param val Enable accelerometer axis.
1432 * @retval interface status (MANDATORY: return 0 -> no Error)
1433 *
1434 */
lsm6dsv16b_tdm_xl_axis_get(const stmdev_ctx_t * ctx,lsm6dsv16b_tdm_xl_axis_t * val)1435 int32_t lsm6dsv16b_tdm_xl_axis_get(const stmdev_ctx_t *ctx, lsm6dsv16b_tdm_xl_axis_t *val)
1436 {
1437 lsm6dsv16b_tdm_cfg1_t tdm_cfg1;
1438 int32_t ret;
1439
1440 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
1441 val->x = tdm_cfg1.tdm_xl_x_en;
1442 val->y = tdm_cfg1.tdm_xl_y_en;
1443 val->z = tdm_cfg1.tdm_xl_z_en;
1444
1445 return ret;
1446 }
1447
1448 /**
1449 * @brief Write buffer in a page.[set]
1450 *
1451 * @param ctx read / write interface definitions
1452 * @param val Write buffer in a page.
1453 * @retval interface status (MANDATORY: return 0 -> no Error)
1454 *
1455 */
lsm6dsv16b_ln_pg_write(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1456 int32_t lsm6dsv16b_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address,
1457 uint8_t *buf, uint8_t len)
1458 {
1459 lsm6dsv16b_page_address_t page_address;
1460 lsm6dsv16b_page_sel_t page_sel;
1461 lsm6dsv16b_page_rw_t page_rw;
1462 uint8_t msb;
1463 uint8_t lsb;
1464 int32_t ret;
1465 uint8_t i ;
1466
1467 msb = ((uint8_t)(address >> 8) & 0x0FU);
1468 lsb = (uint8_t)address & 0xFFU;
1469
1470 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
1471
1472 /* set page write */
1473 ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1);
1474 page_rw.page_read = PROPERTY_DISABLE;
1475 page_rw.page_write = PROPERTY_ENABLE;
1476 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1);
1477
1478 /* select page */
1479 ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, 1);
1480 page_sel.page_sel = msb;
1481 page_sel.not_used0 = 1; // Default value
1482 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel,
1483 1);
1484
1485 /* set page addr */
1486 page_address.page_addr = lsb;
1487 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_ADDRESS,
1488 (uint8_t *)&page_address, 1);
1489
1490 for (i = 0; ((i < len) && (ret == 0)); i++)
1491 {
1492 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_VALUE, &buf[i], 1);
1493 lsb++;
1494
1495 /* Check if page wrap */
1496 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
1497 {
1498 msb++;
1499 ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, 1);
1500
1501 if (ret == 0)
1502 {
1503 page_sel.page_sel = msb;
1504 page_sel.not_used0 = 1; // Default value
1505 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel,
1506 1);
1507 }
1508 }
1509 }
1510
1511 page_sel.page_sel = 0;
1512 page_sel.not_used0 = 1;// Default value
1513 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel,
1514 1);
1515
1516 /* unset page write */
1517 ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1);
1518 page_rw.page_read = PROPERTY_DISABLE;
1519 page_rw.page_write = PROPERTY_DISABLE;
1520 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1);
1521
1522 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
1523
1524 return ret;
1525 }
1526
1527 /**
1528 * @brief Read buffer in a page.[set]
1529 *
1530 * @param ctx read / write interface definitions
1531 * @param val Write buffer in a page.
1532 * @retval interface status (MANDATORY: return 0 -> no Error)
1533 *
1534 */
lsm6dsv16b_ln_pg_read(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1535 int32_t lsm6dsv16b_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address,
1536 uint8_t *buf, uint8_t len)
1537 {
1538 lsm6dsv16b_page_address_t page_address;
1539 lsm6dsv16b_page_sel_t page_sel;
1540 lsm6dsv16b_page_rw_t page_rw;
1541 uint8_t msb;
1542 uint8_t lsb;
1543 int32_t ret;
1544 uint8_t i ;
1545
1546 msb = ((uint8_t)(address >> 8) & 0x0FU);
1547 lsb = (uint8_t)address & 0xFFU;
1548
1549 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
1550
1551 /* set page write */
1552 ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1);
1553 page_rw.page_read = PROPERTY_ENABLE;
1554 page_rw.page_write = PROPERTY_DISABLE;
1555 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1);
1556
1557 /* select page */
1558 ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, 1);
1559 page_sel.page_sel = msb;
1560 page_sel.not_used0 = 1; // Default value
1561 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel,
1562 1);
1563
1564 /* set page addr */
1565 page_address.page_addr = lsb;
1566 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_ADDRESS,
1567 (uint8_t *)&page_address, 1);
1568
1569 for (i = 0; ((i < len) && (ret == 0)); i++)
1570 {
1571 ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_VALUE, &buf[i], 1);
1572 lsb++;
1573
1574 /* Check if page wrap */
1575 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
1576 {
1577 msb++;
1578 ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel, 1);
1579
1580 if (ret == 0)
1581 {
1582 page_sel.page_sel = msb;
1583 page_sel.not_used0 = 1; // Default value
1584 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel,
1585 1);
1586 }
1587 }
1588 }
1589
1590 page_sel.page_sel = 0;
1591 page_sel.not_used0 = 1;// Default value
1592 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_SEL, (uint8_t *)&page_sel,
1593 1);
1594
1595 /* unset page write */
1596 ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1);
1597 page_rw.page_read = PROPERTY_DISABLE;
1598 page_rw.page_write = PROPERTY_DISABLE;
1599 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1);
1600
1601 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
1602
1603 return ret;
1604 }
1605
1606 /**
1607 * @}
1608 *
1609 */
1610
1611 /**
1612 * @defgroup Timestamp
1613 * @brief This section groups all the functions that manage the
1614 * timestamp generation.
1615 * @{
1616 *
1617 */
1618
1619 /**
1620 * @brief Enables timestamp counter.[set]
1621 *
1622 * @param ctx read / write interface definitions
1623 * @param val Enables timestamp counter.
1624 * @retval interface status (MANDATORY: return 0 -> no Error)
1625 *
1626 */
lsm6dsv16b_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)1627 int32_t lsm6dsv16b_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
1628 {
1629 lsm6dsv16b_functions_enable_t functions_enable;
1630 int32_t ret;
1631
1632 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1633 if (ret == 0)
1634 {
1635 functions_enable.timestamp_en = val;
1636 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1637 }
1638
1639 return ret;
1640 }
1641
1642 /**
1643 * @brief Enables timestamp counter.[get]
1644 *
1645 * @param ctx read / write interface definitions
1646 * @param val Enables timestamp counter.
1647 * @retval interface status (MANDATORY: return 0 -> no Error)
1648 *
1649 */
lsm6dsv16b_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)1650 int32_t lsm6dsv16b_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
1651 {
1652 lsm6dsv16b_functions_enable_t functions_enable;
1653 int32_t ret;
1654
1655 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
1656 *val = functions_enable.timestamp_en;
1657
1658 return ret;
1659 }
1660
1661 /**
1662 * @brief Timestamp data output.[get]
1663 *
1664 * @param ctx read / write interface definitions
1665 * @param val Timestamp data output.
1666 * @retval interface status (MANDATORY: return 0 -> no Error)
1667 *
1668 */
lsm6dsv16b_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)1669 int32_t lsm6dsv16b_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
1670 {
1671 uint8_t buff[4];
1672 int32_t ret;
1673
1674 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TIMESTAMP0, &buff[0], 4);
1675 *val = buff[3];
1676 *val = (*val * 256U) + buff[2];
1677 *val = (*val * 256U) + buff[1];
1678 *val = (*val * 256U) + buff[0];
1679
1680 return ret;
1681 }
1682
1683 /**
1684 * @}
1685 *
1686 */
1687
1688 /**
1689 * @defgroup Filters
1690 * @brief This section group all the functions concerning the
1691 * filters configuration
1692 * @{
1693 *
1694 */
1695
1696 /**
1697 * @brief Protocol anti-spike filters.[set]
1698 *
1699 * @param ctx read / write interface definitions
1700 * @param val AUTO, ALWAYS_ACTIVE,
1701 * @retval interface status (MANDATORY: return 0 -> no Error)
1702 *
1703 */
lsm6dsv16b_filt_anti_spike_set(const stmdev_ctx_t * ctx,lsm6dsv16b_filt_anti_spike_t val)1704 int32_t lsm6dsv16b_filt_anti_spike_set(const stmdev_ctx_t *ctx,
1705 lsm6dsv16b_filt_anti_spike_t val)
1706 {
1707 lsm6dsv16b_if_cfg_t if_cfg;
1708 int32_t ret;
1709
1710 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
1711
1712 if (ret == 0)
1713 {
1714 if_cfg.asf_ctrl = (uint8_t)val & 0x01U;
1715 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
1716 }
1717
1718 return ret;
1719 }
1720
1721 /**
1722 * @brief Protocol anti-spike filters.[get]
1723 *
1724 * @param ctx read / write interface definitions
1725 * @param val AUTO, ALWAYS_ACTIVE,
1726 * @retval interface status (MANDATORY: return 0 -> no Error)
1727 *
1728 */
lsm6dsv16b_filt_anti_spike_get(const stmdev_ctx_t * ctx,lsm6dsv16b_filt_anti_spike_t * val)1729 int32_t lsm6dsv16b_filt_anti_spike_get(const stmdev_ctx_t *ctx,
1730 lsm6dsv16b_filt_anti_spike_t *val)
1731 {
1732 lsm6dsv16b_if_cfg_t if_cfg;
1733 int32_t ret;
1734
1735 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
1736 switch (if_cfg.asf_ctrl)
1737 {
1738 case LSM6DSV16B_AUTO:
1739 *val = LSM6DSV16B_AUTO;
1740 break;
1741
1742 case LSM6DSV16B_ALWAYS_ACTIVE:
1743 *val = LSM6DSV16B_ALWAYS_ACTIVE;
1744 break;
1745
1746 default:
1747 *val = LSM6DSV16B_AUTO;
1748 break;
1749 }
1750 return ret;
1751 }
1752
1753 /**
1754 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[set]
1755 *
1756 * @param ctx read / write interface definitions
1757 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
1758 * @retval interface status (MANDATORY: return 0 -> no Error)
1759 *
1760 */
lsm6dsv16b_filt_settling_mask_set(const stmdev_ctx_t * ctx,lsm6dsv16b_filt_settling_mask_t val)1761 int32_t lsm6dsv16b_filt_settling_mask_set(const stmdev_ctx_t *ctx,
1762 lsm6dsv16b_filt_settling_mask_t val)
1763 {
1764 lsm6dsv16b_emb_func_cfg_t emb_func_cfg;
1765 lsm6dsv16b_tdm_cfg2_t tdm_cfg2;
1766 lsm6dsv16b_ctrl4_t ctrl4;
1767 int32_t ret;
1768
1769 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1);
1770
1771 if (ret == 0)
1772 {
1773 ctrl4.drdy_mask = val.drdy;
1774
1775 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1);
1776 }
1777
1778 if (ret == 0)
1779 {
1780 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
1781 }
1782
1783 if (ret == 0)
1784 {
1785 emb_func_cfg.emb_func_irq_mask_xl_settl = val.irq_xl;
1786 emb_func_cfg.emb_func_irq_mask_g_settl = val.irq_g;
1787 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
1788 }
1789
1790 if (ret == 0)
1791 {
1792 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
1793 }
1794
1795 if (ret == 0)
1796 {
1797 tdm_cfg2.tdm_data_mask = val.tdm_excep_code;
1798 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
1799 }
1800
1801 return ret;
1802 }
1803
1804 /**
1805 * @brief It masks DRDY and Interrupts RQ until filter settling ends.[get]
1806 *
1807 * @param ctx read / write interface definitions
1808 * @param val It masks DRDY and Interrupts RQ until filter settling ends.
1809 * @retval interface status (MANDATORY: return 0 -> no Error)
1810 *
1811 */
lsm6dsv16b_filt_settling_mask_get(const stmdev_ctx_t * ctx,lsm6dsv16b_filt_settling_mask_t * val)1812 int32_t lsm6dsv16b_filt_settling_mask_get(const stmdev_ctx_t *ctx,
1813 lsm6dsv16b_filt_settling_mask_t *val)
1814 {
1815 lsm6dsv16b_emb_func_cfg_t emb_func_cfg;
1816 lsm6dsv16b_tdm_cfg2_t tdm_cfg2;
1817 lsm6dsv16b_ctrl4_t ctrl4;
1818 int32_t ret;
1819
1820 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1);
1821 if (ret == 0)
1822 {
1823 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_CFG, (uint8_t *)&emb_func_cfg, 1);
1824 }
1825 if (ret == 0)
1826 {
1827 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
1828 }
1829
1830 val->drdy = ctrl4.drdy_mask;
1831 val->irq_xl = emb_func_cfg.emb_func_irq_mask_xl_settl;
1832 val->irq_g = emb_func_cfg.emb_func_irq_mask_g_settl;
1833 val->tdm_excep_code = tdm_cfg2.tdm_data_mask;
1834
1835 return ret;
1836 }
1837
1838 /**
1839 * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[set]
1840 *
1841 * @param ctx read / write interface definitions
1842 * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME,
1843 * @retval interface status (MANDATORY: return 0 -> no Error)
1844 *
1845 */
lsm6dsv16b_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsv16b_filt_gy_lp1_bandwidth_t val)1846 int32_t lsm6dsv16b_filt_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
1847 lsm6dsv16b_filt_gy_lp1_bandwidth_t val)
1848 {
1849 lsm6dsv16b_ctrl6_t ctrl6;
1850 int32_t ret;
1851
1852 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL6, (uint8_t *)&ctrl6, 1);
1853 if (ret == 0)
1854 {
1855 ctrl6.lpf1_g_bw = (uint8_t)val & 0x7U;
1856 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL6, (uint8_t *)&ctrl6, 1);
1857 }
1858
1859 return ret;
1860 }
1861
1862 /**
1863 * @brief Gyroscope low-pass filter (LPF1) bandwidth selection.[get]
1864 *
1865 * @param ctx read / write interface definitions
1866 * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME,
1867 * @retval interface status (MANDATORY: return 0 -> no Error)
1868 *
1869 */
lsm6dsv16b_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsv16b_filt_gy_lp1_bandwidth_t * val)1870 int32_t lsm6dsv16b_filt_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
1871 lsm6dsv16b_filt_gy_lp1_bandwidth_t *val)
1872 {
1873 lsm6dsv16b_ctrl6_t ctrl6;
1874 int32_t ret;
1875
1876 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL6, (uint8_t *)&ctrl6, 1);
1877
1878 switch (ctrl6.lpf1_g_bw)
1879 {
1880 case LSM6DSV16B_GY_ULTRA_LIGHT:
1881 *val = LSM6DSV16B_GY_ULTRA_LIGHT;
1882 break;
1883
1884 case LSM6DSV16B_GY_VERY_LIGHT:
1885 *val = LSM6DSV16B_GY_VERY_LIGHT;
1886 break;
1887
1888 case LSM6DSV16B_GY_LIGHT:
1889 *val = LSM6DSV16B_GY_LIGHT;
1890 break;
1891
1892 case LSM6DSV16B_GY_MEDIUM:
1893 *val = LSM6DSV16B_GY_MEDIUM;
1894 break;
1895
1896 case LSM6DSV16B_GY_STRONG:
1897 *val = LSM6DSV16B_GY_STRONG;
1898 break;
1899
1900 case LSM6DSV16B_GY_VERY_STRONG:
1901 *val = LSM6DSV16B_GY_VERY_STRONG;
1902 break;
1903
1904 case LSM6DSV16B_GY_AGGRESSIVE:
1905 *val = LSM6DSV16B_GY_AGGRESSIVE;
1906 break;
1907
1908 case LSM6DSV16B_GY_XTREME:
1909 *val = LSM6DSV16B_GY_XTREME;
1910 break;
1911
1912 default:
1913 *val = LSM6DSV16B_GY_ULTRA_LIGHT;
1914 break;
1915 }
1916 return ret;
1917 }
1918
1919 /**
1920 * @brief It enables gyroscope digital LPF1 filter.[set]
1921 *
1922 * @param ctx read / write interface definitions
1923 * @param val It enables gyroscope digital LPF1 filter.
1924 * @retval interface status (MANDATORY: return 0 -> no Error)
1925 *
1926 */
lsm6dsv16b_filt_gy_lp1_set(const stmdev_ctx_t * ctx,uint8_t val)1927 int32_t lsm6dsv16b_filt_gy_lp1_set(const stmdev_ctx_t *ctx, uint8_t val)
1928 {
1929 lsm6dsv16b_ctrl7_t ctrl7;
1930 int32_t ret;
1931
1932 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL7, (uint8_t *)&ctrl7, 1);
1933
1934 if (ret == 0)
1935 {
1936 ctrl7.lpf1_g_en = val;
1937 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL7, (uint8_t *)&ctrl7, 1);
1938 }
1939
1940 return ret;
1941 }
1942
1943 /**
1944 * @brief It enables gyroscope digital LPF1 filter.[get]
1945 *
1946 * @param ctx read / write interface definitions
1947 * @param val It enables gyroscope digital LPF1 filter.
1948 * @retval interface status (MANDATORY: return 0 -> no Error)
1949 *
1950 */
lsm6dsv16b_filt_gy_lp1_get(const stmdev_ctx_t * ctx,uint8_t * val)1951 int32_t lsm6dsv16b_filt_gy_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val)
1952 {
1953 lsm6dsv16b_ctrl7_t ctrl7;
1954 int32_t ret;
1955
1956 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL7, (uint8_t *)&ctrl7, 1);
1957 *val = ctrl7.lpf1_g_en;
1958
1959 return ret;
1960 }
1961
1962 /**
1963 * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[set]
1964 *
1965 * @param ctx read / write interface definitions
1966 * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME,
1967 * @retval interface status (MANDATORY: return 0 -> no Error)
1968 *
1969 */
lsm6dsv16b_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsv16b_filt_xl_lp2_bandwidth_t val)1970 int32_t lsm6dsv16b_filt_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx,
1971 lsm6dsv16b_filt_xl_lp2_bandwidth_t val)
1972 {
1973 lsm6dsv16b_ctrl8_t ctrl8;
1974 int32_t ret;
1975
1976 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1);
1977 if (ret == 0)
1978 {
1979 ctrl8.hp_lpf2_xl_bw = (uint8_t)val & 0x7U;
1980 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1);
1981 }
1982
1983 return ret;
1984 }
1985
1986 /**
1987 * @brief Accelerometer LPF2 and high pass filter configuration and cutoff setting.[get]
1988 *
1989 * @param ctx read / write interface definitions
1990 * @param val ULTRA_LIGHT, VERY_LIGHT, LIGHT, MEDIUM, STRONG, VERY_STRONG, AGGRESSIVE, XTREME,
1991 * @retval interface status (MANDATORY: return 0 -> no Error)
1992 *
1993 */
lsm6dsv16b_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsv16b_filt_xl_lp2_bandwidth_t * val)1994 int32_t lsm6dsv16b_filt_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx,
1995 lsm6dsv16b_filt_xl_lp2_bandwidth_t *val)
1996 {
1997 lsm6dsv16b_ctrl8_t ctrl8;
1998 int32_t ret;
1999
2000 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL8, (uint8_t *)&ctrl8, 1);
2001 switch (ctrl8.hp_lpf2_xl_bw)
2002 {
2003 case LSM6DSV16B_XL_ULTRA_LIGHT:
2004 *val = LSM6DSV16B_XL_ULTRA_LIGHT;
2005 break;
2006
2007 case LSM6DSV16B_XL_VERY_LIGHT:
2008 *val = LSM6DSV16B_XL_VERY_LIGHT;
2009 break;
2010
2011 case LSM6DSV16B_XL_LIGHT:
2012 *val = LSM6DSV16B_XL_LIGHT;
2013 break;
2014
2015 case LSM6DSV16B_XL_MEDIUM:
2016 *val = LSM6DSV16B_XL_MEDIUM;
2017 break;
2018
2019 case LSM6DSV16B_XL_STRONG:
2020 *val = LSM6DSV16B_XL_STRONG;
2021 break;
2022
2023 case LSM6DSV16B_XL_VERY_STRONG:
2024 *val = LSM6DSV16B_XL_VERY_STRONG;
2025 break;
2026
2027 case LSM6DSV16B_XL_AGGRESSIVE:
2028 *val = LSM6DSV16B_XL_AGGRESSIVE;
2029 break;
2030
2031 case LSM6DSV16B_XL_XTREME:
2032 *val = LSM6DSV16B_XL_XTREME;
2033 break;
2034
2035 default:
2036 *val = LSM6DSV16B_XL_ULTRA_LIGHT;
2037 break;
2038 }
2039 return ret;
2040 }
2041
2042 /**
2043 * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[set]
2044 *
2045 * @param ctx read / write interface definitions
2046 * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.
2047 * @retval interface status (MANDATORY: return 0 -> no Error)
2048 *
2049 */
lsm6dsv16b_filt_xl_lp2_set(const stmdev_ctx_t * ctx,uint8_t val)2050 int32_t lsm6dsv16b_filt_xl_lp2_set(const stmdev_ctx_t *ctx, uint8_t val)
2051 {
2052 lsm6dsv16b_ctrl9_t ctrl9;
2053 int32_t ret;
2054
2055 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1);
2056 if (ret == 0)
2057 {
2058 ctrl9.lpf2_xl_en = val;
2059 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1);
2060 }
2061
2062 return ret;
2063 }
2064
2065 /**
2066 * @brief Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.[get]
2067 *
2068 * @param ctx read / write interface definitions
2069 * @param val Enable accelerometer LPS2 (Low Pass Filter 2) filtering stage.
2070 * @retval interface status (MANDATORY: return 0 -> no Error)
2071 *
2072 */
lsm6dsv16b_filt_xl_lp2_get(const stmdev_ctx_t * ctx,uint8_t * val)2073 int32_t lsm6dsv16b_filt_xl_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val)
2074 {
2075 lsm6dsv16b_ctrl9_t ctrl9;
2076 int32_t ret;
2077
2078 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1);
2079 *val = ctrl9.lpf2_xl_en;
2080
2081 return ret;
2082 }
2083
2084 /**
2085 * @brief Accelerometer slope filter / high-pass filter selection.[set]
2086 *
2087 * @param ctx read / write interface definitions
2088 * @param val Accelerometer slope filter / high-pass filter selection.
2089 * @retval interface status (MANDATORY: return 0 -> no Error)
2090 *
2091 */
lsm6dsv16b_filt_xl_hp_set(const stmdev_ctx_t * ctx,uint8_t val)2092 int32_t lsm6dsv16b_filt_xl_hp_set(const stmdev_ctx_t *ctx, uint8_t val)
2093 {
2094 lsm6dsv16b_ctrl9_t ctrl9;
2095 int32_t ret;
2096
2097 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1);
2098 if (ret == 0)
2099 {
2100 ctrl9.hp_slope_xl_en = val;
2101 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1);
2102 }
2103
2104 return ret;
2105 }
2106
2107 /**
2108 * @brief Accelerometer slope filter / high-pass filter selection.[get]
2109 *
2110 * @param ctx read / write interface definitions
2111 * @param val Accelerometer slope filter / high-pass filter selection.
2112 * @retval interface status (MANDATORY: return 0 -> no Error)
2113 *
2114 */
lsm6dsv16b_filt_xl_hp_get(const stmdev_ctx_t * ctx,uint8_t * val)2115 int32_t lsm6dsv16b_filt_xl_hp_get(const stmdev_ctx_t *ctx, uint8_t *val)
2116 {
2117 lsm6dsv16b_ctrl9_t ctrl9;
2118 int32_t ret;
2119
2120 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1);
2121 *val = ctrl9.hp_slope_xl_en;
2122
2123 return ret;
2124 }
2125
2126 /**
2127 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[set]
2128 *
2129 * @param ctx read / write interface definitions
2130 * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.
2131 * @retval interface status (MANDATORY: return 0 -> no Error)
2132 *
2133 */
lsm6dsv16b_filt_xl_fast_settling_set(const stmdev_ctx_t * ctx,uint8_t val)2134 int32_t lsm6dsv16b_filt_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val)
2135 {
2136 lsm6dsv16b_ctrl9_t ctrl9;
2137 int32_t ret;
2138
2139 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1);
2140 if (ret == 0)
2141 {
2142 ctrl9.xl_fastsettl_mode = val;
2143 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1);
2144 }
2145
2146 return ret;
2147 }
2148
2149 /**
2150 * @brief Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.[get]
2151 *
2152 * @param ctx read / write interface definitions
2153 * @param val Enables accelerometer LPF2 and HPF fast-settling mode. The filter sets the first sample.
2154 * @retval interface status (MANDATORY: return 0 -> no Error)
2155 *
2156 */
lsm6dsv16b_filt_xl_fast_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)2157 int32_t lsm6dsv16b_filt_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val)
2158 {
2159 lsm6dsv16b_ctrl9_t ctrl9;
2160 int32_t ret;
2161
2162 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1);
2163 *val = ctrl9.xl_fastsettl_mode;
2164
2165 return ret;
2166 }
2167
2168 /**
2169 * @brief Accelerometer high-pass filter mode.[set]
2170 *
2171 * @param ctx read / write interface definitions
2172 * @param val HP_MD_NORMAL, HP_MD_REFERENCE,
2173 * @retval interface status (MANDATORY: return 0 -> no Error)
2174 *
2175 */
lsm6dsv16b_filt_xl_hp_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16b_filt_xl_hp_mode_t val)2176 int32_t lsm6dsv16b_filt_xl_hp_mode_set(const stmdev_ctx_t *ctx,
2177 lsm6dsv16b_filt_xl_hp_mode_t val)
2178 {
2179 lsm6dsv16b_ctrl9_t ctrl9;
2180 int32_t ret;
2181
2182 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1);
2183 if (ret == 0)
2184 {
2185 ctrl9.hp_ref_mode_xl = (uint8_t)val & 0x01U;
2186 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1);
2187 }
2188
2189 return ret;
2190 }
2191
2192 /**
2193 * @brief Accelerometer high-pass filter mode.[get]
2194 *
2195 * @param ctx read / write interface definitions
2196 * @param val HP_MD_NORMAL, HP_MD_REFERENCE,
2197 * @retval interface status (MANDATORY: return 0 -> no Error)
2198 *
2199 */
lsm6dsv16b_filt_xl_hp_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16b_filt_xl_hp_mode_t * val)2200 int32_t lsm6dsv16b_filt_xl_hp_mode_get(const stmdev_ctx_t *ctx,
2201 lsm6dsv16b_filt_xl_hp_mode_t *val)
2202 {
2203 lsm6dsv16b_ctrl9_t ctrl9;
2204 int32_t ret;
2205
2206 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1);
2207 switch (ctrl9.hp_ref_mode_xl)
2208 {
2209 case LSM6DSV16B_HP_MD_NORMAL:
2210 *val = LSM6DSV16B_HP_MD_NORMAL;
2211 break;
2212
2213 case LSM6DSV16B_HP_MD_REFERENCE:
2214 *val = LSM6DSV16B_HP_MD_REFERENCE;
2215 break;
2216
2217 default:
2218 *val = LSM6DSV16B_HP_MD_NORMAL;
2219 break;
2220 }
2221 return ret;
2222 }
2223
2224 /**
2225 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[set]
2226 *
2227 * @param ctx read / write interface definitions
2228 * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS,
2229 * @retval interface status (MANDATORY: return 0 -> no Error)
2230 *
2231 */
lsm6dsv16b_filt_wkup_act_feed_set(const stmdev_ctx_t * ctx,lsm6dsv16b_filt_wkup_act_feed_t val)2232 int32_t lsm6dsv16b_filt_wkup_act_feed_set(const stmdev_ctx_t *ctx,
2233 lsm6dsv16b_filt_wkup_act_feed_t val)
2234 {
2235 lsm6dsv16b_wake_up_ths_t wake_up_ths;
2236 lsm6dsv16b_tap_cfg0_t tap_cfg0;
2237 int32_t ret;
2238
2239 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2240 if (ret == 0)
2241 {
2242 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
2243 }
2244
2245 tap_cfg0.slope_fds = (uint8_t)val & 0x01U;
2246 wake_up_ths.usr_off_on_wu = ((uint8_t)val & 0x02U) >> 1;
2247
2248 if (ret == 0)
2249 {
2250
2251 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2252 }
2253 if (ret == 0)
2254 {
2255
2256 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
2257 }
2258
2259 return ret;
2260 }
2261
2262 /**
2263 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity functions.[get]
2264 *
2265 * @param ctx read / write interface definitions
2266 * @param val WK_FEED_SLOPE, WK_FEED_HIGH_PASS,
2267 * @retval interface status (MANDATORY: return 0 -> no Error)
2268 *
2269 */
lsm6dsv16b_filt_wkup_act_feed_get(const stmdev_ctx_t * ctx,lsm6dsv16b_filt_wkup_act_feed_t * val)2270 int32_t lsm6dsv16b_filt_wkup_act_feed_get(const stmdev_ctx_t *ctx,
2271 lsm6dsv16b_filt_wkup_act_feed_t *val)
2272 {
2273 lsm6dsv16b_wake_up_ths_t wake_up_ths;
2274 lsm6dsv16b_tap_cfg0_t tap_cfg0;
2275 int32_t ret;
2276
2277 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
2278 if (ret == 0)
2279 {
2280 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2281 }
2282
2283 switch ((wake_up_ths.usr_off_on_wu << 1) + tap_cfg0.slope_fds)
2284 {
2285 case LSM6DSV16B_WK_FEED_SLOPE:
2286 *val = LSM6DSV16B_WK_FEED_SLOPE;
2287 break;
2288
2289 case LSM6DSV16B_WK_FEED_HIGH_PASS:
2290 *val = LSM6DSV16B_WK_FEED_HIGH_PASS;
2291 break;
2292
2293 case LSM6DSV16B_WK_FEED_LP_WITH_OFFSET:
2294 *val = LSM6DSV16B_WK_FEED_LP_WITH_OFFSET;
2295 break;
2296
2297 default:
2298 *val = LSM6DSV16B_WK_FEED_SLOPE;
2299 break;
2300 }
2301 return ret;
2302 }
2303
2304 /**
2305 * @brief Mask hw function triggers when xl is settling.[set]
2306 *
2307 * @param ctx read / write interface definitions
2308 * @param val 0 or 1,
2309 * @retval interface status (MANDATORY: return 0 -> no Error)
2310 *
2311 */
lsm6dsv16b_mask_trigger_xl_settl_set(const stmdev_ctx_t * ctx,uint8_t val)2312 int32_t lsm6dsv16b_mask_trigger_xl_settl_set(const stmdev_ctx_t *ctx, uint8_t val)
2313 {
2314 lsm6dsv16b_tap_cfg0_t tap_cfg0;
2315 int32_t ret;
2316
2317 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2318
2319 if (ret == 0)
2320 {
2321 tap_cfg0.hw_func_mask_xl_settl = val & 0x01U;
2322 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2323 }
2324
2325 return ret;
2326 }
2327
2328 /**
2329 * @brief Mask hw function triggers when xl is settling.[get]
2330 *
2331 * @param ctx read / write interface definitions
2332 * @param val 0 or 1,
2333 * @retval interface status (MANDATORY: return 0 -> no Error)
2334 *
2335 */
lsm6dsv16b_mask_trigger_xl_settl_get(const stmdev_ctx_t * ctx,uint8_t * val)2336 int32_t lsm6dsv16b_mask_trigger_xl_settl_get(const stmdev_ctx_t *ctx, uint8_t *val)
2337 {
2338 lsm6dsv16b_tap_cfg0_t tap_cfg0;
2339 int32_t ret;
2340
2341 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2342 *val = tap_cfg0.hw_func_mask_xl_settl;
2343
2344 return ret;
2345 }
2346
2347
2348 /**
2349 * @brief LPF2 filter on 6D (sixd) function selection.[set]
2350 *
2351 * @param ctx read / write interface definitions
2352 * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS,
2353 * @retval interface status (MANDATORY: return 0 -> no Error)
2354 *
2355 */
lsm6dsv16b_filt_sixd_feed_set(const stmdev_ctx_t * ctx,lsm6dsv16b_filt_sixd_feed_t val)2356 int32_t lsm6dsv16b_filt_sixd_feed_set(const stmdev_ctx_t *ctx,
2357 lsm6dsv16b_filt_sixd_feed_t val)
2358 {
2359 lsm6dsv16b_tap_cfg0_t tap_cfg0;
2360 int32_t ret;
2361
2362 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2363 if (ret == 0)
2364 {
2365 tap_cfg0.low_pass_on_6d = (uint8_t)val & 0x01U;
2366 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2367 }
2368
2369 return ret;
2370 }
2371
2372 /**
2373 * @brief LPF2 filter on 6D (sixd) function selection.[get]
2374 *
2375 * @param ctx read / write interface definitions
2376 * @param val SIXD_FEED_ODR_DIV_2, SIXD_FEED_LOW_PASS,
2377 * @retval interface status (MANDATORY: return 0 -> no Error)
2378 *
2379 */
lsm6dsv16b_filt_sixd_feed_get(const stmdev_ctx_t * ctx,lsm6dsv16b_filt_sixd_feed_t * val)2380 int32_t lsm6dsv16b_filt_sixd_feed_get(const stmdev_ctx_t *ctx,
2381 lsm6dsv16b_filt_sixd_feed_t *val)
2382 {
2383 lsm6dsv16b_tap_cfg0_t tap_cfg0;
2384 int32_t ret;
2385
2386 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2387 switch (tap_cfg0.low_pass_on_6d)
2388 {
2389 case LSM6DSV16B_SIXD_FEED_ODR_DIV_2:
2390 *val = LSM6DSV16B_SIXD_FEED_ODR_DIV_2;
2391 break;
2392
2393 case LSM6DSV16B_SIXD_FEED_LOW_PASS:
2394 *val = LSM6DSV16B_SIXD_FEED_LOW_PASS;
2395 break;
2396
2397 default:
2398 *val = LSM6DSV16B_SIXD_FEED_ODR_DIV_2;
2399 break;
2400 }
2401 return ret;
2402 }
2403
2404 /**
2405 * @}
2406 *
2407 */
2408
2409 /**
2410 * @defgroup Serial interfaces
2411 * @brief This section groups all the functions concerning
2412 * serial interfaces management (not auxiliary)
2413 * @{
2414 *
2415 */
2416
2417 /**
2418 * @brief Enables pull-up on SDO pin of UI (User Interface).[set]
2419 *
2420 * @param ctx read / write interface definitions
2421 * @param val Enables pull-up on SDO pin of UI (User Interface).
2422 * @retval interface status (MANDATORY: return 0 -> no Error)
2423 *
2424 */
lsm6dsv16b_ui_sdo_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)2425 int32_t lsm6dsv16b_ui_sdo_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
2426 {
2427 lsm6dsv16b_pin_ctrl_t pin_ctrl;
2428 int32_t ret;
2429
2430 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2431 if (ret == 0)
2432 {
2433 pin_ctrl.sdo_pu_en = val;
2434 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2435 }
2436
2437 return ret;
2438 }
2439
2440 /**
2441 * @brief Enables pull-up on SDO pin of UI (User Interface).[get]
2442 *
2443 * @param ctx read / write interface definitions
2444 * @param val Enables pull-up on SDO pin of UI (User Interface).
2445 * @retval interface status (MANDATORY: return 0 -> no Error)
2446 *
2447 */
lsm6dsv16b_ui_sdo_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)2448 int32_t lsm6dsv16b_ui_sdo_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
2449 {
2450 lsm6dsv16b_pin_ctrl_t pin_ctrl;
2451 int32_t ret;
2452
2453 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2454 *val = pin_ctrl.sdo_pu_en;
2455
2456 return ret;
2457 }
2458
2459 /**
2460 * @brief Disables I2C and I3C on UI (User Interface).[set]
2461 *
2462 * @param ctx read / write interface definitions
2463 * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE,
2464 * @retval interface status (MANDATORY: return 0 -> no Error)
2465 *
2466 */
lsm6dsv16b_ui_i2c_i3c_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16b_ui_i2c_i3c_mode_t val)2467 int32_t lsm6dsv16b_ui_i2c_i3c_mode_set(const stmdev_ctx_t *ctx,
2468 lsm6dsv16b_ui_i2c_i3c_mode_t val)
2469 {
2470 lsm6dsv16b_if_cfg_t if_cfg;
2471 int32_t ret;
2472
2473 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
2474 if (ret == 0)
2475 {
2476 if_cfg.i2c_i3c_disable = (uint8_t)val & 0x01U;
2477 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
2478 }
2479
2480 return ret;
2481 }
2482
2483 /**
2484 * @brief Disables I2C and I3C on UI (User Interface).[get]
2485 *
2486 * @param ctx read / write interface definitions
2487 * @param val I2C_I3C_ENABLE, I2C_I3C_DISABLE,
2488 * @retval interface status (MANDATORY: return 0 -> no Error)
2489 *
2490 */
lsm6dsv16b_ui_i2c_i3c_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16b_ui_i2c_i3c_mode_t * val)2491 int32_t lsm6dsv16b_ui_i2c_i3c_mode_get(const stmdev_ctx_t *ctx,
2492 lsm6dsv16b_ui_i2c_i3c_mode_t *val)
2493 {
2494 lsm6dsv16b_if_cfg_t if_cfg;
2495 int32_t ret;
2496
2497 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
2498 switch (if_cfg.i2c_i3c_disable)
2499 {
2500 case LSM6DSV16B_I2C_I3C_ENABLE:
2501 *val = LSM6DSV16B_I2C_I3C_ENABLE;
2502 break;
2503
2504 case LSM6DSV16B_I2C_I3C_DISABLE:
2505 *val = LSM6DSV16B_I2C_I3C_DISABLE;
2506 break;
2507
2508 default:
2509 *val = LSM6DSV16B_I2C_I3C_ENABLE;
2510 break;
2511 }
2512 return ret;
2513 }
2514
2515 /**
2516 * @brief SPI Serial Interface Mode selection.[set]
2517 *
2518 * @param ctx read / write interface definitions
2519 * @param val SPI_4_WIRE, SPI_3_WIRE,
2520 * @retval interface status (MANDATORY: return 0 -> no Error)
2521 *
2522 */
lsm6dsv16b_spi_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16b_spi_mode_t val)2523 int32_t lsm6dsv16b_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_spi_mode_t val)
2524 {
2525 lsm6dsv16b_if_cfg_t if_cfg;
2526 int32_t ret;
2527
2528 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
2529 if (ret == 0)
2530 {
2531 if_cfg.sim = (uint8_t)val & 0x01U;
2532 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
2533 }
2534
2535 return ret;
2536 }
2537
2538 /**
2539 * @brief SPI Serial Interface Mode selection.[get]
2540 *
2541 * @param ctx read / write interface definitions
2542 * @param val SPI_4_WIRE, SPI_3_WIRE,
2543 * @retval interface status (MANDATORY: return 0 -> no Error)
2544 *
2545 */
lsm6dsv16b_spi_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16b_spi_mode_t * val)2546 int32_t lsm6dsv16b_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_spi_mode_t *val)
2547 {
2548 lsm6dsv16b_if_cfg_t if_cfg;
2549 int32_t ret;
2550
2551 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
2552 switch (if_cfg.sim)
2553 {
2554 case LSM6DSV16B_SPI_4_WIRE:
2555 *val = LSM6DSV16B_SPI_4_WIRE;
2556 break;
2557
2558 case LSM6DSV16B_SPI_3_WIRE:
2559 *val = LSM6DSV16B_SPI_3_WIRE;
2560 break;
2561
2562 default:
2563 *val = LSM6DSV16B_SPI_4_WIRE;
2564 break;
2565 }
2566 return ret;
2567 }
2568
2569 /**
2570 * @brief Enables pull-up on SDA pin.[set]
2571 *
2572 * @param ctx read / write interface definitions
2573 * @param val Enables pull-up on SDA pin.
2574 * @retval interface status (MANDATORY: return 0 -> no Error)
2575 *
2576 */
lsm6dsv16b_ui_sda_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)2577 int32_t lsm6dsv16b_ui_sda_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
2578 {
2579 lsm6dsv16b_if_cfg_t if_cfg;
2580 int32_t ret;
2581
2582 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
2583 if (ret == 0)
2584 {
2585 if_cfg.sda_pu_en = (uint8_t)val & 0x01U;
2586 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
2587 }
2588
2589 return ret;
2590 }
2591
2592 /**
2593 * @brief Enables pull-up on SDA pin.[get]
2594 *
2595 * @param ctx read / write interface definitions
2596 * @param val Enables pull-up on SDA pin.
2597 * @retval interface status (MANDATORY: return 0 -> no Error)
2598 *
2599 */
lsm6dsv16b_ui_sda_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)2600 int32_t lsm6dsv16b_ui_sda_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
2601 {
2602 lsm6dsv16b_if_cfg_t if_cfg;
2603 int32_t ret;
2604
2605 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
2606 *val = if_cfg.sda_pu_en;
2607
2608 return ret;
2609 }
2610
2611 /**
2612 * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[set]
2613 *
2614 * @param ctx read / write interface definitions
2615 * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms,
2616 * @retval interface status (MANDATORY: return 0 -> no Error)
2617 *
2618 */
lsm6dsv16b_i3c_ibi_time_set(const stmdev_ctx_t * ctx,lsm6dsv16b_i3c_ibi_time_t val)2619 int32_t lsm6dsv16b_i3c_ibi_time_set(const stmdev_ctx_t *ctx,
2620 lsm6dsv16b_i3c_ibi_time_t val)
2621 {
2622 lsm6dsv16b_ctrl5_t ctrl5;
2623 int32_t ret;
2624
2625 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL5, (uint8_t *)&ctrl5, 1);
2626 if (ret == 0)
2627 {
2628 ctrl5.bus_act_sel = (uint8_t)val & 0x03U;
2629 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL5, (uint8_t *)&ctrl5, 1);
2630 }
2631
2632 return ret;
2633 }
2634
2635 /**
2636 * @brief Select the us activity time for IBI (In-Band Interrupt) with I3C[get]
2637 *
2638 * @param ctx read / write interface definitions
2639 * @param val IBI_2us, IBI_50us, IBI_1ms, IBI_25ms,
2640 * @retval interface status (MANDATORY: return 0 -> no Error)
2641 *
2642 */
lsm6dsv16b_i3c_ibi_time_get(const stmdev_ctx_t * ctx,lsm6dsv16b_i3c_ibi_time_t * val)2643 int32_t lsm6dsv16b_i3c_ibi_time_get(const stmdev_ctx_t *ctx,
2644 lsm6dsv16b_i3c_ibi_time_t *val)
2645 {
2646 lsm6dsv16b_ctrl5_t ctrl5;
2647 int32_t ret;
2648
2649 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL5, (uint8_t *)&ctrl5, 1);
2650 switch (ctrl5.bus_act_sel)
2651 {
2652 case LSM6DSV16B_IBI_2us:
2653 *val = LSM6DSV16B_IBI_2us;
2654 break;
2655
2656 case LSM6DSV16B_IBI_50us:
2657 *val = LSM6DSV16B_IBI_50us;
2658 break;
2659
2660 case LSM6DSV16B_IBI_1ms:
2661 *val = LSM6DSV16B_IBI_1ms;
2662 break;
2663
2664 case LSM6DSV16B_IBI_25ms:
2665 *val = LSM6DSV16B_IBI_25ms;
2666 break;
2667
2668 default:
2669 *val = LSM6DSV16B_IBI_2us;
2670 break;
2671 }
2672 return ret;
2673 }
2674
2675 /**
2676 * @}
2677 *
2678 */
2679
2680 /**
2681 * @defgroup Interrupt pins
2682 * @brief This section groups all the functions that manage interrupt pins
2683 * @{
2684 *
2685 */
2686
2687 /**
2688 * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[set]
2689 *
2690 * @param ctx read / write interface definitions
2691 * @param val PUSH_PULL, OPEN_DRAIN,
2692 * @retval interface status (MANDATORY: return 0 -> no Error)
2693 *
2694 */
lsm6dsv16b_int_pin_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16b_int_pin_mode_t val)2695 int32_t lsm6dsv16b_int_pin_mode_set(const stmdev_ctx_t *ctx,
2696 lsm6dsv16b_int_pin_mode_t val)
2697 {
2698 lsm6dsv16b_if_cfg_t if_cfg;
2699 int32_t ret;
2700
2701 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
2702 if (ret == 0)
2703 {
2704 if_cfg.pp_od = (uint8_t)val & 0x01U;
2705 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
2706 }
2707
2708 return ret;
2709 }
2710
2711 /**
2712 * @brief Push-pull/open-drain selection on INT1 and INT2 pins.[get]
2713 *
2714 * @param ctx read / write interface definitions
2715 * @param val PUSH_PULL, OPEN_DRAIN,
2716 * @retval interface status (MANDATORY: return 0 -> no Error)
2717 *
2718 */
lsm6dsv16b_int_pin_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16b_int_pin_mode_t * val)2719 int32_t lsm6dsv16b_int_pin_mode_get(const stmdev_ctx_t *ctx,
2720 lsm6dsv16b_int_pin_mode_t *val)
2721 {
2722 lsm6dsv16b_if_cfg_t if_cfg;
2723 int32_t ret;
2724
2725 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
2726 switch (if_cfg.pp_od)
2727 {
2728 case LSM6DSV16B_PUSH_PULL:
2729 *val = LSM6DSV16B_PUSH_PULL;
2730 break;
2731
2732 case LSM6DSV16B_OPEN_DRAIN:
2733 *val = LSM6DSV16B_OPEN_DRAIN;
2734 break;
2735
2736 default:
2737 *val = LSM6DSV16B_PUSH_PULL;
2738 break;
2739 }
2740 return ret;
2741 }
2742
2743 /**
2744 * @brief Interrupt activation level.[set]
2745 *
2746 * @param ctx read / write interface definitions
2747 * @param val ACTIVE_HIGH, ACTIVE_LOW,
2748 * @retval interface status (MANDATORY: return 0 -> no Error)
2749 *
2750 */
lsm6dsv16b_pin_polarity_set(const stmdev_ctx_t * ctx,lsm6dsv16b_pin_polarity_t val)2751 int32_t lsm6dsv16b_pin_polarity_set(const stmdev_ctx_t *ctx,
2752 lsm6dsv16b_pin_polarity_t val)
2753 {
2754 lsm6dsv16b_if_cfg_t if_cfg;
2755 int32_t ret;
2756
2757 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
2758 if (ret == 0)
2759 {
2760 if_cfg.h_lactive = (uint8_t)val & 0x01U;
2761 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
2762 }
2763
2764 return ret;
2765 }
2766
2767 /**
2768 * @brief Interrupt activation level.[get]
2769 *
2770 * @param ctx read / write interface definitions
2771 * @param val ACTIVE_HIGH, ACTIVE_LOW,
2772 * @retval interface status (MANDATORY: return 0 -> no Error)
2773 *
2774 */
lsm6dsv16b_pin_polarity_get(const stmdev_ctx_t * ctx,lsm6dsv16b_pin_polarity_t * val)2775 int32_t lsm6dsv16b_pin_polarity_get(const stmdev_ctx_t *ctx,
2776 lsm6dsv16b_pin_polarity_t *val)
2777 {
2778 lsm6dsv16b_if_cfg_t if_cfg;
2779 int32_t ret;
2780
2781 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
2782 switch (if_cfg.h_lactive)
2783 {
2784 case LSM6DSV16B_ACTIVE_HIGH:
2785 *val = LSM6DSV16B_ACTIVE_HIGH;
2786 break;
2787
2788 case LSM6DSV16B_ACTIVE_LOW:
2789 *val = LSM6DSV16B_ACTIVE_LOW;
2790 break;
2791
2792 default:
2793 *val = LSM6DSV16B_ACTIVE_HIGH;
2794 break;
2795 }
2796 return ret;
2797 }
2798
2799 /**
2800 * @brief It routes interrupt signals on INT 1 pin.[set]
2801 *
2802 * @param ctx read / write interface definitions
2803 * @param val It routes interrupt signals on INT 1 pin.
2804 * @retval interface status (MANDATORY: return 0 -> no Error)
2805 *
2806 */
lsm6dsv16b_pin_int1_route_set(const stmdev_ctx_t * ctx,lsm6dsv16b_pin_int_route_t val)2807 int32_t lsm6dsv16b_pin_int1_route_set(const stmdev_ctx_t *ctx,
2808 lsm6dsv16b_pin_int_route_t val)
2809 {
2810 lsm6dsv16b_functions_enable_t functions_enable;
2811 lsm6dsv16b_pin_int_route_t pin_int2_route;
2812 lsm6dsv16b_inactivity_dur_t inactivity_dur;
2813 lsm6dsv16b_emb_func_int1_t emb_func_int1;
2814 lsm6dsv16b_pedo_cmd_reg_t pedo_cmd_reg;
2815 lsm6dsv16b_int2_ctrl_t int2_ctrl;
2816 lsm6dsv16b_int1_ctrl_t int1_ctrl;
2817 lsm6dsv16b_fsm_int1_t fsm_int1;
2818 lsm6dsv16b_md1_cfg_t md1_cfg;
2819 lsm6dsv16b_md2_cfg_t md2_cfg;
2820 lsm6dsv16b_ctrl4_t ctrl4;
2821 int32_t ret;
2822
2823 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
2824 if (ret == 0)
2825 {
2826 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
2827 }
2828 if (ret == 0)
2829 {
2830 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_INT1, (uint8_t *)&fsm_int1, 1);
2831 }
2832
2833 if (ret == 0)
2834 {
2835 emb_func_int1.int1_step_detector = val.step_detector;
2836 emb_func_int1.int1_tilt = val.tilt;
2837 emb_func_int1.int1_sig_mot = val.sig_mot;
2838 emb_func_int1.int1_fsm_lc = val.fsm_lc;
2839 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
2840 }
2841 if (ret == 0)
2842 {
2843 fsm_int1.int1_fsm1 = val.fsm1;
2844 fsm_int1.int1_fsm2 = val.fsm2;
2845 fsm_int1.int1_fsm3 = val.fsm3;
2846 fsm_int1.int1_fsm4 = val.fsm4;
2847 fsm_int1.int1_fsm5 = val.fsm5;
2848 fsm_int1.int1_fsm6 = val.fsm6;
2849 fsm_int1.int1_fsm7 = val.fsm7;
2850 fsm_int1.int1_fsm8 = val.fsm8;
2851 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FSM_INT1, (uint8_t *)&fsm_int1, 1);
2852 }
2853
2854 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
2855
2856 if (ret == 0)
2857 {
2858 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1);
2859 }
2860 if (ret == 0)
2861 {
2862 if ((val.emb_func_stand_by | val.timestamp) != PROPERTY_DISABLE)
2863 {
2864 ctrl4.int2_on_int1 = PROPERTY_ENABLE;
2865 }
2866 else
2867 {
2868 ctrl4.int2_on_int1 = PROPERTY_DISABLE;
2869 }
2870 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1);
2871 }
2872
2873 if (ret == 0)
2874 {
2875 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2876 }
2877
2878 if (ret == 0)
2879 {
2880 int2_ctrl.int2_emb_func_endop = val.emb_func_stand_by;
2881 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2882 }
2883
2884
2885 if (ret == 0)
2886 {
2887 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2888 }
2889
2890 if (ret == 0)
2891 {
2892 md2_cfg.int2_timestamp = val.timestamp;
2893 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2894 }
2895
2896 if (ret == 0)
2897 {
2898 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
2899 }
2900
2901 if (ret == 0)
2902 {
2903 inactivity_dur.sleep_status_on_int = val.sleep_status;
2904 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
2905 }
2906
2907
2908 if (ret == 0)
2909 {
2910 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
2911 }
2912
2913 if (ret == 0)
2914 {
2915 int1_ctrl.int1_drdy_xl = val.drdy_xl;
2916 int1_ctrl.int1_drdy_g = val.drdy_gy;
2917 int1_ctrl.int1_fifo_th = val.fifo_th;
2918 int1_ctrl.int1_fifo_ovr = val.fifo_ovr;
2919 int1_ctrl.int1_fifo_full = val.fifo_full;
2920 int1_ctrl.int1_cnt_bdr = val.fifo_bdr;
2921 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
2922 }
2923
2924 if (ret == 0)
2925 {
2926 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD1_CFG, (uint8_t *)&md1_cfg, 1);
2927 }
2928
2929 if (ret == 0)
2930 {
2931 if ((emb_func_int1.int1_fsm_lc
2932 | emb_func_int1.int1_sig_mot
2933 | emb_func_int1.int1_step_detector
2934 | emb_func_int1.int1_tilt
2935 | fsm_int1.int1_fsm1
2936 | fsm_int1.int1_fsm2
2937 | fsm_int1.int1_fsm3
2938 | fsm_int1.int1_fsm4
2939 | fsm_int1.int1_fsm5
2940 | fsm_int1.int1_fsm6
2941 | fsm_int1.int1_fsm7
2942 | fsm_int1.int1_fsm8) != PROPERTY_DISABLE)
2943 {
2944 md1_cfg.int1_emb_func = PROPERTY_ENABLE;
2945 }
2946 else
2947 {
2948 md1_cfg.int1_emb_func = PROPERTY_DISABLE;
2949 }
2950 md1_cfg.int1_6d = val.six_d;
2951 md1_cfg.int1_double_tap = val.double_tap;
2952 md1_cfg.int1_ff = val.free_fall;
2953 md1_cfg.int1_wu = val.wake_up;
2954 md1_cfg.int1_single_tap = val.single_tap;
2955 if ((val.sleep_status | val.sleep_change) != PROPERTY_DISABLE)
2956 {
2957 md1_cfg.int1_sleep_change = PROPERTY_ENABLE;
2958 }
2959 else
2960 {
2961 md1_cfg.int1_sleep_change = PROPERTY_DISABLE;
2962 }
2963 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_MD1_CFG, (uint8_t *)&md1_cfg, 1);
2964 }
2965
2966 if (ret == 0)
2967 {
2968 ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
2969 }
2970
2971 if (ret == 0)
2972 {
2973 pedo_cmd_reg.carry_count_en = val.step_count_overflow;
2974 ret = lsm6dsv16b_ln_pg_write(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
2975 }
2976
2977
2978 if (ret == 0)
2979 {
2980 ret = lsm6dsv16b_pin_int2_route_get(ctx, &pin_int2_route);
2981 }
2982
2983 if (ret == 0)
2984 {
2985 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
2986 }
2987 if (ret == 0)
2988 {
2989 if ((pin_int2_route.six_d
2990 | pin_int2_route.double_tap
2991 | pin_int2_route.free_fall
2992 | pin_int2_route.wake_up
2993 | pin_int2_route.single_tap
2994 | pin_int2_route.sleep_status
2995 | pin_int2_route.sleep_change
2996 | val.six_d
2997 | val.double_tap
2998 | val.free_fall
2999 | val.wake_up
3000 | val.single_tap
3001 | val.sleep_status
3002 | val.sleep_change) != PROPERTY_DISABLE)
3003 {
3004 functions_enable.interrupts_enable = PROPERTY_ENABLE;
3005 }
3006
3007 else
3008 {
3009 functions_enable.interrupts_enable = PROPERTY_DISABLE;
3010 }
3011
3012 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3013 }
3014
3015 return ret;
3016 }
3017
3018 /**
3019 * @brief It routes interrupt signals on INT 1 pin.[get]
3020 *
3021 * @param ctx read / write interface definitions
3022 * @param val It routes interrupt signals on INT 1 pin.
3023 * @retval interface status (MANDATORY: return 0 -> no Error)
3024 *
3025 */
lsm6dsv16b_pin_int1_route_get(const stmdev_ctx_t * ctx,lsm6dsv16b_pin_int_route_t * val)3026 int32_t lsm6dsv16b_pin_int1_route_get(const stmdev_ctx_t *ctx,
3027 lsm6dsv16b_pin_int_route_t *val)
3028 {
3029 lsm6dsv16b_inactivity_dur_t inactivity_dur;
3030 lsm6dsv16b_emb_func_int1_t emb_func_int1;
3031 lsm6dsv16b_pedo_cmd_reg_t pedo_cmd_reg;
3032 lsm6dsv16b_int1_ctrl_t int1_ctrl;
3033 lsm6dsv16b_int2_ctrl_t int2_ctrl;
3034 lsm6dsv16b_fsm_int1_t fsm_int1;
3035 lsm6dsv16b_md1_cfg_t md1_cfg;
3036 lsm6dsv16b_md2_cfg_t md2_cfg;
3037 lsm6dsv16b_ctrl4_t ctrl4;
3038 int32_t ret;
3039
3040
3041 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1);
3042 if (ctrl4.int2_on_int1 == PROPERTY_ENABLE)
3043 {
3044 if (ret == 0)
3045 {
3046 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3047 val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop;
3048 }
3049 if (ret == 0)
3050 {
3051 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3052 val->timestamp = md2_cfg.int2_timestamp;
3053 }
3054 }
3055
3056 if (ret == 0)
3057 {
3058 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3059 val->sleep_status = inactivity_dur.sleep_status_on_int;
3060 }
3061
3062
3063 if (ret == 0)
3064 {
3065 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
3066 val->drdy_xl = int1_ctrl.int1_drdy_xl;
3067 val->drdy_gy = int1_ctrl.int1_drdy_g;
3068 val->fifo_th = int1_ctrl.int1_fifo_th;
3069 val->fifo_ovr = int1_ctrl.int1_fifo_ovr;
3070 val->fifo_full = int1_ctrl.int1_fifo_full;
3071 val->fifo_bdr = int1_ctrl.int1_cnt_bdr;
3072 }
3073
3074
3075 if (ret == 0)
3076 {
3077 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3078 val->six_d = md1_cfg.int1_6d;
3079 val->double_tap = md1_cfg.int1_double_tap;
3080 val->free_fall = md1_cfg.int1_ff;
3081 val->wake_up = md1_cfg.int1_wu;
3082 val->single_tap = md1_cfg.int1_single_tap;
3083 val->sleep_change = md1_cfg.int1_sleep_change;
3084 }
3085
3086 if (ret == 0)
3087 {
3088 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
3089 }
3090 if (ret == 0)
3091 {
3092 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
3093 val->step_detector = emb_func_int1.int1_step_detector;
3094 val->tilt = emb_func_int1.int1_tilt;
3095 val->sig_mot = emb_func_int1.int1_sig_mot;
3096 val->fsm_lc = emb_func_int1.int1_fsm_lc;
3097 }
3098 if (ret == 0)
3099 {
3100 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_INT1, (uint8_t *)&fsm_int1, 1);
3101 val->fsm1 = fsm_int1.int1_fsm1;
3102 val->fsm2 = fsm_int1.int1_fsm2;
3103 val->fsm3 = fsm_int1.int1_fsm3;
3104 val->fsm4 = fsm_int1.int1_fsm4;
3105 val->fsm5 = fsm_int1.int1_fsm5;
3106 val->fsm6 = fsm_int1.int1_fsm6;
3107 val->fsm7 = fsm_int1.int1_fsm7;
3108 val->fsm8 = fsm_int1.int1_fsm8;
3109 }
3110
3111 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
3112
3113 if (ret == 0)
3114 {
3115 ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3116 val->step_count_overflow = pedo_cmd_reg.carry_count_en;
3117 }
3118
3119 return ret;
3120 }
3121
3122
3123 /**
3124 * @brief It routes interrupt signals on INT 2 pin.[set]
3125 *
3126 * @param ctx read / write interface definitions
3127 * @param val It routes interrupt signals on INT 2 pin.
3128 * @retval interface status (MANDATORY: return 0 -> no Error)
3129 *
3130 */
lsm6dsv16b_pin_int2_route_set(const stmdev_ctx_t * ctx,lsm6dsv16b_pin_int_route_t val)3131 int32_t lsm6dsv16b_pin_int2_route_set(const stmdev_ctx_t *ctx,
3132 lsm6dsv16b_pin_int_route_t val)
3133 {
3134 lsm6dsv16b_functions_enable_t functions_enable;
3135 lsm6dsv16b_pin_int_route_t pin_int1_route;
3136 lsm6dsv16b_inactivity_dur_t inactivity_dur;
3137 lsm6dsv16b_emb_func_int2_t emb_func_int2;
3138 lsm6dsv16b_pedo_cmd_reg_t pedo_cmd_reg;
3139 lsm6dsv16b_int2_ctrl_t int2_ctrl;
3140 lsm6dsv16b_fsm_int2_t fsm_int2;
3141 lsm6dsv16b_md2_cfg_t md2_cfg;
3142 lsm6dsv16b_ctrl4_t ctrl4;
3143 int32_t ret;
3144
3145
3146 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
3147 if (ret == 0)
3148 {
3149 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
3150 }
3151 if (ret == 0)
3152 {
3153 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_INT2, (uint8_t *)&fsm_int2, 1);
3154 }
3155
3156 if (ret == 0)
3157 {
3158 emb_func_int2.int2_step_detector = val.step_detector;
3159 emb_func_int2.int2_tilt = val.tilt;
3160 emb_func_int2.int2_sig_mot = val.sig_mot;
3161 emb_func_int2.int2_fsm_lc = val.fsm_lc;
3162 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
3163 }
3164 if (ret == 0)
3165 {
3166 fsm_int2.int2_fsm1 = val.fsm1;
3167 fsm_int2.int2_fsm2 = val.fsm2;
3168 fsm_int2.int2_fsm3 = val.fsm3;
3169 fsm_int2.int2_fsm4 = val.fsm4;
3170 fsm_int2.int2_fsm5 = val.fsm5;
3171 fsm_int2.int2_fsm6 = val.fsm6;
3172 fsm_int2.int2_fsm7 = val.fsm7;
3173 fsm_int2.int2_fsm8 = val.fsm8;
3174 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FSM_INT2, (uint8_t *)&fsm_int2, 1);
3175 }
3176
3177 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
3178
3179 if (ret == 0)
3180 {
3181 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1);
3182 }
3183 if (ret == 0)
3184 {
3185 if ((val.emb_func_stand_by | val.timestamp) != PROPERTY_DISABLE)
3186 {
3187 ctrl4.int2_on_int1 = PROPERTY_DISABLE;
3188 }
3189 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1);
3190 }
3191
3192 if (ret == 0)
3193 {
3194 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3195 }
3196
3197 if (ret == 0)
3198 {
3199 inactivity_dur.sleep_status_on_int = val.sleep_status;
3200 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3201 }
3202
3203 if (ret == 0)
3204 {
3205 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3206 }
3207
3208 if (ret == 0)
3209 {
3210 int2_ctrl.int2_drdy_xl = val.drdy_xl;
3211 int2_ctrl.int2_drdy_g = val.drdy_gy;
3212 int2_ctrl.int2_fifo_th = val.fifo_th;
3213 int2_ctrl.int2_fifo_ovr = val.fifo_ovr;
3214 int2_ctrl.int2_fifo_full = val.fifo_full;
3215 int2_ctrl.int2_cnt_bdr = val.fifo_bdr;
3216 int2_ctrl.int2_emb_func_endop = val.emb_func_stand_by;
3217 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3218 }
3219
3220 if (ret == 0)
3221 {
3222 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3223 }
3224
3225 if (ret == 0)
3226 {
3227 if ((emb_func_int2.int2_fsm_lc
3228 | emb_func_int2.int2_sig_mot
3229 | emb_func_int2.int2_step_detector
3230 | emb_func_int2.int2_tilt
3231 | fsm_int2.int2_fsm1
3232 | fsm_int2.int2_fsm2
3233 | fsm_int2.int2_fsm3
3234 | fsm_int2.int2_fsm4
3235 | fsm_int2.int2_fsm5
3236 | fsm_int2.int2_fsm6
3237 | fsm_int2.int2_fsm7
3238 | fsm_int2.int2_fsm8) != PROPERTY_DISABLE)
3239 {
3240 md2_cfg.int2_emb_func = PROPERTY_ENABLE;
3241 }
3242 else
3243 {
3244 md2_cfg.int2_emb_func = PROPERTY_DISABLE;
3245 }
3246 md2_cfg.int2_6d = val.six_d;
3247 md2_cfg.int2_double_tap = val.double_tap;
3248 md2_cfg.int2_ff = val.free_fall;
3249 md2_cfg.int2_wu = val.wake_up;
3250 md2_cfg.int2_single_tap = val.single_tap;
3251 md2_cfg.int2_timestamp = val.timestamp;
3252 if ((val.sleep_status | val.sleep_change) != PROPERTY_DISABLE)
3253 {
3254 md2_cfg.int2_sleep_change = PROPERTY_ENABLE;
3255 }
3256 else
3257 {
3258 md2_cfg.int2_sleep_change = PROPERTY_DISABLE;
3259 }
3260 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3261 }
3262
3263 if (ret == 0)
3264 {
3265 ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3266 }
3267
3268 if (ret == 0)
3269 {
3270 pedo_cmd_reg.carry_count_en = val.step_count_overflow;
3271 ret = lsm6dsv16b_ln_pg_write(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3272 }
3273
3274
3275 if (ret == 0)
3276 {
3277 ret = lsm6dsv16b_pin_int1_route_get(ctx, &pin_int1_route);
3278 }
3279
3280 if (ret == 0)
3281 {
3282 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3283 }
3284 if (ret == 0)
3285 {
3286 if ((pin_int1_route.six_d
3287 | pin_int1_route.double_tap
3288 | pin_int1_route.free_fall
3289 | pin_int1_route.wake_up
3290 | pin_int1_route.single_tap
3291 | pin_int1_route.sleep_status
3292 | pin_int1_route.sleep_change
3293 | val.six_d
3294 | val.double_tap
3295 | val.free_fall
3296 | val.wake_up
3297 | val.single_tap
3298 | val.sleep_status
3299 | val.sleep_change) != PROPERTY_DISABLE)
3300 {
3301 functions_enable.interrupts_enable = PROPERTY_ENABLE;
3302 }
3303
3304 else
3305 {
3306 functions_enable.interrupts_enable = PROPERTY_DISABLE;
3307 }
3308
3309 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3310 }
3311
3312 return ret;
3313 }
3314
3315 /**
3316 * @brief It routes interrupt signals on INT 2 pin.[get]
3317 *
3318 * @param ctx read / write interface definitions
3319 * @param val It routes interrupt signals on INT 2 pin.
3320 * @retval interface status (MANDATORY: return 0 -> no Error)
3321 *
3322 */
lsm6dsv16b_pin_int2_route_get(const stmdev_ctx_t * ctx,lsm6dsv16b_pin_int_route_t * val)3323 int32_t lsm6dsv16b_pin_int2_route_get(const stmdev_ctx_t *ctx,
3324 lsm6dsv16b_pin_int_route_t *val)
3325 {
3326 lsm6dsv16b_inactivity_dur_t inactivity_dur;
3327 lsm6dsv16b_emb_func_int2_t emb_func_int2;
3328 lsm6dsv16b_pedo_cmd_reg_t pedo_cmd_reg;
3329 lsm6dsv16b_int2_ctrl_t int2_ctrl;
3330 lsm6dsv16b_fsm_int2_t fsm_int2;
3331 lsm6dsv16b_md2_cfg_t md2_cfg;
3332 lsm6dsv16b_ctrl4_t ctrl4;
3333 int32_t ret;
3334
3335
3336 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL4, (uint8_t *)&ctrl4, 1);
3337 if (ctrl4.int2_on_int1 == PROPERTY_DISABLE)
3338 {
3339 if (ret == 0)
3340 {
3341 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3342 val->emb_func_stand_by = int2_ctrl.int2_emb_func_endop;
3343 }
3344 if (ret == 0)
3345 {
3346 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3347 val->timestamp = md2_cfg.int2_timestamp;
3348 }
3349 }
3350
3351 if (ret == 0)
3352 {
3353 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3354 val->sleep_status = inactivity_dur.sleep_status_on_int;
3355 }
3356
3357
3358 if (ret == 0)
3359 {
3360 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3361 val->drdy_xl = int2_ctrl.int2_drdy_xl;
3362 val->drdy_gy = int2_ctrl.int2_drdy_g;
3363 val->fifo_th = int2_ctrl.int2_fifo_th;
3364 val->fifo_ovr = int2_ctrl.int2_fifo_ovr;
3365 val->fifo_full = int2_ctrl.int2_fifo_full;
3366 val->fifo_bdr = int2_ctrl.int2_cnt_bdr;
3367 }
3368
3369 if (ret == 0)
3370 {
3371 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3372 val->six_d = md2_cfg.int2_6d;
3373 val->double_tap = md2_cfg.int2_double_tap;
3374 val->free_fall = md2_cfg.int2_ff;
3375 val->wake_up = md2_cfg.int2_wu;
3376 val->single_tap = md2_cfg.int2_single_tap;
3377 val->sleep_change = md2_cfg.int2_sleep_change;
3378 }
3379
3380 if (ret == 0)
3381 {
3382 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
3383 }
3384 if (ret == 0)
3385 {
3386 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
3387 val->step_detector = emb_func_int2.int2_step_detector;
3388 val->tilt = emb_func_int2.int2_tilt;
3389 val->sig_mot = emb_func_int2.int2_sig_mot;
3390 val->fsm_lc = emb_func_int2.int2_fsm_lc;
3391 }
3392 if (ret == 0)
3393 {
3394 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_INT2, (uint8_t *)&fsm_int2, 1);
3395 val->fsm1 = fsm_int2.int2_fsm1;
3396 val->fsm2 = fsm_int2.int2_fsm2;
3397 val->fsm3 = fsm_int2.int2_fsm3;
3398 val->fsm4 = fsm_int2.int2_fsm4;
3399 val->fsm5 = fsm_int2.int2_fsm5;
3400 val->fsm6 = fsm_int2.int2_fsm6;
3401 val->fsm7 = fsm_int2.int2_fsm7;
3402 val->fsm8 = fsm_int2.int2_fsm8;
3403 }
3404
3405 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
3406
3407 if (ret == 0)
3408 {
3409 ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
3410 val->step_count_overflow = pedo_cmd_reg.carry_count_en;
3411 }
3412
3413 return ret;
3414 }
3415
3416 /**
3417 * @brief Enables INT pin when I3C is enabled.[set]
3418 *
3419 * @param ctx read / write interface definitions
3420 * @param val Enables INT pin when I3C is enabled.
3421 * @retval interface status (MANDATORY: return 0 -> no Error)
3422 *
3423 */
lsm6dsv16b_pin_int_en_when_i2c_set(const stmdev_ctx_t * ctx,uint8_t val)3424 int32_t lsm6dsv16b_pin_int_en_when_i2c_set(const stmdev_ctx_t *ctx, uint8_t val)
3425 {
3426 lsm6dsv16b_ctrl5_t ctrl5;
3427 int32_t ret;
3428
3429 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL5, (uint8_t *)&ctrl5, 1);
3430 if (ret == 0)
3431 {
3432 ctrl5.int_en_i3c = val;
3433 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL5, (uint8_t *)&ctrl5, 1);
3434 }
3435
3436 return ret;
3437 }
3438
3439 /**
3440 * @brief Enables INT pin when I3C is enabled.[get]
3441 *
3442 * @param ctx read / write interface definitions
3443 * @param val Enables INT pin when I3C is enabled.
3444 * @retval interface status (MANDATORY: return 0 -> no Error)
3445 *
3446 */
lsm6dsv16b_pin_int_en_when_i2c_get(const stmdev_ctx_t * ctx,uint8_t * val)3447 int32_t lsm6dsv16b_pin_int_en_when_i2c_get(const stmdev_ctx_t *ctx, uint8_t *val)
3448 {
3449 lsm6dsv16b_ctrl5_t ctrl5;
3450 int32_t ret;
3451
3452 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL5, (uint8_t *)&ctrl5, 1);
3453 *val = ctrl5.int_en_i3c;
3454
3455 return ret;
3456 }
3457
3458 /**
3459 * @brief Interrupt notification mode.[set]
3460 *
3461 * @param ctx read / write interface definitions
3462 * @param val ALL_INT_PULSED, BASE_LATCHED_EMB_PULSED, BASE_PULSED_EMB_LATCHED, ALL_INT_LATCHED,
3463 * @retval interface status (MANDATORY: return 0 -> no Error)
3464 *
3465 */
lsm6dsv16b_int_notification_set(const stmdev_ctx_t * ctx,lsm6dsv16b_int_notification_t val)3466 int32_t lsm6dsv16b_int_notification_set(const stmdev_ctx_t *ctx,
3467 lsm6dsv16b_int_notification_t val)
3468 {
3469 lsm6dsv16b_tap_cfg0_t tap_cfg0;
3470 lsm6dsv16b_page_rw_t page_rw;
3471 int32_t ret;
3472
3473 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3474 if (ret == 0)
3475 {
3476 tap_cfg0.lir = (uint8_t)val & 0x01U;
3477 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3478 }
3479
3480 if (ret == 0)
3481 {
3482 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
3483 }
3484 if (ret == 0)
3485 {
3486 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1);
3487 }
3488
3489 if (ret == 0)
3490 {
3491 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
3492 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1);
3493 }
3494
3495 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
3496
3497 return ret;
3498 }
3499
3500 /**
3501 * @brief Interrupt notification mode.[get]
3502 *
3503 * @param ctx read / write interface definitions
3504 * @param val ALL_INT_PULSED, BASE_LATCHED_EMB_PULSED, BASE_PULSED_EMB_LATCHED, ALL_INT_LATCHED,
3505 * @retval interface status (MANDATORY: return 0 -> no Error)
3506 *
3507 */
lsm6dsv16b_int_notification_get(const stmdev_ctx_t * ctx,lsm6dsv16b_int_notification_t * val)3508 int32_t lsm6dsv16b_int_notification_get(const stmdev_ctx_t *ctx,
3509 lsm6dsv16b_int_notification_t *val)
3510 {
3511 lsm6dsv16b_tap_cfg0_t tap_cfg0;
3512 lsm6dsv16b_page_rw_t page_rw;
3513 int32_t ret;
3514
3515 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3516 if (ret == 0)
3517 {
3518 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
3519 }
3520 if (ret == 0)
3521 {
3522 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PAGE_RW, (uint8_t *)&page_rw, 1);
3523 }
3524
3525 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
3526
3527 switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir)
3528 {
3529 case LSM6DSV16B_ALL_INT_PULSED:
3530 *val = LSM6DSV16B_ALL_INT_PULSED;
3531 break;
3532
3533 case LSM6DSV16B_BASE_LATCHED_EMB_PULSED:
3534 *val = LSM6DSV16B_BASE_LATCHED_EMB_PULSED;
3535 break;
3536
3537 case LSM6DSV16B_BASE_PULSED_EMB_LATCHED:
3538 *val = LSM6DSV16B_BASE_PULSED_EMB_LATCHED;
3539 break;
3540
3541 case LSM6DSV16B_ALL_INT_LATCHED:
3542 *val = LSM6DSV16B_ALL_INT_LATCHED;
3543 break;
3544
3545 default:
3546 *val = LSM6DSV16B_ALL_INT_PULSED;
3547 break;
3548 }
3549 return ret;
3550 }
3551
3552 /**
3553 * @}
3554 *
3555 */
3556
3557 /**
3558 * @defgroup Wake Up event and Activity / Inactivity detection
3559 * @brief This section groups all the functions that manage the Wake Up
3560 * event generation.
3561 * @{
3562 *
3563 */
3564
3565 /**
3566 * @brief Enable activity/inactivity (sleep) function.[set]
3567 *
3568 * @param ctx read / write interface definitions
3569 * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN,
3570 * @retval interface status (MANDATORY: return 0 -> no Error)
3571 *
3572 */
lsm6dsv16b_act_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16b_act_mode_t val)3573 int32_t lsm6dsv16b_act_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_act_mode_t val)
3574 {
3575 lsm6dsv16b_functions_enable_t functions_enable;
3576 int32_t ret;
3577
3578 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3579 if (ret == 0)
3580 {
3581 functions_enable.inact_en = (uint8_t)val & 0x03U;
3582 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3583 }
3584
3585 return ret;
3586 }
3587
3588 /**
3589 * @brief Enable activity/inactivity (sleep) function.[get]
3590 *
3591 * @param ctx read / write interface definitions
3592 * @param val XL_AND_GY_NOT_AFFECTED, XL_LOW_POWER_GY_NOT_AFFECTED, XL_LOW_POWER_GY_SLEEP, XL_LOW_POWER_GY_POWER_DOWN,
3593 * @retval interface status (MANDATORY: return 0 -> no Error)
3594 *
3595 */
lsm6dsv16b_act_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16b_act_mode_t * val)3596 int32_t lsm6dsv16b_act_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_act_mode_t *val)
3597 {
3598 lsm6dsv16b_functions_enable_t functions_enable;
3599 int32_t ret;
3600
3601 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNCTIONS_ENABLE, (uint8_t *)&functions_enable, 1);
3602 switch (functions_enable.inact_en)
3603 {
3604 case LSM6DSV16B_XL_AND_GY_NOT_AFFECTED:
3605 *val = LSM6DSV16B_XL_AND_GY_NOT_AFFECTED;
3606 break;
3607
3608 case LSM6DSV16B_XL_LOW_POWER_GY_NOT_AFFECTED:
3609 *val = LSM6DSV16B_XL_LOW_POWER_GY_NOT_AFFECTED;
3610 break;
3611
3612 case LSM6DSV16B_XL_LOW_POWER_GY_SLEEP:
3613 *val = LSM6DSV16B_XL_LOW_POWER_GY_SLEEP;
3614 break;
3615
3616 case LSM6DSV16B_XL_LOW_POWER_GY_POWER_DOWN:
3617 *val = LSM6DSV16B_XL_LOW_POWER_GY_POWER_DOWN;
3618 break;
3619
3620 default:
3621 *val = LSM6DSV16B_XL_AND_GY_NOT_AFFECTED;
3622 break;
3623 }
3624 return ret;
3625 }
3626
3627 /**
3628 * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[set]
3629 *
3630 * @param ctx read / write interface definitions
3631 * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE,
3632 * @retval interface status (MANDATORY: return 0 -> no Error)
3633 *
3634 */
lsm6dsv16b_act_from_sleep_to_act_dur_set(const stmdev_ctx_t * ctx,lsm6dsv16b_act_from_sleep_to_act_dur_t val)3635 int32_t lsm6dsv16b_act_from_sleep_to_act_dur_set(const stmdev_ctx_t *ctx,
3636 lsm6dsv16b_act_from_sleep_to_act_dur_t val)
3637 {
3638 lsm6dsv16b_inactivity_dur_t inactivity_dur;
3639 int32_t ret;
3640
3641 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3642 if (ret == 0)
3643 {
3644 inactivity_dur.inact_dur = (uint8_t)val & 0x3U;
3645 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3646 }
3647
3648 return ret;
3649 }
3650
3651 /**
3652 * @brief Duration in the transition from Stationary to Motion (from Inactivity to Activity).[get]
3653 *
3654 * @param ctx read / write interface definitions
3655 * @param val SLEEP_TO_ACT_AT_1ST_SAMPLE, SLEEP_TO_ACT_AT_2ND_SAMPLE, SLEEP_TO_ACT_AT_3RD_SAMPLE, SLEEP_TO_ACT_AT_4th_SAMPLE,
3656 * @retval interface status (MANDATORY: return 0 -> no Error)
3657 *
3658 */
lsm6dsv16b_act_from_sleep_to_act_dur_get(const stmdev_ctx_t * ctx,lsm6dsv16b_act_from_sleep_to_act_dur_t * val)3659 int32_t lsm6dsv16b_act_from_sleep_to_act_dur_get(const stmdev_ctx_t *ctx,
3660 lsm6dsv16b_act_from_sleep_to_act_dur_t *val)
3661 {
3662 lsm6dsv16b_inactivity_dur_t inactivity_dur;
3663 int32_t ret;
3664
3665 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3666 switch (inactivity_dur.inact_dur)
3667 {
3668 case LSM6DSV16B_SLEEP_TO_ACT_AT_1ST_SAMPLE:
3669 *val = LSM6DSV16B_SLEEP_TO_ACT_AT_1ST_SAMPLE;
3670 break;
3671
3672 case LSM6DSV16B_SLEEP_TO_ACT_AT_2ND_SAMPLE:
3673 *val = LSM6DSV16B_SLEEP_TO_ACT_AT_2ND_SAMPLE;
3674 break;
3675
3676 case LSM6DSV16B_SLEEP_TO_ACT_AT_3RD_SAMPLE:
3677 *val = LSM6DSV16B_SLEEP_TO_ACT_AT_3RD_SAMPLE;
3678 break;
3679
3680 case LSM6DSV16B_SLEEP_TO_ACT_AT_4th_SAMPLE:
3681 *val = LSM6DSV16B_SLEEP_TO_ACT_AT_4th_SAMPLE;
3682 break;
3683
3684 default:
3685 *val = LSM6DSV16B_SLEEP_TO_ACT_AT_1ST_SAMPLE;
3686 break;
3687 }
3688 return ret;
3689 }
3690
3691 /**
3692 * @brief Selects the accelerometer data rate during Inactivity.[set]
3693 *
3694 * @param ctx read / write interface definitions
3695 * @param val 1Hz875, 15Hz, 30Hz, 60Hz,
3696 * @retval interface status (MANDATORY: return 0 -> no Error)
3697 *
3698 */
lsm6dsv16b_act_sleep_xl_odr_set(const stmdev_ctx_t * ctx,lsm6dsv16b_act_sleep_xl_odr_t val)3699 int32_t lsm6dsv16b_act_sleep_xl_odr_set(const stmdev_ctx_t *ctx,
3700 lsm6dsv16b_act_sleep_xl_odr_t val)
3701 {
3702 lsm6dsv16b_inactivity_dur_t inactivity_dur;
3703 int32_t ret;
3704
3705 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3706 if (ret == 0)
3707 {
3708 inactivity_dur.xl_inact_odr = (uint8_t)val & 0x03U;
3709 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3710 }
3711
3712 return ret;
3713 }
3714
3715 /**
3716 * @brief Selects the accelerometer data rate during Inactivity.[get]
3717 *
3718 * @param ctx read / write interface definitions
3719 * @param val 1Hz875, 15Hz, 30Hz, 60Hz,
3720 * @retval interface status (MANDATORY: return 0 -> no Error)
3721 *
3722 */
lsm6dsv16b_act_sleep_xl_odr_get(const stmdev_ctx_t * ctx,lsm6dsv16b_act_sleep_xl_odr_t * val)3723 int32_t lsm6dsv16b_act_sleep_xl_odr_get(const stmdev_ctx_t *ctx,
3724 lsm6dsv16b_act_sleep_xl_odr_t *val)
3725 {
3726 lsm6dsv16b_inactivity_dur_t inactivity_dur;
3727 int32_t ret;
3728
3729 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3730 switch (inactivity_dur.xl_inact_odr)
3731 {
3732 case LSM6DSV16B_1Hz875:
3733 *val = LSM6DSV16B_1Hz875;
3734 break;
3735
3736 case LSM6DSV16B_15Hz:
3737 *val = LSM6DSV16B_15Hz;
3738 break;
3739
3740 case LSM6DSV16B_30Hz:
3741 *val = LSM6DSV16B_30Hz;
3742 break;
3743
3744 case LSM6DSV16B_60Hz:
3745 *val = LSM6DSV16B_60Hz;
3746 break;
3747
3748 default:
3749 *val = LSM6DSV16B_1Hz875;
3750 break;
3751 }
3752 return ret;
3753 }
3754
3755 /**
3756 * @brief Wakeup and activity/inactivity threshold.[set]
3757 *
3758 * @param ctx read / write interface definitions
3759 * @param val Wakeup and activity/inactivity threshold.
3760 * @retval interface status (MANDATORY: return 0 -> no Error)
3761 *
3762 */
lsm6dsv16b_act_thresholds_set(const stmdev_ctx_t * ctx,lsm6dsv16b_act_thresholds_t val)3763 int32_t lsm6dsv16b_act_thresholds_set(const stmdev_ctx_t *ctx,
3764 lsm6dsv16b_act_thresholds_t val)
3765 {
3766 lsm6dsv16b_inactivity_ths_t inactivity_ths;
3767 lsm6dsv16b_inactivity_dur_t inactivity_dur;
3768 lsm6dsv16b_wake_up_ths_t wake_up_ths;
3769 int32_t ret;
3770 float_t tmp;
3771
3772 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3773 if (ret == 0)
3774 {
3775 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
3776 }
3777
3778 if (ret == 0)
3779 {
3780 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
3781 }
3782
3783 if ((val.wk_ths_mg < (uint32_t)(7.8125f * 63.0f))
3784 && (val.inact_ths_mg < (uint32_t)(7.8125f * 63.0f)))
3785 {
3786 inactivity_dur.wu_inact_ths_w = 0;
3787
3788 tmp = (float_t)val.inact_ths_mg / 7.8125f;
3789 inactivity_ths.inact_ths = (uint8_t)tmp;
3790
3791 tmp = (float_t)val.wk_ths_mg / 7.8125f;
3792 wake_up_ths.wk_ths = (uint8_t)tmp;
3793 }
3794 else if ((val.wk_ths_mg < (uint32_t)(15.625f * 63.0f))
3795 && (val.inact_ths_mg < (uint32_t)(15.625f * 63.0f)))
3796 {
3797 inactivity_dur.wu_inact_ths_w = 1;
3798
3799 tmp = (float_t)val.inact_ths_mg / 15.625f;
3800 inactivity_ths.inact_ths = (uint8_t)tmp;
3801
3802 tmp = (float_t)val.wk_ths_mg / 15.625f;
3803 wake_up_ths.wk_ths = (uint8_t)tmp;
3804 }
3805 else if ((val.wk_ths_mg < (uint32_t)(31.25f * 63.0f))
3806 && (val.inact_ths_mg < (uint32_t)(31.25f * 63.0f)))
3807 {
3808 inactivity_dur.wu_inact_ths_w = 2;
3809
3810 tmp = (float_t)val.inact_ths_mg / 31.25f;
3811 inactivity_ths.inact_ths = (uint8_t)tmp;
3812
3813 tmp = (float_t)val.wk_ths_mg / 31.25f;
3814 wake_up_ths.wk_ths = (uint8_t)tmp;
3815 }
3816 else if ((val.wk_ths_mg < (uint32_t)(62.5f * 63.0f))
3817 && (val.inact_ths_mg < (uint32_t)(62.5f * 63.0f)))
3818 {
3819 inactivity_dur.wu_inact_ths_w = 3;
3820
3821 tmp = (float_t)val.inact_ths_mg / 62.5f;
3822 inactivity_ths.inact_ths = (uint8_t)tmp;
3823
3824 tmp = (float_t)val.wk_ths_mg / 62.5f;
3825 wake_up_ths.wk_ths = (uint8_t)tmp;
3826 }
3827 else if ((val.wk_ths_mg < (uint32_t)(125.0f * 63.0f))
3828 && (val.inact_ths_mg < (uint32_t)(125.0f * 63.0f)))
3829 {
3830 inactivity_dur.wu_inact_ths_w = 4;
3831
3832 tmp = (float_t)val.inact_ths_mg / 125.0f;
3833 inactivity_ths.inact_ths = (uint8_t)tmp;
3834
3835 tmp = (float_t)val.wk_ths_mg / 125.0f;
3836 wake_up_ths.wk_ths = (uint8_t)tmp;
3837 }
3838 else if ((val.wk_ths_mg < (uint32_t)(250.0f * 63.0f))
3839 && (val.inact_ths_mg < (uint32_t)(250.0f * 63.0f)))
3840 {
3841 inactivity_dur.wu_inact_ths_w = 5;
3842
3843 tmp = (float_t)val.inact_ths_mg / 250.0f;
3844 inactivity_ths.inact_ths = (uint8_t)tmp;
3845
3846 tmp = (float_t)val.wk_ths_mg / 250.0f;
3847 wake_up_ths.wk_ths = (uint8_t)tmp;
3848 }
3849 else // out of limit
3850 {
3851 inactivity_dur.wu_inact_ths_w = 5;
3852 inactivity_ths.inact_ths = 0x3FU;
3853 wake_up_ths.wk_ths = 0x3FU;
3854 }
3855
3856 if (ret == 0)
3857 {
3858 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3859 }
3860 if (ret == 0)
3861 {
3862
3863 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
3864 }
3865 if (ret == 0)
3866 {
3867
3868 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
3869 }
3870
3871 return ret;
3872 }
3873
3874 /**
3875 * @brief Wakeup and activity/inactivity threshold.[get]
3876 *
3877 * @param ctx read / write interface definitions
3878 * @param val Wakeup and activity/inactivity threshold.
3879 * @retval interface status (MANDATORY: return 0 -> no Error)
3880 *
3881 */
lsm6dsv16b_act_thresholds_get(const stmdev_ctx_t * ctx,lsm6dsv16b_act_thresholds_t * val)3882 int32_t lsm6dsv16b_act_thresholds_get(const stmdev_ctx_t *ctx,
3883 lsm6dsv16b_act_thresholds_t *val)
3884 {
3885 lsm6dsv16b_inactivity_dur_t inactivity_dur;
3886 lsm6dsv16b_inactivity_ths_t inactivity_ths;
3887 lsm6dsv16b_wake_up_ths_t wake_up_ths;
3888 int32_t ret;
3889 float_t tmp;
3890
3891 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_DUR, (uint8_t *)&inactivity_dur, 1);
3892 if (ret == 0)
3893 {
3894 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_INACTIVITY_THS, (uint8_t *)&inactivity_ths, 1);
3895 }
3896 if (ret == 0)
3897 {
3898 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
3899 }
3900
3901 switch (inactivity_dur.wu_inact_ths_w)
3902 {
3903 case 0:
3904 tmp = (float_t)wake_up_ths.wk_ths * 7.8125f;
3905 val->wk_ths_mg = (uint32_t)tmp;
3906
3907 tmp = (float_t)inactivity_ths.inact_ths * 7.8125f;
3908 val->inact_ths_mg = (uint32_t)tmp;
3909 break;
3910
3911 case 1:
3912 tmp = (float_t)wake_up_ths.wk_ths * 15.625f;
3913 val->wk_ths_mg = (uint32_t)tmp;
3914
3915 tmp = (float_t)inactivity_ths.inact_ths * 15.625f;
3916 val->inact_ths_mg = (uint32_t)tmp;
3917 break;
3918
3919 case 2:
3920 tmp = (float_t)wake_up_ths.wk_ths * 31.25f;
3921 val->wk_ths_mg = (uint32_t)tmp;
3922
3923 tmp = (float_t)inactivity_ths.inact_ths * 31.25f;
3924 val->inact_ths_mg = (uint32_t)tmp;
3925 break;
3926
3927 case 3:
3928 tmp = (float_t)wake_up_ths.wk_ths * 62.5f;
3929 val->wk_ths_mg = (uint32_t)tmp;
3930
3931 tmp = (float_t)inactivity_ths.inact_ths * 62.5f;
3932 val->inact_ths_mg = (uint32_t)tmp;
3933 break;
3934
3935 case 4:
3936 tmp = (float_t)wake_up_ths.wk_ths * 125.0f;
3937 val->wk_ths_mg = (uint32_t)tmp;
3938
3939 tmp = (float_t)inactivity_ths.inact_ths * 125.0f;
3940 val->inact_ths_mg = (uint32_t)tmp;
3941 break;
3942
3943 default:
3944 tmp = (float_t)wake_up_ths.wk_ths * 250.0f;
3945 val->wk_ths_mg = (uint32_t)tmp;
3946
3947 tmp = (float_t)inactivity_ths.inact_ths * 250.0f;
3948 val->inact_ths_mg = (uint32_t)tmp;
3949 break;
3950 }
3951
3952 return ret;
3953 }
3954
3955 /**
3956 * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [set]
3957 *
3958 * @param ctx read / write interface definitions
3959 * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time.
3960 * @retval interface status (MANDATORY: return 0 -> no Error)
3961 *
3962 */
lsm6dsv16b_act_wkup_time_windows_set(const stmdev_ctx_t * ctx,lsm6dsv16b_act_wkup_time_windows_t val)3963 int32_t lsm6dsv16b_act_wkup_time_windows_set(const stmdev_ctx_t *ctx,
3964 lsm6dsv16b_act_wkup_time_windows_t val)
3965 {
3966 lsm6dsv16b_wake_up_dur_t wake_up_dur;
3967 int32_t ret;
3968
3969 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
3970 if (ret == 0)
3971 {
3972 wake_up_dur.wake_dur = val.shock;
3973 wake_up_dur.sleep_dur = val.quiet;
3974 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
3975 }
3976
3977 return ret;
3978 }
3979
3980 /**
3981 * @brief Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time. [get]
3982 *
3983 * @param ctx read / write interface definitions
3984 * @param val Time windows configuration for Wake Up - Activity - Inactivity (SLEEP, WAKE). Duration to go in sleep mode. Default value: 0000 (this corresponds to 16 ODR) 1 LSB = 512/ODR_XL time. Wake up duration event. 1 LSB = 1/ODR_XL time.
3985 * @retval interface status (MANDATORY: return 0 -> no Error)
3986 *
3987 */
lsm6dsv16b_act_wkup_time_windows_get(const stmdev_ctx_t * ctx,lsm6dsv16b_act_wkup_time_windows_t * val)3988 int32_t lsm6dsv16b_act_wkup_time_windows_get(const stmdev_ctx_t *ctx,
3989 lsm6dsv16b_act_wkup_time_windows_t *val)
3990 {
3991 lsm6dsv16b_wake_up_dur_t wake_up_dur;
3992 int32_t ret;
3993
3994 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
3995 val->shock = wake_up_dur.wake_dur;
3996 val->quiet = wake_up_dur.sleep_dur;
3997
3998 return ret;
3999 }
4000
4001 /**
4002 * @}
4003 *
4004 */
4005
4006 /**
4007 * @defgroup Tap Generator
4008 * @brief This section groups all the functions that manage the
4009 * tap and double tap event generation.
4010 * @{
4011 *
4012 */
4013
4014 /**
4015 * @brief Enable axis for Tap - Double Tap detection.[set]
4016 *
4017 * @param ctx read / write interface definitions
4018 * @param val Enable axis for Tap - Double Tap detection.
4019 * @retval interface status (MANDATORY: return 0 -> no Error)
4020 *
4021 */
lsm6dsv16b_tap_detection_set(const stmdev_ctx_t * ctx,lsm6dsv16b_tap_detection_t val)4022 int32_t lsm6dsv16b_tap_detection_set(const stmdev_ctx_t *ctx,
4023 lsm6dsv16b_tap_detection_t val)
4024 {
4025 lsm6dsv16b_tap_cfg0_t tap_cfg0;
4026 int32_t ret;
4027
4028 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4029 if (ret == 0)
4030 {
4031 tap_cfg0.tap_x_en = val.tap_x_en;
4032 tap_cfg0.tap_y_en = val.tap_y_en;
4033 tap_cfg0.tap_z_en = val.tap_z_en;
4034 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4035 }
4036
4037 return ret;
4038 }
4039
4040 /**
4041 * @brief Enable axis for Tap - Double Tap detection.[get]
4042 *
4043 * @param ctx read / write interface definitions
4044 * @param val Enable axis for Tap - Double Tap detection.
4045 * @retval interface status (MANDATORY: return 0 -> no Error)
4046 *
4047 */
lsm6dsv16b_tap_detection_get(const stmdev_ctx_t * ctx,lsm6dsv16b_tap_detection_t * val)4048 int32_t lsm6dsv16b_tap_detection_get(const stmdev_ctx_t *ctx,
4049 lsm6dsv16b_tap_detection_t *val)
4050 {
4051 lsm6dsv16b_tap_cfg0_t tap_cfg0;
4052 int32_t ret;
4053
4054 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4055 val->tap_x_en = tap_cfg0.tap_x_en;
4056 val->tap_y_en = tap_cfg0.tap_y_en;
4057 val->tap_z_en = tap_cfg0.tap_z_en;
4058
4059 return ret;
4060 }
4061
4062 /**
4063 * @brief axis Tap - Double Tap recognition thresholds.[set]
4064 *
4065 * @param ctx read / write interface definitions
4066 * @param val axis Tap - Double Tap recognition thresholds.
4067 * @retval interface status (MANDATORY: return 0 -> no Error)
4068 *
4069 */
lsm6dsv16b_tap_thresholds_set(const stmdev_ctx_t * ctx,lsm6dsv16b_tap_thresholds_t val)4070 int32_t lsm6dsv16b_tap_thresholds_set(const stmdev_ctx_t *ctx,
4071 lsm6dsv16b_tap_thresholds_t val)
4072 {
4073 lsm6dsv16b_tap_ths_6d_t tap_ths_6d;
4074 lsm6dsv16b_tap_cfg2_t tap_cfg2;
4075 lsm6dsv16b_tap_cfg1_t tap_cfg1;
4076 int32_t ret;
4077
4078 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4079 if (ret == 0)
4080 {
4081 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
4082 }
4083 if (ret == 0)
4084 {
4085 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4086 }
4087
4088 tap_cfg1.tap_ths_z = val.z;
4089 tap_cfg2.tap_ths_y = val.y;
4090 tap_ths_6d.tap_ths_x = val.x;
4091
4092 if (ret == 0)
4093 {
4094 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4095 }
4096 if (ret == 0)
4097 {
4098 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
4099 }
4100 if (ret == 0)
4101 {
4102 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4103 }
4104
4105 return ret;
4106 }
4107
4108 /**
4109 * @brief axis Tap - Double Tap recognition thresholds.[get]
4110 *
4111 * @param ctx read / write interface definitions
4112 * @param val axis Tap - Double Tap recognition thresholds.
4113 * @retval interface status (MANDATORY: return 0 -> no Error)
4114 *
4115 */
lsm6dsv16b_tap_thresholds_get(const stmdev_ctx_t * ctx,lsm6dsv16b_tap_thresholds_t * val)4116 int32_t lsm6dsv16b_tap_thresholds_get(const stmdev_ctx_t *ctx,
4117 lsm6dsv16b_tap_thresholds_t *val)
4118 {
4119 lsm6dsv16b_tap_ths_6d_t tap_ths_6d;
4120 lsm6dsv16b_tap_cfg2_t tap_cfg2;
4121 lsm6dsv16b_tap_cfg1_t tap_cfg1;
4122 int32_t ret;
4123
4124 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4125 if (ret == 0)
4126 {
4127 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
4128 }
4129 if (ret == 0)
4130 {
4131 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4132 }
4133
4134 val->z = tap_cfg1.tap_ths_z;
4135 val->y = tap_cfg2.tap_ths_y;
4136 val->x = tap_ths_6d.tap_ths_x;
4137
4138 return ret;
4139 }
4140
4141 /**
4142 * @brief Selection of axis priority for TAP detection.[set]
4143 *
4144 * @param ctx read / write interface definitions
4145 * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY ,
4146 * @retval interface status (MANDATORY: return 0 -> no Error)
4147 *
4148 */
lsm6dsv16b_tap_axis_priority_set(const stmdev_ctx_t * ctx,lsm6dsv16b_tap_axis_priority_t val)4149 int32_t lsm6dsv16b_tap_axis_priority_set(const stmdev_ctx_t *ctx,
4150 lsm6dsv16b_tap_axis_priority_t val)
4151 {
4152 lsm6dsv16b_tap_cfg1_t tap_cfg1;
4153 int32_t ret;
4154
4155 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4156 if (ret == 0)
4157 {
4158 tap_cfg1.tap_priority = (uint8_t)val & 0x07U;
4159 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4160 }
4161
4162 return ret;
4163 }
4164
4165 /**
4166 * @brief Selection of axis priority for TAP detection.[get]
4167 *
4168 * @param ctx read / write interface definitions
4169 * @param val XYZ , YXZ , XZY, ZYX , YZX , ZXY ,
4170 * @retval interface status (MANDATORY: return 0 -> no Error)
4171 *
4172 */
lsm6dsv16b_tap_axis_priority_get(const stmdev_ctx_t * ctx,lsm6dsv16b_tap_axis_priority_t * val)4173 int32_t lsm6dsv16b_tap_axis_priority_get(const stmdev_ctx_t *ctx,
4174 lsm6dsv16b_tap_axis_priority_t *val)
4175 {
4176 lsm6dsv16b_tap_cfg1_t tap_cfg1;
4177 int32_t ret;
4178
4179 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
4180 switch (tap_cfg1.tap_priority)
4181 {
4182 case LSM6DSV16B_XYZ :
4183 *val = LSM6DSV16B_XYZ ;
4184 break;
4185
4186 case LSM6DSV16B_YXZ :
4187 *val = LSM6DSV16B_YXZ ;
4188 break;
4189
4190 case LSM6DSV16B_XZY:
4191 *val = LSM6DSV16B_XZY;
4192 break;
4193
4194 case LSM6DSV16B_ZYX :
4195 *val = LSM6DSV16B_ZYX ;
4196 break;
4197
4198 case LSM6DSV16B_YZX :
4199 *val = LSM6DSV16B_YZX ;
4200 break;
4201
4202 case LSM6DSV16B_ZXY :
4203 *val = LSM6DSV16B_ZXY ;
4204 break;
4205
4206 default:
4207 *val = LSM6DSV16B_XYZ ;
4208 break;
4209 }
4210 return ret;
4211 }
4212
4213
4214 /**
4215 * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[set]
4216 *
4217 * @param ctx read / write interface definitions
4218 * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.
4219 * @retval interface status (MANDATORY: return 0 -> no Error)
4220 *
4221 */
lsm6dsv16b_tap_time_windows_set(const stmdev_ctx_t * ctx,lsm6dsv16b_tap_time_windows_t val)4222 int32_t lsm6dsv16b_tap_time_windows_set(const stmdev_ctx_t *ctx,
4223 lsm6dsv16b_tap_time_windows_t val)
4224 {
4225 lsm6dsv16b_tap_dur_t tap_dur;
4226 int32_t ret;
4227
4228 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_DUR, (uint8_t *)&tap_dur, 1);
4229 if (ret == 0)
4230 {
4231 tap_dur.shock = val.shock;
4232 tap_dur.quiet = val.quiet;
4233 tap_dur.dur = val.tap_gap;
4234 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_DUR, (uint8_t *)&tap_dur, 1);
4235 }
4236
4237 return ret;
4238 }
4239
4240 /**
4241 * @brief Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.[get]
4242 *
4243 * @param ctx read / write interface definitions
4244 * @param val Time windows configuration for Tap - Double Tap SHOCK, QUIET, DUR : SHOCK Maximum duration is the maximum time of an overthreshold signal detection to be recognized as a tap event. The default value of these bits is 00b which corresponds to 4/ODR_XL time. If the SHOCK bits are set to a different value, 1LSB corresponds to 8/ODR_XL time. QUIET Expected quiet time after a tap detection. Quiet time is the time after the first detected tap in which there must not be any overthreshold event. The default value of these bits is 00b which corresponds to 2/ODR_XL time. If the QUIET bits are set to a different value, 1LSB corresponds to 4/ODR_XL time. DUR Duration of maximum time gap for double tap recognition. When double tap recognition is enabled, this register expresses the maximum time between two consecutive detected taps to determine a double tap event. The default value of these bits is 0000b which corresponds to 16/ODR_XL time. If the DUR_[3:0] bits are set to a different value, 1LSB corresponds to 32/ODR_XL time.
4245 * @retval interface status (MANDATORY: return 0 -> no Error)
4246 *
4247 */
lsm6dsv16b_tap_time_windows_get(const stmdev_ctx_t * ctx,lsm6dsv16b_tap_time_windows_t * val)4248 int32_t lsm6dsv16b_tap_time_windows_get(const stmdev_ctx_t *ctx,
4249 lsm6dsv16b_tap_time_windows_t *val)
4250 {
4251 lsm6dsv16b_tap_dur_t tap_dur;
4252 int32_t ret;
4253
4254 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_DUR, (uint8_t *)&tap_dur, 1);
4255 val->shock = tap_dur.shock;
4256 val->quiet = tap_dur.quiet;
4257 val->tap_gap = tap_dur.dur;
4258
4259 return ret;
4260 }
4261
4262 /**
4263 * @brief Single/double-tap event enable.[set]
4264 *
4265 * @param ctx read / write interface definitions
4266 * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE,
4267 * @retval interface status (MANDATORY: return 0 -> no Error)
4268 *
4269 */
lsm6dsv16b_tap_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16b_tap_mode_t val)4270 int32_t lsm6dsv16b_tap_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_tap_mode_t val)
4271 {
4272 lsm6dsv16b_wake_up_ths_t wake_up_ths;
4273 int32_t ret;
4274
4275 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4276 if (ret == 0)
4277 {
4278 wake_up_ths.single_double_tap = (uint8_t)val & 0x01U;
4279 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4280 }
4281
4282 return ret;
4283 }
4284
4285 /**
4286 * @brief Single/double-tap event enable.[get]
4287 *
4288 * @param ctx read / write interface definitions
4289 * @param val ONLY_SINGLE, BOTH_SINGLE_DOUBLE,
4290 * @retval interface status (MANDATORY: return 0 -> no Error)
4291 *
4292 */
lsm6dsv16b_tap_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16b_tap_mode_t * val)4293 int32_t lsm6dsv16b_tap_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_tap_mode_t *val)
4294 {
4295 lsm6dsv16b_wake_up_ths_t wake_up_ths;
4296 int32_t ret;
4297
4298 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_THS, (uint8_t *)&wake_up_ths, 1);
4299 switch (wake_up_ths.single_double_tap)
4300 {
4301 case LSM6DSV16B_ONLY_SINGLE:
4302 *val = LSM6DSV16B_ONLY_SINGLE;
4303 break;
4304
4305 case LSM6DSV16B_BOTH_SINGLE_DOUBLE:
4306 *val = LSM6DSV16B_BOTH_SINGLE_DOUBLE;
4307 break;
4308
4309 default:
4310 *val = LSM6DSV16B_ONLY_SINGLE;
4311 break;
4312 }
4313 return ret;
4314 }
4315
4316 /**
4317 * @}
4318 *
4319 */
4320
4321 /**
4322 * @defgroup Six position detection (6D)
4323 * @brief This section groups all the functions concerning six position
4324 * detection (6D).
4325 * @{
4326 *
4327 */
4328
4329 /**
4330 * @brief Threshold for 4D/6D function.[set]
4331 *
4332 * @param ctx read / write interface definitions
4333 * @param val DEG_80, DEG_70, DEG_60, DEG_50,
4334 * @retval interface status (MANDATORY: return 0 -> no Error)
4335 *
4336 */
lsm6dsv16b_6d_threshold_set(const stmdev_ctx_t * ctx,lsm6dsv16b_6d_threshold_t val)4337 int32_t lsm6dsv16b_6d_threshold_set(const stmdev_ctx_t *ctx,
4338 lsm6dsv16b_6d_threshold_t val)
4339 {
4340 lsm6dsv16b_tap_ths_6d_t tap_ths_6d;
4341 int32_t ret;
4342
4343 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4344 if (ret == 0)
4345 {
4346 tap_ths_6d.sixd_ths = (uint8_t)val & 0x03U;
4347 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4348 }
4349
4350 return ret;
4351 }
4352
4353 /**
4354 * @brief Threshold for 4D/6D function.[get]
4355 *
4356 * @param ctx read / write interface definitions
4357 * @param val DEG_80, DEG_70, DEG_60, DEG_50,
4358 * @retval interface status (MANDATORY: return 0 -> no Error)
4359 *
4360 */
lsm6dsv16b_6d_threshold_get(const stmdev_ctx_t * ctx,lsm6dsv16b_6d_threshold_t * val)4361 int32_t lsm6dsv16b_6d_threshold_get(const stmdev_ctx_t *ctx,
4362 lsm6dsv16b_6d_threshold_t *val)
4363 {
4364 lsm6dsv16b_tap_ths_6d_t tap_ths_6d;
4365 int32_t ret;
4366
4367 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TAP_THS_6D, (uint8_t *)&tap_ths_6d, 1);
4368 switch (tap_ths_6d.sixd_ths)
4369 {
4370 case LSM6DSV16B_DEG_80:
4371 *val = LSM6DSV16B_DEG_80;
4372 break;
4373
4374 case LSM6DSV16B_DEG_70:
4375 *val = LSM6DSV16B_DEG_70;
4376 break;
4377
4378 case LSM6DSV16B_DEG_60:
4379 *val = LSM6DSV16B_DEG_60;
4380 break;
4381
4382 case LSM6DSV16B_DEG_50:
4383 *val = LSM6DSV16B_DEG_50;
4384 break;
4385
4386 default:
4387 *val = LSM6DSV16B_DEG_80;
4388 break;
4389 }
4390 return ret;
4391 }
4392
4393 /**
4394 * @}
4395 *
4396 */
4397
4398 /**
4399 * @defgroup Free fall
4400 * @brief This section group all the functions concerning the free
4401 * fall detection.
4402 * @{
4403 *
4404 */
4405
4406 /**
4407 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[set]
4408 *
4409 * @param ctx read / write interface definitions
4410 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
4411 * @retval interface status (MANDATORY: return 0 -> no Error)
4412 *
4413 */
lsm6dsv16b_ff_time_windows_set(const stmdev_ctx_t * ctx,uint8_t val)4414 int32_t lsm6dsv16b_ff_time_windows_set(const stmdev_ctx_t *ctx, uint8_t val)
4415 {
4416 lsm6dsv16b_wake_up_dur_t wake_up_dur;
4417 lsm6dsv16b_free_fall_t free_fall;
4418 int32_t ret;
4419
4420 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4421 if (ret == 0)
4422 {
4423 wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
4424 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4425 }
4426 if (ret == 0)
4427 {
4428 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FREE_FALL, (uint8_t *)&free_fall, 1);
4429 }
4430
4431 if (ret == 0)
4432 {
4433 free_fall.ff_dur = (uint8_t)val & 0x1FU;
4434 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FREE_FALL, (uint8_t *)&free_fall, 1);
4435 }
4436
4437 return ret;
4438 }
4439
4440 /**
4441 * @brief Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time[get]
4442 *
4443 * @param ctx read / write interface definitions
4444 * @param val Time windows configuration for Free Fall detection 1 LSB = 1/ODR_XL time
4445 * @retval interface status (MANDATORY: return 0 -> no Error)
4446 *
4447 */
lsm6dsv16b_ff_time_windows_get(const stmdev_ctx_t * ctx,uint8_t * val)4448 int32_t lsm6dsv16b_ff_time_windows_get(const stmdev_ctx_t *ctx, uint8_t *val)
4449 {
4450 lsm6dsv16b_wake_up_dur_t wake_up_dur;
4451 lsm6dsv16b_free_fall_t free_fall;
4452 int32_t ret;
4453
4454 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
4455 if (ret == 0)
4456 {
4457 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FREE_FALL, (uint8_t *)&free_fall, 1);
4458 }
4459
4460 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
4461
4462 return ret;
4463 }
4464
4465 /**
4466 * @brief Free fall threshold setting.[set]
4467 *
4468 * @param ctx read / write interface definitions
4469 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
4470 * @retval interface status (MANDATORY: return 0 -> no Error)
4471 *
4472 */
lsm6dsv16b_ff_thresholds_set(const stmdev_ctx_t * ctx,lsm6dsv16b_ff_thresholds_t val)4473 int32_t lsm6dsv16b_ff_thresholds_set(const stmdev_ctx_t *ctx,
4474 lsm6dsv16b_ff_thresholds_t val)
4475 {
4476 lsm6dsv16b_free_fall_t free_fall;
4477 int32_t ret;
4478
4479 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FREE_FALL, (uint8_t *)&free_fall, 1);
4480 if (ret == 0)
4481 {
4482 free_fall.ff_ths = (uint8_t)val & 0x7U;
4483 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FREE_FALL, (uint8_t *)&free_fall, 1);
4484 }
4485
4486 return ret;
4487 }
4488
4489 /**
4490 * @brief Free fall threshold setting.[get]
4491 *
4492 * @param ctx read / write interface definitions
4493 * @param val 156_mg, 219_mg, 250_mg, 312_mg, 344_mg, 406_mg, 469_mg, 500_mg,
4494 * @retval interface status (MANDATORY: return 0 -> no Error)
4495 *
4496 */
lsm6dsv16b_ff_thresholds_get(const stmdev_ctx_t * ctx,lsm6dsv16b_ff_thresholds_t * val)4497 int32_t lsm6dsv16b_ff_thresholds_get(const stmdev_ctx_t *ctx,
4498 lsm6dsv16b_ff_thresholds_t *val)
4499 {
4500 lsm6dsv16b_free_fall_t free_fall;
4501 int32_t ret;
4502
4503 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FREE_FALL, (uint8_t *)&free_fall, 1);
4504
4505 switch (free_fall.ff_ths)
4506 {
4507 case LSM6DSV16B_156_mg:
4508 *val = LSM6DSV16B_156_mg;
4509 break;
4510
4511 case LSM6DSV16B_219_mg:
4512 *val = LSM6DSV16B_219_mg;
4513 break;
4514
4515 case LSM6DSV16B_250_mg:
4516 *val = LSM6DSV16B_250_mg;
4517 break;
4518
4519 case LSM6DSV16B_312_mg:
4520 *val = LSM6DSV16B_312_mg;
4521 break;
4522
4523 case LSM6DSV16B_344_mg:
4524 *val = LSM6DSV16B_344_mg;
4525 break;
4526
4527 case LSM6DSV16B_406_mg:
4528 *val = LSM6DSV16B_406_mg;
4529 break;
4530
4531 case LSM6DSV16B_469_mg:
4532 *val = LSM6DSV16B_469_mg;
4533 break;
4534
4535 case LSM6DSV16B_500_mg:
4536 *val = LSM6DSV16B_500_mg;
4537 break;
4538
4539 default:
4540 *val = LSM6DSV16B_156_mg;
4541 break;
4542 }
4543 return ret;
4544 }
4545
4546 /**
4547 * @}
4548 *
4549 */
4550
4551 /**
4552 * @defgroup FIFO
4553 * @brief This section group all the functions concerning the fifo usage
4554 * @{
4555 *
4556 */
4557
4558 /**
4559 * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[set]
4560 *
4561 * @param ctx read / write interface definitions
4562 * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).
4563 * @retval interface status (MANDATORY: return 0 -> no Error)
4564 *
4565 */
lsm6dsv16b_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)4566 int32_t lsm6dsv16b_fifo_watermark_set(const stmdev_ctx_t *ctx, uint8_t val)
4567 {
4568 lsm6dsv16b_fifo_ctrl1_t fifo_ctrl1;
4569 int32_t ret;
4570
4571 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
4572
4573 if (ret == 0)
4574 {
4575 fifo_ctrl1.wtm = val;
4576 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
4577 }
4578
4579 return ret;
4580 }
4581
4582 /**
4583 * @brief FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).[get]
4584 *
4585 * @param ctx read / write interface definitions
4586 * @param val FIFO watermark threshold (1 LSb = TAG (1 Byte) + 1 sensor (6 Bytes) written in FIFO).
4587 * @retval interface status (MANDATORY: return 0 -> no Error)
4588 *
4589 */
lsm6dsv16b_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)4590 int32_t lsm6dsv16b_fifo_watermark_get(const stmdev_ctx_t *ctx, uint8_t *val)
4591 {
4592 lsm6dsv16b_fifo_ctrl1_t fifo_ctrl1;
4593 int32_t ret;
4594
4595 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
4596 *val = fifo_ctrl1.wtm;
4597
4598 return ret;
4599 }
4600
4601 /**
4602 * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[set]
4603 *
4604 * @param ctx read / write interface definitions
4605 * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.
4606 * @retval interface status (MANDATORY: return 0 -> no Error)
4607 *
4608 */
lsm6dsv16b_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t * ctx,uint8_t val)4609 int32_t lsm6dsv16b_fifo_xl_dual_fsm_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
4610 {
4611 lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2;
4612 int32_t ret;
4613
4614 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4615 if (ret == 0)
4616 {
4617 fifo_ctrl2.xl_dualc_batch_from_fsm = val;
4618 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4619 }
4620
4621 return ret;
4622 }
4623
4624 /**
4625 * @brief When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.[get]
4626 *
4627 * @param ctx read / write interface definitions
4628 * @param val When dual channel mode is enabled, this function enables FSM-triggered batching in FIFO of accelerometer channel 2.
4629 * @retval interface status (MANDATORY: return 0 -> no Error)
4630 *
4631 */
lsm6dsv16b_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)4632 int32_t lsm6dsv16b_fifo_xl_dual_fsm_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
4633 {
4634 lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2;
4635 int32_t ret;
4636
4637 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4638 *val = fifo_ctrl2.xl_dualc_batch_from_fsm;
4639
4640 return ret;
4641 }
4642
4643 /**
4644 * @brief It configures the compression algorithm to write non-compressed data at each rate.[set]
4645 *
4646 * @param ctx read / write interface definitions
4647 * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1,
4648 * @retval interface status (MANDATORY: return 0 -> no Error)
4649 *
4650 */
lsm6dsv16b_fifo_compress_algo_set(const stmdev_ctx_t * ctx,lsm6dsv16b_fifo_compress_algo_t val)4651 int32_t lsm6dsv16b_fifo_compress_algo_set(const stmdev_ctx_t *ctx,
4652 lsm6dsv16b_fifo_compress_algo_t val)
4653 {
4654 lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2;
4655 int32_t ret;
4656
4657 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4658 if (ret == 0)
4659 {
4660 fifo_ctrl2.uncompr_rate = (uint8_t)val & 0x03U;
4661 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4662 }
4663
4664 return ret;
4665 }
4666
4667 /**
4668 * @brief It configures the compression algorithm to write non-compressed data at each rate.[get]
4669 *
4670 * @param ctx read / write interface definitions
4671 * @param val CMP_DISABLE, CMP_ALWAYS, CMP_8_TO_1, CMP_16_TO_1, CMP_32_TO_1,
4672 * @retval interface status (MANDATORY: return 0 -> no Error)
4673 *
4674 */
lsm6dsv16b_fifo_compress_algo_get(const stmdev_ctx_t * ctx,lsm6dsv16b_fifo_compress_algo_t * val)4675 int32_t lsm6dsv16b_fifo_compress_algo_get(const stmdev_ctx_t *ctx,
4676 lsm6dsv16b_fifo_compress_algo_t *val)
4677 {
4678 lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2;
4679 int32_t ret;
4680
4681 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4682
4683 switch (fifo_ctrl2.uncompr_rate)
4684 {
4685 case LSM6DSV16B_CMP_DISABLE:
4686 *val = LSM6DSV16B_CMP_DISABLE;
4687 break;
4688
4689 case LSM6DSV16B_CMP_8_TO_1:
4690 *val = LSM6DSV16B_CMP_8_TO_1;
4691 break;
4692
4693 case LSM6DSV16B_CMP_16_TO_1:
4694 *val = LSM6DSV16B_CMP_16_TO_1;
4695 break;
4696
4697 case LSM6DSV16B_CMP_32_TO_1:
4698 *val = LSM6DSV16B_CMP_32_TO_1;
4699 break;
4700
4701 default:
4702 *val = LSM6DSV16B_CMP_DISABLE;
4703 break;
4704 }
4705 return ret;
4706 }
4707
4708 /**
4709 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
4710 *
4711 * @param ctx read / write interface definitions
4712 * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO.
4713 * @retval interface status (MANDATORY: return 0 -> no Error)
4714 *
4715 */
lsm6dsv16b_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t * ctx,uint8_t val)4716 int32_t lsm6dsv16b_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx,
4717 uint8_t val)
4718 {
4719 lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2;
4720 int32_t ret;
4721
4722 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4723 if (ret == 0)
4724 {
4725 fifo_ctrl2.odr_chg_en = val;
4726 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4727 }
4728
4729 return ret;
4730 }
4731
4732 /**
4733 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
4734 *
4735 * @param ctx read / write interface definitions
4736 * @param val Enables ODR CHANGE virtual sensor to be batched in FIFO.
4737 * @retval interface status (MANDATORY: return 0 -> no Error)
4738 *
4739 */
lsm6dsv16b_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t * ctx,uint8_t * val)4740 int32_t lsm6dsv16b_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx,
4741 uint8_t *val)
4742 {
4743 lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2;
4744 int32_t ret;
4745
4746 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4747 *val = fifo_ctrl2.odr_chg_en;
4748
4749 return ret;
4750 }
4751
4752 /**
4753 * @brief Enables/Disables compression algorithm runtime.[set]
4754 *
4755 * @param ctx read / write interface definitions
4756 * @param val Enables/Disables compression algorithm runtime.
4757 * @retval interface status (MANDATORY: return 0 -> no Error)
4758 *
4759 */
lsm6dsv16b_fifo_compress_algo_real_time_set(const stmdev_ctx_t * ctx,uint8_t val)4760 int32_t lsm6dsv16b_fifo_compress_algo_real_time_set(const stmdev_ctx_t *ctx,
4761 uint8_t val)
4762 {
4763 lsm6dsv16b_emb_func_en_b_t emb_func_en_b;
4764 lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2;
4765
4766 int32_t ret;
4767
4768 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4769 if (ret == 0)
4770 {
4771 fifo_ctrl2.fifo_compr_rt_en = val;
4772 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4773 }
4774
4775 if (ret == 0)
4776 {
4777 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
4778 }
4779 if (ret == 0)
4780 {
4781 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
4782 }
4783 if (ret == 0)
4784 {
4785 emb_func_en_b.fifo_compr_en = val;
4786 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
4787 }
4788
4789 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
4790
4791 return ret;
4792 }
4793
4794 /**
4795 * @brief Enables/Disables compression algorithm runtime.[get]
4796 *
4797 * @param ctx read / write interface definitions
4798 * @param val Enables/Disables compression algorithm runtime.
4799 * @retval interface status (MANDATORY: return 0 -> no Error)
4800 *
4801 */
lsm6dsv16b_fifo_compress_algo_real_time_get(const stmdev_ctx_t * ctx,uint8_t * val)4802 int32_t lsm6dsv16b_fifo_compress_algo_real_time_get(const stmdev_ctx_t *ctx,
4803 uint8_t *val)
4804 {
4805 lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2;
4806 int32_t ret;
4807
4808 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4809
4810 *val = fifo_ctrl2.fifo_compr_rt_en;
4811
4812 return ret;
4813 }
4814
4815 /**
4816 * @brief Sensing chain FIFO stop values memorization at threshold level.[set]
4817 *
4818 * @param ctx read / write interface definitions
4819 * @param val Sensing chain FIFO stop values memorization at threshold level.
4820 * @retval interface status (MANDATORY: return 0 -> no Error)
4821 *
4822 */
lsm6dsv16b_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)4823 int32_t lsm6dsv16b_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
4824 {
4825 lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2;
4826 int32_t ret;
4827
4828 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4829 if (ret == 0)
4830 {
4831 fifo_ctrl2.stop_on_wtm = val;
4832 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4833 }
4834
4835 return ret;
4836 }
4837
4838 /**
4839 * @brief Sensing chain FIFO stop values memorization at threshold level.[get]
4840 *
4841 * @param ctx read / write interface definitions
4842 * @param val Sensing chain FIFO stop values memorization at threshold level.
4843 * @retval interface status (MANDATORY: return 0 -> no Error)
4844 *
4845 */
lsm6dsv16b_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)4846 int32_t lsm6dsv16b_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val)
4847 {
4848 lsm6dsv16b_fifo_ctrl2_t fifo_ctrl2;
4849 int32_t ret;
4850
4851 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
4852 *val = fifo_ctrl2.stop_on_wtm;
4853
4854 return ret;
4855 }
4856
4857 /**
4858 * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[set]
4859 *
4860 * @param ctx read / write interface definitions
4861 * @param val lsm6dsv16b_fifo_xl_batch_t enum
4862 * @retval interface status (MANDATORY: return 0 -> no Error)
4863 *
4864 */
lsm6dsv16b_fifo_xl_batch_set(const stmdev_ctx_t * ctx,lsm6dsv16b_fifo_xl_batch_t val)4865 int32_t lsm6dsv16b_fifo_xl_batch_set(const stmdev_ctx_t *ctx,
4866 lsm6dsv16b_fifo_xl_batch_t val)
4867 {
4868 lsm6dsv16b_fifo_ctrl3_t fifo_ctrl3;
4869 int32_t ret;
4870
4871 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
4872 if (ret == 0)
4873 {
4874 fifo_ctrl3.bdr_xl = (uint8_t)val & 0xFU;
4875 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
4876 }
4877
4878 return ret;
4879 }
4880
4881 /**
4882 * @brief Selects Batch Data Rate (write frequency in FIFO) for accelerometer data.[get]
4883 *
4884 * @param ctx read / write interface definitions
4885 * @param val lsm6dsv16b_fifo_xl_batch_t enum
4886 * @retval interface status (MANDATORY: return 0 -> no Error)
4887 *
4888 */
lsm6dsv16b_fifo_xl_batch_get(const stmdev_ctx_t * ctx,lsm6dsv16b_fifo_xl_batch_t * val)4889 int32_t lsm6dsv16b_fifo_xl_batch_get(const stmdev_ctx_t *ctx,
4890 lsm6dsv16b_fifo_xl_batch_t *val)
4891 {
4892 lsm6dsv16b_fifo_ctrl3_t fifo_ctrl3;
4893 int32_t ret;
4894
4895 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
4896 switch (fifo_ctrl3.bdr_xl)
4897 {
4898 case LSM6DSV16B_XL_NOT_BATCHED:
4899 *val = LSM6DSV16B_XL_NOT_BATCHED;
4900 break;
4901
4902 case LSM6DSV16B_XL_BATCHED_AT_1Hz875:
4903 *val = LSM6DSV16B_XL_BATCHED_AT_1Hz875;
4904 break;
4905
4906 case LSM6DSV16B_XL_BATCHED_AT_7Hz5:
4907 *val = LSM6DSV16B_XL_BATCHED_AT_7Hz5;
4908 break;
4909
4910 case LSM6DSV16B_XL_BATCHED_AT_15Hz:
4911 *val = LSM6DSV16B_XL_BATCHED_AT_15Hz;
4912 break;
4913
4914 case LSM6DSV16B_XL_BATCHED_AT_30Hz:
4915 *val = LSM6DSV16B_XL_BATCHED_AT_30Hz;
4916 break;
4917
4918 case LSM6DSV16B_XL_BATCHED_AT_60Hz:
4919 *val = LSM6DSV16B_XL_BATCHED_AT_60Hz;
4920 break;
4921
4922 case LSM6DSV16B_XL_BATCHED_AT_120Hz:
4923 *val = LSM6DSV16B_XL_BATCHED_AT_120Hz;
4924 break;
4925
4926 case LSM6DSV16B_XL_BATCHED_AT_240Hz:
4927 *val = LSM6DSV16B_XL_BATCHED_AT_240Hz;
4928 break;
4929
4930 case LSM6DSV16B_XL_BATCHED_AT_480Hz:
4931 *val = LSM6DSV16B_XL_BATCHED_AT_480Hz;
4932 break;
4933
4934 case LSM6DSV16B_XL_BATCHED_AT_960Hz:
4935 *val = LSM6DSV16B_XL_BATCHED_AT_960Hz;
4936 break;
4937
4938 case LSM6DSV16B_XL_BATCHED_AT_1920Hz:
4939 *val = LSM6DSV16B_XL_BATCHED_AT_1920Hz;
4940 break;
4941
4942 case LSM6DSV16B_XL_BATCHED_AT_3840Hz:
4943 *val = LSM6DSV16B_XL_BATCHED_AT_3840Hz;
4944 break;
4945
4946 case LSM6DSV16B_XL_BATCHED_AT_7680Hz:
4947 *val = LSM6DSV16B_XL_BATCHED_AT_7680Hz;
4948 break;
4949
4950 default:
4951 *val = LSM6DSV16B_XL_NOT_BATCHED;
4952 break;
4953 }
4954 return ret;
4955 }
4956
4957 /**
4958 * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[set]
4959 *
4960 * @param ctx read / write interface definitions
4961 * @param val lsm6dsv16b_fifo_gy_batch_t enum
4962 * @retval interface status (MANDATORY: return 0 -> no Error)
4963 *
4964 */
lsm6dsv16b_fifo_gy_batch_set(const stmdev_ctx_t * ctx,lsm6dsv16b_fifo_gy_batch_t val)4965 int32_t lsm6dsv16b_fifo_gy_batch_set(const stmdev_ctx_t *ctx,
4966 lsm6dsv16b_fifo_gy_batch_t val)
4967 {
4968 lsm6dsv16b_fifo_ctrl3_t fifo_ctrl3;
4969 int32_t ret;
4970
4971 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
4972 if (ret == 0)
4973 {
4974 fifo_ctrl3.bdr_gy = (uint8_t)val & 0xFU;
4975 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
4976 }
4977
4978 return ret;
4979 }
4980
4981 /**
4982 * @brief Selects Batch Data Rate (write frequency in FIFO) for gyroscope data.[get]
4983 *
4984 * @param ctx read / write interface definitions
4985 * @param val lsm6dsv16b_fifo_gy_batch_t enum
4986 * @retval interface status (MANDATORY: return 0 -> no Error)
4987 *
4988 */
lsm6dsv16b_fifo_gy_batch_get(const stmdev_ctx_t * ctx,lsm6dsv16b_fifo_gy_batch_t * val)4989 int32_t lsm6dsv16b_fifo_gy_batch_get(const stmdev_ctx_t *ctx,
4990 lsm6dsv16b_fifo_gy_batch_t *val)
4991 {
4992 lsm6dsv16b_fifo_ctrl3_t fifo_ctrl3;
4993 int32_t ret;
4994
4995 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL3, (uint8_t *)&fifo_ctrl3, 1);
4996 switch (fifo_ctrl3.bdr_gy)
4997 {
4998 case LSM6DSV16B_GY_NOT_BATCHED:
4999 *val = LSM6DSV16B_GY_NOT_BATCHED;
5000 break;
5001
5002 case LSM6DSV16B_GY_BATCHED_AT_1Hz875:
5003 *val = LSM6DSV16B_GY_BATCHED_AT_1Hz875;
5004 break;
5005
5006 case LSM6DSV16B_GY_BATCHED_AT_7Hz5:
5007 *val = LSM6DSV16B_GY_BATCHED_AT_7Hz5;
5008 break;
5009
5010 case LSM6DSV16B_GY_BATCHED_AT_15Hz:
5011 *val = LSM6DSV16B_GY_BATCHED_AT_15Hz;
5012 break;
5013
5014 case LSM6DSV16B_GY_BATCHED_AT_30Hz:
5015 *val = LSM6DSV16B_GY_BATCHED_AT_30Hz;
5016 break;
5017
5018 case LSM6DSV16B_GY_BATCHED_AT_60Hz:
5019 *val = LSM6DSV16B_GY_BATCHED_AT_60Hz;
5020 break;
5021
5022 case LSM6DSV16B_GY_BATCHED_AT_120Hz:
5023 *val = LSM6DSV16B_GY_BATCHED_AT_120Hz;
5024 break;
5025
5026 case LSM6DSV16B_GY_BATCHED_AT_240Hz:
5027 *val = LSM6DSV16B_GY_BATCHED_AT_240Hz;
5028 break;
5029
5030 case LSM6DSV16B_GY_BATCHED_AT_480Hz:
5031 *val = LSM6DSV16B_GY_BATCHED_AT_480Hz;
5032 break;
5033
5034 case LSM6DSV16B_GY_BATCHED_AT_960Hz:
5035 *val = LSM6DSV16B_GY_BATCHED_AT_960Hz;
5036 break;
5037
5038 case LSM6DSV16B_GY_BATCHED_AT_1920Hz:
5039 *val = LSM6DSV16B_GY_BATCHED_AT_1920Hz;
5040 break;
5041
5042 case LSM6DSV16B_GY_BATCHED_AT_3840Hz:
5043 *val = LSM6DSV16B_GY_BATCHED_AT_3840Hz;
5044 break;
5045
5046 case LSM6DSV16B_GY_BATCHED_AT_7680Hz:
5047 *val = LSM6DSV16B_GY_BATCHED_AT_7680Hz;
5048 break;
5049
5050 default:
5051 *val = LSM6DSV16B_GY_NOT_BATCHED;
5052 break;
5053 }
5054 return ret;
5055 }
5056
5057 /**
5058 * @brief FIFO mode selection.[set]
5059 *
5060 * @param ctx read / write interface definitions
5061 * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
5062 * @retval interface status (MANDATORY: return 0 -> no Error)
5063 *
5064 */
lsm6dsv16b_fifo_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16b_fifo_mode_t val)5065 int32_t lsm6dsv16b_fifo_mode_set(const stmdev_ctx_t *ctx,
5066 lsm6dsv16b_fifo_mode_t val)
5067 {
5068 lsm6dsv16b_fifo_ctrl4_t fifo_ctrl4;
5069 int32_t ret;
5070
5071 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5072 if (ret == 0)
5073 {
5074 fifo_ctrl4.fifo_mode = (uint8_t)val & 0x07U;
5075 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5076 }
5077
5078 return ret;
5079 }
5080
5081 /**
5082 * @brief FIFO mode selection.[get]
5083 *
5084 * @param ctx read / write interface definitions
5085 * @param val BYPASS_MODE, FIFO_MODE, STREAM_WTM_TO_FULL_MODE, STREAM_TO_FIFO_MODE, BYPASS_TO_STREAM_MODE, STREAM_MODE, BYPASS_TO_FIFO_MODE,
5086 * @retval interface status (MANDATORY: return 0 -> no Error)
5087 *
5088 */
lsm6dsv16b_fifo_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16b_fifo_mode_t * val)5089 int32_t lsm6dsv16b_fifo_mode_get(const stmdev_ctx_t *ctx,
5090 lsm6dsv16b_fifo_mode_t *val)
5091 {
5092 lsm6dsv16b_fifo_ctrl4_t fifo_ctrl4;
5093 int32_t ret;
5094
5095 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5096 switch (fifo_ctrl4.fifo_mode)
5097 {
5098 case LSM6DSV16B_BYPASS_MODE:
5099 *val = LSM6DSV16B_BYPASS_MODE;
5100 break;
5101
5102 case LSM6DSV16B_FIFO_MODE:
5103 *val = LSM6DSV16B_FIFO_MODE;
5104 break;
5105
5106 case LSM6DSV16B_STREAM_WTM_TO_FULL_MODE:
5107 *val = LSM6DSV16B_STREAM_WTM_TO_FULL_MODE;
5108 break;
5109
5110 case LSM6DSV16B_STREAM_TO_FIFO_MODE:
5111 *val = LSM6DSV16B_STREAM_TO_FIFO_MODE;
5112 break;
5113
5114 case LSM6DSV16B_BYPASS_TO_STREAM_MODE:
5115 *val = LSM6DSV16B_BYPASS_TO_STREAM_MODE;
5116 break;
5117
5118 case LSM6DSV16B_STREAM_MODE:
5119 *val = LSM6DSV16B_STREAM_MODE;
5120 break;
5121
5122 case LSM6DSV16B_BYPASS_TO_FIFO_MODE:
5123 *val = LSM6DSV16B_BYPASS_TO_FIFO_MODE;
5124 break;
5125
5126 default:
5127 *val = LSM6DSV16B_BYPASS_MODE;
5128 break;
5129 }
5130 return ret;
5131 }
5132
5133 /**
5134 * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[set]
5135 *
5136 * @param ctx read / write interface definitions
5137 * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz,
5138 * @retval interface status (MANDATORY: return 0 -> no Error)
5139 *
5140 */
lsm6dsv16b_fifo_temp_batch_set(const stmdev_ctx_t * ctx,lsm6dsv16b_fifo_temp_batch_t val)5141 int32_t lsm6dsv16b_fifo_temp_batch_set(const stmdev_ctx_t *ctx,
5142 lsm6dsv16b_fifo_temp_batch_t val)
5143 {
5144 lsm6dsv16b_fifo_ctrl4_t fifo_ctrl4;
5145 int32_t ret;
5146
5147 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5148 if (ret == 0)
5149 {
5150 fifo_ctrl4.odr_t_batch = (uint8_t)val & 0x03U;
5151 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5152 }
5153
5154 return ret;
5155 }
5156
5157 /**
5158 * @brief Selects batch data rate (write frequency in FIFO) for temperature data.[get]
5159 *
5160 * @param ctx read / write interface definitions
5161 * @param val TEMP_NOT_BATCHED, TEMP_BATCHED_AT_1Hz875, TEMP_BATCHED_AT_15Hz, TEMP_BATCHED_AT_60Hz,
5162 * @retval interface status (MANDATORY: return 0 -> no Error)
5163 *
5164 */
lsm6dsv16b_fifo_temp_batch_get(const stmdev_ctx_t * ctx,lsm6dsv16b_fifo_temp_batch_t * val)5165 int32_t lsm6dsv16b_fifo_temp_batch_get(const stmdev_ctx_t *ctx,
5166 lsm6dsv16b_fifo_temp_batch_t *val)
5167 {
5168 lsm6dsv16b_fifo_ctrl4_t fifo_ctrl4;
5169 int32_t ret;
5170
5171 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5172 switch (fifo_ctrl4.odr_t_batch)
5173 {
5174 case LSM6DSV16B_TEMP_NOT_BATCHED:
5175 *val = LSM6DSV16B_TEMP_NOT_BATCHED;
5176 break;
5177
5178 case LSM6DSV16B_TEMP_BATCHED_AT_1Hz875:
5179 *val = LSM6DSV16B_TEMP_BATCHED_AT_1Hz875;
5180 break;
5181
5182 case LSM6DSV16B_TEMP_BATCHED_AT_15Hz:
5183 *val = LSM6DSV16B_TEMP_BATCHED_AT_15Hz;
5184 break;
5185
5186 case LSM6DSV16B_TEMP_BATCHED_AT_60Hz:
5187 *val = LSM6DSV16B_TEMP_BATCHED_AT_60Hz;
5188 break;
5189
5190 default:
5191 *val = LSM6DSV16B_TEMP_NOT_BATCHED;
5192 break;
5193 }
5194 return ret;
5195 }
5196
5197 /**
5198 * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[set]
5199 *
5200 * @param ctx read / write interface definitions
5201 * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32,
5202 * @retval interface status (MANDATORY: return 0 -> no Error)
5203 *
5204 */
lsm6dsv16b_fifo_timestamp_batch_set(const stmdev_ctx_t * ctx,lsm6dsv16b_fifo_timestamp_batch_t val)5205 int32_t lsm6dsv16b_fifo_timestamp_batch_set(const stmdev_ctx_t *ctx,
5206 lsm6dsv16b_fifo_timestamp_batch_t val)
5207 {
5208 lsm6dsv16b_fifo_ctrl4_t fifo_ctrl4;
5209 int32_t ret;
5210
5211 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5212 if (ret == 0)
5213 {
5214 fifo_ctrl4.dec_ts_batch = (uint8_t)val & 0x3U;
5215 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5216 }
5217
5218 return ret;
5219 }
5220
5221 /**
5222 * @brief Selects decimation for timestamp batching in FIFO. Write rate will be the maximum rate between XL and GYRO BDR divided by decimation decoder.[get]
5223 *
5224 * @param ctx read / write interface definitions
5225 * @param val TMSTMP_NOT_BATCHED, TMSTMP_DEC_1, TMSTMP_DEC_8, TMSTMP_DEC_32,
5226 * @retval interface status (MANDATORY: return 0 -> no Error)
5227 *
5228 */
lsm6dsv16b_fifo_timestamp_batch_get(const stmdev_ctx_t * ctx,lsm6dsv16b_fifo_timestamp_batch_t * val)5229 int32_t lsm6dsv16b_fifo_timestamp_batch_get(const stmdev_ctx_t *ctx,
5230 lsm6dsv16b_fifo_timestamp_batch_t *val)
5231 {
5232 lsm6dsv16b_fifo_ctrl4_t fifo_ctrl4;
5233 int32_t ret;
5234
5235 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_CTRL4, (uint8_t *)&fifo_ctrl4, 1);
5236 switch (fifo_ctrl4.dec_ts_batch)
5237 {
5238 case LSM6DSV16B_TMSTMP_NOT_BATCHED:
5239 *val = LSM6DSV16B_TMSTMP_NOT_BATCHED;
5240 break;
5241
5242 case LSM6DSV16B_TMSTMP_DEC_1:
5243 *val = LSM6DSV16B_TMSTMP_DEC_1;
5244 break;
5245
5246 case LSM6DSV16B_TMSTMP_DEC_8:
5247 *val = LSM6DSV16B_TMSTMP_DEC_8;
5248 break;
5249
5250 case LSM6DSV16B_TMSTMP_DEC_32:
5251 *val = LSM6DSV16B_TMSTMP_DEC_32;
5252 break;
5253
5254 default:
5255 *val = LSM6DSV16B_TMSTMP_NOT_BATCHED;
5256 break;
5257 }
5258 return ret;
5259 }
5260
5261 /**
5262 * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[set]
5263 *
5264 * @param ctx read / write interface definitions
5265 * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.
5266 * @retval interface status (MANDATORY: return 0 -> no Error)
5267 *
5268 */
lsm6dsv16b_fifo_batch_counter_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)5269 int32_t lsm6dsv16b_fifo_batch_counter_threshold_set(const stmdev_ctx_t *ctx,
5270 uint16_t val)
5271 {
5272 lsm6dsv16b_counter_bdr_reg1_t counter_bdr_reg1;
5273 lsm6dsv16b_counter_bdr_reg2_t counter_bdr_reg2;
5274 int32_t ret;
5275
5276 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5277
5278 if (ret == 0)
5279 {
5280 counter_bdr_reg2.cnt_bdr_th = (uint8_t)val & 0xFFU;
5281 counter_bdr_reg1.cnt_bdr_th = (uint8_t)(val >> 8) & 0x3U;
5282 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5283 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1);
5284 }
5285
5286 return ret;
5287 }
5288
5289 /**
5290 * @brief The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.[get]
5291 *
5292 * @param ctx read / write interface definitions
5293 * @param val The threshold for the internal counter of batch events. When this counter reaches the threshold, the counter is reset and the interrupt flag is set to 1.
5294 * @retval interface status (MANDATORY: return 0 -> no Error)
5295 *
5296 */
lsm6dsv16b_fifo_batch_counter_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)5297 int32_t lsm6dsv16b_fifo_batch_counter_threshold_get(const stmdev_ctx_t *ctx,
5298 uint16_t *val)
5299 {
5300 uint8_t buff[2];
5301 int32_t ret;
5302
5303 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_COUNTER_BDR_REG1, &buff[0], 2);
5304 *val = (uint16_t)buff[0] & 0x3U;
5305 *val = (*val * 256U) + (uint16_t)buff[1];
5306
5307 return ret;
5308 }
5309
5310 /**
5311 * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope.[set]
5312 *
5313 * @param ctx read / write interface definitions
5314 * @param val XL_BATCH_EVENT, GY_BATCH_EVENT
5315 * @retval interface status (MANDATORY: return 0 -> no Error)
5316 *
5317 */
lsm6dsv16b_fifo_batch_cnt_event_set(const stmdev_ctx_t * ctx,lsm6dsv16b_fifo_batch_cnt_event_t val)5318 int32_t lsm6dsv16b_fifo_batch_cnt_event_set(const stmdev_ctx_t *ctx,
5319 lsm6dsv16b_fifo_batch_cnt_event_t val)
5320 {
5321 lsm6dsv16b_counter_bdr_reg1_t counter_bdr_reg1;
5322 int32_t ret;
5323
5324 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5325
5326 if (ret == 0)
5327 {
5328 counter_bdr_reg1.trig_counter_bdr = (uint8_t)val & 0x03U;
5329 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5330 }
5331
5332 return ret;
5333 }
5334
5335 /**
5336 * @brief Selects the trigger for the internal counter of batch events between the accelerometer, gyroscope.[get]
5337 *
5338 * @param ctx read / write interface definitions
5339 * @param val XL_BATCH_EVENT, GY_BATCH_EVENT
5340 * @retval interface status (MANDATORY: return 0 -> no Error)
5341 *
5342 */
lsm6dsv16b_fifo_batch_cnt_event_get(const stmdev_ctx_t * ctx,lsm6dsv16b_fifo_batch_cnt_event_t * val)5343 int32_t lsm6dsv16b_fifo_batch_cnt_event_get(const stmdev_ctx_t *ctx,
5344 lsm6dsv16b_fifo_batch_cnt_event_t *val)
5345 {
5346 lsm6dsv16b_counter_bdr_reg1_t counter_bdr_reg1;
5347 int32_t ret;
5348
5349 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
5350 switch (counter_bdr_reg1.trig_counter_bdr)
5351 {
5352 case LSM6DSV16B_XL_BATCH_EVENT:
5353 *val = LSM6DSV16B_XL_BATCH_EVENT;
5354 break;
5355
5356 case LSM6DSV16B_GY_BATCH_EVENT:
5357 *val = LSM6DSV16B_GY_BATCH_EVENT;
5358 break;
5359
5360 default:
5361 *val = LSM6DSV16B_XL_BATCH_EVENT;
5362 break;
5363 }
5364 return ret;
5365 }
5366
5367 /**
5368 * @brief Batching in FIFO buffer of SFLP.[set]
5369 *
5370 * @param ctx read / write interface definitions
5371 * @param val Batching in FIFO buffer of SFLP values.
5372 * @retval interface status (MANDATORY: return 0 -> no Error)
5373 *
5374 */
lsm6dsv16b_fifo_sflp_batch_set(const stmdev_ctx_t * ctx,lsm6dsv16b_fifo_sflp_raw_t val)5375 int32_t lsm6dsv16b_fifo_sflp_batch_set(const stmdev_ctx_t *ctx,
5376 lsm6dsv16b_fifo_sflp_raw_t val)
5377 {
5378 lsm6dsv16b_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5379 int32_t ret;
5380
5381 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
5382 if (ret == 0)
5383 {
5384 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5385 emb_func_fifo_en_a.sflp_game_fifo_en = val.game_rotation;
5386 emb_func_fifo_en_a.sflp_gravity_fifo_en = val.gravity;
5387 emb_func_fifo_en_a.sflp_gbias_fifo_en = val.gbias;
5388 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_FIFO_EN_A,
5389 (uint8_t *)&emb_func_fifo_en_a, 1);
5390 }
5391
5392 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
5393
5394 return ret;
5395 }
5396
5397 /**
5398 * @brief Batching in FIFO buffer of SFLP.[get]
5399 *
5400 * @param ctx read / write interface definitions
5401 * @param val Batching in FIFO buffer of SFLP values.
5402 * @retval interface status (MANDATORY: return 0 -> no Error)
5403 *
5404 */
lsm6dsv16b_fifo_sflp_batch_get(const stmdev_ctx_t * ctx,lsm6dsv16b_fifo_sflp_raw_t * val)5405 int32_t lsm6dsv16b_fifo_sflp_batch_get(const stmdev_ctx_t *ctx,
5406 lsm6dsv16b_fifo_sflp_raw_t *val)
5407 {
5408 lsm6dsv16b_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5409 int32_t ret;
5410
5411 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
5412 if (ret == 0)
5413 {
5414 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5415
5416 val->game_rotation = emb_func_fifo_en_a.sflp_game_fifo_en;
5417 val->gravity = emb_func_fifo_en_a.sflp_gravity_fifo_en;
5418 val->gbias = emb_func_fifo_en_a.sflp_gbias_fifo_en;
5419 }
5420
5421 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
5422
5423 return ret;
5424 }
5425
5426 /**
5427 * @brief Status of FIFO.[get]
5428 *
5429 * @param ctx read / write interface definitions
5430 * @param val Status of FIFO (level and flags).
5431 * @retval interface status (MANDATORY: return 0 -> no Error)
5432 *
5433 */
lsm6dsv16b_fifo_status_get(const stmdev_ctx_t * ctx,lsm6dsv16b_fifo_status_t * val)5434 int32_t lsm6dsv16b_fifo_status_get(const stmdev_ctx_t *ctx,
5435 lsm6dsv16b_fifo_status_t *val)
5436 {
5437 uint8_t buff[2];
5438 lsm6dsv16b_fifo_status2_t status;
5439 int32_t ret;
5440
5441 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_STATUS1, (uint8_t *)&buff[0], 2);
5442 bytecpy((uint8_t *)&status, &buff[1]);
5443
5444 val->fifo_bdr = status.counter_bdr_ia;
5445 val->fifo_ovr = status.fifo_ovr_ia;
5446 val->fifo_full = status.fifo_full_ia;
5447 val->fifo_th = status.fifo_wtm_ia;
5448
5449 val->fifo_level = (uint16_t)buff[1] & 0x01U;
5450 val->fifo_level = (val->fifo_level * 256U) + buff[0];
5451
5452 return ret;
5453 }
5454
5455 /**
5456 * @brief FIFO data output[get]
5457 *
5458 * @param ctx read / write interface definitions
5459 * @param val lsm6dsv16b_fifo_out_raw_t enum
5460 * @retval interface status (MANDATORY: return 0 -> no Error)
5461 *
5462 */
lsm6dsv16b_fifo_out_raw_get(const stmdev_ctx_t * ctx,lsm6dsv16b_fifo_out_raw_t * val)5463 int32_t lsm6dsv16b_fifo_out_raw_get(const stmdev_ctx_t *ctx,
5464 lsm6dsv16b_fifo_out_raw_t *val)
5465 {
5466 lsm6dsv16b_fifo_data_out_tag_t fifo_data_out_tag;
5467 uint8_t buff[7];
5468 int32_t ret;
5469
5470 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FIFO_DATA_OUT_TAG, buff, 7);
5471 bytecpy((uint8_t *)&fifo_data_out_tag, &buff[0]);
5472
5473 switch (fifo_data_out_tag.tag_sensor)
5474 {
5475 case LSM6DSV16B_FIFO_EMPTY:
5476 val->tag = LSM6DSV16B_FIFO_EMPTY;
5477 break;
5478
5479 case LSM6DSV16B_GY_NC_TAG:
5480 val->tag = LSM6DSV16B_GY_NC_TAG;
5481 break;
5482
5483 case LSM6DSV16B_XL_NC_TAG:
5484 val->tag = LSM6DSV16B_XL_NC_TAG;
5485 break;
5486
5487 case LSM6DSV16B_TIMESTAMP_TAG:
5488 val->tag = LSM6DSV16B_TIMESTAMP_TAG;
5489 break;
5490
5491 case LSM6DSV16B_TEMPERATURE_TAG:
5492 val->tag = LSM6DSV16B_TEMPERATURE_TAG;
5493 break;
5494
5495 case LSM6DSV16B_CFG_CHANGE_TAG:
5496 val->tag = LSM6DSV16B_CFG_CHANGE_TAG;
5497 break;
5498
5499 case LSM6DSV16B_XL_NC_T_2_TAG:
5500 val->tag = LSM6DSV16B_XL_NC_T_2_TAG;
5501 break;
5502
5503 case LSM6DSV16B_XL_NC_T_1_TAG:
5504 val->tag = LSM6DSV16B_XL_NC_T_1_TAG;
5505 break;
5506
5507 case LSM6DSV16B_XL_2XC_TAG:
5508 val->tag = LSM6DSV16B_XL_2XC_TAG;
5509 break;
5510
5511 case LSM6DSV16B_XL_3XC_TAG:
5512 val->tag = LSM6DSV16B_XL_3XC_TAG;
5513 break;
5514
5515 case LSM6DSV16B_GY_NC_T_2_TAG:
5516 val->tag = LSM6DSV16B_GY_NC_T_2_TAG;
5517 break;
5518
5519 case LSM6DSV16B_GY_NC_T_1_TAG:
5520 val->tag = LSM6DSV16B_GY_NC_T_1_TAG;
5521 break;
5522
5523 case LSM6DSV16B_GY_2XC_TAG:
5524 val->tag = LSM6DSV16B_GY_2XC_TAG;
5525 break;
5526
5527 case LSM6DSV16B_GY_3XC_TAG:
5528 val->tag = LSM6DSV16B_GY_3XC_TAG;
5529 break;
5530
5531 case LSM6DSV16B_STEP_COUNTER_TAG:
5532 val->tag = LSM6DSV16B_STEP_COUNTER_TAG;
5533 break;
5534
5535 case LSM6DSV16B_SFLP_GAME_ROTATION_VECTOR_TAG:
5536 val->tag = LSM6DSV16B_SFLP_GAME_ROTATION_VECTOR_TAG;
5537 break;
5538
5539 case LSM6DSV16B_SFLP_GYROSCOPE_BIAS_TAG:
5540 val->tag = LSM6DSV16B_SFLP_GYROSCOPE_BIAS_TAG;
5541 break;
5542
5543 case LSM6DSV16B_SFLP_GRAVITY_VECTOR_TAG:
5544 val->tag = LSM6DSV16B_SFLP_GRAVITY_VECTOR_TAG;
5545 break;
5546
5547 case LSM6DSV16B_XL_DUAL_CORE:
5548 val->tag = LSM6DSV16B_XL_DUAL_CORE;
5549 break;
5550
5551 default:
5552 val->tag = LSM6DSV16B_FIFO_EMPTY;
5553 break;
5554 }
5555
5556 val->cnt = fifo_data_out_tag.tag_cnt;
5557
5558 val->data[0] = buff[1];
5559 val->data[1] = buff[2];
5560 val->data[2] = buff[3];
5561 val->data[3] = buff[4];
5562 val->data[4] = buff[5];
5563 val->data[5] = buff[6];
5564
5565 return ret;
5566 }
5567
5568 /**
5569 * @brief Batching in FIFO buffer of step counter value.[set]
5570 *
5571 * @param ctx read / write interface definitions
5572 * @param val Batching in FIFO buffer of step counter value.
5573 * @retval interface status (MANDATORY: return 0 -> no Error)
5574 *
5575 */
lsm6dsv16b_fifo_stpcnt_batch_set(const stmdev_ctx_t * ctx,uint8_t val)5576 int32_t lsm6dsv16b_fifo_stpcnt_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
5577 {
5578 lsm6dsv16b_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5579 int32_t ret;
5580
5581 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
5582 if (ret == 0)
5583 {
5584 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5585 }
5586
5587 if (ret == 0)
5588 {
5589 emb_func_fifo_en_a.step_counter_fifo_en = val;
5590 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5591 }
5592
5593 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
5594
5595 return ret;
5596 }
5597
5598 /**
5599 * @brief Batching in FIFO buffer of step counter value.[get]
5600 *
5601 * @param ctx read / write interface definitions
5602 * @param val Batching in FIFO buffer of step counter value.
5603 * @retval interface status (MANDATORY: return 0 -> no Error)
5604 *
5605 */
lsm6dsv16b_fifo_stpcnt_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)5606 int32_t lsm6dsv16b_fifo_stpcnt_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
5607 {
5608 lsm6dsv16b_emb_func_fifo_en_a_t emb_func_fifo_en_a;
5609 int32_t ret;
5610
5611 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
5612 if (ret == 0)
5613 {
5614 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_FIFO_EN_A, (uint8_t *)&emb_func_fifo_en_a, 1);
5615 }
5616
5617 *val = emb_func_fifo_en_a.step_counter_fifo_en;
5618
5619 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
5620
5621
5622 return ret;
5623 }
5624
5625 /**
5626 * @}
5627 *
5628 */
5629
5630 /**
5631 * @defgroup Step Counter
5632 * @brief This section groups all the functions that manage pedometer.
5633 * @{
5634 *
5635 */
5636
5637 /**
5638 * @brief Step counter mode[set]
5639 *
5640 * @param ctx read / write interface definitions
5641 * @param val false_step_rej, step_counter, step_detector,
5642 * @retval interface status (MANDATORY: return 0 -> no Error)
5643 *
5644 */
lsm6dsv16b_stpcnt_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16b_stpcnt_mode_t val)5645 int32_t lsm6dsv16b_stpcnt_mode_set(const stmdev_ctx_t *ctx,
5646 lsm6dsv16b_stpcnt_mode_t val)
5647 {
5648 lsm6dsv16b_emb_func_en_a_t emb_func_en_a;
5649 lsm6dsv16b_emb_func_en_b_t emb_func_en_b;
5650 lsm6dsv16b_pedo_cmd_reg_t pedo_cmd_reg;
5651 int32_t ret;
5652
5653 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
5654 if (ret == 0)
5655 {
5656 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
5657 }
5658 if (ret == 0)
5659 {
5660 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
5661 }
5662 if (ret == 0)
5663 {
5664 emb_func_en_a.pedo_en = val.step_counter_enable;
5665 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
5666 }
5667
5668 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
5669
5670 if (ret == 0)
5671 {
5672 ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
5673 }
5674 if (ret == 0)
5675 {
5676 pedo_cmd_reg.fp_rejection_en = val.false_step_rej;
5677 ret = lsm6dsv16b_ln_pg_write(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
5678 }
5679
5680 return ret;
5681 }
5682
5683 /**
5684 * @brief Step counter mode[get]
5685 *
5686 * @param ctx read / write interface definitions
5687 * @param val false_step_rej, step_counter, step_detector,
5688 * @retval interface status (MANDATORY: return 0 -> no Error)
5689 *
5690 */
lsm6dsv16b_stpcnt_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16b_stpcnt_mode_t * val)5691 int32_t lsm6dsv16b_stpcnt_mode_get(const stmdev_ctx_t *ctx,
5692 lsm6dsv16b_stpcnt_mode_t *val)
5693 {
5694 lsm6dsv16b_emb_func_en_a_t emb_func_en_a;
5695 lsm6dsv16b_pedo_cmd_reg_t pedo_cmd_reg;
5696 int32_t ret;
5697
5698 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
5699 if (ret == 0)
5700 {
5701 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
5702 }
5703
5704 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
5705
5706 if (ret == 0)
5707 {
5708 ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_CMD_REG, (uint8_t *)&pedo_cmd_reg, 1);
5709 }
5710 val->false_step_rej = pedo_cmd_reg.fp_rejection_en;
5711 val->step_counter_enable = emb_func_en_a.pedo_en;
5712
5713 return ret;
5714 }
5715
5716 /**
5717 * @brief Step counter output, number of detected steps.[get]
5718 *
5719 * @param ctx read / write interface definitions
5720 * @param val Step counter output, number of detected steps.
5721 * @retval interface status (MANDATORY: return 0 -> no Error)
5722 *
5723 */
lsm6dsv16b_stpcnt_steps_get(const stmdev_ctx_t * ctx,uint16_t * val)5724 int32_t lsm6dsv16b_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val)
5725 {
5726 uint8_t buff[2];
5727 int32_t ret;
5728
5729 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
5730 if (ret == 0)
5731 {
5732 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_STEP_COUNTER_L, &buff[0], 2);
5733 }
5734
5735 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
5736
5737 *val = buff[1];
5738 *val = (*val * 256U) + buff[0];
5739
5740 return ret;
5741 }
5742
5743 /**
5744 * @brief Reset step counter.[set]
5745 *
5746 * @param ctx read / write interface definitions
5747 * @param val Reset step counter.
5748 * @retval interface status (MANDATORY: return 0 -> no Error)
5749 *
5750 */
lsm6dsv16b_stpcnt_rst_step_set(const stmdev_ctx_t * ctx,uint8_t val)5751 int32_t lsm6dsv16b_stpcnt_rst_step_set(const stmdev_ctx_t *ctx, uint8_t val)
5752 {
5753 lsm6dsv16b_emb_func_src_t emb_func_src;
5754 int32_t ret;
5755
5756 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
5757 if (ret == 0)
5758 {
5759 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
5760 }
5761
5762 if (ret == 0)
5763 {
5764 emb_func_src.pedo_rst_step = val;
5765 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
5766 }
5767
5768 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
5769
5770 return ret;
5771 }
5772
5773 /**
5774 * @brief Reset step counter.[get]
5775 *
5776 * @param ctx read / write interface definitions
5777 * @param val Reset step counter.
5778 * @retval interface status (MANDATORY: return 0 -> no Error)
5779 *
5780 */
lsm6dsv16b_stpcnt_rst_step_get(const stmdev_ctx_t * ctx,uint8_t * val)5781 int32_t lsm6dsv16b_stpcnt_rst_step_get(const stmdev_ctx_t *ctx, uint8_t *val)
5782 {
5783 lsm6dsv16b_emb_func_src_t emb_func_src;
5784 int32_t ret;
5785
5786 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
5787 if (ret == 0)
5788 {
5789 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_SRC, (uint8_t *)&emb_func_src, 1);
5790 }
5791
5792 *val = emb_func_src.pedo_rst_step;
5793
5794 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
5795
5796 return ret;
5797 }
5798
5799 /**
5800 * @brief Pedometer debounce configuration.[set]
5801 *
5802 * @param ctx read / write interface definitions
5803 * @param val Pedometer debounce configuration.
5804 * @retval interface status (MANDATORY: return 0 -> no Error)
5805 *
5806 */
lsm6dsv16b_stpcnt_debounce_set(const stmdev_ctx_t * ctx,uint8_t val)5807 int32_t lsm6dsv16b_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val)
5808 {
5809 lsm6dsv16b_pedo_deb_steps_conf_t pedo_deb_steps_conf;
5810 int32_t ret;
5811
5812 ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf,
5813 1);
5814 if (ret == 0)
5815 {
5816 pedo_deb_steps_conf.deb_step = val;
5817 ret = lsm6dsv16b_ln_pg_write(ctx, LSM6DSV16B_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf,
5818 1);
5819 }
5820
5821 return ret;
5822 }
5823
5824 /**
5825 * @brief Pedometer debounce configuration.[get]
5826 *
5827 * @param ctx read / write interface definitions
5828 * @param val Pedometer debounce configuration.
5829 * @retval interface status (MANDATORY: return 0 -> no Error)
5830 *
5831 */
lsm6dsv16b_stpcnt_debounce_get(const stmdev_ctx_t * ctx,uint8_t * val)5832 int32_t lsm6dsv16b_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val)
5833 {
5834 lsm6dsv16b_pedo_deb_steps_conf_t pedo_deb_steps_conf;
5835 int32_t ret;
5836
5837 ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_DEB_STEPS_CONF, (uint8_t *)&pedo_deb_steps_conf,
5838 1);
5839 *val = pedo_deb_steps_conf.deb_step;
5840
5841 return ret;
5842 }
5843
5844 /**
5845 * @brief Time period register for step detection on delta time.[set]
5846 *
5847 * @param ctx read / write interface definitions
5848 * @param val Time period register for step detection on delta time.
5849 * @retval interface status (MANDATORY: return 0 -> no Error)
5850 *
5851 */
lsm6dsv16b_stpcnt_period_set(const stmdev_ctx_t * ctx,uint16_t val)5852 int32_t lsm6dsv16b_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val)
5853 {
5854 uint8_t buff[2];
5855 int32_t ret;
5856
5857 buff[1] = (uint8_t)(val / 256U);
5858 buff[0] = (uint8_t)(val - (buff[1] * 256U));
5859
5860 ret = lsm6dsv16b_ln_pg_write(ctx, LSM6DSV16B_PEDO_SC_DELTAT_L, (uint8_t *)&buff[0], 2);
5861
5862 return ret;
5863 }
5864
5865 /**
5866 * @brief Time period register for step detection on delta time.[get]
5867 *
5868 * @param ctx read / write interface definitions
5869 * @param val Time period register for step detection on delta time.
5870 * @retval interface status (MANDATORY: return 0 -> no Error)
5871 *
5872 */
lsm6dsv16b_stpcnt_period_get(const stmdev_ctx_t * ctx,uint16_t * val)5873 int32_t lsm6dsv16b_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val)
5874 {
5875 uint8_t buff[2];
5876 int32_t ret;
5877
5878 ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_PEDO_SC_DELTAT_L, &buff[0], 2);
5879 *val = buff[1];
5880 *val = (*val * 256U) + buff[0];
5881
5882 return ret;
5883 }
5884
5885 /**
5886 * @}
5887 *
5888 */
5889
5890 /**
5891 * @defgroup Significant motion
5892 * @brief This section groups all the functions that manage the
5893 * significant motion detection.
5894 * @{
5895 *
5896 */
5897
5898 /**
5899 * @brief Enables significant motion detection function.[set]
5900 *
5901 * @param ctx read / write interface definitions
5902 * @param val Enables significant motion detection function.
5903 * @retval interface status (MANDATORY: return 0 -> no Error)
5904 *
5905 */
lsm6dsv16b_sigmot_mode_set(const stmdev_ctx_t * ctx,uint8_t val)5906 int32_t lsm6dsv16b_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
5907 {
5908 lsm6dsv16b_emb_func_en_a_t emb_func_en_a;
5909 int32_t ret;
5910
5911 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
5912 if (ret == 0)
5913 {
5914 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
5915 }
5916 if (ret == 0)
5917 {
5918 emb_func_en_a.sign_motion_en = val;
5919 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
5920 }
5921
5922 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
5923
5924
5925 return ret;
5926 }
5927
5928 /**
5929 * @brief Enables significant motion detection function.[get]
5930 *
5931 * @param ctx read / write interface definitions
5932 * @param val Enables significant motion detection function.
5933 * @retval interface status (MANDATORY: return 0 -> no Error)
5934 *
5935 */
lsm6dsv16b_sigmot_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)5936 int32_t lsm6dsv16b_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
5937 {
5938 lsm6dsv16b_emb_func_en_a_t emb_func_en_a;
5939 int32_t ret;
5940
5941 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
5942 if (ret == 0)
5943 {
5944 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
5945 }
5946 *val = emb_func_en_a.sign_motion_en;
5947
5948 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
5949
5950
5951 return ret;
5952 }
5953
5954 /**
5955 * @}
5956 *
5957 */
5958
5959 /**
5960 * @defgroup Tilt detection
5961 * @brief This section groups all the functions that manage the tilt
5962 * event detection.
5963 * @{
5964 *
5965 */
5966
5967 /**
5968 * @brief Tilt calculation.[set]
5969 *
5970 * @param ctx read / write interface definitions
5971 * @param val Tilt calculation.
5972 * @retval interface status (MANDATORY: return 0 -> no Error)
5973 *
5974 */
lsm6dsv16b_tilt_mode_set(const stmdev_ctx_t * ctx,uint8_t val)5975 int32_t lsm6dsv16b_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
5976 {
5977 lsm6dsv16b_emb_func_en_a_t emb_func_en_a;
5978 int32_t ret;
5979
5980 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
5981 if (ret == 0)
5982 {
5983 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
5984 }
5985 if (ret == 0)
5986 {
5987 emb_func_en_a.tilt_en = val;
5988 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
5989 }
5990
5991 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
5992
5993 return ret;
5994 }
5995
5996 /**
5997 * @brief Tilt calculation.[get]
5998 *
5999 * @param ctx read / write interface definitions
6000 * @param val Tilt calculation.
6001 * @retval interface status (MANDATORY: return 0 -> no Error)
6002 *
6003 */
lsm6dsv16b_tilt_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)6004 int32_t lsm6dsv16b_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
6005 {
6006 lsm6dsv16b_emb_func_en_a_t emb_func_en_a;
6007 int32_t ret;
6008
6009 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
6010 if (ret == 0)
6011 {
6012 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6013 }
6014 *val = emb_func_en_a.tilt_en;
6015
6016 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
6017
6018 return ret;
6019 }
6020
6021 /**
6022 * @}
6023 *
6024 */
6025
6026 /**
6027 * @defgroup Sensor Fusion Low Power (SFLP)
6028 * @brief This section groups all the functions that manage pedometer.
6029 * @{
6030 *
6031 */
6032
6033 /**
6034 * @brief Enable SFLP Game Rotation Vector (6x).[set]
6035 *
6036 * @param ctx read / write interface definitions
6037 * @param val Enable/Disable game rotation value (0/1).
6038 * @retval interface status (MANDATORY: return 0 -> no Error)
6039 *
6040 */
lsm6dsv16b_sflp_game_rotation_set(const stmdev_ctx_t * ctx,uint16_t val)6041 int32_t lsm6dsv16b_sflp_game_rotation_set(const stmdev_ctx_t *ctx, uint16_t val)
6042 {
6043 lsm6dsv16b_emb_func_en_a_t emb_func_en_a;
6044 int32_t ret;
6045
6046 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
6047 if (ret == 0)
6048 {
6049 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6050 emb_func_en_a.sflp_game_en = val;
6051 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A,
6052 (uint8_t *)&emb_func_en_a, 1);
6053 }
6054
6055 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
6056
6057 return ret;
6058 }
6059
6060 /**
6061 * @brief Enable SFLP Game Rotation Vector (6x).[get]
6062 *
6063 * @param ctx read / write interface definitions
6064 * @param val Enable/Disable game rotation value (0/1).
6065 * @retval interface status (MANDATORY: return 0 -> no Error)
6066 *
6067 */
lsm6dsv16b_sflp_game_rotation_get(const stmdev_ctx_t * ctx,uint16_t * val)6068 int32_t lsm6dsv16b_sflp_game_rotation_get(const stmdev_ctx_t *ctx, uint16_t *val)
6069 {
6070 lsm6dsv16b_emb_func_en_a_t emb_func_en_a;
6071 int32_t ret;
6072
6073 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
6074 if (ret == 0)
6075 {
6076 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
6077 *val = emb_func_en_a.sflp_game_en;
6078 }
6079
6080 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
6081
6082 return ret;
6083 }
6084
6085 /**
6086 * @brief SFLP Data Rate (ODR) configuration.[set]
6087 *
6088 * @param ctx read / write interface definitions
6089 * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz
6090 * @retval interface status (MANDATORY: return 0 -> no Error)
6091 *
6092 */
lsm6dsv16b_sflp_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv16b_sflp_data_rate_t val)6093 int32_t lsm6dsv16b_sflp_data_rate_set(const stmdev_ctx_t *ctx,
6094 lsm6dsv16b_sflp_data_rate_t val)
6095 {
6096 lsm6dsv16b_sflp_odr_t sflp_odr;
6097 int32_t ret;
6098
6099 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
6100 if (ret == 0)
6101 {
6102 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
6103 sflp_odr.sflp_game_odr = (uint8_t)val & 0x07U;
6104 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_SFLP_ODR, (uint8_t *)&sflp_odr,
6105 1);
6106 }
6107
6108 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
6109
6110 return ret;
6111 }
6112
6113 /**
6114 * @brief SFLP Data Rate (ODR) configuration.[get]
6115 *
6116 * @param ctx read / write interface definitions
6117 * @param val SFLP_15Hz, SFLP_30Hz, SFLP_60Hz, SFLP_120Hz, SFLP_240Hz, SFLP_480Hz
6118 * @retval interface status (MANDATORY: return 0 -> no Error)
6119 *
6120 */
lsm6dsv16b_sflp_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv16b_sflp_data_rate_t * val)6121 int32_t lsm6dsv16b_sflp_data_rate_get(const stmdev_ctx_t *ctx,
6122 lsm6dsv16b_sflp_data_rate_t *val)
6123 {
6124 lsm6dsv16b_sflp_odr_t sflp_odr;
6125 int32_t ret;
6126
6127 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
6128 ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_SFLP_ODR, (uint8_t *)&sflp_odr, 1);
6129 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
6130
6131 switch (sflp_odr.sflp_game_odr)
6132 {
6133 case LSM6DSV16B_SFLP_15Hz:
6134 *val = LSM6DSV16B_SFLP_15Hz;
6135 break;
6136
6137 case LSM6DSV16B_SFLP_30Hz:
6138 *val = LSM6DSV16B_SFLP_30Hz;
6139 break;
6140
6141 case LSM6DSV16B_SFLP_60Hz:
6142 *val = LSM6DSV16B_SFLP_60Hz;
6143 break;
6144
6145 case LSM6DSV16B_SFLP_120Hz:
6146 *val = LSM6DSV16B_SFLP_120Hz;
6147 break;
6148
6149 case LSM6DSV16B_SFLP_240Hz:
6150 *val = LSM6DSV16B_SFLP_240Hz;
6151 break;
6152
6153 case LSM6DSV16B_SFLP_480Hz:
6154 *val = LSM6DSV16B_SFLP_480Hz;
6155 break;
6156
6157 default:
6158 *val = LSM6DSV16B_SFLP_15Hz;
6159 break;
6160 }
6161 return ret;
6162 }
6163
6164 /*
6165 * Original conversion routines taken from: https://github.com/numpy/numpy
6166 *
6167 * uint16_t npy_floatbits_to_halfbits(uint32_t f);
6168 * uint16_t npy_float_to_half(float_t f);
6169 *
6170 * Released under BSD-3-Clause License
6171 */
6172
6173 #define NPY_HALF_GENERATE_OVERFLOW 0 /* do not trigger FP overflow */
6174 #define NPY_HALF_GENERATE_UNDERFLOW 0 /* do not trigger FP underflow */
6175 #ifndef NPY_HALF_ROUND_TIES_TO_EVEN
6176 #define NPY_HALF_ROUND_TIES_TO_EVEN 1
6177 #endif
6178
npy_floatbits_to_halfbits(uint32_t f)6179 static uint16_t npy_floatbits_to_halfbits(uint32_t f)
6180 {
6181 uint32_t f_exp, f_sig;
6182 uint16_t h_sgn, h_exp, h_sig;
6183
6184 h_sgn = (uint16_t)((f & 0x80000000u) >> 16);
6185 f_exp = (f & 0x7f800000u);
6186
6187 /* Exponent overflow/NaN converts to signed inf/NaN */
6188 if (f_exp >= 0x47800000u)
6189 {
6190 if (f_exp == 0x7f800000u)
6191 {
6192 /* Inf or NaN */
6193 f_sig = (f & 0x007fffffu);
6194 if (f_sig != 0)
6195 {
6196 /* NaN - propagate the flag in the significand... */
6197 uint16_t ret = (uint16_t)(0x7c00u + (f_sig >> 13));
6198 /* ...but make sure it stays a NaN */
6199 if (ret == 0x7c00u)
6200 {
6201 ret++;
6202 }
6203 return h_sgn + ret;
6204 }
6205 else
6206 {
6207 /* signed inf */
6208 return (uint16_t)(h_sgn + 0x7c00u);
6209 }
6210 }
6211 else
6212 {
6213 /* overflow to signed inf */
6214 #if NPY_HALF_GENERATE_OVERFLOW
6215 npy_set_floatstatus_overflow();
6216 #endif
6217 return (uint16_t)(h_sgn + 0x7c00u);
6218 }
6219 }
6220
6221 /* Exponent underflow converts to a subnormal half or signed zero */
6222 if (f_exp <= 0x38000000u)
6223 {
6224 /*
6225 * Signed zeros, subnormal floats, and floats with small
6226 * exponents all convert to signed zero half-floats.
6227 */
6228 if (f_exp < 0x33000000u)
6229 {
6230 #if NPY_HALF_GENERATE_UNDERFLOW
6231 /* If f != 0, it underflowed to 0 */
6232 if ((f & 0x7fffffff) != 0)
6233 {
6234 npy_set_floatstatus_underflow();
6235 }
6236 #endif
6237 return h_sgn;
6238 }
6239 /* Make the subnormal significand */
6240 f_exp >>= 23;
6241 f_sig = (0x00800000u + (f & 0x007fffffu));
6242 #if NPY_HALF_GENERATE_UNDERFLOW
6243 /* If it's not exactly represented, it underflowed */
6244 if ((f_sig & (((uint32_t)1 << (126 - f_exp)) - 1)) != 0)
6245 {
6246 npy_set_floatstatus_underflow();
6247 }
6248 #endif
6249 /*
6250 * Usually the significand is shifted by 13. For subnormals an
6251 * additional shift needs to occur. This shift is one for the largest
6252 * exponent giving a subnormal `f_exp = 0x38000000 >> 23 = 112`, which
6253 * offsets the new first bit. At most the shift can be 1+10 bits.
6254 */
6255 f_sig >>= (113 - f_exp);
6256 /* Handle rounding by adding 1 to the bit beyond half precision */
6257 #if NPY_HALF_ROUND_TIES_TO_EVEN
6258 /*
6259 * If the last bit in the half significand is 0 (already even), and
6260 * the remaining bit pattern is 1000...0, then we do not add one
6261 * to the bit after the half significand. However, the (113 - f_exp)
6262 * shift can lose up to 11 bits, so the || checks them in the original.
6263 * In all other cases, we can just add one.
6264 */
6265 if (((f_sig & 0x00003fffu) != 0x00001000u) || (f & 0x000007ffu))
6266 {
6267 f_sig += 0x00001000u;
6268 }
6269 #else
6270 f_sig += 0x00001000u;
6271 #endif
6272 h_sig = (uint16_t)(f_sig >> 13);
6273 /*
6274 * If the rounding causes a bit to spill into h_exp, it will
6275 * increment h_exp from zero to one and h_sig will be zero.
6276 * This is the correct result.
6277 */
6278 return (uint16_t)(h_sgn + h_sig);
6279 }
6280
6281 /* Regular case with no overflow or underflow */
6282 h_exp = (uint16_t)((f_exp - 0x38000000u) >> 13);
6283 /* Handle rounding by adding 1 to the bit beyond half precision */
6284 f_sig = (f & 0x007fffffu);
6285 #if NPY_HALF_ROUND_TIES_TO_EVEN
6286 /*
6287 * If the last bit in the half significand is 0 (already even), and
6288 * the remaining bit pattern is 1000...0, then we do not add one
6289 * to the bit after the half significand. In all other cases, we do.
6290 */
6291 if ((f_sig & 0x00003fffu) != 0x00001000u)
6292 {
6293 f_sig += 0x00001000u;
6294 }
6295 #else
6296 f_sig += 0x00001000u;
6297 #endif
6298 h_sig = (uint16_t)(f_sig >> 13);
6299 /*
6300 * If the rounding causes a bit to spill into h_exp, it will
6301 * increment h_exp by one and h_sig will be zero. This is the
6302 * correct result. h_exp may increment to 15, at greatest, in
6303 * which case the result overflows to a signed inf.
6304 */
6305 #if NPY_HALF_GENERATE_OVERFLOW
6306 h_sig += h_exp;
6307 if (h_sig == 0x7c00u)
6308 {
6309 npy_set_floatstatus_overflow();
6310 }
6311 return h_sgn + h_sig;
6312 #else
6313 return h_sgn + h_exp + h_sig;
6314 #endif
6315 }
6316
npy_float_to_half(float_t f)6317 static uint16_t npy_float_to_half(float_t f)
6318 {
6319 union
6320 {
6321 float_t f;
6322 uint32_t fbits;
6323 } conv;
6324 conv.f = f;
6325 return npy_floatbits_to_halfbits(conv.fbits);
6326 }
6327
6328 /**
6329 * @brief SFLP GBIAS value. The register value is expressed as half-precision
6330 * floating-point format: SEEEEEFFFFFFFFFF (S: 1 sign bit; E: 5 exponent
6331 * bits; F: 10 fraction bits).[set]
6332 *
6333 * @param ctx read / write interface definitions
6334 * @param val GBIAS x/y/z val.
6335 * @retval interface status (MANDATORY: return 0 -> no Error)
6336 *
6337 */
lsm6dsv16b_sflp_game_gbias_set(const stmdev_ctx_t * ctx,lsm6dsv16b_sflp_gbias_t * val)6338 int32_t lsm6dsv16b_sflp_game_gbias_set(const stmdev_ctx_t *ctx,
6339 lsm6dsv16b_sflp_gbias_t *val)
6340 {
6341 lsm6dsv16b_sflp_data_rate_t sflp_odr;
6342 lsm6dsv16b_emb_func_exec_status_t emb_func_sts;
6343 lsm6dsv16b_data_ready_t drdy;
6344 lsm6dsv16b_xl_full_scale_t xl_fs;
6345 lsm6dsv16b_ctrl10_t ctrl10;
6346 uint8_t master_config;
6347 uint8_t emb_func_en_saved[2];
6348 uint8_t conf_saved[2];
6349 uint8_t reg_zero[2] = {0x0, 0x0};
6350 uint16_t gbias_hf[3];
6351 float_t k = 0.005f;
6352 int16_t xl_data[3];
6353 int32_t data_tmp;
6354 uint8_t *data_ptr = (uint8_t *)&data_tmp;
6355 uint8_t i, j;
6356 int32_t ret;
6357
6358 ret = lsm6dsv16b_sflp_data_rate_get(ctx, &sflp_odr);
6359 if (ret != 0)
6360 {
6361 return ret;
6362 }
6363
6364 /* Calculate k factor */
6365 switch (sflp_odr)
6366 {
6367 case LSM6DSV16B_SFLP_15Hz:
6368 k = 0.04f;
6369 break;
6370 case LSM6DSV16B_SFLP_30Hz:
6371 k = 0.02f;
6372 break;
6373 case LSM6DSV16B_SFLP_60Hz:
6374 k = 0.01f;
6375 break;
6376 case LSM6DSV16B_SFLP_120Hz:
6377 k = 0.005f;
6378 break;
6379 case LSM6DSV16B_SFLP_240Hz:
6380 k = 0.0025f;
6381 break;
6382 case LSM6DSV16B_SFLP_480Hz:
6383 k = 0.00125f;
6384 break;
6385 }
6386
6387 /* compute gbias as half precision float in order to be put in embedded advanced feature register */
6388 gbias_hf[0] = npy_float_to_half(val->gbias_x * (3.14159265358979323846f / 180.0f) / k);
6389 gbias_hf[1] = npy_float_to_half(val->gbias_y * (3.14159265358979323846f / 180.0f) / k);
6390 gbias_hf[2] = npy_float_to_half(val->gbias_z * (3.14159265358979323846f / 180.0f) / k);
6391
6392 /* Save sensor configuration and set high-performance mode (if the sensor is in power-down mode, turn it on) */
6393 ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL1, conf_saved, 2);
6394 ret += lsm6dsv16b_xl_mode_set(ctx, LSM6DSV16B_XL_HIGH_PERFORMANCE_MD);
6395 ret += lsm6dsv16b_gy_mode_set(ctx, LSM6DSV16B_GY_HIGH_PERFORMANCE_MD);
6396 if ((conf_saved[0] & 0x0FU) == LSM6DSV16B_XL_ODR_OFF)
6397 {
6398 ret += lsm6dsv16b_xl_data_rate_set(ctx, LSM6DSV16B_XL_ODR_AT_120Hz);
6399 }
6400
6401 /* disable algos */
6402 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
6403 ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, emb_func_en_saved,
6404 2);
6405 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, reg_zero, 2);
6406 do
6407 {
6408 ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EXEC_STATUS,
6409 (uint8_t *)&emb_func_sts, 1);
6410 } while (emb_func_sts.emb_func_endop != 1);
6411 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
6412
6413 // enable gbias setting
6414 ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1);
6415 ctrl10.emb_func_debug = 1;
6416 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1);
6417
6418 /* enable algos */
6419 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
6420 emb_func_en_saved[0] |= 0x02; /* force SFLP GAME en */
6421 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_A, emb_func_en_saved,
6422 2);
6423 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
6424
6425 ret += lsm6dsv16b_xl_full_scale_get(ctx, &xl_fs);
6426
6427 /* Read XL data */
6428 do
6429 {
6430 ret += lsm6dsv16b_flag_data_ready_get(ctx, &drdy);
6431 } while (drdy.drdy_xl != 1);
6432 ret += lsm6dsv16b_acceleration_raw_get(ctx, xl_data);
6433
6434 /* force sflp initialization */
6435 master_config = 0x40;
6436 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, &master_config,
6437 1);
6438 for (i = 0; i < 3; i++)
6439 {
6440 j = 0;
6441 data_tmp = (int32_t)xl_data[i];
6442 data_tmp <<= xl_fs; // shift based on current fs
6443 ret += lsm6dsv16b_write_reg(ctx, 0x02 + 3 * i, &data_ptr[j++], 1);
6444 ret += lsm6dsv16b_write_reg(ctx, 0x03 + 3 * i, &data_ptr[j++], 1);
6445 ret += lsm6dsv16b_write_reg(ctx, 0x04 + 3 * i, &data_ptr[j], 1);
6446 }
6447 for (i = 0; i < 3; i++)
6448 {
6449 j = 0;
6450 data_tmp = 0;
6451 ret += lsm6dsv16b_write_reg(ctx, 0x0B + 3 * i, &data_ptr[j++], 1);
6452 ret += lsm6dsv16b_write_reg(ctx, 0x0C + 3 * i, &data_ptr[j++], 1);
6453 ret += lsm6dsv16b_write_reg(ctx, 0x0D + 3 * i, &data_ptr[j], 1);
6454 }
6455 master_config = 0x00;
6456 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, &master_config,
6457 1);
6458
6459 // wait end_op (and at least 30 us)
6460 ctx->mdelay(1);
6461 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
6462 do
6463 {
6464 ret += lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EXEC_STATUS,
6465 (uint8_t *)&emb_func_sts, 1);
6466 } while (emb_func_sts.emb_func_endop != 1);
6467 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
6468
6469 /* write gbias in embedded advanced features registers */
6470 ret += lsm6dsv16b_ln_pg_write(ctx, LSM6DSV16B_SFLP_GAME_GBIASX_L,
6471 (uint8_t *)gbias_hf, 6);
6472
6473 /* reload previous sensor configuration */
6474 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL1, conf_saved, 2);
6475
6476 // disable gbias setting
6477 ctrl10.emb_func_debug = 0;
6478 ret += lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL10, (uint8_t *)&ctrl10, 1);
6479
6480 return ret;
6481 }
6482
6483 /**
6484 * @brief SFLP initial configuration [set]
6485 *
6486 * @param ctx read / write interface definitions
6487 * @retval interface status (MANDATORY: return 0 -> no Error)
6488 *
6489 */
lsm6dsv16b_sflp_configure(const stmdev_ctx_t * ctx)6490 int32_t lsm6dsv16b_sflp_configure(const stmdev_ctx_t *ctx)
6491 {
6492 uint8_t val = 0x50;
6493 int32_t ret;
6494
6495 ret = lsm6dsv16b_ln_pg_write(ctx, 0xD2, &val, 1);
6496
6497 return ret;
6498 }
6499
6500 /**
6501 * @}
6502 *
6503 */
6504
6505 /**
6506 * @defgroup Finite State Machine (FSM)
6507 * @brief This section groups all the functions that manage the
6508 * state_machine.
6509 * @{
6510 *
6511 */
6512
6513 /**
6514 * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[set]
6515 *
6516 * @param ctx read / write interface definitions
6517 * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG,
6518 * @retval interface status (MANDATORY: return 0 -> no Error)
6519 *
6520 */
lsm6dsv16b_fsm_permission_set(const stmdev_ctx_t * ctx,lsm6dsv16b_fsm_permission_t val)6521 int32_t lsm6dsv16b_fsm_permission_set(const stmdev_ctx_t *ctx,
6522 lsm6dsv16b_fsm_permission_t val)
6523 {
6524 lsm6dsv16b_func_cfg_access_t func_cfg_access;
6525 int32_t ret;
6526
6527 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
6528 if (ret == 0)
6529 {
6530 func_cfg_access.fsm_wr_ctrl_en = (uint8_t)val & 0x01U;
6531 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
6532 }
6533
6534 return ret;
6535 }
6536
6537 /**
6538 * @brief Enables the control of the CTRL registers to FSM (FSM can change some configurations of the device autonomously).[get]
6539 *
6540 * @param ctx read / write interface definitions
6541 * @param val PROTECT_CTRL_REGS, WRITE_CTRL_REG,
6542 * @retval interface status (MANDATORY: return 0 -> no Error)
6543 *
6544 */
lsm6dsv16b_fsm_permission_get(const stmdev_ctx_t * ctx,lsm6dsv16b_fsm_permission_t * val)6545 int32_t lsm6dsv16b_fsm_permission_get(const stmdev_ctx_t *ctx,
6546 lsm6dsv16b_fsm_permission_t *val)
6547 {
6548 lsm6dsv16b_func_cfg_access_t func_cfg_access;
6549 int32_t ret;
6550
6551 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
6552 switch (func_cfg_access.fsm_wr_ctrl_en)
6553 {
6554 case LSM6DSV16B_PROTECT_CTRL_REGS:
6555 *val = LSM6DSV16B_PROTECT_CTRL_REGS;
6556 break;
6557
6558 case LSM6DSV16B_WRITE_CTRL_REG:
6559 *val = LSM6DSV16B_WRITE_CTRL_REG;
6560 break;
6561
6562 default:
6563 *val = LSM6DSV16B_PROTECT_CTRL_REGS;
6564 break;
6565 }
6566 return ret;
6567 }
6568
6569 /**
6570 * @brief Return the status of the CTRL registers permission (standard interface vs FSM).[get]
6571 *
6572 * @param ctx read / write interface definitions
6573 * @param val 0: all FSM regs are under std_if control, 1: some regs are under FSM control.
6574 * @retval interface status (MANDATORY: return 0 -> no Error)
6575 *
6576 */
lsm6dsv16b_fsm_permission_status(const stmdev_ctx_t * ctx,lsm6dsv16b_fsm_permission_status_t * val)6577 int32_t lsm6dsv16b_fsm_permission_status(const stmdev_ctx_t *ctx,
6578 lsm6dsv16b_fsm_permission_status_t *val)
6579 {
6580 lsm6dsv16b_ctrl_status_t status;
6581 int32_t ret;
6582
6583 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL_STATUS, (uint8_t *)&status, 1);
6584 *val = (status.fsm_wr_ctrl_status == 0) ? LSM6DSV16B_STD_IF_CONTROL : LSM6DSV16B_FSM_CONTROL;
6585
6586 return ret;
6587 }
6588
6589 /**
6590 * @brief Enable Finite State Machine (FSM) feature.[set]
6591 *
6592 * @param ctx read / write interface definitions
6593 * @param val Enable Finite State Machine (FSM) feature.
6594 * @retval interface status (MANDATORY: return 0 -> no Error)
6595 *
6596 */
lsm6dsv16b_fsm_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16b_fsm_mode_t val)6597 int32_t lsm6dsv16b_fsm_mode_set(const stmdev_ctx_t *ctx, lsm6dsv16b_fsm_mode_t val)
6598 {
6599 lsm6dsv16b_emb_func_en_b_t emb_func_en_b;
6600 lsm6dsv16b_fsm_enable_t fsm_enable;
6601 int32_t ret;
6602
6603 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
6604 if (ret == 0)
6605 {
6606 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
6607 }
6608 if (ret == 0)
6609 {
6610 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
6611 }
6612 if ((val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en
6613 | val.fsm1_en | val.fsm2_en | val.fsm1_en | val.fsm1_en) == PROPERTY_ENABLE)
6614 {
6615 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
6616 }
6617 else
6618 {
6619 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
6620 }
6621 if (ret == 0)
6622 {
6623 fsm_enable.fsm1_en = val.fsm1_en;
6624 fsm_enable.fsm2_en = val.fsm2_en;
6625 fsm_enable.fsm3_en = val.fsm3_en;
6626 fsm_enable.fsm4_en = val.fsm4_en;
6627 fsm_enable.fsm5_en = val.fsm5_en;
6628 fsm_enable.fsm6_en = val.fsm6_en;
6629 fsm_enable.fsm7_en = val.fsm7_en;
6630 fsm_enable.fsm8_en = val.fsm8_en;
6631 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
6632 }
6633 if (ret == 0)
6634 {
6635 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
6636 }
6637
6638 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
6639
6640 return ret;
6641 }
6642
6643 /**
6644 * @brief Enable Finite State Machine (FSM) feature.[get]
6645 *
6646 * @param ctx read / write interface definitions
6647 * @param val Enable Finite State Machine (FSM) feature.
6648 * @retval interface status (MANDATORY: return 0 -> no Error)
6649 *
6650 */
lsm6dsv16b_fsm_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16b_fsm_mode_t * val)6651 int32_t lsm6dsv16b_fsm_mode_get(const stmdev_ctx_t *ctx, lsm6dsv16b_fsm_mode_t *val)
6652 {
6653 lsm6dsv16b_fsm_enable_t fsm_enable;
6654 int32_t ret;
6655
6656 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
6657 if (ret == 0)
6658 {
6659 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_ENABLE, (uint8_t *)&fsm_enable, 1);
6660 }
6661
6662 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
6663
6664 val->fsm1_en = fsm_enable.fsm1_en;
6665 val->fsm2_en = fsm_enable.fsm2_en;
6666 val->fsm3_en = fsm_enable.fsm3_en;
6667 val->fsm4_en = fsm_enable.fsm4_en;
6668 val->fsm5_en = fsm_enable.fsm5_en;
6669 val->fsm6_en = fsm_enable.fsm6_en;
6670 val->fsm7_en = fsm_enable.fsm7_en;
6671 val->fsm8_en = fsm_enable.fsm8_en;
6672
6673 return ret;
6674 }
6675
6676 /**
6677 * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[set]
6678 *
6679 * @param ctx read / write interface definitions
6680 * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).
6681 * @retval interface status (MANDATORY: return 0 -> no Error)
6682 *
6683 */
lsm6dsv16b_fsm_long_cnt_set(const stmdev_ctx_t * ctx,uint16_t val)6684 int32_t lsm6dsv16b_fsm_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val)
6685 {
6686 uint8_t buff[2];
6687 int32_t ret;
6688
6689 buff[1] = (uint8_t)(val / 256U);
6690 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6691
6692 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
6693 if (ret == 0)
6694 {
6695 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FSM_LONG_COUNTER_L, (uint8_t *)&buff[0], 2);
6696 }
6697
6698 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
6699
6700 return ret;
6701 }
6702
6703 /**
6704 * @brief FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).[get]
6705 *
6706 * @param ctx read / write interface definitions
6707 * @param val FSM long counter status register. Long counter value is an unsigned integer value (16-bit format).
6708 * @retval interface status (MANDATORY: return 0 -> no Error)
6709 *
6710 */
lsm6dsv16b_fsm_long_cnt_get(const stmdev_ctx_t * ctx,uint16_t * val)6711 int32_t lsm6dsv16b_fsm_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val)
6712 {
6713 uint8_t buff[2];
6714 int32_t ret;
6715
6716 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
6717 if (ret == 0)
6718 {
6719 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_LONG_COUNTER_L, &buff[0], 2);
6720 }
6721
6722 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
6723
6724 *val = buff[1];
6725 *val = (*val * 256U) + buff[0];
6726
6727 return ret;
6728 }
6729
6730 /**
6731 * @brief FSM output registers[get]
6732 *
6733 * @param ctx read / write interface definitions
6734 * @param val FSM output registers
6735 * @retval interface status (MANDATORY: return 0 -> no Error)
6736 *
6737 */
lsm6dsv16b_fsm_out_get(const stmdev_ctx_t * ctx,lsm6dsv16b_fsm_out_t * val)6738 int32_t lsm6dsv16b_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dsv16b_fsm_out_t *val)
6739 {
6740 int32_t ret;
6741
6742 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
6743 if (ret == 0)
6744 {
6745 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_OUTS1, (uint8_t *)val, 8);
6746 }
6747
6748 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
6749
6750 return ret;
6751 }
6752
6753 /**
6754 * @brief Finite State Machine Output Data Rate (ODR) configuration.[set]
6755 *
6756 * @param ctx read / write interface definitions
6757 * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz,
6758 * @retval interface status (MANDATORY: return 0 -> no Error)
6759 *
6760 */
lsm6dsv16b_fsm_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsv16b_fsm_data_rate_t val)6761 int32_t lsm6dsv16b_fsm_data_rate_set(const stmdev_ctx_t *ctx,
6762 lsm6dsv16b_fsm_data_rate_t val)
6763 {
6764 lsm6dsv16b_fsm_odr_t fsm_odr;
6765 int32_t ret;
6766
6767 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
6768 if (ret == 0)
6769 {
6770 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_ODR, (uint8_t *)&fsm_odr, 1);
6771 }
6772
6773 if (ret == 0)
6774 {
6775 fsm_odr.fsm_odr = (uint8_t)val & 0x07U;
6776 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_FSM_ODR, (uint8_t *)&fsm_odr, 1);
6777 }
6778
6779 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
6780
6781 return ret;
6782 }
6783
6784 /**
6785 * @brief Finite State Machine Output Data Rate (ODR) configuration.[get]
6786 *
6787 * @param ctx read / write interface definitions
6788 * @param val FSM_15Hz, FSM_30Hz, FSM_60Hz, FSM_120Hz, FSM_240Hz, FSM_480Hz, FSM_960Hz,
6789 * @retval interface status (MANDATORY: return 0 -> no Error)
6790 *
6791 */
lsm6dsv16b_fsm_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsv16b_fsm_data_rate_t * val)6792 int32_t lsm6dsv16b_fsm_data_rate_get(const stmdev_ctx_t *ctx,
6793 lsm6dsv16b_fsm_data_rate_t *val)
6794 {
6795 lsm6dsv16b_fsm_odr_t fsm_odr;
6796 int32_t ret;
6797
6798 ret = lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_EMBED_FUNC_MEM_BANK);
6799 if (ret == 0)
6800 {
6801 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_FSM_ODR, (uint8_t *)&fsm_odr, 1);
6802 }
6803
6804 ret += lsm6dsv16b_mem_bank_set(ctx, LSM6DSV16B_MAIN_MEM_BANK);
6805
6806 switch (fsm_odr.fsm_odr)
6807 {
6808 case LSM6DSV16B_FSM_15Hz:
6809 *val = LSM6DSV16B_FSM_15Hz;
6810 break;
6811
6812 case LSM6DSV16B_FSM_30Hz:
6813 *val = LSM6DSV16B_FSM_30Hz;
6814 break;
6815
6816 case LSM6DSV16B_FSM_60Hz:
6817 *val = LSM6DSV16B_FSM_60Hz;
6818 break;
6819
6820 case LSM6DSV16B_FSM_120Hz:
6821 *val = LSM6DSV16B_FSM_120Hz;
6822 break;
6823
6824 case LSM6DSV16B_FSM_240Hz:
6825 *val = LSM6DSV16B_FSM_240Hz;
6826 break;
6827
6828 case LSM6DSV16B_FSM_480Hz:
6829 *val = LSM6DSV16B_FSM_480Hz;
6830 break;
6831
6832 case LSM6DSV16B_FSM_960Hz:
6833 *val = LSM6DSV16B_FSM_960Hz;
6834 break;
6835
6836 default:
6837 *val = LSM6DSV16B_FSM_15Hz;
6838 break;
6839 }
6840 return ret;
6841 }
6842
6843 /**
6844 * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[set]
6845 *
6846 * @param ctx read / write interface definitions
6847 * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.
6848 * @retval interface status (MANDATORY: return 0 -> no Error)
6849 *
6850 */
lsm6dsv16b_fsm_long_cnt_timeout_set(const stmdev_ctx_t * ctx,uint16_t val)6851 int32_t lsm6dsv16b_fsm_long_cnt_timeout_set(const stmdev_ctx_t *ctx, uint16_t val)
6852 {
6853 uint8_t buff[2];
6854 int32_t ret;
6855
6856 buff[1] = (uint8_t)(val / 256U);
6857 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6858 ret = lsm6dsv16b_ln_pg_write(ctx, LSM6DSV16B_FSM_LC_TIMEOUT_L, (uint8_t *)&buff[0], 2);
6859
6860 return ret;
6861 }
6862
6863 /**
6864 * @brief FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.[get]
6865 *
6866 * @param ctx read / write interface definitions
6867 * @param val FSM long counter timeout. The long counter timeout value is an unsigned integer value (16-bit format). When the long counter value reached this value, the FSM generates an interrupt.
6868 * @retval interface status (MANDATORY: return 0 -> no Error)
6869 *
6870 */
lsm6dsv16b_fsm_long_cnt_timeout_get(const stmdev_ctx_t * ctx,uint16_t * val)6871 int32_t lsm6dsv16b_fsm_long_cnt_timeout_get(const stmdev_ctx_t *ctx, uint16_t *val)
6872 {
6873 uint8_t buff[2];
6874 int32_t ret;
6875
6876 ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_FSM_LC_TIMEOUT_L, &buff[0], 2);
6877 *val = buff[1];
6878 *val = (*val * 256U) + buff[0];
6879
6880 return ret;
6881 }
6882
6883 /**
6884 * @brief FSM number of programs.[set]
6885 *
6886 * @param ctx read / write interface definitions
6887 * @param val FSM number of programs.
6888 * @retval interface status (MANDATORY: return 0 -> no Error)
6889 *
6890 */
lsm6dsv16b_fsm_number_of_programs_set(const stmdev_ctx_t * ctx,uint8_t val)6891 int32_t lsm6dsv16b_fsm_number_of_programs_set(const stmdev_ctx_t *ctx, uint8_t val)
6892 {
6893 lsm6dsv16b_fsm_programs_t fsm_programs;
6894 int32_t ret;
6895
6896 ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1);
6897 if (ret == 0)
6898 {
6899 fsm_programs.fsm_n_prog = val;
6900 ret = lsm6dsv16b_ln_pg_write(ctx, LSM6DSV16B_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1);
6901 }
6902
6903 return ret;
6904 }
6905
6906 /**
6907 * @brief FSM number of programs.[get]
6908 *
6909 * @param ctx read / write interface definitions
6910 * @param val FSM number of programs.
6911 * @retval interface status (MANDATORY: return 0 -> no Error)
6912 *
6913 */
lsm6dsv16b_fsm_number_of_programs_get(const stmdev_ctx_t * ctx,uint8_t * val)6914 int32_t lsm6dsv16b_fsm_number_of_programs_get(const stmdev_ctx_t *ctx, uint8_t *val)
6915 {
6916 lsm6dsv16b_fsm_programs_t fsm_programs;
6917 int32_t ret;
6918
6919 ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_FSM_PROGRAMS, (uint8_t *)&fsm_programs, 1);
6920 *val = fsm_programs.fsm_n_prog;
6921
6922
6923 return ret;
6924 }
6925
6926 /**
6927 * @brief FSM start address. First available address is 0x35C.[set]
6928 *
6929 * @param ctx read / write interface definitions
6930 * @param val FSM start address. First available address is 0x35C.
6931 * @retval interface status (MANDATORY: return 0 -> no Error)
6932 *
6933 */
lsm6dsv16b_fsm_start_address_set(const stmdev_ctx_t * ctx,uint16_t val)6934 int32_t lsm6dsv16b_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val)
6935 {
6936 uint8_t buff[2];
6937 int32_t ret;
6938
6939 buff[1] = (uint8_t)(val / 256U);
6940 buff[0] = (uint8_t)(val - (buff[1] * 256U));
6941 ret = lsm6dsv16b_ln_pg_write(ctx, LSM6DSV16B_FSM_START_ADD_L, (uint8_t *)&buff[0], 2);
6942
6943 return ret;
6944 }
6945
6946 /**
6947 * @brief FSM start address. First available address is 0x35C.[get]
6948 *
6949 * @param ctx read / write interface definitions
6950 * @param val FSM start address. First available address is 0x35C.
6951 * @retval interface status (MANDATORY: return 0 -> no Error)
6952 *
6953 */
lsm6dsv16b_fsm_start_address_get(const stmdev_ctx_t * ctx,uint16_t * val)6954 int32_t lsm6dsv16b_fsm_start_address_get(const stmdev_ctx_t *ctx, uint16_t *val)
6955 {
6956 uint8_t buff[2];
6957 int32_t ret;
6958
6959 ret = lsm6dsv16b_ln_pg_read(ctx, LSM6DSV16B_FSM_START_ADD_L, &buff[0], 2);
6960 *val = buff[1];
6961 *val = (*val * 256U) + buff[0];
6962
6963 return ret;
6964 }
6965
6966 /**
6967 * @}
6968 *
6969 */
6970
6971 /**
6972 * @addtogroup Accelerometer user offset correction
6973 * @brief This section group all the functions concerning the
6974 * usage of Accelerometer user offset correction
6975 * @{
6976 *
6977 */
6978
6979 /**
6980 * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[set]
6981 *
6982 * @param ctx read / write interface definitions
6983 * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path.
6984 * @retval interface status (MANDATORY: return 0 -> no Error)
6985 *
6986 */
lsm6dsv16b_xl_offset_on_out_set(const stmdev_ctx_t * ctx,uint8_t val)6987 int32_t lsm6dsv16b_xl_offset_on_out_set(const stmdev_ctx_t *ctx, uint8_t val)
6988 {
6989 lsm6dsv16b_ctrl9_t ctrl9;
6990 int32_t ret;
6991
6992 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1);
6993 if (ret == 0)
6994 {
6995 ctrl9.usr_off_on_out = val;
6996 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1);
6997 }
6998
6999 return ret;
7000 }
7001
7002 /**
7003 * @brief Enables accelerometer user offset correction block; it is valid for the low-pass path.[get]
7004 *
7005 * @param ctx read / write interface definitions
7006 * @param val Enables accelerometer user offset correction block; it is valid for the low-pass path.
7007 * @retval interface status (MANDATORY: return 0 -> no Error)
7008 *
7009 */
lsm6dsv16b_xl_offset_on_out_get(const stmdev_ctx_t * ctx,uint8_t * val)7010 int32_t lsm6dsv16b_xl_offset_on_out_get(const stmdev_ctx_t *ctx, uint8_t *val)
7011 {
7012 lsm6dsv16b_ctrl9_t ctrl9;
7013 int32_t ret;
7014
7015 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1);
7016 *val = ctrl9.usr_off_on_out;
7017
7018 return ret;
7019 }
7020
7021 /**
7022 * @brief Accelerometer user offset correction values in mg.[set]
7023 *
7024 * @param ctx read / write interface definitions
7025 * @param val Accelerometer user offset correction values in mg.
7026 * @retval interface status (MANDATORY: return 0 -> no Error)
7027 *
7028 */
lsm6dsv16b_xl_offset_mg_set(const stmdev_ctx_t * ctx,lsm6dsv16b_xl_offset_mg_t val)7029 int32_t lsm6dsv16b_xl_offset_mg_set(const stmdev_ctx_t *ctx,
7030 lsm6dsv16b_xl_offset_mg_t val)
7031 {
7032 lsm6dsv16b_z_ofs_usr_t z_ofs_usr;
7033 lsm6dsv16b_y_ofs_usr_t y_ofs_usr;
7034 lsm6dsv16b_x_ofs_usr_t x_ofs_usr;
7035 lsm6dsv16b_ctrl9_t ctrl9;
7036 int32_t ret;
7037 float_t tmp;
7038
7039 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1);
7040 if (ret == 0)
7041 {
7042 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
7043 }
7044 if (ret == 0)
7045 {
7046 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
7047 }
7048 if (ret == 0)
7049 {
7050 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
7051 }
7052
7053
7054 if ((val.x_mg < (0.0078125f * 127.0f)) && (val.x_mg > (0.0078125f * -127.0f)) &&
7055 (val.y_mg < (0.0078125f * 127.0f)) && (val.y_mg > (0.0078125f * -127.0f)) &&
7056 (val.z_mg < (0.0078125f * 127.0f)) && (val.z_mg > (0.0078125f * -127.0f)))
7057 {
7058 ctrl9.usr_off_w = 0;
7059
7060 tmp = val.z_mg / 0.0078125f;
7061 z_ofs_usr.z_ofs_usr = (uint8_t)tmp;
7062
7063 tmp = val.y_mg / 0.0078125f;
7064 y_ofs_usr.y_ofs_usr = (uint8_t)tmp;
7065
7066 tmp = val.x_mg / 0.0078125f;
7067 x_ofs_usr.x_ofs_usr = (uint8_t)tmp;
7068 }
7069 else if ((val.x_mg < (0.125f * 127.0f)) && (val.x_mg > (0.125f * -127.0f)) &&
7070 (val.y_mg < (0.125f * 127.0f)) && (val.y_mg > (0.125f * -127.0f)) &&
7071 (val.z_mg < (0.125f * 127.0f)) && (val.z_mg > (0.125f * -127.0f)))
7072 {
7073 ctrl9.usr_off_w = 1;
7074
7075 tmp = val.z_mg / 0.125f;
7076 z_ofs_usr.z_ofs_usr = (uint8_t)tmp;
7077
7078 tmp = val.y_mg / 0.125f;
7079 y_ofs_usr.y_ofs_usr = (uint8_t)tmp;
7080
7081 tmp = val.x_mg / 0.125f;
7082 x_ofs_usr.x_ofs_usr = (uint8_t)tmp;
7083 }
7084 else // out of limit
7085 {
7086 ctrl9.usr_off_w = 1;
7087 z_ofs_usr.z_ofs_usr = 0xFFU;
7088 y_ofs_usr.y_ofs_usr = 0xFFU;
7089 x_ofs_usr.x_ofs_usr = 0xFFU;
7090 }
7091
7092 if (ret == 0)
7093 {
7094 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
7095 }
7096 if (ret == 0)
7097 {
7098 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
7099 }
7100 if (ret == 0)
7101 {
7102 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
7103 }
7104 if (ret == 0)
7105 {
7106 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1);
7107 }
7108 return ret;
7109 }
7110
7111 /**
7112 * @brief Accelerometer user offset correction values in mg.[get]
7113 *
7114 * @param ctx read / write interface definitions
7115 * @param val Accelerometer user offset correction values in mg.
7116 * @retval interface status (MANDATORY: return 0 -> no Error)
7117 *
7118 */
lsm6dsv16b_xl_offset_mg_get(const stmdev_ctx_t * ctx,lsm6dsv16b_xl_offset_mg_t * val)7119 int32_t lsm6dsv16b_xl_offset_mg_get(const stmdev_ctx_t *ctx,
7120 lsm6dsv16b_xl_offset_mg_t *val)
7121 {
7122 lsm6dsv16b_z_ofs_usr_t z_ofs_usr;
7123 lsm6dsv16b_y_ofs_usr_t y_ofs_usr;
7124 lsm6dsv16b_x_ofs_usr_t x_ofs_usr;
7125 lsm6dsv16b_ctrl9_t ctrl9;
7126 int32_t ret;
7127
7128 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_CTRL9, (uint8_t *)&ctrl9, 1);
7129 if (ret == 0)
7130 {
7131 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_Z_OFS_USR, (uint8_t *)&z_ofs_usr, 1);
7132 }
7133 if (ret == 0)
7134 {
7135 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_Y_OFS_USR, (uint8_t *)&y_ofs_usr, 1);
7136 }
7137 if (ret == 0)
7138 {
7139 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_X_OFS_USR, (uint8_t *)&x_ofs_usr, 1);
7140 }
7141
7142 if (ctrl9.usr_off_w == PROPERTY_DISABLE)
7143 {
7144 val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.0078125f);
7145 val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.0078125f);
7146 val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.0078125f);
7147 }
7148 else
7149 {
7150 val->z_mg = ((float_t)z_ofs_usr.z_ofs_usr * 0.125f);
7151 val->y_mg = ((float_t)y_ofs_usr.y_ofs_usr * 0.125f);
7152 val->x_mg = ((float_t)x_ofs_usr.x_ofs_usr * 0.125f);
7153 }
7154
7155 return ret;
7156 }
7157
7158 /**
7159 * @}
7160 *
7161 */
7162
7163 /**
7164 * @addtogroup SenseWire (I3C)
7165 * @brief This section group all the functions concerning the
7166 * usage of SenseWire (I3C)
7167 * @{
7168 *
7169 */
7170
7171 /**
7172 * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[set]
7173 *
7174 * @param ctx read / write interface definitions
7175 * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST_,
7176 * @retval interface status (MANDATORY: return 0 -> no Error)
7177 *
7178 */
lsm6dsv16b_i3c_reset_mode_set(const stmdev_ctx_t * ctx,lsm6dsv16b_i3c_reset_mode_t val)7179 int32_t lsm6dsv16b_i3c_reset_mode_set(const stmdev_ctx_t *ctx,
7180 lsm6dsv16b_i3c_reset_mode_t val)
7181 {
7182 lsm6dsv16b_pin_ctrl_t pin_ctrl;
7183 int32_t ret;
7184
7185 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7186 if (ret == 0)
7187 {
7188 pin_ctrl.ibhr_por_en = (uint8_t)val & 0x01U;
7189 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7190 }
7191
7192 return ret;
7193 }
7194
7195 /**
7196 * @brief Selects the action the device will perform after "Reset whole chip" I3C pattern.[get]
7197 *
7198 * @param ctx read / write interface definitions
7199 * @param val SW_RST_DYN_ADDRESS_RST, GLOBAL_RST_,
7200 * @retval interface status (MANDATORY: return 0 -> no Error)
7201 *
7202 */
lsm6dsv16b_i3c_reset_mode_get(const stmdev_ctx_t * ctx,lsm6dsv16b_i3c_reset_mode_t * val)7203 int32_t lsm6dsv16b_i3c_reset_mode_get(const stmdev_ctx_t *ctx,
7204 lsm6dsv16b_i3c_reset_mode_t *val)
7205 {
7206 lsm6dsv16b_pin_ctrl_t pin_ctrl;
7207 int32_t ret;
7208
7209 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7210 switch (pin_ctrl.ibhr_por_en)
7211 {
7212 case LSM6DSV16B_SW_RST_DYN_ADDRESS_RST:
7213 *val = LSM6DSV16B_SW_RST_DYN_ADDRESS_RST;
7214 break;
7215
7216 case LSM6DSV16B_I3C_GLOBAL_RST:
7217 *val = LSM6DSV16B_I3C_GLOBAL_RST;
7218 break;
7219
7220 default:
7221 *val = LSM6DSV16B_SW_RST_DYN_ADDRESS_RST;
7222 break;
7223 }
7224 return ret;
7225 }
7226
7227 /**
7228 * @}
7229 *
7230 */
7231
7232 /**
7233 * @addtogroup Time-Division Multiplexing (TDM)
7234 * @brief This section group all the functions concerning the
7235 * usage of Time-Division Multiplexing (TDM)
7236 * @{
7237 *
7238 */
7239
7240 /**
7241 * @brief Disables pull-up on WCLK pin.[set]
7242 *
7243 * @param ctx read / write interface definitions
7244 * @param val Disables pull-up on WCLK pin.
7245 * @retval interface status (MANDATORY: return 0 -> no Error)
7246 *
7247 */
lsm6dsv16b_tdm_dis_wclk_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)7248 int32_t lsm6dsv16b_tdm_dis_wclk_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
7249 {
7250 lsm6dsv16b_pin_ctrl_t pin_ctrl;
7251 int32_t ret;
7252
7253 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7254 if (ret == 0)
7255 {
7256 pin_ctrl.tdm_wclk_pu_dis = val;
7257 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7258 }
7259
7260 return ret;
7261 }
7262
7263 /**
7264 * @brief Disables pull-up on WCLK pin.[get]
7265 *
7266 * @param ctx read / write interface definitions
7267 * @param val Disables pull-up on WCLK pin.
7268 * @retval interface status (MANDATORY: return 0 -> no Error)
7269 *
7270 */
lsm6dsv16b_tdm_dis_wclk_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)7271 int32_t lsm6dsv16b_tdm_dis_wclk_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
7272 {
7273 lsm6dsv16b_pin_ctrl_t pin_ctrl;
7274 int32_t ret;
7275
7276 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
7277 *val = pin_ctrl.tdm_wclk_pu_dis;
7278
7279 return ret;
7280 }
7281
7282 /**
7283 * @brief Enables pull-up on TDMout pin.[set]
7284 *
7285 * @param ctx read / write interface definitions
7286 * @param val Enables pull-up on TDMout pin.
7287 * @retval interface status (MANDATORY: return 0 -> no Error)
7288 *
7289 */
lsm6dsv16b_tdm_tdmout_pull_up_set(const stmdev_ctx_t * ctx,uint8_t val)7290 int32_t lsm6dsv16b_tdm_tdmout_pull_up_set(const stmdev_ctx_t *ctx, uint8_t val)
7291 {
7292 lsm6dsv16b_if_cfg_t if_cfg;
7293 int32_t ret;
7294
7295 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
7296 if (ret == 0)
7297 {
7298 if_cfg.tdm_out_pu_en = val;
7299 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
7300 }
7301
7302 return ret;
7303 }
7304
7305 /**
7306 * @brief Enables pull-up on TDMout pin.[get]
7307 *
7308 * @param ctx read / write interface definitions
7309 * @param val Enables pull-up on TDMout pin.
7310 * @retval interface status (MANDATORY: return 0 -> no Error)
7311 *
7312 */
lsm6dsv16b_tdm_tdmout_pull_up_get(const stmdev_ctx_t * ctx,uint8_t * val)7313 int32_t lsm6dsv16b_tdm_tdmout_pull_up_get(const stmdev_ctx_t *ctx, uint8_t *val)
7314 {
7315 lsm6dsv16b_if_cfg_t if_cfg;
7316 int32_t ret;
7317
7318 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_IF_CFG, (uint8_t *)&if_cfg, 1);
7319 *val = if_cfg.tdm_out_pu_en;
7320
7321 return ret;
7322 }
7323
7324 /**
7325 * @brief WCLK and BCLK frequencies.[set]
7326 *
7327 * @param ctx read / write interface definitions
7328 * @param val WCLK_8kHZ_1024kHz, WCLK_16kHZ_2048kHz, WCLK_8kHZ_2048kHz, WCLK_16kHZ_1024kHz,
7329 * @retval interface status (MANDATORY: return 0 -> no Error)
7330 *
7331 */
lsm6dsv16b_tdm_wclk_bclk_set(const stmdev_ctx_t * ctx,lsm6dsv16b_tdm_wclk_bclk_t val)7332 int32_t lsm6dsv16b_tdm_wclk_bclk_set(const stmdev_ctx_t *ctx,
7333 lsm6dsv16b_tdm_wclk_bclk_t val)
7334 {
7335 lsm6dsv16b_tdm_cfg0_t tdm_cfg0;
7336 int32_t ret;
7337
7338 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
7339 if (ret == 0)
7340 {
7341 tdm_cfg0.tdm_wclk_bclk_sel = ((uint8_t)val & 0x4U) >> 2;
7342 tdm_cfg0.tdm_wclk = (uint8_t)val & 0x3U;
7343 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
7344 }
7345
7346 return ret;
7347 }
7348
7349 /**
7350 * @brief WCLK and BCLK frequencies.[get]
7351 *
7352 * @param ctx read / write interface definitions
7353 * @param val WCLK_8kHZ_1024kHz, WCLK_16kHZ_2048kHz, WCLK_8kHZ_2048kHz, WCLK_16kHZ_1024kHz,
7354 * @retval interface status (MANDATORY: return 0 -> no Error)
7355 *
7356 */
lsm6dsv16b_tdm_wclk_bclk_get(const stmdev_ctx_t * ctx,lsm6dsv16b_tdm_wclk_bclk_t * val)7357 int32_t lsm6dsv16b_tdm_wclk_bclk_get(const stmdev_ctx_t *ctx,
7358 lsm6dsv16b_tdm_wclk_bclk_t *val)
7359 {
7360 lsm6dsv16b_tdm_cfg0_t tdm_cfg0;
7361 int32_t ret;
7362
7363 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
7364 switch ((tdm_cfg0.tdm_wclk_bclk_sel << 2) + tdm_cfg0.tdm_wclk)
7365 {
7366 case LSM6DSV16B_WCLK_16kHZ_BCLK_2048kHz:
7367 *val = LSM6DSV16B_WCLK_16kHZ_BCLK_2048kHz;
7368 break;
7369
7370 case LSM6DSV16B_WCLK_8kHZ_BCLK_2048kHz:
7371 *val = LSM6DSV16B_WCLK_8kHZ_BCLK_2048kHz;
7372 break;
7373
7374 default:
7375 *val = LSM6DSV16B_WCLK_8kHZ_BCLK_2048kHz;
7376 break;
7377 }
7378 return ret;
7379 }
7380
7381 /**
7382 * @brief Selection of TDM slot for transmission.[set]
7383 *
7384 * @param ctx read / write interface definitions
7385 * @param val SLOT_012, SLOT_456,
7386 * @retval interface status (MANDATORY: return 0 -> no Error)
7387 *
7388 */
lsm6dsv16b_tdm_slot_set(const stmdev_ctx_t * ctx,lsm6dsv16b_tdm_slot_t val)7389 int32_t lsm6dsv16b_tdm_slot_set(const stmdev_ctx_t *ctx, lsm6dsv16b_tdm_slot_t val)
7390 {
7391 lsm6dsv16b_tdm_cfg0_t tdm_cfg0;
7392 int32_t ret;
7393
7394 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
7395 if (ret == 0)
7396 {
7397 tdm_cfg0.tdm_slot_sel = (uint8_t)val & 0x01U;
7398 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
7399 }
7400
7401 return ret;
7402 }
7403
7404 /**
7405 * @brief Selection of TDM slot for transmission.[get]
7406 *
7407 * @param ctx read / write interface definitions
7408 * @param val SLOT_012, SLOT_456,
7409 * @retval interface status (MANDATORY: return 0 -> no Error)
7410 *
7411 */
lsm6dsv16b_tdm_slot_get(const stmdev_ctx_t * ctx,lsm6dsv16b_tdm_slot_t * val)7412 int32_t lsm6dsv16b_tdm_slot_get(const stmdev_ctx_t *ctx, lsm6dsv16b_tdm_slot_t *val)
7413 {
7414 lsm6dsv16b_tdm_cfg0_t tdm_cfg0;
7415 int32_t ret;
7416
7417 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
7418 switch (tdm_cfg0.tdm_slot_sel)
7419 {
7420 case LSM6DSV16B_SLOT_012:
7421 *val = LSM6DSV16B_SLOT_012;
7422 break;
7423
7424 case LSM6DSV16B_SLOT_456:
7425 *val = LSM6DSV16B_SLOT_456;
7426 break;
7427
7428 default:
7429 *val = LSM6DSV16B_SLOT_012;
7430 break;
7431 }
7432 return ret;
7433 }
7434
7435 /**
7436 * @brief BCLK edge selection for TDM interface.[set]
7437 *
7438 * @param ctx read / write interface definitions
7439 * @param val BCLK_RISING, BCLK_FALLING,
7440 * @retval interface status (MANDATORY: return 0 -> no Error)
7441 *
7442 */
lsm6dsv16b_tdm_bclk_edge_set(const stmdev_ctx_t * ctx,lsm6dsv16b_tdm_bclk_edge_t val)7443 int32_t lsm6dsv16b_tdm_bclk_edge_set(const stmdev_ctx_t *ctx,
7444 lsm6dsv16b_tdm_bclk_edge_t val)
7445 {
7446 lsm6dsv16b_tdm_cfg0_t tdm_cfg0;
7447 int32_t ret;
7448
7449 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
7450 if (ret == 0)
7451 {
7452 tdm_cfg0.tdm_bclk_edge_sel = (uint8_t)val & 0x01U;
7453 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
7454 }
7455
7456 return ret;
7457 }
7458
7459 /**
7460 * @brief BCLK edge selection for TDM interface.[get]
7461 *
7462 * @param ctx read / write interface definitions
7463 * @param val BCLK_RISING, BCLK_FALLING,
7464 * @retval interface status (MANDATORY: return 0 -> no Error)
7465 *
7466 */
lsm6dsv16b_tdm_bclk_edge_get(const stmdev_ctx_t * ctx,lsm6dsv16b_tdm_bclk_edge_t * val)7467 int32_t lsm6dsv16b_tdm_bclk_edge_get(const stmdev_ctx_t *ctx,
7468 lsm6dsv16b_tdm_bclk_edge_t *val)
7469 {
7470 lsm6dsv16b_tdm_cfg0_t tdm_cfg0;
7471 int32_t ret;
7472
7473 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
7474 switch (tdm_cfg0.tdm_bclk_edge_sel)
7475 {
7476 case LSM6DSV16B_BCLK_RISING:
7477 *val = LSM6DSV16B_BCLK_RISING;
7478 break;
7479
7480 case LSM6DSV16B_BCLK_FALLING:
7481 *val = LSM6DSV16B_BCLK_FALLING;
7482 break;
7483
7484 default:
7485 *val = LSM6DSV16B_BCLK_RISING;
7486 break;
7487 }
7488 return ret;
7489 }
7490
7491 /**
7492 * @brief Enables TDM delayed configuration.[set]
7493 *
7494 * @param ctx read / write interface definitions
7495 * @param val Enables TDM delayed configuration.
7496 * @retval interface status (MANDATORY: return 0 -> no Error)
7497 *
7498 */
lsm6dsv16b_tdm_delayed_conf_set(const stmdev_ctx_t * ctx,uint8_t val)7499 int32_t lsm6dsv16b_tdm_delayed_conf_set(const stmdev_ctx_t *ctx, uint8_t val)
7500 {
7501 lsm6dsv16b_tdm_cfg0_t tdm_cfg0;
7502 int32_t ret;
7503
7504 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
7505 if (ret == 0)
7506 {
7507 tdm_cfg0.tdm_delayed_cfg = val;
7508 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
7509 }
7510
7511 return ret;
7512 }
7513
7514 /**
7515 * @brief Enables TDM delayed configuration.[get]
7516 *
7517 * @param ctx read / write interface definitions
7518 * @param val Enables TDM delayed configuration.
7519 * @retval interface status (MANDATORY: return 0 -> no Error)
7520 *
7521 */
lsm6dsv16b_tdm_delayed_conf_get(const stmdev_ctx_t * ctx,uint8_t * val)7522 int32_t lsm6dsv16b_tdm_delayed_conf_get(const stmdev_ctx_t *ctx, uint8_t *val)
7523 {
7524 lsm6dsv16b_tdm_cfg0_t tdm_cfg0;
7525 int32_t ret;
7526
7527 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG0, (uint8_t *)&tdm_cfg0, 1);
7528 *val = tdm_cfg0.tdm_delayed_cfg;
7529
7530 return ret;
7531 }
7532
7533
7534 /**
7535 * @brief Selects order of transmission of TDM axes.[set]
7536 *
7537 * @param ctx read / write interface definitions
7538 * @param val TDM_ORDER_ZYX, TDM_ORDER_XZY, TDM_ORDER_XYZ,
7539 * @retval interface status (MANDATORY: return 0 -> no Error)
7540 *
7541 */
lsm6dsv16b_tdm_axis_order_set(const stmdev_ctx_t * ctx,lsm6dsv16b_tdm_axis_order_t val)7542 int32_t lsm6dsv16b_tdm_axis_order_set(const stmdev_ctx_t *ctx,
7543 lsm6dsv16b_tdm_axis_order_t val)
7544 {
7545 lsm6dsv16b_tdm_cfg1_t tdm_cfg1;
7546 int32_t ret;
7547
7548 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
7549 if (ret == 0)
7550 {
7551 tdm_cfg1.tdm_axes_ord_sel = (uint8_t)val & 0x03U;
7552 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
7553 }
7554
7555 return ret;
7556 }
7557
7558 /**
7559 * @brief Selects order of transmission of TDM axes.[get]
7560 *
7561 * @param ctx read / write interface definitions
7562 * @param val TDM_ORDER_ZYX, TDM_ORDER_XZY, TDM_ORDER_XYZ,
7563 * @retval interface status (MANDATORY: return 0 -> no Error)
7564 *
7565 */
lsm6dsv16b_tdm_axis_order_get(const stmdev_ctx_t * ctx,lsm6dsv16b_tdm_axis_order_t * val)7566 int32_t lsm6dsv16b_tdm_axis_order_get(const stmdev_ctx_t *ctx,
7567 lsm6dsv16b_tdm_axis_order_t *val)
7568 {
7569 lsm6dsv16b_tdm_cfg1_t tdm_cfg1;
7570 int32_t ret;
7571
7572 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG1, (uint8_t *)&tdm_cfg1, 1);
7573 switch (tdm_cfg1.tdm_axes_ord_sel)
7574 {
7575 case LSM6DSV16B_TDM_ORDER_ZYX:
7576 *val = LSM6DSV16B_TDM_ORDER_ZYX;
7577 break;
7578
7579 case LSM6DSV16B_TDM_ORDER_XZY:
7580 *val = LSM6DSV16B_TDM_ORDER_XZY;
7581 break;
7582
7583 case LSM6DSV16B_TDM_ORDER_XYZ:
7584 *val = LSM6DSV16B_TDM_ORDER_XYZ;
7585 break;
7586
7587 default:
7588 *val = LSM6DSV16B_TDM_ORDER_ZYX;
7589 break;
7590 }
7591 return ret;
7592 }
7593
7594 /**
7595 * @brief TDM channel accelerometer full-scale selection.[set]
7596 *
7597 * @param ctx read / write interface definitions
7598 * @param val TDM_2g, TDM_4g, TDM_8g,
7599 * @retval interface status (MANDATORY: return 0 -> no Error)
7600 *
7601 */
lsm6dsv16b_tdm_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsv16b_tdm_xl_full_scale_t val)7602 int32_t lsm6dsv16b_tdm_xl_full_scale_set(const stmdev_ctx_t *ctx,
7603 lsm6dsv16b_tdm_xl_full_scale_t val)
7604 {
7605 lsm6dsv16b_tdm_cfg2_t tdm_cfg2;
7606 int32_t ret;
7607
7608 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
7609 if (ret == 0)
7610 {
7611 tdm_cfg2.tdm_fs_xl = (uint8_t)val & 0x3U;
7612 ret = lsm6dsv16b_write_reg(ctx, LSM6DSV16B_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
7613 }
7614
7615 return ret;
7616 }
7617
7618 /**
7619 * @brief TDM channel accelerometer full-scale selection.[get]
7620 *
7621 * @param ctx read / write interface definitions
7622 * @param val TDM_2g, TDM_4g, TDM_8g,
7623 * @retval interface status (MANDATORY: return 0 -> no Error)
7624 *
7625 */
lsm6dsv16b_tdm_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsv16b_tdm_xl_full_scale_t * val)7626 int32_t lsm6dsv16b_tdm_xl_full_scale_get(const stmdev_ctx_t *ctx,
7627 lsm6dsv16b_tdm_xl_full_scale_t *val)
7628 {
7629 lsm6dsv16b_tdm_cfg2_t tdm_cfg2;
7630 int32_t ret;
7631
7632 ret = lsm6dsv16b_read_reg(ctx, LSM6DSV16B_TDM_CFG2, (uint8_t *)&tdm_cfg2, 1);
7633 switch (tdm_cfg2.tdm_fs_xl)
7634 {
7635 case LSM6DSV16B_TDM_2g:
7636 *val = LSM6DSV16B_TDM_2g;
7637 break;
7638
7639 case LSM6DSV16B_TDM_4g:
7640 *val = LSM6DSV16B_TDM_4g;
7641 break;
7642
7643 case LSM6DSV16B_TDM_8g:
7644 *val = LSM6DSV16B_TDM_8g;
7645 break;
7646
7647 default:
7648 *val = LSM6DSV16B_TDM_2g;
7649 break;
7650 }
7651 return ret;
7652 }
7653
7654 /**
7655 * @}
7656 *
7657 */
7658
7659 /**
7660 * @}
7661 *
7662 */
7663
7664 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
7665
