1 /**
2 ******************************************************************************
3 * @file lsm6dsrx_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSRX driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dsrx_reg.h"
21
22 /**
23 * @defgroup LSM6DSRX
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dsrx enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LSM6DSRX_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6dsrx_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dsrx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx read / write interface definitions(ptr)
69 * @param reg register to write
70 * @param data pointer to data to write in register reg(ptr)
71 * @param len number of consecutive register to write
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lsm6dsrx_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lsm6dsrx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup LSM6DSRX_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
102
lsm6dsrx_from_fs2g_to_mg(int16_t lsb)103 float_t lsm6dsrx_from_fs2g_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb * 0.061f);
106 }
107
lsm6dsrx_from_fs4g_to_mg(int16_t lsb)108 float_t lsm6dsrx_from_fs4g_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb * 0.122f);
111 }
112
lsm6dsrx_from_fs8g_to_mg(int16_t lsb)113 float_t lsm6dsrx_from_fs8g_to_mg(int16_t lsb)
114 {
115 return ((float_t)lsb * 0.244f);
116 }
117
lsm6dsrx_from_fs16g_to_mg(int16_t lsb)118 float_t lsm6dsrx_from_fs16g_to_mg(int16_t lsb)
119 {
120 return ((float_t)lsb * 0.488f);
121 }
122
lsm6dsrx_from_fs125dps_to_mdps(int16_t lsb)123 float_t lsm6dsrx_from_fs125dps_to_mdps(int16_t lsb)
124 {
125 return ((float_t)lsb * 4.375f);
126 }
127
lsm6dsrx_from_fs250dps_to_mdps(int16_t lsb)128 float_t lsm6dsrx_from_fs250dps_to_mdps(int16_t lsb)
129 {
130 return ((float_t)lsb * 8.75f);
131 }
132
lsm6dsrx_from_fs500dps_to_mdps(int16_t lsb)133 float_t lsm6dsrx_from_fs500dps_to_mdps(int16_t lsb)
134 {
135 return ((float_t)lsb * 17.50f);
136 }
137
lsm6dsrx_from_fs1000dps_to_mdps(int16_t lsb)138 float_t lsm6dsrx_from_fs1000dps_to_mdps(int16_t lsb)
139 {
140 return ((float_t)lsb * 35.0f);
141 }
142
lsm6dsrx_from_fs2000dps_to_mdps(int16_t lsb)143 float_t lsm6dsrx_from_fs2000dps_to_mdps(int16_t lsb)
144 {
145 return ((float_t)lsb * 70.0f);
146 }
147
lsm6dsrx_from_fs4000dps_to_mdps(int16_t lsb)148 float_t lsm6dsrx_from_fs4000dps_to_mdps(int16_t lsb)
149 {
150 return ((float_t)lsb * 140.0f);
151 }
152
lsm6dsrx_from_lsb_to_celsius(int16_t lsb)153 float_t lsm6dsrx_from_lsb_to_celsius(int16_t lsb)
154 {
155 return (((float_t)lsb / 256.0f) + 25.0f);
156 }
157
lsm6dsrx_from_lsb_to_nsec(uint32_t lsb)158 uint64_t lsm6dsrx_from_lsb_to_nsec(uint32_t lsb)
159 {
160 return ((uint64_t)lsb * 25000ULL);
161 }
162
163 /**
164 * @}
165 *
166 */
167
168 /**
169 * @defgroup LSM9DS1_Data_generation
170 * @brief This section groups all the functions concerning data
171 * generation
172 * @{
173 *
174 */
175
176 /**
177 * @brief Accelerometer full-scale selection[set]
178 *
179 * @param ctx Read / write interface definitions.(ptr)
180 * @param val Change the values of fs_xl in reg CTRL1_XL
181 * @retval Interface status (MANDATORY: return 0 -> no Error).
182 *
183 */
lsm6dsrx_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsrx_fs_xl_t val)184 int32_t lsm6dsrx_xl_full_scale_set(const stmdev_ctx_t *ctx,
185 lsm6dsrx_fs_xl_t val)
186 {
187 lsm6dsrx_ctrl1_xl_t ctrl1_xl;
188 int32_t ret;
189 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL,
190 (uint8_t *)&ctrl1_xl, 1);
191
192 if (ret == 0)
193 {
194 ctrl1_xl.fs_xl = (uint8_t)val;
195 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_XL,
196 (uint8_t *)&ctrl1_xl, 1);
197 }
198
199 return ret;
200 }
201
202 /**
203 * @brief Accelerometer full-scale selection.[get]
204 *
205 * @param ctx Read / write interface definitions.(ptr)
206 * @param val Get the values of fs_xl in reg CTRL1_XL
207 * @retval Interface status (MANDATORY: return 0 -> no Error).
208 *
209 */
lsm6dsrx_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsrx_fs_xl_t * val)210 int32_t lsm6dsrx_xl_full_scale_get(const stmdev_ctx_t *ctx,
211 lsm6dsrx_fs_xl_t *val)
212 {
213 lsm6dsrx_ctrl1_xl_t ctrl1_xl;
214 int32_t ret;
215 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL,
216 (uint8_t *)&ctrl1_xl, 1);
217
218 switch (ctrl1_xl.fs_xl)
219 {
220 case LSM6DSRX_2g:
221 *val = LSM6DSRX_2g;
222 break;
223
224 case LSM6DSRX_16g:
225 *val = LSM6DSRX_16g;
226 break;
227
228 case LSM6DSRX_4g:
229 *val = LSM6DSRX_4g;
230 break;
231
232 case LSM6DSRX_8g:
233 *val = LSM6DSRX_8g;
234 break;
235
236 default:
237 *val = LSM6DSRX_2g;
238 break;
239 }
240
241 return ret;
242 }
243
244 /**
245 * @brief Accelerometer UI data rate selection.[set]
246 *
247 * @param ctx Read / write interface definitions.(ptr)
248 * @param val Change the values of odr_xl in reg CTRL1_XL
249 * @retval Interface status (MANDATORY: return 0 -> no Error).
250 *
251 */
lsm6dsrx_xl_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsrx_odr_xl_t val)252 int32_t lsm6dsrx_xl_data_rate_set(const stmdev_ctx_t *ctx,
253 lsm6dsrx_odr_xl_t val)
254 {
255 lsm6dsrx_odr_xl_t odr_xl = val;
256 lsm6dsrx_emb_fsm_enable_t fsm_enable;
257 lsm6dsrx_fsm_odr_t fsm_odr;
258 uint8_t mlc_enable;
259 lsm6dsrx_mlc_odr_t mlc_odr;
260 lsm6dsrx_ctrl1_xl_t ctrl1_xl;
261 int32_t ret;
262
263 /* Check the Finite State Machine data rate constraints */
264 ret = lsm6dsrx_fsm_enable_get(ctx, &fsm_enable);
265
266 if (ret == 0)
267 {
268 if ((fsm_enable.fsm_enable_a.fsm1_en |
269 fsm_enable.fsm_enable_a.fsm2_en |
270 fsm_enable.fsm_enable_a.fsm3_en |
271 fsm_enable.fsm_enable_a.fsm4_en |
272 fsm_enable.fsm_enable_a.fsm5_en |
273 fsm_enable.fsm_enable_a.fsm6_en |
274 fsm_enable.fsm_enable_a.fsm7_en |
275 fsm_enable.fsm_enable_a.fsm8_en |
276 fsm_enable.fsm_enable_b.fsm9_en |
277 fsm_enable.fsm_enable_b.fsm10_en |
278 fsm_enable.fsm_enable_b.fsm11_en |
279 fsm_enable.fsm_enable_b.fsm12_en |
280 fsm_enable.fsm_enable_b.fsm13_en |
281 fsm_enable.fsm_enable_b.fsm14_en |
282 fsm_enable.fsm_enable_b.fsm15_en |
283 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
284 {
285 ret = lsm6dsrx_fsm_data_rate_get(ctx, &fsm_odr);
286
287 if (ret == 0)
288 {
289 switch (fsm_odr)
290 {
291 case LSM6DSRX_ODR_FSM_12Hz5:
292 if (val == LSM6DSRX_XL_ODR_OFF)
293 {
294 odr_xl = LSM6DSRX_XL_ODR_12Hz5;
295 }
296
297 else
298 {
299 odr_xl = val;
300 }
301
302 break;
303
304 case LSM6DSRX_ODR_FSM_26Hz:
305 if (val == LSM6DSRX_XL_ODR_OFF)
306 {
307 odr_xl = LSM6DSRX_XL_ODR_26Hz;
308 }
309
310 else if (val == LSM6DSRX_XL_ODR_12Hz5)
311 {
312 odr_xl = LSM6DSRX_XL_ODR_26Hz;
313 }
314
315 else
316 {
317 odr_xl = val;
318 }
319
320 break;
321
322 case LSM6DSRX_ODR_FSM_52Hz:
323 if (val == LSM6DSRX_XL_ODR_OFF)
324 {
325 odr_xl = LSM6DSRX_XL_ODR_52Hz;
326 }
327
328 else if (val == LSM6DSRX_XL_ODR_12Hz5)
329 {
330 odr_xl = LSM6DSRX_XL_ODR_52Hz;
331 }
332
333 else if (val == LSM6DSRX_XL_ODR_26Hz)
334 {
335 odr_xl = LSM6DSRX_XL_ODR_52Hz;
336 }
337
338 else
339 {
340 odr_xl = val;
341 }
342
343 break;
344
345 case LSM6DSRX_ODR_FSM_104Hz:
346 if (val == LSM6DSRX_XL_ODR_OFF)
347 {
348 odr_xl = LSM6DSRX_XL_ODR_104Hz;
349 }
350
351 else if (val == LSM6DSRX_XL_ODR_12Hz5)
352 {
353 odr_xl = LSM6DSRX_XL_ODR_104Hz;
354 }
355
356 else if (val == LSM6DSRX_XL_ODR_26Hz)
357 {
358 odr_xl = LSM6DSRX_XL_ODR_104Hz;
359 }
360
361 else if (val == LSM6DSRX_XL_ODR_52Hz)
362 {
363 odr_xl = LSM6DSRX_XL_ODR_104Hz;
364 }
365
366 else
367 {
368 odr_xl = val;
369 }
370
371 break;
372
373 default:
374 odr_xl = val;
375 break;
376 }
377 }
378 }
379 }
380
381 /* Check the Machine Learning Core data rate constraints */
382 mlc_enable = PROPERTY_DISABLE;
383
384 if (ret == 0)
385 {
386 ret = lsm6dsrx_mlc_get(ctx, &mlc_enable);
387
388 if (mlc_enable == PROPERTY_ENABLE)
389 {
390 ret = lsm6dsrx_mlc_data_rate_get(ctx, &mlc_odr);
391
392 if (ret == 0)
393 {
394 switch (mlc_odr)
395 {
396 case LSM6DSRX_ODR_PRGS_12Hz5:
397 if (val == LSM6DSRX_XL_ODR_OFF)
398 {
399 odr_xl = LSM6DSRX_XL_ODR_12Hz5;
400 }
401
402 else
403 {
404 odr_xl = val;
405 }
406
407 break;
408
409 case LSM6DSRX_ODR_PRGS_26Hz:
410 if (val == LSM6DSRX_XL_ODR_OFF)
411 {
412 odr_xl = LSM6DSRX_XL_ODR_26Hz;
413 }
414
415 else if (val == LSM6DSRX_XL_ODR_12Hz5)
416 {
417 odr_xl = LSM6DSRX_XL_ODR_26Hz;
418 }
419
420 else
421 {
422 odr_xl = val;
423 }
424
425 break;
426
427 case LSM6DSRX_ODR_PRGS_52Hz:
428 if (val == LSM6DSRX_XL_ODR_OFF)
429 {
430 odr_xl = LSM6DSRX_XL_ODR_52Hz;
431 }
432
433 else if (val == LSM6DSRX_XL_ODR_12Hz5)
434 {
435 odr_xl = LSM6DSRX_XL_ODR_52Hz;
436 }
437
438 else if (val == LSM6DSRX_XL_ODR_26Hz)
439 {
440 odr_xl = LSM6DSRX_XL_ODR_52Hz;
441 }
442
443 else
444 {
445 odr_xl = val;
446 }
447
448 break;
449
450 case LSM6DSRX_ODR_PRGS_104Hz:
451 if (val == LSM6DSRX_XL_ODR_OFF)
452 {
453 odr_xl = LSM6DSRX_XL_ODR_104Hz;
454 }
455
456 else if (val == LSM6DSRX_XL_ODR_12Hz5)
457 {
458 odr_xl = LSM6DSRX_XL_ODR_104Hz;
459 }
460
461 else if (val == LSM6DSRX_XL_ODR_26Hz)
462 {
463 odr_xl = LSM6DSRX_XL_ODR_104Hz;
464 }
465
466 else if (val == LSM6DSRX_XL_ODR_52Hz)
467 {
468 odr_xl = LSM6DSRX_XL_ODR_104Hz;
469 }
470
471 else
472 {
473 odr_xl = val;
474 }
475
476 break;
477
478 default:
479 odr_xl = val;
480 break;
481 }
482 }
483 }
484 }
485
486 if (ret == 0)
487 {
488 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL,
489 (uint8_t *)&ctrl1_xl, 1);
490 }
491
492 if (ret == 0)
493 {
494 ctrl1_xl.odr_xl = (uint8_t)odr_xl;
495 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_XL,
496 (uint8_t *)&ctrl1_xl, 1);
497 }
498
499 return ret;
500 }
501
502 /**
503 * @brief Accelerometer UI data rate selection.[get]
504 *
505 * @param ctx Read / write interface definitions.(ptr)
506 * @param val Get the values of odr_xl in reg CTRL1_XL
507 * @retval Interface status (MANDATORY: return 0 -> no Error).
508 *
509 */
lsm6dsrx_xl_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsrx_odr_xl_t * val)510 int32_t lsm6dsrx_xl_data_rate_get(const stmdev_ctx_t *ctx,
511 lsm6dsrx_odr_xl_t *val)
512 {
513 lsm6dsrx_ctrl1_xl_t ctrl1_xl;
514 int32_t ret;
515 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL,
516 (uint8_t *)&ctrl1_xl, 1);
517
518 switch (ctrl1_xl.odr_xl)
519 {
520 case LSM6DSRX_XL_ODR_OFF:
521 *val = LSM6DSRX_XL_ODR_OFF;
522 break;
523
524 case LSM6DSRX_XL_ODR_12Hz5:
525 *val = LSM6DSRX_XL_ODR_12Hz5;
526 break;
527
528 case LSM6DSRX_XL_ODR_26Hz:
529 *val = LSM6DSRX_XL_ODR_26Hz;
530 break;
531
532 case LSM6DSRX_XL_ODR_52Hz:
533 *val = LSM6DSRX_XL_ODR_52Hz;
534 break;
535
536 case LSM6DSRX_XL_ODR_104Hz:
537 *val = LSM6DSRX_XL_ODR_104Hz;
538 break;
539
540 case LSM6DSRX_XL_ODR_208Hz:
541 *val = LSM6DSRX_XL_ODR_208Hz;
542 break;
543
544 case LSM6DSRX_XL_ODR_416Hz:
545 *val = LSM6DSRX_XL_ODR_416Hz;
546 break;
547
548 case LSM6DSRX_XL_ODR_833Hz:
549 *val = LSM6DSRX_XL_ODR_833Hz;
550 break;
551
552 case LSM6DSRX_XL_ODR_1666Hz:
553 *val = LSM6DSRX_XL_ODR_1666Hz;
554 break;
555
556 case LSM6DSRX_XL_ODR_3332Hz:
557 *val = LSM6DSRX_XL_ODR_3332Hz;
558 break;
559
560 case LSM6DSRX_XL_ODR_6667Hz:
561 *val = LSM6DSRX_XL_ODR_6667Hz;
562 break;
563
564 case LSM6DSRX_XL_ODR_1Hz6:
565 *val = LSM6DSRX_XL_ODR_1Hz6;
566 break;
567
568 default:
569 *val = LSM6DSRX_XL_ODR_OFF;
570 break;
571 }
572
573 return ret;
574 }
575
576 /**
577 * @brief Gyroscope UI chain full-scale selection.[set]
578 *
579 * @param ctx Read / write interface definitions.(ptr)
580 * @param val Change the values of fs_g in reg CTRL2_G
581 * @retval Interface status (MANDATORY: return 0 -> no Error).
582 *
583 */
lsm6dsrx_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsrx_fs_g_t val)584 int32_t lsm6dsrx_gy_full_scale_set(const stmdev_ctx_t *ctx,
585 lsm6dsrx_fs_g_t val)
586 {
587 lsm6dsrx_ctrl2_g_t ctrl2_g;
588 int32_t ret;
589 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_G,
590 (uint8_t *)&ctrl2_g, 1);
591
592 if (ret == 0)
593 {
594 ctrl2_g.fs_g = (uint8_t)val;
595 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL2_G,
596 (uint8_t *)&ctrl2_g, 1);
597 }
598
599 return ret;
600 }
601
602 /**
603 * @brief Gyroscope UI chain full-scale selection.[get]
604 *
605 * @param ctx Read / write interface definitions.(ptr)
606 * @param val Get the values of fs_g in reg CTRL2_G
607 * @retval Interface status (MANDATORY: return 0 -> no Error).
608 *
609 */
lsm6dsrx_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsrx_fs_g_t * val)610 int32_t lsm6dsrx_gy_full_scale_get(const stmdev_ctx_t *ctx,
611 lsm6dsrx_fs_g_t *val)
612 {
613 lsm6dsrx_ctrl2_g_t ctrl2_g;
614 int32_t ret;
615 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_G,
616 (uint8_t *)&ctrl2_g, 1);
617
618 switch (ctrl2_g.fs_g)
619 {
620 case LSM6DSRX_125dps:
621 *val = LSM6DSRX_125dps;
622 break;
623
624 case LSM6DSRX_250dps:
625 *val = LSM6DSRX_250dps;
626 break;
627
628 case LSM6DSRX_500dps:
629 *val = LSM6DSRX_500dps;
630 break;
631
632 case LSM6DSRX_1000dps:
633 *val = LSM6DSRX_1000dps;
634 break;
635
636 case LSM6DSRX_2000dps:
637 *val = LSM6DSRX_2000dps;
638 break;
639
640 case LSM6DSRX_4000dps:
641 *val = LSM6DSRX_4000dps;
642 break;
643
644 default:
645 *val = LSM6DSRX_125dps;
646 break;
647 }
648
649 return ret;
650 }
651
652 /**
653 * @brief Gyroscope data rate.[set]
654 *
655 * @param ctx Read / write interface definitions.(ptr)
656 * @param val Change the values of odr_g in reg CTRL2_G
657 * @retval Interface status (MANDATORY: return 0 -> no Error).
658 *
659 */
lsm6dsrx_gy_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsrx_odr_g_t val)660 int32_t lsm6dsrx_gy_data_rate_set(const stmdev_ctx_t *ctx,
661 lsm6dsrx_odr_g_t val)
662 {
663 lsm6dsrx_odr_g_t odr_gy = val;
664 lsm6dsrx_emb_fsm_enable_t fsm_enable;
665 lsm6dsrx_fsm_odr_t fsm_odr;
666 uint8_t mlc_enable;
667 lsm6dsrx_mlc_odr_t mlc_odr;
668 lsm6dsrx_ctrl2_g_t ctrl2_g;
669 int32_t ret;
670
671 /* Check the Finite State Machine data rate constraints */
672 ret = lsm6dsrx_fsm_enable_get(ctx, &fsm_enable);
673
674 if (ret == 0)
675 {
676 if ((fsm_enable.fsm_enable_a.fsm1_en |
677 fsm_enable.fsm_enable_a.fsm2_en |
678 fsm_enable.fsm_enable_a.fsm3_en |
679 fsm_enable.fsm_enable_a.fsm4_en |
680 fsm_enable.fsm_enable_a.fsm5_en |
681 fsm_enable.fsm_enable_a.fsm6_en |
682 fsm_enable.fsm_enable_a.fsm7_en |
683 fsm_enable.fsm_enable_a.fsm8_en |
684 fsm_enable.fsm_enable_b.fsm9_en |
685 fsm_enable.fsm_enable_b.fsm10_en |
686 fsm_enable.fsm_enable_b.fsm11_en |
687 fsm_enable.fsm_enable_b.fsm12_en |
688 fsm_enable.fsm_enable_b.fsm13_en |
689 fsm_enable.fsm_enable_b.fsm14_en |
690 fsm_enable.fsm_enable_b.fsm15_en |
691 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
692 {
693 ret = lsm6dsrx_fsm_data_rate_get(ctx, &fsm_odr);
694
695 if (ret == 0)
696 {
697 switch (fsm_odr)
698 {
699 case LSM6DSRX_ODR_FSM_12Hz5:
700 if (val == LSM6DSRX_GY_ODR_OFF)
701 {
702 odr_gy = LSM6DSRX_GY_ODR_12Hz5;
703 }
704
705 else
706 {
707 odr_gy = val;
708 }
709
710 break;
711
712 case LSM6DSRX_ODR_FSM_26Hz:
713 if (val == LSM6DSRX_GY_ODR_OFF)
714 {
715 odr_gy = LSM6DSRX_GY_ODR_26Hz;
716 }
717
718 else if (val == LSM6DSRX_GY_ODR_12Hz5)
719 {
720 odr_gy = LSM6DSRX_GY_ODR_26Hz;
721 }
722
723 else
724 {
725 odr_gy = val;
726 }
727
728 break;
729
730 case LSM6DSRX_ODR_FSM_52Hz:
731 if (val == LSM6DSRX_GY_ODR_OFF)
732 {
733 odr_gy = LSM6DSRX_GY_ODR_52Hz;
734 }
735
736 else if (val == LSM6DSRX_GY_ODR_12Hz5)
737 {
738 odr_gy = LSM6DSRX_GY_ODR_52Hz;
739 }
740
741 else if (val == LSM6DSRX_GY_ODR_26Hz)
742 {
743 odr_gy = LSM6DSRX_GY_ODR_52Hz;
744 }
745
746 else
747 {
748 odr_gy = val;
749 }
750
751 break;
752
753 case LSM6DSRX_ODR_FSM_104Hz:
754 if (val == LSM6DSRX_GY_ODR_OFF)
755 {
756 odr_gy = LSM6DSRX_GY_ODR_104Hz;
757 }
758
759 else if (val == LSM6DSRX_GY_ODR_12Hz5)
760 {
761 odr_gy = LSM6DSRX_GY_ODR_104Hz;
762 }
763
764 else if (val == LSM6DSRX_GY_ODR_26Hz)
765 {
766 odr_gy = LSM6DSRX_GY_ODR_104Hz;
767 }
768
769 else if (val == LSM6DSRX_GY_ODR_52Hz)
770 {
771 odr_gy = LSM6DSRX_GY_ODR_104Hz;
772 }
773
774 else
775 {
776 odr_gy = val;
777 }
778
779 break;
780
781 default:
782 odr_gy = val;
783 break;
784 }
785 }
786 }
787 }
788
789 /* Check the Machine Learning Core data rate constraints */
790 mlc_enable = PROPERTY_DISABLE;
791
792 if (ret == 0)
793 {
794 ret = lsm6dsrx_mlc_get(ctx, &mlc_enable);
795
796 if (mlc_enable == PROPERTY_ENABLE)
797 {
798 ret = lsm6dsrx_mlc_data_rate_get(ctx, &mlc_odr);
799
800 if (ret == 0)
801 {
802 switch (mlc_odr)
803 {
804 case LSM6DSRX_ODR_PRGS_12Hz5:
805 if (val == LSM6DSRX_GY_ODR_OFF)
806 {
807 odr_gy = LSM6DSRX_GY_ODR_12Hz5;
808 }
809
810 else
811 {
812 odr_gy = val;
813 }
814
815 break;
816
817 case LSM6DSRX_ODR_PRGS_26Hz:
818 if (val == LSM6DSRX_GY_ODR_OFF)
819 {
820 odr_gy = LSM6DSRX_GY_ODR_26Hz;
821 }
822
823 else if (val == LSM6DSRX_GY_ODR_12Hz5)
824 {
825 odr_gy = LSM6DSRX_GY_ODR_26Hz;
826 }
827
828 else
829 {
830 odr_gy = val;
831 }
832
833 break;
834
835 case LSM6DSRX_ODR_PRGS_52Hz:
836 if (val == LSM6DSRX_GY_ODR_OFF)
837 {
838 odr_gy = LSM6DSRX_GY_ODR_52Hz;
839 }
840
841 else if (val == LSM6DSRX_GY_ODR_12Hz5)
842 {
843 odr_gy = LSM6DSRX_GY_ODR_52Hz;
844 }
845
846 else if (val == LSM6DSRX_GY_ODR_26Hz)
847 {
848 odr_gy = LSM6DSRX_GY_ODR_52Hz;
849 }
850
851 else
852 {
853 odr_gy = val;
854 }
855
856 break;
857
858 case LSM6DSRX_ODR_PRGS_104Hz:
859 if (val == LSM6DSRX_GY_ODR_OFF)
860 {
861 odr_gy = LSM6DSRX_GY_ODR_104Hz;
862 }
863
864 else if (val == LSM6DSRX_GY_ODR_12Hz5)
865 {
866 odr_gy = LSM6DSRX_GY_ODR_104Hz;
867 }
868
869 else if (val == LSM6DSRX_GY_ODR_26Hz)
870 {
871 odr_gy = LSM6DSRX_GY_ODR_104Hz;
872 }
873
874 else if (val == LSM6DSRX_GY_ODR_52Hz)
875 {
876 odr_gy = LSM6DSRX_GY_ODR_104Hz;
877 }
878
879 else
880 {
881 odr_gy = val;
882 }
883
884 break;
885
886 default:
887 odr_gy = val;
888 break;
889 }
890 }
891 }
892 }
893
894 if (ret == 0)
895 {
896 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_G,
897 (uint8_t *)&ctrl2_g, 1);
898 }
899
900 if (ret == 0)
901 {
902 ctrl2_g.odr_g = (uint8_t)odr_gy;
903 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL2_G,
904 (uint8_t *)&ctrl2_g, 1);
905 }
906
907 return ret;
908 }
909
910 /**
911 * @brief Gyroscope data rate.[get]
912 *
913 * @param ctx Read / write interface definitions.(ptr)
914 * @param val Get the values of odr_g in reg CTRL2_G
915 * @retval Interface status (MANDATORY: return 0 -> no Error).
916 *
917 */
lsm6dsrx_gy_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsrx_odr_g_t * val)918 int32_t lsm6dsrx_gy_data_rate_get(const stmdev_ctx_t *ctx,
919 lsm6dsrx_odr_g_t *val)
920 {
921 lsm6dsrx_ctrl2_g_t ctrl2_g;
922 int32_t ret;
923 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_G,
924 (uint8_t *)&ctrl2_g, 1);
925
926 switch (ctrl2_g.odr_g)
927 {
928 case LSM6DSRX_GY_ODR_OFF:
929 *val = LSM6DSRX_GY_ODR_OFF;
930 break;
931
932 case LSM6DSRX_GY_ODR_12Hz5:
933 *val = LSM6DSRX_GY_ODR_12Hz5;
934 break;
935
936 case LSM6DSRX_GY_ODR_26Hz:
937 *val = LSM6DSRX_GY_ODR_26Hz;
938 break;
939
940 case LSM6DSRX_GY_ODR_52Hz:
941 *val = LSM6DSRX_GY_ODR_52Hz;
942 break;
943
944 case LSM6DSRX_GY_ODR_104Hz:
945 *val = LSM6DSRX_GY_ODR_104Hz;
946 break;
947
948 case LSM6DSRX_GY_ODR_208Hz:
949 *val = LSM6DSRX_GY_ODR_208Hz;
950 break;
951
952 case LSM6DSRX_GY_ODR_416Hz:
953 *val = LSM6DSRX_GY_ODR_416Hz;
954 break;
955
956 case LSM6DSRX_GY_ODR_833Hz:
957 *val = LSM6DSRX_GY_ODR_833Hz;
958 break;
959
960 case LSM6DSRX_GY_ODR_1666Hz:
961 *val = LSM6DSRX_GY_ODR_1666Hz;
962 break;
963
964 case LSM6DSRX_GY_ODR_3332Hz:
965 *val = LSM6DSRX_GY_ODR_3332Hz;
966 break;
967
968 case LSM6DSRX_GY_ODR_6667Hz:
969 *val = LSM6DSRX_GY_ODR_6667Hz;
970 break;
971
972 default:
973 *val = LSM6DSRX_GY_ODR_OFF;
974 break;
975 }
976
977 return ret;
978 }
979
980 /**
981 * @brief Block data update.[set]
982 *
983 * @param ctx Read / write interface definitions.(ptr)
984 * @param val Change the values of bdu in reg CTRL3_C
985 * @retval Interface status (MANDATORY: return 0 -> no Error).
986 *
987 */
lsm6dsrx_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)988 int32_t lsm6dsrx_block_data_update_set(const stmdev_ctx_t *ctx,
989 uint8_t val)
990 {
991 lsm6dsrx_ctrl3_c_t ctrl3_c;
992 int32_t ret;
993 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C,
994 (uint8_t *)&ctrl3_c, 1);
995
996 if (ret == 0)
997 {
998 ctrl3_c.bdu = (uint8_t)val;
999 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C,
1000 (uint8_t *)&ctrl3_c, 1);
1001 }
1002
1003 return ret;
1004 }
1005
1006 /**
1007 * @brief Block data update.[get]
1008 *
1009 * @param ctx Read / write interface definitions.(ptr)
1010 * @param val Change the values of bdu in reg CTRL3_C
1011 * @retval Interface status (MANDATORY: return 0 -> no Error).
1012 *
1013 */
lsm6dsrx_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)1014 int32_t lsm6dsrx_block_data_update_get(const stmdev_ctx_t *ctx,
1015 uint8_t *val)
1016 {
1017 lsm6dsrx_ctrl3_c_t ctrl3_c;
1018 int32_t ret;
1019 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C,
1020 (uint8_t *)&ctrl3_c, 1);
1021 *val = ctrl3_c.bdu;
1022
1023 return ret;
1024 }
1025
1026 /**
1027 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
1028 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
1029 *
1030 * @param ctx Read / write interface definitions.(ptr)
1031 * @param val Change the values of usr_off_w in reg CTRL6_C
1032 * @retval Interface status (MANDATORY: return 0 -> no Error).
1033 *
1034 */
lsm6dsrx_xl_offset_weight_set(const stmdev_ctx_t * ctx,lsm6dsrx_usr_off_w_t val)1035 int32_t lsm6dsrx_xl_offset_weight_set(const stmdev_ctx_t *ctx,
1036 lsm6dsrx_usr_off_w_t val)
1037 {
1038 lsm6dsrx_ctrl6_c_t ctrl6_c;
1039 int32_t ret;
1040 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C,
1041 (uint8_t *)&ctrl6_c, 1);
1042
1043 if (ret == 0)
1044 {
1045 ctrl6_c.usr_off_w = (uint8_t)val;
1046 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL6_C,
1047 (uint8_t *)&ctrl6_c, 1);
1048 }
1049
1050 return ret;
1051 }
1052
1053 /**
1054 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
1055 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
1056 *
1057 * @param ctx Read / write interface definitions.(ptr)
1058 * @param val Get the values of usr_off_w in reg CTRL6_C
1059 * @retval Interface status (MANDATORY: return 0 -> no Error).
1060 *
1061 */
lsm6dsrx_xl_offset_weight_get(const stmdev_ctx_t * ctx,lsm6dsrx_usr_off_w_t * val)1062 int32_t lsm6dsrx_xl_offset_weight_get(const stmdev_ctx_t *ctx,
1063 lsm6dsrx_usr_off_w_t *val)
1064 {
1065 lsm6dsrx_ctrl6_c_t ctrl6_c;
1066 int32_t ret;
1067 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C,
1068 (uint8_t *)&ctrl6_c, 1);
1069
1070 switch (ctrl6_c.usr_off_w)
1071 {
1072 case LSM6DSRX_LSb_1mg:
1073 *val = LSM6DSRX_LSb_1mg;
1074 break;
1075
1076 case LSM6DSRX_LSb_16mg:
1077 *val = LSM6DSRX_LSb_16mg;
1078 break;
1079
1080 default:
1081 *val = LSM6DSRX_LSb_1mg;
1082 break;
1083 }
1084
1085 return ret;
1086 }
1087
1088 /**
1089 * @brief Accelerometer power mode.[set]
1090 *
1091 * @param ctx Read / write interface definitions.(ptr)
1092 * @param val Change the values of xl_hm_mode in reg CTRL6_C
1093 * @retval Interface status (MANDATORY: return 0 -> no Error).
1094 *
1095 */
lsm6dsrx_xl_power_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_xl_hm_mode_t val)1096 int32_t lsm6dsrx_xl_power_mode_set(const stmdev_ctx_t *ctx,
1097 lsm6dsrx_xl_hm_mode_t val)
1098 {
1099 lsm6dsrx_ctrl6_c_t ctrl6_c;
1100 int32_t ret;
1101 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C,
1102 (uint8_t *)&ctrl6_c, 1);
1103
1104 if (ret == 0)
1105 {
1106 ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
1107 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL6_C,
1108 (uint8_t *)&ctrl6_c, 1);
1109 }
1110
1111 return ret;
1112 }
1113
1114 /**
1115 * @brief Accelerometer power mode[get]
1116 *
1117 * @param ctx Read / write interface definitions.(ptr)
1118 * @param val Get the values of xl_hm_mode in reg CTRL6_C
1119 * @retval Interface status (MANDATORY: return 0 -> no Error).
1120 *
1121 */
lsm6dsrx_xl_power_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_xl_hm_mode_t * val)1122 int32_t lsm6dsrx_xl_power_mode_get(const stmdev_ctx_t *ctx,
1123 lsm6dsrx_xl_hm_mode_t *val)
1124 {
1125 lsm6dsrx_ctrl6_c_t ctrl6_c;
1126 int32_t ret;
1127 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C,
1128 (uint8_t *)&ctrl6_c, 1);
1129
1130 switch (ctrl6_c.xl_hm_mode)
1131 {
1132 case LSM6DSRX_HIGH_PERFORMANCE_MD:
1133 *val = LSM6DSRX_HIGH_PERFORMANCE_MD;
1134 break;
1135
1136 case LSM6DSRX_LOW_NORMAL_POWER_MD:
1137 *val = LSM6DSRX_LOW_NORMAL_POWER_MD;
1138 break;
1139
1140 default:
1141 *val = LSM6DSRX_HIGH_PERFORMANCE_MD;
1142 break;
1143 }
1144
1145 return ret;
1146 }
1147
1148 /**
1149 * @brief Operating mode for gyroscope.[set]
1150 *
1151 * @param ctx Read / write interface definitions.(ptr)
1152 * @param val Change the values of g_hm_mode in reg CTRL7_G
1153 * @retval Interface status (MANDATORY: return 0 -> no Error).
1154 *
1155 */
lsm6dsrx_gy_power_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_g_hm_mode_t val)1156 int32_t lsm6dsrx_gy_power_mode_set(const stmdev_ctx_t *ctx,
1157 lsm6dsrx_g_hm_mode_t val)
1158 {
1159 lsm6dsrx_ctrl7_g_t ctrl7_g;
1160 int32_t ret;
1161 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G,
1162 (uint8_t *)&ctrl7_g, 1);
1163
1164 if (ret == 0)
1165 {
1166 ctrl7_g.g_hm_mode = (uint8_t)val;
1167 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL7_G,
1168 (uint8_t *)&ctrl7_g, 1);
1169 }
1170
1171 return ret;
1172 }
1173
1174 /**
1175 * @brief gy_power_mode: [get] Operating mode for gyroscope.
1176 *
1177 * @param ctx Read / write interface definitions.(ptr)
1178 * @param val Get the values of g_hm_mode in reg CTRL7_G
1179 * @retval Interface status (MANDATORY: return 0 -> no Error).
1180 *
1181 */
lsm6dsrx_gy_power_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_g_hm_mode_t * val)1182 int32_t lsm6dsrx_gy_power_mode_get(const stmdev_ctx_t *ctx,
1183 lsm6dsrx_g_hm_mode_t *val)
1184 {
1185 lsm6dsrx_ctrl7_g_t ctrl7_g;
1186 int32_t ret;
1187 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G,
1188 (uint8_t *)&ctrl7_g, 1);
1189
1190 switch (ctrl7_g.g_hm_mode)
1191 {
1192 case LSM6DSRX_GY_HIGH_PERFORMANCE:
1193 *val = LSM6DSRX_GY_HIGH_PERFORMANCE;
1194 break;
1195
1196 case LSM6DSRX_GY_NORMAL:
1197 *val = LSM6DSRX_GY_NORMAL;
1198 break;
1199
1200 default:
1201 *val = LSM6DSRX_GY_HIGH_PERFORMANCE;
1202 break;
1203 }
1204
1205 return ret;
1206 }
1207
1208 /**
1209 * @brief Read all the interrupt flag of the device.
1210 *[get]
1211 * @param ctx Read / write interface definitions.(ptr)
1212 * @param val Get registers ALL_INT_SRC; WAKE_UP_SRC;
1213 * TAP_SRC; D6D_SRC; STATUS_REG;
1214 * EMB_FUNC_STATUS; FSM_STATUS_A/B
1215 * @retval Interface status (MANDATORY: return 0 -> no Error).
1216 *
1217 */
lsm6dsrx_all_sources_get(const stmdev_ctx_t * ctx,lsm6dsrx_all_sources_t * val)1218 int32_t lsm6dsrx_all_sources_get(const stmdev_ctx_t *ctx,
1219 lsm6dsrx_all_sources_t *val)
1220 {
1221 int32_t ret;
1222
1223 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_ALL_INT_SRC,
1224 (uint8_t *)&val->all_int_src, 1);
1225
1226 if (ret == 0)
1227 {
1228 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_SRC,
1229 (uint8_t *)&val->wake_up_src, 1);
1230 }
1231
1232 if (ret == 0)
1233 {
1234 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_SRC,
1235 (uint8_t *)&val->tap_src, 1);
1236 }
1237
1238 if (ret == 0)
1239 {
1240 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_D6D_SRC,
1241 (uint8_t *)&val->d6d_src, 1);
1242 }
1243
1244 if (ret == 0)
1245 {
1246 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG,
1247 (uint8_t *)&val->status_reg, 1);
1248 }
1249
1250 if (ret == 0)
1251 {
1252 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
1253 }
1254
1255 if (ret == 0)
1256 {
1257 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_STATUS,
1258 (uint8_t *)&val->emb_func_status, 1);
1259 }
1260
1261 if (ret == 0)
1262 {
1263 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_STATUS_A,
1264 (uint8_t *)&val->fsm_status_a, 1);
1265 }
1266
1267 if (ret == 0)
1268 {
1269 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_STATUS_B,
1270 (uint8_t *)&val->fsm_status_b, 1);
1271 }
1272
1273 if (ret == 0)
1274 {
1275 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
1276 }
1277
1278 return ret;
1279 }
1280
1281 /**
1282 * @brief The STATUS_REG register is read by the primary interface.[get]
1283 *
1284 * @param ctx Read / write interface definitions.(ptr)
1285 * @param val Get register STATUS_REG
1286 * @retval Interface status (MANDATORY: return 0 -> no Error).
1287 *
1288 */
lsm6dsrx_status_reg_get(const stmdev_ctx_t * ctx,lsm6dsrx_status_reg_t * val)1289 int32_t lsm6dsrx_status_reg_get(const stmdev_ctx_t *ctx,
1290 lsm6dsrx_status_reg_t *val)
1291 {
1292 int32_t ret;
1293
1294 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG, (uint8_t *) val, 1);
1295
1296 return ret;
1297 }
1298
1299 /**
1300 * @brief Accelerometer new data available.[get]
1301 *
1302 * @param ctx Read / write interface definitions.(ptr)
1303 * @param val Change the values of xlda in reg STATUS_REG
1304 * @retval Interface status (MANDATORY: return 0 -> no Error).
1305 *
1306 */
lsm6dsrx_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1307 int32_t lsm6dsrx_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
1308 uint8_t *val)
1309 {
1310 lsm6dsrx_status_reg_t status_reg;
1311 int32_t ret;
1312
1313 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG,
1314 (uint8_t *)&status_reg, 1);
1315 *val = status_reg.xlda;
1316
1317 return ret;
1318 }
1319
1320 /**
1321 * @brief Gyroscope new data available.[get]
1322 *
1323 * @param ctx Read / write interface definitions.(ptr)
1324 * @param val Change the values of gda in reg STATUS_REG
1325 * @retval Interface status (MANDATORY: return 0 -> no Error).
1326 *
1327 */
lsm6dsrx_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1328 int32_t lsm6dsrx_gy_flag_data_ready_get(const stmdev_ctx_t *ctx,
1329 uint8_t *val)
1330 {
1331 lsm6dsrx_status_reg_t status_reg;
1332 int32_t ret;
1333
1334 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG,
1335 (uint8_t *)&status_reg, 1);
1336 *val = status_reg.gda;
1337
1338 return ret;
1339 }
1340
1341 /**
1342 * @brief Temperature new data available.[get]
1343 *
1344 * @param ctx Read / write interface definitions.(ptr)
1345 * @param val Change the values of tda in reg STATUS_REG
1346 * @retval Interface status (MANDATORY: return 0 -> no Error).
1347 *
1348 */
lsm6dsrx_temp_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1349 int32_t lsm6dsrx_temp_flag_data_ready_get(const stmdev_ctx_t *ctx,
1350 uint8_t *val)
1351 {
1352 lsm6dsrx_status_reg_t status_reg;
1353 int32_t ret;
1354
1355 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG,
1356 (uint8_t *)&status_reg, 1);
1357 *val = status_reg.tda;
1358
1359 return ret;
1360 }
1361
1362 /**
1363 * @brief Accelerometer X-axis user offset correction expressed in two's
1364 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1365 * The value must be in the range [-127 127].[set]
1366 *
1367 * @param ctx Read / write interface definitions.(ptr)
1368 * @param buff Buffer that contains data to write
1369 * @retval Interface status (MANDATORY: return 0 -> no Error).
1370 *
1371 */
lsm6dsrx_xl_usr_offset_x_set(const stmdev_ctx_t * ctx,uint8_t * buff)1372 int32_t lsm6dsrx_xl_usr_offset_x_set(const stmdev_ctx_t *ctx,
1373 uint8_t *buff)
1374 {
1375 int32_t ret;
1376
1377 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_X_OFS_USR, buff, 1);
1378
1379 return ret;
1380 }
1381
1382 /**
1383 * @brief Accelerometer X-axis user offset correction expressed in two's
1384 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1385 * The value must be in the range [-127 127].[get]
1386 *
1387 * @param ctx Read / write interface definitions.(ptr)
1388 * @param buff Buffer that stores data read
1389 * @retval Interface status (MANDATORY: return 0 -> no Error).
1390 *
1391 */
lsm6dsrx_xl_usr_offset_x_get(const stmdev_ctx_t * ctx,uint8_t * buff)1392 int32_t lsm6dsrx_xl_usr_offset_x_get(const stmdev_ctx_t *ctx,
1393 uint8_t *buff)
1394 {
1395 int32_t ret;
1396
1397 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_X_OFS_USR, buff, 1);
1398
1399 return ret;
1400 }
1401
1402 /**
1403 * @brief Accelerometer Y-axis user offset correction expressed in two's
1404 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1405 * The value must be in the range [-127 127].[set]
1406 *
1407 * @param ctx Read / write interface definitions.(ptr)
1408 * @param buff Buffer that contains data to write
1409 * @retval Interface status (MANDATORY: return 0 -> no Error).
1410 *
1411 */
lsm6dsrx_xl_usr_offset_y_set(const stmdev_ctx_t * ctx,uint8_t * buff)1412 int32_t lsm6dsrx_xl_usr_offset_y_set(const stmdev_ctx_t *ctx,
1413 uint8_t *buff)
1414 {
1415 int32_t ret;
1416
1417 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_Y_OFS_USR, buff, 1);
1418
1419 return ret;
1420 }
1421
1422 /**
1423 * @brief Accelerometer Y-axis user offset correction expressed in two's
1424 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1425 * The value must be in the range [-127 127].[get]
1426 *
1427 * @param ctx Read / write interface definitions.(ptr)
1428 * @param buff Buffer that stores data read
1429 * @retval Interface status (MANDATORY: return 0 -> no Error).
1430 *
1431 */
lsm6dsrx_xl_usr_offset_y_get(const stmdev_ctx_t * ctx,uint8_t * buff)1432 int32_t lsm6dsrx_xl_usr_offset_y_get(const stmdev_ctx_t *ctx,
1433 uint8_t *buff)
1434 {
1435 int32_t ret;
1436
1437 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_Y_OFS_USR, buff, 1);
1438
1439 return ret;
1440 }
1441
1442 /**
1443 * @brief Accelerometer Z-axis user offset correction expressed in two's
1444 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1445 * The value must be in the range [-127 127].[set]
1446 *
1447 * @param ctx Read / write interface definitions.(ptr)
1448 * @param buff Buffer that contains data to write
1449 * @retval Interface status (MANDATORY: return 0 -> no Error).
1450 *
1451 */
lsm6dsrx_xl_usr_offset_z_set(const stmdev_ctx_t * ctx,uint8_t * buff)1452 int32_t lsm6dsrx_xl_usr_offset_z_set(const stmdev_ctx_t *ctx,
1453 uint8_t *buff)
1454 {
1455 int32_t ret;
1456
1457 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_Z_OFS_USR, buff, 1);
1458
1459 return ret;
1460 }
1461
1462 /**
1463 * @brief Accelerometer X-axis user offset correction expressed in two's
1464 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1465 * The value must be in the range [-127 127].[get]
1466 *
1467 * @param ctx Read / write interface definitions.(ptr)
1468 * @param buff Buffer that stores data read
1469 * @retval Interface status (MANDATORY: return 0 -> no Error).
1470 *
1471 */
lsm6dsrx_xl_usr_offset_z_get(const stmdev_ctx_t * ctx,uint8_t * buff)1472 int32_t lsm6dsrx_xl_usr_offset_z_get(const stmdev_ctx_t *ctx,
1473 uint8_t *buff)
1474 {
1475 int32_t ret;
1476
1477 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_Z_OFS_USR, buff, 1);
1478
1479 return ret;
1480 }
1481
1482 /**
1483 * @brief Enables user offset on out.[set]
1484 *
1485 * @param ctx Read / write interface definitions.(ptr)
1486 * @param val Change the values of usr_off_on_out in reg CTRL7_G
1487 * @retval Interface status (MANDATORY: return 0 -> no Error).
1488 *
1489 */
lsm6dsrx_xl_usr_offset_set(const stmdev_ctx_t * ctx,uint8_t val)1490 int32_t lsm6dsrx_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val)
1491 {
1492 lsm6dsrx_ctrl7_g_t ctrl7_g;
1493 int32_t ret;
1494
1495 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G,
1496 (uint8_t *)&ctrl7_g, 1);
1497
1498 if (ret == 0)
1499 {
1500 ctrl7_g.usr_off_on_out = (uint8_t)val;
1501 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL7_G,
1502 (uint8_t *)&ctrl7_g, 1);
1503 }
1504
1505 return ret;
1506 }
1507
1508 /**
1509 * @brief Get user offset on out flag.[get]
1510 *
1511 * @param ctx Read / write interface definitions.(ptr)
1512 * @param val Get values of usr_off_on_out in reg CTRL7_G
1513 * @retval Interface status (MANDATORY: return 0 -> no Error).
1514 *
1515 */
lsm6dsrx_xl_usr_offset_get(const stmdev_ctx_t * ctx,uint8_t * val)1516 int32_t lsm6dsrx_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val)
1517 {
1518 lsm6dsrx_ctrl7_g_t ctrl7_g;
1519 int32_t ret;
1520
1521 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G,
1522 (uint8_t *)&ctrl7_g, 1);
1523 *val = ctrl7_g.usr_off_on_out;
1524
1525 return ret;
1526 }
1527
1528 /**
1529 * @}
1530 *
1531 */
1532
1533 /**
1534 * @defgroup LSM6DSRX_Timestamp
1535 * @brief This section groups all the functions that manage the
1536 * timestamp generation.
1537 * @{
1538 *
1539 */
1540
1541 /**
1542 * @brief Reset timestamp counter.[set]
1543 *
1544 * @param ctx Read / write interface definitions.(ptr)
1545 * @retval Interface status (MANDATORY: return 0 -> no Error).
1546 *
1547 */
lsm6dsrx_timestamp_rst(const stmdev_ctx_t * ctx)1548 int32_t lsm6dsrx_timestamp_rst(const stmdev_ctx_t *ctx)
1549 {
1550 uint8_t rst_val = 0xAA;
1551 return lsm6dsrx_write_reg(ctx, LSM6DSRX_TIMESTAMP2, &rst_val, 1);
1552 }
1553
1554 /**
1555 * @brief Enables timestamp counter.[set]
1556 *
1557 * @param ctx Read / write interface definitions.(ptr)
1558 * @param val Change the values of timestamp_en in reg CTRL10_C
1559 * @retval Interface status (MANDATORY: return 0 -> no Error).
1560 *
1561 */
lsm6dsrx_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)1562 int32_t lsm6dsrx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
1563 {
1564 lsm6dsrx_ctrl10_c_t ctrl10_c;
1565 int32_t ret;
1566
1567 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL10_C,
1568 (uint8_t *)&ctrl10_c, 1);
1569
1570 if (ret == 0)
1571 {
1572 ctrl10_c.timestamp_en = (uint8_t)val;
1573 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL10_C,
1574 (uint8_t *)&ctrl10_c, 1);
1575 }
1576
1577 return ret;
1578 }
1579
1580 /**
1581 * @brief Enables timestamp counter.[get]
1582 *
1583 * @param ctx Read / write interface definitions.(ptr)
1584 * @param val Change the values of timestamp_en in reg CTRL10_C
1585 * @retval Interface status (MANDATORY: return 0 -> no Error).
1586 *
1587 */
lsm6dsrx_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)1588 int32_t lsm6dsrx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
1589 {
1590 lsm6dsrx_ctrl10_c_t ctrl10_c;
1591 int32_t ret;
1592
1593 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL10_C,
1594 (uint8_t *)&ctrl10_c, 1);
1595 *val = ctrl10_c.timestamp_en;
1596
1597 return ret;
1598 }
1599
1600 /**
1601 * @brief Timestamp first data output register (r).
1602 * The value is expressed as a 32-bit word and the bit resolution
1603 * is 25 us.[get]
1604 *
1605 * @param ctx Read / write interface definitions.(ptr)
1606 * @param buff Buffer that stores data read
1607 * @retval Interface status (MANDATORY: return 0 -> no Error).
1608 *
1609 */
lsm6dsrx_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)1610 int32_t lsm6dsrx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
1611 {
1612 uint8_t buff[4];
1613 int32_t ret;
1614
1615 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TIMESTAMP0, buff, 4);
1616 *val = buff[3];
1617 *val = (*val * 256U) + buff[2];
1618 *val = (*val * 256U) + buff[1];
1619 *val = (*val * 256U) + buff[0];
1620
1621 return ret;
1622 }
1623
1624 /**
1625 * @}
1626 *
1627 */
1628
1629 /**
1630 * @defgroup LSM6DSRX_Data output
1631 * @brief This section groups all the data output functions.
1632 * @{
1633 *
1634 */
1635
1636 /**
1637 * @brief Circular burst-mode (rounding) read of the output registers.[set]
1638 *
1639 * @param ctx Read / write interface definitions.(ptr)
1640 * @param val Change the values of rounding in reg CTRL5_C
1641 * @retval Interface status (MANDATORY: return 0 -> no Error).
1642 *
1643 */
lsm6dsrx_rounding_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_rounding_t val)1644 int32_t lsm6dsrx_rounding_mode_set(const stmdev_ctx_t *ctx,
1645 lsm6dsrx_rounding_t val)
1646 {
1647 lsm6dsrx_ctrl5_c_t ctrl5_c;
1648 int32_t ret;
1649
1650 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C,
1651 (uint8_t *)&ctrl5_c, 1);
1652
1653 if (ret == 0)
1654 {
1655 ctrl5_c.rounding = (uint8_t)val;
1656 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL5_C,
1657 (uint8_t *)&ctrl5_c, 1);
1658 }
1659
1660 return ret;
1661 }
1662
1663 /**
1664 * @brief Gyroscope UI chain full-scale selection.[get]
1665 *
1666 * @param ctx Read / write interface definitions.(ptr)
1667 * @param val Get the values of rounding in reg CTRL5_C
1668 * @retval Interface status (MANDATORY: return 0 -> no Error).
1669 *
1670 */
lsm6dsrx_rounding_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_rounding_t * val)1671 int32_t lsm6dsrx_rounding_mode_get(const stmdev_ctx_t *ctx,
1672 lsm6dsrx_rounding_t *val)
1673 {
1674 lsm6dsrx_ctrl5_c_t ctrl5_c;
1675 int32_t ret;
1676
1677 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C,
1678 (uint8_t *)&ctrl5_c, 1);
1679
1680 switch (ctrl5_c.rounding)
1681 {
1682 case LSM6DSRX_NO_ROUND:
1683 *val = LSM6DSRX_NO_ROUND;
1684 break;
1685
1686 case LSM6DSRX_ROUND_XL:
1687 *val = LSM6DSRX_ROUND_XL;
1688 break;
1689
1690 case LSM6DSRX_ROUND_GY:
1691 *val = LSM6DSRX_ROUND_GY;
1692 break;
1693
1694 case LSM6DSRX_ROUND_GY_XL:
1695 *val = LSM6DSRX_ROUND_GY_XL;
1696 break;
1697
1698 default:
1699 *val = LSM6DSRX_NO_ROUND;
1700 break;
1701 }
1702
1703 return ret;
1704 }
1705
1706 /**
1707 * @brief Temperature data output register (r).
1708 * L and H registers together express a 16-bit word in two's
1709 * complement.[get]
1710 *
1711 * @param ctx Read / write interface definitions.(ptr)
1712 * @param buff Buffer that stores data read
1713 * @retval Interface status (MANDATORY: return 0 -> no Error).
1714 *
1715 */
lsm6dsrx_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1716 int32_t lsm6dsrx_temperature_raw_get(const stmdev_ctx_t *ctx,
1717 int16_t *val)
1718 {
1719 uint8_t buff[2];
1720 int32_t ret;
1721
1722 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_OUT_TEMP_L, buff, 2);
1723 *val = (int16_t)buff[1];
1724 *val = (*val * 256) + (int16_t)buff[0];
1725
1726 return ret;
1727 }
1728
1729 /**
1730 * @brief Angular rate sensor. The value is expressed as a 16-bit
1731 * word in two's complement.[get]
1732 *
1733 * @param ctx Read / write interface definitions.(ptr)
1734 * @param buff Buffer that stores data read
1735 * @retval Interface status (MANDATORY: return 0 -> no Error).
1736 *
1737 */
lsm6dsrx_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1738 int32_t lsm6dsrx_angular_rate_raw_get(const stmdev_ctx_t *ctx,
1739 int16_t *val)
1740 {
1741 uint8_t buff[6];
1742 int32_t ret;
1743
1744 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_OUTX_L_G, buff, 6);
1745 val[0] = (int16_t)buff[1];
1746 val[0] = (val[0] * 256) + (int16_t)buff[0];
1747 val[1] = (int16_t)buff[3];
1748 val[1] = (val[1] * 256) + (int16_t)buff[2];
1749 val[2] = (int16_t)buff[5];
1750 val[2] = (val[2] * 256) + (int16_t)buff[4];
1751
1752 return ret;
1753 }
1754
1755 /**
1756 * @brief Linear acceleration output register. The value is expressed as a
1757 * 16-bit word in two's complement.[get]
1758 *
1759 * @param ctx Read / write interface definitions.(ptr)
1760 * @param buff Buffer that stores data read
1761 * @retval Interface status (MANDATORY: return 0 -> no Error).
1762 *
1763 */
lsm6dsrx_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1764 int32_t lsm6dsrx_acceleration_raw_get(const stmdev_ctx_t *ctx,
1765 int16_t *val)
1766 {
1767 uint8_t buff[6];
1768 int32_t ret;
1769
1770 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_OUTX_L_A, buff, 6);
1771 val[0] = (int16_t)buff[1];
1772 val[0] = (val[0] * 256) + (int16_t)buff[0];
1773 val[1] = (int16_t)buff[3];
1774 val[1] = (val[1] * 256) + (int16_t)buff[2];
1775 val[2] = (int16_t)buff[5];
1776 val[2] = (val[2] * 256) + (int16_t)buff[4];
1777
1778 return ret;
1779 }
1780
1781 /**
1782 * @brief FIFO data output.[get]
1783 *
1784 * @param ctx Read / write interface definitions.(ptr)
1785 * @param buff Buffer that stores data read
1786 * @retval Interface status (MANDATORY: return 0 -> no Error).
1787 *
1788 */
lsm6dsrx_fifo_out_raw_get(const stmdev_ctx_t * ctx,uint8_t * buff)1789 int32_t lsm6dsrx_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1790 {
1791 int32_t ret;
1792
1793 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_DATA_OUT_X_L, buff, 6);
1794
1795 return ret;
1796 }
1797
1798 /**
1799 * @brief Step counter output register.[get]
1800 *
1801 * @param ctx Read / write interface definitions.(ptr)
1802 * @param buff Buffer that stores data read
1803 * @retval Interface status (MANDATORY: return 0 -> no Error).
1804 *
1805 */
lsm6dsrx_number_of_steps_get(const stmdev_ctx_t * ctx,uint16_t * val)1806 int32_t lsm6dsrx_number_of_steps_get(const stmdev_ctx_t *ctx,
1807 uint16_t *val)
1808 {
1809 uint8_t buff[2];
1810 int32_t ret;
1811
1812 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
1813
1814 if (ret == 0)
1815 {
1816 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STEP_COUNTER_L, buff, 2);
1817 *val = buff[1];
1818 *val = (*val * 256U) + buff[0];
1819 }
1820
1821 if (ret == 0)
1822 {
1823 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
1824 }
1825
1826 return ret;
1827 }
1828
1829 /**
1830 * @brief Reset step counter register.[get]
1831 *
1832 * @param ctx Read / write interface definitions.(ptr)
1833 * @retval Interface status (MANDATORY: return 0 -> no Error).
1834 *
1835 */
lsm6dsrx_steps_reset(const stmdev_ctx_t * ctx)1836 int32_t lsm6dsrx_steps_reset(const stmdev_ctx_t *ctx)
1837 {
1838 lsm6dsrx_emb_func_src_t emb_func_src;
1839 int32_t ret;
1840
1841 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
1842
1843 if (ret == 0)
1844 {
1845 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_SRC,
1846 (uint8_t *)&emb_func_src, 1);
1847 }
1848
1849 if (ret == 0)
1850 {
1851 emb_func_src.pedo_rst_step = PROPERTY_ENABLE;
1852 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_SRC,
1853 (uint8_t *)&emb_func_src, 1);
1854 }
1855
1856 if (ret == 0)
1857 {
1858 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
1859 }
1860
1861 return ret;
1862 }
1863
1864 /**
1865 * @}
1866 *
1867 */
1868
1869 /**
1870 * @defgroup LSM6DSRX_common
1871 * @brief This section groups common useful functions.
1872 * @{
1873 *
1874 */
1875
1876 /**
1877 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1878 * with respect to the typical.[set]
1879 * Step: 0.15%. 8-bit format, 2's complement.
1880 *
1881 * @param ctx Read / write interface definitions.(ptr)
1882 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1883 * @retval Interface status (MANDATORY: return 0 -> no Error).
1884 *
1885 */
lsm6dsrx_odr_cal_reg_set(const stmdev_ctx_t * ctx,uint8_t val)1886 int32_t lsm6dsrx_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val)
1887 {
1888 lsm6dsrx_internal_freq_fine_t internal_freq_fine;
1889 int32_t ret;
1890
1891 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INTERNAL_FREQ_FINE,
1892 (uint8_t *)&internal_freq_fine, 1);
1893
1894 if (ret == 0)
1895 {
1896 internal_freq_fine.freq_fine = (uint8_t)val;
1897 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INTERNAL_FREQ_FINE,
1898 (uint8_t *)&internal_freq_fine, 1);
1899 }
1900
1901 return ret;
1902 }
1903
1904 /**
1905 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1906 * with respect to the typical.[get]
1907 * Step: 0.15%. 8-bit format, 2's complement.
1908 *
1909 * @param ctx Read / write interface definitions.(ptr)
1910 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1911 * @retval Interface status (MANDATORY: return 0 -> no Error).
1912 *
1913 */
lsm6dsrx_odr_cal_reg_get(const stmdev_ctx_t * ctx,uint8_t * val)1914 int32_t lsm6dsrx_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val)
1915 {
1916 lsm6dsrx_internal_freq_fine_t internal_freq_fine;
1917 int32_t ret;
1918
1919 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INTERNAL_FREQ_FINE,
1920 (uint8_t *)&internal_freq_fine, 1);
1921 *val = internal_freq_fine.freq_fine;
1922
1923 return ret;
1924 }
1925
1926 /**
1927 * @brief Enable access to the embedded functions/sensor hub configuration
1928 * registers.[set]
1929 *
1930 * @param ctx Read / write interface definitions.(ptr)
1931 * @param val Change the values of reg_access in reg FUNC_CFG_ACCESS
1932 * @retval Interface status (MANDATORY: return 0 -> no Error).
1933 *
1934 */
lsm6dsrx_mem_bank_set(const stmdev_ctx_t * ctx,lsm6dsrx_reg_access_t val)1935 int32_t lsm6dsrx_mem_bank_set(const stmdev_ctx_t *ctx,
1936 lsm6dsrx_reg_access_t val)
1937 {
1938 lsm6dsrx_func_cfg_access_t func_cfg_access;
1939 int32_t ret;
1940
1941 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FUNC_CFG_ACCESS,
1942 (uint8_t *)&func_cfg_access, 1);
1943
1944 if (ret == 0)
1945 {
1946 func_cfg_access.reg_access = (uint8_t)val;
1947 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FUNC_CFG_ACCESS,
1948 (uint8_t *)&func_cfg_access, 1);
1949 }
1950
1951 return ret;
1952 }
1953
1954 /**
1955 * @brief Enable access to the embedded functions/sensor hub configuration
1956 * registers.[get]
1957 *
1958 * @param ctx Read / write interface definitions.(ptr)
1959 * @param val Get the values of reg_access in reg FUNC_CFG_ACCESS
1960 * @retval Interface status (MANDATORY: return 0 -> no Error).
1961 *
1962 */
lsm6dsrx_mem_bank_get(const stmdev_ctx_t * ctx,lsm6dsrx_reg_access_t * val)1963 int32_t lsm6dsrx_mem_bank_get(const stmdev_ctx_t *ctx,
1964 lsm6dsrx_reg_access_t *val)
1965 {
1966 lsm6dsrx_func_cfg_access_t func_cfg_access;
1967 int32_t ret;
1968
1969 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FUNC_CFG_ACCESS,
1970 (uint8_t *)&func_cfg_access, 1);
1971
1972 switch (func_cfg_access.reg_access)
1973 {
1974 case LSM6DSRX_USER_BANK:
1975 *val = LSM6DSRX_USER_BANK;
1976 break;
1977
1978 case LSM6DSRX_SENSOR_HUB_BANK:
1979 *val = LSM6DSRX_SENSOR_HUB_BANK;
1980 break;
1981
1982 case LSM6DSRX_EMBEDDED_FUNC_BANK:
1983 *val = LSM6DSRX_EMBEDDED_FUNC_BANK;
1984 break;
1985
1986 default:
1987 *val = LSM6DSRX_USER_BANK;
1988 break;
1989 }
1990
1991 return ret;
1992 }
1993
1994 /**
1995 * @brief Write a line(byte) in a page.[set]
1996 *
1997 * @param ctx Read / write interface definitions.(ptr)
1998 * @param add Page line address
1999 * @param val Value to write
2000 * @retval Interface status (MANDATORY: return 0 -> no Error).
2001 *
2002 */
lsm6dsrx_ln_pg_write_byte(const stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)2003 int32_t lsm6dsrx_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t add,
2004 uint8_t *val)
2005 {
2006 lsm6dsrx_page_rw_t page_rw;
2007 lsm6dsrx_page_sel_t page_sel;
2008 lsm6dsrx_page_address_t page_address;
2009 int32_t ret;
2010
2011 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
2012
2013 if (ret == 0)
2014 {
2015 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW,
2016 (uint8_t *)&page_rw, 1);
2017 }
2018
2019 if (ret == 0)
2020 {
2021 page_rw.page_rw = 0x02U; /* page_write enable */
2022 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW,
2023 (uint8_t *)&page_rw, 1);
2024 }
2025
2026 if (ret == 0)
2027 {
2028 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL,
2029 (uint8_t *)&page_sel, 1);
2030 }
2031
2032 if (ret == 0)
2033 {
2034 page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
2035 page_sel.not_used_01 = 1;
2036 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL,
2037 (uint8_t *)&page_sel, 1);
2038 }
2039
2040 if (ret == 0)
2041 {
2042 page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
2043 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_ADDRESS,
2044 (uint8_t *)&page_address, 1);
2045 }
2046
2047 if (ret == 0)
2048 {
2049 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_VALUE, val, 1);
2050 }
2051
2052 if (ret == 0)
2053 {
2054 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW,
2055 (uint8_t *)&page_rw, 1);
2056 }
2057
2058 if (ret == 0)
2059 {
2060 page_rw.page_rw = 0x00; /* page_write disable */
2061 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW,
2062 (uint8_t *)&page_rw, 1);
2063 }
2064
2065 if (ret == 0)
2066 {
2067 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
2068 }
2069
2070 return ret;
2071 }
2072
2073 /**
2074 * @brief Write buffer in a page.[set]
2075 *
2076 * @param ctx Read / write interface definitions.(ptr)
2077 * @param buf Page line address.(ptr)
2078 * @param val Value to write.
2079 * @param len buffer length.
2080 * @retval Interface status (MANDATORY: return 0 -> no Error).
2081 *
2082 */
lsm6dsrx_ln_pg_write(const stmdev_ctx_t * ctx,uint16_t add,uint8_t * buf,uint8_t len)2083 int32_t lsm6dsrx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t add,
2084 uint8_t *buf, uint8_t len)
2085 {
2086 lsm6dsrx_page_rw_t page_rw;
2087 lsm6dsrx_page_sel_t page_sel;
2088 lsm6dsrx_page_address_t page_address;
2089 uint8_t msb;
2090 uint8_t lsb;
2091 int32_t ret;
2092 uint8_t i ;
2093
2094 msb = (uint8_t)((add / 256U) & 0x0FU);
2095 lsb = (uint8_t)(add - (msb * 256U));
2096 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
2097
2098 if (ret == 0)
2099 {
2100 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW,
2101 (uint8_t *)&page_rw, 1);
2102 }
2103
2104 if (ret == 0)
2105 {
2106 page_rw.page_rw = 0x02U; /* page_write enable*/
2107 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW,
2108 (uint8_t *)&page_rw, 1);
2109 }
2110
2111 if (ret == 0)
2112 {
2113 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL,
2114 (uint8_t *)&page_sel, 1);
2115 }
2116
2117 if (ret == 0)
2118 {
2119 page_sel.page_sel = msb;
2120 page_sel.not_used_01 = 1;
2121 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL,
2122 (uint8_t *)&page_sel, 1);
2123 }
2124
2125 if (ret == 0)
2126 {
2127 page_address.page_addr = lsb;
2128 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_ADDRESS,
2129 (uint8_t *)&page_address, 1);
2130 }
2131
2132 for (i = 0; i < len; i++)
2133 {
2134 if (ret == 0)
2135 {
2136 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_VALUE, &buf[i], 1);
2137
2138 if (ret == 0)
2139 {
2140 /* Check if page wrap */
2141 if (lsb == 0x00U)
2142 {
2143 msb++;
2144 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL,
2145 (uint8_t *)&page_sel, 1);
2146 }
2147
2148 lsb++;
2149 }
2150
2151 if (ret == 0)
2152 {
2153 page_sel.page_sel = msb;
2154 page_sel.not_used_01 = 1;
2155 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL,
2156 (uint8_t *)&page_sel, 1);
2157 }
2158 }
2159 }
2160
2161 if (ret == 0)
2162 {
2163 page_sel.page_sel = 0;
2164 page_sel.not_used_01 = 1;
2165 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL,
2166 (uint8_t *)&page_sel, 1);
2167 }
2168
2169 if (ret == 0)
2170 {
2171 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW,
2172 (uint8_t *)&page_rw, 1);
2173 }
2174
2175 if (ret == 0)
2176 {
2177 page_rw.page_rw = 0x00U; /* page_write disable */
2178 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW,
2179 (uint8_t *)&page_rw, 1);
2180 }
2181
2182 if (ret == 0)
2183 {
2184 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
2185 }
2186
2187 return ret;
2188 }
2189
2190 /**
2191 * @brief Read a line(byte) in a page.[get]
2192 *
2193 * @param ctx Read / write interface definitions.(ptr)
2194 * @param add Page line address.
2195 * @param val Read value.(ptr)
2196 * @retval Interface status (MANDATORY: return 0 -> no Error).
2197 *
2198 */
lsm6dsrx_ln_pg_read_byte(const stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)2199 int32_t lsm6dsrx_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t add,
2200 uint8_t *val)
2201 {
2202 lsm6dsrx_page_rw_t page_rw;
2203 lsm6dsrx_page_sel_t page_sel;
2204 lsm6dsrx_page_address_t page_address;
2205 int32_t ret;
2206
2207 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
2208
2209 if (ret == 0)
2210 {
2211 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW,
2212 (uint8_t *)&page_rw, 1);
2213 }
2214
2215 if (ret == 0)
2216 {
2217 page_rw.page_rw = 0x01U; /* page_read enable*/
2218 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW,
2219 (uint8_t *)&page_rw, 1);
2220 }
2221
2222 if (ret == 0)
2223 {
2224 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL,
2225 (uint8_t *)&page_sel, 1);
2226 }
2227
2228 if (ret == 0)
2229 {
2230 page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
2231 page_sel.not_used_01 = 1;
2232 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL,
2233 (uint8_t *)&page_sel, 1);
2234 }
2235
2236 if (ret == 0)
2237 {
2238 page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
2239 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_ADDRESS,
2240 (uint8_t *)&page_address, 1);
2241 }
2242
2243 if (ret == 0)
2244 {
2245 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_VALUE, val, 2);
2246 }
2247
2248 if (ret == 0)
2249 {
2250 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW,
2251 (uint8_t *)&page_rw, 1);
2252 }
2253
2254 if (ret == 0)
2255 {
2256 page_rw.page_rw = 0x00U; /* page_read disable */
2257 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW,
2258 (uint8_t *)&page_rw, 1);
2259 }
2260
2261 if (ret == 0)
2262 {
2263 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
2264 }
2265
2266 return ret;
2267 }
2268
2269 /**
2270 * @brief Data-ready pulsed / letched mode.[set]
2271 *
2272 * @param ctx Read / write interface definitions.(ptr)
2273 * @param val Change the values of dataready_pulsed in
2274 * reg COUNTER_BDR_REG1
2275 * @retval Interface status (MANDATORY: return 0 -> no Error).
2276 *
2277 */
lsm6dsrx_data_ready_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_dataready_pulsed_t val)2278 int32_t lsm6dsrx_data_ready_mode_set(const stmdev_ctx_t *ctx,
2279 lsm6dsrx_dataready_pulsed_t val)
2280 {
2281 lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
2282 int32_t ret;
2283
2284 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
2285 (uint8_t *)&counter_bdr_reg1, 1);
2286
2287 if (ret == 0)
2288 {
2289 counter_bdr_reg1.dataready_pulsed = (uint8_t)val;
2290 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
2291 (uint8_t *)&counter_bdr_reg1, 1);
2292 }
2293
2294 return ret;
2295 }
2296
2297 /**
2298 * @brief Data-ready pulsed / letched mode.[get]
2299 *
2300 * @param ctx Read / write interface definitions.(ptr)
2301 * @param val Get the values of dataready_pulsed in
2302 * reg COUNTER_BDR_REG1
2303 * @retval Interface status (MANDATORY: return 0 -> no Error).
2304 *
2305 */
lsm6dsrx_data_ready_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_dataready_pulsed_t * val)2306 int32_t lsm6dsrx_data_ready_mode_get(const stmdev_ctx_t *ctx,
2307 lsm6dsrx_dataready_pulsed_t *val)
2308 {
2309 lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
2310 int32_t ret;
2311
2312 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
2313 (uint8_t *)&counter_bdr_reg1, 1);
2314
2315 switch (counter_bdr_reg1.dataready_pulsed)
2316 {
2317 case LSM6DSRX_DRDY_LATCHED:
2318 *val = LSM6DSRX_DRDY_LATCHED;
2319 break;
2320
2321 case LSM6DSRX_DRDY_PULSED:
2322 *val = LSM6DSRX_DRDY_PULSED;
2323 break;
2324
2325 default:
2326 *val = LSM6DSRX_DRDY_LATCHED;
2327 break;
2328 }
2329
2330 return ret;
2331 }
2332
2333 /**
2334 * @brief Device Who am I.[get]
2335 *
2336 * @param ctx Read / write interface definitions.(ptr)
2337 * @param buff Buffer that stores data read
2338 * @retval Interface status (MANDATORY: return 0 -> no Error).
2339 *
2340 */
lsm6dsrx_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)2341 int32_t lsm6dsrx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
2342 {
2343 int32_t ret;
2344
2345 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WHO_AM_I, buff, 1);
2346
2347 return ret;
2348 }
2349
2350 /**
2351 * @brief Software reset. Restore the default values in user registers.[set]
2352 *
2353 * @param ctx Read / write interface definitions.(ptr)
2354 * @param val Change the values of sw_reset in reg CTRL3_C
2355 * @retval Interface status (MANDATORY: return 0 -> no Error).
2356 *
2357 */
lsm6dsrx_reset_set(const stmdev_ctx_t * ctx,uint8_t val)2358 int32_t lsm6dsrx_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
2359 {
2360 lsm6dsrx_ctrl3_c_t ctrl3_c;
2361 int32_t ret;
2362
2363 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C,
2364 (uint8_t *)&ctrl3_c, 1);
2365
2366 if (ret == 0)
2367 {
2368 ctrl3_c.sw_reset = (uint8_t)val;
2369 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C,
2370 (uint8_t *)&ctrl3_c, 1);
2371 }
2372
2373 return ret;
2374 }
2375
2376 /**
2377 * @brief Software reset. Restore the default values in user registers.[get]
2378 *
2379 * @param ctx Read / write interface definitions.(ptr)
2380 * @param val Change the values of sw_reset in reg CTRL3_C
2381 * @retval Interface status (MANDATORY: return 0 -> no Error).
2382 *
2383 */
lsm6dsrx_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)2384 int32_t lsm6dsrx_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
2385 {
2386 lsm6dsrx_ctrl3_c_t ctrl3_c;
2387 int32_t ret;
2388
2389 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C,
2390 (uint8_t *)&ctrl3_c, 1);
2391 *val = ctrl3_c.sw_reset;
2392
2393 return ret;
2394 }
2395
2396 /**
2397 * @brief Register address automatically incremented during a multiple byte
2398 * access with a serial interface.[set]
2399 *
2400 * @param ctx Read / write interface definitions.(ptr)
2401 * @param val Change the values of if_inc in reg CTRL3_C
2402 * @retval Interface status (MANDATORY: return 0 -> no Error).
2403 *
2404 */
lsm6dsrx_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)2405 int32_t lsm6dsrx_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
2406 {
2407 lsm6dsrx_ctrl3_c_t ctrl3_c;
2408 int32_t ret;
2409
2410 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C,
2411 (uint8_t *)&ctrl3_c, 1);
2412
2413 if (ret == 0)
2414 {
2415 ctrl3_c.if_inc = (uint8_t)val;
2416 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C,
2417 (uint8_t *)&ctrl3_c, 1);
2418 }
2419
2420 return ret;
2421 }
2422
2423 /**
2424 * @brief Register address automatically incremented during a multiple byte
2425 * access with a serial interface.[get]
2426 *
2427 * @param ctx Read / write interface definitions.(ptr)
2428 * @param val Change the values of if_inc in reg CTRL3_C
2429 * @retval Interface status (MANDATORY: return 0 -> no Error).
2430 *
2431 */
lsm6dsrx_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)2432 int32_t lsm6dsrx_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
2433 {
2434 lsm6dsrx_ctrl3_c_t ctrl3_c;
2435 int32_t ret;
2436
2437 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C,
2438 (uint8_t *)&ctrl3_c, 1);
2439 *val = ctrl3_c.if_inc;
2440
2441 return ret;
2442 }
2443
2444 /**
2445 * @brief Reboot memory content. Reload the calibration parameters.[set]
2446 *
2447 * @param ctx Read / write interface definitions.(ptr)
2448 * @param val Change the values of boot in reg CTRL3_C
2449 * @retval Interface status (MANDATORY: return 0 -> no Error).
2450 *
2451 */
lsm6dsrx_boot_set(const stmdev_ctx_t * ctx,uint8_t val)2452 int32_t lsm6dsrx_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
2453 {
2454 lsm6dsrx_ctrl3_c_t ctrl3_c;
2455 int32_t ret;
2456
2457 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C,
2458 (uint8_t *)&ctrl3_c, 1);
2459
2460 if (ret == 0)
2461 {
2462 ctrl3_c.boot = (uint8_t)val;
2463 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C,
2464 (uint8_t *)&ctrl3_c, 1);
2465 }
2466
2467 return ret;
2468 }
2469
2470 /**
2471 * @brief Reboot memory content. Reload the calibration parameters.[get]
2472 *
2473 * @param ctx Read / write interface definitions.(ptr)
2474 * @param val Change the values of boot in reg CTRL3_C
2475 * @retval Interface status (MANDATORY: return 0 -> no Error).
2476 *
2477 */
lsm6dsrx_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)2478 int32_t lsm6dsrx_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
2479 {
2480 lsm6dsrx_ctrl3_c_t ctrl3_c;
2481 int32_t ret;
2482
2483 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C,
2484 (uint8_t *)&ctrl3_c, 1);
2485 *val = ctrl3_c.boot;
2486
2487 return ret;
2488 }
2489
2490
2491
2492 /**
2493 * @brief Linear acceleration sensor self-test enable.[set]
2494 *
2495 * @param ctx Read / write interface definitions.(ptr)
2496 * @param val Change the values of st_xl in reg CTRL5_C
2497 * @retval Interface status (MANDATORY: return 0 -> no Error).
2498 *
2499 */
lsm6dsrx_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6dsrx_st_xl_t val)2500 int32_t lsm6dsrx_xl_self_test_set(const stmdev_ctx_t *ctx,
2501 lsm6dsrx_st_xl_t val)
2502 {
2503 lsm6dsrx_ctrl5_c_t ctrl5_c;
2504 int32_t ret;
2505
2506 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C,
2507 (uint8_t *)&ctrl5_c, 1);
2508
2509 if (ret == 0)
2510 {
2511 ctrl5_c.st_xl = (uint8_t)val;
2512 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL5_C,
2513 (uint8_t *)&ctrl5_c, 1);
2514 }
2515
2516 return ret;
2517 }
2518
2519 /**
2520 * @brief Linear acceleration sensor self-test enable.[get]
2521 *
2522 * @param ctx Read / write interface definitions.(ptr)
2523 * @param val Get the values of st_xl in reg CTRL5_C
2524 * @retval Interface status (MANDATORY: return 0 -> no Error).
2525 *
2526 */
lsm6dsrx_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6dsrx_st_xl_t * val)2527 int32_t lsm6dsrx_xl_self_test_get(const stmdev_ctx_t *ctx,
2528 lsm6dsrx_st_xl_t *val)
2529 {
2530 lsm6dsrx_ctrl5_c_t ctrl5_c;
2531 int32_t ret;
2532
2533 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C,
2534 (uint8_t *)&ctrl5_c, 1);
2535
2536 switch (ctrl5_c.st_xl)
2537 {
2538 case LSM6DSRX_XL_ST_DISABLE:
2539 *val = LSM6DSRX_XL_ST_DISABLE;
2540 break;
2541
2542 case LSM6DSRX_XL_ST_POSITIVE:
2543 *val = LSM6DSRX_XL_ST_POSITIVE;
2544 break;
2545
2546 case LSM6DSRX_XL_ST_NEGATIVE:
2547 *val = LSM6DSRX_XL_ST_NEGATIVE;
2548 break;
2549
2550 default:
2551 *val = LSM6DSRX_XL_ST_DISABLE;
2552 break;
2553 }
2554
2555 return ret;
2556 }
2557
2558 /**
2559 * @brief Angular rate sensor self-test enable.[set]
2560 *
2561 * @param ctx Read / write interface definitions.(ptr)
2562 * @param val Change the values of st_g in reg CTRL5_C
2563 * @retval Interface status (MANDATORY: return 0 -> no Error).
2564 *
2565 */
lsm6dsrx_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dsrx_st_g_t val)2566 int32_t lsm6dsrx_gy_self_test_set(const stmdev_ctx_t *ctx,
2567 lsm6dsrx_st_g_t val)
2568 {
2569 lsm6dsrx_ctrl5_c_t ctrl5_c;
2570 int32_t ret;
2571
2572 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C,
2573 (uint8_t *)&ctrl5_c, 1);
2574
2575 if (ret == 0)
2576 {
2577 ctrl5_c.st_g = (uint8_t)val;
2578 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL5_C,
2579 (uint8_t *)&ctrl5_c, 1);
2580 }
2581
2582 return ret;
2583 }
2584
2585 /**
2586 * @brief Angular rate sensor self-test enable.[get]
2587 *
2588 * @param ctx Read / write interface definitions.(ptr)
2589 * @param val Get the values of st_g in reg CTRL5_C
2590 * @retval Interface status (MANDATORY: return 0 -> no Error).
2591 *
2592 */
lsm6dsrx_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dsrx_st_g_t * val)2593 int32_t lsm6dsrx_gy_self_test_get(const stmdev_ctx_t *ctx,
2594 lsm6dsrx_st_g_t *val)
2595 {
2596 lsm6dsrx_ctrl5_c_t ctrl5_c;
2597 int32_t ret;
2598
2599 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C,
2600 (uint8_t *)&ctrl5_c, 1);
2601
2602 switch (ctrl5_c.st_g)
2603 {
2604 case LSM6DSRX_GY_ST_DISABLE:
2605 *val = LSM6DSRX_GY_ST_DISABLE;
2606 break;
2607
2608 case LSM6DSRX_GY_ST_POSITIVE:
2609 *val = LSM6DSRX_GY_ST_POSITIVE;
2610 break;
2611
2612 case LSM6DSRX_GY_ST_NEGATIVE:
2613 *val = LSM6DSRX_GY_ST_NEGATIVE;
2614 break;
2615
2616 default:
2617 *val = LSM6DSRX_GY_ST_DISABLE;
2618 break;
2619 }
2620
2621 return ret;
2622 }
2623
2624 /**
2625 * @}
2626 *
2627 */
2628
2629 /**
2630 * @defgroup LSM6DSRX_filters
2631 * @brief This section group all the functions concerning the
2632 * filters configuration
2633 * @{
2634 *
2635 */
2636
2637 /**
2638 * @brief Accelerometer output from LPF2 filtering stage selection.[set]
2639 *
2640 * @param ctx Read / write interface definitions.(ptr)
2641 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
2642 * @retval Interface status (MANDATORY: return 0 -> no Error).
2643 *
2644 */
lsm6dsrx_xl_filter_lp2_set(const stmdev_ctx_t * ctx,uint8_t val)2645 int32_t lsm6dsrx_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val)
2646 {
2647 lsm6dsrx_ctrl1_xl_t ctrl1_xl;
2648 int32_t ret;
2649
2650 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL,
2651 (uint8_t *)&ctrl1_xl, 1);
2652
2653 if (ret == 0)
2654 {
2655 ctrl1_xl.lpf2_xl_en = (uint8_t)val;
2656 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_XL,
2657 (uint8_t *)&ctrl1_xl, 1);
2658 }
2659
2660 return ret;
2661 }
2662
2663 /**
2664 * @brief Accelerometer output from LPF2 filtering stage selection.[get]
2665 *
2666 * @param ctx Read / write interface definitions.(ptr)
2667 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
2668 * @retval Interface status (MANDATORY: return 0 -> no Error).
2669 *
2670 */
lsm6dsrx_xl_filter_lp2_get(const stmdev_ctx_t * ctx,uint8_t * val)2671 int32_t lsm6dsrx_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val)
2672 {
2673 lsm6dsrx_ctrl1_xl_t ctrl1_xl;
2674 int32_t ret;
2675
2676 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL,
2677 (uint8_t *)&ctrl1_xl, 1);
2678 *val = ctrl1_xl.lpf2_xl_en;
2679
2680 return ret;
2681 }
2682
2683 /**
2684 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2685 * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[set]
2686 *
2687 * @param ctx Read / write interface definitions.(ptr)
2688 * @param val Change the values of lpf1_sel_g in reg CTRL4_C
2689 * @retval Interface status (MANDATORY: return 0 -> no Error).
2690 *
2691 */
lsm6dsrx_gy_filter_lp1_set(const stmdev_ctx_t * ctx,uint8_t val)2692 int32_t lsm6dsrx_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val)
2693 {
2694 lsm6dsrx_ctrl4_c_t ctrl4_c;
2695 int32_t ret;
2696
2697 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C,
2698 (uint8_t *)&ctrl4_c, 1);
2699
2700 if (ret == 0)
2701 {
2702 ctrl4_c.lpf1_sel_g = (uint8_t)val;
2703 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C,
2704 (uint8_t *)&ctrl4_c, 1);
2705 }
2706
2707 return ret;
2708 }
2709
2710 /**
2711 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2712 * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[get]
2713 *
2714 * @param ctx Read / write interface definitions.(ptr)
2715 * @param val Change the values of lpf1_sel_g in reg CTRL4_C
2716 * @retval Interface status (MANDATORY: return 0 -> no Error).
2717 *
2718 */
lsm6dsrx_gy_filter_lp1_get(const stmdev_ctx_t * ctx,uint8_t * val)2719 int32_t lsm6dsrx_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val)
2720 {
2721 lsm6dsrx_ctrl4_c_t ctrl4_c;
2722 int32_t ret;
2723
2724 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C,
2725 (uint8_t *)&ctrl4_c, 1);
2726 *val = ctrl4_c.lpf1_sel_g;
2727
2728 return ret;
2729 }
2730
2731 /**
2732 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2733 * (XL and Gyro independently masked).[set]
2734 *
2735 * @param ctx Read / write interface definitions.(ptr)
2736 * @param val Change the values of drdy_mask in reg CTRL4_C
2737 * @retval Interface status (MANDATORY: return 0 -> no Error).
2738 *
2739 */
lsm6dsrx_filter_settling_mask_set(const stmdev_ctx_t * ctx,uint8_t val)2740 int32_t lsm6dsrx_filter_settling_mask_set(const stmdev_ctx_t *ctx,
2741 uint8_t val)
2742 {
2743 lsm6dsrx_ctrl4_c_t ctrl4_c;
2744 int32_t ret;
2745
2746 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C,
2747 (uint8_t *)&ctrl4_c, 1);
2748
2749 if (ret == 0)
2750 {
2751 ctrl4_c.drdy_mask = (uint8_t)val;
2752 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C,
2753 (uint8_t *)&ctrl4_c, 1);
2754 }
2755
2756 return ret;
2757 }
2758
2759 /**
2760 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2761 * (XL and Gyro independently masked).[get]
2762 *
2763 * @param ctx Read / write interface definitions.(ptr)
2764 * @param val Change the values of drdy_mask in reg CTRL4_C
2765 * @retval Interface status (MANDATORY: return 0 -> no Error).
2766 *
2767 */
lsm6dsrx_filter_settling_mask_get(const stmdev_ctx_t * ctx,uint8_t * val)2768 int32_t lsm6dsrx_filter_settling_mask_get(const stmdev_ctx_t *ctx,
2769 uint8_t *val)
2770 {
2771 lsm6dsrx_ctrl4_c_t ctrl4_c;
2772 int32_t ret;
2773
2774 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C,
2775 (uint8_t *)&ctrl4_c, 1);
2776 *val = ctrl4_c.drdy_mask;
2777
2778 return ret;
2779 }
2780
2781 /**
2782 * @brief Gyroscope low pass filter 1 bandwidth.[set]
2783 *
2784 * @param ctx Read / write interface definitions.(ptr)
2785 * @param val Change the values of ftype in reg CTRL6_C
2786 * @retval Interface status (MANDATORY: return 0 -> no Error).
2787 *
2788 */
lsm6dsrx_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsrx_ftype_t val)2789 int32_t lsm6dsrx_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
2790 lsm6dsrx_ftype_t val)
2791 {
2792 lsm6dsrx_ctrl6_c_t ctrl6_c;
2793 int32_t ret;
2794
2795 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C,
2796 (uint8_t *)&ctrl6_c, 1);
2797
2798 if (ret == 0)
2799 {
2800 ctrl6_c.ftype = (uint8_t)val;
2801 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL6_C,
2802 (uint8_t *)&ctrl6_c, 1);
2803 }
2804
2805 return ret;
2806 }
2807
2808 /**
2809 * @brief Gyroscope low pass filter 1 bandwidth.[get]
2810 *
2811 * @param ctx Read / write interface definitions.(ptr)
2812 * @param val Get the values of ftype in reg CTRL6_C
2813 * @retval Interface status (MANDATORY: return 0 -> no Error).
2814 *
2815 */
lsm6dsrx_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsrx_ftype_t * val)2816 int32_t lsm6dsrx_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
2817 lsm6dsrx_ftype_t *val)
2818 {
2819 lsm6dsrx_ctrl6_c_t ctrl6_c;
2820 int32_t ret;
2821
2822 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C,
2823 (uint8_t *)&ctrl6_c, 1);
2824
2825 switch (ctrl6_c.ftype)
2826 {
2827 case LSM6DSRX_ULTRA_LIGHT:
2828 *val = LSM6DSRX_ULTRA_LIGHT;
2829 break;
2830
2831 case LSM6DSRX_VERY_LIGHT:
2832 *val = LSM6DSRX_VERY_LIGHT;
2833 break;
2834
2835 case LSM6DSRX_LIGHT:
2836 *val = LSM6DSRX_LIGHT;
2837 break;
2838
2839 case LSM6DSRX_MEDIUM:
2840 *val = LSM6DSRX_MEDIUM;
2841 break;
2842
2843 case LSM6DSRX_STRONG:
2844 *val = LSM6DSRX_STRONG;
2845 break;
2846
2847 case LSM6DSRX_VERY_STRONG:
2848 *val = LSM6DSRX_VERY_STRONG;
2849 break;
2850
2851 case LSM6DSRX_AGGRESSIVE:
2852 *val = LSM6DSRX_AGGRESSIVE;
2853 break;
2854
2855 case LSM6DSRX_XTREME:
2856 *val = LSM6DSRX_XTREME;
2857 break;
2858
2859 default:
2860 *val = LSM6DSRX_ULTRA_LIGHT;
2861 break;
2862 }
2863
2864 return ret;
2865 }
2866
2867 /**
2868 * @brief Low pass filter 2 on 6D function selection.[set]
2869 *
2870 * @param ctx Read / write interface definitions.(ptr)
2871 * @param val Change the values of low_pass_on_6d in reg CTRL8_XL
2872 * @retval Interface status (MANDATORY: return 0 -> no Error).
2873 *
2874 */
lsm6dsrx_xl_lp2_on_6d_set(const stmdev_ctx_t * ctx,uint8_t val)2875 int32_t lsm6dsrx_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val)
2876 {
2877 lsm6dsrx_ctrl8_xl_t ctrl8_xl;
2878 int32_t ret;
2879
2880 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL,
2881 (uint8_t *)&ctrl8_xl, 1);
2882
2883 if (ret == 0)
2884 {
2885 ctrl8_xl.low_pass_on_6d = (uint8_t)val;
2886 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL8_XL,
2887 (uint8_t *)&ctrl8_xl, 1);
2888 }
2889
2890 return ret;
2891 }
2892
2893 /**
2894 * @brief Low pass filter 2 on 6D function selection.[get]
2895 *
2896 * @param ctx Read / write interface definitions.(ptr)
2897 * @param val Change the values of low_pass_on_6d in reg CTRL8_XL
2898 * @retval Interface status (MANDATORY: return 0 -> no Error).
2899 *
2900 */
lsm6dsrx_xl_lp2_on_6d_get(const stmdev_ctx_t * ctx,uint8_t * val)2901 int32_t lsm6dsrx_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val)
2902 {
2903 lsm6dsrx_ctrl8_xl_t ctrl8_xl;
2904 int32_t ret;
2905
2906 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL,
2907 (uint8_t *)&ctrl8_xl, 1);
2908 *val = ctrl8_xl.low_pass_on_6d;
2909
2910 return ret;
2911 }
2912
2913 /**
2914 * @brief Accelerometer slope filter / high-pass filter selection
2915 * on output.[set]
2916 *
2917 * @param ctx Read / write interface definitions.(ptr)
2918 * @param val Change the values of hp_slope_xl_en in reg CTRL8_XL
2919 * @retval Interface status (MANDATORY: return 0 -> no Error).
2920 *
2921 */
lsm6dsrx_xl_hp_path_on_out_set(const stmdev_ctx_t * ctx,lsm6dsrx_hp_slope_xl_en_t val)2922 int32_t lsm6dsrx_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx,
2923 lsm6dsrx_hp_slope_xl_en_t val)
2924 {
2925 lsm6dsrx_ctrl8_xl_t ctrl8_xl;
2926 int32_t ret;
2927
2928 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL,
2929 (uint8_t *)&ctrl8_xl, 1);
2930
2931 if (ret == 0)
2932 {
2933 ctrl8_xl.hp_slope_xl_en = (((uint8_t)val & 0x10U) >> 4);
2934 ctrl8_xl.hp_ref_mode_xl = (((uint8_t)val & 0x20U) >> 5);
2935 ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U;
2936 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL8_XL,
2937 (uint8_t *)&ctrl8_xl, 1);
2938 }
2939
2940 return ret;
2941 }
2942
2943 /**
2944 * @brief Accelerometer slope filter / high-pass filter selection on
2945 * output.[get]
2946 *
2947 * @param ctx Read / write interface definitions.(ptr)
2948 * @param val Get the values of hp_slope_xl_en in reg CTRL8_XL
2949 * @retval Interface status (MANDATORY: return 0 -> no Error).
2950 *
2951 */
lsm6dsrx_xl_hp_path_on_out_get(const stmdev_ctx_t * ctx,lsm6dsrx_hp_slope_xl_en_t * val)2952 int32_t lsm6dsrx_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx,
2953 lsm6dsrx_hp_slope_xl_en_t *val)
2954 {
2955 lsm6dsrx_ctrl8_xl_t ctrl8_xl;
2956 int32_t ret;
2957
2958 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL,
2959 (uint8_t *)&ctrl8_xl, 1);
2960
2961 switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en <<
2962 4) +
2963 ctrl8_xl.hpcf_xl))
2964 {
2965 case LSM6DSRX_HP_PATH_DISABLE_ON_OUT:
2966 *val = LSM6DSRX_HP_PATH_DISABLE_ON_OUT;
2967 break;
2968
2969 case LSM6DSRX_SLOPE_ODR_DIV_4:
2970 *val = LSM6DSRX_SLOPE_ODR_DIV_4;
2971 break;
2972
2973 case LSM6DSRX_HP_ODR_DIV_10:
2974 *val = LSM6DSRX_HP_ODR_DIV_10;
2975 break;
2976
2977 case LSM6DSRX_HP_ODR_DIV_20:
2978 *val = LSM6DSRX_HP_ODR_DIV_20;
2979 break;
2980
2981 case LSM6DSRX_HP_ODR_DIV_45:
2982 *val = LSM6DSRX_HP_ODR_DIV_45;
2983 break;
2984
2985 case LSM6DSRX_HP_ODR_DIV_100:
2986 *val = LSM6DSRX_HP_ODR_DIV_100;
2987 break;
2988
2989 case LSM6DSRX_HP_ODR_DIV_200:
2990 *val = LSM6DSRX_HP_ODR_DIV_200;
2991 break;
2992
2993 case LSM6DSRX_HP_ODR_DIV_400:
2994 *val = LSM6DSRX_HP_ODR_DIV_400;
2995 break;
2996
2997 case LSM6DSRX_HP_ODR_DIV_800:
2998 *val = LSM6DSRX_HP_ODR_DIV_800;
2999 break;
3000
3001 case LSM6DSRX_HP_REF_MD_ODR_DIV_10:
3002 *val = LSM6DSRX_HP_REF_MD_ODR_DIV_10;
3003 break;
3004
3005 case LSM6DSRX_HP_REF_MD_ODR_DIV_20:
3006 *val = LSM6DSRX_HP_REF_MD_ODR_DIV_20;
3007 break;
3008
3009 case LSM6DSRX_HP_REF_MD_ODR_DIV_45:
3010 *val = LSM6DSRX_HP_REF_MD_ODR_DIV_45;
3011 break;
3012
3013 case LSM6DSRX_HP_REF_MD_ODR_DIV_100:
3014 *val = LSM6DSRX_HP_REF_MD_ODR_DIV_100;
3015 break;
3016
3017 case LSM6DSRX_HP_REF_MD_ODR_DIV_200:
3018 *val = LSM6DSRX_HP_REF_MD_ODR_DIV_200;
3019 break;
3020
3021 case LSM6DSRX_HP_REF_MD_ODR_DIV_400:
3022 *val = LSM6DSRX_HP_REF_MD_ODR_DIV_400;
3023 break;
3024
3025 case LSM6DSRX_HP_REF_MD_ODR_DIV_800:
3026 *val = LSM6DSRX_HP_REF_MD_ODR_DIV_800;
3027 break;
3028
3029 case LSM6DSRX_LP_ODR_DIV_10:
3030 *val = LSM6DSRX_LP_ODR_DIV_10;
3031 break;
3032
3033 case LSM6DSRX_LP_ODR_DIV_20:
3034 *val = LSM6DSRX_LP_ODR_DIV_20;
3035 break;
3036
3037 case LSM6DSRX_LP_ODR_DIV_45:
3038 *val = LSM6DSRX_LP_ODR_DIV_45;
3039 break;
3040
3041 case LSM6DSRX_LP_ODR_DIV_100:
3042 *val = LSM6DSRX_LP_ODR_DIV_100;
3043 break;
3044
3045 case LSM6DSRX_LP_ODR_DIV_200:
3046 *val = LSM6DSRX_LP_ODR_DIV_200;
3047 break;
3048
3049 case LSM6DSRX_LP_ODR_DIV_400:
3050 *val = LSM6DSRX_LP_ODR_DIV_400;
3051 break;
3052
3053 case LSM6DSRX_LP_ODR_DIV_800:
3054 *val = LSM6DSRX_LP_ODR_DIV_800;
3055 break;
3056
3057 default:
3058 *val = LSM6DSRX_HP_PATH_DISABLE_ON_OUT;
3059 break;
3060 }
3061
3062 return ret;
3063 }
3064
3065 /**
3066 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
3067 * The filter sets the second samples after writing this bit.
3068 * Active only during device exit from powerdown mode.[set]
3069 *
3070 * @param ctx Read / write interface definitions.(ptr)
3071 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
3072 * @retval Interface status (MANDATORY: return 0 -> no Error).
3073 *
3074 */
lsm6dsrx_xl_fast_settling_set(const stmdev_ctx_t * ctx,uint8_t val)3075 int32_t lsm6dsrx_xl_fast_settling_set(const stmdev_ctx_t *ctx,
3076 uint8_t val)
3077 {
3078 lsm6dsrx_ctrl8_xl_t ctrl8_xl;
3079 int32_t ret;
3080
3081 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL,
3082 (uint8_t *)&ctrl8_xl, 1);
3083
3084 if (ret == 0)
3085 {
3086 ctrl8_xl.fastsettl_mode_xl = (uint8_t)val;
3087 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL8_XL,
3088 (uint8_t *)&ctrl8_xl, 1);
3089 }
3090
3091 return ret;
3092 }
3093
3094 /**
3095 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
3096 * The filter sets the second samples after writing
3097 * this bit. Active only during device exit from powerdown mode.[get]
3098 *
3099 * @param ctx Read / write interface definitions.(ptr)
3100 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
3101 * @retval Interface status (MANDATORY: return 0 -> no Error).
3102 *
3103 */
lsm6dsrx_xl_fast_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)3104 int32_t lsm6dsrx_xl_fast_settling_get(const stmdev_ctx_t *ctx,
3105 uint8_t *val)
3106 {
3107 lsm6dsrx_ctrl8_xl_t ctrl8_xl;
3108 int32_t ret;
3109
3110 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL,
3111 (uint8_t *)&ctrl8_xl, 1);
3112 *val = ctrl8_xl.fastsettl_mode_xl;
3113
3114 return ret;
3115 }
3116
3117 /**
3118 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
3119 * functions.[set]
3120 *
3121 * @param ctx Read / write interface definitions.(ptr)
3122 * @param val Change the values of slope_fds in reg TAP_CFG0
3123 * @retval Interface status (MANDATORY: return 0 -> no Error).
3124 *
3125 */
lsm6dsrx_xl_hp_path_internal_set(const stmdev_ctx_t * ctx,lsm6dsrx_slope_fds_t val)3126 int32_t lsm6dsrx_xl_hp_path_internal_set(const stmdev_ctx_t *ctx,
3127 lsm6dsrx_slope_fds_t val)
3128 {
3129 lsm6dsrx_tap_cfg0_t tap_cfg0;
3130 int32_t ret;
3131
3132 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0,
3133 (uint8_t *)&tap_cfg0, 1);
3134
3135 if (ret == 0)
3136 {
3137 tap_cfg0.slope_fds = (uint8_t)val;
3138 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG0,
3139 (uint8_t *)&tap_cfg0, 1);
3140 }
3141
3142 return ret;
3143 }
3144
3145 /**
3146 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
3147 * functions.[get]
3148 *
3149 * @param ctx Read / write interface definitions.(ptr)
3150 * @param val Get the values of slope_fds in reg TAP_CFG0
3151 * @retval Interface status (MANDATORY: return 0 -> no Error).
3152 *
3153 */
lsm6dsrx_xl_hp_path_internal_get(const stmdev_ctx_t * ctx,lsm6dsrx_slope_fds_t * val)3154 int32_t lsm6dsrx_xl_hp_path_internal_get(const stmdev_ctx_t *ctx,
3155 lsm6dsrx_slope_fds_t *val)
3156 {
3157 lsm6dsrx_tap_cfg0_t tap_cfg0;
3158 int32_t ret;
3159
3160 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0,
3161 (uint8_t *)&tap_cfg0, 1);
3162
3163 switch (tap_cfg0.slope_fds)
3164 {
3165 case LSM6DSRX_USE_SLOPE:
3166 *val = LSM6DSRX_USE_SLOPE;
3167 break;
3168
3169 case LSM6DSRX_USE_HPF:
3170 *val = LSM6DSRX_USE_HPF;
3171 break;
3172
3173 default:
3174 *val = LSM6DSRX_USE_SLOPE;
3175 break;
3176 }
3177
3178 return ret;
3179 }
3180
3181 /**
3182 * @brief Enables gyroscope digital high-pass filter. The filter is enabled
3183 * only if the gyro is in HP mode.[set]
3184 *
3185 * @param ctx Read / write interface definitions.(ptr)
3186 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
3187 * @retval Interface status (MANDATORY: return 0 -> no Error).
3188 *
3189 */
lsm6dsrx_gy_hp_path_internal_set(const stmdev_ctx_t * ctx,lsm6dsrx_hpm_g_t val)3190 int32_t lsm6dsrx_gy_hp_path_internal_set(const stmdev_ctx_t *ctx,
3191 lsm6dsrx_hpm_g_t val)
3192 {
3193 lsm6dsrx_ctrl7_g_t ctrl7_g;
3194 int32_t ret;
3195
3196 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G,
3197 (uint8_t *)&ctrl7_g, 1);
3198
3199 if (ret == 0)
3200 {
3201 ctrl7_g.hp_en_g = (((uint8_t)val & 0x80U) >> 7);
3202 ctrl7_g.hpm_g = (uint8_t)val & 0x03U;
3203 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL7_G,
3204 (uint8_t *)&ctrl7_g, 1);
3205 }
3206
3207 return ret;
3208 }
3209
3210 /**
3211 * @brief Enables gyroscope digital high-pass filter. The filter is
3212 * enabled only if the gyro is in HP mode.[get]
3213 *
3214 * @param ctx Read / write interface definitions.(ptr)
3215 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
3216 * @retval Interface status (MANDATORY: return 0 -> no Error).
3217 *
3218 */
lsm6dsrx_gy_hp_path_internal_get(const stmdev_ctx_t * ctx,lsm6dsrx_hpm_g_t * val)3219 int32_t lsm6dsrx_gy_hp_path_internal_get(const stmdev_ctx_t *ctx,
3220 lsm6dsrx_hpm_g_t *val)
3221 {
3222 lsm6dsrx_ctrl7_g_t ctrl7_g;
3223 int32_t ret;
3224
3225 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G,
3226 (uint8_t *)&ctrl7_g, 1);
3227
3228 switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g)
3229 {
3230 case LSM6DSRX_HP_FILTER_NONE:
3231 *val = LSM6DSRX_HP_FILTER_NONE;
3232 break;
3233
3234 case LSM6DSRX_HP_FILTER_16mHz:
3235 *val = LSM6DSRX_HP_FILTER_16mHz;
3236 break;
3237
3238 case LSM6DSRX_HP_FILTER_65mHz:
3239 *val = LSM6DSRX_HP_FILTER_65mHz;
3240 break;
3241
3242 case LSM6DSRX_HP_FILTER_260mHz:
3243 *val = LSM6DSRX_HP_FILTER_260mHz;
3244 break;
3245
3246 case LSM6DSRX_HP_FILTER_1Hz04:
3247 *val = LSM6DSRX_HP_FILTER_1Hz04;
3248 break;
3249
3250 default:
3251 *val = LSM6DSRX_HP_FILTER_NONE;
3252 break;
3253 }
3254
3255 return ret;
3256 }
3257
3258 /**
3259 * @}
3260 *
3261 */
3262
3263 /**
3264 * @defgroup LSM6DSRX_ Auxiliary_interface
3265 * @brief This section groups all the functions concerning
3266 * auxiliary interface.
3267 * @{
3268 *
3269 */
3270
3271 /**
3272 * @brief On auxiliary interface connect/disconnect SDO and OCS
3273 * internal pull-up.[set]
3274 *
3275 * @param ctx Read / write interface definitions.(ptr)
3276 * @param val Change the values of ois_pu_dis in reg PIN_CTRL
3277 * @retval Interface status (MANDATORY: return 0 -> no Error).
3278 *
3279 */
lsm6dsrx_aux_sdo_ocs_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_ois_pu_dis_t val)3280 int32_t lsm6dsrx_aux_sdo_ocs_mode_set(const stmdev_ctx_t *ctx,
3281 lsm6dsrx_ois_pu_dis_t val)
3282 {
3283 lsm6dsrx_pin_ctrl_t pin_ctrl;
3284 int32_t ret;
3285
3286 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PIN_CTRL,
3287 (uint8_t *)&pin_ctrl, 1);
3288
3289 if (ret == 0)
3290 {
3291 pin_ctrl.ois_pu_dis = (uint8_t)val;
3292 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PIN_CTRL,
3293 (uint8_t *)&pin_ctrl, 1);
3294 }
3295
3296 return ret;
3297 }
3298
3299 /**
3300 * @brief On auxiliary interface connect/disconnect SDO and OCS
3301 * internal pull-up.[get]
3302 *
3303 * @param ctx Read / write interface definitions.(ptr)
3304 * @param val Get the values of ois_pu_dis in reg PIN_CTRL
3305 * @retval Interface status (MANDATORY: return 0 -> no Error).
3306 *
3307 */
lsm6dsrx_aux_sdo_ocs_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_ois_pu_dis_t * val)3308 int32_t lsm6dsrx_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx,
3309 lsm6dsrx_ois_pu_dis_t *val)
3310 {
3311 lsm6dsrx_pin_ctrl_t pin_ctrl;
3312 int32_t ret;
3313
3314 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PIN_CTRL,
3315 (uint8_t *)&pin_ctrl, 1);
3316
3317 switch (pin_ctrl.ois_pu_dis)
3318 {
3319 case LSM6DSRX_AUX_PULL_UP_DISC:
3320 *val = LSM6DSRX_AUX_PULL_UP_DISC;
3321 break;
3322
3323 case LSM6DSRX_AUX_PULL_UP_CONNECT:
3324 *val = LSM6DSRX_AUX_PULL_UP_CONNECT;
3325 break;
3326
3327 default:
3328 *val = LSM6DSRX_AUX_PULL_UP_DISC;
3329 break;
3330 }
3331
3332 return ret;
3333 }
3334
3335 /**
3336 * @brief OIS chain on aux interface power on mode.[set]
3337 *
3338 * @param ctx Read / write interface definitions.(ptr)
3339 * @param val Change the values of ois_on in reg CTRL7_G
3340 * @retval Interface status (MANDATORY: return 0 -> no Error).
3341 *
3342 */
lsm6dsrx_aux_pw_on_ctrl_set(const stmdev_ctx_t * ctx,lsm6dsrx_ois_on_t val)3343 int32_t lsm6dsrx_aux_pw_on_ctrl_set(const stmdev_ctx_t *ctx,
3344 lsm6dsrx_ois_on_t val)
3345 {
3346 lsm6dsrx_ctrl7_g_t ctrl7_g;
3347 int32_t ret;
3348
3349 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G,
3350 (uint8_t *)&ctrl7_g, 1);
3351
3352 if (ret == 0)
3353 {
3354 ctrl7_g.ois_on_en = (uint8_t)val & 0x01U;
3355 ctrl7_g.ois_on = (uint8_t)val & 0x01U;
3356 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL7_G,
3357 (uint8_t *)&ctrl7_g, 1);
3358 }
3359
3360 return ret;
3361 }
3362
3363 /**
3364 * @brief OIS chain on aux interface power on mode[get]
3365 *
3366 * @param ctx Read / write interface definitions.(ptr)
3367 * @param val Get the values of ois_on in reg CTRL7_G
3368 * @retval Interface status (MANDATORY: return 0 -> no Error).
3369 *
3370 */
lsm6dsrx_aux_pw_on_ctrl_get(const stmdev_ctx_t * ctx,lsm6dsrx_ois_on_t * val)3371 int32_t lsm6dsrx_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx,
3372 lsm6dsrx_ois_on_t *val)
3373 {
3374 lsm6dsrx_ctrl7_g_t ctrl7_g;
3375 int32_t ret;
3376
3377 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G,
3378 (uint8_t *)&ctrl7_g, 1);
3379
3380 switch (ctrl7_g.ois_on)
3381 {
3382 case LSM6DSRX_AUX_ON:
3383 *val = LSM6DSRX_AUX_ON;
3384 break;
3385
3386 case LSM6DSRX_AUX_ON_BY_AUX_INTERFACE:
3387 *val = LSM6DSRX_AUX_ON_BY_AUX_INTERFACE;
3388 break;
3389
3390 default:
3391 *val = LSM6DSRX_AUX_ON;
3392 break;
3393 }
3394
3395 return ret;
3396 }
3397
3398 /**
3399 * @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get]
3400 *
3401 * @param ctx Read / write interface definitions.(ptr)
3402 * @param lsm6dsrx_status_spiaux_t: registers STATUS_SPIAUX
3403 * @retval Interface status (MANDATORY: return 0 -> no Error).
3404 *
3405 */
lsm6dsrx_aux_status_reg_get(const stmdev_ctx_t * ctx,lsm6dsrx_status_spiaux_t * val)3406 int32_t lsm6dsrx_aux_status_reg_get(const stmdev_ctx_t *ctx,
3407 lsm6dsrx_status_spiaux_t *val)
3408 {
3409 int32_t ret;
3410
3411 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_SPIAUX,
3412 (uint8_t *)val, 1);
3413
3414 return ret;
3415 }
3416
3417 /**
3418 * @brief AUX accelerometer data available.[get]
3419 *
3420 * @param ctx Read / write interface definitions.(ptr)
3421 * @param val Change the values of xlda in reg STATUS_SPIAUX
3422 * @retval Interface status (MANDATORY: return 0 -> no Error).
3423 *
3424 */
lsm6dsrx_aux_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)3425 int32_t lsm6dsrx_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
3426 uint8_t *val)
3427 {
3428 lsm6dsrx_status_spiaux_t status_spiaux;
3429 int32_t ret;
3430
3431 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_SPIAUX,
3432 (uint8_t *)&status_spiaux, 1);
3433 *val = status_spiaux.xlda;
3434
3435 return ret;
3436 }
3437
3438 /**
3439 * @brief AUX gyroscope data available.[get]
3440 *
3441 * @param ctx Read / write interface definitions.(ptr)
3442 * @param val Change the values of gda in reg STATUS_SPIAUX
3443 * @retval Interface status (MANDATORY: return 0 -> no Error).
3444 *
3445 */
lsm6dsrx_aux_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)3446 int32_t lsm6dsrx_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx,
3447 uint8_t *val)
3448 {
3449 lsm6dsrx_status_spiaux_t status_spiaux;
3450 int32_t ret;
3451
3452 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_SPIAUX,
3453 (uint8_t *)&status_spiaux, 1);
3454 *val = status_spiaux.gda;
3455
3456 return ret;
3457 }
3458
3459 /**
3460 * @brief High when the gyroscope output is in the settling phase.[get]
3461 *
3462 * @param ctx Read / write interface definitions.(ptr)
3463 * @param val Change the values of gyro_settling in reg STATUS_SPIAUX
3464 * @retval Interface status (MANDATORY: return 0 -> no Error).
3465 *
3466 */
lsm6dsrx_aux_gy_flag_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)3467 int32_t lsm6dsrx_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx,
3468 uint8_t *val)
3469 {
3470 lsm6dsrx_status_spiaux_t status_spiaux;
3471 int32_t ret;
3472
3473 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_SPIAUX,
3474 (uint8_t *)&status_spiaux, 1);
3475 *val = status_spiaux.gyro_settling;
3476
3477 return ret;
3478 }
3479
3480 /**
3481 * @brief Selects accelerometer self-test. Effective only if XL OIS chain is
3482 * enabled.[set]
3483 *
3484 * @param ctx Read / write interface definitions.(ptr)
3485 * @param val Change the values of st_xl_ois in reg INT_OIS
3486 * @retval Interface status (MANDATORY: return 0 -> no Error).
3487 *
3488 */
lsm6dsrx_aux_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6dsrx_st_xl_ois_t val)3489 int32_t lsm6dsrx_aux_xl_self_test_set(const stmdev_ctx_t *ctx,
3490 lsm6dsrx_st_xl_ois_t val)
3491 {
3492 lsm6dsrx_int_ois_t int_ois;
3493 int32_t ret;
3494
3495 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS,
3496 (uint8_t *)&int_ois, 1);
3497
3498 if (ret == 0)
3499 {
3500 int_ois.st_xl_ois = (uint8_t)val;
3501 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_OIS,
3502 (uint8_t *)&int_ois, 1);
3503 }
3504
3505 return ret;
3506 }
3507
3508 /**
3509 * @brief Selects accelerometer self-test. Effective only if XL OIS chain
3510 * is enabled.[get]
3511 *
3512 * @param ctx Read / write interface definitions.(ptr)
3513 * @param val Get the values of st_xl_ois in reg INT_OIS
3514 * @retval Interface status (MANDATORY: return 0 -> no Error).
3515 *
3516 */
lsm6dsrx_aux_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6dsrx_st_xl_ois_t * val)3517 int32_t lsm6dsrx_aux_xl_self_test_get(const stmdev_ctx_t *ctx,
3518 lsm6dsrx_st_xl_ois_t *val)
3519 {
3520 lsm6dsrx_int_ois_t int_ois;
3521 int32_t ret;
3522
3523 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS,
3524 (uint8_t *)&int_ois, 1);
3525
3526 switch (int_ois.st_xl_ois)
3527 {
3528 case LSM6DSRX_AUX_XL_DISABLE:
3529 *val = LSM6DSRX_AUX_XL_DISABLE;
3530 break;
3531
3532 case LSM6DSRX_AUX_XL_POS:
3533 *val = LSM6DSRX_AUX_XL_POS;
3534 break;
3535
3536 case LSM6DSRX_AUX_XL_NEG:
3537 *val = LSM6DSRX_AUX_XL_NEG;
3538 break;
3539
3540 default:
3541 *val = LSM6DSRX_AUX_XL_DISABLE;
3542 break;
3543 }
3544
3545 return ret;
3546 }
3547
3548 /**
3549 * @brief Indicates polarity of DEN signal on OIS chain.[set]
3550 *
3551 * @param ctx Read / write interface definitions.(ptr)
3552 * @param val Change the values of den_lh_ois in reg INT_OIS
3553 * @retval Interface status (MANDATORY: return 0 -> no Error).
3554 *
3555 */
lsm6dsrx_aux_den_polarity_set(const stmdev_ctx_t * ctx,lsm6dsrx_den_lh_ois_t val)3556 int32_t lsm6dsrx_aux_den_polarity_set(const stmdev_ctx_t *ctx,
3557 lsm6dsrx_den_lh_ois_t val)
3558 {
3559 lsm6dsrx_int_ois_t int_ois;
3560 int32_t ret;
3561
3562 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS,
3563 (uint8_t *)&int_ois, 1);
3564
3565 if (ret == 0)
3566 {
3567 int_ois.den_lh_ois = (uint8_t)val;
3568 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_OIS,
3569 (uint8_t *)&int_ois, 1);
3570 }
3571
3572 return ret;
3573 }
3574
3575 /**
3576 * @brief Indicates polarity of DEN signal on OIS chain.[get]
3577 *
3578 * @param ctx Read / write interface definitions.(ptr)
3579 * @param val Get the values of den_lh_ois in reg INT_OIS
3580 * @retval Interface status (MANDATORY: return 0 -> no Error).
3581 *
3582 */
lsm6dsrx_aux_den_polarity_get(const stmdev_ctx_t * ctx,lsm6dsrx_den_lh_ois_t * val)3583 int32_t lsm6dsrx_aux_den_polarity_get(const stmdev_ctx_t *ctx,
3584 lsm6dsrx_den_lh_ois_t *val)
3585 {
3586 lsm6dsrx_int_ois_t int_ois;
3587 int32_t ret;
3588
3589 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS,
3590 (uint8_t *)&int_ois, 1);
3591
3592 switch (int_ois.den_lh_ois)
3593 {
3594 case LSM6DSRX_AUX_DEN_ACTIVE_LOW:
3595 *val = LSM6DSRX_AUX_DEN_ACTIVE_LOW;
3596 break;
3597
3598 case LSM6DSRX_AUX_DEN_ACTIVE_HIGH:
3599 *val = LSM6DSRX_AUX_DEN_ACTIVE_HIGH;
3600 break;
3601
3602 default:
3603 *val = LSM6DSRX_AUX_DEN_ACTIVE_LOW;
3604 break;
3605 }
3606
3607 return ret;
3608 }
3609
3610 /**
3611 * @brief Configure DEN mode on the OIS chain.[set]
3612 *
3613 * @param ctx Read / write interface definitions.(ptr)
3614 * @param val Change the values of lvl2_ois in reg INT_OIS
3615 * @retval Interface status (MANDATORY: return 0 -> no Error).
3616 *
3617 */
lsm6dsrx_aux_den_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_lvl2_ois_t val)3618 int32_t lsm6dsrx_aux_den_mode_set(const stmdev_ctx_t *ctx,
3619 lsm6dsrx_lvl2_ois_t val)
3620 {
3621 lsm6dsrx_int_ois_t int_ois;
3622 lsm6dsrx_ctrl1_ois_t ctrl1_ois;
3623 int32_t ret;
3624
3625 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS,
3626 (uint8_t *)&int_ois, 1);
3627
3628 if (ret == 0)
3629 {
3630 int_ois.lvl2_ois = (uint8_t)val & 0x01U;
3631 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_OIS,
3632 (uint8_t *)&int_ois, 1);
3633 }
3634
3635 if (ret == 0)
3636 {
3637 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
3638 (uint8_t *)&ctrl1_ois, 1);
3639 }
3640
3641 if (ret == 0)
3642 {
3643 ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
3644 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_OIS,
3645 (uint8_t *)&ctrl1_ois, 1);
3646 }
3647
3648 return ret;
3649 }
3650
3651 /**
3652 * @brief Configure DEN mode on the OIS chain.[get]
3653 *
3654 * @param ctx Read / write interface definitions.(ptr)
3655 * @param val Get the values of lvl2_ois in reg INT_OIS
3656 * @retval Interface status (MANDATORY: return 0 -> no Error).
3657 *
3658 */
lsm6dsrx_aux_den_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_lvl2_ois_t * val)3659 int32_t lsm6dsrx_aux_den_mode_get(const stmdev_ctx_t *ctx,
3660 lsm6dsrx_lvl2_ois_t *val)
3661 {
3662 lsm6dsrx_int_ois_t int_ois;
3663 lsm6dsrx_ctrl1_ois_t ctrl1_ois;
3664 int32_t ret;
3665
3666 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS,
3667 (uint8_t *)&int_ois, 1);
3668
3669 if (ret == 0)
3670 {
3671 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
3672 (uint8_t *)&ctrl1_ois, 1);
3673 }
3674
3675 switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois)
3676 {
3677 case LSM6DSRX_AUX_DEN_DISABLE:
3678 *val = LSM6DSRX_AUX_DEN_DISABLE;
3679 break;
3680
3681 case LSM6DSRX_AUX_DEN_LEVEL_LATCH:
3682 *val = LSM6DSRX_AUX_DEN_LEVEL_LATCH;
3683 break;
3684
3685 case LSM6DSRX_AUX_DEN_LEVEL_TRIG:
3686 *val = LSM6DSRX_AUX_DEN_LEVEL_TRIG;
3687 break;
3688
3689 default:
3690 *val = LSM6DSRX_AUX_DEN_DISABLE;
3691 break;
3692 }
3693
3694 return ret;
3695 }
3696
3697 /**
3698 * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting has
3699 * priority over all other INT2 settings.[set]
3700 *
3701 * @param ctx Read / write interface definitions.(ptr)
3702 * @param val Change the values of int2_drdy_ois in reg INT_OIS
3703 * @retval Interface status (MANDATORY: return 0 -> no Error).
3704 *
3705 */
lsm6dsrx_aux_drdy_on_int2_set(const stmdev_ctx_t * ctx,uint8_t val)3706 int32_t lsm6dsrx_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx,
3707 uint8_t val)
3708 {
3709 lsm6dsrx_int_ois_t int_ois;
3710 int32_t ret;
3711
3712 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS,
3713 (uint8_t *)&int_ois, 1);
3714
3715 if (ret == 0)
3716 {
3717 int_ois.int2_drdy_ois = (uint8_t)val;
3718 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_OIS,
3719 (uint8_t *)&int_ois, 1);
3720 }
3721
3722 return ret;
3723 }
3724
3725 /**
3726 * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting has
3727 * priority over all other INT2 settings.[get]
3728 *
3729 * @param ctx Read / write interface definitions.(ptr)
3730 * @param val Change the values of int2_drdy_ois in reg INT_OIS
3731 * @retval Interface status (MANDATORY: return 0 -> no Error).
3732 *
3733 */
lsm6dsrx_aux_drdy_on_int2_get(const stmdev_ctx_t * ctx,uint8_t * val)3734 int32_t lsm6dsrx_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx,
3735 uint8_t *val)
3736 {
3737 lsm6dsrx_int_ois_t int_ois;
3738 int32_t ret;
3739
3740 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS,
3741 (uint8_t *)&int_ois, 1);
3742 *val = int_ois.int2_drdy_ois;
3743
3744 return ret;
3745 }
3746
3747 /**
3748 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
3749 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
3750 * When the OIS chain is enabled, the OIS outputs are available
3751 * through the SPI2 in registers OUTX_L_G (22h) through OUTZ_H_G(27h)
3752 * and STATUS_REG (1Eh) / STATUS_SPIAux, and LPF1 is dedicated to
3753 * this chain.[set]
3754 *
3755 * @param ctx Read / write interface definitions.(ptr)
3756 * @param val Change the values of ois_en_spi2 in reg CTRL1_OIS
3757 * @retval Interface status (MANDATORY: return 0 -> no Error).
3758 *
3759 */
lsm6dsrx_aux_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_ois_en_spi2_t val)3760 int32_t lsm6dsrx_aux_mode_set(const stmdev_ctx_t *ctx,
3761 lsm6dsrx_ois_en_spi2_t val)
3762 {
3763 lsm6dsrx_ctrl1_ois_t ctrl1_ois;
3764 int32_t ret;
3765
3766 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
3767 (uint8_t *)&ctrl1_ois, 1);
3768
3769 if (ret == 0)
3770 {
3771 ctrl1_ois.ois_en_spi2 = (uint8_t)val & 0x01U;
3772 ctrl1_ois.mode4_en = ((uint8_t)val & 0x02U) >> 1;
3773 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_OIS,
3774 (uint8_t *)&ctrl1_ois, 1);
3775 }
3776
3777 return ret;
3778 }
3779
3780 /**
3781 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
3782 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
3783 * When the OIS chain is enabled, the OIS outputs are available
3784 * through the SPI2 in registers OUTX_L_G (22h) through OUTZ_H_G(27h)
3785 * and STATUS_REG (1Eh) / STATUS_SPIAux, and LPF1 is dedicated to
3786 * this chain.[get]
3787 *
3788 * @param ctx Read / write interface definitions.(ptr)
3789 * @param val Get the values of ois_en_spi2 in
3790 * reg CTRL1_OIS
3791 * @retval Interface status (MANDATORY: return 0 -> no Error).
3792 *
3793 */
lsm6dsrx_aux_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_ois_en_spi2_t * val)3794 int32_t lsm6dsrx_aux_mode_get(const stmdev_ctx_t *ctx,
3795 lsm6dsrx_ois_en_spi2_t *val)
3796 {
3797 lsm6dsrx_ctrl1_ois_t ctrl1_ois;
3798 int32_t ret;
3799
3800 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
3801 (uint8_t *)&ctrl1_ois, 1);
3802
3803 switch (((ctrl1_ois.mode4_en << 1) + ctrl1_ois.ois_en_spi2))
3804 {
3805 case LSM6DSRX_AUX_DISABLE:
3806 *val = LSM6DSRX_AUX_DISABLE;
3807 break;
3808
3809 case LSM6DSRX_MODE_3_GY:
3810 *val = LSM6DSRX_MODE_3_GY;
3811 break;
3812
3813 case LSM6DSRX_MODE_4_GY_XL:
3814 *val = LSM6DSRX_MODE_4_GY_XL;
3815 break;
3816
3817 default:
3818 *val = LSM6DSRX_AUX_DISABLE;
3819 break;
3820 }
3821
3822 return ret;
3823 }
3824
3825 /**
3826 * @brief Selects gyroscope OIS chain full-scale.[set]
3827 *
3828 * @param ctx Read / write interface definitions.(ptr)
3829 * @param val Change the values of fs_g_ois in reg CTRL1_OIS
3830 * @retval Interface status (MANDATORY: return 0 -> no Error).
3831 *
3832 */
lsm6dsrx_aux_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsrx_fs_g_ois_t val)3833 int32_t lsm6dsrx_aux_gy_full_scale_set(const stmdev_ctx_t *ctx,
3834 lsm6dsrx_fs_g_ois_t val)
3835 {
3836 lsm6dsrx_ctrl1_ois_t ctrl1_ois;
3837 int32_t ret;
3838
3839 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
3840 (uint8_t *)&ctrl1_ois, 1);
3841
3842 if (ret == 0)
3843 {
3844 ctrl1_ois.fs_g_ois = (uint8_t)val & 0x03U;
3845 ctrl1_ois.fs_125_ois = ((uint8_t)val & 0x04U) >> 2;
3846 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_OIS,
3847 (uint8_t *)&ctrl1_ois, 1);
3848 }
3849
3850 return ret;
3851 }
3852
3853 /**
3854 * @brief Selects gyroscope OIS chain full-scale.[get]
3855 *
3856 * @param ctx Read / write interface definitions.(ptr)
3857 * @param val Get the values of fs_g_ois in reg CTRL1_OIS
3858 * @retval Interface status (MANDATORY: return 0 -> no Error).
3859 *
3860 */
lsm6dsrx_aux_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsrx_fs_g_ois_t * val)3861 int32_t lsm6dsrx_aux_gy_full_scale_get(const stmdev_ctx_t *ctx,
3862 lsm6dsrx_fs_g_ois_t *val)
3863 {
3864 lsm6dsrx_ctrl1_ois_t ctrl1_ois;
3865 int32_t ret;
3866
3867 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
3868 (uint8_t *)&ctrl1_ois, 1);
3869
3870 switch ((ctrl1_ois.fs_125_ois << 2) + ctrl1_ois.fs_g_ois)
3871 {
3872 case LSM6DSRX_250dps_AUX:
3873 *val = LSM6DSRX_250dps_AUX;
3874 break;
3875
3876 case LSM6DSRX_125dps_AUX:
3877 *val = LSM6DSRX_125dps_AUX;
3878 break;
3879
3880 case LSM6DSRX_500dps_AUX:
3881 *val = LSM6DSRX_500dps_AUX;
3882 break;
3883
3884 case LSM6DSRX_1000dps_AUX:
3885 *val = LSM6DSRX_1000dps_AUX;
3886 break;
3887
3888 case LSM6DSRX_2000dps_AUX:
3889 *val = LSM6DSRX_2000dps_AUX;
3890 break;
3891
3892 default:
3893 *val = LSM6DSRX_250dps_AUX;
3894 break;
3895 }
3896
3897 return ret;
3898 }
3899
3900 /**
3901 * @brief SPI2 3- or 4-wire interface.[set]
3902 *
3903 * @param ctx Read / write interface definitions.(ptr)
3904 * @param val Change the values of sim_ois in reg CTRL1_OIS
3905 * @retval Interface status (MANDATORY: return 0 -> no Error).
3906 *
3907 */
lsm6dsrx_aux_spi_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_sim_ois_t val)3908 int32_t lsm6dsrx_aux_spi_mode_set(const stmdev_ctx_t *ctx,
3909 lsm6dsrx_sim_ois_t val)
3910 {
3911 lsm6dsrx_ctrl1_ois_t ctrl1_ois;
3912 int32_t ret;
3913
3914 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
3915 (uint8_t *)&ctrl1_ois, 1);
3916
3917 if (ret == 0)
3918 {
3919 ctrl1_ois.sim_ois = (uint8_t)val;
3920 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_OIS,
3921 (uint8_t *)&ctrl1_ois, 1);
3922 }
3923
3924 return ret;
3925 }
3926
3927 /**
3928 * @brief SPI2 3- or 4-wire interface.[get]
3929 *
3930 * @param ctx Read / write interface definitions.(ptr)
3931 * @param val Get the values of sim_ois in reg CTRL1_OIS
3932 * @retval Interface status (MANDATORY: return 0 -> no Error).
3933 *
3934 */
lsm6dsrx_aux_spi_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_sim_ois_t * val)3935 int32_t lsm6dsrx_aux_spi_mode_get(const stmdev_ctx_t *ctx,
3936 lsm6dsrx_sim_ois_t *val)
3937 {
3938 lsm6dsrx_ctrl1_ois_t ctrl1_ois;
3939 int32_t ret;
3940
3941 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
3942 (uint8_t *)&ctrl1_ois, 1);
3943
3944 switch (ctrl1_ois.sim_ois)
3945 {
3946 case LSM6DSRX_AUX_SPI_4_WIRE:
3947 *val = LSM6DSRX_AUX_SPI_4_WIRE;
3948 break;
3949
3950 case LSM6DSRX_AUX_SPI_3_WIRE:
3951 *val = LSM6DSRX_AUX_SPI_3_WIRE;
3952 break;
3953
3954 default:
3955 *val = LSM6DSRX_AUX_SPI_4_WIRE;
3956 break;
3957 }
3958
3959 return ret;
3960 }
3961
3962 /**
3963 * @brief Selects gyroscope digital LPF1 filter bandwidth.[set]
3964 *
3965 * @param ctx Read / write interface definitions.(ptr)
3966 * @param val Change the values of ftype_ois in reg CTRL2_OIS
3967 * @retval Interface status (MANDATORY: return 0 -> no Error).
3968 *
3969 */
lsm6dsrx_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsrx_ftype_ois_t val)3970 int32_t lsm6dsrx_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
3971 lsm6dsrx_ftype_ois_t val)
3972 {
3973 lsm6dsrx_ctrl2_ois_t ctrl2_ois;
3974 int32_t ret;
3975
3976 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_OIS,
3977 (uint8_t *)&ctrl2_ois, 1);
3978
3979 if (ret == 0)
3980 {
3981 ctrl2_ois.ftype_ois = (uint8_t)val;
3982 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL2_OIS,
3983 (uint8_t *)&ctrl2_ois, 1);
3984 }
3985
3986 return ret;
3987 }
3988
3989 /**
3990 * @brief Selects gyroscope digital LPF1 filter bandwidth.[get]
3991 *
3992 * @param ctx Read / write interface definitions.(ptr)
3993 * @param val Get the values of ftype_ois in reg CTRL2_OIS
3994 * @retval Interface status (MANDATORY: return 0 -> no Error).
3995 *
3996 */
lsm6dsrx_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsrx_ftype_ois_t * val)3997 int32_t lsm6dsrx_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
3998 lsm6dsrx_ftype_ois_t *val)
3999 {
4000 lsm6dsrx_ctrl2_ois_t ctrl2_ois;
4001 int32_t ret;
4002
4003 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_OIS,
4004 (uint8_t *)&ctrl2_ois, 1);
4005
4006 switch (ctrl2_ois.ftype_ois)
4007 {
4008 case LSM6DSRX_351Hz39:
4009 *val = LSM6DSRX_351Hz39;
4010 break;
4011
4012 case LSM6DSRX_236Hz63:
4013 *val = LSM6DSRX_236Hz63;
4014 break;
4015
4016 case LSM6DSRX_172Hz70:
4017 *val = LSM6DSRX_172Hz70;
4018 break;
4019
4020 case LSM6DSRX_937Hz91:
4021 *val = LSM6DSRX_937Hz91;
4022 break;
4023
4024 default:
4025 *val = LSM6DSRX_351Hz39;
4026 break;
4027 }
4028
4029 return ret;
4030 }
4031
4032 /**
4033 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[set]
4034 *
4035 * @param ctx Read / write interface definitions.(ptr)
4036 * @param val Change the values of hpm_ois in reg CTRL2_OIS
4037 * @retval Interface status (MANDATORY: return 0 -> no Error).
4038 *
4039 */
lsm6dsrx_aux_gy_hp_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsrx_hpm_ois_t val)4040 int32_t lsm6dsrx_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx,
4041 lsm6dsrx_hpm_ois_t val)
4042 {
4043 lsm6dsrx_ctrl2_ois_t ctrl2_ois;
4044 int32_t ret;
4045
4046 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_OIS,
4047 (uint8_t *)&ctrl2_ois, 1);
4048
4049 if (ret == 0)
4050 {
4051 ctrl2_ois.hpm_ois = (uint8_t)val & 0x03U;
4052 ctrl2_ois.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
4053 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL2_OIS,
4054 (uint8_t *)&ctrl2_ois, 1);
4055 }
4056
4057 return ret;
4058 }
4059
4060 /**
4061 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[get]
4062 *
4063 * @param ctx Read / write interface definitions.(ptr)
4064 * @param val Get the values of hpm_ois in reg CTRL2_OIS
4065 * @retval Interface status (MANDATORY: return 0 -> no Error).
4066 *
4067 */
lsm6dsrx_aux_gy_hp_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsrx_hpm_ois_t * val)4068 int32_t lsm6dsrx_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx,
4069 lsm6dsrx_hpm_ois_t *val)
4070 {
4071 lsm6dsrx_ctrl2_ois_t ctrl2_ois;
4072 int32_t ret;
4073
4074 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_OIS,
4075 (uint8_t *)&ctrl2_ois, 1);
4076
4077 switch ((ctrl2_ois.hp_en_ois << 4) + ctrl2_ois.hpm_ois)
4078 {
4079 case LSM6DSRX_AUX_HP_DISABLE:
4080 *val = LSM6DSRX_AUX_HP_DISABLE;
4081 break;
4082
4083 case LSM6DSRX_AUX_HP_Hz016:
4084 *val = LSM6DSRX_AUX_HP_Hz016;
4085 break;
4086
4087 case LSM6DSRX_AUX_HP_Hz065:
4088 *val = LSM6DSRX_AUX_HP_Hz065;
4089 break;
4090
4091 case LSM6DSRX_AUX_HP_Hz260:
4092 *val = LSM6DSRX_AUX_HP_Hz260;
4093 break;
4094
4095 case LSM6DSRX_AUX_HP_1Hz040:
4096 *val = LSM6DSRX_AUX_HP_1Hz040;
4097 break;
4098
4099 default:
4100 *val = LSM6DSRX_AUX_HP_DISABLE;
4101 break;
4102 }
4103
4104 return ret;
4105 }
4106
4107 /**
4108 * @brief Enable / Disables OIS chain clamp. Enable: All OIS chain
4109 * outputs = 8000h during self-test; Disable: OIS chain self-test
4110 * outputs dependent from the aux gyro full scale selected.[set]
4111 *
4112 * @param ctx Read / write interface definitions.(ptr)
4113 * @param val Change the values of st_ois_clampdis in reg CTRL3_OIS
4114 * @retval Interface status (MANDATORY: return 0 -> no Error).
4115 *
4116 */
lsm6dsrx_aux_gy_clamp_set(const stmdev_ctx_t * ctx,lsm6dsrx_st_ois_clampdis_t val)4117 int32_t lsm6dsrx_aux_gy_clamp_set(const stmdev_ctx_t *ctx,
4118 lsm6dsrx_st_ois_clampdis_t val)
4119 {
4120 lsm6dsrx_ctrl3_ois_t ctrl3_ois;
4121 int32_t ret;
4122
4123 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
4124 (uint8_t *)&ctrl3_ois, 1);
4125
4126 if (ret == 0)
4127 {
4128 ctrl3_ois.st_ois_clampdis = (uint8_t)val;
4129 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_OIS,
4130 (uint8_t *)&ctrl3_ois, 1);
4131 }
4132
4133 return ret;
4134 }
4135
4136 /**
4137 * @brief Enable / Disables OIS chain clamp. Enable: All OIS chain
4138 * outputs = 8000h during self-test; Disable: OIS chain self-test
4139 * outputs dependent from the aux gyro full scale selected.[get]
4140 *
4141 * @param ctx Read / write interface definitions.(ptr)
4142 * @param val Get the values of st_ois_clampdis in reg CTRL3_OIS
4143 * @retval Interface status (MANDATORY: return 0 -> no Error).
4144 *
4145 */
lsm6dsrx_aux_gy_clamp_get(const stmdev_ctx_t * ctx,lsm6dsrx_st_ois_clampdis_t * val)4146 int32_t lsm6dsrx_aux_gy_clamp_get(const stmdev_ctx_t *ctx,
4147 lsm6dsrx_st_ois_clampdis_t *val)
4148 {
4149 lsm6dsrx_ctrl3_ois_t ctrl3_ois;
4150 int32_t ret;
4151
4152 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
4153 (uint8_t *)&ctrl3_ois, 1);
4154
4155 switch (ctrl3_ois.st_ois_clampdis)
4156 {
4157 case LSM6DSRX_ENABLE_CLAMP:
4158 *val = LSM6DSRX_ENABLE_CLAMP;
4159 break;
4160
4161 case LSM6DSRX_DISABLE_CLAMP:
4162 *val = LSM6DSRX_DISABLE_CLAMP;
4163 break;
4164
4165 default:
4166 *val = LSM6DSRX_ENABLE_CLAMP;
4167 break;
4168 }
4169
4170 return ret;
4171 }
4172
4173 /**
4174 * @brief Selects gyroscope OIS chain self-test.[set]
4175 *
4176 * @param ctx Read / write interface definitions.(ptr)
4177 * @param val Change the values of st_ois in reg CTRL3_OIS
4178 * @retval Interface status (MANDATORY: return 0 -> no Error).
4179 *
4180 */
lsm6dsrx_aux_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dsrx_st_ois_t val)4181 int32_t lsm6dsrx_aux_gy_self_test_set(const stmdev_ctx_t *ctx,
4182 lsm6dsrx_st_ois_t val)
4183 {
4184 lsm6dsrx_ctrl3_ois_t ctrl3_ois;
4185 int32_t ret;
4186
4187 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
4188 (uint8_t *)&ctrl3_ois, 1);
4189
4190 if (ret == 0)
4191 {
4192 ctrl3_ois.st_ois = (uint8_t)val;
4193 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_OIS,
4194 (uint8_t *)&ctrl3_ois, 1);
4195 }
4196
4197 return ret;
4198 }
4199
4200 /**
4201 * @brief Selects gyroscope OIS chain self-test.[get]
4202 *
4203 * @param ctx Read / write interface definitions.(ptr)
4204 * @param val Get the values of st_ois in reg CTRL3_OIS
4205 * @retval Interface status (MANDATORY: return 0 -> no Error).
4206 *
4207 */
lsm6dsrx_aux_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dsrx_st_ois_t * val)4208 int32_t lsm6dsrx_aux_gy_self_test_get(const stmdev_ctx_t *ctx,
4209 lsm6dsrx_st_ois_t *val)
4210 {
4211 lsm6dsrx_ctrl3_ois_t ctrl3_ois;
4212 int32_t ret;
4213
4214 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
4215 (uint8_t *)&ctrl3_ois, 1);
4216
4217 switch (ctrl3_ois.st_ois)
4218 {
4219 case LSM6DSRX_AUX_GY_DISABLE:
4220 *val = LSM6DSRX_AUX_GY_DISABLE;
4221 break;
4222
4223 case LSM6DSRX_AUX_GY_POS:
4224 *val = LSM6DSRX_AUX_GY_POS;
4225 break;
4226
4227 case LSM6DSRX_AUX_GY_NEG:
4228 *val = LSM6DSRX_AUX_GY_NEG;
4229 break;
4230
4231 default:
4232 *val = LSM6DSRX_AUX_GY_DISABLE;
4233 break;
4234 }
4235
4236 return ret;
4237 }
4238
4239 /**
4240 * @brief Selects accelerometer OIS channel bandwidth.[set]
4241 *
4242 * @param ctx Read / write interface definitions.(ptr)
4243 * @param val Change the values of filter_xl_conf_ois in reg CTRL3_OIS
4244 * @retval Interface status (MANDATORY: return 0 -> no Error).
4245 *
4246 */
lsm6dsrx_aux_xl_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsrx_filter_xl_conf_ois_t val)4247 int32_t lsm6dsrx_aux_xl_bandwidth_set(const stmdev_ctx_t *ctx,
4248 lsm6dsrx_filter_xl_conf_ois_t val)
4249 {
4250 lsm6dsrx_ctrl3_ois_t ctrl3_ois;
4251 int32_t ret;
4252
4253 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
4254 (uint8_t *)&ctrl3_ois, 1);
4255
4256 if (ret == 0)
4257 {
4258 ctrl3_ois.filter_xl_conf_ois = (uint8_t)val;
4259 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_OIS,
4260 (uint8_t *)&ctrl3_ois, 1);
4261 }
4262
4263 return ret;
4264 }
4265
4266 /**
4267 * @brief Selects accelerometer OIS channel bandwidth.[get]
4268 *
4269 * @param ctx Read / write interface definitions.(ptr)
4270 * @param val Get the values of filter_xl_conf_ois in reg CTRL3_OIS
4271 * @retval Interface status (MANDATORY: return 0 -> no Error).
4272 *
4273 */
lsm6dsrx_aux_xl_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsrx_filter_xl_conf_ois_t * val)4274 int32_t lsm6dsrx_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx,
4275 lsm6dsrx_filter_xl_conf_ois_t *val)
4276 {
4277 lsm6dsrx_ctrl3_ois_t ctrl3_ois;
4278 int32_t ret;
4279
4280 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
4281 (uint8_t *)&ctrl3_ois, 1);
4282
4283 switch (ctrl3_ois.filter_xl_conf_ois)
4284 {
4285 case LSM6DSRX_631Hz:
4286 *val = LSM6DSRX_631Hz;
4287 break;
4288
4289 case LSM6DSRX_295Hz:
4290 *val = LSM6DSRX_295Hz;
4291 break;
4292
4293 case LSM6DSRX_140Hz:
4294 *val = LSM6DSRX_140Hz;
4295 break;
4296
4297 case LSM6DSRX_68Hz2:
4298 *val = LSM6DSRX_68Hz2;
4299 break;
4300
4301 case LSM6DSRX_33Hz6:
4302 *val = LSM6DSRX_33Hz6;
4303 break;
4304
4305 case LSM6DSRX_16Hz7:
4306 *val = LSM6DSRX_16Hz7;
4307 break;
4308
4309 case LSM6DSRX_8Hz3:
4310 *val = LSM6DSRX_8Hz3;
4311 break;
4312
4313 case LSM6DSRX_4Hz11:
4314 *val = LSM6DSRX_4Hz11;
4315 break;
4316
4317 default:
4318 *val = LSM6DSRX_631Hz;
4319 break;
4320 }
4321
4322 return ret;
4323 }
4324
4325 /**
4326 * @brief Selects accelerometer OIS channel full-scale.[set]
4327 *
4328 * @param ctx Read / write interface definitions.(ptr)
4329 * @param val Change the values of fs_xl_ois in reg CTRL3_OIS
4330 * @retval Interface status (MANDATORY: return 0 -> no Error).
4331 *
4332 */
lsm6dsrx_aux_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsrx_fs_xl_ois_t val)4333 int32_t lsm6dsrx_aux_xl_full_scale_set(const stmdev_ctx_t *ctx,
4334 lsm6dsrx_fs_xl_ois_t val)
4335 {
4336 lsm6dsrx_ctrl3_ois_t ctrl3_ois;
4337 int32_t ret;
4338
4339 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
4340 (uint8_t *)&ctrl3_ois, 1);
4341
4342 if (ret == 0)
4343 {
4344 ctrl3_ois.fs_xl_ois = (uint8_t)val;
4345 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_OIS,
4346 (uint8_t *)&ctrl3_ois, 1);
4347 }
4348
4349 return ret;
4350 }
4351
4352 /**
4353 * @brief Selects accelerometer OIS channel full-scale.[get]
4354 *
4355 * @param ctx Read / write interface definitions.(ptr)
4356 * @param val Get the values of fs_xl_ois in reg CTRL3_OIS
4357 * @retval Interface status (MANDATORY: return 0 -> no Error).
4358 *
4359 */
lsm6dsrx_aux_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsrx_fs_xl_ois_t * val)4360 int32_t lsm6dsrx_aux_xl_full_scale_get(const stmdev_ctx_t *ctx,
4361 lsm6dsrx_fs_xl_ois_t *val)
4362 {
4363 lsm6dsrx_ctrl3_ois_t ctrl3_ois;
4364 int32_t ret;
4365
4366 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
4367 (uint8_t *)&ctrl3_ois, 1);
4368
4369 switch (ctrl3_ois.fs_xl_ois)
4370 {
4371 case LSM6DSRX_AUX_2g:
4372 *val = LSM6DSRX_AUX_2g;
4373 break;
4374
4375 case LSM6DSRX_AUX_16g:
4376 *val = LSM6DSRX_AUX_16g;
4377 break;
4378
4379 case LSM6DSRX_AUX_4g:
4380 *val = LSM6DSRX_AUX_4g;
4381 break;
4382
4383 case LSM6DSRX_AUX_8g:
4384 *val = LSM6DSRX_AUX_8g;
4385 break;
4386
4387 default:
4388 *val = LSM6DSRX_AUX_2g;
4389 break;
4390 }
4391
4392 return ret;
4393 }
4394
4395 /**
4396 * @}
4397 *
4398 */
4399
4400 /**
4401 * @defgroup LSM6DSRX_ main_serial_interface
4402 * @brief This section groups all the functions concerning main
4403 * serial interface management (not auxiliary)
4404 * @{
4405 *
4406 */
4407
4408 /**
4409 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
4410 *
4411 * @param ctx Read / write interface definitions.(ptr)
4412 * @param val Change the values of sdo_pu_en in reg PIN_CTRL
4413 * @retval Interface status (MANDATORY: return 0 -> no Error).
4414 *
4415 */
lsm6dsrx_sdo_sa0_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_sdo_pu_en_t val)4416 int32_t lsm6dsrx_sdo_sa0_mode_set(const stmdev_ctx_t *ctx,
4417 lsm6dsrx_sdo_pu_en_t val)
4418 {
4419 lsm6dsrx_pin_ctrl_t pin_ctrl;
4420 int32_t ret;
4421
4422 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PIN_CTRL,
4423 (uint8_t *)&pin_ctrl, 1);
4424
4425 if (ret == 0)
4426 {
4427 pin_ctrl.sdo_pu_en = (uint8_t)val;
4428 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PIN_CTRL,
4429 (uint8_t *)&pin_ctrl, 1);
4430 }
4431
4432 return ret;
4433 }
4434
4435 /**
4436 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
4437 *
4438 * @param ctx Read / write interface definitions.(ptr)
4439 * @param val Get the values of sdo_pu_en in reg PIN_CTRL
4440 * @retval Interface status (MANDATORY: return 0 -> no Error).
4441 *
4442 */
lsm6dsrx_sdo_sa0_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_sdo_pu_en_t * val)4443 int32_t lsm6dsrx_sdo_sa0_mode_get(const stmdev_ctx_t *ctx,
4444 lsm6dsrx_sdo_pu_en_t *val)
4445 {
4446 lsm6dsrx_pin_ctrl_t pin_ctrl;
4447 int32_t ret;
4448
4449 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PIN_CTRL,
4450 (uint8_t *)&pin_ctrl, 1);
4451
4452 switch (pin_ctrl.sdo_pu_en)
4453 {
4454 case LSM6DSRX_PULL_UP_DISC:
4455 *val = LSM6DSRX_PULL_UP_DISC;
4456 break;
4457
4458 case LSM6DSRX_PULL_UP_CONNECT:
4459 *val = LSM6DSRX_PULL_UP_CONNECT;
4460 break;
4461
4462 default:
4463 *val = LSM6DSRX_PULL_UP_DISC;
4464 break;
4465 }
4466
4467 return ret;
4468 }
4469
4470 /**
4471 * @brief Connect/Disconnect INT1 pull-down.[set]
4472 *
4473 * @param ctx Read / write interface definitions.(ptr)
4474 * @param val Change the values of pd_dis_int1 in reg I3C_BUS_AVB
4475 * @retval Interface status (MANDATORY: return 0 -> no Error).
4476 *
4477 */
lsm6dsrx_int1_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_pd_dis_int1_t val)4478 int32_t lsm6dsrx_int1_mode_set(const stmdev_ctx_t *ctx,
4479 lsm6dsrx_pd_dis_int1_t val)
4480 {
4481 lsm6dsrx_i3c_bus_avb_t i3c_bus_avb;
4482 int32_t ret;
4483
4484 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_I3C_BUS_AVB,
4485 (uint8_t *)&i3c_bus_avb, 1);
4486
4487 if (ret == 0)
4488 {
4489 i3c_bus_avb.pd_dis_int1 = (uint8_t)val;
4490 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_I3C_BUS_AVB,
4491 (uint8_t *)&i3c_bus_avb, 1);
4492 }
4493
4494 return ret;
4495 }
4496
4497 /**
4498 * @brief Connect/Disconnect INT1 pull-down.[get]
4499 *
4500 * @param ctx Read / write interface definitions.(ptr)
4501 * @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB
4502 * @retval Interface status (MANDATORY: return 0 -> no Error).
4503 *
4504 */
lsm6dsrx_int1_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_pd_dis_int1_t * val)4505 int32_t lsm6dsrx_int1_mode_get(const stmdev_ctx_t *ctx,
4506 lsm6dsrx_pd_dis_int1_t *val)
4507 {
4508 lsm6dsrx_i3c_bus_avb_t i3c_bus_avb;
4509 int32_t ret;
4510
4511 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_I3C_BUS_AVB,
4512 (uint8_t *)&i3c_bus_avb, 1);
4513
4514 switch (i3c_bus_avb.pd_dis_int1)
4515 {
4516 case LSM6DSRX_PULL_DOWN_CONNECT:
4517 *val = LSM6DSRX_PULL_DOWN_CONNECT;
4518 break;
4519
4520 case LSM6DSRX_PULL_DOWN_DISC:
4521 *val = LSM6DSRX_PULL_DOWN_DISC;
4522 break;
4523
4524 default:
4525 *val = LSM6DSRX_PULL_DOWN_CONNECT;
4526 break;
4527 }
4528
4529 return ret;
4530 }
4531
4532 /**
4533 * @brief SPI Serial Interface Mode selection.[set]
4534 *
4535 * @param ctx Read / write interface definitions.(ptr)
4536 * @param val Change the values of sim in reg CTRL3_C
4537 * @retval Interface status (MANDATORY: return 0 -> no Error).
4538 *
4539 */
lsm6dsrx_spi_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_sim_t val)4540 int32_t lsm6dsrx_spi_mode_set(const stmdev_ctx_t *ctx,
4541 lsm6dsrx_sim_t val)
4542 {
4543 lsm6dsrx_ctrl3_c_t ctrl3_c;
4544 int32_t ret;
4545
4546 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C,
4547 (uint8_t *)&ctrl3_c, 1);
4548
4549 if (ret == 0)
4550 {
4551 ctrl3_c.sim = (uint8_t)val;
4552 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C,
4553 (uint8_t *)&ctrl3_c, 1);
4554 }
4555
4556 return ret;
4557 }
4558
4559 /**
4560 * @brief SPI Serial Interface Mode selection.[get]
4561 *
4562 * @param ctx Read / write interface definitions.(ptr)
4563 * @param val Get the values of sim in reg CTRL3_C
4564 * @retval Interface status (MANDATORY: return 0 -> no Error).
4565 *
4566 */
lsm6dsrx_spi_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_sim_t * val)4567 int32_t lsm6dsrx_spi_mode_get(const stmdev_ctx_t *ctx,
4568 lsm6dsrx_sim_t *val)
4569 {
4570 lsm6dsrx_ctrl3_c_t ctrl3_c;
4571 int32_t ret;
4572
4573 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C,
4574 (uint8_t *)&ctrl3_c, 1);
4575
4576 switch (ctrl3_c.sim)
4577 {
4578 case LSM6DSRX_SPI_4_WIRE:
4579 *val = LSM6DSRX_SPI_4_WIRE;
4580 break;
4581
4582 case LSM6DSRX_SPI_3_WIRE:
4583 *val = LSM6DSRX_SPI_3_WIRE;
4584 break;
4585
4586 default:
4587 *val = LSM6DSRX_SPI_4_WIRE;
4588 break;
4589 }
4590
4591 return ret;
4592 }
4593
4594 /**
4595 * @brief Disable / Enable I2C interface.[set]
4596 *
4597 * @param ctx Read / write interface definitions.(ptr)
4598 * @param val Change the values of i2c_disable in reg CTRL4_C
4599 * @retval Interface status (MANDATORY: return 0 -> no Error).
4600 *
4601 */
lsm6dsrx_i2c_interface_set(const stmdev_ctx_t * ctx,lsm6dsrx_i2c_disable_t val)4602 int32_t lsm6dsrx_i2c_interface_set(const stmdev_ctx_t *ctx,
4603 lsm6dsrx_i2c_disable_t val)
4604 {
4605 lsm6dsrx_ctrl4_c_t ctrl4_c;
4606 int32_t ret;
4607
4608 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C,
4609 (uint8_t *)&ctrl4_c, 1);
4610
4611 if (ret == 0)
4612 {
4613 ctrl4_c.i2c_disable = (uint8_t)val;
4614 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C,
4615 (uint8_t *)&ctrl4_c, 1);
4616 }
4617
4618 return ret;
4619 }
4620
4621 /**
4622 * @brief Disable / Enable I2C interface.[get]
4623 *
4624 * @param ctx Read / write interface definitions.(ptr)
4625 * @param val Get the values of i2c reg CTRL4_C
4626 * @retval Interface status (MANDATORY: return 0 -> no Error).
4627 *
4628 */
lsm6dsrx_i2c_interface_get(const stmdev_ctx_t * ctx,lsm6dsrx_i2c_disable_t * val)4629 int32_t lsm6dsrx_i2c_interface_get(const stmdev_ctx_t *ctx,
4630 lsm6dsrx_i2c_disable_t *val)
4631 {
4632 lsm6dsrx_ctrl4_c_t ctrl4_c;
4633 int32_t ret;
4634
4635 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C,
4636 (uint8_t *)&ctrl4_c, 1);
4637
4638 switch (ctrl4_c.i2c_disable)
4639 {
4640 case LSM6DSRX_I2C_ENABLE:
4641 *val = LSM6DSRX_I2C_ENABLE;
4642 break;
4643
4644 case LSM6DSRX_I2C_DISABLE:
4645 *val = LSM6DSRX_I2C_DISABLE;
4646 break;
4647
4648 default:
4649 *val = LSM6DSRX_I2C_ENABLE;
4650 break;
4651 }
4652
4653 return ret;
4654 }
4655
4656 /**
4657 * @brief I3C Enable/Disable communication protocol.[set]
4658 *
4659 * @param ctx Read / write interface definitions.(ptr)
4660 * @param val Change the values of i3c_disable in reg CTRL9_XL
4661 * @retval Interface status (MANDATORY: return 0 -> no Error).
4662 *
4663 */
lsm6dsrx_i3c_disable_set(const stmdev_ctx_t * ctx,lsm6dsrx_i3c_disable_t val)4664 int32_t lsm6dsrx_i3c_disable_set(const stmdev_ctx_t *ctx,
4665 lsm6dsrx_i3c_disable_t val)
4666 {
4667 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
4668 lsm6dsrx_i3c_bus_avb_t i3c_bus_avb;
4669 int32_t ret;
4670
4671 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
4672
4673 if (ret == 0)
4674 {
4675 ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
4676 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL,
4677 (uint8_t *)&ctrl9_xl, 1);
4678 }
4679
4680 if (ret == 0)
4681 {
4682 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_I3C_BUS_AVB,
4683 (uint8_t *)&i3c_bus_avb, 1);
4684 }
4685
4686 if (ret == 0)
4687 {
4688 i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
4689 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_I3C_BUS_AVB,
4690 (uint8_t *)&i3c_bus_avb, 1);
4691 }
4692
4693 return ret;
4694 }
4695
4696 /**
4697 * @brief I3C Enable/Disable communication protocol.[get]
4698 *
4699 * @param ctx Read / write interface definitions.(ptr)
4700 * @param val Change the values of i3c_disable in reg CTRL9_XL
4701 * @retval Interface status (MANDATORY: return 0 -> no Error).
4702 *
4703 */
lsm6dsrx_i3c_disable_get(const stmdev_ctx_t * ctx,lsm6dsrx_i3c_disable_t * val)4704 int32_t lsm6dsrx_i3c_disable_get(const stmdev_ctx_t *ctx,
4705 lsm6dsrx_i3c_disable_t *val)
4706 {
4707 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
4708 lsm6dsrx_i3c_bus_avb_t i3c_bus_avb;
4709 int32_t ret;
4710
4711 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
4712
4713 if (ret == 0)
4714 {
4715 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_I3C_BUS_AVB,
4716 (uint8_t *)&i3c_bus_avb, 1);
4717 }
4718
4719 switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel)
4720 {
4721 case LSM6DSRX_I3C_DISABLE:
4722 *val = LSM6DSRX_I3C_DISABLE;
4723 break;
4724
4725 case LSM6DSRX_I3C_ENABLE_T_50us:
4726 *val = LSM6DSRX_I3C_ENABLE_T_50us;
4727 break;
4728
4729 case LSM6DSRX_I3C_ENABLE_T_2us:
4730 *val = LSM6DSRX_I3C_ENABLE_T_2us;
4731 break;
4732
4733 case LSM6DSRX_I3C_ENABLE_T_1ms:
4734 *val = LSM6DSRX_I3C_ENABLE_T_1ms;
4735 break;
4736
4737 case LSM6DSRX_I3C_ENABLE_T_25ms:
4738 *val = LSM6DSRX_I3C_ENABLE_T_25ms;
4739 break;
4740
4741 default:
4742 *val = LSM6DSRX_I3C_DISABLE;
4743 break;
4744 }
4745
4746 return ret;
4747 }
4748
4749 /**
4750 * @}
4751 *
4752 */
4753
4754 /**
4755 * @defgroup LSM6DSRX_interrupt_pins
4756 * @brief This section groups all the functions that manage
4757 * interrupt pins
4758 * @{
4759 *
4760 */
4761
4762 /**
4763 * @brief Select the signal that need to route on int1 pad[set]
4764 *
4765 * @param ctx Read / write interface definitions.(ptr)
4766 * @param val Structure of registers: INT1_CTRL,MD1_CFG,
4767 * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B
4768 * @retval Interface status (MANDATORY: return 0 -> no Error).
4769 *
4770 */
lsm6dsrx_pin_int1_route_set(const stmdev_ctx_t * ctx,lsm6dsrx_pin_int1_route_t * val)4771 int32_t lsm6dsrx_pin_int1_route_set(const stmdev_ctx_t *ctx,
4772 lsm6dsrx_pin_int1_route_t *val)
4773 {
4774 lsm6dsrx_tap_cfg2_t tap_cfg2;
4775 int32_t ret;
4776
4777 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
4778
4779 if (ret == 0)
4780 {
4781 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MLC_INT1,
4782 (uint8_t *)&val->mlc_int1, 1);
4783 }
4784
4785 if (ret == 0)
4786 {
4787 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_INT1,
4788 (uint8_t *)&val->emb_func_int1, 1);
4789 }
4790
4791 if (ret == 0)
4792 {
4793 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_INT1_A,
4794 (uint8_t *)&val->fsm_int1_a, 1);
4795 }
4796
4797 if (ret == 0)
4798 {
4799 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_INT1_B,
4800 (uint8_t *)&val->fsm_int1_b, 1);
4801 }
4802
4803 if (ret == 0)
4804 {
4805 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
4806 }
4807
4808 if (ret == 0)
4809 {
4810 if ((val->emb_func_int1.int1_fsm_lc |
4811 val->emb_func_int1.int1_sig_mot |
4812 val->emb_func_int1.int1_step_detector |
4813 val->emb_func_int1.int1_tilt |
4814 val->fsm_int1_a.int1_fsm1 |
4815 val->fsm_int1_a.int1_fsm2 |
4816 val->fsm_int1_a.int1_fsm3 |
4817 val->fsm_int1_a.int1_fsm4 |
4818 val->fsm_int1_a.int1_fsm5 |
4819 val->fsm_int1_a.int1_fsm6 |
4820 val->fsm_int1_a.int1_fsm7 |
4821 val->fsm_int1_a.int1_fsm8 |
4822 val->fsm_int1_b.int1_fsm9 |
4823 val->fsm_int1_b.int1_fsm10 |
4824 val->fsm_int1_b.int1_fsm11 |
4825 val->fsm_int1_b.int1_fsm12 |
4826 val->fsm_int1_b.int1_fsm13 |
4827 val->fsm_int1_b.int1_fsm14 |
4828 val->fsm_int1_b.int1_fsm15 |
4829 val->fsm_int1_b.int1_fsm16 |
4830 val->mlc_int1.int1_mlc1 |
4831 val->mlc_int1.int1_mlc2 |
4832 val->mlc_int1.int1_mlc3 |
4833 val->mlc_int1.int1_mlc4 |
4834 val->mlc_int1.int1_mlc5 |
4835 val->mlc_int1.int1_mlc6 |
4836 val->mlc_int1.int1_mlc7 |
4837 val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE)
4838 {
4839 val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
4840 }
4841 else
4842 {
4843 val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
4844 }
4845
4846 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT1_CTRL,
4847 (uint8_t *)&val->int1_ctrl, 1);
4848 }
4849
4850 if (ret == 0)
4851 {
4852 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MD1_CFG,
4853 (uint8_t *)&val->md1_cfg, 1);
4854 }
4855
4856 if (ret == 0)
4857 {
4858 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2,
4859 (uint8_t *)&tap_cfg2, 1);
4860
4861 if ((val->int1_ctrl.den_drdy_flag |
4862 val->int1_ctrl.int1_boot |
4863 val->int1_ctrl.int1_cnt_bdr |
4864 val->int1_ctrl.int1_drdy_g |
4865 val->int1_ctrl.int1_drdy_xl |
4866 val->int1_ctrl.int1_fifo_full |
4867 val->int1_ctrl.int1_fifo_ovr |
4868 val->int1_ctrl.int1_fifo_th |
4869 val->md1_cfg.int1_shub |
4870 val->md1_cfg.int1_6d |
4871 val->md1_cfg.int1_double_tap |
4872 val->md1_cfg.int1_ff |
4873 val->md1_cfg.int1_wu |
4874 val->md1_cfg.int1_single_tap |
4875 val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
4876 {
4877 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
4878 }
4879
4880 else
4881 {
4882 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
4883 }
4884 }
4885
4886 if (ret == 0)
4887 {
4888 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG2,
4889 (uint8_t *)&tap_cfg2, 1);
4890 }
4891
4892 return ret;
4893 }
4894
4895 /**
4896 * @brief Select the signal that need to route on int1 pad.[get]
4897 *
4898 * @param ctx Read / write interface definitions.(ptr)
4899 * @param val Structure of registers: INT1_CTRL, MD1_CFG,
4900 * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B.(ptr)
4901 * @retval Interface status (MANDATORY: return 0 -> no Error).
4902 *
4903 */
lsm6dsrx_pin_int1_route_get(const stmdev_ctx_t * ctx,lsm6dsrx_pin_int1_route_t * val)4904 int32_t lsm6dsrx_pin_int1_route_get(const stmdev_ctx_t *ctx,
4905 lsm6dsrx_pin_int1_route_t *val)
4906 {
4907 int32_t ret;
4908
4909 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
4910
4911 if (ret == 0)
4912 {
4913 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MLC_INT1,
4914 (uint8_t *)&val->mlc_int1, 1);
4915 }
4916
4917 if (ret == 0)
4918 {
4919 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INT1,
4920 (uint8_t *)&val->emb_func_int1, 1);
4921 }
4922
4923 if (ret == 0)
4924 {
4925 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_INT1_A,
4926 (uint8_t *)&val->fsm_int1_a, 1);
4927 }
4928
4929 if (ret == 0)
4930 {
4931 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_INT1_B,
4932 (uint8_t *)&val->fsm_int1_b, 1);
4933 }
4934
4935 if (ret == 0)
4936 {
4937 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
4938 }
4939
4940 if (ret == 0)
4941 {
4942 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT1_CTRL,
4943 (uint8_t *)&val->int1_ctrl, 1);
4944 }
4945
4946 if (ret == 0)
4947 {
4948 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MD1_CFG,
4949 (uint8_t *)&val->md1_cfg, 1);
4950 }
4951
4952 return ret;
4953 }
4954
4955 /**
4956 * @brief Select the signal that need to route on int2 pad[set]
4957 *
4958 * @param ctx Read / write interface definitions.(ptr)
4959 * @param val Structure of registers INT2_CTRL, MD2_CFG,
4960 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
4961 * @retval Interface status (MANDATORY: return 0 -> no Error).
4962 *
4963 */
lsm6dsrx_pin_int2_route_set(const stmdev_ctx_t * ctx,lsm6dsrx_pin_int2_route_t * val)4964 int32_t lsm6dsrx_pin_int2_route_set(const stmdev_ctx_t *ctx,
4965 lsm6dsrx_pin_int2_route_t *val)
4966 {
4967 lsm6dsrx_tap_cfg2_t tap_cfg2;
4968 int32_t ret;
4969
4970 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
4971
4972 if (ret == 0)
4973 {
4974 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MLC_INT2,
4975 (uint8_t *)&val->mlc_int2, 1);
4976 }
4977
4978 if (ret == 0)
4979 {
4980 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_INT2,
4981 (uint8_t *)&val->emb_func_int2, 1);
4982 }
4983
4984 if (ret == 0)
4985 {
4986 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_INT2_A,
4987 (uint8_t *)&val->fsm_int2_a, 1);
4988 }
4989
4990 if (ret == 0)
4991 {
4992 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_INT2_B,
4993 (uint8_t *)&val->fsm_int2_b, 1);
4994 }
4995
4996 if (ret == 0)
4997 {
4998 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
4999 }
5000
5001 if (ret == 0)
5002 {
5003 if ((val->emb_func_int2.int2_step_detector |
5004 val->emb_func_int2.int2_tilt |
5005 val->emb_func_int2.int2_sig_mot |
5006 val->emb_func_int2.int2_fsm_lc |
5007 val->fsm_int2_a.int2_fsm1 |
5008 val->fsm_int2_a.int2_fsm2 |
5009 val->fsm_int2_a.int2_fsm3 |
5010 val->fsm_int2_a.int2_fsm4 |
5011 val->fsm_int2_a.int2_fsm5 |
5012 val->fsm_int2_a.int2_fsm6 |
5013 val->fsm_int2_a.int2_fsm7 |
5014 val->fsm_int2_a.int2_fsm8 |
5015 val->fsm_int2_b.int2_fsm9 |
5016 val->fsm_int2_b.int2_fsm10 |
5017 val->fsm_int2_b.int2_fsm11 |
5018 val->fsm_int2_b.int2_fsm12 |
5019 val->fsm_int2_b.int2_fsm13 |
5020 val->fsm_int2_b.int2_fsm14 |
5021 val->fsm_int2_b.int2_fsm15 |
5022 val->fsm_int2_b.int2_fsm16 |
5023 val->mlc_int2.int2_mlc1 |
5024 val->mlc_int2.int2_mlc2 |
5025 val->mlc_int2.int2_mlc3 |
5026 val->mlc_int2.int2_mlc4 |
5027 val->mlc_int2.int2_mlc5 |
5028 val->mlc_int2.int2_mlc6 |
5029 val->mlc_int2.int2_mlc7 |
5030 val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE)
5031 {
5032 val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
5033 }
5034 else
5035 {
5036 val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
5037 }
5038
5039 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT2_CTRL,
5040 (uint8_t *)&val->int2_ctrl, 1);
5041 }
5042
5043 if (ret == 0)
5044 {
5045 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MD2_CFG,
5046 (uint8_t *)&val->md2_cfg, 1);
5047 }
5048
5049 if (ret == 0)
5050 {
5051 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2,
5052 (uint8_t *)&tap_cfg2, 1);
5053 }
5054
5055 if (ret == 0)
5056 {
5057 if ((val->int2_ctrl.int2_drdy_xl |
5058 val->int2_ctrl.int2_drdy_g |
5059 val->int2_ctrl.int2_drdy_temp |
5060 val->int2_ctrl.int2_fifo_th |
5061 val->int2_ctrl.int2_fifo_ovr |
5062 val->int2_ctrl.int2_fifo_full |
5063 val->int2_ctrl.int2_cnt_bdr |
5064 val->md2_cfg.int2_6d |
5065 val->md2_cfg.int2_double_tap |
5066 val->md2_cfg.int2_ff |
5067 val->md2_cfg.int2_wu |
5068 val->md2_cfg.int2_single_tap |
5069 val->md2_cfg.int2_sleep_change) != PROPERTY_DISABLE)
5070 {
5071 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
5072 }
5073
5074 else
5075 {
5076 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
5077 }
5078
5079 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG2,
5080 (uint8_t *)&tap_cfg2, 1);
5081 }
5082
5083 return ret;
5084 }
5085
5086 /**
5087 * @brief Select the signal that need to route on int2 pad.[get]
5088 *
5089 * @param ctx Read / write interface definitions.(ptr)
5090 * @param val Structure of registers INT2_CTRL, MD2_CFG,
5091 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B.[get]
5092 * @retval Interface status (MANDATORY: return 0 -> no Error).
5093 *
5094 */
lsm6dsrx_pin_int2_route_get(const stmdev_ctx_t * ctx,lsm6dsrx_pin_int2_route_t * val)5095 int32_t lsm6dsrx_pin_int2_route_get(const stmdev_ctx_t *ctx,
5096 lsm6dsrx_pin_int2_route_t *val)
5097 {
5098 int32_t ret;
5099
5100 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
5101
5102 if (ret == 0)
5103 {
5104 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MLC_INT2,
5105 (uint8_t *)&val->mlc_int2, 1);
5106 }
5107
5108 if (ret == 0)
5109 {
5110 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INT2,
5111 (uint8_t *)&val->emb_func_int2, 1);
5112 }
5113
5114 if (ret == 0)
5115 {
5116 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_INT2_A,
5117 (uint8_t *)&val->fsm_int2_a, 1);
5118 }
5119
5120 if (ret == 0)
5121 {
5122 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_INT2_B,
5123 (uint8_t *)&val->fsm_int2_b, 1);
5124 }
5125
5126 if (ret == 0)
5127 {
5128 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
5129 }
5130
5131 if (ret == 0)
5132 {
5133 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT2_CTRL,
5134 (uint8_t *)&val->int2_ctrl, 1);
5135 }
5136
5137 if (ret == 0)
5138 {
5139 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MD2_CFG,
5140 (uint8_t *)&val->md2_cfg, 1);
5141 }
5142
5143 return ret;
5144 }
5145
5146 /**
5147 * @brief Push-pull/open drain selection on interrupt pads.[set]
5148 *
5149 * @param ctx Read / write interface definitions.(ptr)
5150 * @param val Change the values of pp_od in reg CTRL3_C
5151 * @retval Interface status (MANDATORY: return 0 -> no Error).
5152 *
5153 */
lsm6dsrx_pin_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_pp_od_t val)5154 int32_t lsm6dsrx_pin_mode_set(const stmdev_ctx_t *ctx,
5155 lsm6dsrx_pp_od_t val)
5156 {
5157 lsm6dsrx_ctrl3_c_t ctrl3_c;
5158 int32_t ret;
5159
5160 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C,
5161 (uint8_t *)&ctrl3_c, 1);
5162
5163 if (ret == 0)
5164 {
5165 ctrl3_c.pp_od = (uint8_t)val;
5166 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C,
5167 (uint8_t *)&ctrl3_c, 1);
5168 }
5169
5170 return ret;
5171 }
5172
5173 /**
5174 * @brief Push-pull/open drain selection on interrupt pads.[get]
5175 *
5176 * @param ctx Read / write interface definitions.(ptr)
5177 * @param val Get the values of pp_od in reg CTRL3_C
5178 * @retval Interface status (MANDATORY: return 0 -> no Error).
5179 *
5180 */
lsm6dsrx_pin_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_pp_od_t * val)5181 int32_t lsm6dsrx_pin_mode_get(const stmdev_ctx_t *ctx,
5182 lsm6dsrx_pp_od_t *val)
5183 {
5184 lsm6dsrx_ctrl3_c_t ctrl3_c;
5185 int32_t ret;
5186
5187 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C,
5188 (uint8_t *)&ctrl3_c, 1);
5189
5190 switch (ctrl3_c.pp_od)
5191 {
5192 case LSM6DSRX_PUSH_PULL:
5193 *val = LSM6DSRX_PUSH_PULL;
5194 break;
5195
5196 case LSM6DSRX_OPEN_DRAIN:
5197 *val = LSM6DSRX_OPEN_DRAIN;
5198 break;
5199
5200 default:
5201 *val = LSM6DSRX_PUSH_PULL;
5202 break;
5203 }
5204
5205 return ret;
5206 }
5207
5208 /**
5209 * @brief Interrupt active-high/low.[set]
5210 *
5211 * @param ctx Read / write interface definitions.(ptr)
5212 * @param val Change the values of h_lactive in reg CTRL3_C
5213 * @retval Interface status (MANDATORY: return 0 -> no Error).
5214 *
5215 */
lsm6dsrx_pin_polarity_set(const stmdev_ctx_t * ctx,lsm6dsrx_h_lactive_t val)5216 int32_t lsm6dsrx_pin_polarity_set(const stmdev_ctx_t *ctx,
5217 lsm6dsrx_h_lactive_t val)
5218 {
5219 lsm6dsrx_ctrl3_c_t ctrl3_c;
5220 int32_t ret;
5221
5222 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C,
5223 (uint8_t *)&ctrl3_c, 1);
5224
5225 if (ret == 0)
5226 {
5227 ctrl3_c.h_lactive = (uint8_t)val;
5228 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C,
5229 (uint8_t *)&ctrl3_c, 1);
5230 }
5231
5232 return ret;
5233 }
5234
5235 /**
5236 * @brief Interrupt active-high/low.[get]
5237 *
5238 * @param ctx Read / write interface definitions.(ptr)
5239 * @param val Get the values of h_lactive in reg CTRL3_C
5240 * @retval Interface status (MANDATORY: return 0 -> no Error).
5241 *
5242 */
lsm6dsrx_pin_polarity_get(const stmdev_ctx_t * ctx,lsm6dsrx_h_lactive_t * val)5243 int32_t lsm6dsrx_pin_polarity_get(const stmdev_ctx_t *ctx,
5244 lsm6dsrx_h_lactive_t *val)
5245 {
5246 lsm6dsrx_ctrl3_c_t ctrl3_c;
5247 int32_t ret;
5248
5249 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C,
5250 (uint8_t *)&ctrl3_c, 1);
5251
5252 switch (ctrl3_c.h_lactive)
5253 {
5254 case LSM6DSRX_ACTIVE_HIGH:
5255 *val = LSM6DSRX_ACTIVE_HIGH;
5256 break;
5257
5258 case LSM6DSRX_ACTIVE_LOW:
5259 *val = LSM6DSRX_ACTIVE_LOW;
5260 break;
5261
5262 default:
5263 *val = LSM6DSRX_ACTIVE_HIGH;
5264 break;
5265 }
5266
5267 return ret;
5268 }
5269
5270 /**
5271 * @brief All interrupt signals become available on INT1 pin.[set]
5272 *
5273 * @param ctx Read / write interface definitions.(ptr)
5274 * @param val Change the values of int2_on_int1 in reg CTRL4_C
5275 * @retval Interface status (MANDATORY: return 0 -> no Error).
5276 *
5277 */
lsm6dsrx_all_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)5278 int32_t lsm6dsrx_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
5279 {
5280 lsm6dsrx_ctrl4_c_t ctrl4_c;
5281 int32_t ret;
5282
5283 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C,
5284 (uint8_t *)&ctrl4_c, 1);
5285
5286 if (ret == 0)
5287 {
5288 ctrl4_c.int2_on_int1 = (uint8_t)val;
5289 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C,
5290 (uint8_t *)&ctrl4_c, 1);
5291 }
5292
5293 return ret;
5294 }
5295
5296 /**
5297 * @brief All interrupt signals become available on INT1 pin.[get]
5298 *
5299 * @param ctx Read / write interface definitions.(ptr)
5300 * @param val Change the values of int2_on_int1 in reg CTRL4_C
5301 * @retval Interface status (MANDATORY: return 0 -> no Error).
5302 *
5303 */
lsm6dsrx_all_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)5304 int32_t lsm6dsrx_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
5305 {
5306 lsm6dsrx_ctrl4_c_t ctrl4_c;
5307 int32_t ret;
5308
5309 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C,
5310 (uint8_t *)&ctrl4_c, 1);
5311 *val = ctrl4_c.int2_on_int1;
5312
5313 return ret;
5314 }
5315
5316 /**
5317 * @brief All interrupt signals notification mode.[set]
5318 *
5319 * @param ctx Read / write interface definitions.(ptr)
5320 * @param val Change the values of lir in reg TAP_CFG0
5321 * @retval Interface status (MANDATORY: return 0 -> no Error).
5322 *
5323 */
lsm6dsrx_int_notification_set(const stmdev_ctx_t * ctx,lsm6dsrx_lir_t val)5324 int32_t lsm6dsrx_int_notification_set(const stmdev_ctx_t *ctx,
5325 lsm6dsrx_lir_t val)
5326 {
5327 lsm6dsrx_tap_cfg0_t tap_cfg0;
5328 lsm6dsrx_page_rw_t page_rw;
5329 int32_t ret;
5330
5331 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0,
5332 (uint8_t *)&tap_cfg0, 1);
5333
5334 if (ret == 0)
5335 {
5336 tap_cfg0.lir = (uint8_t)val & 0x01U;
5337 tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
5338 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG0,
5339 (uint8_t *)&tap_cfg0, 1);
5340 }
5341
5342 if (ret == 0)
5343 {
5344 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
5345 }
5346
5347 if (ret == 0)
5348 {
5349 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW,
5350 (uint8_t *)&page_rw, 1);
5351 }
5352
5353 if (ret == 0)
5354 {
5355 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
5356 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW,
5357 (uint8_t *)&page_rw, 1);
5358 }
5359
5360 if (ret == 0)
5361 {
5362 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
5363 }
5364
5365 return ret;
5366 }
5367
5368 /**
5369 * @brief All interrupt signals notification mode.[get]
5370 *
5371 * @param ctx Read / write interface definitions.(ptr)
5372 * @param val Get the values of lir in reg TAP_CFG0
5373 * @retval Interface status (MANDATORY: return 0 -> no Error).
5374 *
5375 */
lsm6dsrx_int_notification_get(const stmdev_ctx_t * ctx,lsm6dsrx_lir_t * val)5376 int32_t lsm6dsrx_int_notification_get(const stmdev_ctx_t *ctx,
5377 lsm6dsrx_lir_t *val)
5378 {
5379 lsm6dsrx_tap_cfg0_t tap_cfg0;
5380 lsm6dsrx_page_rw_t page_rw;
5381 int32_t ret;
5382
5383 *val = LSM6DSRX_ALL_INT_PULSED;
5384 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0,
5385 (uint8_t *)&tap_cfg0, 1);
5386
5387 if (ret == 0)
5388 {
5389 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
5390 }
5391
5392 if (ret == 0)
5393 {
5394 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW,
5395 (uint8_t *)&page_rw, 1);
5396 }
5397
5398 if (ret == 0)
5399 {
5400 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
5401 }
5402
5403 switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir)
5404 {
5405 case LSM6DSRX_ALL_INT_PULSED:
5406 *val = LSM6DSRX_ALL_INT_PULSED;
5407 break;
5408
5409 case LSM6DSRX_BASE_LATCHED_EMB_PULSED:
5410 *val = LSM6DSRX_BASE_LATCHED_EMB_PULSED;
5411 break;
5412
5413 case LSM6DSRX_BASE_PULSED_EMB_LATCHED:
5414 *val = LSM6DSRX_BASE_PULSED_EMB_LATCHED;
5415 break;
5416
5417 case LSM6DSRX_ALL_INT_LATCHED:
5418 *val = LSM6DSRX_ALL_INT_LATCHED;
5419 break;
5420
5421 default:
5422 *val = LSM6DSRX_ALL_INT_PULSED;
5423 break;
5424 }
5425
5426 return ret;
5427 }
5428
5429 /**
5430 * @}
5431 *
5432 */
5433
5434 /**
5435 * @defgroup LSM6DSRX_Wake_Up_event
5436 * @brief This section groups all the functions that manage the
5437 * Wake Up event generation.
5438 * @{
5439 *
5440 */
5441
5442 /**
5443 * @brief Weight of 1 LSB of wakeup threshold.[set]
5444 * 0: 1 LSB =FS_XL / 64
5445 * 1: 1 LSB = FS_XL / 256
5446 *
5447 * @param ctx Read / write interface definitions.(ptr)
5448 * @param val Change the values of wake_ths_w in reg WAKE_UP_DUR
5449 * @retval Interface status (MANDATORY: return 0 -> no Error).
5450 *
5451 */
lsm6dsrx_wkup_ths_weight_set(const stmdev_ctx_t * ctx,lsm6dsrx_wake_ths_w_t val)5452 int32_t lsm6dsrx_wkup_ths_weight_set(const stmdev_ctx_t *ctx,
5453 lsm6dsrx_wake_ths_w_t val)
5454 {
5455 lsm6dsrx_wake_up_dur_t wake_up_dur;
5456 int32_t ret;
5457
5458 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
5459 (uint8_t *)&wake_up_dur, 1);
5460
5461 if (ret == 0)
5462 {
5463 wake_up_dur.wake_ths_w = (uint8_t)val;
5464 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
5465 (uint8_t *)&wake_up_dur, 1);
5466 }
5467
5468 return ret;
5469 }
5470
5471 /**
5472 * @brief Weight of 1 LSB of wakeup threshold.[get]
5473 * 0: 1 LSB =FS_XL / 64
5474 * 1: 1 LSB = FS_XL / 256
5475 *
5476 * @param ctx Read / write interface definitions.(ptr)
5477 * @param val Get the values of wake_ths_w in reg WAKE_UP_DUR
5478 * @retval Interface status (MANDATORY: return 0 -> no Error).
5479 *
5480 */
lsm6dsrx_wkup_ths_weight_get(const stmdev_ctx_t * ctx,lsm6dsrx_wake_ths_w_t * val)5481 int32_t lsm6dsrx_wkup_ths_weight_get(const stmdev_ctx_t *ctx,
5482 lsm6dsrx_wake_ths_w_t *val)
5483 {
5484 lsm6dsrx_wake_up_dur_t wake_up_dur;
5485 int32_t ret;
5486
5487 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
5488 (uint8_t *)&wake_up_dur, 1);
5489
5490 switch (wake_up_dur.wake_ths_w)
5491 {
5492 case LSM6DSRX_LSb_FS_DIV_64:
5493 *val = LSM6DSRX_LSb_FS_DIV_64;
5494 break;
5495
5496 case LSM6DSRX_LSb_FS_DIV_256:
5497 *val = LSM6DSRX_LSb_FS_DIV_256;
5498 break;
5499
5500 default:
5501 *val = LSM6DSRX_LSb_FS_DIV_64;
5502 break;
5503 }
5504
5505 return ret;
5506 }
5507
5508 /**
5509 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
5510 * WAKE_UP_DUR.[set]
5511 *
5512 * @param ctx Read / write interface definitions.(ptr)
5513 * @param val Change the values of wk_ths in reg WAKE_UP_THS
5514 * @retval Interface status (MANDATORY: return 0 -> no Error).
5515 *
5516 */
lsm6dsrx_wkup_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)5517 int32_t lsm6dsrx_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
5518 {
5519 lsm6dsrx_wake_up_ths_t wake_up_ths;
5520 int32_t ret;
5521
5522 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS,
5523 (uint8_t *)&wake_up_ths, 1);
5524
5525 if (ret == 0)
5526 {
5527 wake_up_ths.wk_ths = (uint8_t)val;
5528 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_THS,
5529 (uint8_t *)&wake_up_ths, 1);
5530 }
5531
5532 return ret;
5533 }
5534
5535 /**
5536 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
5537 * WAKE_UP_DUR.[get]
5538 *
5539 * @param ctx Read / write interface definitions.(ptr)
5540 * @param val Change the values of wk_ths in reg WAKE_UP_THS
5541 * @retval Interface status (MANDATORY: return 0 -> no Error).
5542 *
5543 */
lsm6dsrx_wkup_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)5544 int32_t lsm6dsrx_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
5545 {
5546 lsm6dsrx_wake_up_ths_t wake_up_ths;
5547 int32_t ret;
5548
5549 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS,
5550 (uint8_t *)&wake_up_ths, 1);
5551 *val = wake_up_ths.wk_ths;
5552
5553 return ret;
5554 }
5555
5556 /**
5557 * @brief Wake up duration event( 1LSb = 1 / ODR ).[set]
5558 *
5559 * @param ctx Read / write interface definitions.(ptr)
5560 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
5561 * @retval Interface status (MANDATORY: return 0 -> no Error).
5562 *
5563 */
lsm6dsrx_xl_usr_offset_on_wkup_set(const stmdev_ctx_t * ctx,uint8_t val)5564 int32_t lsm6dsrx_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx,
5565 uint8_t val)
5566 {
5567 lsm6dsrx_wake_up_ths_t wake_up_ths;
5568 int32_t ret;
5569
5570 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS,
5571 (uint8_t *)&wake_up_ths, 1);
5572
5573 if (ret == 0)
5574 {
5575 wake_up_ths.usr_off_on_wu = (uint8_t)val;
5576 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_THS,
5577 (uint8_t *)&wake_up_ths, 1);
5578 }
5579
5580 return ret;
5581 }
5582
5583 /**
5584 * @brief Wake up duration event( 1LSb = 1 / ODR ).[get]
5585 *
5586 * @param ctx Read / write interface definitions.(ptr)
5587 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
5588 * @retval Interface status (MANDATORY: return 0 -> no Error).
5589 *
5590 */
lsm6dsrx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t * ctx,uint8_t * val)5591 int32_t lsm6dsrx_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx,
5592 uint8_t *val)
5593 {
5594 lsm6dsrx_wake_up_ths_t wake_up_ths;
5595 int32_t ret;
5596
5597 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS,
5598 (uint8_t *)&wake_up_ths, 1);
5599 *val = wake_up_ths.usr_off_on_wu;
5600
5601 return ret;
5602 }
5603
5604 /**
5605 * @brief Wake up duration event(1LSb = 1 / ODR).[set]
5606 *
5607 * @param ctx Read / write interface definitions.(ptr)
5608 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
5609 * @retval Interface status (MANDATORY: return 0 -> no Error).
5610 *
5611 */
lsm6dsrx_wkup_dur_set(const stmdev_ctx_t * ctx,uint8_t val)5612 int32_t lsm6dsrx_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
5613 {
5614 lsm6dsrx_wake_up_dur_t wake_up_dur;
5615 int32_t ret;
5616
5617 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
5618 (uint8_t *)&wake_up_dur, 1);
5619
5620 if (ret == 0)
5621 {
5622 wake_up_dur.wake_dur = (uint8_t)val;
5623 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
5624 (uint8_t *)&wake_up_dur, 1);
5625 }
5626
5627 return ret;
5628 }
5629
5630 /**
5631 * @brief Wake up duration event(1LSb = 1 / ODR).[get]
5632 *
5633 * @param ctx Read / write interface definitions.(ptr)
5634 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
5635 * @retval Interface status (MANDATORY: return 0 -> no Error).
5636 *
5637 */
lsm6dsrx_wkup_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)5638 int32_t lsm6dsrx_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
5639 {
5640 lsm6dsrx_wake_up_dur_t wake_up_dur;
5641 int32_t ret;
5642
5643 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
5644 (uint8_t *)&wake_up_dur, 1);
5645 *val = wake_up_dur.wake_dur;
5646
5647 return ret;
5648 }
5649
5650 /**
5651 * @}
5652 *
5653 */
5654
5655 /**
5656 * @defgroup LSM6DSRX_ Activity/Inactivity_detection
5657 * @brief This section groups all the functions concerning
5658 * activity/inactivity detection.
5659 * @{
5660 *
5661 */
5662
5663 /**
5664 * @brief Enables gyroscope Sleep mode.[set]
5665 *
5666 * @param ctx Read / write interface definitions.(ptr)
5667 * @param val Change the values of sleep_g in reg CTRL4_C
5668 * @retval Interface status (MANDATORY: return 0 -> no Error).
5669 *
5670 */
lsm6dsrx_gy_sleep_mode_set(const stmdev_ctx_t * ctx,uint8_t val)5671 int32_t lsm6dsrx_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
5672 {
5673 lsm6dsrx_ctrl4_c_t ctrl4_c;
5674 int32_t ret;
5675
5676 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C,
5677 (uint8_t *)&ctrl4_c, 1);
5678
5679 if (ret == 0)
5680 {
5681 ctrl4_c.sleep_g = (uint8_t)val;
5682 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C,
5683 (uint8_t *)&ctrl4_c, 1);
5684 }
5685
5686 return ret;
5687 }
5688
5689 /**
5690 * @brief Enables gyroscope Sleep mode.[get]
5691 *
5692 * @param ctx Read / write interface definitions.(ptr)
5693 * @param val Change the values of sleep_g in reg CTRL4_C
5694 * @retval Interface status (MANDATORY: return 0 -> no Error).
5695 *
5696 */
lsm6dsrx_gy_sleep_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)5697 int32_t lsm6dsrx_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
5698 {
5699 lsm6dsrx_ctrl4_c_t ctrl4_c;
5700 int32_t ret;
5701
5702 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C,
5703 (uint8_t *)&ctrl4_c, 1);
5704 *val = ctrl4_c.sleep_g;
5705
5706 return ret;
5707 }
5708
5709 /**
5710 * @brief Drives the sleep status instead of sleep change on INT pins
5711 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
5712 * are enabled).[set]
5713 *
5714 * @param ctx Read / write interface definitions.(ptr)
5715 * @param val Change the values of sleep_status_on_int in reg TAP_CFG0
5716 * @retval Interface status (MANDATORY: return 0 -> no Error).
5717 *
5718 */
lsm6dsrx_act_pin_notification_set(const stmdev_ctx_t * ctx,lsm6dsrx_sleep_status_on_int_t val)5719 int32_t lsm6dsrx_act_pin_notification_set(const stmdev_ctx_t *ctx,
5720 lsm6dsrx_sleep_status_on_int_t val)
5721 {
5722 lsm6dsrx_tap_cfg0_t tap_cfg0;
5723 int32_t ret;
5724
5725 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0,
5726 (uint8_t *)&tap_cfg0, 1);
5727
5728 if (ret == 0)
5729 {
5730 tap_cfg0. sleep_status_on_int = (uint8_t)val;
5731 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG0,
5732 (uint8_t *)&tap_cfg0, 1);
5733 }
5734
5735 return ret;
5736 }
5737
5738 /**
5739 * @brief Drives the sleep status instead of sleep change on INT pins
5740 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
5741 * are enabled).[get]
5742 *
5743 * @param ctx Read / write interface definitions.(ptr)
5744 * @param val Get the values of sleep_status_on_int in reg TAP_CFG0
5745 * @retval Interface status (MANDATORY: return 0 -> no Error).
5746 *
5747 */
lsm6dsrx_act_pin_notification_get(const stmdev_ctx_t * ctx,lsm6dsrx_sleep_status_on_int_t * val)5748 int32_t lsm6dsrx_act_pin_notification_get(const stmdev_ctx_t *ctx,
5749 lsm6dsrx_sleep_status_on_int_t *val)
5750 {
5751 lsm6dsrx_tap_cfg0_t tap_cfg0;
5752 int32_t ret;
5753
5754 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0,
5755 (uint8_t *)&tap_cfg0, 1);
5756
5757 switch (tap_cfg0. sleep_status_on_int)
5758 {
5759 case LSM6DSRX_DRIVE_SLEEP_CHG_EVENT:
5760 *val = LSM6DSRX_DRIVE_SLEEP_CHG_EVENT;
5761 break;
5762
5763 case LSM6DSRX_DRIVE_SLEEP_STATUS:
5764 *val = LSM6DSRX_DRIVE_SLEEP_STATUS;
5765 break;
5766
5767 default:
5768 *val = LSM6DSRX_DRIVE_SLEEP_CHG_EVENT;
5769 break;
5770 }
5771
5772 return ret;
5773 }
5774
5775 /**
5776 * @brief Enable inactivity function.[set]
5777 *
5778 * @param ctx Read / write interface definitions.(ptr)
5779 * @param val Change the values of inact_en in reg TAP_CFG2
5780 * @retval Interface status (MANDATORY: return 0 -> no Error).
5781 *
5782 */
lsm6dsrx_act_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_inact_en_t val)5783 int32_t lsm6dsrx_act_mode_set(const stmdev_ctx_t *ctx,
5784 lsm6dsrx_inact_en_t val)
5785 {
5786 lsm6dsrx_tap_cfg2_t tap_cfg2;
5787 int32_t ret;
5788
5789 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2,
5790 (uint8_t *)&tap_cfg2, 1);
5791
5792 if (ret == 0)
5793 {
5794 tap_cfg2.inact_en = (uint8_t)val;
5795 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG2,
5796 (uint8_t *)&tap_cfg2, 1);
5797 }
5798
5799 return ret;
5800 }
5801
5802 /**
5803 * @brief Enable inactivity function.[get]
5804 *
5805 * @param ctx Read / write interface definitions.(ptr)
5806 * @param val Get the values of inact_en in reg TAP_CFG2
5807 * @retval Interface status (MANDATORY: return 0 -> no Error).
5808 *
5809 */
lsm6dsrx_act_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_inact_en_t * val)5810 int32_t lsm6dsrx_act_mode_get(const stmdev_ctx_t *ctx,
5811 lsm6dsrx_inact_en_t *val)
5812 {
5813 lsm6dsrx_tap_cfg2_t tap_cfg2;
5814 int32_t ret;
5815
5816 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2,
5817 (uint8_t *)&tap_cfg2, 1);
5818
5819 switch (tap_cfg2.inact_en)
5820 {
5821 case LSM6DSRX_XL_AND_GY_NOT_AFFECTED:
5822 *val = LSM6DSRX_XL_AND_GY_NOT_AFFECTED;
5823 break;
5824
5825 case LSM6DSRX_XL_12Hz5_GY_NOT_AFFECTED:
5826 *val = LSM6DSRX_XL_12Hz5_GY_NOT_AFFECTED;
5827 break;
5828
5829 case LSM6DSRX_XL_12Hz5_GY_SLEEP:
5830 *val = LSM6DSRX_XL_12Hz5_GY_SLEEP;
5831 break;
5832
5833 case LSM6DSRX_XL_12Hz5_GY_PD:
5834 *val = LSM6DSRX_XL_12Hz5_GY_PD;
5835 break;
5836
5837 default:
5838 *val = LSM6DSRX_XL_AND_GY_NOT_AFFECTED;
5839 break;
5840 }
5841
5842 return ret;
5843 }
5844
5845 /**
5846 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
5847 *
5848 * @param ctx Read / write interface definitions.(ptr)
5849 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
5850 * @retval Interface status (MANDATORY: return 0 -> no Error).
5851 *
5852 */
lsm6dsrx_act_sleep_dur_set(const stmdev_ctx_t * ctx,uint8_t val)5853 int32_t lsm6dsrx_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
5854 {
5855 lsm6dsrx_wake_up_dur_t wake_up_dur;
5856 int32_t ret;
5857
5858 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
5859 (uint8_t *)&wake_up_dur, 1);
5860
5861 if (ret == 0)
5862 {
5863 wake_up_dur.sleep_dur = (uint8_t)val;
5864 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
5865 (uint8_t *)&wake_up_dur, 1);
5866 }
5867
5868 return ret;
5869 }
5870
5871 /**
5872 * @brief Duration to go in sleep mode.(1 LSb = 512 / ODR).[get]
5873 *
5874 * @param ctx Read / write interface definitions.(ptr)
5875 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
5876 * @retval Interface status (MANDATORY: return 0 -> no Error).
5877 *
5878 */
lsm6dsrx_act_sleep_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)5879 int32_t lsm6dsrx_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
5880 {
5881 lsm6dsrx_wake_up_dur_t wake_up_dur;
5882 int32_t ret;
5883
5884 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
5885 (uint8_t *)&wake_up_dur, 1);
5886 *val = wake_up_dur.sleep_dur;
5887
5888 return ret;
5889 }
5890
5891 /**
5892 * @}
5893 *
5894 */
5895
5896 /**
5897 * @defgroup LSM6DSRX_tap_generator
5898 * @brief This section groups all the functions that manage the
5899 * tap and double tap event generation.
5900 * @{
5901 *
5902 */
5903
5904 /**
5905 * @brief Enable Z direction in tap recognition.[set]
5906 *
5907 * @param ctx Read / write interface definitions.(ptr)
5908 * @param val Change the values of tap_z_en in reg TAP_CFG0
5909 * @retval Interface status (MANDATORY: return 0 -> no Error).
5910 *
5911 */
lsm6dsrx_tap_detection_on_z_set(const stmdev_ctx_t * ctx,uint8_t val)5912 int32_t lsm6dsrx_tap_detection_on_z_set(const stmdev_ctx_t *ctx,
5913 uint8_t val)
5914 {
5915 lsm6dsrx_tap_cfg0_t tap_cfg0;
5916 int32_t ret;
5917
5918 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0,
5919 (uint8_t *)&tap_cfg0, 1);
5920
5921 if (ret == 0)
5922 {
5923 tap_cfg0.tap_z_en = (uint8_t)val;
5924 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG0,
5925 (uint8_t *)&tap_cfg0, 1);
5926 }
5927
5928 return ret;
5929 }
5930
5931 /**
5932 * @brief Enable Z direction in tap recognition.[get]
5933 *
5934 * @param ctx Read / write interface definitions.(ptr)
5935 * @param val Change the values of tap_z_en in reg TAP_CFG0
5936 * @retval Interface status (MANDATORY: return 0 -> no Error).
5937 *
5938 */
lsm6dsrx_tap_detection_on_z_get(const stmdev_ctx_t * ctx,uint8_t * val)5939 int32_t lsm6dsrx_tap_detection_on_z_get(const stmdev_ctx_t *ctx,
5940 uint8_t *val)
5941 {
5942 lsm6dsrx_tap_cfg0_t tap_cfg0;
5943 int32_t ret;
5944
5945 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0,
5946 (uint8_t *)&tap_cfg0, 1);
5947 *val = tap_cfg0.tap_z_en;
5948
5949 return ret;
5950 }
5951
5952 /**
5953 * @brief Enable Y direction in tap recognition.[set]
5954 *
5955 * @param ctx Read / write interface definitions.(ptr)
5956 * @param val Change the values of tap_y_en in reg TAP_CFG0
5957 * @retval Interface status (MANDATORY: return 0 -> no Error).
5958 *
5959 */
lsm6dsrx_tap_detection_on_y_set(const stmdev_ctx_t * ctx,uint8_t val)5960 int32_t lsm6dsrx_tap_detection_on_y_set(const stmdev_ctx_t *ctx,
5961 uint8_t val)
5962 {
5963 lsm6dsrx_tap_cfg0_t tap_cfg0;
5964 int32_t ret;
5965
5966 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0,
5967 (uint8_t *)&tap_cfg0, 1);
5968
5969 if (ret == 0)
5970 {
5971 tap_cfg0.tap_y_en = (uint8_t)val;
5972 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG0,
5973 (uint8_t *)&tap_cfg0, 1);
5974 }
5975
5976 return ret;
5977 }
5978
5979 /**
5980 * @brief Enable Y direction in tap recognition.[get]
5981 *
5982 * @param ctx Read / write interface definitions.(ptr)
5983 * @param val Change the values of tap_y_en in reg TAP_CFG0
5984 * @retval Interface status (MANDATORY: return 0 -> no Error).
5985 *
5986 */
lsm6dsrx_tap_detection_on_y_get(const stmdev_ctx_t * ctx,uint8_t * val)5987 int32_t lsm6dsrx_tap_detection_on_y_get(const stmdev_ctx_t *ctx,
5988 uint8_t *val)
5989 {
5990 lsm6dsrx_tap_cfg0_t tap_cfg0;
5991 int32_t ret;
5992
5993 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0,
5994 (uint8_t *)&tap_cfg0, 1);
5995 *val = tap_cfg0.tap_y_en;
5996
5997 return ret;
5998 }
5999
6000 /**
6001 * @brief Enable X direction in tap recognition.[set]
6002 *
6003 * @param ctx Read / write interface definitions.(ptr)
6004 * @param val Change the values of tap_x_en in reg TAP_CFG0
6005 * @retval Interface status (MANDATORY: return 0 -> no Error).
6006 *
6007 */
lsm6dsrx_tap_detection_on_x_set(const stmdev_ctx_t * ctx,uint8_t val)6008 int32_t lsm6dsrx_tap_detection_on_x_set(const stmdev_ctx_t *ctx,
6009 uint8_t val)
6010 {
6011 lsm6dsrx_tap_cfg0_t tap_cfg0;
6012 int32_t ret;
6013
6014 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0,
6015 (uint8_t *)&tap_cfg0, 1);
6016
6017 if (ret == 0)
6018 {
6019 tap_cfg0.tap_x_en = (uint8_t)val;
6020 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG0,
6021 (uint8_t *)&tap_cfg0, 1);
6022 }
6023
6024 return ret;
6025 }
6026
6027 /**
6028 * @brief Enable X direction in tap recognition.[get]
6029 *
6030 * @param ctx Read / write interface definitions.(ptr)
6031 * @param val Change the values of tap_x_en in reg TAP_CFG0
6032 * @retval Interface status (MANDATORY: return 0 -> no Error).
6033 *
6034 */
lsm6dsrx_tap_detection_on_x_get(const stmdev_ctx_t * ctx,uint8_t * val)6035 int32_t lsm6dsrx_tap_detection_on_x_get(const stmdev_ctx_t *ctx,
6036 uint8_t *val)
6037 {
6038 lsm6dsrx_tap_cfg0_t tap_cfg0;
6039 int32_t ret;
6040
6041 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0,
6042 (uint8_t *)&tap_cfg0, 1);
6043 *val = tap_cfg0.tap_x_en;
6044
6045 return ret;
6046 }
6047
6048 /**
6049 * @brief X-axis tap recognition threshold.[set]
6050 *
6051 * @param ctx Read / write interface definitions.(ptr)
6052 * @param val Change the values of tap_ths_x in reg TAP_CFG1
6053 * @retval Interface status (MANDATORY: return 0 -> no Error).
6054 *
6055 */
lsm6dsrx_tap_threshold_x_set(const stmdev_ctx_t * ctx,uint8_t val)6056 int32_t lsm6dsrx_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val)
6057 {
6058 lsm6dsrx_tap_cfg1_t tap_cfg1;
6059 int32_t ret;
6060
6061 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG1,
6062 (uint8_t *)&tap_cfg1, 1);
6063
6064 if (ret == 0)
6065 {
6066 tap_cfg1.tap_ths_x = (uint8_t)val;
6067 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG1,
6068 (uint8_t *)&tap_cfg1, 1);
6069 }
6070
6071 return ret;
6072 }
6073
6074 /**
6075 * @brief X-axis tap recognition threshold.[get]
6076 *
6077 * @param ctx Read / write interface definitions.(ptr)
6078 * @param val Change the values of tap_ths_x in reg TAP_CFG1
6079 * @retval Interface status (MANDATORY: return 0 -> no Error).
6080 *
6081 */
lsm6dsrx_tap_threshold_x_get(const stmdev_ctx_t * ctx,uint8_t * val)6082 int32_t lsm6dsrx_tap_threshold_x_get(const stmdev_ctx_t *ctx,
6083 uint8_t *val)
6084 {
6085 lsm6dsrx_tap_cfg1_t tap_cfg1;
6086 int32_t ret;
6087
6088 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG1,
6089 (uint8_t *)&tap_cfg1, 1);
6090 *val = tap_cfg1.tap_ths_x;
6091
6092 return ret;
6093 }
6094
6095 /**
6096 * @brief Selection of axis priority for TAP detection.[set]
6097 *
6098 * @param ctx Read / write interface definitions.(ptr)
6099 * @param val Change the values of tap_priority in reg TAP_CFG1
6100 * @retval Interface status (MANDATORY: return 0 -> no Error).
6101 *
6102 */
lsm6dsrx_tap_axis_priority_set(const stmdev_ctx_t * ctx,lsm6dsrx_tap_priority_t val)6103 int32_t lsm6dsrx_tap_axis_priority_set(const stmdev_ctx_t *ctx,
6104 lsm6dsrx_tap_priority_t val)
6105 {
6106 lsm6dsrx_tap_cfg1_t tap_cfg1;
6107 int32_t ret;
6108
6109 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG1,
6110 (uint8_t *)&tap_cfg1, 1);
6111
6112 if (ret == 0)
6113 {
6114 tap_cfg1.tap_priority = (uint8_t)val;
6115 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG1,
6116 (uint8_t *)&tap_cfg1, 1);
6117 }
6118
6119 return ret;
6120 }
6121
6122 /**
6123 * @brief Selection of axis priority for TAP detection[get]
6124 *
6125 * @param ctx Read / write interface definitions.(ptr)
6126 * @param val Get the values of tap_priority in reg TAP_CFG1
6127 * @retval Interface status (MANDATORY: return 0 -> no Error).
6128 *
6129 */
lsm6dsrx_tap_axis_priority_get(const stmdev_ctx_t * ctx,lsm6dsrx_tap_priority_t * val)6130 int32_t lsm6dsrx_tap_axis_priority_get(const stmdev_ctx_t *ctx,
6131 lsm6dsrx_tap_priority_t *val)
6132 {
6133 lsm6dsrx_tap_cfg1_t tap_cfg1;
6134 int32_t ret;
6135
6136 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG1,
6137 (uint8_t *)&tap_cfg1, 1);
6138
6139 switch (tap_cfg1.tap_priority)
6140 {
6141 case LSM6DSRX_XYZ:
6142 *val = LSM6DSRX_XYZ;
6143 break;
6144
6145 case LSM6DSRX_YXZ:
6146 *val = LSM6DSRX_YXZ;
6147 break;
6148
6149 case LSM6DSRX_XZY:
6150 *val = LSM6DSRX_XZY;
6151 break;
6152
6153 case LSM6DSRX_ZYX:
6154 *val = LSM6DSRX_ZYX;
6155 break;
6156
6157 case LSM6DSRX_YZX:
6158 *val = LSM6DSRX_YZX;
6159 break;
6160
6161 case LSM6DSRX_ZXY:
6162 *val = LSM6DSRX_ZXY;
6163 break;
6164
6165 default:
6166 *val = LSM6DSRX_XYZ;
6167 break;
6168 }
6169
6170 return ret;
6171 }
6172
6173 /**
6174 * @brief Y-axis tap recognition threshold.[set]
6175 *
6176 * @param ctx Read / write interface definitions.(ptr)
6177 * @param val Change the values of tap_ths_y in reg TAP_CFG2
6178 * @retval Interface status (MANDATORY: return 0 -> no Error).
6179 *
6180 */
lsm6dsrx_tap_threshold_y_set(const stmdev_ctx_t * ctx,uint8_t val)6181 int32_t lsm6dsrx_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val)
6182 {
6183 lsm6dsrx_tap_cfg2_t tap_cfg2;
6184 int32_t ret;
6185
6186 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2,
6187 (uint8_t *)&tap_cfg2, 1);
6188
6189 if (ret == 0)
6190 {
6191 tap_cfg2.tap_ths_y = (uint8_t)val;
6192 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG2,
6193 (uint8_t *)&tap_cfg2, 1);
6194 }
6195
6196 return ret;
6197 }
6198
6199 /**
6200 * @brief Y-axis tap recognition threshold.[get]
6201 *
6202 * @param ctx Read / write interface definitions.(ptr)
6203 * @param val Change the values of tap_ths_y in reg TAP_CFG2
6204 * @retval Interface status (MANDATORY: return 0 -> no Error).
6205 *
6206 */
lsm6dsrx_tap_threshold_y_get(const stmdev_ctx_t * ctx,uint8_t * val)6207 int32_t lsm6dsrx_tap_threshold_y_get(const stmdev_ctx_t *ctx,
6208 uint8_t *val)
6209 {
6210 lsm6dsrx_tap_cfg2_t tap_cfg2;
6211 int32_t ret;
6212
6213 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2,
6214 (uint8_t *)&tap_cfg2, 1);
6215 *val = tap_cfg2.tap_ths_y;
6216
6217 return ret;
6218 }
6219
6220 /**
6221 * @brief Z-axis recognition threshold.[set]
6222 *
6223 * @param ctx Read / write interface definitions.(ptr)
6224 * @param val Change the values of tap_ths_z in reg TAP_THS_6D
6225 * @retval Interface status (MANDATORY: return 0 -> no Error).
6226 *
6227 */
lsm6dsrx_tap_threshold_z_set(const stmdev_ctx_t * ctx,uint8_t val)6228 int32_t lsm6dsrx_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val)
6229 {
6230 lsm6dsrx_tap_ths_6d_t tap_ths_6d;
6231 int32_t ret;
6232
6233 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D,
6234 (uint8_t *)&tap_ths_6d, 1);
6235
6236 if (ret == 0)
6237 {
6238 tap_ths_6d.tap_ths_z = (uint8_t)val;
6239 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_THS_6D,
6240 (uint8_t *)&tap_ths_6d, 1);
6241 }
6242
6243 return ret;
6244 }
6245
6246 /**
6247 * @brief Z-axis recognition threshold.[get]
6248 *
6249 * @param ctx Read / write interface definitions.(ptr)
6250 * @param val Change the values of tap_ths_z in reg TAP_THS_6D
6251 * @retval Interface status (MANDATORY: return 0 -> no Error).
6252 *
6253 */
lsm6dsrx_tap_threshold_z_get(const stmdev_ctx_t * ctx,uint8_t * val)6254 int32_t lsm6dsrx_tap_threshold_z_get(const stmdev_ctx_t *ctx,
6255 uint8_t *val)
6256 {
6257 lsm6dsrx_tap_ths_6d_t tap_ths_6d;
6258 int32_t ret;
6259
6260 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D,
6261 (uint8_t *)&tap_ths_6d, 1);
6262 *val = tap_ths_6d.tap_ths_z;
6263
6264 return ret;
6265 }
6266
6267 /**
6268 * @brief Maximum duration is the maximum time of an overthreshold signal
6269 * detection to be recognized as a tap event. The default value of
6270 * these bits is 00b which corresponds to 4*ODR_XL time.
6271 * If the SHOCK[1:0] bits are set to a different value, 1LSB
6272 * corresponds to 8*ODR_XL time.[set]
6273 *
6274 * @param ctx Read / write interface definitions.(ptr)
6275 * @param val Change the values of shock in reg INT_DUR2
6276 * @retval Interface status (MANDATORY: return 0 -> no Error).
6277 *
6278 */
lsm6dsrx_tap_shock_set(const stmdev_ctx_t * ctx,uint8_t val)6279 int32_t lsm6dsrx_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val)
6280 {
6281 lsm6dsrx_int_dur2_t int_dur2;
6282 int32_t ret;
6283
6284 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2,
6285 (uint8_t *)&int_dur2, 1);
6286
6287 if (ret == 0)
6288 {
6289 int_dur2.shock = (uint8_t)val;
6290 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_DUR2,
6291 (uint8_t *)&int_dur2, 1);
6292 }
6293
6294 return ret;
6295 }
6296
6297 /**
6298 * @brief Maximum duration is the maximum time of an overthreshold signal
6299 * detection to be recognized as a tap event. The default value of
6300 * these bits is 00b which corresponds to 4*ODR_XL time.
6301 * If the SHOCK[1:0] bits are set to a different value, 1LSB
6302 * corresponds to 8*ODR_XL time.[get]
6303 *
6304 * @param ctx Read / write interface definitions.(ptr)
6305 * @param val Change the values of shock in reg INT_DUR2
6306 * @retval Interface status (MANDATORY: return 0 -> no Error).
6307 *
6308 */
lsm6dsrx_tap_shock_get(const stmdev_ctx_t * ctx,uint8_t * val)6309 int32_t lsm6dsrx_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val)
6310 {
6311 lsm6dsrx_int_dur2_t int_dur2;
6312 int32_t ret;
6313
6314 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2,
6315 (uint8_t *)&int_dur2, 1);
6316 *val = int_dur2.shock;
6317
6318 return ret;
6319 }
6320
6321 /**
6322 * @brief Quiet time is the time after the first detected tap in which
6323 * there must not be any overthreshold event.
6324 * The default value of these bits is 00b which corresponds to
6325 * 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
6326 * value, 1LSB corresponds to 4*ODR_XL time.[set]
6327 *
6328 * @param ctx Read / write interface definitions.(ptr)
6329 * @param val Change the values of quiet in reg INT_DUR2
6330 * @retval Interface status (MANDATORY: return 0 -> no Error).
6331 *
6332 */
lsm6dsrx_tap_quiet_set(const stmdev_ctx_t * ctx,uint8_t val)6333 int32_t lsm6dsrx_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val)
6334 {
6335 lsm6dsrx_int_dur2_t int_dur2;
6336 int32_t ret;
6337
6338 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2,
6339 (uint8_t *)&int_dur2, 1);
6340
6341 if (ret == 0)
6342 {
6343 int_dur2.quiet = (uint8_t)val;
6344 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_DUR2,
6345 (uint8_t *)&int_dur2, 1);
6346 }
6347
6348 return ret;
6349 }
6350
6351 /**
6352 * @brief Quiet time is the time after the first detected tap in which
6353 * there must not be any overthreshold event.
6354 * The default value of these bits is 00b which corresponds to
6355 * 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
6356 * value, 1LSB corresponds to 4*ODR_XL time.[get]
6357 *
6358 * @param ctx Read / write interface definitions.(ptr)
6359 * @param val Change the values of quiet in reg INT_DUR2
6360 * @retval Interface status (MANDATORY: return 0 -> no Error).
6361 *
6362 */
lsm6dsrx_tap_quiet_get(const stmdev_ctx_t * ctx,uint8_t * val)6363 int32_t lsm6dsrx_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val)
6364 {
6365 lsm6dsrx_int_dur2_t int_dur2;
6366 int32_t ret;
6367
6368 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2,
6369 (uint8_t *)&int_dur2, 1);
6370 *val = int_dur2.quiet;
6371
6372 return ret;
6373 }
6374
6375 /**
6376 * @brief When double tap recognition is enabled, this register expresses
6377 * the maximum time between two consecutive detected taps to
6378 * determine a double tap event.
6379 * The default value of these bits is 0000b which corresponds to
6380 * 16*ODR_XL time.
6381 * If the DUR[3:0] bits are set to a different value, 1LSB
6382 * corresponds to 32*ODR_XL time.[set]
6383 *
6384 * @param ctx Read / write interface definitions.(ptr)
6385 * @param val Change the values of dur in reg INT_DUR2
6386 * @retval Interface status (MANDATORY: return 0 -> no Error).
6387 *
6388 */
lsm6dsrx_tap_dur_set(const stmdev_ctx_t * ctx,uint8_t val)6389 int32_t lsm6dsrx_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
6390 {
6391 lsm6dsrx_int_dur2_t int_dur2;
6392 int32_t ret;
6393
6394 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2,
6395 (uint8_t *)&int_dur2, 1);
6396
6397 if (ret == 0)
6398 {
6399 int_dur2.dur = (uint8_t)val;
6400 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_DUR2,
6401 (uint8_t *)&int_dur2, 1);
6402 }
6403
6404 return ret;
6405 }
6406
6407 /**
6408 * @brief When double tap recognition is enabled, this register expresses the
6409 * maximum time between two consecutive detected taps to determine
6410 * a double tap event. The default value of these bits is 0000b which
6411 * corresponds to 16*ODR_XL time. If the DUR[3:0] bits are set to
6412 * a different value, 1LSB corresponds to 32*ODR_XL time.[get]
6413 *
6414 * @param ctx Read / write interface definitions.(ptr)
6415 * @param val Change the values of dur in reg INT_DUR2
6416 * @retval Interface status (MANDATORY: return 0 -> no Error).
6417 *
6418 */
lsm6dsrx_tap_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)6419 int32_t lsm6dsrx_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
6420 {
6421 lsm6dsrx_int_dur2_t int_dur2;
6422 int32_t ret;
6423
6424 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2,
6425 (uint8_t *)&int_dur2, 1);
6426 *val = int_dur2.dur;
6427
6428 return ret;
6429 }
6430
6431 /**
6432 * @brief Single/double-tap event enable.[set]
6433 *
6434 * @param ctx Read / write interface definitions.(ptr)
6435 * @param val Change the values of single_double_tap in reg WAKE_UP_THS
6436 * @retval Interface status (MANDATORY: return 0 -> no Error).
6437 *
6438 */
lsm6dsrx_tap_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_single_double_tap_t val)6439 int32_t lsm6dsrx_tap_mode_set(const stmdev_ctx_t *ctx,
6440 lsm6dsrx_single_double_tap_t val)
6441 {
6442 lsm6dsrx_wake_up_ths_t wake_up_ths;
6443 int32_t ret;
6444
6445 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS,
6446 (uint8_t *)&wake_up_ths, 1);
6447
6448 if (ret == 0)
6449 {
6450 wake_up_ths.single_double_tap = (uint8_t)val;
6451 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_THS,
6452 (uint8_t *)&wake_up_ths, 1);
6453 }
6454
6455 return ret;
6456 }
6457
6458 /**
6459 * @brief Single/double-tap event enable.[get]
6460 *
6461 * @param ctx Read / write interface definitions.(ptr)
6462 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
6463 * @retval Interface status (MANDATORY: return 0 -> no Error).
6464 *
6465 */
lsm6dsrx_tap_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_single_double_tap_t * val)6466 int32_t lsm6dsrx_tap_mode_get(const stmdev_ctx_t *ctx,
6467 lsm6dsrx_single_double_tap_t *val)
6468 {
6469 lsm6dsrx_wake_up_ths_t wake_up_ths;
6470 int32_t ret;
6471
6472 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS,
6473 (uint8_t *)&wake_up_ths, 1);
6474
6475 switch (wake_up_ths.single_double_tap)
6476 {
6477 case LSM6DSRX_ONLY_SINGLE:
6478 *val = LSM6DSRX_ONLY_SINGLE;
6479 break;
6480
6481 case LSM6DSRX_BOTH_SINGLE_DOUBLE:
6482 *val = LSM6DSRX_BOTH_SINGLE_DOUBLE;
6483 break;
6484
6485 default:
6486 *val = LSM6DSRX_ONLY_SINGLE;
6487 break;
6488 }
6489
6490 return ret;
6491 }
6492
6493 /**
6494 * @}
6495 *
6496 */
6497
6498 /**
6499 * @defgroup LSM6DSRX_ Six_position_detection(6D/4D)
6500 * @brief This section groups all the functions concerning six
6501 * position detection (6D).
6502 * @{
6503 *
6504 */
6505
6506 /**
6507 * @brief Threshold for 4D/6D function.[set]
6508 *
6509 * @param ctx Read / write interface definitions.(ptr)
6510 * @param val Change the values of sixd_ths in reg TAP_THS_6D
6511 * @retval Interface status (MANDATORY: return 0 -> no Error).
6512 *
6513 */
lsm6dsrx_6d_threshold_set(const stmdev_ctx_t * ctx,lsm6dsrx_sixd_ths_t val)6514 int32_t lsm6dsrx_6d_threshold_set(const stmdev_ctx_t *ctx,
6515 lsm6dsrx_sixd_ths_t val)
6516 {
6517 lsm6dsrx_tap_ths_6d_t tap_ths_6d;
6518 int32_t ret;
6519
6520 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D,
6521 (uint8_t *)&tap_ths_6d, 1);
6522
6523 if (ret == 0)
6524 {
6525 tap_ths_6d.sixd_ths = (uint8_t)val;
6526 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_THS_6D,
6527 (uint8_t *)&tap_ths_6d, 1);
6528 }
6529
6530 return ret;
6531 }
6532
6533 /**
6534 * @brief Threshold for 4D/6D function.[get]
6535 *
6536 * @param ctx Read / write interface definitions.(ptr)
6537 * @param val Get the values of sixd_ths in reg TAP_THS_6D
6538 * @retval Interface status (MANDATORY: return 0 -> no Error).
6539 *
6540 */
lsm6dsrx_6d_threshold_get(const stmdev_ctx_t * ctx,lsm6dsrx_sixd_ths_t * val)6541 int32_t lsm6dsrx_6d_threshold_get(const stmdev_ctx_t *ctx,
6542 lsm6dsrx_sixd_ths_t *val)
6543 {
6544 lsm6dsrx_tap_ths_6d_t tap_ths_6d;
6545 int32_t ret;
6546
6547 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D,
6548 (uint8_t *)&tap_ths_6d, 1);
6549
6550 switch (tap_ths_6d.sixd_ths)
6551 {
6552 case LSM6DSRX_DEG_80:
6553 *val = LSM6DSRX_DEG_80;
6554 break;
6555
6556 case LSM6DSRX_DEG_70:
6557 *val = LSM6DSRX_DEG_70;
6558 break;
6559
6560 case LSM6DSRX_DEG_60:
6561 *val = LSM6DSRX_DEG_60;
6562 break;
6563
6564 case LSM6DSRX_DEG_50:
6565 *val = LSM6DSRX_DEG_50;
6566 break;
6567
6568 default:
6569 *val = LSM6DSRX_DEG_80;
6570 break;
6571 }
6572
6573 return ret;
6574 }
6575
6576 /**
6577 * @brief 4D orientation detection enable.[set]
6578 *
6579 * @param ctx Read / write interface definitions.(ptr)
6580 * @param val Change the values of d4d_en in reg TAP_THS_6D
6581 * @retval Interface status (MANDATORY: return 0 -> no Error).
6582 *
6583 */
lsm6dsrx_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)6584 int32_t lsm6dsrx_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
6585 {
6586 lsm6dsrx_tap_ths_6d_t tap_ths_6d;
6587 int32_t ret;
6588
6589 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D,
6590 (uint8_t *)&tap_ths_6d, 1);
6591
6592 if (ret == 0)
6593 {
6594 tap_ths_6d.d4d_en = (uint8_t)val;
6595 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_THS_6D,
6596 (uint8_t *)&tap_ths_6d, 1);
6597 }
6598
6599 return ret;
6600 }
6601
6602 /**
6603 * @brief 4D orientation detection enable.[get]
6604 *
6605 * @param ctx Read / write interface definitions.(ptr)
6606 * @param val Change the values of d4d_en in reg TAP_THS_6D
6607 * @retval Interface status (MANDATORY: return 0 -> no Error).
6608 *
6609 */
lsm6dsrx_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)6610 int32_t lsm6dsrx_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
6611 {
6612 lsm6dsrx_tap_ths_6d_t tap_ths_6d;
6613 int32_t ret;
6614
6615 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D,
6616 (uint8_t *)&tap_ths_6d, 1);
6617 *val = tap_ths_6d.d4d_en;
6618
6619 return ret;
6620 }
6621
6622 /**
6623 * @}
6624 *
6625 */
6626
6627 /**
6628 * @defgroup LSM6DSRX_free_fall
6629 * @brief This section group all the functions concerning the free
6630 * fall detection.
6631 * @{
6632 *
6633 */
6634
6635 /**
6636 * @brief Free fall threshold setting.[set]
6637 *
6638 * @param ctx Read / write interface definitions.(ptr)
6639 * @param val Change the values of ff_ths in reg FREE_FALL
6640 * @retval Interface status (MANDATORY: return 0 -> no Error).
6641 *
6642 */
lsm6dsrx_ff_threshold_set(const stmdev_ctx_t * ctx,lsm6dsrx_ff_ths_t val)6643 int32_t lsm6dsrx_ff_threshold_set(const stmdev_ctx_t *ctx,
6644 lsm6dsrx_ff_ths_t val)
6645 {
6646 lsm6dsrx_free_fall_t free_fall;
6647 int32_t ret;
6648
6649 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FREE_FALL,
6650 (uint8_t *)&free_fall, 1);
6651
6652 if (ret == 0)
6653 {
6654 free_fall.ff_ths = (uint8_t)val;
6655 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FREE_FALL,
6656 (uint8_t *)&free_fall, 1);
6657 }
6658
6659 return ret;
6660 }
6661
6662 /**
6663 * @brief Free fall threshold setting.[get]
6664 *
6665 * @param ctx Read / write interface definitions.(ptr)
6666 * @param val Get the values of ff_ths in reg FREE_FALL
6667 * @retval Interface status (MANDATORY: return 0 -> no Error).
6668 *
6669 */
lsm6dsrx_ff_threshold_get(const stmdev_ctx_t * ctx,lsm6dsrx_ff_ths_t * val)6670 int32_t lsm6dsrx_ff_threshold_get(const stmdev_ctx_t *ctx,
6671 lsm6dsrx_ff_ths_t *val)
6672 {
6673 lsm6dsrx_free_fall_t free_fall;
6674 int32_t ret;
6675
6676 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FREE_FALL,
6677 (uint8_t *)&free_fall, 1);
6678
6679 switch (free_fall.ff_ths)
6680 {
6681 case LSM6DSRX_FF_TSH_156mg:
6682 *val = LSM6DSRX_FF_TSH_156mg;
6683 break;
6684
6685 case LSM6DSRX_FF_TSH_219mg:
6686 *val = LSM6DSRX_FF_TSH_219mg;
6687 break;
6688
6689 case LSM6DSRX_FF_TSH_250mg:
6690 *val = LSM6DSRX_FF_TSH_250mg;
6691 break;
6692
6693 case LSM6DSRX_FF_TSH_312mg:
6694 *val = LSM6DSRX_FF_TSH_312mg;
6695 break;
6696
6697 case LSM6DSRX_FF_TSH_344mg:
6698 *val = LSM6DSRX_FF_TSH_344mg;
6699 break;
6700
6701 case LSM6DSRX_FF_TSH_406mg:
6702 *val = LSM6DSRX_FF_TSH_406mg;
6703 break;
6704
6705 case LSM6DSRX_FF_TSH_469mg:
6706 *val = LSM6DSRX_FF_TSH_469mg;
6707 break;
6708
6709 case LSM6DSRX_FF_TSH_500mg:
6710 *val = LSM6DSRX_FF_TSH_500mg;
6711 break;
6712
6713 default:
6714 *val = LSM6DSRX_FF_TSH_156mg;
6715 break;
6716 }
6717
6718 return ret;
6719 }
6720
6721 /**
6722 * @brief Free-fall duration event(1LSb = 1 / ODR).[set]
6723 *
6724 * @param ctx Read / write interface definitions.(ptr)
6725 * @param val Change the values of ff_dur in reg FREE_FALL
6726 * @retval Interface status (MANDATORY: return 0 -> no Error).
6727 *
6728 */
lsm6dsrx_ff_dur_set(const stmdev_ctx_t * ctx,uint8_t val)6729 int32_t lsm6dsrx_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
6730 {
6731 lsm6dsrx_wake_up_dur_t wake_up_dur;
6732 lsm6dsrx_free_fall_t free_fall;
6733 int32_t ret;
6734
6735 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
6736 (uint8_t *)&wake_up_dur, 1);
6737
6738 if (ret == 0)
6739 {
6740 wake_up_dur.ff_dur = (val & 0x20U) >> 5;
6741 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
6742 (uint8_t *)&wake_up_dur, 1);
6743 }
6744
6745 if (ret == 0)
6746 {
6747 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FREE_FALL,
6748 (uint8_t *)&free_fall, 1);
6749 }
6750
6751 if (ret == 0)
6752 {
6753 free_fall.ff_dur = val & 0x1FU;
6754 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FREE_FALL,
6755 (uint8_t *)&free_fall, 1);
6756 }
6757
6758 return ret;
6759 }
6760
6761 /**
6762 * @brief Free-fall duration event(1LSb = 1 / ODR).[get]
6763 *
6764 * @param ctx Read / write interface definitions.(ptr)
6765 * @param val Change the values of ff_dur in reg FREE_FALL
6766 * @retval Interface status (MANDATORY: return 0 -> no Error).
6767 *
6768 */
lsm6dsrx_ff_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)6769 int32_t lsm6dsrx_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
6770 {
6771 lsm6dsrx_wake_up_dur_t wake_up_dur;
6772 lsm6dsrx_free_fall_t free_fall;
6773 int32_t ret;
6774
6775 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
6776 (uint8_t *)&wake_up_dur, 1);
6777
6778 if (ret == 0)
6779 {
6780 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FREE_FALL,
6781 (uint8_t *)&free_fall, 1);
6782 }
6783
6784 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
6785
6786 return ret;
6787 }
6788
6789 /**
6790 * @}
6791 *
6792 */
6793
6794 /**
6795 * @defgroup LSM6DSRX_fifo
6796 * @brief This section group all the functions concerning
6797 * the fifo usage
6798 * @{
6799 *
6800 */
6801
6802 /**
6803 * @brief FIFO watermark level selection.[set]
6804 *
6805 * @param ctx Read / write interface definitions.(ptr)
6806 * @param val Change the values of wtm in reg FIFO_CTRL1
6807 * @retval Interface status (MANDATORY: return 0 -> no Error).
6808 *
6809 */
lsm6dsrx_fifo_watermark_set(const stmdev_ctx_t * ctx,uint16_t val)6810 int32_t lsm6dsrx_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val)
6811 {
6812 lsm6dsrx_fifo_ctrl1_t fifo_ctrl1;
6813 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
6814 int32_t ret;
6815
6816 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
6817 ret += lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
6818
6819 if (ret == 0)
6820 {
6821 fifo_ctrl1.wtm = (uint8_t)(val & 0xFFU);
6822 fifo_ctrl2.wtm = (uint8_t)(val / 256U) & 0x01U;
6823
6824 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
6825 ret += lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
6826 }
6827
6828 return ret;
6829 }
6830
6831 /**
6832 * @brief FIFO watermark level selection.[get]
6833 *
6834 * @param ctx Read / write interface definitions.(ptr)
6835 * @param val Change the values of wtm in reg FIFO_CTRL1
6836 * @retval Interface status (MANDATORY: return 0 -> no Error).
6837 *
6838 */
lsm6dsrx_fifo_watermark_get(const stmdev_ctx_t * ctx,uint16_t * val)6839 int32_t lsm6dsrx_fifo_watermark_get(const stmdev_ctx_t *ctx,
6840 uint16_t *val)
6841 {
6842 lsm6dsrx_fifo_ctrl1_t fifo_ctrl1;
6843 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
6844 int32_t ret;
6845
6846 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
6847 ret += lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
6848
6849 *val = fifo_ctrl2.wtm;
6850 *val = (*val * 256U) + fifo_ctrl1.wtm;;
6851
6852 return ret;
6853 }
6854
6855 /**
6856 * @brief FIFO compression feature initialization request.[set].
6857 *
6858 * @param ctx Read / write interface definitions.(ptr)
6859 * @param val Change the values of FIFO_COMPR_INIT in reg EMB_FUNC_INIT_B
6860 * @retval Interface status (MANDATORY: return 0 -> no Error).
6861 *
6862 */
lsm6dsrx_compression_algo_init_set(const stmdev_ctx_t * ctx,uint8_t val)6863 int32_t lsm6dsrx_compression_algo_init_set(const stmdev_ctx_t *ctx,
6864 uint8_t val)
6865 {
6866 lsm6dsrx_emb_func_init_b_t emb_func_init_b;
6867 int32_t ret;
6868
6869 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
6870
6871 if (ret == 0)
6872 {
6873 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
6874 (uint8_t *)&emb_func_init_b, 1);
6875 }
6876
6877 if (ret == 0)
6878 {
6879 emb_func_init_b.fifo_compr_init = (uint8_t)val;
6880 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
6881 (uint8_t *)&emb_func_init_b, 1);
6882 }
6883
6884 if (ret == 0)
6885 {
6886 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
6887 }
6888
6889 return ret;
6890 }
6891
6892 /**
6893 * @brief FIFO compression feature initialization request.[get].
6894 *
6895 * @param ctx Read / write interface definitions.(ptr)
6896 * @param val change the values of FIFO_COMPR_INIT in
6897 * reg EMB_FUNC_INIT_B
6898 * @retval Interface status (MANDATORY: return 0 -> no Error).
6899 *
6900 */
lsm6dsrx_compression_algo_init_get(const stmdev_ctx_t * ctx,uint8_t * val)6901 int32_t lsm6dsrx_compression_algo_init_get(const stmdev_ctx_t *ctx,
6902 uint8_t *val)
6903 {
6904 lsm6dsrx_emb_func_init_b_t emb_func_init_b;
6905 int32_t ret;
6906
6907 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
6908
6909 if (ret == 0)
6910 {
6911 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
6912 (uint8_t *)&emb_func_init_b, 1);
6913 }
6914
6915 if (ret == 0)
6916 {
6917 *val = emb_func_init_b.fifo_compr_init;
6918 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
6919 }
6920
6921 return ret;
6922 }
6923
6924 /**
6925 * @brief Enable and configure compression algo.[set]
6926 *
6927 * @param ctx Read / write interface definitions.(ptr)
6928 * @param val Change the values of uncoptr_rate in reg FIFO_CTRL2
6929 * @retval Interface status (MANDATORY: return 0 -> no Error).
6930 *
6931 */
lsm6dsrx_compression_algo_set(const stmdev_ctx_t * ctx,lsm6dsrx_uncoptr_rate_t val)6932 int32_t lsm6dsrx_compression_algo_set(const stmdev_ctx_t *ctx,
6933 lsm6dsrx_uncoptr_rate_t val)
6934 {
6935 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
6936 lsm6dsrx_emb_func_en_b_t emb_func_en_b;
6937 int32_t ret;
6938
6939 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
6940
6941 if (ret == 0)
6942 {
6943 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
6944 (uint8_t *)&emb_func_en_b, 1);
6945 }
6946
6947 if (ret == 0)
6948 {
6949 emb_func_en_b.fifo_compr_en = ((uint8_t)val & 0x04U) >> 2;
6950 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
6951 (uint8_t *)&emb_func_en_b, 1);
6952 }
6953
6954 if (ret == 0)
6955 {
6956 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
6957 }
6958
6959 if (ret == 0)
6960 {
6961 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
6962 (uint8_t *)&fifo_ctrl2, 1);
6963 }
6964
6965 if (ret == 0)
6966 {
6967 fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
6968 fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
6969 }
6970
6971 if (ret == 0)
6972 {
6973 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL2,
6974 (uint8_t *)&fifo_ctrl2, 1);
6975 }
6976
6977 return ret;
6978 }
6979
6980 /**
6981 * @brief Enable and configure compression algo.[get]
6982 *
6983 * @param ctx Read / write interface definitions.(ptr)
6984 * @param val Get the values of uncoptr_rate in reg FIFO_CTRL2
6985 * @retval Interface status (MANDATORY: return 0 -> no Error).
6986 *
6987 */
lsm6dsrx_compression_algo_get(const stmdev_ctx_t * ctx,lsm6dsrx_uncoptr_rate_t * val)6988 int32_t lsm6dsrx_compression_algo_get(const stmdev_ctx_t *ctx,
6989 lsm6dsrx_uncoptr_rate_t *val)
6990 {
6991 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
6992 int32_t ret;
6993
6994 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
6995 (uint8_t *)&fifo_ctrl2, 1);
6996
6997 switch ((fifo_ctrl2.fifo_compr_rt_en << 2) +
6998 fifo_ctrl2.uncoptr_rate)
6999 {
7000 case LSM6DSRX_CMP_DISABLE:
7001 *val = LSM6DSRX_CMP_DISABLE;
7002 break;
7003
7004 case LSM6DSRX_CMP_ALWAYS:
7005 *val = LSM6DSRX_CMP_ALWAYS;
7006 break;
7007
7008 case LSM6DSRX_CMP_8_TO_1:
7009 *val = LSM6DSRX_CMP_8_TO_1;
7010 break;
7011
7012 case LSM6DSRX_CMP_16_TO_1:
7013 *val = LSM6DSRX_CMP_16_TO_1;
7014 break;
7015
7016 case LSM6DSRX_CMP_32_TO_1:
7017 *val = LSM6DSRX_CMP_32_TO_1;
7018 break;
7019
7020 default:
7021 *val = LSM6DSRX_CMP_DISABLE;
7022 break;
7023 }
7024
7025 return ret;
7026 }
7027
7028 /**
7029 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
7030 *
7031 * @param ctx Read / write interface definitions.(ptr)
7032 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
7033 * @retval Interface status (MANDATORY: return 0 -> no Error).
7034 *
7035 */
lsm6dsrx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t * ctx,uint8_t val)7036 int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx,
7037 uint8_t val)
7038 {
7039 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
7040 int32_t ret;
7041
7042 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
7043 (uint8_t *)&fifo_ctrl2, 1);
7044
7045 if (ret == 0)
7046 {
7047 fifo_ctrl2.odrchg_en = (uint8_t)val;
7048 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL2,
7049 (uint8_t *)&fifo_ctrl2, 1);
7050 }
7051
7052 return ret;
7053 }
7054
7055 /**
7056 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
7057 *
7058 * @param ctx Read / write interface definitions.(ptr)
7059 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
7060 * @retval Interface status (MANDATORY: return 0 -> no Error).
7061 *
7062 */
lsm6dsrx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t * ctx,uint8_t * val)7063 int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx,
7064 uint8_t *val)
7065 {
7066 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
7067 int32_t ret;
7068
7069 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
7070 (uint8_t *)&fifo_ctrl2, 1);
7071 *val = fifo_ctrl2.odrchg_en;
7072
7073 return ret;
7074 }
7075
7076 /**
7077 * @brief Enables/Disables compression algorithm runtime[set]
7078 *
7079 * @param ctx Read / write interface definitions.(ptr)
7080 * @param val Change the values of fifo_compr_rt_en in reg FIFO_CTRL2
7081 * @retval Interface status (MANDATORY: return 0 -> no Error).
7082 *
7083 */
lsm6dsrx_compression_algo_real_time_set(const stmdev_ctx_t * ctx,uint8_t val)7084 int32_t lsm6dsrx_compression_algo_real_time_set(const stmdev_ctx_t *ctx,
7085 uint8_t val)
7086 {
7087 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
7088 int32_t ret;
7089
7090 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
7091 (uint8_t *)&fifo_ctrl2, 1);
7092
7093 if (ret == 0)
7094 {
7095 fifo_ctrl2.fifo_compr_rt_en = (uint8_t)val;
7096 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL2,
7097 (uint8_t *)&fifo_ctrl2, 1);
7098 }
7099
7100 return ret;
7101 }
7102
7103 /**
7104 * @brief Enables/Disables compression algorithm runtime.[get]
7105 *
7106 * @param ctx Read / write interface definitions.(ptr)
7107 * @param val Change the values of fifo_compr_rt_en in reg FIFO_CTRL2
7108 * @retval Interface status (MANDATORY: return 0 -> no Error).
7109 *
7110 */
lsm6dsrx_compression_algo_real_time_get(const stmdev_ctx_t * ctx,uint8_t * val)7111 int32_t lsm6dsrx_compression_algo_real_time_get(const stmdev_ctx_t *ctx,
7112 uint8_t *val)
7113 {
7114 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
7115 int32_t ret;
7116
7117 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
7118 (uint8_t *)&fifo_ctrl2, 1);
7119 *val = fifo_ctrl2.fifo_compr_rt_en;
7120
7121 return ret;
7122 }
7123
7124 /**
7125 * @brief Sensing chain FIFO stop values memorization at threshold
7126 * level.[set]
7127 *
7128 * @param ctx Read / write interface definitions.(ptr)
7129 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
7130 * @retval Interface status (MANDATORY: return 0 -> no Error).
7131 *
7132 */
lsm6dsrx_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)7133 int32_t lsm6dsrx_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx,
7134 uint8_t val)
7135 {
7136 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
7137 int32_t ret;
7138
7139 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
7140 (uint8_t *)&fifo_ctrl2, 1);
7141
7142 if (ret == 0)
7143 {
7144 fifo_ctrl2.stop_on_wtm = (uint8_t)val;
7145 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL2,
7146 (uint8_t *)&fifo_ctrl2, 1);
7147 }
7148
7149 return ret;
7150 }
7151
7152 /**
7153 * @brief Sensing chain FIFO stop values memorization at threshold
7154 * level.[get]
7155 *
7156 * @param ctx Read / write interface definitions.(ptr)
7157 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
7158 * @retval Interface status (MANDATORY: return 0 -> no Error).
7159 *
7160 */
lsm6dsrx_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)7161 int32_t lsm6dsrx_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx,
7162 uint8_t *val)
7163 {
7164 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
7165 int32_t ret;
7166
7167 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
7168 (uint8_t *)&fifo_ctrl2, 1);
7169 *val = fifo_ctrl2.stop_on_wtm;
7170
7171 return ret;
7172 }
7173
7174 /**
7175 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7176 * for accelerometer data.[set]
7177 *
7178 * @param ctx Read / write interface definitions.(ptr)
7179 * @param val Change the values of bdr_xl in reg FIFO_CTRL3
7180 * @retval Interface status (MANDATORY: return 0 -> no Error).
7181 *
7182 */
lsm6dsrx_fifo_xl_batch_set(const stmdev_ctx_t * ctx,lsm6dsrx_bdr_xl_t val)7183 int32_t lsm6dsrx_fifo_xl_batch_set(const stmdev_ctx_t *ctx,
7184 lsm6dsrx_bdr_xl_t val)
7185 {
7186 lsm6dsrx_fifo_ctrl3_t fifo_ctrl3;
7187 int32_t ret;
7188
7189 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL3,
7190 (uint8_t *)&fifo_ctrl3, 1);
7191
7192 if (ret == 0)
7193 {
7194 fifo_ctrl3.bdr_xl = (uint8_t)val;
7195 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL3,
7196 (uint8_t *)&fifo_ctrl3, 1);
7197 }
7198
7199 return ret;
7200 }
7201
7202 /**
7203 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7204 * for accelerometer data.[get]
7205 *
7206 * @param ctx Read / write interface definitions.(ptr)
7207 * @param val Get the values of bdr_xl in reg FIFO_CTRL3
7208 * @retval Interface status (MANDATORY: return 0 -> no Error).
7209 *
7210 */
lsm6dsrx_fifo_xl_batch_get(const stmdev_ctx_t * ctx,lsm6dsrx_bdr_xl_t * val)7211 int32_t lsm6dsrx_fifo_xl_batch_get(const stmdev_ctx_t *ctx,
7212 lsm6dsrx_bdr_xl_t *val)
7213 {
7214 lsm6dsrx_fifo_ctrl3_t fifo_ctrl3;
7215 int32_t ret;
7216
7217 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL3,
7218 (uint8_t *)&fifo_ctrl3, 1);
7219
7220 switch (fifo_ctrl3.bdr_xl)
7221 {
7222 case LSM6DSRX_XL_NOT_BATCHED:
7223 *val = LSM6DSRX_XL_NOT_BATCHED;
7224 break;
7225
7226 case LSM6DSRX_XL_BATCHED_AT_12Hz5:
7227 *val = LSM6DSRX_XL_BATCHED_AT_12Hz5;
7228 break;
7229
7230 case LSM6DSRX_XL_BATCHED_AT_26Hz:
7231 *val = LSM6DSRX_XL_BATCHED_AT_26Hz;
7232 break;
7233
7234 case LSM6DSRX_XL_BATCHED_AT_52Hz:
7235 *val = LSM6DSRX_XL_BATCHED_AT_52Hz;
7236 break;
7237
7238 case LSM6DSRX_XL_BATCHED_AT_104Hz:
7239 *val = LSM6DSRX_XL_BATCHED_AT_104Hz;
7240 break;
7241
7242 case LSM6DSRX_XL_BATCHED_AT_208Hz:
7243 *val = LSM6DSRX_XL_BATCHED_AT_208Hz;
7244 break;
7245
7246 case LSM6DSRX_XL_BATCHED_AT_417Hz:
7247 *val = LSM6DSRX_XL_BATCHED_AT_417Hz;
7248 break;
7249
7250 case LSM6DSRX_XL_BATCHED_AT_833Hz:
7251 *val = LSM6DSRX_XL_BATCHED_AT_833Hz;
7252 break;
7253
7254 case LSM6DSRX_XL_BATCHED_AT_1667Hz:
7255 *val = LSM6DSRX_XL_BATCHED_AT_1667Hz;
7256 break;
7257
7258 case LSM6DSRX_XL_BATCHED_AT_3333Hz:
7259 *val = LSM6DSRX_XL_BATCHED_AT_3333Hz;
7260 break;
7261
7262 case LSM6DSRX_XL_BATCHED_AT_6667Hz:
7263 *val = LSM6DSRX_XL_BATCHED_AT_6667Hz;
7264 break;
7265
7266 case LSM6DSRX_XL_BATCHED_AT_6Hz5:
7267 *val = LSM6DSRX_XL_BATCHED_AT_6Hz5;
7268 break;
7269
7270 default:
7271 *val = LSM6DSRX_XL_NOT_BATCHED;
7272 break;
7273 }
7274
7275 return ret;
7276 }
7277
7278 /**
7279 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7280 * for gyroscope data.[set]
7281 *
7282 * @param ctx Read / write interface definitions.(ptr)
7283 * @param val Change the values of bdr_gy in reg FIFO_CTRL3
7284 * @retval Interface status (MANDATORY: return 0 -> no Error).
7285 *
7286 */
lsm6dsrx_fifo_gy_batch_set(const stmdev_ctx_t * ctx,lsm6dsrx_bdr_gy_t val)7287 int32_t lsm6dsrx_fifo_gy_batch_set(const stmdev_ctx_t *ctx,
7288 lsm6dsrx_bdr_gy_t val)
7289 {
7290 lsm6dsrx_fifo_ctrl3_t fifo_ctrl3;
7291 int32_t ret;
7292
7293 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL3,
7294 (uint8_t *)&fifo_ctrl3, 1);
7295
7296 if (ret == 0)
7297 {
7298 fifo_ctrl3.bdr_gy = (uint8_t)val;
7299 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL3,
7300 (uint8_t *)&fifo_ctrl3, 1);
7301 }
7302
7303 return ret;
7304 }
7305
7306 /**
7307 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7308 * for gyroscope data.[get]
7309 *
7310 * @param ctx Read / write interface definitions.(ptr)
7311 * @param val Get the values of bdr_gy in reg FIFO_CTRL3
7312 * @retval Interface status (MANDATORY: return 0 -> no Error).
7313 *
7314 */
lsm6dsrx_fifo_gy_batch_get(const stmdev_ctx_t * ctx,lsm6dsrx_bdr_gy_t * val)7315 int32_t lsm6dsrx_fifo_gy_batch_get(const stmdev_ctx_t *ctx,
7316 lsm6dsrx_bdr_gy_t *val)
7317 {
7318 lsm6dsrx_fifo_ctrl3_t fifo_ctrl3;
7319 int32_t ret;
7320
7321 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL3,
7322 (uint8_t *)&fifo_ctrl3, 1);
7323
7324 switch (fifo_ctrl3.bdr_gy)
7325 {
7326 case LSM6DSRX_GY_NOT_BATCHED:
7327 *val = LSM6DSRX_GY_NOT_BATCHED;
7328 break;
7329
7330 case LSM6DSRX_GY_BATCHED_AT_12Hz5:
7331 *val = LSM6DSRX_GY_BATCHED_AT_12Hz5;
7332 break;
7333
7334 case LSM6DSRX_GY_BATCHED_AT_26Hz:
7335 *val = LSM6DSRX_GY_BATCHED_AT_26Hz;
7336 break;
7337
7338 case LSM6DSRX_GY_BATCHED_AT_52Hz:
7339 *val = LSM6DSRX_GY_BATCHED_AT_52Hz;
7340 break;
7341
7342 case LSM6DSRX_GY_BATCHED_AT_104Hz:
7343 *val = LSM6DSRX_GY_BATCHED_AT_104Hz;
7344 break;
7345
7346 case LSM6DSRX_GY_BATCHED_AT_208Hz:
7347 *val = LSM6DSRX_GY_BATCHED_AT_208Hz;
7348 break;
7349
7350 case LSM6DSRX_GY_BATCHED_AT_417Hz:
7351 *val = LSM6DSRX_GY_BATCHED_AT_417Hz;
7352 break;
7353
7354 case LSM6DSRX_GY_BATCHED_AT_833Hz:
7355 *val = LSM6DSRX_GY_BATCHED_AT_833Hz;
7356 break;
7357
7358 case LSM6DSRX_GY_BATCHED_AT_1667Hz:
7359 *val = LSM6DSRX_GY_BATCHED_AT_1667Hz;
7360 break;
7361
7362 case LSM6DSRX_GY_BATCHED_AT_3333Hz:
7363 *val = LSM6DSRX_GY_BATCHED_AT_3333Hz;
7364 break;
7365
7366 case LSM6DSRX_GY_BATCHED_AT_6667Hz:
7367 *val = LSM6DSRX_GY_BATCHED_AT_6667Hz;
7368 break;
7369
7370 case LSM6DSRX_GY_BATCHED_6Hz5:
7371 *val = LSM6DSRX_GY_BATCHED_6Hz5;
7372 break;
7373
7374 default:
7375 *val = LSM6DSRX_GY_NOT_BATCHED;
7376 break;
7377 }
7378
7379 return ret;
7380 }
7381
7382 /**
7383 * @brief FIFO mode selection.[set]
7384 *
7385 * @param ctx Read / write interface definitions.(ptr)
7386 * @param val Change the values of fifo_mode in reg FIFO_CTRL4
7387 * @retval Interface status (MANDATORY: return 0 -> no Error).
7388 *
7389 */
lsm6dsrx_fifo_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_fifo_mode_t val)7390 int32_t lsm6dsrx_fifo_mode_set(const stmdev_ctx_t *ctx,
7391 lsm6dsrx_fifo_mode_t val)
7392 {
7393 lsm6dsrx_fifo_ctrl4_t fifo_ctrl4;
7394 int32_t ret;
7395
7396 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4,
7397 (uint8_t *)&fifo_ctrl4, 1);
7398
7399 if (ret == 0)
7400 {
7401 fifo_ctrl4.fifo_mode = (uint8_t)val;
7402 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL4,
7403 (uint8_t *)&fifo_ctrl4, 1);
7404 }
7405
7406 return ret;
7407 }
7408
7409 /**
7410 * @brief FIFO mode selection.[get]
7411 *
7412 * @param ctx Read / write interface definitions.(ptr)
7413 * @param val Get the values of fifo_mode in reg FIFO_CTRL4
7414 * @retval Interface status (MANDATORY: return 0 -> no Error).
7415 *
7416 */
lsm6dsrx_fifo_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_fifo_mode_t * val)7417 int32_t lsm6dsrx_fifo_mode_get(const stmdev_ctx_t *ctx,
7418 lsm6dsrx_fifo_mode_t *val)
7419 {
7420 lsm6dsrx_fifo_ctrl4_t fifo_ctrl4;
7421 int32_t ret;
7422
7423 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4,
7424 (uint8_t *)&fifo_ctrl4, 1);
7425
7426 switch (fifo_ctrl4.fifo_mode)
7427 {
7428 case LSM6DSRX_BYPASS_MODE:
7429 *val = LSM6DSRX_BYPASS_MODE;
7430 break;
7431
7432 case LSM6DSRX_FIFO_MODE:
7433 *val = LSM6DSRX_FIFO_MODE;
7434 break;
7435
7436 case LSM6DSRX_STREAM_TO_FIFO_MODE:
7437 *val = LSM6DSRX_STREAM_TO_FIFO_MODE;
7438 break;
7439
7440 case LSM6DSRX_BYPASS_TO_STREAM_MODE:
7441 *val = LSM6DSRX_BYPASS_TO_STREAM_MODE;
7442 break;
7443
7444 case LSM6DSRX_STREAM_MODE:
7445 *val = LSM6DSRX_STREAM_MODE;
7446 break;
7447
7448 case LSM6DSRX_BYPASS_TO_FIFO_MODE:
7449 *val = LSM6DSRX_BYPASS_TO_FIFO_MODE;
7450 break;
7451
7452 default:
7453 *val = LSM6DSRX_BYPASS_MODE;
7454 break;
7455 }
7456
7457 return ret;
7458 }
7459
7460 /**
7461 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7462 * for temperature data.[set]
7463 *
7464 * @param ctx Read / write interface definitions.(ptr)
7465 * @param val Change the values of odr_t_batch in reg FIFO_CTRL4
7466 * @retval Interface status (MANDATORY: return 0 -> no Error).
7467 *
7468 */
lsm6dsrx_fifo_temp_batch_set(const stmdev_ctx_t * ctx,lsm6dsrx_odr_t_batch_t val)7469 int32_t lsm6dsrx_fifo_temp_batch_set(const stmdev_ctx_t *ctx,
7470 lsm6dsrx_odr_t_batch_t val)
7471 {
7472 lsm6dsrx_fifo_ctrl4_t fifo_ctrl4;
7473 int32_t ret;
7474
7475 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4,
7476 (uint8_t *)&fifo_ctrl4, 1);
7477
7478 if (ret == 0)
7479 {
7480 fifo_ctrl4.odr_t_batch = (uint8_t)val;
7481 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL4,
7482 (uint8_t *)&fifo_ctrl4, 1);
7483 }
7484
7485 return ret;
7486 }
7487
7488 /**
7489 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7490 * for temperature data.[get]
7491 *
7492 * @param ctx Read / write interface definitions.(ptr)
7493 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4
7494 * @retval Interface status (MANDATORY: return 0 -> no Error).
7495 *
7496 */
lsm6dsrx_fifo_temp_batch_get(const stmdev_ctx_t * ctx,lsm6dsrx_odr_t_batch_t * val)7497 int32_t lsm6dsrx_fifo_temp_batch_get(const stmdev_ctx_t *ctx,
7498 lsm6dsrx_odr_t_batch_t *val)
7499 {
7500 lsm6dsrx_fifo_ctrl4_t fifo_ctrl4;
7501 int32_t ret;
7502
7503 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4,
7504 (uint8_t *)&fifo_ctrl4, 1);
7505
7506 switch (fifo_ctrl4.odr_t_batch)
7507 {
7508 case LSM6DSRX_TEMP_NOT_BATCHED:
7509 *val = LSM6DSRX_TEMP_NOT_BATCHED;
7510 break;
7511
7512 case LSM6DSRX_TEMP_BATCHED_AT_52Hz:
7513 *val = LSM6DSRX_TEMP_BATCHED_AT_52Hz;
7514 break;
7515
7516 case LSM6DSRX_TEMP_BATCHED_AT_12Hz5:
7517 *val = LSM6DSRX_TEMP_BATCHED_AT_12Hz5;
7518 break;
7519
7520 case LSM6DSRX_TEMP_BATCHED_AT_1Hz6:
7521 *val = LSM6DSRX_TEMP_BATCHED_AT_1Hz6;
7522 break;
7523
7524 default:
7525 *val = LSM6DSRX_TEMP_NOT_BATCHED;
7526 break;
7527 }
7528
7529 return ret;
7530 }
7531
7532 /**
7533 * @brief Selects decimation for timestamp batching in FIFO.
7534 * Writing rate will be the maximum rate between XL and
7535 * GYRO BDR divided by decimation decoder.[set]
7536 *
7537 * @param ctx Read / write interface definitions.(ptr)
7538 * @param val Change the values of odr_ts_batch in reg FIFO_CTRL4
7539 * @retval Interface status (MANDATORY: return 0 -> no Error).
7540 *
7541 */
lsm6dsrx_fifo_timestamp_decimation_set(const stmdev_ctx_t * ctx,lsm6dsrx_odr_ts_batch_t val)7542 int32_t lsm6dsrx_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx,
7543 lsm6dsrx_odr_ts_batch_t val)
7544 {
7545 lsm6dsrx_fifo_ctrl4_t fifo_ctrl4;
7546 int32_t ret;
7547
7548 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4,
7549 (uint8_t *)&fifo_ctrl4, 1);
7550
7551 if (ret == 0)
7552 {
7553 fifo_ctrl4.odr_ts_batch = (uint8_t)val;
7554 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL4,
7555 (uint8_t *)&fifo_ctrl4, 1);
7556 }
7557
7558 return ret;
7559 }
7560
7561 /**
7562 * @brief Selects decimation for timestamp batching in FIFO.
7563 * Writing rate will be the maximum rate between XL and
7564 * GYRO BDR divided by decimation decoder.[get]
7565 *
7566 * @param ctx Read / write interface definitions.(ptr)
7567 * @param val Get the values of odr_ts_batch in reg
7568 * FIFO_CTRL4
7569 * @retval Interface status (MANDATORY: return 0 -> no Error).
7570 *
7571 */
lsm6dsrx_fifo_timestamp_decimation_get(const stmdev_ctx_t * ctx,lsm6dsrx_odr_ts_batch_t * val)7572 int32_t lsm6dsrx_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx,
7573 lsm6dsrx_odr_ts_batch_t *val)
7574 {
7575 lsm6dsrx_fifo_ctrl4_t fifo_ctrl4;
7576 int32_t ret;
7577
7578 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4,
7579 (uint8_t *)&fifo_ctrl4, 1);
7580
7581 switch (fifo_ctrl4.odr_ts_batch)
7582 {
7583 case LSM6DSRX_NO_DECIMATION:
7584 *val = LSM6DSRX_NO_DECIMATION;
7585 break;
7586
7587 case LSM6DSRX_DEC_1:
7588 *val = LSM6DSRX_DEC_1;
7589 break;
7590
7591 case LSM6DSRX_DEC_8:
7592 *val = LSM6DSRX_DEC_8;
7593 break;
7594
7595 case LSM6DSRX_DEC_32:
7596 *val = LSM6DSRX_DEC_32;
7597 break;
7598
7599 default:
7600 *val = LSM6DSRX_NO_DECIMATION;
7601 break;
7602 }
7603
7604 return ret;
7605 }
7606
7607 /**
7608 * @brief Selects the trigger for the internal counter of batching events
7609 * between XL and gyro.[set]
7610 *
7611 * @param ctx Read / write interface definitions.(ptr)
7612 * @param val Change the values of trig_counter_bdr in
7613 * reg COUNTER_BDR_REG1
7614 * @retval Interface status (MANDATORY: return 0 -> no Error).
7615 *
7616 */
lsm6dsrx_fifo_cnt_event_batch_set(const stmdev_ctx_t * ctx,lsm6dsrx_trig_counter_bdr_t val)7617 int32_t lsm6dsrx_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx,
7618 lsm6dsrx_trig_counter_bdr_t val)
7619 {
7620 lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
7621 int32_t ret;
7622
7623 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
7624 (uint8_t *)&counter_bdr_reg1, 1);
7625
7626 if (ret == 0)
7627 {
7628 counter_bdr_reg1.trig_counter_bdr = (uint8_t)val;
7629 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
7630 (uint8_t *)&counter_bdr_reg1, 1);
7631 }
7632
7633 return ret;
7634 }
7635
7636 /**
7637 * @brief Selects the trigger for the internal counter of batching events
7638 * between XL and gyro.[get]
7639 *
7640 * @param ctx Read / write interface definitions.(ptr)
7641 * @param val Get the values of trig_counter_bdr
7642 * in reg COUNTER_BDR_REG1
7643 * @retval Interface status (MANDATORY: return 0 -> no Error).
7644 *
7645 */
lsm6dsrx_fifo_cnt_event_batch_get(const stmdev_ctx_t * ctx,lsm6dsrx_trig_counter_bdr_t * val)7646 int32_t lsm6dsrx_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx,
7647 lsm6dsrx_trig_counter_bdr_t *val)
7648 {
7649 lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
7650 int32_t ret;
7651
7652 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
7653 (uint8_t *)&counter_bdr_reg1, 1);
7654
7655 switch (counter_bdr_reg1.trig_counter_bdr)
7656 {
7657 case LSM6DSRX_XL_BATCH_EVENT:
7658 *val = LSM6DSRX_XL_BATCH_EVENT;
7659 break;
7660
7661 case LSM6DSRX_GYRO_BATCH_EVENT:
7662 *val = LSM6DSRX_GYRO_BATCH_EVENT;
7663 break;
7664
7665 default:
7666 *val = LSM6DSRX_XL_BATCH_EVENT;
7667 break;
7668 }
7669
7670 return ret;
7671 }
7672
7673 /**
7674 * @brief Resets the internal counter of batching events for a single sensor.
7675 * This bit is automatically reset to zero if it was set to '1'.[set]
7676 *
7677 * @param ctx Read / write interface definitions.(ptr)
7678 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
7679 * @retval Interface status (MANDATORY: return 0 -> no Error).
7680 *
7681 */
lsm6dsrx_rst_batch_counter_set(const stmdev_ctx_t * ctx,uint8_t val)7682 int32_t lsm6dsrx_rst_batch_counter_set(const stmdev_ctx_t *ctx,
7683 uint8_t val)
7684 {
7685 lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
7686 int32_t ret;
7687
7688 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
7689 (uint8_t *)&counter_bdr_reg1, 1);
7690
7691 if (ret == 0)
7692 {
7693 counter_bdr_reg1.rst_counter_bdr = (uint8_t)val;
7694 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
7695 (uint8_t *)&counter_bdr_reg1, 1);
7696 }
7697
7698 return ret;
7699 }
7700
7701 /**
7702 * @brief Resets the internal counter of batching events for a single sensor.
7703 * This bit is automatically reset to zero if it was set to '1'.[get]
7704 *
7705 * @param ctx Read / write interface definitions.(ptr)
7706 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
7707 * @retval Interface status (MANDATORY: return 0 -> no Error).
7708 *
7709 */
lsm6dsrx_rst_batch_counter_get(const stmdev_ctx_t * ctx,uint8_t * val)7710 int32_t lsm6dsrx_rst_batch_counter_get(const stmdev_ctx_t *ctx,
7711 uint8_t *val)
7712 {
7713 lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
7714 int32_t ret;
7715
7716 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
7717 (uint8_t *)&counter_bdr_reg1, 1);
7718 *val = counter_bdr_reg1.rst_counter_bdr;
7719
7720 return ret;
7721 }
7722
7723 /**
7724 * @brief Batch data rate counter.[set]
7725 *
7726 * @param ctx Read / write interface definitions.(ptr)
7727 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
7728 * and COUNTER_BDR_REG1.
7729 * @retval Interface status (MANDATORY: return 0 -> no Error).
7730 *
7731 */
lsm6dsrx_batch_counter_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)7732 int32_t lsm6dsrx_batch_counter_threshold_set(const stmdev_ctx_t *ctx,
7733 uint16_t val)
7734 {
7735 lsm6dsrx_counter_bdr_reg2_t counter_bdr_reg1;
7736 lsm6dsrx_counter_bdr_reg2_t counter_bdr_reg2;
7737 int32_t ret;
7738
7739 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
7740 (uint8_t *)&counter_bdr_reg1, 1);
7741
7742 if (ret == 0)
7743 {
7744 counter_bdr_reg1.cnt_bdr_th = (uint8_t)((val / 256U) & 0x07U);
7745 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
7746 (uint8_t *)&counter_bdr_reg1, 1);
7747 }
7748
7749 if (ret == 0)
7750 {
7751 counter_bdr_reg2.cnt_bdr_th = (uint8_t)(val -
7752 (counter_bdr_reg1.cnt_bdr_th * 256U));
7753 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_COUNTER_BDR_REG2,
7754 (uint8_t *)&counter_bdr_reg2, 1);
7755 }
7756
7757 return ret;
7758 }
7759
7760 /**
7761 * @brief Batch data rate counter.[get]
7762 *
7763 * @param ctx Read / write interface definitions.(ptr)
7764 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
7765 * and COUNTER_BDR_REG1.
7766 * @retval Interface status (MANDATORY: return 0 -> no Error).
7767 *
7768 */
lsm6dsrx_batch_counter_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)7769 int32_t lsm6dsrx_batch_counter_threshold_get(const stmdev_ctx_t *ctx,
7770 uint16_t *val)
7771 {
7772 lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
7773 lsm6dsrx_counter_bdr_reg2_t counter_bdr_reg2;
7774 int32_t ret;
7775
7776 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
7777 (uint8_t *)&counter_bdr_reg1, 1);
7778
7779 if (ret == 0)
7780 {
7781 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG2,
7782 (uint8_t *)&counter_bdr_reg2, 1);
7783 }
7784
7785 *val = counter_bdr_reg1.cnt_bdr_th;
7786 *val = (*val * 256U) + counter_bdr_reg2.cnt_bdr_th;
7787
7788 return ret;
7789 }
7790
7791 /**
7792 * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
7793 *
7794 * @param ctx Read / write interface definitions.(ptr)
7795 * @param val Read the value of diff_fifo in reg FIFO_STATUS1 and FIFO_STATUS2
7796 * @retval Interface status (MANDATORY: return 0 -> no Error).
7797 *
7798 */
lsm6dsrx_fifo_data_level_get(const stmdev_ctx_t * ctx,uint16_t * val)7799 int32_t lsm6dsrx_fifo_data_level_get(const stmdev_ctx_t *ctx,
7800 uint16_t *val)
7801 {
7802 uint8_t reg[2];
7803 lsm6dsrx_fifo_status1_t *fifo_status1 = (lsm6dsrx_fifo_status1_t *)®[0];
7804 lsm6dsrx_fifo_status2_t *fifo_status2 = (lsm6dsrx_fifo_status2_t *)®[1];
7805 int32_t ret;
7806
7807 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7808 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_STATUS1, (uint8_t *)reg, 2);
7809 if (ret == 0)
7810 {
7811 *val = fifo_status2->diff_fifo;
7812 *val = (*val * 256U) + fifo_status1->diff_fifo;
7813 }
7814
7815 return ret;
7816 }
7817
7818 /**
7819 * @brief Smart FIFO status.[get]
7820 *
7821 * @param ctx Read / write interface definitions.(ptr)
7822 * @param val Read registers FIFO_STATUS2
7823 * @retval Interface status (MANDATORY: return 0 -> no Error).
7824 *
7825 */
lsm6dsrx_fifo_status_get(const stmdev_ctx_t * ctx,lsm6dsrx_fifo_status2_t * val)7826 int32_t lsm6dsrx_fifo_status_get(const stmdev_ctx_t *ctx,
7827 lsm6dsrx_fifo_status2_t *val)
7828 {
7829 uint8_t reg[2];
7830 lsm6dsrx_fifo_status2_t *fifo_status2 = (lsm6dsrx_fifo_status2_t *)®[1];
7831 int32_t ret;
7832
7833 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7834 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_STATUS1, (uint8_t *)reg, 2);
7835 if (ret == 0)
7836 {
7837 *val = *fifo_status2;
7838 }
7839
7840 return ret;
7841 }
7842
7843 /**
7844 * @brief Smart FIFO full status.[get]
7845 *
7846 * @param ctx Read / write interface definitions.(ptr)
7847 * @param val Read the values of fifo_full_ia in reg FIFO_STATUS2
7848 * @retval Interface status (MANDATORY: return 0 -> no Error).
7849 *
7850 */
lsm6dsrx_fifo_full_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)7851 int32_t lsm6dsrx_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
7852 {
7853 uint8_t reg[2];
7854 lsm6dsrx_fifo_status2_t *fifo_status2 = (lsm6dsrx_fifo_status2_t *)®[1];
7855 int32_t ret;
7856
7857 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7858 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_STATUS1, (uint8_t *)reg, 2);
7859 if (ret == 0)
7860 {
7861 *val = fifo_status2->fifo_full_ia;
7862 }
7863
7864 return ret;
7865 }
7866
7867 /**
7868 * @brief FIFO overrun status.[get]
7869 *
7870 * @param ctx Read / write interface definitions.(ptr)
7871 * @param val Read the values of fifo_over_run_latched in
7872 * reg FIFO_STATUS2
7873 * @retval Interface status (MANDATORY: return 0 -> no Error).
7874 *
7875 */
lsm6dsrx_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)7876 int32_t lsm6dsrx_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
7877 {
7878 uint8_t reg[2];
7879 lsm6dsrx_fifo_status2_t *fifo_status2 = (lsm6dsrx_fifo_status2_t *)®[1];
7880 int32_t ret;
7881
7882 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7883 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_STATUS1, (uint8_t *)reg, 2);
7884 if (ret == 0)
7885 {
7886 *val = fifo_status2->fifo_ovr_ia;
7887 }
7888
7889 return ret;
7890 }
7891
7892 /**
7893 * @brief FIFO watermark status.[get]
7894 *
7895 * @param ctx Read / write interface definitions.(ptr)
7896 * @param val Read the values of fifo_wtm_ia in reg FIFO_STATUS2
7897 * @retval Interface status (MANDATORY: return 0 -> no Error).
7898 *
7899 */
lsm6dsrx_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)7900 int32_t lsm6dsrx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
7901 {
7902 uint8_t reg[2];
7903 lsm6dsrx_fifo_status2_t *fifo_status2 = (lsm6dsrx_fifo_status2_t *)®[1];
7904 int32_t ret;
7905
7906 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7907 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_STATUS1, (uint8_t *)reg, 2);
7908 if (ret == 0)
7909 {
7910 *val = fifo_status2->fifo_wtm_ia;
7911 }
7912
7913 return ret;
7914 }
7915
7916 /**
7917 * @brief Identifies the sensor in FIFO_DATA_OUT.[get]
7918 *
7919 * @param ctx Read / write interface definitions.(ptr)
7920 * @param val Change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
7921 * @retval Interface status (MANDATORY: return 0 -> no Error).
7922 *
7923 */
lsm6dsrx_fifo_sensor_tag_get(const stmdev_ctx_t * ctx,lsm6dsrx_fifo_tag_t * val)7924 int32_t lsm6dsrx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx,
7925 lsm6dsrx_fifo_tag_t *val)
7926 {
7927 lsm6dsrx_fifo_data_out_tag_t fifo_data_out_tag;
7928 int32_t ret;
7929
7930 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_DATA_OUT_TAG,
7931 (uint8_t *)&fifo_data_out_tag, 1);
7932
7933 switch (fifo_data_out_tag.tag_sensor)
7934 {
7935 case LSM6DSRX_GYRO_NC_TAG:
7936 *val = LSM6DSRX_GYRO_NC_TAG;
7937 break;
7938
7939 case LSM6DSRX_XL_NC_TAG:
7940 *val = LSM6DSRX_XL_NC_TAG;
7941 break;
7942
7943 case LSM6DSRX_TEMPERATURE_TAG:
7944 *val = LSM6DSRX_TEMPERATURE_TAG;
7945 break;
7946
7947 case LSM6DSRX_TIMESTAMP_TAG:
7948 *val = LSM6DSRX_TIMESTAMP_TAG;
7949 break;
7950
7951 case LSM6DSRX_CFG_CHANGE_TAG:
7952 *val = LSM6DSRX_CFG_CHANGE_TAG;
7953 break;
7954
7955 case LSM6DSRX_XL_NC_T_2_TAG:
7956 *val = LSM6DSRX_XL_NC_T_2_TAG;
7957 break;
7958
7959 case LSM6DSRX_XL_NC_T_1_TAG:
7960 *val = LSM6DSRX_XL_NC_T_1_TAG;
7961 break;
7962
7963 case LSM6DSRX_XL_2XC_TAG:
7964 *val = LSM6DSRX_XL_2XC_TAG;
7965 break;
7966
7967 case LSM6DSRX_XL_3XC_TAG:
7968 *val = LSM6DSRX_XL_3XC_TAG;
7969 break;
7970
7971 case LSM6DSRX_GYRO_NC_T_2_TAG:
7972 *val = LSM6DSRX_GYRO_NC_T_2_TAG;
7973 break;
7974
7975 case LSM6DSRX_GYRO_NC_T_1_TAG:
7976 *val = LSM6DSRX_GYRO_NC_T_1_TAG;
7977 break;
7978
7979 case LSM6DSRX_GYRO_2XC_TAG:
7980 *val = LSM6DSRX_GYRO_2XC_TAG;
7981 break;
7982
7983 case LSM6DSRX_GYRO_3XC_TAG:
7984 *val = LSM6DSRX_GYRO_3XC_TAG;
7985 break;
7986
7987 case LSM6DSRX_SENSORHUB_SLAVE0_TAG:
7988 *val = LSM6DSRX_SENSORHUB_SLAVE0_TAG;
7989 break;
7990
7991 case LSM6DSRX_SENSORHUB_SLAVE1_TAG:
7992 *val = LSM6DSRX_SENSORHUB_SLAVE1_TAG;
7993 break;
7994
7995 case LSM6DSRX_SENSORHUB_SLAVE2_TAG:
7996 *val = LSM6DSRX_SENSORHUB_SLAVE2_TAG;
7997 break;
7998
7999 case LSM6DSRX_SENSORHUB_SLAVE3_TAG:
8000 *val = LSM6DSRX_SENSORHUB_SLAVE3_TAG;
8001 break;
8002
8003 case LSM6DSRX_STEP_CPUNTER_TAG:
8004 *val = LSM6DSRX_STEP_CPUNTER_TAG;
8005 break;
8006
8007 case LSM6DSRX_GAME_ROTATION_TAG:
8008 *val = LSM6DSRX_GAME_ROTATION_TAG;
8009 break;
8010
8011 case LSM6DSRX_GEOMAG_ROTATION_TAG:
8012 *val = LSM6DSRX_GEOMAG_ROTATION_TAG;
8013 break;
8014
8015 case LSM6DSRX_ROTATION_TAG:
8016 *val = LSM6DSRX_ROTATION_TAG;
8017 break;
8018
8019 case LSM6DSRX_SENSORHUB_NACK_TAG:
8020 *val = LSM6DSRX_SENSORHUB_NACK_TAG;
8021 break;
8022
8023 default:
8024 *val = LSM6DSRX_SENSORHUB_NACK_TAG;
8025 break;
8026 }
8027
8028 return ret;
8029 }
8030
8031 /**
8032 * @brief Enable FIFO batching of pedometer embedded function values.[set]
8033 *
8034 * @param ctx Read / write interface definitions.(ptr)
8035 * @param val Change the values of gbias_fifo_en in
8036 * reg LSM6DSRX_EMB_FUNC_FIFO_CFG
8037 * @retval Interface status (MANDATORY: return 0 -> no Error).
8038 *
8039 */
lsm6dsrx_fifo_pedo_batch_set(const stmdev_ctx_t * ctx,uint8_t val)8040 int32_t lsm6dsrx_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
8041 {
8042 lsm6dsrx_emb_func_fifo_cfg_t emb_func_fifo_cfg;
8043 int32_t ret;
8044
8045 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
8046
8047 if (ret == 0)
8048 {
8049 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_FIFO_CFG,
8050 (uint8_t *)&emb_func_fifo_cfg, 1);
8051 }
8052
8053 if (ret == 0)
8054 {
8055 emb_func_fifo_cfg.pedo_fifo_en = (uint8_t)val;
8056 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_FIFO_CFG,
8057 (uint8_t *)&emb_func_fifo_cfg, 1);
8058 }
8059
8060 if (ret == 0)
8061 {
8062 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8063 }
8064
8065 return ret;
8066 }
8067
8068 /**
8069 * @brief Enable FIFO batching of pedometer embedded function values.[get]
8070 *
8071 * @param ctx Read / write interface definitions.(ptr)
8072 * @param val Change the values of pedo_fifo_en in reg
8073 * LSM6DSRX_EMB_FUNC_FIFO_CFG
8074 * @retval Interface status (MANDATORY: return 0 -> no Error).
8075 *
8076 */
lsm6dsrx_fifo_pedo_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)8077 int32_t lsm6dsrx_fifo_pedo_batch_get(const stmdev_ctx_t *ctx,
8078 uint8_t *val)
8079 {
8080 lsm6dsrx_emb_func_fifo_cfg_t emb_func_fifo_cfg;
8081 int32_t ret;
8082
8083 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
8084
8085 if (ret == 0)
8086 {
8087 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_FIFO_CFG,
8088 (uint8_t *)&emb_func_fifo_cfg, 1);
8089 *val = emb_func_fifo_cfg.pedo_fifo_en;
8090 }
8091
8092 if (ret == 0)
8093 {
8094 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8095 }
8096
8097 return ret;
8098 }
8099
8100 /**
8101 * @brief Enable FIFO batching data of first slave.[set]
8102 *
8103 * @param ctx Read / write interface definitions.(ptr)
8104 * @param val Change the values of batch_ext_sens_0_en in reg SLV0_CONFIG
8105 * @retval Interface status (MANDATORY: return 0 -> no Error).
8106 *
8107 */
lsm6dsrx_sh_batch_slave_0_set(const stmdev_ctx_t * ctx,uint8_t val)8108 int32_t lsm6dsrx_sh_batch_slave_0_set(const stmdev_ctx_t *ctx,
8109 uint8_t val)
8110 {
8111 lsm6dsrx_slv0_config_t slv0_config;
8112 int32_t ret;
8113
8114 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
8115
8116 if (ret == 0)
8117 {
8118 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV0_CONFIG,
8119 (uint8_t *)&slv0_config, 1);
8120 }
8121
8122 if (ret == 0)
8123 {
8124 slv0_config. batch_ext_sens_0_en = (uint8_t)val;
8125 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_CONFIG,
8126 (uint8_t *)&slv0_config, 1);
8127 }
8128
8129 if (ret == 0)
8130 {
8131 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8132 }
8133
8134 return ret;
8135 }
8136
8137 /**
8138 * @brief Enable FIFO batching data of first slave.[get]
8139 *
8140 * @param ctx Read / write interface definitions.(ptr)
8141 * @param val Change the values of batch_ext_sens_0_en in
8142 * reg SLV0_CONFIG
8143 * @retval Interface status (MANDATORY: return 0 -> no Error).
8144 *
8145 */
lsm6dsrx_sh_batch_slave_0_get(const stmdev_ctx_t * ctx,uint8_t * val)8146 int32_t lsm6dsrx_sh_batch_slave_0_get(const stmdev_ctx_t *ctx,
8147 uint8_t *val)
8148 {
8149 lsm6dsrx_slv0_config_t slv0_config;
8150 int32_t ret;
8151
8152 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
8153
8154 if (ret == 0)
8155 {
8156 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV0_CONFIG,
8157 (uint8_t *)&slv0_config, 1);
8158 }
8159
8160 if (ret == 0)
8161 {
8162 *val = slv0_config. batch_ext_sens_0_en;
8163 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8164 }
8165
8166 return ret;
8167 }
8168
8169 /**
8170 * @brief Enable FIFO batching data of second slave.[set]
8171 *
8172 * @param ctx Read / write interface definitions.(ptr)
8173 * @param val Change the values of batch_ext_sens_1_en in
8174 * reg SLV1_CONFIG
8175 * @retval Interface status (MANDATORY: return 0 -> no Error).
8176 *
8177 */
lsm6dsrx_sh_batch_slave_1_set(const stmdev_ctx_t * ctx,uint8_t val)8178 int32_t lsm6dsrx_sh_batch_slave_1_set(const stmdev_ctx_t *ctx,
8179 uint8_t val)
8180 {
8181 lsm6dsrx_slv1_config_t slv1_config;
8182 int32_t ret;
8183
8184 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
8185
8186 if (ret == 0)
8187 {
8188 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV1_CONFIG,
8189 (uint8_t *)&slv1_config, 1);
8190 }
8191
8192 if (ret == 0)
8193 {
8194 slv1_config. batch_ext_sens_1_en = (uint8_t)val;
8195 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV1_CONFIG,
8196 (uint8_t *)&slv1_config, 1);
8197 }
8198
8199 if (ret == 0)
8200 {
8201 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8202 }
8203
8204 return ret;
8205 }
8206
8207 /**
8208 * @brief Enable FIFO batching data of second slave.[get]
8209 *
8210 * @param ctx Read / write interface definitions.(ptr)
8211 * @param val Change the values of batch_ext_sens_1_en in
8212 * reg SLV1_CONFIG
8213 * @retval Interface status (MANDATORY: return 0 -> no Error).
8214 *
8215 */
lsm6dsrx_sh_batch_slave_1_get(const stmdev_ctx_t * ctx,uint8_t * val)8216 int32_t lsm6dsrx_sh_batch_slave_1_get(const stmdev_ctx_t *ctx,
8217 uint8_t *val)
8218 {
8219 lsm6dsrx_slv1_config_t slv1_config;
8220 int32_t ret;
8221
8222 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
8223
8224 if (ret == 0)
8225 {
8226 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV1_CONFIG,
8227 (uint8_t *)&slv1_config, 1);
8228 *val = slv1_config. batch_ext_sens_1_en;
8229 }
8230
8231 if (ret == 0)
8232 {
8233 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8234 }
8235
8236 return ret;
8237 }
8238
8239 /**
8240 * @brief Enable FIFO batching data of third slave.[set]
8241 *
8242 * @param ctx Read / write interface definitions.(ptr)
8243 * @param val Change the values of batch_ext_sens_2_en in
8244 * reg SLV2_CONFIG
8245 * @retval Interface status (MANDATORY: return 0 -> no Error).
8246 *
8247 */
lsm6dsrx_sh_batch_slave_2_set(const stmdev_ctx_t * ctx,uint8_t val)8248 int32_t lsm6dsrx_sh_batch_slave_2_set(const stmdev_ctx_t *ctx,
8249 uint8_t val)
8250 {
8251 lsm6dsrx_slv2_config_t slv2_config;
8252 int32_t ret;
8253
8254 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
8255
8256 if (ret == 0)
8257 {
8258 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV2_CONFIG,
8259 (uint8_t *)&slv2_config, 1);
8260 }
8261
8262 if (ret == 0)
8263 {
8264 slv2_config. batch_ext_sens_2_en = (uint8_t)val;
8265 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV2_CONFIG,
8266 (uint8_t *)&slv2_config, 1);
8267 }
8268
8269 if (ret == 0)
8270 {
8271 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8272 }
8273
8274 return ret;
8275 }
8276
8277 /**
8278 * @brief Enable FIFO batching data of third slave.[get]
8279 *
8280 * @param ctx Read / write interface definitions.(ptr)
8281 * @param val Change the values of batch_ext_sens_2_en in
8282 * reg SLV2_CONFIG
8283 * @retval Interface status (MANDATORY: return 0 -> no Error).
8284 *
8285 */
lsm6dsrx_sh_batch_slave_2_get(const stmdev_ctx_t * ctx,uint8_t * val)8286 int32_t lsm6dsrx_sh_batch_slave_2_get(const stmdev_ctx_t *ctx,
8287 uint8_t *val)
8288 {
8289 lsm6dsrx_slv2_config_t slv2_config;
8290 int32_t ret;
8291
8292 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
8293
8294 if (ret == 0)
8295 {
8296 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV2_CONFIG,
8297 (uint8_t *)&slv2_config, 1);
8298 }
8299
8300 if (ret == 0)
8301 {
8302 *val = slv2_config. batch_ext_sens_2_en;
8303 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8304 }
8305
8306 return ret;
8307 }
8308
8309 /**
8310 * @brief Enable FIFO batching data of fourth slave.[set]
8311 *
8312 * @param ctx Read / write interface definitions.(ptr)
8313 * @param val Change the values of batch_ext_sens_3_en in
8314 * reg SLV3_CONFIG
8315 * @retval Interface status (MANDATORY: return 0 -> no Error).
8316 *
8317 */
lsm6dsrx_sh_batch_slave_3_set(const stmdev_ctx_t * ctx,uint8_t val)8318 int32_t lsm6dsrx_sh_batch_slave_3_set(const stmdev_ctx_t *ctx,
8319 uint8_t val)
8320 {
8321 lsm6dsrx_slv3_config_t slv3_config;
8322 int32_t ret;
8323
8324 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
8325
8326 if (ret == 0)
8327 {
8328 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV3_CONFIG,
8329 (uint8_t *)&slv3_config, 1);
8330 }
8331
8332 if (ret == 0)
8333 {
8334 slv3_config. batch_ext_sens_3_en = (uint8_t)val;
8335 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV3_CONFIG,
8336 (uint8_t *)&slv3_config, 1);
8337 }
8338
8339 if (ret == 0)
8340 {
8341 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8342 }
8343
8344 return ret;
8345 }
8346
8347 /**
8348 * @brief Enable FIFO batching data of fourth slave.[get]
8349 *
8350 * @param ctx Read / write interface definitions.(ptr)
8351 * @param val Change the values of batch_ext_sens_3_en in
8352 * reg SLV3_CONFIG
8353 * @retval Interface status (MANDATORY: return 0 -> no Error).
8354 *
8355 */
lsm6dsrx_sh_batch_slave_3_get(const stmdev_ctx_t * ctx,uint8_t * val)8356 int32_t lsm6dsrx_sh_batch_slave_3_get(const stmdev_ctx_t *ctx,
8357 uint8_t *val)
8358 {
8359 lsm6dsrx_slv3_config_t slv3_config;
8360 int32_t ret;
8361
8362 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
8363
8364 if (ret == 0)
8365 {
8366 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV3_CONFIG,
8367 (uint8_t *)&slv3_config, 1);
8368 *val = slv3_config. batch_ext_sens_3_en;
8369 }
8370
8371 if (ret == 0)
8372 {
8373 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8374 }
8375
8376 return ret;
8377 }
8378
8379 /**
8380 * @}
8381 *
8382 */
8383
8384 /**
8385 * @defgroup LSM6DSRX_DEN_functionality
8386 * @brief This section groups all the functions concerning
8387 * DEN functionality.
8388 * @{
8389 *
8390 */
8391
8392 /**
8393 * @brief DEN functionality marking mode.[set]
8394 *
8395 * @param ctx Read / write interface definitions.(ptr)
8396 * @param val Change the values of den_mode in reg CTRL6_C
8397 * @retval Interface status (MANDATORY: return 0 -> no Error).
8398 *
8399 */
lsm6dsrx_den_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_den_mode_t val)8400 int32_t lsm6dsrx_den_mode_set(const stmdev_ctx_t *ctx,
8401 lsm6dsrx_den_mode_t val)
8402 {
8403 lsm6dsrx_ctrl6_c_t ctrl6_c;
8404 int32_t ret;
8405
8406 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C,
8407 (uint8_t *)&ctrl6_c, 1);
8408
8409 if (ret == 0)
8410 {
8411 ctrl6_c.den_mode = (uint8_t)val;
8412 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL6_C,
8413 (uint8_t *)&ctrl6_c, 1);
8414 }
8415
8416 return ret;
8417 }
8418
8419 /**
8420 * @brief DEN functionality marking mode.[get]
8421 *
8422 * @param ctx Read / write interface definitions.(ptr)
8423 * @param val Get the values of den_mode in reg CTRL6_C
8424 * @retval Interface status (MANDATORY: return 0 -> no Error).
8425 *
8426 */
lsm6dsrx_den_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_den_mode_t * val)8427 int32_t lsm6dsrx_den_mode_get(const stmdev_ctx_t *ctx,
8428 lsm6dsrx_den_mode_t *val)
8429 {
8430 lsm6dsrx_ctrl6_c_t ctrl6_c;
8431 int32_t ret;
8432
8433 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C,
8434 (uint8_t *)&ctrl6_c, 1);
8435
8436 switch (ctrl6_c.den_mode)
8437 {
8438 case LSM6DSRX_DEN_DISABLE:
8439 *val = LSM6DSRX_DEN_DISABLE;
8440 break;
8441
8442 case LSM6DSRX_LEVEL_FIFO:
8443 *val = LSM6DSRX_LEVEL_FIFO;
8444 break;
8445
8446 case LSM6DSRX_LEVEL_LETCHED:
8447 *val = LSM6DSRX_LEVEL_LETCHED;
8448 break;
8449
8450 case LSM6DSRX_LEVEL_TRIGGER:
8451 *val = LSM6DSRX_LEVEL_TRIGGER;
8452 break;
8453
8454 case LSM6DSRX_EDGE_TRIGGER:
8455 *val = LSM6DSRX_EDGE_TRIGGER;
8456 break;
8457
8458 default:
8459 *val = LSM6DSRX_DEN_DISABLE;
8460 break;
8461 }
8462
8463 return ret;
8464 }
8465
8466 /**
8467 * @brief DEN active level configuration.[set]
8468 *
8469 * @param ctx Read / write interface definitions.(ptr)
8470 * @param val Change the values of den_lh in reg CTRL9_XL
8471 * @retval Interface status (MANDATORY: return 0 -> no Error).
8472 *
8473 */
lsm6dsrx_den_polarity_set(const stmdev_ctx_t * ctx,lsm6dsrx_den_lh_t val)8474 int32_t lsm6dsrx_den_polarity_set(const stmdev_ctx_t *ctx,
8475 lsm6dsrx_den_lh_t val)
8476 {
8477 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8478 int32_t ret;
8479
8480 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL,
8481 (uint8_t *)&ctrl9_xl, 1);
8482
8483 if (ret == 0)
8484 {
8485 ctrl9_xl.den_lh = (uint8_t)val;
8486 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL,
8487 (uint8_t *)&ctrl9_xl, 1);
8488 }
8489
8490 return ret;
8491 }
8492
8493 /**
8494 * @brief DEN active level configuration.[get]
8495 *
8496 * @param ctx Read / write interface definitions.(ptr)
8497 * @param val Get the values of den_lh in reg CTRL9_XL
8498 * @retval Interface status (MANDATORY: return 0 -> no Error).
8499 *
8500 */
lsm6dsrx_den_polarity_get(const stmdev_ctx_t * ctx,lsm6dsrx_den_lh_t * val)8501 int32_t lsm6dsrx_den_polarity_get(const stmdev_ctx_t *ctx,
8502 lsm6dsrx_den_lh_t *val)
8503 {
8504 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8505 int32_t ret;
8506
8507 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL,
8508 (uint8_t *)&ctrl9_xl, 1);
8509
8510 switch (ctrl9_xl.den_lh)
8511 {
8512 case LSM6DSRX_DEN_ACT_LOW:
8513 *val = LSM6DSRX_DEN_ACT_LOW;
8514 break;
8515
8516 case LSM6DSRX_DEN_ACT_HIGH:
8517 *val = LSM6DSRX_DEN_ACT_HIGH;
8518 break;
8519
8520 default:
8521 *val = LSM6DSRX_DEN_ACT_LOW;
8522 break;
8523 }
8524
8525 return ret;
8526 }
8527
8528 /**
8529 * @brief DEN configuration.[set]
8530 *
8531 * @param ctx Read / write interface definitions.(ptr)
8532 * @param val Change the values of den_xl_g in reg CTRL9_XL
8533 * @retval Interface status (MANDATORY: return 0 -> no Error).
8534 *
8535 */
lsm6dsrx_den_enable_set(const stmdev_ctx_t * ctx,lsm6dsrx_den_xl_g_t val)8536 int32_t lsm6dsrx_den_enable_set(const stmdev_ctx_t *ctx,
8537 lsm6dsrx_den_xl_g_t val)
8538 {
8539 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8540 int32_t ret;
8541
8542 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL,
8543 (uint8_t *)&ctrl9_xl, 1);
8544
8545 if (ret == 0)
8546 {
8547 ctrl9_xl.den_xl_g = (uint8_t)val;
8548 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL,
8549 (uint8_t *)&ctrl9_xl, 1);
8550 }
8551
8552 return ret;
8553 }
8554
8555 /**
8556 * @brief DEN configuration.[get]
8557 *
8558 * @param ctx Read / write interface definitions.(ptr)
8559 * @param val Get the values of den_xl_g in reg CTRL9_XL
8560 * @retval Interface status (MANDATORY: return 0 -> no Error).
8561 *
8562 */
lsm6dsrx_den_enable_get(const stmdev_ctx_t * ctx,lsm6dsrx_den_xl_g_t * val)8563 int32_t lsm6dsrx_den_enable_get(const stmdev_ctx_t *ctx,
8564 lsm6dsrx_den_xl_g_t *val)
8565 {
8566 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8567 int32_t ret;
8568
8569 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL,
8570 (uint8_t *)&ctrl9_xl, 1);
8571
8572 switch (ctrl9_xl.den_xl_g)
8573 {
8574 case LSM6DSRX_STAMP_IN_GY_DATA:
8575 *val = LSM6DSRX_STAMP_IN_GY_DATA;
8576 break;
8577
8578 case LSM6DSRX_STAMP_IN_XL_DATA:
8579 *val = LSM6DSRX_STAMP_IN_XL_DATA;
8580 break;
8581
8582 case LSM6DSRX_STAMP_IN_GY_XL_DATA:
8583 *val = LSM6DSRX_STAMP_IN_GY_XL_DATA;
8584 break;
8585
8586 default:
8587 *val = LSM6DSRX_STAMP_IN_GY_DATA;
8588 break;
8589 }
8590
8591 return ret;
8592 }
8593
8594 /**
8595 * @brief DEN value stored in LSB of X-axis.[set]
8596 *
8597 * @param ctx Read / write interface definitions.(ptr)
8598 * @param val Change the values of den_z in reg CTRL9_XL
8599 * @retval Interface status (MANDATORY: return 0 -> no Error).
8600 *
8601 */
lsm6dsrx_den_mark_axis_x_set(const stmdev_ctx_t * ctx,uint8_t val)8602 int32_t lsm6dsrx_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val)
8603 {
8604 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8605 int32_t ret;
8606
8607 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL,
8608 (uint8_t *)&ctrl9_xl, 1);
8609
8610 if (ret == 0)
8611 {
8612 ctrl9_xl.den_z = (uint8_t)val;
8613 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL,
8614 (uint8_t *)&ctrl9_xl, 1);
8615 }
8616
8617 return ret;
8618 }
8619
8620 /**
8621 * @brief DEN value stored in LSB of X-axis.[get]
8622 *
8623 * @param ctx Read / write interface definitions.(ptr)
8624 * @param val Change the values of den_z in reg CTRL9_XL
8625 * @retval Interface status (MANDATORY: return 0 -> no Error).
8626 *
8627 */
lsm6dsrx_den_mark_axis_x_get(const stmdev_ctx_t * ctx,uint8_t * val)8628 int32_t lsm6dsrx_den_mark_axis_x_get(const stmdev_ctx_t *ctx,
8629 uint8_t *val)
8630 {
8631 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8632 int32_t ret;
8633
8634 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL,
8635 (uint8_t *)&ctrl9_xl, 1);
8636 *val = ctrl9_xl.den_z;
8637
8638 return ret;
8639 }
8640
8641 /**
8642 * @brief DEN value stored in LSB of Y-axis.[set]
8643 *
8644 * @param ctx Read / write interface definitions.(ptr)
8645 * @param val Change the values of den_y in reg CTRL9_XL
8646 * @retval Interface status (MANDATORY: return 0 -> no Error).
8647 *
8648 */
lsm6dsrx_den_mark_axis_y_set(const stmdev_ctx_t * ctx,uint8_t val)8649 int32_t lsm6dsrx_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val)
8650 {
8651 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8652 int32_t ret;
8653
8654 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL,
8655 (uint8_t *)&ctrl9_xl, 1);
8656
8657 if (ret == 0)
8658 {
8659 ctrl9_xl.den_y = (uint8_t)val;
8660 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL,
8661 (uint8_t *)&ctrl9_xl, 1);
8662 }
8663
8664 return ret;
8665 }
8666
8667 /**
8668 * @brief DEN value stored in LSB of Y-axis.[get]
8669 *
8670 * @param ctx Read / write interface definitions.(ptr)
8671 * @param val Change the values of den_y in reg CTRL9_XL
8672 * @retval Interface status (MANDATORY: return 0 -> no Error).
8673 *
8674 */
lsm6dsrx_den_mark_axis_y_get(const stmdev_ctx_t * ctx,uint8_t * val)8675 int32_t lsm6dsrx_den_mark_axis_y_get(const stmdev_ctx_t *ctx,
8676 uint8_t *val)
8677 {
8678 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8679 int32_t ret;
8680
8681 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL,
8682 (uint8_t *)&ctrl9_xl, 1);
8683 *val = ctrl9_xl.den_y;
8684
8685 return ret;
8686 }
8687
8688 /**
8689 * @brief DEN value stored in LSB of Z-axis.[set]
8690 *
8691 * @param ctx Read / write interface definitions.(ptr)
8692 * @param val Change the values of den_x in reg CTRL9_XL
8693 * @retval Interface status (MANDATORY: return 0 -> no Error).
8694 *
8695 */
lsm6dsrx_den_mark_axis_z_set(const stmdev_ctx_t * ctx,uint8_t val)8696 int32_t lsm6dsrx_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val)
8697 {
8698 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8699 int32_t ret;
8700
8701 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL,
8702 (uint8_t *)&ctrl9_xl, 1);
8703
8704 if (ret == 0)
8705 {
8706 ctrl9_xl.den_x = (uint8_t)val;
8707 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL,
8708 (uint8_t *)&ctrl9_xl, 1);
8709 }
8710
8711 return ret;
8712 }
8713
8714 /**
8715 * @brief DEN value stored in LSB of Z-axis.[get]
8716 *
8717 * @param ctx Read / write interface definitions.(ptr)
8718 * @param val Change the values of den_x in reg CTRL9_XL
8719 * @retval Interface status (MANDATORY: return 0 -> no Error).
8720 *
8721 */
lsm6dsrx_den_mark_axis_z_get(const stmdev_ctx_t * ctx,uint8_t * val)8722 int32_t lsm6dsrx_den_mark_axis_z_get(const stmdev_ctx_t *ctx,
8723 uint8_t *val)
8724 {
8725 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8726 int32_t ret;
8727
8728 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL,
8729 (uint8_t *)&ctrl9_xl, 1);
8730 *val = ctrl9_xl.den_x;
8731
8732 return ret;
8733 }
8734
8735 /**
8736 * @}
8737 *
8738 */
8739
8740 /**
8741 * @defgroup LSM6DSRX_Pedometer
8742 * @brief This section groups all the functions that manage pedometer.
8743 * @{
8744 *
8745 */
8746
8747 /**
8748 * @brief Enable pedometer algorithm.[set]
8749 *
8750 * @param ctx Read / write interface definitions.(ptr)
8751 * @param val Change the values of pedo_en in reg EMB_FUNC_EN_A
8752 * @retval Interface status (MANDATORY: return 0 -> no Error).
8753 *
8754 */
lsm6dsrx_pedo_sens_set(const stmdev_ctx_t * ctx,uint8_t val)8755 int32_t lsm6dsrx_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val)
8756 {
8757 lsm6dsrx_emb_func_en_a_t emb_func_en_a;
8758 int32_t ret;
8759
8760 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
8761
8762 if (ret == 0)
8763 {
8764 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
8765 (uint8_t *)&emb_func_en_a, 1);
8766 }
8767
8768 if (ret == 0)
8769 {
8770 emb_func_en_a.pedo_en = (uint8_t)val;
8771 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
8772 (uint8_t *)&emb_func_en_a, 1);
8773 }
8774
8775 if (ret == 0)
8776 {
8777 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8778 }
8779
8780 return ret;
8781 }
8782
8783 /**
8784 * @brief Enable pedometer algorithm.[get]
8785 *
8786 * @param ctx Read / write interface definitions.(ptr)
8787 * @param val Change the values of pedo_en in reg EMB_FUNC_EN_A
8788 * @retval Interface status (MANDATORY: return 0 -> no Error).
8789 *
8790 */
lsm6dsrx_pedo_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)8791 int32_t lsm6dsrx_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val)
8792 {
8793 lsm6dsrx_emb_func_en_a_t emb_func_en_a;
8794 int32_t ret;
8795
8796 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
8797
8798 if (ret == 0)
8799 {
8800 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
8801 (uint8_t *)&emb_func_en_a, 1);
8802 *val = emb_func_en_a.pedo_en;
8803 }
8804
8805 if (ret == 0)
8806 {
8807 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8808 }
8809
8810 return ret;
8811 }
8812
8813 /**
8814 * @brief Interrupt status bit for step detection.[get]
8815 *
8816 * @param ctx Read / write interface definitions.(ptr)
8817 * @param val Change the values of is_step_det in reg EMB_FUNC_STATUS
8818 * @retval Interface status (MANDATORY: return 0 -> no Error).
8819 *
8820 */
lsm6dsrx_pedo_step_detect_get(const stmdev_ctx_t * ctx,uint8_t * val)8821 int32_t lsm6dsrx_pedo_step_detect_get(const stmdev_ctx_t *ctx,
8822 uint8_t *val)
8823 {
8824 lsm6dsrx_emb_func_status_t emb_func_status;
8825 int32_t ret;
8826
8827 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
8828
8829 if (ret == 0)
8830 {
8831 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_STATUS,
8832 (uint8_t *)&emb_func_status, 1);
8833 *val = emb_func_status.is_step_det;
8834 }
8835
8836 if (ret == 0)
8837 {
8838 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8839 }
8840
8841 return ret;
8842 }
8843
8844 /**
8845 * @brief Pedometer debounce configuration register (r/w).[set]
8846 *
8847 * @param ctx Read / write interface definitions.(ptr)
8848 * @param buff Buffer that contains data to write
8849 * @retval Interface status (MANDATORY: return 0 -> no Error).
8850 *
8851 */
lsm6dsrx_pedo_debounce_steps_set(const stmdev_ctx_t * ctx,uint8_t * buff)8852 int32_t lsm6dsrx_pedo_debounce_steps_set(const stmdev_ctx_t *ctx,
8853 uint8_t *buff)
8854 {
8855 int32_t ret;
8856
8857 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_PEDO_DEB_STEPS_CONF,
8858 buff);
8859
8860 return ret;
8861 }
8862
8863 /**
8864 * @brief Pedometer debounce configuration register (r/w).[get]
8865 *
8866 * @param ctx Read / write interface definitions.(ptr)
8867 * @param buff Buffer that stores data read
8868 * @retval Interface status (MANDATORY: return 0 -> no Error).
8869 *
8870 */
lsm6dsrx_pedo_debounce_steps_get(const stmdev_ctx_t * ctx,uint8_t * buff)8871 int32_t lsm6dsrx_pedo_debounce_steps_get(const stmdev_ctx_t *ctx,
8872 uint8_t *buff)
8873 {
8874 int32_t ret;
8875
8876 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_DEB_STEPS_CONF,
8877 buff);
8878
8879 return ret;
8880 }
8881
8882 /**
8883 * @brief Time period register for step detection on delta time (r/w).[set]
8884 *
8885 * @param ctx Read / write interface definitions.(ptr)
8886 * @param buff Buffer that contains data to write
8887 * @retval Interface status (MANDATORY: return 0 -> no Error).
8888 *
8889 */
lsm6dsrx_pedo_steps_period_set(const stmdev_ctx_t * ctx,uint16_t val)8890 int32_t lsm6dsrx_pedo_steps_period_set(const stmdev_ctx_t *ctx,
8891 uint16_t val)
8892 {
8893 uint8_t buff[2];
8894 int32_t ret;
8895
8896 buff[1] = (uint8_t)(val / 256U);
8897 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8898 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_PEDO_SC_DELTAT_L,
8899 &buff[0]);
8900
8901 if (ret == 0)
8902 {
8903 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_PEDO_SC_DELTAT_H,
8904 &buff[1]);
8905 }
8906
8907 return ret;
8908 }
8909
8910 /**
8911 * @brief Time period register for step detection on delta time (r/w).[get]
8912 *
8913 * @param ctx Read / write interface definitions.(ptr)
8914 * @param buff Buffer that stores data read
8915 * @retval Interface status (MANDATORY: return 0 -> no Error).
8916 *
8917 */
lsm6dsrx_pedo_steps_period_get(const stmdev_ctx_t * ctx,uint16_t * val)8918 int32_t lsm6dsrx_pedo_steps_period_get(const stmdev_ctx_t *ctx,
8919 uint16_t *val)
8920 {
8921 uint8_t buff[2];
8922 int32_t ret;
8923
8924 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_SC_DELTAT_L,
8925 &buff[0]);
8926
8927 if (ret == 0)
8928 {
8929 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_SC_DELTAT_H,
8930 &buff[1]);
8931 *val = buff[1];
8932 *val = (*val * 256U) + buff[0];
8933 }
8934
8935 return ret;
8936 }
8937
8938 /**
8939 * @brief Set when user wants to generate interrupt on count overflow
8940 * event/every step.[set]
8941 *
8942 * @param ctx Read / write interface definitions.(ptr)
8943 * @param val Change the values of carry_count_en in reg PEDO_CMD_REG
8944 * @retval Interface status (MANDATORY: return 0 -> no Error).
8945 *
8946 */
lsm6dsrx_pedo_int_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_carry_count_en_t val)8947 int32_t lsm6dsrx_pedo_int_mode_set(const stmdev_ctx_t *ctx,
8948 lsm6dsrx_carry_count_en_t val)
8949 {
8950 lsm6dsrx_pedo_cmd_reg_t pedo_cmd_reg;
8951 int32_t ret;
8952
8953 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_CMD_REG,
8954 (uint8_t *)&pedo_cmd_reg);
8955
8956 if (ret == 0)
8957 {
8958 pedo_cmd_reg.carry_count_en = (uint8_t)val;
8959 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_PEDO_CMD_REG,
8960 (uint8_t *)&pedo_cmd_reg);
8961 }
8962
8963 return ret;
8964 }
8965
8966 /**
8967 * @brief Set when user wants to generate interrupt on count overflow
8968 * event/every step.[get]
8969 *
8970 * @param ctx Read / write interface definitions.(ptr)
8971 * @param val Get the values of carry_count_en in reg PEDO_CMD_REG
8972 * @retval Interface status (MANDATORY: return 0 -> no Error).
8973 *
8974 */
lsm6dsrx_pedo_int_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_carry_count_en_t * val)8975 int32_t lsm6dsrx_pedo_int_mode_get(const stmdev_ctx_t *ctx,
8976 lsm6dsrx_carry_count_en_t *val)
8977 {
8978 lsm6dsrx_pedo_cmd_reg_t pedo_cmd_reg;
8979 int32_t ret;
8980
8981 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_CMD_REG,
8982 (uint8_t *)&pedo_cmd_reg);
8983
8984 switch (pedo_cmd_reg.carry_count_en)
8985 {
8986 case LSM6DSRX_EVERY_STEP:
8987 *val = LSM6DSRX_EVERY_STEP;
8988 break;
8989
8990 case LSM6DSRX_COUNT_OVERFLOW:
8991 *val = LSM6DSRX_COUNT_OVERFLOW;
8992 break;
8993
8994 default:
8995 *val = LSM6DSRX_EVERY_STEP;
8996 break;
8997 }
8998
8999 return ret;
9000 }
9001
9002 /**
9003 * @}
9004 *
9005 */
9006
9007 /**
9008 * @defgroup LSM6DSRX_significant_motion
9009 * @brief This section groups all the functions that manage the
9010 * significant motion detection.
9011 * @{
9012 *
9013 */
9014
9015 /**
9016 * @brief Enable significant motion detection function.[set]
9017 *
9018 * @param ctx Read / write interface definitions.(ptr)
9019 * @param val Change the values of sign_motion_en in reg EMB_FUNC_EN_A
9020 * @retval Interface status (MANDATORY: return 0 -> no Error).
9021 *
9022 */
lsm6dsrx_motion_sens_set(const stmdev_ctx_t * ctx,uint8_t val)9023 int32_t lsm6dsrx_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val)
9024 {
9025 lsm6dsrx_emb_func_en_a_t emb_func_en_a;
9026 int32_t ret;
9027
9028 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
9029
9030 if (ret == 0)
9031 {
9032 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
9033 (uint8_t *)&emb_func_en_a, 1);
9034 }
9035
9036 if (ret == 0)
9037 {
9038 emb_func_en_a.sign_motion_en = (uint8_t)val;
9039 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
9040 (uint8_t *)&emb_func_en_a, 1);
9041 }
9042
9043 if (ret == 0)
9044 {
9045 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
9046 }
9047
9048 return ret;
9049 }
9050
9051 /**
9052 * @brief Enable significant motion detection function.[get]
9053 *
9054 * @param ctx Read / write interface definitions.(ptr)
9055 * @param val Change the values of sign_motion_en in reg EMB_FUNC_EN_A
9056 * @retval Interface status (MANDATORY: return 0 -> no Error).
9057 *
9058 */
lsm6dsrx_motion_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)9059 int32_t lsm6dsrx_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val)
9060 {
9061 lsm6dsrx_emb_func_en_a_t emb_func_en_a;
9062 int32_t ret;
9063
9064 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
9065
9066 if (ret == 0)
9067 {
9068 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
9069 (uint8_t *)&emb_func_en_a, 1);
9070 }
9071
9072 if (ret == 0)
9073 {
9074 *val = emb_func_en_a.sign_motion_en;
9075 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
9076 }
9077
9078 return ret;
9079 }
9080
9081 /**
9082 * @brief Interrupt status bit for significant motion detection.[get]
9083 *
9084 * @param ctx Read / write interface definitions.(ptr)
9085 * @param val Change the values of is_sigmot in reg EMB_FUNC_STATUS
9086 * @retval Interface status (MANDATORY: return 0 -> no Error).
9087 *
9088 */
lsm6dsrx_motion_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)9089 int32_t lsm6dsrx_motion_flag_data_ready_get(const stmdev_ctx_t *ctx,
9090 uint8_t *val)
9091 {
9092 lsm6dsrx_emb_func_status_t emb_func_status;
9093 int32_t ret;
9094
9095 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
9096
9097 if (ret == 0)
9098 {
9099 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_STATUS,
9100 (uint8_t *)&emb_func_status, 1);
9101 }
9102
9103 if (ret == 0)
9104 {
9105 *val = emb_func_status.is_sigmot;
9106 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
9107 }
9108
9109 return ret;
9110 }
9111
9112 /**
9113 * @}
9114 *
9115 */
9116
9117 /**
9118 * @defgroup LSM6DSRX_tilt_detection
9119 * @brief This section groups all the functions that manage the tilt
9120 * event detection.
9121 * @{
9122 *
9123 */
9124
9125 /**
9126 * @brief Enable tilt calculation.[set]
9127 *
9128 * @param ctx Read / write interface definitions.(ptr)
9129 * @param val Change the values of tilt_en in reg EMB_FUNC_EN_A
9130 * @retval Interface status (MANDATORY: return 0 -> no Error).
9131 *
9132 */
lsm6dsrx_tilt_sens_set(const stmdev_ctx_t * ctx,uint8_t val)9133 int32_t lsm6dsrx_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val)
9134 {
9135 lsm6dsrx_emb_func_en_a_t emb_func_en_a;
9136 int32_t ret;
9137
9138 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
9139
9140 if (ret == 0)
9141 {
9142 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
9143 (uint8_t *)&emb_func_en_a, 1);
9144 }
9145
9146 if (ret == 0)
9147 {
9148 emb_func_en_a.tilt_en = (uint8_t)val;
9149 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
9150 (uint8_t *)&emb_func_en_a, 1);
9151 }
9152
9153 if (ret == 0)
9154 {
9155 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
9156 }
9157
9158 return ret;
9159 }
9160
9161 /**
9162 * @brief Enable tilt calculation.[get]
9163 *
9164 * @param ctx Read / write interface definitions.(ptr)
9165 * @param val Change the values of tilt_en in reg EMB_FUNC_EN_A
9166 * @retval Interface status (MANDATORY: return 0 -> no Error).
9167 *
9168 */
lsm6dsrx_tilt_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)9169 int32_t lsm6dsrx_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val)
9170 {
9171 lsm6dsrx_emb_func_en_a_t emb_func_en_a;
9172 int32_t ret;
9173
9174 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
9175
9176 if (ret == 0)
9177 {
9178 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
9179 (uint8_t *)&emb_func_en_a, 1);
9180 }
9181
9182 if (ret == 0)
9183 {
9184 *val = emb_func_en_a.tilt_en;
9185 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
9186 }
9187
9188 return ret;
9189 }
9190
9191 /**
9192 * @brief Interrupt status bit for tilt detection.[get]
9193 *
9194 * @param ctx Read / write interface definitions.(ptr)
9195 * @param val Change the values of is_tilt in reg EMB_FUNC_STATUS
9196 * @retval Interface status (MANDATORY: return 0 -> no Error).
9197 *
9198 */
lsm6dsrx_tilt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)9199 int32_t lsm6dsrx_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx,
9200 uint8_t *val)
9201 {
9202 lsm6dsrx_emb_func_status_t emb_func_status;
9203 int32_t ret;
9204
9205 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
9206
9207 if (ret == 0)
9208 {
9209 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_STATUS,
9210 (uint8_t *)&emb_func_status, 1);
9211 }
9212
9213 if (ret == 0)
9214 {
9215 *val = emb_func_status.is_tilt;
9216 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
9217 }
9218
9219 return ret;
9220 }
9221
9222 /**
9223 * @}
9224 *
9225 */
9226
9227 /**
9228 * @defgroup LSM6DSRX_ magnetometer_sensor
9229 * @brief This section groups all the functions that manage additional
9230 * magnetometer sensor.
9231 * @{
9232 *
9233 */
9234
9235 /**
9236 * @brief External magnetometer sensitivity value register.[set]
9237 *
9238 * @param ctx Read / write interface definitions.(ptr)
9239 * @param buff Buffer that contains data to write
9240 * @retval Interface status (MANDATORY: return 0 -> no Error).
9241 *
9242 */
lsm6dsrx_mag_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)9243 int32_t lsm6dsrx_mag_sensitivity_set(const stmdev_ctx_t *ctx,
9244 uint16_t val)
9245 {
9246 uint8_t buff[2];
9247 int32_t ret;
9248
9249 buff[1] = (uint8_t)(val / 256U);
9250 buff[0] = (uint8_t)(val - (buff[1] * 256U));
9251 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SENSITIVITY_L,
9252 &buff[0]);
9253
9254 if (ret == 0)
9255 {
9256 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SENSITIVITY_H,
9257 &buff[1]);
9258 }
9259
9260 return ret;
9261 }
9262
9263 /**
9264 * @brief External magnetometer sensitivity value register.[get]
9265 *
9266 * @param ctx Read / write interface definitions.(ptr)
9267 * @param buff Buffer that stores data read
9268 * @retval Interface status (MANDATORY: return 0 -> no Error).
9269 *
9270 */
lsm6dsrx_mag_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)9271 int32_t lsm6dsrx_mag_sensitivity_get(const stmdev_ctx_t *ctx,
9272 uint16_t *val)
9273 {
9274 uint8_t buff[2];
9275 int32_t ret;
9276
9277 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SENSITIVITY_L,
9278 &buff[0]);
9279
9280 if (ret == 0)
9281 {
9282 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SENSITIVITY_H,
9283 &buff[1]);
9284 *val = buff[1];
9285 *val = (*val * 256U) + buff[0];
9286 }
9287
9288 return ret;
9289 }
9290
9291 /**
9292 * @brief Offset for hard-iron compensation register (r/w).[set]
9293 *
9294 * @param ctx Read / write interface definitions.(ptr)
9295 * @param buff Buffer that contains data to write
9296 * @retval Interface status (MANDATORY: return 0 -> no Error).
9297 *
9298 */
lsm6dsrx_mag_offset_set(const stmdev_ctx_t * ctx,int16_t * val)9299 int32_t lsm6dsrx_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val)
9300 {
9301 uint8_t buff[6];
9302 int32_t ret;
9303 uint8_t i;
9304
9305 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
9306 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
9307 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
9308 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
9309 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
9310 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
9311 i = 0x00U;
9312 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_OFFX_L, &buff[i]);
9313
9314 if (ret == 0)
9315 {
9316 i++;
9317 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_OFFX_H, &buff[i]);
9318 }
9319
9320 if (ret == 0)
9321 {
9322 i++;
9323 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_OFFY_L, &buff[i]);
9324 }
9325
9326 if (ret == 0)
9327 {
9328 i++;
9329 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_OFFY_H, &buff[i]);
9330 }
9331
9332 if (ret == 0)
9333 {
9334 i++;
9335 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_OFFZ_L, &buff[i]);
9336 }
9337
9338 if (ret == 0)
9339 {
9340 i++;
9341 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_OFFZ_H, &buff[i]);
9342 }
9343
9344 return ret;
9345 }
9346
9347 /**
9348 * @brief Offset for hard-iron compensation register (r/w).[get]
9349 *
9350 * @param ctx Read / write interface definitions.(ptr)
9351 * @param buff Buffer that stores data read
9352 * @retval Interface status (MANDATORY: return 0 -> no Error).
9353 *
9354 */
lsm6dsrx_mag_offset_get(const stmdev_ctx_t * ctx,int16_t * val)9355 int32_t lsm6dsrx_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
9356 {
9357 uint8_t buff[6];
9358 int32_t ret;
9359 uint8_t i;
9360
9361 i = 0x00U;
9362 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_OFFX_L, &buff[i]);
9363
9364 if (ret == 0)
9365 {
9366 i++;
9367 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_OFFX_H, &buff[i]);
9368 }
9369
9370 if (ret == 0)
9371 {
9372 i++;
9373 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_OFFY_L, &buff[i]);
9374 }
9375
9376 if (ret == 0)
9377 {
9378 i++;
9379 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_OFFY_H, &buff[i]);
9380 }
9381
9382 if (ret == 0)
9383 {
9384 i++;
9385 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_OFFZ_L, &buff[i]);
9386 }
9387
9388 if (ret == 0)
9389 {
9390 i++;
9391 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_OFFZ_H, &buff[i]);
9392
9393 val[0] = (int16_t)buff[1];
9394 val[0] = (val[0] * 256) + (int16_t)buff[0];
9395 val[1] = (int16_t)buff[3];
9396 val[1] = (val[1] * 256) + (int16_t)buff[2];
9397 val[2] = (int16_t)buff[5];
9398 val[2] = (val[2] * 256) + (int16_t)buff[4];
9399 }
9400
9401 return ret;
9402 }
9403
9404 /**
9405 * @brief Soft-iron (3x3 symmetric) matrix correction register (r/w).
9406 * The value is expressed as half-precision floating-point format:
9407 * SEEEEEFFFFFFFFFF
9408 * S: 1 sign bit;
9409 * E: 5 exponent bits;
9410 * F: 10 fraction bits).[set]
9411 *
9412 * @param ctx Read / write interface definitions.(ptr)
9413 * @param buff Buffer that contains data to write
9414 * @retval Interface status (MANDATORY: return 0 -> no Error).
9415 *
9416 */
lsm6dsrx_mag_soft_iron_set(const stmdev_ctx_t * ctx,uint16_t * val)9417 int32_t lsm6dsrx_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val)
9418 {
9419 uint8_t buff[12];
9420 int32_t ret;
9421 uint8_t i;
9422
9423 buff[1] = (uint8_t)(val[0] / 256U);
9424 buff[0] = (uint8_t)(val[0] - (buff[1] * 256U));
9425 buff[3] = (uint8_t)(val[1] / 256U);
9426 buff[2] = (uint8_t)(val[1] - (buff[3] * 256U));
9427 buff[5] = (uint8_t)(val[2] / 256U);
9428 buff[4] = (uint8_t)(val[2] - (buff[5] * 256U));
9429 buff[7] = (uint8_t)(val[3] / 256U);
9430 buff[6] = (uint8_t)(val[3] - (buff[1] * 256U));
9431 buff[9] = (uint8_t)(val[4] / 256U);
9432 buff[8] = (uint8_t)(val[4] - (buff[3] * 256U));
9433 buff[11] = (uint8_t)(val[5] / 256U);
9434 buff[10] = (uint8_t)(val[5] - (buff[5] * 256U));
9435 i = 0x00U;
9436 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_XX_L,
9437 &buff[i]);
9438
9439 if (ret == 0)
9440 {
9441 i++;
9442 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_XX_H,
9443 &buff[i]);
9444 }
9445
9446 if (ret == 0)
9447 {
9448 i++;
9449 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_XY_L,
9450 &buff[i]);
9451 }
9452
9453 if (ret == 0)
9454 {
9455 i++;
9456 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_XY_H,
9457 &buff[i]);
9458 }
9459
9460 if (ret == 0)
9461 {
9462 i++;
9463 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_XZ_L,
9464 &buff[i]);
9465 }
9466
9467 if (ret == 0)
9468 {
9469 i++;
9470 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_XZ_H,
9471 &buff[i]);
9472 }
9473
9474 if (ret == 0)
9475 {
9476 i++;
9477 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_YY_L,
9478 &buff[i]);
9479 }
9480
9481 if (ret == 0)
9482 {
9483 i++;
9484 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_YY_H,
9485 &buff[i]);
9486 }
9487
9488 if (ret == 0)
9489 {
9490 i++;
9491 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_YZ_L,
9492 &buff[i]);
9493 }
9494
9495 if (ret == 0)
9496 {
9497 i++;
9498 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_YZ_H,
9499 &buff[i]);
9500 }
9501
9502 if (ret == 0)
9503 {
9504 i++;
9505 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_ZZ_L,
9506 &buff[i]);
9507 }
9508
9509 if (ret == 0)
9510 {
9511 i++;
9512 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_ZZ_H,
9513 &buff[i]);
9514 }
9515
9516 return ret;
9517 }
9518
9519 /**
9520 * @brief Soft-iron (3x3 symmetric) matrix correction register (r/w).
9521 * The value is expressed as half-precision floating-point format:
9522 * SEEEEEFFFFFFFFFF
9523 * S: 1 sign bit;
9524 * E: 5 exponent bits;
9525 * F: 10 fraction bits).[get]
9526 *
9527 * @param ctx Read / write interface definitions.(ptr)
9528 * @param buff Buffer that stores data read
9529 * @retval Interface status (MANDATORY: return 0 -> no Error).
9530 *
9531 */
lsm6dsrx_mag_soft_iron_get(const stmdev_ctx_t * ctx,uint16_t * val)9532 int32_t lsm6dsrx_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val)
9533 {
9534 uint8_t buff[12];
9535 int32_t ret;
9536 uint8_t i;
9537
9538 i = 0x00U;
9539 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_XX_L,
9540 &buff[i]);
9541
9542 if (ret == 0)
9543 {
9544 i++;
9545 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_XX_H,
9546 &buff[i]);
9547 }
9548
9549 if (ret == 0)
9550 {
9551 i++;
9552 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_XY_L,
9553 &buff[i]);
9554 }
9555
9556 if (ret == 0)
9557 {
9558 i++;
9559 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_XY_H,
9560 &buff[i]);
9561 }
9562
9563 if (ret == 0)
9564 {
9565 i++;
9566 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_XZ_L,
9567 &buff[i]);
9568 }
9569
9570 if (ret == 0)
9571 {
9572 i++;
9573 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_XZ_H,
9574 &buff[i]);
9575 }
9576
9577 if (ret == 0)
9578 {
9579 i++;
9580 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_YY_L,
9581 &buff[i]);
9582 }
9583
9584 if (ret == 0)
9585 {
9586 i++;
9587 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_YY_H,
9588 &buff[i]);
9589 }
9590
9591 if (ret == 0)
9592 {
9593 i++;
9594 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_YZ_L,
9595 &buff[i]);
9596 }
9597
9598 if (ret == 0)
9599 {
9600 i++;
9601 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_YZ_H,
9602 &buff[i]);
9603 }
9604
9605 if (ret == 0)
9606 {
9607 i++;
9608 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_ZZ_L,
9609 &buff[i]);
9610 }
9611
9612 if (ret == 0)
9613 {
9614 i++;
9615 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_ZZ_H,
9616 &buff[i]);
9617 }
9618
9619 val[0] = buff[1];
9620 val[0] = (val[0] * 256U) + buff[0];
9621 val[1] = buff[3];
9622 val[1] = (val[1] * 256U) + buff[2];
9623 val[2] = buff[5];
9624 val[2] = (val[2] * 256U) + buff[4];
9625 val[3] = buff[7];
9626 val[3] = (val[3] * 256U) + buff[6];
9627 val[4] = buff[9];
9628 val[4] = (val[4] * 256U) + buff[8];
9629 val[5] = buff[11];
9630 val[6] = (val[5] * 256U) + buff[10];
9631
9632 return ret;
9633 }
9634
9635 /**
9636 * @brief Magnetometer Z-axis coordinates rotation (to be aligned to
9637 * accelerometer/gyroscope axes orientation).[set]
9638 *
9639 * @param ctx Read / write interface definitions.(ptr)
9640 * @param val Change the values of mag_z_axis in reg MAG_CFG_A
9641 * @retval Interface status (MANDATORY: return 0 -> no Error).
9642 *
9643 */
lsm6dsrx_mag_z_orient_set(const stmdev_ctx_t * ctx,lsm6dsrx_mag_z_axis_t val)9644 int32_t lsm6dsrx_mag_z_orient_set(const stmdev_ctx_t *ctx,
9645 lsm6dsrx_mag_z_axis_t val)
9646 {
9647 lsm6dsrx_mag_cfg_a_t mag_cfg_a;
9648 int32_t ret;
9649
9650 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_A,
9651 (uint8_t *)&mag_cfg_a);
9652
9653 if (ret == 0)
9654 {
9655 mag_cfg_a.mag_z_axis = (uint8_t)val;
9656 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_CFG_A,
9657 (uint8_t *)&mag_cfg_a);
9658 }
9659
9660 return ret;
9661 }
9662
9663 /**
9664 * @brief Magnetometer Z-axis coordinates rotation (to be aligned to
9665 * accelerometer/gyroscope axes orientation).[get]
9666 *
9667 * @param ctx Read / write interface definitions.(ptr)
9668 * @param val Get the values of mag_z_axis in reg MAG_CFG_A
9669 * @retval Interface status (MANDATORY: return 0 -> no Error).
9670 *
9671 */
lsm6dsrx_mag_z_orient_get(const stmdev_ctx_t * ctx,lsm6dsrx_mag_z_axis_t * val)9672 int32_t lsm6dsrx_mag_z_orient_get(const stmdev_ctx_t *ctx,
9673 lsm6dsrx_mag_z_axis_t *val)
9674 {
9675 lsm6dsrx_mag_cfg_a_t mag_cfg_a;
9676 int32_t ret;
9677
9678 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_A,
9679 (uint8_t *)&mag_cfg_a);
9680
9681 switch (mag_cfg_a.mag_z_axis)
9682 {
9683 case LSM6DSRX_Z_EQ_Y:
9684 *val = LSM6DSRX_Z_EQ_Y;
9685 break;
9686
9687 case LSM6DSRX_Z_EQ_MIN_Y:
9688 *val = LSM6DSRX_Z_EQ_MIN_Y;
9689 break;
9690
9691 case LSM6DSRX_Z_EQ_X:
9692 *val = LSM6DSRX_Z_EQ_X;
9693 break;
9694
9695 case LSM6DSRX_Z_EQ_MIN_X:
9696 *val = LSM6DSRX_Z_EQ_MIN_X;
9697 break;
9698
9699 case LSM6DSRX_Z_EQ_MIN_Z:
9700 *val = LSM6DSRX_Z_EQ_MIN_Z;
9701 break;
9702
9703 case LSM6DSRX_Z_EQ_Z:
9704 *val = LSM6DSRX_Z_EQ_Z;
9705 break;
9706
9707 default:
9708 *val = LSM6DSRX_Z_EQ_Y;
9709 break;
9710 }
9711
9712 return ret;
9713 }
9714
9715 /**
9716 * @brief Magnetometer Y-axis coordinates rotation (to be aligned to
9717 * accelerometer/gyroscope axes orientation).[set]
9718 *
9719 * @param ctx Read / write interface definitions.(ptr)
9720 * @param val Change the values of mag_y_axis in
9721 * reg MAG_CFG_A
9722 * @retval Interface status (MANDATORY: return 0 -> no Error).
9723 *
9724 */
lsm6dsrx_mag_y_orient_set(const stmdev_ctx_t * ctx,lsm6dsrx_mag_y_axis_t val)9725 int32_t lsm6dsrx_mag_y_orient_set(const stmdev_ctx_t *ctx,
9726 lsm6dsrx_mag_y_axis_t val)
9727 {
9728 lsm6dsrx_mag_cfg_a_t mag_cfg_a;
9729 int32_t ret;
9730
9731 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_A,
9732 (uint8_t *)&mag_cfg_a);
9733
9734 if (ret == 0)
9735 {
9736 mag_cfg_a.mag_y_axis = (uint8_t)val;
9737 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_CFG_A,
9738 (uint8_t *)&mag_cfg_a);
9739 }
9740
9741 return ret;
9742 }
9743
9744 /**
9745 * @brief Magnetometer Y-axis coordinates rotation (to be aligned to
9746 * accelerometer/gyroscope axes orientation).[get]
9747 *
9748 * @param ctx Read / write interface definitions.(ptr)
9749 * @param val Get the values of mag_y_axis in reg MAG_CFG_A
9750 * @retval Interface status (MANDATORY: return 0 -> no Error).
9751 *
9752 */
lsm6dsrx_mag_y_orient_get(const stmdev_ctx_t * ctx,lsm6dsrx_mag_y_axis_t * val)9753 int32_t lsm6dsrx_mag_y_orient_get(const stmdev_ctx_t *ctx,
9754 lsm6dsrx_mag_y_axis_t *val)
9755 {
9756 lsm6dsrx_mag_cfg_a_t mag_cfg_a;
9757 int32_t ret;
9758
9759 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_A,
9760 (uint8_t *)&mag_cfg_a);
9761
9762 switch (mag_cfg_a.mag_y_axis)
9763 {
9764 case LSM6DSRX_Y_EQ_Y:
9765 *val = LSM6DSRX_Y_EQ_Y;
9766 break;
9767
9768 case LSM6DSRX_Y_EQ_MIN_Y:
9769 *val = LSM6DSRX_Y_EQ_MIN_Y;
9770 break;
9771
9772 case LSM6DSRX_Y_EQ_X:
9773 *val = LSM6DSRX_Y_EQ_X;
9774 break;
9775
9776 case LSM6DSRX_Y_EQ_MIN_X:
9777 *val = LSM6DSRX_Y_EQ_MIN_X;
9778 break;
9779
9780 case LSM6DSRX_Y_EQ_MIN_Z:
9781 *val = LSM6DSRX_Y_EQ_MIN_Z;
9782 break;
9783
9784 case LSM6DSRX_Y_EQ_Z:
9785 *val = LSM6DSRX_Y_EQ_Z;
9786 break;
9787
9788 default:
9789 *val = LSM6DSRX_Y_EQ_Y;
9790 break;
9791 }
9792
9793 return ret;
9794 }
9795
9796 /**
9797 * @brief Magnetometer X-axis coordinates rotation (to be aligned to
9798 * accelerometer/gyroscope axes orientation).[set]
9799 *
9800 * @param ctx Read / write interface definitions.(ptr)
9801 * @param val Change the values of mag_x_axis in reg MAG_CFG_B
9802 * @retval Interface status (MANDATORY: return 0 -> no Error).
9803 *
9804 */
lsm6dsrx_mag_x_orient_set(const stmdev_ctx_t * ctx,lsm6dsrx_mag_x_axis_t val)9805 int32_t lsm6dsrx_mag_x_orient_set(const stmdev_ctx_t *ctx,
9806 lsm6dsrx_mag_x_axis_t val)
9807 {
9808 lsm6dsrx_mag_cfg_b_t mag_cfg_b;
9809 int32_t ret;
9810
9811 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_B,
9812 (uint8_t *)&mag_cfg_b);
9813
9814 if (ret == 0)
9815 {
9816 mag_cfg_b.mag_x_axis = (uint8_t)val;
9817 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_CFG_B,
9818 (uint8_t *)&mag_cfg_b);
9819 }
9820
9821 return ret;
9822 }
9823
9824 /**
9825 * @brief Magnetometer X-axis coordinates rotation (to be aligned to
9826 * accelerometer/gyroscope axes orientation).[get]
9827 *
9828 * @param ctx Read / write interface definitions.(ptr)
9829 * @param val Get the values of mag_x_axis in reg MAG_CFG_B
9830 * @retval Interface status (MANDATORY: return 0 -> no Error).
9831 *
9832 */
lsm6dsrx_mag_x_orient_get(const stmdev_ctx_t * ctx,lsm6dsrx_mag_x_axis_t * val)9833 int32_t lsm6dsrx_mag_x_orient_get(const stmdev_ctx_t *ctx,
9834 lsm6dsrx_mag_x_axis_t *val)
9835 {
9836 lsm6dsrx_mag_cfg_b_t mag_cfg_b;
9837 int32_t ret;
9838
9839 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_B,
9840 (uint8_t *)&mag_cfg_b);
9841
9842 switch (mag_cfg_b.mag_x_axis)
9843 {
9844 case LSM6DSRX_X_EQ_Y:
9845 *val = LSM6DSRX_X_EQ_Y;
9846 break;
9847
9848 case LSM6DSRX_X_EQ_MIN_Y:
9849 *val = LSM6DSRX_X_EQ_MIN_Y;
9850 break;
9851
9852 case LSM6DSRX_X_EQ_X:
9853 *val = LSM6DSRX_X_EQ_X;
9854 break;
9855
9856 case LSM6DSRX_X_EQ_MIN_X:
9857 *val = LSM6DSRX_X_EQ_MIN_X;
9858 break;
9859
9860 case LSM6DSRX_X_EQ_MIN_Z:
9861 *val = LSM6DSRX_X_EQ_MIN_Z;
9862 break;
9863
9864 case LSM6DSRX_X_EQ_Z:
9865 *val = LSM6DSRX_X_EQ_Z;
9866 break;
9867
9868 default:
9869 *val = LSM6DSRX_X_EQ_Y;
9870 break;
9871 }
9872
9873 return ret;
9874 }
9875
9876 /**
9877 * @}
9878 *
9879 */
9880
9881 /**
9882 * @defgroup LSM6DSRX_finite_state_machine
9883 * @brief This section groups all the functions that manage the
9884 * state_machine.
9885 * @{
9886 *
9887 */
9888
9889 /**
9890 * @brief Interrupt status bit for FSM long counter timeout interrupt
9891 * event.[get]
9892 *
9893 * @param ctx Read / write interface definitions.(ptr)
9894 * @param val Change the values of is_fsm_lc in reg EMB_FUNC_STATUS
9895 * @retval Interface status (MANDATORY: return 0 -> no Error).
9896 *
9897 */
lsm6dsrx_long_cnt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)9898 int32_t lsm6dsrx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx,
9899 uint8_t *val)
9900 {
9901 lsm6dsrx_emb_func_status_t emb_func_status;
9902 int32_t ret;
9903
9904 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
9905
9906 if (ret == 0)
9907 {
9908 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_STATUS,
9909 (uint8_t *)&emb_func_status, 1);
9910 }
9911
9912 if (ret == 0)
9913 {
9914 *val = emb_func_status.is_fsm_lc;
9915 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
9916 }
9917
9918 return ret;
9919 }
9920
9921 /**
9922 * @brief Embedded final state machine functions mode.[set]
9923 *
9924 * @param ctx Read / write interface definitions.(ptr)
9925 * @param val Change the values of fsm_en in reg EMB_FUNC_EN_B
9926 * @retval Interface status (MANDATORY: return 0 -> no Error).
9927 *
9928 */
lsm6dsrx_emb_fsm_en_set(const stmdev_ctx_t * ctx,uint8_t val)9929 int32_t lsm6dsrx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val)
9930 {
9931 int32_t ret;
9932
9933 lsm6dsrx_emb_func_en_b_t emb_func_en_b;
9934 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
9935
9936 if (ret == 0)
9937 {
9938 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
9939 (uint8_t *)&emb_func_en_b, 1);
9940 }
9941
9942 if (ret == 0)
9943 {
9944 emb_func_en_b.fsm_en = (uint8_t)val;
9945 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
9946 (uint8_t *)&emb_func_en_b, 1);
9947 }
9948
9949 if (ret == 0)
9950 {
9951 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
9952 }
9953
9954 return ret;
9955 }
9956
9957 /**
9958 * @brief Embedded final state machine functions mode.[get]
9959 *
9960 * @param ctx Read / write interface definitions.(ptr)
9961 * @param val Get the values of fsm_en in reg EMB_FUNC_EN_B
9962 * @retval Interface status (MANDATORY: return 0 -> no Error).
9963 *
9964 */
lsm6dsrx_emb_fsm_en_get(const stmdev_ctx_t * ctx,uint8_t * val)9965 int32_t lsm6dsrx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val)
9966 {
9967 int32_t ret;
9968 lsm6dsrx_emb_func_en_b_t emb_func_en_b;
9969
9970 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
9971
9972 if (ret == 0)
9973 {
9974 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
9975 (uint8_t *)&emb_func_en_b, 1);
9976 }
9977
9978 if (ret == 0)
9979 {
9980 *val = emb_func_en_b.fsm_en;
9981 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
9982 (uint8_t *)&emb_func_en_b, 1);
9983 }
9984
9985 if (ret == 0)
9986 {
9987 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
9988 }
9989
9990 return ret;
9991 }
9992
9993 /**
9994 * @brief Embedded final state machine functions mode.[set]
9995 *
9996 * @param ctx Read / write interface definitions.(ptr)
9997 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
9998 * @retval Interface status (MANDATORY: return 0 -> no Error).
9999 *
10000 */
lsm6dsrx_fsm_enable_set(const stmdev_ctx_t * ctx,lsm6dsrx_emb_fsm_enable_t * val)10001 int32_t lsm6dsrx_fsm_enable_set(const stmdev_ctx_t *ctx,
10002 lsm6dsrx_emb_fsm_enable_t *val)
10003 {
10004 lsm6dsrx_emb_func_en_b_t emb_func_en_b;
10005 int32_t ret;
10006
10007 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10008
10009 if (ret == 0)
10010 {
10011 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_ENABLE_A,
10012 (uint8_t *)&val->fsm_enable_a, 1);
10013 }
10014
10015 if (ret == 0)
10016 {
10017 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_ENABLE_B,
10018 (uint8_t *)&val->fsm_enable_b, 1);
10019 }
10020
10021 if (ret == 0)
10022 {
10023 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
10024 (uint8_t *)&emb_func_en_b, 1);
10025 }
10026
10027 if (ret == 0)
10028 {
10029 if ((val->fsm_enable_a.fsm1_en |
10030 val->fsm_enable_a.fsm2_en |
10031 val->fsm_enable_a.fsm3_en |
10032 val->fsm_enable_a.fsm4_en |
10033 val->fsm_enable_a.fsm5_en |
10034 val->fsm_enable_a.fsm6_en |
10035 val->fsm_enable_a.fsm7_en |
10036 val->fsm_enable_a.fsm8_en |
10037 val->fsm_enable_b.fsm9_en |
10038 val->fsm_enable_b.fsm10_en |
10039 val->fsm_enable_b.fsm11_en |
10040 val->fsm_enable_b.fsm12_en |
10041 val->fsm_enable_b.fsm13_en |
10042 val->fsm_enable_b.fsm14_en |
10043 val->fsm_enable_b.fsm15_en |
10044 val->fsm_enable_b.fsm16_en) != PROPERTY_DISABLE)
10045 {
10046 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
10047 }
10048
10049 else
10050 {
10051 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
10052 }
10053 }
10054
10055 if (ret == 0)
10056 {
10057 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
10058 (uint8_t *)&emb_func_en_b, 1);
10059 }
10060
10061 if (ret == 0)
10062 {
10063 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10064 }
10065
10066 return ret;
10067 }
10068
10069 /**
10070 * @brief Embedded final state machine functions mode.[get]
10071 *
10072 * @param ctx Read / write interface definitions.(ptr)
10073 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
10074 * @retval Interface status (MANDATORY: return 0 -> no Error).
10075 *
10076 */
lsm6dsrx_fsm_enable_get(const stmdev_ctx_t * ctx,lsm6dsrx_emb_fsm_enable_t * val)10077 int32_t lsm6dsrx_fsm_enable_get(const stmdev_ctx_t *ctx,
10078 lsm6dsrx_emb_fsm_enable_t *val)
10079 {
10080 int32_t ret;
10081
10082 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10083
10084 if (ret == 0)
10085 {
10086 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_ENABLE_A,
10087 (uint8_t *)&val->fsm_enable_a, 1);
10088 }
10089
10090 if (ret == 0)
10091 {
10092 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_ENABLE_B,
10093 (uint8_t *)&val->fsm_enable_b, 1);
10094 }
10095
10096 if (ret == 0)
10097 {
10098 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10099 }
10100
10101 return ret;
10102 }
10103
10104 /**
10105 * @brief FSM long counter status register. Long counter value is an
10106 * unsigned integer value (16-bit format).[set]
10107 *
10108 * @param ctx Read / write interface definitions.(ptr)
10109 * @param buff Buffer that contains data to write
10110 * @retval Interface status (MANDATORY: return 0 -> no Error).
10111 *
10112 */
lsm6dsrx_long_cnt_set(const stmdev_ctx_t * ctx,uint16_t val)10113 int32_t lsm6dsrx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val)
10114 {
10115 uint8_t buff[2];
10116 int32_t ret;
10117
10118 buff[1] = (uint8_t)(val / 256U);
10119 buff[0] = (uint8_t)(val - (buff[1] * 256U));
10120 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10121
10122 if (ret == 0)
10123 {
10124 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_LONG_COUNTER_L, buff,
10125 2);
10126 }
10127
10128 if (ret == 0)
10129 {
10130 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10131 }
10132
10133 return ret;
10134 }
10135
10136 /**
10137 * @brief FSM long counter status register. Long counter value is an
10138 * unsigned integer value (16-bit format).[get]
10139 *
10140 * @param ctx Read / write interface definitions.(ptr)
10141 * @param buff Buffer that stores data read
10142 * @retval Interface status (MANDATORY: return 0 -> no Error).
10143 *
10144 */
lsm6dsrx_long_cnt_get(const stmdev_ctx_t * ctx,uint16_t * val)10145 int32_t lsm6dsrx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val)
10146 {
10147 uint8_t buff[2];
10148 int32_t ret;
10149
10150 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10151
10152 if (ret == 0)
10153 {
10154 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_LONG_COUNTER_L, buff,
10155 2);
10156 *val = buff[1];
10157 *val = (*val * 256U) + buff[0];
10158 }
10159
10160 if (ret == 0)
10161 {
10162 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10163 }
10164
10165 return ret;
10166 }
10167
10168 /**
10169 * @brief Clear FSM long counter value.[set]
10170 *
10171 * @param ctx Read / write interface definitions.(ptr)
10172 * @param val Change the values of fsm_lc_clr in reg
10173 * FSM_LONG_COUNTER_CLEAR
10174 * @retval Interface status (MANDATORY: return 0 -> no Error).
10175 *
10176 */
lsm6dsrx_long_clr_set(const stmdev_ctx_t * ctx,lsm6dsrx_fsm_lc_clr_t val)10177 int32_t lsm6dsrx_long_clr_set(const stmdev_ctx_t *ctx,
10178 lsm6dsrx_fsm_lc_clr_t val)
10179 {
10180 lsm6dsrx_fsm_long_counter_clear_t fsm_long_counter_clear;
10181 int32_t ret;
10182
10183 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10184
10185 if (ret == 0)
10186 {
10187 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_LONG_COUNTER_CLEAR,
10188 (uint8_t *)&fsm_long_counter_clear, 1);
10189 }
10190
10191 if (ret == 0)
10192 {
10193 fsm_long_counter_clear.fsm_lc_clr = (uint8_t)val;
10194 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_LONG_COUNTER_CLEAR,
10195 (uint8_t *)&fsm_long_counter_clear, 1);
10196 }
10197
10198 if (ret == 0)
10199 {
10200 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10201 }
10202
10203 return ret;
10204 }
10205
10206 /**
10207 * @brief Clear FSM long counter value.[get]
10208 *
10209 * @param ctx Read / write interface definitions.(ptr)
10210 * @param val Get the values of fsm_lc_clr in reg FSM_LONG_COUNTER_CLEAR
10211 * @retval Interface status (MANDATORY: return 0 -> no Error).
10212 *
10213 */
lsm6dsrx_long_clr_get(const stmdev_ctx_t * ctx,lsm6dsrx_fsm_lc_clr_t * val)10214 int32_t lsm6dsrx_long_clr_get(const stmdev_ctx_t *ctx,
10215 lsm6dsrx_fsm_lc_clr_t *val)
10216 {
10217 lsm6dsrx_fsm_long_counter_clear_t fsm_long_counter_clear;
10218 int32_t ret;
10219
10220 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10221
10222 if (ret == 0)
10223 {
10224 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_LONG_COUNTER_CLEAR,
10225 (uint8_t *)&fsm_long_counter_clear, 1);
10226 }
10227
10228 if (ret == 0)
10229 {
10230 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10231 }
10232
10233 switch (fsm_long_counter_clear.fsm_lc_clr)
10234 {
10235 case LSM6DSRX_LC_NORMAL:
10236 *val = LSM6DSRX_LC_NORMAL;
10237 break;
10238
10239 case LSM6DSRX_LC_CLEAR:
10240 *val = LSM6DSRX_LC_CLEAR;
10241 break;
10242
10243 case LSM6DSRX_LC_CLEAR_DONE:
10244 *val = LSM6DSRX_LC_CLEAR_DONE;
10245 break;
10246
10247 default:
10248 *val = LSM6DSRX_LC_NORMAL;
10249 break;
10250 }
10251
10252 return ret;
10253 }
10254
10255 /**
10256 * @brief FSM output registers.[get]
10257 *
10258 * @param ctx Read / write interface definitions.(ptr)
10259 * @param val Structure of registers from FSM_OUTS1 to FSM_OUTS16
10260 * @retval Interface status (MANDATORY: return 0 -> no Error).
10261 *
10262 */
lsm6dsrx_fsm_out_get(const stmdev_ctx_t * ctx,lsm6dsrx_fsm_out_t * val)10263 int32_t lsm6dsrx_fsm_out_get(const stmdev_ctx_t *ctx,
10264 lsm6dsrx_fsm_out_t *val)
10265 {
10266 int32_t ret;
10267
10268 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10269
10270 if (ret == 0)
10271 {
10272 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_OUTS1,
10273 (uint8_t *)&val->fsm_outs1, 16);
10274 }
10275
10276 if (ret == 0)
10277 {
10278 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10279 }
10280
10281 return ret;
10282 }
10283
10284 /**
10285 * @brief Finite State Machine ODR configuration.[set]
10286 *
10287 * @param ctx Read / write interface definitions.(ptr)
10288 * @param val Change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
10289 * @retval Interface status (MANDATORY: return 0 -> no Error).
10290 *
10291 */
lsm6dsrx_fsm_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsrx_fsm_odr_t val)10292 int32_t lsm6dsrx_fsm_data_rate_set(const stmdev_ctx_t *ctx,
10293 lsm6dsrx_fsm_odr_t val)
10294 {
10295 lsm6dsrx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
10296 int32_t ret;
10297
10298 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10299
10300 if (ret == 0)
10301 {
10302 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_ODR_CFG_B,
10303 (uint8_t *)&emb_func_odr_cfg_b, 1);
10304 }
10305
10306 if (ret == 0)
10307 {
10308 emb_func_odr_cfg_b.not_used_01 = 3; /* set default values */
10309 emb_func_odr_cfg_b.not_used_02 = 1; /* set default values */
10310 emb_func_odr_cfg_b.fsm_odr = (uint8_t)val;
10311 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_ODR_CFG_B,
10312 (uint8_t *)&emb_func_odr_cfg_b, 1);
10313 }
10314
10315 if (ret == 0)
10316 {
10317 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10318 }
10319
10320 return ret;
10321 }
10322
10323 /**
10324 * @brief Finite State Machine ODR configuration.[get]
10325 *
10326 * @param ctx Read / write interface definitions.(ptr)
10327 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
10328 * @retval Interface status (MANDATORY: return 0 -> no Error).
10329 *
10330 */
lsm6dsrx_fsm_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsrx_fsm_odr_t * val)10331 int32_t lsm6dsrx_fsm_data_rate_get(const stmdev_ctx_t *ctx,
10332 lsm6dsrx_fsm_odr_t *val)
10333 {
10334 lsm6dsrx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
10335 int32_t ret;
10336
10337 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10338
10339 if (ret == 0)
10340 {
10341 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_ODR_CFG_B,
10342 (uint8_t *)&emb_func_odr_cfg_b, 1);
10343 }
10344
10345 if (ret == 0)
10346 {
10347 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10348 }
10349
10350 switch (emb_func_odr_cfg_b.fsm_odr)
10351 {
10352 case LSM6DSRX_ODR_FSM_12Hz5:
10353 *val = LSM6DSRX_ODR_FSM_12Hz5;
10354 break;
10355
10356 case LSM6DSRX_ODR_FSM_26Hz:
10357 *val = LSM6DSRX_ODR_FSM_26Hz;
10358 break;
10359
10360 case LSM6DSRX_ODR_FSM_52Hz:
10361 *val = LSM6DSRX_ODR_FSM_52Hz;
10362 break;
10363
10364 case LSM6DSRX_ODR_FSM_104Hz:
10365 *val = LSM6DSRX_ODR_FSM_104Hz;
10366 break;
10367
10368 default:
10369 *val = LSM6DSRX_ODR_FSM_12Hz5;
10370 break;
10371 }
10372
10373 return ret;
10374 }
10375
10376 /**
10377 * @brief FSM initialization request.[set]
10378 *
10379 * @param ctx Read / write interface definitions.(ptr)
10380 * @param val Change the values of fsm_init in reg FSM_INIT
10381 * @retval Interface status (MANDATORY: return 0 -> no Error).
10382 *
10383 */
lsm6dsrx_fsm_init_set(const stmdev_ctx_t * ctx,uint8_t val)10384 int32_t lsm6dsrx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val)
10385 {
10386 lsm6dsrx_emb_func_init_b_t emb_func_init_b;
10387 int32_t ret;
10388
10389 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10390
10391 if (ret == 0)
10392 {
10393 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
10394 (uint8_t *)&emb_func_init_b, 1);
10395 }
10396
10397 if (ret == 0)
10398 {
10399 emb_func_init_b.fsm_init = (uint8_t)val;
10400 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
10401 (uint8_t *)&emb_func_init_b, 1);
10402 }
10403
10404 if (ret == 0)
10405 {
10406 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10407 }
10408
10409 return ret;
10410 }
10411
10412 /**
10413 * @brief FSM initialization request.[get]
10414 *
10415 * @param ctx Read / write interface definitions.(ptr)
10416 * @param val Change the values of fsm_init in reg FSM_INIT
10417 * @retval Interface status (MANDATORY: return 0 -> no Error).
10418 *
10419 */
lsm6dsrx_fsm_init_get(const stmdev_ctx_t * ctx,uint8_t * val)10420 int32_t lsm6dsrx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val)
10421 {
10422 lsm6dsrx_emb_func_init_b_t emb_func_init_b;
10423 int32_t ret;
10424
10425 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10426
10427 if (ret == 0)
10428 {
10429 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
10430 (uint8_t *)&emb_func_init_b, 1);
10431 }
10432
10433 if (ret == 0)
10434 {
10435 *val = emb_func_init_b.fsm_init;
10436 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10437 }
10438
10439 return ret;
10440 }
10441
10442 /**
10443 * @brief FSM long counter timeout register (r/w). The long counter
10444 * timeout value is an unsigned integer value (16-bit format).
10445 * When the long counter value reached this value, the FSM
10446 * generates an interrupt.[set]
10447 *
10448 * @param ctx Read / write interface definitions.(ptr)
10449 * @param buff Buffer that contains data to write
10450 * @retval Interface status (MANDATORY: return 0 -> no Error).
10451 *
10452 */
lsm6dsrx_long_cnt_int_value_set(const stmdev_ctx_t * ctx,uint16_t val)10453 int32_t lsm6dsrx_long_cnt_int_value_set(const stmdev_ctx_t *ctx,
10454 uint16_t val)
10455 {
10456 uint8_t buff[2];
10457 int32_t ret;
10458
10459 buff[1] = (uint8_t)(val / 256U);
10460 buff[0] = (uint8_t)(val - (buff[1] * 256U));
10461 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_LC_TIMEOUT_L,
10462 &buff[0]);
10463
10464 if (ret == 0)
10465 {
10466 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_LC_TIMEOUT_H,
10467 &buff[1]);
10468 }
10469
10470 return ret;
10471 }
10472
10473 /**
10474 * @brief FSM long counter timeout register (r/w). The long counter
10475 * timeout value is an unsigned integer value (16-bit format).
10476 * When the long counter value reached this value, the FSM generates
10477 * an interrupt.[get]
10478 *
10479 * @param ctx Read / write interface definitions.(ptr)
10480 * @param buff Buffer that stores data read
10481 * @retval Interface status (MANDATORY: return 0 -> no Error).
10482 *
10483 */
lsm6dsrx_long_cnt_int_value_get(const stmdev_ctx_t * ctx,uint16_t * val)10484 int32_t lsm6dsrx_long_cnt_int_value_get(const stmdev_ctx_t *ctx,
10485 uint16_t *val)
10486 {
10487 uint8_t buff[2];
10488 int32_t ret;
10489
10490 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_FSM_LC_TIMEOUT_L,
10491 &buff[0]);
10492
10493 if (ret == 0)
10494 {
10495 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_FSM_LC_TIMEOUT_H,
10496 &buff[1]);
10497 *val = buff[1];
10498 *val = (*val * 256U) + buff[0];
10499 }
10500
10501 return ret;
10502 }
10503
10504 /**
10505 * @brief FSM number of programs register.[set]
10506 *
10507 * @param ctx Read / write interface definitions.(ptr)
10508 * @param buff Buffer that contains data to write
10509 * @retval Interface status (MANDATORY: return 0 -> no Error).
10510 *
10511 */
lsm6dsrx_fsm_number_of_programs_set(const stmdev_ctx_t * ctx,uint8_t * buff)10512 int32_t lsm6dsrx_fsm_number_of_programs_set(const stmdev_ctx_t *ctx,
10513 uint8_t *buff)
10514 {
10515 int32_t ret;
10516
10517 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_PROGRAMS, buff);
10518
10519 if (ret == 0)
10520 {
10521 ret = lsm6dsrx_ln_pg_write_byte(ctx,
10522 LSM6DSRX_FSM_PROGRAMS + 0x01U,
10523 buff);
10524 }
10525
10526 return ret;
10527 }
10528
10529 /**
10530 * @brief FSM number of programs register.[get]
10531 *
10532 * @param ctx Read / write interface definitions.(ptr)
10533 * @param buff Buffer that stores data read
10534 * @retval Interface status (MANDATORY: return 0 -> no Error).
10535 *
10536 */
lsm6dsrx_fsm_number_of_programs_get(const stmdev_ctx_t * ctx,uint8_t * buff)10537 int32_t lsm6dsrx_fsm_number_of_programs_get(const stmdev_ctx_t *ctx,
10538 uint8_t *buff)
10539 {
10540 int32_t ret;
10541
10542 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_FSM_PROGRAMS, buff);
10543
10544 return ret;
10545 }
10546
10547 /**
10548 * @brief FSM start address register (r/w). First available address is
10549 * 0x033C.[set]
10550 *
10551 * @param ctx Read / write interface definitions.(ptr)
10552 * @param buff Buffer that contains data to write
10553 * @retval Interface status (MANDATORY: return 0 -> no Error).
10554 *
10555 */
lsm6dsrx_fsm_start_address_set(const stmdev_ctx_t * ctx,uint16_t val)10556 int32_t lsm6dsrx_fsm_start_address_set(const stmdev_ctx_t *ctx,
10557 uint16_t val)
10558 {
10559 uint8_t buff[2];
10560 int32_t ret;
10561
10562 buff[1] = (uint8_t)(val / 256U);
10563 buff[0] = (uint8_t)(val - (buff[1] * 256U));
10564 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_START_ADD_L,
10565 &buff[0]);
10566
10567 if (ret == 0)
10568 {
10569 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_START_ADD_H,
10570 &buff[1]);
10571 }
10572
10573 return ret;
10574 }
10575
10576 /**
10577 * @brief FSM start address register (r/w). First available address
10578 * is 0x033C.[get]
10579 *
10580 * @param ctx Read / write interface definitions.(ptr)
10581 * @param buff Buffer that stores data read
10582 * @retval Interface status (MANDATORY: return 0 -> no Error).
10583 *
10584 */
lsm6dsrx_fsm_start_address_get(const stmdev_ctx_t * ctx,uint16_t * val)10585 int32_t lsm6dsrx_fsm_start_address_get(const stmdev_ctx_t *ctx,
10586 uint16_t *val)
10587 {
10588 uint8_t buff[2];
10589 int32_t ret;
10590
10591 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_FSM_START_ADD_L,
10592 &buff[0]);
10593
10594 if (ret == 0)
10595 {
10596 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_FSM_START_ADD_H,
10597 &buff[1]);
10598 *val = buff[1];
10599 *val = (*val * 256U) + buff[0];
10600 }
10601
10602 return ret;
10603 }
10604
10605 /**
10606 * @}
10607 *
10608 */
10609
10610 /**
10611 * @addtogroup Machine Learning Core
10612 * @brief This section group all the functions concerning the
10613 * usage of Machine Learning Core
10614 * @{
10615 *
10616 */
10617
10618 /**
10619 * @brief Enable Machine Learning Core.[set]
10620 *
10621 * @param ctx read / write interface definitions
10622 * @param val change the values of mlc_en in
10623 * reg EMB_FUNC_EN_B and mlc_init
10624 * in EMB_FUNC_INIT_B
10625 *
10626 */
lsm6dsrx_mlc_set(const stmdev_ctx_t * ctx,uint8_t val)10627 int32_t lsm6dsrx_mlc_set(const stmdev_ctx_t *ctx, uint8_t val)
10628 {
10629 lsm6dsrx_emb_func_en_b_t reg;
10630 int32_t ret;
10631
10632 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10633
10634 if (ret == 0)
10635 {
10636 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
10637 (uint8_t *)®, 1);
10638 }
10639
10640 if (ret == 0)
10641 {
10642 reg.mlc_en = val;
10643 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
10644 (uint8_t *)®, 1);
10645 }
10646
10647 if ((val != PROPERTY_DISABLE) && (ret == 0))
10648 {
10649 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
10650 (uint8_t *)®, 1);
10651
10652 if (ret == 0)
10653 {
10654 reg.mlc_en = val;
10655 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
10656 (uint8_t *)®, 1);
10657 }
10658 }
10659
10660 if (ret == 0)
10661 {
10662 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10663 }
10664
10665 return ret;
10666 }
10667
10668 /**
10669 * @brief Enable Machine Learning Core.[get]
10670 *
10671 * @param ctx read / write interface definitions
10672 * @param val Get the values of mlc_en in
10673 * reg EMB_FUNC_EN_B
10674 *
10675 */
lsm6dsrx_mlc_get(const stmdev_ctx_t * ctx,uint8_t * val)10676 int32_t lsm6dsrx_mlc_get(const stmdev_ctx_t *ctx, uint8_t *val)
10677 {
10678 lsm6dsrx_emb_func_en_b_t reg;
10679 int32_t ret;
10680
10681 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10682
10683 if (ret == 0)
10684 {
10685 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
10686 (uint8_t *)®, 1);
10687 }
10688
10689 if (ret == 0)
10690 {
10691 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10692 *val = reg.mlc_en;
10693 }
10694
10695 return ret;
10696 }
10697
10698 /**
10699 * @brief Machine Learning Core status register[get]
10700 *
10701 * @param ctx read / write interface definitions
10702 * @param val register MLC_STATUS_MAINPAGE
10703 *
10704 */
lsm6dsrx_mlc_status_get(const stmdev_ctx_t * ctx,lsm6dsrx_mlc_status_mainpage_t * val)10705 int32_t lsm6dsrx_mlc_status_get(const stmdev_ctx_t *ctx,
10706 lsm6dsrx_mlc_status_mainpage_t *val)
10707 {
10708 return lsm6dsrx_read_reg(ctx, LSM6DSRX_MLC_STATUS_MAINPAGE,
10709 (uint8_t *) val, 1);
10710 }
10711
10712 /**
10713 * @brief Machine Learning Core data rate selection.[set]
10714 *
10715 * @param ctx read / write interface definitions
10716 * @param val get the values of mlc_odr in
10717 * reg EMB_FUNC_ODR_CFG_C
10718 *
10719 */
lsm6dsrx_mlc_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsrx_mlc_odr_t val)10720 int32_t lsm6dsrx_mlc_data_rate_set(const stmdev_ctx_t *ctx,
10721 lsm6dsrx_mlc_odr_t val)
10722 {
10723 lsm6dsrx_emb_func_odr_cfg_c_t reg;
10724 int32_t ret;
10725
10726 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10727
10728 if (ret == 0)
10729 {
10730 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_ODR_CFG_C,
10731 (uint8_t *)®, 1);
10732 }
10733
10734 if (ret == 0)
10735 {
10736 reg.mlc_odr = (uint8_t)val;
10737 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_ODR_CFG_C,
10738 (uint8_t *)®, 1);
10739 }
10740
10741 if (ret == 0)
10742 {
10743 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10744 }
10745
10746 return ret;
10747 }
10748
10749 /**
10750 * @brief Machine Learning Core data rate selection.[get]
10751 *
10752 * @param ctx read / write interface definitions
10753 * @param val change the values of mlc_odr in
10754 * reg EMB_FUNC_ODR_CFG_C
10755 *
10756 */
lsm6dsrx_mlc_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsrx_mlc_odr_t * val)10757 int32_t lsm6dsrx_mlc_data_rate_get(const stmdev_ctx_t *ctx,
10758 lsm6dsrx_mlc_odr_t *val)
10759 {
10760 lsm6dsrx_emb_func_odr_cfg_c_t reg;
10761 int32_t ret;
10762
10763 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10764
10765 if (ret == 0)
10766 {
10767 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_ODR_CFG_C,
10768 (uint8_t *)®, 1);
10769 }
10770
10771 if (ret == 0)
10772 {
10773 switch (reg.mlc_odr)
10774 {
10775 case LSM6DSRX_ODR_PRGS_12Hz5:
10776 *val = LSM6DSRX_ODR_PRGS_12Hz5;
10777 break;
10778
10779 case LSM6DSRX_ODR_PRGS_26Hz:
10780 *val = LSM6DSRX_ODR_PRGS_26Hz;
10781 break;
10782
10783 case LSM6DSRX_ODR_PRGS_52Hz:
10784 *val = LSM6DSRX_ODR_PRGS_52Hz;
10785 break;
10786
10787 case LSM6DSRX_ODR_PRGS_104Hz:
10788 *val = LSM6DSRX_ODR_PRGS_104Hz;
10789 break;
10790
10791 default:
10792 *val = LSM6DSRX_ODR_PRGS_12Hz5;
10793 break;
10794 }
10795
10796 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10797 }
10798
10799 return ret;
10800 }
10801
10802 /**
10803 * @brief prgsens_out: [get] Output value of all MLCx decision trees.
10804 *
10805 * @param ctx_t *ctx: read / write interface definitions
10806 * @param uint8_t * : buffer that stores data read
10807 *
10808 */
lsm6dsrx_mlc_out_get(const stmdev_ctx_t * ctx,uint8_t * buff)10809 int32_t lsm6dsrx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff)
10810 {
10811 int32_t ret;
10812
10813 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10814
10815 if (ret == 0)
10816 {
10817 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MLC0_SRC, buff, 8);
10818 }
10819
10820 if (ret == 0)
10821 {
10822 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10823 }
10824
10825 return ret;
10826 }
10827
10828 /**
10829 * @brief External magnetometer sensitivity value register for
10830 * Machine Learning Core.[set]
10831 *
10832 * @param ctx read / write interface definitions
10833 * @param buff buffer that contains data to write
10834 *
10835 */
lsm6dsrx_mlc_mag_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)10836 int32_t lsm6dsrx_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx,
10837 uint16_t val)
10838 {
10839 uint8_t buff[2];
10840 int32_t ret;
10841
10842 buff[1] = (uint8_t)(val / 256U);
10843 buff[0] = (uint8_t)(val - (buff[1] * 256U));
10844 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MLC_MAG_SENSITIVITY_L,
10845 &buff[0]);
10846
10847 if (ret == 0)
10848 {
10849 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MLC_MAG_SENSITIVITY_H,
10850 &buff[1]);
10851 }
10852
10853 return ret;
10854 }
10855
10856 /**
10857 * @brief External magnetometer sensitivity value register for
10858 * Machine Learning Core.[get]
10859 *
10860 * @param ctx read / write interface definitions
10861 * @param buff buffer that stores data read
10862 *
10863 */
lsm6dsrx_mlc_mag_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)10864 int32_t lsm6dsrx_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx,
10865 uint16_t *val)
10866 {
10867 uint8_t buff[2];
10868 int32_t ret;
10869
10870 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MLC_MAG_SENSITIVITY_L,
10871 &buff[0]);
10872
10873 if (ret == 0)
10874 {
10875 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MLC_MAG_SENSITIVITY_H,
10876 &buff[1]);
10877 *val = buff[1];
10878 *val = (*val * 256U) + buff[0];
10879 }
10880
10881 return ret;
10882 }
10883
10884 /**
10885 * @}
10886 *
10887 */
10888
10889 /**
10890 * @defgroup LSM6DSRX_Sensor_hub
10891 * @brief This section groups all the functions that manage the
10892 * sensor hub.
10893 * @{
10894 *
10895 */
10896
10897 /**
10898 * @brief Sensor hub output registers.[get]
10899 *
10900 * @param ctx Read / write interface definitions.(ptr)
10901 * @param val Structure of registers from SENSOR_HUB_1 to SENSOR_HUB_18
10902 * @retval Interface status (MANDATORY: return 0 -> no Error).
10903 *
10904 */
lsm6dsrx_sh_read_data_raw_get(const stmdev_ctx_t * ctx,lsm6dsrx_emb_sh_read_t * val,uint8_t len)10905 int32_t lsm6dsrx_sh_read_data_raw_get(const stmdev_ctx_t *ctx,
10906 lsm6dsrx_emb_sh_read_t *val,
10907 uint8_t len)
10908 {
10909 int32_t ret;
10910
10911 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
10912
10913 if (ret == 0)
10914 {
10915 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SENSOR_HUB_1,
10916 (uint8_t *)val, len);
10917 }
10918
10919 if (ret == 0)
10920 {
10921 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10922 }
10923
10924 return ret;
10925 }
10926
10927 /**
10928 * @brief Number of external sensors to be read by the sensor hub.[set]
10929 *
10930 * @param ctx Read / write interface definitions.(ptr)
10931 * @param val Change the values of aux_sens_on in reg MASTER_CONFIG
10932 * @retval Interface status (MANDATORY: return 0 -> no Error).
10933 *
10934 */
lsm6dsrx_sh_slave_connected_set(const stmdev_ctx_t * ctx,lsm6dsrx_aux_sens_on_t val)10935 int32_t lsm6dsrx_sh_slave_connected_set(const stmdev_ctx_t *ctx,
10936 lsm6dsrx_aux_sens_on_t val)
10937 {
10938 lsm6dsrx_master_config_t master_config;
10939 int32_t ret;
10940
10941 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
10942
10943 if (ret == 0)
10944 {
10945 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
10946 (uint8_t *)&master_config, 1);
10947 }
10948
10949 if (ret == 0)
10950 {
10951 master_config.aux_sens_on = (uint8_t)val;
10952 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
10953 (uint8_t *)&master_config, 1);
10954 }
10955
10956 if (ret == 0)
10957 {
10958 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10959 }
10960
10961 return ret;
10962 }
10963
10964 /**
10965 * @brief Number of external sensors to be read by the sensor hub.[get]
10966 *
10967 * @param ctx Read / write interface definitions.(ptr)
10968 * @param val Get the values of aux_sens_on in reg MASTER_CONFIG
10969 * @retval Interface status (MANDATORY: return 0 -> no Error).
10970 *
10971 */
lsm6dsrx_sh_slave_connected_get(const stmdev_ctx_t * ctx,lsm6dsrx_aux_sens_on_t * val)10972 int32_t lsm6dsrx_sh_slave_connected_get(const stmdev_ctx_t *ctx,
10973 lsm6dsrx_aux_sens_on_t *val)
10974 {
10975 lsm6dsrx_master_config_t master_config;
10976 int32_t ret;
10977
10978 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
10979
10980 if (ret == 0)
10981 {
10982 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
10983 (uint8_t *)&master_config, 1);
10984 }
10985
10986 if (ret == 0)
10987 {
10988 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10989 }
10990
10991 switch (master_config.aux_sens_on)
10992 {
10993 case LSM6DSRX_SLV_0:
10994 *val = LSM6DSRX_SLV_0;
10995 break;
10996
10997 case LSM6DSRX_SLV_0_1:
10998 *val = LSM6DSRX_SLV_0_1;
10999 break;
11000
11001 case LSM6DSRX_SLV_0_1_2:
11002 *val = LSM6DSRX_SLV_0_1_2;
11003 break;
11004
11005 case LSM6DSRX_SLV_0_1_2_3:
11006 *val = LSM6DSRX_SLV_0_1_2_3;
11007 break;
11008
11009 default:
11010 *val = LSM6DSRX_SLV_0;
11011 break;
11012 }
11013
11014 return ret;
11015 }
11016
11017 /**
11018 * @brief Sensor hub I2C master enable.[set]
11019 *
11020 * @param ctx Read / write interface definitions.(ptr)
11021 * @param val Change the values of master_on in reg MASTER_CONFIG
11022 * @retval Interface status (MANDATORY: return 0 -> no Error).
11023 *
11024 */
lsm6dsrx_sh_master_set(const stmdev_ctx_t * ctx,uint8_t val)11025 int32_t lsm6dsrx_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val)
11026 {
11027 lsm6dsrx_master_config_t master_config;
11028 int32_t ret;
11029
11030 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11031
11032 if (ret == 0)
11033 {
11034 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11035 (uint8_t *)&master_config, 1);
11036 }
11037
11038 if (ret == 0)
11039 {
11040 master_config.master_on = (uint8_t)val;
11041 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11042 (uint8_t *)&master_config, 1);
11043 }
11044
11045 if (ret == 0)
11046 {
11047 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11048 }
11049
11050 return ret;
11051 }
11052
11053 /**
11054 * @brief Sensor hub I2C master enable.[get]
11055 *
11056 * @param ctx Read / write interface definitions.(ptr)
11057 * @param val Change the values of master_on in reg MASTER_CONFIG
11058 * @retval Interface status (MANDATORY: return 0 -> no Error).
11059 *
11060 */
lsm6dsrx_sh_master_get(const stmdev_ctx_t * ctx,uint8_t * val)11061 int32_t lsm6dsrx_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val)
11062 {
11063 lsm6dsrx_master_config_t master_config;
11064 int32_t ret;
11065
11066 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11067
11068 if (ret == 0)
11069 {
11070 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11071 (uint8_t *)&master_config, 1);
11072 }
11073
11074 if (ret == 0)
11075 {
11076 *val = master_config.master_on;
11077 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11078 }
11079
11080 return ret;
11081 }
11082
11083 /**
11084 * @brief Master I2C pull-up enable.[set]
11085 *
11086 * @param ctx Read / write interface definitions.(ptr)
11087 * @param val Change the values of shub_pu_en in reg MASTER_CONFIG
11088 * @retval Interface status (MANDATORY: return 0 -> no Error).
11089 *
11090 */
lsm6dsrx_sh_pin_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_shub_pu_en_t val)11091 int32_t lsm6dsrx_sh_pin_mode_set(const stmdev_ctx_t *ctx,
11092 lsm6dsrx_shub_pu_en_t val)
11093 {
11094 lsm6dsrx_master_config_t master_config;
11095 int32_t ret;
11096
11097 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11098
11099 if (ret == 0)
11100 {
11101 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11102 (uint8_t *)&master_config, 1);
11103 }
11104
11105 if (ret == 0)
11106 {
11107 master_config.shub_pu_en = (uint8_t)val;
11108 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11109 (uint8_t *)&master_config, 1);
11110 }
11111
11112 if (ret == 0)
11113 {
11114 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11115 }
11116
11117 return ret;
11118 }
11119
11120 /**
11121 * @brief Master I2C pull-up enable.[get]
11122 *
11123 * @param ctx Read / write interface definitions.(ptr)
11124 * @param val Get the values of shub_pu_en in reg MASTER_CONFIG
11125 * @retval Interface status (MANDATORY: return 0 -> no Error).
11126 *
11127 */
lsm6dsrx_sh_pin_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_shub_pu_en_t * val)11128 int32_t lsm6dsrx_sh_pin_mode_get(const stmdev_ctx_t *ctx,
11129 lsm6dsrx_shub_pu_en_t *val)
11130 {
11131 lsm6dsrx_master_config_t master_config;
11132 int32_t ret;
11133
11134 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11135
11136 if (ret == 0)
11137 {
11138 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11139 (uint8_t *)&master_config, 1);
11140 }
11141
11142 if (ret == 0)
11143 {
11144 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11145 }
11146
11147 switch (master_config.shub_pu_en)
11148 {
11149 case LSM6DSRX_EXT_PULL_UP:
11150 *val = LSM6DSRX_EXT_PULL_UP;
11151 break;
11152
11153 case LSM6DSRX_INTERNAL_PULL_UP:
11154 *val = LSM6DSRX_INTERNAL_PULL_UP;
11155 break;
11156
11157 default:
11158 *val = LSM6DSRX_EXT_PULL_UP;
11159 break;
11160 }
11161
11162 return ret;
11163 }
11164
11165 /**
11166 * @brief I2C interface pass-through.[set]
11167 *
11168 * @param ctx Read / write interface definitions.(ptr)
11169 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
11170 * @retval Interface status (MANDATORY: return 0 -> no Error).
11171 *
11172 */
lsm6dsrx_sh_pass_through_set(const stmdev_ctx_t * ctx,uint8_t val)11173 int32_t lsm6dsrx_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val)
11174 {
11175 lsm6dsrx_master_config_t master_config;
11176 int32_t ret;
11177
11178 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11179
11180 if (ret == 0)
11181 {
11182 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11183 (uint8_t *)&master_config, 1);
11184 }
11185
11186 if (ret == 0)
11187 {
11188 master_config.pass_through_mode = (uint8_t)val;
11189 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11190 (uint8_t *)&master_config, 1);
11191 }
11192
11193 if (ret == 0)
11194 {
11195 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11196 }
11197
11198 return ret;
11199 }
11200
11201 /**
11202 * @brief I2C interface pass-through.[get]
11203 *
11204 * @param ctx Read / write interface definitions.(ptr)
11205 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
11206 * @retval Interface status (MANDATORY: return 0 -> no Error).
11207 *
11208 */
lsm6dsrx_sh_pass_through_get(const stmdev_ctx_t * ctx,uint8_t * val)11209 int32_t lsm6dsrx_sh_pass_through_get(const stmdev_ctx_t *ctx,
11210 uint8_t *val)
11211 {
11212 lsm6dsrx_master_config_t master_config;
11213 int32_t ret;
11214
11215 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11216
11217 if (ret == 0)
11218 {
11219 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11220 (uint8_t *)&master_config, 1);
11221 }
11222
11223 if (ret == 0)
11224 {
11225 *val = master_config.pass_through_mode;
11226 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11227 }
11228
11229 return ret;
11230 }
11231
11232 /**
11233 * @brief Sensor hub trigger signal selection.[set]
11234 *
11235 * @param ctx Read / write interface definitions.(ptr)
11236 * @param val Change the values of start_config in reg MASTER_CONFIG
11237 * @retval Interface status (MANDATORY: return 0 -> no Error).
11238 *
11239 */
lsm6dsrx_sh_syncro_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_start_config_t val)11240 int32_t lsm6dsrx_sh_syncro_mode_set(const stmdev_ctx_t *ctx,
11241 lsm6dsrx_start_config_t val)
11242 {
11243 lsm6dsrx_master_config_t master_config;
11244 int32_t ret;
11245
11246 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11247
11248 if (ret == 0)
11249 {
11250 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11251 (uint8_t *)&master_config, 1);
11252 }
11253
11254 if (ret == 0)
11255 {
11256 master_config.start_config = (uint8_t)val;
11257 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11258 (uint8_t *)&master_config, 1);
11259 }
11260
11261 if (ret == 0)
11262 {
11263 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11264 }
11265
11266 return ret;
11267 }
11268
11269 /**
11270 * @brief Sensor hub trigger signal selection.[get]
11271 *
11272 * @param ctx Read / write interface definitions.(ptr)
11273 * @param val Get the values of start_config in reg MASTER_CONFIG
11274 * @retval Interface status (MANDATORY: return 0 -> no Error).
11275 *
11276 */
lsm6dsrx_sh_syncro_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_start_config_t * val)11277 int32_t lsm6dsrx_sh_syncro_mode_get(const stmdev_ctx_t *ctx,
11278 lsm6dsrx_start_config_t *val)
11279 {
11280 lsm6dsrx_master_config_t master_config;
11281 int32_t ret;
11282
11283 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11284
11285 if (ret == 0)
11286 {
11287 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11288 (uint8_t *)&master_config, 1);
11289 }
11290
11291 if (ret == 0)
11292 {
11293 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11294 }
11295
11296 switch (master_config.start_config)
11297 {
11298 case LSM6DSRX_EXT_ON_INT2_PIN:
11299 *val = LSM6DSRX_EXT_ON_INT2_PIN;
11300 break;
11301
11302 case LSM6DSRX_XL_GY_DRDY:
11303 *val = LSM6DSRX_XL_GY_DRDY;
11304 break;
11305
11306 default:
11307 *val = LSM6DSRX_EXT_ON_INT2_PIN;
11308 break;
11309 }
11310
11311 return ret;
11312 }
11313
11314 /**
11315 * @brief Slave 0 write operation is performed only at the first sensor
11316 * hub cycle.[set]
11317 *
11318 * @param ctx Read / write interface definitions.(ptr)
11319 * @param val Change the values of write_once in reg MASTER_CONFIG
11320 * @retval Interface status (MANDATORY: return 0 -> no Error).
11321 *
11322 */
lsm6dsrx_sh_write_mode_set(const stmdev_ctx_t * ctx,lsm6dsrx_write_once_t val)11323 int32_t lsm6dsrx_sh_write_mode_set(const stmdev_ctx_t *ctx,
11324 lsm6dsrx_write_once_t val)
11325 {
11326 lsm6dsrx_master_config_t master_config;
11327 int32_t ret;
11328
11329 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11330
11331 if (ret == 0)
11332 {
11333 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11334 (uint8_t *)&master_config, 1);
11335 }
11336
11337 if (ret == 0)
11338 {
11339 master_config.write_once = (uint8_t)val;
11340 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11341 (uint8_t *)&master_config, 1);
11342 }
11343
11344 if (ret == 0)
11345 {
11346 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11347 }
11348
11349 return ret;
11350 }
11351
11352 /**
11353 * @brief Slave 0 write operation is performed only at the first sensor
11354 * hub cycle.[get]
11355 *
11356 * @param ctx Read / write interface definitions.(ptr)
11357 * @param val Get the values of write_once in reg MASTER_CONFIG
11358 * @retval Interface status (MANDATORY: return 0 -> no Error).
11359 *
11360 */
lsm6dsrx_sh_write_mode_get(const stmdev_ctx_t * ctx,lsm6dsrx_write_once_t * val)11361 int32_t lsm6dsrx_sh_write_mode_get(const stmdev_ctx_t *ctx,
11362 lsm6dsrx_write_once_t *val)
11363 {
11364 lsm6dsrx_master_config_t master_config;
11365 int32_t ret;
11366
11367 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11368
11369 if (ret == 0)
11370 {
11371 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11372 (uint8_t *)&master_config, 1);
11373 }
11374
11375 if (ret == 0)
11376 {
11377 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11378 }
11379
11380 switch (master_config.write_once)
11381 {
11382 case LSM6DSRX_EACH_SH_CYCLE:
11383 *val = LSM6DSRX_EACH_SH_CYCLE;
11384 break;
11385
11386 case LSM6DSRX_ONLY_FIRST_CYCLE:
11387 *val = LSM6DSRX_ONLY_FIRST_CYCLE;
11388 break;
11389
11390 default:
11391 *val = LSM6DSRX_EACH_SH_CYCLE;
11392 break;
11393 }
11394
11395 return ret;
11396 }
11397
11398 /**
11399 * @brief Reset Master logic and output registers.[set]
11400 *
11401 * @param ctx Read / write interface definitions.(ptr)
11402 * @retval Interface status (MANDATORY: return 0 -> no Error).
11403 *
11404 */
lsm6dsrx_sh_reset_set(const stmdev_ctx_t * ctx)11405 int32_t lsm6dsrx_sh_reset_set(const stmdev_ctx_t *ctx)
11406 {
11407 lsm6dsrx_master_config_t master_config;
11408 int32_t ret;
11409
11410 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11411
11412 if (ret == 0)
11413 {
11414 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11415 (uint8_t *)&master_config, 1);
11416 }
11417
11418 if (ret == 0)
11419 {
11420 master_config.rst_master_regs = PROPERTY_ENABLE;
11421 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11422 (uint8_t *)&master_config, 1);
11423 }
11424
11425 if (ret == 0)
11426 {
11427 master_config.rst_master_regs = PROPERTY_DISABLE;
11428 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11429 (uint8_t *)&master_config, 1);
11430 }
11431
11432 if (ret == 0)
11433 {
11434 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11435 }
11436
11437 return ret;
11438 }
11439
11440 /**
11441 * @brief Reset Master logic and output registers.[get]
11442 *
11443 * @param ctx Read / write interface definitions.(ptr)
11444 * @param val Change the values of rst_master_regs in reg MASTER_CONFIG
11445 * @retval Interface status (MANDATORY: return 0 -> no Error).
11446 *
11447 */
lsm6dsrx_sh_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)11448 int32_t lsm6dsrx_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
11449 {
11450 lsm6dsrx_master_config_t master_config;
11451 int32_t ret;
11452
11453 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11454
11455 if (ret == 0)
11456 {
11457 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11458 (uint8_t *)&master_config, 1);
11459 *val = master_config.rst_master_regs;
11460 }
11461
11462 if (ret == 0)
11463 {
11464 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11465 }
11466
11467 return ret;
11468 }
11469
11470 /**
11471 * @brief Rate at which the master communicates.[set]
11472 *
11473 * @param ctx Read / write interface definitions.(ptr)
11474 * @param val Change the values of shub_odr in reg SLV0_CONFIG
11475 * @retval Interface status (MANDATORY: return 0 -> no Error).
11476 *
11477 */
lsm6dsrx_sh_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsrx_shub_odr_t val)11478 int32_t lsm6dsrx_sh_data_rate_set(const stmdev_ctx_t *ctx,
11479 lsm6dsrx_shub_odr_t val)
11480 {
11481 lsm6dsrx_slv0_config_t slv0_config;
11482 int32_t ret;
11483
11484 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11485
11486 if (ret == 0)
11487 {
11488 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV0_CONFIG,
11489 (uint8_t *)&slv0_config, 1);
11490 }
11491
11492 if (ret == 0)
11493 {
11494 slv0_config.shub_odr = (uint8_t)val;
11495 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_CONFIG,
11496 (uint8_t *)&slv0_config, 1);
11497 }
11498
11499 if (ret == 0)
11500 {
11501 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11502 }
11503
11504 return ret;
11505 }
11506
11507 /**
11508 * @brief Rate at which the master communicates.[get]
11509 *
11510 * @param ctx Read / write interface definitions.(ptr)
11511 * @param val Get the values of shub_odr in reg slv1_CONFIG
11512 * @retval Interface status (MANDATORY: return 0 -> no Error).
11513 *
11514 */
lsm6dsrx_sh_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsrx_shub_odr_t * val)11515 int32_t lsm6dsrx_sh_data_rate_get(const stmdev_ctx_t *ctx,
11516 lsm6dsrx_shub_odr_t *val)
11517 {
11518 lsm6dsrx_slv0_config_t slv0_config;
11519 int32_t ret;
11520
11521 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11522
11523 if (ret == 0)
11524 {
11525 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV0_CONFIG,
11526 (uint8_t *)&slv0_config, 1);
11527 }
11528
11529 if (ret == 0)
11530 {
11531 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11532 }
11533
11534 switch (slv0_config.shub_odr)
11535 {
11536 case LSM6DSRX_SH_ODR_104Hz:
11537 *val = LSM6DSRX_SH_ODR_104Hz;
11538 break;
11539
11540 case LSM6DSRX_SH_ODR_52Hz:
11541 *val = LSM6DSRX_SH_ODR_52Hz;
11542 break;
11543
11544 case LSM6DSRX_SH_ODR_26Hz:
11545 *val = LSM6DSRX_SH_ODR_26Hz;
11546 break;
11547
11548 case LSM6DSRX_SH_ODR_13Hz:
11549 *val = LSM6DSRX_SH_ODR_13Hz;
11550 break;
11551
11552 default:
11553 *val = LSM6DSRX_SH_ODR_104Hz;
11554 break;
11555 }
11556
11557 return ret;
11558 }
11559
11560 /**
11561 * @brief Configure slave 0 for perform a write.[set]
11562 *
11563 * @param ctx Read / write interface definitions.(ptr)
11564 * @param val Structure that contain
11565 * - uint8_t slv0_add; 8 bit i2c device address
11566 * - uint8_t slv0_subadd; 8 bit register device address
11567 * - uint8_t slv0_data; 8 bit data to write
11568 * @retval Interface status (MANDATORY: return 0 -> no Error).
11569 *
11570 */
lsm6dsrx_sh_cfg_write(const stmdev_ctx_t * ctx,lsm6dsrx_sh_cfg_write_t * val)11571 int32_t lsm6dsrx_sh_cfg_write(const stmdev_ctx_t *ctx,
11572 lsm6dsrx_sh_cfg_write_t *val)
11573 {
11574 lsm6dsrx_slv0_add_t slv0_add;
11575 int32_t ret;
11576
11577 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11578
11579 if (ret == 0)
11580 {
11581 slv0_add.slave0 = (uint8_t)(val->slv0_add >> 1);
11582 slv0_add.rw_0 = 0;
11583 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_ADD,
11584 (uint8_t *) & (slv0_add), 1);
11585 }
11586
11587 if (ret == 0)
11588 {
11589 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_SUBADD,
11590 (uint8_t *) & (val->slv0_subadd), 1);
11591 }
11592
11593 if (ret == 0)
11594 {
11595 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_DATAWRITE_SLV0,
11596 (uint8_t *) & (val->slv0_data), 1);
11597 }
11598
11599 if (ret == 0)
11600 {
11601 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11602 }
11603
11604 return ret;
11605 }
11606
11607 /**
11608 * @brief Configure slave 0 for perform a write/read.[get]
11609 *
11610 * @param ctx Read / write interface definitions.(ptr)
11611 * @param val Structure that contain
11612 * - uint8_t slv_add; 8 bit i2c device address
11613 * - uint8_t slv_subadd; 8 bit register device address
11614 * - uint8_t slv_len; num of bit to read
11615 * @retval Interface status (MANDATORY: return 0 -> no Error).
11616 *
11617 */
lsm6dsrx_sh_slv0_cfg_read(const stmdev_ctx_t * ctx,lsm6dsrx_sh_cfg_read_t * val)11618 int32_t lsm6dsrx_sh_slv0_cfg_read(const stmdev_ctx_t *ctx,
11619 lsm6dsrx_sh_cfg_read_t *val)
11620 {
11621 lsm6dsrx_slv0_config_t slv0_config;
11622 lsm6dsrx_slv0_add_t slv0_add;
11623 int32_t ret;
11624
11625 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11626
11627 if (ret == 0)
11628 {
11629 slv0_add.slave0 = (uint8_t) val->slv_add >> 1;
11630 slv0_add.rw_0 = 1;
11631 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_ADD,
11632 (uint8_t *) & (slv0_add), 1);
11633 }
11634
11635 if (ret == 0)
11636 {
11637 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_SUBADD,
11638 &(val->slv_subadd), 1);
11639 }
11640
11641 if (ret == 0)
11642 {
11643 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV0_CONFIG,
11644 (uint8_t *)&slv0_config, 1);
11645 }
11646
11647 if (ret == 0)
11648 {
11649 slv0_config.slave0_numop = val->slv_len;
11650 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_CONFIG,
11651 (uint8_t *)&slv0_config, 1);
11652 }
11653
11654 if (ret == 0)
11655 {
11656 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11657 }
11658
11659 return ret;
11660 }
11661
11662 /**
11663 * @brief Configure slave 0 for perform a write/read.[get]
11664 *
11665 * @param ctx Read / write interface definitions.(ptr)
11666 * @param val Structure that contain
11667 * - uint8_t slv_add; 8 bit i2c device address
11668 * - uint8_t slv_subadd; 8 bit register device address
11669 * - uint8_t slv_len; num of bit to read
11670 * @retval Interface status (MANDATORY: return 0 -> no Error).
11671 *
11672 */
lsm6dsrx_sh_slv1_cfg_read(const stmdev_ctx_t * ctx,lsm6dsrx_sh_cfg_read_t * val)11673 int32_t lsm6dsrx_sh_slv1_cfg_read(const stmdev_ctx_t *ctx,
11674 lsm6dsrx_sh_cfg_read_t *val)
11675 {
11676 lsm6dsrx_slv1_config_t slv1_config;
11677 lsm6dsrx_slv1_add_t slv1_add;
11678 int32_t ret;
11679
11680 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11681
11682 if (ret == 0)
11683 {
11684 slv1_add.slave1_add = (uint8_t)(val->slv_add >> 1);
11685 slv1_add.r_1 = 1;
11686 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV1_ADD,
11687 (uint8_t *)&slv1_add, 1);
11688 }
11689
11690 if (ret == 0)
11691 {
11692 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV1_SUBADD,
11693 &(val->slv_subadd), 1);
11694 }
11695
11696 if (ret == 0)
11697 {
11698 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV1_CONFIG,
11699 (uint8_t *)&slv1_config, 1);
11700 }
11701
11702 if (ret == 0)
11703 {
11704 slv1_config.slave1_numop = val->slv_len;
11705 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV1_CONFIG,
11706 (uint8_t *)&slv1_config, 1);
11707 }
11708
11709 if (ret == 0)
11710 {
11711 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11712 }
11713
11714 return ret;
11715 }
11716
11717 /**
11718 * @brief Configure slave 2 for perform a write/read.[get]
11719 *
11720 * @param ctx Read / write interface definitions.(ptr)
11721 * @param val Structure that contain
11722 * - uint8_t slv_add; 8 bit i2c device address
11723 * - uint8_t slv_subadd; 8 bit register device address
11724 * - uint8_t slv_len; num of bit to read
11725 * @retval Interface status (MANDATORY: return 0 -> no Error).
11726 *
11727 */
lsm6dsrx_sh_slv2_cfg_read(const stmdev_ctx_t * ctx,lsm6dsrx_sh_cfg_read_t * val)11728 int32_t lsm6dsrx_sh_slv2_cfg_read(const stmdev_ctx_t *ctx,
11729 lsm6dsrx_sh_cfg_read_t *val)
11730 {
11731 lsm6dsrx_slv2_config_t slv2_config;
11732 lsm6dsrx_slv2_add_t slv2_add;
11733 int32_t ret;
11734
11735 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11736
11737 if (ret == 0)
11738 {
11739 slv2_add.slave2_add = (uint8_t)(val->slv_add >> 1);
11740 slv2_add.r_2 = 1;
11741 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV2_ADD,
11742 (uint8_t *)&slv2_add, 1);
11743 }
11744
11745 if (ret == 0)
11746 {
11747 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV2_SUBADD,
11748 (uint8_t *) & (val->slv_subadd), 1);
11749 }
11750
11751 if (ret == 0)
11752 {
11753 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV2_CONFIG,
11754 (uint8_t *)&slv2_config, 1);
11755 }
11756
11757 if (ret == 0)
11758 {
11759 slv2_config.slave2_numop = val->slv_len;
11760 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV2_CONFIG,
11761 (uint8_t *)&slv2_config, 1);
11762 }
11763
11764 if (ret == 0)
11765 {
11766 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11767 }
11768
11769 return ret;
11770 }
11771
11772 /**
11773 * @brief Configure slave 3 for perform a write/read.[get]
11774 *
11775 * @param ctx Read / write interface definitions.(ptr)
11776 * @param val Structure that contain
11777 * - uint8_t slv_add; 8 bit i2c device address
11778 * - uint8_t slv_subadd; 8 bit register device address
11779 * - uint8_t slv_len; num of bit to read
11780 * @retval Interface status (MANDATORY: return 0 -> no Error).
11781 *
11782 */
lsm6dsrx_sh_slv3_cfg_read(const stmdev_ctx_t * ctx,lsm6dsrx_sh_cfg_read_t * val)11783 int32_t lsm6dsrx_sh_slv3_cfg_read(const stmdev_ctx_t *ctx,
11784 lsm6dsrx_sh_cfg_read_t *val)
11785 {
11786 lsm6dsrx_slv3_config_t slv3_config;
11787 lsm6dsrx_slv3_add_t slv3_add;
11788 int32_t ret;
11789
11790 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11791
11792 if (ret == 0)
11793 {
11794 slv3_add.slave3_add = (uint8_t)(val->slv_add >> 1);
11795 slv3_add.r_3 = 1;
11796 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV3_ADD,
11797 (uint8_t *)&slv3_add, 1);
11798 }
11799
11800 if (ret == 0)
11801 {
11802 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV3_SUBADD,
11803 &(val->slv_subadd), 1);
11804 }
11805
11806 if (ret == 0)
11807 {
11808 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV3_CONFIG,
11809 (uint8_t *)&slv3_config, 1);
11810 }
11811
11812 if (ret == 0)
11813 {
11814 slv3_config.slave3_numop = val->slv_len;
11815 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV3_CONFIG,
11816 (uint8_t *)&slv3_config, 1);
11817 }
11818
11819 if (ret == 0)
11820 {
11821 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11822 }
11823
11824 return ret;
11825 }
11826
11827 /**
11828 * @brief Sensor hub source register.[get]
11829 *
11830 * @param ctx Read / write interface definitions.(ptr)
11831 * @param val Registers from STATUS_MASTER
11832 * @retval Interface status (MANDATORY: return 0 -> no Error).
11833 *
11834 */
lsm6dsrx_sh_status_get(const stmdev_ctx_t * ctx,lsm6dsrx_status_master_t * val)11835 int32_t lsm6dsrx_sh_status_get(const stmdev_ctx_t *ctx,
11836 lsm6dsrx_status_master_t *val)
11837 {
11838 int32_t ret;
11839
11840 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11841
11842 if (ret == 0)
11843 {
11844 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_MASTER,
11845 (uint8_t *)val, 1);
11846 }
11847
11848 if (ret == 0)
11849 {
11850 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11851 }
11852
11853 return ret;
11854 }
11855
11856 /**
11857 * @}
11858 *
11859 */
11860
11861 /**
11862 * @defgroup LSM6DSRX_Sensors for Smart Mobile Devices
11863 * @brief This section groups all the functions that manage the
11864 * Sensors for Smart Mobile Devices.
11865 * @{
11866 *
11867 */
11868
11869 /**
11870 * @brief Sensor synchronization time frame resolution[set]
11871 *
11872 * @param ctx Read / write interface definitions.(ptr)
11873 * @param val Change the values of tph_h_sel in LSM6DSRX_S4S_TPH_L
11874 * @retval Interface status (MANDATORY: return 0 -> no Error).
11875 *
11876 */
lsm6dsrx_s4s_tph_res_set(const stmdev_ctx_t * ctx,lsm6dsrx_s4s_tph_res_t val)11877 int32_t lsm6dsrx_s4s_tph_res_set(const stmdev_ctx_t *ctx,
11878 lsm6dsrx_s4s_tph_res_t val)
11879 {
11880 lsm6dsrx_s4s_tph_l_t s4s_tph_l;
11881 int32_t ret;
11882
11883 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1);
11884
11885 if (ret == 0)
11886 {
11887 s4s_tph_l.tph_h_sel = (uint8_t)val;
11888 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_S4S_TPH_L,
11889 (uint8_t *)&s4s_tph_l, 1);
11890 }
11891
11892 return ret;
11893 }
11894
11895 /**
11896 * @brief Sensor synchronization time frame resolution.[get]
11897 *
11898 * @param ctx Read / write interface definitions.(ptr)
11899 * @param val Get the values of tph_h_sel in LSM6DSRX_S4S_TPH_L
11900 * @retval Interface status (MANDATORY: return 0 -> no Error).
11901 *
11902 */
lsm6dsrx_s4s_tph_res_get(const stmdev_ctx_t * ctx,lsm6dsrx_s4s_tph_res_t * val)11903 int32_t lsm6dsrx_s4s_tph_res_get(const stmdev_ctx_t *ctx,
11904 lsm6dsrx_s4s_tph_res_t *val)
11905 {
11906 lsm6dsrx_s4s_tph_l_t s4s_tph_l;
11907 int32_t ret;
11908
11909 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1);
11910
11911 switch (s4s_tph_l.tph_h_sel)
11912 {
11913 case LSM6DSRX_S4S_TPH_7bit:
11914 *val = LSM6DSRX_S4S_TPH_7bit;
11915 break;
11916
11917 case LSM6DSRX_S4S_TPH_15bit:
11918 *val = LSM6DSRX_S4S_TPH_15bit;
11919 break;
11920
11921 default:
11922 *val = LSM6DSRX_S4S_TPH_7bit;
11923 break;
11924 }
11925
11926 return ret;
11927 }
11928
11929 /**
11930 * @brief Sensor synchronization time frame.[set]
11931 *
11932 * @param ctx Read / write interface definitions.(ptr)
11933 * @param val Change the values of tph_l in S4S_TPH_L and
11934 * tph_h in S4S_TPH_H
11935 * @retval Interface status (MANDATORY: return 0 -> no Error).
11936 *
11937 */
lsm6dsrx_s4s_tph_val_set(const stmdev_ctx_t * ctx,uint16_t val)11938 int32_t lsm6dsrx_s4s_tph_val_set(const stmdev_ctx_t *ctx, uint16_t val)
11939 {
11940 lsm6dsrx_s4s_tph_l_t s4s_tph_l;
11941 lsm6dsrx_s4s_tph_h_t s4s_tph_h;
11942 int32_t ret;
11943
11944 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1);
11945
11946 if (ret == 0)
11947 {
11948 s4s_tph_l.tph_l = (uint8_t)(val & 0x007FU);
11949 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_S4S_TPH_L,
11950 (uint8_t *)&s4s_tph_l, 1);
11951 }
11952
11953 if (ret == 0)
11954 {
11955 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_H,
11956 (uint8_t *)&s4s_tph_h, 1);
11957 }
11958
11959 if (ret == 0)
11960 {
11961 s4s_tph_h.tph_h = (uint8_t)((val & 0x7F80U) >> 7);
11962 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_S4S_TPH_H,
11963 (uint8_t *)&s4s_tph_h, 1);
11964 }
11965
11966 return ret;
11967 }
11968
11969 /**
11970 * @brief Sensor synchronization time frame.[get]
11971 *
11972 * @param ctx Read / write interface definitions.(ptr)
11973 * @param val Get the values of tph_l in S4S_TPH_L and tph_h in S4S_TPH_H
11974 * @retval Interface status (MANDATORY: return 0 -> no Error).
11975 *
11976 */
lsm6dsrx_s4s_tph_val_get(const stmdev_ctx_t * ctx,uint16_t * val)11977 int32_t lsm6dsrx_s4s_tph_val_get(const stmdev_ctx_t *ctx, uint16_t *val)
11978 {
11979 lsm6dsrx_s4s_tph_l_t s4s_tph_l;
11980 lsm6dsrx_s4s_tph_h_t s4s_tph_h;
11981 int32_t ret;
11982
11983 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1);
11984
11985 if (ret == 0)
11986 {
11987 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_H,
11988 (uint8_t *)&s4s_tph_h, 1);
11989 }
11990
11991 *val = s4s_tph_h.tph_h;
11992 *val = *val << 7;
11993 *val += s4s_tph_l.tph_l;
11994
11995 return ret;
11996 }
11997
11998 /**
11999 * @brief Sensor synchronization resolution ratio register.[set]
12000 *
12001 * @param ctx Read / write interface definitions.(ptr)
12002 * @param val Change the values of rr in S4S_RR.
12003 * @retval Interface status (MANDATORY: return 0 -> no Error).
12004 *
12005 */
lsm6dsrx_s4s_res_ratio_set(const stmdev_ctx_t * ctx,lsm6dsrx_s4s_res_ratio_t val)12006 int32_t lsm6dsrx_s4s_res_ratio_set(const stmdev_ctx_t *ctx,
12007 lsm6dsrx_s4s_res_ratio_t val)
12008 {
12009 lsm6dsrx_s4s_rr_t s4s_rr;
12010 int32_t ret;
12011
12012 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_RR, (uint8_t *)&s4s_rr, 1);
12013
12014 if (ret == 0)
12015 {
12016 s4s_rr.rr = (uint8_t)val;
12017 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_S4S_RR, (uint8_t *)&s4s_rr, 1);
12018 }
12019
12020 return ret;
12021 }
12022
12023 /**
12024 * @brief Sensor synchronization resolution ratio register.[get]
12025 *
12026 * @param ctx Read / write interface definitions.(ptr)
12027 * @param val get the values of rr in S4S_RR
12028 * @retval Interface status (MANDATORY: return 0 -> no Error).
12029 *
12030 */
lsm6dsrx_s4s_res_ratio_get(const stmdev_ctx_t * ctx,lsm6dsrx_s4s_res_ratio_t * val)12031 int32_t lsm6dsrx_s4s_res_ratio_get(const stmdev_ctx_t *ctx,
12032 lsm6dsrx_s4s_res_ratio_t *val)
12033 {
12034 lsm6dsrx_s4s_rr_t s4s_rr;
12035 int32_t ret;
12036
12037 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_RR, (uint8_t *)&s4s_rr, 1);
12038
12039 switch (s4s_rr.rr)
12040 {
12041 case LSM6DSRX_S4S_DT_RES_11:
12042 *val = LSM6DSRX_S4S_DT_RES_11;
12043 break;
12044
12045 case LSM6DSRX_S4S_DT_RES_12:
12046 *val = LSM6DSRX_S4S_DT_RES_12;
12047 break;
12048
12049 case LSM6DSRX_S4S_DT_RES_13:
12050 *val = LSM6DSRX_S4S_DT_RES_13;
12051 break;
12052
12053 case LSM6DSRX_S4S_DT_RES_14:
12054 *val = LSM6DSRX_S4S_DT_RES_14;
12055 break;
12056
12057 default:
12058 *val = LSM6DSRX_S4S_DT_RES_11;
12059 break;
12060 }
12061
12062 return ret;
12063 }
12064
12065 /**
12066 * @brief s4s master command.[set]
12067 *
12068 * @param ctx Read / write interface definitions.(ptr)
12069 * @param val Change the values of S4S_ST_CMD_CODE.
12070 * @retval Interface status (MANDATORY: return 0 -> no Error).
12071 *
12072 */
lsm6dsrx_s4s_command_set(const stmdev_ctx_t * ctx,uint8_t val)12073 int32_t lsm6dsrx_s4s_command_set(const stmdev_ctx_t *ctx, uint8_t val)
12074 {
12075 lsm6dsrx_s4s_st_cmd_code_t s4s_st_cmd_code;
12076 int32_t ret;
12077
12078 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_ST_CMD_CODE,
12079 (uint8_t *)&s4s_st_cmd_code, 1);
12080
12081 if (ret == 0)
12082 {
12083 s4s_st_cmd_code.s4s_st_cmd_code = (uint8_t)val;
12084 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_S4S_ST_CMD_CODE,
12085 (uint8_t *)&s4s_st_cmd_code, 1);
12086 }
12087
12088 return ret;
12089 }
12090
12091 /**
12092 * @brief s4s master command.[get]
12093 *
12094 * @param ctx Read / write interface definitions.(ptr)
12095 * @param val get the values of S4S_ST_CMD_CODE.
12096 * @retval Interface status (MANDATORY: return 0 -> no Error).
12097 *
12098 */
lsm6dsrx_s4s_command_get(const stmdev_ctx_t * ctx,uint8_t * val)12099 int32_t lsm6dsrx_s4s_command_get(const stmdev_ctx_t *ctx, uint8_t *val)
12100 {
12101 lsm6dsrx_s4s_st_cmd_code_t s4s_st_cmd_code;
12102 int32_t ret;
12103
12104 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_ST_CMD_CODE,
12105 (uint8_t *)&s4s_st_cmd_code, 1);
12106 *val = s4s_st_cmd_code.s4s_st_cmd_code;
12107
12108 return ret;
12109 }
12110
12111 /**
12112 * @brief S4S DT register.[set]
12113 *
12114 * @param ctx Read / write interface definitions.(ptr)
12115 * @param val Change the values of S4S_DT_REG.
12116 * @retval Interface status (MANDATORY: return 0 -> no Error).
12117 *
12118 */
lsm6dsrx_s4s_dt_set(const stmdev_ctx_t * ctx,uint8_t val)12119 int32_t lsm6dsrx_s4s_dt_set(const stmdev_ctx_t *ctx, uint8_t val)
12120 {
12121 lsm6dsrx_s4s_dt_reg_t s4s_dt_reg;
12122 int32_t ret;
12123
12124 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_DT_REG,
12125 (uint8_t *)&s4s_dt_reg, 1);
12126
12127 if (ret == 0)
12128 {
12129 s4s_dt_reg.dt = (uint8_t)val;
12130 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_S4S_DT_REG,
12131 (uint8_t *)&s4s_dt_reg, 1);
12132 }
12133
12134 return ret;
12135 }
12136
12137 /**
12138 * @brief S4S DT register.[get]
12139 *
12140 * @param ctx Read / write interface definitions.(ptr)
12141 * @param val get the values of S4S_DT_REG.
12142 * @retval Interface status (MANDATORY: return 0 -> no Error).
12143 *
12144 */
lsm6dsrx_s4s_dt_get(const stmdev_ctx_t * ctx,uint8_t * val)12145 int32_t lsm6dsrx_s4s_dt_get(const stmdev_ctx_t *ctx, uint8_t *val)
12146 {
12147 lsm6dsrx_s4s_dt_reg_t s4s_dt_reg;
12148 int32_t ret;
12149
12150 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_DT_REG,
12151 (uint8_t *)&s4s_dt_reg, 1);
12152 *val = s4s_dt_reg.dt;
12153
12154 return ret;
12155 }
12156
12157 /**
12158 * @}
12159 *
12160 */
12161
12162 /**
12163 * @}
12164 *
12165 */
12166
12167 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
12168
