1 /**
2 ******************************************************************************
3 * @file lsm6dsrx_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSRX driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dsrx_reg.h"
21
22 /**
23 * @defgroup LSM6DSRX
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dsrx enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LSM6DSRX_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6dsrx_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dsrx_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 ret = ctx->read_reg(ctx->handle, reg, data, len);
56
57 return ret;
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx read / write interface definitions(ptr)
64 * @param reg register to write
65 * @param data pointer to data to write in register reg(ptr)
66 * @param len number of consecutive register to write
67 * @retval interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
lsm6dsrx_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak lsm6dsrx_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
71 uint8_t *data,
72 uint16_t len)
73 {
74 int32_t ret;
75
76 ret = ctx->write_reg(ctx->handle, reg, data, len);
77
78 return ret;
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup LSM6DSRX_Sensitivity
88 * @brief These functions convert raw-data into engineering units.
89 * @{
90 *
91 */
92
lsm6dsrx_from_fs2g_to_mg(int16_t lsb)93 float_t lsm6dsrx_from_fs2g_to_mg(int16_t lsb)
94 {
95 return ((float_t)lsb * 0.061f);
96 }
97
lsm6dsrx_from_fs4g_to_mg(int16_t lsb)98 float_t lsm6dsrx_from_fs4g_to_mg(int16_t lsb)
99 {
100 return ((float_t)lsb * 0.122f);
101 }
102
lsm6dsrx_from_fs8g_to_mg(int16_t lsb)103 float_t lsm6dsrx_from_fs8g_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb * 0.244f);
106 }
107
lsm6dsrx_from_fs16g_to_mg(int16_t lsb)108 float_t lsm6dsrx_from_fs16g_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb * 0.488f);
111 }
112
lsm6dsrx_from_fs125dps_to_mdps(int16_t lsb)113 float_t lsm6dsrx_from_fs125dps_to_mdps(int16_t lsb)
114 {
115 return ((float_t)lsb * 4.375f);
116 }
117
lsm6dsrx_from_fs250dps_to_mdps(int16_t lsb)118 float_t lsm6dsrx_from_fs250dps_to_mdps(int16_t lsb)
119 {
120 return ((float_t)lsb * 8.75f);
121 }
122
lsm6dsrx_from_fs500dps_to_mdps(int16_t lsb)123 float_t lsm6dsrx_from_fs500dps_to_mdps(int16_t lsb)
124 {
125 return ((float_t)lsb * 17.50f);
126 }
127
lsm6dsrx_from_fs1000dps_to_mdps(int16_t lsb)128 float_t lsm6dsrx_from_fs1000dps_to_mdps(int16_t lsb)
129 {
130 return ((float_t)lsb * 35.0f);
131 }
132
lsm6dsrx_from_fs2000dps_to_mdps(int16_t lsb)133 float_t lsm6dsrx_from_fs2000dps_to_mdps(int16_t lsb)
134 {
135 return ((float_t)lsb * 70.0f);
136 }
137
lsm6dsrx_from_fs4000dps_to_mdps(int16_t lsb)138 float_t lsm6dsrx_from_fs4000dps_to_mdps(int16_t lsb)
139 {
140 return ((float_t)lsb * 140.0f);
141 }
142
lsm6dsrx_from_lsb_to_celsius(int16_t lsb)143 float_t lsm6dsrx_from_lsb_to_celsius(int16_t lsb)
144 {
145 return (((float_t)lsb / 256.0f) + 25.0f);
146 }
147
lsm6dsrx_from_lsb_to_nsec(int32_t lsb)148 float_t lsm6dsrx_from_lsb_to_nsec(int32_t lsb)
149 {
150 return ((float_t)lsb * 25000.0f);
151 }
152
153 /**
154 * @}
155 *
156 */
157
158 /**
159 * @defgroup LSM9DS1_Data_generation
160 * @brief This section groups all the functions concerning data
161 * generation
162 * @{
163 *
164 */
165
166 /**
167 * @brief Accelerometer full-scale selection[set]
168 *
169 * @param ctx Read / write interface definitions.(ptr)
170 * @param val Change the values of fs_xl in reg CTRL1_XL
171 * @retval Interface status (MANDATORY: return 0 -> no Error).
172 *
173 */
lsm6dsrx_xl_full_scale_set(stmdev_ctx_t * ctx,lsm6dsrx_fs_xl_t val)174 int32_t lsm6dsrx_xl_full_scale_set(stmdev_ctx_t *ctx,
175 lsm6dsrx_fs_xl_t val)
176 {
177 lsm6dsrx_ctrl1_xl_t ctrl1_xl;
178 int32_t ret;
179
180 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
181
182 if (ret == 0)
183 {
184 ctrl1_xl.fs_xl = (uint8_t)val;
185 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_XL,
186 (uint8_t *)&ctrl1_xl, 1);
187 }
188
189 return ret;
190 }
191
192 /**
193 * @brief Accelerometer full-scale selection.[get]
194 *
195 * @param ctx Read / write interface definitions.(ptr)
196 * @param val Get the values of fs_xl in reg CTRL1_XL
197 * @retval Interface status (MANDATORY: return 0 -> no Error).
198 *
199 */
lsm6dsrx_xl_full_scale_get(stmdev_ctx_t * ctx,lsm6dsrx_fs_xl_t * val)200 int32_t lsm6dsrx_xl_full_scale_get(stmdev_ctx_t *ctx,
201 lsm6dsrx_fs_xl_t *val)
202 {
203 lsm6dsrx_ctrl1_xl_t ctrl1_xl;
204 int32_t ret;
205
206 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
207
208 switch (ctrl1_xl.fs_xl)
209 {
210 case LSM6DSRX_2g:
211 *val = LSM6DSRX_2g;
212 break;
213
214 case LSM6DSRX_16g:
215 *val = LSM6DSRX_16g;
216 break;
217
218 case LSM6DSRX_4g:
219 *val = LSM6DSRX_4g;
220 break;
221
222 case LSM6DSRX_8g:
223 *val = LSM6DSRX_8g;
224 break;
225
226 default:
227 *val = LSM6DSRX_2g;
228 break;
229 }
230
231 return ret;
232 }
233
234 /**
235 * @brief Accelerometer UI data rate selection.[set]
236 *
237 * @param ctx Read / write interface definitions.(ptr)
238 * @param val Change the values of odr_xl in reg CTRL1_XL
239 * @retval Interface status (MANDATORY: return 0 -> no Error).
240 *
241 */
lsm6dsrx_xl_data_rate_set(stmdev_ctx_t * ctx,lsm6dsrx_odr_xl_t val)242 int32_t lsm6dsrx_xl_data_rate_set(stmdev_ctx_t *ctx,
243 lsm6dsrx_odr_xl_t val)
244 {
245 lsm6dsrx_odr_xl_t odr_xl = val;
246 lsm6dsrx_emb_fsm_enable_t fsm_enable;
247 lsm6dsrx_fsm_odr_t fsm_odr;
248 lsm6dsrx_ctrl1_xl_t ctrl1_xl;
249 lsm6dsrx_mlc_odr_t mlc_odr;
250 uint8_t mlc_enable;
251 int32_t ret;
252
253 /* Check the Finite State Machine data rate constraints */
254 ret = lsm6dsrx_fsm_enable_get(ctx, &fsm_enable);
255
256 if (ret == 0)
257 {
258 if ((fsm_enable.fsm_enable_a.fsm1_en |
259 fsm_enable.fsm_enable_a.fsm2_en |
260 fsm_enable.fsm_enable_a.fsm3_en |
261 fsm_enable.fsm_enable_a.fsm4_en |
262 fsm_enable.fsm_enable_a.fsm5_en |
263 fsm_enable.fsm_enable_a.fsm6_en |
264 fsm_enable.fsm_enable_a.fsm7_en |
265 fsm_enable.fsm_enable_a.fsm8_en |
266 fsm_enable.fsm_enable_b.fsm9_en |
267 fsm_enable.fsm_enable_b.fsm10_en |
268 fsm_enable.fsm_enable_b.fsm11_en |
269 fsm_enable.fsm_enable_b.fsm12_en |
270 fsm_enable.fsm_enable_b.fsm13_en |
271 fsm_enable.fsm_enable_b.fsm14_en |
272 fsm_enable.fsm_enable_b.fsm15_en |
273 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
274 {
275 ret = lsm6dsrx_fsm_data_rate_get(ctx, &fsm_odr);
276
277 if (ret == 0)
278 {
279 switch (fsm_odr)
280 {
281 case LSM6DSRX_ODR_FSM_12Hz5:
282 if (val == LSM6DSRX_XL_ODR_OFF)
283 {
284 odr_xl = LSM6DSRX_XL_ODR_12Hz5;
285 }
286
287 else
288 {
289 odr_xl = val;
290 }
291
292 break;
293
294 case LSM6DSRX_ODR_FSM_26Hz:
295 if (val == LSM6DSRX_XL_ODR_OFF)
296 {
297 odr_xl = LSM6DSRX_XL_ODR_26Hz;
298 }
299
300 else if (val == LSM6DSRX_XL_ODR_12Hz5)
301 {
302 odr_xl = LSM6DSRX_XL_ODR_26Hz;
303 }
304
305 else
306 {
307 odr_xl = val;
308 }
309
310 break;
311
312 case LSM6DSRX_ODR_FSM_52Hz:
313 if (val == LSM6DSRX_XL_ODR_OFF)
314 {
315 odr_xl = LSM6DSRX_XL_ODR_52Hz;
316 }
317
318 else if (val == LSM6DSRX_XL_ODR_12Hz5)
319 {
320 odr_xl = LSM6DSRX_XL_ODR_52Hz;
321 }
322
323 else if (val == LSM6DSRX_XL_ODR_26Hz)
324 {
325 odr_xl = LSM6DSRX_XL_ODR_52Hz;
326 }
327
328 else
329 {
330 odr_xl = val;
331 }
332
333 break;
334
335 case LSM6DSRX_ODR_FSM_104Hz:
336 if (val == LSM6DSRX_XL_ODR_OFF)
337 {
338 odr_xl = LSM6DSRX_XL_ODR_104Hz;
339 }
340
341 else if (val == LSM6DSRX_XL_ODR_12Hz5)
342 {
343 odr_xl = LSM6DSRX_XL_ODR_104Hz;
344 }
345
346 else if (val == LSM6DSRX_XL_ODR_26Hz)
347 {
348 odr_xl = LSM6DSRX_XL_ODR_104Hz;
349 }
350
351 else if (val == LSM6DSRX_XL_ODR_52Hz)
352 {
353 odr_xl = LSM6DSRX_XL_ODR_104Hz;
354 }
355
356 else
357 {
358 odr_xl = val;
359 }
360
361 break;
362
363 default:
364 odr_xl = val;
365 break;
366 }
367 }
368 }
369 }
370
371 /* Check the Machine Learning Core data rate constraints */
372 mlc_enable = PROPERTY_DISABLE;
373
374 if (ret == 0)
375 {
376 ret = lsm6dsrx_mlc_get(ctx, &mlc_enable);
377
378 if (mlc_enable == PROPERTY_ENABLE)
379 {
380 ret = lsm6dsrx_mlc_data_rate_get(ctx, &mlc_odr);
381
382 if (ret == 0)
383 {
384 switch (mlc_odr)
385 {
386 case LSM6DSRX_ODR_PRGS_12Hz5:
387 if (val == LSM6DSRX_XL_ODR_OFF)
388 {
389 odr_xl = LSM6DSRX_XL_ODR_12Hz5;
390 }
391
392 else
393 {
394 odr_xl = val;
395 }
396
397 break;
398
399 case LSM6DSRX_ODR_PRGS_26Hz:
400 if (val == LSM6DSRX_XL_ODR_OFF)
401 {
402 odr_xl = LSM6DSRX_XL_ODR_26Hz;
403 }
404
405 else if (val == LSM6DSRX_XL_ODR_12Hz5)
406 {
407 odr_xl = LSM6DSRX_XL_ODR_26Hz;
408 }
409
410 else
411 {
412 odr_xl = val;
413 }
414
415 break;
416
417 case LSM6DSRX_ODR_PRGS_52Hz:
418 if (val == LSM6DSRX_XL_ODR_OFF)
419 {
420 odr_xl = LSM6DSRX_XL_ODR_52Hz;
421 }
422
423 else if (val == LSM6DSRX_XL_ODR_12Hz5)
424 {
425 odr_xl = LSM6DSRX_XL_ODR_52Hz;
426 }
427
428 else if (val == LSM6DSRX_XL_ODR_26Hz)
429 {
430 odr_xl = LSM6DSRX_XL_ODR_52Hz;
431 }
432
433 else
434 {
435 odr_xl = val;
436 }
437
438 break;
439
440 case LSM6DSRX_ODR_PRGS_104Hz:
441 if (val == LSM6DSRX_XL_ODR_OFF)
442 {
443 odr_xl = LSM6DSRX_XL_ODR_104Hz;
444 }
445
446 else if (val == LSM6DSRX_XL_ODR_12Hz5)
447 {
448 odr_xl = LSM6DSRX_XL_ODR_104Hz;
449 }
450
451 else if (val == LSM6DSRX_XL_ODR_26Hz)
452 {
453 odr_xl = LSM6DSRX_XL_ODR_104Hz;
454 }
455
456 else if (val == LSM6DSRX_XL_ODR_52Hz)
457 {
458 odr_xl = LSM6DSRX_XL_ODR_104Hz;
459 }
460
461 else
462 {
463 odr_xl = val;
464 }
465
466 break;
467
468 default:
469 odr_xl = val;
470 break;
471 }
472 }
473 }
474 }
475
476 if (ret == 0)
477 {
478 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
479 }
480
481 if (ret == 0)
482 {
483 ctrl1_xl.odr_xl = (uint8_t)odr_xl;
484 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_XL,
485 (uint8_t *)&ctrl1_xl, 1);
486 }
487
488 return ret;
489 }
490
491 /**
492 * @brief Accelerometer UI data rate selection.[get]
493 *
494 * @param ctx Read / write interface definitions.(ptr)
495 * @param val Get the values of odr_xl in reg CTRL1_XL
496 * @retval Interface status (MANDATORY: return 0 -> no Error).
497 *
498 */
lsm6dsrx_xl_data_rate_get(stmdev_ctx_t * ctx,lsm6dsrx_odr_xl_t * val)499 int32_t lsm6dsrx_xl_data_rate_get(stmdev_ctx_t *ctx,
500 lsm6dsrx_odr_xl_t *val)
501 {
502 lsm6dsrx_ctrl1_xl_t ctrl1_xl;
503 int32_t ret;
504
505 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
506
507 switch (ctrl1_xl.odr_xl)
508 {
509 case LSM6DSRX_XL_ODR_OFF:
510 *val = LSM6DSRX_XL_ODR_OFF;
511 break;
512
513 case LSM6DSRX_XL_ODR_12Hz5:
514 *val = LSM6DSRX_XL_ODR_12Hz5;
515 break;
516
517 case LSM6DSRX_XL_ODR_26Hz:
518 *val = LSM6DSRX_XL_ODR_26Hz;
519 break;
520
521 case LSM6DSRX_XL_ODR_52Hz:
522 *val = LSM6DSRX_XL_ODR_52Hz;
523 break;
524
525 case LSM6DSRX_XL_ODR_104Hz:
526 *val = LSM6DSRX_XL_ODR_104Hz;
527 break;
528
529 case LSM6DSRX_XL_ODR_208Hz:
530 *val = LSM6DSRX_XL_ODR_208Hz;
531 break;
532
533 case LSM6DSRX_XL_ODR_416Hz:
534 *val = LSM6DSRX_XL_ODR_416Hz;
535 break;
536
537 case LSM6DSRX_XL_ODR_833Hz:
538 *val = LSM6DSRX_XL_ODR_833Hz;
539 break;
540
541 case LSM6DSRX_XL_ODR_1666Hz:
542 *val = LSM6DSRX_XL_ODR_1666Hz;
543 break;
544
545 case LSM6DSRX_XL_ODR_3332Hz:
546 *val = LSM6DSRX_XL_ODR_3332Hz;
547 break;
548
549 case LSM6DSRX_XL_ODR_6667Hz:
550 *val = LSM6DSRX_XL_ODR_6667Hz;
551 break;
552
553 case LSM6DSRX_XL_ODR_1Hz6:
554 *val = LSM6DSRX_XL_ODR_1Hz6;
555 break;
556
557 default:
558 *val = LSM6DSRX_XL_ODR_OFF;
559 break;
560 }
561
562 return ret;
563 }
564
565 /**
566 * @brief Gyroscope UI chain full-scale selection.[set]
567 *
568 * @param ctx Read / write interface definitions.(ptr)
569 * @param val Change the values of fs_g in reg CTRL2_G
570 * @retval Interface status (MANDATORY: return 0 -> no Error).
571 *
572 */
lsm6dsrx_gy_full_scale_set(stmdev_ctx_t * ctx,lsm6dsrx_fs_g_t val)573 int32_t lsm6dsrx_gy_full_scale_set(stmdev_ctx_t *ctx,
574 lsm6dsrx_fs_g_t val)
575 {
576 lsm6dsrx_ctrl2_g_t ctrl2_g;
577 int32_t ret;
578
579 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
580
581 if (ret == 0)
582 {
583 ctrl2_g.fs_g = (uint8_t)val;
584 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
585 }
586
587 return ret;
588 }
589
590 /**
591 * @brief Gyroscope UI chain full-scale selection.[get]
592 *
593 * @param ctx Read / write interface definitions.(ptr)
594 * @param val Get the values of fs_g in reg CTRL2_G
595 * @retval Interface status (MANDATORY: return 0 -> no Error).
596 *
597 */
lsm6dsrx_gy_full_scale_get(stmdev_ctx_t * ctx,lsm6dsrx_fs_g_t * val)598 int32_t lsm6dsrx_gy_full_scale_get(stmdev_ctx_t *ctx,
599 lsm6dsrx_fs_g_t *val)
600 {
601 lsm6dsrx_ctrl2_g_t ctrl2_g;
602 int32_t ret;
603
604 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
605
606 switch (ctrl2_g.fs_g)
607 {
608 case LSM6DSRX_125dps:
609 *val = LSM6DSRX_125dps;
610 break;
611
612 case LSM6DSRX_250dps:
613 *val = LSM6DSRX_250dps;
614 break;
615
616 case LSM6DSRX_500dps:
617 *val = LSM6DSRX_500dps;
618 break;
619
620 case LSM6DSRX_1000dps:
621 *val = LSM6DSRX_1000dps;
622 break;
623
624 case LSM6DSRX_2000dps:
625 *val = LSM6DSRX_2000dps;
626 break;
627
628 case LSM6DSRX_4000dps:
629 *val = LSM6DSRX_4000dps;
630 break;
631
632 default:
633 *val = LSM6DSRX_125dps;
634 break;
635 }
636
637 return ret;
638 }
639
640 /**
641 * @brief Gyroscope data rate.[set]
642 *
643 * @param ctx Read / write interface definitions.(ptr)
644 * @param val Change the values of odr_g in reg CTRL2_G
645 * @retval Interface status (MANDATORY: return 0 -> no Error).
646 *
647 */
lsm6dsrx_gy_data_rate_set(stmdev_ctx_t * ctx,lsm6dsrx_odr_g_t val)648 int32_t lsm6dsrx_gy_data_rate_set(stmdev_ctx_t *ctx,
649 lsm6dsrx_odr_g_t val)
650 {
651 lsm6dsrx_odr_g_t odr_gy = val;
652 lsm6dsrx_emb_fsm_enable_t fsm_enable;
653 lsm6dsrx_fsm_odr_t fsm_odr;
654 lsm6dsrx_ctrl2_g_t ctrl2_g;
655 lsm6dsrx_mlc_odr_t mlc_odr;
656 uint8_t mlc_enable;
657 int32_t ret;
658
659 /* Check the Finite State Machine data rate constraints */
660 ret = lsm6dsrx_fsm_enable_get(ctx, &fsm_enable);
661
662 if (ret == 0)
663 {
664 if ((fsm_enable.fsm_enable_a.fsm1_en |
665 fsm_enable.fsm_enable_a.fsm2_en |
666 fsm_enable.fsm_enable_a.fsm3_en |
667 fsm_enable.fsm_enable_a.fsm4_en |
668 fsm_enable.fsm_enable_a.fsm5_en |
669 fsm_enable.fsm_enable_a.fsm6_en |
670 fsm_enable.fsm_enable_a.fsm7_en |
671 fsm_enable.fsm_enable_a.fsm8_en |
672 fsm_enable.fsm_enable_b.fsm9_en |
673 fsm_enable.fsm_enable_b.fsm10_en |
674 fsm_enable.fsm_enable_b.fsm11_en |
675 fsm_enable.fsm_enable_b.fsm12_en |
676 fsm_enable.fsm_enable_b.fsm13_en |
677 fsm_enable.fsm_enable_b.fsm14_en |
678 fsm_enable.fsm_enable_b.fsm15_en |
679 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
680 {
681 ret = lsm6dsrx_fsm_data_rate_get(ctx, &fsm_odr);
682
683 if (ret == 0)
684 {
685 switch (fsm_odr)
686 {
687 case LSM6DSRX_ODR_FSM_12Hz5:
688 if (val == LSM6DSRX_GY_ODR_OFF)
689 {
690 odr_gy = LSM6DSRX_GY_ODR_12Hz5;
691 }
692
693 else
694 {
695 odr_gy = val;
696 }
697
698 break;
699
700 case LSM6DSRX_ODR_FSM_26Hz:
701 if (val == LSM6DSRX_GY_ODR_OFF)
702 {
703 odr_gy = LSM6DSRX_GY_ODR_26Hz;
704 }
705
706 else if (val == LSM6DSRX_GY_ODR_12Hz5)
707 {
708 odr_gy = LSM6DSRX_GY_ODR_26Hz;
709 }
710
711 else
712 {
713 odr_gy = val;
714 }
715
716 break;
717
718 case LSM6DSRX_ODR_FSM_52Hz:
719 if (val == LSM6DSRX_GY_ODR_OFF)
720 {
721 odr_gy = LSM6DSRX_GY_ODR_52Hz;
722 }
723
724 else if (val == LSM6DSRX_GY_ODR_12Hz5)
725 {
726 odr_gy = LSM6DSRX_GY_ODR_52Hz;
727 }
728
729 else if (val == LSM6DSRX_GY_ODR_26Hz)
730 {
731 odr_gy = LSM6DSRX_GY_ODR_52Hz;
732 }
733
734 else
735 {
736 odr_gy = val;
737 }
738
739 break;
740
741 case LSM6DSRX_ODR_FSM_104Hz:
742 if (val == LSM6DSRX_GY_ODR_OFF)
743 {
744 odr_gy = LSM6DSRX_GY_ODR_104Hz;
745 }
746
747 else if (val == LSM6DSRX_GY_ODR_12Hz5)
748 {
749 odr_gy = LSM6DSRX_GY_ODR_104Hz;
750 }
751
752 else if (val == LSM6DSRX_GY_ODR_26Hz)
753 {
754 odr_gy = LSM6DSRX_GY_ODR_104Hz;
755 }
756
757 else if (val == LSM6DSRX_GY_ODR_52Hz)
758 {
759 odr_gy = LSM6DSRX_GY_ODR_104Hz;
760 }
761
762 else
763 {
764 odr_gy = val;
765 }
766
767 break;
768
769 default:
770 odr_gy = val;
771 break;
772 }
773 }
774 }
775 }
776
777 /* Check the Machine Learning Core data rate constraints */
778 mlc_enable = PROPERTY_DISABLE;
779
780 if (ret == 0)
781 {
782 ret = lsm6dsrx_mlc_get(ctx, &mlc_enable);
783
784 if (mlc_enable == PROPERTY_ENABLE)
785 {
786 ret = lsm6dsrx_mlc_data_rate_get(ctx, &mlc_odr);
787
788 if (ret == 0)
789 {
790 switch (mlc_odr)
791 {
792 case LSM6DSRX_ODR_PRGS_12Hz5:
793 if (val == LSM6DSRX_GY_ODR_OFF)
794 {
795 odr_gy = LSM6DSRX_GY_ODR_12Hz5;
796 }
797
798 else
799 {
800 odr_gy = val;
801 }
802
803 break;
804
805 case LSM6DSRX_ODR_PRGS_26Hz:
806 if (val == LSM6DSRX_GY_ODR_OFF)
807 {
808 odr_gy = LSM6DSRX_GY_ODR_26Hz;
809 }
810
811 else if (val == LSM6DSRX_GY_ODR_12Hz5)
812 {
813 odr_gy = LSM6DSRX_GY_ODR_26Hz;
814 }
815
816 else
817 {
818 odr_gy = val;
819 }
820
821 break;
822
823 case LSM6DSRX_ODR_PRGS_52Hz:
824 if (val == LSM6DSRX_GY_ODR_OFF)
825 {
826 odr_gy = LSM6DSRX_GY_ODR_52Hz;
827 }
828
829 else if (val == LSM6DSRX_GY_ODR_12Hz5)
830 {
831 odr_gy = LSM6DSRX_GY_ODR_52Hz;
832 }
833
834 else if (val == LSM6DSRX_GY_ODR_26Hz)
835 {
836 odr_gy = LSM6DSRX_GY_ODR_52Hz;
837 }
838
839 else
840 {
841 odr_gy = val;
842 }
843
844 break;
845
846 case LSM6DSRX_ODR_PRGS_104Hz:
847 if (val == LSM6DSRX_GY_ODR_OFF)
848 {
849 odr_gy = LSM6DSRX_GY_ODR_104Hz;
850 }
851
852 else if (val == LSM6DSRX_GY_ODR_12Hz5)
853 {
854 odr_gy = LSM6DSRX_GY_ODR_104Hz;
855 }
856
857 else if (val == LSM6DSRX_GY_ODR_26Hz)
858 {
859 odr_gy = LSM6DSRX_GY_ODR_104Hz;
860 }
861
862 else if (val == LSM6DSRX_GY_ODR_52Hz)
863 {
864 odr_gy = LSM6DSRX_GY_ODR_104Hz;
865 }
866
867 else
868 {
869 odr_gy = val;
870 }
871
872 break;
873
874 default:
875 odr_gy = val;
876 break;
877 }
878 }
879 }
880 }
881
882 if (ret == 0)
883 {
884 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
885 }
886
887 if (ret == 0)
888 {
889 ctrl2_g.odr_g = (uint8_t)odr_gy;
890 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
891 }
892
893 return ret;
894 }
895
896 /**
897 * @brief Gyroscope data rate.[get]
898 *
899 * @param ctx Read / write interface definitions.(ptr)
900 * @param val Get the values of odr_g in reg CTRL2_G
901 * @retval Interface status (MANDATORY: return 0 -> no Error).
902 *
903 */
lsm6dsrx_gy_data_rate_get(stmdev_ctx_t * ctx,lsm6dsrx_odr_g_t * val)904 int32_t lsm6dsrx_gy_data_rate_get(stmdev_ctx_t *ctx,
905 lsm6dsrx_odr_g_t *val)
906 {
907 lsm6dsrx_ctrl2_g_t ctrl2_g;
908 int32_t ret;
909
910 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
911
912 switch (ctrl2_g.odr_g)
913 {
914 case LSM6DSRX_GY_ODR_OFF:
915 *val = LSM6DSRX_GY_ODR_OFF;
916 break;
917
918 case LSM6DSRX_GY_ODR_12Hz5:
919 *val = LSM6DSRX_GY_ODR_12Hz5;
920 break;
921
922 case LSM6DSRX_GY_ODR_26Hz:
923 *val = LSM6DSRX_GY_ODR_26Hz;
924 break;
925
926 case LSM6DSRX_GY_ODR_52Hz:
927 *val = LSM6DSRX_GY_ODR_52Hz;
928 break;
929
930 case LSM6DSRX_GY_ODR_104Hz:
931 *val = LSM6DSRX_GY_ODR_104Hz;
932 break;
933
934 case LSM6DSRX_GY_ODR_208Hz:
935 *val = LSM6DSRX_GY_ODR_208Hz;
936 break;
937
938 case LSM6DSRX_GY_ODR_416Hz:
939 *val = LSM6DSRX_GY_ODR_416Hz;
940 break;
941
942 case LSM6DSRX_GY_ODR_833Hz:
943 *val = LSM6DSRX_GY_ODR_833Hz;
944 break;
945
946 case LSM6DSRX_GY_ODR_1666Hz:
947 *val = LSM6DSRX_GY_ODR_1666Hz;
948 break;
949
950 case LSM6DSRX_GY_ODR_3332Hz:
951 *val = LSM6DSRX_GY_ODR_3332Hz;
952 break;
953
954 case LSM6DSRX_GY_ODR_6667Hz:
955 *val = LSM6DSRX_GY_ODR_6667Hz;
956 break;
957
958 default:
959 *val = LSM6DSRX_GY_ODR_OFF;
960 break;
961 }
962
963 return ret;
964 }
965
966 /**
967 * @brief Block data update.[set]
968 *
969 * @param ctx Read / write interface definitions.(ptr)
970 * @param val Change the values of bdu in reg CTRL3_C
971 * @retval Interface status (MANDATORY: return 0 -> no Error).
972 *
973 */
lsm6dsrx_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)974 int32_t lsm6dsrx_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
975 {
976 lsm6dsrx_ctrl3_c_t ctrl3_c;
977 int32_t ret;
978
979 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
980
981 if (ret == 0)
982 {
983 ctrl3_c.bdu = (uint8_t)val;
984 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
985 }
986
987 return ret;
988 }
989
990 /**
991 * @brief Block data update.[get]
992 *
993 * @param ctx Read / write interface definitions.(ptr)
994 * @param val Change the values of bdu in reg CTRL3_C
995 * @retval Interface status (MANDATORY: return 0 -> no Error).
996 *
997 */
lsm6dsrx_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)998 int32_t lsm6dsrx_block_data_update_get(stmdev_ctx_t *ctx,
999 uint8_t *val)
1000 {
1001 lsm6dsrx_ctrl3_c_t ctrl3_c;
1002 int32_t ret;
1003
1004 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1005 *val = ctrl3_c.bdu;
1006
1007 return ret;
1008 }
1009
1010 /**
1011 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
1012 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
1013 *
1014 * @param ctx Read / write interface definitions.(ptr)
1015 * @param val Change the values of usr_off_w in reg CTRL6_C
1016 * @retval Interface status (MANDATORY: return 0 -> no Error).
1017 *
1018 */
lsm6dsrx_xl_offset_weight_set(stmdev_ctx_t * ctx,lsm6dsrx_usr_off_w_t val)1019 int32_t lsm6dsrx_xl_offset_weight_set(stmdev_ctx_t *ctx,
1020 lsm6dsrx_usr_off_w_t val)
1021 {
1022 lsm6dsrx_ctrl6_c_t ctrl6_c;
1023 int32_t ret;
1024
1025 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
1026
1027 if (ret == 0)
1028 {
1029 ctrl6_c.usr_off_w = (uint8_t)val;
1030 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
1031 }
1032
1033 return ret;
1034 }
1035
1036 /**
1037 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
1038 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
1039 *
1040 * @param ctx Read / write interface definitions.(ptr)
1041 * @param val Get the values of usr_off_w in reg CTRL6_C
1042 * @retval Interface status (MANDATORY: return 0 -> no Error).
1043 *
1044 */
lsm6dsrx_xl_offset_weight_get(stmdev_ctx_t * ctx,lsm6dsrx_usr_off_w_t * val)1045 int32_t lsm6dsrx_xl_offset_weight_get(stmdev_ctx_t *ctx,
1046 lsm6dsrx_usr_off_w_t *val)
1047 {
1048 lsm6dsrx_ctrl6_c_t ctrl6_c;
1049 int32_t ret;
1050
1051 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
1052
1053 switch (ctrl6_c.usr_off_w)
1054 {
1055 case LSM6DSRX_LSb_1mg:
1056 *val = LSM6DSRX_LSb_1mg;
1057 break;
1058
1059 case LSM6DSRX_LSb_16mg:
1060 *val = LSM6DSRX_LSb_16mg;
1061 break;
1062
1063 default:
1064 *val = LSM6DSRX_LSb_1mg;
1065 break;
1066 }
1067
1068 return ret;
1069 }
1070
1071 /**
1072 * @brief Accelerometer power mode.[set]
1073 *
1074 * @param ctx Read / write interface definitions.(ptr)
1075 * @param val Change the values of xl_hm_mode in reg CTRL6_C
1076 * @retval Interface status (MANDATORY: return 0 -> no Error).
1077 *
1078 */
lsm6dsrx_xl_power_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_xl_hm_mode_t val)1079 int32_t lsm6dsrx_xl_power_mode_set(stmdev_ctx_t *ctx,
1080 lsm6dsrx_xl_hm_mode_t val)
1081 {
1082 lsm6dsrx_ctrl6_c_t ctrl6_c;
1083 int32_t ret;
1084
1085 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
1086
1087 if (ret == 0)
1088 {
1089 ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
1090 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
1091 }
1092
1093 return ret;
1094 }
1095
1096 /**
1097 * @brief Accelerometer power mode[get]
1098 *
1099 * @param ctx Read / write interface definitions.(ptr)
1100 * @param val Get the values of xl_hm_mode in reg CTRL6_C
1101 * @retval Interface status (MANDATORY: return 0 -> no Error).
1102 *
1103 */
lsm6dsrx_xl_power_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_xl_hm_mode_t * val)1104 int32_t lsm6dsrx_xl_power_mode_get(stmdev_ctx_t *ctx,
1105 lsm6dsrx_xl_hm_mode_t *val)
1106 {
1107 lsm6dsrx_ctrl6_c_t ctrl6_c;
1108 int32_t ret;
1109
1110 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
1111
1112 switch (ctrl6_c.xl_hm_mode)
1113 {
1114 case LSM6DSRX_HIGH_PERFORMANCE_MD:
1115 *val = LSM6DSRX_HIGH_PERFORMANCE_MD;
1116 break;
1117
1118 case LSM6DSRX_LOW_NORMAL_POWER_MD:
1119 *val = LSM6DSRX_LOW_NORMAL_POWER_MD;
1120 break;
1121
1122 default:
1123 *val = LSM6DSRX_HIGH_PERFORMANCE_MD;
1124 break;
1125 }
1126
1127 return ret;
1128 }
1129
1130 /**
1131 * @brief Operating mode for gyroscope.[set]
1132 *
1133 * @param ctx Read / write interface definitions.(ptr)
1134 * @param val Change the values of g_hm_mode in reg CTRL7_G
1135 * @retval Interface status (MANDATORY: return 0 -> no Error).
1136 *
1137 */
lsm6dsrx_gy_power_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_g_hm_mode_t val)1138 int32_t lsm6dsrx_gy_power_mode_set(stmdev_ctx_t *ctx,
1139 lsm6dsrx_g_hm_mode_t val)
1140 {
1141 lsm6dsrx_ctrl7_g_t ctrl7_g;
1142 int32_t ret;
1143
1144 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1145
1146 if (ret == 0)
1147 {
1148 ctrl7_g.g_hm_mode = (uint8_t)val;
1149 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1150 }
1151
1152 return ret;
1153 }
1154
1155 /**
1156 * @brief gy_power_mode: [get] Operating mode for gyroscope.
1157 *
1158 * @param ctx Read / write interface definitions.(ptr)
1159 * @param val Get the values of g_hm_mode in reg CTRL7_G
1160 * @retval Interface status (MANDATORY: return 0 -> no Error).
1161 *
1162 */
lsm6dsrx_gy_power_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_g_hm_mode_t * val)1163 int32_t lsm6dsrx_gy_power_mode_get(stmdev_ctx_t *ctx,
1164 lsm6dsrx_g_hm_mode_t *val)
1165 {
1166 lsm6dsrx_ctrl7_g_t ctrl7_g;
1167 int32_t ret;
1168
1169 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1170
1171 switch (ctrl7_g.g_hm_mode)
1172 {
1173 case LSM6DSRX_GY_HIGH_PERFORMANCE:
1174 *val = LSM6DSRX_GY_HIGH_PERFORMANCE;
1175 break;
1176
1177 case LSM6DSRX_GY_NORMAL:
1178 *val = LSM6DSRX_GY_NORMAL;
1179 break;
1180
1181 default:
1182 *val = LSM6DSRX_GY_HIGH_PERFORMANCE;
1183 break;
1184 }
1185
1186 return ret;
1187 }
1188
1189 /**
1190 * @brief Read all the interrupt flag of the device.
1191 *[get]
1192 * @param ctx Read / write interface definitions.(ptr)
1193 * @param val Get registers ALL_INT_SRC; WAKE_UP_SRC;
1194 * TAP_SRC; D6D_SRC; STATUS_REG;
1195 * EMB_FUNC_STATUS; FSM_STATUS_A/B
1196 * @retval Interface status (MANDATORY: return 0 -> no Error).
1197 *
1198 */
lsm6dsrx_all_sources_get(stmdev_ctx_t * ctx,lsm6dsrx_all_sources_t * val)1199 int32_t lsm6dsrx_all_sources_get(stmdev_ctx_t *ctx,
1200 lsm6dsrx_all_sources_t *val)
1201 {
1202 int32_t ret;
1203
1204 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_ALL_INT_SRC,
1205 (uint8_t *)&val->all_int_src, 1);
1206
1207 if (ret == 0)
1208 {
1209 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_SRC,
1210 (uint8_t *)&val->wake_up_src, 1);
1211 }
1212
1213 if (ret == 0)
1214 {
1215 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_SRC,
1216 (uint8_t *)&val->tap_src, 1);
1217 }
1218
1219 if (ret == 0)
1220 {
1221 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_D6D_SRC,
1222 (uint8_t *)&val->d6d_src, 1);
1223 }
1224
1225 if (ret == 0)
1226 {
1227 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG,
1228 (uint8_t *)&val->status_reg, 1);
1229 }
1230
1231 if (ret == 0)
1232 {
1233 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
1234 }
1235
1236 if (ret == 0)
1237 {
1238 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_STATUS,
1239 (uint8_t *)&val->emb_func_status, 1);
1240 }
1241
1242 if (ret == 0)
1243 {
1244 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_STATUS_A,
1245 (uint8_t *)&val->fsm_status_a, 1);
1246 }
1247
1248 if (ret == 0)
1249 {
1250 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_STATUS_B,
1251 (uint8_t *)&val->fsm_status_b, 1);
1252 }
1253
1254 if (ret == 0)
1255 {
1256 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MLC_STATUS,
1257 (uint8_t *)&val->mlc_status, 1);
1258 }
1259
1260 if (ret == 0)
1261 {
1262 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
1263 }
1264
1265 return ret;
1266 }
1267
1268 /**
1269 * @brief The STATUS_REG register is read by the primary interface.[get]
1270 *
1271 * @param ctx Read / write interface definitions.(ptr)
1272 * @param val Get register STATUS_REG
1273 * @retval Interface status (MANDATORY: return 0 -> no Error).
1274 *
1275 */
lsm6dsrx_status_reg_get(stmdev_ctx_t * ctx,lsm6dsrx_status_reg_t * val)1276 int32_t lsm6dsrx_status_reg_get(stmdev_ctx_t *ctx,
1277 lsm6dsrx_status_reg_t *val)
1278 {
1279 int32_t ret;
1280
1281 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG, (uint8_t *) val, 1);
1282
1283 return ret;
1284 }
1285
1286 /**
1287 * @brief Accelerometer new data available.[get]
1288 *
1289 * @param ctx Read / write interface definitions.(ptr)
1290 * @param val Change the values of xlda in reg STATUS_REG
1291 * @retval Interface status (MANDATORY: return 0 -> no Error).
1292 *
1293 */
lsm6dsrx_xl_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1294 int32_t lsm6dsrx_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
1295 uint8_t *val)
1296 {
1297 lsm6dsrx_status_reg_t status_reg;
1298 int32_t ret;
1299
1300 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG,
1301 (uint8_t *)&status_reg, 1);
1302 *val = status_reg.xlda;
1303
1304 return ret;
1305 }
1306
1307 /**
1308 * @brief Gyroscope new data available.[get]
1309 *
1310 * @param ctx Read / write interface definitions.(ptr)
1311 * @param val Change the values of gda in reg STATUS_REG
1312 * @retval Interface status (MANDATORY: return 0 -> no Error).
1313 *
1314 */
lsm6dsrx_gy_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1315 int32_t lsm6dsrx_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
1316 uint8_t *val)
1317 {
1318 lsm6dsrx_status_reg_t status_reg;
1319 int32_t ret;
1320
1321 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG,
1322 (uint8_t *)&status_reg, 1);
1323 *val = status_reg.gda;
1324
1325 return ret;
1326 }
1327
1328 /**
1329 * @brief Temperature new data available.[get]
1330 *
1331 * @param ctx Read / write interface definitions.(ptr)
1332 * @param val Change the values of tda in reg STATUS_REG
1333 * @retval Interface status (MANDATORY: return 0 -> no Error).
1334 *
1335 */
lsm6dsrx_temp_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1336 int32_t lsm6dsrx_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
1337 uint8_t *val)
1338 {
1339 lsm6dsrx_status_reg_t status_reg;
1340 int32_t ret;
1341
1342 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_REG,
1343 (uint8_t *)&status_reg, 1);
1344 *val = status_reg.tda;
1345
1346 return ret;
1347 }
1348
1349 /**
1350 * @brief Accelerometer X-axis user offset correction expressed in two’s
1351 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1352 * The value must be in the range [-127 127].[set]
1353 *
1354 * @param ctx Read / write interface definitions.(ptr)
1355 * @param buff Buffer that contains data to write
1356 * @retval Interface status (MANDATORY: return 0 -> no Error).
1357 *
1358 */
lsm6dsrx_xl_usr_offset_x_set(stmdev_ctx_t * ctx,uint8_t * buff)1359 int32_t lsm6dsrx_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
1360 {
1361 int32_t ret;
1362
1363 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_X_OFS_USR, buff, 1);
1364
1365 return ret;
1366 }
1367
1368 /**
1369 * @brief Accelerometer X-axis user offset correction expressed in two’s
1370 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1371 * The value must be in the range [-127 127].[get]
1372 *
1373 * @param ctx Read / write interface definitions.(ptr)
1374 * @param buff Buffer that stores data read
1375 * @retval Interface status (MANDATORY: return 0 -> no Error).
1376 *
1377 */
lsm6dsrx_xl_usr_offset_x_get(stmdev_ctx_t * ctx,uint8_t * buff)1378 int32_t lsm6dsrx_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
1379 {
1380 int32_t ret;
1381
1382 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_X_OFS_USR, buff, 1);
1383
1384 return ret;
1385 }
1386
1387 /**
1388 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1389 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1390 * The value must be in the range [-127 127].[set]
1391 *
1392 * @param ctx Read / write interface definitions.(ptr)
1393 * @param buff Buffer that contains data to write
1394 * @retval Interface status (MANDATORY: return 0 -> no Error).
1395 *
1396 */
lsm6dsrx_xl_usr_offset_y_set(stmdev_ctx_t * ctx,uint8_t * buff)1397 int32_t lsm6dsrx_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
1398 {
1399 int32_t ret;
1400
1401 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_Y_OFS_USR, buff, 1);
1402
1403 return ret;
1404 }
1405
1406 /**
1407 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1408 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1409 * The value must be in the range [-127 127].[get]
1410 *
1411 * @param ctx Read / write interface definitions.(ptr)
1412 * @param buff Buffer that stores data read
1413 * @retval Interface status (MANDATORY: return 0 -> no Error).
1414 *
1415 */
lsm6dsrx_xl_usr_offset_y_get(stmdev_ctx_t * ctx,uint8_t * buff)1416 int32_t lsm6dsrx_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
1417 {
1418 int32_t ret;
1419
1420 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_Y_OFS_USR, buff, 1);
1421
1422 return ret;
1423 }
1424
1425 /**
1426 * @brief Accelerometer Z-axis user offset correction expressed in two’s
1427 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1428 * The value must be in the range [-127 127].[set]
1429 *
1430 * @param ctx Read / write interface definitions.(ptr)
1431 * @param buff Buffer that contains data to write
1432 * @retval Interface status (MANDATORY: return 0 -> no Error).
1433 *
1434 */
lsm6dsrx_xl_usr_offset_z_set(stmdev_ctx_t * ctx,uint8_t * buff)1435 int32_t lsm6dsrx_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
1436 {
1437 int32_t ret;
1438
1439 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_Z_OFS_USR, buff, 1);
1440
1441 return ret;
1442 }
1443
1444 /**
1445 * @brief Accelerometer X-axis user offset correction expressed in two’s
1446 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1447 * The value must be in the range [-127 127].[get]
1448 *
1449 * @param ctx Read / write interface definitions.(ptr)
1450 * @param buff Buffer that stores data read
1451 * @retval Interface status (MANDATORY: return 0 -> no Error).
1452 *
1453 */
lsm6dsrx_xl_usr_offset_z_get(stmdev_ctx_t * ctx,uint8_t * buff)1454 int32_t lsm6dsrx_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
1455 {
1456 int32_t ret;
1457
1458 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_Z_OFS_USR, buff, 1);
1459
1460 return ret;
1461 }
1462
1463 /**
1464 * @brief Enables user offset on out.[set]
1465 *
1466 * @param ctx Read / write interface definitions.(ptr)
1467 * @param val Change the values of usr_off_on_out in reg CTRL7_G
1468 * @retval Interface status (MANDATORY: return 0 -> no Error).
1469 *
1470 */
lsm6dsrx_xl_usr_offset_set(stmdev_ctx_t * ctx,uint8_t val)1471 int32_t lsm6dsrx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
1472 {
1473 lsm6dsrx_ctrl7_g_t ctrl7_g;
1474 int32_t ret;
1475
1476 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1477
1478 if (ret == 0)
1479 {
1480 ctrl7_g.usr_off_on_out = (uint8_t)val;
1481 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1482 }
1483
1484 return ret;
1485 }
1486
1487 /**
1488 * @brief Get user offset on out flag.[get]
1489 *
1490 * @param ctx Read / write interface definitions.(ptr)
1491 * @param val Get values of usr_off_on_out in reg CTRL7_G
1492 * @retval Interface status (MANDATORY: return 0 -> no Error).
1493 *
1494 */
lsm6dsrx_xl_usr_offset_get(stmdev_ctx_t * ctx,uint8_t * val)1495 int32_t lsm6dsrx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
1496 {
1497 lsm6dsrx_ctrl7_g_t ctrl7_g;
1498 int32_t ret;
1499
1500 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1501 *val = ctrl7_g.usr_off_on_out;
1502
1503 return ret;
1504 }
1505
1506 /**
1507 * @}
1508 *
1509 */
1510
1511 /**
1512 * @defgroup LSM6DSRX_Timestamp
1513 * @brief This section groups all the functions that manage the
1514 * timestamp generation.
1515 * @{
1516 *
1517 */
1518
1519 /**
1520 * @brief Reset timestamp counter.[set]
1521 *
1522 * @param ctx Read / write interface definitions.(ptr)
1523 * @retval Interface status (MANDATORY: return 0 -> no Error).
1524 *
1525 */
lsm6dsrx_timestamp_rst(stmdev_ctx_t * ctx)1526 int32_t lsm6dsrx_timestamp_rst(stmdev_ctx_t *ctx)
1527 {
1528 uint8_t rst_val = 0xAA;
1529 return lsm6dsrx_write_reg(ctx, LSM6DSRX_TIMESTAMP2, &rst_val, 1);
1530 }
1531
1532 /**
1533 * @brief Enables timestamp counter.[set]
1534 *
1535 * @param ctx Read / write interface definitions.(ptr)
1536 * @param val Change the values of timestamp_en in reg CTRL10_C
1537 * @retval Interface status (MANDATORY: return 0 -> no Error).
1538 *
1539 */
lsm6dsrx_timestamp_set(stmdev_ctx_t * ctx,uint8_t val)1540 int32_t lsm6dsrx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
1541 {
1542 lsm6dsrx_ctrl10_c_t ctrl10_c;
1543 int32_t ret;
1544
1545 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1546
1547 if (ret == 0)
1548 {
1549 ctrl10_c.timestamp_en = (uint8_t)val;
1550 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL10_C,
1551 (uint8_t *)&ctrl10_c, 1);
1552 }
1553
1554 return ret;
1555 }
1556
1557 /**
1558 * @brief Enables timestamp counter.[get]
1559 *
1560 * @param ctx Read / write interface definitions.(ptr)
1561 * @param val Change the values of timestamp_en in reg CTRL10_C
1562 * @retval Interface status (MANDATORY: return 0 -> no Error).
1563 *
1564 */
lsm6dsrx_timestamp_get(stmdev_ctx_t * ctx,uint8_t * val)1565 int32_t lsm6dsrx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
1566 {
1567 lsm6dsrx_ctrl10_c_t ctrl10_c;
1568 int32_t ret;
1569
1570 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1571 *val = ctrl10_c.timestamp_en;
1572
1573 return ret;
1574 }
1575
1576 /**
1577 * @brief Timestamp first data output register (r).
1578 * The value is expressed as a 32-bit word and the bit resolution
1579 * is 25 μs.[get]
1580 *
1581 * @param ctx Read / write interface definitions.(ptr)
1582 * @param buff Buffer that stores data read
1583 * @retval Interface status (MANDATORY: return 0 -> no Error).
1584 *
1585 */
lsm6dsrx_timestamp_raw_get(stmdev_ctx_t * ctx,uint32_t * val)1586 int32_t lsm6dsrx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
1587 {
1588 uint8_t buff[4];
1589 int32_t ret;
1590
1591 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TIMESTAMP0, buff, 4);
1592 *val = buff[3];
1593 *val = (*val * 256U) + buff[2];
1594 *val = (*val * 256U) + buff[1];
1595 *val = (*val * 256U) + buff[0];
1596
1597 return ret;
1598 }
1599
1600 /**
1601 * @}
1602 *
1603 */
1604
1605 /**
1606 * @defgroup LSM6DSRX_Data output
1607 * @brief This section groups all the data output functions.
1608 * @{
1609 *
1610 */
1611
1612 /**
1613 * @brief Circular burst-mode (rounding) read of the output registers.[set]
1614 *
1615 * @param ctx Read / write interface definitions.(ptr)
1616 * @param val Change the values of rounding in reg CTRL5_C
1617 * @retval Interface status (MANDATORY: return 0 -> no Error).
1618 *
1619 */
lsm6dsrx_rounding_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_rounding_t val)1620 int32_t lsm6dsrx_rounding_mode_set(stmdev_ctx_t *ctx,
1621 lsm6dsrx_rounding_t val)
1622 {
1623 lsm6dsrx_ctrl5_c_t ctrl5_c;
1624 int32_t ret;
1625
1626 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1627
1628 if (ret == 0)
1629 {
1630 ctrl5_c.rounding = (uint8_t)val;
1631 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1632 }
1633
1634 return ret;
1635 }
1636
1637 /**
1638 * @brief Gyroscope UI chain full-scale selection.[get]
1639 *
1640 * @param ctx Read / write interface definitions.(ptr)
1641 * @param val Get the values of rounding in reg CTRL5_C
1642 * @retval Interface status (MANDATORY: return 0 -> no Error).
1643 *
1644 */
lsm6dsrx_rounding_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_rounding_t * val)1645 int32_t lsm6dsrx_rounding_mode_get(stmdev_ctx_t *ctx,
1646 lsm6dsrx_rounding_t *val)
1647 {
1648 lsm6dsrx_ctrl5_c_t ctrl5_c;
1649 int32_t ret;
1650
1651 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1652
1653 switch (ctrl5_c.rounding)
1654 {
1655 case LSM6DSRX_NO_ROUND:
1656 *val = LSM6DSRX_NO_ROUND;
1657 break;
1658
1659 case LSM6DSRX_ROUND_XL:
1660 *val = LSM6DSRX_ROUND_XL;
1661 break;
1662
1663 case LSM6DSRX_ROUND_GY:
1664 *val = LSM6DSRX_ROUND_GY;
1665 break;
1666
1667 case LSM6DSRX_ROUND_GY_XL:
1668 *val = LSM6DSRX_ROUND_GY_XL;
1669 break;
1670
1671 default:
1672 *val = LSM6DSRX_NO_ROUND;
1673 break;
1674 }
1675
1676 return ret;
1677 }
1678
1679 /**
1680 * @brief Temperature data output register (r).
1681 * L and H registers together express a 16-bit word in two’s
1682 * complement.[get]
1683 *
1684 * @param ctx Read / write interface definitions.(ptr)
1685 * @param buff Buffer that stores data read
1686 * @retval Interface status (MANDATORY: return 0 -> no Error).
1687 *
1688 */
lsm6dsrx_temperature_raw_get(stmdev_ctx_t * ctx,int16_t * val)1689 int32_t lsm6dsrx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1690 {
1691 uint8_t buff[2];
1692 int32_t ret;
1693
1694 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_OUT_TEMP_L, buff, 2);
1695 *val = (int16_t)buff[1];
1696 *val = (*val * 256) + (int16_t)buff[0];
1697
1698 return ret;
1699 }
1700
1701 /**
1702 * @brief Angular rate sensor. The value is expressed as a 16-bit
1703 * word in two’s complement.[get]
1704 *
1705 * @param ctx Read / write interface definitions.(ptr)
1706 * @param buff Buffer that stores data read
1707 * @retval Interface status (MANDATORY: return 0 -> no Error).
1708 *
1709 */
lsm6dsrx_angular_rate_raw_get(stmdev_ctx_t * ctx,int16_t * val)1710 int32_t lsm6dsrx_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1711 {
1712 uint8_t buff[6];
1713 int32_t ret;
1714
1715 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_OUTX_L_G, buff, 6);
1716 val[0] = (int16_t)buff[1];
1717 val[0] = (val[0] * 256) + (int16_t)buff[0];
1718 val[1] = (int16_t)buff[3];
1719 val[1] = (val[1] * 256) + (int16_t)buff[2];
1720 val[2] = (int16_t)buff[5];
1721 val[2] = (val[2] * 256) + (int16_t)buff[4];
1722
1723 return ret;
1724 }
1725
1726 /**
1727 * @brief Linear acceleration output register. The value is expressed as a
1728 * 16-bit word in two’s complement.[get]
1729 *
1730 * @param ctx Read / write interface definitions.(ptr)
1731 * @param buff Buffer that stores data read
1732 * @retval Interface status (MANDATORY: return 0 -> no Error).
1733 *
1734 */
lsm6dsrx_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)1735 int32_t lsm6dsrx_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1736 {
1737 uint8_t buff[6];
1738 int32_t ret;
1739
1740 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_OUTX_L_A, buff, 6);
1741 val[0] = (int16_t)buff[1];
1742 val[0] = (val[0] * 256) + (int16_t)buff[0];
1743 val[1] = (int16_t)buff[3];
1744 val[1] = (val[1] * 256) + (int16_t)buff[2];
1745 val[2] = (int16_t)buff[5];
1746 val[2] = (val[2] * 256) + (int16_t)buff[4];
1747
1748 return ret;
1749 }
1750
1751 /**
1752 * @brief FIFO data output.[get]
1753 *
1754 * @param ctx Read / write interface definitions.(ptr)
1755 * @param buff Buffer that stores data read
1756 * @retval Interface status (MANDATORY: return 0 -> no Error).
1757 *
1758 */
lsm6dsrx_fifo_out_raw_get(stmdev_ctx_t * ctx,uint8_t * val)1759 int32_t lsm6dsrx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val)
1760 {
1761 int32_t ret;
1762
1763 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_DATA_OUT_X_L, val, 6);
1764
1765 return ret;
1766 }
1767
1768 /**
1769 * @brief Step counter output register.[get]
1770 *
1771 * @param ctx Read / write interface definitions.(ptr)
1772 * @param buff Buffer that stores data read
1773 * @retval Interface status (MANDATORY: return 0 -> no Error).
1774 *
1775 */
lsm6dsrx_number_of_steps_get(stmdev_ctx_t * ctx,uint16_t * val)1776 int32_t lsm6dsrx_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val)
1777 {
1778 uint8_t buff[2];
1779 int32_t ret;
1780
1781 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
1782
1783 if (ret == 0)
1784 {
1785 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STEP_COUNTER_L, buff, 2);
1786 *val = buff[1];
1787 *val = (*val * 256U) + buff[0];
1788 }
1789
1790 if (ret == 0)
1791 {
1792 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
1793 }
1794
1795 return ret;
1796 }
1797
1798 /**
1799 * @brief Reset step counter register.[get]
1800 *
1801 * @param ctx Read / write interface definitions.(ptr)
1802 * @retval Interface status (MANDATORY: return 0 -> no Error).
1803 *
1804 */
lsm6dsrx_steps_reset(stmdev_ctx_t * ctx)1805 int32_t lsm6dsrx_steps_reset(stmdev_ctx_t *ctx)
1806 {
1807 lsm6dsrx_emb_func_src_t emb_func_src;
1808 int32_t ret;
1809
1810 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
1811
1812 if (ret == 0)
1813 {
1814 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_SRC,
1815 (uint8_t *)&emb_func_src, 1);
1816 }
1817
1818 if (ret == 0)
1819 {
1820 emb_func_src.pedo_rst_step = PROPERTY_ENABLE;
1821 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_SRC,
1822 (uint8_t *)&emb_func_src, 1);
1823 }
1824
1825 if (ret == 0)
1826 {
1827 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
1828 }
1829
1830 return ret;
1831 }
1832
1833 /**
1834 * @}
1835 *
1836 */
1837
1838 /**
1839 * @defgroup LSM6DSRX_common
1840 * @brief This section groups common useful functions.
1841 * @{
1842 *
1843 */
1844
1845 /**
1846 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1847 * with respect to the typical.[set]
1848 * Step: 0.15%. 8-bit format, 2's complement.
1849 *
1850 * @param ctx Read / write interface definitions.(ptr)
1851 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1852 * @retval Interface status (MANDATORY: return 0 -> no Error).
1853 *
1854 */
lsm6dsrx_odr_cal_reg_set(stmdev_ctx_t * ctx,uint8_t val)1855 int32_t lsm6dsrx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
1856 {
1857 lsm6dsrx_internal_freq_fine_t internal_freq_fine;
1858 int32_t ret;
1859
1860 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INTERNAL_FREQ_FINE,
1861 (uint8_t *)&internal_freq_fine, 1);
1862
1863 if (ret == 0)
1864 {
1865 internal_freq_fine.freq_fine = (uint8_t)val;
1866 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INTERNAL_FREQ_FINE,
1867 (uint8_t *)&internal_freq_fine, 1);
1868 }
1869
1870 return ret;
1871 }
1872
1873 /**
1874 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1875 * with respect to the typical.[get]
1876 * Step: 0.15%. 8-bit format, 2's complement.
1877 *
1878 * @param ctx Read / write interface definitions.(ptr)
1879 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1880 * @retval Interface status (MANDATORY: return 0 -> no Error).
1881 *
1882 */
lsm6dsrx_odr_cal_reg_get(stmdev_ctx_t * ctx,uint8_t * val)1883 int32_t lsm6dsrx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
1884 {
1885 lsm6dsrx_internal_freq_fine_t internal_freq_fine;
1886 int32_t ret;
1887
1888 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INTERNAL_FREQ_FINE,
1889 (uint8_t *)&internal_freq_fine, 1);
1890 *val = internal_freq_fine.freq_fine;
1891
1892 return ret;
1893 }
1894
1895 /**
1896 * @brief Enable access to the embedded functions/sensor hub configuration
1897 * registers.[set]
1898 *
1899 * @param ctx Read / write interface definitions.(ptr)
1900 * @param val Change the values of reg_access in reg FUNC_CFG_ACCESS
1901 * @retval Interface status (MANDATORY: return 0 -> no Error).
1902 *
1903 */
lsm6dsrx_mem_bank_set(stmdev_ctx_t * ctx,lsm6dsrx_reg_access_t val)1904 int32_t lsm6dsrx_mem_bank_set(stmdev_ctx_t *ctx,
1905 lsm6dsrx_reg_access_t val)
1906 {
1907 lsm6dsrx_func_cfg_access_t func_cfg_access;
1908 int32_t ret;
1909
1910 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FUNC_CFG_ACCESS,
1911 (uint8_t *)&func_cfg_access, 1);
1912
1913 if (ret == 0)
1914 {
1915 func_cfg_access.reg_access = (uint8_t)val;
1916 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FUNC_CFG_ACCESS,
1917 (uint8_t *)&func_cfg_access, 1);
1918 }
1919
1920 return ret;
1921 }
1922
1923 /**
1924 * @brief Enable access to the embedded functions/sensor hub configuration
1925 * registers.[get]
1926 *
1927 * @param ctx Read / write interface definitions.(ptr)
1928 * @param val Get the values of reg_access in reg FUNC_CFG_ACCESS
1929 * @retval Interface status (MANDATORY: return 0 -> no Error).
1930 *
1931 */
lsm6dsrx_mem_bank_get(stmdev_ctx_t * ctx,lsm6dsrx_reg_access_t * val)1932 int32_t lsm6dsrx_mem_bank_get(stmdev_ctx_t *ctx,
1933 lsm6dsrx_reg_access_t *val)
1934 {
1935 lsm6dsrx_func_cfg_access_t func_cfg_access;
1936 int32_t ret;
1937
1938 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FUNC_CFG_ACCESS,
1939 (uint8_t *)&func_cfg_access, 1);
1940
1941 switch (func_cfg_access.reg_access)
1942 {
1943 case LSM6DSRX_USER_BANK:
1944 *val = LSM6DSRX_USER_BANK;
1945 break;
1946
1947 case LSM6DSRX_SENSOR_HUB_BANK:
1948 *val = LSM6DSRX_SENSOR_HUB_BANK;
1949 break;
1950
1951 case LSM6DSRX_EMBEDDED_FUNC_BANK:
1952 *val = LSM6DSRX_EMBEDDED_FUNC_BANK;
1953 break;
1954
1955 default:
1956 *val = LSM6DSRX_USER_BANK;
1957 break;
1958 }
1959
1960 return ret;
1961 }
1962
1963 /**
1964 * @brief Write a line(byte) in a page.[set]
1965 *
1966 * @param ctx Read / write interface definitions.(ptr)
1967 * @param add Page line address
1968 * @param val Value to write
1969 * @retval Interface status (MANDATORY: return 0 -> no Error).
1970 *
1971 */
lsm6dsrx_ln_pg_write_byte(stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)1972 int32_t lsm6dsrx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add,
1973 uint8_t *val)
1974 {
1975 lsm6dsrx_page_rw_t page_rw;
1976 lsm6dsrx_page_sel_t page_sel;
1977 lsm6dsrx_page_address_t page_address;
1978 int32_t ret;
1979
1980 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
1981
1982 if (ret == 0)
1983 {
1984 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
1985 }
1986
1987 if (ret == 0)
1988 {
1989 page_rw.page_rw = 0x02U; /* page_write enable */
1990 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
1991 }
1992
1993 if (ret == 0)
1994 {
1995 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL, (uint8_t *)&page_sel, 1);
1996 }
1997
1998 if (ret == 0)
1999 {
2000 page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
2001 page_sel.not_used_01 = 1;
2002 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL,
2003 (uint8_t *)&page_sel, 1);
2004 }
2005
2006 if (ret == 0)
2007 {
2008 page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
2009 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_ADDRESS,
2010 (uint8_t *)&page_address, 1);
2011 }
2012
2013 if (ret == 0)
2014 {
2015 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_VALUE, val, 1);
2016 }
2017
2018 if (ret == 0)
2019 {
2020 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
2021 }
2022
2023 if (ret == 0)
2024 {
2025 page_rw.page_rw = 0x00; /* page_write disable */
2026 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
2027 }
2028
2029 if (ret == 0)
2030 {
2031 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
2032 }
2033
2034 return ret;
2035 }
2036
2037 /**
2038 * @brief Write buffer in a page.[set]
2039 *
2040 * @param ctx Read / write interface definitions.(ptr)
2041 * @param buf Page line address.(ptr)
2042 * @param val Value to write.
2043 * @param len buffer length.
2044 * @retval Interface status (MANDATORY: return 0 -> no Error).
2045 *
2046 */
lsm6dsrx_ln_pg_write(stmdev_ctx_t * ctx,uint16_t add,uint8_t * buf,uint8_t len)2047 int32_t lsm6dsrx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add,
2048 uint8_t *buf, uint8_t len)
2049 {
2050 lsm6dsrx_page_rw_t page_rw;
2051 lsm6dsrx_page_sel_t page_sel;
2052 lsm6dsrx_page_address_t page_address;
2053 int32_t ret;
2054
2055 uint8_t msb, lsb;
2056 uint8_t i ;
2057 msb = (uint8_t)(add / 256U);
2058 lsb = (uint8_t)(add - (msb * 256U));
2059 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
2060
2061 if (ret == 0)
2062 {
2063 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
2064 }
2065
2066 if (ret == 0)
2067 {
2068 page_rw.page_rw = 0x02U; /* page_write enable*/
2069 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
2070 }
2071
2072 if (ret == 0)
2073 {
2074 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL, (uint8_t *)&page_sel, 1);
2075 }
2076
2077 if (ret == 0)
2078 {
2079 page_sel.page_sel = msb;
2080 page_sel.not_used_01 = 1;
2081 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL,
2082 (uint8_t *)&page_sel, 1);
2083 }
2084
2085 if (ret == 0)
2086 {
2087 page_address.page_addr = lsb;
2088 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_ADDRESS,
2089 (uint8_t *)&page_address, 1);
2090 }
2091
2092 for (i = 0; i < len; i++)
2093 {
2094 if (ret == 0)
2095 {
2096 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_VALUE, &buf[i], 1);
2097
2098 if (ret == 0)
2099 {
2100 /* Check if page wrap */
2101 if (lsb == 0x00U)
2102 {
2103 msb++;
2104 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL,
2105 (uint8_t *)&page_sel, 1);
2106 }
2107
2108 lsb++;
2109 }
2110
2111 if (ret == 0)
2112 {
2113 page_sel.page_sel = msb;
2114 page_sel.not_used_01 = 1;
2115 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL,
2116 (uint8_t *)&page_sel, 1);
2117 }
2118 }
2119 }
2120
2121 if (ret == 0)
2122 {
2123 page_sel.page_sel = 0;
2124 page_sel.not_used_01 = 1;
2125 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL,
2126 (uint8_t *)&page_sel, 1);
2127 }
2128
2129 if (ret == 0)
2130 {
2131 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
2132 }
2133
2134 if (ret == 0)
2135 {
2136 page_rw.page_rw = 0x00U; /* page_write disable */
2137 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
2138 }
2139
2140 if (ret == 0)
2141 {
2142 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
2143 }
2144
2145 return ret;
2146 }
2147
2148 /**
2149 * @brief Read a line(byte) in a page.[get]
2150 *
2151 * @param ctx Read / write interface definitions.(ptr)
2152 * @param add Page line address.
2153 * @param val Read value.(ptr)
2154 * @retval Interface status (MANDATORY: return 0 -> no Error).
2155 *
2156 */
lsm6dsrx_ln_pg_read_byte(stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)2157 int32_t lsm6dsrx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
2158 uint8_t *val)
2159 {
2160 lsm6dsrx_page_rw_t page_rw;
2161 lsm6dsrx_page_sel_t page_sel;
2162 lsm6dsrx_page_address_t page_address;
2163 int32_t ret;
2164
2165 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
2166
2167 if (ret == 0)
2168 {
2169 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
2170 }
2171
2172 if (ret == 0)
2173 {
2174 page_rw.page_rw = 0x01U; /* page_read enable*/
2175 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
2176 }
2177
2178 if (ret == 0)
2179 {
2180 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_SEL, (uint8_t *)&page_sel, 1);
2181 }
2182
2183 if (ret == 0)
2184 {
2185 page_sel.page_sel = (uint8_t)((add / 256U) & 0x0FU);
2186 page_sel.not_used_01 = 1;
2187 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_SEL,
2188 (uint8_t *)&page_sel, 1);
2189 }
2190
2191 if (ret == 0)
2192 {
2193 page_address.page_addr = (uint8_t)(add - (page_sel.page_sel * 256U));
2194 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_ADDRESS,
2195 (uint8_t *)&page_address, 1);
2196 }
2197
2198 if (ret == 0)
2199 {
2200 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_VALUE, val, 2);
2201 }
2202
2203 if (ret == 0)
2204 {
2205 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
2206 }
2207
2208 if (ret == 0)
2209 {
2210 page_rw.page_rw = 0x00U; /* page_read disable */
2211 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
2212 }
2213
2214 if (ret == 0)
2215 {
2216 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
2217 }
2218
2219 return ret;
2220 }
2221
2222 /**
2223 * @brief Data-ready pulsed / letched mode.[set]
2224 *
2225 * @param ctx Read / write interface definitions.(ptr)
2226 * @param val Change the values of dataready_pulsed in
2227 * reg COUNTER_BDR_REG1
2228 * @retval Interface status (MANDATORY: return 0 -> no Error).
2229 *
2230 */
lsm6dsrx_data_ready_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_dataready_pulsed_t val)2231 int32_t lsm6dsrx_data_ready_mode_set(stmdev_ctx_t *ctx,
2232 lsm6dsrx_dataready_pulsed_t val)
2233 {
2234 lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
2235 int32_t ret;
2236
2237 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
2238 (uint8_t *)&counter_bdr_reg1, 1);
2239
2240 if (ret == 0)
2241 {
2242 counter_bdr_reg1.dataready_pulsed = (uint8_t)val;
2243 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
2244 (uint8_t *)&counter_bdr_reg1, 1);
2245 }
2246
2247 return ret;
2248 }
2249
2250 /**
2251 * @brief Data-ready pulsed / letched mode.[get]
2252 *
2253 * @param ctx Read / write interface definitions.(ptr)
2254 * @param val Get the values of dataready_pulsed in
2255 * reg COUNTER_BDR_REG1
2256 * @retval Interface status (MANDATORY: return 0 -> no Error).
2257 *
2258 */
lsm6dsrx_data_ready_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_dataready_pulsed_t * val)2259 int32_t lsm6dsrx_data_ready_mode_get(stmdev_ctx_t *ctx,
2260 lsm6dsrx_dataready_pulsed_t *val)
2261 {
2262 lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
2263 int32_t ret;
2264
2265 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
2266 (uint8_t *)&counter_bdr_reg1, 1);
2267
2268 switch (counter_bdr_reg1.dataready_pulsed)
2269 {
2270 case LSM6DSRX_DRDY_LATCHED:
2271 *val = LSM6DSRX_DRDY_LATCHED;
2272 break;
2273
2274 case LSM6DSRX_DRDY_PULSED:
2275 *val = LSM6DSRX_DRDY_PULSED;
2276 break;
2277
2278 default:
2279 *val = LSM6DSRX_DRDY_LATCHED;
2280 break;
2281 }
2282
2283 return ret;
2284 }
2285
2286 /**
2287 * @brief Device Who am I.[get]
2288 *
2289 * @param ctx Read / write interface definitions.(ptr)
2290 * @param buff Buffer that stores data read
2291 * @retval Interface status (MANDATORY: return 0 -> no Error).
2292 *
2293 */
lsm6dsrx_device_id_get(stmdev_ctx_t * ctx,uint8_t * buff)2294 int32_t lsm6dsrx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
2295 {
2296 int32_t ret;
2297
2298 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WHO_AM_I, buff, 1);
2299
2300 return ret;
2301 }
2302
2303 /**
2304 * @brief Software reset. Restore the default values in user registers.[set]
2305 *
2306 * @param ctx Read / write interface definitions.(ptr)
2307 * @param val Change the values of sw_reset in reg CTRL3_C
2308 * @retval Interface status (MANDATORY: return 0 -> no Error).
2309 *
2310 */
lsm6dsrx_reset_set(stmdev_ctx_t * ctx,uint8_t val)2311 int32_t lsm6dsrx_reset_set(stmdev_ctx_t *ctx, uint8_t val)
2312 {
2313 lsm6dsrx_ctrl3_c_t ctrl3_c;
2314 int32_t ret;
2315
2316 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2317
2318 if (ret == 0)
2319 {
2320 ctrl3_c.sw_reset = (uint8_t)val;
2321 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2322 }
2323
2324 return ret;
2325 }
2326
2327 /**
2328 * @brief Software reset. Restore the default values in user registers.[get]
2329 *
2330 * @param ctx Read / write interface definitions.(ptr)
2331 * @param val Change the values of sw_reset in reg CTRL3_C
2332 * @retval Interface status (MANDATORY: return 0 -> no Error).
2333 *
2334 */
lsm6dsrx_reset_get(stmdev_ctx_t * ctx,uint8_t * val)2335 int32_t lsm6dsrx_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
2336 {
2337 lsm6dsrx_ctrl3_c_t ctrl3_c;
2338 int32_t ret;
2339
2340 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2341 *val = ctrl3_c.sw_reset;
2342
2343 return ret;
2344 }
2345
2346 /**
2347 * @brief Register address automatically incremented during a multiple byte
2348 * access with a serial interface.[set]
2349 *
2350 * @param ctx Read / write interface definitions.(ptr)
2351 * @param val Change the values of if_inc in reg CTRL3_C
2352 * @retval Interface status (MANDATORY: return 0 -> no Error).
2353 *
2354 */
lsm6dsrx_auto_increment_set(stmdev_ctx_t * ctx,uint8_t val)2355 int32_t lsm6dsrx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
2356 {
2357 lsm6dsrx_ctrl3_c_t ctrl3_c;
2358 int32_t ret;
2359
2360 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2361
2362 if (ret == 0)
2363 {
2364 ctrl3_c.if_inc = (uint8_t)val;
2365 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2366 }
2367
2368 return ret;
2369 }
2370
2371 /**
2372 * @brief Register address automatically incremented during a multiple byte
2373 * access with a serial interface.[get]
2374 *
2375 * @param ctx Read / write interface definitions.(ptr)
2376 * @param val Change the values of if_inc in reg CTRL3_C
2377 * @retval Interface status (MANDATORY: return 0 -> no Error).
2378 *
2379 */
lsm6dsrx_auto_increment_get(stmdev_ctx_t * ctx,uint8_t * val)2380 int32_t lsm6dsrx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
2381 {
2382 lsm6dsrx_ctrl3_c_t ctrl3_c;
2383 int32_t ret;
2384
2385 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2386 *val = ctrl3_c.if_inc;
2387
2388 return ret;
2389 }
2390
2391 /**
2392 * @brief Reboot memory content. Reload the calibration parameters.[set]
2393 *
2394 * @param ctx Read / write interface definitions.(ptr)
2395 * @param val Change the values of boot in reg CTRL3_C
2396 * @retval Interface status (MANDATORY: return 0 -> no Error).
2397 *
2398 */
lsm6dsrx_boot_set(stmdev_ctx_t * ctx,uint8_t val)2399 int32_t lsm6dsrx_boot_set(stmdev_ctx_t *ctx, uint8_t val)
2400 {
2401 lsm6dsrx_ctrl3_c_t ctrl3_c;
2402 int32_t ret;
2403
2404 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2405
2406 if (ret == 0)
2407 {
2408 ctrl3_c.boot = (uint8_t)val;
2409 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2410 }
2411
2412 return ret;
2413 }
2414
2415 /**
2416 * @brief Reboot memory content. Reload the calibration parameters.[get]
2417 *
2418 * @param ctx Read / write interface definitions.(ptr)
2419 * @param val Change the values of boot in reg CTRL3_C
2420 * @retval Interface status (MANDATORY: return 0 -> no Error).
2421 *
2422 */
lsm6dsrx_boot_get(stmdev_ctx_t * ctx,uint8_t * val)2423 int32_t lsm6dsrx_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
2424 {
2425 lsm6dsrx_ctrl3_c_t ctrl3_c;
2426 int32_t ret;
2427
2428 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2429 *val = ctrl3_c.boot;
2430
2431 return ret;
2432 }
2433
2434
2435
2436 /**
2437 * @brief Linear acceleration sensor self-test enable.[set]
2438 *
2439 * @param ctx Read / write interface definitions.(ptr)
2440 * @param val Change the values of st_xl in reg CTRL5_C
2441 * @retval Interface status (MANDATORY: return 0 -> no Error).
2442 *
2443 */
lsm6dsrx_xl_self_test_set(stmdev_ctx_t * ctx,lsm6dsrx_st_xl_t val)2444 int32_t lsm6dsrx_xl_self_test_set(stmdev_ctx_t *ctx,
2445 lsm6dsrx_st_xl_t val)
2446 {
2447 lsm6dsrx_ctrl5_c_t ctrl5_c;
2448 int32_t ret;
2449
2450 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2451
2452 if (ret == 0)
2453 {
2454 ctrl5_c.st_xl = (uint8_t)val;
2455 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2456 }
2457
2458 return ret;
2459 }
2460
2461 /**
2462 * @brief Linear acceleration sensor self-test enable.[get]
2463 *
2464 * @param ctx Read / write interface definitions.(ptr)
2465 * @param val Get the values of st_xl in reg CTRL5_C
2466 * @retval Interface status (MANDATORY: return 0 -> no Error).
2467 *
2468 */
lsm6dsrx_xl_self_test_get(stmdev_ctx_t * ctx,lsm6dsrx_st_xl_t * val)2469 int32_t lsm6dsrx_xl_self_test_get(stmdev_ctx_t *ctx,
2470 lsm6dsrx_st_xl_t *val)
2471 {
2472 lsm6dsrx_ctrl5_c_t ctrl5_c;
2473 int32_t ret;
2474
2475 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2476
2477 switch (ctrl5_c.st_xl)
2478 {
2479 case LSM6DSRX_XL_ST_DISABLE:
2480 *val = LSM6DSRX_XL_ST_DISABLE;
2481 break;
2482
2483 case LSM6DSRX_XL_ST_POSITIVE:
2484 *val = LSM6DSRX_XL_ST_POSITIVE;
2485 break;
2486
2487 case LSM6DSRX_XL_ST_NEGATIVE:
2488 *val = LSM6DSRX_XL_ST_NEGATIVE;
2489 break;
2490
2491 default:
2492 *val = LSM6DSRX_XL_ST_DISABLE;
2493 break;
2494 }
2495
2496 return ret;
2497 }
2498
2499 /**
2500 * @brief Angular rate sensor self-test enable.[set]
2501 *
2502 * @param ctx Read / write interface definitions.(ptr)
2503 * @param val Change the values of st_g in reg CTRL5_C
2504 * @retval Interface status (MANDATORY: return 0 -> no Error).
2505 *
2506 */
lsm6dsrx_gy_self_test_set(stmdev_ctx_t * ctx,lsm6dsrx_st_g_t val)2507 int32_t lsm6dsrx_gy_self_test_set(stmdev_ctx_t *ctx,
2508 lsm6dsrx_st_g_t val)
2509 {
2510 lsm6dsrx_ctrl5_c_t ctrl5_c;
2511 int32_t ret;
2512
2513 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2514
2515 if (ret == 0)
2516 {
2517 ctrl5_c.st_g = (uint8_t)val;
2518 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2519 }
2520
2521 return ret;
2522 }
2523
2524 /**
2525 * @brief Angular rate sensor self-test enable.[get]
2526 *
2527 * @param ctx Read / write interface definitions.(ptr)
2528 * @param val Get the values of st_g in reg CTRL5_C
2529 * @retval Interface status (MANDATORY: return 0 -> no Error).
2530 *
2531 */
lsm6dsrx_gy_self_test_get(stmdev_ctx_t * ctx,lsm6dsrx_st_g_t * val)2532 int32_t lsm6dsrx_gy_self_test_get(stmdev_ctx_t *ctx,
2533 lsm6dsrx_st_g_t *val)
2534 {
2535 lsm6dsrx_ctrl5_c_t ctrl5_c;
2536 int32_t ret;
2537
2538 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2539
2540 switch (ctrl5_c.st_g)
2541 {
2542 case LSM6DSRX_GY_ST_DISABLE:
2543 *val = LSM6DSRX_GY_ST_DISABLE;
2544 break;
2545
2546 case LSM6DSRX_GY_ST_POSITIVE:
2547 *val = LSM6DSRX_GY_ST_POSITIVE;
2548 break;
2549
2550 case LSM6DSRX_GY_ST_NEGATIVE:
2551 *val = LSM6DSRX_GY_ST_NEGATIVE;
2552 break;
2553
2554 default:
2555 *val = LSM6DSRX_GY_ST_DISABLE;
2556 break;
2557 }
2558
2559 return ret;
2560 }
2561
2562 /**
2563 * @}
2564 *
2565 */
2566
2567 /**
2568 * @defgroup LSM6DSRX_filters
2569 * @brief This section group all the functions concerning the
2570 * filters configuration
2571 * @{
2572 *
2573 */
2574
2575 /**
2576 * @brief Accelerometer output from LPF2 filtering stage selection.[set]
2577 *
2578 * @param ctx Read / write interface definitions.(ptr)
2579 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
2580 * @retval Interface status (MANDATORY: return 0 -> no Error).
2581 *
2582 */
lsm6dsrx_xl_filter_lp2_set(stmdev_ctx_t * ctx,uint8_t val)2583 int32_t lsm6dsrx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
2584 {
2585 lsm6dsrx_ctrl1_xl_t ctrl1_xl;
2586 int32_t ret;
2587
2588 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2589
2590 if (ret == 0)
2591 {
2592 ctrl1_xl.lpf2_xl_en = (uint8_t)val;
2593 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_XL,
2594 (uint8_t *)&ctrl1_xl, 1);
2595 }
2596
2597 return ret;
2598 }
2599
2600 /**
2601 * @brief Accelerometer output from LPF2 filtering stage selection.[get]
2602 *
2603 * @param ctx Read / write interface definitions.(ptr)
2604 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
2605 * @retval Interface status (MANDATORY: return 0 -> no Error).
2606 *
2607 */
lsm6dsrx_xl_filter_lp2_get(stmdev_ctx_t * ctx,uint8_t * val)2608 int32_t lsm6dsrx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
2609 {
2610 lsm6dsrx_ctrl1_xl_t ctrl1_xl;
2611 int32_t ret;
2612
2613 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2614 *val = ctrl1_xl.lpf2_xl_en;
2615
2616 return ret;
2617 }
2618
2619 /**
2620 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2621 * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[set]
2622 *
2623 * @param ctx Read / write interface definitions.(ptr)
2624 * @param val Change the values of lpf1_sel_g in reg CTRL4_C
2625 * @retval Interface status (MANDATORY: return 0 -> no Error).
2626 *
2627 */
lsm6dsrx_gy_filter_lp1_set(stmdev_ctx_t * ctx,uint8_t val)2628 int32_t lsm6dsrx_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
2629 {
2630 lsm6dsrx_ctrl4_c_t ctrl4_c;
2631 int32_t ret;
2632
2633 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2634
2635 if (ret == 0)
2636 {
2637 ctrl4_c.lpf1_sel_g = (uint8_t)val;
2638 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2639 }
2640
2641 return ret;
2642 }
2643
2644 /**
2645 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2646 * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[get]
2647 *
2648 * @param ctx Read / write interface definitions.(ptr)
2649 * @param val Change the values of lpf1_sel_g in reg CTRL4_C
2650 * @retval Interface status (MANDATORY: return 0 -> no Error).
2651 *
2652 */
lsm6dsrx_gy_filter_lp1_get(stmdev_ctx_t * ctx,uint8_t * val)2653 int32_t lsm6dsrx_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
2654 {
2655 lsm6dsrx_ctrl4_c_t ctrl4_c;
2656 int32_t ret;
2657
2658 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2659 *val = ctrl4_c.lpf1_sel_g;
2660
2661 return ret;
2662 }
2663
2664 /**
2665 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2666 * (XL and Gyro independently masked).[set]
2667 *
2668 * @param ctx Read / write interface definitions.(ptr)
2669 * @param val Change the values of drdy_mask in reg CTRL4_C
2670 * @retval Interface status (MANDATORY: return 0 -> no Error).
2671 *
2672 */
lsm6dsrx_filter_settling_mask_set(stmdev_ctx_t * ctx,uint8_t val)2673 int32_t lsm6dsrx_filter_settling_mask_set(stmdev_ctx_t *ctx,
2674 uint8_t val)
2675 {
2676 lsm6dsrx_ctrl4_c_t ctrl4_c;
2677 int32_t ret;
2678
2679 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2680
2681 if (ret == 0)
2682 {
2683 ctrl4_c.drdy_mask = (uint8_t)val;
2684 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2685 }
2686
2687 return ret;
2688 }
2689
2690 /**
2691 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2692 * (XL and Gyro independently masked).[get]
2693 *
2694 * @param ctx Read / write interface definitions.(ptr)
2695 * @param val Change the values of drdy_mask in reg CTRL4_C
2696 * @retval Interface status (MANDATORY: return 0 -> no Error).
2697 *
2698 */
lsm6dsrx_filter_settling_mask_get(stmdev_ctx_t * ctx,uint8_t * val)2699 int32_t lsm6dsrx_filter_settling_mask_get(stmdev_ctx_t *ctx,
2700 uint8_t *val)
2701 {
2702 lsm6dsrx_ctrl4_c_t ctrl4_c;
2703 int32_t ret;
2704
2705 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2706 *val = ctrl4_c.drdy_mask;
2707
2708 return ret;
2709 }
2710
2711 /**
2712 * @brief Gyroscope low pass filter 1 bandwidth.[set]
2713 *
2714 * @param ctx Read / write interface definitions.(ptr)
2715 * @param val Change the values of ftype in reg CTRL6_C
2716 * @retval Interface status (MANDATORY: return 0 -> no Error).
2717 *
2718 */
lsm6dsrx_gy_lp1_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsrx_ftype_t val)2719 int32_t lsm6dsrx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
2720 lsm6dsrx_ftype_t val)
2721 {
2722 lsm6dsrx_ctrl6_c_t ctrl6_c;
2723 int32_t ret;
2724
2725 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2726
2727 if (ret == 0)
2728 {
2729 ctrl6_c.ftype = (uint8_t)val;
2730 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2731 }
2732
2733 return ret;
2734 }
2735
2736 /**
2737 * @brief Gyroscope low pass filter 1 bandwidth.[get]
2738 *
2739 * @param ctx Read / write interface definitions.(ptr)
2740 * @param val Get the values of ftype in reg CTRL6_C
2741 * @retval Interface status (MANDATORY: return 0 -> no Error).
2742 *
2743 */
lsm6dsrx_gy_lp1_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsrx_ftype_t * val)2744 int32_t lsm6dsrx_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
2745 lsm6dsrx_ftype_t *val)
2746 {
2747 lsm6dsrx_ctrl6_c_t ctrl6_c;
2748 int32_t ret;
2749
2750 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2751
2752 switch (ctrl6_c.ftype)
2753 {
2754 case LSM6DSRX_ULTRA_LIGHT:
2755 *val = LSM6DSRX_ULTRA_LIGHT;
2756 break;
2757
2758 case LSM6DSRX_VERY_LIGHT:
2759 *val = LSM6DSRX_VERY_LIGHT;
2760 break;
2761
2762 case LSM6DSRX_LIGHT:
2763 *val = LSM6DSRX_LIGHT;
2764 break;
2765
2766 case LSM6DSRX_MEDIUM:
2767 *val = LSM6DSRX_MEDIUM;
2768 break;
2769
2770 case LSM6DSRX_STRONG:
2771 *val = LSM6DSRX_STRONG;
2772 break;
2773
2774 case LSM6DSRX_VERY_STRONG:
2775 *val = LSM6DSRX_VERY_STRONG;
2776 break;
2777
2778 case LSM6DSRX_AGGRESSIVE:
2779 *val = LSM6DSRX_AGGRESSIVE;
2780 break;
2781
2782 case LSM6DSRX_XTREME:
2783 *val = LSM6DSRX_XTREME;
2784 break;
2785
2786 default:
2787 *val = LSM6DSRX_ULTRA_LIGHT;
2788 break;
2789 }
2790
2791 return ret;
2792 }
2793
2794 /**
2795 * @brief Low pass filter 2 on 6D function selection.[set]
2796 *
2797 * @param ctx Read / write interface definitions.(ptr)
2798 * @param val Change the values of low_pass_on_6d in reg CTRL8_XL
2799 * @retval Interface status (MANDATORY: return 0 -> no Error).
2800 *
2801 */
lsm6dsrx_xl_lp2_on_6d_set(stmdev_ctx_t * ctx,uint8_t val)2802 int32_t lsm6dsrx_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
2803 {
2804 lsm6dsrx_ctrl8_xl_t ctrl8_xl;
2805 int32_t ret;
2806
2807 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2808
2809 if (ret == 0)
2810 {
2811 ctrl8_xl.low_pass_on_6d = (uint8_t)val;
2812 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL8_XL,
2813 (uint8_t *)&ctrl8_xl, 1);
2814 }
2815
2816 return ret;
2817 }
2818
2819 /**
2820 * @brief Low pass filter 2 on 6D function selection.[get]
2821 *
2822 * @param ctx Read / write interface definitions.(ptr)
2823 * @param val Change the values of low_pass_on_6d in reg CTRL8_XL
2824 * @retval Interface status (MANDATORY: return 0 -> no Error).
2825 *
2826 */
lsm6dsrx_xl_lp2_on_6d_get(stmdev_ctx_t * ctx,uint8_t * val)2827 int32_t lsm6dsrx_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
2828 {
2829 lsm6dsrx_ctrl8_xl_t ctrl8_xl;
2830 int32_t ret;
2831
2832 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2833 *val = ctrl8_xl.low_pass_on_6d;
2834
2835 return ret;
2836 }
2837
2838 /**
2839 * @brief Accelerometer slope filter / high-pass filter selection
2840 * on output.[set]
2841 *
2842 * @param ctx Read / write interface definitions.(ptr)
2843 * @param val Change the values of hp_slope_xl_en in reg CTRL8_XL
2844 * @retval Interface status (MANDATORY: return 0 -> no Error).
2845 *
2846 */
lsm6dsrx_xl_hp_path_on_out_set(stmdev_ctx_t * ctx,lsm6dsrx_hp_slope_xl_en_t val)2847 int32_t lsm6dsrx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
2848 lsm6dsrx_hp_slope_xl_en_t val)
2849 {
2850 lsm6dsrx_ctrl8_xl_t ctrl8_xl;
2851 int32_t ret;
2852
2853 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2854
2855 if (ret == 0)
2856 {
2857 ctrl8_xl.hp_slope_xl_en = (((uint8_t)val & 0x10U) >> 4);
2858 ctrl8_xl.hp_ref_mode_xl = (((uint8_t)val & 0x20U) >> 5);
2859 ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U;
2860 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL8_XL,
2861 (uint8_t *)&ctrl8_xl, 1);
2862 }
2863
2864 return ret;
2865 }
2866
2867 /**
2868 * @brief Accelerometer slope filter / high-pass filter selection on
2869 * output.[get]
2870 *
2871 * @param ctx Read / write interface definitions.(ptr)
2872 * @param val Get the values of hp_slope_xl_en in reg CTRL8_XL
2873 * @retval Interface status (MANDATORY: return 0 -> no Error).
2874 *
2875 */
lsm6dsrx_xl_hp_path_on_out_get(stmdev_ctx_t * ctx,lsm6dsrx_hp_slope_xl_en_t * val)2876 int32_t lsm6dsrx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
2877 lsm6dsrx_hp_slope_xl_en_t *val)
2878 {
2879 lsm6dsrx_ctrl8_xl_t ctrl8_xl;
2880 int32_t ret;
2881
2882 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2883
2884 switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en <<
2885 4) +
2886 ctrl8_xl.hpcf_xl))
2887 {
2888 case LSM6DSRX_HP_PATH_DISABLE_ON_OUT:
2889 *val = LSM6DSRX_HP_PATH_DISABLE_ON_OUT;
2890 break;
2891
2892 case LSM6DSRX_SLOPE_ODR_DIV_4:
2893 *val = LSM6DSRX_SLOPE_ODR_DIV_4;
2894 break;
2895
2896 case LSM6DSRX_HP_ODR_DIV_10:
2897 *val = LSM6DSRX_HP_ODR_DIV_10;
2898 break;
2899
2900 case LSM6DSRX_HP_ODR_DIV_20:
2901 *val = LSM6DSRX_HP_ODR_DIV_20;
2902 break;
2903
2904 case LSM6DSRX_HP_ODR_DIV_45:
2905 *val = LSM6DSRX_HP_ODR_DIV_45;
2906 break;
2907
2908 case LSM6DSRX_HP_ODR_DIV_100:
2909 *val = LSM6DSRX_HP_ODR_DIV_100;
2910 break;
2911
2912 case LSM6DSRX_HP_ODR_DIV_200:
2913 *val = LSM6DSRX_HP_ODR_DIV_200;
2914 break;
2915
2916 case LSM6DSRX_HP_ODR_DIV_400:
2917 *val = LSM6DSRX_HP_ODR_DIV_400;
2918 break;
2919
2920 case LSM6DSRX_HP_ODR_DIV_800:
2921 *val = LSM6DSRX_HP_ODR_DIV_800;
2922 break;
2923
2924 case LSM6DSRX_HP_REF_MD_ODR_DIV_10:
2925 *val = LSM6DSRX_HP_REF_MD_ODR_DIV_10;
2926 break;
2927
2928 case LSM6DSRX_HP_REF_MD_ODR_DIV_20:
2929 *val = LSM6DSRX_HP_REF_MD_ODR_DIV_20;
2930 break;
2931
2932 case LSM6DSRX_HP_REF_MD_ODR_DIV_45:
2933 *val = LSM6DSRX_HP_REF_MD_ODR_DIV_45;
2934 break;
2935
2936 case LSM6DSRX_HP_REF_MD_ODR_DIV_100:
2937 *val = LSM6DSRX_HP_REF_MD_ODR_DIV_100;
2938 break;
2939
2940 case LSM6DSRX_HP_REF_MD_ODR_DIV_200:
2941 *val = LSM6DSRX_HP_REF_MD_ODR_DIV_200;
2942 break;
2943
2944 case LSM6DSRX_HP_REF_MD_ODR_DIV_400:
2945 *val = LSM6DSRX_HP_REF_MD_ODR_DIV_400;
2946 break;
2947
2948 case LSM6DSRX_HP_REF_MD_ODR_DIV_800:
2949 *val = LSM6DSRX_HP_REF_MD_ODR_DIV_800;
2950 break;
2951
2952 case LSM6DSRX_LP_ODR_DIV_10:
2953 *val = LSM6DSRX_LP_ODR_DIV_10;
2954 break;
2955
2956 case LSM6DSRX_LP_ODR_DIV_20:
2957 *val = LSM6DSRX_LP_ODR_DIV_20;
2958 break;
2959
2960 case LSM6DSRX_LP_ODR_DIV_45:
2961 *val = LSM6DSRX_LP_ODR_DIV_45;
2962 break;
2963
2964 case LSM6DSRX_LP_ODR_DIV_100:
2965 *val = LSM6DSRX_LP_ODR_DIV_100;
2966 break;
2967
2968 case LSM6DSRX_LP_ODR_DIV_200:
2969 *val = LSM6DSRX_LP_ODR_DIV_200;
2970 break;
2971
2972 case LSM6DSRX_LP_ODR_DIV_400:
2973 *val = LSM6DSRX_LP_ODR_DIV_400;
2974 break;
2975
2976 case LSM6DSRX_LP_ODR_DIV_800:
2977 *val = LSM6DSRX_LP_ODR_DIV_800;
2978 break;
2979
2980 default:
2981 *val = LSM6DSRX_HP_PATH_DISABLE_ON_OUT;
2982 break;
2983 }
2984
2985 return ret;
2986 }
2987
2988 /**
2989 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2990 * The filter sets the second samples after writing this bit.
2991 * Active only during device exit from powerdown mode.[set]
2992 *
2993 * @param ctx Read / write interface definitions.(ptr)
2994 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
2995 * @retval Interface status (MANDATORY: return 0 -> no Error).
2996 *
2997 */
lsm6dsrx_xl_fast_settling_set(stmdev_ctx_t * ctx,uint8_t val)2998 int32_t lsm6dsrx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
2999 {
3000 lsm6dsrx_ctrl8_xl_t ctrl8_xl;
3001 int32_t ret;
3002
3003 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
3004
3005 if (ret == 0)
3006 {
3007 ctrl8_xl.fastsettl_mode_xl = (uint8_t)val;
3008 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL8_XL,
3009 (uint8_t *)&ctrl8_xl, 1);
3010 }
3011
3012 return ret;
3013 }
3014
3015 /**
3016 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
3017 * The filter sets the second samples after writing
3018 * this bit. Active only during device exit from powerdown mode.[get]
3019 *
3020 * @param ctx Read / write interface definitions.(ptr)
3021 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
3022 * @retval Interface status (MANDATORY: return 0 -> no Error).
3023 *
3024 */
lsm6dsrx_xl_fast_settling_get(stmdev_ctx_t * ctx,uint8_t * val)3025 int32_t lsm6dsrx_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
3026 {
3027 lsm6dsrx_ctrl8_xl_t ctrl8_xl;
3028 int32_t ret;
3029
3030 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
3031 *val = ctrl8_xl.fastsettl_mode_xl;
3032
3033 return ret;
3034 }
3035
3036 /**
3037 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
3038 * functions.[set]
3039 *
3040 * @param ctx Read / write interface definitions.(ptr)
3041 * @param val Change the values of slope_fds in reg TAP_CFG0
3042 * @retval Interface status (MANDATORY: return 0 -> no Error).
3043 *
3044 */
lsm6dsrx_xl_hp_path_internal_set(stmdev_ctx_t * ctx,lsm6dsrx_slope_fds_t val)3045 int32_t lsm6dsrx_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
3046 lsm6dsrx_slope_fds_t val)
3047 {
3048 lsm6dsrx_tap_cfg0_t tap_cfg0;
3049 int32_t ret;
3050
3051 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3052
3053 if (ret == 0)
3054 {
3055 tap_cfg0.slope_fds = (uint8_t)val;
3056 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG0,
3057 (uint8_t *)&tap_cfg0, 1);
3058 }
3059
3060 return ret;
3061 }
3062
3063 /**
3064 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
3065 * functions.[get]
3066 *
3067 * @param ctx Read / write interface definitions.(ptr)
3068 * @param val Get the values of slope_fds in reg TAP_CFG0
3069 * @retval Interface status (MANDATORY: return 0 -> no Error).
3070 *
3071 */
lsm6dsrx_xl_hp_path_internal_get(stmdev_ctx_t * ctx,lsm6dsrx_slope_fds_t * val)3072 int32_t lsm6dsrx_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
3073 lsm6dsrx_slope_fds_t *val)
3074 {
3075 lsm6dsrx_tap_cfg0_t tap_cfg0;
3076 int32_t ret;
3077
3078 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
3079
3080 switch (tap_cfg0.slope_fds)
3081 {
3082 case LSM6DSRX_USE_SLOPE:
3083 *val = LSM6DSRX_USE_SLOPE;
3084 break;
3085
3086 case LSM6DSRX_USE_HPF:
3087 *val = LSM6DSRX_USE_HPF;
3088 break;
3089
3090 default:
3091 *val = LSM6DSRX_USE_SLOPE;
3092 break;
3093 }
3094
3095 return ret;
3096 }
3097
3098 /**
3099 * @brief Enables gyroscope digital high-pass filter. The filter is enabled
3100 * only if the gyro is in HP mode.[set]
3101 *
3102 * @param ctx Read / write interface definitions.(ptr)
3103 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
3104 * @retval Interface status (MANDATORY: return 0 -> no Error).
3105 *
3106 */
lsm6dsrx_gy_hp_path_internal_set(stmdev_ctx_t * ctx,lsm6dsrx_hpm_g_t val)3107 int32_t lsm6dsrx_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
3108 lsm6dsrx_hpm_g_t val)
3109 {
3110 lsm6dsrx_ctrl7_g_t ctrl7_g;
3111 int32_t ret;
3112
3113 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
3114
3115 if (ret == 0)
3116 {
3117 ctrl7_g.hp_en_g = (((uint8_t)val & 0x80U) >> 7);
3118 ctrl7_g.hpm_g = (uint8_t)val & 0x03U;
3119 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
3120 }
3121
3122 return ret;
3123 }
3124
3125 /**
3126 * @brief Enables gyroscope digital high-pass filter. The filter is
3127 * enabled only if the gyro is in HP mode.[get]
3128 *
3129 * @param ctx Read / write interface definitions.(ptr)
3130 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
3131 * @retval Interface status (MANDATORY: return 0 -> no Error).
3132 *
3133 */
lsm6dsrx_gy_hp_path_internal_get(stmdev_ctx_t * ctx,lsm6dsrx_hpm_g_t * val)3134 int32_t lsm6dsrx_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
3135 lsm6dsrx_hpm_g_t *val)
3136 {
3137 lsm6dsrx_ctrl7_g_t ctrl7_g;
3138 int32_t ret;
3139
3140 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
3141
3142 switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g)
3143 {
3144 case LSM6DSRX_HP_FILTER_NONE:
3145 *val = LSM6DSRX_HP_FILTER_NONE;
3146 break;
3147
3148 case LSM6DSRX_HP_FILTER_16mHz:
3149 *val = LSM6DSRX_HP_FILTER_16mHz;
3150 break;
3151
3152 case LSM6DSRX_HP_FILTER_65mHz:
3153 *val = LSM6DSRX_HP_FILTER_65mHz;
3154 break;
3155
3156 case LSM6DSRX_HP_FILTER_260mHz:
3157 *val = LSM6DSRX_HP_FILTER_260mHz;
3158 break;
3159
3160 case LSM6DSRX_HP_FILTER_1Hz04:
3161 *val = LSM6DSRX_HP_FILTER_1Hz04;
3162 break;
3163
3164 default:
3165 *val = LSM6DSRX_HP_FILTER_NONE;
3166 break;
3167 }
3168
3169 return ret;
3170 }
3171
3172 /**
3173 * @}
3174 *
3175 */
3176
3177 /**
3178 * @defgroup LSM6DSRX_ Auxiliary_interface
3179 * @brief This section groups all the functions concerning
3180 * auxiliary interface.
3181 * @{
3182 *
3183 */
3184
3185 /**
3186 * @brief On auxiliary interface connect/disconnect SDO and OCS
3187 * internal pull-up.[set]
3188 *
3189 * @param ctx Read / write interface definitions.(ptr)
3190 * @param val Change the values of ois_pu_dis in reg PIN_CTRL
3191 * @retval Interface status (MANDATORY: return 0 -> no Error).
3192 *
3193 */
lsm6dsrx_aux_sdo_ocs_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_ois_pu_dis_t val)3194 int32_t lsm6dsrx_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
3195 lsm6dsrx_ois_pu_dis_t val)
3196 {
3197 lsm6dsrx_pin_ctrl_t pin_ctrl;
3198 int32_t ret;
3199
3200 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
3201
3202 if (ret == 0)
3203 {
3204 pin_ctrl.ois_pu_dis = (uint8_t)val;
3205 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PIN_CTRL,
3206 (uint8_t *)&pin_ctrl, 1);
3207 }
3208
3209 return ret;
3210 }
3211
3212 /**
3213 * @brief On auxiliary interface connect/disconnect SDO and OCS
3214 * internal pull-up.[get]
3215 *
3216 * @param ctx Read / write interface definitions.(ptr)
3217 * @param val Get the values of ois_pu_dis in reg PIN_CTRL
3218 * @retval Interface status (MANDATORY: return 0 -> no Error).
3219 *
3220 */
lsm6dsrx_aux_sdo_ocs_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_ois_pu_dis_t * val)3221 int32_t lsm6dsrx_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
3222 lsm6dsrx_ois_pu_dis_t *val)
3223 {
3224 lsm6dsrx_pin_ctrl_t pin_ctrl;
3225 int32_t ret;
3226
3227 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
3228
3229 switch (pin_ctrl.ois_pu_dis)
3230 {
3231 case LSM6DSRX_AUX_PULL_UP_DISC:
3232 *val = LSM6DSRX_AUX_PULL_UP_DISC;
3233 break;
3234
3235 case LSM6DSRX_AUX_PULL_UP_CONNECT:
3236 *val = LSM6DSRX_AUX_PULL_UP_CONNECT;
3237 break;
3238
3239 default:
3240 *val = LSM6DSRX_AUX_PULL_UP_DISC;
3241 break;
3242 }
3243
3244 return ret;
3245 }
3246
3247 /**
3248 * @brief OIS chain on aux interface power on mode.[set]
3249 *
3250 * @param ctx Read / write interface definitions.(ptr)
3251 * @param val Change the values of ois_on in reg CTRL7_G
3252 * @retval Interface status (MANDATORY: return 0 -> no Error).
3253 *
3254 */
lsm6dsrx_aux_pw_on_ctrl_set(stmdev_ctx_t * ctx,lsm6dsrx_ois_on_t val)3255 int32_t lsm6dsrx_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
3256 lsm6dsrx_ois_on_t val)
3257 {
3258 lsm6dsrx_ctrl7_g_t ctrl7_g;
3259 int32_t ret;
3260
3261 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
3262
3263 if (ret == 0)
3264 {
3265 ctrl7_g.ois_on_en = (uint8_t)val & 0x01U;
3266 ctrl7_g.ois_on = (uint8_t)val & 0x01U;
3267 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
3268 }
3269
3270 return ret;
3271 }
3272
3273 /**
3274 * @brief OIS chain on aux interface power on mode[get]
3275 *
3276 * @param ctx Read / write interface definitions.(ptr)
3277 * @param val Get the values of ois_on in reg CTRL7_G
3278 * @retval Interface status (MANDATORY: return 0 -> no Error).
3279 *
3280 */
lsm6dsrx_aux_pw_on_ctrl_get(stmdev_ctx_t * ctx,lsm6dsrx_ois_on_t * val)3281 int32_t lsm6dsrx_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
3282 lsm6dsrx_ois_on_t *val)
3283 {
3284 lsm6dsrx_ctrl7_g_t ctrl7_g;
3285 int32_t ret;
3286
3287 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
3288
3289 switch (ctrl7_g.ois_on)
3290 {
3291 case LSM6DSRX_AUX_ON:
3292 *val = LSM6DSRX_AUX_ON;
3293 break;
3294
3295 case LSM6DSRX_AUX_ON_BY_AUX_INTERFACE:
3296 *val = LSM6DSRX_AUX_ON_BY_AUX_INTERFACE;
3297 break;
3298
3299 default:
3300 *val = LSM6DSRX_AUX_ON;
3301 break;
3302 }
3303
3304 return ret;
3305 }
3306
3307 /**
3308 * @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get]
3309 *
3310 * @param ctx Read / write interface definitions.(ptr)
3311 * @param lsm6dsrx_status_spiaux_t: registers STATUS_SPIAUX
3312 * @retval Interface status (MANDATORY: return 0 -> no Error).
3313 *
3314 */
lsm6dsrx_aux_status_reg_get(stmdev_ctx_t * ctx,lsm6dsrx_status_spiaux_t * val)3315 int32_t lsm6dsrx_aux_status_reg_get(stmdev_ctx_t *ctx,
3316 lsm6dsrx_status_spiaux_t *val)
3317 {
3318 int32_t ret;
3319
3320 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_SPIAUX, (uint8_t *)val, 1);
3321
3322 return ret;
3323 }
3324
3325 /**
3326 * @brief AUX accelerometer data available.[get]
3327 *
3328 * @param ctx Read / write interface definitions.(ptr)
3329 * @param val Change the values of xlda in reg STATUS_SPIAUX
3330 * @retval Interface status (MANDATORY: return 0 -> no Error).
3331 *
3332 */
lsm6dsrx_aux_xl_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)3333 int32_t lsm6dsrx_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
3334 uint8_t *val)
3335 {
3336 lsm6dsrx_status_spiaux_t status_spiaux;
3337 int32_t ret;
3338
3339 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_SPIAUX,
3340 (uint8_t *)&status_spiaux, 1);
3341 *val = status_spiaux.xlda;
3342
3343 return ret;
3344 }
3345
3346 /**
3347 * @brief AUX gyroscope data available.[get]
3348 *
3349 * @param ctx Read / write interface definitions.(ptr)
3350 * @param val Change the values of gda in reg STATUS_SPIAUX
3351 * @retval Interface status (MANDATORY: return 0 -> no Error).
3352 *
3353 */
lsm6dsrx_aux_gy_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)3354 int32_t lsm6dsrx_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
3355 uint8_t *val)
3356 {
3357 lsm6dsrx_status_spiaux_t status_spiaux;
3358 int32_t ret;
3359
3360 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_SPIAUX,
3361 (uint8_t *)&status_spiaux, 1);
3362 *val = status_spiaux.gda;
3363
3364 return ret;
3365 }
3366
3367 /**
3368 * @brief High when the gyroscope output is in the settling phase.[get]
3369 *
3370 * @param ctx Read / write interface definitions.(ptr)
3371 * @param val Change the values of gyro_settling in reg STATUS_SPIAUX
3372 * @retval Interface status (MANDATORY: return 0 -> no Error).
3373 *
3374 */
lsm6dsrx_aux_gy_flag_settling_get(stmdev_ctx_t * ctx,uint8_t * val)3375 int32_t lsm6dsrx_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
3376 uint8_t *val)
3377 {
3378 lsm6dsrx_status_spiaux_t status_spiaux;
3379 int32_t ret;
3380
3381 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_SPIAUX,
3382 (uint8_t *)&status_spiaux, 1);
3383 *val = status_spiaux.gyro_settling;
3384
3385 return ret;
3386 }
3387
3388 /**
3389 * @brief Selects accelerometer self-test. Effective only if XL OIS chain is
3390 * enabled.[set]
3391 *
3392 * @param ctx Read / write interface definitions.(ptr)
3393 * @param val Change the values of st_xl_ois in reg INT_OIS
3394 * @retval Interface status (MANDATORY: return 0 -> no Error).
3395 *
3396 */
lsm6dsrx_aux_xl_self_test_set(stmdev_ctx_t * ctx,lsm6dsrx_st_xl_ois_t val)3397 int32_t lsm6dsrx_aux_xl_self_test_set(stmdev_ctx_t *ctx,
3398 lsm6dsrx_st_xl_ois_t val)
3399 {
3400 lsm6dsrx_int_ois_t int_ois;
3401 int32_t ret;
3402
3403 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
3404
3405 if (ret == 0)
3406 {
3407 int_ois.st_xl_ois = (uint8_t)val;
3408 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
3409 }
3410
3411 return ret;
3412 }
3413
3414 /**
3415 * @brief Selects accelerometer self-test. Effective only if XL OIS chain
3416 * is enabled.[get]
3417 *
3418 * @param ctx Read / write interface definitions.(ptr)
3419 * @param val Get the values of st_xl_ois in reg INT_OIS
3420 * @retval Interface status (MANDATORY: return 0 -> no Error).
3421 *
3422 */
lsm6dsrx_aux_xl_self_test_get(stmdev_ctx_t * ctx,lsm6dsrx_st_xl_ois_t * val)3423 int32_t lsm6dsrx_aux_xl_self_test_get(stmdev_ctx_t *ctx,
3424 lsm6dsrx_st_xl_ois_t *val)
3425 {
3426 lsm6dsrx_int_ois_t int_ois;
3427 int32_t ret;
3428
3429 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
3430
3431 switch (int_ois.st_xl_ois)
3432 {
3433 case LSM6DSRX_AUX_XL_DISABLE:
3434 *val = LSM6DSRX_AUX_XL_DISABLE;
3435 break;
3436
3437 case LSM6DSRX_AUX_XL_POS:
3438 *val = LSM6DSRX_AUX_XL_POS;
3439 break;
3440
3441 case LSM6DSRX_AUX_XL_NEG:
3442 *val = LSM6DSRX_AUX_XL_NEG;
3443 break;
3444
3445 default:
3446 *val = LSM6DSRX_AUX_XL_DISABLE;
3447 break;
3448 }
3449
3450 return ret;
3451 }
3452
3453 /**
3454 * @brief Indicates polarity of DEN signal on OIS chain.[set]
3455 *
3456 * @param ctx Read / write interface definitions.(ptr)
3457 * @param val Change the values of den_lh_ois in reg INT_OIS
3458 * @retval Interface status (MANDATORY: return 0 -> no Error).
3459 *
3460 */
lsm6dsrx_aux_den_polarity_set(stmdev_ctx_t * ctx,lsm6dsrx_den_lh_ois_t val)3461 int32_t lsm6dsrx_aux_den_polarity_set(stmdev_ctx_t *ctx,
3462 lsm6dsrx_den_lh_ois_t val)
3463 {
3464 lsm6dsrx_int_ois_t int_ois;
3465 int32_t ret;
3466
3467 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
3468
3469 if (ret == 0)
3470 {
3471 int_ois.den_lh_ois = (uint8_t)val;
3472 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
3473 }
3474
3475 return ret;
3476 }
3477
3478 /**
3479 * @brief Indicates polarity of DEN signal on OIS chain.[get]
3480 *
3481 * @param ctx Read / write interface definitions.(ptr)
3482 * @param val Get the values of den_lh_ois in reg INT_OIS
3483 * @retval Interface status (MANDATORY: return 0 -> no Error).
3484 *
3485 */
lsm6dsrx_aux_den_polarity_get(stmdev_ctx_t * ctx,lsm6dsrx_den_lh_ois_t * val)3486 int32_t lsm6dsrx_aux_den_polarity_get(stmdev_ctx_t *ctx,
3487 lsm6dsrx_den_lh_ois_t *val)
3488 {
3489 lsm6dsrx_int_ois_t int_ois;
3490 int32_t ret;
3491
3492 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
3493
3494 switch (int_ois.den_lh_ois)
3495 {
3496 case LSM6DSRX_AUX_DEN_ACTIVE_LOW:
3497 *val = LSM6DSRX_AUX_DEN_ACTIVE_LOW;
3498 break;
3499
3500 case LSM6DSRX_AUX_DEN_ACTIVE_HIGH:
3501 *val = LSM6DSRX_AUX_DEN_ACTIVE_HIGH;
3502 break;
3503
3504 default:
3505 *val = LSM6DSRX_AUX_DEN_ACTIVE_LOW;
3506 break;
3507 }
3508
3509 return ret;
3510 }
3511
3512 /**
3513 * @brief Configure DEN mode on the OIS chain.[set]
3514 *
3515 * @param ctx Read / write interface definitions.(ptr)
3516 * @param val Change the values of lvl2_ois in reg INT_OIS
3517 * @retval Interface status (MANDATORY: return 0 -> no Error).
3518 *
3519 */
lsm6dsrx_aux_den_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_lvl2_ois_t val)3520 int32_t lsm6dsrx_aux_den_mode_set(stmdev_ctx_t *ctx,
3521 lsm6dsrx_lvl2_ois_t val)
3522 {
3523 lsm6dsrx_int_ois_t int_ois;
3524 lsm6dsrx_ctrl1_ois_t ctrl1_ois;
3525 int32_t ret;
3526
3527 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
3528
3529 if (ret == 0)
3530 {
3531 int_ois.lvl2_ois = (uint8_t)val & 0x01U;
3532 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
3533 }
3534
3535 if (ret == 0)
3536 {
3537 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
3538 (uint8_t *)&ctrl1_ois, 1);
3539 }
3540
3541 if (ret == 0)
3542 {
3543 ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
3544 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_OIS,
3545 (uint8_t *)&ctrl1_ois, 1);
3546 }
3547
3548 return ret;
3549 }
3550
3551 /**
3552 * @brief Configure DEN mode on the OIS chain.[get]
3553 *
3554 * @param ctx Read / write interface definitions.(ptr)
3555 * @param val Get the values of lvl2_ois in reg INT_OIS
3556 * @retval Interface status (MANDATORY: return 0 -> no Error).
3557 *
3558 */
lsm6dsrx_aux_den_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_lvl2_ois_t * val)3559 int32_t lsm6dsrx_aux_den_mode_get(stmdev_ctx_t *ctx,
3560 lsm6dsrx_lvl2_ois_t *val)
3561 {
3562 lsm6dsrx_int_ois_t int_ois;
3563 lsm6dsrx_ctrl1_ois_t ctrl1_ois;
3564 int32_t ret;
3565
3566 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
3567
3568 if (ret == 0)
3569 {
3570 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
3571 (uint8_t *)&ctrl1_ois, 1);
3572 }
3573
3574 switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois)
3575 {
3576 case LSM6DSRX_AUX_DEN_DISABLE:
3577 *val = LSM6DSRX_AUX_DEN_DISABLE;
3578 break;
3579
3580 case LSM6DSRX_AUX_DEN_LEVEL_LATCH:
3581 *val = LSM6DSRX_AUX_DEN_LEVEL_LATCH;
3582 break;
3583
3584 case LSM6DSRX_AUX_DEN_LEVEL_TRIG:
3585 *val = LSM6DSRX_AUX_DEN_LEVEL_TRIG;
3586 break;
3587
3588 default:
3589 *val = LSM6DSRX_AUX_DEN_DISABLE;
3590 break;
3591 }
3592
3593 return ret;
3594 }
3595
3596 /**
3597 * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting has
3598 * priority over all other INT2 settings.[set]
3599 *
3600 * @param ctx Read / write interface definitions.(ptr)
3601 * @param val Change the values of int2_drdy_ois in reg INT_OIS
3602 * @retval Interface status (MANDATORY: return 0 -> no Error).
3603 *
3604 */
lsm6dsrx_aux_drdy_on_int2_set(stmdev_ctx_t * ctx,uint8_t val)3605 int32_t lsm6dsrx_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
3606 {
3607 lsm6dsrx_int_ois_t int_ois;
3608 int32_t ret;
3609
3610 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
3611
3612 if (ret == 0)
3613 {
3614 int_ois.int2_drdy_ois = (uint8_t)val;
3615 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
3616 }
3617
3618 return ret;
3619 }
3620
3621 /**
3622 * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting has
3623 * priority over all other INT2 settings.[get]
3624 *
3625 * @param ctx Read / write interface definitions.(ptr)
3626 * @param val Change the values of int2_drdy_ois in reg INT_OIS
3627 * @retval Interface status (MANDATORY: return 0 -> no Error).
3628 *
3629 */
lsm6dsrx_aux_drdy_on_int2_get(stmdev_ctx_t * ctx,uint8_t * val)3630 int32_t lsm6dsrx_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
3631 {
3632 lsm6dsrx_int_ois_t int_ois;
3633 int32_t ret;
3634
3635 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_OIS, (uint8_t *)&int_ois, 1);
3636 *val = int_ois.int2_drdy_ois;
3637
3638 return ret;
3639 }
3640
3641 /**
3642 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
3643 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
3644 * When the OIS chain is enabled, the OIS outputs are available
3645 * through the SPI2 in registers OUTX_L_G (22h) through OUTZ_H_G(27h)
3646 * and STATUS_REG (1Eh) / STATUS_SPIAux, and LPF1 is dedicated to
3647 * this chain.[set]
3648 *
3649 * @param ctx Read / write interface definitions.(ptr)
3650 * @param val Change the values of ois_en_spi2 in reg CTRL1_OIS
3651 * @retval Interface status (MANDATORY: return 0 -> no Error).
3652 *
3653 */
lsm6dsrx_aux_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_ois_en_spi2_t val)3654 int32_t lsm6dsrx_aux_mode_set(stmdev_ctx_t *ctx,
3655 lsm6dsrx_ois_en_spi2_t val)
3656 {
3657 lsm6dsrx_ctrl1_ois_t ctrl1_ois;
3658 int32_t ret;
3659
3660 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
3661 (uint8_t *)&ctrl1_ois, 1);
3662
3663 if (ret == 0)
3664 {
3665 ctrl1_ois.ois_en_spi2 = (uint8_t)val & 0x01U;
3666 ctrl1_ois.mode4_en = ((uint8_t)val & 0x02U) >> 1;
3667 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_OIS,
3668 (uint8_t *)&ctrl1_ois, 1);
3669 }
3670
3671 return ret;
3672 }
3673
3674 /**
3675 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
3676 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
3677 * When the OIS chain is enabled, the OIS outputs are available
3678 * through the SPI2 in registers OUTX_L_G (22h) through OUTZ_H_G(27h)
3679 * and STATUS_REG (1Eh) / STATUS_SPIAux, and LPF1 is dedicated to
3680 * this chain.[get]
3681 *
3682 * @param ctx Read / write interface definitions.(ptr)
3683 * @param val Get the values of ois_en_spi2 in
3684 * reg CTRL1_OIS
3685 * @retval Interface status (MANDATORY: return 0 -> no Error).
3686 *
3687 */
lsm6dsrx_aux_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_ois_en_spi2_t * val)3688 int32_t lsm6dsrx_aux_mode_get(stmdev_ctx_t *ctx,
3689 lsm6dsrx_ois_en_spi2_t *val)
3690 {
3691 lsm6dsrx_ctrl1_ois_t ctrl1_ois;
3692 int32_t ret;
3693
3694 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
3695 (uint8_t *)&ctrl1_ois, 1);
3696
3697 switch (((ctrl1_ois.mode4_en << 1) + ctrl1_ois.ois_en_spi2))
3698 {
3699 case LSM6DSRX_AUX_DISABLE:
3700 *val = LSM6DSRX_AUX_DISABLE;
3701 break;
3702
3703 case LSM6DSRX_MODE_3_GY:
3704 *val = LSM6DSRX_MODE_3_GY;
3705 break;
3706
3707 case LSM6DSRX_MODE_4_GY_XL:
3708 *val = LSM6DSRX_MODE_4_GY_XL;
3709 break;
3710
3711 default:
3712 *val = LSM6DSRX_AUX_DISABLE;
3713 break;
3714 }
3715
3716 return ret;
3717 }
3718
3719 /**
3720 * @brief Selects gyroscope OIS chain full-scale.[set]
3721 *
3722 * @param ctx Read / write interface definitions.(ptr)
3723 * @param val Change the values of fs_g_ois in reg CTRL1_OIS
3724 * @retval Interface status (MANDATORY: return 0 -> no Error).
3725 *
3726 */
lsm6dsrx_aux_gy_full_scale_set(stmdev_ctx_t * ctx,lsm6dsrx_fs_g_ois_t val)3727 int32_t lsm6dsrx_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
3728 lsm6dsrx_fs_g_ois_t val)
3729 {
3730 lsm6dsrx_ctrl1_ois_t ctrl1_ois;
3731 int32_t ret;
3732
3733 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
3734 (uint8_t *)&ctrl1_ois, 1);
3735
3736 if (ret == 0)
3737 {
3738 ctrl1_ois.fs_g_ois = (uint8_t)val & 0x03U;
3739 ctrl1_ois.fs_125_ois = ((uint8_t)val & 0x04U) >> 2;
3740 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_OIS,
3741 (uint8_t *)&ctrl1_ois, 1);
3742 }
3743
3744 return ret;
3745 }
3746
3747 /**
3748 * @brief Selects gyroscope OIS chain full-scale.[get]
3749 *
3750 * @param ctx Read / write interface definitions.(ptr)
3751 * @param val Get the values of fs_g_ois in reg CTRL1_OIS
3752 * @retval Interface status (MANDATORY: return 0 -> no Error).
3753 *
3754 */
lsm6dsrx_aux_gy_full_scale_get(stmdev_ctx_t * ctx,lsm6dsrx_fs_g_ois_t * val)3755 int32_t lsm6dsrx_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
3756 lsm6dsrx_fs_g_ois_t *val)
3757 {
3758 lsm6dsrx_ctrl1_ois_t ctrl1_ois;
3759 int32_t ret;
3760
3761 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
3762 (uint8_t *)&ctrl1_ois, 1);
3763
3764 switch ((ctrl1_ois.fs_125_ois << 2) + ctrl1_ois.fs_g_ois)
3765 {
3766 case LSM6DSRX_250dps_AUX:
3767 *val = LSM6DSRX_250dps_AUX;
3768 break;
3769
3770 case LSM6DSRX_125dps_AUX:
3771 *val = LSM6DSRX_125dps_AUX;
3772 break;
3773
3774 case LSM6DSRX_500dps_AUX:
3775 *val = LSM6DSRX_500dps_AUX;
3776 break;
3777
3778 case LSM6DSRX_1000dps_AUX:
3779 *val = LSM6DSRX_1000dps_AUX;
3780 break;
3781
3782 case LSM6DSRX_2000dps_AUX:
3783 *val = LSM6DSRX_2000dps_AUX;
3784 break;
3785
3786 default:
3787 *val = LSM6DSRX_250dps_AUX;
3788 break;
3789 }
3790
3791 return ret;
3792 }
3793
3794 /**
3795 * @brief SPI2 3- or 4-wire interface.[set]
3796 *
3797 * @param ctx Read / write interface definitions.(ptr)
3798 * @param val Change the values of sim_ois in reg CTRL1_OIS
3799 * @retval Interface status (MANDATORY: return 0 -> no Error).
3800 *
3801 */
lsm6dsrx_aux_spi_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_sim_ois_t val)3802 int32_t lsm6dsrx_aux_spi_mode_set(stmdev_ctx_t *ctx,
3803 lsm6dsrx_sim_ois_t val)
3804 {
3805 lsm6dsrx_ctrl1_ois_t ctrl1_ois;
3806 int32_t ret;
3807
3808 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
3809 (uint8_t *)&ctrl1_ois, 1);
3810
3811 if (ret == 0)
3812 {
3813 ctrl1_ois.sim_ois = (uint8_t)val;
3814 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL1_OIS,
3815 (uint8_t *)&ctrl1_ois, 1);
3816 }
3817
3818 return ret;
3819 }
3820
3821 /**
3822 * @brief SPI2 3- or 4-wire interface.[get]
3823 *
3824 * @param ctx Read / write interface definitions.(ptr)
3825 * @param val Get the values of sim_ois in reg CTRL1_OIS
3826 * @retval Interface status (MANDATORY: return 0 -> no Error).
3827 *
3828 */
lsm6dsrx_aux_spi_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_sim_ois_t * val)3829 int32_t lsm6dsrx_aux_spi_mode_get(stmdev_ctx_t *ctx,
3830 lsm6dsrx_sim_ois_t *val)
3831 {
3832 lsm6dsrx_ctrl1_ois_t ctrl1_ois;
3833 int32_t ret;
3834
3835 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL1_OIS,
3836 (uint8_t *)&ctrl1_ois, 1);
3837
3838 switch (ctrl1_ois.sim_ois)
3839 {
3840 case LSM6DSRX_AUX_SPI_4_WIRE:
3841 *val = LSM6DSRX_AUX_SPI_4_WIRE;
3842 break;
3843
3844 case LSM6DSRX_AUX_SPI_3_WIRE:
3845 *val = LSM6DSRX_AUX_SPI_3_WIRE;
3846 break;
3847
3848 default:
3849 *val = LSM6DSRX_AUX_SPI_4_WIRE;
3850 break;
3851 }
3852
3853 return ret;
3854 }
3855
3856 /**
3857 * @brief Selects gyroscope digital LPF1 filter bandwidth.[set]
3858 *
3859 * @param ctx Read / write interface definitions.(ptr)
3860 * @param val Change the values of ftype_ois in reg CTRL2_OIS
3861 * @retval Interface status (MANDATORY: return 0 -> no Error).
3862 *
3863 */
lsm6dsrx_aux_gy_lp1_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsrx_ftype_ois_t val)3864 int32_t lsm6dsrx_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
3865 lsm6dsrx_ftype_ois_t val)
3866 {
3867 lsm6dsrx_ctrl2_ois_t ctrl2_ois;
3868 int32_t ret;
3869
3870 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_OIS,
3871 (uint8_t *)&ctrl2_ois, 1);
3872
3873 if (ret == 0)
3874 {
3875 ctrl2_ois.ftype_ois = (uint8_t)val;
3876 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL2_OIS,
3877 (uint8_t *)&ctrl2_ois, 1);
3878 }
3879
3880 return ret;
3881 }
3882
3883 /**
3884 * @brief Selects gyroscope digital LPF1 filter bandwidth.[get]
3885 *
3886 * @param ctx Read / write interface definitions.(ptr)
3887 * @param val Get the values of ftype_ois in reg CTRL2_OIS
3888 * @retval Interface status (MANDATORY: return 0 -> no Error).
3889 *
3890 */
lsm6dsrx_aux_gy_lp1_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsrx_ftype_ois_t * val)3891 int32_t lsm6dsrx_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
3892 lsm6dsrx_ftype_ois_t *val)
3893 {
3894 lsm6dsrx_ctrl2_ois_t ctrl2_ois;
3895 int32_t ret;
3896
3897 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_OIS,
3898 (uint8_t *)&ctrl2_ois, 1);
3899
3900 switch (ctrl2_ois.ftype_ois)
3901 {
3902 case LSM6DSRX_351Hz39:
3903 *val = LSM6DSRX_351Hz39;
3904 break;
3905
3906 case LSM6DSRX_236Hz63:
3907 *val = LSM6DSRX_236Hz63;
3908 break;
3909
3910 case LSM6DSRX_172Hz70:
3911 *val = LSM6DSRX_172Hz70;
3912 break;
3913
3914 case LSM6DSRX_937Hz91:
3915 *val = LSM6DSRX_937Hz91;
3916 break;
3917
3918 default:
3919 *val = LSM6DSRX_351Hz39;
3920 break;
3921 }
3922
3923 return ret;
3924 }
3925
3926 /**
3927 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[set]
3928 *
3929 * @param ctx Read / write interface definitions.(ptr)
3930 * @param val Change the values of hpm_ois in reg CTRL2_OIS
3931 * @retval Interface status (MANDATORY: return 0 -> no Error).
3932 *
3933 */
lsm6dsrx_aux_gy_hp_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsrx_hpm_ois_t val)3934 int32_t lsm6dsrx_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
3935 lsm6dsrx_hpm_ois_t val)
3936 {
3937 lsm6dsrx_ctrl2_ois_t ctrl2_ois;
3938 int32_t ret;
3939
3940 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_OIS,
3941 (uint8_t *)&ctrl2_ois, 1);
3942
3943 if (ret == 0)
3944 {
3945 ctrl2_ois.hpm_ois = (uint8_t)val & 0x03U;
3946 ctrl2_ois.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
3947 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL2_OIS,
3948 (uint8_t *)&ctrl2_ois, 1);
3949 }
3950
3951 return ret;
3952 }
3953
3954 /**
3955 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[get]
3956 *
3957 * @param ctx Read / write interface definitions.(ptr)
3958 * @param val Get the values of hpm_ois in reg CTRL2_OIS
3959 * @retval Interface status (MANDATORY: return 0 -> no Error).
3960 *
3961 */
lsm6dsrx_aux_gy_hp_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsrx_hpm_ois_t * val)3962 int32_t lsm6dsrx_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
3963 lsm6dsrx_hpm_ois_t *val)
3964 {
3965 lsm6dsrx_ctrl2_ois_t ctrl2_ois;
3966 int32_t ret;
3967
3968 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL2_OIS,
3969 (uint8_t *)&ctrl2_ois, 1);
3970
3971 switch ((ctrl2_ois.hp_en_ois << 4) + ctrl2_ois.hpm_ois)
3972 {
3973 case LSM6DSRX_AUX_HP_DISABLE:
3974 *val = LSM6DSRX_AUX_HP_DISABLE;
3975 break;
3976
3977 case LSM6DSRX_AUX_HP_Hz016:
3978 *val = LSM6DSRX_AUX_HP_Hz016;
3979 break;
3980
3981 case LSM6DSRX_AUX_HP_Hz065:
3982 *val = LSM6DSRX_AUX_HP_Hz065;
3983 break;
3984
3985 case LSM6DSRX_AUX_HP_Hz260:
3986 *val = LSM6DSRX_AUX_HP_Hz260;
3987 break;
3988
3989 case LSM6DSRX_AUX_HP_1Hz040:
3990 *val = LSM6DSRX_AUX_HP_1Hz040;
3991 break;
3992
3993 default:
3994 *val = LSM6DSRX_AUX_HP_DISABLE;
3995 break;
3996 }
3997
3998 return ret;
3999 }
4000
4001 /**
4002 * @brief Enable / Disables OIS chain clamp. Enable: All OIS chain
4003 * outputs = 8000h during self-test; Disable: OIS chain self-test
4004 * outputs dependent from the aux gyro full scale selected.[set]
4005 *
4006 * @param ctx Read / write interface definitions.(ptr)
4007 * @param val Change the values of st_ois_clampdis in reg CTRL3_OIS
4008 * @retval Interface status (MANDATORY: return 0 -> no Error).
4009 *
4010 */
lsm6dsrx_aux_gy_clamp_set(stmdev_ctx_t * ctx,lsm6dsrx_st_ois_clampdis_t val)4011 int32_t lsm6dsrx_aux_gy_clamp_set(stmdev_ctx_t *ctx,
4012 lsm6dsrx_st_ois_clampdis_t val)
4013 {
4014 lsm6dsrx_ctrl3_ois_t ctrl3_ois;
4015 int32_t ret;
4016
4017 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
4018 (uint8_t *)&ctrl3_ois, 1);
4019
4020 if (ret == 0)
4021 {
4022 ctrl3_ois.st_ois_clampdis = (uint8_t)val;
4023 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_OIS,
4024 (uint8_t *)&ctrl3_ois, 1);
4025 }
4026
4027 return ret;
4028 }
4029
4030 /**
4031 * @brief Enable / Disables OIS chain clamp. Enable: All OIS chain
4032 * outputs = 8000h during self-test; Disable: OIS chain self-test
4033 * outputs dependent from the aux gyro full scale selected.[get]
4034 *
4035 * @param ctx Read / write interface definitions.(ptr)
4036 * @param val Get the values of st_ois_clampdis in reg CTRL3_OIS
4037 * @retval Interface status (MANDATORY: return 0 -> no Error).
4038 *
4039 */
lsm6dsrx_aux_gy_clamp_get(stmdev_ctx_t * ctx,lsm6dsrx_st_ois_clampdis_t * val)4040 int32_t lsm6dsrx_aux_gy_clamp_get(stmdev_ctx_t *ctx,
4041 lsm6dsrx_st_ois_clampdis_t *val)
4042 {
4043 lsm6dsrx_ctrl3_ois_t ctrl3_ois;
4044 int32_t ret;
4045
4046 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
4047 (uint8_t *)&ctrl3_ois, 1);
4048
4049 switch (ctrl3_ois.st_ois_clampdis)
4050 {
4051 case LSM6DSRX_ENABLE_CLAMP:
4052 *val = LSM6DSRX_ENABLE_CLAMP;
4053 break;
4054
4055 case LSM6DSRX_DISABLE_CLAMP:
4056 *val = LSM6DSRX_DISABLE_CLAMP;
4057 break;
4058
4059 default:
4060 *val = LSM6DSRX_ENABLE_CLAMP;
4061 break;
4062 }
4063
4064 return ret;
4065 }
4066
4067 /**
4068 * @brief Selects gyroscope OIS chain self-test.[set]
4069 *
4070 * @param ctx Read / write interface definitions.(ptr)
4071 * @param val Change the values of st_ois in reg CTRL3_OIS
4072 * @retval Interface status (MANDATORY: return 0 -> no Error).
4073 *
4074 */
lsm6dsrx_aux_gy_self_test_set(stmdev_ctx_t * ctx,lsm6dsrx_st_ois_t val)4075 int32_t lsm6dsrx_aux_gy_self_test_set(stmdev_ctx_t *ctx,
4076 lsm6dsrx_st_ois_t val)
4077 {
4078 lsm6dsrx_ctrl3_ois_t ctrl3_ois;
4079 int32_t ret;
4080
4081 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
4082 (uint8_t *)&ctrl3_ois, 1);
4083
4084 if (ret == 0)
4085 {
4086 ctrl3_ois.st_ois = (uint8_t)val;
4087 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_OIS,
4088 (uint8_t *)&ctrl3_ois, 1);
4089 }
4090
4091 return ret;
4092 }
4093
4094 /**
4095 * @brief Selects gyroscope OIS chain self-test.[get]
4096 *
4097 * @param ctx Read / write interface definitions.(ptr)
4098 * @param val Get the values of st_ois in reg CTRL3_OIS
4099 * @retval Interface status (MANDATORY: return 0 -> no Error).
4100 *
4101 */
lsm6dsrx_aux_gy_self_test_get(stmdev_ctx_t * ctx,lsm6dsrx_st_ois_t * val)4102 int32_t lsm6dsrx_aux_gy_self_test_get(stmdev_ctx_t *ctx,
4103 lsm6dsrx_st_ois_t *val)
4104 {
4105 lsm6dsrx_ctrl3_ois_t ctrl3_ois;
4106 int32_t ret;
4107
4108 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
4109 (uint8_t *)&ctrl3_ois, 1);
4110
4111 switch (ctrl3_ois.st_ois)
4112 {
4113 case LSM6DSRX_AUX_GY_DISABLE:
4114 *val = LSM6DSRX_AUX_GY_DISABLE;
4115 break;
4116
4117 case LSM6DSRX_AUX_GY_POS:
4118 *val = LSM6DSRX_AUX_GY_POS;
4119 break;
4120
4121 case LSM6DSRX_AUX_GY_NEG:
4122 *val = LSM6DSRX_AUX_GY_NEG;
4123 break;
4124
4125 default:
4126 *val = LSM6DSRX_AUX_GY_DISABLE;
4127 break;
4128 }
4129
4130 return ret;
4131 }
4132
4133 /**
4134 * @brief Selects accelerometer OIS channel bandwidth.[set]
4135 *
4136 * @param ctx Read / write interface definitions.(ptr)
4137 * @param val Change the values of filter_xl_conf_ois in reg CTRL3_OIS
4138 * @retval Interface status (MANDATORY: return 0 -> no Error).
4139 *
4140 */
lsm6dsrx_aux_xl_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsrx_filter_xl_conf_ois_t val)4141 int32_t lsm6dsrx_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
4142 lsm6dsrx_filter_xl_conf_ois_t val)
4143 {
4144 lsm6dsrx_ctrl3_ois_t ctrl3_ois;
4145 int32_t ret;
4146
4147 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
4148 (uint8_t *)&ctrl3_ois, 1);
4149
4150 if (ret == 0)
4151 {
4152 ctrl3_ois.filter_xl_conf_ois = (uint8_t)val;
4153 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_OIS,
4154 (uint8_t *)&ctrl3_ois, 1);
4155 }
4156
4157 return ret;
4158 }
4159
4160 /**
4161 * @brief Selects accelerometer OIS channel bandwidth.[get]
4162 *
4163 * @param ctx Read / write interface definitions.(ptr)
4164 * @param val Get the values of filter_xl_conf_ois in reg CTRL3_OIS
4165 * @retval Interface status (MANDATORY: return 0 -> no Error).
4166 *
4167 */
lsm6dsrx_aux_xl_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsrx_filter_xl_conf_ois_t * val)4168 int32_t lsm6dsrx_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
4169 lsm6dsrx_filter_xl_conf_ois_t *val)
4170 {
4171 lsm6dsrx_ctrl3_ois_t ctrl3_ois;
4172 int32_t ret;
4173
4174 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
4175 (uint8_t *)&ctrl3_ois, 1);
4176
4177 switch (ctrl3_ois.filter_xl_conf_ois)
4178 {
4179 case LSM6DSRX_631Hz:
4180 *val = LSM6DSRX_631Hz;
4181 break;
4182
4183 case LSM6DSRX_295Hz:
4184 *val = LSM6DSRX_295Hz;
4185 break;
4186
4187 case LSM6DSRX_140Hz:
4188 *val = LSM6DSRX_140Hz;
4189 break;
4190
4191 case LSM6DSRX_68Hz2:
4192 *val = LSM6DSRX_68Hz2;
4193 break;
4194
4195 case LSM6DSRX_33Hz6:
4196 *val = LSM6DSRX_33Hz6;
4197 break;
4198
4199 case LSM6DSRX_16Hz7:
4200 *val = LSM6DSRX_16Hz7;
4201 break;
4202
4203 case LSM6DSRX_8Hz3:
4204 *val = LSM6DSRX_8Hz3;
4205 break;
4206
4207 case LSM6DSRX_4Hz11:
4208 *val = LSM6DSRX_4Hz11;
4209 break;
4210
4211 default:
4212 *val = LSM6DSRX_631Hz;
4213 break;
4214 }
4215
4216 return ret;
4217 }
4218
4219 /**
4220 * @brief Selects accelerometer OIS channel full-scale.[set]
4221 *
4222 * @param ctx Read / write interface definitions.(ptr)
4223 * @param val Change the values of fs_xl_ois in reg CTRL3_OIS
4224 * @retval Interface status (MANDATORY: return 0 -> no Error).
4225 *
4226 */
lsm6dsrx_aux_xl_full_scale_set(stmdev_ctx_t * ctx,lsm6dsrx_fs_xl_ois_t val)4227 int32_t lsm6dsrx_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
4228 lsm6dsrx_fs_xl_ois_t val)
4229 {
4230 lsm6dsrx_ctrl3_ois_t ctrl3_ois;
4231 int32_t ret;
4232
4233 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
4234 (uint8_t *)&ctrl3_ois, 1);
4235
4236 if (ret == 0)
4237 {
4238 ctrl3_ois.fs_xl_ois = (uint8_t)val;
4239 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_OIS,
4240 (uint8_t *)&ctrl3_ois, 1);
4241 }
4242
4243 return ret;
4244 }
4245
4246 /**
4247 * @brief Selects accelerometer OIS channel full-scale.[get]
4248 *
4249 * @param ctx Read / write interface definitions.(ptr)
4250 * @param val Get the values of fs_xl_ois in reg CTRL3_OIS
4251 * @retval Interface status (MANDATORY: return 0 -> no Error).
4252 *
4253 */
lsm6dsrx_aux_xl_full_scale_get(stmdev_ctx_t * ctx,lsm6dsrx_fs_xl_ois_t * val)4254 int32_t lsm6dsrx_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
4255 lsm6dsrx_fs_xl_ois_t *val)
4256 {
4257 lsm6dsrx_ctrl3_ois_t ctrl3_ois;
4258 int32_t ret;
4259
4260 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_OIS,
4261 (uint8_t *)&ctrl3_ois, 1);
4262
4263 switch (ctrl3_ois.fs_xl_ois)
4264 {
4265 case LSM6DSRX_AUX_2g:
4266 *val = LSM6DSRX_AUX_2g;
4267 break;
4268
4269 case LSM6DSRX_AUX_16g:
4270 *val = LSM6DSRX_AUX_16g;
4271 break;
4272
4273 case LSM6DSRX_AUX_4g:
4274 *val = LSM6DSRX_AUX_4g;
4275 break;
4276
4277 case LSM6DSRX_AUX_8g:
4278 *val = LSM6DSRX_AUX_8g;
4279 break;
4280
4281 default:
4282 *val = LSM6DSRX_AUX_2g;
4283 break;
4284 }
4285
4286 return ret;
4287 }
4288
4289 /**
4290 * @}
4291 *
4292 */
4293
4294 /**
4295 * @defgroup LSM6DSRX_ main_serial_interface
4296 * @brief This section groups all the functions concerning main
4297 * serial interface management (not auxiliary)
4298 * @{
4299 *
4300 */
4301
4302 /**
4303 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
4304 *
4305 * @param ctx Read / write interface definitions.(ptr)
4306 * @param val Change the values of sdo_pu_en in reg PIN_CTRL
4307 * @retval Interface status (MANDATORY: return 0 -> no Error).
4308 *
4309 */
lsm6dsrx_sdo_sa0_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_sdo_pu_en_t val)4310 int32_t lsm6dsrx_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
4311 lsm6dsrx_sdo_pu_en_t val)
4312 {
4313 lsm6dsrx_pin_ctrl_t pin_ctrl;
4314 int32_t ret;
4315
4316 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
4317
4318 if (ret == 0)
4319 {
4320 pin_ctrl.sdo_pu_en = (uint8_t)val;
4321 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
4322 }
4323
4324 return ret;
4325 }
4326
4327 /**
4328 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
4329 *
4330 * @param ctx Read / write interface definitions.(ptr)
4331 * @param val Get the values of sdo_pu_en in reg PIN_CTRL
4332 * @retval Interface status (MANDATORY: return 0 -> no Error).
4333 *
4334 */
lsm6dsrx_sdo_sa0_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_sdo_pu_en_t * val)4335 int32_t lsm6dsrx_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
4336 lsm6dsrx_sdo_pu_en_t *val)
4337 {
4338 lsm6dsrx_pin_ctrl_t pin_ctrl;
4339 int32_t ret;
4340
4341 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
4342
4343 switch (pin_ctrl.sdo_pu_en)
4344 {
4345 case LSM6DSRX_PULL_UP_DISC:
4346 *val = LSM6DSRX_PULL_UP_DISC;
4347 break;
4348
4349 case LSM6DSRX_PULL_UP_CONNECT:
4350 *val = LSM6DSRX_PULL_UP_CONNECT;
4351 break;
4352
4353 default:
4354 *val = LSM6DSRX_PULL_UP_DISC;
4355 break;
4356 }
4357
4358 return ret;
4359 }
4360
4361 /**
4362 * @brief Connect/Disconnect INT1 pull-down.[set]
4363 *
4364 * @param ctx Read / write interface definitions.(ptr)
4365 * @param val Change the values of pd_dis_int1 in reg I3C_BUS_AVB
4366 * @retval Interface status (MANDATORY: return 0 -> no Error).
4367 *
4368 */
lsm6dsrx_int1_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_pd_dis_int1_t val)4369 int32_t lsm6dsrx_int1_mode_set(stmdev_ctx_t *ctx,
4370 lsm6dsrx_pd_dis_int1_t val)
4371 {
4372 lsm6dsrx_i3c_bus_avb_t i3c_bus_avb;
4373 int32_t ret;
4374
4375 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_I3C_BUS_AVB,
4376 (uint8_t *)&i3c_bus_avb, 1);
4377
4378 if (ret == 0)
4379 {
4380 i3c_bus_avb.pd_dis_int1 = (uint8_t)val;
4381 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_I3C_BUS_AVB,
4382 (uint8_t *)&i3c_bus_avb, 1);
4383 }
4384
4385 return ret;
4386 }
4387
4388 /**
4389 * @brief Connect/Disconnect INT1 pull-down.[get]
4390 *
4391 * @param ctx Read / write interface definitions.(ptr)
4392 * @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB
4393 * @retval Interface status (MANDATORY: return 0 -> no Error).
4394 *
4395 */
lsm6dsrx_int1_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_pd_dis_int1_t * val)4396 int32_t lsm6dsrx_int1_mode_get(stmdev_ctx_t *ctx,
4397 lsm6dsrx_pd_dis_int1_t *val)
4398 {
4399 lsm6dsrx_i3c_bus_avb_t i3c_bus_avb;
4400 int32_t ret;
4401
4402 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_I3C_BUS_AVB,
4403 (uint8_t *)&i3c_bus_avb, 1);
4404
4405 switch (i3c_bus_avb.pd_dis_int1)
4406 {
4407 case LSM6DSRX_PULL_DOWN_CONNECT:
4408 *val = LSM6DSRX_PULL_DOWN_CONNECT;
4409 break;
4410
4411 case LSM6DSRX_PULL_DOWN_DISC:
4412 *val = LSM6DSRX_PULL_DOWN_DISC;
4413 break;
4414
4415 default:
4416 *val = LSM6DSRX_PULL_DOWN_CONNECT;
4417 break;
4418 }
4419
4420 return ret;
4421 }
4422
4423 /**
4424 * @brief SPI Serial Interface Mode selection.[set]
4425 *
4426 * @param ctx Read / write interface definitions.(ptr)
4427 * @param val Change the values of sim in reg CTRL3_C
4428 * @retval Interface status (MANDATORY: return 0 -> no Error).
4429 *
4430 */
lsm6dsrx_spi_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_sim_t val)4431 int32_t lsm6dsrx_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_sim_t val)
4432 {
4433 lsm6dsrx_ctrl3_c_t ctrl3_c;
4434 int32_t ret;
4435
4436 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4437
4438 if (ret == 0)
4439 {
4440 ctrl3_c.sim = (uint8_t)val;
4441 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4442 }
4443
4444 return ret;
4445 }
4446
4447 /**
4448 * @brief SPI Serial Interface Mode selection.[get]
4449 *
4450 * @param ctx Read / write interface definitions.(ptr)
4451 * @param val Get the values of sim in reg CTRL3_C
4452 * @retval Interface status (MANDATORY: return 0 -> no Error).
4453 *
4454 */
lsm6dsrx_spi_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_sim_t * val)4455 int32_t lsm6dsrx_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsrx_sim_t *val)
4456 {
4457 lsm6dsrx_ctrl3_c_t ctrl3_c;
4458 int32_t ret;
4459
4460 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4461
4462 switch (ctrl3_c.sim)
4463 {
4464 case LSM6DSRX_SPI_4_WIRE:
4465 *val = LSM6DSRX_SPI_4_WIRE;
4466 break;
4467
4468 case LSM6DSRX_SPI_3_WIRE:
4469 *val = LSM6DSRX_SPI_3_WIRE;
4470 break;
4471
4472 default:
4473 *val = LSM6DSRX_SPI_4_WIRE;
4474 break;
4475 }
4476
4477 return ret;
4478 }
4479
4480 /**
4481 * @brief Disable / Enable I2C interface.[set]
4482 *
4483 * @param ctx Read / write interface definitions.(ptr)
4484 * @param val Change the values of i2c_disable in reg CTRL4_C
4485 * @retval Interface status (MANDATORY: return 0 -> no Error).
4486 *
4487 */
lsm6dsrx_i2c_interface_set(stmdev_ctx_t * ctx,lsm6dsrx_i2c_disable_t val)4488 int32_t lsm6dsrx_i2c_interface_set(stmdev_ctx_t *ctx,
4489 lsm6dsrx_i2c_disable_t val)
4490 {
4491 lsm6dsrx_ctrl4_c_t ctrl4_c;
4492 int32_t ret;
4493
4494 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4495
4496 if (ret == 0)
4497 {
4498 ctrl4_c.i2c_disable = (uint8_t)val;
4499 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4500 }
4501
4502 return ret;
4503 }
4504
4505 /**
4506 * @brief Disable / Enable I2C interface.[get]
4507 *
4508 * @param ctx Read / write interface definitions.(ptr)
4509 * @param val Get the values of i2c reg CTRL4_C
4510 * @retval Interface status (MANDATORY: return 0 -> no Error).
4511 *
4512 */
lsm6dsrx_i2c_interface_get(stmdev_ctx_t * ctx,lsm6dsrx_i2c_disable_t * val)4513 int32_t lsm6dsrx_i2c_interface_get(stmdev_ctx_t *ctx,
4514 lsm6dsrx_i2c_disable_t *val)
4515 {
4516 lsm6dsrx_ctrl4_c_t ctrl4_c;
4517 int32_t ret;
4518
4519 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4520
4521 switch (ctrl4_c.i2c_disable)
4522 {
4523 case LSM6DSRX_I2C_ENABLE:
4524 *val = LSM6DSRX_I2C_ENABLE;
4525 break;
4526
4527 case LSM6DSRX_I2C_DISABLE:
4528 *val = LSM6DSRX_I2C_DISABLE;
4529 break;
4530
4531 default:
4532 *val = LSM6DSRX_I2C_ENABLE;
4533 break;
4534 }
4535
4536 return ret;
4537 }
4538
4539 /**
4540 * @brief I3C Enable/Disable communication protocol.[set]
4541 *
4542 * @param ctx Read / write interface definitions.(ptr)
4543 * @param val Change the values of i3c_disable in reg CTRL9_XL
4544 * @retval Interface status (MANDATORY: return 0 -> no Error).
4545 *
4546 */
lsm6dsrx_i3c_disable_set(stmdev_ctx_t * ctx,lsm6dsrx_i3c_disable_t val)4547 int32_t lsm6dsrx_i3c_disable_set(stmdev_ctx_t *ctx,
4548 lsm6dsrx_i3c_disable_t val)
4549 {
4550 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
4551 lsm6dsrx_i3c_bus_avb_t i3c_bus_avb;
4552 int32_t ret;
4553
4554 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
4555
4556 if (ret == 0)
4557 {
4558 ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
4559 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL,
4560 (uint8_t *)&ctrl9_xl, 1);
4561 }
4562
4563 if (ret == 0)
4564 {
4565 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_I3C_BUS_AVB,
4566 (uint8_t *)&i3c_bus_avb, 1);
4567 }
4568
4569 if (ret == 0)
4570 {
4571 i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
4572 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_I3C_BUS_AVB,
4573 (uint8_t *)&i3c_bus_avb, 1);
4574 }
4575
4576 return ret;
4577 }
4578
4579 /**
4580 * @brief I3C Enable/Disable communication protocol.[get]
4581 *
4582 * @param ctx Read / write interface definitions.(ptr)
4583 * @param val Change the values of i3c_disable in reg CTRL9_XL
4584 * @retval Interface status (MANDATORY: return 0 -> no Error).
4585 *
4586 */
lsm6dsrx_i3c_disable_get(stmdev_ctx_t * ctx,lsm6dsrx_i3c_disable_t * val)4587 int32_t lsm6dsrx_i3c_disable_get(stmdev_ctx_t *ctx,
4588 lsm6dsrx_i3c_disable_t *val)
4589 {
4590 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
4591 lsm6dsrx_i3c_bus_avb_t i3c_bus_avb;
4592 int32_t ret;
4593
4594 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
4595
4596 if (ret == 0)
4597 {
4598 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_I3C_BUS_AVB,
4599 (uint8_t *)&i3c_bus_avb, 1);
4600 }
4601
4602 switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel)
4603 {
4604 case LSM6DSRX_I3C_DISABLE:
4605 *val = LSM6DSRX_I3C_DISABLE;
4606 break;
4607
4608 case LSM6DSRX_I3C_ENABLE_T_50us:
4609 *val = LSM6DSRX_I3C_ENABLE_T_50us;
4610 break;
4611
4612 case LSM6DSRX_I3C_ENABLE_T_2us:
4613 *val = LSM6DSRX_I3C_ENABLE_T_2us;
4614 break;
4615
4616 case LSM6DSRX_I3C_ENABLE_T_1ms:
4617 *val = LSM6DSRX_I3C_ENABLE_T_1ms;
4618 break;
4619
4620 case LSM6DSRX_I3C_ENABLE_T_25ms:
4621 *val = LSM6DSRX_I3C_ENABLE_T_25ms;
4622 break;
4623
4624 default:
4625 *val = LSM6DSRX_I3C_DISABLE;
4626 break;
4627 }
4628
4629 return ret;
4630 }
4631
4632 /**
4633 * @}
4634 *
4635 */
4636
4637 /**
4638 * @defgroup LSM6DSRX_interrupt_pins
4639 * @brief This section groups all the functions that manage
4640 * interrupt pins
4641 * @{
4642 *
4643 */
4644
4645 /**
4646 * @brief Select the signal that need to route on int1 pad.[set]
4647 *
4648 * @param ctx read / write interface definitions
4649 * @param val struct of registers: INT1_CTRL,
4650 * MD1_CFG, EMB_FUNC_INT1, FSM_INT1_A,
4651 * FSM_INT1_B
4652 *
4653 */
lsm6dsrx_pin_int1_route_set(stmdev_ctx_t * ctx,lsm6dsrx_pin_int1_route_t * val)4654 int32_t lsm6dsrx_pin_int1_route_set(stmdev_ctx_t *ctx,
4655 lsm6dsrx_pin_int1_route_t *val)
4656 {
4657 lsm6dsrx_pin_int2_route_t pin_int2_route;
4658 lsm6dsrx_tap_cfg2_t tap_cfg2;
4659 int32_t ret;
4660
4661 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
4662
4663 if (ret == 0)
4664 {
4665 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MLC_INT1,
4666 (uint8_t *)&val->mlc_int1, 1);
4667 }
4668
4669 if (ret == 0)
4670 {
4671 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_INT1,
4672 (uint8_t *)&val->emb_func_int1, 1);
4673 }
4674
4675 if (ret == 0)
4676 {
4677 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_INT1_A,
4678 (uint8_t *)&val->fsm_int1_a, 1);
4679 }
4680
4681 if (ret == 0)
4682 {
4683 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_INT1_B,
4684 (uint8_t *)&val->fsm_int1_b, 1);
4685 }
4686
4687 if (ret == 0)
4688 {
4689 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
4690 }
4691
4692 if (ret == 0)
4693 {
4694 if ((val->emb_func_int1.int1_fsm_lc
4695 | val->emb_func_int1.int1_sig_mot
4696 | val->emb_func_int1.int1_step_detector
4697 | val->emb_func_int1.int1_tilt
4698 | val->fsm_int1_a.int1_fsm1
4699 | val->fsm_int1_a.int1_fsm2
4700 | val->fsm_int1_a.int1_fsm3
4701 | val->fsm_int1_a.int1_fsm4
4702 | val->fsm_int1_a.int1_fsm5
4703 | val->fsm_int1_a.int1_fsm6
4704 | val->fsm_int1_a.int1_fsm7
4705 | val->fsm_int1_a.int1_fsm8
4706 | val->fsm_int1_b.int1_fsm9
4707 | val->fsm_int1_b.int1_fsm10
4708 | val->fsm_int1_b.int1_fsm11
4709 | val->fsm_int1_b.int1_fsm12
4710 | val->fsm_int1_b.int1_fsm13
4711 | val->fsm_int1_b.int1_fsm14
4712 | val->fsm_int1_b.int1_fsm15
4713 | val->fsm_int1_b.int1_fsm16
4714 | val->mlc_int1.int1_mlc1
4715 | val->mlc_int1.int1_mlc2
4716 | val->mlc_int1.int1_mlc3
4717 | val->mlc_int1.int1_mlc4
4718 | val->mlc_int1.int1_mlc5
4719 | val->mlc_int1.int1_mlc6
4720 | val->mlc_int1.int1_mlc7
4721 | val->mlc_int1.int1_mlc8) != PROPERTY_DISABLE)
4722 {
4723 val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
4724 }
4725
4726 else
4727 {
4728 val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
4729 }
4730
4731 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT1_CTRL,
4732 (uint8_t *)&val->int1_ctrl, 1);
4733 }
4734
4735 if (ret == 0)
4736 {
4737 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MD1_CFG,
4738 (uint8_t *)&val->md1_cfg, 1);
4739 }
4740
4741 if (ret == 0)
4742 {
4743 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
4744 }
4745
4746 if (ret == 0)
4747 {
4748 ret = lsm6dsrx_pin_int2_route_get(ctx, &pin_int2_route);
4749 }
4750
4751 if (ret == 0)
4752 {
4753 if ((pin_int2_route.int2_ctrl.int2_cnt_bdr
4754 | pin_int2_route.int2_ctrl.int2_drdy_g
4755 | pin_int2_route.int2_ctrl.int2_drdy_temp
4756 | pin_int2_route.int2_ctrl.int2_drdy_xl
4757 | pin_int2_route.int2_ctrl.int2_fifo_full
4758 | pin_int2_route.int2_ctrl.int2_fifo_ovr
4759 | pin_int2_route.int2_ctrl.int2_fifo_th
4760 | pin_int2_route.md2_cfg.int2_6d
4761 | pin_int2_route.md2_cfg.int2_double_tap
4762 | pin_int2_route.md2_cfg.int2_ff
4763 | pin_int2_route.md2_cfg.int2_wu
4764 | pin_int2_route.md2_cfg.int2_single_tap
4765 | pin_int2_route.md2_cfg.int2_sleep_change
4766 | val->int1_ctrl.den_drdy_flag
4767 | val->int1_ctrl.int1_boot
4768 | val->int1_ctrl.int1_cnt_bdr
4769 | val->int1_ctrl.int1_drdy_g
4770 | val->int1_ctrl.int1_drdy_xl
4771 | val->int1_ctrl.int1_fifo_full
4772 | val->int1_ctrl.int1_fifo_ovr
4773 | val->int1_ctrl.int1_fifo_th
4774 | val->md1_cfg.int1_shub
4775 | val->md1_cfg.int1_6d
4776 | val->md1_cfg.int1_double_tap
4777 | val->md1_cfg.int1_ff
4778 | val->md1_cfg.int1_wu
4779 | val->md1_cfg.int1_single_tap
4780 | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
4781 {
4782 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
4783 }
4784
4785 else
4786 {
4787 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
4788 }
4789
4790 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG2,
4791 (uint8_t *) &tap_cfg2, 1);
4792 }
4793
4794 return ret;
4795 }
4796
4797 /**
4798 * @brief Select the signal that need to route on int1 pad.[get]
4799 *
4800 * @param ctx read / write interface definitions
4801 * @param val struct of registers: INT1_CTRL, MD1_CFG,
4802 * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B
4803 *
4804 */
lsm6dsrx_pin_int1_route_get(stmdev_ctx_t * ctx,lsm6dsrx_pin_int1_route_t * val)4805 int32_t lsm6dsrx_pin_int1_route_get(stmdev_ctx_t *ctx,
4806 lsm6dsrx_pin_int1_route_t *val)
4807 {
4808 int32_t ret;
4809
4810 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
4811
4812 if (ret == 0)
4813 {
4814 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MLC_INT1,
4815 (uint8_t *)&val->mlc_int1, 1);
4816 }
4817
4818 if (ret == 0)
4819 {
4820 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INT1,
4821 (uint8_t *)&val->emb_func_int1, 1);
4822 }
4823
4824 if (ret == 0)
4825 {
4826 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_INT1_A,
4827 (uint8_t *)&val->fsm_int1_a, 1);
4828 }
4829
4830 if (ret == 0)
4831 {
4832 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_INT1_B,
4833 (uint8_t *)&val->fsm_int1_b, 1);
4834 }
4835
4836 if (ret == 0)
4837 {
4838 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
4839 }
4840
4841 if (ret == 0)
4842 {
4843 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT1_CTRL,
4844 (uint8_t *)&val->int1_ctrl, 1);
4845 }
4846
4847 if (ret == 0)
4848 {
4849 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MD1_CFG,
4850 (uint8_t *)&val->md1_cfg, 1);
4851 }
4852
4853 return ret;
4854 }
4855
4856 /**
4857 * @brief Select the signal that need to route on int2 pad.[set]
4858 *
4859 * @param ctx read / write interface definitions
4860 * @param val union of registers INT2_CTRL, MD2_CFG,
4861 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
4862 *
4863 */
lsm6dsrx_pin_int2_route_set(stmdev_ctx_t * ctx,lsm6dsrx_pin_int2_route_t * val)4864 int32_t lsm6dsrx_pin_int2_route_set(stmdev_ctx_t *ctx,
4865 lsm6dsrx_pin_int2_route_t *val)
4866 {
4867 lsm6dsrx_pin_int1_route_t pin_int1_route;
4868 lsm6dsrx_tap_cfg2_t tap_cfg2;
4869 int32_t ret;
4870
4871 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
4872
4873 if (ret == 0)
4874 {
4875 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MLC_INT2,
4876 (uint8_t *)&val->mlc_int2, 1);
4877 }
4878
4879 if (ret == 0)
4880 {
4881 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_INT2,
4882 (uint8_t *)&val->emb_func_int2, 1);
4883 }
4884
4885 if (ret == 0)
4886 {
4887 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_INT2_A,
4888 (uint8_t *)&val->fsm_int2_a, 1);
4889 }
4890
4891 if (ret == 0)
4892 {
4893 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_INT2_B,
4894 (uint8_t *)&val->fsm_int2_b, 1);
4895 }
4896
4897 if (ret == 0)
4898 {
4899 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
4900 }
4901
4902 if (ret == 0)
4903 {
4904 if ((val->emb_func_int2.int2_fsm_lc
4905 | val->emb_func_int2.int2_sig_mot
4906 | val->emb_func_int2.int2_step_detector
4907 | val->emb_func_int2.int2_tilt
4908 | val->fsm_int2_a.int2_fsm1
4909 | val->fsm_int2_a.int2_fsm2
4910 | val->fsm_int2_a.int2_fsm3
4911 | val->fsm_int2_a.int2_fsm4
4912 | val->fsm_int2_a.int2_fsm5
4913 | val->fsm_int2_a.int2_fsm6
4914 | val->fsm_int2_a.int2_fsm7
4915 | val->fsm_int2_a.int2_fsm8
4916 | val->fsm_int2_b.int2_fsm9
4917 | val->fsm_int2_b.int2_fsm10
4918 | val->fsm_int2_b.int2_fsm11
4919 | val->fsm_int2_b.int2_fsm12
4920 | val->fsm_int2_b.int2_fsm13
4921 | val->fsm_int2_b.int2_fsm14
4922 | val->fsm_int2_b.int2_fsm15
4923 | val->fsm_int2_b.int2_fsm16
4924 | val->mlc_int2.int2_mlc1
4925 | val->mlc_int2.int2_mlc2
4926 | val->mlc_int2.int2_mlc3
4927 | val->mlc_int2.int2_mlc4
4928 | val->mlc_int2.int2_mlc5
4929 | val->mlc_int2.int2_mlc6
4930 | val->mlc_int2.int2_mlc7
4931 | val->mlc_int2.int2_mlc8) != PROPERTY_DISABLE)
4932 {
4933 val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
4934 }
4935
4936 else
4937 {
4938 val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
4939 }
4940
4941 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT2_CTRL,
4942 (uint8_t *)&val->int2_ctrl, 1);
4943 }
4944
4945 if (ret == 0)
4946 {
4947 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MD2_CFG,
4948 (uint8_t *)&val->md2_cfg, 1);
4949 }
4950
4951 if (ret == 0)
4952 {
4953 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
4954 }
4955
4956 if (ret == 0)
4957 {
4958 ret = lsm6dsrx_pin_int1_route_get(ctx, &pin_int1_route);
4959 }
4960
4961 if (ret == 0)
4962 {
4963 if ((val->int2_ctrl.int2_cnt_bdr
4964 | val->int2_ctrl.int2_drdy_g
4965 | val->int2_ctrl.int2_drdy_temp
4966 | val->int2_ctrl.int2_drdy_xl
4967 | val->int2_ctrl.int2_fifo_full
4968 | val->int2_ctrl.int2_fifo_ovr
4969 | val->int2_ctrl.int2_fifo_th
4970 | val->md2_cfg.int2_6d
4971 | val->md2_cfg.int2_double_tap
4972 | val->md2_cfg.int2_ff
4973 | val->md2_cfg.int2_wu
4974 | val->md2_cfg.int2_single_tap
4975 | val->md2_cfg.int2_sleep_change
4976 | pin_int1_route.int1_ctrl.den_drdy_flag
4977 | pin_int1_route.int1_ctrl.int1_boot
4978 | pin_int1_route.int1_ctrl.int1_cnt_bdr
4979 | pin_int1_route.int1_ctrl.int1_drdy_g
4980 | pin_int1_route.int1_ctrl.int1_drdy_xl
4981 | pin_int1_route.int1_ctrl.int1_fifo_full
4982 | pin_int1_route.int1_ctrl.int1_fifo_ovr
4983 | pin_int1_route.int1_ctrl.int1_fifo_th
4984 | pin_int1_route.md1_cfg.int1_6d
4985 | pin_int1_route.md1_cfg.int1_double_tap
4986 | pin_int1_route.md1_cfg.int1_ff
4987 | pin_int1_route.md1_cfg.int1_wu
4988 | pin_int1_route.md1_cfg.int1_single_tap
4989 | pin_int1_route.md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
4990 {
4991 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
4992 }
4993
4994 else
4995 {
4996 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
4997 }
4998
4999 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG2,
5000 (uint8_t *) &tap_cfg2, 1);
5001 }
5002
5003 return ret;
5004 }
5005
5006 /**
5007 * @brief Select the signal that need to route on int2 pad.[get]
5008 *
5009 * @param ctx read / write interface definitions
5010 * @param val union of registers INT2_CTRL, MD2_CFG,
5011 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
5012 *
5013 */
lsm6dsrx_pin_int2_route_get(stmdev_ctx_t * ctx,lsm6dsrx_pin_int2_route_t * val)5014 int32_t lsm6dsrx_pin_int2_route_get(stmdev_ctx_t *ctx,
5015 lsm6dsrx_pin_int2_route_t *val)
5016 {
5017 int32_t ret;
5018
5019 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
5020
5021 if (ret == 0)
5022 {
5023 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MLC_INT2,
5024 (uint8_t *)&val->mlc_int2, 1);
5025 }
5026
5027 if (ret == 0)
5028 {
5029 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INT2,
5030 (uint8_t *)&val->emb_func_int2, 1);
5031 }
5032
5033 if (ret == 0)
5034 {
5035 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_INT2_A,
5036 (uint8_t *)&val->fsm_int2_a, 1);
5037 }
5038
5039 if (ret == 0)
5040 {
5041 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_INT2_B,
5042 (uint8_t *)&val->fsm_int2_b, 1);
5043 }
5044
5045 if (ret == 0)
5046 {
5047 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
5048 }
5049
5050 if (ret == 0)
5051 {
5052 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT2_CTRL,
5053 (uint8_t *)&val->int2_ctrl, 1);
5054 }
5055
5056 if (ret == 0)
5057 {
5058 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MD2_CFG,
5059 (uint8_t *)&val->md2_cfg, 1);
5060 }
5061
5062 return ret;
5063 }
5064
5065 /**
5066 * @brief Push-pull/open drain selection on interrupt pads.[set]
5067 *
5068 * @param ctx Read / write interface definitions.(ptr)
5069 * @param val Change the values of pp_od in reg CTRL3_C
5070 * @retval Interface status (MANDATORY: return 0 -> no Error).
5071 *
5072 */
lsm6dsrx_pin_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_pp_od_t val)5073 int32_t lsm6dsrx_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_pp_od_t val)
5074 {
5075 lsm6dsrx_ctrl3_c_t ctrl3_c;
5076 int32_t ret;
5077
5078 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
5079
5080 if (ret == 0)
5081 {
5082 ctrl3_c.pp_od = (uint8_t)val;
5083 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
5084 }
5085
5086 return ret;
5087 }
5088
5089 /**
5090 * @brief Push-pull/open drain selection on interrupt pads.[get]
5091 *
5092 * @param ctx Read / write interface definitions.(ptr)
5093 * @param val Get the values of pp_od in reg CTRL3_C
5094 * @retval Interface status (MANDATORY: return 0 -> no Error).
5095 *
5096 */
lsm6dsrx_pin_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_pp_od_t * val)5097 int32_t lsm6dsrx_pin_mode_get(stmdev_ctx_t *ctx,
5098 lsm6dsrx_pp_od_t *val)
5099 {
5100 lsm6dsrx_ctrl3_c_t ctrl3_c;
5101 int32_t ret;
5102
5103 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
5104
5105 switch (ctrl3_c.pp_od)
5106 {
5107 case LSM6DSRX_PUSH_PULL:
5108 *val = LSM6DSRX_PUSH_PULL;
5109 break;
5110
5111 case LSM6DSRX_OPEN_DRAIN:
5112 *val = LSM6DSRX_OPEN_DRAIN;
5113 break;
5114
5115 default:
5116 *val = LSM6DSRX_PUSH_PULL;
5117 break;
5118 }
5119
5120 return ret;
5121 }
5122
5123 /**
5124 * @brief Interrupt active-high/low.[set]
5125 *
5126 * @param ctx Read / write interface definitions.(ptr)
5127 * @param val Change the values of h_lactive in reg CTRL3_C
5128 * @retval Interface status (MANDATORY: return 0 -> no Error).
5129 *
5130 */
lsm6dsrx_pin_polarity_set(stmdev_ctx_t * ctx,lsm6dsrx_h_lactive_t val)5131 int32_t lsm6dsrx_pin_polarity_set(stmdev_ctx_t *ctx,
5132 lsm6dsrx_h_lactive_t val)
5133 {
5134 lsm6dsrx_ctrl3_c_t ctrl3_c;
5135 int32_t ret;
5136
5137 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
5138
5139 if (ret == 0)
5140 {
5141 ctrl3_c.h_lactive = (uint8_t)val;
5142 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
5143 }
5144
5145 return ret;
5146 }
5147
5148 /**
5149 * @brief Interrupt active-high/low.[get]
5150 *
5151 * @param ctx Read / write interface definitions.(ptr)
5152 * @param val Get the values of h_lactive in reg CTRL3_C
5153 * @retval Interface status (MANDATORY: return 0 -> no Error).
5154 *
5155 */
lsm6dsrx_pin_polarity_get(stmdev_ctx_t * ctx,lsm6dsrx_h_lactive_t * val)5156 int32_t lsm6dsrx_pin_polarity_get(stmdev_ctx_t *ctx,
5157 lsm6dsrx_h_lactive_t *val)
5158 {
5159 lsm6dsrx_ctrl3_c_t ctrl3_c;
5160 int32_t ret;
5161
5162 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
5163
5164 switch (ctrl3_c.h_lactive)
5165 {
5166 case LSM6DSRX_ACTIVE_HIGH:
5167 *val = LSM6DSRX_ACTIVE_HIGH;
5168 break;
5169
5170 case LSM6DSRX_ACTIVE_LOW:
5171 *val = LSM6DSRX_ACTIVE_LOW;
5172 break;
5173
5174 default:
5175 *val = LSM6DSRX_ACTIVE_HIGH;
5176 break;
5177 }
5178
5179 return ret;
5180 }
5181
5182 /**
5183 * @brief All interrupt signals become available on INT1 pin.[set]
5184 *
5185 * @param ctx Read / write interface definitions.(ptr)
5186 * @param val Change the values of int2_on_int1 in reg CTRL4_C
5187 * @retval Interface status (MANDATORY: return 0 -> no Error).
5188 *
5189 */
lsm6dsrx_all_on_int1_set(stmdev_ctx_t * ctx,uint8_t val)5190 int32_t lsm6dsrx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
5191 {
5192 lsm6dsrx_ctrl4_c_t ctrl4_c;
5193 int32_t ret;
5194
5195 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
5196
5197 if (ret == 0)
5198 {
5199 ctrl4_c.int2_on_int1 = (uint8_t)val;
5200 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
5201 }
5202
5203 return ret;
5204 }
5205
5206 /**
5207 * @brief All interrupt signals become available on INT1 pin.[get]
5208 *
5209 * @param ctx Read / write interface definitions.(ptr)
5210 * @param val Change the values of int2_on_int1 in reg CTRL4_C
5211 * @retval Interface status (MANDATORY: return 0 -> no Error).
5212 *
5213 */
lsm6dsrx_all_on_int1_get(stmdev_ctx_t * ctx,uint8_t * val)5214 int32_t lsm6dsrx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
5215 {
5216 lsm6dsrx_ctrl4_c_t ctrl4_c;
5217 int32_t ret;
5218
5219 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
5220 *val = ctrl4_c.int2_on_int1;
5221
5222 return ret;
5223 }
5224
5225 /**
5226 * @brief All interrupt signals notification mode.[set]
5227 *
5228 * @param ctx Read / write interface definitions.(ptr)
5229 * @param val Change the values of lir in reg TAP_CFG0
5230 * @retval Interface status (MANDATORY: return 0 -> no Error).
5231 *
5232 */
lsm6dsrx_int_notification_set(stmdev_ctx_t * ctx,lsm6dsrx_lir_t val)5233 int32_t lsm6dsrx_int_notification_set(stmdev_ctx_t *ctx,
5234 lsm6dsrx_lir_t val)
5235 {
5236 lsm6dsrx_tap_cfg0_t tap_cfg0;
5237 lsm6dsrx_page_rw_t page_rw;
5238 int32_t ret;
5239
5240 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5241
5242 if (ret == 0)
5243 {
5244 tap_cfg0.lir = (uint8_t)val & 0x01U;
5245 tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
5246 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG0,
5247 (uint8_t *)&tap_cfg0, 1);
5248 }
5249
5250 if (ret == 0)
5251 {
5252 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
5253 }
5254
5255 if (ret == 0)
5256 {
5257 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
5258 }
5259
5260 if (ret == 0)
5261 {
5262 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
5263 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
5264 }
5265
5266 if (ret == 0)
5267 {
5268 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
5269 }
5270
5271 return ret;
5272 }
5273
5274 /**
5275 * @brief All interrupt signals notification mode.[get]
5276 *
5277 * @param ctx Read / write interface definitions.(ptr)
5278 * @param val Get the values of lir in reg TAP_CFG0
5279 * @retval Interface status (MANDATORY: return 0 -> no Error).
5280 *
5281 */
lsm6dsrx_int_notification_get(stmdev_ctx_t * ctx,lsm6dsrx_lir_t * val)5282 int32_t lsm6dsrx_int_notification_get(stmdev_ctx_t *ctx,
5283 lsm6dsrx_lir_t *val)
5284 {
5285 lsm6dsrx_tap_cfg0_t tap_cfg0;
5286 lsm6dsrx_page_rw_t page_rw;
5287 int32_t ret;
5288
5289 *val = LSM6DSRX_ALL_INT_PULSED;
5290 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5291
5292 if (ret == 0)
5293 {
5294 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
5295 }
5296
5297 if (ret == 0)
5298 {
5299 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_PAGE_RW, (uint8_t *)&page_rw, 1);
5300 }
5301
5302 if (ret == 0)
5303 {
5304 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
5305 }
5306
5307 switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir)
5308 {
5309 case LSM6DSRX_ALL_INT_PULSED:
5310 *val = LSM6DSRX_ALL_INT_PULSED;
5311 break;
5312
5313 case LSM6DSRX_BASE_LATCHED_EMB_PULSED:
5314 *val = LSM6DSRX_BASE_LATCHED_EMB_PULSED;
5315 break;
5316
5317 case LSM6DSRX_BASE_PULSED_EMB_LATCHED:
5318 *val = LSM6DSRX_BASE_PULSED_EMB_LATCHED;
5319 break;
5320
5321 case LSM6DSRX_ALL_INT_LATCHED:
5322 *val = LSM6DSRX_ALL_INT_LATCHED;
5323 break;
5324
5325 default:
5326 *val = LSM6DSRX_ALL_INT_PULSED;
5327 break;
5328 }
5329
5330 return ret;
5331 }
5332
5333 /**
5334 * @}
5335 *
5336 */
5337
5338 /**
5339 * @defgroup LSM6DSRX_Wake_Up_event
5340 * @brief This section groups all the functions that manage the
5341 * Wake Up event generation.
5342 * @{
5343 *
5344 */
5345
5346 /**
5347 * @brief Weight of 1 LSB of wakeup threshold.[set]
5348 * 0: 1 LSB =FS_XL / 64
5349 * 1: 1 LSB = FS_XL / 256
5350 *
5351 * @param ctx Read / write interface definitions.(ptr)
5352 * @param val Change the values of wake_ths_w in reg WAKE_UP_DUR
5353 * @retval Interface status (MANDATORY: return 0 -> no Error).
5354 *
5355 */
lsm6dsrx_wkup_ths_weight_set(stmdev_ctx_t * ctx,lsm6dsrx_wake_ths_w_t val)5356 int32_t lsm6dsrx_wkup_ths_weight_set(stmdev_ctx_t *ctx,
5357 lsm6dsrx_wake_ths_w_t val)
5358 {
5359 lsm6dsrx_wake_up_dur_t wake_up_dur;
5360 int32_t ret;
5361
5362 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
5363 (uint8_t *)&wake_up_dur, 1);
5364
5365 if (ret == 0)
5366 {
5367 wake_up_dur.wake_ths_w = (uint8_t)val;
5368 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
5369 (uint8_t *)&wake_up_dur, 1);
5370 }
5371
5372 return ret;
5373 }
5374
5375 /**
5376 * @brief Weight of 1 LSB of wakeup threshold.[get]
5377 * 0: 1 LSB =FS_XL / 64
5378 * 1: 1 LSB = FS_XL / 256
5379 *
5380 * @param ctx Read / write interface definitions.(ptr)
5381 * @param val Get the values of wake_ths_w in reg WAKE_UP_DUR
5382 * @retval Interface status (MANDATORY: return 0 -> no Error).
5383 *
5384 */
lsm6dsrx_wkup_ths_weight_get(stmdev_ctx_t * ctx,lsm6dsrx_wake_ths_w_t * val)5385 int32_t lsm6dsrx_wkup_ths_weight_get(stmdev_ctx_t *ctx,
5386 lsm6dsrx_wake_ths_w_t *val)
5387 {
5388 lsm6dsrx_wake_up_dur_t wake_up_dur;
5389 int32_t ret;
5390
5391 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
5392 (uint8_t *)&wake_up_dur, 1);
5393
5394 switch (wake_up_dur.wake_ths_w)
5395 {
5396 case LSM6DSRX_LSb_FS_DIV_64:
5397 *val = LSM6DSRX_LSb_FS_DIV_64;
5398 break;
5399
5400 case LSM6DSRX_LSb_FS_DIV_256:
5401 *val = LSM6DSRX_LSb_FS_DIV_256;
5402 break;
5403
5404 default:
5405 *val = LSM6DSRX_LSb_FS_DIV_64;
5406 break;
5407 }
5408
5409 return ret;
5410 }
5411
5412 /**
5413 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
5414 * WAKE_UP_DUR.[set]
5415 *
5416 * @param ctx Read / write interface definitions.(ptr)
5417 * @param val Change the values of wk_ths in reg WAKE_UP_THS
5418 * @retval Interface status (MANDATORY: return 0 -> no Error).
5419 *
5420 */
lsm6dsrx_wkup_threshold_set(stmdev_ctx_t * ctx,uint8_t val)5421 int32_t lsm6dsrx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
5422 {
5423 lsm6dsrx_wake_up_ths_t wake_up_ths;
5424 int32_t ret;
5425
5426 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS,
5427 (uint8_t *)&wake_up_ths, 1);
5428
5429 if (ret == 0)
5430 {
5431 wake_up_ths.wk_ths = (uint8_t)val;
5432 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_THS,
5433 (uint8_t *)&wake_up_ths, 1);
5434 }
5435
5436 return ret;
5437 }
5438
5439 /**
5440 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
5441 * WAKE_UP_DUR.[get]
5442 *
5443 * @param ctx Read / write interface definitions.(ptr)
5444 * @param val Change the values of wk_ths in reg WAKE_UP_THS
5445 * @retval Interface status (MANDATORY: return 0 -> no Error).
5446 *
5447 */
lsm6dsrx_wkup_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)5448 int32_t lsm6dsrx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
5449 {
5450 lsm6dsrx_wake_up_ths_t wake_up_ths;
5451 int32_t ret;
5452
5453 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS,
5454 (uint8_t *)&wake_up_ths, 1);
5455 *val = wake_up_ths.wk_ths;
5456
5457 return ret;
5458 }
5459
5460 /**
5461 * @brief Wake up duration event( 1LSb = 1 / ODR ).[set]
5462 *
5463 * @param ctx Read / write interface definitions.(ptr)
5464 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
5465 * @retval Interface status (MANDATORY: return 0 -> no Error).
5466 *
5467 */
lsm6dsrx_xl_usr_offset_on_wkup_set(stmdev_ctx_t * ctx,uint8_t val)5468 int32_t lsm6dsrx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
5469 uint8_t val)
5470 {
5471 lsm6dsrx_wake_up_ths_t wake_up_ths;
5472 int32_t ret;
5473
5474 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS,
5475 (uint8_t *)&wake_up_ths, 1);
5476
5477 if (ret == 0)
5478 {
5479 wake_up_ths.usr_off_on_wu = (uint8_t)val;
5480 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_THS,
5481 (uint8_t *)&wake_up_ths, 1);
5482 }
5483
5484 return ret;
5485 }
5486
5487 /**
5488 * @brief Wake up duration event( 1LSb = 1 / ODR ).[get]
5489 *
5490 * @param ctx Read / write interface definitions.(ptr)
5491 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
5492 * @retval Interface status (MANDATORY: return 0 -> no Error).
5493 *
5494 */
lsm6dsrx_xl_usr_offset_on_wkup_get(stmdev_ctx_t * ctx,uint8_t * val)5495 int32_t lsm6dsrx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
5496 uint8_t *val)
5497 {
5498 lsm6dsrx_wake_up_ths_t wake_up_ths;
5499 int32_t ret;
5500
5501 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS,
5502 (uint8_t *)&wake_up_ths, 1);
5503 *val = wake_up_ths.usr_off_on_wu;
5504
5505 return ret;
5506 }
5507
5508 /**
5509 * @brief Wake up duration event(1LSb = 1 / ODR).[set]
5510 *
5511 * @param ctx Read / write interface definitions.(ptr)
5512 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
5513 * @retval Interface status (MANDATORY: return 0 -> no Error).
5514 *
5515 */
lsm6dsrx_wkup_dur_set(stmdev_ctx_t * ctx,uint8_t val)5516 int32_t lsm6dsrx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
5517 {
5518 lsm6dsrx_wake_up_dur_t wake_up_dur;
5519 int32_t ret;
5520
5521 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
5522 (uint8_t *)&wake_up_dur, 1);
5523
5524 if (ret == 0)
5525 {
5526 wake_up_dur.wake_dur = (uint8_t)val;
5527 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
5528 (uint8_t *)&wake_up_dur, 1);
5529 }
5530
5531 return ret;
5532 }
5533
5534 /**
5535 * @brief Wake up duration event(1LSb = 1 / ODR).[get]
5536 *
5537 * @param ctx Read / write interface definitions.(ptr)
5538 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
5539 * @retval Interface status (MANDATORY: return 0 -> no Error).
5540 *
5541 */
lsm6dsrx_wkup_dur_get(stmdev_ctx_t * ctx,uint8_t * val)5542 int32_t lsm6dsrx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
5543 {
5544 lsm6dsrx_wake_up_dur_t wake_up_dur;
5545 int32_t ret;
5546
5547 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
5548 (uint8_t *)&wake_up_dur, 1);
5549 *val = wake_up_dur.wake_dur;
5550
5551 return ret;
5552 }
5553
5554 /**
5555 * @}
5556 *
5557 */
5558
5559 /**
5560 * @defgroup LSM6DSRX_ Activity/Inactivity_detection
5561 * @brief This section groups all the functions concerning
5562 * activity/inactivity detection.
5563 * @{
5564 *
5565 */
5566
5567 /**
5568 * @brief Enables gyroscope Sleep mode.[set]
5569 *
5570 * @param ctx Read / write interface definitions.(ptr)
5571 * @param val Change the values of sleep_g in reg CTRL4_C
5572 * @retval Interface status (MANDATORY: return 0 -> no Error).
5573 *
5574 */
lsm6dsrx_gy_sleep_mode_set(stmdev_ctx_t * ctx,uint8_t val)5575 int32_t lsm6dsrx_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
5576 {
5577 lsm6dsrx_ctrl4_c_t ctrl4_c;
5578 int32_t ret;
5579
5580 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
5581
5582 if (ret == 0)
5583 {
5584 ctrl4_c.sleep_g = (uint8_t)val;
5585 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
5586 }
5587
5588 return ret;
5589 }
5590
5591 /**
5592 * @brief Enables gyroscope Sleep mode.[get]
5593 *
5594 * @param ctx Read / write interface definitions.(ptr)
5595 * @param val Change the values of sleep_g in reg CTRL4_C
5596 * @retval Interface status (MANDATORY: return 0 -> no Error).
5597 *
5598 */
lsm6dsrx_gy_sleep_mode_get(stmdev_ctx_t * ctx,uint8_t * val)5599 int32_t lsm6dsrx_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
5600 {
5601 lsm6dsrx_ctrl4_c_t ctrl4_c;
5602 int32_t ret;
5603
5604 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
5605 *val = ctrl4_c.sleep_g;
5606
5607 return ret;
5608 }
5609
5610 /**
5611 * @brief Drives the sleep status instead of sleep change on INT pins
5612 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
5613 * are enabled).[set]
5614 *
5615 * @param ctx Read / write interface definitions.(ptr)
5616 * @param val Change the values of sleep_status_on_int in reg TAP_CFG0
5617 * @retval Interface status (MANDATORY: return 0 -> no Error).
5618 *
5619 */
lsm6dsrx_act_pin_notification_set(stmdev_ctx_t * ctx,lsm6dsrx_sleep_status_on_int_t val)5620 int32_t lsm6dsrx_act_pin_notification_set(stmdev_ctx_t *ctx,
5621 lsm6dsrx_sleep_status_on_int_t val)
5622 {
5623 lsm6dsrx_tap_cfg0_t tap_cfg0;
5624 int32_t ret;
5625
5626 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5627
5628 if (ret == 0)
5629 {
5630 tap_cfg0. sleep_status_on_int = (uint8_t)val;
5631 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG0,
5632 (uint8_t *)&tap_cfg0, 1);
5633 }
5634
5635 return ret;
5636 }
5637
5638 /**
5639 * @brief Drives the sleep status instead of sleep change on INT pins
5640 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
5641 * are enabled).[get]
5642 *
5643 * @param ctx Read / write interface definitions.(ptr)
5644 * @param val Get the values of sleep_status_on_int in reg TAP_CFG0
5645 * @retval Interface status (MANDATORY: return 0 -> no Error).
5646 *
5647 */
lsm6dsrx_act_pin_notification_get(stmdev_ctx_t * ctx,lsm6dsrx_sleep_status_on_int_t * val)5648 int32_t lsm6dsrx_act_pin_notification_get(stmdev_ctx_t *ctx,
5649 lsm6dsrx_sleep_status_on_int_t *val)
5650 {
5651 lsm6dsrx_tap_cfg0_t tap_cfg0;
5652 int32_t ret;
5653
5654 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5655
5656 switch (tap_cfg0. sleep_status_on_int)
5657 {
5658 case LSM6DSRX_DRIVE_SLEEP_CHG_EVENT:
5659 *val = LSM6DSRX_DRIVE_SLEEP_CHG_EVENT;
5660 break;
5661
5662 case LSM6DSRX_DRIVE_SLEEP_STATUS:
5663 *val = LSM6DSRX_DRIVE_SLEEP_STATUS;
5664 break;
5665
5666 default:
5667 *val = LSM6DSRX_DRIVE_SLEEP_CHG_EVENT;
5668 break;
5669 }
5670
5671 return ret;
5672 }
5673
5674 /**
5675 * @brief Enable inactivity function.[set]
5676 *
5677 * @param ctx Read / write interface definitions.(ptr)
5678 * @param val Change the values of inact_en in reg TAP_CFG2
5679 * @retval Interface status (MANDATORY: return 0 -> no Error).
5680 *
5681 */
lsm6dsrx_act_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_inact_en_t val)5682 int32_t lsm6dsrx_act_mode_set(stmdev_ctx_t *ctx,
5683 lsm6dsrx_inact_en_t val)
5684 {
5685 lsm6dsrx_tap_cfg2_t tap_cfg2;
5686 int32_t ret;
5687
5688 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
5689
5690 if (ret == 0)
5691 {
5692 tap_cfg2.inact_en = (uint8_t)val;
5693 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
5694 }
5695
5696 return ret;
5697 }
5698
5699 /**
5700 * @brief Enable inactivity function.[get]
5701 *
5702 * @param ctx Read / write interface definitions.(ptr)
5703 * @param val Get the values of inact_en in reg TAP_CFG2
5704 * @retval Interface status (MANDATORY: return 0 -> no Error).
5705 *
5706 */
lsm6dsrx_act_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_inact_en_t * val)5707 int32_t lsm6dsrx_act_mode_get(stmdev_ctx_t *ctx,
5708 lsm6dsrx_inact_en_t *val)
5709 {
5710 lsm6dsrx_tap_cfg2_t tap_cfg2;
5711 int32_t ret;
5712
5713 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
5714
5715 switch (tap_cfg2.inact_en)
5716 {
5717 case LSM6DSRX_XL_AND_GY_NOT_AFFECTED:
5718 *val = LSM6DSRX_XL_AND_GY_NOT_AFFECTED;
5719 break;
5720
5721 case LSM6DSRX_XL_12Hz5_GY_NOT_AFFECTED:
5722 *val = LSM6DSRX_XL_12Hz5_GY_NOT_AFFECTED;
5723 break;
5724
5725 case LSM6DSRX_XL_12Hz5_GY_SLEEP:
5726 *val = LSM6DSRX_XL_12Hz5_GY_SLEEP;
5727 break;
5728
5729 case LSM6DSRX_XL_12Hz5_GY_PD:
5730 *val = LSM6DSRX_XL_12Hz5_GY_PD;
5731 break;
5732
5733 default:
5734 *val = LSM6DSRX_XL_AND_GY_NOT_AFFECTED;
5735 break;
5736 }
5737
5738 return ret;
5739 }
5740
5741 /**
5742 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
5743 *
5744 * @param ctx Read / write interface definitions.(ptr)
5745 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
5746 * @retval Interface status (MANDATORY: return 0 -> no Error).
5747 *
5748 */
lsm6dsrx_act_sleep_dur_set(stmdev_ctx_t * ctx,uint8_t val)5749 int32_t lsm6dsrx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
5750 {
5751 lsm6dsrx_wake_up_dur_t wake_up_dur;
5752 int32_t ret;
5753
5754 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
5755 (uint8_t *)&wake_up_dur, 1);
5756
5757 if (ret == 0)
5758 {
5759 wake_up_dur.sleep_dur = (uint8_t)val;
5760 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
5761 (uint8_t *)&wake_up_dur, 1);
5762 }
5763
5764 return ret;
5765 }
5766
5767 /**
5768 * @brief Duration to go in sleep mode.(1 LSb = 512 / ODR).[get]
5769 *
5770 * @param ctx Read / write interface definitions.(ptr)
5771 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
5772 * @retval Interface status (MANDATORY: return 0 -> no Error).
5773 *
5774 */
lsm6dsrx_act_sleep_dur_get(stmdev_ctx_t * ctx,uint8_t * val)5775 int32_t lsm6dsrx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
5776 {
5777 lsm6dsrx_wake_up_dur_t wake_up_dur;
5778 int32_t ret;
5779
5780 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
5781 (uint8_t *)&wake_up_dur, 1);
5782 *val = wake_up_dur.sleep_dur;
5783
5784 return ret;
5785 }
5786
5787 /**
5788 * @}
5789 *
5790 */
5791
5792 /**
5793 * @defgroup LSM6DSRX_tap_generator
5794 * @brief This section groups all the functions that manage the
5795 * tap and double tap event generation.
5796 * @{
5797 *
5798 */
5799
5800 /**
5801 * @brief Enable Z direction in tap recognition.[set]
5802 *
5803 * @param ctx Read / write interface definitions.(ptr)
5804 * @param val Change the values of tap_z_en in reg TAP_CFG0
5805 * @retval Interface status (MANDATORY: return 0 -> no Error).
5806 *
5807 */
lsm6dsrx_tap_detection_on_z_set(stmdev_ctx_t * ctx,uint8_t val)5808 int32_t lsm6dsrx_tap_detection_on_z_set(stmdev_ctx_t *ctx,
5809 uint8_t val)
5810 {
5811 lsm6dsrx_tap_cfg0_t tap_cfg0;
5812 int32_t ret;
5813
5814 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5815
5816 if (ret == 0)
5817 {
5818 tap_cfg0.tap_z_en = (uint8_t)val;
5819 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG0,
5820 (uint8_t *)&tap_cfg0, 1);
5821 }
5822
5823 return ret;
5824 }
5825
5826 /**
5827 * @brief Enable Z direction in tap recognition.[get]
5828 *
5829 * @param ctx Read / write interface definitions.(ptr)
5830 * @param val Change the values of tap_z_en in reg TAP_CFG0
5831 * @retval Interface status (MANDATORY: return 0 -> no Error).
5832 *
5833 */
lsm6dsrx_tap_detection_on_z_get(stmdev_ctx_t * ctx,uint8_t * val)5834 int32_t lsm6dsrx_tap_detection_on_z_get(stmdev_ctx_t *ctx,
5835 uint8_t *val)
5836 {
5837 lsm6dsrx_tap_cfg0_t tap_cfg0;
5838 int32_t ret;
5839
5840 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5841 *val = tap_cfg0.tap_z_en;
5842
5843 return ret;
5844 }
5845
5846 /**
5847 * @brief Enable Y direction in tap recognition.[set]
5848 *
5849 * @param ctx Read / write interface definitions.(ptr)
5850 * @param val Change the values of tap_y_en in reg TAP_CFG0
5851 * @retval Interface status (MANDATORY: return 0 -> no Error).
5852 *
5853 */
lsm6dsrx_tap_detection_on_y_set(stmdev_ctx_t * ctx,uint8_t val)5854 int32_t lsm6dsrx_tap_detection_on_y_set(stmdev_ctx_t *ctx,
5855 uint8_t val)
5856 {
5857 lsm6dsrx_tap_cfg0_t tap_cfg0;
5858 int32_t ret;
5859
5860 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5861
5862 if (ret == 0)
5863 {
5864 tap_cfg0.tap_y_en = (uint8_t)val;
5865 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG0,
5866 (uint8_t *)&tap_cfg0, 1);
5867 }
5868
5869 return ret;
5870 }
5871
5872 /**
5873 * @brief Enable Y direction in tap recognition.[get]
5874 *
5875 * @param ctx Read / write interface definitions.(ptr)
5876 * @param val Change the values of tap_y_en in reg TAP_CFG0
5877 * @retval Interface status (MANDATORY: return 0 -> no Error).
5878 *
5879 */
lsm6dsrx_tap_detection_on_y_get(stmdev_ctx_t * ctx,uint8_t * val)5880 int32_t lsm6dsrx_tap_detection_on_y_get(stmdev_ctx_t *ctx,
5881 uint8_t *val)
5882 {
5883 lsm6dsrx_tap_cfg0_t tap_cfg0;
5884 int32_t ret;
5885
5886 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5887 *val = tap_cfg0.tap_y_en;
5888
5889 return ret;
5890 }
5891
5892 /**
5893 * @brief Enable X direction in tap recognition.[set]
5894 *
5895 * @param ctx Read / write interface definitions.(ptr)
5896 * @param val Change the values of tap_x_en in reg TAP_CFG0
5897 * @retval Interface status (MANDATORY: return 0 -> no Error).
5898 *
5899 */
lsm6dsrx_tap_detection_on_x_set(stmdev_ctx_t * ctx,uint8_t val)5900 int32_t lsm6dsrx_tap_detection_on_x_set(stmdev_ctx_t *ctx,
5901 uint8_t val)
5902 {
5903 lsm6dsrx_tap_cfg0_t tap_cfg0;
5904 int32_t ret;
5905
5906 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5907
5908 if (ret == 0)
5909 {
5910 tap_cfg0.tap_x_en = (uint8_t)val;
5911 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG0,
5912 (uint8_t *)&tap_cfg0, 1);
5913 }
5914
5915 return ret;
5916 }
5917
5918 /**
5919 * @brief Enable X direction in tap recognition.[get]
5920 *
5921 * @param ctx Read / write interface definitions.(ptr)
5922 * @param val Change the values of tap_x_en in reg TAP_CFG0
5923 * @retval Interface status (MANDATORY: return 0 -> no Error).
5924 *
5925 */
lsm6dsrx_tap_detection_on_x_get(stmdev_ctx_t * ctx,uint8_t * val)5926 int32_t lsm6dsrx_tap_detection_on_x_get(stmdev_ctx_t *ctx,
5927 uint8_t *val)
5928 {
5929 lsm6dsrx_tap_cfg0_t tap_cfg0;
5930 int32_t ret;
5931
5932 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5933 *val = tap_cfg0.tap_x_en;
5934
5935 return ret;
5936 }
5937
5938 /**
5939 * @brief X-axis tap recognition threshold.[set]
5940 *
5941 * @param ctx Read / write interface definitions.(ptr)
5942 * @param val Change the values of tap_ths_x in reg TAP_CFG1
5943 * @retval Interface status (MANDATORY: return 0 -> no Error).
5944 *
5945 */
lsm6dsrx_tap_threshold_x_set(stmdev_ctx_t * ctx,uint8_t val)5946 int32_t lsm6dsrx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
5947 {
5948 lsm6dsrx_tap_cfg1_t tap_cfg1;
5949 int32_t ret;
5950
5951 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
5952
5953 if (ret == 0)
5954 {
5955 tap_cfg1.tap_ths_x = (uint8_t)val;
5956 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG1,
5957 (uint8_t *)&tap_cfg1, 1);
5958 }
5959
5960 return ret;
5961 }
5962
5963 /**
5964 * @brief X-axis tap recognition threshold.[get]
5965 *
5966 * @param ctx Read / write interface definitions.(ptr)
5967 * @param val Change the values of tap_ths_x in reg TAP_CFG1
5968 * @retval Interface status (MANDATORY: return 0 -> no Error).
5969 *
5970 */
lsm6dsrx_tap_threshold_x_get(stmdev_ctx_t * ctx,uint8_t * val)5971 int32_t lsm6dsrx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
5972 {
5973 lsm6dsrx_tap_cfg1_t tap_cfg1;
5974 int32_t ret;
5975
5976 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
5977 *val = tap_cfg1.tap_ths_x;
5978
5979 return ret;
5980 }
5981
5982 /**
5983 * @brief Selection of axis priority for TAP detection.[set]
5984 *
5985 * @param ctx Read / write interface definitions.(ptr)
5986 * @param val Change the values of tap_priority in reg TAP_CFG1
5987 * @retval Interface status (MANDATORY: return 0 -> no Error).
5988 *
5989 */
lsm6dsrx_tap_axis_priority_set(stmdev_ctx_t * ctx,lsm6dsrx_tap_priority_t val)5990 int32_t lsm6dsrx_tap_axis_priority_set(stmdev_ctx_t *ctx,
5991 lsm6dsrx_tap_priority_t val)
5992 {
5993 lsm6dsrx_tap_cfg1_t tap_cfg1;
5994 int32_t ret;
5995
5996 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
5997
5998 if (ret == 0)
5999 {
6000 tap_cfg1.tap_priority = (uint8_t)val;
6001 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
6002 }
6003
6004 return ret;
6005 }
6006
6007 /**
6008 * @brief Selection of axis priority for TAP detection[get]
6009 *
6010 * @param ctx Read / write interface definitions.(ptr)
6011 * @param val Get the values of tap_priority in reg TAP_CFG1
6012 * @retval Interface status (MANDATORY: return 0 -> no Error).
6013 *
6014 */
lsm6dsrx_tap_axis_priority_get(stmdev_ctx_t * ctx,lsm6dsrx_tap_priority_t * val)6015 int32_t lsm6dsrx_tap_axis_priority_get(stmdev_ctx_t *ctx,
6016 lsm6dsrx_tap_priority_t *val)
6017 {
6018 lsm6dsrx_tap_cfg1_t tap_cfg1;
6019 int32_t ret;
6020
6021 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
6022
6023 switch (tap_cfg1.tap_priority)
6024 {
6025 case LSM6DSRX_XYZ:
6026 *val = LSM6DSRX_XYZ;
6027 break;
6028
6029 case LSM6DSRX_YXZ:
6030 *val = LSM6DSRX_YXZ;
6031 break;
6032
6033 case LSM6DSRX_XZY:
6034 *val = LSM6DSRX_XZY;
6035 break;
6036
6037 case LSM6DSRX_ZYX:
6038 *val = LSM6DSRX_ZYX;
6039 break;
6040
6041 case LSM6DSRX_YZX:
6042 *val = LSM6DSRX_YZX;
6043 break;
6044
6045 case LSM6DSRX_ZXY:
6046 *val = LSM6DSRX_ZXY;
6047 break;
6048
6049 default:
6050 *val = LSM6DSRX_XYZ;
6051 break;
6052 }
6053
6054 return ret;
6055 }
6056
6057 /**
6058 * @brief Y-axis tap recognition threshold.[set]
6059 *
6060 * @param ctx Read / write interface definitions.(ptr)
6061 * @param val Change the values of tap_ths_y in reg TAP_CFG2
6062 * @retval Interface status (MANDATORY: return 0 -> no Error).
6063 *
6064 */
lsm6dsrx_tap_threshold_y_set(stmdev_ctx_t * ctx,uint8_t val)6065 int32_t lsm6dsrx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
6066 {
6067 lsm6dsrx_tap_cfg2_t tap_cfg2;
6068 int32_t ret;
6069
6070 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
6071
6072 if (ret == 0)
6073 {
6074 tap_cfg2.tap_ths_y = (uint8_t)val;
6075 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_CFG2,
6076 (uint8_t *)&tap_cfg2, 1);
6077 }
6078
6079 return ret;
6080 }
6081
6082 /**
6083 * @brief Y-axis tap recognition threshold.[get]
6084 *
6085 * @param ctx Read / write interface definitions.(ptr)
6086 * @param val Change the values of tap_ths_y in reg TAP_CFG2
6087 * @retval Interface status (MANDATORY: return 0 -> no Error).
6088 *
6089 */
lsm6dsrx_tap_threshold_y_get(stmdev_ctx_t * ctx,uint8_t * val)6090 int32_t lsm6dsrx_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
6091 {
6092 lsm6dsrx_tap_cfg2_t tap_cfg2;
6093 int32_t ret;
6094
6095 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
6096 *val = tap_cfg2.tap_ths_y;
6097
6098 return ret;
6099 }
6100
6101 /**
6102 * @brief Z-axis recognition threshold.[set]
6103 *
6104 * @param ctx Read / write interface definitions.(ptr)
6105 * @param val Change the values of tap_ths_z in reg TAP_THS_6D
6106 * @retval Interface status (MANDATORY: return 0 -> no Error).
6107 *
6108 */
lsm6dsrx_tap_threshold_z_set(stmdev_ctx_t * ctx,uint8_t val)6109 int32_t lsm6dsrx_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
6110 {
6111 lsm6dsrx_tap_ths_6d_t tap_ths_6d;
6112 int32_t ret;
6113
6114 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D,
6115 (uint8_t *)&tap_ths_6d, 1);
6116
6117 if (ret == 0)
6118 {
6119 tap_ths_6d.tap_ths_z = (uint8_t)val;
6120 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_THS_6D,
6121 (uint8_t *)&tap_ths_6d, 1);
6122 }
6123
6124 return ret;
6125 }
6126
6127 /**
6128 * @brief Z-axis recognition threshold.[get]
6129 *
6130 * @param ctx Read / write interface definitions.(ptr)
6131 * @param val Change the values of tap_ths_z in reg TAP_THS_6D
6132 * @retval Interface status (MANDATORY: return 0 -> no Error).
6133 *
6134 */
lsm6dsrx_tap_threshold_z_get(stmdev_ctx_t * ctx,uint8_t * val)6135 int32_t lsm6dsrx_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
6136 {
6137 lsm6dsrx_tap_ths_6d_t tap_ths_6d;
6138 int32_t ret;
6139
6140 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D,
6141 (uint8_t *)&tap_ths_6d, 1);
6142 *val = tap_ths_6d.tap_ths_z;
6143
6144 return ret;
6145 }
6146
6147 /**
6148 * @brief Maximum duration is the maximum time of an overthreshold signal
6149 * detection to be recognized as a tap event. The default value of
6150 * these bits is 00b which corresponds to 4*ODR_XL time.
6151 * If the SHOCK[1:0] bits are set to a different value, 1LSB
6152 * corresponds to 8*ODR_XL time.[set]
6153 *
6154 * @param ctx Read / write interface definitions.(ptr)
6155 * @param val Change the values of shock in reg INT_DUR2
6156 * @retval Interface status (MANDATORY: return 0 -> no Error).
6157 *
6158 */
lsm6dsrx_tap_shock_set(stmdev_ctx_t * ctx,uint8_t val)6159 int32_t lsm6dsrx_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
6160 {
6161 lsm6dsrx_int_dur2_t int_dur2;
6162 int32_t ret;
6163
6164 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t *)&int_dur2, 1);
6165
6166 if (ret == 0)
6167 {
6168 int_dur2.shock = (uint8_t)val;
6169 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_DUR2,
6170 (uint8_t *)&int_dur2, 1);
6171 }
6172
6173 return ret;
6174 }
6175
6176 /**
6177 * @brief Maximum duration is the maximum time of an overthreshold signal
6178 * detection to be recognized as a tap event. The default value of
6179 * these bits is 00b which corresponds to 4*ODR_XL time.
6180 * If the SHOCK[1:0] bits are set to a different value, 1LSB
6181 * corresponds to 8*ODR_XL time.[get]
6182 *
6183 * @param ctx Read / write interface definitions.(ptr)
6184 * @param val Change the values of shock in reg INT_DUR2
6185 * @retval Interface status (MANDATORY: return 0 -> no Error).
6186 *
6187 */
lsm6dsrx_tap_shock_get(stmdev_ctx_t * ctx,uint8_t * val)6188 int32_t lsm6dsrx_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
6189 {
6190 lsm6dsrx_int_dur2_t int_dur2;
6191 int32_t ret;
6192
6193 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t *)&int_dur2, 1);
6194 *val = int_dur2.shock;
6195
6196 return ret;
6197 }
6198
6199 /**
6200 * @brief Quiet time is the time after the first detected tap in which
6201 * there must not be any overthreshold event.
6202 * The default value of these bits is 00b which corresponds to
6203 * 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
6204 * value, 1LSB corresponds to 4*ODR_XL time.[set]
6205 *
6206 * @param ctx Read / write interface definitions.(ptr)
6207 * @param val Change the values of quiet in reg INT_DUR2
6208 * @retval Interface status (MANDATORY: return 0 -> no Error).
6209 *
6210 */
lsm6dsrx_tap_quiet_set(stmdev_ctx_t * ctx,uint8_t val)6211 int32_t lsm6dsrx_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
6212 {
6213 lsm6dsrx_int_dur2_t int_dur2;
6214 int32_t ret;
6215
6216 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t *)&int_dur2, 1);
6217
6218 if (ret == 0)
6219 {
6220 int_dur2.quiet = (uint8_t)val;
6221 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_DUR2,
6222 (uint8_t *)&int_dur2, 1);
6223 }
6224
6225 return ret;
6226 }
6227
6228 /**
6229 * @brief Quiet time is the time after the first detected tap in which
6230 * there must not be any overthreshold event.
6231 * The default value of these bits is 00b which corresponds to
6232 * 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
6233 * value, 1LSB corresponds to 4*ODR_XL time.[get]
6234 *
6235 * @param ctx Read / write interface definitions.(ptr)
6236 * @param val Change the values of quiet in reg INT_DUR2
6237 * @retval Interface status (MANDATORY: return 0 -> no Error).
6238 *
6239 */
lsm6dsrx_tap_quiet_get(stmdev_ctx_t * ctx,uint8_t * val)6240 int32_t lsm6dsrx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
6241 {
6242 lsm6dsrx_int_dur2_t int_dur2;
6243 int32_t ret;
6244
6245 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t *)&int_dur2, 1);
6246 *val = int_dur2.quiet;
6247
6248 return ret;
6249 }
6250
6251 /**
6252 * @brief When double tap recognition is enabled, this register expresses
6253 * the maximum time between two consecutive detected taps to
6254 * determine a double tap event.
6255 * The default value of these bits is 0000b which corresponds to
6256 * 16*ODR_XL time.
6257 * If the DUR[3:0] bits are set to a different value, 1LSB
6258 * corresponds to 32*ODR_XL time.[set]
6259 *
6260 * @param ctx Read / write interface definitions.(ptr)
6261 * @param val Change the values of dur in reg INT_DUR2
6262 * @retval Interface status (MANDATORY: return 0 -> no Error).
6263 *
6264 */
lsm6dsrx_tap_dur_set(stmdev_ctx_t * ctx,uint8_t val)6265 int32_t lsm6dsrx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
6266 {
6267 lsm6dsrx_int_dur2_t int_dur2;
6268 int32_t ret;
6269
6270 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t *)&int_dur2, 1);
6271
6272 if (ret == 0)
6273 {
6274 int_dur2.dur = (uint8_t)val;
6275 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_INT_DUR2,
6276 (uint8_t *)&int_dur2, 1);
6277 }
6278
6279 return ret;
6280 }
6281
6282 /**
6283 * @brief When double tap recognition is enabled, this register expresses the
6284 * maximum time between two consecutive detected taps to determine
6285 * a double tap event. The default value of these bits is 0000b which
6286 * corresponds to 16*ODR_XL time. If the DUR[3:0] bits are set to
6287 * a different value, 1LSB corresponds to 32*ODR_XL time.[get]
6288 *
6289 * @param ctx Read / write interface definitions.(ptr)
6290 * @param val Change the values of dur in reg INT_DUR2
6291 * @retval Interface status (MANDATORY: return 0 -> no Error).
6292 *
6293 */
lsm6dsrx_tap_dur_get(stmdev_ctx_t * ctx,uint8_t * val)6294 int32_t lsm6dsrx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
6295 {
6296 lsm6dsrx_int_dur2_t int_dur2;
6297 int32_t ret;
6298
6299 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_INT_DUR2, (uint8_t *)&int_dur2, 1);
6300 *val = int_dur2.dur;
6301
6302 return ret;
6303 }
6304
6305 /**
6306 * @brief Single/double-tap event enable.[set]
6307 *
6308 * @param ctx Read / write interface definitions.(ptr)
6309 * @param val Change the values of single_double_tap in reg WAKE_UP_THS
6310 * @retval Interface status (MANDATORY: return 0 -> no Error).
6311 *
6312 */
lsm6dsrx_tap_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_single_double_tap_t val)6313 int32_t lsm6dsrx_tap_mode_set(stmdev_ctx_t *ctx,
6314 lsm6dsrx_single_double_tap_t val)
6315 {
6316 lsm6dsrx_wake_up_ths_t wake_up_ths;
6317 int32_t ret;
6318
6319 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS,
6320 (uint8_t *)&wake_up_ths, 1);
6321
6322 if (ret == 0)
6323 {
6324 wake_up_ths.single_double_tap = (uint8_t)val;
6325 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_THS,
6326 (uint8_t *)&wake_up_ths, 1);
6327 }
6328
6329 return ret;
6330 }
6331
6332 /**
6333 * @brief Single/double-tap event enable.[get]
6334 *
6335 * @param ctx Read / write interface definitions.(ptr)
6336 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
6337 * @retval Interface status (MANDATORY: return 0 -> no Error).
6338 *
6339 */
lsm6dsrx_tap_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_single_double_tap_t * val)6340 int32_t lsm6dsrx_tap_mode_get(stmdev_ctx_t *ctx,
6341 lsm6dsrx_single_double_tap_t *val)
6342 {
6343 lsm6dsrx_wake_up_ths_t wake_up_ths;
6344 int32_t ret;
6345
6346 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_THS,
6347 (uint8_t *)&wake_up_ths, 1);
6348
6349 switch (wake_up_ths.single_double_tap)
6350 {
6351 case LSM6DSRX_ONLY_SINGLE:
6352 *val = LSM6DSRX_ONLY_SINGLE;
6353 break;
6354
6355 case LSM6DSRX_BOTH_SINGLE_DOUBLE:
6356 *val = LSM6DSRX_BOTH_SINGLE_DOUBLE;
6357 break;
6358
6359 default:
6360 *val = LSM6DSRX_ONLY_SINGLE;
6361 break;
6362 }
6363
6364 return ret;
6365 }
6366
6367 /**
6368 * @}
6369 *
6370 */
6371
6372 /**
6373 * @defgroup LSM6DSRX_ Six_position_detection(6D/4D)
6374 * @brief This section groups all the functions concerning six
6375 * position detection (6D).
6376 * @{
6377 *
6378 */
6379
6380 /**
6381 * @brief Threshold for 4D/6D function.[set]
6382 *
6383 * @param ctx Read / write interface definitions.(ptr)
6384 * @param val Change the values of sixd_ths in reg TAP_THS_6D
6385 * @retval Interface status (MANDATORY: return 0 -> no Error).
6386 *
6387 */
lsm6dsrx_6d_threshold_set(stmdev_ctx_t * ctx,lsm6dsrx_sixd_ths_t val)6388 int32_t lsm6dsrx_6d_threshold_set(stmdev_ctx_t *ctx,
6389 lsm6dsrx_sixd_ths_t val)
6390 {
6391 lsm6dsrx_tap_ths_6d_t tap_ths_6d;
6392 int32_t ret;
6393
6394 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D,
6395 (uint8_t *)&tap_ths_6d, 1);
6396
6397 if (ret == 0)
6398 {
6399 tap_ths_6d.sixd_ths = (uint8_t)val;
6400 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_THS_6D,
6401 (uint8_t *)&tap_ths_6d, 1);
6402 }
6403
6404 return ret;
6405 }
6406
6407 /**
6408 * @brief Threshold for 4D/6D function.[get]
6409 *
6410 * @param ctx Read / write interface definitions.(ptr)
6411 * @param val Get the values of sixd_ths in reg TAP_THS_6D
6412 * @retval Interface status (MANDATORY: return 0 -> no Error).
6413 *
6414 */
lsm6dsrx_6d_threshold_get(stmdev_ctx_t * ctx,lsm6dsrx_sixd_ths_t * val)6415 int32_t lsm6dsrx_6d_threshold_get(stmdev_ctx_t *ctx,
6416 lsm6dsrx_sixd_ths_t *val)
6417 {
6418 lsm6dsrx_tap_ths_6d_t tap_ths_6d;
6419 int32_t ret;
6420
6421 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D,
6422 (uint8_t *)&tap_ths_6d, 1);
6423
6424 switch (tap_ths_6d.sixd_ths)
6425 {
6426 case LSM6DSRX_DEG_80:
6427 *val = LSM6DSRX_DEG_80;
6428 break;
6429
6430 case LSM6DSRX_DEG_70:
6431 *val = LSM6DSRX_DEG_70;
6432 break;
6433
6434 case LSM6DSRX_DEG_60:
6435 *val = LSM6DSRX_DEG_60;
6436 break;
6437
6438 case LSM6DSRX_DEG_50:
6439 *val = LSM6DSRX_DEG_50;
6440 break;
6441
6442 default:
6443 *val = LSM6DSRX_DEG_80;
6444 break;
6445 }
6446
6447 return ret;
6448 }
6449
6450 /**
6451 * @brief 4D orientation detection enable.[set]
6452 *
6453 * @param ctx Read / write interface definitions.(ptr)
6454 * @param val Change the values of d4d_en in reg TAP_THS_6D
6455 * @retval Interface status (MANDATORY: return 0 -> no Error).
6456 *
6457 */
lsm6dsrx_4d_mode_set(stmdev_ctx_t * ctx,uint8_t val)6458 int32_t lsm6dsrx_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
6459 {
6460 lsm6dsrx_tap_ths_6d_t tap_ths_6d;
6461 int32_t ret;
6462
6463 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D,
6464 (uint8_t *)&tap_ths_6d, 1);
6465
6466 if (ret == 0)
6467 {
6468 tap_ths_6d.d4d_en = (uint8_t)val;
6469 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_TAP_THS_6D,
6470 (uint8_t *)&tap_ths_6d, 1);
6471 }
6472
6473 return ret;
6474 }
6475
6476 /**
6477 * @brief 4D orientation detection enable.[get]
6478 *
6479 * @param ctx Read / write interface definitions.(ptr)
6480 * @param val Change the values of d4d_en in reg TAP_THS_6D
6481 * @retval Interface status (MANDATORY: return 0 -> no Error).
6482 *
6483 */
lsm6dsrx_4d_mode_get(stmdev_ctx_t * ctx,uint8_t * val)6484 int32_t lsm6dsrx_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
6485 {
6486 lsm6dsrx_tap_ths_6d_t tap_ths_6d;
6487 int32_t ret;
6488
6489 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_TAP_THS_6D,
6490 (uint8_t *)&tap_ths_6d, 1);
6491 *val = tap_ths_6d.d4d_en;
6492
6493 return ret;
6494 }
6495
6496 /**
6497 * @}
6498 *
6499 */
6500
6501 /**
6502 * @defgroup LSM6DSRX_free_fall
6503 * @brief This section group all the functions concerning the free
6504 * fall detection.
6505 * @{
6506 *
6507 */
6508
6509 /**
6510 * @brief Free fall threshold setting.[set]
6511 *
6512 * @param ctx Read / write interface definitions.(ptr)
6513 * @param val Change the values of ff_ths in reg FREE_FALL
6514 * @retval Interface status (MANDATORY: return 0 -> no Error).
6515 *
6516 */
lsm6dsrx_ff_threshold_set(stmdev_ctx_t * ctx,lsm6dsrx_ff_ths_t val)6517 int32_t lsm6dsrx_ff_threshold_set(stmdev_ctx_t *ctx,
6518 lsm6dsrx_ff_ths_t val)
6519 {
6520 lsm6dsrx_free_fall_t free_fall;
6521 int32_t ret;
6522
6523 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FREE_FALL,
6524 (uint8_t *)&free_fall, 1);
6525
6526 if (ret == 0)
6527 {
6528 free_fall.ff_ths = (uint8_t)val;
6529 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FREE_FALL,
6530 (uint8_t *)&free_fall, 1);
6531 }
6532
6533 return ret;
6534 }
6535
6536 /**
6537 * @brief Free fall threshold setting.[get]
6538 *
6539 * @param ctx Read / write interface definitions.(ptr)
6540 * @param val Get the values of ff_ths in reg FREE_FALL
6541 * @retval Interface status (MANDATORY: return 0 -> no Error).
6542 *
6543 */
lsm6dsrx_ff_threshold_get(stmdev_ctx_t * ctx,lsm6dsrx_ff_ths_t * val)6544 int32_t lsm6dsrx_ff_threshold_get(stmdev_ctx_t *ctx,
6545 lsm6dsrx_ff_ths_t *val)
6546 {
6547 lsm6dsrx_free_fall_t free_fall;
6548 int32_t ret;
6549
6550 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FREE_FALL,
6551 (uint8_t *)&free_fall, 1);
6552
6553 switch (free_fall.ff_ths)
6554 {
6555 case LSM6DSRX_FF_TSH_156mg:
6556 *val = LSM6DSRX_FF_TSH_156mg;
6557 break;
6558
6559 case LSM6DSRX_FF_TSH_219mg:
6560 *val = LSM6DSRX_FF_TSH_219mg;
6561 break;
6562
6563 case LSM6DSRX_FF_TSH_250mg:
6564 *val = LSM6DSRX_FF_TSH_250mg;
6565 break;
6566
6567 case LSM6DSRX_FF_TSH_312mg:
6568 *val = LSM6DSRX_FF_TSH_312mg;
6569 break;
6570
6571 case LSM6DSRX_FF_TSH_344mg:
6572 *val = LSM6DSRX_FF_TSH_344mg;
6573 break;
6574
6575 case LSM6DSRX_FF_TSH_406mg:
6576 *val = LSM6DSRX_FF_TSH_406mg;
6577 break;
6578
6579 case LSM6DSRX_FF_TSH_469mg:
6580 *val = LSM6DSRX_FF_TSH_469mg;
6581 break;
6582
6583 case LSM6DSRX_FF_TSH_500mg:
6584 *val = LSM6DSRX_FF_TSH_500mg;
6585 break;
6586
6587 default:
6588 *val = LSM6DSRX_FF_TSH_156mg;
6589 break;
6590 }
6591
6592 return ret;
6593 }
6594
6595 /**
6596 * @brief Free-fall duration event(1LSb = 1 / ODR).[set]
6597 *
6598 * @param ctx Read / write interface definitions.(ptr)
6599 * @param val Change the values of ff_dur in reg FREE_FALL
6600 * @retval Interface status (MANDATORY: return 0 -> no Error).
6601 *
6602 */
lsm6dsrx_ff_dur_set(stmdev_ctx_t * ctx,uint8_t val)6603 int32_t lsm6dsrx_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
6604 {
6605 lsm6dsrx_wake_up_dur_t wake_up_dur;
6606 lsm6dsrx_free_fall_t free_fall;
6607 int32_t ret;
6608
6609 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
6610 (uint8_t *)&wake_up_dur, 1);
6611
6612 if (ret == 0)
6613 {
6614 wake_up_dur.ff_dur = (val & 0x20U) >> 5;
6615 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
6616 (uint8_t *)&wake_up_dur, 1);
6617 }
6618
6619 if (ret == 0)
6620 {
6621 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FREE_FALL,
6622 (uint8_t *)&free_fall, 1);
6623 }
6624
6625 if (ret == 0)
6626 {
6627 free_fall.ff_dur = val & 0x1FU;
6628 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FREE_FALL,
6629 (uint8_t *)&free_fall, 1);
6630 }
6631
6632 return ret;
6633 }
6634
6635 /**
6636 * @brief Free-fall duration event(1LSb = 1 / ODR).[get]
6637 *
6638 * @param ctx Read / write interface definitions.(ptr)
6639 * @param val Change the values of ff_dur in reg FREE_FALL
6640 * @retval Interface status (MANDATORY: return 0 -> no Error).
6641 *
6642 */
lsm6dsrx_ff_dur_get(stmdev_ctx_t * ctx,uint8_t * val)6643 int32_t lsm6dsrx_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
6644 {
6645 lsm6dsrx_wake_up_dur_t wake_up_dur;
6646 lsm6dsrx_free_fall_t free_fall;
6647 int32_t ret;
6648
6649 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_WAKE_UP_DUR,
6650 (uint8_t *)&wake_up_dur, 1);
6651
6652 if (ret == 0)
6653 {
6654 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FREE_FALL,
6655 (uint8_t *)&free_fall, 1);
6656 }
6657
6658 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
6659
6660 return ret;
6661 }
6662
6663 /**
6664 * @}
6665 *
6666 */
6667
6668 /**
6669 * @defgroup LSM6DSRX_fifo
6670 * @brief This section group all the functions concerning
6671 * the fifo usage
6672 * @{
6673 *
6674 */
6675
6676 /**
6677 * @brief FIFO watermark level selection.[set]
6678 *
6679 * @param ctx Read / write interface definitions.(ptr)
6680 * @param val Change the values of wtm in reg FIFO_CTRL1
6681 * @retval Interface status (MANDATORY: return 0 -> no Error).
6682 *
6683 */
lsm6dsrx_fifo_watermark_set(stmdev_ctx_t * ctx,uint16_t val)6684 int32_t lsm6dsrx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
6685 {
6686 lsm6dsrx_fifo_ctrl1_t fifo_ctrl1;
6687 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
6688 int32_t ret;
6689
6690 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
6691 (uint8_t *)&fifo_ctrl2, 1);
6692
6693 if (ret == 0)
6694 {
6695 fifo_ctrl2.wtm = (uint8_t)((val / 256U) & 0x01U);
6696 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL2,
6697 (uint8_t *)&fifo_ctrl2, 1);
6698 }
6699
6700 if (ret == 0)
6701 {
6702 fifo_ctrl1.wtm = (uint8_t)(val - (fifo_ctrl2.wtm * 256U));
6703 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL1,
6704 (uint8_t *)&fifo_ctrl1, 1);
6705 }
6706
6707 return ret;
6708 }
6709
6710 /**
6711 * @brief FIFO watermark level selection.[get]
6712 *
6713 * @param ctx Read / write interface definitions.(ptr)
6714 * @param val Change the values of wtm in reg FIFO_CTRL1
6715 * @retval Interface status (MANDATORY: return 0 -> no Error).
6716 *
6717 */
lsm6dsrx_fifo_watermark_get(stmdev_ctx_t * ctx,uint16_t * val)6718 int32_t lsm6dsrx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
6719 {
6720 lsm6dsrx_fifo_ctrl1_t fifo_ctrl1;
6721 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
6722 int32_t ret;
6723
6724 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
6725 (uint8_t *)&fifo_ctrl2, 1);
6726
6727 if (ret == 0)
6728 {
6729 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL1,
6730 (uint8_t *)&fifo_ctrl1, 1);
6731 }
6732
6733 *val = fifo_ctrl2.wtm;
6734 *val = (*val * 256U) + fifo_ctrl1.wtm;
6735
6736 return ret;
6737 }
6738
6739 /**
6740 * @brief FIFO compression feature initialization request.[set].
6741 *
6742 * @param ctx Read / write interface definitions.(ptr)
6743 * @param val Change the values of FIFO_COMPR_INIT in reg EMB_FUNC_INIT_B
6744 * @retval Interface status (MANDATORY: return 0 -> no Error).
6745 *
6746 */
lsm6dsrx_compression_algo_init_set(stmdev_ctx_t * ctx,uint8_t val)6747 int32_t lsm6dsrx_compression_algo_init_set(stmdev_ctx_t *ctx,
6748 uint8_t val)
6749 {
6750 lsm6dsrx_emb_func_init_b_t emb_func_init_b;
6751 int32_t ret;
6752
6753 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
6754
6755 if (ret == 0)
6756 {
6757 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
6758 (uint8_t *)&emb_func_init_b, 1);
6759 }
6760
6761 if (ret == 0)
6762 {
6763 emb_func_init_b.fifo_compr_init = (uint8_t)val;
6764 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
6765 (uint8_t *)&emb_func_init_b, 1);
6766 }
6767
6768 if (ret == 0)
6769 {
6770 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
6771 }
6772
6773 return ret;
6774 }
6775
6776 /**
6777 * @brief FIFO compression feature initialization request.[get].
6778 *
6779 * @param ctx Read / write interface definitions.(ptr)
6780 * @param val change the values of FIFO_COMPR_INIT in
6781 * reg EMB_FUNC_INIT_B
6782 * @retval Interface status (MANDATORY: return 0 -> no Error).
6783 *
6784 */
lsm6dsrx_compression_algo_init_get(stmdev_ctx_t * ctx,uint8_t * val)6785 int32_t lsm6dsrx_compression_algo_init_get(stmdev_ctx_t *ctx,
6786 uint8_t *val)
6787 {
6788 lsm6dsrx_emb_func_init_b_t emb_func_init_b;
6789 int32_t ret;
6790
6791 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
6792
6793 if (ret == 0)
6794 {
6795 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
6796 (uint8_t *)&emb_func_init_b, 1);
6797 }
6798
6799 if (ret == 0)
6800 {
6801 *val = emb_func_init_b.fifo_compr_init;
6802 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
6803 }
6804
6805 return ret;
6806 }
6807
6808 /**
6809 * @brief Enable and configure compression algo.[set]
6810 *
6811 * @param ctx Read / write interface definitions.(ptr)
6812 * @param val Change the values of uncoptr_rate in reg FIFO_CTRL2
6813 * @retval Interface status (MANDATORY: return 0 -> no Error).
6814 *
6815 */
lsm6dsrx_compression_algo_set(stmdev_ctx_t * ctx,lsm6dsrx_uncoptr_rate_t val)6816 int32_t lsm6dsrx_compression_algo_set(stmdev_ctx_t *ctx,
6817 lsm6dsrx_uncoptr_rate_t val)
6818 {
6819 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
6820 lsm6dsrx_emb_func_en_b_t emb_func_en_b;
6821 int32_t ret;
6822
6823 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
6824
6825 if (ret == 0)
6826 {
6827 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
6828 (uint8_t *)&emb_func_en_b, 1);
6829 }
6830
6831 if (ret == 0)
6832 {
6833 emb_func_en_b.fifo_compr_en = ((uint8_t)val & 0x04U) >> 2;
6834 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
6835 (uint8_t *)&emb_func_en_b, 1);
6836 }
6837
6838 if (ret == 0)
6839 {
6840 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
6841 }
6842
6843 if (ret == 0)
6844 {
6845 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
6846 (uint8_t *)&fifo_ctrl2, 1);
6847 }
6848
6849 if (ret == 0)
6850 {
6851 fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
6852 fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
6853 }
6854
6855 if (ret == 0)
6856 {
6857 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL2,
6858 (uint8_t *)&fifo_ctrl2, 1);
6859 }
6860
6861 return ret;
6862 }
6863
6864 /**
6865 * @brief Enable and configure compression algo.[get]
6866 *
6867 * @param ctx Read / write interface definitions.(ptr)
6868 * @param val Get the values of uncoptr_rate in reg FIFO_CTRL2
6869 * @retval Interface status (MANDATORY: return 0 -> no Error).
6870 *
6871 */
lsm6dsrx_compression_algo_get(stmdev_ctx_t * ctx,lsm6dsrx_uncoptr_rate_t * val)6872 int32_t lsm6dsrx_compression_algo_get(stmdev_ctx_t *ctx,
6873 lsm6dsrx_uncoptr_rate_t *val)
6874 {
6875 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
6876 int32_t ret;
6877
6878 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
6879 (uint8_t *)&fifo_ctrl2, 1);
6880
6881 switch ((fifo_ctrl2.fifo_compr_rt_en << 2) +
6882 fifo_ctrl2.uncoptr_rate)
6883 {
6884 case LSM6DSRX_CMP_DISABLE:
6885 *val = LSM6DSRX_CMP_DISABLE;
6886 break;
6887
6888 case LSM6DSRX_CMP_ALWAYS:
6889 *val = LSM6DSRX_CMP_ALWAYS;
6890 break;
6891
6892 case LSM6DSRX_CMP_8_TO_1:
6893 *val = LSM6DSRX_CMP_8_TO_1;
6894 break;
6895
6896 case LSM6DSRX_CMP_16_TO_1:
6897 *val = LSM6DSRX_CMP_16_TO_1;
6898 break;
6899
6900 case LSM6DSRX_CMP_32_TO_1:
6901 *val = LSM6DSRX_CMP_32_TO_1;
6902 break;
6903
6904 default:
6905 *val = LSM6DSRX_CMP_DISABLE;
6906 break;
6907 }
6908
6909 return ret;
6910 }
6911
6912 /**
6913 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
6914 *
6915 * @param ctx Read / write interface definitions.(ptr)
6916 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
6917 * @retval Interface status (MANDATORY: return 0 -> no Error).
6918 *
6919 */
lsm6dsrx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t * ctx,uint8_t val)6920 int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
6921 uint8_t val)
6922 {
6923 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
6924 int32_t ret;
6925
6926 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
6927 (uint8_t *)&fifo_ctrl2, 1);
6928
6929 if (ret == 0)
6930 {
6931 fifo_ctrl2.odrchg_en = (uint8_t)val;
6932 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL2,
6933 (uint8_t *)&fifo_ctrl2, 1);
6934 }
6935
6936 return ret;
6937 }
6938
6939 /**
6940 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
6941 *
6942 * @param ctx Read / write interface definitions.(ptr)
6943 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
6944 * @retval Interface status (MANDATORY: return 0 -> no Error).
6945 *
6946 */
lsm6dsrx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t * ctx,uint8_t * val)6947 int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
6948 uint8_t *val)
6949 {
6950 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
6951 int32_t ret;
6952
6953 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
6954 (uint8_t *)&fifo_ctrl2, 1);
6955 *val = fifo_ctrl2.odrchg_en;
6956
6957 return ret;
6958 }
6959
6960 /**
6961 * @brief Enables/Disables compression algorithm runtime[set]
6962 *
6963 * @param ctx Read / write interface definitions.(ptr)
6964 * @param val Change the values of fifo_compr_rt_en in reg FIFO_CTRL2
6965 * @retval Interface status (MANDATORY: return 0 -> no Error).
6966 *
6967 */
lsm6dsrx_compression_algo_real_time_set(stmdev_ctx_t * ctx,uint8_t val)6968 int32_t lsm6dsrx_compression_algo_real_time_set(stmdev_ctx_t *ctx,
6969 uint8_t val)
6970 {
6971 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
6972 int32_t ret;
6973
6974 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
6975 (uint8_t *)&fifo_ctrl2, 1);
6976
6977 if (ret == 0)
6978 {
6979 fifo_ctrl2.fifo_compr_rt_en = (uint8_t)val;
6980 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL2,
6981 (uint8_t *)&fifo_ctrl2, 1);
6982 }
6983
6984 return ret;
6985 }
6986
6987 /**
6988 * @brief Enables/Disables compression algorithm runtime.[get]
6989 *
6990 * @param ctx Read / write interface definitions.(ptr)
6991 * @param val Change the values of fifo_compr_rt_en in reg FIFO_CTRL2
6992 * @retval Interface status (MANDATORY: return 0 -> no Error).
6993 *
6994 */
lsm6dsrx_compression_algo_real_time_get(stmdev_ctx_t * ctx,uint8_t * val)6995 int32_t lsm6dsrx_compression_algo_real_time_get(stmdev_ctx_t *ctx,
6996 uint8_t *val)
6997 {
6998 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
6999 int32_t ret;
7000
7001 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
7002 (uint8_t *)&fifo_ctrl2, 1);
7003 *val = fifo_ctrl2.fifo_compr_rt_en;
7004
7005 return ret;
7006 }
7007
7008 /**
7009 * @brief Sensing chain FIFO stop values memorization at threshold
7010 * level.[set]
7011 *
7012 * @param ctx Read / write interface definitions.(ptr)
7013 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
7014 * @retval Interface status (MANDATORY: return 0 -> no Error).
7015 *
7016 */
lsm6dsrx_fifo_stop_on_wtm_set(stmdev_ctx_t * ctx,uint8_t val)7017 int32_t lsm6dsrx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
7018 {
7019 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
7020 int32_t ret;
7021
7022 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
7023 (uint8_t *)&fifo_ctrl2, 1);
7024
7025 if (ret == 0)
7026 {
7027 fifo_ctrl2.stop_on_wtm = (uint8_t)val;
7028 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL2,
7029 (uint8_t *)&fifo_ctrl2, 1);
7030 }
7031
7032 return ret;
7033 }
7034
7035 /**
7036 * @brief Sensing chain FIFO stop values memorization at threshold
7037 * level.[get]
7038 *
7039 * @param ctx Read / write interface definitions.(ptr)
7040 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
7041 * @retval Interface status (MANDATORY: return 0 -> no Error).
7042 *
7043 */
lsm6dsrx_fifo_stop_on_wtm_get(stmdev_ctx_t * ctx,uint8_t * val)7044 int32_t lsm6dsrx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
7045 {
7046 lsm6dsrx_fifo_ctrl2_t fifo_ctrl2;
7047 int32_t ret;
7048
7049 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL2,
7050 (uint8_t *)&fifo_ctrl2, 1);
7051 *val = fifo_ctrl2.stop_on_wtm;
7052
7053 return ret;
7054 }
7055
7056 /**
7057 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7058 * for accelerometer data.[set]
7059 *
7060 * @param ctx Read / write interface definitions.(ptr)
7061 * @param val Change the values of bdr_xl in reg FIFO_CTRL3
7062 * @retval Interface status (MANDATORY: return 0 -> no Error).
7063 *
7064 */
lsm6dsrx_fifo_xl_batch_set(stmdev_ctx_t * ctx,lsm6dsrx_bdr_xl_t val)7065 int32_t lsm6dsrx_fifo_xl_batch_set(stmdev_ctx_t *ctx,
7066 lsm6dsrx_bdr_xl_t val)
7067 {
7068 lsm6dsrx_fifo_ctrl3_t fifo_ctrl3;
7069 int32_t ret;
7070
7071 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL3,
7072 (uint8_t *)&fifo_ctrl3, 1);
7073
7074 if (ret == 0)
7075 {
7076 fifo_ctrl3.bdr_xl = (uint8_t)val;
7077 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL3,
7078 (uint8_t *)&fifo_ctrl3, 1);
7079 }
7080
7081 return ret;
7082 }
7083
7084 /**
7085 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7086 * for accelerometer data.[get]
7087 *
7088 * @param ctx Read / write interface definitions.(ptr)
7089 * @param val Get the values of bdr_xl in reg FIFO_CTRL3
7090 * @retval Interface status (MANDATORY: return 0 -> no Error).
7091 *
7092 */
lsm6dsrx_fifo_xl_batch_get(stmdev_ctx_t * ctx,lsm6dsrx_bdr_xl_t * val)7093 int32_t lsm6dsrx_fifo_xl_batch_get(stmdev_ctx_t *ctx,
7094 lsm6dsrx_bdr_xl_t *val)
7095 {
7096 lsm6dsrx_fifo_ctrl3_t fifo_ctrl3;
7097 int32_t ret;
7098
7099 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL3,
7100 (uint8_t *)&fifo_ctrl3, 1);
7101
7102 switch (fifo_ctrl3.bdr_xl)
7103 {
7104 case LSM6DSRX_XL_NOT_BATCHED:
7105 *val = LSM6DSRX_XL_NOT_BATCHED;
7106 break;
7107
7108 case LSM6DSRX_XL_BATCHED_AT_12Hz5:
7109 *val = LSM6DSRX_XL_BATCHED_AT_12Hz5;
7110 break;
7111
7112 case LSM6DSRX_XL_BATCHED_AT_26Hz:
7113 *val = LSM6DSRX_XL_BATCHED_AT_26Hz;
7114 break;
7115
7116 case LSM6DSRX_XL_BATCHED_AT_52Hz:
7117 *val = LSM6DSRX_XL_BATCHED_AT_52Hz;
7118 break;
7119
7120 case LSM6DSRX_XL_BATCHED_AT_104Hz:
7121 *val = LSM6DSRX_XL_BATCHED_AT_104Hz;
7122 break;
7123
7124 case LSM6DSRX_XL_BATCHED_AT_208Hz:
7125 *val = LSM6DSRX_XL_BATCHED_AT_208Hz;
7126 break;
7127
7128 case LSM6DSRX_XL_BATCHED_AT_417Hz:
7129 *val = LSM6DSRX_XL_BATCHED_AT_417Hz;
7130 break;
7131
7132 case LSM6DSRX_XL_BATCHED_AT_833Hz:
7133 *val = LSM6DSRX_XL_BATCHED_AT_833Hz;
7134 break;
7135
7136 case LSM6DSRX_XL_BATCHED_AT_1667Hz:
7137 *val = LSM6DSRX_XL_BATCHED_AT_1667Hz;
7138 break;
7139
7140 case LSM6DSRX_XL_BATCHED_AT_3333Hz:
7141 *val = LSM6DSRX_XL_BATCHED_AT_3333Hz;
7142 break;
7143
7144 case LSM6DSRX_XL_BATCHED_AT_6667Hz:
7145 *val = LSM6DSRX_XL_BATCHED_AT_6667Hz;
7146 break;
7147
7148 case LSM6DSRX_XL_BATCHED_AT_6Hz5:
7149 *val = LSM6DSRX_XL_BATCHED_AT_6Hz5;
7150 break;
7151
7152 default:
7153 *val = LSM6DSRX_XL_NOT_BATCHED;
7154 break;
7155 }
7156
7157 return ret;
7158 }
7159
7160 /**
7161 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7162 * for gyroscope data.[set]
7163 *
7164 * @param ctx Read / write interface definitions.(ptr)
7165 * @param val Change the values of bdr_gy in reg FIFO_CTRL3
7166 * @retval Interface status (MANDATORY: return 0 -> no Error).
7167 *
7168 */
lsm6dsrx_fifo_gy_batch_set(stmdev_ctx_t * ctx,lsm6dsrx_bdr_gy_t val)7169 int32_t lsm6dsrx_fifo_gy_batch_set(stmdev_ctx_t *ctx,
7170 lsm6dsrx_bdr_gy_t val)
7171 {
7172 lsm6dsrx_fifo_ctrl3_t fifo_ctrl3;
7173 int32_t ret;
7174
7175 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL3,
7176 (uint8_t *)&fifo_ctrl3, 1);
7177
7178 if (ret == 0)
7179 {
7180 fifo_ctrl3.bdr_gy = (uint8_t)val;
7181 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL3,
7182 (uint8_t *)&fifo_ctrl3, 1);
7183 }
7184
7185 return ret;
7186 }
7187
7188 /**
7189 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7190 * for gyroscope data.[get]
7191 *
7192 * @param ctx Read / write interface definitions.(ptr)
7193 * @param val Get the values of bdr_gy in reg FIFO_CTRL3
7194 * @retval Interface status (MANDATORY: return 0 -> no Error).
7195 *
7196 */
lsm6dsrx_fifo_gy_batch_get(stmdev_ctx_t * ctx,lsm6dsrx_bdr_gy_t * val)7197 int32_t lsm6dsrx_fifo_gy_batch_get(stmdev_ctx_t *ctx,
7198 lsm6dsrx_bdr_gy_t *val)
7199 {
7200 lsm6dsrx_fifo_ctrl3_t fifo_ctrl3;
7201 int32_t ret;
7202
7203 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL3,
7204 (uint8_t *)&fifo_ctrl3, 1);
7205
7206 switch (fifo_ctrl3.bdr_gy)
7207 {
7208 case LSM6DSRX_GY_NOT_BATCHED:
7209 *val = LSM6DSRX_GY_NOT_BATCHED;
7210 break;
7211
7212 case LSM6DSRX_GY_BATCHED_AT_12Hz5:
7213 *val = LSM6DSRX_GY_BATCHED_AT_12Hz5;
7214 break;
7215
7216 case LSM6DSRX_GY_BATCHED_AT_26Hz:
7217 *val = LSM6DSRX_GY_BATCHED_AT_26Hz;
7218 break;
7219
7220 case LSM6DSRX_GY_BATCHED_AT_52Hz:
7221 *val = LSM6DSRX_GY_BATCHED_AT_52Hz;
7222 break;
7223
7224 case LSM6DSRX_GY_BATCHED_AT_104Hz:
7225 *val = LSM6DSRX_GY_BATCHED_AT_104Hz;
7226 break;
7227
7228 case LSM6DSRX_GY_BATCHED_AT_208Hz:
7229 *val = LSM6DSRX_GY_BATCHED_AT_208Hz;
7230 break;
7231
7232 case LSM6DSRX_GY_BATCHED_AT_417Hz:
7233 *val = LSM6DSRX_GY_BATCHED_AT_417Hz;
7234 break;
7235
7236 case LSM6DSRX_GY_BATCHED_AT_833Hz:
7237 *val = LSM6DSRX_GY_BATCHED_AT_833Hz;
7238 break;
7239
7240 case LSM6DSRX_GY_BATCHED_AT_1667Hz:
7241 *val = LSM6DSRX_GY_BATCHED_AT_1667Hz;
7242 break;
7243
7244 case LSM6DSRX_GY_BATCHED_AT_3333Hz:
7245 *val = LSM6DSRX_GY_BATCHED_AT_3333Hz;
7246 break;
7247
7248 case LSM6DSRX_GY_BATCHED_AT_6667Hz:
7249 *val = LSM6DSRX_GY_BATCHED_AT_6667Hz;
7250 break;
7251
7252 case LSM6DSRX_GY_BATCHED_6Hz5:
7253 *val = LSM6DSRX_GY_BATCHED_6Hz5;
7254 break;
7255
7256 default:
7257 *val = LSM6DSRX_GY_NOT_BATCHED;
7258 break;
7259 }
7260
7261 return ret;
7262 }
7263
7264 /**
7265 * @brief FIFO mode selection.[set]
7266 *
7267 * @param ctx Read / write interface definitions.(ptr)
7268 * @param val Change the values of fifo_mode in reg FIFO_CTRL4
7269 * @retval Interface status (MANDATORY: return 0 -> no Error).
7270 *
7271 */
lsm6dsrx_fifo_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_fifo_mode_t val)7272 int32_t lsm6dsrx_fifo_mode_set(stmdev_ctx_t *ctx,
7273 lsm6dsrx_fifo_mode_t val)
7274 {
7275 lsm6dsrx_fifo_ctrl4_t fifo_ctrl4;
7276 int32_t ret;
7277
7278 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4,
7279 (uint8_t *)&fifo_ctrl4, 1);
7280
7281 if (ret == 0)
7282 {
7283 fifo_ctrl4.fifo_mode = (uint8_t)val;
7284 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL4,
7285 (uint8_t *)&fifo_ctrl4, 1);
7286 }
7287
7288 return ret;
7289 }
7290
7291 /**
7292 * @brief FIFO mode selection.[get]
7293 *
7294 * @param ctx Read / write interface definitions.(ptr)
7295 * @param val Get the values of fifo_mode in reg FIFO_CTRL4
7296 * @retval Interface status (MANDATORY: return 0 -> no Error).
7297 *
7298 */
lsm6dsrx_fifo_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_fifo_mode_t * val)7299 int32_t lsm6dsrx_fifo_mode_get(stmdev_ctx_t *ctx,
7300 lsm6dsrx_fifo_mode_t *val)
7301 {
7302 lsm6dsrx_fifo_ctrl4_t fifo_ctrl4;
7303 int32_t ret;
7304
7305 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4,
7306 (uint8_t *)&fifo_ctrl4, 1);
7307
7308 switch (fifo_ctrl4.fifo_mode)
7309 {
7310 case LSM6DSRX_BYPASS_MODE:
7311 *val = LSM6DSRX_BYPASS_MODE;
7312 break;
7313
7314 case LSM6DSRX_FIFO_MODE:
7315 *val = LSM6DSRX_FIFO_MODE;
7316 break;
7317
7318 case LSM6DSRX_STREAM_TO_FIFO_MODE:
7319 *val = LSM6DSRX_STREAM_TO_FIFO_MODE;
7320 break;
7321
7322 case LSM6DSRX_BYPASS_TO_STREAM_MODE:
7323 *val = LSM6DSRX_BYPASS_TO_STREAM_MODE;
7324 break;
7325
7326 case LSM6DSRX_STREAM_MODE:
7327 *val = LSM6DSRX_STREAM_MODE;
7328 break;
7329
7330 case LSM6DSRX_BYPASS_TO_FIFO_MODE:
7331 *val = LSM6DSRX_BYPASS_TO_FIFO_MODE;
7332 break;
7333
7334 default:
7335 *val = LSM6DSRX_BYPASS_MODE;
7336 break;
7337 }
7338
7339 return ret;
7340 }
7341
7342 /**
7343 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7344 * for temperature data.[set]
7345 *
7346 * @param ctx Read / write interface definitions.(ptr)
7347 * @param val Change the values of odr_t_batch in reg FIFO_CTRL4
7348 * @retval Interface status (MANDATORY: return 0 -> no Error).
7349 *
7350 */
lsm6dsrx_fifo_temp_batch_set(stmdev_ctx_t * ctx,lsm6dsrx_odr_t_batch_t val)7351 int32_t lsm6dsrx_fifo_temp_batch_set(stmdev_ctx_t *ctx,
7352 lsm6dsrx_odr_t_batch_t val)
7353 {
7354 lsm6dsrx_fifo_ctrl4_t fifo_ctrl4;
7355 int32_t ret;
7356
7357 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4,
7358 (uint8_t *)&fifo_ctrl4, 1);
7359
7360 if (ret == 0)
7361 {
7362 fifo_ctrl4.odr_t_batch = (uint8_t)val;
7363 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL4,
7364 (uint8_t *)&fifo_ctrl4, 1);
7365 }
7366
7367 return ret;
7368 }
7369
7370 /**
7371 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7372 * for temperature data.[get]
7373 *
7374 * @param ctx Read / write interface definitions.(ptr)
7375 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4
7376 * @retval Interface status (MANDATORY: return 0 -> no Error).
7377 *
7378 */
lsm6dsrx_fifo_temp_batch_get(stmdev_ctx_t * ctx,lsm6dsrx_odr_t_batch_t * val)7379 int32_t lsm6dsrx_fifo_temp_batch_get(stmdev_ctx_t *ctx,
7380 lsm6dsrx_odr_t_batch_t *val)
7381 {
7382 lsm6dsrx_fifo_ctrl4_t fifo_ctrl4;
7383 int32_t ret;
7384
7385 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4,
7386 (uint8_t *)&fifo_ctrl4, 1);
7387
7388 switch (fifo_ctrl4.odr_t_batch)
7389 {
7390 case LSM6DSRX_TEMP_NOT_BATCHED:
7391 *val = LSM6DSRX_TEMP_NOT_BATCHED;
7392 break;
7393
7394 case LSM6DSRX_TEMP_BATCHED_AT_52Hz:
7395 *val = LSM6DSRX_TEMP_BATCHED_AT_52Hz;
7396 break;
7397
7398 case LSM6DSRX_TEMP_BATCHED_AT_12Hz5:
7399 *val = LSM6DSRX_TEMP_BATCHED_AT_12Hz5;
7400 break;
7401
7402 case LSM6DSRX_TEMP_BATCHED_AT_1Hz6:
7403 *val = LSM6DSRX_TEMP_BATCHED_AT_1Hz6;
7404 break;
7405
7406 default:
7407 *val = LSM6DSRX_TEMP_NOT_BATCHED;
7408 break;
7409 }
7410
7411 return ret;
7412 }
7413
7414 /**
7415 * @brief Selects decimation for timestamp batching in FIFO.
7416 * Writing rate will be the maximum rate between XL and
7417 * GYRO BDR divided by decimation decoder.[set]
7418 *
7419 * @param ctx Read / write interface definitions.(ptr)
7420 * @param val Change the values of odr_ts_batch in reg FIFO_CTRL4
7421 * @retval Interface status (MANDATORY: return 0 -> no Error).
7422 *
7423 */
lsm6dsrx_fifo_timestamp_decimation_set(stmdev_ctx_t * ctx,lsm6dsrx_odr_ts_batch_t val)7424 int32_t lsm6dsrx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
7425 lsm6dsrx_odr_ts_batch_t val)
7426 {
7427 lsm6dsrx_fifo_ctrl4_t fifo_ctrl4;
7428 int32_t ret;
7429
7430 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4,
7431 (uint8_t *)&fifo_ctrl4, 1);
7432
7433 if (ret == 0)
7434 {
7435 fifo_ctrl4.odr_ts_batch = (uint8_t)val;
7436 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FIFO_CTRL4,
7437 (uint8_t *)&fifo_ctrl4, 1);
7438 }
7439
7440 return ret;
7441 }
7442
7443 /**
7444 * @brief Selects decimation for timestamp batching in FIFO.
7445 * Writing rate will be the maximum rate between XL and
7446 * GYRO BDR divided by decimation decoder.[get]
7447 *
7448 * @param ctx Read / write interface definitions.(ptr)
7449 * @param val Get the values of odr_ts_batch in reg
7450 * FIFO_CTRL4
7451 * @retval Interface status (MANDATORY: return 0 -> no Error).
7452 *
7453 */
lsm6dsrx_fifo_timestamp_decimation_get(stmdev_ctx_t * ctx,lsm6dsrx_odr_ts_batch_t * val)7454 int32_t lsm6dsrx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
7455 lsm6dsrx_odr_ts_batch_t *val)
7456 {
7457 lsm6dsrx_fifo_ctrl4_t fifo_ctrl4;
7458 int32_t ret;
7459
7460 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_CTRL4,
7461 (uint8_t *)&fifo_ctrl4, 1);
7462
7463 switch (fifo_ctrl4.odr_ts_batch)
7464 {
7465 case LSM6DSRX_NO_DECIMATION:
7466 *val = LSM6DSRX_NO_DECIMATION;
7467 break;
7468
7469 case LSM6DSRX_DEC_1:
7470 *val = LSM6DSRX_DEC_1;
7471 break;
7472
7473 case LSM6DSRX_DEC_8:
7474 *val = LSM6DSRX_DEC_8;
7475 break;
7476
7477 case LSM6DSRX_DEC_32:
7478 *val = LSM6DSRX_DEC_32;
7479 break;
7480
7481 default:
7482 *val = LSM6DSRX_NO_DECIMATION;
7483 break;
7484 }
7485
7486 return ret;
7487 }
7488
7489 /**
7490 * @brief Selects the trigger for the internal counter of batching events
7491 * between XL and gyro.[set]
7492 *
7493 * @param ctx Read / write interface definitions.(ptr)
7494 * @param val Change the values of trig_counter_bdr in
7495 * reg COUNTER_BDR_REG1
7496 * @retval Interface status (MANDATORY: return 0 -> no Error).
7497 *
7498 */
lsm6dsrx_fifo_cnt_event_batch_set(stmdev_ctx_t * ctx,lsm6dsrx_trig_counter_bdr_t val)7499 int32_t lsm6dsrx_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
7500 lsm6dsrx_trig_counter_bdr_t val)
7501 {
7502 lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
7503 int32_t ret;
7504
7505 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
7506 (uint8_t *)&counter_bdr_reg1, 1);
7507
7508 if (ret == 0)
7509 {
7510 counter_bdr_reg1.trig_counter_bdr = (uint8_t)val;
7511 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
7512 (uint8_t *)&counter_bdr_reg1, 1);
7513 }
7514
7515 return ret;
7516 }
7517
7518 /**
7519 * @brief Selects the trigger for the internal counter of batching events
7520 * between XL and gyro.[get]
7521 *
7522 * @param ctx Read / write interface definitions.(ptr)
7523 * @param val Get the values of trig_counter_bdr
7524 * in reg COUNTER_BDR_REG1
7525 * @retval Interface status (MANDATORY: return 0 -> no Error).
7526 *
7527 */
lsm6dsrx_fifo_cnt_event_batch_get(stmdev_ctx_t * ctx,lsm6dsrx_trig_counter_bdr_t * val)7528 int32_t lsm6dsrx_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
7529 lsm6dsrx_trig_counter_bdr_t *val)
7530 {
7531 lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
7532 int32_t ret;
7533
7534 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
7535 (uint8_t *)&counter_bdr_reg1, 1);
7536
7537 switch (counter_bdr_reg1.trig_counter_bdr)
7538 {
7539 case LSM6DSRX_XL_BATCH_EVENT:
7540 *val = LSM6DSRX_XL_BATCH_EVENT;
7541 break;
7542
7543 case LSM6DSRX_GYRO_BATCH_EVENT:
7544 *val = LSM6DSRX_GYRO_BATCH_EVENT;
7545 break;
7546
7547 default:
7548 *val = LSM6DSRX_XL_BATCH_EVENT;
7549 break;
7550 }
7551
7552 return ret;
7553 }
7554
7555 /**
7556 * @brief Resets the internal counter of batching events for a single sensor.
7557 * This bit is automatically reset to zero if it was set to ‘1’.[set]
7558 *
7559 * @param ctx Read / write interface definitions.(ptr)
7560 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
7561 * @retval Interface status (MANDATORY: return 0 -> no Error).
7562 *
7563 */
lsm6dsrx_rst_batch_counter_set(stmdev_ctx_t * ctx,uint8_t val)7564 int32_t lsm6dsrx_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
7565 {
7566 lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
7567 int32_t ret;
7568
7569 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
7570 (uint8_t *)&counter_bdr_reg1, 1);
7571
7572 if (ret == 0)
7573 {
7574 counter_bdr_reg1.rst_counter_bdr = (uint8_t)val;
7575 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
7576 (uint8_t *)&counter_bdr_reg1, 1);
7577 }
7578
7579 return ret;
7580 }
7581
7582 /**
7583 * @brief Resets the internal counter of batching events for a single sensor.
7584 * This bit is automatically reset to zero if it was set to ‘1’.[get]
7585 *
7586 * @param ctx Read / write interface definitions.(ptr)
7587 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
7588 * @retval Interface status (MANDATORY: return 0 -> no Error).
7589 *
7590 */
lsm6dsrx_rst_batch_counter_get(stmdev_ctx_t * ctx,uint8_t * val)7591 int32_t lsm6dsrx_rst_batch_counter_get(stmdev_ctx_t *ctx,
7592 uint8_t *val)
7593 {
7594 lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
7595 int32_t ret;
7596
7597 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
7598 (uint8_t *)&counter_bdr_reg1, 1);
7599 *val = counter_bdr_reg1.rst_counter_bdr;
7600
7601 return ret;
7602 }
7603
7604 /**
7605 * @brief Batch data rate counter.[set]
7606 *
7607 * @param ctx Read / write interface definitions.(ptr)
7608 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
7609 * and COUNTER_BDR_REG1.
7610 * @retval Interface status (MANDATORY: return 0 -> no Error).
7611 *
7612 */
lsm6dsrx_batch_counter_threshold_set(stmdev_ctx_t * ctx,uint16_t val)7613 int32_t lsm6dsrx_batch_counter_threshold_set(stmdev_ctx_t *ctx,
7614 uint16_t val)
7615 {
7616 lsm6dsrx_counter_bdr_reg2_t counter_bdr_reg1;
7617 lsm6dsrx_counter_bdr_reg2_t counter_bdr_reg2;
7618 int32_t ret;
7619
7620 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
7621 (uint8_t *)&counter_bdr_reg1, 1);
7622
7623 if (ret == 0)
7624 {
7625 counter_bdr_reg1.cnt_bdr_th = (uint8_t)((val / 256U) & 0x07U);
7626 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
7627 (uint8_t *)&counter_bdr_reg1, 1);
7628 }
7629
7630 if (ret == 0)
7631 {
7632 counter_bdr_reg2.cnt_bdr_th = (uint8_t)(val -
7633 (counter_bdr_reg1.cnt_bdr_th * 256U));
7634 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_COUNTER_BDR_REG2,
7635 (uint8_t *)&counter_bdr_reg2, 1);
7636 }
7637
7638 return ret;
7639 }
7640
7641 /**
7642 * @brief Batch data rate counter.[get]
7643 *
7644 * @param ctx Read / write interface definitions.(ptr)
7645 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
7646 * and COUNTER_BDR_REG1.
7647 * @retval Interface status (MANDATORY: return 0 -> no Error).
7648 *
7649 */
lsm6dsrx_batch_counter_threshold_get(stmdev_ctx_t * ctx,uint16_t * val)7650 int32_t lsm6dsrx_batch_counter_threshold_get(stmdev_ctx_t *ctx,
7651 uint16_t *val)
7652 {
7653 lsm6dsrx_counter_bdr_reg1_t counter_bdr_reg1;
7654 lsm6dsrx_counter_bdr_reg2_t counter_bdr_reg2;
7655 int32_t ret;
7656
7657 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG1,
7658 (uint8_t *)&counter_bdr_reg1, 1);
7659
7660 if (ret == 0)
7661 {
7662 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_COUNTER_BDR_REG2,
7663 (uint8_t *)&counter_bdr_reg2, 1);
7664 }
7665
7666 *val = counter_bdr_reg1.cnt_bdr_th;
7667 *val = (*val * 256U) + counter_bdr_reg2.cnt_bdr_th;
7668
7669 return ret;
7670 }
7671
7672 /**
7673 * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
7674 *
7675 * @param ctx Read / write interface definitions.(ptr)
7676 * @param val Change the values of diff_fifo in reg FIFO_STATUS1
7677 * @retval Interface status (MANDATORY: return 0 -> no Error).
7678 *
7679 */
lsm6dsrx_fifo_data_level_get(stmdev_ctx_t * ctx,uint16_t * val)7680 int32_t lsm6dsrx_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
7681 {
7682 lsm6dsrx_fifo_status1_t fifo_status1;
7683 lsm6dsrx_fifo_status2_t fifo_status2;
7684 int32_t ret;
7685
7686 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_STATUS1,
7687 (uint8_t *)&fifo_status1, 1);
7688
7689 if (ret == 0)
7690 {
7691 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_STATUS2,
7692 (uint8_t *)&fifo_status2, 1);
7693 *val = fifo_status2.diff_fifo;
7694 *val = (*val * 256U) + fifo_status1.diff_fifo;
7695 }
7696
7697 return ret;
7698 }
7699
7700 /**
7701 * @brief Smart FIFO status.[get]
7702 *
7703 * @param ctx Read / write interface definitions.(ptr)
7704 * @param val Registers FIFO_STATUS2
7705 * @retval Interface status (MANDATORY: return 0 -> no Error).
7706 *
7707 */
lsm6dsrx_fifo_status_get(stmdev_ctx_t * ctx,lsm6dsrx_fifo_status2_t * val)7708 int32_t lsm6dsrx_fifo_status_get(stmdev_ctx_t *ctx,
7709 lsm6dsrx_fifo_status2_t *val)
7710 {
7711 int32_t ret;
7712
7713 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_STATUS2, (uint8_t *)val, 1);
7714
7715 return ret;
7716 }
7717
7718 /**
7719 * @brief Smart FIFO full status.[get]
7720 *
7721 * @param ctx Read / write interface definitions.(ptr)
7722 * @param val Change the values of fifo_full_ia in reg FIFO_STATUS2
7723 * @retval Interface status (MANDATORY: return 0 -> no Error).
7724 *
7725 */
lsm6dsrx_fifo_full_flag_get(stmdev_ctx_t * ctx,uint8_t * val)7726 int32_t lsm6dsrx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
7727 {
7728 lsm6dsrx_fifo_status2_t fifo_status2;
7729 int32_t ret;
7730
7731 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_STATUS2,
7732 (uint8_t *)&fifo_status2, 1);
7733 *val = fifo_status2.fifo_full_ia;
7734
7735 return ret;
7736 }
7737
7738 /**
7739 * @brief FIFO overrun status.[get]
7740 *
7741 * @param ctx Read / write interface definitions.(ptr)
7742 * @param val Change the values of fifo_over_run_latched in
7743 * reg FIFO_STATUS2
7744 * @retval Interface status (MANDATORY: return 0 -> no Error).
7745 *
7746 */
lsm6dsrx_fifo_ovr_flag_get(stmdev_ctx_t * ctx,uint8_t * val)7747 int32_t lsm6dsrx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
7748 {
7749 lsm6dsrx_fifo_status2_t fifo_status2;
7750 int32_t ret;
7751
7752 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_STATUS2,
7753 (uint8_t *)&fifo_status2, 1);
7754 *val = fifo_status2. fifo_ovr_ia;
7755
7756 return ret;
7757 }
7758
7759 /**
7760 * @brief FIFO watermark status.[get]
7761 *
7762 * @param ctx Read / write interface definitions.(ptr)
7763 * @param val Change the values of fifo_wtm_ia in reg FIFO_STATUS2
7764 * @retval Interface status (MANDATORY: return 0 -> no Error).
7765 *
7766 */
lsm6dsrx_fifo_wtm_flag_get(stmdev_ctx_t * ctx,uint8_t * val)7767 int32_t lsm6dsrx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
7768 {
7769 lsm6dsrx_fifo_status2_t fifo_status2;
7770 int32_t ret;
7771
7772 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_STATUS2,
7773 (uint8_t *)&fifo_status2, 1);
7774 *val = fifo_status2.fifo_wtm_ia;
7775
7776 return ret;
7777 }
7778
7779 /**
7780 * @brief Identifies the sensor in FIFO_DATA_OUT.[get]
7781 *
7782 * @param ctx Read / write interface definitions.(ptr)
7783 * @param val Change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
7784 * @retval Interface status (MANDATORY: return 0 -> no Error).
7785 *
7786 */
lsm6dsrx_fifo_sensor_tag_get(stmdev_ctx_t * ctx,lsm6dsrx_fifo_tag_t * val)7787 int32_t lsm6dsrx_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
7788 lsm6dsrx_fifo_tag_t *val)
7789 {
7790 lsm6dsrx_fifo_data_out_tag_t fifo_data_out_tag;
7791 int32_t ret;
7792
7793 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FIFO_DATA_OUT_TAG,
7794 (uint8_t *)&fifo_data_out_tag, 1);
7795
7796 switch (fifo_data_out_tag.tag_sensor)
7797 {
7798 case LSM6DSRX_GYRO_NC_TAG:
7799 *val = LSM6DSRX_GYRO_NC_TAG;
7800 break;
7801
7802 case LSM6DSRX_XL_NC_TAG:
7803 *val = LSM6DSRX_XL_NC_TAG;
7804 break;
7805
7806 case LSM6DSRX_TEMPERATURE_TAG:
7807 *val = LSM6DSRX_TEMPERATURE_TAG;
7808 break;
7809
7810 case LSM6DSRX_TIMESTAMP_TAG:
7811 *val = LSM6DSRX_TIMESTAMP_TAG;
7812 break;
7813
7814 case LSM6DSRX_CFG_CHANGE_TAG:
7815 *val = LSM6DSRX_CFG_CHANGE_TAG;
7816 break;
7817
7818 case LSM6DSRX_XL_NC_T_2_TAG:
7819 *val = LSM6DSRX_XL_NC_T_2_TAG;
7820 break;
7821
7822 case LSM6DSRX_XL_NC_T_1_TAG:
7823 *val = LSM6DSRX_XL_NC_T_1_TAG;
7824 break;
7825
7826 case LSM6DSRX_XL_2XC_TAG:
7827 *val = LSM6DSRX_XL_2XC_TAG;
7828 break;
7829
7830 case LSM6DSRX_XL_3XC_TAG:
7831 *val = LSM6DSRX_XL_3XC_TAG;
7832 break;
7833
7834 case LSM6DSRX_GYRO_NC_T_2_TAG:
7835 *val = LSM6DSRX_GYRO_NC_T_2_TAG;
7836 break;
7837
7838 case LSM6DSRX_GYRO_NC_T_1_TAG:
7839 *val = LSM6DSRX_GYRO_NC_T_1_TAG;
7840 break;
7841
7842 case LSM6DSRX_GYRO_2XC_TAG:
7843 *val = LSM6DSRX_GYRO_2XC_TAG;
7844 break;
7845
7846 case LSM6DSRX_GYRO_3XC_TAG:
7847 *val = LSM6DSRX_GYRO_3XC_TAG;
7848 break;
7849
7850 case LSM6DSRX_SENSORHUB_SLAVE0_TAG:
7851 *val = LSM6DSRX_SENSORHUB_SLAVE0_TAG;
7852 break;
7853
7854 case LSM6DSRX_SENSORHUB_SLAVE1_TAG:
7855 *val = LSM6DSRX_SENSORHUB_SLAVE1_TAG;
7856 break;
7857
7858 case LSM6DSRX_SENSORHUB_SLAVE2_TAG:
7859 *val = LSM6DSRX_SENSORHUB_SLAVE2_TAG;
7860 break;
7861
7862 case LSM6DSRX_SENSORHUB_SLAVE3_TAG:
7863 *val = LSM6DSRX_SENSORHUB_SLAVE3_TAG;
7864 break;
7865
7866 case LSM6DSRX_STEP_CPUNTER_TAG:
7867 *val = LSM6DSRX_STEP_CPUNTER_TAG;
7868 break;
7869
7870 case LSM6DSRX_GAME_ROTATION_TAG:
7871 *val = LSM6DSRX_GAME_ROTATION_TAG;
7872 break;
7873
7874 case LSM6DSRX_GEOMAG_ROTATION_TAG:
7875 *val = LSM6DSRX_GEOMAG_ROTATION_TAG;
7876 break;
7877
7878 case LSM6DSRX_ROTATION_TAG:
7879 *val = LSM6DSRX_ROTATION_TAG;
7880 break;
7881
7882 case LSM6DSRX_SENSORHUB_NACK_TAG:
7883 *val = LSM6DSRX_SENSORHUB_NACK_TAG;
7884 break;
7885
7886 default:
7887 *val = LSM6DSRX_SENSORHUB_NACK_TAG;
7888 break;
7889 }
7890
7891 return ret;
7892 }
7893
7894 /**
7895 * @brief Enable FIFO batching of pedometer embedded function values.[set]
7896 *
7897 * @param ctx Read / write interface definitions.(ptr)
7898 * @param val Change the values of gbias_fifo_en in
7899 * reg LSM6DSRX_EMB_FUNC_FIFO_CFG
7900 * @retval Interface status (MANDATORY: return 0 -> no Error).
7901 *
7902 */
lsm6dsrx_fifo_pedo_batch_set(stmdev_ctx_t * ctx,uint8_t val)7903 int32_t lsm6dsrx_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
7904 {
7905 lsm6dsrx_emb_func_fifo_cfg_t emb_func_fifo_cfg;
7906 int32_t ret;
7907
7908 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
7909
7910 if (ret == 0)
7911 {
7912 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_FIFO_CFG,
7913 (uint8_t *)&emb_func_fifo_cfg, 1);
7914 }
7915
7916 if (ret == 0)
7917 {
7918 emb_func_fifo_cfg.pedo_fifo_en = (uint8_t)val;
7919 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_FIFO_CFG,
7920 (uint8_t *)&emb_func_fifo_cfg, 1);
7921 }
7922
7923 if (ret == 0)
7924 {
7925 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
7926 }
7927
7928 return ret;
7929 }
7930
7931 /**
7932 * @brief Enable FIFO batching of pedometer embedded function values.[get]
7933 *
7934 * @param ctx Read / write interface definitions.(ptr)
7935 * @param val Change the values of pedo_fifo_en in reg
7936 * LSM6DSRX_EMB_FUNC_FIFO_CFG
7937 * @retval Interface status (MANDATORY: return 0 -> no Error).
7938 *
7939 */
lsm6dsrx_fifo_pedo_batch_get(stmdev_ctx_t * ctx,uint8_t * val)7940 int32_t lsm6dsrx_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
7941 {
7942 lsm6dsrx_emb_func_fifo_cfg_t emb_func_fifo_cfg;
7943 int32_t ret;
7944
7945 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
7946
7947 if (ret == 0)
7948 {
7949 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_FIFO_CFG,
7950 (uint8_t *)&emb_func_fifo_cfg, 1);
7951 *val = emb_func_fifo_cfg.pedo_fifo_en;
7952 }
7953
7954 if (ret == 0)
7955 {
7956 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
7957 }
7958
7959 return ret;
7960 }
7961
7962 /**
7963 * @brief Enable FIFO batching data of first slave.[set]
7964 *
7965 * @param ctx Read / write interface definitions.(ptr)
7966 * @param val Change the values of batch_ext_sens_0_en in reg SLV0_CONFIG
7967 * @retval Interface status (MANDATORY: return 0 -> no Error).
7968 *
7969 */
lsm6dsrx_sh_batch_slave_0_set(stmdev_ctx_t * ctx,uint8_t val)7970 int32_t lsm6dsrx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
7971 {
7972 lsm6dsrx_slv0_config_t slv0_config;
7973 int32_t ret;
7974
7975 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
7976
7977 if (ret == 0)
7978 {
7979 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV0_CONFIG,
7980 (uint8_t *)&slv0_config, 1);
7981 }
7982
7983 if (ret == 0)
7984 {
7985 slv0_config. batch_ext_sens_0_en = (uint8_t)val;
7986 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_CONFIG,
7987 (uint8_t *)&slv0_config, 1);
7988 }
7989
7990 if (ret == 0)
7991 {
7992 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
7993 }
7994
7995 return ret;
7996 }
7997
7998 /**
7999 * @brief Enable FIFO batching data of first slave.[get]
8000 *
8001 * @param ctx Read / write interface definitions.(ptr)
8002 * @param val Change the values of batch_ext_sens_0_en in
8003 * reg SLV0_CONFIG
8004 * @retval Interface status (MANDATORY: return 0 -> no Error).
8005 *
8006 */
lsm6dsrx_sh_batch_slave_0_get(stmdev_ctx_t * ctx,uint8_t * val)8007 int32_t lsm6dsrx_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val)
8008 {
8009 lsm6dsrx_slv0_config_t slv0_config;
8010 int32_t ret;
8011
8012 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
8013
8014 if (ret == 0)
8015 {
8016 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV0_CONFIG,
8017 (uint8_t *)&slv0_config, 1);
8018 }
8019
8020 if (ret == 0)
8021 {
8022 *val = slv0_config. batch_ext_sens_0_en;
8023 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8024 }
8025
8026 return ret;
8027 }
8028
8029 /**
8030 * @brief Enable FIFO batching data of second slave.[set]
8031 *
8032 * @param ctx Read / write interface definitions.(ptr)
8033 * @param val Change the values of batch_ext_sens_1_en in
8034 * reg SLV1_CONFIG
8035 * @retval Interface status (MANDATORY: return 0 -> no Error).
8036 *
8037 */
lsm6dsrx_sh_batch_slave_1_set(stmdev_ctx_t * ctx,uint8_t val)8038 int32_t lsm6dsrx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
8039 {
8040 lsm6dsrx_slv1_config_t slv1_config;
8041 int32_t ret;
8042
8043 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
8044
8045 if (ret == 0)
8046 {
8047 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV1_CONFIG,
8048 (uint8_t *)&slv1_config, 1);
8049 }
8050
8051 if (ret == 0)
8052 {
8053 slv1_config. batch_ext_sens_1_en = (uint8_t)val;
8054 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV1_CONFIG,
8055 (uint8_t *)&slv1_config, 1);
8056 }
8057
8058 if (ret == 0)
8059 {
8060 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8061 }
8062
8063 return ret;
8064 }
8065
8066 /**
8067 * @brief Enable FIFO batching data of second slave.[get]
8068 *
8069 * @param ctx Read / write interface definitions.(ptr)
8070 * @param val Change the values of batch_ext_sens_1_en in
8071 * reg SLV1_CONFIG
8072 * @retval Interface status (MANDATORY: return 0 -> no Error).
8073 *
8074 */
lsm6dsrx_sh_batch_slave_1_get(stmdev_ctx_t * ctx,uint8_t * val)8075 int32_t lsm6dsrx_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val)
8076 {
8077 lsm6dsrx_slv1_config_t slv1_config;
8078 int32_t ret;
8079
8080 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
8081
8082 if (ret == 0)
8083 {
8084 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV1_CONFIG,
8085 (uint8_t *)&slv1_config, 1);
8086 *val = slv1_config. batch_ext_sens_1_en;
8087 }
8088
8089 if (ret == 0)
8090 {
8091 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8092 }
8093
8094 return ret;
8095 }
8096
8097 /**
8098 * @brief Enable FIFO batching data of third slave.[set]
8099 *
8100 * @param ctx Read / write interface definitions.(ptr)
8101 * @param val Change the values of batch_ext_sens_2_en in
8102 * reg SLV2_CONFIG
8103 * @retval Interface status (MANDATORY: return 0 -> no Error).
8104 *
8105 */
lsm6dsrx_sh_batch_slave_2_set(stmdev_ctx_t * ctx,uint8_t val)8106 int32_t lsm6dsrx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
8107 {
8108 lsm6dsrx_slv2_config_t slv2_config;
8109 int32_t ret;
8110
8111 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
8112
8113 if (ret == 0)
8114 {
8115 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV2_CONFIG,
8116 (uint8_t *)&slv2_config, 1);
8117 }
8118
8119 if (ret == 0)
8120 {
8121 slv2_config. batch_ext_sens_2_en = (uint8_t)val;
8122 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV2_CONFIG,
8123 (uint8_t *)&slv2_config, 1);
8124 }
8125
8126 if (ret == 0)
8127 {
8128 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8129 }
8130
8131 return ret;
8132 }
8133
8134 /**
8135 * @brief Enable FIFO batching data of third slave.[get]
8136 *
8137 * @param ctx Read / write interface definitions.(ptr)
8138 * @param val Change the values of batch_ext_sens_2_en in
8139 * reg SLV2_CONFIG
8140 * @retval Interface status (MANDATORY: return 0 -> no Error).
8141 *
8142 */
lsm6dsrx_sh_batch_slave_2_get(stmdev_ctx_t * ctx,uint8_t * val)8143 int32_t lsm6dsrx_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val)
8144 {
8145 lsm6dsrx_slv2_config_t slv2_config;
8146 int32_t ret;
8147
8148 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
8149
8150 if (ret == 0)
8151 {
8152 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV2_CONFIG,
8153 (uint8_t *)&slv2_config, 1);
8154 }
8155
8156 if (ret == 0)
8157 {
8158 *val = slv2_config. batch_ext_sens_2_en;
8159 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8160 }
8161
8162 return ret;
8163 }
8164
8165 /**
8166 * @brief Enable FIFO batching data of fourth slave.[set]
8167 *
8168 * @param ctx Read / write interface definitions.(ptr)
8169 * @param val Change the values of batch_ext_sens_3_en in
8170 * reg SLV3_CONFIG
8171 * @retval Interface status (MANDATORY: return 0 -> no Error).
8172 *
8173 */
lsm6dsrx_sh_batch_slave_3_set(stmdev_ctx_t * ctx,uint8_t val)8174 int32_t lsm6dsrx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
8175 {
8176 lsm6dsrx_slv3_config_t slv3_config;
8177 int32_t ret;
8178
8179 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
8180
8181 if (ret == 0)
8182 {
8183 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV3_CONFIG,
8184 (uint8_t *)&slv3_config, 1);
8185 }
8186
8187 if (ret == 0)
8188 {
8189 slv3_config. batch_ext_sens_3_en = (uint8_t)val;
8190 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV3_CONFIG,
8191 (uint8_t *)&slv3_config, 1);
8192 }
8193
8194 if (ret == 0)
8195 {
8196 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8197 }
8198
8199 return ret;
8200 }
8201
8202 /**
8203 * @brief Enable FIFO batching data of fourth slave.[get]
8204 *
8205 * @param ctx Read / write interface definitions.(ptr)
8206 * @param val Change the values of batch_ext_sens_3_en in
8207 * reg SLV3_CONFIG
8208 * @retval Interface status (MANDATORY: return 0 -> no Error).
8209 *
8210 */
lsm6dsrx_sh_batch_slave_3_get(stmdev_ctx_t * ctx,uint8_t * val)8211 int32_t lsm6dsrx_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
8212 {
8213 lsm6dsrx_slv3_config_t slv3_config;
8214 int32_t ret;
8215
8216 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
8217
8218 if (ret == 0)
8219 {
8220 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV3_CONFIG,
8221 (uint8_t *)&slv3_config, 1);
8222 *val = slv3_config. batch_ext_sens_3_en;
8223 }
8224
8225 if (ret == 0)
8226 {
8227 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8228 }
8229
8230 return ret;
8231 }
8232
8233 /**
8234 * @}
8235 *
8236 */
8237
8238 /**
8239 * @defgroup LSM6DSRX_DEN_functionality
8240 * @brief This section groups all the functions concerning
8241 * DEN functionality.
8242 * @{
8243 *
8244 */
8245
8246 /**
8247 * @brief DEN functionality marking mode.[set]
8248 *
8249 * @param ctx Read / write interface definitions.(ptr)
8250 * @param val Change the values of den_mode in reg CTRL6_C
8251 * @retval Interface status (MANDATORY: return 0 -> no Error).
8252 *
8253 */
lsm6dsrx_den_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_den_mode_t val)8254 int32_t lsm6dsrx_den_mode_set(stmdev_ctx_t *ctx,
8255 lsm6dsrx_den_mode_t val)
8256 {
8257 lsm6dsrx_ctrl6_c_t ctrl6_c;
8258 int32_t ret;
8259
8260 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
8261
8262 if (ret == 0)
8263 {
8264 ctrl6_c.den_mode = (uint8_t)val;
8265 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
8266 }
8267
8268 return ret;
8269 }
8270
8271 /**
8272 * @brief DEN functionality marking mode.[get]
8273 *
8274 * @param ctx Read / write interface definitions.(ptr)
8275 * @param val Get the values of den_mode in reg CTRL6_C
8276 * @retval Interface status (MANDATORY: return 0 -> no Error).
8277 *
8278 */
lsm6dsrx_den_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_den_mode_t * val)8279 int32_t lsm6dsrx_den_mode_get(stmdev_ctx_t *ctx,
8280 lsm6dsrx_den_mode_t *val)
8281 {
8282 lsm6dsrx_ctrl6_c_t ctrl6_c;
8283 int32_t ret;
8284
8285 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
8286
8287 switch (ctrl6_c.den_mode)
8288 {
8289 case LSM6DSRX_DEN_DISABLE:
8290 *val = LSM6DSRX_DEN_DISABLE;
8291 break;
8292
8293 case LSM6DSRX_LEVEL_FIFO:
8294 *val = LSM6DSRX_LEVEL_FIFO;
8295 break;
8296
8297 case LSM6DSRX_LEVEL_LETCHED:
8298 *val = LSM6DSRX_LEVEL_LETCHED;
8299 break;
8300
8301 case LSM6DSRX_LEVEL_TRIGGER:
8302 *val = LSM6DSRX_LEVEL_TRIGGER;
8303 break;
8304
8305 case LSM6DSRX_EDGE_TRIGGER:
8306 *val = LSM6DSRX_EDGE_TRIGGER;
8307 break;
8308
8309 default:
8310 *val = LSM6DSRX_DEN_DISABLE;
8311 break;
8312 }
8313
8314 return ret;
8315 }
8316
8317 /**
8318 * @brief DEN active level configuration.[set]
8319 *
8320 * @param ctx Read / write interface definitions.(ptr)
8321 * @param val Change the values of den_lh in reg CTRL9_XL
8322 * @retval Interface status (MANDATORY: return 0 -> no Error).
8323 *
8324 */
lsm6dsrx_den_polarity_set(stmdev_ctx_t * ctx,lsm6dsrx_den_lh_t val)8325 int32_t lsm6dsrx_den_polarity_set(stmdev_ctx_t *ctx,
8326 lsm6dsrx_den_lh_t val)
8327 {
8328 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8329 int32_t ret;
8330
8331 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8332
8333 if (ret == 0)
8334 {
8335 ctrl9_xl.den_lh = (uint8_t)val;
8336 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL,
8337 (uint8_t *)&ctrl9_xl, 1);
8338 }
8339
8340 return ret;
8341 }
8342
8343 /**
8344 * @brief DEN active level configuration.[get]
8345 *
8346 * @param ctx Read / write interface definitions.(ptr)
8347 * @param val Get the values of den_lh in reg CTRL9_XL
8348 * @retval Interface status (MANDATORY: return 0 -> no Error).
8349 *
8350 */
lsm6dsrx_den_polarity_get(stmdev_ctx_t * ctx,lsm6dsrx_den_lh_t * val)8351 int32_t lsm6dsrx_den_polarity_get(stmdev_ctx_t *ctx,
8352 lsm6dsrx_den_lh_t *val)
8353 {
8354 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8355 int32_t ret;
8356
8357 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8358
8359 switch (ctrl9_xl.den_lh)
8360 {
8361 case LSM6DSRX_DEN_ACT_LOW:
8362 *val = LSM6DSRX_DEN_ACT_LOW;
8363 break;
8364
8365 case LSM6DSRX_DEN_ACT_HIGH:
8366 *val = LSM6DSRX_DEN_ACT_HIGH;
8367 break;
8368
8369 default:
8370 *val = LSM6DSRX_DEN_ACT_LOW;
8371 break;
8372 }
8373
8374 return ret;
8375 }
8376
8377 /**
8378 * @brief DEN configuration.[set]
8379 *
8380 * @param ctx Read / write interface definitions.(ptr)
8381 * @param val Change the values of den_xl_g in reg CTRL9_XL
8382 * @retval Interface status (MANDATORY: return 0 -> no Error).
8383 *
8384 */
lsm6dsrx_den_enable_set(stmdev_ctx_t * ctx,lsm6dsrx_den_xl_g_t val)8385 int32_t lsm6dsrx_den_enable_set(stmdev_ctx_t *ctx,
8386 lsm6dsrx_den_xl_g_t val)
8387 {
8388 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8389 int32_t ret;
8390
8391 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8392
8393 if (ret == 0)
8394 {
8395 ctrl9_xl.den_xl_g = (uint8_t)val;
8396 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL,
8397 (uint8_t *)&ctrl9_xl, 1);
8398 }
8399
8400 return ret;
8401 }
8402
8403 /**
8404 * @brief DEN configuration.[get]
8405 *
8406 * @param ctx Read / write interface definitions.(ptr)
8407 * @param val Get the values of den_xl_g in reg CTRL9_XL
8408 * @retval Interface status (MANDATORY: return 0 -> no Error).
8409 *
8410 */
lsm6dsrx_den_enable_get(stmdev_ctx_t * ctx,lsm6dsrx_den_xl_g_t * val)8411 int32_t lsm6dsrx_den_enable_get(stmdev_ctx_t *ctx,
8412 lsm6dsrx_den_xl_g_t *val)
8413 {
8414 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8415 int32_t ret;
8416
8417 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8418
8419 switch (ctrl9_xl.den_xl_g)
8420 {
8421 case LSM6DSRX_STAMP_IN_GY_DATA:
8422 *val = LSM6DSRX_STAMP_IN_GY_DATA;
8423 break;
8424
8425 case LSM6DSRX_STAMP_IN_XL_DATA:
8426 *val = LSM6DSRX_STAMP_IN_XL_DATA;
8427 break;
8428
8429 case LSM6DSRX_STAMP_IN_GY_XL_DATA:
8430 *val = LSM6DSRX_STAMP_IN_GY_XL_DATA;
8431 break;
8432
8433 default:
8434 *val = LSM6DSRX_STAMP_IN_GY_DATA;
8435 break;
8436 }
8437
8438 return ret;
8439 }
8440
8441 /**
8442 * @brief DEN value stored in LSB of X-axis.[set]
8443 *
8444 * @param ctx Read / write interface definitions.(ptr)
8445 * @param val Change the values of den_z in reg CTRL9_XL
8446 * @retval Interface status (MANDATORY: return 0 -> no Error).
8447 *
8448 */
lsm6dsrx_den_mark_axis_x_set(stmdev_ctx_t * ctx,uint8_t val)8449 int32_t lsm6dsrx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
8450 {
8451 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8452 int32_t ret;
8453
8454 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8455
8456 if (ret == 0)
8457 {
8458 ctrl9_xl.den_z = (uint8_t)val;
8459 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL,
8460 (uint8_t *)&ctrl9_xl, 1);
8461 }
8462
8463 return ret;
8464 }
8465
8466 /**
8467 * @brief DEN value stored in LSB of X-axis.[get]
8468 *
8469 * @param ctx Read / write interface definitions.(ptr)
8470 * @param val Change the values of den_z in reg CTRL9_XL
8471 * @retval Interface status (MANDATORY: return 0 -> no Error).
8472 *
8473 */
lsm6dsrx_den_mark_axis_x_get(stmdev_ctx_t * ctx,uint8_t * val)8474 int32_t lsm6dsrx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
8475 {
8476 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8477 int32_t ret;
8478
8479 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8480 *val = ctrl9_xl.den_z;
8481
8482 return ret;
8483 }
8484
8485 /**
8486 * @brief DEN value stored in LSB of Y-axis.[set]
8487 *
8488 * @param ctx Read / write interface definitions.(ptr)
8489 * @param val Change the values of den_y in reg CTRL9_XL
8490 * @retval Interface status (MANDATORY: return 0 -> no Error).
8491 *
8492 */
lsm6dsrx_den_mark_axis_y_set(stmdev_ctx_t * ctx,uint8_t val)8493 int32_t lsm6dsrx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
8494 {
8495 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8496 int32_t ret;
8497
8498 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8499
8500 if (ret == 0)
8501 {
8502 ctrl9_xl.den_y = (uint8_t)val;
8503 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL,
8504 (uint8_t *)&ctrl9_xl, 1);
8505 }
8506
8507 return ret;
8508 }
8509
8510 /**
8511 * @brief DEN value stored in LSB of Y-axis.[get]
8512 *
8513 * @param ctx Read / write interface definitions.(ptr)
8514 * @param val Change the values of den_y in reg CTRL9_XL
8515 * @retval Interface status (MANDATORY: return 0 -> no Error).
8516 *
8517 */
lsm6dsrx_den_mark_axis_y_get(stmdev_ctx_t * ctx,uint8_t * val)8518 int32_t lsm6dsrx_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
8519 {
8520 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8521 int32_t ret;
8522
8523 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8524 *val = ctrl9_xl.den_y;
8525
8526 return ret;
8527 }
8528
8529 /**
8530 * @brief DEN value stored in LSB of Z-axis.[set]
8531 *
8532 * @param ctx Read / write interface definitions.(ptr)
8533 * @param val Change the values of den_x in reg CTRL9_XL
8534 * @retval Interface status (MANDATORY: return 0 -> no Error).
8535 *
8536 */
lsm6dsrx_den_mark_axis_z_set(stmdev_ctx_t * ctx,uint8_t val)8537 int32_t lsm6dsrx_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
8538 {
8539 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8540 int32_t ret;
8541
8542 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8543
8544 if (ret == 0)
8545 {
8546 ctrl9_xl.den_x = (uint8_t)val;
8547 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8548 }
8549
8550 return ret;
8551 }
8552
8553 /**
8554 * @brief DEN value stored in LSB of Z-axis.[get]
8555 *
8556 * @param ctx Read / write interface definitions.(ptr)
8557 * @param val Change the values of den_x in reg CTRL9_XL
8558 * @retval Interface status (MANDATORY: return 0 -> no Error).
8559 *
8560 */
lsm6dsrx_den_mark_axis_z_get(stmdev_ctx_t * ctx,uint8_t * val)8561 int32_t lsm6dsrx_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
8562 {
8563 lsm6dsrx_ctrl9_xl_t ctrl9_xl;
8564 int32_t ret;
8565
8566 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8567 *val = ctrl9_xl.den_x;
8568
8569 return ret;
8570 }
8571
8572 /**
8573 * @}
8574 *
8575 */
8576
8577 /**
8578 * @defgroup LSM6DSRX_Pedometer
8579 * @brief This section groups all the functions that manage pedometer.
8580 * @{
8581 *
8582 */
8583
8584 /**
8585 * @brief Enable pedometer algorithm.[set]
8586 *
8587 * @param ctx Read / write interface definitions.(ptr)
8588 * @param val Change the values of pedo_en in reg EMB_FUNC_EN_A
8589 * @retval Interface status (MANDATORY: return 0 -> no Error).
8590 *
8591 */
lsm6dsrx_pedo_sens_set(stmdev_ctx_t * ctx,uint8_t val)8592 int32_t lsm6dsrx_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val)
8593 {
8594 lsm6dsrx_emb_func_en_a_t emb_func_en_a;
8595 int32_t ret;
8596
8597 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
8598
8599 if (ret == 0)
8600 {
8601 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
8602 (uint8_t *)&emb_func_en_a, 1);
8603 }
8604
8605 if (ret == 0)
8606 {
8607 emb_func_en_a.pedo_en = (uint8_t)val;
8608 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
8609 (uint8_t *)&emb_func_en_a, 1);
8610 }
8611
8612 if (ret == 0)
8613 {
8614 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8615 }
8616
8617 return ret;
8618 }
8619
8620 /**
8621 * @brief Enable pedometer algorithm.[get]
8622 *
8623 * @param ctx Read / write interface definitions.(ptr)
8624 * @param val Change the values of pedo_en in reg EMB_FUNC_EN_A
8625 * @retval Interface status (MANDATORY: return 0 -> no Error).
8626 *
8627 */
lsm6dsrx_pedo_sens_get(stmdev_ctx_t * ctx,uint8_t * val)8628 int32_t lsm6dsrx_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
8629 {
8630 lsm6dsrx_emb_func_en_a_t emb_func_en_a;
8631 int32_t ret;
8632
8633 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
8634
8635 if (ret == 0)
8636 {
8637 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
8638 (uint8_t *)&emb_func_en_a, 1);
8639 *val = emb_func_en_a.pedo_en;
8640 }
8641
8642 if (ret == 0)
8643 {
8644 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8645 }
8646
8647 return ret;
8648 }
8649
8650 /**
8651 * @brief Interrupt status bit for step detection.[get]
8652 *
8653 * @param ctx Read / write interface definitions.(ptr)
8654 * @param val Change the values of is_step_det in reg EMB_FUNC_STATUS
8655 * @retval Interface status (MANDATORY: return 0 -> no Error).
8656 *
8657 */
lsm6dsrx_pedo_step_detect_get(stmdev_ctx_t * ctx,uint8_t * val)8658 int32_t lsm6dsrx_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val)
8659 {
8660 lsm6dsrx_emb_func_status_t emb_func_status;
8661 int32_t ret;
8662
8663 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
8664
8665 if (ret == 0)
8666 {
8667 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_STATUS,
8668 (uint8_t *)&emb_func_status, 1);
8669 *val = emb_func_status.is_step_det;
8670 }
8671
8672 if (ret == 0)
8673 {
8674 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8675 }
8676
8677 return ret;
8678 }
8679
8680 /**
8681 * @brief Pedometer debounce configuration register (r/w).[set]
8682 *
8683 * @param ctx Read / write interface definitions.(ptr)
8684 * @param buff Buffer that contains data to write
8685 * @retval Interface status (MANDATORY: return 0 -> no Error).
8686 *
8687 */
lsm6dsrx_pedo_debounce_steps_set(stmdev_ctx_t * ctx,uint8_t * buff)8688 int32_t lsm6dsrx_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
8689 uint8_t *buff)
8690 {
8691 int32_t ret;
8692
8693 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_PEDO_DEB_STEPS_CONF,
8694 buff);
8695
8696 return ret;
8697 }
8698
8699 /**
8700 * @brief Pedometer debounce configuration register (r/w).[get]
8701 *
8702 * @param ctx Read / write interface definitions.(ptr)
8703 * @param buff Buffer that stores data read
8704 * @retval Interface status (MANDATORY: return 0 -> no Error).
8705 *
8706 */
lsm6dsrx_pedo_debounce_steps_get(stmdev_ctx_t * ctx,uint8_t * buff)8707 int32_t lsm6dsrx_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
8708 uint8_t *buff)
8709 {
8710 int32_t ret;
8711
8712 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_DEB_STEPS_CONF,
8713 buff);
8714
8715 return ret;
8716 }
8717
8718 /**
8719 * @brief Time period register for step detection on delta time (r/w).[set]
8720 *
8721 * @param ctx Read / write interface definitions.(ptr)
8722 * @param buff Buffer that contains data to write
8723 * @retval Interface status (MANDATORY: return 0 -> no Error).
8724 *
8725 */
lsm6dsrx_pedo_steps_period_set(stmdev_ctx_t * ctx,uint16_t val)8726 int32_t lsm6dsrx_pedo_steps_period_set(stmdev_ctx_t *ctx,
8727 uint16_t val)
8728 {
8729 uint8_t buff[2];
8730 int32_t ret;
8731
8732 buff[1] = (uint8_t)(val / 256U);
8733 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8734 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_PEDO_SC_DELTAT_L,
8735 &buff[0]);
8736
8737 if (ret == 0)
8738 {
8739 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_PEDO_SC_DELTAT_H,
8740 &buff[1]);
8741 }
8742
8743 return ret;
8744 }
8745
8746 /**
8747 * @brief Time period register for step detection on delta time (r/w).[get]
8748 *
8749 * @param ctx Read / write interface definitions.(ptr)
8750 * @param buff Buffer that stores data read
8751 * @retval Interface status (MANDATORY: return 0 -> no Error).
8752 *
8753 */
lsm6dsrx_pedo_steps_period_get(stmdev_ctx_t * ctx,uint16_t * val)8754 int32_t lsm6dsrx_pedo_steps_period_get(stmdev_ctx_t *ctx,
8755 uint16_t *val)
8756 {
8757 uint8_t buff[2];
8758 int32_t ret;
8759
8760 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_SC_DELTAT_L,
8761 &buff[0]);
8762
8763 if (ret == 0)
8764 {
8765 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_SC_DELTAT_H,
8766 &buff[1]);
8767 *val = buff[1];
8768 *val = (*val * 256U) + buff[0];
8769 }
8770
8771 return ret;
8772 }
8773
8774 /**
8775 * @brief Set when user wants to generate interrupt on count overflow
8776 * event/every step.[set]
8777 *
8778 * @param ctx Read / write interface definitions.(ptr)
8779 * @param val Change the values of carry_count_en in reg PEDO_CMD_REG
8780 * @retval Interface status (MANDATORY: return 0 -> no Error).
8781 *
8782 */
lsm6dsrx_pedo_int_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_carry_count_en_t val)8783 int32_t lsm6dsrx_pedo_int_mode_set(stmdev_ctx_t *ctx,
8784 lsm6dsrx_carry_count_en_t val)
8785 {
8786 lsm6dsrx_pedo_cmd_reg_t pedo_cmd_reg;
8787 int32_t ret;
8788
8789 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_CMD_REG,
8790 (uint8_t *)&pedo_cmd_reg);
8791
8792 if (ret == 0)
8793 {
8794 pedo_cmd_reg.carry_count_en = (uint8_t)val;
8795 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_PEDO_CMD_REG,
8796 (uint8_t *)&pedo_cmd_reg);
8797 }
8798
8799 return ret;
8800 }
8801
8802 /**
8803 * @brief Set when user wants to generate interrupt on count overflow
8804 * event/every step.[get]
8805 *
8806 * @param ctx Read / write interface definitions.(ptr)
8807 * @param val Get the values of carry_count_en in reg PEDO_CMD_REG
8808 * @retval Interface status (MANDATORY: return 0 -> no Error).
8809 *
8810 */
lsm6dsrx_pedo_int_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_carry_count_en_t * val)8811 int32_t lsm6dsrx_pedo_int_mode_get(stmdev_ctx_t *ctx,
8812 lsm6dsrx_carry_count_en_t *val)
8813 {
8814 lsm6dsrx_pedo_cmd_reg_t pedo_cmd_reg;
8815 int32_t ret;
8816
8817 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_PEDO_CMD_REG,
8818 (uint8_t *)&pedo_cmd_reg);
8819
8820 switch (pedo_cmd_reg.carry_count_en)
8821 {
8822 case LSM6DSRX_EVERY_STEP:
8823 *val = LSM6DSRX_EVERY_STEP;
8824 break;
8825
8826 case LSM6DSRX_COUNT_OVERFLOW:
8827 *val = LSM6DSRX_COUNT_OVERFLOW;
8828 break;
8829
8830 default:
8831 *val = LSM6DSRX_EVERY_STEP;
8832 break;
8833 }
8834
8835 return ret;
8836 }
8837
8838 /**
8839 * @}
8840 *
8841 */
8842
8843 /**
8844 * @defgroup LSM6DSRX_significant_motion
8845 * @brief This section groups all the functions that manage the
8846 * significant motion detection.
8847 * @{
8848 *
8849 */
8850
8851 /**
8852 * @brief Enable significant motion detection function.[set]
8853 *
8854 * @param ctx Read / write interface definitions.(ptr)
8855 * @param val Change the values of sign_motion_en in reg EMB_FUNC_EN_A
8856 * @retval Interface status (MANDATORY: return 0 -> no Error).
8857 *
8858 */
lsm6dsrx_motion_sens_set(stmdev_ctx_t * ctx,uint8_t val)8859 int32_t lsm6dsrx_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
8860 {
8861 lsm6dsrx_emb_func_en_a_t emb_func_en_a;
8862 int32_t ret;
8863
8864 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
8865
8866 if (ret == 0)
8867 {
8868 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
8869 (uint8_t *)&emb_func_en_a, 1);
8870 }
8871
8872 if (ret == 0)
8873 {
8874 emb_func_en_a.sign_motion_en = (uint8_t)val;
8875 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
8876 (uint8_t *)&emb_func_en_a, 1);
8877 }
8878
8879 if (ret == 0)
8880 {
8881 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8882 }
8883
8884 return ret;
8885 }
8886
8887 /**
8888 * @brief Enable significant motion detection function.[get]
8889 *
8890 * @param ctx Read / write interface definitions.(ptr)
8891 * @param val Change the values of sign_motion_en in reg EMB_FUNC_EN_A
8892 * @retval Interface status (MANDATORY: return 0 -> no Error).
8893 *
8894 */
lsm6dsrx_motion_sens_get(stmdev_ctx_t * ctx,uint8_t * val)8895 int32_t lsm6dsrx_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
8896 {
8897 lsm6dsrx_emb_func_en_a_t emb_func_en_a;
8898 int32_t ret;
8899
8900 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
8901
8902 if (ret == 0)
8903 {
8904 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
8905 (uint8_t *)&emb_func_en_a, 1);
8906 }
8907
8908 if (ret == 0)
8909 {
8910 *val = emb_func_en_a.sign_motion_en;
8911 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8912 }
8913
8914 return ret;
8915 }
8916
8917 /**
8918 * @brief Interrupt status bit for significant motion detection.[get]
8919 *
8920 * @param ctx Read / write interface definitions.(ptr)
8921 * @param val Change the values of is_sigmot in reg EMB_FUNC_STATUS
8922 * @retval Interface status (MANDATORY: return 0 -> no Error).
8923 *
8924 */
lsm6dsrx_motion_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)8925 int32_t lsm6dsrx_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
8926 uint8_t *val)
8927 {
8928 lsm6dsrx_emb_func_status_t emb_func_status;
8929 int32_t ret;
8930
8931 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
8932
8933 if (ret == 0)
8934 {
8935 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_STATUS,
8936 (uint8_t *)&emb_func_status, 1);
8937 }
8938
8939 if (ret == 0)
8940 {
8941 *val = emb_func_status.is_sigmot;
8942 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8943 }
8944
8945 return ret;
8946 }
8947
8948 /**
8949 * @}
8950 *
8951 */
8952
8953 /**
8954 * @defgroup LSM6DSRX_tilt_detection
8955 * @brief This section groups all the functions that manage the tilt
8956 * event detection.
8957 * @{
8958 *
8959 */
8960
8961 /**
8962 * @brief Enable tilt calculation.[set]
8963 *
8964 * @param ctx Read / write interface definitions.(ptr)
8965 * @param val Change the values of tilt_en in reg EMB_FUNC_EN_A
8966 * @retval Interface status (MANDATORY: return 0 -> no Error).
8967 *
8968 */
lsm6dsrx_tilt_sens_set(stmdev_ctx_t * ctx,uint8_t val)8969 int32_t lsm6dsrx_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
8970 {
8971 lsm6dsrx_emb_func_en_a_t emb_func_en_a;
8972 int32_t ret;
8973
8974 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
8975
8976 if (ret == 0)
8977 {
8978 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
8979 (uint8_t *)&emb_func_en_a, 1);
8980 }
8981
8982 if (ret == 0)
8983 {
8984 emb_func_en_a.tilt_en = (uint8_t)val;
8985 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
8986 (uint8_t *)&emb_func_en_a, 1);
8987 }
8988
8989 if (ret == 0)
8990 {
8991 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
8992 }
8993
8994 return ret;
8995 }
8996
8997 /**
8998 * @brief Enable tilt calculation.[get]
8999 *
9000 * @param ctx Read / write interface definitions.(ptr)
9001 * @param val Change the values of tilt_en in reg EMB_FUNC_EN_A
9002 * @retval Interface status (MANDATORY: return 0 -> no Error).
9003 *
9004 */
lsm6dsrx_tilt_sens_get(stmdev_ctx_t * ctx,uint8_t * val)9005 int32_t lsm6dsrx_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
9006 {
9007 lsm6dsrx_emb_func_en_a_t emb_func_en_a;
9008 int32_t ret;
9009
9010 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
9011
9012 if (ret == 0)
9013 {
9014 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_A,
9015 (uint8_t *)&emb_func_en_a, 1);
9016 }
9017
9018 if (ret == 0)
9019 {
9020 *val = emb_func_en_a.tilt_en;
9021 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
9022 }
9023
9024 return ret;
9025 }
9026
9027 /**
9028 * @brief Interrupt status bit for tilt detection.[get]
9029 *
9030 * @param ctx Read / write interface definitions.(ptr)
9031 * @param val Change the values of is_tilt in reg EMB_FUNC_STATUS
9032 * @retval Interface status (MANDATORY: return 0 -> no Error).
9033 *
9034 */
lsm6dsrx_tilt_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)9035 int32_t lsm6dsrx_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
9036 uint8_t *val)
9037 {
9038 lsm6dsrx_emb_func_status_t emb_func_status;
9039 int32_t ret;
9040
9041 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
9042
9043 if (ret == 0)
9044 {
9045 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_STATUS,
9046 (uint8_t *)&emb_func_status, 1);
9047 }
9048
9049 if (ret == 0)
9050 {
9051 *val = emb_func_status.is_tilt;
9052 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
9053 }
9054
9055 return ret;
9056 }
9057
9058 /**
9059 * @}
9060 *
9061 */
9062
9063 /**
9064 * @defgroup LSM6DSRX_ magnetometer_sensor
9065 * @brief This section groups all the functions that manage additional
9066 * magnetometer sensor.
9067 * @{
9068 *
9069 */
9070
9071 /**
9072 * @brief External magnetometer sensitivity value register.[set]
9073 *
9074 * @param ctx Read / write interface definitions.(ptr)
9075 * @param buff Buffer that contains data to write
9076 * @retval Interface status (MANDATORY: return 0 -> no Error).
9077 *
9078 */
lsm6dsrx_mag_sensitivity_set(stmdev_ctx_t * ctx,uint16_t val)9079 int32_t lsm6dsrx_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val)
9080 {
9081 uint8_t buff[2];
9082 int32_t ret;
9083
9084 buff[1] = (uint8_t)(val / 256U);
9085 buff[0] = (uint8_t)(val - (buff[1] * 256U));
9086 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SENSITIVITY_L,
9087 &buff[0]);
9088
9089 if (ret == 0)
9090 {
9091 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SENSITIVITY_H,
9092 &buff[1]);
9093 }
9094
9095 return ret;
9096 }
9097
9098 /**
9099 * @brief External magnetometer sensitivity value register.[get]
9100 *
9101 * @param ctx Read / write interface definitions.(ptr)
9102 * @param buff Buffer that stores data read
9103 * @retval Interface status (MANDATORY: return 0 -> no Error).
9104 *
9105 */
lsm6dsrx_mag_sensitivity_get(stmdev_ctx_t * ctx,uint16_t * val)9106 int32_t lsm6dsrx_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val)
9107 {
9108 uint8_t buff[2];
9109 int32_t ret;
9110
9111 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SENSITIVITY_L,
9112 &buff[0]);
9113
9114 if (ret == 0)
9115 {
9116 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SENSITIVITY_H,
9117 &buff[1]);
9118 *val = buff[1];
9119 *val = (*val * 256U) + buff[0];
9120 }
9121
9122 return ret;
9123 }
9124
9125 /**
9126 * @brief Offset for hard-iron compensation register (r/w).[set]
9127 *
9128 * @param ctx Read / write interface definitions.(ptr)
9129 * @param buff Buffer that contains data to write
9130 * @retval Interface status (MANDATORY: return 0 -> no Error).
9131 *
9132 */
lsm6dsrx_mag_offset_set(stmdev_ctx_t * ctx,int16_t * val)9133 int32_t lsm6dsrx_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
9134 {
9135 uint8_t buff[6];
9136 int32_t ret;
9137
9138 uint8_t i;
9139 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
9140 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
9141 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
9142 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
9143 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
9144 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
9145 i = 0x00U;
9146 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_OFFX_L, &buff[i]);
9147
9148 if (ret == 0)
9149 {
9150 i++;
9151 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_OFFX_H, &buff[i]);
9152 }
9153
9154 if (ret == 0)
9155 {
9156 i++;
9157 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_OFFY_L, &buff[i]);
9158 }
9159
9160 if (ret == 0)
9161 {
9162 i++;
9163 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_OFFY_H, &buff[i]);
9164 }
9165
9166 if (ret == 0)
9167 {
9168 i++;
9169 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_OFFZ_L, &buff[i]);
9170 }
9171
9172 if (ret == 0)
9173 {
9174 i++;
9175 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_OFFZ_H, &buff[i]);
9176 }
9177
9178 return ret;
9179 }
9180
9181 /**
9182 * @brief Offset for hard-iron compensation register (r/w).[get]
9183 *
9184 * @param ctx Read / write interface definitions.(ptr)
9185 * @param buff Buffer that stores data read
9186 * @retval Interface status (MANDATORY: return 0 -> no Error).
9187 *
9188 */
lsm6dsrx_mag_offset_get(stmdev_ctx_t * ctx,int16_t * val)9189 int32_t lsm6dsrx_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
9190 {
9191 uint8_t buff[6];
9192 int32_t ret;
9193
9194 uint8_t i;
9195 i = 0x00U;
9196 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_OFFX_L, &buff[i]);
9197
9198 if (ret == 0)
9199 {
9200 i++;
9201 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_OFFX_H, &buff[i]);
9202 }
9203
9204 if (ret == 0)
9205 {
9206 i++;
9207 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_OFFY_L, &buff[i]);
9208 }
9209
9210 if (ret == 0)
9211 {
9212 i++;
9213 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_OFFY_H, &buff[i]);
9214 }
9215
9216 if (ret == 0)
9217 {
9218 i++;
9219 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_OFFZ_L, &buff[i]);
9220 }
9221
9222 if (ret == 0)
9223 {
9224 i++;
9225 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_OFFZ_H, &buff[i]);
9226 }
9227
9228 val[0] = (int16_t)buff[1];
9229 val[0] = (val[0] * 256) + (int16_t)buff[0];
9230 val[1] = (int16_t)buff[3];
9231 val[1] = (val[1] * 256) + (int16_t)buff[2];
9232 val[2] = (int16_t)buff[5];
9233 val[2] = (val[2] * 256) + (int16_t)buff[4];
9234
9235 return ret;
9236 }
9237
9238 /**
9239 * @brief Soft-iron (3x3 symmetric) matrix correction register (r/w).
9240 * The value is expressed as half-precision floating-point format:
9241 * SEEEEEFFFFFFFFFF
9242 * S: 1 sign bit;
9243 * E: 5 exponent bits;
9244 * F: 10 fraction bits).[set]
9245 *
9246 * @param ctx Read / write interface definitions.(ptr)
9247 * @param buff Buffer that contains data to write
9248 * @retval Interface status (MANDATORY: return 0 -> no Error).
9249 *
9250 */
lsm6dsrx_mag_soft_iron_set(stmdev_ctx_t * ctx,uint16_t * val)9251 int32_t lsm6dsrx_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val)
9252 {
9253 uint8_t buff[12];
9254 int32_t ret;
9255
9256 uint8_t i;
9257 buff[1] = (uint8_t)(val[0] / 256U);
9258 buff[0] = (uint8_t)(val[0] - (buff[1] * 256U));
9259 buff[3] = (uint8_t)(val[1] / 256U);
9260 buff[2] = (uint8_t)(val[1] - (buff[3] * 256U));
9261 buff[5] = (uint8_t)(val[2] / 256U);
9262 buff[4] = (uint8_t)(val[2] - (buff[5] * 256U));
9263 buff[7] = (uint8_t)(val[3] / 256U);
9264 buff[6] = (uint8_t)(val[3] - (buff[1] * 256U));
9265 buff[9] = (uint8_t)(val[4] / 256U);
9266 buff[8] = (uint8_t)(val[4] - (buff[3] * 256U));
9267 buff[11] = (uint8_t)(val[5] / 256U);
9268 buff[10] = (uint8_t)(val[5] - (buff[5] * 256U));
9269 i = 0x00U;
9270 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_XX_L, &buff[i]);
9271
9272 if (ret == 0)
9273 {
9274 i++;
9275 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_XX_H, &buff[i]);
9276 }
9277
9278 if (ret == 0)
9279 {
9280 i++;
9281 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_XY_L, &buff[i]);
9282 }
9283
9284 if (ret == 0)
9285 {
9286 i++;
9287 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_XY_H, &buff[i]);
9288 }
9289
9290 if (ret == 0)
9291 {
9292 i++;
9293 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_XZ_L, &buff[i]);
9294 }
9295
9296 if (ret == 0)
9297 {
9298 i++;
9299 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_XZ_H, &buff[i]);
9300 }
9301
9302 if (ret == 0)
9303 {
9304 i++;
9305 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_YY_L, &buff[i]);
9306 }
9307
9308 if (ret == 0)
9309 {
9310 i++;
9311 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_YY_H, &buff[i]);
9312 }
9313
9314 if (ret == 0)
9315 {
9316 i++;
9317 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_YZ_L, &buff[i]);
9318 }
9319
9320 if (ret == 0)
9321 {
9322 i++;
9323 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_YZ_H, &buff[i]);
9324 }
9325
9326 if (ret == 0)
9327 {
9328 i++;
9329 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_ZZ_L, &buff[i]);
9330 }
9331
9332 if (ret == 0)
9333 {
9334 i++;
9335 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_SI_ZZ_H, &buff[i]);
9336 }
9337
9338 return ret;
9339 }
9340
9341 /**
9342 * @brief Soft-iron (3x3 symmetric) matrix correction register (r/w).
9343 * The value is expressed as half-precision floating-point format:
9344 * SEEEEEFFFFFFFFFF
9345 * S: 1 sign bit;
9346 * E: 5 exponent bits;
9347 * F: 10 fraction bits).[get]
9348 *
9349 * @param ctx Read / write interface definitions.(ptr)
9350 * @param buff Buffer that stores data read
9351 * @retval Interface status (MANDATORY: return 0 -> no Error).
9352 *
9353 */
lsm6dsrx_mag_soft_iron_get(stmdev_ctx_t * ctx,uint16_t * val)9354 int32_t lsm6dsrx_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val)
9355 {
9356 uint8_t buff[12];
9357 int32_t ret;
9358
9359 uint8_t i;
9360 i = 0x00U;
9361 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_XX_L, &buff[i]);
9362
9363 if (ret == 0)
9364 {
9365 i++;
9366 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_XX_H, &buff[i]);
9367 }
9368
9369 if (ret == 0)
9370 {
9371 i++;
9372 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_XY_L, &buff[i]);
9373 }
9374
9375 if (ret == 0)
9376 {
9377 i++;
9378 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_XY_H, &buff[i]);
9379 }
9380
9381 if (ret == 0)
9382 {
9383 i++;
9384 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_XZ_L, &buff[i]);
9385 }
9386
9387 if (ret == 0)
9388 {
9389 i++;
9390 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_XZ_H, &buff[i]);
9391 }
9392
9393 if (ret == 0)
9394 {
9395 i++;
9396 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_YY_L, &buff[i]);
9397 }
9398
9399 if (ret == 0)
9400 {
9401 i++;
9402 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_YY_H, &buff[i]);
9403 }
9404
9405 if (ret == 0)
9406 {
9407 i++;
9408 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_YZ_L, &buff[i]);
9409 }
9410
9411 if (ret == 0)
9412 {
9413 i++;
9414 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_YZ_H, &buff[i]);
9415 }
9416
9417 if (ret == 0)
9418 {
9419 i++;
9420 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_ZZ_L, &buff[i]);
9421 }
9422
9423 if (ret == 0)
9424 {
9425 i++;
9426 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_SI_ZZ_H, &buff[i]);
9427 }
9428
9429 val[0] = buff[1];
9430 val[0] = (val[0] * 256U) + buff[0];
9431 val[1] = buff[3];
9432 val[1] = (val[1] * 256U) + buff[2];
9433 val[2] = buff[5];
9434 val[2] = (val[2] * 256U) + buff[4];
9435 val[3] = buff[7];
9436 val[3] = (val[3] * 256U) + buff[6];
9437 val[4] = buff[9];
9438 val[4] = (val[4] * 256U) + buff[8];
9439 val[5] = buff[11];
9440 val[6] = (val[5] * 256U) + buff[10];
9441
9442 return ret;
9443 }
9444
9445 /**
9446 * @brief Magnetometer Z-axis coordinates rotation (to be aligned to
9447 * accelerometer/gyroscope axes orientation).[set]
9448 *
9449 * @param ctx Read / write interface definitions.(ptr)
9450 * @param val Change the values of mag_z_axis in reg MAG_CFG_A
9451 * @retval Interface status (MANDATORY: return 0 -> no Error).
9452 *
9453 */
lsm6dsrx_mag_z_orient_set(stmdev_ctx_t * ctx,lsm6dsrx_mag_z_axis_t val)9454 int32_t lsm6dsrx_mag_z_orient_set(stmdev_ctx_t *ctx,
9455 lsm6dsrx_mag_z_axis_t val)
9456 {
9457 lsm6dsrx_mag_cfg_a_t mag_cfg_a;
9458 int32_t ret;
9459
9460 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_A,
9461 (uint8_t *)&mag_cfg_a);
9462
9463 if (ret == 0)
9464 {
9465 mag_cfg_a.mag_z_axis = (uint8_t)val;
9466 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_CFG_A,
9467 (uint8_t *)&mag_cfg_a);
9468 }
9469
9470 return ret;
9471 }
9472
9473 /**
9474 * @brief Magnetometer Z-axis coordinates rotation (to be aligned to
9475 * accelerometer/gyroscope axes orientation).[get]
9476 *
9477 * @param ctx Read / write interface definitions.(ptr)
9478 * @param val Get the values of mag_z_axis in reg MAG_CFG_A
9479 * @retval Interface status (MANDATORY: return 0 -> no Error).
9480 *
9481 */
lsm6dsrx_mag_z_orient_get(stmdev_ctx_t * ctx,lsm6dsrx_mag_z_axis_t * val)9482 int32_t lsm6dsrx_mag_z_orient_get(stmdev_ctx_t *ctx,
9483 lsm6dsrx_mag_z_axis_t *val)
9484 {
9485 lsm6dsrx_mag_cfg_a_t mag_cfg_a;
9486 int32_t ret;
9487
9488 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_A,
9489 (uint8_t *)&mag_cfg_a);
9490
9491 switch (mag_cfg_a.mag_z_axis)
9492 {
9493 case LSM6DSRX_Z_EQ_Y:
9494 *val = LSM6DSRX_Z_EQ_Y;
9495 break;
9496
9497 case LSM6DSRX_Z_EQ_MIN_Y:
9498 *val = LSM6DSRX_Z_EQ_MIN_Y;
9499 break;
9500
9501 case LSM6DSRX_Z_EQ_X:
9502 *val = LSM6DSRX_Z_EQ_X;
9503 break;
9504
9505 case LSM6DSRX_Z_EQ_MIN_X:
9506 *val = LSM6DSRX_Z_EQ_MIN_X;
9507 break;
9508
9509 case LSM6DSRX_Z_EQ_MIN_Z:
9510 *val = LSM6DSRX_Z_EQ_MIN_Z;
9511 break;
9512
9513 case LSM6DSRX_Z_EQ_Z:
9514 *val = LSM6DSRX_Z_EQ_Z;
9515 break;
9516
9517 default:
9518 *val = LSM6DSRX_Z_EQ_Y;
9519 break;
9520 }
9521
9522 return ret;
9523 }
9524
9525 /**
9526 * @brief Magnetometer Y-axis coordinates rotation (to be aligned to
9527 * accelerometer/gyroscope axes orientation).[set]
9528 *
9529 * @param ctx Read / write interface definitions.(ptr)
9530 * @param val Change the values of mag_y_axis in
9531 * reg MAG_CFG_A
9532 * @retval Interface status (MANDATORY: return 0 -> no Error).
9533 *
9534 */
lsm6dsrx_mag_y_orient_set(stmdev_ctx_t * ctx,lsm6dsrx_mag_y_axis_t val)9535 int32_t lsm6dsrx_mag_y_orient_set(stmdev_ctx_t *ctx,
9536 lsm6dsrx_mag_y_axis_t val)
9537 {
9538 lsm6dsrx_mag_cfg_a_t mag_cfg_a;
9539 int32_t ret;
9540
9541 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_A,
9542 (uint8_t *)&mag_cfg_a);
9543
9544 if (ret == 0)
9545 {
9546 mag_cfg_a.mag_y_axis = (uint8_t)val;
9547 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_CFG_A,
9548 (uint8_t *)&mag_cfg_a);
9549 }
9550
9551 return ret;
9552 }
9553
9554 /**
9555 * @brief Magnetometer Y-axis coordinates rotation (to be aligned to
9556 * accelerometer/gyroscope axes orientation).[get]
9557 *
9558 * @param ctx Read / write interface definitions.(ptr)
9559 * @param val Get the values of mag_y_axis in reg MAG_CFG_A
9560 * @retval Interface status (MANDATORY: return 0 -> no Error).
9561 *
9562 */
lsm6dsrx_mag_y_orient_get(stmdev_ctx_t * ctx,lsm6dsrx_mag_y_axis_t * val)9563 int32_t lsm6dsrx_mag_y_orient_get(stmdev_ctx_t *ctx,
9564 lsm6dsrx_mag_y_axis_t *val)
9565 {
9566 lsm6dsrx_mag_cfg_a_t mag_cfg_a;
9567 int32_t ret;
9568
9569 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_A,
9570 (uint8_t *)&mag_cfg_a);
9571
9572 switch (mag_cfg_a.mag_y_axis)
9573 {
9574 case LSM6DSRX_Y_EQ_Y:
9575 *val = LSM6DSRX_Y_EQ_Y;
9576 break;
9577
9578 case LSM6DSRX_Y_EQ_MIN_Y:
9579 *val = LSM6DSRX_Y_EQ_MIN_Y;
9580 break;
9581
9582 case LSM6DSRX_Y_EQ_X:
9583 *val = LSM6DSRX_Y_EQ_X;
9584 break;
9585
9586 case LSM6DSRX_Y_EQ_MIN_X:
9587 *val = LSM6DSRX_Y_EQ_MIN_X;
9588 break;
9589
9590 case LSM6DSRX_Y_EQ_MIN_Z:
9591 *val = LSM6DSRX_Y_EQ_MIN_Z;
9592 break;
9593
9594 case LSM6DSRX_Y_EQ_Z:
9595 *val = LSM6DSRX_Y_EQ_Z;
9596 break;
9597
9598 default:
9599 *val = LSM6DSRX_Y_EQ_Y;
9600 break;
9601 }
9602
9603 return ret;
9604 }
9605
9606 /**
9607 * @brief Magnetometer X-axis coordinates rotation (to be aligned to
9608 * accelerometer/gyroscope axes orientation).[set]
9609 *
9610 * @param ctx Read / write interface definitions.(ptr)
9611 * @param val Change the values of mag_x_axis in reg MAG_CFG_B
9612 * @retval Interface status (MANDATORY: return 0 -> no Error).
9613 *
9614 */
lsm6dsrx_mag_x_orient_set(stmdev_ctx_t * ctx,lsm6dsrx_mag_x_axis_t val)9615 int32_t lsm6dsrx_mag_x_orient_set(stmdev_ctx_t *ctx,
9616 lsm6dsrx_mag_x_axis_t val)
9617 {
9618 lsm6dsrx_mag_cfg_b_t mag_cfg_b;
9619 int32_t ret;
9620
9621 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_B,
9622 (uint8_t *)&mag_cfg_b);
9623
9624 if (ret == 0)
9625 {
9626 mag_cfg_b.mag_x_axis = (uint8_t)val;
9627 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MAG_CFG_B,
9628 (uint8_t *)&mag_cfg_b);
9629 }
9630
9631 return ret;
9632 }
9633
9634 /**
9635 * @brief Magnetometer X-axis coordinates rotation (to be aligned to
9636 * accelerometer/gyroscope axes orientation).[get]
9637 *
9638 * @param ctx Read / write interface definitions.(ptr)
9639 * @param val Get the values of mag_x_axis in reg MAG_CFG_B
9640 * @retval Interface status (MANDATORY: return 0 -> no Error).
9641 *
9642 */
lsm6dsrx_mag_x_orient_get(stmdev_ctx_t * ctx,lsm6dsrx_mag_x_axis_t * val)9643 int32_t lsm6dsrx_mag_x_orient_get(stmdev_ctx_t *ctx,
9644 lsm6dsrx_mag_x_axis_t *val)
9645 {
9646 lsm6dsrx_mag_cfg_b_t mag_cfg_b;
9647 int32_t ret;
9648
9649 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MAG_CFG_B,
9650 (uint8_t *)&mag_cfg_b);
9651
9652 switch (mag_cfg_b.mag_x_axis)
9653 {
9654 case LSM6DSRX_X_EQ_Y:
9655 *val = LSM6DSRX_X_EQ_Y;
9656 break;
9657
9658 case LSM6DSRX_X_EQ_MIN_Y:
9659 *val = LSM6DSRX_X_EQ_MIN_Y;
9660 break;
9661
9662 case LSM6DSRX_X_EQ_X:
9663 *val = LSM6DSRX_X_EQ_X;
9664 break;
9665
9666 case LSM6DSRX_X_EQ_MIN_X:
9667 *val = LSM6DSRX_X_EQ_MIN_X;
9668 break;
9669
9670 case LSM6DSRX_X_EQ_MIN_Z:
9671 *val = LSM6DSRX_X_EQ_MIN_Z;
9672 break;
9673
9674 case LSM6DSRX_X_EQ_Z:
9675 *val = LSM6DSRX_X_EQ_Z;
9676 break;
9677
9678 default:
9679 *val = LSM6DSRX_X_EQ_Y;
9680 break;
9681 }
9682
9683 return ret;
9684 }
9685
9686 /**
9687 * @}
9688 *
9689 */
9690
9691 /**
9692 * @defgroup LSM6DSRX_finite_state_machine
9693 * @brief This section groups all the functions that manage the
9694 * state_machine.
9695 * @{
9696 *
9697 */
9698
9699 /**
9700 * @brief Interrupt status bit for FSM long counter timeout interrupt
9701 * event.[get]
9702 *
9703 * @param ctx Read / write interface definitions.(ptr)
9704 * @param val Change the values of is_fsm_lc in reg EMB_FUNC_STATUS
9705 * @retval Interface status (MANDATORY: return 0 -> no Error).
9706 *
9707 */
lsm6dsrx_long_cnt_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)9708 int32_t lsm6dsrx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
9709 uint8_t *val)
9710 {
9711 lsm6dsrx_emb_func_status_t emb_func_status;
9712 int32_t ret;
9713
9714 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
9715
9716 if (ret == 0)
9717 {
9718 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_STATUS,
9719 (uint8_t *)&emb_func_status, 1);
9720 }
9721
9722 if (ret == 0)
9723 {
9724 *val = emb_func_status.is_fsm_lc;
9725 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
9726 }
9727
9728 return ret;
9729 }
9730
9731 /**
9732 * @brief Embedded final state machine functions mode.[set]
9733 *
9734 * @param ctx Read / write interface definitions.(ptr)
9735 * @param val Change the values of fsm_en in reg EMB_FUNC_EN_B
9736 * @retval Interface status (MANDATORY: return 0 -> no Error).
9737 *
9738 */
lsm6dsrx_emb_fsm_en_set(stmdev_ctx_t * ctx,uint8_t val)9739 int32_t lsm6dsrx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val)
9740 {
9741 int32_t ret;
9742
9743 lsm6dsrx_emb_func_en_b_t emb_func_en_b;
9744 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
9745
9746 if (ret == 0)
9747 {
9748 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
9749 (uint8_t *)&emb_func_en_b, 1);
9750 }
9751
9752 if (ret == 0)
9753 {
9754 emb_func_en_b.fsm_en = (uint8_t)val;
9755 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
9756 (uint8_t *)&emb_func_en_b, 1);
9757 }
9758
9759 if (ret == 0)
9760 {
9761 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
9762 }
9763
9764 return ret;
9765 }
9766
9767 /**
9768 * @brief Embedded final state machine functions mode.[get]
9769 *
9770 * @param ctx Read / write interface definitions.(ptr)
9771 * @param val Get the values of fsm_en in reg EMB_FUNC_EN_B
9772 * @retval Interface status (MANDATORY: return 0 -> no Error).
9773 *
9774 */
lsm6dsrx_emb_fsm_en_get(stmdev_ctx_t * ctx,uint8_t * val)9775 int32_t lsm6dsrx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
9776 {
9777 int32_t ret;
9778
9779 lsm6dsrx_emb_func_en_b_t emb_func_en_b;
9780 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
9781
9782 if (ret == 0)
9783 {
9784 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
9785 (uint8_t *)&emb_func_en_b, 1);
9786 }
9787
9788 if (ret == 0)
9789 {
9790 *val = emb_func_en_b.fsm_en;
9791 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
9792 (uint8_t *)&emb_func_en_b, 1);
9793 }
9794
9795 if (ret == 0)
9796 {
9797 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
9798 }
9799
9800 return ret;
9801 }
9802
9803 /**
9804 * @brief Embedded final state machine functions mode.[set]
9805 *
9806 * @param ctx Read / write interface definitions.(ptr)
9807 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
9808 * @retval Interface status (MANDATORY: return 0 -> no Error).
9809 *
9810 */
lsm6dsrx_fsm_enable_set(stmdev_ctx_t * ctx,lsm6dsrx_emb_fsm_enable_t * val)9811 int32_t lsm6dsrx_fsm_enable_set(stmdev_ctx_t *ctx,
9812 lsm6dsrx_emb_fsm_enable_t *val)
9813 {
9814 lsm6dsrx_emb_func_en_b_t emb_func_en_b;
9815 int32_t ret;
9816
9817 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
9818
9819 if (ret == 0)
9820 {
9821 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_ENABLE_A,
9822 (uint8_t *)&val->fsm_enable_a, 1);
9823 }
9824
9825 if (ret == 0)
9826 {
9827 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_ENABLE_B,
9828 (uint8_t *)&val->fsm_enable_b, 1);
9829 }
9830
9831 if (ret == 0)
9832 {
9833 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
9834 (uint8_t *)&emb_func_en_b, 1);
9835 }
9836
9837 if (ret == 0)
9838 {
9839 if ((val->fsm_enable_a.fsm1_en |
9840 val->fsm_enable_a.fsm2_en |
9841 val->fsm_enable_a.fsm3_en |
9842 val->fsm_enable_a.fsm4_en |
9843 val->fsm_enable_a.fsm5_en |
9844 val->fsm_enable_a.fsm6_en |
9845 val->fsm_enable_a.fsm7_en |
9846 val->fsm_enable_a.fsm8_en |
9847 val->fsm_enable_b.fsm9_en |
9848 val->fsm_enable_b.fsm10_en |
9849 val->fsm_enable_b.fsm11_en |
9850 val->fsm_enable_b.fsm12_en |
9851 val->fsm_enable_b.fsm13_en |
9852 val->fsm_enable_b.fsm14_en |
9853 val->fsm_enable_b.fsm15_en |
9854 val->fsm_enable_b.fsm16_en) != PROPERTY_DISABLE)
9855 {
9856 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
9857 }
9858
9859 else
9860 {
9861 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
9862 }
9863 }
9864
9865 if (ret == 0)
9866 {
9867 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B,
9868 (uint8_t *)&emb_func_en_b, 1);
9869 }
9870
9871 if (ret == 0)
9872 {
9873 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
9874 }
9875
9876 return ret;
9877 }
9878
9879 /**
9880 * @brief Embedded final state machine functions mode.[get]
9881 *
9882 * @param ctx Read / write interface definitions.(ptr)
9883 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
9884 * @retval Interface status (MANDATORY: return 0 -> no Error).
9885 *
9886 */
lsm6dsrx_fsm_enable_get(stmdev_ctx_t * ctx,lsm6dsrx_emb_fsm_enable_t * val)9887 int32_t lsm6dsrx_fsm_enable_get(stmdev_ctx_t *ctx,
9888 lsm6dsrx_emb_fsm_enable_t *val)
9889 {
9890 int32_t ret;
9891
9892 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
9893
9894 if (ret == 0)
9895 {
9896 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_ENABLE_A,
9897 (uint8_t *)&val->fsm_enable_a, 1);
9898 }
9899
9900 if (ret == 0)
9901 {
9902 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_ENABLE_B,
9903 (uint8_t *)&val->fsm_enable_b, 1);
9904 }
9905
9906 if (ret == 0)
9907 {
9908 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
9909 }
9910
9911 return ret;
9912 }
9913
9914 /**
9915 * @brief FSM long counter status register. Long counter value is an
9916 * unsigned integer value (16-bit format).[set]
9917 *
9918 * @param ctx Read / write interface definitions.(ptr)
9919 * @param buff Buffer that contains data to write
9920 * @retval Interface status (MANDATORY: return 0 -> no Error).
9921 *
9922 */
lsm6dsrx_long_cnt_set(stmdev_ctx_t * ctx,uint16_t val)9923 int32_t lsm6dsrx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
9924 {
9925 uint8_t buff[2];
9926 int32_t ret;
9927
9928 buff[1] = (uint8_t)(val / 256U);
9929 buff[0] = (uint8_t)(val - (buff[1] * 256U));
9930 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
9931
9932 if (ret == 0)
9933 {
9934 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_LONG_COUNTER_L, buff, 2);
9935 }
9936
9937 if (ret == 0)
9938 {
9939 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
9940 }
9941
9942 return ret;
9943 }
9944
9945 /**
9946 * @brief FSM long counter status register. Long counter value is an
9947 * unsigned integer value (16-bit format).[get]
9948 *
9949 * @param ctx Read / write interface definitions.(ptr)
9950 * @param buff Buffer that stores data read
9951 * @retval Interface status (MANDATORY: return 0 -> no Error).
9952 *
9953 */
lsm6dsrx_long_cnt_get(stmdev_ctx_t * ctx,uint16_t * val)9954 int32_t lsm6dsrx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
9955 {
9956 uint8_t buff[2];
9957 int32_t ret;
9958
9959 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
9960
9961 if (ret == 0)
9962 {
9963 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_LONG_COUNTER_L, buff, 2);
9964 *val = buff[1];
9965 *val = (*val * 256U) + buff[0];
9966 }
9967
9968 if (ret == 0)
9969 {
9970 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
9971 }
9972
9973 return ret;
9974 }
9975
9976 /**
9977 * @brief Clear FSM long counter value.[set]
9978 *
9979 * @param ctx Read / write interface definitions.(ptr)
9980 * @param val Change the values of fsm_lc_clr in reg
9981 * FSM_LONG_COUNTER_CLEAR
9982 * @retval Interface status (MANDATORY: return 0 -> no Error).
9983 *
9984 */
lsm6dsrx_long_clr_set(stmdev_ctx_t * ctx,lsm6dsrx_fsm_lc_clr_t val)9985 int32_t lsm6dsrx_long_clr_set(stmdev_ctx_t *ctx,
9986 lsm6dsrx_fsm_lc_clr_t val)
9987 {
9988 lsm6dsrx_fsm_long_counter_clear_t fsm_long_counter_clear;
9989 int32_t ret;
9990
9991 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
9992
9993 if (ret == 0)
9994 {
9995 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_LONG_COUNTER_CLEAR,
9996 (uint8_t *)&fsm_long_counter_clear, 1);
9997 }
9998
9999 if (ret == 0)
10000 {
10001 fsm_long_counter_clear.fsm_lc_clr = (uint8_t)val;
10002 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_FSM_LONG_COUNTER_CLEAR,
10003 (uint8_t *)&fsm_long_counter_clear, 1);
10004 }
10005
10006 if (ret == 0)
10007 {
10008 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10009 }
10010
10011 return ret;
10012 }
10013
10014 /**
10015 * @brief Clear FSM long counter value.[get]
10016 *
10017 * @param ctx Read / write interface definitions.(ptr)
10018 * @param val Get the values of fsm_lc_clr in reg FSM_LONG_COUNTER_CLEAR
10019 * @retval Interface status (MANDATORY: return 0 -> no Error).
10020 *
10021 */
lsm6dsrx_long_clr_get(stmdev_ctx_t * ctx,lsm6dsrx_fsm_lc_clr_t * val)10022 int32_t lsm6dsrx_long_clr_get(stmdev_ctx_t *ctx,
10023 lsm6dsrx_fsm_lc_clr_t *val)
10024 {
10025 lsm6dsrx_fsm_long_counter_clear_t fsm_long_counter_clear;
10026 int32_t ret;
10027
10028 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10029
10030 if (ret == 0)
10031 {
10032 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_LONG_COUNTER_CLEAR,
10033 (uint8_t *)&fsm_long_counter_clear, 1);
10034 }
10035
10036 if (ret == 0)
10037 {
10038 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10039 }
10040
10041 switch (fsm_long_counter_clear.fsm_lc_clr)
10042 {
10043 case LSM6DSRX_LC_NORMAL:
10044 *val = LSM6DSRX_LC_NORMAL;
10045 break;
10046
10047 case LSM6DSRX_LC_CLEAR:
10048 *val = LSM6DSRX_LC_CLEAR;
10049 break;
10050
10051 case LSM6DSRX_LC_CLEAR_DONE:
10052 *val = LSM6DSRX_LC_CLEAR_DONE;
10053 break;
10054
10055 default:
10056 *val = LSM6DSRX_LC_NORMAL;
10057 break;
10058 }
10059
10060 return ret;
10061 }
10062
10063 /**
10064 * @brief FSM output registers.[get]
10065 *
10066 * @param ctx Read / write interface definitions.(ptr)
10067 * @param val Structure of registers from FSM_OUTS1 to FSM_OUTS16
10068 * @retval Interface status (MANDATORY: return 0 -> no Error).
10069 *
10070 */
lsm6dsrx_fsm_out_get(stmdev_ctx_t * ctx,lsm6dsrx_fsm_out_t * val)10071 int32_t lsm6dsrx_fsm_out_get(stmdev_ctx_t *ctx,
10072 lsm6dsrx_fsm_out_t *val)
10073 {
10074 int32_t ret;
10075
10076 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10077
10078 if (ret == 0)
10079 {
10080 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_FSM_OUTS1,
10081 (uint8_t *)&val->fsm_outs1, 16);
10082 }
10083
10084 if (ret == 0)
10085 {
10086 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10087 }
10088
10089 return ret;
10090 }
10091
10092 /**
10093 * @brief Finite State Machine ODR configuration.[set]
10094 *
10095 * @param ctx Read / write interface definitions.(ptr)
10096 * @param val Change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
10097 * @retval Interface status (MANDATORY: return 0 -> no Error).
10098 *
10099 */
lsm6dsrx_fsm_data_rate_set(stmdev_ctx_t * ctx,lsm6dsrx_fsm_odr_t val)10100 int32_t lsm6dsrx_fsm_data_rate_set(stmdev_ctx_t *ctx,
10101 lsm6dsrx_fsm_odr_t val)
10102 {
10103 lsm6dsrx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
10104 int32_t ret;
10105
10106 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10107
10108 if (ret == 0)
10109 {
10110 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_ODR_CFG_B,
10111 (uint8_t *)&emb_func_odr_cfg_b, 1);
10112 }
10113
10114 if (ret == 0)
10115 {
10116 emb_func_odr_cfg_b.not_used_01 = 3; /* set default values */
10117 emb_func_odr_cfg_b.not_used_02 = 1; /* set default values */
10118 emb_func_odr_cfg_b.fsm_odr = (uint8_t)val;
10119 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_ODR_CFG_B,
10120 (uint8_t *)&emb_func_odr_cfg_b, 1);
10121 }
10122
10123 if (ret == 0)
10124 {
10125 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10126 }
10127
10128 return ret;
10129 }
10130
10131 /**
10132 * @brief Finite State Machine ODR configuration.[get]
10133 *
10134 * @param ctx Read / write interface definitions.(ptr)
10135 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
10136 * @retval Interface status (MANDATORY: return 0 -> no Error).
10137 *
10138 */
lsm6dsrx_fsm_data_rate_get(stmdev_ctx_t * ctx,lsm6dsrx_fsm_odr_t * val)10139 int32_t lsm6dsrx_fsm_data_rate_get(stmdev_ctx_t *ctx,
10140 lsm6dsrx_fsm_odr_t *val)
10141 {
10142 lsm6dsrx_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
10143 int32_t ret;
10144
10145 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10146
10147 if (ret == 0)
10148 {
10149 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_ODR_CFG_B,
10150 (uint8_t *)&emb_func_odr_cfg_b, 1);
10151 }
10152
10153 if (ret == 0)
10154 {
10155 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10156 }
10157
10158 switch (emb_func_odr_cfg_b.fsm_odr)
10159 {
10160 case LSM6DSRX_ODR_FSM_12Hz5:
10161 *val = LSM6DSRX_ODR_FSM_12Hz5;
10162 break;
10163
10164 case LSM6DSRX_ODR_FSM_26Hz:
10165 *val = LSM6DSRX_ODR_FSM_26Hz;
10166 break;
10167
10168 case LSM6DSRX_ODR_FSM_52Hz:
10169 *val = LSM6DSRX_ODR_FSM_52Hz;
10170 break;
10171
10172 case LSM6DSRX_ODR_FSM_104Hz:
10173 *val = LSM6DSRX_ODR_FSM_104Hz;
10174 break;
10175
10176 default:
10177 *val = LSM6DSRX_ODR_FSM_12Hz5;
10178 break;
10179 }
10180
10181 return ret;
10182 }
10183
10184 /**
10185 * @brief FSM initialization request.[set]
10186 *
10187 * @param ctx Read / write interface definitions.(ptr)
10188 * @param val Change the values of fsm_init in reg FSM_INIT
10189 * @retval Interface status (MANDATORY: return 0 -> no Error).
10190 *
10191 */
lsm6dsrx_fsm_init_set(stmdev_ctx_t * ctx,uint8_t val)10192 int32_t lsm6dsrx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
10193 {
10194 lsm6dsrx_emb_func_init_b_t emb_func_init_b;
10195 int32_t ret;
10196
10197 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10198
10199 if (ret == 0)
10200 {
10201 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
10202 (uint8_t *)&emb_func_init_b, 1);
10203 }
10204
10205 if (ret == 0)
10206 {
10207 emb_func_init_b.fsm_init = (uint8_t)val;
10208 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
10209 (uint8_t *)&emb_func_init_b, 1);
10210 }
10211
10212 if (ret == 0)
10213 {
10214 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10215 }
10216
10217 return ret;
10218 }
10219
10220 /**
10221 * @brief FSM initialization request.[get]
10222 *
10223 * @param ctx Read / write interface definitions.(ptr)
10224 * @param val Change the values of fsm_init in reg FSM_INIT
10225 * @retval Interface status (MANDATORY: return 0 -> no Error).
10226 *
10227 */
lsm6dsrx_fsm_init_get(stmdev_ctx_t * ctx,uint8_t * val)10228 int32_t lsm6dsrx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
10229 {
10230 lsm6dsrx_emb_func_init_b_t emb_func_init_b;
10231 int32_t ret;
10232
10233 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10234
10235 if (ret == 0)
10236 {
10237 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
10238 (uint8_t *)&emb_func_init_b, 1);
10239 }
10240
10241 if (ret == 0)
10242 {
10243 *val = emb_func_init_b.fsm_init;
10244 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10245 }
10246
10247 return ret;
10248 }
10249
10250 /**
10251 * @brief FSM long counter timeout register (r/w). The long counter
10252 * timeout value is an unsigned integer value (16-bit format).
10253 * When the long counter value reached this value, the FSM
10254 * generates an interrupt.[set]
10255 *
10256 * @param ctx Read / write interface definitions.(ptr)
10257 * @param buff Buffer that contains data to write
10258 * @retval Interface status (MANDATORY: return 0 -> no Error).
10259 *
10260 */
lsm6dsrx_long_cnt_int_value_set(stmdev_ctx_t * ctx,uint16_t val)10261 int32_t lsm6dsrx_long_cnt_int_value_set(stmdev_ctx_t *ctx,
10262 uint16_t val)
10263 {
10264 uint8_t buff[2];
10265 int32_t ret;
10266
10267 buff[1] = (uint8_t)(val / 256U);
10268 buff[0] = (uint8_t)(val - (buff[1] * 256U));
10269 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_LC_TIMEOUT_L,
10270 &buff[0]);
10271
10272 if (ret == 0)
10273 {
10274 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_LC_TIMEOUT_H,
10275 &buff[1]);
10276 }
10277
10278 return ret;
10279 }
10280
10281 /**
10282 * @brief FSM long counter timeout register (r/w). The long counter
10283 * timeout value is an unsigned integer value (16-bit format).
10284 * When the long counter value reached this value, the FSM generates
10285 * an interrupt.[get]
10286 *
10287 * @param ctx Read / write interface definitions.(ptr)
10288 * @param buff Buffer that stores data read
10289 * @retval Interface status (MANDATORY: return 0 -> no Error).
10290 *
10291 */
lsm6dsrx_long_cnt_int_value_get(stmdev_ctx_t * ctx,uint16_t * val)10292 int32_t lsm6dsrx_long_cnt_int_value_get(stmdev_ctx_t *ctx,
10293 uint16_t *val)
10294 {
10295 uint8_t buff[2];
10296 int32_t ret;
10297
10298 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_FSM_LC_TIMEOUT_L,
10299 &buff[0]);
10300
10301 if (ret == 0)
10302 {
10303 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_FSM_LC_TIMEOUT_H,
10304 &buff[1]);
10305 *val = buff[1];
10306 *val = (*val * 256U) + buff[0];
10307 }
10308
10309 return ret;
10310 }
10311
10312 /**
10313 * @brief FSM number of programs register.[set]
10314 *
10315 * @param ctx Read / write interface definitions.(ptr)
10316 * @param buff Buffer that contains data to write
10317 * @retval Interface status (MANDATORY: return 0 -> no Error).
10318 *
10319 */
lsm6dsrx_fsm_number_of_programs_set(stmdev_ctx_t * ctx,uint8_t * buff)10320 int32_t lsm6dsrx_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
10321 uint8_t *buff)
10322 {
10323 int32_t ret;
10324
10325 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_PROGRAMS, buff);
10326
10327 if (ret == 0)
10328 {
10329 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_PROGRAMS + 0x01U,
10330 buff);
10331 }
10332
10333 return ret;
10334 }
10335
10336 /**
10337 * @brief FSM number of programs register.[get]
10338 *
10339 * @param ctx Read / write interface definitions.(ptr)
10340 * @param buff Buffer that stores data read
10341 * @retval Interface status (MANDATORY: return 0 -> no Error).
10342 *
10343 */
lsm6dsrx_fsm_number_of_programs_get(stmdev_ctx_t * ctx,uint8_t * buff)10344 int32_t lsm6dsrx_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
10345 uint8_t *buff)
10346 {
10347 int32_t ret;
10348
10349 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_FSM_PROGRAMS, buff);
10350
10351 return ret;
10352 }
10353
10354 /**
10355 * @brief FSM start address register (r/w). First available address is
10356 * 0x033C.[set]
10357 *
10358 * @param ctx Read / write interface definitions.(ptr)
10359 * @param buff Buffer that contains data to write
10360 * @retval Interface status (MANDATORY: return 0 -> no Error).
10361 *
10362 */
lsm6dsrx_fsm_start_address_set(stmdev_ctx_t * ctx,uint16_t val)10363 int32_t lsm6dsrx_fsm_start_address_set(stmdev_ctx_t *ctx,
10364 uint16_t val)
10365 {
10366 uint8_t buff[2];
10367 int32_t ret;
10368
10369 buff[1] = (uint8_t)(val / 256U);
10370 buff[0] = (uint8_t)(val - (buff[1] * 256U));
10371 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_START_ADD_L,
10372 &buff[0]);
10373
10374 if (ret == 0)
10375 {
10376 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_FSM_START_ADD_H,
10377 &buff[1]);
10378 }
10379
10380 return ret;
10381 }
10382
10383 /**
10384 * @brief FSM start address register (r/w). First available address
10385 * is 0x033C.[get]
10386 *
10387 * @param ctx Read / write interface definitions.(ptr)
10388 * @param buff Buffer that stores data read
10389 * @retval Interface status (MANDATORY: return 0 -> no Error).
10390 *
10391 */
lsm6dsrx_fsm_start_address_get(stmdev_ctx_t * ctx,uint16_t * val)10392 int32_t lsm6dsrx_fsm_start_address_get(stmdev_ctx_t *ctx,
10393 uint16_t *val)
10394 {
10395 uint8_t buff[2];
10396 int32_t ret;
10397
10398 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_FSM_START_ADD_L,
10399 &buff[0]);
10400
10401 if (ret == 0)
10402 {
10403 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_FSM_START_ADD_H,
10404 &buff[1]);
10405 *val = buff[1];
10406 *val = (*val * 256U) + buff[0];
10407 }
10408
10409 return ret;
10410 }
10411
10412 /**
10413 * @}
10414 *
10415 */
10416
10417 /**
10418 * @addtogroup Machine Learning Core
10419 * @brief This section group all the functions concerning the
10420 * usage of Machine Learning Core
10421 * @{
10422 *
10423 */
10424
10425 /**
10426 * @brief Enable Machine Learning Core.[set]
10427 *
10428 * @param ctx read / write interface definitions
10429 * @param val change the values of mlc_en in
10430 * reg EMB_FUNC_EN_B and mlc_init
10431 * in EMB_FUNC_INIT_B
10432 *
10433 */
lsm6dsrx_mlc_set(stmdev_ctx_t * ctx,uint8_t val)10434 int32_t lsm6dsrx_mlc_set(stmdev_ctx_t *ctx, uint8_t val)
10435 {
10436 lsm6dsrx_emb_func_en_b_t reg;
10437 int32_t ret;
10438
10439 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10440
10441 if (ret == 0)
10442 {
10443 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B, (uint8_t *)®, 1);
10444 }
10445
10446 if (ret == 0)
10447 {
10448 reg.mlc_en = val;
10449 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B, (uint8_t *)®, 1);
10450 }
10451
10452 if ((val != PROPERTY_DISABLE) && (ret == 0))
10453 {
10454 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
10455 (uint8_t *)®, 1);
10456
10457 if (ret == 0)
10458 {
10459 reg.mlc_en = val;
10460 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_INIT_B,
10461 (uint8_t *)®, 1);
10462 }
10463 }
10464
10465 if (ret == 0)
10466 {
10467 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10468 }
10469
10470 return ret;
10471 }
10472
10473 /**
10474 * @brief Enable Machine Learning Core.[get]
10475 *
10476 * @param ctx read / write interface definitions
10477 * @param val Get the values of mlc_en in
10478 * reg EMB_FUNC_EN_B
10479 *
10480 */
lsm6dsrx_mlc_get(stmdev_ctx_t * ctx,uint8_t * val)10481 int32_t lsm6dsrx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val)
10482 {
10483 lsm6dsrx_emb_func_en_b_t reg;
10484 int32_t ret;
10485
10486 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10487
10488 if (ret == 0)
10489 {
10490 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_EN_B, (uint8_t *)®, 1);
10491 }
10492
10493 if (ret == 0)
10494 {
10495 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10496 *val = reg.mlc_en;
10497 }
10498
10499 return ret;
10500 }
10501
10502 /**
10503 * @brief Machine Learning Core status register[get]
10504 *
10505 * @param ctx read / write interface definitions
10506 * @param val register MLC_STATUS_MAINPAGE
10507 *
10508 */
lsm6dsrx_mlc_status_get(stmdev_ctx_t * ctx,lsm6dsrx_mlc_status_mainpage_t * val)10509 int32_t lsm6dsrx_mlc_status_get(stmdev_ctx_t *ctx,
10510 lsm6dsrx_mlc_status_mainpage_t *val)
10511 {
10512 return lsm6dsrx_read_reg(ctx, LSM6DSRX_MLC_STATUS_MAINPAGE,
10513 (uint8_t *) val, 1);
10514 }
10515
10516 /**
10517 * @brief Machine Learning Core data rate selection.[set]
10518 *
10519 * @param ctx read / write interface definitions
10520 * @param val get the values of mlc_odr in
10521 * reg EMB_FUNC_ODR_CFG_C
10522 *
10523 */
lsm6dsrx_mlc_data_rate_set(stmdev_ctx_t * ctx,lsm6dsrx_mlc_odr_t val)10524 int32_t lsm6dsrx_mlc_data_rate_set(stmdev_ctx_t *ctx,
10525 lsm6dsrx_mlc_odr_t val)
10526 {
10527 lsm6dsrx_emb_func_odr_cfg_c_t reg;
10528 int32_t ret;
10529
10530 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10531
10532 if (ret == 0)
10533 {
10534 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_ODR_CFG_C,
10535 (uint8_t *)®, 1);
10536 }
10537
10538 if (ret == 0)
10539 {
10540 reg.mlc_odr = (uint8_t)val;
10541 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_EMB_FUNC_ODR_CFG_C,
10542 (uint8_t *)®, 1);
10543 }
10544
10545 if (ret == 0)
10546 {
10547 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10548 }
10549
10550 return ret;
10551 }
10552
10553 /**
10554 * @brief Machine Learning Core data rate selection.[get]
10555 *
10556 * @param ctx read / write interface definitions
10557 * @param val change the values of mlc_odr in
10558 * reg EMB_FUNC_ODR_CFG_C
10559 *
10560 */
lsm6dsrx_mlc_data_rate_get(stmdev_ctx_t * ctx,lsm6dsrx_mlc_odr_t * val)10561 int32_t lsm6dsrx_mlc_data_rate_get(stmdev_ctx_t *ctx,
10562 lsm6dsrx_mlc_odr_t *val)
10563 {
10564 lsm6dsrx_emb_func_odr_cfg_c_t reg;
10565 int32_t ret;
10566
10567 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10568
10569 if (ret == 0)
10570 {
10571 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_EMB_FUNC_ODR_CFG_C,
10572 (uint8_t *)®, 1);
10573 }
10574
10575 if (ret == 0)
10576 {
10577 switch (reg.mlc_odr)
10578 {
10579 case LSM6DSRX_ODR_PRGS_12Hz5:
10580 *val = LSM6DSRX_ODR_PRGS_12Hz5;
10581 break;
10582
10583 case LSM6DSRX_ODR_PRGS_26Hz:
10584 *val = LSM6DSRX_ODR_PRGS_26Hz;
10585 break;
10586
10587 case LSM6DSRX_ODR_PRGS_52Hz:
10588 *val = LSM6DSRX_ODR_PRGS_52Hz;
10589 break;
10590
10591 case LSM6DSRX_ODR_PRGS_104Hz:
10592 *val = LSM6DSRX_ODR_PRGS_104Hz;
10593 break;
10594
10595 default:
10596 *val = LSM6DSRX_ODR_PRGS_12Hz5;
10597 break;
10598 }
10599
10600 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10601 }
10602
10603 return ret;
10604 }
10605
10606 /**
10607 * @brief prgsens_out: [get] Output value of all MLCx decision trees.
10608 *
10609 * @param ctx_t *ctx: read / write interface definitions
10610 * @param uint8_t * : buffer that stores data read
10611 *
10612 */
lsm6dsrx_mlc_out_get(stmdev_ctx_t * ctx,uint8_t * buff)10613 int32_t lsm6dsrx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff)
10614 {
10615 int32_t ret;
10616
10617 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_EMBEDDED_FUNC_BANK);
10618
10619 if (ret == 0)
10620 {
10621 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MLC0_SRC, buff, 8);
10622 }
10623
10624 if (ret == 0)
10625 {
10626 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10627 }
10628
10629 return ret;
10630 }
10631
10632 /**
10633 * @brief External magnetometer sensitivity value register for
10634 * Machine Learning Core.[set]
10635 *
10636 * @param ctx read / write interface definitions
10637 * @param buff buffer that contains data to write
10638 *
10639 */
lsm6dsrx_mlc_mag_sensitivity_set(stmdev_ctx_t * ctx,uint16_t val)10640 int32_t lsm6dsrx_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx,
10641 uint16_t val)
10642 {
10643 uint8_t buff[2];
10644 int32_t ret;
10645
10646 buff[1] = (uint8_t)(val / 256U);
10647 buff[0] = (uint8_t)(val - (buff[1] * 256U));
10648 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MLC_MAG_SENSITIVITY_L,
10649 &buff[0]);
10650
10651 if (ret == 0)
10652 {
10653 ret = lsm6dsrx_ln_pg_write_byte(ctx, LSM6DSRX_MLC_MAG_SENSITIVITY_H,
10654 &buff[1]);
10655 }
10656
10657 return ret;
10658 }
10659
10660 /**
10661 * @brief External magnetometer sensitivity value register for
10662 * Machine Learning Core.[get]
10663 *
10664 * @param ctx read / write interface definitions
10665 * @param buff buffer that stores data read
10666 *
10667 */
lsm6dsrx_mlc_mag_sensitivity_get(stmdev_ctx_t * ctx,uint16_t * val)10668 int32_t lsm6dsrx_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx,
10669 uint16_t *val)
10670 {
10671 uint8_t buff[2];
10672 int32_t ret;
10673
10674 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MLC_MAG_SENSITIVITY_L,
10675 &buff[0]);
10676
10677 if (ret == 0)
10678 {
10679 ret = lsm6dsrx_ln_pg_read_byte(ctx, LSM6DSRX_MLC_MAG_SENSITIVITY_H,
10680 &buff[1]);
10681 *val = buff[1];
10682 *val = (*val * 256U) + buff[0];
10683 }
10684
10685 return ret;
10686 }
10687
10688 /**
10689 * @}
10690 *
10691 */
10692
10693 /**
10694 * @defgroup LSM6DSRX_Sensor_hub
10695 * @brief This section groups all the functions that manage the
10696 * sensor hub.
10697 * @{
10698 *
10699 */
10700
10701 /**
10702 * @brief Sensor hub output registers.[get]
10703 *
10704 * @param ctx Read / write interface definitions.(ptr)
10705 * @param val Structure of registers from SENSOR_HUB_1 to SENSOR_HUB_18
10706 * @retval Interface status (MANDATORY: return 0 -> no Error).
10707 *
10708 */
lsm6dsrx_sh_read_data_raw_get(stmdev_ctx_t * ctx,lsm6dsrx_emb_sh_read_t * val)10709 int32_t lsm6dsrx_sh_read_data_raw_get(stmdev_ctx_t *ctx,
10710 lsm6dsrx_emb_sh_read_t *val)
10711 {
10712 int32_t ret;
10713
10714 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
10715
10716 if (ret == 0)
10717 {
10718 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SENSOR_HUB_1, (uint8_t *)val,
10719 18);
10720 }
10721
10722 if (ret == 0)
10723 {
10724 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10725 }
10726
10727 return ret;
10728 }
10729
10730 /**
10731 * @brief Number of external sensors to be read by the sensor hub.[set]
10732 *
10733 * @param ctx Read / write interface definitions.(ptr)
10734 * @param val Change the values of aux_sens_on in reg MASTER_CONFIG
10735 * @retval Interface status (MANDATORY: return 0 -> no Error).
10736 *
10737 */
lsm6dsrx_sh_slave_connected_set(stmdev_ctx_t * ctx,lsm6dsrx_aux_sens_on_t val)10738 int32_t lsm6dsrx_sh_slave_connected_set(stmdev_ctx_t *ctx,
10739 lsm6dsrx_aux_sens_on_t val)
10740 {
10741 lsm6dsrx_master_config_t master_config;
10742 int32_t ret;
10743
10744 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
10745
10746 if (ret == 0)
10747 {
10748 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
10749 (uint8_t *)&master_config, 1);
10750 }
10751
10752 if (ret == 0)
10753 {
10754 master_config.aux_sens_on = (uint8_t)val;
10755 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
10756 (uint8_t *)&master_config, 1);
10757 }
10758
10759 if (ret == 0)
10760 {
10761 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10762 }
10763
10764 return ret;
10765 }
10766
10767 /**
10768 * @brief Number of external sensors to be read by the sensor hub.[get]
10769 *
10770 * @param ctx Read / write interface definitions.(ptr)
10771 * @param val Get the values of aux_sens_on in reg MASTER_CONFIG
10772 * @retval Interface status (MANDATORY: return 0 -> no Error).
10773 *
10774 */
lsm6dsrx_sh_slave_connected_get(stmdev_ctx_t * ctx,lsm6dsrx_aux_sens_on_t * val)10775 int32_t lsm6dsrx_sh_slave_connected_get(stmdev_ctx_t *ctx,
10776 lsm6dsrx_aux_sens_on_t *val)
10777 {
10778 lsm6dsrx_master_config_t master_config;
10779 int32_t ret;
10780
10781 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
10782
10783 if (ret == 0)
10784 {
10785 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
10786 (uint8_t *)&master_config, 1);
10787 }
10788
10789 if (ret == 0)
10790 {
10791 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10792 }
10793
10794 switch (master_config.aux_sens_on)
10795 {
10796 case LSM6DSRX_SLV_0:
10797 *val = LSM6DSRX_SLV_0;
10798 break;
10799
10800 case LSM6DSRX_SLV_0_1:
10801 *val = LSM6DSRX_SLV_0_1;
10802 break;
10803
10804 case LSM6DSRX_SLV_0_1_2:
10805 *val = LSM6DSRX_SLV_0_1_2;
10806 break;
10807
10808 case LSM6DSRX_SLV_0_1_2_3:
10809 *val = LSM6DSRX_SLV_0_1_2_3;
10810 break;
10811
10812 default:
10813 *val = LSM6DSRX_SLV_0;
10814 break;
10815 }
10816
10817 return ret;
10818 }
10819
10820 /**
10821 * @brief Sensor hub I2C master enable.[set]
10822 *
10823 * @param ctx Read / write interface definitions.(ptr)
10824 * @param val Change the values of master_on in reg MASTER_CONFIG
10825 * @retval Interface status (MANDATORY: return 0 -> no Error).
10826 *
10827 */
lsm6dsrx_sh_master_set(stmdev_ctx_t * ctx,uint8_t val)10828 int32_t lsm6dsrx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
10829 {
10830 lsm6dsrx_master_config_t master_config;
10831 int32_t ret;
10832
10833 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
10834
10835 if (ret == 0)
10836 {
10837 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
10838 (uint8_t *)&master_config, 1);
10839 }
10840
10841 if (ret == 0)
10842 {
10843 master_config.master_on = (uint8_t)val;
10844 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
10845 (uint8_t *)&master_config, 1);
10846 }
10847
10848 if (ret == 0)
10849 {
10850 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10851 }
10852
10853 return ret;
10854 }
10855
10856 /**
10857 * @brief Sensor hub I2C master enable.[get]
10858 *
10859 * @param ctx Read / write interface definitions.(ptr)
10860 * @param val Change the values of master_on in reg MASTER_CONFIG
10861 * @retval Interface status (MANDATORY: return 0 -> no Error).
10862 *
10863 */
lsm6dsrx_sh_master_get(stmdev_ctx_t * ctx,uint8_t * val)10864 int32_t lsm6dsrx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
10865 {
10866 lsm6dsrx_master_config_t master_config;
10867 int32_t ret;
10868
10869 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
10870
10871 if (ret == 0)
10872 {
10873 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
10874 (uint8_t *)&master_config, 1);
10875 }
10876
10877 if (ret == 0)
10878 {
10879 *val = master_config.master_on;
10880 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10881 }
10882
10883 return ret;
10884 }
10885
10886 /**
10887 * @brief Master I2C pull-up enable.[set]
10888 *
10889 * @param ctx Read / write interface definitions.(ptr)
10890 * @param val Change the values of shub_pu_en in reg MASTER_CONFIG
10891 * @retval Interface status (MANDATORY: return 0 -> no Error).
10892 *
10893 */
lsm6dsrx_sh_pin_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_shub_pu_en_t val)10894 int32_t lsm6dsrx_sh_pin_mode_set(stmdev_ctx_t *ctx,
10895 lsm6dsrx_shub_pu_en_t val)
10896 {
10897 lsm6dsrx_master_config_t master_config;
10898 int32_t ret;
10899
10900 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
10901
10902 if (ret == 0)
10903 {
10904 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
10905 (uint8_t *)&master_config, 1);
10906 }
10907
10908 if (ret == 0)
10909 {
10910 master_config.shub_pu_en = (uint8_t)val;
10911 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
10912 (uint8_t *)&master_config, 1);
10913 }
10914
10915 if (ret == 0)
10916 {
10917 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10918 }
10919
10920 return ret;
10921 }
10922
10923 /**
10924 * @brief Master I2C pull-up enable.[get]
10925 *
10926 * @param ctx Read / write interface definitions.(ptr)
10927 * @param val Get the values of shub_pu_en in reg MASTER_CONFIG
10928 * @retval Interface status (MANDATORY: return 0 -> no Error).
10929 *
10930 */
lsm6dsrx_sh_pin_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_shub_pu_en_t * val)10931 int32_t lsm6dsrx_sh_pin_mode_get(stmdev_ctx_t *ctx,
10932 lsm6dsrx_shub_pu_en_t *val)
10933 {
10934 lsm6dsrx_master_config_t master_config;
10935 int32_t ret;
10936
10937 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
10938
10939 if (ret == 0)
10940 {
10941 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
10942 (uint8_t *)&master_config, 1);
10943 }
10944
10945 if (ret == 0)
10946 {
10947 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10948 }
10949
10950 switch (master_config.shub_pu_en)
10951 {
10952 case LSM6DSRX_EXT_PULL_UP:
10953 *val = LSM6DSRX_EXT_PULL_UP;
10954 break;
10955
10956 case LSM6DSRX_INTERNAL_PULL_UP:
10957 *val = LSM6DSRX_INTERNAL_PULL_UP;
10958 break;
10959
10960 default:
10961 *val = LSM6DSRX_EXT_PULL_UP;
10962 break;
10963 }
10964
10965 return ret;
10966 }
10967
10968 /**
10969 * @brief I2C interface pass-through.[set]
10970 *
10971 * @param ctx Read / write interface definitions.(ptr)
10972 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
10973 * @retval Interface status (MANDATORY: return 0 -> no Error).
10974 *
10975 */
lsm6dsrx_sh_pass_through_set(stmdev_ctx_t * ctx,uint8_t val)10976 int32_t lsm6dsrx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
10977 {
10978 lsm6dsrx_master_config_t master_config;
10979 int32_t ret;
10980
10981 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
10982
10983 if (ret == 0)
10984 {
10985 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
10986 (uint8_t *)&master_config, 1);
10987 }
10988
10989 if (ret == 0)
10990 {
10991 master_config.pass_through_mode = (uint8_t)val;
10992 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
10993 (uint8_t *)&master_config, 1);
10994 }
10995
10996 if (ret == 0)
10997 {
10998 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
10999 }
11000
11001 return ret;
11002 }
11003
11004 /**
11005 * @brief I2C interface pass-through.[get]
11006 *
11007 * @param ctx Read / write interface definitions.(ptr)
11008 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
11009 * @retval Interface status (MANDATORY: return 0 -> no Error).
11010 *
11011 */
lsm6dsrx_sh_pass_through_get(stmdev_ctx_t * ctx,uint8_t * val)11012 int32_t lsm6dsrx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
11013 {
11014 lsm6dsrx_master_config_t master_config;
11015 int32_t ret;
11016
11017 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11018
11019 if (ret == 0)
11020 {
11021 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11022 (uint8_t *)&master_config, 1);
11023 }
11024
11025 if (ret == 0)
11026 {
11027 *val = master_config.pass_through_mode;
11028 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11029 }
11030
11031 return ret;
11032 }
11033
11034 /**
11035 * @brief Sensor hub trigger signal selection.[set]
11036 *
11037 * @param ctx Read / write interface definitions.(ptr)
11038 * @param val Change the values of start_config in reg MASTER_CONFIG
11039 * @retval Interface status (MANDATORY: return 0 -> no Error).
11040 *
11041 */
lsm6dsrx_sh_syncro_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_start_config_t val)11042 int32_t lsm6dsrx_sh_syncro_mode_set(stmdev_ctx_t *ctx,
11043 lsm6dsrx_start_config_t val)
11044 {
11045 lsm6dsrx_master_config_t master_config;
11046 int32_t ret;
11047
11048 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11049
11050 if (ret == 0)
11051 {
11052 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11053 (uint8_t *)&master_config, 1);
11054 }
11055
11056 if (ret == 0)
11057 {
11058 master_config.start_config = (uint8_t)val;
11059 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11060 (uint8_t *)&master_config, 1);
11061 }
11062
11063 if (ret == 0)
11064 {
11065 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11066 }
11067
11068 return ret;
11069 }
11070
11071 /**
11072 * @brief Sensor hub trigger signal selection.[get]
11073 *
11074 * @param ctx Read / write interface definitions.(ptr)
11075 * @param val Get the values of start_config in reg MASTER_CONFIG
11076 * @retval Interface status (MANDATORY: return 0 -> no Error).
11077 *
11078 */
lsm6dsrx_sh_syncro_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_start_config_t * val)11079 int32_t lsm6dsrx_sh_syncro_mode_get(stmdev_ctx_t *ctx,
11080 lsm6dsrx_start_config_t *val)
11081 {
11082 lsm6dsrx_master_config_t master_config;
11083 int32_t ret;
11084
11085 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11086
11087 if (ret == 0)
11088 {
11089 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11090 (uint8_t *)&master_config, 1);
11091 }
11092
11093 if (ret == 0)
11094 {
11095 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11096 }
11097
11098 switch (master_config.start_config)
11099 {
11100 case LSM6DSRX_EXT_ON_INT2_PIN:
11101 *val = LSM6DSRX_EXT_ON_INT2_PIN;
11102 break;
11103
11104 case LSM6DSRX_XL_GY_DRDY:
11105 *val = LSM6DSRX_XL_GY_DRDY;
11106 break;
11107
11108 default:
11109 *val = LSM6DSRX_EXT_ON_INT2_PIN;
11110 break;
11111 }
11112
11113 return ret;
11114 }
11115
11116 /**
11117 * @brief Slave 0 write operation is performed only at the first sensor
11118 * hub cycle.[set]
11119 *
11120 * @param ctx Read / write interface definitions.(ptr)
11121 * @param val Change the values of write_once in reg MASTER_CONFIG
11122 * @retval Interface status (MANDATORY: return 0 -> no Error).
11123 *
11124 */
lsm6dsrx_sh_write_mode_set(stmdev_ctx_t * ctx,lsm6dsrx_write_once_t val)11125 int32_t lsm6dsrx_sh_write_mode_set(stmdev_ctx_t *ctx,
11126 lsm6dsrx_write_once_t val)
11127 {
11128 lsm6dsrx_master_config_t master_config;
11129 int32_t ret;
11130
11131 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11132
11133 if (ret == 0)
11134 {
11135 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11136 (uint8_t *)&master_config, 1);
11137 }
11138
11139 if (ret == 0)
11140 {
11141 master_config.write_once = (uint8_t)val;
11142 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11143 (uint8_t *)&master_config, 1);
11144 }
11145
11146 if (ret == 0)
11147 {
11148 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11149 }
11150
11151 return ret;
11152 }
11153
11154 /**
11155 * @brief Slave 0 write operation is performed only at the first sensor
11156 * hub cycle.[get]
11157 *
11158 * @param ctx Read / write interface definitions.(ptr)
11159 * @param val Get the values of write_once in reg MASTER_CONFIG
11160 * @retval Interface status (MANDATORY: return 0 -> no Error).
11161 *
11162 */
lsm6dsrx_sh_write_mode_get(stmdev_ctx_t * ctx,lsm6dsrx_write_once_t * val)11163 int32_t lsm6dsrx_sh_write_mode_get(stmdev_ctx_t *ctx,
11164 lsm6dsrx_write_once_t *val)
11165 {
11166 lsm6dsrx_master_config_t master_config;
11167 int32_t ret;
11168
11169 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11170
11171 if (ret == 0)
11172 {
11173 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11174 (uint8_t *)&master_config, 1);
11175 }
11176
11177 if (ret == 0)
11178 {
11179 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11180 }
11181
11182 switch (master_config.write_once)
11183 {
11184 case LSM6DSRX_EACH_SH_CYCLE:
11185 *val = LSM6DSRX_EACH_SH_CYCLE;
11186 break;
11187
11188 case LSM6DSRX_ONLY_FIRST_CYCLE:
11189 *val = LSM6DSRX_ONLY_FIRST_CYCLE;
11190 break;
11191
11192 default:
11193 *val = LSM6DSRX_EACH_SH_CYCLE;
11194 break;
11195 }
11196
11197 return ret;
11198 }
11199
11200 /**
11201 * @brief Reset Master logic and output registers.[set]
11202 *
11203 * @param ctx Read / write interface definitions.(ptr)
11204 * @retval Interface status (MANDATORY: return 0 -> no Error).
11205 *
11206 */
lsm6dsrx_sh_reset_set(stmdev_ctx_t * ctx)11207 int32_t lsm6dsrx_sh_reset_set(stmdev_ctx_t *ctx)
11208 {
11209 lsm6dsrx_master_config_t master_config;
11210 int32_t ret;
11211
11212 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11213
11214 if (ret == 0)
11215 {
11216 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11217 (uint8_t *)&master_config, 1);
11218 }
11219
11220 if (ret == 0)
11221 {
11222 master_config.rst_master_regs = PROPERTY_ENABLE;
11223 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11224 (uint8_t *)&master_config, 1);
11225 }
11226
11227 if (ret == 0)
11228 {
11229 master_config.rst_master_regs = PROPERTY_DISABLE;
11230 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11231 (uint8_t *)&master_config, 1);
11232 }
11233
11234 if (ret == 0)
11235 {
11236 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11237 }
11238
11239 return ret;
11240 }
11241
11242 /**
11243 * @brief Reset Master logic and output registers.[get]
11244 *
11245 * @param ctx Read / write interface definitions.(ptr)
11246 * @param val Change the values of rst_master_regs in reg MASTER_CONFIG
11247 * @retval Interface status (MANDATORY: return 0 -> no Error).
11248 *
11249 */
lsm6dsrx_sh_reset_get(stmdev_ctx_t * ctx,uint8_t * val)11250 int32_t lsm6dsrx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
11251 {
11252 lsm6dsrx_master_config_t master_config;
11253 int32_t ret;
11254
11255 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11256
11257 if (ret == 0)
11258 {
11259 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_MASTER_CONFIG,
11260 (uint8_t *)&master_config, 1);
11261 *val = master_config.rst_master_regs;
11262 }
11263
11264 if (ret == 0)
11265 {
11266 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11267 }
11268
11269 return ret;
11270 }
11271
11272 /**
11273 * @brief Rate at which the master communicates.[set]
11274 *
11275 * @param ctx Read / write interface definitions.(ptr)
11276 * @param val Change the values of shub_odr in reg SLV0_CONFIG
11277 * @retval Interface status (MANDATORY: return 0 -> no Error).
11278 *
11279 */
lsm6dsrx_sh_data_rate_set(stmdev_ctx_t * ctx,lsm6dsrx_shub_odr_t val)11280 int32_t lsm6dsrx_sh_data_rate_set(stmdev_ctx_t *ctx,
11281 lsm6dsrx_shub_odr_t val)
11282 {
11283 lsm6dsrx_slv0_config_t slv0_config;
11284 int32_t ret;
11285
11286 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11287
11288 if (ret == 0)
11289 {
11290 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV0_CONFIG,
11291 (uint8_t *)&slv0_config, 1);
11292 }
11293
11294 if (ret == 0)
11295 {
11296 slv0_config.shub_odr = (uint8_t)val;
11297 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_CONFIG,
11298 (uint8_t *)&slv0_config, 1);
11299 }
11300
11301 if (ret == 0)
11302 {
11303 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11304 }
11305
11306 return ret;
11307 }
11308
11309 /**
11310 * @brief Rate at which the master communicates.[get]
11311 *
11312 * @param ctx Read / write interface definitions.(ptr)
11313 * @param val Get the values of shub_odr in reg slv1_CONFIG
11314 * @retval Interface status (MANDATORY: return 0 -> no Error).
11315 *
11316 */
lsm6dsrx_sh_data_rate_get(stmdev_ctx_t * ctx,lsm6dsrx_shub_odr_t * val)11317 int32_t lsm6dsrx_sh_data_rate_get(stmdev_ctx_t *ctx,
11318 lsm6dsrx_shub_odr_t *val)
11319 {
11320 lsm6dsrx_slv0_config_t slv0_config;
11321 int32_t ret;
11322
11323 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11324
11325 if (ret == 0)
11326 {
11327 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV0_CONFIG,
11328 (uint8_t *)&slv0_config, 1);
11329 }
11330
11331 if (ret == 0)
11332 {
11333 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11334 }
11335
11336 switch (slv0_config.shub_odr)
11337 {
11338 case LSM6DSRX_SH_ODR_104Hz:
11339 *val = LSM6DSRX_SH_ODR_104Hz;
11340 break;
11341
11342 case LSM6DSRX_SH_ODR_52Hz:
11343 *val = LSM6DSRX_SH_ODR_52Hz;
11344 break;
11345
11346 case LSM6DSRX_SH_ODR_26Hz:
11347 *val = LSM6DSRX_SH_ODR_26Hz;
11348 break;
11349
11350 case LSM6DSRX_SH_ODR_13Hz:
11351 *val = LSM6DSRX_SH_ODR_13Hz;
11352 break;
11353
11354 default:
11355 *val = LSM6DSRX_SH_ODR_104Hz;
11356 break;
11357 }
11358
11359 return ret;
11360 }
11361
11362 /**
11363 * @brief Configure slave 0 for perform a write.[set]
11364 *
11365 * @param ctx Read / write interface definitions.(ptr)
11366 * @param val Structure that contain
11367 * - uint8_t slv0_add; 8 bit i2c device address
11368 * - uint8_t slv0_subadd; 8 bit register device address
11369 * - uint8_t slv0_data; 8 bit data to write
11370 * @retval Interface status (MANDATORY: return 0 -> no Error).
11371 *
11372 */
lsm6dsrx_sh_cfg_write(stmdev_ctx_t * ctx,lsm6dsrx_sh_cfg_write_t * val)11373 int32_t lsm6dsrx_sh_cfg_write(stmdev_ctx_t *ctx,
11374 lsm6dsrx_sh_cfg_write_t *val)
11375 {
11376 lsm6dsrx_slv0_add_t slv0_add;
11377 int32_t ret;
11378
11379 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11380
11381 if (ret == 0)
11382 {
11383 slv0_add.slave0 = (uint8_t)(val->slv0_add >> 1);
11384 slv0_add.rw_0 = 0;
11385 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_ADD,
11386 (uint8_t *) & (slv0_add), 1);
11387 }
11388
11389 if (ret == 0)
11390 {
11391 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_SUBADD,
11392 (uint8_t *) & (val->slv0_subadd), 1);
11393 }
11394
11395 if (ret == 0)
11396 {
11397 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_DATAWRITE_SLV0,
11398 (uint8_t *) & (val->slv0_data), 1);
11399 }
11400
11401 if (ret == 0)
11402 {
11403 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11404 }
11405
11406 return ret;
11407 }
11408
11409 /**
11410 * @brief Configure slave 0 for perform a write/read.[get]
11411 *
11412 * @param ctx Read / write interface definitions.(ptr)
11413 * @param val Structure that contain
11414 * - uint8_t slv_add; 8 bit i2c device address
11415 * - uint8_t slv_subadd; 8 bit register device address
11416 * - uint8_t slv_len; num of bit to read
11417 * @retval Interface status (MANDATORY: return 0 -> no Error).
11418 *
11419 */
lsm6dsrx_sh_slv0_cfg_read(stmdev_ctx_t * ctx,lsm6dsrx_sh_cfg_read_t * val)11420 int32_t lsm6dsrx_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
11421 lsm6dsrx_sh_cfg_read_t *val)
11422 {
11423 lsm6dsrx_slv0_config_t slv0_config;
11424 lsm6dsrx_slv0_add_t slv0_add;
11425 int32_t ret;
11426
11427 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11428
11429 if (ret == 0)
11430 {
11431 slv0_add.slave0 = (uint8_t) val->slv_add >> 1;
11432 slv0_add.rw_0 = 1;
11433 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_ADD,
11434 (uint8_t *) & (slv0_add), 1);
11435 }
11436
11437 if (ret == 0)
11438 {
11439 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_SUBADD,
11440 &(val->slv_subadd), 1);
11441 }
11442
11443 if (ret == 0)
11444 {
11445 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV0_CONFIG,
11446 (uint8_t *)&slv0_config, 1);
11447 }
11448
11449 if (ret == 0)
11450 {
11451 slv0_config.slave0_numop = val->slv_len;
11452 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV0_CONFIG,
11453 (uint8_t *)&slv0_config, 1);
11454 }
11455
11456 if (ret == 0)
11457 {
11458 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11459 }
11460
11461 return ret;
11462 }
11463
11464 /**
11465 * @brief Configure slave 0 for perform a write/read.[get]
11466 *
11467 * @param ctx Read / write interface definitions.(ptr)
11468 * @param val Structure that contain
11469 * - uint8_t slv_add; 8 bit i2c device address
11470 * - uint8_t slv_subadd; 8 bit register device address
11471 * - uint8_t slv_len; num of bit to read
11472 * @retval Interface status (MANDATORY: return 0 -> no Error).
11473 *
11474 */
lsm6dsrx_sh_slv1_cfg_read(stmdev_ctx_t * ctx,lsm6dsrx_sh_cfg_read_t * val)11475 int32_t lsm6dsrx_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
11476 lsm6dsrx_sh_cfg_read_t *val)
11477 {
11478 lsm6dsrx_slv1_config_t slv1_config;
11479 lsm6dsrx_slv1_add_t slv1_add;
11480 int32_t ret;
11481
11482 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11483
11484 if (ret == 0)
11485 {
11486 slv1_add.slave1_add = (uint8_t)(val->slv_add >> 1);
11487 slv1_add.r_1 = 1;
11488 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV1_ADD, (uint8_t *)&slv1_add, 1);
11489 }
11490
11491 if (ret == 0)
11492 {
11493 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV1_SUBADD,
11494 &(val->slv_subadd), 1);
11495 }
11496
11497 if (ret == 0)
11498 {
11499 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV1_CONFIG,
11500 (uint8_t *)&slv1_config, 1);
11501 }
11502
11503 if (ret == 0)
11504 {
11505 slv1_config.slave1_numop = val->slv_len;
11506 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV1_CONFIG,
11507 (uint8_t *)&slv1_config, 1);
11508 }
11509
11510 if (ret == 0)
11511 {
11512 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11513 }
11514
11515 return ret;
11516 }
11517
11518 /**
11519 * @brief Configure slave 2 for perform a write/read.[get]
11520 *
11521 * @param ctx Read / write interface definitions.(ptr)
11522 * @param val Structure that contain
11523 * - uint8_t slv_add; 8 bit i2c device address
11524 * - uint8_t slv_subadd; 8 bit register device address
11525 * - uint8_t slv_len; num of bit to read
11526 * @retval Interface status (MANDATORY: return 0 -> no Error).
11527 *
11528 */
lsm6dsrx_sh_slv2_cfg_read(stmdev_ctx_t * ctx,lsm6dsrx_sh_cfg_read_t * val)11529 int32_t lsm6dsrx_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
11530 lsm6dsrx_sh_cfg_read_t *val)
11531 {
11532 lsm6dsrx_slv2_config_t slv2_config;
11533 lsm6dsrx_slv2_add_t slv2_add;
11534 int32_t ret;
11535
11536 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11537
11538 if (ret == 0)
11539 {
11540 slv2_add.slave2_add = (uint8_t)(val->slv_add >> 1);
11541 slv2_add.r_2 = 1;
11542 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV2_ADD,
11543 (uint8_t *)&slv2_add, 1);
11544 }
11545
11546 if (ret == 0)
11547 {
11548 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV2_SUBADD,
11549 (uint8_t *) & (val->slv_subadd), 1);
11550 }
11551
11552 if (ret == 0)
11553 {
11554 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV2_CONFIG,
11555 (uint8_t *)&slv2_config, 1);
11556 }
11557
11558 if (ret == 0)
11559 {
11560 slv2_config.slave2_numop = val->slv_len;
11561 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV2_CONFIG,
11562 (uint8_t *)&slv2_config, 1);
11563 }
11564
11565 if (ret == 0)
11566 {
11567 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11568 }
11569
11570 return ret;
11571 }
11572
11573 /**
11574 * @brief Configure slave 3 for perform a write/read.[get]
11575 *
11576 * @param ctx Read / write interface definitions.(ptr)
11577 * @param val Structure that contain
11578 * - uint8_t slv_add; 8 bit i2c device address
11579 * - uint8_t slv_subadd; 8 bit register device address
11580 * - uint8_t slv_len; num of bit to read
11581 * @retval Interface status (MANDATORY: return 0 -> no Error).
11582 *
11583 */
lsm6dsrx_sh_slv3_cfg_read(stmdev_ctx_t * ctx,lsm6dsrx_sh_cfg_read_t * val)11584 int32_t lsm6dsrx_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
11585 lsm6dsrx_sh_cfg_read_t *val)
11586 {
11587 lsm6dsrx_slv3_config_t slv3_config;
11588 lsm6dsrx_slv3_add_t slv3_add;
11589 int32_t ret;
11590
11591 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11592
11593 if (ret == 0)
11594 {
11595 slv3_add.slave3_add = (uint8_t)(val->slv_add >> 1);
11596 slv3_add.r_3 = 1;
11597 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV3_ADD,
11598 (uint8_t *)&slv3_add, 1);
11599 }
11600
11601 if (ret == 0)
11602 {
11603 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV3_SUBADD,
11604 &(val->slv_subadd), 1);
11605 }
11606
11607 if (ret == 0)
11608 {
11609 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_SLV3_CONFIG,
11610 (uint8_t *)&slv3_config, 1);
11611 }
11612
11613 if (ret == 0)
11614 {
11615 slv3_config.slave3_numop = val->slv_len;
11616 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_SLV3_CONFIG,
11617 (uint8_t *)&slv3_config, 1);
11618 }
11619
11620 if (ret == 0)
11621 {
11622 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11623 }
11624
11625 return ret;
11626 }
11627
11628 /**
11629 * @brief Sensor hub source register.[get]
11630 *
11631 * @param ctx Read / write interface definitions.(ptr)
11632 * @param val Registers from STATUS_MASTER
11633 * @retval Interface status (MANDATORY: return 0 -> no Error).
11634 *
11635 */
lsm6dsrx_sh_status_get(stmdev_ctx_t * ctx,lsm6dsrx_status_master_t * val)11636 int32_t lsm6dsrx_sh_status_get(stmdev_ctx_t *ctx,
11637 lsm6dsrx_status_master_t *val)
11638 {
11639 int32_t ret;
11640
11641 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_SENSOR_HUB_BANK);
11642
11643 if (ret == 0)
11644 {
11645 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_STATUS_MASTER, (uint8_t *)val, 1);
11646 }
11647
11648 if (ret == 0)
11649 {
11650 ret = lsm6dsrx_mem_bank_set(ctx, LSM6DSRX_USER_BANK);
11651 }
11652
11653 return ret;
11654 }
11655
11656 /**
11657 * @}
11658 *
11659 */
11660
11661 /**
11662 * @defgroup LSM6DSRX_Sensors for Smart Mobile Devices
11663 * @brief This section groups all the functions that manage the
11664 * Sensors for Smart Mobile Devices.
11665 * @{
11666 *
11667 */
11668
11669 /**
11670 * @brief Sensor synchronization time frame resolution[set]
11671 *
11672 * @param ctx Read / write interface definitions.(ptr)
11673 * @param val Change the values of tph_h_sel in LSM6DSRX_S4S_TPH_L
11674 * @retval Interface status (MANDATORY: return 0 -> no Error).
11675 *
11676 */
lsm6dsrx_s4s_tph_res_set(stmdev_ctx_t * ctx,lsm6dsrx_s4s_tph_res_t val)11677 int32_t lsm6dsrx_s4s_tph_res_set(stmdev_ctx_t *ctx,
11678 lsm6dsrx_s4s_tph_res_t val)
11679 {
11680 lsm6dsrx_s4s_tph_l_t s4s_tph_l;
11681 int32_t ret;
11682
11683 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_L,
11684 (uint8_t *)&s4s_tph_l, 1);
11685
11686 if (ret == 0)
11687 {
11688 s4s_tph_l.tph_h_sel = (uint8_t)val;
11689 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_S4S_TPH_L,
11690 (uint8_t *)&s4s_tph_l, 1);
11691 }
11692
11693 return ret;
11694 }
11695
11696 /**
11697 * @brief Sensor synchronization time frame resolution.[get]
11698 *
11699 * @param ctx Read / write interface definitions.(ptr)
11700 * @param val Get the values of tph_h_sel in LSM6DSRX_S4S_TPH_L
11701 * @retval Interface status (MANDATORY: return 0 -> no Error).
11702 *
11703 */
lsm6dsrx_s4s_tph_res_get(stmdev_ctx_t * ctx,lsm6dsrx_s4s_tph_res_t * val)11704 int32_t lsm6dsrx_s4s_tph_res_get(stmdev_ctx_t *ctx,
11705 lsm6dsrx_s4s_tph_res_t *val)
11706 {
11707 lsm6dsrx_s4s_tph_l_t s4s_tph_l;
11708 int32_t ret;
11709
11710 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_L,
11711 (uint8_t *)&s4s_tph_l, 1);
11712
11713 switch (s4s_tph_l.tph_h_sel)
11714 {
11715 case LSM6DSRX_S4S_TPH_7bit:
11716 *val = LSM6DSRX_S4S_TPH_7bit;
11717 break;
11718
11719 case LSM6DSRX_S4S_TPH_15bit:
11720 *val = LSM6DSRX_S4S_TPH_15bit;
11721 break;
11722
11723 default:
11724 *val = LSM6DSRX_S4S_TPH_7bit;
11725 break;
11726 }
11727
11728 return ret;
11729 }
11730
11731 /**
11732 * @brief Sensor synchronization time frame.[set]
11733 *
11734 * @param ctx Read / write interface definitions.(ptr)
11735 * @param val Change the values of tph_l in S4S_TPH_L and
11736 * tph_h in S4S_TPH_H
11737 * @retval Interface status (MANDATORY: return 0 -> no Error).
11738 *
11739 */
lsm6dsrx_s4s_tph_val_set(stmdev_ctx_t * ctx,uint16_t val)11740 int32_t lsm6dsrx_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val)
11741 {
11742 lsm6dsrx_s4s_tph_l_t s4s_tph_l;
11743 lsm6dsrx_s4s_tph_h_t s4s_tph_h;
11744 int32_t ret;
11745
11746 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_L,
11747 (uint8_t *)&s4s_tph_l, 1);
11748
11749 if (ret == 0)
11750 {
11751 s4s_tph_l.tph_l = (uint8_t)(val & 0x007FU);
11752 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_S4S_TPH_L,
11753 (uint8_t *)&s4s_tph_l, 1);
11754 }
11755
11756 if (ret == 0)
11757 {
11758 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_H,
11759 (uint8_t *)&s4s_tph_h, 1);
11760 }
11761
11762 if (ret == 0)
11763 {
11764 s4s_tph_h.tph_h = (uint8_t)((val & 0x7F80U) >> 7);
11765 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_S4S_TPH_H,
11766 (uint8_t *)&s4s_tph_h, 1);
11767 }
11768
11769 return ret;
11770 }
11771
11772 /**
11773 * @brief Sensor synchronization time frame.[get]
11774 *
11775 * @param ctx Read / write interface definitions.(ptr)
11776 * @param val Get the values of tph_l in S4S_TPH_L and tph_h in S4S_TPH_H
11777 * @retval Interface status (MANDATORY: return 0 -> no Error).
11778 *
11779 */
lsm6dsrx_s4s_tph_val_get(stmdev_ctx_t * ctx,uint16_t * val)11780 int32_t lsm6dsrx_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val)
11781 {
11782 lsm6dsrx_s4s_tph_l_t s4s_tph_l;
11783 lsm6dsrx_s4s_tph_h_t s4s_tph_h;
11784 int32_t ret;
11785
11786 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_L,
11787 (uint8_t *)&s4s_tph_l, 1);
11788
11789 if (ret == 0)
11790 {
11791 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_TPH_H,
11792 (uint8_t *)&s4s_tph_h, 1);
11793 }
11794
11795 *val = s4s_tph_h.tph_h;
11796 *val = *val << 7;
11797 *val += s4s_tph_l.tph_l;
11798
11799 return ret;
11800 }
11801
11802 /**
11803 * @brief Sensor synchronization resolution ratio register.[set]
11804 *
11805 * @param ctx Read / write interface definitions.(ptr)
11806 * @param val Change the values of rr in S4S_RR.
11807 * @retval Interface status (MANDATORY: return 0 -> no Error).
11808 *
11809 */
lsm6dsrx_s4s_res_ratio_set(stmdev_ctx_t * ctx,lsm6dsrx_s4s_res_ratio_t val)11810 int32_t lsm6dsrx_s4s_res_ratio_set(stmdev_ctx_t *ctx,
11811 lsm6dsrx_s4s_res_ratio_t val)
11812 {
11813 lsm6dsrx_s4s_rr_t s4s_rr;
11814 int32_t ret;
11815
11816 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_RR, (uint8_t *)&s4s_rr, 1);
11817
11818 if (ret == 0)
11819 {
11820 s4s_rr.rr = (uint8_t)val;
11821 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_S4S_RR, (uint8_t *)&s4s_rr, 1);
11822 }
11823
11824 return ret;
11825 }
11826
11827 /**
11828 * @brief Sensor synchronization resolution ratio register.[get]
11829 *
11830 * @param ctx Read / write interface definitions.(ptr)
11831 * @param val get the values of rr in S4S_RR
11832 * @retval Interface status (MANDATORY: return 0 -> no Error).
11833 *
11834 */
lsm6dsrx_s4s_res_ratio_get(stmdev_ctx_t * ctx,lsm6dsrx_s4s_res_ratio_t * val)11835 int32_t lsm6dsrx_s4s_res_ratio_get(stmdev_ctx_t *ctx,
11836 lsm6dsrx_s4s_res_ratio_t *val)
11837 {
11838 lsm6dsrx_s4s_rr_t s4s_rr;
11839 int32_t ret;
11840
11841 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_RR, (uint8_t *)&s4s_rr, 1);
11842
11843 switch (s4s_rr.rr)
11844 {
11845 case LSM6DSRX_S4S_DT_RES_11:
11846 *val = LSM6DSRX_S4S_DT_RES_11;
11847 break;
11848
11849 case LSM6DSRX_S4S_DT_RES_12:
11850 *val = LSM6DSRX_S4S_DT_RES_12;
11851 break;
11852
11853 case LSM6DSRX_S4S_DT_RES_13:
11854 *val = LSM6DSRX_S4S_DT_RES_13;
11855 break;
11856
11857 case LSM6DSRX_S4S_DT_RES_14:
11858 *val = LSM6DSRX_S4S_DT_RES_14;
11859 break;
11860
11861 default:
11862 *val = LSM6DSRX_S4S_DT_RES_11;
11863 break;
11864 }
11865
11866 return ret;
11867 }
11868
11869 /**
11870 * @brief s4s master command.[set]
11871 *
11872 * @param ctx Read / write interface definitions.(ptr)
11873 * @param val Change the values of S4S_ST_CMD_CODE.
11874 * @retval Interface status (MANDATORY: return 0 -> no Error).
11875 *
11876 */
lsm6dsrx_s4s_command_set(stmdev_ctx_t * ctx,uint8_t val)11877 int32_t lsm6dsrx_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val)
11878 {
11879 lsm6dsrx_s4s_st_cmd_code_t s4s_st_cmd_code;
11880 int32_t ret;
11881
11882 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_ST_CMD_CODE,
11883 (uint8_t *)&s4s_st_cmd_code, 1);
11884
11885 if (ret == 0)
11886 {
11887 s4s_st_cmd_code.s4s_st_cmd_code = (uint8_t)val;
11888 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_S4S_ST_CMD_CODE,
11889 (uint8_t *)&s4s_st_cmd_code, 1);
11890 }
11891
11892 return ret;
11893 }
11894
11895 /**
11896 * @brief s4s master command.[get]
11897 *
11898 * @param ctx Read / write interface definitions.(ptr)
11899 * @param val get the values of S4S_ST_CMD_CODE.
11900 * @retval Interface status (MANDATORY: return 0 -> no Error).
11901 *
11902 */
lsm6dsrx_s4s_command_get(stmdev_ctx_t * ctx,uint8_t * val)11903 int32_t lsm6dsrx_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val)
11904 {
11905 lsm6dsrx_s4s_st_cmd_code_t s4s_st_cmd_code;
11906 int32_t ret;
11907
11908 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_ST_CMD_CODE,
11909 (uint8_t *)&s4s_st_cmd_code, 1);
11910 *val = s4s_st_cmd_code.s4s_st_cmd_code;
11911
11912 return ret;
11913 }
11914
11915 /**
11916 * @brief S4S DT register.[set]
11917 *
11918 * @param ctx Read / write interface definitions.(ptr)
11919 * @param val Change the values of S4S_DT_REG.
11920 * @retval Interface status (MANDATORY: return 0 -> no Error).
11921 *
11922 */
lsm6dsrx_s4s_dt_set(stmdev_ctx_t * ctx,uint8_t val)11923 int32_t lsm6dsrx_s4s_dt_set(stmdev_ctx_t *ctx, uint8_t val)
11924 {
11925 lsm6dsrx_s4s_dt_reg_t s4s_dt_reg;
11926 int32_t ret;
11927
11928 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_DT_REG,
11929 (uint8_t *)&s4s_dt_reg, 1);
11930
11931 if (ret == 0)
11932 {
11933 s4s_dt_reg.dt = (uint8_t)val;
11934 ret = lsm6dsrx_write_reg(ctx, LSM6DSRX_S4S_DT_REG,
11935 (uint8_t *)&s4s_dt_reg, 1);
11936 }
11937
11938 return ret;
11939 }
11940
11941 /**
11942 * @brief S4S DT register.[get]
11943 *
11944 * @param ctx Read / write interface definitions.(ptr)
11945 * @param val get the values of S4S_DT_REG.
11946 * @retval Interface status (MANDATORY: return 0 -> no Error).
11947 *
11948 */
lsm6dsrx_s4s_dt_get(stmdev_ctx_t * ctx,uint8_t * val)11949 int32_t lsm6dsrx_s4s_dt_get(stmdev_ctx_t *ctx, uint8_t *val)
11950 {
11951 lsm6dsrx_s4s_dt_reg_t s4s_dt_reg;
11952 int32_t ret;
11953
11954 ret = lsm6dsrx_read_reg(ctx, LSM6DSRX_S4S_DT_REG,
11955 (uint8_t *)&s4s_dt_reg, 1);
11956 *val = s4s_dt_reg.dt;
11957
11958 return ret;
11959 }
11960
11961 /**
11962 * @}
11963 *
11964 */
11965
11966 /**
11967 * @}
11968 *
11969 */
11970
11971 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
11972
