1 /**
2   ******************************************************************************
3   * @file    lsm6dsrx_reg.h
4   * @author  Sensor Solutions Software Team
5   * @brief   This file contains all the functions prototypes for the
6   *          lsm6dsrx_reg.c driver.
7   ******************************************************************************
8   * @attention
9   *
10   * <h2><center>&copy; Copyright (c) 2021 STMicroelectronics.
11   * All rights reserved.</center></h2>
12   *
13   * This software component is licensed by ST under BSD 3-Clause license,
14   * the "License"; You may not use this file except in compliance with the
15   * License. You may obtain a copy of the License at:
16   *                        opensource.org/licenses/BSD-3-Clause
17   *
18   ******************************************************************************
19   */
20 
21 /* Define to prevent recursive inclusion -------------------------------------*/
22 #ifndef LSM6DSRX_REGS_H
23 #define LSM6DSRX_REGS_H
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
29 /* Includes ------------------------------------------------------------------*/
30 #include <stdint.h>
31 #include <stddef.h>
32 #include <math.h>
33 
34 /** @addtogroup LSM6DSRX
35   * @{
36   *
37   */
38 
39 /** @defgroup  Endianness definitions
40   * @{
41   *
42   */
43 
44 #ifndef DRV_BYTE_ORDER
45 #ifndef __BYTE_ORDER__
46 
47 #define DRV_LITTLE_ENDIAN 1234
48 #define DRV_BIG_ENDIAN    4321
49 
50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture
51   * by uncommenting the define which fits your platform endianness
52   */
53 //#define DRV_BYTE_ORDER    DRV_BIG_ENDIAN
54 #define DRV_BYTE_ORDER    DRV_LITTLE_ENDIAN
55 
56 #else /* defined __BYTE_ORDER__ */
57 
58 #define DRV_LITTLE_ENDIAN  __ORDER_LITTLE_ENDIAN__
59 #define DRV_BIG_ENDIAN     __ORDER_BIG_ENDIAN__
60 #define DRV_BYTE_ORDER     __BYTE_ORDER__
61 
62 #endif /* __BYTE_ORDER__*/
63 #endif /* DRV_BYTE_ORDER */
64 
65 /**
66   * @}
67   *
68   */
69 
70 /** @defgroup STMicroelectronics sensors common types
71   * @{
72   *
73   */
74 
75 #ifndef MEMS_SHARED_TYPES
76 #define MEMS_SHARED_TYPES
77 
78 typedef struct
79 {
80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
81   uint8_t bit0       : 1;
82   uint8_t bit1       : 1;
83   uint8_t bit2       : 1;
84   uint8_t bit3       : 1;
85   uint8_t bit4       : 1;
86   uint8_t bit5       : 1;
87   uint8_t bit6       : 1;
88   uint8_t bit7       : 1;
89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
90   uint8_t bit7       : 1;
91   uint8_t bit6       : 1;
92   uint8_t bit5       : 1;
93   uint8_t bit4       : 1;
94   uint8_t bit3       : 1;
95   uint8_t bit2       : 1;
96   uint8_t bit1       : 1;
97   uint8_t bit0       : 1;
98 #endif /* DRV_BYTE_ORDER */
99 } bitwise_t;
100 
101 #define PROPERTY_DISABLE                (0U)
102 #define PROPERTY_ENABLE                 (1U)
103 
104 /** @addtogroup  Interfaces_Functions
105   * @brief       This section provide a set of functions used to read and
106   *              write a generic register of the device.
107   *              MANDATORY: return 0 -> no Error.
108   * @{
109   *
110   */
111 
112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t);
113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t);
114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec);
115 
116 typedef struct
117 {
118   /** Component mandatory fields **/
119   stmdev_write_ptr  write_reg;
120   stmdev_read_ptr   read_reg;
121   /** Component optional fields **/
122   stmdev_mdelay_ptr   mdelay;
123   /** Customizable optional pointer **/
124   void *handle;
125 } stmdev_ctx_t;
126 
127 /**
128   * @}
129   *
130   */
131 
132 #endif /* MEMS_SHARED_TYPES */
133 
134 #ifndef MEMS_UCF_SHARED_TYPES
135 #define MEMS_UCF_SHARED_TYPES
136 
137 /** @defgroup    Generic address-data structure definition
138   * @brief       This structure is useful to load a predefined configuration
139   *              of a sensor.
140   *              You can create a sensor configuration by your own or using
141   *              Unico / Unicleo tools available on STMicroelectronics
142   *              web site.
143   *
144   * @{
145   *
146   */
147 
148 typedef struct
149 {
150   uint8_t address;
151   uint8_t data;
152 } ucf_line_t;
153 
154 /**
155   * @}
156   *
157   */
158 
159 #endif /* MEMS_UCF_SHARED_TYPES */
160 
161 /**
162   * @}
163   *
164   */
165 
166 /** @defgroup LSM6DSRX Infos
167   * @{
168   *
169   */
170 
171 /** I2C Device Address 8 bit format  if SA0=0 -> D5 if SA0=1 -> D7 **/
172 #define LSM6DSRX_I2C_ADD_L                    0xD5U
173 #define LSM6DSRX_I2C_ADD_H                    0xD7U
174 
175 /** Device Identification (Who am I) **/
176 #define LSM6DSRX_ID                           0x6BU
177 
178 /**
179   * @}
180   *
181   */
182 
183 #define LSM6DSRX_FUNC_CFG_ACCESS              0x01U
184 typedef struct
185 {
186 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
187   uint8_t not_used_01              : 6;
188 uint8_t reg_access               :
189   2; /* shub_reg_access + func_cfg_access */
190 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
191 uint8_t reg_access               :
192   2; /* shub_reg_access + func_cfg_access */
193   uint8_t not_used_01              : 6;
194 #endif /* DRV_BYTE_ORDER */
195 } lsm6dsrx_func_cfg_access_t;
196 
197 #define LSM6DSRX_PIN_CTRL                     0x02U
198 typedef struct
199 {
200 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
201   uint8_t not_used_01              : 6;
202   uint8_t sdo_pu_en                : 1;
203   uint8_t ois_pu_dis               : 1;
204 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
205   uint8_t ois_pu_dis               : 1;
206   uint8_t sdo_pu_en                : 1;
207   uint8_t not_used_01              : 6;
208 #endif /* DRV_BYTE_ORDER */
209 } lsm6dsrx_pin_ctrl_t;
210 
211 #define LSM6DSRX_S4S_TPH_L                    0x04U
212 typedef struct
213 {
214 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
215   uint8_t tph_l                    : 7;
216   uint8_t tph_h_sel                : 1;
217 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
218   uint8_t tph_h_sel                : 1;
219   uint8_t tph_l                    : 7;
220 #endif /* DRV_BYTE_ORDER */
221 } lsm6dsrx_s4s_tph_l_t;
222 
223 #define LSM6DSRX_S4S_TPH_H                    0x05U
224 typedef struct
225 {
226   uint8_t tph_h                    : 8;
227 } lsm6dsrx_s4s_tph_h_t;
228 
229 #define LSM6DSRX_S4S_RR                       0x06U
230 typedef struct
231 {
232 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
233   uint8_t rr                       : 2;
234   uint8_t not_used_01              : 6;
235 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
236   uint8_t not_used_01              : 6;
237   uint8_t rr                       : 2;
238 #endif /* DRV_BYTE_ORDER */
239 } lsm6dsrx_s4s_rr_t;
240 
241 #define LSM6DSRX_FIFO_CTRL1                   0x07U
242 typedef struct
243 {
244   uint8_t wtm                      : 8;
245 } lsm6dsrx_fifo_ctrl1_t;
246 
247 #define LSM6DSRX_FIFO_CTRL2                   0x08U
248 typedef struct
249 {
250 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
251   uint8_t wtm                      : 1;
252   uint8_t uncoptr_rate             : 2;
253   uint8_t not_used_01              : 1;
254   uint8_t odrchg_en                : 1;
255   uint8_t not_used_02              : 1;
256   uint8_t fifo_compr_rt_en         : 1;
257   uint8_t stop_on_wtm              : 1;
258 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
259   uint8_t stop_on_wtm              : 1;
260   uint8_t fifo_compr_rt_en         : 1;
261   uint8_t not_used_02              : 1;
262   uint8_t odrchg_en                : 1;
263   uint8_t not_used_01              : 1;
264   uint8_t uncoptr_rate             : 2;
265   uint8_t wtm                      : 1;
266 #endif /* DRV_BYTE_ORDER */
267 } lsm6dsrx_fifo_ctrl2_t;
268 
269 #define LSM6DSRX_FIFO_CTRL3                   0x09U
270 typedef struct
271 {
272 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
273   uint8_t bdr_xl                   : 4;
274   uint8_t bdr_gy                   : 4;
275 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
276   uint8_t bdr_gy                   : 4;
277   uint8_t bdr_xl                   : 4;
278 #endif /* DRV_BYTE_ORDER */
279 } lsm6dsrx_fifo_ctrl3_t;
280 
281 #define LSM6DSRX_FIFO_CTRL4                   0x0AU
282 typedef struct
283 {
284 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
285   uint8_t fifo_mode                : 3;
286   uint8_t not_used_01              : 1;
287   uint8_t odr_t_batch              : 2;
288   uint8_t odr_ts_batch             : 2;
289 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
290   uint8_t odr_ts_batch             : 2;
291   uint8_t odr_t_batch              : 2;
292   uint8_t not_used_01              : 1;
293   uint8_t fifo_mode                : 3;
294 #endif /* DRV_BYTE_ORDER */
295 } lsm6dsrx_fifo_ctrl4_t;
296 
297 #define LSM6DSRX_COUNTER_BDR_REG1             0x0BU
298 typedef struct
299 {
300 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
301   uint8_t cnt_bdr_th               : 3;
302   uint8_t not_used_01              : 2;
303   uint8_t trig_counter_bdr         : 1;
304   uint8_t rst_counter_bdr          : 1;
305   uint8_t dataready_pulsed         : 1;
306 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
307   uint8_t dataready_pulsed         : 1;
308   uint8_t rst_counter_bdr          : 1;
309   uint8_t trig_counter_bdr         : 1;
310   uint8_t not_used_01              : 2;
311   uint8_t cnt_bdr_th               : 3;
312 #endif /* DRV_BYTE_ORDER */
313 } lsm6dsrx_counter_bdr_reg1_t;
314 
315 #define LSM6DSRX_COUNTER_BDR_REG2             0x0CU
316 typedef struct
317 {
318   uint8_t cnt_bdr_th               : 8;
319 } lsm6dsrx_counter_bdr_reg2_t;
320 
321 #define LSM6DSRX_INT1_CTRL                    0x0DU
322 typedef struct
323 {
324 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
325   uint8_t int1_drdy_xl             : 1;
326   uint8_t int1_drdy_g              : 1;
327   uint8_t int1_boot                : 1;
328   uint8_t int1_fifo_th             : 1;
329   uint8_t int1_fifo_ovr            : 1;
330   uint8_t int1_fifo_full           : 1;
331   uint8_t int1_cnt_bdr             : 1;
332   uint8_t den_drdy_flag            : 1;
333 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
334   uint8_t den_drdy_flag            : 1;
335   uint8_t int1_cnt_bdr             : 1;
336   uint8_t int1_fifo_full           : 1;
337   uint8_t int1_fifo_ovr            : 1;
338   uint8_t int1_fifo_th             : 1;
339   uint8_t int1_boot                : 1;
340   uint8_t int1_drdy_g              : 1;
341   uint8_t int1_drdy_xl             : 1;
342 #endif /* DRV_BYTE_ORDER */
343 } lsm6dsrx_int1_ctrl_t;
344 
345 #define LSM6DSRX_INT2_CTRL                    0x0EU
346 typedef struct
347 {
348 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
349   uint8_t int2_drdy_xl             : 1;
350   uint8_t int2_drdy_g              : 1;
351   uint8_t int2_drdy_temp           : 1;
352   uint8_t int2_fifo_th             : 1;
353   uint8_t int2_fifo_ovr            : 1;
354   uint8_t int2_fifo_full           : 1;
355   uint8_t int2_cnt_bdr             : 1;
356   uint8_t not_used_01              : 1;
357 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
358   uint8_t not_used_01              : 1;
359   uint8_t int2_cnt_bdr             : 1;
360   uint8_t int2_fifo_full           : 1;
361   uint8_t int2_fifo_ovr            : 1;
362   uint8_t int2_fifo_th             : 1;
363   uint8_t int2_drdy_temp           : 1;
364   uint8_t int2_drdy_g              : 1;
365   uint8_t int2_drdy_xl             : 1;
366 #endif /* DRV_BYTE_ORDER */
367 } lsm6dsrx_int2_ctrl_t;
368 
369 #define LSM6DSRX_WHO_AM_I                     0x0FU
370 #define LSM6DSRX_CTRL1_XL                     0x10U
371 typedef struct
372 {
373 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
374   uint8_t not_used_01              : 1;
375   uint8_t lpf2_xl_en               : 1;
376   uint8_t fs_xl                    : 2;
377   uint8_t odr_xl                   : 4;
378 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
379   uint8_t odr_xl                   : 4;
380   uint8_t fs_xl                    : 2;
381   uint8_t lpf2_xl_en               : 1;
382   uint8_t not_used_01              : 1;
383 #endif /* DRV_BYTE_ORDER */
384 } lsm6dsrx_ctrl1_xl_t;
385 
386 #define LSM6DSRX_CTRL2_G                      0x11U
387 typedef struct
388 {
389 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
390   uint8_t fs_g                     : 4; /* fs_4000 + fs_125 + fs_g */
391   uint8_t odr_g                    : 4;
392 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
393   uint8_t odr_g                    : 4;
394   uint8_t fs_g                     : 4; /* fs_4000 + fs_125 + fs_g */
395 #endif /* DRV_BYTE_ORDER */
396 } lsm6dsrx_ctrl2_g_t;
397 
398 #define LSM6DSRX_CTRL3_C                      0x12U
399 typedef struct
400 {
401 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
402   uint8_t sw_reset                 : 1;
403   uint8_t not_used_01              : 1;
404   uint8_t if_inc                   : 1;
405   uint8_t sim                      : 1;
406   uint8_t pp_od                    : 1;
407   uint8_t h_lactive                : 1;
408   uint8_t bdu                      : 1;
409   uint8_t boot                     : 1;
410 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
411   uint8_t boot                     : 1;
412   uint8_t bdu                      : 1;
413   uint8_t h_lactive                : 1;
414   uint8_t pp_od                    : 1;
415   uint8_t sim                      : 1;
416   uint8_t if_inc                   : 1;
417   uint8_t not_used_01              : 1;
418   uint8_t sw_reset                 : 1;
419 #endif /* DRV_BYTE_ORDER */
420 } lsm6dsrx_ctrl3_c_t;
421 
422 #define LSM6DSRX_CTRL4_C                      0x13U
423 typedef struct
424 {
425 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
426   uint8_t not_used_01              : 1;
427   uint8_t lpf1_sel_g               : 1;
428   uint8_t i2c_disable              : 1;
429   uint8_t drdy_mask                : 1;
430   uint8_t not_used_02              : 1;
431   uint8_t int2_on_int1             : 1;
432   uint8_t sleep_g                  : 1;
433   uint8_t not_used_03              : 1;
434 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
435   uint8_t not_used_03              : 1;
436   uint8_t sleep_g                  : 1;
437   uint8_t int2_on_int1             : 1;
438   uint8_t not_used_02              : 1;
439   uint8_t drdy_mask                : 1;
440   uint8_t i2c_disable              : 1;
441   uint8_t lpf1_sel_g               : 1;
442   uint8_t not_used_01              : 1;
443 #endif /* DRV_BYTE_ORDER */
444 } lsm6dsrx_ctrl4_c_t;
445 
446 #define LSM6DSRX_CTRL5_C                      0x14U
447 typedef struct
448 {
449 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
450   uint8_t st_xl                    : 2;
451   uint8_t st_g                     : 2;
452   uint8_t not_used_01              : 1;
453   uint8_t rounding                 : 2;
454   uint8_t not_used_02              : 1;
455 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
456   uint8_t not_used_02              : 1;
457   uint8_t rounding                 : 2;
458   uint8_t not_used_01              : 1;
459   uint8_t st_g                     : 2;
460   uint8_t st_xl                    : 2;
461 #endif /* DRV_BYTE_ORDER */
462 } lsm6dsrx_ctrl5_c_t;
463 
464 #define LSM6DSRX_CTRL6_C                      0x15U
465 typedef struct
466 {
467 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
468   uint8_t ftype                    : 3;
469   uint8_t usr_off_w                : 1;
470   uint8_t xl_hm_mode               : 1;
471 uint8_t den_mode                 :
472   3;   /* trig_en + lvl1_en + lvl2_en */
473 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
474 uint8_t den_mode                 :
475   3;   /* trig_en + lvl1_en + lvl2_en */
476   uint8_t xl_hm_mode               : 1;
477   uint8_t usr_off_w                : 1;
478   uint8_t ftype                    : 3;
479 #endif /* DRV_BYTE_ORDER */
480 } lsm6dsrx_ctrl6_c_t;
481 
482 #define LSM6DSRX_CTRL7_G                      0x16U
483 typedef struct
484 {
485 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
486   uint8_t ois_on                   : 1;
487   uint8_t usr_off_on_out           : 1;
488   uint8_t ois_on_en                : 1;
489   uint8_t not_used_01              : 1;
490   uint8_t hpm_g                    : 2;
491   uint8_t hp_en_g                  : 1;
492   uint8_t g_hm_mode                : 1;
493 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
494   uint8_t g_hm_mode                : 1;
495   uint8_t hp_en_g                  : 1;
496   uint8_t hpm_g                    : 2;
497   uint8_t not_used_01              : 1;
498   uint8_t ois_on_en                : 1;
499   uint8_t usr_off_on_out           : 1;
500   uint8_t ois_on                   : 1;
501 #endif /* DRV_BYTE_ORDER */
502 } lsm6dsrx_ctrl7_g_t;
503 
504 #define LSM6DSRX_CTRL8_XL                     0x17U
505 typedef struct
506 {
507 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
508   uint8_t low_pass_on_6d           : 1;
509   uint8_t not_used_01              : 1;
510   uint8_t hp_slope_xl_en           : 1;
511   uint8_t fastsettl_mode_xl        : 1;
512   uint8_t hp_ref_mode_xl           : 1;
513   uint8_t hpcf_xl                  : 3;
514 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
515   uint8_t hpcf_xl                  : 3;
516   uint8_t hp_ref_mode_xl           : 1;
517   uint8_t fastsettl_mode_xl        : 1;
518   uint8_t hp_slope_xl_en           : 1;
519   uint8_t not_used_01              : 1;
520   uint8_t low_pass_on_6d           : 1;
521 #endif /* DRV_BYTE_ORDER */
522 } lsm6dsrx_ctrl8_xl_t;
523 
524 #define LSM6DSRX_CTRL9_XL                     0x18U
525 typedef struct
526 {
527 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
528   uint8_t not_used_01              : 1;
529   uint8_t i3c_disable              : 1;
530   uint8_t den_lh                   : 1;
531   uint8_t den_xl_g                 : 2;   /* den_xl_en + den_xl_g */
532   uint8_t den_z                    : 1;
533   uint8_t den_y                    : 1;
534   uint8_t den_x                    : 1;
535 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
536   uint8_t den_x                    : 1;
537   uint8_t den_y                    : 1;
538   uint8_t den_z                    : 1;
539   uint8_t den_xl_g                 : 2;   /* den_xl_en + den_xl_g */
540   uint8_t den_lh                   : 1;
541   uint8_t i3c_disable              : 1;
542   uint8_t not_used_01              : 1;
543 #endif /* DRV_BYTE_ORDER */
544 } lsm6dsrx_ctrl9_xl_t;
545 
546 #define LSM6DSRX_CTRL10_C                     0x19U
547 typedef struct
548 {
549 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
550   uint8_t not_used_01              : 5;
551   uint8_t timestamp_en             : 1;
552   uint8_t not_used_02              : 2;
553 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
554   uint8_t not_used_02              : 2;
555   uint8_t timestamp_en             : 1;
556   uint8_t not_used_01              : 5;
557 #endif /* DRV_BYTE_ORDER */
558 } lsm6dsrx_ctrl10_c_t;
559 
560 #define LSM6DSRX_ALL_INT_SRC                  0x1AU
561 typedef struct
562 {
563 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
564   uint8_t ff_ia                    : 1;
565   uint8_t wu_ia                    : 1;
566   uint8_t single_tap               : 1;
567   uint8_t double_tap               : 1;
568   uint8_t d6d_ia                   : 1;
569   uint8_t sleep_change_ia          : 1;
570   uint8_t not_used_01              : 1;
571   uint8_t timestamp_endcount       : 1;
572 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
573   uint8_t timestamp_endcount       : 1;
574   uint8_t not_used_01              : 1;
575   uint8_t sleep_change_ia          : 1;
576   uint8_t d6d_ia                   : 1;
577   uint8_t double_tap               : 1;
578   uint8_t single_tap               : 1;
579   uint8_t wu_ia                    : 1;
580   uint8_t ff_ia                    : 1;
581 #endif /* DRV_BYTE_ORDER */
582 } lsm6dsrx_all_int_src_t;
583 
584 #define LSM6DSRX_WAKE_UP_SRC                  0x1BU
585 typedef struct
586 {
587 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
588   uint8_t z_wu                     : 1;
589   uint8_t y_wu                     : 1;
590   uint8_t x_wu                     : 1;
591   uint8_t wu_ia                    : 1;
592   uint8_t sleep_state              : 1;
593   uint8_t ff_ia                    : 1;
594   uint8_t sleep_change_ia          : 1;
595   uint8_t not_used_01              : 1;
596 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
597   uint8_t not_used_01              : 1;
598   uint8_t sleep_change_ia          : 1;
599   uint8_t ff_ia                    : 1;
600   uint8_t sleep_state              : 1;
601   uint8_t wu_ia                    : 1;
602   uint8_t x_wu                     : 1;
603   uint8_t y_wu                     : 1;
604   uint8_t z_wu                     : 1;
605 #endif /* DRV_BYTE_ORDER */
606 } lsm6dsrx_wake_up_src_t;
607 
608 #define LSM6DSRX_TAP_SRC                      0x1CU
609 typedef struct
610 {
611 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
612   uint8_t z_tap                    : 1;
613   uint8_t y_tap                    : 1;
614   uint8_t x_tap                    : 1;
615   uint8_t tap_sign                 : 1;
616   uint8_t double_tap               : 1;
617   uint8_t single_tap               : 1;
618   uint8_t tap_ia                   : 1;
619   uint8_t not_used_01              : 1;
620 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
621   uint8_t not_used_01              : 1;
622   uint8_t tap_ia                   : 1;
623   uint8_t single_tap               : 1;
624   uint8_t double_tap               : 1;
625   uint8_t tap_sign                 : 1;
626   uint8_t x_tap                    : 1;
627   uint8_t y_tap                    : 1;
628   uint8_t z_tap                    : 1;
629 #endif /* DRV_BYTE_ORDER */
630 } lsm6dsrx_tap_src_t;
631 
632 #define LSM6DSRX_D6D_SRC                      0x1DU
633 typedef struct
634 {
635 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
636   uint8_t xl                       : 1;
637   uint8_t xh                       : 1;
638   uint8_t yl                       : 1;
639   uint8_t yh                       : 1;
640   uint8_t zl                       : 1;
641   uint8_t zh                       : 1;
642   uint8_t d6d_ia                   : 1;
643   uint8_t den_drdy                 : 1;
644 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
645   uint8_t den_drdy                 : 1;
646   uint8_t d6d_ia                   : 1;
647   uint8_t zh                       : 1;
648   uint8_t zl                       : 1;
649   uint8_t yh                       : 1;
650   uint8_t yl                       : 1;
651   uint8_t xh                       : 1;
652   uint8_t xl                       : 1;
653 #endif /* DRV_BYTE_ORDER */
654 } lsm6dsrx_d6d_src_t;
655 
656 #define LSM6DSRX_STATUS_REG                   0x1EU
657 typedef struct
658 {
659 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
660   uint8_t xlda                     : 1;
661   uint8_t gda                      : 1;
662   uint8_t tda                      : 1;
663   uint8_t not_used_01              : 5;
664 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
665   uint8_t not_used_01              : 5;
666   uint8_t tda                      : 1;
667   uint8_t gda                      : 1;
668   uint8_t xlda                     : 1;
669 #endif /* DRV_BYTE_ORDER */
670 } lsm6dsrx_status_reg_t;
671 
672 #define LSM6DSRX_STATUS_SPIAUX                0x1EU
673 typedef struct
674 {
675 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
676   uint8_t xlda                     : 1;
677   uint8_t gda                      : 1;
678   uint8_t gyro_settling            : 1;
679   uint8_t not_used_01              : 5;
680 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
681   uint8_t not_used_01              : 5;
682   uint8_t gyro_settling            : 1;
683   uint8_t gda                      : 1;
684   uint8_t xlda                     : 1;
685 #endif /* DRV_BYTE_ORDER */
686 } lsm6dsrx_status_spiaux_t;
687 
688 #define LSM6DSRX_OUT_TEMP_L                   0x20U
689 #define LSM6DSRX_OUT_TEMP_H                   0x21U
690 #define LSM6DSRX_OUTX_L_G                     0x22U
691 #define LSM6DSRX_OUTX_H_G                     0x23U
692 #define LSM6DSRX_OUTY_L_G                     0x24U
693 #define LSM6DSRX_OUTY_H_G                     0x25U
694 #define LSM6DSRX_OUTZ_L_G                     0x26U
695 #define LSM6DSRX_OUTZ_H_G                     0x27U
696 #define LSM6DSRX_OUTX_L_A                     0x28U
697 #define LSM6DSRX_OUTX_H_A                     0x29U
698 #define LSM6DSRX_OUTY_L_A                     0x2AU
699 #define LSM6DSRX_OUTY_H_A                     0x2BU
700 #define LSM6DSRX_OUTZ_L_A                     0x2CU
701 #define LSM6DSRX_OUTZ_H_A                     0x2DU
702 #define LSM6DSRX_EMB_FUNC_STATUS_MAINPAGE     0x35U
703 typedef struct
704 {
705 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
706   uint8_t not_used_01             : 3;
707   uint8_t is_step_det             : 1;
708   uint8_t is_tilt                 : 1;
709   uint8_t is_sigmot               : 1;
710   uint8_t not_used_02             : 1;
711   uint8_t is_fsm_lc               : 1;
712 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
713   uint8_t is_fsm_lc               : 1;
714   uint8_t not_used_02             : 1;
715   uint8_t is_sigmot               : 1;
716   uint8_t is_tilt                 : 1;
717   uint8_t is_step_det             : 1;
718   uint8_t not_used_01             : 3;
719 #endif /* DRV_BYTE_ORDER */
720 } lsm6dsrx_emb_func_status_mainpage_t;
721 
722 #define LSM6DSRX_FSM_STATUS_A_MAINPAGE        0x36U
723 typedef struct
724 {
725 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
726   uint8_t is_fsm1                 : 1;
727   uint8_t is_fsm2                 : 1;
728   uint8_t is_fsm3                 : 1;
729   uint8_t is_fsm4                 : 1;
730   uint8_t is_fsm5                 : 1;
731   uint8_t is_fsm6                 : 1;
732   uint8_t is_fsm7                 : 1;
733   uint8_t is_fsm8                 : 1;
734 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
735   uint8_t is_fsm8                 : 1;
736   uint8_t is_fsm7                 : 1;
737   uint8_t is_fsm6                 : 1;
738   uint8_t is_fsm5                 : 1;
739   uint8_t is_fsm4                 : 1;
740   uint8_t is_fsm3                 : 1;
741   uint8_t is_fsm2                 : 1;
742   uint8_t is_fsm1                 : 1;
743 #endif /* DRV_BYTE_ORDER */
744 } lsm6dsrx_fsm_status_a_mainpage_t;
745 
746 #define LSM6DSRX_FSM_STATUS_B_MAINPAGE        0x37U
747 typedef struct
748 {
749 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
750   uint8_t is_fsm9                 : 1;
751   uint8_t is_fsm10                : 1;
752   uint8_t is_fsm11                : 1;
753   uint8_t is_fsm12                : 1;
754   uint8_t is_fsm13                : 1;
755   uint8_t is_fsm14                : 1;
756   uint8_t is_fsm15                : 1;
757   uint8_t is_fsm16                : 1;
758 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
759   uint8_t is_fsm16                : 1;
760   uint8_t is_fsm15                : 1;
761   uint8_t is_fsm14                : 1;
762   uint8_t is_fsm13                : 1;
763   uint8_t is_fsm12                : 1;
764   uint8_t is_fsm11                : 1;
765   uint8_t is_fsm10                : 1;
766   uint8_t is_fsm9                 : 1;
767 #endif /* DRV_BYTE_ORDER */
768 } lsm6dsrx_fsm_status_b_mainpage_t;
769 
770 #define LSM6DSRX_MLC_STATUS_MAINPAGE          0x38U
771 typedef struct
772 {
773 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
774   uint8_t is_mlc1                 : 1;
775   uint8_t is_mlc2                 : 1;
776   uint8_t is_mlc3                 : 1;
777   uint8_t is_mlc4                 : 1;
778   uint8_t is_mlc5                 : 1;
779   uint8_t is_mlc6                 : 1;
780   uint8_t is_mlc7                 : 1;
781   uint8_t is_mlc8                 : 1;
782 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
783   uint8_t is_mlc8                 : 1;
784   uint8_t is_mlc7                 : 1;
785   uint8_t is_mlc6                 : 1;
786   uint8_t is_mlc5                 : 1;
787   uint8_t is_mlc4                 : 1;
788   uint8_t is_mlc3                 : 1;
789   uint8_t is_mlc2                 : 1;
790   uint8_t is_mlc1                 : 1;
791 #endif /* DRV_BYTE_ORDER */
792 } lsm6dsrx_mlc_status_mainpage_t;
793 
794 #define LSM6DSRX_STATUS_MASTER_MAINPAGE       0x39U
795 typedef struct
796 {
797 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
798   uint8_t sens_hub_endop          : 1;
799   uint8_t not_used_01             : 2;
800   uint8_t slave0_nack             : 1;
801   uint8_t slave1_nack             : 1;
802   uint8_t slave2_nack             : 1;
803   uint8_t slave3_nack             : 1;
804   uint8_t wr_once_done            : 1;
805 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
806   uint8_t wr_once_done            : 1;
807   uint8_t slave3_nack             : 1;
808   uint8_t slave2_nack             : 1;
809   uint8_t slave1_nack             : 1;
810   uint8_t slave0_nack             : 1;
811   uint8_t not_used_01             : 2;
812   uint8_t sens_hub_endop          : 1;
813 #endif /* DRV_BYTE_ORDER */
814 } lsm6dsrx_status_master_mainpage_t;
815 
816 #define LSM6DSRX_FIFO_STATUS1                 0x3AU
817 typedef struct
818 {
819   uint8_t diff_fifo                : 8;
820 } lsm6dsrx_fifo_status1_t;
821 
822 #define LSM6DSRX_FIFO_STATUS2                 0x3BU
823 typedef struct
824 {
825 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
826   uint8_t diff_fifo                : 2;
827   uint8_t not_used_01              : 1;
828   uint8_t over_run_latched         : 1;
829   uint8_t counter_bdr_ia           : 1;
830   uint8_t fifo_full_ia             : 1;
831   uint8_t fifo_ovr_ia              : 1;
832   uint8_t fifo_wtm_ia              : 1;
833 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
834   uint8_t fifo_wtm_ia              : 1;
835   uint8_t fifo_ovr_ia              : 1;
836   uint8_t fifo_full_ia             : 1;
837   uint8_t counter_bdr_ia           : 1;
838   uint8_t over_run_latched         : 1;
839   uint8_t not_used_01              : 1;
840   uint8_t diff_fifo                : 2;
841 #endif /* DRV_BYTE_ORDER */
842 } lsm6dsrx_fifo_status2_t;
843 
844 #define LSM6DSRX_TIMESTAMP0                   0x40U
845 #define LSM6DSRX_TIMESTAMP1                   0x41U
846 #define LSM6DSRX_TIMESTAMP2                   0x42U
847 #define LSM6DSRX_TIMESTAMP3                   0x43U
848 #define LSM6DSRX_TAP_CFG0                     0x56U
849 typedef struct
850 {
851 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
852   uint8_t lir                      : 1;
853   uint8_t tap_z_en                 : 1;
854   uint8_t tap_y_en                 : 1;
855   uint8_t tap_x_en                 : 1;
856   uint8_t slope_fds                : 1;
857   uint8_t sleep_status_on_int      : 1;
858   uint8_t int_clr_on_read          : 1;
859   uint8_t not_used_01              : 1;
860 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
861   uint8_t not_used_01              : 1;
862   uint8_t int_clr_on_read          : 1;
863   uint8_t sleep_status_on_int      : 1;
864   uint8_t slope_fds                : 1;
865   uint8_t tap_x_en                 : 1;
866   uint8_t tap_y_en                 : 1;
867   uint8_t tap_z_en                 : 1;
868   uint8_t lir                      : 1;
869 #endif /* DRV_BYTE_ORDER */
870 } lsm6dsrx_tap_cfg0_t;
871 
872 #define LSM6DSRX_TAP_CFG1                     0x57U
873 typedef struct
874 {
875 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
876   uint8_t tap_ths_x                : 5;
877   uint8_t tap_priority             : 3;
878 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
879   uint8_t tap_priority             : 3;
880   uint8_t tap_ths_x                : 5;
881 #endif /* DRV_BYTE_ORDER */
882 } lsm6dsrx_tap_cfg1_t;
883 
884 #define LSM6DSRX_TAP_CFG2                     0x58U
885 typedef struct
886 {
887 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
888   uint8_t tap_ths_y                : 5;
889   uint8_t inact_en                 : 2;
890   uint8_t interrupts_enable        : 1;
891 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
892   uint8_t interrupts_enable        : 1;
893   uint8_t inact_en                 : 2;
894   uint8_t tap_ths_y                : 5;
895 #endif /* DRV_BYTE_ORDER */
896 } lsm6dsrx_tap_cfg2_t;
897 
898 #define LSM6DSRX_TAP_THS_6D                   0x59U
899 typedef struct
900 {
901 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
902   uint8_t tap_ths_z                : 5;
903   uint8_t sixd_ths                 : 2;
904   uint8_t d4d_en                   : 1;
905 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
906   uint8_t d4d_en                   : 1;
907   uint8_t sixd_ths                 : 2;
908   uint8_t tap_ths_z                : 5;
909 #endif /* DRV_BYTE_ORDER */
910 } lsm6dsrx_tap_ths_6d_t;
911 
912 #define LSM6DSRX_INT_DUR2                     0x5AU
913 typedef struct
914 {
915 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
916   uint8_t shock                    : 2;
917   uint8_t quiet                    : 2;
918   uint8_t dur                      : 4;
919 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
920   uint8_t dur                      : 4;
921   uint8_t quiet                    : 2;
922   uint8_t shock                    : 2;
923 #endif /* DRV_BYTE_ORDER */
924 } lsm6dsrx_int_dur2_t;
925 
926 #define LSM6DSRX_WAKE_UP_THS                  0x5BU
927 typedef struct
928 {
929 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
930   uint8_t wk_ths                   : 6;
931   uint8_t usr_off_on_wu            : 1;
932   uint8_t single_double_tap        : 1;
933 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
934   uint8_t single_double_tap        : 1;
935   uint8_t usr_off_on_wu            : 1;
936   uint8_t wk_ths                   : 6;
937 #endif /* DRV_BYTE_ORDER */
938 } lsm6dsrx_wake_up_ths_t;
939 
940 #define LSM6DSRX_WAKE_UP_DUR                  0x5CU
941 typedef struct
942 {
943 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
944   uint8_t sleep_dur                : 4;
945   uint8_t wake_ths_w               : 1;
946   uint8_t wake_dur                 : 2;
947   uint8_t ff_dur                   : 1;
948 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
949   uint8_t ff_dur                   : 1;
950   uint8_t wake_dur                 : 2;
951   uint8_t wake_ths_w               : 1;
952   uint8_t sleep_dur                : 4;
953 #endif /* DRV_BYTE_ORDER */
954 } lsm6dsrx_wake_up_dur_t;
955 
956 #define LSM6DSRX_FREE_FALL                    0x5DU
957 typedef struct
958 {
959 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
960   uint8_t ff_ths                   : 3;
961   uint8_t ff_dur                   : 5;
962 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
963   uint8_t ff_dur                   : 5;
964   uint8_t ff_ths                   : 3;
965 #endif /* DRV_BYTE_ORDER */
966 } lsm6dsrx_free_fall_t;
967 
968 #define LSM6DSRX_MD1_CFG                      0x5EU
969 typedef struct
970 {
971 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
972   uint8_t int1_shub                : 1;
973   uint8_t int1_emb_func            : 1;
974   uint8_t int1_6d                  : 1;
975   uint8_t int1_double_tap          : 1;
976   uint8_t int1_ff                  : 1;
977   uint8_t int1_wu                  : 1;
978   uint8_t int1_single_tap          : 1;
979   uint8_t int1_sleep_change        : 1;
980 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
981   uint8_t int1_sleep_change        : 1;
982   uint8_t int1_single_tap          : 1;
983   uint8_t int1_wu                  : 1;
984   uint8_t int1_ff                  : 1;
985   uint8_t int1_double_tap          : 1;
986   uint8_t int1_6d                  : 1;
987   uint8_t int1_emb_func            : 1;
988   uint8_t int1_shub                : 1;
989 #endif /* DRV_BYTE_ORDER */
990 } lsm6dsrx_md1_cfg_t;
991 
992 #define LSM6DSRX_MD2_CFG                      0x5FU
993 typedef struct
994 {
995 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
996   uint8_t int2_timestamp           : 1;
997   uint8_t int2_emb_func            : 1;
998   uint8_t int2_6d                  : 1;
999   uint8_t int2_double_tap          : 1;
1000   uint8_t int2_ff                  : 1;
1001   uint8_t int2_wu                  : 1;
1002   uint8_t int2_single_tap          : 1;
1003   uint8_t int2_sleep_change        : 1;
1004 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1005   uint8_t int2_sleep_change        : 1;
1006   uint8_t int2_single_tap          : 1;
1007   uint8_t int2_wu                  : 1;
1008   uint8_t int2_ff                  : 1;
1009   uint8_t int2_double_tap          : 1;
1010   uint8_t int2_6d                  : 1;
1011   uint8_t int2_emb_func            : 1;
1012   uint8_t int2_timestamp           : 1;
1013 #endif /* DRV_BYTE_ORDER */
1014 } lsm6dsrx_md2_cfg_t;
1015 
1016 #define LSM6DSRX_S4S_ST_CMD_CODE              0x60U
1017 typedef struct
1018 {
1019   uint8_t s4s_st_cmd_code          : 8;
1020 } lsm6dsrx_s4s_st_cmd_code_t;
1021 
1022 #define LSM6DSRX_S4S_DT_REG                   0x61U
1023 typedef struct
1024 {
1025   uint8_t dt                       : 8;
1026 } lsm6dsrx_s4s_dt_reg_t;
1027 
1028 #define LSM6DSRX_I3C_BUS_AVB                  0x62U
1029 typedef struct
1030 {
1031 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1032   uint8_t pd_dis_int1              : 1;
1033   uint8_t not_used_01              : 2;
1034   uint8_t i3c_bus_avb_sel          : 2;
1035   uint8_t not_used_02              : 3;
1036 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1037   uint8_t not_used_02              : 3;
1038   uint8_t i3c_bus_avb_sel          : 2;
1039   uint8_t not_used_01              : 2;
1040   uint8_t pd_dis_int1              : 1;
1041 #endif /* DRV_BYTE_ORDER */
1042 } lsm6dsrx_i3c_bus_avb_t;
1043 
1044 #define LSM6DSRX_INTERNAL_FREQ_FINE           0x63U
1045 typedef struct
1046 {
1047   uint8_t freq_fine                : 8;
1048 } lsm6dsrx_internal_freq_fine_t;
1049 
1050 #define LSM6DSRX_INT_OIS                      0x6FU
1051 typedef struct
1052 {
1053 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1054   uint8_t st_xl_ois                : 2;
1055   uint8_t not_used_01              : 3;
1056   uint8_t den_lh_ois               : 1;
1057   uint8_t lvl2_ois                 : 1;
1058   uint8_t int2_drdy_ois            : 1;
1059 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1060   uint8_t int2_drdy_ois            : 1;
1061   uint8_t lvl2_ois                 : 1;
1062   uint8_t den_lh_ois               : 1;
1063   uint8_t not_used_01              : 3;
1064   uint8_t st_xl_ois                : 2;
1065 #endif /* DRV_BYTE_ORDER */
1066 } lsm6dsrx_int_ois_t;
1067 
1068 #define LSM6DSRX_CTRL1_OIS                    0x70U
1069 typedef struct
1070 {
1071 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1072   uint8_t ois_en_spi2              : 1;
1073   uint8_t fs_125_ois               : 1;
1074   uint8_t fs_g_ois                 : 2;
1075   uint8_t mode4_en                 : 1;
1076   uint8_t sim_ois                  : 1;
1077   uint8_t lvl1_ois                 : 1;
1078   uint8_t not_used_01              : 1;
1079 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1080   uint8_t not_used_01              : 1;
1081   uint8_t lvl1_ois                 : 1;
1082   uint8_t sim_ois                  : 1;
1083   uint8_t mode4_en                 : 1;
1084   uint8_t fs_g_ois                 : 2;
1085   uint8_t fs_125_ois               : 1;
1086   uint8_t ois_en_spi2              : 1;
1087 #endif /* DRV_BYTE_ORDER */
1088 } lsm6dsrx_ctrl1_ois_t;
1089 
1090 #define LSM6DSRX_CTRL2_OIS                    0x71U
1091 typedef struct
1092 {
1093 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1094   uint8_t hp_en_ois                : 1;
1095   uint8_t ftype_ois                : 2;
1096   uint8_t not_used_01              : 1;
1097   uint8_t hpm_ois                  : 2;
1098   uint8_t not_used_02              : 2;
1099 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1100   uint8_t not_used_02              : 2;
1101   uint8_t hpm_ois                  : 2;
1102   uint8_t not_used_01              : 1;
1103   uint8_t ftype_ois                : 2;
1104   uint8_t hp_en_ois                : 1;
1105 #endif /* DRV_BYTE_ORDER */
1106 } lsm6dsrx_ctrl2_ois_t;
1107 
1108 #define LSM6DSRX_CTRL3_OIS                    0x72U
1109 typedef struct
1110 {
1111 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1112   uint8_t st_ois_clampdis          : 1;
1113   uint8_t st_ois                   : 2;
1114   uint8_t filter_xl_conf_ois       : 3;
1115   uint8_t fs_xl_ois                : 2;
1116 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1117   uint8_t fs_xl_ois                : 2;
1118   uint8_t filter_xl_conf_ois       : 3;
1119   uint8_t st_ois                   : 2;
1120   uint8_t st_ois_clampdis          : 1;
1121 #endif /* DRV_BYTE_ORDER */
1122 } lsm6dsrx_ctrl3_ois_t;
1123 
1124 #define LSM6DSRX_X_OFS_USR                    0x73U
1125 #define LSM6DSRX_Y_OFS_USR                    0x74U
1126 #define LSM6DSRX_Z_OFS_USR                    0x75U
1127 #define LSM6DSRX_FIFO_DATA_OUT_TAG            0x78U
1128 typedef struct
1129 {
1130 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1131   uint8_t tag_parity               : 1;
1132   uint8_t tag_cnt                  : 2;
1133   uint8_t tag_sensor               : 5;
1134 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1135   uint8_t tag_sensor               : 5;
1136   uint8_t tag_cnt                  : 2;
1137   uint8_t tag_parity               : 1;
1138 #endif /* DRV_BYTE_ORDER */
1139 } lsm6dsrx_fifo_data_out_tag_t;
1140 
1141 #define LSM6DSRX_FIFO_DATA_OUT_X_L            0x79U
1142 #define LSM6DSRX_FIFO_DATA_OUT_X_H            0x7AU
1143 #define LSM6DSRX_FIFO_DATA_OUT_Y_L            0x7BU
1144 #define LSM6DSRX_FIFO_DATA_OUT_Y_H            0x7CU
1145 #define LSM6DSRX_FIFO_DATA_OUT_Z_L            0x7DU
1146 #define LSM6DSRX_FIFO_DATA_OUT_Z_H            0x7EU
1147 #define LSM6DSRX_PAGE_SEL                     0x02U
1148 typedef struct
1149 {
1150 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1151   uint8_t not_used_01              : 4;
1152   uint8_t page_sel                 : 4;
1153 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1154   uint8_t page_sel                 : 4;
1155   uint8_t not_used_01              : 4;
1156 #endif /* DRV_BYTE_ORDER */
1157 } lsm6dsrx_page_sel_t;
1158 
1159 #define LSM6DSRX_EMB_FUNC_EN_A                0x04U
1160 typedef struct
1161 {
1162 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1163   uint8_t not_used_01              : 3;
1164   uint8_t pedo_en                  : 1;
1165   uint8_t tilt_en                  : 1;
1166   uint8_t sign_motion_en           : 1;
1167   uint8_t not_used_02              : 2;
1168 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1169   uint8_t not_used_02              : 2;
1170   uint8_t sign_motion_en           : 1;
1171   uint8_t tilt_en                  : 1;
1172   uint8_t pedo_en                  : 1;
1173   uint8_t not_used_01              : 3;
1174 #endif /* DRV_BYTE_ORDER */
1175 } lsm6dsrx_emb_func_en_a_t;
1176 
1177 #define LSM6DSRX_EMB_FUNC_EN_B                0x05U
1178 typedef struct
1179 {
1180 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1181   uint8_t fsm_en                   : 1;
1182   uint8_t not_used_01              : 2;
1183   uint8_t fifo_compr_en            : 1;
1184   uint8_t mlc_en                   : 1;
1185   uint8_t not_used_02              : 3;
1186 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1187   uint8_t not_used_02              : 3;
1188   uint8_t mlc_en                   : 1;
1189   uint8_t fifo_compr_en            : 1;
1190   uint8_t not_used_01              : 2;
1191   uint8_t fsm_en                   : 1;
1192 #endif /* DRV_BYTE_ORDER */
1193 } lsm6dsrx_emb_func_en_b_t;
1194 
1195 #define LSM6DSRX_PAGE_ADDRESS                 0x08U
1196 typedef struct
1197 {
1198   uint8_t page_addr                : 8;
1199 } lsm6dsrx_page_address_t;
1200 
1201 #define LSM6DSRX_PAGE_VALUE                   0x09U
1202 typedef struct
1203 {
1204   uint8_t page_value               : 8;
1205 } lsm6dsrx_page_value_t;
1206 
1207 #define LSM6DSRX_EMB_FUNC_INT1                0x0AU
1208 typedef struct
1209 {
1210 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1211   uint8_t not_used_01              : 3;
1212   uint8_t int1_step_detector       : 1;
1213   uint8_t int1_tilt                : 1;
1214   uint8_t int1_sig_mot             : 1;
1215   uint8_t not_used_02              : 1;
1216   uint8_t int1_fsm_lc              : 1;
1217 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1218   uint8_t int1_fsm_lc              : 1;
1219   uint8_t not_used_02              : 1;
1220   uint8_t int1_sig_mot             : 1;
1221   uint8_t int1_tilt                : 1;
1222   uint8_t int1_step_detector       : 1;
1223   uint8_t not_used_01              : 3;
1224 #endif /* DRV_BYTE_ORDER */
1225 } lsm6dsrx_emb_func_int1_t;
1226 
1227 #define LSM6DSRX_FSM_INT1_A                   0x0BU
1228 typedef struct
1229 {
1230 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1231   uint8_t int1_fsm1                : 1;
1232   uint8_t int1_fsm2                : 1;
1233   uint8_t int1_fsm3                : 1;
1234   uint8_t int1_fsm4                : 1;
1235   uint8_t int1_fsm5                : 1;
1236   uint8_t int1_fsm6                : 1;
1237   uint8_t int1_fsm7                : 1;
1238   uint8_t int1_fsm8                : 1;
1239 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1240   uint8_t int1_fsm8                : 1;
1241   uint8_t int1_fsm7                : 1;
1242   uint8_t int1_fsm6                : 1;
1243   uint8_t int1_fsm5                : 1;
1244   uint8_t int1_fsm4                : 1;
1245   uint8_t int1_fsm3                : 1;
1246   uint8_t int1_fsm2                : 1;
1247   uint8_t int1_fsm1                : 1;
1248 #endif /* DRV_BYTE_ORDER */
1249 } lsm6dsrx_fsm_int1_a_t;
1250 
1251 #define LSM6DSRX_FSM_INT1_B                   0x0CU
1252 typedef struct
1253 {
1254 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1255   uint8_t int1_fsm9                : 1;
1256   uint8_t int1_fsm10               : 1;
1257   uint8_t int1_fsm11               : 1;
1258   uint8_t int1_fsm12               : 1;
1259   uint8_t int1_fsm13               : 1;
1260   uint8_t int1_fsm14               : 1;
1261   uint8_t int1_fsm15               : 1;
1262   uint8_t int1_fsm16               : 1;
1263 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1264   uint8_t int1_fsm16               : 1;
1265   uint8_t int1_fsm15               : 1;
1266   uint8_t int1_fsm14               : 1;
1267   uint8_t int1_fsm13               : 1;
1268   uint8_t int1_fsm12               : 1;
1269   uint8_t int1_fsm11               : 1;
1270   uint8_t int1_fsm10               : 1;
1271   uint8_t int1_fsm9                : 1;
1272 #endif /* DRV_BYTE_ORDER */
1273 } lsm6dsrx_fsm_int1_b_t;
1274 
1275 #define LSM6DSRX_MLC_INT1                     0x0DU
1276 typedef struct
1277 {
1278 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1279   uint8_t int1_mlc1                : 1;
1280   uint8_t int1_mlc2                : 1;
1281   uint8_t int1_mlc3                : 1;
1282   uint8_t int1_mlc4                : 1;
1283   uint8_t int1_mlc5                : 1;
1284   uint8_t int1_mlc6                : 1;
1285   uint8_t int1_mlc7                : 1;
1286   uint8_t int1_mlc8                : 1;
1287 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1288   uint8_t int1_mlc8                : 1;
1289   uint8_t int1_mlc7                : 1;
1290   uint8_t int1_mlc6                : 1;
1291   uint8_t int1_mlc5                : 1;
1292   uint8_t int1_mlc4                : 1;
1293   uint8_t int1_mlc3                : 1;
1294   uint8_t int1_mlc2                : 1;
1295   uint8_t int1_mlc1                : 1;
1296 #endif /* DRV_BYTE_ORDER */
1297 } lsm6dsrx_mlc_int1_t;
1298 
1299 #define LSM6DSRX_EMB_FUNC_INT2                0x0EU
1300 typedef struct
1301 {
1302 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1303   uint8_t not_used_01              : 3;
1304   uint8_t int2_step_detector       : 1;
1305   uint8_t int2_tilt                : 1;
1306   uint8_t int2_sig_mot             : 1;
1307   uint8_t not_used_02              : 1;
1308   uint8_t int2_fsm_lc              : 1;
1309 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1310   uint8_t int2_fsm_lc              : 1;
1311   uint8_t not_used_02              : 1;
1312   uint8_t int2_sig_mot             : 1;
1313   uint8_t int2_tilt                : 1;
1314   uint8_t int2_step_detector       : 1;
1315   uint8_t not_used_01              : 3;
1316 #endif /* DRV_BYTE_ORDER */
1317 } lsm6dsrx_emb_func_int2_t;
1318 
1319 #define LSM6DSRX_FSM_INT2_A                   0x0FU
1320 typedef struct
1321 {
1322 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1323   uint8_t int2_fsm1                : 1;
1324   uint8_t int2_fsm2                : 1;
1325   uint8_t int2_fsm3                : 1;
1326   uint8_t int2_fsm4                : 1;
1327   uint8_t int2_fsm5                : 1;
1328   uint8_t int2_fsm6                : 1;
1329   uint8_t int2_fsm7                : 1;
1330   uint8_t int2_fsm8                : 1;
1331 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1332   uint8_t int2_fsm8                : 1;
1333   uint8_t int2_fsm7                : 1;
1334   uint8_t int2_fsm6                : 1;
1335   uint8_t int2_fsm5                : 1;
1336   uint8_t int2_fsm4                : 1;
1337   uint8_t int2_fsm3                : 1;
1338   uint8_t int2_fsm2                : 1;
1339   uint8_t int2_fsm1                : 1;
1340 #endif /* DRV_BYTE_ORDER */
1341 } lsm6dsrx_fsm_int2_a_t;
1342 
1343 #define LSM6DSRX_FSM_INT2_B                   0x10U
1344 typedef struct
1345 {
1346 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1347   uint8_t int2_fsm9                : 1;
1348   uint8_t int2_fsm10               : 1;
1349   uint8_t int2_fsm11               : 1;
1350   uint8_t int2_fsm12               : 1;
1351   uint8_t int2_fsm13               : 1;
1352   uint8_t int2_fsm14               : 1;
1353   uint8_t int2_fsm15               : 1;
1354   uint8_t int2_fsm16               : 1;
1355 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1356   uint8_t int2_fsm16               : 1;
1357   uint8_t int2_fsm15               : 1;
1358   uint8_t int2_fsm14               : 1;
1359   uint8_t int2_fsm13               : 1;
1360   uint8_t int2_fsm12               : 1;
1361   uint8_t int2_fsm11               : 1;
1362   uint8_t int2_fsm10               : 1;
1363   uint8_t int2_fsm9                : 1;
1364 #endif /* DRV_BYTE_ORDER */
1365 } lsm6dsrx_fsm_int2_b_t;
1366 
1367 #define LSM6DSRX_MLC_INT2                     0x11U
1368 typedef struct
1369 {
1370 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1371   uint8_t int2_mlc1             : 1;
1372   uint8_t int2_mlc2             : 1;
1373   uint8_t int2_mlc3             : 1;
1374   uint8_t int2_mlc4             : 1;
1375   uint8_t int2_mlc5             : 1;
1376   uint8_t int2_mlc6             : 1;
1377   uint8_t int2_mlc7             : 1;
1378   uint8_t int2_mlc8             : 1;
1379 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1380   uint8_t int2_mlc8             : 1;
1381   uint8_t int2_mlc7             : 1;
1382   uint8_t int2_mlc6             : 1;
1383   uint8_t int2_mlc5             : 1;
1384   uint8_t int2_mlc4             : 1;
1385   uint8_t int2_mlc3             : 1;
1386   uint8_t int2_mlc2             : 1;
1387   uint8_t int2_mlc1             : 1;
1388 #endif /* DRV_BYTE_ORDER */
1389 } lsm6dsrx_mlc_int2_t;
1390 
1391 #define LSM6DSRX_EMB_FUNC_STATUS              0x12U
1392 typedef struct
1393 {
1394 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1395   uint8_t not_used_01              : 3;
1396   uint8_t is_step_det              : 1;
1397   uint8_t is_tilt                  : 1;
1398   uint8_t is_sigmot                : 1;
1399   uint8_t not_used_02              : 1;
1400   uint8_t is_fsm_lc                : 1;
1401 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1402   uint8_t is_fsm_lc                : 1;
1403   uint8_t not_used_02              : 1;
1404   uint8_t is_sigmot                : 1;
1405   uint8_t is_tilt                  : 1;
1406   uint8_t is_step_det              : 1;
1407   uint8_t not_used_01              : 3;
1408 #endif /* DRV_BYTE_ORDER */
1409 } lsm6dsrx_emb_func_status_t;
1410 
1411 #define LSM6DSRX_FSM_STATUS_A                 0x13U
1412 typedef struct
1413 {
1414 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1415   uint8_t is_fsm1                  : 1;
1416   uint8_t is_fsm2                  : 1;
1417   uint8_t is_fsm3                  : 1;
1418   uint8_t is_fsm4                  : 1;
1419   uint8_t is_fsm5                  : 1;
1420   uint8_t is_fsm6                  : 1;
1421   uint8_t is_fsm7                  : 1;
1422   uint8_t is_fsm8                  : 1;
1423 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1424   uint8_t is_fsm8                  : 1;
1425   uint8_t is_fsm7                  : 1;
1426   uint8_t is_fsm6                  : 1;
1427   uint8_t is_fsm5                  : 1;
1428   uint8_t is_fsm4                  : 1;
1429   uint8_t is_fsm3                  : 1;
1430   uint8_t is_fsm2                  : 1;
1431   uint8_t is_fsm1                  : 1;
1432 #endif /* DRV_BYTE_ORDER */
1433 } lsm6dsrx_fsm_status_a_t;
1434 
1435 #define LSM6DSRX_FSM_STATUS_B                 0x14U
1436 typedef struct
1437 {
1438 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1439   uint8_t is_fsm9                  : 1;
1440   uint8_t is_fsm10                 : 1;
1441   uint8_t is_fsm11                 : 1;
1442   uint8_t is_fsm12                 : 1;
1443   uint8_t is_fsm13                 : 1;
1444   uint8_t is_fsm14                 : 1;
1445   uint8_t is_fsm15                 : 1;
1446   uint8_t is_fsm16                 : 1;
1447 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1448   uint8_t is_fsm16                 : 1;
1449   uint8_t is_fsm15                 : 1;
1450   uint8_t is_fsm14                 : 1;
1451   uint8_t is_fsm13                 : 1;
1452   uint8_t is_fsm12                 : 1;
1453   uint8_t is_fsm11                 : 1;
1454   uint8_t is_fsm10                 : 1;
1455   uint8_t is_fsm9                  : 1;
1456 #endif /* DRV_BYTE_ORDER */
1457 } lsm6dsrx_fsm_status_b_t;
1458 
1459 #define LSM6DSRX_MLC_STATUS                   0x15U
1460 typedef struct
1461 {
1462 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1463   uint8_t is_mlc1            : 1;
1464   uint8_t is_mlc2            : 1;
1465   uint8_t is_mlc3            : 1;
1466   uint8_t is_mlc4            : 1;
1467   uint8_t is_mlc5            : 1;
1468   uint8_t is_mlc6            : 1;
1469   uint8_t is_mlc7            : 1;
1470   uint8_t is_mlc8            : 1;
1471 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1472   uint8_t is_mlc8            : 1;
1473   uint8_t is_mlc7            : 1;
1474   uint8_t is_mlc6            : 1;
1475   uint8_t is_mlc5            : 1;
1476   uint8_t is_mlc4            : 1;
1477   uint8_t is_mlc3            : 1;
1478   uint8_t is_mlc2            : 1;
1479   uint8_t is_mlc1            : 1;
1480 #endif /* DRV_BYTE_ORDER */
1481 } lsm6dsrx_mlc_status_t;
1482 
1483 #define LSM6DSRX_PAGE_RW                      0x17U
1484 typedef struct
1485 {
1486 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1487   uint8_t not_used_01              : 5;
1488   uint8_t page_rw                  : 2;  /* page_write + page_read */
1489   uint8_t emb_func_lir             : 1;
1490 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1491   uint8_t emb_func_lir             : 1;
1492   uint8_t page_rw                  : 2;  /* page_write + page_read */
1493   uint8_t not_used_01              : 5;
1494 #endif /* DRV_BYTE_ORDER */
1495 } lsm6dsrx_page_rw_t;
1496 
1497 #define LSM6DSRX_EMB_FUNC_FIFO_CFG            0x44U
1498 typedef struct
1499 {
1500 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1501   uint8_t not_used_01              : 6;
1502   uint8_t pedo_fifo_en             : 1;
1503   uint8_t not_used_02              : 1;
1504 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1505   uint8_t not_used_02              : 1;
1506   uint8_t pedo_fifo_en             : 1;
1507   uint8_t not_used_01              : 6;
1508 #endif /* DRV_BYTE_ORDER */
1509 } lsm6dsrx_emb_func_fifo_cfg_t;
1510 
1511 #define LSM6DSRX_FSM_ENABLE_A                 0x46U
1512 typedef struct
1513 {
1514 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1515   uint8_t fsm1_en                  : 1;
1516   uint8_t fsm2_en                  : 1;
1517   uint8_t fsm3_en                  : 1;
1518   uint8_t fsm4_en                  : 1;
1519   uint8_t fsm5_en                  : 1;
1520   uint8_t fsm6_en                  : 1;
1521   uint8_t fsm7_en                  : 1;
1522   uint8_t fsm8_en                  : 1;
1523 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1524   uint8_t fsm8_en                  : 1;
1525   uint8_t fsm7_en                  : 1;
1526   uint8_t fsm6_en                  : 1;
1527   uint8_t fsm5_en                  : 1;
1528   uint8_t fsm4_en                  : 1;
1529   uint8_t fsm3_en                  : 1;
1530   uint8_t fsm2_en                  : 1;
1531   uint8_t fsm1_en                  : 1;
1532 #endif /* DRV_BYTE_ORDER */
1533 } lsm6dsrx_fsm_enable_a_t;
1534 
1535 #define LSM6DSRX_FSM_ENABLE_B                 0x47U
1536 typedef struct
1537 {
1538 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1539   uint8_t fsm9_en                  : 1;
1540   uint8_t fsm10_en                 : 1;
1541   uint8_t fsm11_en                 : 1;
1542   uint8_t fsm12_en                 : 1;
1543   uint8_t fsm13_en                 : 1;
1544   uint8_t fsm14_en                 : 1;
1545   uint8_t fsm15_en                 : 1;
1546   uint8_t fsm16_en                 : 1;
1547 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1548   uint8_t fsm16_en                 : 1;
1549   uint8_t fsm15_en                 : 1;
1550   uint8_t fsm14_en                 : 1;
1551   uint8_t fsm13_en                 : 1;
1552   uint8_t fsm12_en                 : 1;
1553   uint8_t fsm11_en                 : 1;
1554   uint8_t fsm10_en                 : 1;
1555   uint8_t fsm9_en                  : 1;
1556 #endif /* DRV_BYTE_ORDER */
1557 } lsm6dsrx_fsm_enable_b_t;
1558 
1559 #define LSM6DSRX_FSM_LONG_COUNTER_L           0x48U
1560 #define LSM6DSRX_FSM_LONG_COUNTER_H           0x49U
1561 #define LSM6DSRX_FSM_LONG_COUNTER_CLEAR       0x4AU
1562 typedef struct
1563 {
1564 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1565 uint8_t fsm_lc_clr               :
1566   2;  /* fsm_lc_cleared + fsm_lc_clear */
1567   uint8_t not_used_01              : 6;
1568 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1569   uint8_t not_used_01              : 6;
1570 uint8_t fsm_lc_clr               :
1571   2;  /* fsm_lc_cleared + fsm_lc_clear */
1572 #endif /* DRV_BYTE_ORDER */
1573 } lsm6dsrx_fsm_long_counter_clear_t;
1574 
1575 #define LSM6DSRX_FSM_OUTS1                    0x4CU
1576 typedef struct
1577 {
1578 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1579   uint8_t n_v                      : 1;
1580   uint8_t p_v                      : 1;
1581   uint8_t n_z                      : 1;
1582   uint8_t p_z                      : 1;
1583   uint8_t n_y                      : 1;
1584   uint8_t p_y                      : 1;
1585   uint8_t n_x                      : 1;
1586   uint8_t p_x                      : 1;
1587 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1588   uint8_t p_x                      : 1;
1589   uint8_t n_x                      : 1;
1590   uint8_t p_y                      : 1;
1591   uint8_t n_y                      : 1;
1592   uint8_t p_z                      : 1;
1593   uint8_t n_z                      : 1;
1594   uint8_t p_v                      : 1;
1595   uint8_t n_v                      : 1;
1596 #endif /* DRV_BYTE_ORDER */
1597 } lsm6dsrx_fsm_outs1_t;
1598 
1599 #define LSM6DSRX_FSM_OUTS2                    0x4DU
1600 typedef struct
1601 {
1602 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1603   uint8_t n_v                      : 1;
1604   uint8_t p_v                      : 1;
1605   uint8_t n_z                      : 1;
1606   uint8_t p_z                      : 1;
1607   uint8_t n_y                      : 1;
1608   uint8_t p_y                      : 1;
1609   uint8_t n_x                      : 1;
1610   uint8_t p_x                      : 1;
1611 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1612   uint8_t p_x                      : 1;
1613   uint8_t n_x                      : 1;
1614   uint8_t p_y                      : 1;
1615   uint8_t n_y                      : 1;
1616   uint8_t p_z                      : 1;
1617   uint8_t n_z                      : 1;
1618   uint8_t p_v                      : 1;
1619   uint8_t n_v                      : 1;
1620 #endif /* DRV_BYTE_ORDER */
1621 } lsm6dsrx_fsm_outs2_t;
1622 
1623 #define LSM6DSRX_FSM_OUTS3                    0x4EU
1624 typedef struct
1625 {
1626 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1627   uint8_t n_v                      : 1;
1628   uint8_t p_v                      : 1;
1629   uint8_t n_z                      : 1;
1630   uint8_t p_z                      : 1;
1631   uint8_t n_y                      : 1;
1632   uint8_t p_y                      : 1;
1633   uint8_t n_x                      : 1;
1634   uint8_t p_x                      : 1;
1635 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1636   uint8_t p_x                      : 1;
1637   uint8_t n_x                      : 1;
1638   uint8_t p_y                      : 1;
1639   uint8_t n_y                      : 1;
1640   uint8_t p_z                      : 1;
1641   uint8_t n_z                      : 1;
1642   uint8_t p_v                      : 1;
1643   uint8_t n_v                      : 1;
1644 #endif /* DRV_BYTE_ORDER */
1645 } lsm6dsrx_fsm_outs3_t;
1646 
1647 #define LSM6DSRX_FSM_OUTS4                    0x4FU
1648 typedef struct
1649 {
1650 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1651   uint8_t n_v                      : 1;
1652   uint8_t p_v                      : 1;
1653   uint8_t n_z                      : 1;
1654   uint8_t p_z                      : 1;
1655   uint8_t n_y                      : 1;
1656   uint8_t p_y                      : 1;
1657   uint8_t n_x                      : 1;
1658   uint8_t p_x                      : 1;
1659 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1660   uint8_t p_x                      : 1;
1661   uint8_t n_x                      : 1;
1662   uint8_t p_y                      : 1;
1663   uint8_t n_y                      : 1;
1664   uint8_t p_z                      : 1;
1665   uint8_t n_z                      : 1;
1666   uint8_t p_v                      : 1;
1667   uint8_t n_v                      : 1;
1668 #endif /* DRV_BYTE_ORDER */
1669 } lsm6dsrx_fsm_outs4_t;
1670 
1671 #define LSM6DSRX_FSM_OUTS5                    0x50U
1672 typedef struct
1673 {
1674 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1675   uint8_t n_v                      : 1;
1676   uint8_t p_v                      : 1;
1677   uint8_t n_z                      : 1;
1678   uint8_t p_z                      : 1;
1679   uint8_t n_y                      : 1;
1680   uint8_t p_y                      : 1;
1681   uint8_t n_x                      : 1;
1682   uint8_t p_x                      : 1;
1683 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1684   uint8_t p_x                      : 1;
1685   uint8_t n_x                      : 1;
1686   uint8_t p_y                      : 1;
1687   uint8_t n_y                      : 1;
1688   uint8_t p_z                      : 1;
1689   uint8_t n_z                      : 1;
1690   uint8_t p_v                      : 1;
1691   uint8_t n_v                      : 1;
1692 #endif /* DRV_BYTE_ORDER */
1693 } lsm6dsrx_fsm_outs5_t;
1694 
1695 #define LSM6DSRX_FSM_OUTS6                    0x51U
1696 typedef struct
1697 {
1698 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1699   uint8_t n_v                      : 1;
1700   uint8_t p_v                      : 1;
1701   uint8_t n_z                      : 1;
1702   uint8_t p_z                      : 1;
1703   uint8_t n_y                      : 1;
1704   uint8_t p_y                      : 1;
1705   uint8_t n_x                      : 1;
1706   uint8_t p_x                      : 1;
1707 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1708   uint8_t p_x                      : 1;
1709   uint8_t n_x                      : 1;
1710   uint8_t p_y                      : 1;
1711   uint8_t n_y                      : 1;
1712   uint8_t p_z                      : 1;
1713   uint8_t n_z                      : 1;
1714   uint8_t p_v                      : 1;
1715   uint8_t n_v                      : 1;
1716 #endif /* DRV_BYTE_ORDER */
1717 } lsm6dsrx_fsm_outs6_t;
1718 
1719 #define LSM6DSRX_FSM_OUTS7                    0x52U
1720 typedef struct
1721 {
1722 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1723   uint8_t n_v                      : 1;
1724   uint8_t p_v                      : 1;
1725   uint8_t n_z                      : 1;
1726   uint8_t p_z                      : 1;
1727   uint8_t n_y                      : 1;
1728   uint8_t p_y                      : 1;
1729   uint8_t n_x                      : 1;
1730   uint8_t p_x                      : 1;
1731 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1732   uint8_t p_x                      : 1;
1733   uint8_t n_x                      : 1;
1734   uint8_t p_y                      : 1;
1735   uint8_t n_y                      : 1;
1736   uint8_t p_z                      : 1;
1737   uint8_t n_z                      : 1;
1738   uint8_t p_v                      : 1;
1739   uint8_t n_v                      : 1;
1740 #endif /* DRV_BYTE_ORDER */
1741 } lsm6dsrx_fsm_outs7_t;
1742 
1743 #define LSM6DSRX_FSM_OUTS8                    0x53U
1744 typedef struct
1745 {
1746 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1747   uint8_t n_v                      : 1;
1748   uint8_t p_v                      : 1;
1749   uint8_t n_z                      : 1;
1750   uint8_t p_z                      : 1;
1751   uint8_t n_y                      : 1;
1752   uint8_t p_y                      : 1;
1753   uint8_t n_x                      : 1;
1754   uint8_t p_x                      : 1;
1755 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1756   uint8_t p_x                      : 1;
1757   uint8_t n_x                      : 1;
1758   uint8_t p_y                      : 1;
1759   uint8_t n_y                      : 1;
1760   uint8_t p_z                      : 1;
1761   uint8_t n_z                      : 1;
1762   uint8_t p_v                      : 1;
1763   uint8_t n_v                      : 1;
1764 #endif /* DRV_BYTE_ORDER */
1765 } lsm6dsrx_fsm_outs8_t;
1766 
1767 #define LSM6DSRX_FSM_OUTS9                    0x54U
1768 typedef struct
1769 {
1770 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1771   uint8_t n_v                      : 1;
1772   uint8_t p_v                      : 1;
1773   uint8_t n_z                      : 1;
1774   uint8_t p_z                      : 1;
1775   uint8_t n_y                      : 1;
1776   uint8_t p_y                      : 1;
1777   uint8_t n_x                      : 1;
1778   uint8_t p_x                      : 1;
1779 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1780   uint8_t p_x                      : 1;
1781   uint8_t n_x                      : 1;
1782   uint8_t p_y                      : 1;
1783   uint8_t n_y                      : 1;
1784   uint8_t p_z                      : 1;
1785   uint8_t n_z                      : 1;
1786   uint8_t p_v                      : 1;
1787   uint8_t n_v                      : 1;
1788 #endif /* DRV_BYTE_ORDER */
1789 } lsm6dsrx_fsm_outs9_t;
1790 
1791 #define LSM6DSRX_FSM_OUTS10                   0x55U
1792 typedef struct
1793 {
1794 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1795   uint8_t n_v                      : 1;
1796   uint8_t p_v                      : 1;
1797   uint8_t n_z                      : 1;
1798   uint8_t p_z                      : 1;
1799   uint8_t n_y                      : 1;
1800   uint8_t p_y                      : 1;
1801   uint8_t n_x                      : 1;
1802   uint8_t p_x                      : 1;
1803 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1804   uint8_t p_x                      : 1;
1805   uint8_t n_x                      : 1;
1806   uint8_t p_y                      : 1;
1807   uint8_t n_y                      : 1;
1808   uint8_t p_z                      : 1;
1809   uint8_t n_z                      : 1;
1810   uint8_t p_v                      : 1;
1811   uint8_t n_v                      : 1;
1812 #endif /* DRV_BYTE_ORDER */
1813 } lsm6dsrx_fsm_outs10_t;
1814 
1815 #define LSM6DSRX_FSM_OUTS11                   0x56U
1816 typedef struct
1817 {
1818 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1819   uint8_t n_v                      : 1;
1820   uint8_t p_v                      : 1;
1821   uint8_t n_z                      : 1;
1822   uint8_t p_z                      : 1;
1823   uint8_t n_y                      : 1;
1824   uint8_t p_y                      : 1;
1825   uint8_t n_x                      : 1;
1826   uint8_t p_x                      : 1;
1827 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1828   uint8_t p_x                      : 1;
1829   uint8_t n_x                      : 1;
1830   uint8_t p_y                      : 1;
1831   uint8_t n_y                      : 1;
1832   uint8_t p_z                      : 1;
1833   uint8_t n_z                      : 1;
1834   uint8_t p_v                      : 1;
1835   uint8_t n_v                      : 1;
1836 #endif /* DRV_BYTE_ORDER */
1837 } lsm6dsrx_fsm_outs11_t;
1838 
1839 #define LSM6DSRX_FSM_OUTS12                   0x57U
1840 typedef struct
1841 {
1842 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1843   uint8_t n_v                      : 1;
1844   uint8_t p_v                      : 1;
1845   uint8_t n_z                      : 1;
1846   uint8_t p_z                      : 1;
1847   uint8_t n_y                      : 1;
1848   uint8_t p_y                      : 1;
1849   uint8_t n_x                      : 1;
1850   uint8_t p_x                      : 1;
1851 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1852   uint8_t p_x                      : 1;
1853   uint8_t n_x                      : 1;
1854   uint8_t p_y                      : 1;
1855   uint8_t n_y                      : 1;
1856   uint8_t p_z                      : 1;
1857   uint8_t n_z                      : 1;
1858   uint8_t p_v                      : 1;
1859   uint8_t n_v                      : 1;
1860 #endif /* DRV_BYTE_ORDER */
1861 } lsm6dsrx_fsm_outs12_t;
1862 
1863 #define LSM6DSRX_FSM_OUTS13                   0x58U
1864 typedef struct
1865 {
1866 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1867   uint8_t n_v                      : 1;
1868   uint8_t p_v                      : 1;
1869   uint8_t n_z                      : 1;
1870   uint8_t p_z                      : 1;
1871   uint8_t n_y                      : 1;
1872   uint8_t p_y                      : 1;
1873   uint8_t n_x                      : 1;
1874   uint8_t p_x                      : 1;
1875 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1876   uint8_t p_x                      : 1;
1877   uint8_t n_x                      : 1;
1878   uint8_t p_y                      : 1;
1879   uint8_t n_y                      : 1;
1880   uint8_t p_z                      : 1;
1881   uint8_t n_z                      : 1;
1882   uint8_t p_v                      : 1;
1883   uint8_t n_v                      : 1;
1884 #endif /* DRV_BYTE_ORDER */
1885 } lsm6dsrx_fsm_outs13_t;
1886 
1887 #define LSM6DSRX_FSM_OUTS14                   0x59U
1888 typedef struct
1889 {
1890 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1891   uint8_t n_v                      : 1;
1892   uint8_t p_v                      : 1;
1893   uint8_t n_z                      : 1;
1894   uint8_t p_z                      : 1;
1895   uint8_t n_y                      : 1;
1896   uint8_t p_y                      : 1;
1897   uint8_t n_x                      : 1;
1898   uint8_t p_x                      : 1;
1899 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1900   uint8_t p_x                      : 1;
1901   uint8_t n_x                      : 1;
1902   uint8_t p_y                      : 1;
1903   uint8_t n_y                      : 1;
1904   uint8_t p_z                      : 1;
1905   uint8_t n_z                      : 1;
1906   uint8_t p_v                      : 1;
1907   uint8_t n_v                      : 1;
1908 #endif /* DRV_BYTE_ORDER */
1909 } lsm6dsrx_fsm_outs14_t;
1910 
1911 #define LSM6DSRX_FSM_OUTS15                   0x5AU
1912 typedef struct
1913 {
1914 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1915   uint8_t n_v                      : 1;
1916   uint8_t p_v                      : 1;
1917   uint8_t n_z                      : 1;
1918   uint8_t p_z                      : 1;
1919   uint8_t n_y                      : 1;
1920   uint8_t p_y                      : 1;
1921   uint8_t n_x                      : 1;
1922   uint8_t p_x                      : 1;
1923 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1924   uint8_t p_x                      : 1;
1925   uint8_t n_x                      : 1;
1926   uint8_t p_y                      : 1;
1927   uint8_t n_y                      : 1;
1928   uint8_t p_z                      : 1;
1929   uint8_t n_z                      : 1;
1930   uint8_t p_v                      : 1;
1931   uint8_t n_v                      : 1;
1932 #endif /* DRV_BYTE_ORDER */
1933 } lsm6dsrx_fsm_outs15_t;
1934 
1935 #define LSM6DSRX_FSM_OUTS16                   0x5BU
1936 typedef struct
1937 {
1938 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1939   uint8_t n_v                      : 1;
1940   uint8_t p_v                      : 1;
1941   uint8_t n_z                      : 1;
1942   uint8_t p_z                      : 1;
1943   uint8_t n_y                      : 1;
1944   uint8_t p_y                      : 1;
1945   uint8_t n_x                      : 1;
1946   uint8_t p_x                      : 1;
1947 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1948   uint8_t p_x                      : 1;
1949   uint8_t n_x                      : 1;
1950   uint8_t p_y                      : 1;
1951   uint8_t n_y                      : 1;
1952   uint8_t p_z                      : 1;
1953   uint8_t n_z                      : 1;
1954   uint8_t p_v                      : 1;
1955   uint8_t n_v                      : 1;
1956 #endif /* DRV_BYTE_ORDER */
1957 } lsm6dsrx_fsm_outs16_t;
1958 
1959 #define LSM6DSRX_EMB_FUNC_ODR_CFG_B           0x5FU
1960 typedef struct
1961 {
1962 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1963   uint8_t not_used_01              : 3;
1964   uint8_t fsm_odr                  : 2;
1965   uint8_t not_used_02              : 3;
1966 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1967   uint8_t not_used_02              : 3;
1968   uint8_t fsm_odr                  : 2;
1969   uint8_t not_used_01              : 3;
1970 #endif /* DRV_BYTE_ORDER */
1971 } lsm6dsrx_emb_func_odr_cfg_b_t;
1972 
1973 #define LSM6DSRX_EMB_FUNC_ODR_CFG_C           0x60U
1974 typedef struct
1975 {
1976 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1977   uint8_t not_used_01             : 4;
1978   uint8_t mlc_odr                 : 2;
1979   uint8_t not_used_02             : 2;
1980 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
1981   uint8_t not_used_02             : 2;
1982   uint8_t mlc_odr                 : 2;
1983   uint8_t not_used_01             : 4;
1984 #endif /* DRV_BYTE_ORDER */
1985 } lsm6dsrx_emb_func_odr_cfg_c_t;
1986 
1987 #define LSM6DSRX_STEP_COUNTER_L               0x62U
1988 #define LSM6DSRX_STEP_COUNTER_H               0x63U
1989 #define LSM6DSRX_EMB_FUNC_SRC                 0x64U
1990 typedef struct
1991 {
1992 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
1993   uint8_t not_used_01              : 2;
1994   uint8_t stepcounter_bit_set      : 1;
1995   uint8_t step_overflow            : 1;
1996   uint8_t step_count_delta_ia      : 1;
1997   uint8_t step_detected            : 1;
1998   uint8_t not_used_02              : 1;
1999   uint8_t pedo_rst_step            : 1;
2000 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2001   uint8_t pedo_rst_step            : 1;
2002   uint8_t not_used_02              : 1;
2003   uint8_t step_detected            : 1;
2004   uint8_t step_count_delta_ia      : 1;
2005   uint8_t step_overflow            : 1;
2006   uint8_t stepcounter_bit_set      : 1;
2007   uint8_t not_used_01              : 2;
2008 #endif /* DRV_BYTE_ORDER */
2009 } lsm6dsrx_emb_func_src_t;
2010 
2011 #define LSM6DSRX_EMB_FUNC_INIT_A              0x66U
2012 typedef struct
2013 {
2014 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2015   uint8_t not_used_01               : 3;
2016   uint8_t step_det_init             : 1;
2017   uint8_t tilt_init                 : 1;
2018   uint8_t sig_mot_init              : 1;
2019   uint8_t not_used_02               : 2;
2020 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2021   uint8_t not_used_02               : 2;
2022   uint8_t sig_mot_init              : 1;
2023   uint8_t tilt_init                 : 1;
2024   uint8_t step_det_init             : 1;
2025   uint8_t not_used_01               : 3;
2026 #endif /* DRV_BYTE_ORDER */
2027 } lsm6dsrx_emb_func_init_a_t;
2028 
2029 #define LSM6DSRX_EMB_FUNC_INIT_B              0x67U
2030 typedef struct
2031 {
2032 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2033   uint8_t fsm_init                 : 1;
2034   uint8_t not_used_01              : 2;
2035   uint8_t fifo_compr_init          : 1;
2036   uint8_t not_used_02              : 4;
2037 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2038   uint8_t not_used_02              : 4;
2039   uint8_t fifo_compr_init          : 1;
2040   uint8_t not_used_01              : 2;
2041   uint8_t fsm_init                 : 1;
2042 #endif /* DRV_BYTE_ORDER */
2043 } lsm6dsrx_emb_func_init_b_t;
2044 
2045 #define LSM6DSRX_MLC0_SRC                     0x70U
2046 #define LSM6DSRX_MLC1_SRC                     0x71U
2047 #define LSM6DSRX_MLC2_SRC                     0x72U
2048 #define LSM6DSRX_MLC3_SRC                     0x73U
2049 #define LSM6DSRX_MLC4_SRC                     0x74U
2050 #define LSM6DSRX_MLC5_SRC                     0x75U
2051 #define LSM6DSRX_MLC6_SRC                     0x76U
2052 #define LSM6DSRX_MLC7_SRC                     0x77U
2053 #define LSM6DSRX_MAG_SENSITIVITY_L            0xBAU
2054 #define LSM6DSRX_MAG_SENSITIVITY_H            0xBBU
2055 #define LSM6DSRX_MAG_OFFX_L                   0xC0U
2056 #define LSM6DSRX_MAG_OFFX_H                   0xC1U
2057 #define LSM6DSRX_MAG_OFFY_L                   0xC2U
2058 #define LSM6DSRX_MAG_OFFY_H                   0xC3U
2059 #define LSM6DSRX_MAG_OFFZ_L                   0xC4U
2060 #define LSM6DSRX_MAG_OFFZ_H                   0xC5U
2061 #define LSM6DSRX_MAG_SI_XX_L                  0xC6U
2062 #define LSM6DSRX_MAG_SI_XX_H                  0xC7U
2063 #define LSM6DSRX_MAG_SI_XY_L                  0xC8U
2064 #define LSM6DSRX_MAG_SI_XY_H                  0xC9U
2065 #define LSM6DSRX_MAG_SI_XZ_L                  0xCAU
2066 #define LSM6DSRX_MAG_SI_XZ_H                  0xCBU
2067 #define LSM6DSRX_MAG_SI_YY_L                  0xCCU
2068 #define LSM6DSRX_MAG_SI_YY_H                  0xCDU
2069 #define LSM6DSRX_MAG_SI_YZ_L                  0xCEU
2070 #define LSM6DSRX_MAG_SI_YZ_H                  0xCFU
2071 #define LSM6DSRX_MAG_SI_ZZ_L                  0xD0U
2072 #define LSM6DSRX_MAG_SI_ZZ_H                  0xD1U
2073 #define LSM6DSRX_MAG_CFG_A                    0xD4U
2074 typedef struct
2075 {
2076 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2077   uint8_t mag_z_axis               : 3;
2078   uint8_t not_used_01              : 1;
2079   uint8_t mag_y_axis               : 3;
2080   uint8_t not_used_02              : 1;
2081 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2082   uint8_t not_used_02              : 1;
2083   uint8_t mag_y_axis               : 3;
2084   uint8_t not_used_01              : 1;
2085   uint8_t mag_z_axis               : 3;
2086 #endif /* DRV_BYTE_ORDER */
2087 } lsm6dsrx_mag_cfg_a_t;
2088 
2089 #define LSM6DSRX_MAG_CFG_B                    0xD5U
2090 typedef struct
2091 {
2092 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2093   uint8_t mag_x_axis               : 3;
2094   uint8_t not_used_01              : 5;
2095 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2096   uint8_t not_used_01              : 5;
2097   uint8_t mag_x_axis               : 3;
2098 #endif /* DRV_BYTE_ORDER */
2099 } lsm6dsrx_mag_cfg_b_t;
2100 
2101 #define LSM6DSRX_FSM_LC_TIMEOUT_L             0x17AU
2102 #define LSM6DSRX_FSM_LC_TIMEOUT_H             0x17BU
2103 #define LSM6DSRX_FSM_PROGRAMS                 0x17CU
2104 #define LSM6DSRX_FSM_START_ADD_L              0x17EU
2105 #define LSM6DSRX_FSM_START_ADD_H              0x17FU
2106 #define LSM6DSRX_PEDO_CMD_REG                 0x183U
2107 typedef struct
2108 {
2109 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2110   uint8_t not_used_01              : 3;
2111   uint8_t carry_count_en           : 1;
2112   uint8_t not_used_02              : 4;
2113 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2114   uint8_t not_used_02              : 4;
2115   uint8_t carry_count_en           : 1;
2116   uint8_t not_used_01              : 3;
2117 #endif /* DRV_BYTE_ORDER */
2118 } lsm6dsrx_pedo_cmd_reg_t;
2119 
2120 #define LSM6DSRX_PEDO_DEB_STEPS_CONF          0x184U
2121 #define LSM6DSRX_PEDO_SC_DELTAT_L             0x1D0U
2122 #define LSM6DSRX_PEDO_SC_DELTAT_H             0x1D1U
2123 
2124 #define LSM6DSRX_MLC_MAG_SENSITIVITY_L        0x1E8U
2125 #define LSM6DSRX_MLC_MAG_SENSITIVITY_H        0x1E9U
2126 
2127 #define LSM6DSRX_SENSOR_HUB_1                 0x02U
2128 typedef struct
2129 {
2130 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2131   uint8_t bit0                    : 1;
2132   uint8_t bit1                    : 1;
2133   uint8_t bit2                    : 1;
2134   uint8_t bit3                    : 1;
2135   uint8_t bit4                    : 1;
2136   uint8_t bit5                    : 1;
2137   uint8_t bit6                    : 1;
2138   uint8_t bit7                    : 1;
2139 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2140   uint8_t bit7                    : 1;
2141   uint8_t bit6                    : 1;
2142   uint8_t bit5                    : 1;
2143   uint8_t bit4                    : 1;
2144   uint8_t bit3                    : 1;
2145   uint8_t bit2                    : 1;
2146   uint8_t bit1                    : 1;
2147   uint8_t bit0                    : 1;
2148 #endif /* DRV_BYTE_ORDER */
2149 } lsm6dsrx_sensor_hub_1_t;
2150 
2151 #define LSM6DSRX_SENSOR_HUB_2                 0x03U
2152 typedef struct
2153 {
2154 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2155   uint8_t bit0                    : 1;
2156   uint8_t bit1                    : 1;
2157   uint8_t bit2                    : 1;
2158   uint8_t bit3                    : 1;
2159   uint8_t bit4                    : 1;
2160   uint8_t bit5                    : 1;
2161   uint8_t bit6                    : 1;
2162   uint8_t bit7                    : 1;
2163 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2164   uint8_t bit7                    : 1;
2165   uint8_t bit6                    : 1;
2166   uint8_t bit5                    : 1;
2167   uint8_t bit4                    : 1;
2168   uint8_t bit3                    : 1;
2169   uint8_t bit2                    : 1;
2170   uint8_t bit1                    : 1;
2171   uint8_t bit0                    : 1;
2172 #endif /* DRV_BYTE_ORDER */
2173 } lsm6dsrx_sensor_hub_2_t;
2174 
2175 #define LSM6DSRX_SENSOR_HUB_3                 0x04U
2176 typedef struct
2177 {
2178 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2179   uint8_t bit0                    : 1;
2180   uint8_t bit1                    : 1;
2181   uint8_t bit2                    : 1;
2182   uint8_t bit3                    : 1;
2183   uint8_t bit4                    : 1;
2184   uint8_t bit5                    : 1;
2185   uint8_t bit6                    : 1;
2186   uint8_t bit7                    : 1;
2187 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2188   uint8_t bit7                    : 1;
2189   uint8_t bit6                    : 1;
2190   uint8_t bit5                    : 1;
2191   uint8_t bit4                    : 1;
2192   uint8_t bit3                    : 1;
2193   uint8_t bit2                    : 1;
2194   uint8_t bit1                    : 1;
2195   uint8_t bit0                    : 1;
2196 #endif /* DRV_BYTE_ORDER */
2197 } lsm6dsrx_sensor_hub_3_t;
2198 
2199 #define LSM6DSRX_SENSOR_HUB_4                 0x05U
2200 typedef struct
2201 {
2202 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2203   uint8_t bit0                    : 1;
2204   uint8_t bit1                    : 1;
2205   uint8_t bit2                    : 1;
2206   uint8_t bit3                    : 1;
2207   uint8_t bit4                    : 1;
2208   uint8_t bit5                    : 1;
2209   uint8_t bit6                    : 1;
2210   uint8_t bit7                    : 1;
2211 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2212   uint8_t bit7                    : 1;
2213   uint8_t bit6                    : 1;
2214   uint8_t bit5                    : 1;
2215   uint8_t bit4                    : 1;
2216   uint8_t bit3                    : 1;
2217   uint8_t bit2                    : 1;
2218   uint8_t bit1                    : 1;
2219   uint8_t bit0                    : 1;
2220 #endif /* DRV_BYTE_ORDER */
2221 } lsm6dsrx_sensor_hub_4_t;
2222 
2223 #define LSM6DSRX_SENSOR_HUB_5                 0x06U
2224 typedef struct
2225 {
2226 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2227   uint8_t bit0                    : 1;
2228   uint8_t bit1                    : 1;
2229   uint8_t bit2                    : 1;
2230   uint8_t bit3                    : 1;
2231   uint8_t bit4                    : 1;
2232   uint8_t bit5                    : 1;
2233   uint8_t bit6                    : 1;
2234   uint8_t bit7                    : 1;
2235 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2236   uint8_t bit7                    : 1;
2237   uint8_t bit6                    : 1;
2238   uint8_t bit5                    : 1;
2239   uint8_t bit4                    : 1;
2240   uint8_t bit3                    : 1;
2241   uint8_t bit2                    : 1;
2242   uint8_t bit1                    : 1;
2243   uint8_t bit0                    : 1;
2244 #endif /* DRV_BYTE_ORDER */
2245 } lsm6dsrx_sensor_hub_5_t;
2246 
2247 #define LSM6DSRX_SENSOR_HUB_6                 0x07U
2248 typedef struct
2249 {
2250 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2251   uint8_t bit0                    : 1;
2252   uint8_t bit1                    : 1;
2253   uint8_t bit2                    : 1;
2254   uint8_t bit3                    : 1;
2255   uint8_t bit4                    : 1;
2256   uint8_t bit5                    : 1;
2257   uint8_t bit6                    : 1;
2258   uint8_t bit7                    : 1;
2259 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2260   uint8_t bit7                    : 1;
2261   uint8_t bit6                    : 1;
2262   uint8_t bit5                    : 1;
2263   uint8_t bit4                    : 1;
2264   uint8_t bit3                    : 1;
2265   uint8_t bit2                    : 1;
2266   uint8_t bit1                    : 1;
2267   uint8_t bit0                    : 1;
2268 #endif /* DRV_BYTE_ORDER */
2269 } lsm6dsrx_sensor_hub_6_t;
2270 
2271 #define LSM6DSRX_SENSOR_HUB_7                 0x08U
2272 typedef struct
2273 {
2274 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2275   uint8_t bit0                    : 1;
2276   uint8_t bit1                    : 1;
2277   uint8_t bit2                    : 1;
2278   uint8_t bit3                    : 1;
2279   uint8_t bit4                    : 1;
2280   uint8_t bit5                    : 1;
2281   uint8_t bit6                    : 1;
2282   uint8_t bit7                    : 1;
2283 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2284   uint8_t bit7                    : 1;
2285   uint8_t bit6                    : 1;
2286   uint8_t bit5                    : 1;
2287   uint8_t bit4                    : 1;
2288   uint8_t bit3                    : 1;
2289   uint8_t bit2                    : 1;
2290   uint8_t bit1                    : 1;
2291   uint8_t bit0                    : 1;
2292 #endif /* DRV_BYTE_ORDER */
2293 } lsm6dsrx_sensor_hub_7_t;
2294 
2295 #define LSM6DSRX_SENSOR_HUB_8                 0x09U
2296 typedef struct
2297 {
2298 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2299   uint8_t bit0                    : 1;
2300   uint8_t bit1                    : 1;
2301   uint8_t bit2                    : 1;
2302   uint8_t bit3                    : 1;
2303   uint8_t bit4                    : 1;
2304   uint8_t bit5                    : 1;
2305   uint8_t bit6                    : 1;
2306   uint8_t bit7                    : 1;
2307 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2308   uint8_t bit7                    : 1;
2309   uint8_t bit6                    : 1;
2310   uint8_t bit5                    : 1;
2311   uint8_t bit4                    : 1;
2312   uint8_t bit3                    : 1;
2313   uint8_t bit2                    : 1;
2314   uint8_t bit1                    : 1;
2315   uint8_t bit0                    : 1;
2316 #endif /* DRV_BYTE_ORDER */
2317 } lsm6dsrx_sensor_hub_8_t;
2318 
2319 #define LSM6DSRX_SENSOR_HUB_9                 0x0AU
2320 typedef struct
2321 {
2322 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2323   uint8_t bit0                    : 1;
2324   uint8_t bit1                    : 1;
2325   uint8_t bit2                    : 1;
2326   uint8_t bit3                    : 1;
2327   uint8_t bit4                    : 1;
2328   uint8_t bit5                    : 1;
2329   uint8_t bit6                    : 1;
2330   uint8_t bit7                    : 1;
2331 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2332   uint8_t bit7                    : 1;
2333   uint8_t bit6                    : 1;
2334   uint8_t bit5                    : 1;
2335   uint8_t bit4                    : 1;
2336   uint8_t bit3                    : 1;
2337   uint8_t bit2                    : 1;
2338   uint8_t bit1                    : 1;
2339   uint8_t bit0                    : 1;
2340 #endif /* DRV_BYTE_ORDER */
2341 } lsm6dsrx_sensor_hub_9_t;
2342 
2343 #define LSM6DSRX_SENSOR_HUB_10                0x0BU
2344 typedef struct
2345 {
2346 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2347   uint8_t bit0                    : 1;
2348   uint8_t bit1                    : 1;
2349   uint8_t bit2                    : 1;
2350   uint8_t bit3                    : 1;
2351   uint8_t bit4                    : 1;
2352   uint8_t bit5                    : 1;
2353   uint8_t bit6                    : 1;
2354   uint8_t bit7                    : 1;
2355 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2356   uint8_t bit7                    : 1;
2357   uint8_t bit6                    : 1;
2358   uint8_t bit5                    : 1;
2359   uint8_t bit4                    : 1;
2360   uint8_t bit3                    : 1;
2361   uint8_t bit2                    : 1;
2362   uint8_t bit1                    : 1;
2363   uint8_t bit0                    : 1;
2364 #endif /* DRV_BYTE_ORDER */
2365 } lsm6dsrx_sensor_hub_10_t;
2366 
2367 #define LSM6DSRX_SENSOR_HUB_11                0x0CU
2368 typedef struct
2369 {
2370 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2371   uint8_t bit0                    : 1;
2372   uint8_t bit1                    : 1;
2373   uint8_t bit2                    : 1;
2374   uint8_t bit3                    : 1;
2375   uint8_t bit4                    : 1;
2376   uint8_t bit5                    : 1;
2377   uint8_t bit6                    : 1;
2378   uint8_t bit7                    : 1;
2379 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2380   uint8_t bit7                    : 1;
2381   uint8_t bit6                    : 1;
2382   uint8_t bit5                    : 1;
2383   uint8_t bit4                    : 1;
2384   uint8_t bit3                    : 1;
2385   uint8_t bit2                    : 1;
2386   uint8_t bit1                    : 1;
2387   uint8_t bit0                    : 1;
2388 #endif /* DRV_BYTE_ORDER */
2389 } lsm6dsrx_sensor_hub_11_t;
2390 
2391 #define LSM6DSRX_SENSOR_HUB_12                0x0DU
2392 typedef struct
2393 {
2394 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2395   uint8_t bit0                    : 1;
2396   uint8_t bit1                    : 1;
2397   uint8_t bit2                    : 1;
2398   uint8_t bit3                    : 1;
2399   uint8_t bit4                    : 1;
2400   uint8_t bit5                    : 1;
2401   uint8_t bit6                    : 1;
2402   uint8_t bit7                    : 1;
2403 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2404   uint8_t bit7                    : 1;
2405   uint8_t bit6                    : 1;
2406   uint8_t bit5                    : 1;
2407   uint8_t bit4                    : 1;
2408   uint8_t bit3                    : 1;
2409   uint8_t bit2                    : 1;
2410   uint8_t bit1                    : 1;
2411   uint8_t bit0                    : 1;
2412 #endif /* DRV_BYTE_ORDER */
2413 } lsm6dsrx_sensor_hub_12_t;
2414 
2415 #define LSM6DSRX_SENSOR_HUB_13                0x0EU
2416 typedef struct
2417 {
2418 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2419   uint8_t bit0                    : 1;
2420   uint8_t bit1                    : 1;
2421   uint8_t bit2                    : 1;
2422   uint8_t bit3                    : 1;
2423   uint8_t bit4                    : 1;
2424   uint8_t bit5                    : 1;
2425   uint8_t bit6                    : 1;
2426   uint8_t bit7                    : 1;
2427 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2428   uint8_t bit7                    : 1;
2429   uint8_t bit6                    : 1;
2430   uint8_t bit5                    : 1;
2431   uint8_t bit4                    : 1;
2432   uint8_t bit3                    : 1;
2433   uint8_t bit2                    : 1;
2434   uint8_t bit1                    : 1;
2435   uint8_t bit0                    : 1;
2436 #endif /* DRV_BYTE_ORDER */
2437 } lsm6dsrx_sensor_hub_13_t;
2438 
2439 #define LSM6DSRX_SENSOR_HUB_14                0x0FU
2440 typedef struct
2441 {
2442 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2443   uint8_t bit0                    : 1;
2444   uint8_t bit1                    : 1;
2445   uint8_t bit2                    : 1;
2446   uint8_t bit3                    : 1;
2447   uint8_t bit4                    : 1;
2448   uint8_t bit5                    : 1;
2449   uint8_t bit6                    : 1;
2450   uint8_t bit7                    : 1;
2451 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2452   uint8_t bit7                    : 1;
2453   uint8_t bit6                    : 1;
2454   uint8_t bit5                    : 1;
2455   uint8_t bit4                    : 1;
2456   uint8_t bit3                    : 1;
2457   uint8_t bit2                    : 1;
2458   uint8_t bit1                    : 1;
2459   uint8_t bit0                    : 1;
2460 #endif /* DRV_BYTE_ORDER */
2461 } lsm6dsrx_sensor_hub_14_t;
2462 
2463 #define LSM6DSRX_SENSOR_HUB_15                0x10U
2464 typedef struct
2465 {
2466 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2467   uint8_t bit0                    : 1;
2468   uint8_t bit1                    : 1;
2469   uint8_t bit2                    : 1;
2470   uint8_t bit3                    : 1;
2471   uint8_t bit4                    : 1;
2472   uint8_t bit5                    : 1;
2473   uint8_t bit6                    : 1;
2474   uint8_t bit7                    : 1;
2475 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2476   uint8_t bit7                    : 1;
2477   uint8_t bit6                    : 1;
2478   uint8_t bit5                    : 1;
2479   uint8_t bit4                    : 1;
2480   uint8_t bit3                    : 1;
2481   uint8_t bit2                    : 1;
2482   uint8_t bit1                    : 1;
2483   uint8_t bit0                    : 1;
2484 #endif /* DRV_BYTE_ORDER */
2485 } lsm6dsrx_sensor_hub_15_t;
2486 
2487 #define LSM6DSRX_SENSOR_HUB_16                0x11U
2488 typedef struct
2489 {
2490 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2491   uint8_t bit0                    : 1;
2492   uint8_t bit1                    : 1;
2493   uint8_t bit2                    : 1;
2494   uint8_t bit3                    : 1;
2495   uint8_t bit4                    : 1;
2496   uint8_t bit5                    : 1;
2497   uint8_t bit6                    : 1;
2498   uint8_t bit7                    : 1;
2499 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2500   uint8_t bit7                    : 1;
2501   uint8_t bit6                    : 1;
2502   uint8_t bit5                    : 1;
2503   uint8_t bit4                    : 1;
2504   uint8_t bit3                    : 1;
2505   uint8_t bit2                    : 1;
2506   uint8_t bit1                    : 1;
2507   uint8_t bit0                    : 1;
2508 #endif /* DRV_BYTE_ORDER */
2509 } lsm6dsrx_sensor_hub_16_t;
2510 
2511 #define LSM6DSRX_SENSOR_HUB_17                0x12U
2512 typedef struct
2513 {
2514 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2515   uint8_t bit0                    : 1;
2516   uint8_t bit1                    : 1;
2517   uint8_t bit2                    : 1;
2518   uint8_t bit3                    : 1;
2519   uint8_t bit4                    : 1;
2520   uint8_t bit5                    : 1;
2521   uint8_t bit6                    : 1;
2522   uint8_t bit7                    : 1;
2523 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2524   uint8_t bit7                    : 1;
2525   uint8_t bit6                    : 1;
2526   uint8_t bit5                    : 1;
2527   uint8_t bit4                    : 1;
2528   uint8_t bit3                    : 1;
2529   uint8_t bit2                    : 1;
2530   uint8_t bit1                    : 1;
2531   uint8_t bit0                    : 1;
2532 #endif /* DRV_BYTE_ORDER */
2533 } lsm6dsrx_sensor_hub_17_t;
2534 
2535 #define LSM6DSRX_SENSOR_HUB_18                0x13U
2536 typedef struct
2537 {
2538 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2539   uint8_t bit0                    : 1;
2540   uint8_t bit1                    : 1;
2541   uint8_t bit2                    : 1;
2542   uint8_t bit3                    : 1;
2543   uint8_t bit4                    : 1;
2544   uint8_t bit5                    : 1;
2545   uint8_t bit6                    : 1;
2546   uint8_t bit7                    : 1;
2547 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2548   uint8_t bit7                    : 1;
2549   uint8_t bit6                    : 1;
2550   uint8_t bit5                    : 1;
2551   uint8_t bit4                    : 1;
2552   uint8_t bit3                    : 1;
2553   uint8_t bit2                    : 1;
2554   uint8_t bit1                    : 1;
2555   uint8_t bit0                    : 1;
2556 #endif /* DRV_BYTE_ORDER */
2557 } lsm6dsrx_sensor_hub_18_t;
2558 
2559 #define LSM6DSRX_MASTER_CONFIG                0x14U
2560 typedef struct
2561 {
2562 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2563   uint8_t aux_sens_on              : 2;
2564   uint8_t master_on                : 1;
2565   uint8_t shub_pu_en               : 1;
2566   uint8_t pass_through_mode        : 1;
2567   uint8_t start_config             : 1;
2568   uint8_t write_once               : 1;
2569   uint8_t rst_master_regs          : 1;
2570 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2571   uint8_t rst_master_regs          : 1;
2572   uint8_t write_once               : 1;
2573   uint8_t start_config             : 1;
2574   uint8_t pass_through_mode        : 1;
2575   uint8_t shub_pu_en               : 1;
2576   uint8_t master_on                : 1;
2577   uint8_t aux_sens_on              : 2;
2578 #endif /* DRV_BYTE_ORDER */
2579 } lsm6dsrx_master_config_t;
2580 
2581 #define LSM6DSRX_SLV0_ADD                     0x15U
2582 typedef struct
2583 {
2584 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2585   uint8_t rw_0                     : 1;
2586   uint8_t slave0                   : 7;
2587 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2588   uint8_t slave0                   : 7;
2589   uint8_t rw_0                     : 1;
2590 #endif /* DRV_BYTE_ORDER */
2591 } lsm6dsrx_slv0_add_t;
2592 
2593 #define LSM6DSRX_SLV0_SUBADD                  0x16U
2594 typedef struct
2595 {
2596   uint8_t slave0_reg               : 8;
2597 } lsm6dsrx_slv0_subadd_t;
2598 
2599 #define LSM6DSRX_SLV0_CONFIG                  0x17U
2600 typedef struct
2601 {
2602 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2603   uint8_t slave0_numop             : 3;
2604   uint8_t batch_ext_sens_0_en      : 1;
2605   uint8_t not_used_01              : 2;
2606   uint8_t shub_odr                 : 2;
2607 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2608   uint8_t shub_odr                 : 2;
2609   uint8_t not_used_01              : 2;
2610   uint8_t batch_ext_sens_0_en      : 1;
2611   uint8_t slave0_numop             : 3;
2612 #endif /* DRV_BYTE_ORDER */
2613 } lsm6dsrx_slv0_config_t;
2614 
2615 #define LSM6DSRX_SLV1_ADD                     0x18U
2616 typedef struct
2617 {
2618 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2619   uint8_t r_1                      : 1;
2620   uint8_t slave1_add               : 7;
2621 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2622   uint8_t slave1_add               : 7;
2623   uint8_t r_1                      : 1;
2624 #endif /* DRV_BYTE_ORDER */
2625 } lsm6dsrx_slv1_add_t;
2626 
2627 #define LSM6DSRX_SLV1_SUBADD                  0x19U
2628 typedef struct
2629 {
2630   uint8_t slave1_reg               : 8;
2631 } lsm6dsrx_slv1_subadd_t;
2632 
2633 #define LSM6DSRX_SLV1_CONFIG                  0x1AU
2634 typedef struct
2635 {
2636 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2637   uint8_t slave1_numop             : 3;
2638   uint8_t batch_ext_sens_1_en      : 1;
2639   uint8_t not_used_01              : 4;
2640 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2641   uint8_t not_used_01              : 4;
2642   uint8_t batch_ext_sens_1_en      : 1;
2643   uint8_t slave1_numop             : 3;
2644 #endif /* DRV_BYTE_ORDER */
2645 } lsm6dsrx_slv1_config_t;
2646 
2647 #define LSM6DSRX_SLV2_ADD                     0x1BU
2648 typedef struct
2649 {
2650 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2651   uint8_t r_2                      : 1;
2652   uint8_t slave2_add               : 7;
2653 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2654   uint8_t slave2_add               : 7;
2655   uint8_t r_2                      : 1;
2656 #endif /* DRV_BYTE_ORDER */
2657 } lsm6dsrx_slv2_add_t;
2658 
2659 #define LSM6DSRX_SLV2_SUBADD                  0x1CU
2660 typedef struct
2661 {
2662   uint8_t slave2_reg               : 8;
2663 } lsm6dsrx_slv2_subadd_t;
2664 
2665 #define LSM6DSRX_SLV2_CONFIG                  0x1DU
2666 typedef struct
2667 {
2668 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2669   uint8_t slave2_numop             : 3;
2670   uint8_t batch_ext_sens_2_en      : 1;
2671   uint8_t not_used_01              : 4;
2672 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2673   uint8_t not_used_01              : 4;
2674   uint8_t batch_ext_sens_2_en      : 1;
2675   uint8_t slave2_numop             : 3;
2676 #endif /* DRV_BYTE_ORDER */
2677 } lsm6dsrx_slv2_config_t;
2678 
2679 #define LSM6DSRX_SLV3_ADD                     0x1EU
2680 typedef struct
2681 {
2682 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2683   uint8_t r_3                      : 1;
2684   uint8_t slave3_add               : 7;
2685 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2686   uint8_t slave3_add               : 7;
2687   uint8_t r_3                      : 1;
2688 #endif /* DRV_BYTE_ORDER */
2689 } lsm6dsrx_slv3_add_t;
2690 
2691 #define LSM6DSRX_SLV3_SUBADD                  0x1FU
2692 typedef struct
2693 {
2694   uint8_t slave3_reg               : 8;
2695 } lsm6dsrx_slv3_subadd_t;
2696 
2697 #define LSM6DSRX_SLV3_CONFIG                  0x20U
2698 typedef struct
2699 {
2700 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2701   uint8_t slave3_numop             : 3;
2702   uint8_t batch_ext_sens_3_en      : 1;
2703   uint8_t not_used_01              : 4;
2704 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2705   uint8_t not_used_01              : 4;
2706   uint8_t batch_ext_sens_3_en      : 1;
2707   uint8_t slave3_numop             : 3;
2708 #endif /* DRV_BYTE_ORDER */
2709 } lsm6dsrx_slv3_config_t;
2710 
2711 #define LSM6DSRX_DATAWRITE_SLV0  0x21U
2712 typedef struct
2713 {
2714   uint8_t slave0_dataw             : 8;
2715 } lsm6dsrx_datawrite_slv0_t;
2716 
2717 #define LSM6DSRX_STATUS_MASTER                0x22U
2718 typedef struct
2719 {
2720 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN
2721   uint8_t sens_hub_endop           : 1;
2722   uint8_t not_used_01              : 2;
2723   uint8_t slave0_nack              : 1;
2724   uint8_t slave1_nack              : 1;
2725   uint8_t slave2_nack              : 1;
2726   uint8_t slave3_nack              : 1;
2727   uint8_t wr_once_done             : 1;
2728 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN
2729   uint8_t wr_once_done             : 1;
2730   uint8_t slave3_nack              : 1;
2731   uint8_t slave2_nack              : 1;
2732   uint8_t slave1_nack              : 1;
2733   uint8_t slave0_nack              : 1;
2734   uint8_t not_used_01              : 2;
2735   uint8_t sens_hub_endop           : 1;
2736 #endif /* DRV_BYTE_ORDER */
2737 } lsm6dsrx_status_master_t;
2738 
2739 /**
2740   * @defgroup LSM6DSRX_Register_Union
2741   * @brief    This union group all the registers having a bit-field
2742   *           description.
2743   *           This union is useful but it's not needed by the driver.
2744   *
2745   *           REMOVING this union you are compliant with:
2746   *           MISRA-C 2012 [Rule 19.2] -> " Union are not allowed "
2747   *
2748   * @{
2749   *
2750   */
2751 typedef union
2752 {
2753   lsm6dsrx_func_cfg_access_t               func_cfg_access;
2754   lsm6dsrx_pin_ctrl_t                      pin_ctrl;
2755   lsm6dsrx_s4s_tph_l_t                     s4s_tph_l;
2756   lsm6dsrx_s4s_tph_h_t                     s4s_tph_h;
2757   lsm6dsrx_s4s_rr_t                        s4s_rr;
2758   lsm6dsrx_fifo_ctrl1_t                    fifo_ctrl1;
2759   lsm6dsrx_fifo_ctrl2_t                    fifo_ctrl2;
2760   lsm6dsrx_fifo_ctrl3_t                    fifo_ctrl3;
2761   lsm6dsrx_fifo_ctrl4_t                    fifo_ctrl4;
2762   lsm6dsrx_counter_bdr_reg1_t              counter_bdr_reg1;
2763   lsm6dsrx_counter_bdr_reg2_t              counter_bdr_reg2;
2764   lsm6dsrx_int1_ctrl_t                     int1_ctrl;
2765   lsm6dsrx_int2_ctrl_t                     int2_ctrl;
2766   lsm6dsrx_ctrl1_xl_t                      ctrl1_xl;
2767   lsm6dsrx_ctrl2_g_t                       ctrl2_g;
2768   lsm6dsrx_ctrl3_c_t                       ctrl3_c;
2769   lsm6dsrx_ctrl4_c_t                       ctrl4_c;
2770   lsm6dsrx_ctrl5_c_t                       ctrl5_c;
2771   lsm6dsrx_ctrl6_c_t                       ctrl6_c;
2772   lsm6dsrx_ctrl7_g_t                       ctrl7_g;
2773   lsm6dsrx_ctrl8_xl_t                      ctrl8_xl;
2774   lsm6dsrx_ctrl9_xl_t                      ctrl9_xl;
2775   lsm6dsrx_ctrl10_c_t                      ctrl10_c;
2776   lsm6dsrx_all_int_src_t                   all_int_src;
2777   lsm6dsrx_wake_up_src_t                   wake_up_src;
2778   lsm6dsrx_tap_src_t                       tap_src;
2779   lsm6dsrx_d6d_src_t                       d6d_src;
2780   lsm6dsrx_status_reg_t                    status_reg;
2781   lsm6dsrx_status_spiaux_t                 status_spiaux;
2782   lsm6dsrx_fifo_status1_t                  fifo_status1;
2783   lsm6dsrx_fifo_status2_t                  fifo_status2;
2784   lsm6dsrx_tap_cfg0_t                      tap_cfg0;
2785   lsm6dsrx_tap_cfg1_t                      tap_cfg1;
2786   lsm6dsrx_tap_cfg2_t                      tap_cfg2;
2787   lsm6dsrx_tap_ths_6d_t                    tap_ths_6d;
2788   lsm6dsrx_int_dur2_t                      int_dur2;
2789   lsm6dsrx_wake_up_ths_t                   wake_up_ths;
2790   lsm6dsrx_wake_up_dur_t                   wake_up_dur;
2791   lsm6dsrx_free_fall_t                     free_fall;
2792   lsm6dsrx_md1_cfg_t                       md1_cfg;
2793   lsm6dsrx_md2_cfg_t                       md2_cfg;
2794   lsm6dsrx_s4s_st_cmd_code_t               s4s_st_cmd_code;
2795   lsm6dsrx_s4s_dt_reg_t                    s4s_dt_reg;
2796   lsm6dsrx_i3c_bus_avb_t                   i3c_bus_avb;
2797   lsm6dsrx_internal_freq_fine_t            internal_freq_fine;
2798   lsm6dsrx_int_ois_t                       int_ois;
2799   lsm6dsrx_ctrl1_ois_t                     ctrl1_ois;
2800   lsm6dsrx_ctrl2_ois_t                     ctrl2_ois;
2801   lsm6dsrx_ctrl3_ois_t                     ctrl3_ois;
2802   lsm6dsrx_fifo_data_out_tag_t             fifo_data_out_tag;
2803   lsm6dsrx_page_sel_t                      page_sel;
2804   lsm6dsrx_emb_func_en_a_t                 emb_func_en_a;
2805   lsm6dsrx_emb_func_en_b_t                 emb_func_en_b;
2806   lsm6dsrx_page_address_t                  page_address;
2807   lsm6dsrx_page_value_t                    page_value;
2808   lsm6dsrx_emb_func_int1_t                 emb_func_int1;
2809   lsm6dsrx_fsm_int1_a_t                    fsm_int1_a;
2810   lsm6dsrx_fsm_int1_b_t                    fsm_int1_b;
2811   lsm6dsrx_mlc_int1_t                      mlc_int1;
2812   lsm6dsrx_emb_func_int2_t                 emb_func_int2;
2813   lsm6dsrx_fsm_int2_a_t                    fsm_int2_a;
2814   lsm6dsrx_fsm_int2_b_t                    fsm_int2_b;
2815   lsm6dsrx_mlc_int2_t                      mlc_int2;
2816   lsm6dsrx_emb_func_status_t               emb_func_status;
2817   lsm6dsrx_fsm_status_a_t                  fsm_status_a;
2818   lsm6dsrx_fsm_status_b_t                  fsm_status_b;
2819   lsm6dsrx_mlc_status_mainpage_t           mlc_status_mainpage;
2820   lsm6dsrx_emb_func_odr_cfg_c_t            emb_func_odr_cfg_c;
2821   lsm6dsrx_page_rw_t                       page_rw;
2822   lsm6dsrx_emb_func_fifo_cfg_t              emb_func_fifo_cfg;
2823   lsm6dsrx_fsm_enable_a_t                  fsm_enable_a;
2824   lsm6dsrx_fsm_enable_b_t                  fsm_enable_b;
2825   lsm6dsrx_fsm_long_counter_clear_t        fsm_long_counter_clear;
2826   lsm6dsrx_fsm_outs1_t                     fsm_outs1;
2827   lsm6dsrx_fsm_outs2_t                     fsm_outs2;
2828   lsm6dsrx_fsm_outs3_t                     fsm_outs3;
2829   lsm6dsrx_fsm_outs4_t                     fsm_outs4;
2830   lsm6dsrx_fsm_outs5_t                     fsm_outs5;
2831   lsm6dsrx_fsm_outs6_t                     fsm_outs6;
2832   lsm6dsrx_fsm_outs7_t                     fsm_outs7;
2833   lsm6dsrx_fsm_outs8_t                     fsm_outs8;
2834   lsm6dsrx_fsm_outs9_t                     fsm_outs9;
2835   lsm6dsrx_fsm_outs10_t                    fsm_outs10;
2836   lsm6dsrx_fsm_outs11_t                    fsm_outs11;
2837   lsm6dsrx_fsm_outs12_t                    fsm_outs12;
2838   lsm6dsrx_fsm_outs13_t                    fsm_outs13;
2839   lsm6dsrx_fsm_outs14_t                    fsm_outs14;
2840   lsm6dsrx_fsm_outs15_t                    fsm_outs15;
2841   lsm6dsrx_fsm_outs16_t                    fsm_outs16;
2842   lsm6dsrx_emb_func_odr_cfg_b_t            emb_func_odr_cfg_b;
2843   lsm6dsrx_emb_func_src_t                  emb_func_src;
2844   lsm6dsrx_emb_func_init_a_t               emb_func_init_a;
2845   lsm6dsrx_emb_func_init_b_t               emb_func_init_b;
2846   lsm6dsrx_mag_cfg_a_t                     mag_cfg_a;
2847   lsm6dsrx_mag_cfg_b_t                     mag_cfg_b;
2848   lsm6dsrx_pedo_cmd_reg_t                  pedo_cmd_reg;
2849   lsm6dsrx_sensor_hub_1_t                  sensor_hub_1;
2850   lsm6dsrx_sensor_hub_2_t                  sensor_hub_2;
2851   lsm6dsrx_sensor_hub_3_t                  sensor_hub_3;
2852   lsm6dsrx_sensor_hub_4_t                  sensor_hub_4;
2853   lsm6dsrx_sensor_hub_5_t                  sensor_hub_5;
2854   lsm6dsrx_sensor_hub_6_t                  sensor_hub_6;
2855   lsm6dsrx_sensor_hub_7_t                  sensor_hub_7;
2856   lsm6dsrx_sensor_hub_8_t                  sensor_hub_8;
2857   lsm6dsrx_sensor_hub_9_t                  sensor_hub_9;
2858   lsm6dsrx_sensor_hub_10_t                 sensor_hub_10;
2859   lsm6dsrx_sensor_hub_11_t                 sensor_hub_11;
2860   lsm6dsrx_sensor_hub_12_t                 sensor_hub_12;
2861   lsm6dsrx_sensor_hub_13_t                 sensor_hub_13;
2862   lsm6dsrx_sensor_hub_14_t                 sensor_hub_14;
2863   lsm6dsrx_sensor_hub_15_t                 sensor_hub_15;
2864   lsm6dsrx_sensor_hub_16_t                 sensor_hub_16;
2865   lsm6dsrx_sensor_hub_17_t                 sensor_hub_17;
2866   lsm6dsrx_sensor_hub_18_t                 sensor_hub_18;
2867   lsm6dsrx_master_config_t                 master_config;
2868   lsm6dsrx_slv0_add_t                      slv0_add;
2869   lsm6dsrx_slv0_subadd_t                   slv0_subadd;
2870   lsm6dsrx_slv0_config_t                   slv0_config;
2871   lsm6dsrx_slv1_add_t                      slv1_add;
2872   lsm6dsrx_slv1_subadd_t                   slv1_subadd;
2873   lsm6dsrx_slv1_config_t                   slv1_config;
2874   lsm6dsrx_slv2_add_t                      slv2_add;
2875   lsm6dsrx_slv2_subadd_t                   slv2_subadd;
2876   lsm6dsrx_slv2_config_t                   slv2_config;
2877   lsm6dsrx_slv3_add_t                      slv3_add;
2878   lsm6dsrx_slv3_subadd_t                   slv3_subadd;
2879   lsm6dsrx_slv3_config_t                   slv3_config;
2880   lsm6dsrx_datawrite_slv0_t                datawrite_slv0;
2881   lsm6dsrx_status_master_t                 status_master;
2882   bitwise_t                               bitwise;
2883   uint8_t                                 byte;
2884 } lsm6dsrx_reg_t;
2885 
2886 /**
2887   * @}
2888   *
2889   */
2890 
2891 #ifndef __weak
2892 #define __weak __attribute__((weak))
2893 #endif /* __weak */
2894 
2895 /*
2896  * These are the basic platform dependent I/O routines to read
2897  * and write device registers connected on a standard bus.
2898  * The driver keeps offering a default implementation based on function
2899  * pointers to read/write routines for backward compatibility.
2900  * The __weak directive allows the final application to overwrite
2901  * them with a custom implementation.
2902  */
2903 
2904 int32_t lsm6dsrx_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
2905                           uint8_t *data,
2906                           uint16_t len);
2907 int32_t lsm6dsrx_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
2908                            uint8_t *data,
2909                            uint16_t len);
2910 
2911 float_t lsm6dsrx_from_fs2g_to_mg(int16_t lsb);
2912 float_t lsm6dsrx_from_fs4g_to_mg(int16_t lsb);
2913 float_t lsm6dsrx_from_fs8g_to_mg(int16_t lsb);
2914 float_t lsm6dsrx_from_fs16g_to_mg(int16_t lsb);
2915 
2916 float_t lsm6dsrx_from_fs125dps_to_mdps(int16_t lsb);
2917 float_t lsm6dsrx_from_fs250dps_to_mdps(int16_t lsb);
2918 float_t lsm6dsrx_from_fs500dps_to_mdps(int16_t lsb);
2919 float_t lsm6dsrx_from_fs1000dps_to_mdps(int16_t lsb);
2920 float_t lsm6dsrx_from_fs2000dps_to_mdps(int16_t lsb);
2921 float_t lsm6dsrx_from_fs4000dps_to_mdps(int16_t lsb);
2922 
2923 float_t lsm6dsrx_from_lsb_to_celsius(int16_t lsb);
2924 
2925 float_t lsm6dsrx_from_lsb_to_nsec(int32_t lsb);
2926 
2927 typedef enum
2928 {
2929   LSM6DSRX_2g   = 0,
2930   LSM6DSRX_16g  = 1, /* if XL_FS_MODE = '1' -> LSM6DSRX_2g */
2931   LSM6DSRX_4g   = 2,
2932   LSM6DSRX_8g   = 3,
2933 } lsm6dsrx_fs_xl_t;
2934 int32_t lsm6dsrx_xl_full_scale_set(stmdev_ctx_t *ctx,
2935                                    lsm6dsrx_fs_xl_t val);
2936 int32_t lsm6dsrx_xl_full_scale_get(stmdev_ctx_t *ctx,
2937                                    lsm6dsrx_fs_xl_t *val);
2938 
2939 typedef enum
2940 {
2941   LSM6DSRX_XL_ODR_OFF    = 0,
2942   LSM6DSRX_XL_ODR_12Hz5  = 1,
2943   LSM6DSRX_XL_ODR_26Hz   = 2,
2944   LSM6DSRX_XL_ODR_52Hz   = 3,
2945   LSM6DSRX_XL_ODR_104Hz  = 4,
2946   LSM6DSRX_XL_ODR_208Hz  = 5,
2947   LSM6DSRX_XL_ODR_416Hz  = 6,
2948   LSM6DSRX_XL_ODR_833Hz  = 7,
2949   LSM6DSRX_XL_ODR_1666Hz = 8,
2950   LSM6DSRX_XL_ODR_3332Hz = 9,
2951   LSM6DSRX_XL_ODR_6667Hz = 10,
2952   LSM6DSRX_XL_ODR_1Hz6   = 11, /* (low power only) */
2953 } lsm6dsrx_odr_xl_t;
2954 int32_t lsm6dsrx_xl_data_rate_set(stmdev_ctx_t *ctx,
2955                                   lsm6dsrx_odr_xl_t val);
2956 int32_t lsm6dsrx_xl_data_rate_get(stmdev_ctx_t *ctx,
2957                                   lsm6dsrx_odr_xl_t *val);
2958 
2959 typedef enum
2960 {
2961   LSM6DSRX_125dps = 2,
2962   LSM6DSRX_250dps = 0,
2963   LSM6DSRX_500dps = 4,
2964   LSM6DSRX_1000dps = 8,
2965   LSM6DSRX_2000dps = 12,
2966   LSM6DSRX_4000dps = 1,
2967 } lsm6dsrx_fs_g_t;
2968 int32_t lsm6dsrx_gy_full_scale_set(stmdev_ctx_t *ctx,
2969                                    lsm6dsrx_fs_g_t val);
2970 int32_t lsm6dsrx_gy_full_scale_get(stmdev_ctx_t *ctx,
2971                                    lsm6dsrx_fs_g_t *val);
2972 
2973 typedef enum
2974 {
2975   LSM6DSRX_GY_ODR_OFF    = 0,
2976   LSM6DSRX_GY_ODR_12Hz5  = 1,
2977   LSM6DSRX_GY_ODR_26Hz   = 2,
2978   LSM6DSRX_GY_ODR_52Hz   = 3,
2979   LSM6DSRX_GY_ODR_104Hz  = 4,
2980   LSM6DSRX_GY_ODR_208Hz  = 5,
2981   LSM6DSRX_GY_ODR_416Hz  = 6,
2982   LSM6DSRX_GY_ODR_833Hz  = 7,
2983   LSM6DSRX_GY_ODR_1666Hz = 8,
2984   LSM6DSRX_GY_ODR_3332Hz = 9,
2985   LSM6DSRX_GY_ODR_6667Hz = 10,
2986 } lsm6dsrx_odr_g_t;
2987 int32_t lsm6dsrx_gy_data_rate_set(stmdev_ctx_t *ctx,
2988                                   lsm6dsrx_odr_g_t val);
2989 int32_t lsm6dsrx_gy_data_rate_get(stmdev_ctx_t *ctx,
2990                                   lsm6dsrx_odr_g_t *val);
2991 
2992 int32_t lsm6dsrx_block_data_update_set(stmdev_ctx_t *ctx,
2993                                        uint8_t val);
2994 int32_t lsm6dsrx_block_data_update_get(stmdev_ctx_t *ctx,
2995                                        uint8_t *val);
2996 
2997 typedef enum
2998 {
2999   LSM6DSRX_LSb_1mg  = 0,
3000   LSM6DSRX_LSb_16mg = 1,
3001 } lsm6dsrx_usr_off_w_t;
3002 int32_t lsm6dsrx_xl_offset_weight_set(stmdev_ctx_t *ctx,
3003                                       lsm6dsrx_usr_off_w_t val);
3004 int32_t lsm6dsrx_xl_offset_weight_get(stmdev_ctx_t *ctx,
3005                                       lsm6dsrx_usr_off_w_t *val);
3006 
3007 typedef enum
3008 {
3009   LSM6DSRX_HIGH_PERFORMANCE_MD  = 0,
3010   LSM6DSRX_LOW_NORMAL_POWER_MD  = 1,
3011 } lsm6dsrx_xl_hm_mode_t;
3012 int32_t lsm6dsrx_xl_power_mode_set(stmdev_ctx_t *ctx,
3013                                    lsm6dsrx_xl_hm_mode_t val);
3014 int32_t lsm6dsrx_xl_power_mode_get(stmdev_ctx_t *ctx,
3015                                    lsm6dsrx_xl_hm_mode_t *val);
3016 
3017 typedef enum
3018 {
3019   LSM6DSRX_GY_HIGH_PERFORMANCE  = 0,
3020   LSM6DSRX_GY_NORMAL            = 1,
3021 } lsm6dsrx_g_hm_mode_t;
3022 int32_t lsm6dsrx_gy_power_mode_set(stmdev_ctx_t *ctx,
3023                                    lsm6dsrx_g_hm_mode_t val);
3024 int32_t lsm6dsrx_gy_power_mode_get(stmdev_ctx_t *ctx,
3025                                    lsm6dsrx_g_hm_mode_t *val);
3026 
3027 typedef struct
3028 {
3029   lsm6dsrx_all_int_src_t           all_int_src;
3030   lsm6dsrx_wake_up_src_t           wake_up_src;
3031   lsm6dsrx_tap_src_t               tap_src;
3032   lsm6dsrx_d6d_src_t               d6d_src;
3033   lsm6dsrx_status_reg_t            status_reg;
3034   lsm6dsrx_emb_func_status_t       emb_func_status;
3035   lsm6dsrx_fsm_status_a_t          fsm_status_a;
3036   lsm6dsrx_fsm_status_b_t          fsm_status_b;
3037   lsm6dsrx_mlc_status_mainpage_t   mlc_status;
3038 } lsm6dsrx_all_sources_t;
3039 int32_t lsm6dsrx_all_sources_get(stmdev_ctx_t *ctx,
3040                                  lsm6dsrx_all_sources_t *val);
3041 
3042 int32_t lsm6dsrx_status_reg_get(stmdev_ctx_t *ctx,
3043                                 lsm6dsrx_status_reg_t *val);
3044 
3045 int32_t lsm6dsrx_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
3046                                         uint8_t *val);
3047 
3048 int32_t lsm6dsrx_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
3049                                         uint8_t *val);
3050 
3051 int32_t lsm6dsrx_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
3052                                           uint8_t *val);
3053 
3054 int32_t lsm6dsrx_xl_usr_offset_x_set(stmdev_ctx_t *ctx,
3055                                      uint8_t *buff);
3056 int32_t lsm6dsrx_xl_usr_offset_x_get(stmdev_ctx_t *ctx,
3057                                      uint8_t *buff);
3058 
3059 int32_t lsm6dsrx_xl_usr_offset_y_set(stmdev_ctx_t *ctx,
3060                                      uint8_t *buff);
3061 int32_t lsm6dsrx_xl_usr_offset_y_get(stmdev_ctx_t *ctx,
3062                                      uint8_t *buff);
3063 
3064 int32_t lsm6dsrx_xl_usr_offset_z_set(stmdev_ctx_t *ctx,
3065                                      uint8_t *buff);
3066 int32_t lsm6dsrx_xl_usr_offset_z_get(stmdev_ctx_t *ctx,
3067                                      uint8_t *buff);
3068 
3069 int32_t lsm6dsrx_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val);
3070 int32_t lsm6dsrx_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val);
3071 
3072 int32_t lsm6dsrx_timestamp_rst(stmdev_ctx_t *ctx);
3073 
3074 int32_t lsm6dsrx_timestamp_set(stmdev_ctx_t *ctx, uint8_t val);
3075 int32_t lsm6dsrx_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val);
3076 
3077 int32_t lsm6dsrx_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val);
3078 
3079 typedef enum
3080 {
3081   LSM6DSRX_NO_ROUND      = 0,
3082   LSM6DSRX_ROUND_XL      = 1,
3083   LSM6DSRX_ROUND_GY      = 2,
3084   LSM6DSRX_ROUND_GY_XL   = 3,
3085 } lsm6dsrx_rounding_t;
3086 int32_t lsm6dsrx_rounding_mode_set(stmdev_ctx_t *ctx,
3087                                    lsm6dsrx_rounding_t val);
3088 int32_t lsm6dsrx_rounding_mode_get(stmdev_ctx_t *ctx,
3089                                    lsm6dsrx_rounding_t *val);
3090 
3091 int32_t lsm6dsrx_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val);
3092 
3093 int32_t lsm6dsrx_angular_rate_raw_get(stmdev_ctx_t *ctx,
3094                                       int16_t *val);
3095 
3096 int32_t lsm6dsrx_acceleration_raw_get(stmdev_ctx_t *ctx,
3097                                       int16_t *val);
3098 
3099 int32_t lsm6dsrx_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *val);
3100 
3101 int32_t lsm6dsrx_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val);
3102 int32_t lsm6dsrx_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val);
3103 
3104 int32_t lsm6dsrx_number_of_steps_get(stmdev_ctx_t *ctx,
3105                                      uint16_t *val);
3106 
3107 int32_t lsm6dsrx_steps_reset(stmdev_ctx_t *ctx);
3108 
3109 typedef enum
3110 {
3111   LSM6DSRX_USER_BANK           = 0,
3112   LSM6DSRX_SENSOR_HUB_BANK     = 1,
3113   LSM6DSRX_EMBEDDED_FUNC_BANK  = 2,
3114 } lsm6dsrx_reg_access_t;
3115 int32_t lsm6dsrx_mem_bank_set(stmdev_ctx_t *ctx,
3116                               lsm6dsrx_reg_access_t val);
3117 int32_t lsm6dsrx_mem_bank_get(stmdev_ctx_t *ctx,
3118                               lsm6dsrx_reg_access_t *val);
3119 
3120 int32_t lsm6dsrx_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
3121                                   uint8_t *val);
3122 int32_t lsm6dsrx_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
3123                              uint8_t *buf, uint8_t len);
3124 int32_t lsm6dsrx_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
3125                                  uint8_t *val);
3126 int32_t lsm6dsrx_ln_pg_read(stmdev_ctx_t *ctx, uint16_t address,
3127                             uint8_t *val);
3128 
3129 typedef enum
3130 {
3131   LSM6DSRX_DRDY_LATCHED = 0,
3132   LSM6DSRX_DRDY_PULSED  = 1,
3133 } lsm6dsrx_dataready_pulsed_t;
3134 int32_t lsm6dsrx_data_ready_mode_set(stmdev_ctx_t *ctx,
3135                                      lsm6dsrx_dataready_pulsed_t val);
3136 int32_t lsm6dsrx_data_ready_mode_get(stmdev_ctx_t *ctx,
3137                                      lsm6dsrx_dataready_pulsed_t *val);
3138 
3139 int32_t lsm6dsrx_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff);
3140 
3141 int32_t lsm6dsrx_reset_set(stmdev_ctx_t *ctx, uint8_t val);
3142 int32_t lsm6dsrx_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
3143 
3144 int32_t lsm6dsrx_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val);
3145 int32_t lsm6dsrx_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val);
3146 
3147 int32_t lsm6dsrx_boot_set(stmdev_ctx_t *ctx, uint8_t val);
3148 int32_t lsm6dsrx_boot_get(stmdev_ctx_t *ctx, uint8_t *val);
3149 
3150 typedef enum
3151 {
3152   LSM6DSRX_XL_ST_DISABLE  = 0,
3153   LSM6DSRX_XL_ST_POSITIVE = 1,
3154   LSM6DSRX_XL_ST_NEGATIVE = 2,
3155 } lsm6dsrx_st_xl_t;
3156 int32_t lsm6dsrx_xl_self_test_set(stmdev_ctx_t *ctx,
3157                                   lsm6dsrx_st_xl_t val);
3158 int32_t lsm6dsrx_xl_self_test_get(stmdev_ctx_t *ctx,
3159                                   lsm6dsrx_st_xl_t *val);
3160 
3161 typedef enum
3162 {
3163   LSM6DSRX_GY_ST_DISABLE  = 0,
3164   LSM6DSRX_GY_ST_POSITIVE = 1,
3165   LSM6DSRX_GY_ST_NEGATIVE = 3,
3166 } lsm6dsrx_st_g_t;
3167 int32_t lsm6dsrx_gy_self_test_set(stmdev_ctx_t *ctx,
3168                                   lsm6dsrx_st_g_t val);
3169 int32_t lsm6dsrx_gy_self_test_get(stmdev_ctx_t *ctx,
3170                                   lsm6dsrx_st_g_t *val);
3171 
3172 int32_t lsm6dsrx_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val);
3173 int32_t lsm6dsrx_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val);
3174 
3175 int32_t lsm6dsrx_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val);
3176 int32_t lsm6dsrx_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val);
3177 
3178 int32_t lsm6dsrx_filter_settling_mask_set(stmdev_ctx_t *ctx,
3179                                           uint8_t val);
3180 int32_t lsm6dsrx_filter_settling_mask_get(stmdev_ctx_t *ctx,
3181                                           uint8_t *val);
3182 
3183 typedef enum
3184 {
3185   LSM6DSRX_ULTRA_LIGHT  = 0,
3186   LSM6DSRX_VERY_LIGHT   = 1,
3187   LSM6DSRX_LIGHT        = 2,
3188   LSM6DSRX_MEDIUM       = 3,
3189   LSM6DSRX_STRONG       = 4,
3190   LSM6DSRX_VERY_STRONG  = 5,
3191   LSM6DSRX_AGGRESSIVE   = 6,
3192   LSM6DSRX_XTREME       = 7,
3193 } lsm6dsrx_ftype_t;
3194 int32_t lsm6dsrx_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
3195                                       lsm6dsrx_ftype_t val);
3196 int32_t lsm6dsrx_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
3197                                       lsm6dsrx_ftype_t *val);
3198 
3199 int32_t lsm6dsrx_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val);
3200 int32_t lsm6dsrx_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val);
3201 
3202 typedef enum
3203 {
3204   LSM6DSRX_HP_PATH_DISABLE_ON_OUT    = 0x00,
3205   LSM6DSRX_SLOPE_ODR_DIV_4           = 0x10,
3206   LSM6DSRX_HP_ODR_DIV_10             = 0x11,
3207   LSM6DSRX_HP_ODR_DIV_20             = 0x12,
3208   LSM6DSRX_HP_ODR_DIV_45             = 0x13,
3209   LSM6DSRX_HP_ODR_DIV_100            = 0x14,
3210   LSM6DSRX_HP_ODR_DIV_200            = 0x15,
3211   LSM6DSRX_HP_ODR_DIV_400            = 0x16,
3212   LSM6DSRX_HP_ODR_DIV_800            = 0x17,
3213   LSM6DSRX_HP_REF_MD_ODR_DIV_10      = 0x31,
3214   LSM6DSRX_HP_REF_MD_ODR_DIV_20      = 0x32,
3215   LSM6DSRX_HP_REF_MD_ODR_DIV_45      = 0x33,
3216   LSM6DSRX_HP_REF_MD_ODR_DIV_100     = 0x34,
3217   LSM6DSRX_HP_REF_MD_ODR_DIV_200     = 0x35,
3218   LSM6DSRX_HP_REF_MD_ODR_DIV_400     = 0x36,
3219   LSM6DSRX_HP_REF_MD_ODR_DIV_800     = 0x37,
3220   LSM6DSRX_LP_ODR_DIV_10             = 0x01,
3221   LSM6DSRX_LP_ODR_DIV_20             = 0x02,
3222   LSM6DSRX_LP_ODR_DIV_45             = 0x03,
3223   LSM6DSRX_LP_ODR_DIV_100            = 0x04,
3224   LSM6DSRX_LP_ODR_DIV_200            = 0x05,
3225   LSM6DSRX_LP_ODR_DIV_400            = 0x06,
3226   LSM6DSRX_LP_ODR_DIV_800            = 0x07,
3227 } lsm6dsrx_hp_slope_xl_en_t;
3228 int32_t lsm6dsrx_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
3229                                        lsm6dsrx_hp_slope_xl_en_t val);
3230 int32_t lsm6dsrx_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
3231                                        lsm6dsrx_hp_slope_xl_en_t *val);
3232 
3233 int32_t lsm6dsrx_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val);
3234 int32_t lsm6dsrx_xl_fast_settling_get(stmdev_ctx_t *ctx,
3235                                       uint8_t *val);
3236 
3237 typedef enum
3238 {
3239   LSM6DSRX_USE_SLOPE = 0,
3240   LSM6DSRX_USE_HPF   = 1,
3241 } lsm6dsrx_slope_fds_t;
3242 int32_t lsm6dsrx_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
3243                                          lsm6dsrx_slope_fds_t val);
3244 int32_t lsm6dsrx_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
3245                                          lsm6dsrx_slope_fds_t *val);
3246 
3247 typedef enum
3248 {
3249   LSM6DSRX_HP_FILTER_NONE     = 0x00,
3250   LSM6DSRX_HP_FILTER_16mHz    = 0x80,
3251   LSM6DSRX_HP_FILTER_65mHz    = 0x81,
3252   LSM6DSRX_HP_FILTER_260mHz   = 0x82,
3253   LSM6DSRX_HP_FILTER_1Hz04    = 0x83,
3254 } lsm6dsrx_hpm_g_t;
3255 int32_t lsm6dsrx_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
3256                                          lsm6dsrx_hpm_g_t val);
3257 int32_t lsm6dsrx_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
3258                                          lsm6dsrx_hpm_g_t *val);
3259 
3260 typedef enum
3261 {
3262   LSM6DSRX_AUX_PULL_UP_DISC       = 0,
3263   LSM6DSRX_AUX_PULL_UP_CONNECT    = 1,
3264 } lsm6dsrx_ois_pu_dis_t;
3265 int32_t lsm6dsrx_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
3266                                       lsm6dsrx_ois_pu_dis_t val);
3267 int32_t lsm6dsrx_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
3268                                       lsm6dsrx_ois_pu_dis_t *val);
3269 
3270 typedef enum
3271 {
3272   LSM6DSRX_AUX_ON                    = 1,
3273   LSM6DSRX_AUX_ON_BY_AUX_INTERFACE   = 0,
3274 } lsm6dsrx_ois_on_t;
3275 int32_t lsm6dsrx_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
3276                                     lsm6dsrx_ois_on_t val);
3277 int32_t lsm6dsrx_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
3278                                     lsm6dsrx_ois_on_t *val);
3279 
3280 int32_t lsm6dsrx_aux_status_reg_get(stmdev_ctx_t *ctx,
3281                                     lsm6dsrx_status_spiaux_t *val);
3282 
3283 int32_t lsm6dsrx_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
3284                                             uint8_t *val);
3285 
3286 int32_t lsm6dsrx_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
3287                                             uint8_t *val);
3288 
3289 int32_t lsm6dsrx_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
3290                                           uint8_t *val);
3291 
3292 typedef enum
3293 {
3294   LSM6DSRX_AUX_XL_DISABLE = 0,
3295   LSM6DSRX_AUX_XL_POS     = 1,
3296   LSM6DSRX_AUX_XL_NEG     = 2,
3297 } lsm6dsrx_st_xl_ois_t;
3298 int32_t lsm6dsrx_aux_xl_self_test_set(stmdev_ctx_t *ctx,
3299                                       lsm6dsrx_st_xl_ois_t val);
3300 int32_t lsm6dsrx_aux_xl_self_test_get(stmdev_ctx_t *ctx,
3301                                       lsm6dsrx_st_xl_ois_t *val);
3302 
3303 typedef enum
3304 {
3305   LSM6DSRX_AUX_DEN_ACTIVE_LOW     = 0,
3306   LSM6DSRX_AUX_DEN_ACTIVE_HIGH    = 1,
3307 } lsm6dsrx_den_lh_ois_t;
3308 int32_t lsm6dsrx_aux_den_polarity_set(stmdev_ctx_t *ctx,
3309                                       lsm6dsrx_den_lh_ois_t val);
3310 int32_t lsm6dsrx_aux_den_polarity_get(stmdev_ctx_t *ctx,
3311                                       lsm6dsrx_den_lh_ois_t *val);
3312 
3313 typedef enum
3314 {
3315   LSM6DSRX_AUX_DEN_DISABLE         = 0,
3316   LSM6DSRX_AUX_DEN_LEVEL_LATCH     = 3,
3317   LSM6DSRX_AUX_DEN_LEVEL_TRIG      = 2,
3318 } lsm6dsrx_lvl2_ois_t;
3319 int32_t lsm6dsrx_aux_den_mode_set(stmdev_ctx_t *ctx,
3320                                   lsm6dsrx_lvl2_ois_t val);
3321 int32_t lsm6dsrx_aux_den_mode_get(stmdev_ctx_t *ctx,
3322                                   lsm6dsrx_lvl2_ois_t *val);
3323 
3324 int32_t lsm6dsrx_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val);
3325 int32_t lsm6dsrx_aux_drdy_on_int2_get(stmdev_ctx_t *ctx,
3326                                       uint8_t *val);
3327 
3328 typedef enum
3329 {
3330   LSM6DSRX_AUX_DISABLE  = 0,
3331   LSM6DSRX_MODE_3_GY    = 1,
3332   LSM6DSRX_MODE_4_GY_XL = 3,
3333 } lsm6dsrx_ois_en_spi2_t;
3334 int32_t lsm6dsrx_aux_mode_set(stmdev_ctx_t *ctx,
3335                               lsm6dsrx_ois_en_spi2_t val);
3336 int32_t lsm6dsrx_aux_mode_get(stmdev_ctx_t *ctx,
3337                               lsm6dsrx_ois_en_spi2_t *val);
3338 
3339 typedef enum
3340 {
3341   LSM6DSRX_125dps_AUX  =  0x04,
3342   LSM6DSRX_250dps_AUX  =  0x00,
3343   LSM6DSRX_500dps_AUX  =  0x01,
3344   LSM6DSRX_1000dps_AUX =  0x02,
3345   LSM6DSRX_2000dps_AUX =  0x03,
3346 } lsm6dsrx_fs_g_ois_t;
3347 int32_t lsm6dsrx_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
3348                                        lsm6dsrx_fs_g_ois_t val);
3349 int32_t lsm6dsrx_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
3350                                        lsm6dsrx_fs_g_ois_t *val);
3351 
3352 typedef enum
3353 {
3354   LSM6DSRX_AUX_SPI_4_WIRE = 0,
3355   LSM6DSRX_AUX_SPI_3_WIRE = 1,
3356 } lsm6dsrx_sim_ois_t;
3357 int32_t lsm6dsrx_aux_spi_mode_set(stmdev_ctx_t *ctx,
3358                                   lsm6dsrx_sim_ois_t val);
3359 int32_t lsm6dsrx_aux_spi_mode_get(stmdev_ctx_t *ctx,
3360                                   lsm6dsrx_sim_ois_t *val);
3361 
3362 typedef enum
3363 {
3364   LSM6DSRX_351Hz39 = 0,
3365   LSM6DSRX_236Hz63 = 1,
3366   LSM6DSRX_172Hz70 = 2,
3367   LSM6DSRX_937Hz91 = 3,
3368 } lsm6dsrx_ftype_ois_t;
3369 int32_t lsm6dsrx_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
3370                                           lsm6dsrx_ftype_ois_t val);
3371 int32_t lsm6dsrx_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
3372                                           lsm6dsrx_ftype_ois_t *val);
3373 
3374 typedef enum
3375 {
3376   LSM6DSRX_AUX_HP_DISABLE = 0x00,
3377   LSM6DSRX_AUX_HP_Hz016   = 0x10,
3378   LSM6DSRX_AUX_HP_Hz065   = 0x11,
3379   LSM6DSRX_AUX_HP_Hz260   = 0x12,
3380   LSM6DSRX_AUX_HP_1Hz040  = 0x13,
3381 } lsm6dsrx_hpm_ois_t;
3382 int32_t lsm6dsrx_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
3383                                          lsm6dsrx_hpm_ois_t val);
3384 int32_t lsm6dsrx_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
3385                                          lsm6dsrx_hpm_ois_t *val);
3386 
3387 typedef enum
3388 {
3389   LSM6DSRX_ENABLE_CLAMP  = 0,
3390   LSM6DSRX_DISABLE_CLAMP = 1,
3391 } lsm6dsrx_st_ois_clampdis_t;
3392 int32_t lsm6dsrx_aux_gy_clamp_set(stmdev_ctx_t *ctx,
3393                                   lsm6dsrx_st_ois_clampdis_t val);
3394 int32_t lsm6dsrx_aux_gy_clamp_get(stmdev_ctx_t *ctx,
3395                                   lsm6dsrx_st_ois_clampdis_t *val);
3396 
3397 typedef enum
3398 {
3399   LSM6DSRX_AUX_GY_DISABLE = 0,
3400   LSM6DSRX_AUX_GY_POS     = 1,
3401   LSM6DSRX_AUX_GY_NEG     = 3,
3402 } lsm6dsrx_st_ois_t;
3403 int32_t lsm6dsrx_aux_gy_self_test_set(stmdev_ctx_t *ctx,
3404                                       lsm6dsrx_st_ois_t val);
3405 int32_t lsm6dsrx_aux_gy_self_test_get(stmdev_ctx_t *ctx,
3406                                       lsm6dsrx_st_ois_t *val);
3407 
3408 typedef enum
3409 {
3410   LSM6DSRX_631Hz = 0,
3411   LSM6DSRX_295Hz = 1,
3412   LSM6DSRX_140Hz = 2,
3413   LSM6DSRX_68Hz2 = 3,
3414   LSM6DSRX_33Hz6 = 4,
3415   LSM6DSRX_16Hz7 = 5,
3416   LSM6DSRX_8Hz3  = 6,
3417   LSM6DSRX_4Hz11 = 7,
3418 } lsm6dsrx_filter_xl_conf_ois_t;
3419 int32_t lsm6dsrx_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
3420                                       lsm6dsrx_filter_xl_conf_ois_t val);
3421 int32_t lsm6dsrx_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
3422                                       lsm6dsrx_filter_xl_conf_ois_t *val);
3423 
3424 typedef enum
3425 {
3426   LSM6DSRX_AUX_2g  = 0,
3427   LSM6DSRX_AUX_16g = 1,
3428   LSM6DSRX_AUX_4g  = 2,
3429   LSM6DSRX_AUX_8g  = 3,
3430 } lsm6dsrx_fs_xl_ois_t;
3431 int32_t lsm6dsrx_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
3432                                        lsm6dsrx_fs_xl_ois_t val);
3433 int32_t lsm6dsrx_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
3434                                        lsm6dsrx_fs_xl_ois_t *val);
3435 
3436 typedef enum
3437 {
3438   LSM6DSRX_PULL_UP_DISC       = 0,
3439   LSM6DSRX_PULL_UP_CONNECT    = 1,
3440 } lsm6dsrx_sdo_pu_en_t;
3441 int32_t lsm6dsrx_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
3442                                   lsm6dsrx_sdo_pu_en_t val);
3443 int32_t lsm6dsrx_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
3444                                   lsm6dsrx_sdo_pu_en_t *val);
3445 
3446 typedef enum
3447 {
3448   LSM6DSRX_PULL_DOWN_CONNECT       = 0,
3449   LSM6DSRX_PULL_DOWN_DISC          = 1,
3450 } lsm6dsrx_pd_dis_int1_t;
3451 int32_t lsm6dsrx_int1_mode_set(stmdev_ctx_t *ctx,
3452                                lsm6dsrx_pd_dis_int1_t val);
3453 int32_t lsm6dsrx_int1_mode_get(stmdev_ctx_t *ctx,
3454                                lsm6dsrx_pd_dis_int1_t *val);
3455 
3456 typedef enum
3457 {
3458   LSM6DSRX_SPI_4_WIRE = 0,
3459   LSM6DSRX_SPI_3_WIRE = 1,
3460 } lsm6dsrx_sim_t;
3461 int32_t lsm6dsrx_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsrx_sim_t val);
3462 int32_t lsm6dsrx_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsrx_sim_t *val);
3463 
3464 typedef enum
3465 {
3466   LSM6DSRX_I2C_ENABLE  = 0,
3467   LSM6DSRX_I2C_DISABLE = 1,
3468 } lsm6dsrx_i2c_disable_t;
3469 int32_t lsm6dsrx_i2c_interface_set(stmdev_ctx_t *ctx,
3470                                    lsm6dsrx_i2c_disable_t val);
3471 int32_t lsm6dsrx_i2c_interface_get(stmdev_ctx_t *ctx,
3472                                    lsm6dsrx_i2c_disable_t *val);
3473 
3474 typedef enum
3475 {
3476   LSM6DSRX_I3C_DISABLE         = 0x80,
3477   LSM6DSRX_I3C_ENABLE_T_50us   = 0x00,
3478   LSM6DSRX_I3C_ENABLE_T_2us    = 0x01,
3479   LSM6DSRX_I3C_ENABLE_T_1ms    = 0x02,
3480   LSM6DSRX_I3C_ENABLE_T_25ms   = 0x03,
3481 } lsm6dsrx_i3c_disable_t;
3482 int32_t lsm6dsrx_i3c_disable_set(stmdev_ctx_t *ctx,
3483                                  lsm6dsrx_i3c_disable_t val);
3484 int32_t lsm6dsrx_i3c_disable_get(stmdev_ctx_t *ctx,
3485                                  lsm6dsrx_i3c_disable_t *val);
3486 
3487 typedef struct
3488 {
3489   lsm6dsrx_int1_ctrl_t          int1_ctrl;
3490   lsm6dsrx_md1_cfg_t            md1_cfg;
3491   lsm6dsrx_emb_func_int1_t      emb_func_int1;
3492   lsm6dsrx_fsm_int1_a_t         fsm_int1_a;
3493   lsm6dsrx_fsm_int1_b_t         fsm_int1_b;
3494   lsm6dsrx_mlc_int1_t           mlc_int1;
3495 } lsm6dsrx_pin_int1_route_t;
3496 int32_t lsm6dsrx_pin_int1_route_set(stmdev_ctx_t *ctx,
3497                                     lsm6dsrx_pin_int1_route_t *val);
3498 int32_t lsm6dsrx_pin_int1_route_get(stmdev_ctx_t *ctx,
3499                                     lsm6dsrx_pin_int1_route_t *val);
3500 
3501 typedef struct
3502 {
3503   lsm6dsrx_int2_ctrl_t          int2_ctrl;
3504   lsm6dsrx_md2_cfg_t            md2_cfg;
3505   lsm6dsrx_emb_func_int2_t      emb_func_int2;
3506   lsm6dsrx_fsm_int2_a_t         fsm_int2_a;
3507   lsm6dsrx_fsm_int2_b_t         fsm_int2_b;
3508   lsm6dsrx_mlc_int2_t           mlc_int2;
3509 } lsm6dsrx_pin_int2_route_t;
3510 int32_t lsm6dsrx_pin_int2_route_set(stmdev_ctx_t *ctx,
3511                                     lsm6dsrx_pin_int2_route_t *val);
3512 int32_t lsm6dsrx_pin_int2_route_get(stmdev_ctx_t *ctx,
3513                                     lsm6dsrx_pin_int2_route_t *val);
3514 
3515 typedef enum
3516 {
3517   LSM6DSRX_PUSH_PULL   = 0,
3518   LSM6DSRX_OPEN_DRAIN  = 1,
3519 } lsm6dsrx_pp_od_t;
3520 int32_t lsm6dsrx_pin_mode_set(stmdev_ctx_t *ctx,
3521                               lsm6dsrx_pp_od_t val);
3522 int32_t lsm6dsrx_pin_mode_get(stmdev_ctx_t *ctx,
3523                               lsm6dsrx_pp_od_t *val);
3524 
3525 typedef enum
3526 {
3527   LSM6DSRX_ACTIVE_HIGH = 0,
3528   LSM6DSRX_ACTIVE_LOW  = 1,
3529 } lsm6dsrx_h_lactive_t;
3530 int32_t lsm6dsrx_pin_polarity_set(stmdev_ctx_t *ctx,
3531                                   lsm6dsrx_h_lactive_t val);
3532 int32_t lsm6dsrx_pin_polarity_get(stmdev_ctx_t *ctx,
3533                                   lsm6dsrx_h_lactive_t *val);
3534 
3535 int32_t lsm6dsrx_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val);
3536 int32_t lsm6dsrx_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val);
3537 
3538 typedef enum
3539 {
3540   LSM6DSRX_ALL_INT_PULSED            = 0,
3541   LSM6DSRX_BASE_LATCHED_EMB_PULSED   = 1,
3542   LSM6DSRX_BASE_PULSED_EMB_LATCHED   = 2,
3543   LSM6DSRX_ALL_INT_LATCHED           = 3,
3544 } lsm6dsrx_lir_t;
3545 int32_t lsm6dsrx_int_notification_set(stmdev_ctx_t *ctx,
3546                                       lsm6dsrx_lir_t val);
3547 int32_t lsm6dsrx_int_notification_get(stmdev_ctx_t *ctx,
3548                                       lsm6dsrx_lir_t *val);
3549 
3550 typedef enum
3551 {
3552   LSM6DSRX_LSb_FS_DIV_64       = 0,
3553   LSM6DSRX_LSb_FS_DIV_256      = 1,
3554 } lsm6dsrx_wake_ths_w_t;
3555 int32_t lsm6dsrx_wkup_ths_weight_set(stmdev_ctx_t *ctx,
3556                                      lsm6dsrx_wake_ths_w_t val);
3557 int32_t lsm6dsrx_wkup_ths_weight_get(stmdev_ctx_t *ctx,
3558                                      lsm6dsrx_wake_ths_w_t *val);
3559 
3560 int32_t lsm6dsrx_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val);
3561 int32_t lsm6dsrx_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val);
3562 
3563 int32_t lsm6dsrx_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
3564                                            uint8_t val);
3565 int32_t lsm6dsrx_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
3566                                            uint8_t *val);
3567 
3568 int32_t lsm6dsrx_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val);
3569 int32_t lsm6dsrx_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
3570 
3571 int32_t lsm6dsrx_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val);
3572 int32_t lsm6dsrx_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
3573 
3574 typedef enum
3575 {
3576   LSM6DSRX_DRIVE_SLEEP_CHG_EVENT = 0,
3577   LSM6DSRX_DRIVE_SLEEP_STATUS    = 1,
3578 } lsm6dsrx_sleep_status_on_int_t;
3579 int32_t lsm6dsrx_act_pin_notification_set(stmdev_ctx_t *ctx,
3580                                           lsm6dsrx_sleep_status_on_int_t val);
3581 int32_t lsm6dsrx_act_pin_notification_get(stmdev_ctx_t *ctx,
3582                                           lsm6dsrx_sleep_status_on_int_t *val);
3583 
3584 typedef enum
3585 {
3586   LSM6DSRX_XL_AND_GY_NOT_AFFECTED      = 0,
3587   LSM6DSRX_XL_12Hz5_GY_NOT_AFFECTED    = 1,
3588   LSM6DSRX_XL_12Hz5_GY_SLEEP           = 2,
3589   LSM6DSRX_XL_12Hz5_GY_PD              = 3,
3590 } lsm6dsrx_inact_en_t;
3591 int32_t lsm6dsrx_act_mode_set(stmdev_ctx_t *ctx,
3592                               lsm6dsrx_inact_en_t val);
3593 int32_t lsm6dsrx_act_mode_get(stmdev_ctx_t *ctx,
3594                               lsm6dsrx_inact_en_t *val);
3595 
3596 int32_t lsm6dsrx_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val);
3597 int32_t lsm6dsrx_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
3598 
3599 int32_t lsm6dsrx_tap_detection_on_z_set(stmdev_ctx_t *ctx,
3600                                         uint8_t val);
3601 int32_t lsm6dsrx_tap_detection_on_z_get(stmdev_ctx_t *ctx,
3602                                         uint8_t *val);
3603 
3604 int32_t lsm6dsrx_tap_detection_on_y_set(stmdev_ctx_t *ctx,
3605                                         uint8_t val);
3606 int32_t lsm6dsrx_tap_detection_on_y_get(stmdev_ctx_t *ctx,
3607                                         uint8_t *val);
3608 
3609 int32_t lsm6dsrx_tap_detection_on_x_set(stmdev_ctx_t *ctx,
3610                                         uint8_t val);
3611 int32_t lsm6dsrx_tap_detection_on_x_get(stmdev_ctx_t *ctx,
3612                                         uint8_t *val);
3613 
3614 int32_t lsm6dsrx_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val);
3615 int32_t lsm6dsrx_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val);
3616 
3617 typedef enum
3618 {
3619   LSM6DSRX_XYZ = 0,
3620   LSM6DSRX_YXZ = 1,
3621   LSM6DSRX_XZY = 2,
3622   LSM6DSRX_ZYX = 3,
3623   LSM6DSRX_YZX = 5,
3624   LSM6DSRX_ZXY = 6,
3625 } lsm6dsrx_tap_priority_t;
3626 int32_t lsm6dsrx_tap_axis_priority_set(stmdev_ctx_t *ctx,
3627                                        lsm6dsrx_tap_priority_t val);
3628 int32_t lsm6dsrx_tap_axis_priority_get(stmdev_ctx_t *ctx,
3629                                        lsm6dsrx_tap_priority_t *val);
3630 
3631 int32_t lsm6dsrx_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val);
3632 int32_t lsm6dsrx_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val);
3633 
3634 int32_t lsm6dsrx_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val);
3635 int32_t lsm6dsrx_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val);
3636 
3637 int32_t lsm6dsrx_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val);
3638 int32_t lsm6dsrx_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val);
3639 
3640 int32_t lsm6dsrx_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val);
3641 int32_t lsm6dsrx_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val);
3642 
3643 int32_t lsm6dsrx_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val);
3644 int32_t lsm6dsrx_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
3645 
3646 typedef enum
3647 {
3648   LSM6DSRX_ONLY_SINGLE        = 0,
3649   LSM6DSRX_BOTH_SINGLE_DOUBLE = 1,
3650 } lsm6dsrx_single_double_tap_t;
3651 int32_t lsm6dsrx_tap_mode_set(stmdev_ctx_t *ctx,
3652                               lsm6dsrx_single_double_tap_t val);
3653 int32_t lsm6dsrx_tap_mode_get(stmdev_ctx_t *ctx,
3654                               lsm6dsrx_single_double_tap_t *val);
3655 
3656 typedef enum
3657 {
3658   LSM6DSRX_DEG_80  = 0,
3659   LSM6DSRX_DEG_70  = 1,
3660   LSM6DSRX_DEG_60  = 2,
3661   LSM6DSRX_DEG_50  = 3,
3662 } lsm6dsrx_sixd_ths_t;
3663 int32_t lsm6dsrx_6d_threshold_set(stmdev_ctx_t *ctx,
3664                                   lsm6dsrx_sixd_ths_t val);
3665 int32_t lsm6dsrx_6d_threshold_get(stmdev_ctx_t *ctx,
3666                                   lsm6dsrx_sixd_ths_t *val);
3667 
3668 int32_t lsm6dsrx_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val);
3669 int32_t lsm6dsrx_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val);
3670 
3671 typedef enum
3672 {
3673   LSM6DSRX_FF_TSH_156mg = 0,
3674   LSM6DSRX_FF_TSH_219mg = 1,
3675   LSM6DSRX_FF_TSH_250mg = 2,
3676   LSM6DSRX_FF_TSH_312mg = 3,
3677   LSM6DSRX_FF_TSH_344mg = 4,
3678   LSM6DSRX_FF_TSH_406mg = 5,
3679   LSM6DSRX_FF_TSH_469mg = 6,
3680   LSM6DSRX_FF_TSH_500mg = 7,
3681 } lsm6dsrx_ff_ths_t;
3682 int32_t lsm6dsrx_ff_threshold_set(stmdev_ctx_t *ctx,
3683                                   lsm6dsrx_ff_ths_t val);
3684 int32_t lsm6dsrx_ff_threshold_get(stmdev_ctx_t *ctx,
3685                                   lsm6dsrx_ff_ths_t *val);
3686 
3687 int32_t lsm6dsrx_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val);
3688 int32_t lsm6dsrx_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val);
3689 
3690 int32_t lsm6dsrx_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val);
3691 int32_t lsm6dsrx_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val);
3692 
3693 int32_t lsm6dsrx_compression_algo_init_set(stmdev_ctx_t *ctx,
3694                                            uint8_t val);
3695 int32_t lsm6dsrx_compression_algo_init_get(stmdev_ctx_t *ctx,
3696                                            uint8_t *val);
3697 
3698 typedef enum
3699 {
3700   LSM6DSRX_CMP_DISABLE  = 0x00,
3701   LSM6DSRX_CMP_ALWAYS   = 0x04,
3702   LSM6DSRX_CMP_8_TO_1   = 0x05,
3703   LSM6DSRX_CMP_16_TO_1  = 0x06,
3704   LSM6DSRX_CMP_32_TO_1  = 0x07,
3705 } lsm6dsrx_uncoptr_rate_t;
3706 int32_t lsm6dsrx_compression_algo_set(stmdev_ctx_t *ctx,
3707                                       lsm6dsrx_uncoptr_rate_t val);
3708 int32_t lsm6dsrx_compression_algo_get(stmdev_ctx_t *ctx,
3709                                       lsm6dsrx_uncoptr_rate_t *val);
3710 
3711 int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
3712                                                uint8_t val);
3713 int32_t lsm6dsrx_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
3714                                                uint8_t *val);
3715 
3716 int32_t lsm6dsrx_compression_algo_real_time_set(stmdev_ctx_t *ctx,
3717                                                 uint8_t val);
3718 int32_t lsm6dsrx_compression_algo_real_time_get(stmdev_ctx_t *ctx,
3719                                                 uint8_t *val);
3720 
3721 int32_t lsm6dsrx_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val);
3722 int32_t lsm6dsrx_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
3723                                       uint8_t *val);
3724 
3725 typedef enum
3726 {
3727   LSM6DSRX_XL_NOT_BATCHED       =  0,
3728   LSM6DSRX_XL_BATCHED_AT_12Hz5   =  1,
3729   LSM6DSRX_XL_BATCHED_AT_26Hz    =  2,
3730   LSM6DSRX_XL_BATCHED_AT_52Hz    =  3,
3731   LSM6DSRX_XL_BATCHED_AT_104Hz   =  4,
3732   LSM6DSRX_XL_BATCHED_AT_208Hz   =  5,
3733   LSM6DSRX_XL_BATCHED_AT_417Hz   =  6,
3734   LSM6DSRX_XL_BATCHED_AT_833Hz   =  7,
3735   LSM6DSRX_XL_BATCHED_AT_1667Hz  =  8,
3736   LSM6DSRX_XL_BATCHED_AT_3333Hz  =  9,
3737   LSM6DSRX_XL_BATCHED_AT_6667Hz  = 10,
3738   LSM6DSRX_XL_BATCHED_AT_6Hz5    = 11,
3739 } lsm6dsrx_bdr_xl_t;
3740 int32_t lsm6dsrx_fifo_xl_batch_set(stmdev_ctx_t *ctx,
3741                                    lsm6dsrx_bdr_xl_t val);
3742 int32_t lsm6dsrx_fifo_xl_batch_get(stmdev_ctx_t *ctx,
3743                                    lsm6dsrx_bdr_xl_t *val);
3744 
3745 typedef enum
3746 {
3747   LSM6DSRX_GY_NOT_BATCHED         = 0,
3748   LSM6DSRX_GY_BATCHED_AT_12Hz5    = 1,
3749   LSM6DSRX_GY_BATCHED_AT_26Hz     = 2,
3750   LSM6DSRX_GY_BATCHED_AT_52Hz     = 3,
3751   LSM6DSRX_GY_BATCHED_AT_104Hz    = 4,
3752   LSM6DSRX_GY_BATCHED_AT_208Hz    = 5,
3753   LSM6DSRX_GY_BATCHED_AT_417Hz    = 6,
3754   LSM6DSRX_GY_BATCHED_AT_833Hz    = 7,
3755   LSM6DSRX_GY_BATCHED_AT_1667Hz   = 8,
3756   LSM6DSRX_GY_BATCHED_AT_3333Hz   = 9,
3757   LSM6DSRX_GY_BATCHED_AT_6667Hz   = 10,
3758   LSM6DSRX_GY_BATCHED_6Hz5        = 11,
3759 } lsm6dsrx_bdr_gy_t;
3760 int32_t lsm6dsrx_fifo_gy_batch_set(stmdev_ctx_t *ctx,
3761                                    lsm6dsrx_bdr_gy_t val);
3762 int32_t lsm6dsrx_fifo_gy_batch_get(stmdev_ctx_t *ctx,
3763                                    lsm6dsrx_bdr_gy_t *val);
3764 
3765 typedef enum
3766 {
3767   LSM6DSRX_BYPASS_MODE             = 0,
3768   LSM6DSRX_FIFO_MODE               = 1,
3769   LSM6DSRX_STREAM_TO_FIFO_MODE     = 3,
3770   LSM6DSRX_BYPASS_TO_STREAM_MODE   = 4,
3771   LSM6DSRX_STREAM_MODE             = 6,
3772   LSM6DSRX_BYPASS_TO_FIFO_MODE     = 7,
3773 } lsm6dsrx_fifo_mode_t;
3774 int32_t lsm6dsrx_fifo_mode_set(stmdev_ctx_t *ctx,
3775                                lsm6dsrx_fifo_mode_t val);
3776 int32_t lsm6dsrx_fifo_mode_get(stmdev_ctx_t *ctx,
3777                                lsm6dsrx_fifo_mode_t *val);
3778 
3779 typedef enum
3780 {
3781   LSM6DSRX_TEMP_NOT_BATCHED        = 0,
3782   LSM6DSRX_TEMP_BATCHED_AT_52Hz    = 1,
3783   LSM6DSRX_TEMP_BATCHED_AT_12Hz5   = 2,
3784   LSM6DSRX_TEMP_BATCHED_AT_1Hz6    = 3,
3785 } lsm6dsrx_odr_t_batch_t;
3786 int32_t lsm6dsrx_fifo_temp_batch_set(stmdev_ctx_t *ctx,
3787                                      lsm6dsrx_odr_t_batch_t val);
3788 int32_t lsm6dsrx_fifo_temp_batch_get(stmdev_ctx_t *ctx,
3789                                      lsm6dsrx_odr_t_batch_t *val);
3790 
3791 typedef enum
3792 {
3793   LSM6DSRX_NO_DECIMATION = 0,
3794   LSM6DSRX_DEC_1         = 1,
3795   LSM6DSRX_DEC_8         = 2,
3796   LSM6DSRX_DEC_32        = 3,
3797 } lsm6dsrx_odr_ts_batch_t;
3798 int32_t lsm6dsrx_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
3799                                                lsm6dsrx_odr_ts_batch_t val);
3800 int32_t lsm6dsrx_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
3801                                                lsm6dsrx_odr_ts_batch_t *val);
3802 
3803 typedef enum
3804 {
3805   LSM6DSRX_XL_BATCH_EVENT   = 0,
3806   LSM6DSRX_GYRO_BATCH_EVENT = 1,
3807 } lsm6dsrx_trig_counter_bdr_t;
3808 int32_t lsm6dsrx_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
3809                                           lsm6dsrx_trig_counter_bdr_t val);
3810 int32_t lsm6dsrx_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
3811                                           lsm6dsrx_trig_counter_bdr_t *val);
3812 
3813 int32_t lsm6dsrx_rst_batch_counter_set(stmdev_ctx_t *ctx,
3814                                        uint8_t val);
3815 int32_t lsm6dsrx_rst_batch_counter_get(stmdev_ctx_t *ctx,
3816                                        uint8_t *val);
3817 
3818 int32_t lsm6dsrx_batch_counter_threshold_set(stmdev_ctx_t *ctx,
3819                                              uint16_t val);
3820 int32_t lsm6dsrx_batch_counter_threshold_get(stmdev_ctx_t *ctx,
3821                                              uint16_t *val);
3822 
3823 int32_t lsm6dsrx_fifo_data_level_get(stmdev_ctx_t *ctx,
3824                                      uint16_t *val);
3825 
3826 int32_t lsm6dsrx_fifo_status_get(stmdev_ctx_t *ctx,
3827                                  lsm6dsrx_fifo_status2_t *val);
3828 
3829 int32_t lsm6dsrx_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
3830 
3831 int32_t lsm6dsrx_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
3832 
3833 int32_t lsm6dsrx_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val);
3834 
3835 typedef enum
3836 {
3837   LSM6DSRX_GYRO_NC_TAG    = 1,
3838   LSM6DSRX_XL_NC_TAG,
3839   LSM6DSRX_TEMPERATURE_TAG,
3840   LSM6DSRX_TIMESTAMP_TAG,
3841   LSM6DSRX_CFG_CHANGE_TAG,
3842   LSM6DSRX_XL_NC_T_2_TAG,
3843   LSM6DSRX_XL_NC_T_1_TAG,
3844   LSM6DSRX_XL_2XC_TAG,
3845   LSM6DSRX_XL_3XC_TAG,
3846   LSM6DSRX_GYRO_NC_T_2_TAG,
3847   LSM6DSRX_GYRO_NC_T_1_TAG,
3848   LSM6DSRX_GYRO_2XC_TAG,
3849   LSM6DSRX_GYRO_3XC_TAG,
3850   LSM6DSRX_SENSORHUB_SLAVE0_TAG,
3851   LSM6DSRX_SENSORHUB_SLAVE1_TAG,
3852   LSM6DSRX_SENSORHUB_SLAVE2_TAG,
3853   LSM6DSRX_SENSORHUB_SLAVE3_TAG,
3854   LSM6DSRX_STEP_CPUNTER_TAG,
3855   LSM6DSRX_GAME_ROTATION_TAG,
3856   LSM6DSRX_GEOMAG_ROTATION_TAG,
3857   LSM6DSRX_ROTATION_TAG,
3858   LSM6DSRX_SENSORHUB_NACK_TAG  = 0x19,
3859 } lsm6dsrx_fifo_tag_t;
3860 int32_t lsm6dsrx_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
3861                                      lsm6dsrx_fifo_tag_t *val);
3862 
3863 int32_t lsm6dsrx_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val);
3864 int32_t lsm6dsrx_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val);
3865 
3866 int32_t lsm6dsrx_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val);
3867 int32_t lsm6dsrx_sh_batch_slave_0_get(stmdev_ctx_t *ctx,
3868                                       uint8_t *val);
3869 
3870 int32_t lsm6dsrx_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val);
3871 int32_t lsm6dsrx_sh_batch_slave_1_get(stmdev_ctx_t *ctx,
3872                                       uint8_t *val);
3873 
3874 int32_t lsm6dsrx_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val);
3875 int32_t lsm6dsrx_sh_batch_slave_2_get(stmdev_ctx_t *ctx,
3876                                       uint8_t *val);
3877 
3878 int32_t lsm6dsrx_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val);
3879 int32_t lsm6dsrx_sh_batch_slave_3_get(stmdev_ctx_t *ctx,
3880                                       uint8_t *val);
3881 
3882 typedef enum
3883 {
3884   LSM6DSRX_DEN_DISABLE    = 0,
3885   LSM6DSRX_LEVEL_FIFO     = 6,
3886   LSM6DSRX_LEVEL_LETCHED  = 3,
3887   LSM6DSRX_LEVEL_TRIGGER  = 2,
3888   LSM6DSRX_EDGE_TRIGGER   = 4,
3889 } lsm6dsrx_den_mode_t;
3890 int32_t lsm6dsrx_den_mode_set(stmdev_ctx_t *ctx,
3891                               lsm6dsrx_den_mode_t val);
3892 int32_t lsm6dsrx_den_mode_get(stmdev_ctx_t *ctx,
3893                               lsm6dsrx_den_mode_t *val);
3894 
3895 typedef enum
3896 {
3897   LSM6DSRX_DEN_ACT_LOW  = 0,
3898   LSM6DSRX_DEN_ACT_HIGH = 1,
3899 } lsm6dsrx_den_lh_t;
3900 int32_t lsm6dsrx_den_polarity_set(stmdev_ctx_t *ctx,
3901                                   lsm6dsrx_den_lh_t val);
3902 int32_t lsm6dsrx_den_polarity_get(stmdev_ctx_t *ctx,
3903                                   lsm6dsrx_den_lh_t *val);
3904 
3905 typedef enum
3906 {
3907   LSM6DSRX_STAMP_IN_GY_DATA     = 0,
3908   LSM6DSRX_STAMP_IN_XL_DATA     = 1,
3909   LSM6DSRX_STAMP_IN_GY_XL_DATA  = 2,
3910 } lsm6dsrx_den_xl_g_t;
3911 int32_t lsm6dsrx_den_enable_set(stmdev_ctx_t *ctx,
3912                                 lsm6dsrx_den_xl_g_t val);
3913 int32_t lsm6dsrx_den_enable_get(stmdev_ctx_t *ctx,
3914                                 lsm6dsrx_den_xl_g_t *val);
3915 
3916 int32_t lsm6dsrx_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val);
3917 int32_t lsm6dsrx_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val);
3918 
3919 int32_t lsm6dsrx_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val);
3920 int32_t lsm6dsrx_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val);
3921 
3922 int32_t lsm6dsrx_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val);
3923 int32_t lsm6dsrx_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val);
3924 
3925 int32_t lsm6dsrx_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val);
3926 int32_t lsm6dsrx_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
3927 
3928 int32_t lsm6dsrx_pedo_step_detect_get(stmdev_ctx_t *ctx,
3929                                       uint8_t *val);
3930 
3931 int32_t lsm6dsrx_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
3932                                          uint8_t *buff);
3933 int32_t lsm6dsrx_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
3934                                          uint8_t *buff);
3935 
3936 int32_t lsm6dsrx_pedo_steps_period_set(stmdev_ctx_t *ctx,
3937                                        uint16_t val);
3938 int32_t lsm6dsrx_pedo_steps_period_get(stmdev_ctx_t *ctx,
3939                                        uint16_t *val);
3940 
3941 typedef enum
3942 {
3943   LSM6DSRX_EVERY_STEP     = 0,
3944   LSM6DSRX_COUNT_OVERFLOW = 1,
3945 } lsm6dsrx_carry_count_en_t;
3946 int32_t lsm6dsrx_pedo_int_mode_set(stmdev_ctx_t *ctx,
3947                                    lsm6dsrx_carry_count_en_t val);
3948 int32_t lsm6dsrx_pedo_int_mode_get(stmdev_ctx_t *ctx,
3949                                    lsm6dsrx_carry_count_en_t *val);
3950 
3951 int32_t lsm6dsrx_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val);
3952 int32_t lsm6dsrx_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
3953 
3954 int32_t lsm6dsrx_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
3955                                             uint8_t *val);
3956 
3957 int32_t lsm6dsrx_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val);
3958 int32_t lsm6dsrx_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val);
3959 
3960 int32_t lsm6dsrx_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
3961                                           uint8_t *val);
3962 
3963 int32_t lsm6dsrx_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val);
3964 int32_t lsm6dsrx_mag_sensitivity_get(stmdev_ctx_t *ctx,
3965                                      uint16_t *val);
3966 
3967 int32_t lsm6dsrx_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val);
3968 int32_t lsm6dsrx_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val);
3969 
3970 int32_t lsm6dsrx_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val);
3971 int32_t lsm6dsrx_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val);
3972 
3973 typedef enum
3974 {
3975   LSM6DSRX_Z_EQ_Y     = 0,
3976   LSM6DSRX_Z_EQ_MIN_Y = 1,
3977   LSM6DSRX_Z_EQ_X     = 2,
3978   LSM6DSRX_Z_EQ_MIN_X = 3,
3979   LSM6DSRX_Z_EQ_MIN_Z = 4,
3980   LSM6DSRX_Z_EQ_Z     = 5,
3981 } lsm6dsrx_mag_z_axis_t;
3982 int32_t lsm6dsrx_mag_z_orient_set(stmdev_ctx_t *ctx,
3983                                   lsm6dsrx_mag_z_axis_t val);
3984 int32_t lsm6dsrx_mag_z_orient_get(stmdev_ctx_t *ctx,
3985                                   lsm6dsrx_mag_z_axis_t *val);
3986 
3987 typedef enum
3988 {
3989   LSM6DSRX_Y_EQ_Y     = 0,
3990   LSM6DSRX_Y_EQ_MIN_Y = 1,
3991   LSM6DSRX_Y_EQ_X     = 2,
3992   LSM6DSRX_Y_EQ_MIN_X = 3,
3993   LSM6DSRX_Y_EQ_MIN_Z = 4,
3994   LSM6DSRX_Y_EQ_Z     = 5,
3995 } lsm6dsrx_mag_y_axis_t;
3996 int32_t lsm6dsrx_mag_y_orient_set(stmdev_ctx_t *ctx,
3997                                   lsm6dsrx_mag_y_axis_t val);
3998 int32_t lsm6dsrx_mag_y_orient_get(stmdev_ctx_t *ctx,
3999                                   lsm6dsrx_mag_y_axis_t *val);
4000 
4001 typedef enum
4002 {
4003   LSM6DSRX_X_EQ_Y     = 0,
4004   LSM6DSRX_X_EQ_MIN_Y = 1,
4005   LSM6DSRX_X_EQ_X     = 2,
4006   LSM6DSRX_X_EQ_MIN_X = 3,
4007   LSM6DSRX_X_EQ_MIN_Z = 4,
4008   LSM6DSRX_X_EQ_Z     = 5,
4009 } lsm6dsrx_mag_x_axis_t;
4010 int32_t lsm6dsrx_mag_x_orient_set(stmdev_ctx_t *ctx,
4011                                   lsm6dsrx_mag_x_axis_t val);
4012 int32_t lsm6dsrx_mag_x_orient_get(stmdev_ctx_t *ctx,
4013                                   lsm6dsrx_mag_x_axis_t *val);
4014 
4015 int32_t lsm6dsrx_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
4016                                               uint8_t *val);
4017 
4018 int32_t lsm6dsrx_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val);
4019 int32_t lsm6dsrx_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val);
4020 
4021 typedef struct
4022 {
4023   lsm6dsrx_fsm_enable_a_t          fsm_enable_a;
4024   lsm6dsrx_fsm_enable_b_t          fsm_enable_b;
4025 } lsm6dsrx_emb_fsm_enable_t;
4026 int32_t lsm6dsrx_fsm_enable_set(stmdev_ctx_t *ctx,
4027                                 lsm6dsrx_emb_fsm_enable_t *val);
4028 int32_t lsm6dsrx_fsm_enable_get(stmdev_ctx_t *ctx,
4029                                 lsm6dsrx_emb_fsm_enable_t *val);
4030 
4031 int32_t lsm6dsrx_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val);
4032 int32_t lsm6dsrx_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val);
4033 
4034 typedef enum
4035 {
4036   LSM6DSRX_LC_NORMAL     = 0,
4037   LSM6DSRX_LC_CLEAR      = 1,
4038   LSM6DSRX_LC_CLEAR_DONE = 2,
4039 } lsm6dsrx_fsm_lc_clr_t;
4040 int32_t lsm6dsrx_long_clr_set(stmdev_ctx_t *ctx,
4041                               lsm6dsrx_fsm_lc_clr_t val);
4042 int32_t lsm6dsrx_long_clr_get(stmdev_ctx_t *ctx,
4043                               lsm6dsrx_fsm_lc_clr_t *val);
4044 
4045 typedef struct
4046 {
4047   lsm6dsrx_fsm_outs1_t    fsm_outs1;
4048   lsm6dsrx_fsm_outs2_t    fsm_outs2;
4049   lsm6dsrx_fsm_outs3_t    fsm_outs3;
4050   lsm6dsrx_fsm_outs4_t    fsm_outs4;
4051   lsm6dsrx_fsm_outs5_t    fsm_outs5;
4052   lsm6dsrx_fsm_outs6_t    fsm_outs6;
4053   lsm6dsrx_fsm_outs7_t    fsm_outs7;
4054   lsm6dsrx_fsm_outs8_t    fsm_outs8;
4055   lsm6dsrx_fsm_outs9_t    fsm_outs9;
4056   lsm6dsrx_fsm_outs10_t    fsm_outs10;
4057   lsm6dsrx_fsm_outs11_t    fsm_outs11;
4058   lsm6dsrx_fsm_outs12_t    fsm_outs12;
4059   lsm6dsrx_fsm_outs13_t    fsm_outs13;
4060   lsm6dsrx_fsm_outs14_t    fsm_outs14;
4061   lsm6dsrx_fsm_outs15_t    fsm_outs15;
4062   lsm6dsrx_fsm_outs16_t    fsm_outs16;
4063 } lsm6dsrx_fsm_out_t;
4064 int32_t lsm6dsrx_fsm_out_get(stmdev_ctx_t *ctx,
4065                              lsm6dsrx_fsm_out_t *val);
4066 
4067 typedef enum
4068 {
4069   LSM6DSRX_ODR_FSM_12Hz5 = 0,
4070   LSM6DSRX_ODR_FSM_26Hz  = 1,
4071   LSM6DSRX_ODR_FSM_52Hz  = 2,
4072   LSM6DSRX_ODR_FSM_104Hz = 3,
4073 } lsm6dsrx_fsm_odr_t;
4074 int32_t lsm6dsrx_fsm_data_rate_set(stmdev_ctx_t *ctx,
4075                                    lsm6dsrx_fsm_odr_t val);
4076 int32_t lsm6dsrx_fsm_data_rate_get(stmdev_ctx_t *ctx,
4077                                    lsm6dsrx_fsm_odr_t *val);
4078 
4079 int32_t lsm6dsrx_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val);
4080 int32_t lsm6dsrx_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val);
4081 
4082 int32_t lsm6dsrx_long_cnt_int_value_set(stmdev_ctx_t *ctx,
4083                                         uint16_t val);
4084 int32_t lsm6dsrx_long_cnt_int_value_get(stmdev_ctx_t *ctx,
4085                                         uint16_t *val);
4086 
4087 int32_t lsm6dsrx_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
4088                                             uint8_t *buff);
4089 int32_t lsm6dsrx_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
4090                                             uint8_t *buff);
4091 
4092 int32_t lsm6dsrx_fsm_start_address_set(stmdev_ctx_t *ctx,
4093                                        uint16_t val);
4094 int32_t lsm6dsrx_fsm_start_address_get(stmdev_ctx_t *ctx,
4095                                        uint16_t *val);
4096 
4097 int32_t lsm6dsrx_mlc_set(stmdev_ctx_t *ctx, uint8_t val);
4098 int32_t lsm6dsrx_mlc_get(stmdev_ctx_t *ctx, uint8_t *val);
4099 
4100 int32_t lsm6dsrx_mlc_status_get(stmdev_ctx_t *ctx,
4101                                 lsm6dsrx_mlc_status_mainpage_t *val);
4102 
4103 typedef enum
4104 {
4105   LSM6DSRX_ODR_PRGS_12Hz5 = 0,
4106   LSM6DSRX_ODR_PRGS_26Hz  = 1,
4107   LSM6DSRX_ODR_PRGS_52Hz  = 2,
4108   LSM6DSRX_ODR_PRGS_104Hz = 3,
4109 } lsm6dsrx_mlc_odr_t;
4110 int32_t lsm6dsrx_mlc_data_rate_set(stmdev_ctx_t *ctx,
4111                                    lsm6dsrx_mlc_odr_t val);
4112 int32_t lsm6dsrx_mlc_data_rate_get(stmdev_ctx_t *ctx,
4113                                    lsm6dsrx_mlc_odr_t *val);
4114 
4115 int32_t lsm6dsrx_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff);
4116 
4117 int32_t lsm6dsrx_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx,
4118                                          uint16_t val);
4119 int32_t lsm6dsrx_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx,
4120                                          uint16_t *val);
4121 
4122 typedef struct
4123 {
4124   lsm6dsrx_sensor_hub_1_t   sh_byte_1;
4125   lsm6dsrx_sensor_hub_2_t   sh_byte_2;
4126   lsm6dsrx_sensor_hub_3_t   sh_byte_3;
4127   lsm6dsrx_sensor_hub_4_t   sh_byte_4;
4128   lsm6dsrx_sensor_hub_5_t   sh_byte_5;
4129   lsm6dsrx_sensor_hub_6_t   sh_byte_6;
4130   lsm6dsrx_sensor_hub_7_t   sh_byte_7;
4131   lsm6dsrx_sensor_hub_8_t   sh_byte_8;
4132   lsm6dsrx_sensor_hub_9_t   sh_byte_9;
4133   lsm6dsrx_sensor_hub_10_t  sh_byte_10;
4134   lsm6dsrx_sensor_hub_11_t  sh_byte_11;
4135   lsm6dsrx_sensor_hub_12_t  sh_byte_12;
4136   lsm6dsrx_sensor_hub_13_t  sh_byte_13;
4137   lsm6dsrx_sensor_hub_14_t  sh_byte_14;
4138   lsm6dsrx_sensor_hub_15_t  sh_byte_15;
4139   lsm6dsrx_sensor_hub_16_t  sh_byte_16;
4140   lsm6dsrx_sensor_hub_17_t  sh_byte_17;
4141   lsm6dsrx_sensor_hub_18_t  sh_byte_18;
4142 } lsm6dsrx_emb_sh_read_t;
4143 int32_t lsm6dsrx_sh_read_data_raw_get(stmdev_ctx_t *ctx,
4144                                       lsm6dsrx_emb_sh_read_t *val);
4145 
4146 typedef enum
4147 {
4148   LSM6DSRX_SLV_0       = 0,
4149   LSM6DSRX_SLV_0_1     = 1,
4150   LSM6DSRX_SLV_0_1_2   = 2,
4151   LSM6DSRX_SLV_0_1_2_3 = 3,
4152 } lsm6dsrx_aux_sens_on_t;
4153 int32_t lsm6dsrx_sh_slave_connected_set(stmdev_ctx_t *ctx,
4154                                         lsm6dsrx_aux_sens_on_t val);
4155 int32_t lsm6dsrx_sh_slave_connected_get(stmdev_ctx_t *ctx,
4156                                         lsm6dsrx_aux_sens_on_t *val);
4157 
4158 int32_t lsm6dsrx_sh_master_set(stmdev_ctx_t *ctx, uint8_t val);
4159 int32_t lsm6dsrx_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val);
4160 
4161 typedef enum
4162 {
4163   LSM6DSRX_EXT_PULL_UP      = 0,
4164   LSM6DSRX_INTERNAL_PULL_UP = 1,
4165 } lsm6dsrx_shub_pu_en_t;
4166 int32_t lsm6dsrx_sh_pin_mode_set(stmdev_ctx_t *ctx,
4167                                  lsm6dsrx_shub_pu_en_t val);
4168 int32_t lsm6dsrx_sh_pin_mode_get(stmdev_ctx_t *ctx,
4169                                  lsm6dsrx_shub_pu_en_t *val);
4170 
4171 int32_t lsm6dsrx_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val);
4172 int32_t lsm6dsrx_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val);
4173 
4174 typedef enum
4175 {
4176   LSM6DSRX_EXT_ON_INT2_PIN = 1,
4177   LSM6DSRX_XL_GY_DRDY      = 0,
4178 } lsm6dsrx_start_config_t;
4179 int32_t lsm6dsrx_sh_syncro_mode_set(stmdev_ctx_t *ctx,
4180                                     lsm6dsrx_start_config_t val);
4181 int32_t lsm6dsrx_sh_syncro_mode_get(stmdev_ctx_t *ctx,
4182                                     lsm6dsrx_start_config_t *val);
4183 
4184 typedef enum
4185 {
4186   LSM6DSRX_EACH_SH_CYCLE    = 0,
4187   LSM6DSRX_ONLY_FIRST_CYCLE = 1,
4188 } lsm6dsrx_write_once_t;
4189 int32_t lsm6dsrx_sh_write_mode_set(stmdev_ctx_t *ctx,
4190                                    lsm6dsrx_write_once_t val);
4191 int32_t lsm6dsrx_sh_write_mode_get(stmdev_ctx_t *ctx,
4192                                    lsm6dsrx_write_once_t *val);
4193 
4194 int32_t lsm6dsrx_sh_reset_set(stmdev_ctx_t *ctx);
4195 int32_t lsm6dsrx_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val);
4196 
4197 typedef enum
4198 {
4199   LSM6DSRX_SH_ODR_104Hz = 0,
4200   LSM6DSRX_SH_ODR_52Hz  = 1,
4201   LSM6DSRX_SH_ODR_26Hz  = 2,
4202   LSM6DSRX_SH_ODR_13Hz  = 3,
4203 } lsm6dsrx_shub_odr_t;
4204 int32_t lsm6dsrx_sh_data_rate_set(stmdev_ctx_t *ctx,
4205                                   lsm6dsrx_shub_odr_t val);
4206 int32_t lsm6dsrx_sh_data_rate_get(stmdev_ctx_t *ctx,
4207                                   lsm6dsrx_shub_odr_t *val);
4208 
4209 typedef struct
4210 {
4211   uint8_t   slv0_add;
4212   uint8_t   slv0_subadd;
4213   uint8_t   slv0_data;
4214 } lsm6dsrx_sh_cfg_write_t;
4215 int32_t lsm6dsrx_sh_cfg_write(stmdev_ctx_t *ctx,
4216                               lsm6dsrx_sh_cfg_write_t *val);
4217 
4218 typedef struct
4219 {
4220   uint8_t   slv_add;
4221   uint8_t   slv_subadd;
4222   uint8_t   slv_len;
4223 } lsm6dsrx_sh_cfg_read_t;
4224 int32_t lsm6dsrx_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
4225                                   lsm6dsrx_sh_cfg_read_t *val);
4226 int32_t lsm6dsrx_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
4227                                   lsm6dsrx_sh_cfg_read_t *val);
4228 int32_t lsm6dsrx_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
4229                                   lsm6dsrx_sh_cfg_read_t *val);
4230 int32_t lsm6dsrx_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
4231                                   lsm6dsrx_sh_cfg_read_t *val);
4232 
4233 int32_t lsm6dsrx_sh_status_get(stmdev_ctx_t *ctx,
4234                                lsm6dsrx_status_master_t *val);
4235 
4236 typedef enum
4237 {
4238   LSM6DSRX_S4S_TPH_7bit   = 0,
4239   LSM6DSRX_S4S_TPH_15bit  = 1,
4240 } lsm6dsrx_s4s_tph_res_t;
4241 int32_t lsm6dsrx_s4s_tph_res_set(stmdev_ctx_t *ctx,
4242                                  lsm6dsrx_s4s_tph_res_t val);
4243 int32_t lsm6dsrx_s4s_tph_res_get(stmdev_ctx_t *ctx,
4244                                  lsm6dsrx_s4s_tph_res_t *val);
4245 
4246 int32_t lsm6dsrx_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val);
4247 int32_t lsm6dsrx_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val);
4248 
4249 typedef enum
4250 {
4251   LSM6DSRX_S4S_DT_RES_11 = 0,
4252   LSM6DSRX_S4S_DT_RES_12 = 1,
4253   LSM6DSRX_S4S_DT_RES_13 = 2,
4254   LSM6DSRX_S4S_DT_RES_14 = 3,
4255 } lsm6dsrx_s4s_res_ratio_t;
4256 int32_t lsm6dsrx_s4s_res_ratio_set(stmdev_ctx_t *ctx,
4257                                    lsm6dsrx_s4s_res_ratio_t val);
4258 int32_t lsm6dsrx_s4s_res_ratio_get(stmdev_ctx_t *ctx,
4259                                    lsm6dsrx_s4s_res_ratio_t *val);
4260 
4261 int32_t lsm6dsrx_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val);
4262 int32_t lsm6dsrx_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val);
4263 
4264 int32_t lsm6dsrx_s4s_dt_set(stmdev_ctx_t *ctx, uint8_t val);
4265 int32_t lsm6dsrx_s4s_dt_get(stmdev_ctx_t *ctx, uint8_t *val);
4266 
4267 /**
4268   *@}
4269   *
4270   */
4271 
4272 #ifdef __cplusplus
4273 }
4274 #endif
4275 
4276 #endif /* LSM6DSRX_REGS_H */
4277 
4278 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
4279