1 /**
2 ******************************************************************************
3 * @file lsm6dsr_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSR driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dsr_reg.h"
21
22 /**
23 * @defgroup LSM6DSR
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dsr enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LSM6DSR_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6dsr_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dsr_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 ret = ctx->read_reg(ctx->handle, reg, data, len);
56
57 return ret;
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx read / write interface definitions(ptr)
64 * @param reg register to write
65 * @param data pointer to data to write in register reg(ptr)
66 * @param len number of consecutive register to write
67 * @retval interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
lsm6dsr_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak lsm6dsr_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
71 uint8_t *data,
72 uint16_t len)
73 {
74 int32_t ret;
75
76 ret = ctx->write_reg(ctx->handle, reg, data, len);
77
78 return ret;
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup LSM6DSR_Sensitivity
88 * @brief These functions convert raw-data into engineering units.
89 * @{
90 *
91 */
92
lsm6dsr_from_fs2g_to_mg(int16_t lsb)93 float_t lsm6dsr_from_fs2g_to_mg(int16_t lsb)
94 {
95 return ((float_t)lsb * 0.061f);
96 }
97
lsm6dsr_from_fs4g_to_mg(int16_t lsb)98 float_t lsm6dsr_from_fs4g_to_mg(int16_t lsb)
99 {
100 return ((float_t)lsb * 0.122f);
101 }
102
lsm6dsr_from_fs8g_to_mg(int16_t lsb)103 float_t lsm6dsr_from_fs8g_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb * 0.244f);
106 }
107
lsm6dsr_from_fs16g_to_mg(int16_t lsb)108 float_t lsm6dsr_from_fs16g_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb * 0.488f);
111 }
112
lsm6dsr_from_fs125dps_to_mdps(int16_t lsb)113 float_t lsm6dsr_from_fs125dps_to_mdps(int16_t lsb)
114 {
115 return ((float_t)lsb * 4.375f);
116 }
117
lsm6dsr_from_fs250dps_to_mdps(int16_t lsb)118 float_t lsm6dsr_from_fs250dps_to_mdps(int16_t lsb)
119 {
120 return ((float_t)lsb * 8.75f);
121 }
122
lsm6dsr_from_fs500dps_to_mdps(int16_t lsb)123 float_t lsm6dsr_from_fs500dps_to_mdps(int16_t lsb)
124 {
125 return ((float_t)lsb * 17.50f);
126 }
127
lsm6dsr_from_fs1000dps_to_mdps(int16_t lsb)128 float_t lsm6dsr_from_fs1000dps_to_mdps(int16_t lsb)
129 {
130 return ((float_t)lsb * 35.0f);
131 }
132
lsm6dsr_from_fs2000dps_to_mdps(int16_t lsb)133 float_t lsm6dsr_from_fs2000dps_to_mdps(int16_t lsb)
134 {
135 return ((float_t)lsb * 70.0f);
136 }
137
lsm6dsr_from_fs4000dps_to_mdps(int16_t lsb)138 float_t lsm6dsr_from_fs4000dps_to_mdps(int16_t lsb)
139 {
140 return ((float_t)lsb * 140.0f);
141 }
142
lsm6dsr_from_lsb_to_celsius(int16_t lsb)143 float_t lsm6dsr_from_lsb_to_celsius(int16_t lsb)
144 {
145 return (((float_t)lsb / 256.0f) + 25.0f);
146 }
147
lsm6dsr_from_lsb_to_nsec(int32_t lsb)148 float_t lsm6dsr_from_lsb_to_nsec(int32_t lsb)
149 {
150 return ((float_t)lsb * 25000.0f);
151 }
152
153 /**
154 * @}
155 *
156 */
157
158 /**
159 * @defgroup LSM9DS1_Data_generation
160 * @brief This section groups all the functions concerning data
161 * generation
162 * @{
163 *
164 */
165
166 /**
167 * @brief Accelerometer full-scale selection[set]
168 *
169 * @param ctx Read / write interface definitions.(ptr)
170 * @param val Change the values of fs_xl in reg CTRL1_XL
171 * @retval Interface status (MANDATORY: return 0 -> no Error).
172 *
173 */
lsm6dsr_xl_full_scale_set(stmdev_ctx_t * ctx,lsm6dsr_fs_xl_t val)174 int32_t lsm6dsr_xl_full_scale_set(stmdev_ctx_t *ctx,
175 lsm6dsr_fs_xl_t val)
176 {
177 lsm6dsr_ctrl1_xl_t ctrl1_xl;
178 int32_t ret;
179
180 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
181
182 if (ret == 0)
183 {
184 ctrl1_xl.fs_xl = (uint8_t)val;
185 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_XL,
186 (uint8_t *)&ctrl1_xl, 1);
187 }
188
189 return ret;
190 }
191
192 /**
193 * @brief Accelerometer full-scale selection.[get]
194 *
195 * @param ctx Read / write interface definitions.(ptr)
196 * @param val Get the values of fs_xl in reg CTRL1_XL
197 * @retval Interface status (MANDATORY: return 0 -> no Error).
198 *
199 */
lsm6dsr_xl_full_scale_get(stmdev_ctx_t * ctx,lsm6dsr_fs_xl_t * val)200 int32_t lsm6dsr_xl_full_scale_get(stmdev_ctx_t *ctx,
201 lsm6dsr_fs_xl_t *val)
202 {
203 lsm6dsr_ctrl1_xl_t ctrl1_xl;
204 int32_t ret;
205
206 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
207
208 switch (ctrl1_xl.fs_xl)
209 {
210 case LSM6DSR_2g:
211 *val = LSM6DSR_2g;
212 break;
213
214 case LSM6DSR_16g:
215 *val = LSM6DSR_16g;
216 break;
217
218 case LSM6DSR_4g:
219 *val = LSM6DSR_4g;
220 break;
221
222 case LSM6DSR_8g:
223 *val = LSM6DSR_8g;
224 break;
225
226 default:
227 *val = LSM6DSR_2g;
228 break;
229 }
230
231 return ret;
232 }
233
234 /**
235 * @brief Accelerometer UI data rate selection.[set]
236 *
237 * @param ctx Read / write interface definitions.(ptr)
238 * @param val Change the values of odr_xl in reg CTRL1_XL
239 * @retval Interface status (MANDATORY: return 0 -> no Error).
240 *
241 */
lsm6dsr_xl_data_rate_set(stmdev_ctx_t * ctx,lsm6dsr_odr_xl_t val)242 int32_t lsm6dsr_xl_data_rate_set(stmdev_ctx_t *ctx,
243 lsm6dsr_odr_xl_t val)
244 {
245 lsm6dsr_odr_xl_t odr_xl = val;
246 lsm6dsr_emb_fsm_enable_t fsm_enable;
247 lsm6dsr_fsm_odr_t fsm_odr;
248 lsm6dsr_ctrl1_xl_t ctrl1_xl;
249 int32_t ret;
250
251 /* Check the Finite State Machine data rate constraints */
252 ret = lsm6dsr_fsm_enable_get(ctx, &fsm_enable);
253
254 if (ret == 0)
255 {
256 if ((fsm_enable.fsm_enable_a.fsm1_en |
257 fsm_enable.fsm_enable_a.fsm2_en |
258 fsm_enable.fsm_enable_a.fsm3_en |
259 fsm_enable.fsm_enable_a.fsm4_en |
260 fsm_enable.fsm_enable_a.fsm5_en |
261 fsm_enable.fsm_enable_a.fsm6_en |
262 fsm_enable.fsm_enable_a.fsm7_en |
263 fsm_enable.fsm_enable_a.fsm8_en |
264 fsm_enable.fsm_enable_b.fsm9_en |
265 fsm_enable.fsm_enable_b.fsm10_en |
266 fsm_enable.fsm_enable_b.fsm11_en |
267 fsm_enable.fsm_enable_b.fsm12_en |
268 fsm_enable.fsm_enable_b.fsm13_en |
269 fsm_enable.fsm_enable_b.fsm14_en |
270 fsm_enable.fsm_enable_b.fsm15_en |
271 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
272 {
273 ret = lsm6dsr_fsm_data_rate_get(ctx, &fsm_odr);
274
275 if (ret == 0)
276 {
277 switch (fsm_odr)
278 {
279 case LSM6DSR_ODR_FSM_12Hz5:
280 if (val == LSM6DSR_XL_ODR_OFF)
281 {
282 odr_xl = LSM6DSR_XL_ODR_12Hz5;
283 }
284
285 else
286 {
287 odr_xl = val;
288 }
289
290 break;
291
292 case LSM6DSR_ODR_FSM_26Hz:
293 if (val == LSM6DSR_XL_ODR_OFF)
294 {
295 odr_xl = LSM6DSR_XL_ODR_26Hz;
296 }
297
298 else if (val == LSM6DSR_XL_ODR_12Hz5)
299 {
300 odr_xl = LSM6DSR_XL_ODR_26Hz;
301 }
302
303 else
304 {
305 odr_xl = val;
306 }
307
308 break;
309
310 case LSM6DSR_ODR_FSM_52Hz:
311 if (val == LSM6DSR_XL_ODR_OFF)
312 {
313 odr_xl = LSM6DSR_XL_ODR_52Hz;
314 }
315
316 else if (val == LSM6DSR_XL_ODR_12Hz5)
317 {
318 odr_xl = LSM6DSR_XL_ODR_52Hz;
319 }
320
321 else if (val == LSM6DSR_XL_ODR_26Hz)
322 {
323 odr_xl = LSM6DSR_XL_ODR_52Hz;
324 }
325
326 else
327 {
328 odr_xl = val;
329 }
330
331 break;
332
333 case LSM6DSR_ODR_FSM_104Hz:
334 if (val == LSM6DSR_XL_ODR_OFF)
335 {
336 odr_xl = LSM6DSR_XL_ODR_104Hz;
337 }
338
339 else if (val == LSM6DSR_XL_ODR_12Hz5)
340 {
341 odr_xl = LSM6DSR_XL_ODR_104Hz;
342 }
343
344 else if (val == LSM6DSR_XL_ODR_26Hz)
345 {
346 odr_xl = LSM6DSR_XL_ODR_104Hz;
347 }
348
349 else if (val == LSM6DSR_XL_ODR_52Hz)
350 {
351 odr_xl = LSM6DSR_XL_ODR_104Hz;
352 }
353
354 else
355 {
356 odr_xl = val;
357 }
358
359 break;
360
361 default:
362 odr_xl = val;
363 break;
364 }
365 }
366 }
367 }
368
369 if (ret == 0)
370 {
371 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
372 }
373
374 if (ret == 0)
375 {
376 ctrl1_xl.odr_xl = (uint8_t)odr_xl;
377 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_XL,
378 (uint8_t *)&ctrl1_xl, 1);
379 }
380
381 return ret;
382 }
383
384 /**
385 * @brief Accelerometer UI data rate selection.[get]
386 *
387 * @param ctx Read / write interface definitions.(ptr)
388 * @param val Get the values of odr_xl in reg CTRL1_XL
389 * @retval Interface status (MANDATORY: return 0 -> no Error).
390 *
391 */
lsm6dsr_xl_data_rate_get(stmdev_ctx_t * ctx,lsm6dsr_odr_xl_t * val)392 int32_t lsm6dsr_xl_data_rate_get(stmdev_ctx_t *ctx,
393 lsm6dsr_odr_xl_t *val)
394 {
395 lsm6dsr_ctrl1_xl_t ctrl1_xl;
396 int32_t ret;
397
398 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
399
400 switch (ctrl1_xl.odr_xl)
401 {
402 case LSM6DSR_XL_ODR_OFF:
403 *val = LSM6DSR_XL_ODR_OFF;
404 break;
405
406 case LSM6DSR_XL_ODR_12Hz5:
407 *val = LSM6DSR_XL_ODR_12Hz5;
408 break;
409
410 case LSM6DSR_XL_ODR_26Hz:
411 *val = LSM6DSR_XL_ODR_26Hz;
412 break;
413
414 case LSM6DSR_XL_ODR_52Hz:
415 *val = LSM6DSR_XL_ODR_52Hz;
416 break;
417
418 case LSM6DSR_XL_ODR_104Hz:
419 *val = LSM6DSR_XL_ODR_104Hz;
420 break;
421
422 case LSM6DSR_XL_ODR_208Hz:
423 *val = LSM6DSR_XL_ODR_208Hz;
424 break;
425
426 case LSM6DSR_XL_ODR_416Hz:
427 *val = LSM6DSR_XL_ODR_416Hz;
428 break;
429
430 case LSM6DSR_XL_ODR_833Hz:
431 *val = LSM6DSR_XL_ODR_833Hz;
432 break;
433
434 case LSM6DSR_XL_ODR_1666Hz:
435 *val = LSM6DSR_XL_ODR_1666Hz;
436 break;
437
438 case LSM6DSR_XL_ODR_3332Hz:
439 *val = LSM6DSR_XL_ODR_3332Hz;
440 break;
441
442 case LSM6DSR_XL_ODR_6667Hz:
443 *val = LSM6DSR_XL_ODR_6667Hz;
444 break;
445
446 case LSM6DSR_XL_ODR_1Hz6:
447 *val = LSM6DSR_XL_ODR_1Hz6;
448 break;
449
450 default:
451 *val = LSM6DSR_XL_ODR_OFF;
452 break;
453 }
454
455 return ret;
456 }
457
458 /**
459 * @brief Gyroscope UI chain full-scale selection.[set]
460 *
461 * @param ctx Read / write interface definitions.(ptr)
462 * @param val Change the values of fs_g in reg CTRL2_G
463 * @retval Interface status (MANDATORY: return 0 -> no Error).
464 *
465 */
lsm6dsr_gy_full_scale_set(stmdev_ctx_t * ctx,lsm6dsr_fs_g_t val)466 int32_t lsm6dsr_gy_full_scale_set(stmdev_ctx_t *ctx,
467 lsm6dsr_fs_g_t val)
468 {
469 lsm6dsr_ctrl2_g_t ctrl2_g;
470 int32_t ret;
471
472 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
473
474 if (ret == 0)
475 {
476 ctrl2_g.fs_g = (uint8_t)val;
477 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
478 }
479
480 return ret;
481 }
482
483 /**
484 * @brief Gyroscope UI chain full-scale selection.[get]
485 *
486 * @param ctx Read / write interface definitions.(ptr)
487 * @param val Get the values of fs_g in reg CTRL2_G
488 * @retval Interface status (MANDATORY: return 0 -> no Error).
489 *
490 */
lsm6dsr_gy_full_scale_get(stmdev_ctx_t * ctx,lsm6dsr_fs_g_t * val)491 int32_t lsm6dsr_gy_full_scale_get(stmdev_ctx_t *ctx,
492 lsm6dsr_fs_g_t *val)
493 {
494 lsm6dsr_ctrl2_g_t ctrl2_g;
495 int32_t ret;
496
497 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
498
499 switch (ctrl2_g.fs_g)
500 {
501 case LSM6DSR_125dps:
502 *val = LSM6DSR_125dps;
503 break;
504
505 case LSM6DSR_250dps:
506 *val = LSM6DSR_250dps;
507 break;
508
509 case LSM6DSR_500dps:
510 *val = LSM6DSR_500dps;
511 break;
512
513 case LSM6DSR_1000dps:
514 *val = LSM6DSR_1000dps;
515 break;
516
517 case LSM6DSR_2000dps:
518 *val = LSM6DSR_2000dps;
519 break;
520
521 case LSM6DSR_4000dps:
522 *val = LSM6DSR_4000dps;
523 break;
524
525 default:
526 *val = LSM6DSR_125dps;
527 break;
528 }
529
530 return ret;
531 }
532
533 /**
534 * @brief Gyroscope data rate.[set]
535 *
536 * @param ctx Read / write interface definitions.(ptr)
537 * @param val Change the values of odr_g in reg CTRL2_G
538 * @retval Interface status (MANDATORY: return 0 -> no Error).
539 *
540 */
lsm6dsr_gy_data_rate_set(stmdev_ctx_t * ctx,lsm6dsr_odr_g_t val)541 int32_t lsm6dsr_gy_data_rate_set(stmdev_ctx_t *ctx,
542 lsm6dsr_odr_g_t val)
543 {
544 lsm6dsr_odr_g_t odr_gy = val;
545 lsm6dsr_emb_fsm_enable_t fsm_enable;
546 lsm6dsr_fsm_odr_t fsm_odr;
547 lsm6dsr_ctrl2_g_t ctrl2_g;
548 int32_t ret;
549
550 /* Check the Finite State Machine data rate constraints */
551 ret = lsm6dsr_fsm_enable_get(ctx, &fsm_enable);
552
553 if (ret == 0)
554 {
555 if ((fsm_enable.fsm_enable_a.fsm1_en |
556 fsm_enable.fsm_enable_a.fsm2_en |
557 fsm_enable.fsm_enable_a.fsm3_en |
558 fsm_enable.fsm_enable_a.fsm4_en |
559 fsm_enable.fsm_enable_a.fsm5_en |
560 fsm_enable.fsm_enable_a.fsm6_en |
561 fsm_enable.fsm_enable_a.fsm7_en |
562 fsm_enable.fsm_enable_a.fsm8_en |
563 fsm_enable.fsm_enable_b.fsm9_en |
564 fsm_enable.fsm_enable_b.fsm10_en |
565 fsm_enable.fsm_enable_b.fsm11_en |
566 fsm_enable.fsm_enable_b.fsm12_en |
567 fsm_enable.fsm_enable_b.fsm13_en |
568 fsm_enable.fsm_enable_b.fsm14_en |
569 fsm_enable.fsm_enable_b.fsm15_en |
570 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
571 {
572 ret = lsm6dsr_fsm_data_rate_get(ctx, &fsm_odr);
573
574 if (ret == 0)
575 {
576 switch (fsm_odr)
577 {
578 case LSM6DSR_ODR_FSM_12Hz5:
579 if (val == LSM6DSR_GY_ODR_OFF)
580 {
581 odr_gy = LSM6DSR_GY_ODR_12Hz5;
582 }
583
584 else
585 {
586 odr_gy = val;
587 }
588
589 break;
590
591 case LSM6DSR_ODR_FSM_26Hz:
592 if (val == LSM6DSR_GY_ODR_OFF)
593 {
594 odr_gy = LSM6DSR_GY_ODR_26Hz;
595 }
596
597 else if (val == LSM6DSR_GY_ODR_12Hz5)
598 {
599 odr_gy = LSM6DSR_GY_ODR_26Hz;
600 }
601
602 else
603 {
604 odr_gy = val;
605 }
606
607 break;
608
609 case LSM6DSR_ODR_FSM_52Hz:
610 if (val == LSM6DSR_GY_ODR_OFF)
611 {
612 odr_gy = LSM6DSR_GY_ODR_52Hz;
613 }
614
615 else if (val == LSM6DSR_GY_ODR_12Hz5)
616 {
617 odr_gy = LSM6DSR_GY_ODR_52Hz;
618 }
619
620 else if (val == LSM6DSR_GY_ODR_26Hz)
621 {
622 odr_gy = LSM6DSR_GY_ODR_52Hz;
623 }
624
625 else
626 {
627 odr_gy = val;
628 }
629
630 break;
631
632 case LSM6DSR_ODR_FSM_104Hz:
633 if (val == LSM6DSR_GY_ODR_OFF)
634 {
635 odr_gy = LSM6DSR_GY_ODR_104Hz;
636 }
637
638 else if (val == LSM6DSR_GY_ODR_12Hz5)
639 {
640 odr_gy = LSM6DSR_GY_ODR_104Hz;
641 }
642
643 else if (val == LSM6DSR_GY_ODR_26Hz)
644 {
645 odr_gy = LSM6DSR_GY_ODR_104Hz;
646 }
647
648 else if (val == LSM6DSR_GY_ODR_52Hz)
649 {
650 odr_gy = LSM6DSR_GY_ODR_104Hz;
651 }
652
653 else
654 {
655 odr_gy = val;
656 }
657
658 break;
659
660 default:
661 odr_gy = val;
662 break;
663 }
664 }
665 }
666 }
667
668 if (ret == 0)
669 {
670 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
671 }
672
673 if (ret == 0)
674 {
675 ctrl2_g.odr_g = (uint8_t)odr_gy;
676 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
677 }
678
679 return ret;
680 }
681
682 /**
683 * @brief Gyroscope data rate.[get]
684 *
685 * @param ctx Read / write interface definitions.(ptr)
686 * @param val Get the values of odr_g in reg CTRL2_G
687 * @retval Interface status (MANDATORY: return 0 -> no Error).
688 *
689 */
lsm6dsr_gy_data_rate_get(stmdev_ctx_t * ctx,lsm6dsr_odr_g_t * val)690 int32_t lsm6dsr_gy_data_rate_get(stmdev_ctx_t *ctx,
691 lsm6dsr_odr_g_t *val)
692 {
693 lsm6dsr_ctrl2_g_t ctrl2_g;
694 int32_t ret;
695
696 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
697
698 switch (ctrl2_g.odr_g)
699 {
700 case LSM6DSR_GY_ODR_OFF:
701 *val = LSM6DSR_GY_ODR_OFF;
702 break;
703
704 case LSM6DSR_GY_ODR_12Hz5:
705 *val = LSM6DSR_GY_ODR_12Hz5;
706 break;
707
708 case LSM6DSR_GY_ODR_26Hz:
709 *val = LSM6DSR_GY_ODR_26Hz;
710 break;
711
712 case LSM6DSR_GY_ODR_52Hz:
713 *val = LSM6DSR_GY_ODR_52Hz;
714 break;
715
716 case LSM6DSR_GY_ODR_104Hz:
717 *val = LSM6DSR_GY_ODR_104Hz;
718 break;
719
720 case LSM6DSR_GY_ODR_208Hz:
721 *val = LSM6DSR_GY_ODR_208Hz;
722 break;
723
724 case LSM6DSR_GY_ODR_416Hz:
725 *val = LSM6DSR_GY_ODR_416Hz;
726 break;
727
728 case LSM6DSR_GY_ODR_833Hz:
729 *val = LSM6DSR_GY_ODR_833Hz;
730 break;
731
732 case LSM6DSR_GY_ODR_1666Hz:
733 *val = LSM6DSR_GY_ODR_1666Hz;
734 break;
735
736 case LSM6DSR_GY_ODR_3332Hz:
737 *val = LSM6DSR_GY_ODR_3332Hz;
738 break;
739
740 case LSM6DSR_GY_ODR_6667Hz:
741 *val = LSM6DSR_GY_ODR_6667Hz;
742 break;
743
744 default:
745 *val = LSM6DSR_GY_ODR_OFF;
746 break;
747 }
748
749 return ret;
750 }
751
752 /**
753 * @brief Block data update.[set]
754 *
755 * @param ctx Read / write interface definitions.(ptr)
756 * @param val Change the values of bdu in reg CTRL3_C
757 * @retval Interface status (MANDATORY: return 0 -> no Error).
758 *
759 */
lsm6dsr_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)760 int32_t lsm6dsr_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
761 {
762 lsm6dsr_ctrl3_c_t ctrl3_c;
763 int32_t ret;
764
765 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
766
767 if (ret == 0)
768 {
769 ctrl3_c.bdu = (uint8_t)val;
770 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
771 }
772
773 return ret;
774 }
775
776 /**
777 * @brief Block data update.[get]
778 *
779 * @param ctx Read / write interface definitions.(ptr)
780 * @param val Change the values of bdu in reg CTRL3_C
781 * @retval Interface status (MANDATORY: return 0 -> no Error).
782 *
783 */
lsm6dsr_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)784 int32_t lsm6dsr_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
785 {
786 lsm6dsr_ctrl3_c_t ctrl3_c;
787 int32_t ret;
788
789 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
790 *val = ctrl3_c.bdu;
791
792 return ret;
793 }
794
795 /**
796 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
797 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
798 *
799 * @param ctx Read / write interface definitions.(ptr)
800 * @param val Change the values of usr_off_w in reg CTRL6_C
801 * @retval Interface status (MANDATORY: return 0 -> no Error).
802 *
803 */
lsm6dsr_xl_offset_weight_set(stmdev_ctx_t * ctx,lsm6dsr_usr_off_w_t val)804 int32_t lsm6dsr_xl_offset_weight_set(stmdev_ctx_t *ctx,
805 lsm6dsr_usr_off_w_t val)
806 {
807 lsm6dsr_ctrl6_c_t ctrl6_c;
808 int32_t ret;
809
810 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
811
812 if (ret == 0)
813 {
814 ctrl6_c.usr_off_w = (uint8_t)val;
815 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
816 }
817
818 return ret;
819 }
820
821 /**
822 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
823 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
824 *
825 * @param ctx Read / write interface definitions.(ptr)
826 * @param val Get the values of usr_off_w in reg CTRL6_C
827 * @retval Interface status (MANDATORY: return 0 -> no Error).
828 *
829 */
lsm6dsr_xl_offset_weight_get(stmdev_ctx_t * ctx,lsm6dsr_usr_off_w_t * val)830 int32_t lsm6dsr_xl_offset_weight_get(stmdev_ctx_t *ctx,
831 lsm6dsr_usr_off_w_t *val)
832 {
833 lsm6dsr_ctrl6_c_t ctrl6_c;
834 int32_t ret;
835
836 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
837
838 switch (ctrl6_c.usr_off_w)
839 {
840 case LSM6DSR_LSb_1mg:
841 *val = LSM6DSR_LSb_1mg;
842 break;
843
844 case LSM6DSR_LSb_16mg:
845 *val = LSM6DSR_LSb_16mg;
846 break;
847
848 default:
849 *val = LSM6DSR_LSb_1mg;
850 break;
851 }
852
853 return ret;
854 }
855
856 /**
857 * @brief Accelerometer power mode.[set]
858 *
859 * @param ctx Read / write interface definitions.(ptr)
860 * @param val Change the values of xl_hm_mode in reg CTRL6_C
861 * @retval Interface status (MANDATORY: return 0 -> no Error).
862 *
863 */
lsm6dsr_xl_power_mode_set(stmdev_ctx_t * ctx,lsm6dsr_xl_hm_mode_t val)864 int32_t lsm6dsr_xl_power_mode_set(stmdev_ctx_t *ctx,
865 lsm6dsr_xl_hm_mode_t val)
866 {
867 lsm6dsr_ctrl6_c_t ctrl6_c;
868 int32_t ret;
869
870 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
871
872 if (ret == 0)
873 {
874 ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
875 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
876 }
877
878 return ret;
879 }
880
881 /**
882 * @brief Accelerometer power mode[get]
883 *
884 * @param ctx Read / write interface definitions.(ptr)
885 * @param val Get the values of xl_hm_mode in reg CTRL6_C
886 * @retval Interface status (MANDATORY: return 0 -> no Error).
887 *
888 */
lsm6dsr_xl_power_mode_get(stmdev_ctx_t * ctx,lsm6dsr_xl_hm_mode_t * val)889 int32_t lsm6dsr_xl_power_mode_get(stmdev_ctx_t *ctx,
890 lsm6dsr_xl_hm_mode_t *val)
891 {
892 lsm6dsr_ctrl6_c_t ctrl6_c;
893 int32_t ret;
894
895 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
896
897 switch (ctrl6_c.xl_hm_mode)
898 {
899 case LSM6DSR_HIGH_PERFORMANCE_MD:
900 *val = LSM6DSR_HIGH_PERFORMANCE_MD;
901 break;
902
903 case LSM6DSR_LOW_NORMAL_POWER_MD:
904 *val = LSM6DSR_LOW_NORMAL_POWER_MD;
905 break;
906
907 default:
908 *val = LSM6DSR_HIGH_PERFORMANCE_MD;
909 break;
910 }
911
912 return ret;
913 }
914
915 /**
916 * @brief Operating mode for gyroscope.[set]
917 *
918 * @param ctx Read / write interface definitions.(ptr)
919 * @param val Change the values of g_hm_mode in reg CTRL7_G
920 * @retval Interface status (MANDATORY: return 0 -> no Error).
921 *
922 */
lsm6dsr_gy_power_mode_set(stmdev_ctx_t * ctx,lsm6dsr_g_hm_mode_t val)923 int32_t lsm6dsr_gy_power_mode_set(stmdev_ctx_t *ctx,
924 lsm6dsr_g_hm_mode_t val)
925 {
926 lsm6dsr_ctrl7_g_t ctrl7_g;
927 int32_t ret;
928
929 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
930
931 if (ret == 0)
932 {
933 ctrl7_g.g_hm_mode = (uint8_t)val;
934 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
935 }
936
937 return ret;
938 }
939
940 /**
941 * @brief gy_power_mode: [get] Operating mode for gyroscope.
942 *
943 * @param ctx Read / write interface definitions.(ptr)
944 * @param val Get the values of g_hm_mode in reg CTRL7_G
945 * @retval Interface status (MANDATORY: return 0 -> no Error).
946 *
947 */
lsm6dsr_gy_power_mode_get(stmdev_ctx_t * ctx,lsm6dsr_g_hm_mode_t * val)948 int32_t lsm6dsr_gy_power_mode_get(stmdev_ctx_t *ctx,
949 lsm6dsr_g_hm_mode_t *val)
950 {
951 lsm6dsr_ctrl7_g_t ctrl7_g;
952 int32_t ret;
953
954 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
955
956 switch (ctrl7_g.g_hm_mode)
957 {
958 case LSM6DSR_GY_HIGH_PERFORMANCE:
959 *val = LSM6DSR_GY_HIGH_PERFORMANCE;
960 break;
961
962 case LSM6DSR_GY_NORMAL:
963 *val = LSM6DSR_GY_NORMAL;
964 break;
965
966 default:
967 *val = LSM6DSR_GY_HIGH_PERFORMANCE;
968 break;
969 }
970
971 return ret;
972 }
973
974 /**
975 * @brief Read all the interrupt flag of the device.
976 *[get]
977 * @param ctx Read / write interface definitions.(ptr)
978 * @param val Get registers ALL_INT_SRC; WAKE_UP_SRC;
979 * TAP_SRC; D6D_SRC; STATUS_REG;
980 * EMB_FUNC_STATUS; FSM_STATUS_A/B
981 * @retval Interface status (MANDATORY: return 0 -> no Error).
982 *
983 */
lsm6dsr_all_sources_get(stmdev_ctx_t * ctx,lsm6dsr_all_sources_t * val)984 int32_t lsm6dsr_all_sources_get(stmdev_ctx_t *ctx,
985 lsm6dsr_all_sources_t *val)
986 {
987 int32_t ret;
988
989 ret = lsm6dsr_read_reg(ctx, LSM6DSR_ALL_INT_SRC,
990 (uint8_t *)&val->all_int_src, 1);
991
992 if (ret == 0)
993 {
994 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_SRC,
995 (uint8_t *)&val->wake_up_src, 1);
996 }
997
998 if (ret == 0)
999 {
1000 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_SRC,
1001 (uint8_t *)&val->tap_src, 1);
1002 }
1003
1004 if (ret == 0)
1005 {
1006 ret = lsm6dsr_read_reg(ctx, LSM6DSR_D6D_SRC,
1007 (uint8_t *)&val->d6d_src, 1);
1008 }
1009
1010 if (ret == 0)
1011 {
1012 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG,
1013 (uint8_t *)&val->status_reg, 1);
1014 }
1015
1016 if (ret == 0)
1017 {
1018 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
1019 }
1020
1021 if (ret == 0)
1022 {
1023 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_STATUS,
1024 (uint8_t *)&val->emb_func_status, 1);
1025 }
1026
1027 if (ret == 0)
1028 {
1029 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_STATUS_A,
1030 (uint8_t *)&val->fsm_status_a, 1);
1031 }
1032
1033 if (ret == 0)
1034 {
1035 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_STATUS_B,
1036 (uint8_t *)&val->fsm_status_b, 1);
1037 }
1038
1039 if (ret == 0)
1040 {
1041 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
1042 }
1043
1044 return ret;
1045 }
1046
1047 /**
1048 * @brief The STATUS_REG register is read by the primary interface.[get]
1049 *
1050 * @param ctx Read / write interface definitions.(ptr)
1051 * @param val Get register STATUS_REG
1052 * @retval Interface status (MANDATORY: return 0 -> no Error).
1053 *
1054 */
lsm6dsr_status_reg_get(stmdev_ctx_t * ctx,lsm6dsr_status_reg_t * val)1055 int32_t lsm6dsr_status_reg_get(stmdev_ctx_t *ctx,
1056 lsm6dsr_status_reg_t *val)
1057 {
1058 int32_t ret;
1059
1060 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG, (uint8_t *) val, 1);
1061
1062 return ret;
1063 }
1064
1065 /**
1066 * @brief Accelerometer new data available.[get]
1067 *
1068 * @param ctx Read / write interface definitions.(ptr)
1069 * @param val Change the values of xlda in reg STATUS_REG
1070 * @retval Interface status (MANDATORY: return 0 -> no Error).
1071 *
1072 */
lsm6dsr_xl_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1073 int32_t lsm6dsr_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
1074 uint8_t *val)
1075 {
1076 lsm6dsr_status_reg_t status_reg;
1077 int32_t ret;
1078
1079 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG,
1080 (uint8_t *)&status_reg, 1);
1081 *val = status_reg.xlda;
1082
1083 return ret;
1084 }
1085
1086 /**
1087 * @brief Gyroscope new data available.[get]
1088 *
1089 * @param ctx Read / write interface definitions.(ptr)
1090 * @param val Change the values of gda in reg STATUS_REG
1091 * @retval Interface status (MANDATORY: return 0 -> no Error).
1092 *
1093 */
lsm6dsr_gy_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1094 int32_t lsm6dsr_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
1095 uint8_t *val)
1096 {
1097 lsm6dsr_status_reg_t status_reg;
1098 int32_t ret;
1099
1100 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG,
1101 (uint8_t *)&status_reg, 1);
1102 *val = status_reg.gda;
1103
1104 return ret;
1105 }
1106
1107 /**
1108 * @brief Temperature new data available.[get]
1109 *
1110 * @param ctx Read / write interface definitions.(ptr)
1111 * @param val Change the values of tda in reg STATUS_REG
1112 * @retval Interface status (MANDATORY: return 0 -> no Error).
1113 *
1114 */
lsm6dsr_temp_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1115 int32_t lsm6dsr_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
1116 uint8_t *val)
1117 {
1118 lsm6dsr_status_reg_t status_reg;
1119 int32_t ret;
1120
1121 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_REG,
1122 (uint8_t *)&status_reg, 1);
1123 *val = status_reg.tda;
1124
1125 return ret;
1126 }
1127
1128 /**
1129 * @brief Accelerometer X-axis user offset correction expressed in two’s
1130 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1131 * The value must be in the range [-127 127].[set]
1132 *
1133 * @param ctx Read / write interface definitions.(ptr)
1134 * @param buff Buffer that contains data to write
1135 * @retval Interface status (MANDATORY: return 0 -> no Error).
1136 *
1137 */
lsm6dsr_xl_usr_offset_x_set(stmdev_ctx_t * ctx,uint8_t * buff)1138 int32_t lsm6dsr_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
1139 {
1140 int32_t ret;
1141
1142 ret = lsm6dsr_write_reg(ctx, LSM6DSR_X_OFS_USR, buff, 1);
1143
1144 return ret;
1145 }
1146
1147 /**
1148 * @brief Accelerometer X-axis user offset correction expressed in two’s
1149 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1150 * The value must be in the range [-127 127].[get]
1151 *
1152 * @param ctx Read / write interface definitions.(ptr)
1153 * @param buff Buffer that stores data read
1154 * @retval Interface status (MANDATORY: return 0 -> no Error).
1155 *
1156 */
lsm6dsr_xl_usr_offset_x_get(stmdev_ctx_t * ctx,uint8_t * buff)1157 int32_t lsm6dsr_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
1158 {
1159 int32_t ret;
1160
1161 ret = lsm6dsr_read_reg(ctx, LSM6DSR_X_OFS_USR, buff, 1);
1162
1163 return ret;
1164 }
1165
1166 /**
1167 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1168 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1169 * The value must be in the range [-127 127].[set]
1170 *
1171 * @param ctx Read / write interface definitions.(ptr)
1172 * @param buff Buffer that contains data to write
1173 * @retval Interface status (MANDATORY: return 0 -> no Error).
1174 *
1175 */
lsm6dsr_xl_usr_offset_y_set(stmdev_ctx_t * ctx,uint8_t * buff)1176 int32_t lsm6dsr_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
1177 {
1178 int32_t ret;
1179
1180 ret = lsm6dsr_write_reg(ctx, LSM6DSR_Y_OFS_USR, buff, 1);
1181
1182 return ret;
1183 }
1184
1185 /**
1186 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1187 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1188 * The value must be in the range [-127 127].[get]
1189 *
1190 * @param ctx Read / write interface definitions.(ptr)
1191 * @param buff Buffer that stores data read
1192 * @retval Interface status (MANDATORY: return 0 -> no Error).
1193 *
1194 */
lsm6dsr_xl_usr_offset_y_get(stmdev_ctx_t * ctx,uint8_t * buff)1195 int32_t lsm6dsr_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
1196 {
1197 int32_t ret;
1198
1199 ret = lsm6dsr_read_reg(ctx, LSM6DSR_Y_OFS_USR, buff, 1);
1200
1201 return ret;
1202 }
1203
1204 /**
1205 * @brief Accelerometer Z-axis user offset correction expressed in two’s
1206 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1207 * The value must be in the range [-127 127].[set]
1208 *
1209 * @param ctx Read / write interface definitions.(ptr)
1210 * @param buff Buffer that contains data to write
1211 * @retval Interface status (MANDATORY: return 0 -> no Error).
1212 *
1213 */
lsm6dsr_xl_usr_offset_z_set(stmdev_ctx_t * ctx,uint8_t * buff)1214 int32_t lsm6dsr_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
1215 {
1216 int32_t ret;
1217
1218 ret = lsm6dsr_write_reg(ctx, LSM6DSR_Z_OFS_USR, buff, 1);
1219
1220 return ret;
1221 }
1222
1223 /**
1224 * @brief Accelerometer X-axis user offset correction expressed in two’s
1225 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1226 * The value must be in the range [-127 127].[get]
1227 *
1228 * @param ctx Read / write interface definitions.(ptr)
1229 * @param buff Buffer that stores data read
1230 * @retval Interface status (MANDATORY: return 0 -> no Error).
1231 *
1232 */
lsm6dsr_xl_usr_offset_z_get(stmdev_ctx_t * ctx,uint8_t * buff)1233 int32_t lsm6dsr_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
1234 {
1235 int32_t ret;
1236
1237 ret = lsm6dsr_read_reg(ctx, LSM6DSR_Z_OFS_USR, buff, 1);
1238
1239 return ret;
1240 }
1241
1242 /**
1243 * @brief Enables user offset on out.[set]
1244 *
1245 * @param ctx Read / write interface definitions.(ptr)
1246 * @param val Change the values of usr_off_on_out in reg CTRL7_G
1247 * @retval Interface status (MANDATORY: return 0 -> no Error).
1248 *
1249 */
lsm6dsr_xl_usr_offset_set(stmdev_ctx_t * ctx,uint8_t val)1250 int32_t lsm6dsr_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
1251 {
1252 lsm6dsr_ctrl7_g_t ctrl7_g;
1253 int32_t ret;
1254
1255 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1256
1257 if (ret == 0)
1258 {
1259 ctrl7_g.usr_off_on_out = (uint8_t)val;
1260 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1261 }
1262
1263 return ret;
1264 }
1265
1266 /**
1267 * @brief Get user offset on out flag.[get]
1268 *
1269 * @param ctx Read / write interface definitions.(ptr)
1270 * @param val Get values of usr_off_on_out in reg CTRL7_G
1271 * @retval Interface status (MANDATORY: return 0 -> no Error).
1272 *
1273 */
lsm6dsr_xl_usr_offset_get(stmdev_ctx_t * ctx,uint8_t * val)1274 int32_t lsm6dsr_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
1275 {
1276 lsm6dsr_ctrl7_g_t ctrl7_g;
1277 int32_t ret;
1278
1279 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
1280 *val = ctrl7_g.usr_off_on_out;
1281
1282 return ret;
1283 }
1284
1285 /**
1286 * @}
1287 *
1288 */
1289
1290 /**
1291 * @defgroup LSM6DSR_Timestamp
1292 * @brief This section groups all the functions that manage the
1293 * timestamp generation.
1294 * @{
1295 *
1296 */
1297
1298 /**
1299 * @brief Reset timestamp counter.[set]
1300 *
1301 * @param ctx Read / write interface definitions.(ptr)
1302 * @retval Interface status (MANDATORY: return 0 -> no Error).
1303 *
1304 */
lsm6dsr_timestamp_rst(stmdev_ctx_t * ctx)1305 int32_t lsm6dsr_timestamp_rst(stmdev_ctx_t *ctx)
1306 {
1307 uint8_t rst_val = 0xAA;
1308 return lsm6dsr_write_reg(ctx, LSM6DSR_TIMESTAMP2, &rst_val, 1);
1309 }
1310
1311 /**
1312 * @brief Enables timestamp counter.[set]
1313 *
1314 * @param ctx Read / write interface definitions.(ptr)
1315 * @param val Change the values of timestamp_en in reg CTRL10_C
1316 * @retval Interface status (MANDATORY: return 0 -> no Error).
1317 *
1318 */
lsm6dsr_timestamp_set(stmdev_ctx_t * ctx,uint8_t val)1319 int32_t lsm6dsr_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
1320 {
1321 lsm6dsr_ctrl10_c_t ctrl10_c;
1322 int32_t ret;
1323
1324 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1325
1326 if (ret == 0)
1327 {
1328 ctrl10_c.timestamp_en = (uint8_t)val;
1329 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL10_C,
1330 (uint8_t *)&ctrl10_c, 1);
1331 }
1332
1333 return ret;
1334 }
1335
1336 /**
1337 * @brief Enables timestamp counter.[get]
1338 *
1339 * @param ctx Read / write interface definitions.(ptr)
1340 * @param val Change the values of timestamp_en in reg CTRL10_C
1341 * @retval Interface status (MANDATORY: return 0 -> no Error).
1342 *
1343 */
lsm6dsr_timestamp_get(stmdev_ctx_t * ctx,uint8_t * val)1344 int32_t lsm6dsr_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
1345 {
1346 lsm6dsr_ctrl10_c_t ctrl10_c;
1347 int32_t ret;
1348
1349 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1350 *val = ctrl10_c.timestamp_en;
1351
1352 return ret;
1353 }
1354
1355 /**
1356 * @brief Timestamp first data output register (r).
1357 * The value is expressed as a 32-bit word and the bit resolution
1358 * is 25 μs.[get]
1359 *
1360 * @param ctx Read / write interface definitions.(ptr)
1361 * @param buff Buffer that stores data read
1362 * @retval Interface status (MANDATORY: return 0 -> no Error).
1363 *
1364 */
lsm6dsr_timestamp_raw_get(stmdev_ctx_t * ctx,uint32_t * val)1365 int32_t lsm6dsr_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
1366 {
1367 uint8_t buff[4];
1368 int32_t ret;
1369
1370 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TIMESTAMP0, buff, 4);
1371 *val = buff[3];
1372 *val = (*val * 256U) + buff[2];
1373 *val = (*val * 256U) + buff[1];
1374 *val = (*val * 256U) + buff[0];
1375
1376 return ret;
1377 }
1378
1379 /**
1380 * @}
1381 *
1382 */
1383
1384 /**
1385 * @defgroup LSM6DSR_Data output
1386 * @brief This section groups all the data output functions.
1387 * @{
1388 *
1389 */
1390
1391 /**
1392 * @brief Circular burst-mode (rounding) read of the output registers.[set]
1393 *
1394 * @param ctx Read / write interface definitions.(ptr)
1395 * @param val Change the values of rounding in reg CTRL5_C
1396 * @retval Interface status (MANDATORY: return 0 -> no Error).
1397 *
1398 */
lsm6dsr_rounding_mode_set(stmdev_ctx_t * ctx,lsm6dsr_rounding_t val)1399 int32_t lsm6dsr_rounding_mode_set(stmdev_ctx_t *ctx,
1400 lsm6dsr_rounding_t val)
1401 {
1402 lsm6dsr_ctrl5_c_t ctrl5_c;
1403 int32_t ret;
1404
1405 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1406
1407 if (ret == 0)
1408 {
1409 ctrl5_c.rounding = (uint8_t)val;
1410 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1411 }
1412
1413 return ret;
1414 }
1415
1416 /**
1417 * @brief Gyroscope UI chain full-scale selection.[get]
1418 *
1419 * @param ctx Read / write interface definitions.(ptr)
1420 * @param val Get the values of rounding in reg CTRL5_C
1421 * @retval Interface status (MANDATORY: return 0 -> no Error).
1422 *
1423 */
lsm6dsr_rounding_mode_get(stmdev_ctx_t * ctx,lsm6dsr_rounding_t * val)1424 int32_t lsm6dsr_rounding_mode_get(stmdev_ctx_t *ctx,
1425 lsm6dsr_rounding_t *val)
1426 {
1427 lsm6dsr_ctrl5_c_t ctrl5_c;
1428 int32_t ret;
1429
1430 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1431
1432 switch (ctrl5_c.rounding)
1433 {
1434 case LSM6DSR_NO_ROUND:
1435 *val = LSM6DSR_NO_ROUND;
1436 break;
1437
1438 case LSM6DSR_ROUND_XL:
1439 *val = LSM6DSR_ROUND_XL;
1440 break;
1441
1442 case LSM6DSR_ROUND_GY:
1443 *val = LSM6DSR_ROUND_GY;
1444 break;
1445
1446 case LSM6DSR_ROUND_GY_XL:
1447 *val = LSM6DSR_ROUND_GY_XL;
1448 break;
1449
1450 default:
1451 *val = LSM6DSR_NO_ROUND;
1452 break;
1453 }
1454
1455 return ret;
1456 }
1457
1458 /**
1459 * @brief Temperature data output register (r).
1460 * L and H registers together express a 16-bit word in two’s
1461 * complement.[get]
1462 *
1463 * @param ctx Read / write interface definitions.(ptr)
1464 * @param buff Buffer that stores data read
1465 * @retval Interface status (MANDATORY: return 0 -> no Error).
1466 *
1467 */
lsm6dsr_temperature_raw_get(stmdev_ctx_t * ctx,int16_t * val)1468 int32_t lsm6dsr_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1469 {
1470 uint8_t buff[2];
1471 int32_t ret;
1472
1473 ret = lsm6dsr_read_reg(ctx, LSM6DSR_OUT_TEMP_L, buff, 2);
1474 val[0] = (int16_t)buff[1];
1475 val[0] = (val[0] * 256) + (int16_t)buff[0];
1476
1477 return ret;
1478 }
1479
1480 /**
1481 * @brief Angular rate sensor. The value is expressed as a 16-bit
1482 * word in two’s complement.[get]
1483 *
1484 * @param ctx Read / write interface definitions.(ptr)
1485 * @param buff Buffer that stores data read
1486 * @retval Interface status (MANDATORY: return 0 -> no Error).
1487 *
1488 */
lsm6dsr_angular_rate_raw_get(stmdev_ctx_t * ctx,int16_t * val)1489 int32_t lsm6dsr_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1490 {
1491 uint8_t buff[6];
1492 int32_t ret;
1493
1494 ret = lsm6dsr_read_reg(ctx, LSM6DSR_OUTX_L_G, buff, 6);
1495 val[0] = (int16_t)buff[1];
1496 val[0] = (val[0] * 256) + (int16_t)buff[0];
1497 val[1] = (int16_t)buff[3];
1498 val[1] = (val[1] * 256) + (int16_t)buff[2];
1499 val[2] = (int16_t)buff[5];
1500 val[2] = (val[2] * 256) + (int16_t)buff[4];
1501
1502 return ret;
1503 }
1504
1505 /**
1506 * @brief Linear acceleration output register. The value is expressed as a
1507 * 16-bit word in two’s complement.[get]
1508 *
1509 * @param ctx Read / write interface definitions.(ptr)
1510 * @param buff Buffer that stores data read
1511 * @retval Interface status (MANDATORY: return 0 -> no Error).
1512 *
1513 */
lsm6dsr_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)1514 int32_t lsm6dsr_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1515 {
1516 uint8_t buff[6];
1517 int32_t ret;
1518
1519 ret = lsm6dsr_read_reg(ctx, LSM6DSR_OUTX_L_A, buff, 6);
1520 val[0] = (int16_t)buff[1];
1521 val[0] = (val[0] * 256) + (int16_t)buff[0];
1522 val[1] = (int16_t)buff[3];
1523 val[1] = (val[1] * 256) + (int16_t)buff[2];
1524 val[2] = (int16_t)buff[5];
1525 val[2] = (val[2] * 256) + (int16_t)buff[4];
1526
1527 return ret;
1528 }
1529
1530 /**
1531 * @brief FIFO data output.[get]
1532 *
1533 * @param ctx Read / write interface definitions.(ptr)
1534 * @param buff Buffer that stores data read
1535 * @retval Interface status (MANDATORY: return 0 -> no Error).
1536 *
1537 */
lsm6dsr_fifo_out_raw_get(stmdev_ctx_t * ctx,uint8_t * buff)1538 int32_t lsm6dsr_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
1539 {
1540 int32_t ret;
1541
1542 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_DATA_OUT_X_L, buff, 6);
1543
1544 return ret;
1545 }
1546
1547 /**
1548 * @brief Step counter output register.[get]
1549 *
1550 * @param ctx Read / write interface definitions.(ptr)
1551 * @param buff Buffer that stores data read
1552 * @retval Interface status (MANDATORY: return 0 -> no Error).
1553 *
1554 */
lsm6dsr_number_of_steps_get(stmdev_ctx_t * ctx,uint16_t * val)1555 int32_t lsm6dsr_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val)
1556 {
1557 uint8_t buff[2];
1558 int32_t ret;
1559
1560 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
1561
1562 if (ret == 0)
1563 {
1564 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STEP_COUNTER_L, buff, 2);
1565 }
1566
1567 if (ret == 0)
1568 {
1569 *val = buff[1];
1570 *val = (*val * 256U) + buff[0];
1571 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
1572 }
1573
1574 return ret;
1575 }
1576
1577 /**
1578 * @brief Reset step counter register.[get]
1579 *
1580 * @param ctx Read / write interface definitions.(ptr)
1581 * @retval Interface status (MANDATORY: return 0 -> no Error).
1582 *
1583 */
lsm6dsr_steps_reset(stmdev_ctx_t * ctx)1584 int32_t lsm6dsr_steps_reset(stmdev_ctx_t *ctx)
1585 {
1586 lsm6dsr_emb_func_src_t emb_func_src;
1587 int32_t ret;
1588
1589 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
1590
1591 if (ret == 0)
1592 {
1593 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_SRC,
1594 (uint8_t *)&emb_func_src, 1);
1595 }
1596
1597 if (ret == 0)
1598 {
1599 emb_func_src.pedo_rst_step = PROPERTY_ENABLE;
1600 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_SRC,
1601 (uint8_t *)&emb_func_src, 1);
1602 }
1603
1604 if (ret == 0)
1605 {
1606 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
1607 }
1608
1609 return ret;
1610 }
1611
1612 /**
1613 * @}
1614 *
1615 */
1616
1617 /**
1618 * @defgroup LSM6DSR_common
1619 * @brief This section groups common useful functions.
1620 * @{
1621 *
1622 */
1623
1624 /**
1625 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1626 * with respect to the typical.[set]
1627 * Step: 0.15%. 8-bit format, 2's complement.
1628 *
1629 * @param ctx Read / write interface definitions.(ptr)
1630 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1631 * @retval Interface status (MANDATORY: return 0 -> no Error).
1632 *
1633 */
lsm6dsr_odr_cal_reg_set(stmdev_ctx_t * ctx,uint8_t val)1634 int32_t lsm6dsr_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
1635 {
1636 lsm6dsr_internal_freq_fine_t internal_freq_fine;
1637 int32_t ret;
1638
1639 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INTERNAL_FREQ_FINE,
1640 (uint8_t *)&internal_freq_fine, 1);
1641
1642 if (ret == 0)
1643 {
1644 internal_freq_fine.freq_fine = (uint8_t)val;
1645 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INTERNAL_FREQ_FINE,
1646 (uint8_t *)&internal_freq_fine, 1);
1647 }
1648
1649 return ret;
1650 }
1651
1652 /**
1653 * @brief Difference in percentage of the effective ODR (and timestamp rate)
1654 * with respect to the typical.[get]
1655 * Step: 0.15%. 8-bit format, 2's complement.
1656 *
1657 * @param ctx Read / write interface definitions.(ptr)
1658 * @param val Change the values of freq_fine in reg INTERNAL_FREQ_FINE
1659 * @retval Interface status (MANDATORY: return 0 -> no Error).
1660 *
1661 */
lsm6dsr_odr_cal_reg_get(stmdev_ctx_t * ctx,uint8_t * val)1662 int32_t lsm6dsr_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
1663 {
1664 lsm6dsr_internal_freq_fine_t internal_freq_fine;
1665 int32_t ret;
1666
1667 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INTERNAL_FREQ_FINE,
1668 (uint8_t *)&internal_freq_fine, 1);
1669 *val = internal_freq_fine.freq_fine;
1670
1671 return ret;
1672 }
1673
1674 /**
1675 * @brief Enable access to the embedded functions/sensor hub configuration
1676 * registers.[set]
1677 *
1678 * @param ctx Read / write interface definitions.(ptr)
1679 * @param val Change the values of reg_access in reg FUNC_CFG_ACCESS
1680 * @retval Interface status (MANDATORY: return 0 -> no Error).
1681 *
1682 */
lsm6dsr_mem_bank_set(stmdev_ctx_t * ctx,lsm6dsr_reg_access_t val)1683 int32_t lsm6dsr_mem_bank_set(stmdev_ctx_t *ctx,
1684 lsm6dsr_reg_access_t val)
1685 {
1686 lsm6dsr_func_cfg_access_t func_cfg_access;
1687 int32_t ret;
1688
1689 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FUNC_CFG_ACCESS,
1690 (uint8_t *)&func_cfg_access, 1);
1691
1692 if (ret == 0)
1693 {
1694 func_cfg_access.reg_access = (uint8_t)val;
1695 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FUNC_CFG_ACCESS,
1696 (uint8_t *)&func_cfg_access, 1);
1697 }
1698
1699 return ret;
1700 }
1701
1702 /**
1703 * @brief Enable access to the embedded functions/sensor hub configuration
1704 * registers.[get]
1705 *
1706 * @param ctx Read / write interface definitions.(ptr)
1707 * @param val Get the values of reg_access in reg FUNC_CFG_ACCESS
1708 * @retval Interface status (MANDATORY: return 0 -> no Error).
1709 *
1710 */
lsm6dsr_mem_bank_get(stmdev_ctx_t * ctx,lsm6dsr_reg_access_t * val)1711 int32_t lsm6dsr_mem_bank_get(stmdev_ctx_t *ctx,
1712 lsm6dsr_reg_access_t *val)
1713 {
1714 lsm6dsr_func_cfg_access_t func_cfg_access;
1715 int32_t ret;
1716
1717 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FUNC_CFG_ACCESS,
1718 (uint8_t *)&func_cfg_access, 1);
1719
1720 switch (func_cfg_access.reg_access)
1721 {
1722 case LSM6DSR_USER_BANK:
1723 *val = LSM6DSR_USER_BANK;
1724 break;
1725
1726 case LSM6DSR_SENSOR_HUB_BANK:
1727 *val = LSM6DSR_SENSOR_HUB_BANK;
1728 break;
1729
1730 case LSM6DSR_EMBEDDED_FUNC_BANK:
1731 *val = LSM6DSR_EMBEDDED_FUNC_BANK;
1732 break;
1733
1734 default:
1735 *val = LSM6DSR_USER_BANK;
1736 break;
1737 }
1738
1739 return ret;
1740 }
1741
1742 /**
1743 * @brief Write a line(byte) in a page.[set]
1744 *
1745 * @param ctx Read / write interface definitions.(ptr)
1746 * @param add Page line address
1747 * @param val Value to write
1748 * @retval Interface status (MANDATORY: return 0 -> no Error).
1749 *
1750 */
lsm6dsr_ln_pg_write_byte(stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)1751 int32_t lsm6dsr_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t add,
1752 uint8_t *val)
1753 {
1754 lsm6dsr_page_rw_t page_rw;
1755 lsm6dsr_page_sel_t page_sel;
1756 lsm6dsr_page_address_t page_address;
1757 int32_t ret;
1758
1759 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
1760
1761 if (ret == 0)
1762 {
1763 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
1764 }
1765
1766 if (ret == 0)
1767 {
1768 page_rw.page_rw = 0x02U; /* page_write enable */
1769 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
1770 }
1771
1772 if (ret == 0)
1773 {
1774 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL, (uint8_t *)&page_sel, 1);
1775 }
1776
1777 if (ret == 0)
1778 {
1779 page_sel.page_sel = (uint8_t)((add >> 8) & 0x0FU);
1780 page_sel.not_used_01 = 1;
1781 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL,
1782 (uint8_t *)&page_sel, 1);
1783 }
1784
1785 if (ret == 0)
1786 {
1787 page_address.page_addr = (uint8_t)(add & 0xFFU);
1788 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_ADDRESS,
1789 (uint8_t *)&page_address, 1);
1790 }
1791
1792 if (ret == 0)
1793 {
1794 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_VALUE, val, 1);
1795 }
1796
1797 if (ret == 0)
1798 {
1799 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
1800 }
1801
1802 if (ret == 0)
1803 {
1804 page_rw.page_rw = 0x00; /* page_write disable */
1805 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
1806 }
1807
1808 if (ret == 0)
1809 {
1810 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
1811 }
1812
1813 return ret;
1814 }
1815
1816 /**
1817 * @brief Write buffer in a page.[set]
1818 *
1819 * @param ctx Read / write interface definitions.(ptr)
1820 * @param buf Page line address.(ptr)
1821 * @param val Value to write.
1822 * @param len buffer length.
1823 * @retval Interface status (MANDATORY: return 0 -> no Error).
1824 *
1825 */
lsm6dsr_ln_pg_write(stmdev_ctx_t * ctx,uint16_t add,uint8_t * buf,uint8_t len)1826 int32_t lsm6dsr_ln_pg_write(stmdev_ctx_t *ctx, uint16_t add,
1827 uint8_t *buf, uint8_t len)
1828 {
1829 lsm6dsr_page_rw_t page_rw;
1830 lsm6dsr_page_sel_t page_sel;
1831 lsm6dsr_page_address_t page_address;
1832 int32_t ret;
1833
1834 uint8_t msb, lsb;
1835 uint8_t i ;
1836 msb = (uint8_t)((add >> 8) & 0x0FU);
1837 lsb = (uint8_t)(add & 0xFFU);
1838 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
1839
1840 if (ret == 0)
1841 {
1842 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
1843 }
1844
1845 if (ret == 0)
1846 {
1847 page_rw.page_rw = 0x02U; /* page_write enable*/
1848 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
1849 }
1850
1851 if (ret == 0)
1852 {
1853 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL, (uint8_t *)&page_sel, 1);
1854 }
1855
1856 if (ret == 0)
1857 {
1858 page_sel.page_sel = msb;
1859 page_sel.not_used_01 = 1;
1860 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL,
1861 (uint8_t *)&page_sel, 1);
1862 }
1863
1864 if (ret == 0)
1865 {
1866 page_address.page_addr = lsb;
1867 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_ADDRESS,
1868 (uint8_t *)&page_address, 1);
1869 }
1870
1871 for (i = 0; i < len; i++)
1872 {
1873 if (ret == 0)
1874 {
1875 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_VALUE, &buf[i], 1);
1876
1877 if (ret == 0)
1878 {
1879 /* Check if page wrap */
1880 if (lsb == 0x00U)
1881 {
1882 msb++;
1883 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL,
1884 (uint8_t *)&page_sel, 1);
1885 }
1886
1887 lsb++;
1888 }
1889
1890 if (ret == 0)
1891 {
1892 page_sel.page_sel = msb;
1893 page_sel.not_used_01 = 1;
1894 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL,
1895 (uint8_t *)&page_sel, 1);
1896 }
1897 }
1898 }
1899
1900 if (ret == 0)
1901 {
1902 page_sel.page_sel = 0;
1903 page_sel.not_used_01 = 1;
1904 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL,
1905 (uint8_t *)&page_sel, 1);
1906 }
1907
1908 if (ret == 0)
1909 {
1910 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
1911 }
1912
1913 if (ret == 0)
1914 {
1915 page_rw.page_rw = 0x00U; /* page_write disable */
1916 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
1917 }
1918
1919 if (ret == 0)
1920 {
1921 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
1922 }
1923
1924 return ret;
1925 }
1926
1927 /**
1928 * @brief Read a line(byte) in a page.[get]
1929 *
1930 * @param ctx Read / write interface definitions.(ptr)
1931 * @param add Page line address.
1932 * @param val Read value.(ptr)
1933 * @retval Interface status (MANDATORY: return 0 -> no Error).
1934 *
1935 */
lsm6dsr_ln_pg_read_byte(stmdev_ctx_t * ctx,uint16_t add,uint8_t * val)1936 int32_t lsm6dsr_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t add,
1937 uint8_t *val)
1938 {
1939 lsm6dsr_page_rw_t page_rw;
1940 lsm6dsr_page_sel_t page_sel;
1941 lsm6dsr_page_address_t page_address;
1942 int32_t ret;
1943
1944 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
1945
1946 if (ret == 0)
1947 {
1948 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
1949 }
1950
1951 if (ret == 0)
1952 {
1953 page_rw.page_rw = 0x01U; /* page_read enable*/
1954 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
1955 }
1956
1957 if (ret == 0)
1958 {
1959 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_SEL, (uint8_t *)&page_sel, 1);
1960 }
1961
1962 if (ret == 0)
1963 {
1964 page_sel.page_sel = (uint8_t)((add >> 8) & 0x0FU);
1965 page_sel.not_used_01 = 1;
1966 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_SEL,
1967 (uint8_t *)&page_sel, 1);
1968 }
1969
1970 if (ret == 0)
1971 {
1972 page_address.page_addr = (uint8_t)(add & 0x00FFU);
1973 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_ADDRESS,
1974 (uint8_t *)&page_address, 1);
1975 }
1976
1977 if (ret == 0)
1978 {
1979 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_VALUE, val, 2);
1980 }
1981
1982 if (ret == 0)
1983 {
1984 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
1985 }
1986
1987 if (ret == 0)
1988 {
1989 page_rw.page_rw = 0x00U; /* page_read disable */
1990 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
1991 }
1992
1993 if (ret == 0)
1994 {
1995 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
1996 }
1997
1998 return ret;
1999 }
2000
2001 /**
2002 * @brief Data-ready pulsed / letched mode.[set]
2003 *
2004 * @param ctx Read / write interface definitions.(ptr)
2005 * @param val Change the values of dataready_pulsed in
2006 * reg COUNTER_BDR_REG1
2007 * @retval Interface status (MANDATORY: return 0 -> no Error).
2008 *
2009 */
lsm6dsr_data_ready_mode_set(stmdev_ctx_t * ctx,lsm6dsr_dataready_pulsed_t val)2010 int32_t lsm6dsr_data_ready_mode_set(stmdev_ctx_t *ctx,
2011 lsm6dsr_dataready_pulsed_t val)
2012 {
2013 lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1;
2014 int32_t ret;
2015
2016 ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
2017 (uint8_t *)&counter_bdr_reg1, 1);
2018
2019 if (ret == 0)
2020 {
2021 counter_bdr_reg1.dataready_pulsed = (uint8_t)val;
2022 ret = lsm6dsr_write_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
2023 (uint8_t *)&counter_bdr_reg1, 1);
2024 }
2025
2026 return ret;
2027 }
2028
2029 /**
2030 * @brief Data-ready pulsed / letched mode.[get]
2031 *
2032 * @param ctx Read / write interface definitions.(ptr)
2033 * @param val Get the values of dataready_pulsed in
2034 * reg COUNTER_BDR_REG1
2035 * @retval Interface status (MANDATORY: return 0 -> no Error).
2036 *
2037 */
lsm6dsr_data_ready_mode_get(stmdev_ctx_t * ctx,lsm6dsr_dataready_pulsed_t * val)2038 int32_t lsm6dsr_data_ready_mode_get(stmdev_ctx_t *ctx,
2039 lsm6dsr_dataready_pulsed_t *val)
2040 {
2041 lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1;
2042 int32_t ret;
2043
2044 ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
2045 (uint8_t *)&counter_bdr_reg1, 1);
2046
2047 switch (counter_bdr_reg1.dataready_pulsed)
2048 {
2049 case LSM6DSR_DRDY_LATCHED:
2050 *val = LSM6DSR_DRDY_LATCHED;
2051 break;
2052
2053 case LSM6DSR_DRDY_PULSED:
2054 *val = LSM6DSR_DRDY_PULSED;
2055 break;
2056
2057 default:
2058 *val = LSM6DSR_DRDY_LATCHED;
2059 break;
2060 }
2061
2062 return ret;
2063 }
2064
2065 /**
2066 * @brief Device Who am I.[get]
2067 *
2068 * @param ctx Read / write interface definitions.(ptr)
2069 * @param buff Buffer that stores data read
2070 * @retval Interface status (MANDATORY: return 0 -> no Error).
2071 *
2072 */
lsm6dsr_device_id_get(stmdev_ctx_t * ctx,uint8_t * buff)2073 int32_t lsm6dsr_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
2074 {
2075 int32_t ret;
2076
2077 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WHO_AM_I, buff, 1);
2078
2079 return ret;
2080 }
2081
2082 /**
2083 * @brief Software reset. Restore the default values in user registers.[set]
2084 *
2085 * @param ctx Read / write interface definitions.(ptr)
2086 * @param val Change the values of sw_reset in reg CTRL3_C
2087 * @retval Interface status (MANDATORY: return 0 -> no Error).
2088 *
2089 */
lsm6dsr_reset_set(stmdev_ctx_t * ctx,uint8_t val)2090 int32_t lsm6dsr_reset_set(stmdev_ctx_t *ctx, uint8_t val)
2091 {
2092 lsm6dsr_ctrl3_c_t ctrl3_c;
2093 int32_t ret;
2094
2095 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2096
2097 if (ret == 0)
2098 {
2099 ctrl3_c.sw_reset = (uint8_t)val;
2100 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2101 }
2102
2103 return ret;
2104 }
2105
2106 /**
2107 * @brief Software reset. Restore the default values in user registers.[get]
2108 *
2109 * @param ctx Read / write interface definitions.(ptr)
2110 * @param val Change the values of sw_reset in reg CTRL3_C
2111 * @retval Interface status (MANDATORY: return 0 -> no Error).
2112 *
2113 */
lsm6dsr_reset_get(stmdev_ctx_t * ctx,uint8_t * val)2114 int32_t lsm6dsr_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
2115 {
2116 lsm6dsr_ctrl3_c_t ctrl3_c;
2117 int32_t ret;
2118
2119 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2120 *val = ctrl3_c.sw_reset;
2121
2122 return ret;
2123 }
2124
2125 /**
2126 * @brief Register address automatically incremented during a multiple byte
2127 * access with a serial interface.[set]
2128 *
2129 * @param ctx Read / write interface definitions.(ptr)
2130 * @param val Change the values of if_inc in reg CTRL3_C
2131 * @retval Interface status (MANDATORY: return 0 -> no Error).
2132 *
2133 */
lsm6dsr_auto_increment_set(stmdev_ctx_t * ctx,uint8_t val)2134 int32_t lsm6dsr_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
2135 {
2136 lsm6dsr_ctrl3_c_t ctrl3_c;
2137 int32_t ret;
2138
2139 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2140
2141 if (ret == 0)
2142 {
2143 ctrl3_c.if_inc = (uint8_t)val;
2144 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2145 }
2146
2147 return ret;
2148 }
2149
2150 /**
2151 * @brief Register address automatically incremented during a multiple byte
2152 * access with a serial interface.[get]
2153 *
2154 * @param ctx Read / write interface definitions.(ptr)
2155 * @param val Change the values of if_inc in reg CTRL3_C
2156 * @retval Interface status (MANDATORY: return 0 -> no Error).
2157 *
2158 */
lsm6dsr_auto_increment_get(stmdev_ctx_t * ctx,uint8_t * val)2159 int32_t lsm6dsr_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
2160 {
2161 lsm6dsr_ctrl3_c_t ctrl3_c;
2162 int32_t ret;
2163
2164 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2165 *val = ctrl3_c.if_inc;
2166
2167 return ret;
2168 }
2169
2170 /**
2171 * @brief Reboot memory content. Reload the calibration parameters.[set]
2172 *
2173 * @param ctx Read / write interface definitions.(ptr)
2174 * @param val Change the values of boot in reg CTRL3_C
2175 * @retval Interface status (MANDATORY: return 0 -> no Error).
2176 *
2177 */
lsm6dsr_boot_set(stmdev_ctx_t * ctx,uint8_t val)2178 int32_t lsm6dsr_boot_set(stmdev_ctx_t *ctx, uint8_t val)
2179 {
2180 lsm6dsr_ctrl3_c_t ctrl3_c;
2181 int32_t ret;
2182
2183 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2184
2185 if (ret == 0)
2186 {
2187 ctrl3_c.boot = (uint8_t)val;
2188 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2189 }
2190
2191 return ret;
2192 }
2193
2194 /**
2195 * @brief Reboot memory content. Reload the calibration parameters.[get]
2196 *
2197 * @param ctx Read / write interface definitions.(ptr)
2198 * @param val Change the values of boot in reg CTRL3_C
2199 * @retval Interface status (MANDATORY: return 0 -> no Error).
2200 *
2201 */
lsm6dsr_boot_get(stmdev_ctx_t * ctx,uint8_t * val)2202 int32_t lsm6dsr_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
2203 {
2204 lsm6dsr_ctrl3_c_t ctrl3_c;
2205 int32_t ret;
2206
2207 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2208 *val = ctrl3_c.boot;
2209
2210 return ret;
2211 }
2212
2213
2214
2215 /**
2216 * @brief Linear acceleration sensor self-test enable.[set]
2217 *
2218 * @param ctx Read / write interface definitions.(ptr)
2219 * @param val Change the values of st_xl in reg CTRL5_C
2220 * @retval Interface status (MANDATORY: return 0 -> no Error).
2221 *
2222 */
lsm6dsr_xl_self_test_set(stmdev_ctx_t * ctx,lsm6dsr_st_xl_t val)2223 int32_t lsm6dsr_xl_self_test_set(stmdev_ctx_t *ctx,
2224 lsm6dsr_st_xl_t val)
2225 {
2226 lsm6dsr_ctrl5_c_t ctrl5_c;
2227 int32_t ret;
2228
2229 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2230
2231 if (ret == 0)
2232 {
2233 ctrl5_c.st_xl = (uint8_t)val;
2234 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2235 }
2236
2237 return ret;
2238 }
2239
2240 /**
2241 * @brief Linear acceleration sensor self-test enable.[get]
2242 *
2243 * @param ctx Read / write interface definitions.(ptr)
2244 * @param val Get the values of st_xl in reg CTRL5_C
2245 * @retval Interface status (MANDATORY: return 0 -> no Error).
2246 *
2247 */
lsm6dsr_xl_self_test_get(stmdev_ctx_t * ctx,lsm6dsr_st_xl_t * val)2248 int32_t lsm6dsr_xl_self_test_get(stmdev_ctx_t *ctx,
2249 lsm6dsr_st_xl_t *val)
2250 {
2251 lsm6dsr_ctrl5_c_t ctrl5_c;
2252 int32_t ret;
2253
2254 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2255
2256 switch (ctrl5_c.st_xl)
2257 {
2258 case LSM6DSR_XL_ST_DISABLE:
2259 *val = LSM6DSR_XL_ST_DISABLE;
2260 break;
2261
2262 case LSM6DSR_XL_ST_POSITIVE:
2263 *val = LSM6DSR_XL_ST_POSITIVE;
2264 break;
2265
2266 case LSM6DSR_XL_ST_NEGATIVE:
2267 *val = LSM6DSR_XL_ST_NEGATIVE;
2268 break;
2269
2270 default:
2271 *val = LSM6DSR_XL_ST_DISABLE;
2272 break;
2273 }
2274
2275 return ret;
2276 }
2277
2278 /**
2279 * @brief Angular rate sensor self-test enable.[set]
2280 *
2281 * @param ctx Read / write interface definitions.(ptr)
2282 * @param val Change the values of st_g in reg CTRL5_C
2283 * @retval Interface status (MANDATORY: return 0 -> no Error).
2284 *
2285 */
lsm6dsr_gy_self_test_set(stmdev_ctx_t * ctx,lsm6dsr_st_g_t val)2286 int32_t lsm6dsr_gy_self_test_set(stmdev_ctx_t *ctx,
2287 lsm6dsr_st_g_t val)
2288 {
2289 lsm6dsr_ctrl5_c_t ctrl5_c;
2290 int32_t ret;
2291
2292 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2293
2294 if (ret == 0)
2295 {
2296 ctrl5_c.st_g = (uint8_t)val;
2297 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2298 }
2299
2300 return ret;
2301 }
2302
2303 /**
2304 * @brief Angular rate sensor self-test enable.[get]
2305 *
2306 * @param ctx Read / write interface definitions.(ptr)
2307 * @param val Get the values of st_g in reg CTRL5_C
2308 * @retval Interface status (MANDATORY: return 0 -> no Error).
2309 *
2310 */
lsm6dsr_gy_self_test_get(stmdev_ctx_t * ctx,lsm6dsr_st_g_t * val)2311 int32_t lsm6dsr_gy_self_test_get(stmdev_ctx_t *ctx,
2312 lsm6dsr_st_g_t *val)
2313 {
2314 lsm6dsr_ctrl5_c_t ctrl5_c;
2315 int32_t ret;
2316
2317 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
2318
2319 switch (ctrl5_c.st_g)
2320 {
2321 case LSM6DSR_GY_ST_DISABLE:
2322 *val = LSM6DSR_GY_ST_DISABLE;
2323 break;
2324
2325 case LSM6DSR_GY_ST_POSITIVE:
2326 *val = LSM6DSR_GY_ST_POSITIVE;
2327 break;
2328
2329 case LSM6DSR_GY_ST_NEGATIVE:
2330 *val = LSM6DSR_GY_ST_NEGATIVE;
2331 break;
2332
2333 default:
2334 *val = LSM6DSR_GY_ST_DISABLE;
2335 break;
2336 }
2337
2338 return ret;
2339 }
2340
2341 /**
2342 * @}
2343 *
2344 */
2345
2346 /**
2347 * @defgroup LSM6DSR_filters
2348 * @brief This section group all the functions concerning the
2349 * filters configuration
2350 * @{
2351 *
2352 */
2353
2354 /**
2355 * @brief Accelerometer output from LPF2 filtering stage selection.[set]
2356 *
2357 * @param ctx Read / write interface definitions.(ptr)
2358 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
2359 * @retval Interface status (MANDATORY: return 0 -> no Error).
2360 *
2361 */
lsm6dsr_xl_filter_lp2_set(stmdev_ctx_t * ctx,uint8_t val)2362 int32_t lsm6dsr_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
2363 {
2364 lsm6dsr_ctrl1_xl_t ctrl1_xl;
2365 int32_t ret;
2366
2367 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2368
2369 if (ret == 0)
2370 {
2371 ctrl1_xl.lpf2_xl_en = (uint8_t)val;
2372 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_XL,
2373 (uint8_t *)&ctrl1_xl, 1);
2374 }
2375
2376 return ret;
2377 }
2378
2379 /**
2380 * @brief Accelerometer output from LPF2 filtering stage selection.[get]
2381 *
2382 * @param ctx Read / write interface definitions.(ptr)
2383 * @param val Change the values of lpf2_xl_en in reg CTRL1_XL
2384 * @retval Interface status (MANDATORY: return 0 -> no Error).
2385 *
2386 */
lsm6dsr_xl_filter_lp2_get(stmdev_ctx_t * ctx,uint8_t * val)2387 int32_t lsm6dsr_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
2388 {
2389 lsm6dsr_ctrl1_xl_t ctrl1_xl;
2390 int32_t ret;
2391
2392 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2393 *val = ctrl1_xl.lpf2_xl_en;
2394
2395 return ret;
2396 }
2397
2398 /**
2399 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2400 * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[set]
2401 *
2402 * @param ctx Read / write interface definitions.(ptr)
2403 * @param val Change the values of lpf1_sel_g in reg CTRL4_C
2404 * @retval Interface status (MANDATORY: return 0 -> no Error).
2405 *
2406 */
lsm6dsr_gy_filter_lp1_set(stmdev_ctx_t * ctx,uint8_t val)2407 int32_t lsm6dsr_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
2408 {
2409 lsm6dsr_ctrl4_c_t ctrl4_c;
2410 int32_t ret;
2411
2412 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2413
2414 if (ret == 0)
2415 {
2416 ctrl4_c.lpf1_sel_g = (uint8_t)val;
2417 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2418 }
2419
2420 return ret;
2421 }
2422
2423 /**
2424 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2425 * the bandwidth can be selected through FTYPE [2:0] in CTRL6_C.[get]
2426 *
2427 * @param ctx Read / write interface definitions.(ptr)
2428 * @param val Change the values of lpf1_sel_g in reg CTRL4_C
2429 * @retval Interface status (MANDATORY: return 0 -> no Error).
2430 *
2431 */
lsm6dsr_gy_filter_lp1_get(stmdev_ctx_t * ctx,uint8_t * val)2432 int32_t lsm6dsr_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
2433 {
2434 lsm6dsr_ctrl4_c_t ctrl4_c;
2435 int32_t ret;
2436
2437 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2438 *val = ctrl4_c.lpf1_sel_g;
2439
2440 return ret;
2441 }
2442
2443 /**
2444 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2445 * (XL and Gyro independently masked).[set]
2446 *
2447 * @param ctx Read / write interface definitions.(ptr)
2448 * @param val Change the values of drdy_mask in reg CTRL4_C
2449 * @retval Interface status (MANDATORY: return 0 -> no Error).
2450 *
2451 */
lsm6dsr_filter_settling_mask_set(stmdev_ctx_t * ctx,uint8_t val)2452 int32_t lsm6dsr_filter_settling_mask_set(stmdev_ctx_t *ctx,
2453 uint8_t val)
2454 {
2455 lsm6dsr_ctrl4_c_t ctrl4_c;
2456 int32_t ret;
2457
2458 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2459
2460 if (ret == 0)
2461 {
2462 ctrl4_c.drdy_mask = (uint8_t)val;
2463 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2464 }
2465
2466 return ret;
2467 }
2468
2469 /**
2470 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2471 * (XL and Gyro independently masked).[get]
2472 *
2473 * @param ctx Read / write interface definitions.(ptr)
2474 * @param val Change the values of drdy_mask in reg CTRL4_C
2475 * @retval Interface status (MANDATORY: return 0 -> no Error).
2476 *
2477 */
lsm6dsr_filter_settling_mask_get(stmdev_ctx_t * ctx,uint8_t * val)2478 int32_t lsm6dsr_filter_settling_mask_get(stmdev_ctx_t *ctx,
2479 uint8_t *val)
2480 {
2481 lsm6dsr_ctrl4_c_t ctrl4_c;
2482 int32_t ret;
2483
2484 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2485 *val = ctrl4_c.drdy_mask;
2486
2487 return ret;
2488 }
2489
2490 /**
2491 * @brief Gyroscope low pass filter 1 bandwidth.[set]
2492 *
2493 * @param ctx Read / write interface definitions.(ptr)
2494 * @param val Change the values of ftype in reg CTRL6_C
2495 * @retval Interface status (MANDATORY: return 0 -> no Error).
2496 *
2497 */
lsm6dsr_gy_lp1_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsr_ftype_t val)2498 int32_t lsm6dsr_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
2499 lsm6dsr_ftype_t val)
2500 {
2501 lsm6dsr_ctrl6_c_t ctrl6_c;
2502 int32_t ret;
2503
2504 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2505
2506 if (ret == 0)
2507 {
2508 ctrl6_c.ftype = (uint8_t)val;
2509 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2510 }
2511
2512 return ret;
2513 }
2514
2515 /**
2516 * @brief Gyroscope low pass filter 1 bandwidth.[get]
2517 *
2518 * @param ctx Read / write interface definitions.(ptr)
2519 * @param val Get the values of ftype in reg CTRL6_C
2520 * @retval Interface status (MANDATORY: return 0 -> no Error).
2521 *
2522 */
lsm6dsr_gy_lp1_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsr_ftype_t * val)2523 int32_t lsm6dsr_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
2524 lsm6dsr_ftype_t *val)
2525 {
2526 lsm6dsr_ctrl6_c_t ctrl6_c;
2527 int32_t ret;
2528
2529 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2530
2531 switch (ctrl6_c.ftype)
2532 {
2533 case LSM6DSR_ULTRA_LIGHT:
2534 *val = LSM6DSR_ULTRA_LIGHT;
2535 break;
2536
2537 case LSM6DSR_VERY_LIGHT:
2538 *val = LSM6DSR_VERY_LIGHT;
2539 break;
2540
2541 case LSM6DSR_LIGHT:
2542 *val = LSM6DSR_LIGHT;
2543 break;
2544
2545 case LSM6DSR_MEDIUM:
2546 *val = LSM6DSR_MEDIUM;
2547 break;
2548
2549 case LSM6DSR_STRONG:
2550 *val = LSM6DSR_STRONG;
2551 break;
2552
2553 case LSM6DSR_VERY_STRONG:
2554 *val = LSM6DSR_VERY_STRONG;
2555 break;
2556
2557 case LSM6DSR_AGGRESSIVE:
2558 *val = LSM6DSR_AGGRESSIVE;
2559 break;
2560
2561 case LSM6DSR_XTREME:
2562 *val = LSM6DSR_XTREME;
2563 break;
2564
2565 default:
2566 *val = LSM6DSR_ULTRA_LIGHT;
2567 break;
2568 }
2569
2570 return ret;
2571 }
2572
2573 /**
2574 * @brief Low pass filter 2 on 6D function selection.[set]
2575 *
2576 * @param ctx Read / write interface definitions.(ptr)
2577 * @param val Change the values of low_pass_on_6d in reg CTRL8_XL
2578 * @retval Interface status (MANDATORY: return 0 -> no Error).
2579 *
2580 */
lsm6dsr_xl_lp2_on_6d_set(stmdev_ctx_t * ctx,uint8_t val)2581 int32_t lsm6dsr_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
2582 {
2583 lsm6dsr_ctrl8_xl_t ctrl8_xl;
2584 int32_t ret;
2585
2586 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2587
2588 if (ret == 0)
2589 {
2590 ctrl8_xl.low_pass_on_6d = (uint8_t)val;
2591 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL8_XL,
2592 (uint8_t *)&ctrl8_xl, 1);
2593 }
2594
2595 return ret;
2596 }
2597
2598 /**
2599 * @brief Low pass filter 2 on 6D function selection.[get]
2600 *
2601 * @param ctx Read / write interface definitions.(ptr)
2602 * @param val Change the values of low_pass_on_6d in reg CTRL8_XL
2603 * @retval Interface status (MANDATORY: return 0 -> no Error).
2604 *
2605 */
lsm6dsr_xl_lp2_on_6d_get(stmdev_ctx_t * ctx,uint8_t * val)2606 int32_t lsm6dsr_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
2607 {
2608 lsm6dsr_ctrl8_xl_t ctrl8_xl;
2609 int32_t ret;
2610
2611 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2612 *val = ctrl8_xl.low_pass_on_6d;
2613
2614 return ret;
2615 }
2616
2617 /**
2618 * @brief Accelerometer slope filter / high-pass filter selection
2619 * on output.[set]
2620 *
2621 * @param ctx Read / write interface definitions.(ptr)
2622 * @param val Change the values of hp_slope_xl_en in reg CTRL8_XL
2623 * @retval Interface status (MANDATORY: return 0 -> no Error).
2624 *
2625 */
lsm6dsr_xl_hp_path_on_out_set(stmdev_ctx_t * ctx,lsm6dsr_hp_slope_xl_en_t val)2626 int32_t lsm6dsr_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
2627 lsm6dsr_hp_slope_xl_en_t val)
2628 {
2629 lsm6dsr_ctrl8_xl_t ctrl8_xl;
2630 int32_t ret;
2631
2632 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2633
2634 if (ret == 0)
2635 {
2636 ctrl8_xl.hp_slope_xl_en = (((uint8_t)val & 0x10U) >> 4);
2637 ctrl8_xl.hp_ref_mode_xl = (((uint8_t)val & 0x20U) >> 5);
2638 ctrl8_xl.hpcf_xl = (uint8_t)val & 0x07U;
2639 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL8_XL,
2640 (uint8_t *)&ctrl8_xl, 1);
2641 }
2642
2643 return ret;
2644 }
2645
2646 /**
2647 * @brief Accelerometer slope filter / high-pass filter selection on
2648 * output.[get]
2649 *
2650 * @param ctx Read / write interface definitions.(ptr)
2651 * @param val Get the values of hp_slope_xl_en in reg CTRL8_XL
2652 * @retval Interface status (MANDATORY: return 0 -> no Error).
2653 *
2654 */
lsm6dsr_xl_hp_path_on_out_get(stmdev_ctx_t * ctx,lsm6dsr_hp_slope_xl_en_t * val)2655 int32_t lsm6dsr_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
2656 lsm6dsr_hp_slope_xl_en_t *val)
2657 {
2658 lsm6dsr_ctrl8_xl_t ctrl8_xl;
2659 int32_t ret;
2660
2661 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2662
2663 switch (((ctrl8_xl.hp_ref_mode_xl << 5) + (ctrl8_xl.hp_slope_xl_en <<
2664 4) +
2665 ctrl8_xl.hpcf_xl))
2666 {
2667 case LSM6DSR_HP_PATH_DISABLE_ON_OUT:
2668 *val = LSM6DSR_HP_PATH_DISABLE_ON_OUT;
2669 break;
2670
2671 case LSM6DSR_SLOPE_ODR_DIV_4:
2672 *val = LSM6DSR_SLOPE_ODR_DIV_4;
2673 break;
2674
2675 case LSM6DSR_HP_ODR_DIV_10:
2676 *val = LSM6DSR_HP_ODR_DIV_10;
2677 break;
2678
2679 case LSM6DSR_HP_ODR_DIV_20:
2680 *val = LSM6DSR_HP_ODR_DIV_20;
2681 break;
2682
2683 case LSM6DSR_HP_ODR_DIV_45:
2684 *val = LSM6DSR_HP_ODR_DIV_45;
2685 break;
2686
2687 case LSM6DSR_HP_ODR_DIV_100:
2688 *val = LSM6DSR_HP_ODR_DIV_100;
2689 break;
2690
2691 case LSM6DSR_HP_ODR_DIV_200:
2692 *val = LSM6DSR_HP_ODR_DIV_200;
2693 break;
2694
2695 case LSM6DSR_HP_ODR_DIV_400:
2696 *val = LSM6DSR_HP_ODR_DIV_400;
2697 break;
2698
2699 case LSM6DSR_HP_ODR_DIV_800:
2700 *val = LSM6DSR_HP_ODR_DIV_800;
2701 break;
2702
2703 case LSM6DSR_HP_REF_MD_ODR_DIV_10:
2704 *val = LSM6DSR_HP_REF_MD_ODR_DIV_10;
2705 break;
2706
2707 case LSM6DSR_HP_REF_MD_ODR_DIV_20:
2708 *val = LSM6DSR_HP_REF_MD_ODR_DIV_20;
2709 break;
2710
2711 case LSM6DSR_HP_REF_MD_ODR_DIV_45:
2712 *val = LSM6DSR_HP_REF_MD_ODR_DIV_45;
2713 break;
2714
2715 case LSM6DSR_HP_REF_MD_ODR_DIV_100:
2716 *val = LSM6DSR_HP_REF_MD_ODR_DIV_100;
2717 break;
2718
2719 case LSM6DSR_HP_REF_MD_ODR_DIV_200:
2720 *val = LSM6DSR_HP_REF_MD_ODR_DIV_200;
2721 break;
2722
2723 case LSM6DSR_HP_REF_MD_ODR_DIV_400:
2724 *val = LSM6DSR_HP_REF_MD_ODR_DIV_400;
2725 break;
2726
2727 case LSM6DSR_HP_REF_MD_ODR_DIV_800:
2728 *val = LSM6DSR_HP_REF_MD_ODR_DIV_800;
2729 break;
2730
2731 case LSM6DSR_LP_ODR_DIV_10:
2732 *val = LSM6DSR_LP_ODR_DIV_10;
2733 break;
2734
2735 case LSM6DSR_LP_ODR_DIV_20:
2736 *val = LSM6DSR_LP_ODR_DIV_20;
2737 break;
2738
2739 case LSM6DSR_LP_ODR_DIV_45:
2740 *val = LSM6DSR_LP_ODR_DIV_45;
2741 break;
2742
2743 case LSM6DSR_LP_ODR_DIV_100:
2744 *val = LSM6DSR_LP_ODR_DIV_100;
2745 break;
2746
2747 case LSM6DSR_LP_ODR_DIV_200:
2748 *val = LSM6DSR_LP_ODR_DIV_200;
2749 break;
2750
2751 case LSM6DSR_LP_ODR_DIV_400:
2752 *val = LSM6DSR_LP_ODR_DIV_400;
2753 break;
2754
2755 case LSM6DSR_LP_ODR_DIV_800:
2756 *val = LSM6DSR_LP_ODR_DIV_800;
2757 break;
2758
2759 default:
2760 *val = LSM6DSR_HP_PATH_DISABLE_ON_OUT;
2761 break;
2762 }
2763
2764 return ret;
2765 }
2766
2767 /**
2768 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2769 * The filter sets the second samples after writing this bit.
2770 * Active only during device exit from powerdown mode.[set]
2771 *
2772 * @param ctx Read / write interface definitions.(ptr)
2773 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
2774 * @retval Interface status (MANDATORY: return 0 -> no Error).
2775 *
2776 */
lsm6dsr_xl_fast_settling_set(stmdev_ctx_t * ctx,uint8_t val)2777 int32_t lsm6dsr_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
2778 {
2779 lsm6dsr_ctrl8_xl_t ctrl8_xl;
2780 int32_t ret;
2781
2782 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2783
2784 if (ret == 0)
2785 {
2786 ctrl8_xl.fastsettl_mode_xl = (uint8_t)val;
2787 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL8_XL,
2788 (uint8_t *)&ctrl8_xl, 1);
2789 }
2790
2791 return ret;
2792 }
2793
2794 /**
2795 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2796 * The filter sets the second samples after writing
2797 * this bit. Active only during device exit from powerdown mode.[get]
2798 *
2799 * @param ctx Read / write interface definitions.(ptr)
2800 * @param val Change the values of fastsettl_mode_xl in reg CTRL8_XL
2801 * @retval Interface status (MANDATORY: return 0 -> no Error).
2802 *
2803 */
lsm6dsr_xl_fast_settling_get(stmdev_ctx_t * ctx,uint8_t * val)2804 int32_t lsm6dsr_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
2805 {
2806 lsm6dsr_ctrl8_xl_t ctrl8_xl;
2807 int32_t ret;
2808
2809 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2810 *val = ctrl8_xl.fastsettl_mode_xl;
2811
2812 return ret;
2813 }
2814
2815 /**
2816 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2817 * functions.[set]
2818 *
2819 * @param ctx Read / write interface definitions.(ptr)
2820 * @param val Change the values of slope_fds in reg TAP_CFG0
2821 * @retval Interface status (MANDATORY: return 0 -> no Error).
2822 *
2823 */
lsm6dsr_xl_hp_path_internal_set(stmdev_ctx_t * ctx,lsm6dsr_slope_fds_t val)2824 int32_t lsm6dsr_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
2825 lsm6dsr_slope_fds_t val)
2826 {
2827 lsm6dsr_tap_cfg0_t tap_cfg0;
2828 int32_t ret;
2829
2830 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2831
2832 if (ret == 0)
2833 {
2834 tap_cfg0.slope_fds = (uint8_t)val;
2835 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG0,
2836 (uint8_t *)&tap_cfg0, 1);
2837 }
2838
2839 return ret;
2840 }
2841
2842 /**
2843 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2844 * functions.[get]
2845 *
2846 * @param ctx Read / write interface definitions.(ptr)
2847 * @param val Get the values of slope_fds in reg TAP_CFG0
2848 * @retval Interface status (MANDATORY: return 0 -> no Error).
2849 *
2850 */
lsm6dsr_xl_hp_path_internal_get(stmdev_ctx_t * ctx,lsm6dsr_slope_fds_t * val)2851 int32_t lsm6dsr_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
2852 lsm6dsr_slope_fds_t *val)
2853 {
2854 lsm6dsr_tap_cfg0_t tap_cfg0;
2855 int32_t ret;
2856
2857 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
2858
2859 switch (tap_cfg0.slope_fds)
2860 {
2861 case LSM6DSR_USE_SLOPE:
2862 *val = LSM6DSR_USE_SLOPE;
2863 break;
2864
2865 case LSM6DSR_USE_HPF:
2866 *val = LSM6DSR_USE_HPF;
2867 break;
2868
2869 default:
2870 *val = LSM6DSR_USE_SLOPE;
2871 break;
2872 }
2873
2874 return ret;
2875 }
2876
2877 /**
2878 * @brief Enables gyroscope digital high-pass filter. The filter is enabled
2879 * only if the gyro is in HP mode.[set]
2880 *
2881 * @param ctx Read / write interface definitions.(ptr)
2882 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
2883 * @retval Interface status (MANDATORY: return 0 -> no Error).
2884 *
2885 */
lsm6dsr_gy_hp_path_internal_set(stmdev_ctx_t * ctx,lsm6dsr_hpm_g_t val)2886 int32_t lsm6dsr_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
2887 lsm6dsr_hpm_g_t val)
2888 {
2889 lsm6dsr_ctrl7_g_t ctrl7_g;
2890 int32_t ret;
2891
2892 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2893
2894 if (ret == 0)
2895 {
2896 ctrl7_g.hp_en_g = (((uint8_t)val & 0x80U) >> 7);
2897 ctrl7_g.hpm_g = (uint8_t)val & 0x03U;
2898 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2899 }
2900
2901 return ret;
2902 }
2903
2904 /**
2905 * @brief Enables gyroscope digital high-pass filter. The filter is
2906 * enabled only if the gyro is in HP mode.[get]
2907 *
2908 * @param ctx Read / write interface definitions.(ptr)
2909 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
2910 * @retval Interface status (MANDATORY: return 0 -> no Error).
2911 *
2912 */
lsm6dsr_gy_hp_path_internal_get(stmdev_ctx_t * ctx,lsm6dsr_hpm_g_t * val)2913 int32_t lsm6dsr_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
2914 lsm6dsr_hpm_g_t *val)
2915 {
2916 lsm6dsr_ctrl7_g_t ctrl7_g;
2917 int32_t ret;
2918
2919 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2920
2921 switch ((ctrl7_g.hp_en_g << 7) + ctrl7_g.hpm_g)
2922 {
2923 case LSM6DSR_HP_FILTER_NONE:
2924 *val = LSM6DSR_HP_FILTER_NONE;
2925 break;
2926
2927 case LSM6DSR_HP_FILTER_16mHz:
2928 *val = LSM6DSR_HP_FILTER_16mHz;
2929 break;
2930
2931 case LSM6DSR_HP_FILTER_65mHz:
2932 *val = LSM6DSR_HP_FILTER_65mHz;
2933 break;
2934
2935 case LSM6DSR_HP_FILTER_260mHz:
2936 *val = LSM6DSR_HP_FILTER_260mHz;
2937 break;
2938
2939 case LSM6DSR_HP_FILTER_1Hz04:
2940 *val = LSM6DSR_HP_FILTER_1Hz04;
2941 break;
2942
2943 default:
2944 *val = LSM6DSR_HP_FILTER_NONE;
2945 break;
2946 }
2947
2948 return ret;
2949 }
2950
2951 /**
2952 * @}
2953 *
2954 */
2955
2956 /**
2957 * @defgroup LSM6DSR_ Auxiliary_interface
2958 * @brief This section groups all the functions concerning
2959 * auxiliary interface.
2960 * @{
2961 *
2962 */
2963
2964 /**
2965 * @brief On auxiliary interface connect/disconnect SDO and OCS
2966 * internal pull-up.[set]
2967 *
2968 * @param ctx Read / write interface definitions.(ptr)
2969 * @param val Change the values of ois_pu_dis in reg PIN_CTRL
2970 * @retval Interface status (MANDATORY: return 0 -> no Error).
2971 *
2972 */
lsm6dsr_aux_sdo_ocs_mode_set(stmdev_ctx_t * ctx,lsm6dsr_ois_pu_dis_t val)2973 int32_t lsm6dsr_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
2974 lsm6dsr_ois_pu_dis_t val)
2975 {
2976 lsm6dsr_pin_ctrl_t pin_ctrl;
2977 int32_t ret;
2978
2979 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
2980
2981 if (ret == 0)
2982 {
2983 pin_ctrl.ois_pu_dis = (uint8_t)val;
2984 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PIN_CTRL,
2985 (uint8_t *)&pin_ctrl, 1);
2986 }
2987
2988 return ret;
2989 }
2990
2991 /**
2992 * @brief On auxiliary interface connect/disconnect SDO and OCS
2993 * internal pull-up.[get]
2994 *
2995 * @param ctx Read / write interface definitions.(ptr)
2996 * @param val Get the values of ois_pu_dis in reg PIN_CTRL
2997 * @retval Interface status (MANDATORY: return 0 -> no Error).
2998 *
2999 */
lsm6dsr_aux_sdo_ocs_mode_get(stmdev_ctx_t * ctx,lsm6dsr_ois_pu_dis_t * val)3000 int32_t lsm6dsr_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
3001 lsm6dsr_ois_pu_dis_t *val)
3002 {
3003 lsm6dsr_pin_ctrl_t pin_ctrl;
3004 int32_t ret;
3005
3006 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
3007
3008 switch (pin_ctrl.ois_pu_dis)
3009 {
3010 case LSM6DSR_AUX_PULL_UP_DISC:
3011 *val = LSM6DSR_AUX_PULL_UP_DISC;
3012 break;
3013
3014 case LSM6DSR_AUX_PULL_UP_CONNECT:
3015 *val = LSM6DSR_AUX_PULL_UP_CONNECT;
3016 break;
3017
3018 default:
3019 *val = LSM6DSR_AUX_PULL_UP_DISC;
3020 break;
3021 }
3022
3023 return ret;
3024 }
3025
3026 /**
3027 * @brief OIS chain on aux interface power on mode.[set]
3028 *
3029 * @param ctx Read / write interface definitions.(ptr)
3030 * @param val Change the values of ois_on in reg CTRL7_G
3031 * @retval Interface status (MANDATORY: return 0 -> no Error).
3032 *
3033 */
lsm6dsr_aux_pw_on_ctrl_set(stmdev_ctx_t * ctx,lsm6dsr_ois_on_t val)3034 int32_t lsm6dsr_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
3035 lsm6dsr_ois_on_t val)
3036 {
3037 lsm6dsr_ctrl7_g_t ctrl7_g;
3038 int32_t ret;
3039
3040 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
3041
3042 if (ret == 0)
3043 {
3044 ctrl7_g.ois_on_en = (uint8_t)val & 0x01U;
3045 ctrl7_g.ois_on = (uint8_t)val & 0x01U;
3046 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
3047 }
3048
3049 return ret;
3050 }
3051
3052 /**
3053 * @brief OIS chain on aux interface power on mode[get]
3054 *
3055 * @param ctx Read / write interface definitions.(ptr)
3056 * @param val Get the values of ois_on in reg CTRL7_G
3057 * @retval Interface status (MANDATORY: return 0 -> no Error).
3058 *
3059 */
lsm6dsr_aux_pw_on_ctrl_get(stmdev_ctx_t * ctx,lsm6dsr_ois_on_t * val)3060 int32_t lsm6dsr_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
3061 lsm6dsr_ois_on_t *val)
3062 {
3063 lsm6dsr_ctrl7_g_t ctrl7_g;
3064 int32_t ret;
3065
3066 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
3067
3068 switch (ctrl7_g.ois_on)
3069 {
3070 case LSM6DSR_AUX_ON:
3071 *val = LSM6DSR_AUX_ON;
3072 break;
3073
3074 case LSM6DSR_AUX_ON_BY_AUX_INTERFACE:
3075 *val = LSM6DSR_AUX_ON_BY_AUX_INTERFACE;
3076 break;
3077
3078 default:
3079 *val = LSM6DSR_AUX_ON;
3080 break;
3081 }
3082
3083 return ret;
3084 }
3085
3086 /**
3087 * @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get]
3088 *
3089 * @param ctx Read / write interface definitions.(ptr)
3090 * @param lsm6dsr_status_spiaux_t: registers STATUS_SPIAUX
3091 * @retval Interface status (MANDATORY: return 0 -> no Error).
3092 *
3093 */
lsm6dsr_aux_status_reg_get(stmdev_ctx_t * ctx,lsm6dsr_status_spiaux_t * val)3094 int32_t lsm6dsr_aux_status_reg_get(stmdev_ctx_t *ctx,
3095 lsm6dsr_status_spiaux_t *val)
3096 {
3097 int32_t ret;
3098
3099 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_SPIAUX, (uint8_t *)val, 1);
3100
3101 return ret;
3102 }
3103
3104 /**
3105 * @brief AUX accelerometer data available.[get]
3106 *
3107 * @param ctx Read / write interface definitions.(ptr)
3108 * @param val Change the values of xlda in reg STATUS_SPIAUX
3109 * @retval Interface status (MANDATORY: return 0 -> no Error).
3110 *
3111 */
lsm6dsr_aux_xl_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)3112 int32_t lsm6dsr_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
3113 uint8_t *val)
3114 {
3115 lsm6dsr_status_spiaux_t status_spiaux;
3116 int32_t ret;
3117
3118 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_SPIAUX,
3119 (uint8_t *)&status_spiaux, 1);
3120 *val = status_spiaux.xlda;
3121
3122 return ret;
3123 }
3124
3125 /**
3126 * @brief AUX gyroscope data available.[get]
3127 *
3128 * @param ctx Read / write interface definitions.(ptr)
3129 * @param val Change the values of gda in reg STATUS_SPIAUX
3130 * @retval Interface status (MANDATORY: return 0 -> no Error).
3131 *
3132 */
lsm6dsr_aux_gy_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)3133 int32_t lsm6dsr_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
3134 uint8_t *val)
3135 {
3136 lsm6dsr_status_spiaux_t status_spiaux;
3137 int32_t ret;
3138
3139 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_SPIAUX,
3140 (uint8_t *)&status_spiaux, 1);
3141 *val = status_spiaux.gda;
3142
3143 return ret;
3144 }
3145
3146 /**
3147 * @brief High when the gyroscope output is in the settling phase.[get]
3148 *
3149 * @param ctx Read / write interface definitions.(ptr)
3150 * @param val Change the values of gyro_settling in reg STATUS_SPIAUX
3151 * @retval Interface status (MANDATORY: return 0 -> no Error).
3152 *
3153 */
lsm6dsr_aux_gy_flag_settling_get(stmdev_ctx_t * ctx,uint8_t * val)3154 int32_t lsm6dsr_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
3155 uint8_t *val)
3156 {
3157 lsm6dsr_status_spiaux_t status_spiaux;
3158 int32_t ret;
3159
3160 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_SPIAUX,
3161 (uint8_t *)&status_spiaux, 1);
3162 *val = status_spiaux.gyro_settling;
3163
3164 return ret;
3165 }
3166
3167 /**
3168 * @brief Selects accelerometer self-test. Effective only if XL OIS chain is
3169 * enabled.[set]
3170 *
3171 * @param ctx Read / write interface definitions.(ptr)
3172 * @param val Change the values of st_xl_ois in reg INT_OIS
3173 * @retval Interface status (MANDATORY: return 0 -> no Error).
3174 *
3175 */
lsm6dsr_aux_xl_self_test_set(stmdev_ctx_t * ctx,lsm6dsr_st_xl_ois_t val)3176 int32_t lsm6dsr_aux_xl_self_test_set(stmdev_ctx_t *ctx,
3177 lsm6dsr_st_xl_ois_t val)
3178 {
3179 lsm6dsr_int_ois_t int_ois;
3180 int32_t ret;
3181
3182 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
3183
3184 if (ret == 0)
3185 {
3186 int_ois.st_xl_ois = (uint8_t)val;
3187 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
3188 }
3189
3190 return ret;
3191 }
3192
3193 /**
3194 * @brief Selects accelerometer self-test. Effective only if XL OIS chain
3195 * is enabled.[get]
3196 *
3197 * @param ctx Read / write interface definitions.(ptr)
3198 * @param val Get the values of st_xl_ois in reg INT_OIS
3199 * @retval Interface status (MANDATORY: return 0 -> no Error).
3200 *
3201 */
lsm6dsr_aux_xl_self_test_get(stmdev_ctx_t * ctx,lsm6dsr_st_xl_ois_t * val)3202 int32_t lsm6dsr_aux_xl_self_test_get(stmdev_ctx_t *ctx,
3203 lsm6dsr_st_xl_ois_t *val)
3204 {
3205 lsm6dsr_int_ois_t int_ois;
3206 int32_t ret;
3207
3208 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
3209
3210 switch (int_ois.st_xl_ois)
3211 {
3212 case LSM6DSR_AUX_XL_DISABLE:
3213 *val = LSM6DSR_AUX_XL_DISABLE;
3214 break;
3215
3216 case LSM6DSR_AUX_XL_POS:
3217 *val = LSM6DSR_AUX_XL_POS;
3218 break;
3219
3220 case LSM6DSR_AUX_XL_NEG:
3221 *val = LSM6DSR_AUX_XL_NEG;
3222 break;
3223
3224 default:
3225 *val = LSM6DSR_AUX_XL_DISABLE;
3226 break;
3227 }
3228
3229 return ret;
3230 }
3231
3232 /**
3233 * @brief Indicates polarity of DEN signal on OIS chain.[set]
3234 *
3235 * @param ctx Read / write interface definitions.(ptr)
3236 * @param val Change the values of den_lh_ois in reg INT_OIS
3237 * @retval Interface status (MANDATORY: return 0 -> no Error).
3238 *
3239 */
lsm6dsr_aux_den_polarity_set(stmdev_ctx_t * ctx,lsm6dsr_den_lh_ois_t val)3240 int32_t lsm6dsr_aux_den_polarity_set(stmdev_ctx_t *ctx,
3241 lsm6dsr_den_lh_ois_t val)
3242 {
3243 lsm6dsr_int_ois_t int_ois;
3244 int32_t ret;
3245
3246 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
3247
3248 if (ret == 0)
3249 {
3250 int_ois.den_lh_ois = (uint8_t)val;
3251 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
3252 }
3253
3254 return ret;
3255 }
3256
3257 /**
3258 * @brief Indicates polarity of DEN signal on OIS chain.[get]
3259 *
3260 * @param ctx Read / write interface definitions.(ptr)
3261 * @param val Get the values of den_lh_ois in reg INT_OIS
3262 * @retval Interface status (MANDATORY: return 0 -> no Error).
3263 *
3264 */
lsm6dsr_aux_den_polarity_get(stmdev_ctx_t * ctx,lsm6dsr_den_lh_ois_t * val)3265 int32_t lsm6dsr_aux_den_polarity_get(stmdev_ctx_t *ctx,
3266 lsm6dsr_den_lh_ois_t *val)
3267 {
3268 lsm6dsr_int_ois_t int_ois;
3269 int32_t ret;
3270
3271 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
3272
3273 switch (int_ois.den_lh_ois)
3274 {
3275 case LSM6DSR_AUX_DEN_ACTIVE_LOW:
3276 *val = LSM6DSR_AUX_DEN_ACTIVE_LOW;
3277 break;
3278
3279 case LSM6DSR_AUX_DEN_ACTIVE_HIGH:
3280 *val = LSM6DSR_AUX_DEN_ACTIVE_HIGH;
3281 break;
3282
3283 default:
3284 *val = LSM6DSR_AUX_DEN_ACTIVE_LOW;
3285 break;
3286 }
3287
3288 return ret;
3289 }
3290
3291 /**
3292 * @brief Configure DEN mode on the OIS chain.[set]
3293 *
3294 * @param ctx Read / write interface definitions.(ptr)
3295 * @param val Change the values of lvl2_ois in reg INT_OIS
3296 * @retval Interface status (MANDATORY: return 0 -> no Error).
3297 *
3298 */
lsm6dsr_aux_den_mode_set(stmdev_ctx_t * ctx,lsm6dsr_lvl2_ois_t val)3299 int32_t lsm6dsr_aux_den_mode_set(stmdev_ctx_t *ctx,
3300 lsm6dsr_lvl2_ois_t val)
3301 {
3302 lsm6dsr_int_ois_t int_ois;
3303 lsm6dsr_ctrl1_ois_t ctrl1_ois;
3304 int32_t ret;
3305
3306 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
3307
3308 if (ret == 0)
3309 {
3310 int_ois.lvl2_ois = (uint8_t)val & 0x01U;
3311 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
3312 }
3313
3314 if (ret == 0)
3315 {
3316 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS,
3317 (uint8_t *)&ctrl1_ois, 1);
3318 }
3319
3320 if (ret == 0)
3321 {
3322 ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
3323 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_OIS,
3324 (uint8_t *)&ctrl1_ois, 1);
3325 }
3326
3327 return ret;
3328 }
3329
3330 /**
3331 * @brief Configure DEN mode on the OIS chain.[get]
3332 *
3333 * @param ctx Read / write interface definitions.(ptr)
3334 * @param val Get the values of lvl2_ois in reg INT_OIS
3335 * @retval Interface status (MANDATORY: return 0 -> no Error).
3336 *
3337 */
lsm6dsr_aux_den_mode_get(stmdev_ctx_t * ctx,lsm6dsr_lvl2_ois_t * val)3338 int32_t lsm6dsr_aux_den_mode_get(stmdev_ctx_t *ctx,
3339 lsm6dsr_lvl2_ois_t *val)
3340 {
3341 lsm6dsr_int_ois_t int_ois;
3342 lsm6dsr_ctrl1_ois_t ctrl1_ois;
3343 int32_t ret;
3344
3345 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
3346
3347 if (ret == 0)
3348 {
3349 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS,
3350 (uint8_t *)&ctrl1_ois, 1);
3351 }
3352
3353 switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois)
3354 {
3355 case LSM6DSR_AUX_DEN_DISABLE:
3356 *val = LSM6DSR_AUX_DEN_DISABLE;
3357 break;
3358
3359 case LSM6DSR_AUX_DEN_LEVEL_LATCH:
3360 *val = LSM6DSR_AUX_DEN_LEVEL_LATCH;
3361 break;
3362
3363 case LSM6DSR_AUX_DEN_LEVEL_TRIG:
3364 *val = LSM6DSR_AUX_DEN_LEVEL_TRIG;
3365 break;
3366
3367 default:
3368 *val = LSM6DSR_AUX_DEN_DISABLE;
3369 break;
3370 }
3371
3372 return ret;
3373 }
3374
3375 /**
3376 * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting has
3377 * priority over all other INT2 settings.[set]
3378 *
3379 * @param ctx Read / write interface definitions.(ptr)
3380 * @param val Change the values of int2_drdy_ois in reg INT_OIS
3381 * @retval Interface status (MANDATORY: return 0 -> no Error).
3382 *
3383 */
lsm6dsr_aux_drdy_on_int2_set(stmdev_ctx_t * ctx,uint8_t val)3384 int32_t lsm6dsr_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
3385 {
3386 lsm6dsr_int_ois_t int_ois;
3387 int32_t ret;
3388
3389 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
3390
3391 if (ret == 0)
3392 {
3393 int_ois.int2_drdy_ois = (uint8_t)val;
3394 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
3395 }
3396
3397 return ret;
3398 }
3399
3400 /**
3401 * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting has
3402 * priority over all other INT2 settings.[get]
3403 *
3404 * @param ctx Read / write interface definitions.(ptr)
3405 * @param val Change the values of int2_drdy_ois in reg INT_OIS
3406 * @retval Interface status (MANDATORY: return 0 -> no Error).
3407 *
3408 */
lsm6dsr_aux_drdy_on_int2_get(stmdev_ctx_t * ctx,uint8_t * val)3409 int32_t lsm6dsr_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
3410 {
3411 lsm6dsr_int_ois_t int_ois;
3412 int32_t ret;
3413
3414 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_OIS, (uint8_t *)&int_ois, 1);
3415 *val = int_ois.int2_drdy_ois;
3416
3417 return ret;
3418 }
3419
3420 /**
3421 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
3422 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
3423 * When the OIS chain is enabled, the OIS outputs are available
3424 * through the SPI2 in registers OUTX_L_G (22h) through OUTZ_H_G(27h)
3425 * and STATUS_REG (1Eh) / STATUS_SPIAux, and LPF1 is dedicated to
3426 * this chain.[set]
3427 *
3428 * @param ctx Read / write interface definitions.(ptr)
3429 * @param val Change the values of ois_en_spi2 in reg CTRL1_OIS
3430 * @retval Interface status (MANDATORY: return 0 -> no Error).
3431 *
3432 */
lsm6dsr_aux_mode_set(stmdev_ctx_t * ctx,lsm6dsr_ois_en_spi2_t val)3433 int32_t lsm6dsr_aux_mode_set(stmdev_ctx_t *ctx,
3434 lsm6dsr_ois_en_spi2_t val)
3435 {
3436 lsm6dsr_ctrl1_ois_t ctrl1_ois;
3437 int32_t ret;
3438
3439 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3440
3441 if (ret == 0)
3442 {
3443 ctrl1_ois.ois_en_spi2 = (uint8_t)val & 0x01U;
3444 ctrl1_ois.mode4_en = ((uint8_t)val & 0x02U) >> 1;
3445 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_OIS,
3446 (uint8_t *)&ctrl1_ois, 1);
3447 }
3448
3449 return ret;
3450 }
3451
3452 /**
3453 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
3454 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
3455 * When the OIS chain is enabled, the OIS outputs are available
3456 * through the SPI2 in registers OUTX_L_G (22h) through OUTZ_H_G(27h)
3457 * and STATUS_REG (1Eh) / STATUS_SPIAux, and LPF1 is dedicated to
3458 * this chain.[get]
3459 *
3460 * @param ctx Read / write interface definitions.(ptr)
3461 * @param val Get the values of ois_en_spi2 in
3462 * reg CTRL1_OIS
3463 * @retval Interface status (MANDATORY: return 0 -> no Error).
3464 *
3465 */
lsm6dsr_aux_mode_get(stmdev_ctx_t * ctx,lsm6dsr_ois_en_spi2_t * val)3466 int32_t lsm6dsr_aux_mode_get(stmdev_ctx_t *ctx,
3467 lsm6dsr_ois_en_spi2_t *val)
3468 {
3469 lsm6dsr_ctrl1_ois_t ctrl1_ois;
3470 int32_t ret;
3471
3472 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3473
3474 switch (((ctrl1_ois.mode4_en << 1) + ctrl1_ois.ois_en_spi2))
3475 {
3476 case LSM6DSR_AUX_DISABLE:
3477 *val = LSM6DSR_AUX_DISABLE;
3478 break;
3479
3480 case LSM6DSR_MODE_3_GY:
3481 *val = LSM6DSR_MODE_3_GY;
3482 break;
3483
3484 case LSM6DSR_MODE_4_GY_XL:
3485 *val = LSM6DSR_MODE_4_GY_XL;
3486 break;
3487
3488 default:
3489 *val = LSM6DSR_AUX_DISABLE;
3490 break;
3491 }
3492
3493 return ret;
3494 }
3495
3496 /**
3497 * @brief Selects gyroscope OIS chain full-scale.[set]
3498 *
3499 * @param ctx Read / write interface definitions.(ptr)
3500 * @param val Change the values of fs_g_ois in reg CTRL1_OIS
3501 * @retval Interface status (MANDATORY: return 0 -> no Error).
3502 *
3503 */
lsm6dsr_aux_gy_full_scale_set(stmdev_ctx_t * ctx,lsm6dsr_fs_g_ois_t val)3504 int32_t lsm6dsr_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
3505 lsm6dsr_fs_g_ois_t val)
3506 {
3507 lsm6dsr_ctrl1_ois_t ctrl1_ois;
3508 int32_t ret;
3509
3510 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3511
3512 if (ret == 0)
3513 {
3514 ctrl1_ois.fs_g_ois = (uint8_t)val & 0x03U;
3515 ctrl1_ois.fs_125_ois = ((uint8_t)val & 0x04U) >> 2;
3516 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_OIS,
3517 (uint8_t *)&ctrl1_ois, 1);
3518 }
3519
3520 return ret;
3521 }
3522
3523 /**
3524 * @brief Selects gyroscope OIS chain full-scale.[get]
3525 *
3526 * @param ctx Read / write interface definitions.(ptr)
3527 * @param val Get the values of fs_g_ois in reg CTRL1_OIS
3528 * @retval Interface status (MANDATORY: return 0 -> no Error).
3529 *
3530 */
lsm6dsr_aux_gy_full_scale_get(stmdev_ctx_t * ctx,lsm6dsr_fs_g_ois_t * val)3531 int32_t lsm6dsr_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
3532 lsm6dsr_fs_g_ois_t *val)
3533 {
3534 lsm6dsr_ctrl1_ois_t ctrl1_ois;
3535 int32_t ret;
3536
3537 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS,
3538 (uint8_t *)&ctrl1_ois, 1);
3539
3540 switch ((ctrl1_ois.fs_125_ois << 2) + ctrl1_ois.fs_g_ois)
3541 {
3542 case LSM6DSR_250dps_AUX:
3543 *val = LSM6DSR_250dps_AUX;
3544 break;
3545
3546 case LSM6DSR_125dps_AUX:
3547 *val = LSM6DSR_125dps_AUX;
3548 break;
3549
3550 case LSM6DSR_500dps_AUX:
3551 *val = LSM6DSR_500dps_AUX;
3552 break;
3553
3554 case LSM6DSR_1000dps_AUX:
3555 *val = LSM6DSR_1000dps_AUX;
3556 break;
3557
3558 case LSM6DSR_2000dps_AUX:
3559 *val = LSM6DSR_2000dps_AUX;
3560 break;
3561
3562 default:
3563 *val = LSM6DSR_250dps_AUX;
3564 break;
3565 }
3566
3567 return ret;
3568 }
3569
3570 /**
3571 * @brief SPI2 3- or 4-wire interface.[set]
3572 *
3573 * @param ctx Read / write interface definitions.(ptr)
3574 * @param val Change the values of sim_ois in reg CTRL1_OIS
3575 * @retval Interface status (MANDATORY: return 0 -> no Error).
3576 *
3577 */
lsm6dsr_aux_spi_mode_set(stmdev_ctx_t * ctx,lsm6dsr_sim_ois_t val)3578 int32_t lsm6dsr_aux_spi_mode_set(stmdev_ctx_t *ctx,
3579 lsm6dsr_sim_ois_t val)
3580 {
3581 lsm6dsr_ctrl1_ois_t ctrl1_ois;
3582 int32_t ret;
3583
3584 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3585
3586 if (ret == 0)
3587 {
3588 ctrl1_ois.sim_ois = (uint8_t)val;
3589 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL1_OIS,
3590 (uint8_t *)&ctrl1_ois, 1);
3591 }
3592
3593 return ret;
3594 }
3595
3596 /**
3597 * @brief SPI2 3- or 4-wire interface.[get]
3598 *
3599 * @param ctx Read / write interface definitions.(ptr)
3600 * @param val Get the values of sim_ois in reg CTRL1_OIS
3601 * @retval Interface status (MANDATORY: return 0 -> no Error).
3602 *
3603 */
lsm6dsr_aux_spi_mode_get(stmdev_ctx_t * ctx,lsm6dsr_sim_ois_t * val)3604 int32_t lsm6dsr_aux_spi_mode_get(stmdev_ctx_t *ctx,
3605 lsm6dsr_sim_ois_t *val)
3606 {
3607 lsm6dsr_ctrl1_ois_t ctrl1_ois;
3608 int32_t ret;
3609
3610 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3611
3612 switch (ctrl1_ois.sim_ois)
3613 {
3614 case LSM6DSR_AUX_SPI_4_WIRE:
3615 *val = LSM6DSR_AUX_SPI_4_WIRE;
3616 break;
3617
3618 case LSM6DSR_AUX_SPI_3_WIRE:
3619 *val = LSM6DSR_AUX_SPI_3_WIRE;
3620 break;
3621
3622 default:
3623 *val = LSM6DSR_AUX_SPI_4_WIRE;
3624 break;
3625 }
3626
3627 return ret;
3628 }
3629
3630 /**
3631 * @brief Selects gyroscope digital LPF1 filter bandwidth.[set]
3632 *
3633 * @param ctx Read / write interface definitions.(ptr)
3634 * @param val Change the values of ftype_ois in reg CTRL2_OIS
3635 * @retval Interface status (MANDATORY: return 0 -> no Error).
3636 *
3637 */
lsm6dsr_aux_gy_lp1_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsr_ftype_ois_t val)3638 int32_t lsm6dsr_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
3639 lsm6dsr_ftype_ois_t val)
3640 {
3641 lsm6dsr_ctrl2_ois_t ctrl2_ois;
3642 int32_t ret;
3643
3644 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1);
3645
3646 if (ret == 0)
3647 {
3648 ctrl2_ois.ftype_ois = (uint8_t)val;
3649 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL2_OIS,
3650 (uint8_t *)&ctrl2_ois, 1);
3651 }
3652
3653 return ret;
3654 }
3655
3656 /**
3657 * @brief Selects gyroscope digital LPF1 filter bandwidth.[get]
3658 *
3659 * @param ctx Read / write interface definitions.(ptr)
3660 * @param val Get the values of ftype_ois in reg CTRL2_OIS
3661 * @retval Interface status (MANDATORY: return 0 -> no Error).
3662 *
3663 */
lsm6dsr_aux_gy_lp1_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsr_ftype_ois_t * val)3664 int32_t lsm6dsr_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
3665 lsm6dsr_ftype_ois_t *val)
3666 {
3667 lsm6dsr_ctrl2_ois_t ctrl2_ois;
3668 int32_t ret;
3669
3670 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1);
3671
3672 switch (ctrl2_ois.ftype_ois)
3673 {
3674 case LSM6DSR_351Hz39:
3675 *val = LSM6DSR_351Hz39;
3676 break;
3677
3678 case LSM6DSR_236Hz63:
3679 *val = LSM6DSR_236Hz63;
3680 break;
3681
3682 case LSM6DSR_172Hz70:
3683 *val = LSM6DSR_172Hz70;
3684 break;
3685
3686 case LSM6DSR_937Hz91:
3687 *val = LSM6DSR_937Hz91;
3688 break;
3689
3690 default:
3691 *val = LSM6DSR_351Hz39;
3692 break;
3693 }
3694
3695 return ret;
3696 }
3697
3698 /**
3699 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[set]
3700 *
3701 * @param ctx Read / write interface definitions.(ptr)
3702 * @param val Change the values of hpm_ois in reg CTRL2_OIS
3703 * @retval Interface status (MANDATORY: return 0 -> no Error).
3704 *
3705 */
lsm6dsr_aux_gy_hp_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsr_hpm_ois_t val)3706 int32_t lsm6dsr_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
3707 lsm6dsr_hpm_ois_t val)
3708 {
3709 lsm6dsr_ctrl2_ois_t ctrl2_ois;
3710 int32_t ret;
3711
3712 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1);
3713
3714 if (ret == 0)
3715 {
3716 ctrl2_ois.hpm_ois = (uint8_t)val & 0x03U;
3717 ctrl2_ois.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
3718 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL2_OIS,
3719 (uint8_t *)&ctrl2_ois, 1);
3720 }
3721
3722 return ret;
3723 }
3724
3725 /**
3726 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[get]
3727 *
3728 * @param ctx Read / write interface definitions.(ptr)
3729 * @param val Get the values of hpm_ois in reg CTRL2_OIS
3730 * @retval Interface status (MANDATORY: return 0 -> no Error).
3731 *
3732 */
lsm6dsr_aux_gy_hp_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsr_hpm_ois_t * val)3733 int32_t lsm6dsr_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
3734 lsm6dsr_hpm_ois_t *val)
3735 {
3736 lsm6dsr_ctrl2_ois_t ctrl2_ois;
3737 int32_t ret;
3738
3739 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1);
3740
3741 switch ((ctrl2_ois.hp_en_ois << 4) + ctrl2_ois.hpm_ois)
3742 {
3743 case LSM6DSR_AUX_HP_DISABLE:
3744 *val = LSM6DSR_AUX_HP_DISABLE;
3745 break;
3746
3747 case LSM6DSR_AUX_HP_Hz016:
3748 *val = LSM6DSR_AUX_HP_Hz016;
3749 break;
3750
3751 case LSM6DSR_AUX_HP_Hz065:
3752 *val = LSM6DSR_AUX_HP_Hz065;
3753 break;
3754
3755 case LSM6DSR_AUX_HP_Hz260:
3756 *val = LSM6DSR_AUX_HP_Hz260;
3757 break;
3758
3759 case LSM6DSR_AUX_HP_1Hz040:
3760 *val = LSM6DSR_AUX_HP_1Hz040;
3761 break;
3762
3763 default:
3764 *val = LSM6DSR_AUX_HP_DISABLE;
3765 break;
3766 }
3767
3768 return ret;
3769 }
3770
3771 /**
3772 * @brief Enable / Disables OIS chain clamp. Enable: All OIS chain
3773 * outputs = 8000h during self-test; Disable: OIS chain self-test
3774 * outputs dependent from the aux gyro full scale selected.[set]
3775 *
3776 * @param ctx Read / write interface definitions.(ptr)
3777 * @param val Change the values of st_ois_clampdis in reg CTRL3_OIS
3778 * @retval Interface status (MANDATORY: return 0 -> no Error).
3779 *
3780 */
lsm6dsr_aux_gy_clamp_set(stmdev_ctx_t * ctx,lsm6dsr_st_ois_clampdis_t val)3781 int32_t lsm6dsr_aux_gy_clamp_set(stmdev_ctx_t *ctx,
3782 lsm6dsr_st_ois_clampdis_t val)
3783 {
3784 lsm6dsr_ctrl3_ois_t ctrl3_ois;
3785 int32_t ret;
3786
3787 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3788
3789 if (ret == 0)
3790 {
3791 ctrl3_ois.st_ois_clampdis = (uint8_t)val;
3792 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_OIS,
3793 (uint8_t *)&ctrl3_ois, 1);
3794 }
3795
3796 return ret;
3797 }
3798
3799 /**
3800 * @brief Enable / Disables OIS chain clamp. Enable: All OIS chain
3801 * outputs = 8000h during self-test; Disable: OIS chain self-test
3802 * outputs dependent from the aux gyro full scale selected.[get]
3803 *
3804 * @param ctx Read / write interface definitions.(ptr)
3805 * @param val Get the values of st_ois_clampdis in reg CTRL3_OIS
3806 * @retval Interface status (MANDATORY: return 0 -> no Error).
3807 *
3808 */
lsm6dsr_aux_gy_clamp_get(stmdev_ctx_t * ctx,lsm6dsr_st_ois_clampdis_t * val)3809 int32_t lsm6dsr_aux_gy_clamp_get(stmdev_ctx_t *ctx,
3810 lsm6dsr_st_ois_clampdis_t *val)
3811 {
3812 lsm6dsr_ctrl3_ois_t ctrl3_ois;
3813 int32_t ret;
3814
3815 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3816
3817 switch (ctrl3_ois.st_ois_clampdis)
3818 {
3819 case LSM6DSR_ENABLE_CLAMP:
3820 *val = LSM6DSR_ENABLE_CLAMP;
3821 break;
3822
3823 case LSM6DSR_DISABLE_CLAMP:
3824 *val = LSM6DSR_DISABLE_CLAMP;
3825 break;
3826
3827 default:
3828 *val = LSM6DSR_ENABLE_CLAMP;
3829 break;
3830 }
3831
3832 return ret;
3833 }
3834
3835 /**
3836 * @brief Selects gyroscope OIS chain self-test.[set]
3837 *
3838 * @param ctx Read / write interface definitions.(ptr)
3839 * @param val Change the values of st_ois in reg CTRL3_OIS
3840 * @retval Interface status (MANDATORY: return 0 -> no Error).
3841 *
3842 */
lsm6dsr_aux_gy_self_test_set(stmdev_ctx_t * ctx,lsm6dsr_st_ois_t val)3843 int32_t lsm6dsr_aux_gy_self_test_set(stmdev_ctx_t *ctx,
3844 lsm6dsr_st_ois_t val)
3845 {
3846 lsm6dsr_ctrl3_ois_t ctrl3_ois;
3847 int32_t ret;
3848
3849 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3850
3851 if (ret == 0)
3852 {
3853 ctrl3_ois.st_ois = (uint8_t)val;
3854 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_OIS,
3855 (uint8_t *)&ctrl3_ois, 1);
3856 }
3857
3858 return ret;
3859 }
3860
3861 /**
3862 * @brief Selects gyroscope OIS chain self-test.[get]
3863 *
3864 * @param ctx Read / write interface definitions.(ptr)
3865 * @param val Get the values of st_ois in reg CTRL3_OIS
3866 * @retval Interface status (MANDATORY: return 0 -> no Error).
3867 *
3868 */
lsm6dsr_aux_gy_self_test_get(stmdev_ctx_t * ctx,lsm6dsr_st_ois_t * val)3869 int32_t lsm6dsr_aux_gy_self_test_get(stmdev_ctx_t *ctx,
3870 lsm6dsr_st_ois_t *val)
3871 {
3872 lsm6dsr_ctrl3_ois_t ctrl3_ois;
3873 int32_t ret;
3874
3875 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3876
3877 switch (ctrl3_ois.st_ois)
3878 {
3879 case LSM6DSR_AUX_GY_DISABLE:
3880 *val = LSM6DSR_AUX_GY_DISABLE;
3881 break;
3882
3883 case LSM6DSR_AUX_GY_POS:
3884 *val = LSM6DSR_AUX_GY_POS;
3885 break;
3886
3887 case LSM6DSR_AUX_GY_NEG:
3888 *val = LSM6DSR_AUX_GY_NEG;
3889 break;
3890
3891 default:
3892 *val = LSM6DSR_AUX_GY_DISABLE;
3893 break;
3894 }
3895
3896 return ret;
3897 }
3898
3899 /**
3900 * @brief Selects accelerometer OIS channel bandwidth.[set]
3901 *
3902 * @param ctx Read / write interface definitions.(ptr)
3903 * @param val Change the values of filter_xl_conf_ois in reg CTRL3_OIS
3904 * @retval Interface status (MANDATORY: return 0 -> no Error).
3905 *
3906 */
lsm6dsr_aux_xl_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsr_filter_xl_conf_ois_t val)3907 int32_t lsm6dsr_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
3908 lsm6dsr_filter_xl_conf_ois_t val)
3909 {
3910 lsm6dsr_ctrl3_ois_t ctrl3_ois;
3911 int32_t ret;
3912
3913 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3914
3915 if (ret == 0)
3916 {
3917 ctrl3_ois.filter_xl_conf_ois = (uint8_t)val;
3918 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_OIS,
3919 (uint8_t *)&ctrl3_ois, 1);
3920 }
3921
3922 return ret;
3923 }
3924
3925 /**
3926 * @brief Selects accelerometer OIS channel bandwidth.[get]
3927 *
3928 * @param ctx Read / write interface definitions.(ptr)
3929 * @param val Get the values of filter_xl_conf_ois in reg CTRL3_OIS
3930 * @retval Interface status (MANDATORY: return 0 -> no Error).
3931 *
3932 */
lsm6dsr_aux_xl_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsr_filter_xl_conf_ois_t * val)3933 int32_t lsm6dsr_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
3934 lsm6dsr_filter_xl_conf_ois_t *val)
3935 {
3936 lsm6dsr_ctrl3_ois_t ctrl3_ois;
3937 int32_t ret;
3938
3939 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3940
3941 switch (ctrl3_ois.filter_xl_conf_ois)
3942 {
3943 case LSM6DSR_631Hz:
3944 *val = LSM6DSR_631Hz;
3945 break;
3946
3947 case LSM6DSR_295Hz:
3948 *val = LSM6DSR_295Hz;
3949 break;
3950
3951 case LSM6DSR_140Hz:
3952 *val = LSM6DSR_140Hz;
3953 break;
3954
3955 case LSM6DSR_68Hz2:
3956 *val = LSM6DSR_68Hz2;
3957 break;
3958
3959 case LSM6DSR_33Hz6:
3960 *val = LSM6DSR_33Hz6;
3961 break;
3962
3963 case LSM6DSR_16Hz7:
3964 *val = LSM6DSR_16Hz7;
3965 break;
3966
3967 case LSM6DSR_8Hz3:
3968 *val = LSM6DSR_8Hz3;
3969 break;
3970
3971 case LSM6DSR_4Hz11:
3972 *val = LSM6DSR_4Hz11;
3973 break;
3974
3975 default:
3976 *val = LSM6DSR_631Hz;
3977 break;
3978 }
3979
3980 return ret;
3981 }
3982
3983 /**
3984 * @brief Selects accelerometer OIS channel full-scale.[set]
3985 *
3986 * @param ctx Read / write interface definitions.(ptr)
3987 * @param val Change the values of fs_xl_ois in reg CTRL3_OIS
3988 * @retval Interface status (MANDATORY: return 0 -> no Error).
3989 *
3990 */
lsm6dsr_aux_xl_full_scale_set(stmdev_ctx_t * ctx,lsm6dsr_fs_xl_ois_t val)3991 int32_t lsm6dsr_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
3992 lsm6dsr_fs_xl_ois_t val)
3993 {
3994 lsm6dsr_ctrl3_ois_t ctrl3_ois;
3995 int32_t ret;
3996
3997 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3998
3999 if (ret == 0)
4000 {
4001 ctrl3_ois.fs_xl_ois = (uint8_t)val;
4002 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_OIS,
4003 (uint8_t *)&ctrl3_ois, 1);
4004 }
4005
4006 return ret;
4007 }
4008
4009 /**
4010 * @brief Selects accelerometer OIS channel full-scale.[get]
4011 *
4012 * @param ctx Read / write interface definitions.(ptr)
4013 * @param val Get the values of fs_xl_ois in reg CTRL3_OIS
4014 * @retval Interface status (MANDATORY: return 0 -> no Error).
4015 *
4016 */
lsm6dsr_aux_xl_full_scale_get(stmdev_ctx_t * ctx,lsm6dsr_fs_xl_ois_t * val)4017 int32_t lsm6dsr_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
4018 lsm6dsr_fs_xl_ois_t *val)
4019 {
4020 lsm6dsr_ctrl3_ois_t ctrl3_ois;
4021 int32_t ret;
4022
4023 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
4024
4025 switch (ctrl3_ois.fs_xl_ois)
4026 {
4027 case LSM6DSR_AUX_2g:
4028 *val = LSM6DSR_AUX_2g;
4029 break;
4030
4031 case LSM6DSR_AUX_16g:
4032 *val = LSM6DSR_AUX_16g;
4033 break;
4034
4035 case LSM6DSR_AUX_4g:
4036 *val = LSM6DSR_AUX_4g;
4037 break;
4038
4039 case LSM6DSR_AUX_8g:
4040 *val = LSM6DSR_AUX_8g;
4041 break;
4042
4043 default:
4044 *val = LSM6DSR_AUX_2g;
4045 break;
4046 }
4047
4048 return ret;
4049 }
4050
4051 /**
4052 * @}
4053 *
4054 */
4055
4056 /**
4057 * @defgroup LSM6DSR_ main_serial_interface
4058 * @brief This section groups all the functions concerning main
4059 * serial interface management (not auxiliary)
4060 * @{
4061 *
4062 */
4063
4064 /**
4065 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
4066 *
4067 * @param ctx Read / write interface definitions.(ptr)
4068 * @param val Change the values of sdo_pu_en in reg PIN_CTRL
4069 * @retval Interface status (MANDATORY: return 0 -> no Error).
4070 *
4071 */
lsm6dsr_sdo_sa0_mode_set(stmdev_ctx_t * ctx,lsm6dsr_sdo_pu_en_t val)4072 int32_t lsm6dsr_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
4073 lsm6dsr_sdo_pu_en_t val)
4074 {
4075 lsm6dsr_pin_ctrl_t pin_ctrl;
4076 int32_t ret;
4077
4078 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
4079
4080 if (ret == 0)
4081 {
4082 pin_ctrl.sdo_pu_en = (uint8_t)val;
4083 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
4084 }
4085
4086 return ret;
4087 }
4088
4089 /**
4090 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
4091 *
4092 * @param ctx Read / write interface definitions.(ptr)
4093 * @param val Get the values of sdo_pu_en in reg PIN_CTRL
4094 * @retval Interface status (MANDATORY: return 0 -> no Error).
4095 *
4096 */
lsm6dsr_sdo_sa0_mode_get(stmdev_ctx_t * ctx,lsm6dsr_sdo_pu_en_t * val)4097 int32_t lsm6dsr_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
4098 lsm6dsr_sdo_pu_en_t *val)
4099 {
4100 lsm6dsr_pin_ctrl_t pin_ctrl;
4101 int32_t ret;
4102
4103 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
4104
4105 switch (pin_ctrl.sdo_pu_en)
4106 {
4107 case LSM6DSR_PULL_UP_DISC:
4108 *val = LSM6DSR_PULL_UP_DISC;
4109 break;
4110
4111 case LSM6DSR_PULL_UP_CONNECT:
4112 *val = LSM6DSR_PULL_UP_CONNECT;
4113 break;
4114
4115 default:
4116 *val = LSM6DSR_PULL_UP_DISC;
4117 break;
4118 }
4119
4120 return ret;
4121 }
4122
4123 /**
4124 * @brief Connect/Disconnect INT1 pull-down.[set]
4125 *
4126 * @param ctx Read / write interface definitions.(ptr)
4127 * @param val Change the values of pd_dis_int1 in reg I3C_BUS_AVB
4128 * @retval Interface status (MANDATORY: return 0 -> no Error).
4129 *
4130 */
lsm6dsr_int1_mode_set(stmdev_ctx_t * ctx,lsm6dsr_pd_dis_int1_t val)4131 int32_t lsm6dsr_int1_mode_set(stmdev_ctx_t *ctx,
4132 lsm6dsr_pd_dis_int1_t val)
4133 {
4134 lsm6dsr_i3c_bus_avb_t i3c_bus_avb;
4135 int32_t ret;
4136
4137 ret = lsm6dsr_read_reg(ctx, LSM6DSR_I3C_BUS_AVB,
4138 (uint8_t *)&i3c_bus_avb, 1);
4139
4140 if (ret == 0)
4141 {
4142 i3c_bus_avb.pd_dis_int1 = (uint8_t)val;
4143 ret = lsm6dsr_write_reg(ctx, LSM6DSR_I3C_BUS_AVB,
4144 (uint8_t *)&i3c_bus_avb, 1);
4145 }
4146
4147 return ret;
4148 }
4149
4150 /**
4151 * @brief Connect/Disconnect INT1 pull-down.[get]
4152 *
4153 * @param ctx Read / write interface definitions.(ptr)
4154 * @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB
4155 * @retval Interface status (MANDATORY: return 0 -> no Error).
4156 *
4157 */
lsm6dsr_int1_mode_get(stmdev_ctx_t * ctx,lsm6dsr_pd_dis_int1_t * val)4158 int32_t lsm6dsr_int1_mode_get(stmdev_ctx_t *ctx,
4159 lsm6dsr_pd_dis_int1_t *val)
4160 {
4161 lsm6dsr_i3c_bus_avb_t i3c_bus_avb;
4162 int32_t ret;
4163
4164 ret = lsm6dsr_read_reg(ctx, LSM6DSR_I3C_BUS_AVB,
4165 (uint8_t *)&i3c_bus_avb, 1);
4166
4167 switch (i3c_bus_avb.pd_dis_int1)
4168 {
4169 case LSM6DSR_PULL_DOWN_CONNECT:
4170 *val = LSM6DSR_PULL_DOWN_CONNECT;
4171 break;
4172
4173 case LSM6DSR_PULL_DOWN_DISC:
4174 *val = LSM6DSR_PULL_DOWN_DISC;
4175 break;
4176
4177 default:
4178 *val = LSM6DSR_PULL_DOWN_CONNECT;
4179 break;
4180 }
4181
4182 return ret;
4183 }
4184
4185 /**
4186 * @brief SPI Serial Interface Mode selection.[set]
4187 *
4188 * @param ctx Read / write interface definitions.(ptr)
4189 * @param val Change the values of sim in reg CTRL3_C
4190 * @retval Interface status (MANDATORY: return 0 -> no Error).
4191 *
4192 */
lsm6dsr_spi_mode_set(stmdev_ctx_t * ctx,lsm6dsr_sim_t val)4193 int32_t lsm6dsr_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsr_sim_t val)
4194 {
4195 lsm6dsr_ctrl3_c_t ctrl3_c;
4196 int32_t ret;
4197
4198 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4199
4200 if (ret == 0)
4201 {
4202 ctrl3_c.sim = (uint8_t)val;
4203 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4204 }
4205
4206 return ret;
4207 }
4208
4209 /**
4210 * @brief SPI Serial Interface Mode selection.[get]
4211 *
4212 * @param ctx Read / write interface definitions.(ptr)
4213 * @param val Get the values of sim in reg CTRL3_C
4214 * @retval Interface status (MANDATORY: return 0 -> no Error).
4215 *
4216 */
lsm6dsr_spi_mode_get(stmdev_ctx_t * ctx,lsm6dsr_sim_t * val)4217 int32_t lsm6dsr_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsr_sim_t *val)
4218 {
4219 lsm6dsr_ctrl3_c_t ctrl3_c;
4220 int32_t ret;
4221
4222 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4223
4224 switch (ctrl3_c.sim)
4225 {
4226 case LSM6DSR_SPI_4_WIRE:
4227 *val = LSM6DSR_SPI_4_WIRE;
4228 break;
4229
4230 case LSM6DSR_SPI_3_WIRE:
4231 *val = LSM6DSR_SPI_3_WIRE;
4232 break;
4233
4234 default:
4235 *val = LSM6DSR_SPI_4_WIRE;
4236 break;
4237 }
4238
4239 return ret;
4240 }
4241
4242 /**
4243 * @brief Disable / Enable I2C interface.[set]
4244 *
4245 * @param ctx Read / write interface definitions.(ptr)
4246 * @param val Change the values of i2c_disable in reg CTRL4_C
4247 * @retval Interface status (MANDATORY: return 0 -> no Error).
4248 *
4249 */
lsm6dsr_i2c_interface_set(stmdev_ctx_t * ctx,lsm6dsr_i2c_disable_t val)4250 int32_t lsm6dsr_i2c_interface_set(stmdev_ctx_t *ctx,
4251 lsm6dsr_i2c_disable_t val)
4252 {
4253 lsm6dsr_ctrl4_c_t ctrl4_c;
4254 int32_t ret;
4255
4256 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4257
4258 if (ret == 0)
4259 {
4260 ctrl4_c.i2c_disable = (uint8_t)val;
4261 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4262 }
4263
4264 return ret;
4265 }
4266
4267 /**
4268 * @brief Disable / Enable I2C interface.[get]
4269 *
4270 * @param ctx Read / write interface definitions.(ptr)
4271 * @param val Get the values of i2c reg CTRL4_C
4272 * @retval Interface status (MANDATORY: return 0 -> no Error).
4273 *
4274 */
lsm6dsr_i2c_interface_get(stmdev_ctx_t * ctx,lsm6dsr_i2c_disable_t * val)4275 int32_t lsm6dsr_i2c_interface_get(stmdev_ctx_t *ctx,
4276 lsm6dsr_i2c_disable_t *val)
4277 {
4278 lsm6dsr_ctrl4_c_t ctrl4_c;
4279 int32_t ret;
4280
4281 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4282
4283 switch (ctrl4_c.i2c_disable)
4284 {
4285 case LSM6DSR_I2C_ENABLE:
4286 *val = LSM6DSR_I2C_ENABLE;
4287 break;
4288
4289 case LSM6DSR_I2C_DISABLE:
4290 *val = LSM6DSR_I2C_DISABLE;
4291 break;
4292
4293 default:
4294 *val = LSM6DSR_I2C_ENABLE;
4295 break;
4296 }
4297
4298 return ret;
4299 }
4300
4301 /**
4302 * @brief I3C Enable/Disable communication protocol.[set]
4303 *
4304 * @param ctx Read / write interface definitions.(ptr)
4305 * @param val Change the values of i3c_disable in reg CTRL9_XL
4306 * @retval Interface status (MANDATORY: return 0 -> no Error).
4307 *
4308 */
lsm6dsr_i3c_disable_set(stmdev_ctx_t * ctx,lsm6dsr_i3c_disable_t val)4309 int32_t lsm6dsr_i3c_disable_set(stmdev_ctx_t *ctx,
4310 lsm6dsr_i3c_disable_t val)
4311 {
4312 lsm6dsr_ctrl9_xl_t ctrl9_xl;
4313 lsm6dsr_i3c_bus_avb_t i3c_bus_avb;
4314 int32_t ret;
4315
4316 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
4317
4318 if (ret == 0)
4319 {
4320 ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
4321 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL,
4322 (uint8_t *)&ctrl9_xl, 1);
4323 }
4324
4325 if (ret == 0)
4326 {
4327 ret = lsm6dsr_read_reg(ctx, LSM6DSR_I3C_BUS_AVB,
4328 (uint8_t *)&i3c_bus_avb, 1);
4329 }
4330
4331 if (ret == 0)
4332 {
4333 i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
4334 ret = lsm6dsr_write_reg(ctx, LSM6DSR_I3C_BUS_AVB,
4335 (uint8_t *)&i3c_bus_avb, 1);
4336 }
4337
4338 return ret;
4339 }
4340
4341 /**
4342 * @brief I3C Enable/Disable communication protocol.[get]
4343 *
4344 * @param ctx Read / write interface definitions.(ptr)
4345 * @param val Change the values of i3c_disable in reg CTRL9_XL
4346 * @retval Interface status (MANDATORY: return 0 -> no Error).
4347 *
4348 */
lsm6dsr_i3c_disable_get(stmdev_ctx_t * ctx,lsm6dsr_i3c_disable_t * val)4349 int32_t lsm6dsr_i3c_disable_get(stmdev_ctx_t *ctx,
4350 lsm6dsr_i3c_disable_t *val)
4351 {
4352 lsm6dsr_ctrl9_xl_t ctrl9_xl;
4353 lsm6dsr_i3c_bus_avb_t i3c_bus_avb;
4354 int32_t ret;
4355
4356 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
4357
4358 if (ret == 0)
4359 {
4360 ret = lsm6dsr_read_reg(ctx, LSM6DSR_I3C_BUS_AVB,
4361 (uint8_t *)&i3c_bus_avb, 1);
4362 }
4363
4364 switch ((ctrl9_xl.i3c_disable << 7) + i3c_bus_avb.i3c_bus_avb_sel)
4365 {
4366 case LSM6DSR_I3C_DISABLE:
4367 *val = LSM6DSR_I3C_DISABLE;
4368 break;
4369
4370 case LSM6DSR_I3C_ENABLE_T_50us:
4371 *val = LSM6DSR_I3C_ENABLE_T_50us;
4372 break;
4373
4374 case LSM6DSR_I3C_ENABLE_T_2us:
4375 *val = LSM6DSR_I3C_ENABLE_T_2us;
4376 break;
4377
4378 case LSM6DSR_I3C_ENABLE_T_1ms:
4379 *val = LSM6DSR_I3C_ENABLE_T_1ms;
4380 break;
4381
4382 case LSM6DSR_I3C_ENABLE_T_25ms:
4383 *val = LSM6DSR_I3C_ENABLE_T_25ms;
4384 break;
4385
4386 default:
4387 *val = LSM6DSR_I3C_DISABLE;
4388 break;
4389 }
4390
4391 return ret;
4392 }
4393
4394 /**
4395 * @}
4396 *
4397 */
4398
4399 /**
4400 * @defgroup LSM6DSR_interrupt_pins
4401 * @brief This section groups all the functions that manage
4402 * interrupt pins
4403 * @{
4404 *
4405 */
4406
4407 /**
4408 * @brief Select the signal that need to route on int1 pad[set]
4409 *
4410 * @param ctx Read / write interface definitions.(ptr)
4411 * @param val Structure of registers: INT1_CTRL,MD1_CFG,
4412 * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B
4413 * @retval Interface status (MANDATORY: return 0 -> no Error).
4414 *
4415 */
lsm6dsr_pin_int1_route_set(stmdev_ctx_t * ctx,lsm6dsr_pin_int1_route_t * val)4416 int32_t lsm6dsr_pin_int1_route_set(stmdev_ctx_t *ctx,
4417 lsm6dsr_pin_int1_route_t *val)
4418 {
4419 lsm6dsr_tap_cfg2_t tap_cfg2;
4420 int32_t ret;
4421
4422 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
4423
4424 if (ret == 0)
4425 {
4426 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_INT1,
4427 (uint8_t *)&val->emb_func_int1, 1);
4428 }
4429
4430 if (ret == 0)
4431 {
4432 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_INT1_A,
4433 (uint8_t *)&val->fsm_int1_a, 1);
4434 }
4435
4436 if (ret == 0)
4437 {
4438 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_INT1_B,
4439 (uint8_t *)&val->fsm_int1_b, 1);
4440 }
4441
4442 if (ret == 0)
4443 {
4444 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
4445 }
4446
4447 if (ret == 0)
4448 {
4449 if ((val->emb_func_int1.int1_fsm_lc |
4450 val->emb_func_int1.int1_sig_mot |
4451 val->emb_func_int1.int1_step_detector |
4452 val->emb_func_int1.int1_tilt |
4453 val->fsm_int1_a.int1_fsm1 |
4454 val->fsm_int1_a.int1_fsm2 |
4455 val->fsm_int1_a.int1_fsm3 |
4456 val->fsm_int1_a.int1_fsm4 |
4457 val->fsm_int1_a.int1_fsm5 |
4458 val->fsm_int1_a.int1_fsm6 |
4459 val->fsm_int1_a.int1_fsm7 |
4460 val->fsm_int1_a.int1_fsm8 |
4461 val->fsm_int1_b.int1_fsm9 |
4462 val->fsm_int1_b.int1_fsm10 |
4463 val->fsm_int1_b.int1_fsm11 |
4464 val->fsm_int1_b.int1_fsm12 |
4465 val->fsm_int1_b.int1_fsm13 |
4466 val->fsm_int1_b.int1_fsm14 |
4467 val->fsm_int1_b.int1_fsm15 |
4468 val->fsm_int1_b.int1_fsm16) != PROPERTY_DISABLE)
4469 {
4470 val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
4471 }
4472
4473 else
4474 {
4475 val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
4476 }
4477
4478 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT1_CTRL,
4479 (uint8_t *)&val->int1_ctrl, 1);
4480 }
4481
4482 if (ret == 0)
4483 {
4484 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MD1_CFG,
4485 (uint8_t *)&val->md1_cfg, 1);
4486 }
4487
4488 if (ret == 0)
4489 {
4490 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
4491
4492 if ((val->int1_ctrl.den_drdy_flag |
4493 val->int1_ctrl.int1_boot |
4494 val->int1_ctrl.int1_cnt_bdr |
4495 val->int1_ctrl.int1_drdy_g |
4496 val->int1_ctrl.int1_drdy_xl |
4497 val->int1_ctrl.int1_fifo_full |
4498 val->int1_ctrl.int1_fifo_ovr |
4499 val->int1_ctrl.int1_fifo_th |
4500 val->md1_cfg.int1_6d |
4501 val->md1_cfg.int1_double_tap |
4502 val->md1_cfg.int1_ff |
4503 val->md1_cfg.int1_wu |
4504 val->md1_cfg.int1_single_tap |
4505 val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
4506 {
4507 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
4508 }
4509
4510 else
4511 {
4512 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
4513 }
4514 }
4515
4516 if (ret == 0)
4517 {
4518 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG2,
4519 (uint8_t *)&tap_cfg2, 1);
4520 }
4521
4522 return ret;
4523 }
4524
4525 /**
4526 * @brief Select the signal that need to route on int1 pad.[get]
4527 *
4528 * @param ctx Read / write interface definitions.(ptr)
4529 * @param val Structure of registers: INT1_CTRL, MD1_CFG,
4530 * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B.(ptr)
4531 * @retval Interface status (MANDATORY: return 0 -> no Error).
4532 *
4533 */
lsm6dsr_pin_int1_route_get(stmdev_ctx_t * ctx,lsm6dsr_pin_int1_route_t * val)4534 int32_t lsm6dsr_pin_int1_route_get(stmdev_ctx_t *ctx,
4535 lsm6dsr_pin_int1_route_t *val)
4536 {
4537 int32_t ret;
4538
4539 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
4540
4541 if (ret == 0)
4542 {
4543 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_INT1,
4544 (uint8_t *)&val->emb_func_int1, 1);
4545 }
4546
4547 if (ret == 0)
4548 {
4549 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_INT1_A,
4550 (uint8_t *)&val->fsm_int1_a, 1);
4551 }
4552
4553 if (ret == 0)
4554 {
4555 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_INT1_B,
4556 (uint8_t *)&val->fsm_int1_b, 1);
4557 }
4558
4559 if (ret == 0)
4560 {
4561 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
4562 }
4563
4564 if (ret == 0)
4565 {
4566 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT1_CTRL,
4567 (uint8_t *)&val->int1_ctrl, 1);
4568 }
4569
4570 if (ret == 0)
4571 {
4572 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MD1_CFG,
4573 (uint8_t *)&val->md1_cfg, 1);
4574 }
4575
4576 return ret;
4577 }
4578
4579 /**
4580 * @brief Select the signal that need to route on int2 pad[set]
4581 *
4582 * @param ctx Read / write interface definitions.(ptr)
4583 * @param val Structure of registers INT2_CTRL, MD2_CFG,
4584 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
4585 * @retval Interface status (MANDATORY: return 0 -> no Error).
4586 *
4587 */
lsm6dsr_pin_int2_route_set(stmdev_ctx_t * ctx,lsm6dsr_pin_int2_route_t * val)4588 int32_t lsm6dsr_pin_int2_route_set(stmdev_ctx_t *ctx,
4589 lsm6dsr_pin_int2_route_t *val)
4590 {
4591 lsm6dsr_tap_cfg2_t tap_cfg2;
4592 int32_t ret;
4593
4594 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
4595
4596 if (ret == 0)
4597 {
4598 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_INT2,
4599 (uint8_t *)&val->emb_func_int2, 1);
4600 }
4601
4602 if (ret == 0)
4603 {
4604 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_INT2_A,
4605 (uint8_t *)&val->fsm_int2_a, 1);
4606 }
4607
4608 if (ret == 0)
4609 {
4610 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_INT2_B,
4611 (uint8_t *)&val->fsm_int2_b, 1);
4612 }
4613
4614 if (ret == 0)
4615 {
4616 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
4617 }
4618
4619 if (ret == 0)
4620 {
4621 if ((val->emb_func_int2.int2_step_detector |
4622 val->emb_func_int2.int2_tilt |
4623 val->emb_func_int2.int2_sig_mot |
4624 val->emb_func_int2.int2_fsm_lc |
4625 val->fsm_int2_a.int2_fsm1 |
4626 val->fsm_int2_a.int2_fsm2 |
4627 val->fsm_int2_a.int2_fsm3 |
4628 val->fsm_int2_a.int2_fsm4 |
4629 val->fsm_int2_a.int2_fsm5 |
4630 val->fsm_int2_a.int2_fsm6 |
4631 val->fsm_int2_a.int2_fsm7 |
4632 val->fsm_int2_a.int2_fsm8 |
4633 val->fsm_int2_b.int2_fsm9 |
4634 val->fsm_int2_b.int2_fsm10 |
4635 val->fsm_int2_b.int2_fsm11 |
4636 val->fsm_int2_b.int2_fsm12 |
4637 val->fsm_int2_b.int2_fsm13 |
4638 val->fsm_int2_b.int2_fsm14 |
4639 val->fsm_int2_b.int2_fsm15 |
4640 val->fsm_int2_b.int2_fsm16) != PROPERTY_DISABLE)
4641 {
4642 val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
4643 }
4644
4645 else
4646 {
4647 val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
4648 }
4649
4650 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT2_CTRL,
4651 (uint8_t *)&val->int2_ctrl, 1);
4652 }
4653
4654 if (ret == 0)
4655 {
4656 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MD2_CFG,
4657 (uint8_t *)&val->md2_cfg, 1);
4658 }
4659
4660 if (ret == 0)
4661 {
4662 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2,
4663 (uint8_t *)&tap_cfg2, 1);
4664 }
4665
4666 if (ret == 0)
4667 {
4668 if ((val->int2_ctrl.int2_drdy_xl |
4669 val->int2_ctrl.int2_drdy_g |
4670 val->int2_ctrl.int2_drdy_temp |
4671 val->int2_ctrl.int2_fifo_th |
4672 val->int2_ctrl.int2_fifo_ovr |
4673 val->int2_ctrl.int2_fifo_full |
4674 val->int2_ctrl.int2_cnt_bdr |
4675 val->md2_cfg.int2_6d |
4676 val->md2_cfg.int2_double_tap |
4677 val->md2_cfg.int2_ff |
4678 val->md2_cfg.int2_wu |
4679 val->md2_cfg.int2_single_tap |
4680 val->md2_cfg.int2_sleep_change) != PROPERTY_DISABLE)
4681 {
4682 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
4683 }
4684
4685 else
4686 {
4687 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
4688 }
4689
4690 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG2,
4691 (uint8_t *)&tap_cfg2, 1);
4692 }
4693
4694 return ret;
4695 }
4696
4697 /**
4698 * @brief Select the signal that need to route on int2 pad.[get]
4699 *
4700 * @param ctx Read / write interface definitions.(ptr)
4701 * @param val Structure of registers INT2_CTRL, MD2_CFG,
4702 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B.[get]
4703 * @retval Interface status (MANDATORY: return 0 -> no Error).
4704 *
4705 */
lsm6dsr_pin_int2_route_get(stmdev_ctx_t * ctx,lsm6dsr_pin_int2_route_t * val)4706 int32_t lsm6dsr_pin_int2_route_get(stmdev_ctx_t *ctx,
4707 lsm6dsr_pin_int2_route_t *val)
4708 {
4709 int32_t ret;
4710
4711 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
4712
4713 if (ret == 0)
4714 {
4715 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_INT2,
4716 (uint8_t *)&val->emb_func_int2, 1);
4717 }
4718
4719 if (ret == 0)
4720 {
4721 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_INT2_A,
4722 (uint8_t *)&val->fsm_int2_a, 1);
4723 }
4724
4725 if (ret == 0)
4726 {
4727 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_INT2_B,
4728 (uint8_t *)&val->fsm_int2_b, 1);
4729 }
4730
4731 if (ret == 0)
4732 {
4733 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
4734 }
4735
4736 if (ret == 0)
4737 {
4738 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT2_CTRL,
4739 (uint8_t *)&val->int2_ctrl, 1);
4740 }
4741
4742 if (ret == 0)
4743 {
4744 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MD2_CFG,
4745 (uint8_t *)&val->md2_cfg, 1);
4746 }
4747
4748 return ret;
4749 }
4750
4751 /**
4752 * @brief Push-pull/open drain selection on interrupt pads.[set]
4753 *
4754 * @param ctx Read / write interface definitions.(ptr)
4755 * @param val Change the values of pp_od in reg CTRL3_C
4756 * @retval Interface status (MANDATORY: return 0 -> no Error).
4757 *
4758 */
lsm6dsr_pin_mode_set(stmdev_ctx_t * ctx,lsm6dsr_pp_od_t val)4759 int32_t lsm6dsr_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsr_pp_od_t val)
4760 {
4761 lsm6dsr_ctrl3_c_t ctrl3_c;
4762 int32_t ret;
4763
4764 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4765
4766 if (ret == 0)
4767 {
4768 ctrl3_c.pp_od = (uint8_t)val;
4769 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4770 }
4771
4772 return ret;
4773 }
4774
4775 /**
4776 * @brief Push-pull/open drain selection on interrupt pads.[get]
4777 *
4778 * @param ctx Read / write interface definitions.(ptr)
4779 * @param val Get the values of pp_od in reg CTRL3_C
4780 * @retval Interface status (MANDATORY: return 0 -> no Error).
4781 *
4782 */
lsm6dsr_pin_mode_get(stmdev_ctx_t * ctx,lsm6dsr_pp_od_t * val)4783 int32_t lsm6dsr_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsr_pp_od_t *val)
4784 {
4785 lsm6dsr_ctrl3_c_t ctrl3_c;
4786 int32_t ret;
4787
4788 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4789
4790 switch (ctrl3_c.pp_od)
4791 {
4792 case LSM6DSR_PUSH_PULL:
4793 *val = LSM6DSR_PUSH_PULL;
4794 break;
4795
4796 case LSM6DSR_OPEN_DRAIN:
4797 *val = LSM6DSR_OPEN_DRAIN;
4798 break;
4799
4800 default:
4801 *val = LSM6DSR_PUSH_PULL;
4802 break;
4803 }
4804
4805 return ret;
4806 }
4807
4808 /**
4809 * @brief Interrupt active-high/low.[set]
4810 *
4811 * @param ctx Read / write interface definitions.(ptr)
4812 * @param val Change the values of h_lactive in reg CTRL3_C
4813 * @retval Interface status (MANDATORY: return 0 -> no Error).
4814 *
4815 */
lsm6dsr_pin_polarity_set(stmdev_ctx_t * ctx,lsm6dsr_h_lactive_t val)4816 int32_t lsm6dsr_pin_polarity_set(stmdev_ctx_t *ctx,
4817 lsm6dsr_h_lactive_t val)
4818 {
4819 lsm6dsr_ctrl3_c_t ctrl3_c;
4820 int32_t ret;
4821
4822 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4823
4824 if (ret == 0)
4825 {
4826 ctrl3_c.h_lactive = (uint8_t)val;
4827 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4828 }
4829
4830 return ret;
4831 }
4832
4833 /**
4834 * @brief Interrupt active-high/low.[get]
4835 *
4836 * @param ctx Read / write interface definitions.(ptr)
4837 * @param val Get the values of h_lactive in reg CTRL3_C
4838 * @retval Interface status (MANDATORY: return 0 -> no Error).
4839 *
4840 */
lsm6dsr_pin_polarity_get(stmdev_ctx_t * ctx,lsm6dsr_h_lactive_t * val)4841 int32_t lsm6dsr_pin_polarity_get(stmdev_ctx_t *ctx,
4842 lsm6dsr_h_lactive_t *val)
4843 {
4844 lsm6dsr_ctrl3_c_t ctrl3_c;
4845 int32_t ret;
4846
4847 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4848
4849 switch (ctrl3_c.h_lactive)
4850 {
4851 case LSM6DSR_ACTIVE_HIGH:
4852 *val = LSM6DSR_ACTIVE_HIGH;
4853 break;
4854
4855 case LSM6DSR_ACTIVE_LOW:
4856 *val = LSM6DSR_ACTIVE_LOW;
4857 break;
4858
4859 default:
4860 *val = LSM6DSR_ACTIVE_HIGH;
4861 break;
4862 }
4863
4864 return ret;
4865 }
4866
4867 /**
4868 * @brief All interrupt signals become available on INT1 pin.[set]
4869 *
4870 * @param ctx Read / write interface definitions.(ptr)
4871 * @param val Change the values of int2_on_int1 in reg CTRL4_C
4872 * @retval Interface status (MANDATORY: return 0 -> no Error).
4873 *
4874 */
lsm6dsr_all_on_int1_set(stmdev_ctx_t * ctx,uint8_t val)4875 int32_t lsm6dsr_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
4876 {
4877 lsm6dsr_ctrl4_c_t ctrl4_c;
4878 int32_t ret;
4879
4880 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4881
4882 if (ret == 0)
4883 {
4884 ctrl4_c.int2_on_int1 = (uint8_t)val;
4885 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4886 }
4887
4888 return ret;
4889 }
4890
4891 /**
4892 * @brief All interrupt signals become available on INT1 pin.[get]
4893 *
4894 * @param ctx Read / write interface definitions.(ptr)
4895 * @param val Change the values of int2_on_int1 in reg CTRL4_C
4896 * @retval Interface status (MANDATORY: return 0 -> no Error).
4897 *
4898 */
lsm6dsr_all_on_int1_get(stmdev_ctx_t * ctx,uint8_t * val)4899 int32_t lsm6dsr_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
4900 {
4901 lsm6dsr_ctrl4_c_t ctrl4_c;
4902 int32_t ret;
4903
4904 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4905 *val = ctrl4_c.int2_on_int1;
4906
4907 return ret;
4908 }
4909
4910 /**
4911 * @brief All interrupt signals notification mode.[set]
4912 *
4913 * @param ctx Read / write interface definitions.(ptr)
4914 * @param val Change the values of lir in reg TAP_CFG0
4915 * @retval Interface status (MANDATORY: return 0 -> no Error).
4916 *
4917 */
lsm6dsr_int_notification_set(stmdev_ctx_t * ctx,lsm6dsr_lir_t val)4918 int32_t lsm6dsr_int_notification_set(stmdev_ctx_t *ctx,
4919 lsm6dsr_lir_t val)
4920 {
4921 lsm6dsr_tap_cfg0_t tap_cfg0;
4922 lsm6dsr_page_rw_t page_rw;
4923 int32_t ret;
4924
4925 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4926
4927 if (ret == 0)
4928 {
4929 tap_cfg0.lir = (uint8_t)val & 0x01U;
4930 tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
4931 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG0,
4932 (uint8_t *)&tap_cfg0, 1);
4933 }
4934
4935 if (ret == 0)
4936 {
4937 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
4938 }
4939
4940 if (ret == 0)
4941 {
4942 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
4943 }
4944
4945 if (ret == 0)
4946 {
4947 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
4948 ret = lsm6dsr_write_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
4949 }
4950
4951 if (ret == 0)
4952 {
4953 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
4954 }
4955
4956 return ret;
4957 }
4958
4959 /**
4960 * @brief All interrupt signals notification mode.[get]
4961 *
4962 * @param ctx Read / write interface definitions.(ptr)
4963 * @param val Get the values of lir in reg TAP_CFG0
4964 * @retval Interface status (MANDATORY: return 0 -> no Error).
4965 *
4966 */
lsm6dsr_int_notification_get(stmdev_ctx_t * ctx,lsm6dsr_lir_t * val)4967 int32_t lsm6dsr_int_notification_get(stmdev_ctx_t *ctx,
4968 lsm6dsr_lir_t *val)
4969 {
4970 lsm6dsr_tap_cfg0_t tap_cfg0;
4971 lsm6dsr_page_rw_t page_rw;
4972 int32_t ret;
4973
4974 *val = LSM6DSR_ALL_INT_PULSED;
4975 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
4976
4977 if (ret == 0)
4978 {
4979 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
4980 }
4981
4982 if (ret == 0)
4983 {
4984 ret = lsm6dsr_read_reg(ctx, LSM6DSR_PAGE_RW, (uint8_t *)&page_rw, 1);
4985 }
4986
4987 if (ret == 0)
4988 {
4989 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
4990 }
4991
4992 switch ((page_rw.emb_func_lir << 1) + tap_cfg0.lir)
4993 {
4994 case LSM6DSR_ALL_INT_PULSED:
4995 *val = LSM6DSR_ALL_INT_PULSED;
4996 break;
4997
4998 case LSM6DSR_BASE_LATCHED_EMB_PULSED:
4999 *val = LSM6DSR_BASE_LATCHED_EMB_PULSED;
5000 break;
5001
5002 case LSM6DSR_BASE_PULSED_EMB_LATCHED:
5003 *val = LSM6DSR_BASE_PULSED_EMB_LATCHED;
5004 break;
5005
5006 case LSM6DSR_ALL_INT_LATCHED:
5007 *val = LSM6DSR_ALL_INT_LATCHED;
5008 break;
5009
5010 default:
5011 *val = LSM6DSR_ALL_INT_PULSED;
5012 break;
5013 }
5014
5015 return ret;
5016 }
5017
5018 /**
5019 * @}
5020 *
5021 */
5022
5023 /**
5024 * @defgroup LSM6DSR_Wake_Up_event
5025 * @brief This section groups all the functions that manage the
5026 * Wake Up event generation.
5027 * @{
5028 *
5029 */
5030
5031 /**
5032 * @brief Weight of 1 LSB of wakeup threshold.[set]
5033 * 0: 1 LSB =FS_XL / 64
5034 * 1: 1 LSB = FS_XL / 256
5035 *
5036 * @param ctx Read / write interface definitions.(ptr)
5037 * @param val Change the values of wake_ths_w in reg WAKE_UP_DUR
5038 * @retval Interface status (MANDATORY: return 0 -> no Error).
5039 *
5040 */
lsm6dsr_wkup_ths_weight_set(stmdev_ctx_t * ctx,lsm6dsr_wake_ths_w_t val)5041 int32_t lsm6dsr_wkup_ths_weight_set(stmdev_ctx_t *ctx,
5042 lsm6dsr_wake_ths_w_t val)
5043 {
5044 lsm6dsr_wake_up_dur_t wake_up_dur;
5045 int32_t ret;
5046
5047 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
5048 (uint8_t *)&wake_up_dur, 1);
5049
5050 if (ret == 0)
5051 {
5052 wake_up_dur.wake_ths_w = (uint8_t)val;
5053 ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_DUR,
5054 (uint8_t *)&wake_up_dur, 1);
5055 }
5056
5057 return ret;
5058 }
5059
5060 /**
5061 * @brief Weight of 1 LSB of wakeup threshold.[get]
5062 * 0: 1 LSB =FS_XL / 64
5063 * 1: 1 LSB = FS_XL / 256
5064 *
5065 * @param ctx Read / write interface definitions.(ptr)
5066 * @param val Get the values of wake_ths_w in reg WAKE_UP_DUR
5067 * @retval Interface status (MANDATORY: return 0 -> no Error).
5068 *
5069 */
lsm6dsr_wkup_ths_weight_get(stmdev_ctx_t * ctx,lsm6dsr_wake_ths_w_t * val)5070 int32_t lsm6dsr_wkup_ths_weight_get(stmdev_ctx_t *ctx,
5071 lsm6dsr_wake_ths_w_t *val)
5072 {
5073 lsm6dsr_wake_up_dur_t wake_up_dur;
5074 int32_t ret;
5075
5076 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
5077 (uint8_t *)&wake_up_dur, 1);
5078
5079 switch (wake_up_dur.wake_ths_w)
5080 {
5081 case LSM6DSR_LSb_FS_DIV_64:
5082 *val = LSM6DSR_LSb_FS_DIV_64;
5083 break;
5084
5085 case LSM6DSR_LSb_FS_DIV_256:
5086 *val = LSM6DSR_LSb_FS_DIV_256;
5087 break;
5088
5089 default:
5090 *val = LSM6DSR_LSb_FS_DIV_64;
5091 break;
5092 }
5093
5094 return ret;
5095 }
5096
5097 /**
5098 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
5099 * WAKE_UP_DUR.[set]
5100 *
5101 * @param ctx Read / write interface definitions.(ptr)
5102 * @param val Change the values of wk_ths in reg WAKE_UP_THS
5103 * @retval Interface status (MANDATORY: return 0 -> no Error).
5104 *
5105 */
lsm6dsr_wkup_threshold_set(stmdev_ctx_t * ctx,uint8_t val)5106 int32_t lsm6dsr_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
5107 {
5108 lsm6dsr_wake_up_ths_t wake_up_ths;
5109 int32_t ret;
5110
5111 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS,
5112 (uint8_t *)&wake_up_ths, 1);
5113
5114 if (ret == 0)
5115 {
5116 wake_up_ths.wk_ths = (uint8_t)val;
5117 ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_THS,
5118 (uint8_t *)&wake_up_ths, 1);
5119 }
5120
5121 return ret;
5122 }
5123
5124 /**
5125 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
5126 * WAKE_UP_DUR.[get]
5127 *
5128 * @param ctx Read / write interface definitions.(ptr)
5129 * @param val Change the values of wk_ths in reg WAKE_UP_THS
5130 * @retval Interface status (MANDATORY: return 0 -> no Error).
5131 *
5132 */
lsm6dsr_wkup_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)5133 int32_t lsm6dsr_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
5134 {
5135 lsm6dsr_wake_up_ths_t wake_up_ths;
5136 int32_t ret;
5137
5138 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS,
5139 (uint8_t *)&wake_up_ths, 1);
5140 *val = wake_up_ths.wk_ths;
5141
5142 return ret;
5143 }
5144
5145 /**
5146 * @brief Wake up duration event( 1LSb = 1 / ODR ).[set]
5147 *
5148 * @param ctx Read / write interface definitions.(ptr)
5149 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
5150 * @retval Interface status (MANDATORY: return 0 -> no Error).
5151 *
5152 */
lsm6dsr_xl_usr_offset_on_wkup_set(stmdev_ctx_t * ctx,uint8_t val)5153 int32_t lsm6dsr_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
5154 uint8_t val)
5155 {
5156 lsm6dsr_wake_up_ths_t wake_up_ths;
5157 int32_t ret;
5158
5159 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS,
5160 (uint8_t *)&wake_up_ths, 1);
5161
5162 if (ret == 0)
5163 {
5164 wake_up_ths.usr_off_on_wu = (uint8_t)val;
5165 ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_THS,
5166 (uint8_t *)&wake_up_ths, 1);
5167 }
5168
5169 return ret;
5170 }
5171
5172 /**
5173 * @brief Wake up duration event( 1LSb = 1 / ODR ).[get]
5174 *
5175 * @param ctx Read / write interface definitions.(ptr)
5176 * @param val Change the values of usr_off_on_wu in reg WAKE_UP_THS
5177 * @retval Interface status (MANDATORY: return 0 -> no Error).
5178 *
5179 */
lsm6dsr_xl_usr_offset_on_wkup_get(stmdev_ctx_t * ctx,uint8_t * val)5180 int32_t lsm6dsr_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
5181 uint8_t *val)
5182 {
5183 lsm6dsr_wake_up_ths_t wake_up_ths;
5184 int32_t ret;
5185
5186 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS,
5187 (uint8_t *)&wake_up_ths, 1);
5188 *val = wake_up_ths.usr_off_on_wu;
5189
5190 return ret;
5191 }
5192
5193 /**
5194 * @brief Wake up duration event(1LSb = 1 / ODR).[set]
5195 *
5196 * @param ctx Read / write interface definitions.(ptr)
5197 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
5198 * @retval Interface status (MANDATORY: return 0 -> no Error).
5199 *
5200 */
lsm6dsr_wkup_dur_set(stmdev_ctx_t * ctx,uint8_t val)5201 int32_t lsm6dsr_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
5202 {
5203 lsm6dsr_wake_up_dur_t wake_up_dur;
5204 int32_t ret;
5205
5206 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
5207 (uint8_t *)&wake_up_dur, 1);
5208
5209 if (ret == 0)
5210 {
5211 wake_up_dur.wake_dur = (uint8_t)val;
5212 ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_DUR,
5213 (uint8_t *)&wake_up_dur, 1);
5214 }
5215
5216 return ret;
5217 }
5218
5219 /**
5220 * @brief Wake up duration event(1LSb = 1 / ODR).[get]
5221 *
5222 * @param ctx Read / write interface definitions.(ptr)
5223 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
5224 * @retval Interface status (MANDATORY: return 0 -> no Error).
5225 *
5226 */
lsm6dsr_wkup_dur_get(stmdev_ctx_t * ctx,uint8_t * val)5227 int32_t lsm6dsr_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
5228 {
5229 lsm6dsr_wake_up_dur_t wake_up_dur;
5230 int32_t ret;
5231
5232 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
5233 (uint8_t *)&wake_up_dur, 1);
5234 *val = wake_up_dur.wake_dur;
5235
5236 return ret;
5237 }
5238
5239 /**
5240 * @}
5241 *
5242 */
5243
5244 /**
5245 * @defgroup LSM6DSR_ Activity/Inactivity_detection
5246 * @brief This section groups all the functions concerning
5247 * activity/inactivity detection.
5248 * @{
5249 *
5250 */
5251
5252 /**
5253 * @brief Enables gyroscope Sleep mode.[set]
5254 *
5255 * @param ctx Read / write interface definitions.(ptr)
5256 * @param val Change the values of sleep_g in reg CTRL4_C
5257 * @retval Interface status (MANDATORY: return 0 -> no Error).
5258 *
5259 */
lsm6dsr_gy_sleep_mode_set(stmdev_ctx_t * ctx,uint8_t val)5260 int32_t lsm6dsr_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
5261 {
5262 lsm6dsr_ctrl4_c_t ctrl4_c;
5263 int32_t ret;
5264
5265 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
5266
5267 if (ret == 0)
5268 {
5269 ctrl4_c.sleep_g = (uint8_t)val;
5270 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
5271 }
5272
5273 return ret;
5274 }
5275
5276 /**
5277 * @brief Enables gyroscope Sleep mode.[get]
5278 *
5279 * @param ctx Read / write interface definitions.(ptr)
5280 * @param val Change the values of sleep_g in reg CTRL4_C
5281 * @retval Interface status (MANDATORY: return 0 -> no Error).
5282 *
5283 */
lsm6dsr_gy_sleep_mode_get(stmdev_ctx_t * ctx,uint8_t * val)5284 int32_t lsm6dsr_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
5285 {
5286 lsm6dsr_ctrl4_c_t ctrl4_c;
5287 int32_t ret;
5288
5289 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
5290 *val = ctrl4_c.sleep_g;
5291
5292 return ret;
5293 }
5294
5295 /**
5296 * @brief Drives the sleep status instead of sleep change on INT pins
5297 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
5298 * are enabled).[set]
5299 *
5300 * @param ctx Read / write interface definitions.(ptr)
5301 * @param val Change the values of sleep_status_on_int in reg TAP_CFG0
5302 * @retval Interface status (MANDATORY: return 0 -> no Error).
5303 *
5304 */
lsm6dsr_act_pin_notification_set(stmdev_ctx_t * ctx,lsm6dsr_sleep_status_on_int_t val)5305 int32_t lsm6dsr_act_pin_notification_set(stmdev_ctx_t *ctx,
5306 lsm6dsr_sleep_status_on_int_t val)
5307 {
5308 lsm6dsr_tap_cfg0_t tap_cfg0;
5309 int32_t ret;
5310
5311 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5312
5313 if (ret == 0)
5314 {
5315 tap_cfg0. sleep_status_on_int = (uint8_t)val;
5316 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG0,
5317 (uint8_t *)&tap_cfg0, 1);
5318 }
5319
5320 return ret;
5321 }
5322
5323 /**
5324 * @brief Drives the sleep status instead of sleep change on INT pins
5325 * (only if INT1_SLEEP_CHANGE or INT2_SLEEP_CHANGE bits
5326 * are enabled).[get]
5327 *
5328 * @param ctx Read / write interface definitions.(ptr)
5329 * @param val Get the values of sleep_status_on_int in reg TAP_CFG0
5330 * @retval Interface status (MANDATORY: return 0 -> no Error).
5331 *
5332 */
lsm6dsr_act_pin_notification_get(stmdev_ctx_t * ctx,lsm6dsr_sleep_status_on_int_t * val)5333 int32_t lsm6dsr_act_pin_notification_get(stmdev_ctx_t *ctx,
5334 lsm6dsr_sleep_status_on_int_t *val)
5335 {
5336 lsm6dsr_tap_cfg0_t tap_cfg0;
5337 int32_t ret;
5338
5339 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5340
5341 switch (tap_cfg0. sleep_status_on_int)
5342 {
5343 case LSM6DSR_DRIVE_SLEEP_CHG_EVENT:
5344 *val = LSM6DSR_DRIVE_SLEEP_CHG_EVENT;
5345 break;
5346
5347 case LSM6DSR_DRIVE_SLEEP_STATUS:
5348 *val = LSM6DSR_DRIVE_SLEEP_STATUS;
5349 break;
5350
5351 default:
5352 *val = LSM6DSR_DRIVE_SLEEP_CHG_EVENT;
5353 break;
5354 }
5355
5356 return ret;
5357 }
5358
5359 /**
5360 * @brief Enable inactivity function.[set]
5361 *
5362 * @param ctx Read / write interface definitions.(ptr)
5363 * @param val Change the values of inact_en in reg TAP_CFG2
5364 * @retval Interface status (MANDATORY: return 0 -> no Error).
5365 *
5366 */
lsm6dsr_act_mode_set(stmdev_ctx_t * ctx,lsm6dsr_inact_en_t val)5367 int32_t lsm6dsr_act_mode_set(stmdev_ctx_t *ctx,
5368 lsm6dsr_inact_en_t val)
5369 {
5370 lsm6dsr_tap_cfg2_t tap_cfg2;
5371 int32_t ret;
5372
5373 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
5374
5375 if (ret == 0)
5376 {
5377 tap_cfg2.inact_en = (uint8_t)val;
5378 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
5379 }
5380
5381 return ret;
5382 }
5383
5384 /**
5385 * @brief Enable inactivity function.[get]
5386 *
5387 * @param ctx Read / write interface definitions.(ptr)
5388 * @param val Get the values of inact_en in reg TAP_CFG2
5389 * @retval Interface status (MANDATORY: return 0 -> no Error).
5390 *
5391 */
lsm6dsr_act_mode_get(stmdev_ctx_t * ctx,lsm6dsr_inact_en_t * val)5392 int32_t lsm6dsr_act_mode_get(stmdev_ctx_t *ctx,
5393 lsm6dsr_inact_en_t *val)
5394 {
5395 lsm6dsr_tap_cfg2_t tap_cfg2;
5396 int32_t ret;
5397
5398 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
5399
5400 switch (tap_cfg2.inact_en)
5401 {
5402 case LSM6DSR_XL_AND_GY_NOT_AFFECTED:
5403 *val = LSM6DSR_XL_AND_GY_NOT_AFFECTED;
5404 break;
5405
5406 case LSM6DSR_XL_12Hz5_GY_NOT_AFFECTED:
5407 *val = LSM6DSR_XL_12Hz5_GY_NOT_AFFECTED;
5408 break;
5409
5410 case LSM6DSR_XL_12Hz5_GY_SLEEP:
5411 *val = LSM6DSR_XL_12Hz5_GY_SLEEP;
5412 break;
5413
5414 case LSM6DSR_XL_12Hz5_GY_PD:
5415 *val = LSM6DSR_XL_12Hz5_GY_PD;
5416 break;
5417
5418 default:
5419 *val = LSM6DSR_XL_AND_GY_NOT_AFFECTED;
5420 break;
5421 }
5422
5423 return ret;
5424 }
5425
5426 /**
5427 * @brief Duration to go in sleep mode (1 LSb = 512 / ODR).[set]
5428 *
5429 * @param ctx Read / write interface definitions.(ptr)
5430 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
5431 * @retval Interface status (MANDATORY: return 0 -> no Error).
5432 *
5433 */
lsm6dsr_act_sleep_dur_set(stmdev_ctx_t * ctx,uint8_t val)5434 int32_t lsm6dsr_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
5435 {
5436 lsm6dsr_wake_up_dur_t wake_up_dur;
5437 int32_t ret;
5438
5439 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
5440 (uint8_t *)&wake_up_dur, 1);
5441
5442 if (ret == 0)
5443 {
5444 wake_up_dur.sleep_dur = (uint8_t)val;
5445 ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_DUR,
5446 (uint8_t *)&wake_up_dur, 1);
5447 }
5448
5449 return ret;
5450 }
5451
5452 /**
5453 * @brief Duration to go in sleep mode.(1 LSb = 512 / ODR).[get]
5454 *
5455 * @param ctx Read / write interface definitions.(ptr)
5456 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
5457 * @retval Interface status (MANDATORY: return 0 -> no Error).
5458 *
5459 */
lsm6dsr_act_sleep_dur_get(stmdev_ctx_t * ctx,uint8_t * val)5460 int32_t lsm6dsr_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
5461 {
5462 lsm6dsr_wake_up_dur_t wake_up_dur;
5463 int32_t ret;
5464
5465 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
5466 (uint8_t *)&wake_up_dur, 1);
5467 *val = wake_up_dur.sleep_dur;
5468
5469 return ret;
5470 }
5471
5472 /**
5473 * @}
5474 *
5475 */
5476
5477 /**
5478 * @defgroup LSM6DSR_tap_generator
5479 * @brief This section groups all the functions that manage the
5480 * tap and double tap event generation.
5481 * @{
5482 *
5483 */
5484
5485 /**
5486 * @brief Enable Z direction in tap recognition.[set]
5487 *
5488 * @param ctx Read / write interface definitions.(ptr)
5489 * @param val Change the values of tap_z_en in reg TAP_CFG0
5490 * @retval Interface status (MANDATORY: return 0 -> no Error).
5491 *
5492 */
lsm6dsr_tap_detection_on_z_set(stmdev_ctx_t * ctx,uint8_t val)5493 int32_t lsm6dsr_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
5494 {
5495 lsm6dsr_tap_cfg0_t tap_cfg0;
5496 int32_t ret;
5497
5498 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5499
5500 if (ret == 0)
5501 {
5502 tap_cfg0.tap_z_en = (uint8_t)val;
5503 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG0,
5504 (uint8_t *)&tap_cfg0, 1);
5505 }
5506
5507 return ret;
5508 }
5509
5510 /**
5511 * @brief Enable Z direction in tap recognition.[get]
5512 *
5513 * @param ctx Read / write interface definitions.(ptr)
5514 * @param val Change the values of tap_z_en in reg TAP_CFG0
5515 * @retval Interface status (MANDATORY: return 0 -> no Error).
5516 *
5517 */
lsm6dsr_tap_detection_on_z_get(stmdev_ctx_t * ctx,uint8_t * val)5518 int32_t lsm6dsr_tap_detection_on_z_get(stmdev_ctx_t *ctx,
5519 uint8_t *val)
5520 {
5521 lsm6dsr_tap_cfg0_t tap_cfg0;
5522 int32_t ret;
5523
5524 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5525 *val = tap_cfg0.tap_z_en;
5526
5527 return ret;
5528 }
5529
5530 /**
5531 * @brief Enable Y direction in tap recognition.[set]
5532 *
5533 * @param ctx Read / write interface definitions.(ptr)
5534 * @param val Change the values of tap_y_en in reg TAP_CFG0
5535 * @retval Interface status (MANDATORY: return 0 -> no Error).
5536 *
5537 */
lsm6dsr_tap_detection_on_y_set(stmdev_ctx_t * ctx,uint8_t val)5538 int32_t lsm6dsr_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
5539 {
5540 lsm6dsr_tap_cfg0_t tap_cfg0;
5541 int32_t ret;
5542
5543 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5544
5545 if (ret == 0)
5546 {
5547 tap_cfg0.tap_y_en = (uint8_t)val;
5548 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG0,
5549 (uint8_t *)&tap_cfg0, 1);
5550 }
5551
5552 return ret;
5553 }
5554
5555 /**
5556 * @brief Enable Y direction in tap recognition.[get]
5557 *
5558 * @param ctx Read / write interface definitions.(ptr)
5559 * @param val Change the values of tap_y_en in reg TAP_CFG0
5560 * @retval Interface status (MANDATORY: return 0 -> no Error).
5561 *
5562 */
lsm6dsr_tap_detection_on_y_get(stmdev_ctx_t * ctx,uint8_t * val)5563 int32_t lsm6dsr_tap_detection_on_y_get(stmdev_ctx_t *ctx,
5564 uint8_t *val)
5565 {
5566 lsm6dsr_tap_cfg0_t tap_cfg0;
5567 int32_t ret;
5568
5569 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5570 *val = tap_cfg0.tap_y_en;
5571
5572 return ret;
5573 }
5574
5575 /**
5576 * @brief Enable X direction in tap recognition.[set]
5577 *
5578 * @param ctx Read / write interface definitions.(ptr)
5579 * @param val Change the values of tap_x_en in reg TAP_CFG0
5580 * @retval Interface status (MANDATORY: return 0 -> no Error).
5581 *
5582 */
lsm6dsr_tap_detection_on_x_set(stmdev_ctx_t * ctx,uint8_t val)5583 int32_t lsm6dsr_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
5584 {
5585 lsm6dsr_tap_cfg0_t tap_cfg0;
5586 int32_t ret;
5587
5588 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5589
5590 if (ret == 0)
5591 {
5592 tap_cfg0.tap_x_en = (uint8_t)val;
5593 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG0,
5594 (uint8_t *)&tap_cfg0, 1);
5595 }
5596
5597 return ret;
5598 }
5599
5600 /**
5601 * @brief Enable X direction in tap recognition.[get]
5602 *
5603 * @param ctx Read / write interface definitions.(ptr)
5604 * @param val Change the values of tap_x_en in reg TAP_CFG0
5605 * @retval Interface status (MANDATORY: return 0 -> no Error).
5606 *
5607 */
lsm6dsr_tap_detection_on_x_get(stmdev_ctx_t * ctx,uint8_t * val)5608 int32_t lsm6dsr_tap_detection_on_x_get(stmdev_ctx_t *ctx,
5609 uint8_t *val)
5610 {
5611 lsm6dsr_tap_cfg0_t tap_cfg0;
5612 int32_t ret;
5613
5614 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG0, (uint8_t *)&tap_cfg0, 1);
5615 *val = tap_cfg0.tap_x_en;
5616
5617 return ret;
5618 }
5619
5620 /**
5621 * @brief X-axis tap recognition threshold.[set]
5622 *
5623 * @param ctx Read / write interface definitions.(ptr)
5624 * @param val Change the values of tap_ths_x in reg TAP_CFG1
5625 * @retval Interface status (MANDATORY: return 0 -> no Error).
5626 *
5627 */
lsm6dsr_tap_threshold_x_set(stmdev_ctx_t * ctx,uint8_t val)5628 int32_t lsm6dsr_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
5629 {
5630 lsm6dsr_tap_cfg1_t tap_cfg1;
5631 int32_t ret;
5632
5633 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
5634
5635 if (ret == 0)
5636 {
5637 tap_cfg1.tap_ths_x = (uint8_t)val;
5638 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG1,
5639 (uint8_t *)&tap_cfg1, 1);
5640 }
5641
5642 return ret;
5643 }
5644
5645 /**
5646 * @brief X-axis tap recognition threshold.[get]
5647 *
5648 * @param ctx Read / write interface definitions.(ptr)
5649 * @param val Change the values of tap_ths_x in reg TAP_CFG1
5650 * @retval Interface status (MANDATORY: return 0 -> no Error).
5651 *
5652 */
lsm6dsr_tap_threshold_x_get(stmdev_ctx_t * ctx,uint8_t * val)5653 int32_t lsm6dsr_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
5654 {
5655 lsm6dsr_tap_cfg1_t tap_cfg1;
5656 int32_t ret;
5657
5658 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
5659 *val = tap_cfg1.tap_ths_x;
5660
5661 return ret;
5662 }
5663
5664 /**
5665 * @brief Selection of axis priority for TAP detection.[set]
5666 *
5667 * @param ctx Read / write interface definitions.(ptr)
5668 * @param val Change the values of tap_priority in reg TAP_CFG1
5669 * @retval Interface status (MANDATORY: return 0 -> no Error).
5670 *
5671 */
lsm6dsr_tap_axis_priority_set(stmdev_ctx_t * ctx,lsm6dsr_tap_priority_t val)5672 int32_t lsm6dsr_tap_axis_priority_set(stmdev_ctx_t *ctx,
5673 lsm6dsr_tap_priority_t val)
5674 {
5675 lsm6dsr_tap_cfg1_t tap_cfg1;
5676 int32_t ret;
5677
5678 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
5679
5680 if (ret == 0)
5681 {
5682 tap_cfg1.tap_priority = (uint8_t)val;
5683 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
5684 }
5685
5686 return ret;
5687 }
5688
5689 /**
5690 * @brief Selection of axis priority for TAP detection[get]
5691 *
5692 * @param ctx Read / write interface definitions.(ptr)
5693 * @param val Get the values of tap_priority in reg TAP_CFG1
5694 * @retval Interface status (MANDATORY: return 0 -> no Error).
5695 *
5696 */
lsm6dsr_tap_axis_priority_get(stmdev_ctx_t * ctx,lsm6dsr_tap_priority_t * val)5697 int32_t lsm6dsr_tap_axis_priority_get(stmdev_ctx_t *ctx,
5698 lsm6dsr_tap_priority_t *val)
5699 {
5700 lsm6dsr_tap_cfg1_t tap_cfg1;
5701 int32_t ret;
5702
5703 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG1, (uint8_t *)&tap_cfg1, 1);
5704
5705 switch (tap_cfg1.tap_priority)
5706 {
5707 case LSM6DSR_XYZ:
5708 *val = LSM6DSR_XYZ;
5709 break;
5710
5711 case LSM6DSR_YXZ:
5712 *val = LSM6DSR_YXZ;
5713 break;
5714
5715 case LSM6DSR_XZY:
5716 *val = LSM6DSR_XZY;
5717 break;
5718
5719 case LSM6DSR_ZYX:
5720 *val = LSM6DSR_ZYX;
5721 break;
5722
5723 case LSM6DSR_YZX:
5724 *val = LSM6DSR_YZX;
5725 break;
5726
5727 case LSM6DSR_ZXY:
5728 *val = LSM6DSR_ZXY;
5729 break;
5730
5731 default:
5732 *val = LSM6DSR_XYZ;
5733 break;
5734 }
5735
5736 return ret;
5737 }
5738
5739 /**
5740 * @brief Y-axis tap recognition threshold.[set]
5741 *
5742 * @param ctx Read / write interface definitions.(ptr)
5743 * @param val Change the values of tap_ths_y in reg TAP_CFG2
5744 * @retval Interface status (MANDATORY: return 0 -> no Error).
5745 *
5746 */
lsm6dsr_tap_threshold_y_set(stmdev_ctx_t * ctx,uint8_t val)5747 int32_t lsm6dsr_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
5748 {
5749 lsm6dsr_tap_cfg2_t tap_cfg2;
5750 int32_t ret;
5751
5752 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
5753
5754 if (ret == 0)
5755 {
5756 tap_cfg2.tap_ths_y = (uint8_t)val;
5757 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_CFG2,
5758 (uint8_t *)&tap_cfg2, 1);
5759 }
5760
5761 return ret;
5762 }
5763
5764 /**
5765 * @brief Y-axis tap recognition threshold.[get]
5766 *
5767 * @param ctx Read / write interface definitions.(ptr)
5768 * @param val Change the values of tap_ths_y in reg TAP_CFG2
5769 * @retval Interface status (MANDATORY: return 0 -> no Error).
5770 *
5771 */
lsm6dsr_tap_threshold_y_get(stmdev_ctx_t * ctx,uint8_t * val)5772 int32_t lsm6dsr_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
5773 {
5774 lsm6dsr_tap_cfg2_t tap_cfg2;
5775 int32_t ret;
5776
5777 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_CFG2, (uint8_t *)&tap_cfg2, 1);
5778 *val = tap_cfg2.tap_ths_y;
5779
5780 return ret;
5781 }
5782
5783 /**
5784 * @brief Z-axis recognition threshold.[set]
5785 *
5786 * @param ctx Read / write interface definitions.(ptr)
5787 * @param val Change the values of tap_ths_z in reg TAP_THS_6D
5788 * @retval Interface status (MANDATORY: return 0 -> no Error).
5789 *
5790 */
lsm6dsr_tap_threshold_z_set(stmdev_ctx_t * ctx,uint8_t val)5791 int32_t lsm6dsr_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
5792 {
5793 lsm6dsr_tap_ths_6d_t tap_ths_6d;
5794 int32_t ret;
5795
5796 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D,
5797 (uint8_t *)&tap_ths_6d, 1);
5798
5799 if (ret == 0)
5800 {
5801 tap_ths_6d.tap_ths_z = (uint8_t)val;
5802 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_THS_6D,
5803 (uint8_t *)&tap_ths_6d, 1);
5804 }
5805
5806 return ret;
5807 }
5808
5809 /**
5810 * @brief Z-axis recognition threshold.[get]
5811 *
5812 * @param ctx Read / write interface definitions.(ptr)
5813 * @param val Change the values of tap_ths_z in reg TAP_THS_6D
5814 * @retval Interface status (MANDATORY: return 0 -> no Error).
5815 *
5816 */
lsm6dsr_tap_threshold_z_get(stmdev_ctx_t * ctx,uint8_t * val)5817 int32_t lsm6dsr_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
5818 {
5819 lsm6dsr_tap_ths_6d_t tap_ths_6d;
5820 int32_t ret;
5821
5822 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D,
5823 (uint8_t *)&tap_ths_6d, 1);
5824 *val = tap_ths_6d.tap_ths_z;
5825
5826 return ret;
5827 }
5828
5829 /**
5830 * @brief Maximum duration is the maximum time of an overthreshold signal
5831 * detection to be recognized as a tap event. The default value of
5832 * these bits is 00b which corresponds to 4*ODR_XL time.
5833 * If the SHOCK[1:0] bits are set to a different value, 1LSB
5834 * corresponds to 8*ODR_XL time.[set]
5835 *
5836 * @param ctx Read / write interface definitions.(ptr)
5837 * @param val Change the values of shock in reg INT_DUR2
5838 * @retval Interface status (MANDATORY: return 0 -> no Error).
5839 *
5840 */
lsm6dsr_tap_shock_set(stmdev_ctx_t * ctx,uint8_t val)5841 int32_t lsm6dsr_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
5842 {
5843 lsm6dsr_int_dur2_t int_dur2;
5844 int32_t ret;
5845
5846 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t *)&int_dur2, 1);
5847
5848 if (ret == 0)
5849 {
5850 int_dur2.shock = (uint8_t)val;
5851 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_DUR2,
5852 (uint8_t *)&int_dur2, 1);
5853 }
5854
5855 return ret;
5856 }
5857
5858 /**
5859 * @brief Maximum duration is the maximum time of an overthreshold signal
5860 * detection to be recognized as a tap event. The default value of
5861 * these bits is 00b which corresponds to 4*ODR_XL time.
5862 * If the SHOCK[1:0] bits are set to a different value, 1LSB
5863 * corresponds to 8*ODR_XL time.[get]
5864 *
5865 * @param ctx Read / write interface definitions.(ptr)
5866 * @param val Change the values of shock in reg INT_DUR2
5867 * @retval Interface status (MANDATORY: return 0 -> no Error).
5868 *
5869 */
lsm6dsr_tap_shock_get(stmdev_ctx_t * ctx,uint8_t * val)5870 int32_t lsm6dsr_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
5871 {
5872 lsm6dsr_int_dur2_t int_dur2;
5873 int32_t ret;
5874
5875 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t *)&int_dur2, 1);
5876 *val = int_dur2.shock;
5877
5878 return ret;
5879 }
5880
5881 /**
5882 * @brief Quiet time is the time after the first detected tap in which
5883 * there must not be any overthreshold event.
5884 * The default value of these bits is 00b which corresponds to
5885 * 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
5886 * value, 1LSB corresponds to 4*ODR_XL time.[set]
5887 *
5888 * @param ctx Read / write interface definitions.(ptr)
5889 * @param val Change the values of quiet in reg INT_DUR2
5890 * @retval Interface status (MANDATORY: return 0 -> no Error).
5891 *
5892 */
lsm6dsr_tap_quiet_set(stmdev_ctx_t * ctx,uint8_t val)5893 int32_t lsm6dsr_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
5894 {
5895 lsm6dsr_int_dur2_t int_dur2;
5896 int32_t ret;
5897
5898 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t *)&int_dur2, 1);
5899
5900 if (ret == 0)
5901 {
5902 int_dur2.quiet = (uint8_t)val;
5903 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_DUR2,
5904 (uint8_t *)&int_dur2, 1);
5905 }
5906
5907 return ret;
5908 }
5909
5910 /**
5911 * @brief Quiet time is the time after the first detected tap in which
5912 * there must not be any overthreshold event.
5913 * The default value of these bits is 00b which corresponds to
5914 * 2*ODR_XL time. If the QUIET[1:0] bits are set to a different
5915 * value, 1LSB corresponds to 4*ODR_XL time.[get]
5916 *
5917 * @param ctx Read / write interface definitions.(ptr)
5918 * @param val Change the values of quiet in reg INT_DUR2
5919 * @retval Interface status (MANDATORY: return 0 -> no Error).
5920 *
5921 */
lsm6dsr_tap_quiet_get(stmdev_ctx_t * ctx,uint8_t * val)5922 int32_t lsm6dsr_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
5923 {
5924 lsm6dsr_int_dur2_t int_dur2;
5925 int32_t ret;
5926
5927 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t *)&int_dur2, 1);
5928 *val = int_dur2.quiet;
5929
5930 return ret;
5931 }
5932
5933 /**
5934 * @brief When double tap recognition is enabled, this register expresses
5935 * the maximum time between two consecutive detected taps to
5936 * determine a double tap event.
5937 * The default value of these bits is 0000b which corresponds to
5938 * 16*ODR_XL time.
5939 * If the DUR[3:0] bits are set to a different value, 1LSB
5940 * corresponds to 32*ODR_XL time.[set]
5941 *
5942 * @param ctx Read / write interface definitions.(ptr)
5943 * @param val Change the values of dur in reg INT_DUR2
5944 * @retval Interface status (MANDATORY: return 0 -> no Error).
5945 *
5946 */
lsm6dsr_tap_dur_set(stmdev_ctx_t * ctx,uint8_t val)5947 int32_t lsm6dsr_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
5948 {
5949 lsm6dsr_int_dur2_t int_dur2;
5950 int32_t ret;
5951
5952 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t *)&int_dur2, 1);
5953
5954 if (ret == 0)
5955 {
5956 int_dur2.dur = (uint8_t)val;
5957 ret = lsm6dsr_write_reg(ctx, LSM6DSR_INT_DUR2,
5958 (uint8_t *)&int_dur2, 1);
5959 }
5960
5961 return ret;
5962 }
5963
5964 /**
5965 * @brief When double tap recognition is enabled, this register expresses the
5966 * maximum time between two consecutive detected taps to determine
5967 * a double tap event. The default value of these bits is 0000b which
5968 * corresponds to 16*ODR_XL time. If the DUR[3:0] bits are set to
5969 * a different value, 1LSB corresponds to 32*ODR_XL time.[get]
5970 *
5971 * @param ctx Read / write interface definitions.(ptr)
5972 * @param val Change the values of dur in reg INT_DUR2
5973 * @retval Interface status (MANDATORY: return 0 -> no Error).
5974 *
5975 */
lsm6dsr_tap_dur_get(stmdev_ctx_t * ctx,uint8_t * val)5976 int32_t lsm6dsr_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
5977 {
5978 lsm6dsr_int_dur2_t int_dur2;
5979 int32_t ret;
5980
5981 ret = lsm6dsr_read_reg(ctx, LSM6DSR_INT_DUR2, (uint8_t *)&int_dur2, 1);
5982 *val = int_dur2.dur;
5983
5984 return ret;
5985 }
5986
5987 /**
5988 * @brief Single/double-tap event enable.[set]
5989 *
5990 * @param ctx Read / write interface definitions.(ptr)
5991 * @param val Change the values of single_double_tap in reg WAKE_UP_THS
5992 * @retval Interface status (MANDATORY: return 0 -> no Error).
5993 *
5994 */
lsm6dsr_tap_mode_set(stmdev_ctx_t * ctx,lsm6dsr_single_double_tap_t val)5995 int32_t lsm6dsr_tap_mode_set(stmdev_ctx_t *ctx,
5996 lsm6dsr_single_double_tap_t val)
5997 {
5998 lsm6dsr_wake_up_ths_t wake_up_ths;
5999 int32_t ret;
6000
6001 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS,
6002 (uint8_t *)&wake_up_ths, 1);
6003
6004 if (ret == 0)
6005 {
6006 wake_up_ths.single_double_tap = (uint8_t)val;
6007 ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_THS,
6008 (uint8_t *)&wake_up_ths, 1);
6009 }
6010
6011 return ret;
6012 }
6013
6014 /**
6015 * @brief Single/double-tap event enable.[get]
6016 *
6017 * @param ctx Read / write interface definitions.(ptr)
6018 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
6019 * @retval Interface status (MANDATORY: return 0 -> no Error).
6020 *
6021 */
lsm6dsr_tap_mode_get(stmdev_ctx_t * ctx,lsm6dsr_single_double_tap_t * val)6022 int32_t lsm6dsr_tap_mode_get(stmdev_ctx_t *ctx,
6023 lsm6dsr_single_double_tap_t *val)
6024 {
6025 lsm6dsr_wake_up_ths_t wake_up_ths;
6026 int32_t ret;
6027
6028 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_THS,
6029 (uint8_t *)&wake_up_ths, 1);
6030
6031 switch (wake_up_ths.single_double_tap)
6032 {
6033 case LSM6DSR_ONLY_SINGLE:
6034 *val = LSM6DSR_ONLY_SINGLE;
6035 break;
6036
6037 case LSM6DSR_BOTH_SINGLE_DOUBLE:
6038 *val = LSM6DSR_BOTH_SINGLE_DOUBLE;
6039 break;
6040
6041 default:
6042 *val = LSM6DSR_ONLY_SINGLE;
6043 break;
6044 }
6045
6046 return ret;
6047 }
6048
6049 /**
6050 * @}
6051 *
6052 */
6053
6054 /**
6055 * @defgroup LSM6DSR_ Six_position_detection(6D/4D)
6056 * @brief This section groups all the functions concerning six
6057 * position detection (6D).
6058 * @{
6059 *
6060 */
6061
6062 /**
6063 * @brief Threshold for 4D/6D function.[set]
6064 *
6065 * @param ctx Read / write interface definitions.(ptr)
6066 * @param val Change the values of sixd_ths in reg TAP_THS_6D
6067 * @retval Interface status (MANDATORY: return 0 -> no Error).
6068 *
6069 */
lsm6dsr_6d_threshold_set(stmdev_ctx_t * ctx,lsm6dsr_sixd_ths_t val)6070 int32_t lsm6dsr_6d_threshold_set(stmdev_ctx_t *ctx,
6071 lsm6dsr_sixd_ths_t val)
6072 {
6073 lsm6dsr_tap_ths_6d_t tap_ths_6d;
6074 int32_t ret;
6075
6076 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D,
6077 (uint8_t *)&tap_ths_6d, 1);
6078
6079 if (ret == 0)
6080 {
6081 tap_ths_6d.sixd_ths = (uint8_t)val;
6082 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_THS_6D,
6083 (uint8_t *)&tap_ths_6d, 1);
6084 }
6085
6086 return ret;
6087 }
6088
6089 /**
6090 * @brief Threshold for 4D/6D function.[get]
6091 *
6092 * @param ctx Read / write interface definitions.(ptr)
6093 * @param val Get the values of sixd_ths in reg TAP_THS_6D
6094 * @retval Interface status (MANDATORY: return 0 -> no Error).
6095 *
6096 */
lsm6dsr_6d_threshold_get(stmdev_ctx_t * ctx,lsm6dsr_sixd_ths_t * val)6097 int32_t lsm6dsr_6d_threshold_get(stmdev_ctx_t *ctx,
6098 lsm6dsr_sixd_ths_t *val)
6099 {
6100 lsm6dsr_tap_ths_6d_t tap_ths_6d;
6101 int32_t ret;
6102
6103 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D,
6104 (uint8_t *)&tap_ths_6d, 1);
6105
6106 switch (tap_ths_6d.sixd_ths)
6107 {
6108 case LSM6DSR_DEG_80:
6109 *val = LSM6DSR_DEG_80;
6110 break;
6111
6112 case LSM6DSR_DEG_70:
6113 *val = LSM6DSR_DEG_70;
6114 break;
6115
6116 case LSM6DSR_DEG_60:
6117 *val = LSM6DSR_DEG_60;
6118 break;
6119
6120 case LSM6DSR_DEG_50:
6121 *val = LSM6DSR_DEG_50;
6122 break;
6123
6124 default:
6125 *val = LSM6DSR_DEG_80;
6126 break;
6127 }
6128
6129 return ret;
6130 }
6131
6132 /**
6133 * @brief 4D orientation detection enable.[set]
6134 *
6135 * @param ctx Read / write interface definitions.(ptr)
6136 * @param val Change the values of d4d_en in reg TAP_THS_6D
6137 * @retval Interface status (MANDATORY: return 0 -> no Error).
6138 *
6139 */
lsm6dsr_4d_mode_set(stmdev_ctx_t * ctx,uint8_t val)6140 int32_t lsm6dsr_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
6141 {
6142 lsm6dsr_tap_ths_6d_t tap_ths_6d;
6143 int32_t ret;
6144
6145 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D,
6146 (uint8_t *)&tap_ths_6d, 1);
6147
6148 if (ret == 0)
6149 {
6150 tap_ths_6d.d4d_en = (uint8_t)val;
6151 ret = lsm6dsr_write_reg(ctx, LSM6DSR_TAP_THS_6D,
6152 (uint8_t *)&tap_ths_6d, 1);
6153 }
6154
6155 return ret;
6156 }
6157
6158 /**
6159 * @brief 4D orientation detection enable.[get]
6160 *
6161 * @param ctx Read / write interface definitions.(ptr)
6162 * @param val Change the values of d4d_en in reg TAP_THS_6D
6163 * @retval Interface status (MANDATORY: return 0 -> no Error).
6164 *
6165 */
lsm6dsr_4d_mode_get(stmdev_ctx_t * ctx,uint8_t * val)6166 int32_t lsm6dsr_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
6167 {
6168 lsm6dsr_tap_ths_6d_t tap_ths_6d;
6169 int32_t ret;
6170
6171 ret = lsm6dsr_read_reg(ctx, LSM6DSR_TAP_THS_6D,
6172 (uint8_t *)&tap_ths_6d, 1);
6173 *val = tap_ths_6d.d4d_en;
6174
6175 return ret;
6176 }
6177
6178 /**
6179 * @}
6180 *
6181 */
6182
6183 /**
6184 * @defgroup LSM6DSR_free_fall
6185 * @brief This section group all the functions concerning the free
6186 * fall detection.
6187 * @{
6188 *
6189 */
6190
6191 /**
6192 * @brief Free fall threshold setting.[set]
6193 *
6194 * @param ctx Read / write interface definitions.(ptr)
6195 * @param val Change the values of ff_ths in reg FREE_FALL
6196 * @retval Interface status (MANDATORY: return 0 -> no Error).
6197 *
6198 */
lsm6dsr_ff_threshold_set(stmdev_ctx_t * ctx,lsm6dsr_ff_ths_t val)6199 int32_t lsm6dsr_ff_threshold_set(stmdev_ctx_t *ctx,
6200 lsm6dsr_ff_ths_t val)
6201 {
6202 lsm6dsr_free_fall_t free_fall;
6203 int32_t ret;
6204
6205 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FREE_FALL, (uint8_t *)&free_fall, 1);
6206
6207 if (ret == 0)
6208 {
6209 free_fall.ff_ths = (uint8_t)val;
6210 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FREE_FALL,
6211 (uint8_t *)&free_fall, 1);
6212 }
6213
6214 return ret;
6215 }
6216
6217 /**
6218 * @brief Free fall threshold setting.[get]
6219 *
6220 * @param ctx Read / write interface definitions.(ptr)
6221 * @param val Get the values of ff_ths in reg FREE_FALL
6222 * @retval Interface status (MANDATORY: return 0 -> no Error).
6223 *
6224 */
lsm6dsr_ff_threshold_get(stmdev_ctx_t * ctx,lsm6dsr_ff_ths_t * val)6225 int32_t lsm6dsr_ff_threshold_get(stmdev_ctx_t *ctx,
6226 lsm6dsr_ff_ths_t *val)
6227 {
6228 lsm6dsr_free_fall_t free_fall;
6229 int32_t ret;
6230
6231 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FREE_FALL, (uint8_t *)&free_fall, 1);
6232
6233 switch (free_fall.ff_ths)
6234 {
6235 case LSM6DSR_FF_TSH_156mg:
6236 *val = LSM6DSR_FF_TSH_156mg;
6237 break;
6238
6239 case LSM6DSR_FF_TSH_219mg:
6240 *val = LSM6DSR_FF_TSH_219mg;
6241 break;
6242
6243 case LSM6DSR_FF_TSH_250mg:
6244 *val = LSM6DSR_FF_TSH_250mg;
6245 break;
6246
6247 case LSM6DSR_FF_TSH_312mg:
6248 *val = LSM6DSR_FF_TSH_312mg;
6249 break;
6250
6251 case LSM6DSR_FF_TSH_344mg:
6252 *val = LSM6DSR_FF_TSH_344mg;
6253 break;
6254
6255 case LSM6DSR_FF_TSH_406mg:
6256 *val = LSM6DSR_FF_TSH_406mg;
6257 break;
6258
6259 case LSM6DSR_FF_TSH_469mg:
6260 *val = LSM6DSR_FF_TSH_469mg;
6261 break;
6262
6263 case LSM6DSR_FF_TSH_500mg:
6264 *val = LSM6DSR_FF_TSH_500mg;
6265 break;
6266
6267 default:
6268 *val = LSM6DSR_FF_TSH_156mg;
6269 break;
6270 }
6271
6272 return ret;
6273 }
6274
6275 /**
6276 * @brief Free-fall duration event(1LSb = 1 / ODR).[set]
6277 *
6278 * @param ctx Read / write interface definitions.(ptr)
6279 * @param val Change the values of ff_dur in reg FREE_FALL
6280 * @retval Interface status (MANDATORY: return 0 -> no Error).
6281 *
6282 */
lsm6dsr_ff_dur_set(stmdev_ctx_t * ctx,uint8_t val)6283 int32_t lsm6dsr_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
6284 {
6285 lsm6dsr_wake_up_dur_t wake_up_dur;
6286 lsm6dsr_free_fall_t free_fall;
6287 int32_t ret;
6288
6289 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
6290 (uint8_t *)&wake_up_dur, 1);
6291
6292 if (ret == 0)
6293 {
6294 wake_up_dur.ff_dur = (val & 0x20U) >> 5;
6295 ret = lsm6dsr_write_reg(ctx, LSM6DSR_WAKE_UP_DUR,
6296 (uint8_t *)&wake_up_dur, 1);
6297 }
6298
6299 if (ret == 0)
6300 {
6301 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FREE_FALL,
6302 (uint8_t *)&free_fall, 1);
6303 }
6304
6305 if (ret == 0)
6306 {
6307 free_fall.ff_dur = val & 0x1FU;
6308 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FREE_FALL,
6309 (uint8_t *)&free_fall, 1);
6310 }
6311
6312 return ret;
6313 }
6314
6315 /**
6316 * @brief Free-fall duration event(1LSb = 1 / ODR).[get]
6317 *
6318 * @param ctx Read / write interface definitions.(ptr)
6319 * @param val Change the values of ff_dur in reg FREE_FALL
6320 * @retval Interface status (MANDATORY: return 0 -> no Error).
6321 *
6322 */
lsm6dsr_ff_dur_get(stmdev_ctx_t * ctx,uint8_t * val)6323 int32_t lsm6dsr_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
6324 {
6325 lsm6dsr_wake_up_dur_t wake_up_dur;
6326 lsm6dsr_free_fall_t free_fall;
6327 int32_t ret;
6328
6329 ret = lsm6dsr_read_reg(ctx, LSM6DSR_WAKE_UP_DUR,
6330 (uint8_t *)&wake_up_dur, 1);
6331
6332 if (ret == 0)
6333 {
6334 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FREE_FALL,
6335 (uint8_t *)&free_fall, 1);
6336 }
6337
6338 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
6339
6340 return ret;
6341 }
6342
6343 /**
6344 * @}
6345 *
6346 */
6347
6348 /**
6349 * @defgroup LSM6DSR_fifo
6350 * @brief This section group all the functions concerning
6351 * the fifo usage
6352 * @{
6353 *
6354 */
6355
6356 /**
6357 * @brief FIFO watermark level selection.[set]
6358 *
6359 * @param ctx Read / write interface definitions.(ptr)
6360 * @param val Change the values of wtm in reg FIFO_CTRL1
6361 * @retval Interface status (MANDATORY: return 0 -> no Error).
6362 *
6363 */
lsm6dsr_fifo_watermark_set(stmdev_ctx_t * ctx,uint16_t val)6364 int32_t lsm6dsr_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
6365 {
6366 lsm6dsr_fifo_ctrl1_t fifo_ctrl1;
6367 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6368 int32_t ret;
6369
6370 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
6371 (uint8_t *)&fifo_ctrl2, 1);
6372
6373 if (ret == 0)
6374 {
6375 fifo_ctrl1.wtm = (uint8_t)(0x00FFU & val);
6376 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL1,
6377 (uint8_t *)&fifo_ctrl1, 1);
6378 }
6379
6380 if (ret == 0)
6381 {
6382 fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8);
6383 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL2,
6384 (uint8_t *)&fifo_ctrl2, 1);
6385 }
6386
6387 return ret;
6388 }
6389
6390 /**
6391 * @brief FIFO watermark level selection.[get]
6392 *
6393 * @param ctx Read / write interface definitions.(ptr)
6394 * @param val Change the values of wtm in reg FIFO_CTRL1
6395 * @retval Interface status (MANDATORY: return 0 -> no Error).
6396 *
6397 */
lsm6dsr_fifo_watermark_get(stmdev_ctx_t * ctx,uint16_t * val)6398 int32_t lsm6dsr_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
6399 {
6400 lsm6dsr_fifo_ctrl1_t fifo_ctrl1;
6401 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6402 int32_t ret;
6403
6404 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
6405 (uint8_t *)&fifo_ctrl2, 1);
6406
6407 if (ret == 0)
6408 {
6409 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL1,
6410 (uint8_t *)&fifo_ctrl1, 1);
6411 }
6412
6413 *val = fifo_ctrl2.wtm;
6414 *val = *val << 8;
6415 *val += fifo_ctrl1.wtm;
6416
6417 return ret;
6418 }
6419
6420 /**
6421 * @brief FIFO compression feature initialization request.[set].
6422 *
6423 * @param ctx Read / write interface definitions.(ptr)
6424 * @param val Change the values of FIFO_COMPR_INIT in reg EMB_FUNC_INIT_B
6425 * @retval Interface status (MANDATORY: return 0 -> no Error).
6426 *
6427 */
lsm6dsr_compression_algo_init_set(stmdev_ctx_t * ctx,uint8_t val)6428 int32_t lsm6dsr_compression_algo_init_set(stmdev_ctx_t *ctx,
6429 uint8_t val)
6430 {
6431 lsm6dsr_emb_func_init_b_t emb_func_init_b;
6432 int32_t ret;
6433
6434 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
6435
6436 if (ret == 0)
6437 {
6438 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_INIT_B,
6439 (uint8_t *)&emb_func_init_b, 1);
6440 }
6441
6442 if (ret == 0)
6443 {
6444 emb_func_init_b.fifo_compr_init = (uint8_t)val;
6445 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_INIT_B,
6446 (uint8_t *)&emb_func_init_b, 1);
6447 }
6448
6449 if (ret == 0)
6450 {
6451 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
6452 }
6453
6454 return ret;
6455 }
6456
6457 /**
6458 * @brief FIFO compression feature initialization request.[get].
6459 *
6460 * @param ctx Read / write interface definitions.(ptr)
6461 * @param val change the values of FIFO_COMPR_INIT in
6462 * reg EMB_FUNC_INIT_B
6463 * @retval Interface status (MANDATORY: return 0 -> no Error).
6464 *
6465 */
lsm6dsr_compression_algo_init_get(stmdev_ctx_t * ctx,uint8_t * val)6466 int32_t lsm6dsr_compression_algo_init_get(stmdev_ctx_t *ctx,
6467 uint8_t *val)
6468 {
6469 lsm6dsr_emb_func_init_b_t emb_func_init_b;
6470 int32_t ret;
6471
6472 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
6473
6474 if (ret == 0)
6475 {
6476 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_INIT_B,
6477 (uint8_t *)&emb_func_init_b, 1);
6478 }
6479
6480 if (ret == 0)
6481 {
6482 *val = emb_func_init_b.fifo_compr_init;
6483 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
6484 }
6485
6486 return ret;
6487 }
6488
6489 /**
6490 * @brief Enable and configure compression algo.[set]
6491 *
6492 * @param ctx Read / write interface definitions.(ptr)
6493 * @param val Change the values of uncoptr_rate in reg FIFO_CTRL2
6494 * @retval Interface status (MANDATORY: return 0 -> no Error).
6495 *
6496 */
lsm6dsr_compression_algo_set(stmdev_ctx_t * ctx,lsm6dsr_uncoptr_rate_t val)6497 int32_t lsm6dsr_compression_algo_set(stmdev_ctx_t *ctx,
6498 lsm6dsr_uncoptr_rate_t val)
6499 {
6500 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6501 lsm6dsr_emb_func_en_b_t emb_func_en_b;
6502 int32_t ret;
6503
6504 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
6505
6506 if (ret == 0)
6507 {
6508 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
6509 (uint8_t *)&emb_func_en_b, 1);
6510 }
6511
6512 if (ret == 0)
6513 {
6514 emb_func_en_b.fifo_compr_en = ((uint8_t)val & 0x04U) >> 2;
6515 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
6516 (uint8_t *)&emb_func_en_b, 1);
6517 }
6518
6519 if (ret == 0)
6520 {
6521 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
6522 }
6523
6524 if (ret == 0)
6525 {
6526 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
6527 (uint8_t *)&fifo_ctrl2, 1);
6528 }
6529
6530 if (ret == 0)
6531 {
6532 fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
6533 fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
6534 }
6535
6536 if (ret == 0)
6537 {
6538 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL2,
6539 (uint8_t *)&fifo_ctrl2, 1);
6540 }
6541
6542 return ret;
6543 }
6544
6545 /**
6546 * @brief Enable and configure compression algo.[get]
6547 *
6548 * @param ctx Read / write interface definitions.(ptr)
6549 * @param val Get the values of uncoptr_rate in reg FIFO_CTRL2
6550 * @retval Interface status (MANDATORY: return 0 -> no Error).
6551 *
6552 */
lsm6dsr_compression_algo_get(stmdev_ctx_t * ctx,lsm6dsr_uncoptr_rate_t * val)6553 int32_t lsm6dsr_compression_algo_get(stmdev_ctx_t *ctx,
6554 lsm6dsr_uncoptr_rate_t *val)
6555 {
6556 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6557 int32_t ret;
6558
6559 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
6560 (uint8_t *)&fifo_ctrl2, 1);
6561
6562 switch ((fifo_ctrl2.fifo_compr_rt_en << 2) +
6563 fifo_ctrl2.uncoptr_rate)
6564 {
6565 case LSM6DSR_CMP_DISABLE:
6566 *val = LSM6DSR_CMP_DISABLE;
6567 break;
6568
6569 case LSM6DSR_CMP_ALWAYS:
6570 *val = LSM6DSR_CMP_ALWAYS;
6571 break;
6572
6573 case LSM6DSR_CMP_8_TO_1:
6574 *val = LSM6DSR_CMP_8_TO_1;
6575 break;
6576
6577 case LSM6DSR_CMP_16_TO_1:
6578 *val = LSM6DSR_CMP_16_TO_1;
6579 break;
6580
6581 case LSM6DSR_CMP_32_TO_1:
6582 *val = LSM6DSR_CMP_32_TO_1;
6583 break;
6584
6585 default:
6586 *val = LSM6DSR_CMP_DISABLE;
6587 break;
6588 }
6589
6590 return ret;
6591 }
6592
6593 /**
6594 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
6595 *
6596 * @param ctx Read / write interface definitions.(ptr)
6597 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
6598 * @retval Interface status (MANDATORY: return 0 -> no Error).
6599 *
6600 */
lsm6dsr_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t * ctx,uint8_t val)6601 int32_t lsm6dsr_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
6602 uint8_t val)
6603 {
6604 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6605 int32_t ret;
6606
6607 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
6608 (uint8_t *)&fifo_ctrl2, 1);
6609
6610 if (ret == 0)
6611 {
6612 fifo_ctrl2.odrchg_en = (uint8_t)val;
6613 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL2,
6614 (uint8_t *)&fifo_ctrl2, 1);
6615 }
6616
6617 return ret;
6618 }
6619
6620 /**
6621 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
6622 *
6623 * @param ctx Read / write interface definitions.(ptr)
6624 * @param val Change the values of odrchg_en in reg FIFO_CTRL2
6625 * @retval Interface status (MANDATORY: return 0 -> no Error).
6626 *
6627 */
lsm6dsr_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t * ctx,uint8_t * val)6628 int32_t lsm6dsr_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
6629 uint8_t *val)
6630 {
6631 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6632 int32_t ret;
6633
6634 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
6635 (uint8_t *)&fifo_ctrl2, 1);
6636 *val = fifo_ctrl2.odrchg_en;
6637
6638 return ret;
6639 }
6640
6641 /**
6642 * @brief Enables/Disables compression algorithm runtime[set]
6643 *
6644 * @param ctx Read / write interface definitions.(ptr)
6645 * @param val Change the values of fifo_compr_rt_en in reg FIFO_CTRL2
6646 * @retval Interface status (MANDATORY: return 0 -> no Error).
6647 *
6648 */
lsm6dsr_compression_algo_real_time_set(stmdev_ctx_t * ctx,uint8_t val)6649 int32_t lsm6dsr_compression_algo_real_time_set(stmdev_ctx_t *ctx,
6650 uint8_t val)
6651 {
6652 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6653 int32_t ret;
6654
6655 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
6656 (uint8_t *)&fifo_ctrl2, 1);
6657
6658 if (ret == 0)
6659 {
6660 fifo_ctrl2.fifo_compr_rt_en = (uint8_t)val;
6661 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL2,
6662 (uint8_t *)&fifo_ctrl2, 1);
6663 }
6664
6665 return ret;
6666 }
6667
6668 /**
6669 * @brief Enables/Disables compression algorithm runtime.[get]
6670 *
6671 * @param ctx Read / write interface definitions.(ptr)
6672 * @param val Change the values of fifo_compr_rt_en in reg FIFO_CTRL2
6673 * @retval Interface status (MANDATORY: return 0 -> no Error).
6674 *
6675 */
lsm6dsr_compression_algo_real_time_get(stmdev_ctx_t * ctx,uint8_t * val)6676 int32_t lsm6dsr_compression_algo_real_time_get(stmdev_ctx_t *ctx,
6677 uint8_t *val)
6678 {
6679 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6680 int32_t ret;
6681
6682 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
6683 (uint8_t *)&fifo_ctrl2, 1);
6684 *val = fifo_ctrl2.fifo_compr_rt_en;
6685
6686 return ret;
6687 }
6688
6689 /**
6690 * @brief Sensing chain FIFO stop values memorization at threshold
6691 * level.[set]
6692 *
6693 * @param ctx Read / write interface definitions.(ptr)
6694 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
6695 * @retval Interface status (MANDATORY: return 0 -> no Error).
6696 *
6697 */
lsm6dsr_fifo_stop_on_wtm_set(stmdev_ctx_t * ctx,uint8_t val)6698 int32_t lsm6dsr_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
6699 {
6700 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6701 int32_t ret;
6702
6703 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
6704 (uint8_t *)&fifo_ctrl2, 1);
6705
6706 if (ret == 0)
6707 {
6708 fifo_ctrl2.stop_on_wtm = (uint8_t)val;
6709 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL2,
6710 (uint8_t *)&fifo_ctrl2, 1);
6711 }
6712
6713 return ret;
6714 }
6715
6716 /**
6717 * @brief Sensing chain FIFO stop values memorization at threshold
6718 * level.[get]
6719 *
6720 * @param ctx Read / write interface definitions.(ptr)
6721 * @param val Change the values of stop_on_wtm in reg FIFO_CTRL2
6722 * @retval Interface status (MANDATORY: return 0 -> no Error).
6723 *
6724 */
lsm6dsr_fifo_stop_on_wtm_get(stmdev_ctx_t * ctx,uint8_t * val)6725 int32_t lsm6dsr_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
6726 {
6727 lsm6dsr_fifo_ctrl2_t fifo_ctrl2;
6728 int32_t ret;
6729
6730 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL2,
6731 (uint8_t *)&fifo_ctrl2, 1);
6732 *val = fifo_ctrl2.stop_on_wtm;
6733
6734 return ret;
6735 }
6736
6737 /**
6738 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6739 * for accelerometer data.[set]
6740 *
6741 * @param ctx Read / write interface definitions.(ptr)
6742 * @param val Change the values of bdr_xl in reg FIFO_CTRL3
6743 * @retval Interface status (MANDATORY: return 0 -> no Error).
6744 *
6745 */
lsm6dsr_fifo_xl_batch_set(stmdev_ctx_t * ctx,lsm6dsr_bdr_xl_t val)6746 int32_t lsm6dsr_fifo_xl_batch_set(stmdev_ctx_t *ctx,
6747 lsm6dsr_bdr_xl_t val)
6748 {
6749 lsm6dsr_fifo_ctrl3_t fifo_ctrl3;
6750 int32_t ret;
6751
6752 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL3,
6753 (uint8_t *)&fifo_ctrl3, 1);
6754
6755 if (ret == 0)
6756 {
6757 fifo_ctrl3.bdr_xl = (uint8_t)val;
6758 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL3,
6759 (uint8_t *)&fifo_ctrl3, 1);
6760 }
6761
6762 return ret;
6763 }
6764
6765 /**
6766 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6767 * for accelerometer data.[get]
6768 *
6769 * @param ctx Read / write interface definitions.(ptr)
6770 * @param val Get the values of bdr_xl in reg FIFO_CTRL3
6771 * @retval Interface status (MANDATORY: return 0 -> no Error).
6772 *
6773 */
lsm6dsr_fifo_xl_batch_get(stmdev_ctx_t * ctx,lsm6dsr_bdr_xl_t * val)6774 int32_t lsm6dsr_fifo_xl_batch_get(stmdev_ctx_t *ctx,
6775 lsm6dsr_bdr_xl_t *val)
6776 {
6777 lsm6dsr_fifo_ctrl3_t fifo_ctrl3;
6778 int32_t ret;
6779
6780 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL3,
6781 (uint8_t *)&fifo_ctrl3, 1);
6782
6783 switch (fifo_ctrl3.bdr_xl)
6784 {
6785 case LSM6DSR_XL_NOT_BATCHED:
6786 *val = LSM6DSR_XL_NOT_BATCHED;
6787 break;
6788
6789 case LSM6DSR_XL_BATCHED_AT_12Hz5:
6790 *val = LSM6DSR_XL_BATCHED_AT_12Hz5;
6791 break;
6792
6793 case LSM6DSR_XL_BATCHED_AT_26Hz:
6794 *val = LSM6DSR_XL_BATCHED_AT_26Hz;
6795 break;
6796
6797 case LSM6DSR_XL_BATCHED_AT_52Hz:
6798 *val = LSM6DSR_XL_BATCHED_AT_52Hz;
6799 break;
6800
6801 case LSM6DSR_XL_BATCHED_AT_104Hz:
6802 *val = LSM6DSR_XL_BATCHED_AT_104Hz;
6803 break;
6804
6805 case LSM6DSR_XL_BATCHED_AT_208Hz:
6806 *val = LSM6DSR_XL_BATCHED_AT_208Hz;
6807 break;
6808
6809 case LSM6DSR_XL_BATCHED_AT_417Hz:
6810 *val = LSM6DSR_XL_BATCHED_AT_417Hz;
6811 break;
6812
6813 case LSM6DSR_XL_BATCHED_AT_833Hz:
6814 *val = LSM6DSR_XL_BATCHED_AT_833Hz;
6815 break;
6816
6817 case LSM6DSR_XL_BATCHED_AT_1667Hz:
6818 *val = LSM6DSR_XL_BATCHED_AT_1667Hz;
6819 break;
6820
6821 case LSM6DSR_XL_BATCHED_AT_3333Hz:
6822 *val = LSM6DSR_XL_BATCHED_AT_3333Hz;
6823 break;
6824
6825 case LSM6DSR_XL_BATCHED_AT_6667Hz:
6826 *val = LSM6DSR_XL_BATCHED_AT_6667Hz;
6827 break;
6828
6829 case LSM6DSR_XL_BATCHED_AT_6Hz5:
6830 *val = LSM6DSR_XL_BATCHED_AT_6Hz5;
6831 break;
6832
6833 default:
6834 *val = LSM6DSR_XL_NOT_BATCHED;
6835 break;
6836 }
6837
6838 return ret;
6839 }
6840
6841 /**
6842 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6843 * for gyroscope data.[set]
6844 *
6845 * @param ctx Read / write interface definitions.(ptr)
6846 * @param val Change the values of bdr_gy in reg FIFO_CTRL3
6847 * @retval Interface status (MANDATORY: return 0 -> no Error).
6848 *
6849 */
lsm6dsr_fifo_gy_batch_set(stmdev_ctx_t * ctx,lsm6dsr_bdr_gy_t val)6850 int32_t lsm6dsr_fifo_gy_batch_set(stmdev_ctx_t *ctx,
6851 lsm6dsr_bdr_gy_t val)
6852 {
6853 lsm6dsr_fifo_ctrl3_t fifo_ctrl3;
6854 int32_t ret;
6855
6856 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL3,
6857 (uint8_t *)&fifo_ctrl3, 1);
6858
6859 if (ret == 0)
6860 {
6861 fifo_ctrl3.bdr_gy = (uint8_t)val;
6862 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL3,
6863 (uint8_t *)&fifo_ctrl3, 1);
6864 }
6865
6866 return ret;
6867 }
6868
6869 /**
6870 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6871 * for gyroscope data.[get]
6872 *
6873 * @param ctx Read / write interface definitions.(ptr)
6874 * @param val Get the values of bdr_gy in reg FIFO_CTRL3
6875 * @retval Interface status (MANDATORY: return 0 -> no Error).
6876 *
6877 */
lsm6dsr_fifo_gy_batch_get(stmdev_ctx_t * ctx,lsm6dsr_bdr_gy_t * val)6878 int32_t lsm6dsr_fifo_gy_batch_get(stmdev_ctx_t *ctx,
6879 lsm6dsr_bdr_gy_t *val)
6880 {
6881 lsm6dsr_fifo_ctrl3_t fifo_ctrl3;
6882 int32_t ret;
6883
6884 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL3,
6885 (uint8_t *)&fifo_ctrl3, 1);
6886
6887 switch (fifo_ctrl3.bdr_gy)
6888 {
6889 case LSM6DSR_GY_NOT_BATCHED:
6890 *val = LSM6DSR_GY_NOT_BATCHED;
6891 break;
6892
6893 case LSM6DSR_GY_BATCHED_AT_12Hz5:
6894 *val = LSM6DSR_GY_BATCHED_AT_12Hz5;
6895 break;
6896
6897 case LSM6DSR_GY_BATCHED_AT_26Hz:
6898 *val = LSM6DSR_GY_BATCHED_AT_26Hz;
6899 break;
6900
6901 case LSM6DSR_GY_BATCHED_AT_52Hz:
6902 *val = LSM6DSR_GY_BATCHED_AT_52Hz;
6903 break;
6904
6905 case LSM6DSR_GY_BATCHED_AT_104Hz:
6906 *val = LSM6DSR_GY_BATCHED_AT_104Hz;
6907 break;
6908
6909 case LSM6DSR_GY_BATCHED_AT_208Hz:
6910 *val = LSM6DSR_GY_BATCHED_AT_208Hz;
6911 break;
6912
6913 case LSM6DSR_GY_BATCHED_AT_417Hz:
6914 *val = LSM6DSR_GY_BATCHED_AT_417Hz;
6915 break;
6916
6917 case LSM6DSR_GY_BATCHED_AT_833Hz:
6918 *val = LSM6DSR_GY_BATCHED_AT_833Hz;
6919 break;
6920
6921 case LSM6DSR_GY_BATCHED_AT_1667Hz:
6922 *val = LSM6DSR_GY_BATCHED_AT_1667Hz;
6923 break;
6924
6925 case LSM6DSR_GY_BATCHED_AT_3333Hz:
6926 *val = LSM6DSR_GY_BATCHED_AT_3333Hz;
6927 break;
6928
6929 case LSM6DSR_GY_BATCHED_AT_6667Hz:
6930 *val = LSM6DSR_GY_BATCHED_AT_6667Hz;
6931 break;
6932
6933 case LSM6DSR_GY_BATCHED_6Hz5:
6934 *val = LSM6DSR_GY_BATCHED_6Hz5;
6935 break;
6936
6937 default:
6938 *val = LSM6DSR_GY_NOT_BATCHED;
6939 break;
6940 }
6941
6942 return ret;
6943 }
6944
6945 /**
6946 * @brief FIFO mode selection.[set]
6947 *
6948 * @param ctx Read / write interface definitions.(ptr)
6949 * @param val Change the values of fifo_mode in reg FIFO_CTRL4
6950 * @retval Interface status (MANDATORY: return 0 -> no Error).
6951 *
6952 */
lsm6dsr_fifo_mode_set(stmdev_ctx_t * ctx,lsm6dsr_fifo_mode_t val)6953 int32_t lsm6dsr_fifo_mode_set(stmdev_ctx_t *ctx,
6954 lsm6dsr_fifo_mode_t val)
6955 {
6956 lsm6dsr_fifo_ctrl4_t fifo_ctrl4;
6957 int32_t ret;
6958
6959 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4,
6960 (uint8_t *)&fifo_ctrl4, 1);
6961
6962 if (ret == 0)
6963 {
6964 fifo_ctrl4.fifo_mode = (uint8_t)val;
6965 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL4,
6966 (uint8_t *)&fifo_ctrl4, 1);
6967 }
6968
6969 return ret;
6970 }
6971
6972 /**
6973 * @brief FIFO mode selection.[get]
6974 *
6975 * @param ctx Read / write interface definitions.(ptr)
6976 * @param val Get the values of fifo_mode in reg FIFO_CTRL4
6977 * @retval Interface status (MANDATORY: return 0 -> no Error).
6978 *
6979 */
lsm6dsr_fifo_mode_get(stmdev_ctx_t * ctx,lsm6dsr_fifo_mode_t * val)6980 int32_t lsm6dsr_fifo_mode_get(stmdev_ctx_t *ctx,
6981 lsm6dsr_fifo_mode_t *val)
6982 {
6983 lsm6dsr_fifo_ctrl4_t fifo_ctrl4;
6984 int32_t ret;
6985
6986 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4,
6987 (uint8_t *)&fifo_ctrl4, 1);
6988
6989 switch (fifo_ctrl4.fifo_mode)
6990 {
6991 case LSM6DSR_BYPASS_MODE:
6992 *val = LSM6DSR_BYPASS_MODE;
6993 break;
6994
6995 case LSM6DSR_FIFO_MODE:
6996 *val = LSM6DSR_FIFO_MODE;
6997 break;
6998
6999 case LSM6DSR_STREAM_TO_FIFO_MODE:
7000 *val = LSM6DSR_STREAM_TO_FIFO_MODE;
7001 break;
7002
7003 case LSM6DSR_BYPASS_TO_STREAM_MODE:
7004 *val = LSM6DSR_BYPASS_TO_STREAM_MODE;
7005 break;
7006
7007 case LSM6DSR_STREAM_MODE:
7008 *val = LSM6DSR_STREAM_MODE;
7009 break;
7010
7011 case LSM6DSR_BYPASS_TO_FIFO_MODE:
7012 *val = LSM6DSR_BYPASS_TO_FIFO_MODE;
7013 break;
7014
7015 default:
7016 *val = LSM6DSR_BYPASS_MODE;
7017 break;
7018 }
7019
7020 return ret;
7021 }
7022
7023 /**
7024 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7025 * for temperature data.[set]
7026 *
7027 * @param ctx Read / write interface definitions.(ptr)
7028 * @param val Change the values of odr_t_batch in reg FIFO_CTRL4
7029 * @retval Interface status (MANDATORY: return 0 -> no Error).
7030 *
7031 */
lsm6dsr_fifo_temp_batch_set(stmdev_ctx_t * ctx,lsm6dsr_odr_t_batch_t val)7032 int32_t lsm6dsr_fifo_temp_batch_set(stmdev_ctx_t *ctx,
7033 lsm6dsr_odr_t_batch_t val)
7034 {
7035 lsm6dsr_fifo_ctrl4_t fifo_ctrl4;
7036 int32_t ret;
7037
7038 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4,
7039 (uint8_t *)&fifo_ctrl4, 1);
7040
7041 if (ret == 0)
7042 {
7043 fifo_ctrl4.odr_t_batch = (uint8_t)val;
7044 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL4,
7045 (uint8_t *)&fifo_ctrl4, 1);
7046 }
7047
7048 return ret;
7049 }
7050
7051 /**
7052 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7053 * for temperature data.[get]
7054 *
7055 * @param ctx Read / write interface definitions.(ptr)
7056 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4
7057 * @retval Interface status (MANDATORY: return 0 -> no Error).
7058 *
7059 */
lsm6dsr_fifo_temp_batch_get(stmdev_ctx_t * ctx,lsm6dsr_odr_t_batch_t * val)7060 int32_t lsm6dsr_fifo_temp_batch_get(stmdev_ctx_t *ctx,
7061 lsm6dsr_odr_t_batch_t *val)
7062 {
7063 lsm6dsr_fifo_ctrl4_t fifo_ctrl4;
7064 int32_t ret;
7065
7066 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4,
7067 (uint8_t *)&fifo_ctrl4, 1);
7068
7069 switch (fifo_ctrl4.odr_t_batch)
7070 {
7071 case LSM6DSR_TEMP_NOT_BATCHED:
7072 *val = LSM6DSR_TEMP_NOT_BATCHED;
7073 break;
7074
7075 case LSM6DSR_TEMP_BATCHED_AT_52Hz:
7076 *val = LSM6DSR_TEMP_BATCHED_AT_52Hz;
7077 break;
7078
7079 case LSM6DSR_TEMP_BATCHED_AT_12Hz5:
7080 *val = LSM6DSR_TEMP_BATCHED_AT_12Hz5;
7081 break;
7082
7083 case LSM6DSR_TEMP_BATCHED_AT_1Hz6:
7084 *val = LSM6DSR_TEMP_BATCHED_AT_1Hz6;
7085 break;
7086
7087 default:
7088 *val = LSM6DSR_TEMP_NOT_BATCHED;
7089 break;
7090 }
7091
7092 return ret;
7093 }
7094
7095 /**
7096 * @brief Selects decimation for timestamp batching in FIFO.
7097 * Writing rate will be the maximum rate between XL and
7098 * GYRO BDR divided by decimation decoder.[set]
7099 *
7100 * @param ctx Read / write interface definitions.(ptr)
7101 * @param val Change the values of odr_ts_batch in reg FIFO_CTRL4
7102 * @retval Interface status (MANDATORY: return 0 -> no Error).
7103 *
7104 */
lsm6dsr_fifo_timestamp_decimation_set(stmdev_ctx_t * ctx,lsm6dsr_odr_ts_batch_t val)7105 int32_t lsm6dsr_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
7106 lsm6dsr_odr_ts_batch_t val)
7107 {
7108 lsm6dsr_fifo_ctrl4_t fifo_ctrl4;
7109 int32_t ret;
7110
7111 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4,
7112 (uint8_t *)&fifo_ctrl4, 1);
7113
7114 if (ret == 0)
7115 {
7116 fifo_ctrl4.odr_ts_batch = (uint8_t)val;
7117 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FIFO_CTRL4,
7118 (uint8_t *)&fifo_ctrl4, 1);
7119 }
7120
7121 return ret;
7122 }
7123
7124 /**
7125 * @brief Selects decimation for timestamp batching in FIFO.
7126 * Writing rate will be the maximum rate between XL and
7127 * GYRO BDR divided by decimation decoder.[get]
7128 *
7129 * @param ctx Read / write interface definitions.(ptr)
7130 * @param val Get the values of odr_ts_batch in reg
7131 * FIFO_CTRL4
7132 * @retval Interface status (MANDATORY: return 0 -> no Error).
7133 *
7134 */
lsm6dsr_fifo_timestamp_decimation_get(stmdev_ctx_t * ctx,lsm6dsr_odr_ts_batch_t * val)7135 int32_t lsm6dsr_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
7136 lsm6dsr_odr_ts_batch_t *val)
7137 {
7138 lsm6dsr_fifo_ctrl4_t fifo_ctrl4;
7139 int32_t ret;
7140
7141 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_CTRL4,
7142 (uint8_t *)&fifo_ctrl4, 1);
7143
7144 switch (fifo_ctrl4.odr_ts_batch)
7145 {
7146 case LSM6DSR_NO_DECIMATION:
7147 *val = LSM6DSR_NO_DECIMATION;
7148 break;
7149
7150 case LSM6DSR_DEC_1:
7151 *val = LSM6DSR_DEC_1;
7152 break;
7153
7154 case LSM6DSR_DEC_8:
7155 *val = LSM6DSR_DEC_8;
7156 break;
7157
7158 case LSM6DSR_DEC_32:
7159 *val = LSM6DSR_DEC_32;
7160 break;
7161
7162 default:
7163 *val = LSM6DSR_NO_DECIMATION;
7164 break;
7165 }
7166
7167 return ret;
7168 }
7169
7170 /**
7171 * @brief Selects the trigger for the internal counter of batching events
7172 * between XL and gyro.[set]
7173 *
7174 * @param ctx Read / write interface definitions.(ptr)
7175 * @param val Change the values of trig_counter_bdr in
7176 * reg COUNTER_BDR_REG1
7177 * @retval Interface status (MANDATORY: return 0 -> no Error).
7178 *
7179 */
lsm6dsr_fifo_cnt_event_batch_set(stmdev_ctx_t * ctx,lsm6dsr_trig_counter_bdr_t val)7180 int32_t lsm6dsr_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
7181 lsm6dsr_trig_counter_bdr_t val)
7182 {
7183 lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1;
7184 int32_t ret;
7185
7186 ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
7187 (uint8_t *)&counter_bdr_reg1, 1);
7188
7189 if (ret == 0)
7190 {
7191 counter_bdr_reg1.trig_counter_bdr = (uint8_t)val;
7192 ret = lsm6dsr_write_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
7193 (uint8_t *)&counter_bdr_reg1, 1);
7194 }
7195
7196 return ret;
7197 }
7198
7199 /**
7200 * @brief Selects the trigger for the internal counter of batching events
7201 * between XL and gyro.[get]
7202 *
7203 * @param ctx Read / write interface definitions.(ptr)
7204 * @param val Get the values of trig_counter_bdr
7205 * in reg COUNTER_BDR_REG1
7206 * @retval Interface status (MANDATORY: return 0 -> no Error).
7207 *
7208 */
lsm6dsr_fifo_cnt_event_batch_get(stmdev_ctx_t * ctx,lsm6dsr_trig_counter_bdr_t * val)7209 int32_t lsm6dsr_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
7210 lsm6dsr_trig_counter_bdr_t *val)
7211 {
7212 lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1;
7213 int32_t ret;
7214
7215 ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
7216 (uint8_t *)&counter_bdr_reg1, 1);
7217
7218 switch (counter_bdr_reg1.trig_counter_bdr)
7219 {
7220 case LSM6DSR_XL_BATCH_EVENT:
7221 *val = LSM6DSR_XL_BATCH_EVENT;
7222 break;
7223
7224 case LSM6DSR_GYRO_BATCH_EVENT:
7225 *val = LSM6DSR_GYRO_BATCH_EVENT;
7226 break;
7227
7228 default:
7229 *val = LSM6DSR_XL_BATCH_EVENT;
7230 break;
7231 }
7232
7233 return ret;
7234 }
7235
7236 /**
7237 * @brief Resets the internal counter of batching events for a single sensor.
7238 * This bit is automatically reset to zero if it was set to ‘1’.[set]
7239 *
7240 * @param ctx Read / write interface definitions.(ptr)
7241 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
7242 * @retval Interface status (MANDATORY: return 0 -> no Error).
7243 *
7244 */
lsm6dsr_rst_batch_counter_set(stmdev_ctx_t * ctx,uint8_t val)7245 int32_t lsm6dsr_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
7246 {
7247 lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1;
7248 int32_t ret;
7249
7250 ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
7251 (uint8_t *)&counter_bdr_reg1, 1);
7252
7253 if (ret == 0)
7254 {
7255 counter_bdr_reg1.rst_counter_bdr = (uint8_t)val;
7256 ret = lsm6dsr_write_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
7257 (uint8_t *)&counter_bdr_reg1, 1);
7258 }
7259
7260 return ret;
7261 }
7262
7263 /**
7264 * @brief Resets the internal counter of batching events for a single sensor.
7265 * This bit is automatically reset to zero if it was set to ‘1’.[get]
7266 *
7267 * @param ctx Read / write interface definitions.(ptr)
7268 * @param val Change the values of rst_counter_bdr in reg COUNTER_BDR_REG1
7269 * @retval Interface status (MANDATORY: return 0 -> no Error).
7270 *
7271 */
lsm6dsr_rst_batch_counter_get(stmdev_ctx_t * ctx,uint8_t * val)7272 int32_t lsm6dsr_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
7273 {
7274 lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1;
7275 int32_t ret;
7276
7277 ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
7278 (uint8_t *)&counter_bdr_reg1, 1);
7279 *val = counter_bdr_reg1.rst_counter_bdr;
7280
7281 return ret;
7282 }
7283
7284 /**
7285 * @brief Batch data rate counter.[set]
7286 *
7287 * @param ctx Read / write interface definitions.(ptr)
7288 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
7289 * and COUNTER_BDR_REG1.
7290 * @retval Interface status (MANDATORY: return 0 -> no Error).
7291 *
7292 */
lsm6dsr_batch_counter_threshold_set(stmdev_ctx_t * ctx,uint16_t val)7293 int32_t lsm6dsr_batch_counter_threshold_set(stmdev_ctx_t *ctx,
7294 uint16_t val)
7295 {
7296 lsm6dsr_counter_bdr_reg2_t counter_bdr_reg1;
7297 lsm6dsr_counter_bdr_reg2_t counter_bdr_reg2;
7298 int32_t ret;
7299
7300 ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
7301 (uint8_t *)&counter_bdr_reg1, 1);
7302
7303 if (ret == 0)
7304 {
7305 counter_bdr_reg1.cnt_bdr_th = (uint8_t)((0x0700U & val) >> 8);
7306 ret = lsm6dsr_write_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
7307 (uint8_t *)&counter_bdr_reg1, 1);
7308 }
7309
7310 if (ret == 0)
7311 {
7312 counter_bdr_reg2.cnt_bdr_th = (uint8_t)(0x00FFU & val);
7313 ret = lsm6dsr_write_reg(ctx, LSM6DSR_COUNTER_BDR_REG2,
7314 (uint8_t *)&counter_bdr_reg2, 1);
7315 }
7316
7317 return ret;
7318 }
7319
7320 /**
7321 * @brief Batch data rate counter.[get]
7322 *
7323 * @param ctx Read / write interface definitions.(ptr)
7324 * @param val Change the values of cnt_bdr_th in reg COUNTER_BDR_REG2
7325 * and COUNTER_BDR_REG1.
7326 * @retval Interface status (MANDATORY: return 0 -> no Error).
7327 *
7328 */
lsm6dsr_batch_counter_threshold_get(stmdev_ctx_t * ctx,uint16_t * val)7329 int32_t lsm6dsr_batch_counter_threshold_get(stmdev_ctx_t *ctx,
7330 uint16_t *val)
7331 {
7332 lsm6dsr_counter_bdr_reg1_t counter_bdr_reg1;
7333 lsm6dsr_counter_bdr_reg2_t counter_bdr_reg2;
7334 int32_t ret;
7335
7336 ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG1,
7337 (uint8_t *)&counter_bdr_reg1, 1);
7338
7339 if (ret == 0)
7340 {
7341 ret = lsm6dsr_read_reg(ctx, LSM6DSR_COUNTER_BDR_REG2,
7342 (uint8_t *)&counter_bdr_reg2, 1);
7343 }
7344
7345 *val = counter_bdr_reg1.cnt_bdr_th;
7346 *val = *val << 8;
7347 *val += counter_bdr_reg2.cnt_bdr_th;
7348
7349 return ret;
7350 }
7351
7352 /**
7353 * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
7354 *
7355 * @param ctx Read / write interface definitions.(ptr)
7356 * @param val Change the values of diff_fifo in reg FIFO_STATUS1
7357 * @retval Interface status (MANDATORY: return 0 -> no Error).
7358 *
7359 */
lsm6dsr_fifo_data_level_get(stmdev_ctx_t * ctx,uint16_t * val)7360 int32_t lsm6dsr_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
7361 {
7362 lsm6dsr_fifo_status1_t fifo_status1;
7363 lsm6dsr_fifo_status2_t fifo_status2;
7364 int32_t ret;
7365
7366 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_STATUS1,
7367 (uint8_t *)&fifo_status1, 1);
7368
7369 if (ret == 0)
7370 {
7371 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_STATUS2,
7372 (uint8_t *)&fifo_status2, 1);
7373 *val = fifo_status2.diff_fifo;
7374 *val = *val << 8;
7375 *val += fifo_status1.diff_fifo;
7376 }
7377
7378 return ret;
7379 }
7380
7381 /**
7382 * @brief Smart FIFO status.[get]
7383 *
7384 * @param ctx Read / write interface definitions.(ptr)
7385 * @param val Registers FIFO_STATUS2
7386 * @retval Interface status (MANDATORY: return 0 -> no Error).
7387 *
7388 */
lsm6dsr_fifo_status_get(stmdev_ctx_t * ctx,lsm6dsr_fifo_status2_t * val)7389 int32_t lsm6dsr_fifo_status_get(stmdev_ctx_t *ctx,
7390 lsm6dsr_fifo_status2_t *val)
7391 {
7392 int32_t ret;
7393
7394 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_STATUS2, (uint8_t *)val, 1);
7395
7396 return ret;
7397 }
7398
7399 /**
7400 * @brief Smart FIFO full status.[get]
7401 *
7402 * @param ctx Read / write interface definitions.(ptr)
7403 * @param val Change the values of fifo_full_ia in reg FIFO_STATUS2
7404 * @retval Interface status (MANDATORY: return 0 -> no Error).
7405 *
7406 */
lsm6dsr_fifo_full_flag_get(stmdev_ctx_t * ctx,uint8_t * val)7407 int32_t lsm6dsr_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
7408 {
7409 lsm6dsr_fifo_status2_t fifo_status2;
7410 int32_t ret;
7411
7412 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_STATUS2,
7413 (uint8_t *)&fifo_status2, 1);
7414 *val = fifo_status2.fifo_full_ia;
7415
7416 return ret;
7417 }
7418
7419 /**
7420 * @brief FIFO overrun status.[get]
7421 *
7422 * @param ctx Read / write interface definitions.(ptr)
7423 * @param val Change the values of fifo_over_run_latched in
7424 * reg FIFO_STATUS2
7425 * @retval Interface status (MANDATORY: return 0 -> no Error).
7426 *
7427 */
lsm6dsr_fifo_ovr_flag_get(stmdev_ctx_t * ctx,uint8_t * val)7428 int32_t lsm6dsr_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
7429 {
7430 lsm6dsr_fifo_status2_t fifo_status2;
7431 int32_t ret;
7432
7433 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_STATUS2,
7434 (uint8_t *)&fifo_status2, 1);
7435 *val = fifo_status2. fifo_ovr_ia;
7436
7437 return ret;
7438 }
7439
7440 /**
7441 * @brief FIFO watermark status.[get]
7442 *
7443 * @param ctx Read / write interface definitions.(ptr)
7444 * @param val Change the values of fifo_wtm_ia in reg FIFO_STATUS2
7445 * @retval Interface status (MANDATORY: return 0 -> no Error).
7446 *
7447 */
lsm6dsr_fifo_wtm_flag_get(stmdev_ctx_t * ctx,uint8_t * val)7448 int32_t lsm6dsr_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
7449 {
7450 lsm6dsr_fifo_status2_t fifo_status2;
7451 int32_t ret;
7452
7453 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_STATUS2,
7454 (uint8_t *)&fifo_status2, 1);
7455 *val = fifo_status2.fifo_wtm_ia;
7456
7457 return ret;
7458 }
7459
7460 /**
7461 * @brief Identifies the sensor in FIFO_DATA_OUT.[get]
7462 *
7463 * @param ctx Read / write interface definitions.(ptr)
7464 * @param val Change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
7465 * @retval Interface status (MANDATORY: return 0 -> no Error).
7466 *
7467 */
lsm6dsr_fifo_sensor_tag_get(stmdev_ctx_t * ctx,lsm6dsr_fifo_tag_t * val)7468 int32_t lsm6dsr_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
7469 lsm6dsr_fifo_tag_t *val)
7470 {
7471 lsm6dsr_fifo_data_out_tag_t fifo_data_out_tag;
7472 int32_t ret;
7473
7474 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FIFO_DATA_OUT_TAG,
7475 (uint8_t *)&fifo_data_out_tag, 1);
7476
7477 switch (fifo_data_out_tag.tag_sensor)
7478 {
7479 case LSM6DSR_GYRO_NC_TAG:
7480 *val = LSM6DSR_GYRO_NC_TAG;
7481 break;
7482
7483 case LSM6DSR_XL_NC_TAG:
7484 *val = LSM6DSR_XL_NC_TAG;
7485 break;
7486
7487 case LSM6DSR_TEMPERATURE_TAG:
7488 *val = LSM6DSR_TEMPERATURE_TAG;
7489 break;
7490
7491 case LSM6DSR_TIMESTAMP_TAG:
7492 *val = LSM6DSR_TIMESTAMP_TAG;
7493 break;
7494
7495 case LSM6DSR_CFG_CHANGE_TAG:
7496 *val = LSM6DSR_CFG_CHANGE_TAG;
7497 break;
7498
7499 case LSM6DSR_XL_NC_T_2_TAG:
7500 *val = LSM6DSR_XL_NC_T_2_TAG;
7501 break;
7502
7503 case LSM6DSR_XL_NC_T_1_TAG:
7504 *val = LSM6DSR_XL_NC_T_1_TAG;
7505 break;
7506
7507 case LSM6DSR_XL_2XC_TAG:
7508 *val = LSM6DSR_XL_2XC_TAG;
7509 break;
7510
7511 case LSM6DSR_XL_3XC_TAG:
7512 *val = LSM6DSR_XL_3XC_TAG;
7513 break;
7514
7515 case LSM6DSR_GYRO_NC_T_2_TAG:
7516 *val = LSM6DSR_GYRO_NC_T_2_TAG;
7517 break;
7518
7519 case LSM6DSR_GYRO_NC_T_1_TAG:
7520 *val = LSM6DSR_GYRO_NC_T_1_TAG;
7521 break;
7522
7523 case LSM6DSR_GYRO_2XC_TAG:
7524 *val = LSM6DSR_GYRO_2XC_TAG;
7525 break;
7526
7527 case LSM6DSR_GYRO_3XC_TAG:
7528 *val = LSM6DSR_GYRO_3XC_TAG;
7529 break;
7530
7531 case LSM6DSR_SENSORHUB_SLAVE0_TAG:
7532 *val = LSM6DSR_SENSORHUB_SLAVE0_TAG;
7533 break;
7534
7535 case LSM6DSR_SENSORHUB_SLAVE1_TAG:
7536 *val = LSM6DSR_SENSORHUB_SLAVE1_TAG;
7537 break;
7538
7539 case LSM6DSR_SENSORHUB_SLAVE2_TAG:
7540 *val = LSM6DSR_SENSORHUB_SLAVE2_TAG;
7541 break;
7542
7543 case LSM6DSR_SENSORHUB_SLAVE3_TAG:
7544 *val = LSM6DSR_SENSORHUB_SLAVE3_TAG;
7545 break;
7546
7547 case LSM6DSR_STEP_CPUNTER_TAG:
7548 *val = LSM6DSR_STEP_CPUNTER_TAG;
7549 break;
7550
7551 case LSM6DSR_GAME_ROTATION_TAG:
7552 *val = LSM6DSR_GAME_ROTATION_TAG;
7553 break;
7554
7555 case LSM6DSR_GEOMAG_ROTATION_TAG:
7556 *val = LSM6DSR_GEOMAG_ROTATION_TAG;
7557 break;
7558
7559 case LSM6DSR_ROTATION_TAG:
7560 *val = LSM6DSR_ROTATION_TAG;
7561 break;
7562
7563 case LSM6DSR_SENSORHUB_NACK_TAG:
7564 *val = LSM6DSR_SENSORHUB_NACK_TAG;
7565 break;
7566
7567 default:
7568 *val = LSM6DSR_SENSORHUB_NACK_TAG;
7569 break;
7570 }
7571
7572 return ret;
7573 }
7574
7575 /**
7576 * @brief Enable FIFO batching of pedometer embedded function values.[set]
7577 *
7578 * @param ctx Read / write interface definitions.(ptr)
7579 * @param val Change the values of gbias_fifo_en in
7580 * reg LSM6DSR_EMB_FUNC_FIFO_CFG
7581 * @retval Interface status (MANDATORY: return 0 -> no Error).
7582 *
7583 */
lsm6dsr_fifo_pedo_batch_set(stmdev_ctx_t * ctx,uint8_t val)7584 int32_t lsm6dsr_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
7585 {
7586 lsm6dsr_emb_func_fifo_cfg_t emb_func_fifo_cfg;
7587 int32_t ret;
7588
7589 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
7590
7591 if (ret == 0)
7592 {
7593 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_FIFO_CFG,
7594 (uint8_t *)&emb_func_fifo_cfg, 1);
7595 }
7596
7597 if (ret == 0)
7598 {
7599 emb_func_fifo_cfg.pedo_fifo_en = (uint8_t)val;
7600 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_FIFO_CFG,
7601 (uint8_t *)&emb_func_fifo_cfg, 1);
7602 }
7603
7604 if (ret == 0)
7605 {
7606 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
7607 }
7608
7609 return ret;
7610 }
7611
7612 /**
7613 * @brief Enable FIFO batching of pedometer embedded function values.[get]
7614 *
7615 * @param ctx Read / write interface definitions.(ptr)
7616 * @param val Change the values of pedo_fifo_en in reg
7617 * LSM6DSR_EMB_FUNC_FIFO_CFG
7618 * @retval Interface status (MANDATORY: return 0 -> no Error).
7619 *
7620 */
lsm6dsr_fifo_pedo_batch_get(stmdev_ctx_t * ctx,uint8_t * val)7621 int32_t lsm6dsr_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
7622 {
7623 lsm6dsr_emb_func_fifo_cfg_t emb_func_fifo_cfg;
7624 int32_t ret;
7625
7626 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
7627
7628 if (ret == 0)
7629 {
7630 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_FIFO_CFG,
7631 (uint8_t *)&emb_func_fifo_cfg, 1);
7632 *val = emb_func_fifo_cfg.pedo_fifo_en;
7633 }
7634
7635 if (ret == 0)
7636 {
7637 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
7638 }
7639
7640 return ret;
7641 }
7642
7643 /**
7644 * @brief Enable FIFO batching data of first slave.[set]
7645 *
7646 * @param ctx Read / write interface definitions.(ptr)
7647 * @param val Change the values of batch_ext_sens_0_en in reg SLV0_CONFIG
7648 * @retval Interface status (MANDATORY: return 0 -> no Error).
7649 *
7650 */
lsm6dsr_sh_batch_slave_0_set(stmdev_ctx_t * ctx,uint8_t val)7651 int32_t lsm6dsr_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
7652 {
7653 lsm6dsr_slv0_config_t slv0_config;
7654 int32_t ret;
7655
7656 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
7657
7658 if (ret == 0)
7659 {
7660 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV0_CONFIG,
7661 (uint8_t *)&slv0_config, 1);
7662 }
7663
7664 if (ret == 0)
7665 {
7666 slv0_config. batch_ext_sens_0_en = (uint8_t)val;
7667 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_CONFIG,
7668 (uint8_t *)&slv0_config, 1);
7669 }
7670
7671 if (ret == 0)
7672 {
7673 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
7674 }
7675
7676 return ret;
7677 }
7678
7679 /**
7680 * @brief Enable FIFO batching data of first slave.[get]
7681 *
7682 * @param ctx Read / write interface definitions.(ptr)
7683 * @param val Change the values of batch_ext_sens_0_en in
7684 * reg SLV0_CONFIG
7685 * @retval Interface status (MANDATORY: return 0 -> no Error).
7686 *
7687 */
lsm6dsr_sh_batch_slave_0_get(stmdev_ctx_t * ctx,uint8_t * val)7688 int32_t lsm6dsr_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val)
7689 {
7690 lsm6dsr_slv0_config_t slv0_config;
7691 int32_t ret;
7692
7693 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
7694
7695 if (ret == 0)
7696 {
7697 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV0_CONFIG,
7698 (uint8_t *)&slv0_config, 1);
7699 }
7700
7701 if (ret == 0)
7702 {
7703 *val = slv0_config. batch_ext_sens_0_en;
7704 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
7705 }
7706
7707 return ret;
7708 }
7709
7710 /**
7711 * @brief Enable FIFO batching data of second slave.[set]
7712 *
7713 * @param ctx Read / write interface definitions.(ptr)
7714 * @param val Change the values of batch_ext_sens_1_en in
7715 * reg SLV1_CONFIG
7716 * @retval Interface status (MANDATORY: return 0 -> no Error).
7717 *
7718 */
lsm6dsr_sh_batch_slave_1_set(stmdev_ctx_t * ctx,uint8_t val)7719 int32_t lsm6dsr_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
7720 {
7721 lsm6dsr_slv1_config_t slv1_config;
7722 int32_t ret;
7723
7724 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
7725
7726 if (ret == 0)
7727 {
7728 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV1_CONFIG,
7729 (uint8_t *)&slv1_config, 1);
7730 }
7731
7732 if (ret == 0)
7733 {
7734 slv1_config. batch_ext_sens_1_en = (uint8_t)val;
7735 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV1_CONFIG,
7736 (uint8_t *)&slv1_config, 1);
7737 }
7738
7739 if (ret == 0)
7740 {
7741 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
7742 }
7743
7744 return ret;
7745 }
7746
7747 /**
7748 * @brief Enable FIFO batching data of second slave.[get]
7749 *
7750 * @param ctx Read / write interface definitions.(ptr)
7751 * @param val Change the values of batch_ext_sens_1_en in
7752 * reg SLV1_CONFIG
7753 * @retval Interface status (MANDATORY: return 0 -> no Error).
7754 *
7755 */
lsm6dsr_sh_batch_slave_1_get(stmdev_ctx_t * ctx,uint8_t * val)7756 int32_t lsm6dsr_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val)
7757 {
7758 lsm6dsr_slv1_config_t slv1_config;
7759 int32_t ret;
7760
7761 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
7762
7763 if (ret == 0)
7764 {
7765 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV1_CONFIG,
7766 (uint8_t *)&slv1_config, 1);
7767 *val = slv1_config. batch_ext_sens_1_en;
7768 }
7769
7770 if (ret == 0)
7771 {
7772 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
7773 }
7774
7775 return ret;
7776 }
7777
7778 /**
7779 * @brief Enable FIFO batching data of third slave.[set]
7780 *
7781 * @param ctx Read / write interface definitions.(ptr)
7782 * @param val Change the values of batch_ext_sens_2_en in
7783 * reg SLV2_CONFIG
7784 * @retval Interface status (MANDATORY: return 0 -> no Error).
7785 *
7786 */
lsm6dsr_sh_batch_slave_2_set(stmdev_ctx_t * ctx,uint8_t val)7787 int32_t lsm6dsr_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
7788 {
7789 lsm6dsr_slv2_config_t slv2_config;
7790 int32_t ret;
7791
7792 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
7793
7794 if (ret == 0)
7795 {
7796 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV2_CONFIG,
7797 (uint8_t *)&slv2_config, 1);
7798 }
7799
7800 if (ret == 0)
7801 {
7802 slv2_config. batch_ext_sens_2_en = (uint8_t)val;
7803 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV2_CONFIG,
7804 (uint8_t *)&slv2_config, 1);
7805 }
7806
7807 if (ret == 0)
7808 {
7809 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
7810 }
7811
7812 return ret;
7813 }
7814
7815 /**
7816 * @brief Enable FIFO batching data of third slave.[get]
7817 *
7818 * @param ctx Read / write interface definitions.(ptr)
7819 * @param val Change the values of batch_ext_sens_2_en in
7820 * reg SLV2_CONFIG
7821 * @retval Interface status (MANDATORY: return 0 -> no Error).
7822 *
7823 */
lsm6dsr_sh_batch_slave_2_get(stmdev_ctx_t * ctx,uint8_t * val)7824 int32_t lsm6dsr_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val)
7825 {
7826 lsm6dsr_slv2_config_t slv2_config;
7827 int32_t ret;
7828
7829 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
7830
7831 if (ret == 0)
7832 {
7833 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV2_CONFIG,
7834 (uint8_t *)&slv2_config, 1);
7835 }
7836
7837 if (ret == 0)
7838 {
7839 *val = slv2_config. batch_ext_sens_2_en;
7840 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
7841 }
7842
7843 return ret;
7844 }
7845
7846 /**
7847 * @brief Enable FIFO batching data of fourth slave.[set]
7848 *
7849 * @param ctx Read / write interface definitions.(ptr)
7850 * @param val Change the values of batch_ext_sens_3_en in
7851 * reg SLV3_CONFIG
7852 * @retval Interface status (MANDATORY: return 0 -> no Error).
7853 *
7854 */
lsm6dsr_sh_batch_slave_3_set(stmdev_ctx_t * ctx,uint8_t val)7855 int32_t lsm6dsr_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
7856 {
7857 lsm6dsr_slv3_config_t slv3_config;
7858 int32_t ret;
7859
7860 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
7861
7862 if (ret == 0)
7863 {
7864 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV3_CONFIG,
7865 (uint8_t *)&slv3_config, 1);
7866 }
7867
7868 if (ret == 0)
7869 {
7870 slv3_config. batch_ext_sens_3_en = (uint8_t)val;
7871 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV3_CONFIG,
7872 (uint8_t *)&slv3_config, 1);
7873 }
7874
7875 if (ret == 0)
7876 {
7877 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
7878 }
7879
7880 return ret;
7881 }
7882
7883 /**
7884 * @brief Enable FIFO batching data of fourth slave.[get]
7885 *
7886 * @param ctx Read / write interface definitions.(ptr)
7887 * @param val Change the values of batch_ext_sens_3_en in
7888 * reg SLV3_CONFIG
7889 * @retval Interface status (MANDATORY: return 0 -> no Error).
7890 *
7891 */
lsm6dsr_sh_batch_slave_3_get(stmdev_ctx_t * ctx,uint8_t * val)7892 int32_t lsm6dsr_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
7893 {
7894 lsm6dsr_slv3_config_t slv3_config;
7895 int32_t ret;
7896
7897 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
7898
7899 if (ret == 0)
7900 {
7901 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV3_CONFIG,
7902 (uint8_t *)&slv3_config, 1);
7903 *val = slv3_config. batch_ext_sens_3_en;
7904 }
7905
7906 if (ret == 0)
7907 {
7908 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
7909 }
7910
7911 return ret;
7912 }
7913
7914 /**
7915 * @}
7916 *
7917 */
7918
7919 /**
7920 * @defgroup LSM6DSR_DEN_functionality
7921 * @brief This section groups all the functions concerning
7922 * DEN functionality.
7923 * @{
7924 *
7925 */
7926
7927 /**
7928 * @brief DEN functionality marking mode.[set]
7929 *
7930 * @param ctx Read / write interface definitions.(ptr)
7931 * @param val Change the values of den_mode in reg CTRL6_C
7932 * @retval Interface status (MANDATORY: return 0 -> no Error).
7933 *
7934 */
lsm6dsr_den_mode_set(stmdev_ctx_t * ctx,lsm6dsr_den_mode_t val)7935 int32_t lsm6dsr_den_mode_set(stmdev_ctx_t *ctx,
7936 lsm6dsr_den_mode_t val)
7937 {
7938 lsm6dsr_ctrl6_c_t ctrl6_c;
7939 int32_t ret;
7940
7941 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
7942
7943 if (ret == 0)
7944 {
7945 ctrl6_c.den_mode = (uint8_t)val;
7946 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
7947 }
7948
7949 return ret;
7950 }
7951
7952 /**
7953 * @brief DEN functionality marking mode.[get]
7954 *
7955 * @param ctx Read / write interface definitions.(ptr)
7956 * @param val Get the values of den_mode in reg CTRL6_C
7957 * @retval Interface status (MANDATORY: return 0 -> no Error).
7958 *
7959 */
lsm6dsr_den_mode_get(stmdev_ctx_t * ctx,lsm6dsr_den_mode_t * val)7960 int32_t lsm6dsr_den_mode_get(stmdev_ctx_t *ctx,
7961 lsm6dsr_den_mode_t *val)
7962 {
7963 lsm6dsr_ctrl6_c_t ctrl6_c;
7964 int32_t ret;
7965
7966 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
7967
7968 switch (ctrl6_c.den_mode)
7969 {
7970 case LSM6DSR_DEN_DISABLE:
7971 *val = LSM6DSR_DEN_DISABLE;
7972 break;
7973
7974 case LSM6DSR_LEVEL_FIFO:
7975 *val = LSM6DSR_LEVEL_FIFO;
7976 break;
7977
7978 case LSM6DSR_LEVEL_LETCHED:
7979 *val = LSM6DSR_LEVEL_LETCHED;
7980 break;
7981
7982 case LSM6DSR_LEVEL_TRIGGER:
7983 *val = LSM6DSR_LEVEL_TRIGGER;
7984 break;
7985
7986 case LSM6DSR_EDGE_TRIGGER:
7987 *val = LSM6DSR_EDGE_TRIGGER;
7988 break;
7989
7990 default:
7991 *val = LSM6DSR_DEN_DISABLE;
7992 break;
7993 }
7994
7995 return ret;
7996 }
7997
7998 /**
7999 * @brief DEN active level configuration.[set]
8000 *
8001 * @param ctx Read / write interface definitions.(ptr)
8002 * @param val Change the values of den_lh in reg CTRL9_XL
8003 * @retval Interface status (MANDATORY: return 0 -> no Error).
8004 *
8005 */
lsm6dsr_den_polarity_set(stmdev_ctx_t * ctx,lsm6dsr_den_lh_t val)8006 int32_t lsm6dsr_den_polarity_set(stmdev_ctx_t *ctx,
8007 lsm6dsr_den_lh_t val)
8008 {
8009 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8010 int32_t ret;
8011
8012 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8013
8014 if (ret == 0)
8015 {
8016 ctrl9_xl.den_lh = (uint8_t)val;
8017 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL,
8018 (uint8_t *)&ctrl9_xl, 1);
8019 }
8020
8021 return ret;
8022 }
8023
8024 /**
8025 * @brief DEN active level configuration.[get]
8026 *
8027 * @param ctx Read / write interface definitions.(ptr)
8028 * @param val Get the values of den_lh in reg CTRL9_XL
8029 * @retval Interface status (MANDATORY: return 0 -> no Error).
8030 *
8031 */
lsm6dsr_den_polarity_get(stmdev_ctx_t * ctx,lsm6dsr_den_lh_t * val)8032 int32_t lsm6dsr_den_polarity_get(stmdev_ctx_t *ctx,
8033 lsm6dsr_den_lh_t *val)
8034 {
8035 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8036 int32_t ret;
8037
8038 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8039
8040 switch (ctrl9_xl.den_lh)
8041 {
8042 case LSM6DSR_DEN_ACT_LOW:
8043 *val = LSM6DSR_DEN_ACT_LOW;
8044 break;
8045
8046 case LSM6DSR_DEN_ACT_HIGH:
8047 *val = LSM6DSR_DEN_ACT_HIGH;
8048 break;
8049
8050 default:
8051 *val = LSM6DSR_DEN_ACT_LOW;
8052 break;
8053 }
8054
8055 return ret;
8056 }
8057
8058 /**
8059 * @brief DEN configuration.[set]
8060 *
8061 * @param ctx Read / write interface definitions.(ptr)
8062 * @param val Change the values of den_xl_g in reg CTRL9_XL
8063 * @retval Interface status (MANDATORY: return 0 -> no Error).
8064 *
8065 */
lsm6dsr_den_enable_set(stmdev_ctx_t * ctx,lsm6dsr_den_xl_g_t val)8066 int32_t lsm6dsr_den_enable_set(stmdev_ctx_t *ctx,
8067 lsm6dsr_den_xl_g_t val)
8068 {
8069 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8070 int32_t ret;
8071
8072 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8073
8074 if (ret == 0)
8075 {
8076 ctrl9_xl.den_xl_g = (uint8_t)val;
8077 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL,
8078 (uint8_t *)&ctrl9_xl, 1);
8079 }
8080
8081 return ret;
8082 }
8083
8084 /**
8085 * @brief DEN configuration.[get]
8086 *
8087 * @param ctx Read / write interface definitions.(ptr)
8088 * @param val Get the values of den_xl_g in reg CTRL9_XL
8089 * @retval Interface status (MANDATORY: return 0 -> no Error).
8090 *
8091 */
lsm6dsr_den_enable_get(stmdev_ctx_t * ctx,lsm6dsr_den_xl_g_t * val)8092 int32_t lsm6dsr_den_enable_get(stmdev_ctx_t *ctx,
8093 lsm6dsr_den_xl_g_t *val)
8094 {
8095 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8096 int32_t ret;
8097
8098 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8099
8100 switch (ctrl9_xl.den_xl_g)
8101 {
8102 case LSM6DSR_STAMP_IN_GY_DATA:
8103 *val = LSM6DSR_STAMP_IN_GY_DATA;
8104 break;
8105
8106 case LSM6DSR_STAMP_IN_XL_DATA:
8107 *val = LSM6DSR_STAMP_IN_XL_DATA;
8108 break;
8109
8110 case LSM6DSR_STAMP_IN_GY_XL_DATA:
8111 *val = LSM6DSR_STAMP_IN_GY_XL_DATA;
8112 break;
8113
8114 default:
8115 *val = LSM6DSR_STAMP_IN_GY_DATA;
8116 break;
8117 }
8118
8119 return ret;
8120 }
8121
8122 /**
8123 * @brief DEN value stored in LSB of X-axis.[set]
8124 *
8125 * @param ctx Read / write interface definitions.(ptr)
8126 * @param val Change the values of den_z in reg CTRL9_XL
8127 * @retval Interface status (MANDATORY: return 0 -> no Error).
8128 *
8129 */
lsm6dsr_den_mark_axis_x_set(stmdev_ctx_t * ctx,uint8_t val)8130 int32_t lsm6dsr_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
8131 {
8132 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8133 int32_t ret;
8134
8135 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8136
8137 if (ret == 0)
8138 {
8139 ctrl9_xl.den_z = (uint8_t)val;
8140 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL,
8141 (uint8_t *)&ctrl9_xl, 1);
8142 }
8143
8144 return ret;
8145 }
8146
8147 /**
8148 * @brief DEN value stored in LSB of X-axis.[get]
8149 *
8150 * @param ctx Read / write interface definitions.(ptr)
8151 * @param val Change the values of den_z in reg CTRL9_XL
8152 * @retval Interface status (MANDATORY: return 0 -> no Error).
8153 *
8154 */
lsm6dsr_den_mark_axis_x_get(stmdev_ctx_t * ctx,uint8_t * val)8155 int32_t lsm6dsr_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
8156 {
8157 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8158 int32_t ret;
8159
8160 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8161 *val = ctrl9_xl.den_z;
8162
8163 return ret;
8164 }
8165
8166 /**
8167 * @brief DEN value stored in LSB of Y-axis.[set]
8168 *
8169 * @param ctx Read / write interface definitions.(ptr)
8170 * @param val Change the values of den_y in reg CTRL9_XL
8171 * @retval Interface status (MANDATORY: return 0 -> no Error).
8172 *
8173 */
lsm6dsr_den_mark_axis_y_set(stmdev_ctx_t * ctx,uint8_t val)8174 int32_t lsm6dsr_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
8175 {
8176 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8177 int32_t ret;
8178
8179 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8180
8181 if (ret == 0)
8182 {
8183 ctrl9_xl.den_y = (uint8_t)val;
8184 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL,
8185 (uint8_t *)&ctrl9_xl, 1);
8186 }
8187
8188 return ret;
8189 }
8190
8191 /**
8192 * @brief DEN value stored in LSB of Y-axis.[get]
8193 *
8194 * @param ctx Read / write interface definitions.(ptr)
8195 * @param val Change the values of den_y in reg CTRL9_XL
8196 * @retval Interface status (MANDATORY: return 0 -> no Error).
8197 *
8198 */
lsm6dsr_den_mark_axis_y_get(stmdev_ctx_t * ctx,uint8_t * val)8199 int32_t lsm6dsr_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
8200 {
8201 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8202 int32_t ret;
8203
8204 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8205 *val = ctrl9_xl.den_y;
8206
8207 return ret;
8208 }
8209
8210 /**
8211 * @brief DEN value stored in LSB of Z-axis.[set]
8212 *
8213 * @param ctx Read / write interface definitions.(ptr)
8214 * @param val Change the values of den_x in reg CTRL9_XL
8215 * @retval Interface status (MANDATORY: return 0 -> no Error).
8216 *
8217 */
lsm6dsr_den_mark_axis_z_set(stmdev_ctx_t * ctx,uint8_t val)8218 int32_t lsm6dsr_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
8219 {
8220 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8221 int32_t ret;
8222
8223 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8224
8225 if (ret == 0)
8226 {
8227 ctrl9_xl.den_x = (uint8_t)val;
8228 ret = lsm6dsr_write_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8229 }
8230
8231 return ret;
8232 }
8233
8234 /**
8235 * @brief DEN value stored in LSB of Z-axis.[get]
8236 *
8237 * @param ctx Read / write interface definitions.(ptr)
8238 * @param val Change the values of den_x in reg CTRL9_XL
8239 * @retval Interface status (MANDATORY: return 0 -> no Error).
8240 *
8241 */
lsm6dsr_den_mark_axis_z_get(stmdev_ctx_t * ctx,uint8_t * val)8242 int32_t lsm6dsr_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
8243 {
8244 lsm6dsr_ctrl9_xl_t ctrl9_xl;
8245 int32_t ret;
8246
8247 ret = lsm6dsr_read_reg(ctx, LSM6DSR_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
8248 *val = ctrl9_xl.den_x;
8249
8250 return ret;
8251 }
8252
8253 /**
8254 * @}
8255 *
8256 */
8257
8258 /**
8259 * @defgroup LSM6DSR_Pedometer
8260 * @brief This section groups all the functions that manage pedometer.
8261 * @{
8262 *
8263 */
8264
8265 /**
8266 * @brief Enable pedometer algorithm.[set]
8267 *
8268 * @param ctx Read / write interface definitions.(ptr)
8269 * @param val Change the values of pedo_en in reg EMB_FUNC_EN_A
8270 * @retval Interface status (MANDATORY: return 0 -> no Error).
8271 *
8272 */
lsm6dsr_pedo_sens_set(stmdev_ctx_t * ctx,uint8_t val)8273 int32_t lsm6dsr_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val)
8274 {
8275 lsm6dsr_emb_func_en_a_t emb_func_en_a;
8276 int32_t ret;
8277
8278 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
8279
8280 if (ret == 0)
8281 {
8282 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
8283 (uint8_t *)&emb_func_en_a, 1);
8284 }
8285
8286 if (ret == 0)
8287 {
8288 emb_func_en_a.pedo_en = (uint8_t)val;
8289 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
8290 (uint8_t *)&emb_func_en_a, 1);
8291 }
8292
8293 if (ret == 0)
8294 {
8295 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
8296 }
8297
8298 return ret;
8299 }
8300
8301 /**
8302 * @brief Enable pedometer algorithm.[get]
8303 *
8304 * @param ctx Read / write interface definitions.(ptr)
8305 * @param val Change the values of pedo_en in reg EMB_FUNC_EN_A
8306 * @retval Interface status (MANDATORY: return 0 -> no Error).
8307 *
8308 */
lsm6dsr_pedo_sens_get(stmdev_ctx_t * ctx,uint8_t * val)8309 int32_t lsm6dsr_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
8310 {
8311 lsm6dsr_emb_func_en_a_t emb_func_en_a;
8312 int32_t ret;
8313
8314 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
8315
8316 if (ret == 0)
8317 {
8318 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
8319 (uint8_t *)&emb_func_en_a, 1);
8320 *val = emb_func_en_a.pedo_en;
8321 }
8322
8323 if (ret == 0)
8324 {
8325 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
8326 }
8327
8328 return ret;
8329 }
8330
8331 /**
8332 * @brief Pedometer algorithm working mode.[set]
8333 *
8334 * @param ctx read / write interface definitions
8335 * @param val Change the values of:
8336 * - pedo_fpr_adf_dis in reg ADV_PEDO
8337 * - pedo_adv_en in reg EMB_FUNC_EN_B
8338 * - ad_det_en in reg PEDO_CMD_REG
8339 * @retval Interface status (MANDATORY: return 0 -> no Error).
8340 *
8341 */
lsm6dsr_pedo_mode_set(stmdev_ctx_t * ctx,lsm6dsr_pedo_mode_t val)8342 int32_t lsm6dsr_pedo_mode_set(stmdev_ctx_t *ctx,
8343 lsm6dsr_pedo_mode_t val)
8344 {
8345 lsm6dsr_adv_pedo_t adv_pedo;
8346 lsm6dsr_emb_func_en_b_t emb_func_en_b;
8347 lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
8348 int32_t ret;
8349
8350 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
8351
8352 if (ret == 0)
8353 {
8354 ret = lsm6dsr_read_reg(ctx, LSM6DSR_ADV_PEDO, (uint8_t *)&adv_pedo, 1);
8355 }
8356
8357 if (ret == 0)
8358 {
8359 adv_pedo.pedo_fpr_adf_dis = (~((uint8_t)val) & 0x01U);
8360 ret = lsm6dsr_write_reg(ctx, LSM6DSR_ADV_PEDO, (uint8_t *)&adv_pedo, 1);
8361 }
8362
8363 if (ret == 0)
8364 {
8365 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
8366 (uint8_t *)&emb_func_en_b, 1);
8367 }
8368
8369 if (ret == 0)
8370 {
8371 emb_func_en_b.pedo_adv_en = (uint8_t)val & 0x01U;
8372 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
8373 (uint8_t *)&emb_func_en_b, 1);
8374 }
8375
8376 if (ret == 0)
8377 {
8378 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
8379 }
8380
8381 if (ret == 0)
8382 {
8383 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8384 (uint8_t *)&pedo_cmd_reg);
8385 pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x01U);
8386 pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x02U) >> 1;
8387 }
8388
8389 if (ret == 0)
8390 {
8391 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8392 (uint8_t *)&pedo_cmd_reg);
8393 }
8394
8395 return ret;
8396 }
8397
8398 /**
8399 * @brief Pedometer algorithm working mode.[get]
8400 *
8401 * @param ctx read / write interface definitions
8402 * @param val Get the values of:
8403 * - pedo_fpr_adf_dis in reg ADV_PEDO
8404 * - pedo_adv_en in reg EMB_FUNC_EN_B
8405 * - ad_det_en in reg PEDO_CMD_REG
8406 * @retval Interface status (MANDATORY: return 0 -> no Error).
8407 *
8408 */
lsm6dsr_pedo_mode_get(stmdev_ctx_t * ctx,lsm6dsr_pedo_mode_t * val)8409 int32_t lsm6dsr_pedo_mode_get(stmdev_ctx_t *ctx,
8410 lsm6dsr_pedo_mode_t *val)
8411 {
8412 lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
8413 int32_t ret;
8414
8415 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8416 (uint8_t *)&pedo_cmd_reg);
8417
8418 switch ((pedo_cmd_reg.ad_det_en << 1) |
8419 pedo_cmd_reg.fp_rejection_en)
8420 {
8421 case LSM6DSR_PEDO_BASE:
8422 *val = LSM6DSR_PEDO_BASE;
8423 break;
8424
8425 case LSM6DSR_PEDO_BASE_FALSE_STEP_REJ:
8426 *val = LSM6DSR_PEDO_BASE_FALSE_STEP_REJ;
8427 break;
8428
8429 case LSM6DSR_PEDO_ADV_FALSE_STEP_REJ:
8430 *val = LSM6DSR_PEDO_ADV_FALSE_STEP_REJ;
8431 break;
8432
8433 default:
8434 *val = LSM6DSR_PEDO_BASE;
8435 break;
8436 }
8437
8438 return ret;
8439 }
8440
8441 /**
8442 * @brief Interrupt status bit for step detection.[get]
8443 *
8444 * @param ctx Read / write interface definitions.(ptr)
8445 * @param val Change the values of is_step_det in reg EMB_FUNC_STATUS
8446 * @retval Interface status (MANDATORY: return 0 -> no Error).
8447 *
8448 */
lsm6dsr_pedo_step_detect_get(stmdev_ctx_t * ctx,uint8_t * val)8449 int32_t lsm6dsr_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val)
8450 {
8451 lsm6dsr_emb_func_status_t emb_func_status;
8452 int32_t ret;
8453
8454 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
8455
8456 if (ret == 0)
8457 {
8458 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_STATUS,
8459 (uint8_t *)&emb_func_status, 1);
8460 *val = emb_func_status.is_step_det;
8461 }
8462
8463 if (ret == 0)
8464 {
8465 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
8466 }
8467
8468 return ret;
8469 }
8470
8471 /**
8472 * @brief Pedometer debounce configuration register (r/w).[set]
8473 *
8474 * @param ctx Read / write interface definitions.(ptr)
8475 * @param buff Buffer that contains data to write
8476 * @retval Interface status (MANDATORY: return 0 -> no Error).
8477 *
8478 */
lsm6dsr_pedo_debounce_steps_set(stmdev_ctx_t * ctx,uint8_t * buff)8479 int32_t lsm6dsr_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
8480 uint8_t *buff)
8481 {
8482 int32_t ret;
8483
8484 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_DEB_STEPS_CONF,
8485 buff);
8486
8487 return ret;
8488 }
8489
8490 /**
8491 * @brief Pedometer debounce configuration register (r/w).[get]
8492 *
8493 * @param ctx Read / write interface definitions.(ptr)
8494 * @param buff Buffer that stores data read
8495 * @retval Interface status (MANDATORY: return 0 -> no Error).
8496 *
8497 */
lsm6dsr_pedo_debounce_steps_get(stmdev_ctx_t * ctx,uint8_t * buff)8498 int32_t lsm6dsr_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
8499 uint8_t *buff)
8500 {
8501 int32_t ret;
8502
8503 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_DEB_STEPS_CONF, buff);
8504
8505 return ret;
8506 }
8507
8508 /**
8509 * @brief Time period register for step detection on delta time (r/w).[set]
8510 *
8511 * @param ctx Read / write interface definitions.(ptr)
8512 * @param buff Buffer that contains data to write
8513 * @retval Interface status (MANDATORY: return 0 -> no Error).
8514 *
8515 */
lsm6dsr_pedo_steps_period_set(stmdev_ctx_t * ctx,uint16_t val)8516 int32_t lsm6dsr_pedo_steps_period_set(stmdev_ctx_t *ctx, uint16_t val)
8517 {
8518 uint8_t buff[2];
8519 int32_t ret;
8520
8521 buff[1] = (uint8_t)(val / 256U);
8522 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8523 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_SC_DELTAT_L,
8524 &buff[0]);
8525
8526 if (ret == 0)
8527 {
8528 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_SC_DELTAT_H,
8529 &buff[1]);
8530 }
8531
8532 return ret;
8533 }
8534
8535 /**
8536 * @brief Time period register for step detection on delta time (r/w).[get]
8537 *
8538 * @param ctx Read / write interface definitions.(ptr)
8539 * @param buff Buffer that stores data read
8540 * @retval Interface status (MANDATORY: return 0 -> no Error).
8541 *
8542 */
lsm6dsr_pedo_steps_period_get(stmdev_ctx_t * ctx,uint16_t * val)8543 int32_t lsm6dsr_pedo_steps_period_get(stmdev_ctx_t *ctx,
8544 uint16_t *val)
8545 {
8546 uint8_t buff[2];
8547 int32_t ret;
8548
8549 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_SC_DELTAT_L,
8550 &buff[0]);
8551
8552 if (ret == 0)
8553 {
8554 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_SC_DELTAT_H,
8555 &buff[1]);
8556 *val = buff[1];
8557 *val = (*val * 256U) + buff[0];
8558 }
8559
8560 return ret;
8561 }
8562
8563 /**
8564 * @brief Enables the advanced detection feature.[set]
8565 *
8566 * @param ctx Read / write interface definitions.(ptr)
8567 * @param val Change the values of ad_det_en in reg PEDO_CMD_REG
8568 * @retval Interface status (MANDATORY: return 0 -> no Error).
8569 *
8570 */
lsm6dsr_pedo_adv_detection_set(stmdev_ctx_t * ctx,uint8_t val)8571 int32_t lsm6dsr_pedo_adv_detection_set(stmdev_ctx_t *ctx, uint8_t val)
8572 {
8573 lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
8574 int32_t ret;
8575
8576 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8577 (uint8_t *)&pedo_cmd_reg);
8578
8579 if (ret == 0)
8580 {
8581 pedo_cmd_reg.ad_det_en = (uint8_t)val;
8582 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8583 (uint8_t *)&pedo_cmd_reg);
8584 }
8585
8586 return ret;
8587 }
8588
8589 /**
8590 * @brief Enables the advanced detection feature.[get]
8591 *
8592 * @param ctx Read / write interface definitions.(ptr)
8593 * @param val Change the values of ad_det_en in reg PEDO_CMD_REG
8594 * @retval Interface status (MANDATORY: return 0 -> no Error).
8595 *
8596 */
lsm6dsr_pedo_adv_detection_get(stmdev_ctx_t * ctx,uint8_t * val)8597 int32_t lsm6dsr_pedo_adv_detection_get(stmdev_ctx_t *ctx,
8598 uint8_t *val)
8599 {
8600 lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
8601 int32_t ret;
8602
8603 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8604 (uint8_t *)&pedo_cmd_reg);
8605 *val = pedo_cmd_reg.ad_det_en;
8606
8607 return ret;
8608 }
8609
8610 /**
8611 * @brief Enables the false-positive rejection feature.[set]
8612 *
8613 * @param ctx Read / write interface definitions.(ptr)
8614 * @param val Change the values of fp_rejection_en in reg PEDO_CMD_REG
8615 * @retval Interface status (MANDATORY: return 0 -> no Error).
8616 *
8617 */
lsm6dsr_pedo_false_step_rejection_set(stmdev_ctx_t * ctx,uint8_t val)8618 int32_t lsm6dsr_pedo_false_step_rejection_set(stmdev_ctx_t *ctx,
8619 uint8_t val)
8620 {
8621 lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
8622 int32_t ret;
8623
8624 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8625 (uint8_t *)&pedo_cmd_reg);
8626
8627 if (ret == 0)
8628 {
8629 pedo_cmd_reg.fp_rejection_en = (uint8_t)val;
8630 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8631 (uint8_t *)&pedo_cmd_reg);
8632 }
8633
8634 return ret;
8635 }
8636
8637 /**
8638 * @brief Enables the false-positive rejection feature.[get]
8639 *
8640 * @param ctx Read / write interface definitions.(ptr)
8641 * @param val Change the values of fp_rejection_en in reg PEDO_CMD_REG
8642 * @retval Interface status (MANDATORY: return 0 -> no Error).
8643 *
8644 */
lsm6dsr_pedo_false_step_rejection_get(stmdev_ctx_t * ctx,uint8_t * val)8645 int32_t lsm6dsr_pedo_false_step_rejection_get(stmdev_ctx_t *ctx,
8646 uint8_t *val)
8647 {
8648 lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
8649 int32_t ret;
8650
8651 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8652 (uint8_t *)&pedo_cmd_reg);
8653 *val = pedo_cmd_reg.fp_rejection_en;
8654
8655 return ret;
8656 }
8657
8658 /**
8659 * @brief Set when user wants to generate interrupt on count overflow
8660 * event/every step.[set]
8661 *
8662 * @param ctx Read / write interface definitions.(ptr)
8663 * @param val Change the values of carry_count_en in reg PEDO_CMD_REG
8664 * @retval Interface status (MANDATORY: return 0 -> no Error).
8665 *
8666 */
lsm6dsr_pedo_int_mode_set(stmdev_ctx_t * ctx,lsm6dsr_carry_count_en_t val)8667 int32_t lsm6dsr_pedo_int_mode_set(stmdev_ctx_t *ctx,
8668 lsm6dsr_carry_count_en_t val)
8669 {
8670 lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
8671 int32_t ret;
8672
8673 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8674 (uint8_t *)&pedo_cmd_reg);
8675
8676 if (ret == 0)
8677 {
8678 pedo_cmd_reg.carry_count_en = (uint8_t)val;
8679 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8680 (uint8_t *)&pedo_cmd_reg);
8681 }
8682
8683 return ret;
8684 }
8685
8686 /**
8687 * @brief Set when user wants to generate interrupt on count overflow
8688 * event/every step.[get]
8689 *
8690 * @param ctx Read / write interface definitions.(ptr)
8691 * @param val Get the values of carry_count_en in reg PEDO_CMD_REG
8692 * @retval Interface status (MANDATORY: return 0 -> no Error).
8693 *
8694 */
lsm6dsr_pedo_int_mode_get(stmdev_ctx_t * ctx,lsm6dsr_carry_count_en_t * val)8695 int32_t lsm6dsr_pedo_int_mode_get(stmdev_ctx_t *ctx,
8696 lsm6dsr_carry_count_en_t *val)
8697 {
8698 lsm6dsr_pedo_cmd_reg_t pedo_cmd_reg;
8699 int32_t ret;
8700
8701 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_PEDO_CMD_REG,
8702 (uint8_t *)&pedo_cmd_reg);
8703
8704 switch (pedo_cmd_reg.carry_count_en)
8705 {
8706 case LSM6DSR_EVERY_STEP:
8707 *val = LSM6DSR_EVERY_STEP;
8708 break;
8709
8710 case LSM6DSR_COUNT_OVERFLOW:
8711 *val = LSM6DSR_COUNT_OVERFLOW;
8712 break;
8713
8714 default:
8715 *val = LSM6DSR_EVERY_STEP;
8716 break;
8717 }
8718
8719 return ret;
8720 }
8721
8722 /**
8723 * @}
8724 *
8725 */
8726
8727 /**
8728 * @defgroup LSM6DSR_significant_motion
8729 * @brief This section groups all the functions that manage the
8730 * significant motion detection.
8731 * @{
8732 *
8733 */
8734
8735 /**
8736 * @brief Enable significant motion detection function.[set]
8737 *
8738 * @param ctx Read / write interface definitions.(ptr)
8739 * @param val Change the values of sign_motion_en in reg EMB_FUNC_EN_A
8740 * @retval Interface status (MANDATORY: return 0 -> no Error).
8741 *
8742 */
lsm6dsr_motion_sens_set(stmdev_ctx_t * ctx,uint8_t val)8743 int32_t lsm6dsr_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
8744 {
8745 lsm6dsr_emb_func_en_a_t emb_func_en_a;
8746 int32_t ret;
8747
8748 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
8749
8750 if (ret == 0)
8751 {
8752 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
8753 (uint8_t *)&emb_func_en_a, 1);
8754 }
8755
8756 if (ret == 0)
8757 {
8758 emb_func_en_a.sign_motion_en = (uint8_t)val;
8759 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
8760 (uint8_t *)&emb_func_en_a, 1);
8761 }
8762
8763 if (ret == 0)
8764 {
8765 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
8766 }
8767
8768 return ret;
8769 }
8770
8771 /**
8772 * @brief Enable significant motion detection function.[get]
8773 *
8774 * @param ctx Read / write interface definitions.(ptr)
8775 * @param val Change the values of sign_motion_en in reg EMB_FUNC_EN_A
8776 * @retval Interface status (MANDATORY: return 0 -> no Error).
8777 *
8778 */
lsm6dsr_motion_sens_get(stmdev_ctx_t * ctx,uint8_t * val)8779 int32_t lsm6dsr_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
8780 {
8781 lsm6dsr_emb_func_en_a_t emb_func_en_a;
8782 int32_t ret;
8783
8784 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
8785
8786 if (ret == 0)
8787 {
8788 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
8789 (uint8_t *)&emb_func_en_a, 1);
8790 }
8791
8792 if (ret == 0)
8793 {
8794 *val = emb_func_en_a.sign_motion_en;
8795 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
8796 }
8797
8798 return ret;
8799 }
8800
8801 /**
8802 * @brief Interrupt status bit for significant motion detection.[get]
8803 *
8804 * @param ctx Read / write interface definitions.(ptr)
8805 * @param val Change the values of is_sigmot in reg EMB_FUNC_STATUS
8806 * @retval Interface status (MANDATORY: return 0 -> no Error).
8807 *
8808 */
lsm6dsr_motion_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)8809 int32_t lsm6dsr_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
8810 uint8_t *val)
8811 {
8812 lsm6dsr_emb_func_status_t emb_func_status;
8813 int32_t ret;
8814
8815 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
8816
8817 if (ret == 0)
8818 {
8819 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_STATUS,
8820 (uint8_t *)&emb_func_status, 1);
8821 }
8822
8823 if (ret == 0)
8824 {
8825 *val = emb_func_status.is_sigmot;
8826 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
8827 }
8828
8829 return ret;
8830 }
8831
8832 /**
8833 * @}
8834 *
8835 */
8836
8837 /**
8838 * @defgroup LSM6DSR_tilt_detection
8839 * @brief This section groups all the functions that manage the tilt
8840 * event detection.
8841 * @{
8842 *
8843 */
8844
8845 /**
8846 * @brief Enable tilt calculation.[set]
8847 *
8848 * @param ctx Read / write interface definitions.(ptr)
8849 * @param val Change the values of tilt_en in reg EMB_FUNC_EN_A
8850 * @retval Interface status (MANDATORY: return 0 -> no Error).
8851 *
8852 */
lsm6dsr_tilt_sens_set(stmdev_ctx_t * ctx,uint8_t val)8853 int32_t lsm6dsr_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
8854 {
8855 lsm6dsr_emb_func_en_a_t emb_func_en_a;
8856 int32_t ret;
8857
8858 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
8859
8860 if (ret == 0)
8861 {
8862 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
8863 (uint8_t *)&emb_func_en_a, 1);
8864 }
8865
8866 if (ret == 0)
8867 {
8868 emb_func_en_a.tilt_en = (uint8_t)val;
8869 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
8870 (uint8_t *)&emb_func_en_a, 1);
8871 }
8872
8873 if (ret == 0)
8874 {
8875 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
8876 }
8877
8878 return ret;
8879 }
8880
8881 /**
8882 * @brief Enable tilt calculation.[get]
8883 *
8884 * @param ctx Read / write interface definitions.(ptr)
8885 * @param val Change the values of tilt_en in reg EMB_FUNC_EN_A
8886 * @retval Interface status (MANDATORY: return 0 -> no Error).
8887 *
8888 */
lsm6dsr_tilt_sens_get(stmdev_ctx_t * ctx,uint8_t * val)8889 int32_t lsm6dsr_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
8890 {
8891 lsm6dsr_emb_func_en_a_t emb_func_en_a;
8892 int32_t ret;
8893
8894 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
8895
8896 if (ret == 0)
8897 {
8898 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_A,
8899 (uint8_t *)&emb_func_en_a, 1);
8900 }
8901
8902 if (ret == 0)
8903 {
8904 *val = emb_func_en_a.tilt_en;
8905 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
8906 }
8907
8908 return ret;
8909 }
8910
8911 /**
8912 * @brief Interrupt status bit for tilt detection.[get]
8913 *
8914 * @param ctx Read / write interface definitions.(ptr)
8915 * @param val Change the values of is_tilt in reg EMB_FUNC_STATUS
8916 * @retval Interface status (MANDATORY: return 0 -> no Error).
8917 *
8918 */
lsm6dsr_tilt_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)8919 int32_t lsm6dsr_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
8920 uint8_t *val)
8921 {
8922 lsm6dsr_emb_func_status_t emb_func_status;
8923 int32_t ret;
8924
8925 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
8926
8927 if (ret == 0)
8928 {
8929 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_STATUS,
8930 (uint8_t *)&emb_func_status, 1);
8931 }
8932
8933 if (ret == 0)
8934 {
8935 *val = emb_func_status.is_tilt;
8936 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
8937 }
8938
8939 return ret;
8940 }
8941
8942 /**
8943 * @}
8944 *
8945 */
8946
8947 /**
8948 * @defgroup LSM6DSR_ magnetometer_sensor
8949 * @brief This section groups all the functions that manage additional
8950 * magnetometer sensor.
8951 * @{
8952 *
8953 */
8954
8955 /**
8956 * @brief External magnetometer sensitivity value register.[set]
8957 *
8958 * @param ctx Read / write interface definitions.(ptr)
8959 * @param buff Buffer that contains data to write
8960 * @retval Interface status (MANDATORY: return 0 -> no Error).
8961 *
8962 */
lsm6dsr_mag_sensitivity_set(stmdev_ctx_t * ctx,uint16_t val)8963 int32_t lsm6dsr_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val)
8964 {
8965 uint8_t buff[2];
8966 int32_t ret;
8967
8968 buff[1] = (uint8_t)(val / 256U);
8969 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8970 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SENSITIVITY_L,
8971 &buff[0]);
8972
8973 if (ret == 0)
8974 {
8975 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SENSITIVITY_H,
8976 &buff[1]);
8977 }
8978
8979 return ret;
8980 }
8981
8982 /**
8983 * @brief External magnetometer sensitivity value register.[get]
8984 *
8985 * @param ctx Read / write interface definitions.(ptr)
8986 * @param buff Buffer that stores data read
8987 * @retval Interface status (MANDATORY: return 0 -> no Error).
8988 *
8989 */
lsm6dsr_mag_sensitivity_get(stmdev_ctx_t * ctx,uint16_t * val)8990 int32_t lsm6dsr_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val)
8991 {
8992 uint8_t buff[2];
8993 int32_t ret;
8994
8995 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SENSITIVITY_L,
8996 &buff[0]);
8997
8998 if (ret == 0)
8999 {
9000 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SENSITIVITY_H,
9001 &buff[1]);
9002 *val = buff[1];
9003 *val = (*val * 256U) + buff[0];
9004 }
9005
9006 return ret;
9007 }
9008
9009 /**
9010 * @brief Offset for hard-iron compensation register (r/w).[set]
9011 *
9012 * @param ctx Read / write interface definitions.(ptr)
9013 * @param buff Buffer that contains data to write
9014 * @retval Interface status (MANDATORY: return 0 -> no Error).
9015 *
9016 */
lsm6dsr_mag_offset_set(stmdev_ctx_t * ctx,int16_t * val)9017 int32_t lsm6dsr_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
9018 {
9019 uint8_t buff[6];
9020 int32_t ret;
9021
9022 uint8_t i;
9023 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
9024 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
9025 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
9026 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
9027 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
9028 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
9029 i = 0x00U;
9030 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_OFFX_L, &buff[i]);
9031
9032 if (ret == 0)
9033 {
9034 i++;
9035 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_OFFX_H, &buff[i]);
9036 }
9037
9038 if (ret == 0)
9039 {
9040 i++;
9041 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_OFFY_L, &buff[i]);
9042 }
9043
9044 if (ret == 0)
9045 {
9046 i++;
9047 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_OFFY_H, &buff[i]);
9048 }
9049
9050 if (ret == 0)
9051 {
9052 i++;
9053 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_OFFZ_L, &buff[i]);
9054 }
9055
9056 if (ret == 0)
9057 {
9058 i++;
9059 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_OFFZ_H, &buff[i]);
9060 }
9061
9062 return ret;
9063 }
9064
9065 /**
9066 * @brief Offset for hard-iron compensation register (r/w).[get]
9067 *
9068 * @param ctx Read / write interface definitions.(ptr)
9069 * @param buff Buffer that stores data read
9070 * @retval Interface status (MANDATORY: return 0 -> no Error).
9071 *
9072 */
lsm6dsr_mag_offset_get(stmdev_ctx_t * ctx,int16_t * val)9073 int32_t lsm6dsr_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
9074 {
9075 uint8_t buff[6];
9076 int32_t ret;
9077
9078 uint8_t i;
9079 i = 0x00U;
9080 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_OFFX_L, &buff[i]);
9081
9082 if (ret == 0)
9083 {
9084 i++;
9085 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_OFFX_H, &buff[i]);
9086 }
9087
9088 if (ret == 0)
9089 {
9090 i++;
9091 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_OFFY_L, &buff[i]);
9092 }
9093
9094 if (ret == 0)
9095 {
9096 i++;
9097 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_OFFY_H, &buff[i]);
9098 }
9099
9100 if (ret == 0)
9101 {
9102 i++;
9103 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_OFFZ_L, &buff[i]);
9104 }
9105
9106 if (ret == 0)
9107 {
9108 i++;
9109 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_OFFZ_H, &buff[i]);
9110 val[0] = (int16_t)buff[1];
9111 val[0] = (val[0] * 256) + (int16_t)buff[0];
9112 val[1] = (int16_t)buff[3];
9113 val[1] = (val[1] * 256) + (int16_t)buff[2];
9114 val[2] = (int16_t)buff[5];
9115 val[2] = (val[2] * 256) + (int16_t)buff[4];
9116 }
9117
9118 return ret;
9119 }
9120
9121 /**
9122 * @brief Soft-iron (3x3 symmetric) matrix correction register (r/w).
9123 * The value is expressed as half-precision floating-point format:
9124 * SEEEEEFFFFFFFFFF
9125 * S: 1 sign bit;
9126 * E: 5 exponent bits;
9127 * F: 10 fraction bits).[set]
9128 *
9129 * @param ctx Read / write interface definitions.(ptr)
9130 * @param buff Buffer that contains data to write
9131 * @retval Interface status (MANDATORY: return 0 -> no Error).
9132 *
9133 */
lsm6dsr_mag_soft_iron_set(stmdev_ctx_t * ctx,int16_t * val)9134 int32_t lsm6dsr_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val)
9135 {
9136 uint8_t buff[12];
9137 int32_t ret;
9138
9139 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
9140 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
9141 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
9142 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
9143 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
9144 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
9145 buff[7] = (uint8_t)((uint16_t)val[3] / 256U);
9146 buff[6] = (uint8_t)((uint16_t)val[3] - (buff[7] * 256U));
9147 buff[9] = (uint8_t)((uint16_t)val[4] / 256U);
9148 buff[8] = (uint8_t)((uint16_t)val[4] - (buff[9] * 256U));
9149 buff[11] = (uint8_t)((uint16_t)val[5] / 256U);
9150 buff[10] = (uint8_t)((uint16_t)val[5] - (buff[11] * 256U));
9151 uint8_t i;
9152 i = 0x00U;
9153 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_XX_L, &buff[i]);
9154
9155 if (ret == 0)
9156 {
9157 i++;
9158 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_XX_H, &buff[i]);
9159 }
9160
9161 if (ret == 0)
9162 {
9163 i++;
9164 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_XY_L, &buff[i]);
9165 }
9166
9167 if (ret == 0)
9168 {
9169 i++;
9170 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_XY_H, &buff[i]);
9171 }
9172
9173 if (ret == 0)
9174 {
9175 i++;
9176 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_XZ_L, &buff[i]);
9177 }
9178
9179 if (ret == 0)
9180 {
9181 i++;
9182 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_XZ_H, &buff[i]);
9183 }
9184
9185 if (ret == 0)
9186 {
9187 i++;
9188 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_YY_L, &buff[i]);
9189 }
9190
9191 if (ret == 0)
9192 {
9193 i++;
9194 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_YY_H, &buff[i]);
9195 }
9196
9197 if (ret == 0)
9198 {
9199 i++;
9200 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_YZ_L, &buff[i]);
9201 }
9202
9203 if (ret == 0)
9204 {
9205 i++;
9206 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_YZ_H, &buff[i]);
9207 }
9208
9209 if (ret == 0)
9210 {
9211 i++;
9212 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_ZZ_L, &buff[i]);
9213 }
9214
9215 if (ret == 0)
9216 {
9217 i++;
9218 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_SI_ZZ_H, &buff[i]);
9219 }
9220
9221 return ret;
9222 }
9223
9224 /**
9225 * @brief Soft-iron (3x3 symmetric) matrix correction register (r/w).
9226 * The value is expressed as half-precision floating-point format:
9227 * SEEEEEFFFFFFFFFF
9228 * S: 1 sign bit;
9229 * E: 5 exponent bits;
9230 * F: 10 fraction bits).[get]
9231 *
9232 * @param ctx Read / write interface definitions.(ptr)
9233 * @param buff Buffer that stores data read
9234 * @retval Interface status (MANDATORY: return 0 -> no Error).
9235 *
9236 */
lsm6dsr_mag_soft_iron_get(stmdev_ctx_t * ctx,int16_t * val)9237 int32_t lsm6dsr_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val)
9238 {
9239 uint8_t buff[12];
9240 int32_t ret;
9241
9242 uint8_t i;
9243 i = 0x00U;
9244 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_XX_L, &buff[i]);
9245
9246 if (ret == 0)
9247 {
9248 i++;
9249 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_XX_H, &buff[i]);
9250 }
9251
9252 if (ret == 0)
9253 {
9254 i++;
9255 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_XY_L, &buff[i]);
9256 }
9257
9258 if (ret == 0)
9259 {
9260 i++;
9261 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_XY_H, &buff[i]);
9262 }
9263
9264 if (ret == 0)
9265 {
9266 i++;
9267 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_XZ_L, &buff[i]);
9268 }
9269
9270 if (ret == 0)
9271 {
9272 i++;
9273 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_XZ_H, &buff[i]);
9274 }
9275
9276 if (ret == 0)
9277 {
9278 i++;
9279 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_YY_L, &buff[i]);
9280 }
9281
9282 if (ret == 0)
9283 {
9284 i++;
9285 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_YY_H, &buff[i]);
9286 }
9287
9288 if (ret == 0)
9289 {
9290 i++;
9291 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_YZ_L, &buff[i]);
9292 }
9293
9294 if (ret == 0)
9295 {
9296 i++;
9297 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_YZ_H, &buff[i]);
9298 }
9299
9300 if (ret == 0)
9301 {
9302 i++;
9303 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_ZZ_L, &buff[i]);
9304 }
9305
9306 if (ret == 0)
9307 {
9308 i++;
9309 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_SI_ZZ_H, &buff[i]);
9310 }
9311
9312 val[0] = (int16_t)buff[1];
9313 val[0] = (val[0] * 256) + (int16_t)buff[0];
9314 val[1] = (int16_t)buff[3];
9315 val[1] = (val[1] * 256) + (int16_t)buff[2];
9316 val[2] = (int16_t)buff[5];
9317 val[2] = (val[2] * 256) + (int16_t)buff[4];
9318 val[3] = (int16_t)buff[7];
9319 val[3] = (val[3] * 256) + (int16_t)buff[6];
9320 val[4] = (int16_t)buff[9];
9321 val[4] = (val[4] * 256) + (int16_t)buff[8];
9322 val[5] = (int16_t)buff[11];
9323 val[5] = (val[5] * 256) + (int16_t)buff[10];
9324
9325 return ret;
9326 }
9327
9328 /**
9329 * @brief Magnetometer Z-axis coordinates rotation (to be aligned to
9330 * accelerometer/gyroscope axes orientation).[set]
9331 *
9332 * @param ctx Read / write interface definitions.(ptr)
9333 * @param val Change the values of mag_z_axis in reg MAG_CFG_A
9334 * @retval Interface status (MANDATORY: return 0 -> no Error).
9335 *
9336 */
lsm6dsr_mag_z_orient_set(stmdev_ctx_t * ctx,lsm6dsr_mag_z_axis_t val)9337 int32_t lsm6dsr_mag_z_orient_set(stmdev_ctx_t *ctx,
9338 lsm6dsr_mag_z_axis_t val)
9339 {
9340 lsm6dsr_mag_cfg_a_t mag_cfg_a;
9341 int32_t ret;
9342
9343 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_A,
9344 (uint8_t *)&mag_cfg_a);
9345
9346 if (ret == 0)
9347 {
9348 mag_cfg_a.mag_z_axis = (uint8_t)val;
9349 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_CFG_A,
9350 (uint8_t *)&mag_cfg_a);
9351 }
9352
9353 return ret;
9354 }
9355
9356 /**
9357 * @brief Magnetometer Z-axis coordinates rotation (to be aligned to
9358 * accelerometer/gyroscope axes orientation).[get]
9359 *
9360 * @param ctx Read / write interface definitions.(ptr)
9361 * @param val Get the values of mag_z_axis in reg MAG_CFG_A
9362 * @retval Interface status (MANDATORY: return 0 -> no Error).
9363 *
9364 */
lsm6dsr_mag_z_orient_get(stmdev_ctx_t * ctx,lsm6dsr_mag_z_axis_t * val)9365 int32_t lsm6dsr_mag_z_orient_get(stmdev_ctx_t *ctx,
9366 lsm6dsr_mag_z_axis_t *val)
9367 {
9368 lsm6dsr_mag_cfg_a_t mag_cfg_a;
9369 int32_t ret;
9370
9371 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_A,
9372 (uint8_t *)&mag_cfg_a);
9373
9374 switch (mag_cfg_a.mag_z_axis)
9375 {
9376 case LSM6DSR_Z_EQ_Y:
9377 *val = LSM6DSR_Z_EQ_Y;
9378 break;
9379
9380 case LSM6DSR_Z_EQ_MIN_Y:
9381 *val = LSM6DSR_Z_EQ_MIN_Y;
9382 break;
9383
9384 case LSM6DSR_Z_EQ_X:
9385 *val = LSM6DSR_Z_EQ_X;
9386 break;
9387
9388 case LSM6DSR_Z_EQ_MIN_X:
9389 *val = LSM6DSR_Z_EQ_MIN_X;
9390 break;
9391
9392 case LSM6DSR_Z_EQ_MIN_Z:
9393 *val = LSM6DSR_Z_EQ_MIN_Z;
9394 break;
9395
9396 case LSM6DSR_Z_EQ_Z:
9397 *val = LSM6DSR_Z_EQ_Z;
9398 break;
9399
9400 default:
9401 *val = LSM6DSR_Z_EQ_Y;
9402 break;
9403 }
9404
9405 return ret;
9406 }
9407
9408 /**
9409 * @brief Magnetometer Y-axis coordinates rotation (to be aligned to
9410 * accelerometer/gyroscope axes orientation).[set]
9411 *
9412 * @param ctx Read / write interface definitions.(ptr)
9413 * @param val Change the values of mag_y_axis in
9414 * reg MAG_CFG_A
9415 * @retval Interface status (MANDATORY: return 0 -> no Error).
9416 *
9417 */
lsm6dsr_mag_y_orient_set(stmdev_ctx_t * ctx,lsm6dsr_mag_y_axis_t val)9418 int32_t lsm6dsr_mag_y_orient_set(stmdev_ctx_t *ctx,
9419 lsm6dsr_mag_y_axis_t val)
9420 {
9421 lsm6dsr_mag_cfg_a_t mag_cfg_a;
9422 int32_t ret;
9423
9424 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_A,
9425 (uint8_t *)&mag_cfg_a);
9426
9427 if (ret == 0)
9428 {
9429 mag_cfg_a.mag_y_axis = (uint8_t)val;
9430 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_CFG_A,
9431 (uint8_t *)&mag_cfg_a);
9432 }
9433
9434 return ret;
9435 }
9436
9437 /**
9438 * @brief Magnetometer Y-axis coordinates rotation (to be aligned to
9439 * accelerometer/gyroscope axes orientation).[get]
9440 *
9441 * @param ctx Read / write interface definitions.(ptr)
9442 * @param val Get the values of mag_y_axis in reg MAG_CFG_A
9443 * @retval Interface status (MANDATORY: return 0 -> no Error).
9444 *
9445 */
lsm6dsr_mag_y_orient_get(stmdev_ctx_t * ctx,lsm6dsr_mag_y_axis_t * val)9446 int32_t lsm6dsr_mag_y_orient_get(stmdev_ctx_t *ctx,
9447 lsm6dsr_mag_y_axis_t *val)
9448 {
9449 lsm6dsr_mag_cfg_a_t mag_cfg_a;
9450 int32_t ret;
9451
9452 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_A,
9453 (uint8_t *)&mag_cfg_a);
9454
9455 switch (mag_cfg_a.mag_y_axis)
9456 {
9457 case LSM6DSR_Y_EQ_Y:
9458 *val = LSM6DSR_Y_EQ_Y;
9459 break;
9460
9461 case LSM6DSR_Y_EQ_MIN_Y:
9462 *val = LSM6DSR_Y_EQ_MIN_Y;
9463 break;
9464
9465 case LSM6DSR_Y_EQ_X:
9466 *val = LSM6DSR_Y_EQ_X;
9467 break;
9468
9469 case LSM6DSR_Y_EQ_MIN_X:
9470 *val = LSM6DSR_Y_EQ_MIN_X;
9471 break;
9472
9473 case LSM6DSR_Y_EQ_MIN_Z:
9474 *val = LSM6DSR_Y_EQ_MIN_Z;
9475 break;
9476
9477 case LSM6DSR_Y_EQ_Z:
9478 *val = LSM6DSR_Y_EQ_Z;
9479 break;
9480
9481 default:
9482 *val = LSM6DSR_Y_EQ_Y;
9483 break;
9484 }
9485
9486 return ret;
9487 }
9488
9489 /**
9490 * @brief Magnetometer X-axis coordinates rotation (to be aligned to
9491 * accelerometer/gyroscope axes orientation).[set]
9492 *
9493 * @param ctx Read / write interface definitions.(ptr)
9494 * @param val Change the values of mag_x_axis in reg MAG_CFG_B
9495 * @retval Interface status (MANDATORY: return 0 -> no Error).
9496 *
9497 */
lsm6dsr_mag_x_orient_set(stmdev_ctx_t * ctx,lsm6dsr_mag_x_axis_t val)9498 int32_t lsm6dsr_mag_x_orient_set(stmdev_ctx_t *ctx,
9499 lsm6dsr_mag_x_axis_t val)
9500 {
9501 lsm6dsr_mag_cfg_b_t mag_cfg_b;
9502 int32_t ret;
9503
9504 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_B,
9505 (uint8_t *)&mag_cfg_b);
9506
9507 if (ret == 0)
9508 {
9509 mag_cfg_b.mag_x_axis = (uint8_t)val;
9510 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_MAG_CFG_B,
9511 (uint8_t *)&mag_cfg_b);
9512 }
9513
9514 return ret;
9515 }
9516
9517 /**
9518 * @brief Magnetometer X-axis coordinates rotation (to be aligned to
9519 * accelerometer/gyroscope axes orientation).[get]
9520 *
9521 * @param ctx Read / write interface definitions.(ptr)
9522 * @param val Get the values of mag_x_axis in reg MAG_CFG_B
9523 * @retval Interface status (MANDATORY: return 0 -> no Error).
9524 *
9525 */
lsm6dsr_mag_x_orient_get(stmdev_ctx_t * ctx,lsm6dsr_mag_x_axis_t * val)9526 int32_t lsm6dsr_mag_x_orient_get(stmdev_ctx_t *ctx,
9527 lsm6dsr_mag_x_axis_t *val)
9528 {
9529 lsm6dsr_mag_cfg_b_t mag_cfg_b;
9530 int32_t ret;
9531
9532 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_MAG_CFG_B,
9533 (uint8_t *)&mag_cfg_b);
9534
9535 switch (mag_cfg_b.mag_x_axis)
9536 {
9537 case LSM6DSR_X_EQ_Y:
9538 *val = LSM6DSR_X_EQ_Y;
9539 break;
9540
9541 case LSM6DSR_X_EQ_MIN_Y:
9542 *val = LSM6DSR_X_EQ_MIN_Y;
9543 break;
9544
9545 case LSM6DSR_X_EQ_X:
9546 *val = LSM6DSR_X_EQ_X;
9547 break;
9548
9549 case LSM6DSR_X_EQ_MIN_X:
9550 *val = LSM6DSR_X_EQ_MIN_X;
9551 break;
9552
9553 case LSM6DSR_X_EQ_MIN_Z:
9554 *val = LSM6DSR_X_EQ_MIN_Z;
9555 break;
9556
9557 case LSM6DSR_X_EQ_Z:
9558 *val = LSM6DSR_X_EQ_Z;
9559 break;
9560
9561 default:
9562 *val = LSM6DSR_X_EQ_Y;
9563 break;
9564 }
9565
9566 return ret;
9567 }
9568
9569 /**
9570 * @}
9571 *
9572 */
9573
9574 /**
9575 * @defgroup LSM6DSR_finite_state_machine
9576 * @brief This section groups all the functions that manage the
9577 * state_machine.
9578 * @{
9579 *
9580 */
9581
9582 /**
9583 * @brief Interrupt status bit for FSM long counter timeout interrupt
9584 * event.[get]
9585 *
9586 * @param ctx Read / write interface definitions.(ptr)
9587 * @param val Change the values of is_fsm_lc in reg EMB_FUNC_STATUS
9588 * @retval Interface status (MANDATORY: return 0 -> no Error).
9589 *
9590 */
lsm6dsr_long_cnt_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)9591 int32_t lsm6dsr_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
9592 uint8_t *val)
9593 {
9594 lsm6dsr_emb_func_status_t emb_func_status;
9595 int32_t ret;
9596
9597 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9598
9599 if (ret == 0)
9600 {
9601 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_STATUS,
9602 (uint8_t *)&emb_func_status, 1);
9603 }
9604
9605 if (ret == 0)
9606 {
9607 *val = emb_func_status.is_fsm_lc;
9608 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
9609 }
9610
9611 return ret;
9612 }
9613
9614 /**
9615 * @brief Embedded final state machine functions mode.[set]
9616 *
9617 * @param ctx Read / write interface definitions.(ptr)
9618 * @param val Change the values of fsm_en in reg EMB_FUNC_EN_B
9619 * @retval Interface status (MANDATORY: return 0 -> no Error).
9620 *
9621 */
lsm6dsr_emb_fsm_en_set(stmdev_ctx_t * ctx,uint8_t val)9622 int32_t lsm6dsr_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val)
9623 {
9624 int32_t ret;
9625
9626 lsm6dsr_emb_func_en_b_t emb_func_en_b;
9627 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9628
9629 if (ret == 0)
9630 {
9631 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
9632 (uint8_t *)&emb_func_en_b, 1);
9633 }
9634
9635 if (ret == 0)
9636 {
9637 emb_func_en_b.fsm_en = (uint8_t)val;
9638 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
9639 (uint8_t *)&emb_func_en_b, 1);
9640 }
9641
9642 if (ret == 0)
9643 {
9644 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
9645 }
9646
9647 return ret;
9648 }
9649
9650 /**
9651 * @brief Embedded final state machine functions mode.[get]
9652 *
9653 * @param ctx Read / write interface definitions.(ptr)
9654 * @param val Get the values of fsm_en in reg EMB_FUNC_EN_B
9655 * @retval Interface status (MANDATORY: return 0 -> no Error).
9656 *
9657 */
lsm6dsr_emb_fsm_en_get(stmdev_ctx_t * ctx,uint8_t * val)9658 int32_t lsm6dsr_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
9659 {
9660 int32_t ret;
9661
9662 lsm6dsr_emb_func_en_b_t emb_func_en_b;
9663 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9664
9665 if (ret == 0)
9666 {
9667 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
9668 (uint8_t *)&emb_func_en_b, 1);
9669 }
9670
9671 if (ret == 0)
9672 {
9673 *val = emb_func_en_b.fsm_en;
9674 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
9675 (uint8_t *)&emb_func_en_b, 1);
9676 }
9677
9678 if (ret == 0)
9679 {
9680 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
9681 }
9682
9683 return ret;
9684 }
9685
9686 /**
9687 * @brief Embedded final state machine functions mode.[set]
9688 *
9689 * @param ctx Read / write interface definitions.(ptr)
9690 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
9691 * @retval Interface status (MANDATORY: return 0 -> no Error).
9692 *
9693 */
lsm6dsr_fsm_enable_set(stmdev_ctx_t * ctx,lsm6dsr_emb_fsm_enable_t * val)9694 int32_t lsm6dsr_fsm_enable_set(stmdev_ctx_t *ctx,
9695 lsm6dsr_emb_fsm_enable_t *val)
9696 {
9697 lsm6dsr_emb_func_en_b_t emb_func_en_b;
9698 int32_t ret;
9699
9700 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9701
9702 if (ret == 0)
9703 {
9704 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_ENABLE_A,
9705 (uint8_t *)&val->fsm_enable_a, 1);
9706 }
9707
9708 if (ret == 0)
9709 {
9710 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_ENABLE_B,
9711 (uint8_t *)&val->fsm_enable_b, 1);
9712 }
9713
9714 if (ret == 0)
9715 {
9716 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
9717 (uint8_t *)&emb_func_en_b, 1);
9718 }
9719
9720 if (ret == 0)
9721 {
9722 if ((val->fsm_enable_a.fsm1_en |
9723 val->fsm_enable_a.fsm2_en |
9724 val->fsm_enable_a.fsm3_en |
9725 val->fsm_enable_a.fsm4_en |
9726 val->fsm_enable_a.fsm5_en |
9727 val->fsm_enable_a.fsm6_en |
9728 val->fsm_enable_a.fsm7_en |
9729 val->fsm_enable_a.fsm8_en |
9730 val->fsm_enable_b.fsm9_en |
9731 val->fsm_enable_b.fsm10_en |
9732 val->fsm_enable_b.fsm11_en |
9733 val->fsm_enable_b.fsm12_en |
9734 val->fsm_enable_b.fsm13_en |
9735 val->fsm_enable_b.fsm14_en |
9736 val->fsm_enable_b.fsm15_en |
9737 val->fsm_enable_b.fsm16_en) != PROPERTY_DISABLE)
9738 {
9739 emb_func_en_b.fsm_en = PROPERTY_ENABLE;
9740 }
9741
9742 else
9743 {
9744 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
9745 }
9746 }
9747
9748 if (ret == 0)
9749 {
9750 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_EN_B,
9751 (uint8_t *)&emb_func_en_b, 1);
9752 }
9753
9754 if (ret == 0)
9755 {
9756 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
9757 }
9758
9759 return ret;
9760 }
9761
9762 /**
9763 * @brief Embedded final state machine functions mode.[get]
9764 *
9765 * @param ctx Read / write interface definitions.(ptr)
9766 * @param val Structure of registers from FSM_ENABLE_A to FSM_ENABLE_B
9767 * @retval Interface status (MANDATORY: return 0 -> no Error).
9768 *
9769 */
lsm6dsr_fsm_enable_get(stmdev_ctx_t * ctx,lsm6dsr_emb_fsm_enable_t * val)9770 int32_t lsm6dsr_fsm_enable_get(stmdev_ctx_t *ctx,
9771 lsm6dsr_emb_fsm_enable_t *val)
9772 {
9773 int32_t ret;
9774
9775 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9776
9777 if (ret == 0)
9778 {
9779 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_ENABLE_A,
9780 (uint8_t *)&val->fsm_enable_a, 1);
9781 }
9782
9783 if (ret == 0)
9784 {
9785 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_ENABLE_B,
9786 (uint8_t *)&val->fsm_enable_b, 1);
9787 }
9788
9789 if (ret == 0)
9790 {
9791 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
9792 }
9793
9794 return ret;
9795 }
9796
9797 /**
9798 * @brief FSM long counter status register. Long counter value is an
9799 * unsigned integer value (16-bit format).[set]
9800 *
9801 * @param ctx Read / write interface definitions.(ptr)
9802 * @param buff Buffer that contains data to write
9803 * @retval Interface status (MANDATORY: return 0 -> no Error).
9804 *
9805 */
lsm6dsr_long_cnt_set(stmdev_ctx_t * ctx,uint16_t val)9806 int32_t lsm6dsr_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
9807 {
9808 uint8_t buff[2];
9809 int32_t ret;
9810
9811 buff[1] = (uint8_t)(val / 256U);
9812 buff[0] = (uint8_t)(val - (buff[1] * 256U));
9813 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9814
9815 if (ret == 0)
9816 {
9817 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_LONG_COUNTER_L, buff, 2);
9818 }
9819
9820 if (ret == 0)
9821 {
9822 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
9823 }
9824
9825 return ret;
9826 }
9827
9828 /**
9829 * @brief FSM long counter status register. Long counter value is an
9830 * unsigned integer value (16-bit format).[get]
9831 *
9832 * @param ctx Read / write interface definitions.(ptr)
9833 * @param buff Buffer that stores data read
9834 * @retval Interface status (MANDATORY: return 0 -> no Error).
9835 *
9836 */
lsm6dsr_long_cnt_get(stmdev_ctx_t * ctx,uint16_t * val)9837 int32_t lsm6dsr_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
9838 {
9839 uint8_t buff[2];
9840 int32_t ret;
9841
9842 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9843
9844 if (ret == 0)
9845 {
9846 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_LONG_COUNTER_L, buff, 2);
9847 }
9848
9849 if (ret == 0)
9850 {
9851 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
9852 *val = buff[1];
9853 *val = (*val * 256U) + buff[0];
9854 }
9855
9856 return ret;
9857 }
9858
9859 /**
9860 * @brief Clear FSM long counter value.[set]
9861 *
9862 * @param ctx Read / write interface definitions.(ptr)
9863 * @param val Change the values of fsm_lc_clr in reg
9864 * FSM_LONG_COUNTER_CLEAR
9865 * @retval Interface status (MANDATORY: return 0 -> no Error).
9866 *
9867 */
lsm6dsr_long_clr_set(stmdev_ctx_t * ctx,lsm6dsr_fsm_lc_clr_t val)9868 int32_t lsm6dsr_long_clr_set(stmdev_ctx_t *ctx,
9869 lsm6dsr_fsm_lc_clr_t val)
9870 {
9871 lsm6dsr_fsm_long_counter_clear_t fsm_long_counter_clear;
9872 int32_t ret;
9873
9874 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9875
9876 if (ret == 0)
9877 {
9878 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_LONG_COUNTER_CLEAR,
9879 (uint8_t *)&fsm_long_counter_clear, 1);
9880 }
9881
9882 if (ret == 0)
9883 {
9884 fsm_long_counter_clear.fsm_lc_clr = (uint8_t)val;
9885 ret = lsm6dsr_write_reg(ctx, LSM6DSR_FSM_LONG_COUNTER_CLEAR,
9886 (uint8_t *)&fsm_long_counter_clear, 1);
9887 }
9888
9889 if (ret == 0)
9890 {
9891 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
9892 }
9893
9894 return ret;
9895 }
9896
9897 /**
9898 * @brief Clear FSM long counter value.[get]
9899 *
9900 * @param ctx Read / write interface definitions.(ptr)
9901 * @param val Get the values of fsm_lc_clr in reg FSM_LONG_COUNTER_CLEAR
9902 * @retval Interface status (MANDATORY: return 0 -> no Error).
9903 *
9904 */
lsm6dsr_long_clr_get(stmdev_ctx_t * ctx,lsm6dsr_fsm_lc_clr_t * val)9905 int32_t lsm6dsr_long_clr_get(stmdev_ctx_t *ctx,
9906 lsm6dsr_fsm_lc_clr_t *val)
9907 {
9908 lsm6dsr_fsm_long_counter_clear_t fsm_long_counter_clear;
9909 int32_t ret;
9910
9911 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9912
9913 if (ret == 0)
9914 {
9915 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_LONG_COUNTER_CLEAR,
9916 (uint8_t *)&fsm_long_counter_clear, 1);
9917 }
9918
9919 if (ret == 0)
9920 {
9921 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
9922 }
9923
9924 switch (fsm_long_counter_clear.fsm_lc_clr)
9925 {
9926 case LSM6DSR_LC_NORMAL:
9927 *val = LSM6DSR_LC_NORMAL;
9928 break;
9929
9930 case LSM6DSR_LC_CLEAR:
9931 *val = LSM6DSR_LC_CLEAR;
9932 break;
9933
9934 case LSM6DSR_LC_CLEAR_DONE:
9935 *val = LSM6DSR_LC_CLEAR_DONE;
9936 break;
9937
9938 default:
9939 *val = LSM6DSR_LC_NORMAL;
9940 break;
9941 }
9942
9943 return ret;
9944 }
9945
9946 /**
9947 * @brief FSM output registers.[get]
9948 *
9949 * @param ctx Read / write interface definitions.(ptr)
9950 * @param val Structure of registers from FSM_OUTS1 to FSM_OUTS16
9951 * @retval Interface status (MANDATORY: return 0 -> no Error).
9952 *
9953 */
lsm6dsr_fsm_out_get(stmdev_ctx_t * ctx,lsm6dsr_fsm_out_t * val)9954 int32_t lsm6dsr_fsm_out_get(stmdev_ctx_t *ctx, lsm6dsr_fsm_out_t *val)
9955 {
9956 int32_t ret;
9957
9958 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9959
9960 if (ret == 0)
9961 {
9962 ret = lsm6dsr_read_reg(ctx, LSM6DSR_FSM_OUTS1,
9963 (uint8_t *)&val->fsm_outs1, 16);
9964 }
9965
9966 if (ret == 0)
9967 {
9968 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
9969 }
9970
9971 return ret;
9972 }
9973
9974 /**
9975 * @brief Finite State Machine ODR configuration.[set]
9976 *
9977 * @param ctx Read / write interface definitions.(ptr)
9978 * @param val Change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
9979 * @retval Interface status (MANDATORY: return 0 -> no Error).
9980 *
9981 */
lsm6dsr_fsm_data_rate_set(stmdev_ctx_t * ctx,lsm6dsr_fsm_odr_t val)9982 int32_t lsm6dsr_fsm_data_rate_set(stmdev_ctx_t *ctx,
9983 lsm6dsr_fsm_odr_t val)
9984 {
9985 lsm6dsr_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
9986 int32_t ret;
9987
9988 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
9989
9990 if (ret == 0)
9991 {
9992 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_ODR_CFG_B,
9993 (uint8_t *)&emb_func_odr_cfg_b, 1);
9994 }
9995
9996 if (ret == 0)
9997 {
9998 emb_func_odr_cfg_b.not_used_01 = 3; /* set default values */
9999 emb_func_odr_cfg_b.not_used_02 = 1; /* set default values */
10000 emb_func_odr_cfg_b.fsm_odr = (uint8_t)val;
10001 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_ODR_CFG_B,
10002 (uint8_t *)&emb_func_odr_cfg_b, 1);
10003 }
10004
10005 if (ret == 0)
10006 {
10007 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10008 }
10009
10010 return ret;
10011 }
10012
10013 /**
10014 * @brief Finite State Machine ODR configuration.[get]
10015 *
10016 * @param ctx Read / write interface definitions.(ptr)
10017 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
10018 * @retval Interface status (MANDATORY: return 0 -> no Error).
10019 *
10020 */
lsm6dsr_fsm_data_rate_get(stmdev_ctx_t * ctx,lsm6dsr_fsm_odr_t * val)10021 int32_t lsm6dsr_fsm_data_rate_get(stmdev_ctx_t *ctx,
10022 lsm6dsr_fsm_odr_t *val)
10023 {
10024 lsm6dsr_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
10025 int32_t ret;
10026
10027 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
10028
10029 if (ret == 0)
10030 {
10031 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_ODR_CFG_B,
10032 (uint8_t *)&emb_func_odr_cfg_b, 1);
10033 }
10034
10035 if (ret == 0)
10036 {
10037 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10038 }
10039
10040 switch (emb_func_odr_cfg_b.fsm_odr)
10041 {
10042 case LSM6DSR_ODR_FSM_12Hz5:
10043 *val = LSM6DSR_ODR_FSM_12Hz5;
10044 break;
10045
10046 case LSM6DSR_ODR_FSM_26Hz:
10047 *val = LSM6DSR_ODR_FSM_26Hz;
10048 break;
10049
10050 case LSM6DSR_ODR_FSM_52Hz:
10051 *val = LSM6DSR_ODR_FSM_52Hz;
10052 break;
10053
10054 case LSM6DSR_ODR_FSM_104Hz:
10055 *val = LSM6DSR_ODR_FSM_104Hz;
10056 break;
10057
10058 default:
10059 *val = LSM6DSR_ODR_FSM_12Hz5;
10060 break;
10061 }
10062
10063 return ret;
10064 }
10065
10066 /**
10067 * @brief FSM initialization request.[set]
10068 *
10069 * @param ctx Read / write interface definitions.(ptr)
10070 * @param val Change the values of fsm_init in reg FSM_INIT
10071 * @retval Interface status (MANDATORY: return 0 -> no Error).
10072 *
10073 */
lsm6dsr_fsm_init_set(stmdev_ctx_t * ctx,uint8_t val)10074 int32_t lsm6dsr_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
10075 {
10076 lsm6dsr_emb_func_init_b_t emb_func_init_b;
10077 int32_t ret;
10078
10079 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
10080
10081 if (ret == 0)
10082 {
10083 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_INIT_B,
10084 (uint8_t *)&emb_func_init_b, 1);
10085 }
10086
10087 if (ret == 0)
10088 {
10089 emb_func_init_b.fsm_init = (uint8_t)val;
10090 ret = lsm6dsr_write_reg(ctx, LSM6DSR_EMB_FUNC_INIT_B,
10091 (uint8_t *)&emb_func_init_b, 1);
10092 }
10093
10094 if (ret == 0)
10095 {
10096 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10097 }
10098
10099 return ret;
10100 }
10101
10102 /**
10103 * @brief FSM initialization request.[get]
10104 *
10105 * @param ctx Read / write interface definitions.(ptr)
10106 * @param val Change the values of fsm_init in reg FSM_INIT
10107 * @retval Interface status (MANDATORY: return 0 -> no Error).
10108 *
10109 */
lsm6dsr_fsm_init_get(stmdev_ctx_t * ctx,uint8_t * val)10110 int32_t lsm6dsr_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
10111 {
10112 lsm6dsr_emb_func_init_b_t emb_func_init_b;
10113 int32_t ret;
10114
10115 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_EMBEDDED_FUNC_BANK);
10116
10117 if (ret == 0)
10118 {
10119 ret = lsm6dsr_read_reg(ctx, LSM6DSR_EMB_FUNC_INIT_B,
10120 (uint8_t *)&emb_func_init_b, 1);
10121 }
10122
10123 if (ret == 0)
10124 {
10125 *val = emb_func_init_b.fsm_init;
10126 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10127 }
10128
10129 return ret;
10130 }
10131
10132 /**
10133 * @brief FSM long counter timeout register (r/w). The long counter
10134 * timeout value is an unsigned integer value (16-bit format).
10135 * When the long counter value reached this value, the FSM
10136 * generates an interrupt.[set]
10137 *
10138 * @param ctx Read / write interface definitions.(ptr)
10139 * @param buff Buffer that contains data to write
10140 * @retval Interface status (MANDATORY: return 0 -> no Error).
10141 *
10142 */
lsm6dsr_long_cnt_int_value_set(stmdev_ctx_t * ctx,uint16_t val)10143 int32_t lsm6dsr_long_cnt_int_value_set(stmdev_ctx_t *ctx,
10144 uint16_t val)
10145 {
10146 uint8_t buff[2];
10147 int32_t ret;
10148
10149 buff[1] = (uint8_t)(val / 256U);
10150 buff[0] = (uint8_t)(val - (buff[1] * 256U));
10151 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_LC_TIMEOUT_L,
10152 &buff[0]);
10153
10154 if (ret == 0)
10155 {
10156 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_LC_TIMEOUT_H,
10157 &buff[1]);
10158 }
10159
10160 return ret;
10161 }
10162
10163 /**
10164 * @brief FSM long counter timeout register (r/w). The long counter
10165 * timeout value is an unsigned integer value (16-bit format).
10166 * When the long counter value reached this value, the FSM generates
10167 * an interrupt.[get]
10168 *
10169 * @param ctx Read / write interface definitions.(ptr)
10170 * @param buff Buffer that stores data read
10171 * @retval Interface status (MANDATORY: return 0 -> no Error).
10172 *
10173 */
lsm6dsr_long_cnt_int_value_get(stmdev_ctx_t * ctx,uint16_t * val)10174 int32_t lsm6dsr_long_cnt_int_value_get(stmdev_ctx_t *ctx,
10175 uint16_t *val)
10176 {
10177 uint8_t buff[2];
10178 int32_t ret;
10179
10180 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_FSM_LC_TIMEOUT_L,
10181 &buff[0]);
10182
10183 if (ret == 0)
10184 {
10185 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_FSM_LC_TIMEOUT_H,
10186 &buff[1]);
10187 *val = buff[1];
10188 *val = (*val * 256U) + buff[0];
10189 }
10190
10191 return ret;
10192 }
10193
10194 /**
10195 * @brief FSM number of programs register.[set]
10196 *
10197 * @param ctx Read / write interface definitions.(ptr)
10198 * @param buff Buffer that contains data to write
10199 * @retval Interface status (MANDATORY: return 0 -> no Error).
10200 *
10201 */
lsm6dsr_fsm_number_of_programs_set(stmdev_ctx_t * ctx,uint8_t * buff)10202 int32_t lsm6dsr_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
10203 uint8_t *buff)
10204 {
10205 int32_t ret;
10206
10207 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_PROGRAMS, buff);
10208
10209 if (ret == 0)
10210 {
10211 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_PROGRAMS + 0x01U,
10212 buff);
10213 }
10214
10215 return ret;
10216 }
10217
10218 /**
10219 * @brief FSM number of programs register.[get]
10220 *
10221 * @param ctx Read / write interface definitions.(ptr)
10222 * @param buff Buffer that stores data read
10223 * @retval Interface status (MANDATORY: return 0 -> no Error).
10224 *
10225 */
lsm6dsr_fsm_number_of_programs_get(stmdev_ctx_t * ctx,uint8_t * buff)10226 int32_t lsm6dsr_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
10227 uint8_t *buff)
10228 {
10229 int32_t ret;
10230
10231 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_FSM_PROGRAMS, buff);
10232
10233 return ret;
10234 }
10235
10236 /**
10237 * @brief FSM start address register (r/w). First available address is
10238 * 0x033C.[set]
10239 *
10240 * @param ctx Read / write interface definitions.(ptr)
10241 * @param buff Buffer that contains data to write
10242 * @retval Interface status (MANDATORY: return 0 -> no Error).
10243 *
10244 */
lsm6dsr_fsm_start_address_set(stmdev_ctx_t * ctx,uint16_t val)10245 int32_t lsm6dsr_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val)
10246 {
10247 uint8_t buff[2];
10248 int32_t ret;
10249
10250 buff[1] = (uint8_t)(val / 256U);
10251 buff[0] = (uint8_t)(val - (buff[1] * 256U));
10252 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_START_ADD_L,
10253 &buff[0]);
10254
10255 if (ret == 0)
10256 {
10257 ret = lsm6dsr_ln_pg_write_byte(ctx, LSM6DSR_FSM_START_ADD_H,
10258 &buff[1]);
10259 }
10260
10261 return ret;
10262 }
10263
10264 /**
10265 * @brief FSM start address register (r/w). First available address
10266 * is 0x033C.[get]
10267 *
10268 * @param ctx Read / write interface definitions.(ptr)
10269 * @param buff Buffer that stores data read
10270 * @retval Interface status (MANDATORY: return 0 -> no Error).
10271 *
10272 */
lsm6dsr_fsm_start_address_get(stmdev_ctx_t * ctx,uint16_t * val)10273 int32_t lsm6dsr_fsm_start_address_get(stmdev_ctx_t *ctx,
10274 uint16_t *val)
10275 {
10276 uint8_t buff[2];
10277 int32_t ret;
10278
10279 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_FSM_START_ADD_L, &buff[0]);
10280
10281 if (ret == 0)
10282 {
10283 ret = lsm6dsr_ln_pg_read_byte(ctx, LSM6DSR_FSM_START_ADD_H, &buff[1]);
10284 *val = buff[1];
10285 *val = (*val * 256U) + buff[0];
10286 }
10287
10288 return ret;
10289 }
10290
10291 /**
10292 * @}
10293 *
10294 */
10295
10296 /**
10297 * @defgroup LSM6DSR_Sensor_hub
10298 * @brief This section groups all the functions that manage the
10299 * sensor hub.
10300 * @{
10301 *
10302 */
10303
10304 /**
10305 * @brief Sensor hub output registers.[get]
10306 *
10307 * @param ctx Read / write interface definitions.(ptr)
10308 * @param val Structure of registers from SENSOR_HUB_1 to SENSOR_HUB_18
10309 * @retval Interface status (MANDATORY: return 0 -> no Error).
10310 *
10311 */
lsm6dsr_sh_read_data_raw_get(stmdev_ctx_t * ctx,lsm6dsr_emb_sh_read_t * val)10312 int32_t lsm6dsr_sh_read_data_raw_get(stmdev_ctx_t *ctx,
10313 lsm6dsr_emb_sh_read_t *val)
10314 {
10315 int32_t ret;
10316
10317 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10318
10319 if (ret == 0)
10320 {
10321 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SENSOR_HUB_1, (uint8_t *)val, 18);
10322 }
10323
10324 if (ret == 0)
10325 {
10326 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10327 }
10328
10329 return ret;
10330 }
10331
10332 /**
10333 * @brief Number of external sensors to be read by the sensor hub.[set]
10334 *
10335 * @param ctx Read / write interface definitions.(ptr)
10336 * @param val Change the values of aux_sens_on in reg MASTER_CONFIG
10337 * @retval Interface status (MANDATORY: return 0 -> no Error).
10338 *
10339 */
lsm6dsr_sh_slave_connected_set(stmdev_ctx_t * ctx,lsm6dsr_aux_sens_on_t val)10340 int32_t lsm6dsr_sh_slave_connected_set(stmdev_ctx_t *ctx,
10341 lsm6dsr_aux_sens_on_t val)
10342 {
10343 lsm6dsr_master_config_t master_config;
10344 int32_t ret;
10345
10346 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10347
10348 if (ret == 0)
10349 {
10350 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10351 (uint8_t *)&master_config, 1);
10352 }
10353
10354 if (ret == 0)
10355 {
10356 master_config.aux_sens_on = (uint8_t)val;
10357 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
10358 (uint8_t *)&master_config, 1);
10359 }
10360
10361 if (ret == 0)
10362 {
10363 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10364 }
10365
10366 return ret;
10367 }
10368
10369 /**
10370 * @brief Number of external sensors to be read by the sensor hub.[get]
10371 *
10372 * @param ctx Read / write interface definitions.(ptr)
10373 * @param val Get the values of aux_sens_on in reg MASTER_CONFIG
10374 * @retval Interface status (MANDATORY: return 0 -> no Error).
10375 *
10376 */
lsm6dsr_sh_slave_connected_get(stmdev_ctx_t * ctx,lsm6dsr_aux_sens_on_t * val)10377 int32_t lsm6dsr_sh_slave_connected_get(stmdev_ctx_t *ctx,
10378 lsm6dsr_aux_sens_on_t *val)
10379 {
10380 lsm6dsr_master_config_t master_config;
10381 int32_t ret;
10382
10383 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10384
10385 if (ret == 0)
10386 {
10387 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10388 (uint8_t *)&master_config, 1);
10389 }
10390
10391 if (ret == 0)
10392 {
10393 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10394 }
10395
10396 switch (master_config.aux_sens_on)
10397 {
10398 case LSM6DSR_SLV_0:
10399 *val = LSM6DSR_SLV_0;
10400 break;
10401
10402 case LSM6DSR_SLV_0_1:
10403 *val = LSM6DSR_SLV_0_1;
10404 break;
10405
10406 case LSM6DSR_SLV_0_1_2:
10407 *val = LSM6DSR_SLV_0_1_2;
10408 break;
10409
10410 case LSM6DSR_SLV_0_1_2_3:
10411 *val = LSM6DSR_SLV_0_1_2_3;
10412 break;
10413
10414 default:
10415 *val = LSM6DSR_SLV_0;
10416 break;
10417 }
10418
10419 return ret;
10420 }
10421
10422 /**
10423 * @brief Sensor hub I2C master enable.[set]
10424 *
10425 * @param ctx Read / write interface definitions.(ptr)
10426 * @param val Change the values of master_on in reg MASTER_CONFIG
10427 * @retval Interface status (MANDATORY: return 0 -> no Error).
10428 *
10429 */
lsm6dsr_sh_master_set(stmdev_ctx_t * ctx,uint8_t val)10430 int32_t lsm6dsr_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
10431 {
10432 lsm6dsr_master_config_t master_config;
10433 int32_t ret;
10434
10435 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10436
10437 if (ret == 0)
10438 {
10439 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10440 (uint8_t *)&master_config, 1);
10441 }
10442
10443 if (ret == 0)
10444 {
10445 master_config.master_on = (uint8_t)val;
10446 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
10447 (uint8_t *)&master_config, 1);
10448 }
10449
10450 if (ret == 0)
10451 {
10452 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10453 }
10454
10455 return ret;
10456 }
10457
10458 /**
10459 * @brief Sensor hub I2C master enable.[get]
10460 *
10461 * @param ctx Read / write interface definitions.(ptr)
10462 * @param val Change the values of master_on in reg MASTER_CONFIG
10463 * @retval Interface status (MANDATORY: return 0 -> no Error).
10464 *
10465 */
lsm6dsr_sh_master_get(stmdev_ctx_t * ctx,uint8_t * val)10466 int32_t lsm6dsr_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
10467 {
10468 lsm6dsr_master_config_t master_config;
10469 int32_t ret;
10470
10471 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10472
10473 if (ret == 0)
10474 {
10475 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10476 (uint8_t *)&master_config, 1);
10477 }
10478
10479 if (ret == 0)
10480 {
10481 *val = master_config.master_on;
10482 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10483 }
10484
10485 return ret;
10486 }
10487
10488 /**
10489 * @brief Master I2C pull-up enable.[set]
10490 *
10491 * @param ctx Read / write interface definitions.(ptr)
10492 * @param val Change the values of shub_pu_en in reg MASTER_CONFIG
10493 * @retval Interface status (MANDATORY: return 0 -> no Error).
10494 *
10495 */
lsm6dsr_sh_pin_mode_set(stmdev_ctx_t * ctx,lsm6dsr_shub_pu_en_t val)10496 int32_t lsm6dsr_sh_pin_mode_set(stmdev_ctx_t *ctx,
10497 lsm6dsr_shub_pu_en_t val)
10498 {
10499 lsm6dsr_master_config_t master_config;
10500 int32_t ret;
10501
10502 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10503
10504 if (ret == 0)
10505 {
10506 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10507 (uint8_t *)&master_config, 1);
10508 }
10509
10510 if (ret == 0)
10511 {
10512 master_config.shub_pu_en = (uint8_t)val;
10513 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
10514 (uint8_t *)&master_config, 1);
10515 }
10516
10517 if (ret == 0)
10518 {
10519 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10520 }
10521
10522 return ret;
10523 }
10524
10525 /**
10526 * @brief Master I2C pull-up enable.[get]
10527 *
10528 * @param ctx Read / write interface definitions.(ptr)
10529 * @param val Get the values of shub_pu_en in reg MASTER_CONFIG
10530 * @retval Interface status (MANDATORY: return 0 -> no Error).
10531 *
10532 */
lsm6dsr_sh_pin_mode_get(stmdev_ctx_t * ctx,lsm6dsr_shub_pu_en_t * val)10533 int32_t lsm6dsr_sh_pin_mode_get(stmdev_ctx_t *ctx,
10534 lsm6dsr_shub_pu_en_t *val)
10535 {
10536 lsm6dsr_master_config_t master_config;
10537 int32_t ret;
10538
10539 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10540
10541 if (ret == 0)
10542 {
10543 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10544 (uint8_t *)&master_config, 1);
10545 }
10546
10547 if (ret == 0)
10548 {
10549 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10550 }
10551
10552 switch (master_config.shub_pu_en)
10553 {
10554 case LSM6DSR_EXT_PULL_UP:
10555 *val = LSM6DSR_EXT_PULL_UP;
10556 break;
10557
10558 case LSM6DSR_INTERNAL_PULL_UP:
10559 *val = LSM6DSR_INTERNAL_PULL_UP;
10560 break;
10561
10562 default:
10563 *val = LSM6DSR_EXT_PULL_UP;
10564 break;
10565 }
10566
10567 return ret;
10568 }
10569
10570 /**
10571 * @brief I2C interface pass-through.[set]
10572 *
10573 * @param ctx Read / write interface definitions.(ptr)
10574 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
10575 * @retval Interface status (MANDATORY: return 0 -> no Error).
10576 *
10577 */
lsm6dsr_sh_pass_through_set(stmdev_ctx_t * ctx,uint8_t val)10578 int32_t lsm6dsr_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
10579 {
10580 lsm6dsr_master_config_t master_config;
10581 int32_t ret;
10582
10583 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10584
10585 if (ret == 0)
10586 {
10587 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10588 (uint8_t *)&master_config, 1);
10589 }
10590
10591 if (ret == 0)
10592 {
10593 master_config.pass_through_mode = (uint8_t)val;
10594 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
10595 (uint8_t *)&master_config, 1);
10596 }
10597
10598 if (ret == 0)
10599 {
10600 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10601 }
10602
10603 return ret;
10604 }
10605
10606 /**
10607 * @brief I2C interface pass-through.[get]
10608 *
10609 * @param ctx Read / write interface definitions.(ptr)
10610 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
10611 * @retval Interface status (MANDATORY: return 0 -> no Error).
10612 *
10613 */
lsm6dsr_sh_pass_through_get(stmdev_ctx_t * ctx,uint8_t * val)10614 int32_t lsm6dsr_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
10615 {
10616 lsm6dsr_master_config_t master_config;
10617 int32_t ret;
10618
10619 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10620
10621 if (ret == 0)
10622 {
10623 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10624 (uint8_t *)&master_config, 1);
10625 }
10626
10627 if (ret == 0)
10628 {
10629 *val = master_config.pass_through_mode;
10630 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10631 }
10632
10633 return ret;
10634 }
10635
10636 /**
10637 * @brief Sensor hub trigger signal selection.[set]
10638 *
10639 * @param ctx Read / write interface definitions.(ptr)
10640 * @param val Change the values of start_config in reg MASTER_CONFIG
10641 * @retval Interface status (MANDATORY: return 0 -> no Error).
10642 *
10643 */
lsm6dsr_sh_syncro_mode_set(stmdev_ctx_t * ctx,lsm6dsr_start_config_t val)10644 int32_t lsm6dsr_sh_syncro_mode_set(stmdev_ctx_t *ctx,
10645 lsm6dsr_start_config_t val)
10646 {
10647 lsm6dsr_master_config_t master_config;
10648 int32_t ret;
10649
10650 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10651
10652 if (ret == 0)
10653 {
10654 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10655 (uint8_t *)&master_config, 1);
10656 }
10657
10658 if (ret == 0)
10659 {
10660 master_config.start_config = (uint8_t)val;
10661 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
10662 (uint8_t *)&master_config, 1);
10663 }
10664
10665 if (ret == 0)
10666 {
10667 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10668 }
10669
10670 return ret;
10671 }
10672
10673 /**
10674 * @brief Sensor hub trigger signal selection.[get]
10675 *
10676 * @param ctx Read / write interface definitions.(ptr)
10677 * @param val Get the values of start_config in reg MASTER_CONFIG
10678 * @retval Interface status (MANDATORY: return 0 -> no Error).
10679 *
10680 */
lsm6dsr_sh_syncro_mode_get(stmdev_ctx_t * ctx,lsm6dsr_start_config_t * val)10681 int32_t lsm6dsr_sh_syncro_mode_get(stmdev_ctx_t *ctx,
10682 lsm6dsr_start_config_t *val)
10683 {
10684 lsm6dsr_master_config_t master_config;
10685 int32_t ret;
10686
10687 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10688
10689 if (ret == 0)
10690 {
10691 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10692 (uint8_t *)&master_config, 1);
10693 }
10694
10695 if (ret == 0)
10696 {
10697 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10698 }
10699
10700 switch (master_config.start_config)
10701 {
10702 case LSM6DSR_EXT_ON_INT2_PIN:
10703 *val = LSM6DSR_EXT_ON_INT2_PIN;
10704 break;
10705
10706 case LSM6DSR_XL_GY_DRDY:
10707 *val = LSM6DSR_XL_GY_DRDY;
10708 break;
10709
10710 default:
10711 *val = LSM6DSR_EXT_ON_INT2_PIN;
10712 break;
10713 }
10714
10715 return ret;
10716 }
10717
10718 /**
10719 * @brief Slave 0 write operation is performed only at the first sensor
10720 * hub cycle.[set]
10721 *
10722 * @param ctx Read / write interface definitions.(ptr)
10723 * @param val Change the values of write_once in reg MASTER_CONFIG
10724 * @retval Interface status (MANDATORY: return 0 -> no Error).
10725 *
10726 */
lsm6dsr_sh_write_mode_set(stmdev_ctx_t * ctx,lsm6dsr_write_once_t val)10727 int32_t lsm6dsr_sh_write_mode_set(stmdev_ctx_t *ctx,
10728 lsm6dsr_write_once_t val)
10729 {
10730 lsm6dsr_master_config_t master_config;
10731 int32_t ret;
10732
10733 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10734
10735 if (ret == 0)
10736 {
10737 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10738 (uint8_t *)&master_config, 1);
10739 }
10740
10741 if (ret == 0)
10742 {
10743 master_config.write_once = (uint8_t)val;
10744 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
10745 (uint8_t *)&master_config, 1);
10746 }
10747
10748 if (ret == 0)
10749 {
10750 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10751 }
10752
10753 return ret;
10754 }
10755
10756 /**
10757 * @brief Slave 0 write operation is performed only at the first sensor
10758 * hub cycle.[get]
10759 *
10760 * @param ctx Read / write interface definitions.(ptr)
10761 * @param val Get the values of write_once in reg MASTER_CONFIG
10762 * @retval Interface status (MANDATORY: return 0 -> no Error).
10763 *
10764 */
lsm6dsr_sh_write_mode_get(stmdev_ctx_t * ctx,lsm6dsr_write_once_t * val)10765 int32_t lsm6dsr_sh_write_mode_get(stmdev_ctx_t *ctx,
10766 lsm6dsr_write_once_t *val)
10767 {
10768 lsm6dsr_master_config_t master_config;
10769 int32_t ret;
10770
10771 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10772
10773 if (ret == 0)
10774 {
10775 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10776 (uint8_t *)&master_config, 1);
10777 }
10778
10779 if (ret == 0)
10780 {
10781 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10782 }
10783
10784 switch (master_config.write_once)
10785 {
10786 case LSM6DSR_EACH_SH_CYCLE:
10787 *val = LSM6DSR_EACH_SH_CYCLE;
10788 break;
10789
10790 case LSM6DSR_ONLY_FIRST_CYCLE:
10791 *val = LSM6DSR_ONLY_FIRST_CYCLE;
10792 break;
10793
10794 default:
10795 *val = LSM6DSR_EACH_SH_CYCLE;
10796 break;
10797 }
10798
10799 return ret;
10800 }
10801
10802 /**
10803 * @brief Reset Master logic and output registers.[set]
10804 *
10805 * @param ctx Read / write interface definitions.(ptr)
10806 * @retval Interface status (MANDATORY: return 0 -> no Error).
10807 *
10808 */
lsm6dsr_sh_reset_set(stmdev_ctx_t * ctx)10809 int32_t lsm6dsr_sh_reset_set(stmdev_ctx_t *ctx)
10810 {
10811 lsm6dsr_master_config_t master_config;
10812 int32_t ret;
10813
10814 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10815
10816 if (ret == 0)
10817 {
10818 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10819 (uint8_t *)&master_config, 1);
10820 }
10821
10822 if (ret == 0)
10823 {
10824 master_config.rst_master_regs = PROPERTY_ENABLE;
10825 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
10826 (uint8_t *)&master_config, 1);
10827 }
10828
10829 if (ret == 0)
10830 {
10831 master_config.rst_master_regs = PROPERTY_DISABLE;
10832 ret = lsm6dsr_write_reg(ctx, LSM6DSR_MASTER_CONFIG,
10833 (uint8_t *)&master_config, 1);
10834 }
10835
10836 if (ret == 0)
10837 {
10838 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10839 }
10840
10841 return ret;
10842 }
10843
10844 /**
10845 * @brief Reset Master logic and output registers.[get]
10846 *
10847 * @param ctx Read / write interface definitions.(ptr)
10848 * @param val Change the values of rst_master_regs in reg MASTER_CONFIG
10849 * @retval Interface status (MANDATORY: return 0 -> no Error).
10850 *
10851 */
lsm6dsr_sh_reset_get(stmdev_ctx_t * ctx,uint8_t * val)10852 int32_t lsm6dsr_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
10853 {
10854 lsm6dsr_master_config_t master_config;
10855 int32_t ret;
10856
10857 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10858
10859 if (ret == 0)
10860 {
10861 ret = lsm6dsr_read_reg(ctx, LSM6DSR_MASTER_CONFIG,
10862 (uint8_t *)&master_config, 1);
10863 *val = master_config.rst_master_regs;
10864 }
10865
10866 if (ret == 0)
10867 {
10868 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10869 }
10870
10871 return ret;
10872 }
10873
10874 /**
10875 * @brief Rate at which the master communicates.[set]
10876 *
10877 * @param ctx Read / write interface definitions.(ptr)
10878 * @param val Change the values of shub_odr in reg SLV0_CONFIG
10879 * @retval Interface status (MANDATORY: return 0 -> no Error).
10880 *
10881 */
lsm6dsr_sh_data_rate_set(stmdev_ctx_t * ctx,lsm6dsr_shub_odr_t val)10882 int32_t lsm6dsr_sh_data_rate_set(stmdev_ctx_t *ctx,
10883 lsm6dsr_shub_odr_t val)
10884 {
10885 lsm6dsr_slv0_config_t slv0_config;
10886 int32_t ret;
10887
10888 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10889
10890 if (ret == 0)
10891 {
10892 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV0_CONFIG,
10893 (uint8_t *)&slv0_config, 1);
10894 }
10895
10896 if (ret == 0)
10897 {
10898 slv0_config.shub_odr = (uint8_t)val;
10899 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_CONFIG,
10900 (uint8_t *)&slv0_config, 1);
10901 }
10902
10903 if (ret == 0)
10904 {
10905 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10906 }
10907
10908 return ret;
10909 }
10910
10911 /**
10912 * @brief Rate at which the master communicates.[get]
10913 *
10914 * @param ctx Read / write interface definitions.(ptr)
10915 * @param val Get the values of shub_odr in reg slv1_CONFIG
10916 * @retval Interface status (MANDATORY: return 0 -> no Error).
10917 *
10918 */
lsm6dsr_sh_data_rate_get(stmdev_ctx_t * ctx,lsm6dsr_shub_odr_t * val)10919 int32_t lsm6dsr_sh_data_rate_get(stmdev_ctx_t *ctx,
10920 lsm6dsr_shub_odr_t *val)
10921 {
10922 lsm6dsr_slv0_config_t slv0_config;
10923 int32_t ret;
10924
10925 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10926
10927 if (ret == 0)
10928 {
10929 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV0_CONFIG,
10930 (uint8_t *)&slv0_config, 1);
10931 }
10932
10933 if (ret == 0)
10934 {
10935 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
10936 }
10937
10938 switch (slv0_config.shub_odr)
10939 {
10940 case LSM6DSR_SH_ODR_104Hz:
10941 *val = LSM6DSR_SH_ODR_104Hz;
10942 break;
10943
10944 case LSM6DSR_SH_ODR_52Hz:
10945 *val = LSM6DSR_SH_ODR_52Hz;
10946 break;
10947
10948 case LSM6DSR_SH_ODR_26Hz:
10949 *val = LSM6DSR_SH_ODR_26Hz;
10950 break;
10951
10952 case LSM6DSR_SH_ODR_13Hz:
10953 *val = LSM6DSR_SH_ODR_13Hz;
10954 break;
10955
10956 default:
10957 *val = LSM6DSR_SH_ODR_104Hz;
10958 break;
10959 }
10960
10961 return ret;
10962 }
10963
10964 /**
10965 * @brief Configure slave 0 for perform a write.[set]
10966 *
10967 * @param ctx Read / write interface definitions.(ptr)
10968 * @param val Structure that contain
10969 * - uint8_t slv0_add; 8 bit i2c device address
10970 * - uint8_t slv0_subadd; 8 bit register device address
10971 * - uint8_t slv0_data; 8 bit data to write
10972 * @retval Interface status (MANDATORY: return 0 -> no Error).
10973 *
10974 */
lsm6dsr_sh_cfg_write(stmdev_ctx_t * ctx,lsm6dsr_sh_cfg_write_t * val)10975 int32_t lsm6dsr_sh_cfg_write(stmdev_ctx_t *ctx,
10976 lsm6dsr_sh_cfg_write_t *val)
10977 {
10978 lsm6dsr_slv0_add_t slv0_add;
10979 int32_t ret;
10980
10981 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
10982
10983 if (ret == 0)
10984 {
10985 slv0_add.slave0 = (uint8_t)(val->slv0_add >> 1);
10986 slv0_add.rw_0 = 0;
10987 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_ADD,
10988 (uint8_t *) & (slv0_add), 1);
10989 }
10990
10991 if (ret == 0)
10992 {
10993 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_SUBADD,
10994 (uint8_t *) & (val->slv0_subadd), 1);
10995 }
10996
10997 if (ret == 0)
10998 {
10999 ret = lsm6dsr_write_reg(ctx, LSM6DSR_DATAWRITE_SLV0,
11000 (uint8_t *) & (val->slv0_data), 1);
11001 }
11002
11003 if (ret == 0)
11004 {
11005 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
11006 }
11007
11008 return ret;
11009 }
11010
11011 /**
11012 * @brief Configure slave 0 for perform a write/read.[get]
11013 *
11014 * @param ctx Read / write interface definitions.(ptr)
11015 * @param val Structure that contain
11016 * - uint8_t slv_add; 8 bit i2c device address
11017 * - uint8_t slv_subadd; 8 bit register device address
11018 * - uint8_t slv_len; num of bit to read
11019 * @retval Interface status (MANDATORY: return 0 -> no Error).
11020 *
11021 */
lsm6dsr_sh_slv0_cfg_read(stmdev_ctx_t * ctx,lsm6dsr_sh_cfg_read_t * val)11022 int32_t lsm6dsr_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
11023 lsm6dsr_sh_cfg_read_t *val)
11024 {
11025 lsm6dsr_slv0_config_t slv0_config;
11026 lsm6dsr_slv0_add_t slv0_add;
11027 int32_t ret;
11028
11029 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
11030
11031 if (ret == 0)
11032 {
11033 slv0_add.slave0 = (uint8_t) val->slv_add >> 1;
11034 slv0_add.rw_0 = 1;
11035 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_ADD,
11036 (uint8_t *) & (slv0_add), 1);
11037 }
11038
11039 if (ret == 0)
11040 {
11041 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_SUBADD,
11042 &(val->slv_subadd), 1);
11043 }
11044
11045 if (ret == 0)
11046 {
11047 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV0_CONFIG,
11048 (uint8_t *)&slv0_config, 1);
11049 }
11050
11051 if (ret == 0)
11052 {
11053 slv0_config.slave0_numop = val->slv_len;
11054 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV0_CONFIG,
11055 (uint8_t *)&slv0_config, 1);
11056 }
11057
11058 if (ret == 0)
11059 {
11060 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
11061 }
11062
11063 return ret;
11064 }
11065
11066 /**
11067 * @brief Configure slave 0 for perform a write/read.[get]
11068 *
11069 * @param ctx Read / write interface definitions.(ptr)
11070 * @param val Structure that contain
11071 * - uint8_t slv_add; 8 bit i2c device address
11072 * - uint8_t slv_subadd; 8 bit register device address
11073 * - uint8_t slv_len; num of bit to read
11074 * @retval Interface status (MANDATORY: return 0 -> no Error).
11075 *
11076 */
lsm6dsr_sh_slv1_cfg_read(stmdev_ctx_t * ctx,lsm6dsr_sh_cfg_read_t * val)11077 int32_t lsm6dsr_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
11078 lsm6dsr_sh_cfg_read_t *val)
11079 {
11080 lsm6dsr_slv1_config_t slv1_config;
11081 lsm6dsr_slv1_add_t slv1_add;
11082 int32_t ret;
11083
11084 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
11085
11086 if (ret == 0)
11087 {
11088 slv1_add.slave1_add = (uint8_t)(val->slv_add >> 1);
11089 slv1_add.r_1 = 1;
11090 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV1_ADD, (uint8_t *)&slv1_add, 1);
11091 }
11092
11093 if (ret == 0)
11094 {
11095 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV1_SUBADD,
11096 &(val->slv_subadd), 1);
11097 }
11098
11099 if (ret == 0)
11100 {
11101 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV1_CONFIG,
11102 (uint8_t *)&slv1_config, 1);
11103 }
11104
11105 if (ret == 0)
11106 {
11107 slv1_config.slave1_numop = val->slv_len;
11108 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV1_CONFIG,
11109 (uint8_t *)&slv1_config, 1);
11110 }
11111
11112 if (ret == 0)
11113 {
11114 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
11115 }
11116
11117 return ret;
11118 }
11119
11120 /**
11121 * @brief Configure slave 2 for perform a write/read.[get]
11122 *
11123 * @param ctx Read / write interface definitions.(ptr)
11124 * @param val Structure that contain
11125 * - uint8_t slv_add; 8 bit i2c device address
11126 * - uint8_t slv_subadd; 8 bit register device address
11127 * - uint8_t slv_len; num of bit to read
11128 * @retval Interface status (MANDATORY: return 0 -> no Error).
11129 *
11130 */
lsm6dsr_sh_slv2_cfg_read(stmdev_ctx_t * ctx,lsm6dsr_sh_cfg_read_t * val)11131 int32_t lsm6dsr_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
11132 lsm6dsr_sh_cfg_read_t *val)
11133 {
11134 lsm6dsr_slv2_config_t slv2_config;
11135 lsm6dsr_slv2_add_t slv2_add;
11136 int32_t ret;
11137
11138 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
11139
11140 if (ret == 0)
11141 {
11142 slv2_add.slave2_add = (uint8_t)(val->slv_add >> 1);
11143 slv2_add.r_2 = 1;
11144 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV2_ADD,
11145 (uint8_t *)&slv2_add, 1);
11146 }
11147
11148 if (ret == 0)
11149 {
11150 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV2_SUBADD,
11151 (uint8_t *) & (val->slv_subadd), 1);
11152 }
11153
11154 if (ret == 0)
11155 {
11156 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV2_CONFIG,
11157 (uint8_t *)&slv2_config, 1);
11158 }
11159
11160 if (ret == 0)
11161 {
11162 slv2_config.slave2_numop = val->slv_len;
11163 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV2_CONFIG,
11164 (uint8_t *)&slv2_config, 1);
11165 }
11166
11167 if (ret == 0)
11168 {
11169 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
11170 }
11171
11172 return ret;
11173 }
11174
11175 /**
11176 * @brief Configure slave 3 for perform a write/read.[get]
11177 *
11178 * @param ctx Read / write interface definitions.(ptr)
11179 * @param val Structure that contain
11180 * - uint8_t slv_add; 8 bit i2c device address
11181 * - uint8_t slv_subadd; 8 bit register device address
11182 * - uint8_t slv_len; num of bit to read
11183 * @retval Interface status (MANDATORY: return 0 -> no Error).
11184 *
11185 */
lsm6dsr_sh_slv3_cfg_read(stmdev_ctx_t * ctx,lsm6dsr_sh_cfg_read_t * val)11186 int32_t lsm6dsr_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
11187 lsm6dsr_sh_cfg_read_t *val)
11188 {
11189 lsm6dsr_slv3_config_t slv3_config;
11190 lsm6dsr_slv3_add_t slv3_add;
11191 int32_t ret;
11192
11193 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
11194
11195 if (ret == 0)
11196 {
11197 slv3_add.slave3_add = (uint8_t)(val->slv_add >> 1);
11198 slv3_add.r_3 = 1;
11199 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV3_ADD,
11200 (uint8_t *)&slv3_add, 1);
11201 }
11202
11203 if (ret == 0)
11204 {
11205 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV3_SUBADD,
11206 &(val->slv_subadd), 1);
11207 }
11208
11209 if (ret == 0)
11210 {
11211 ret = lsm6dsr_read_reg(ctx, LSM6DSR_SLV3_CONFIG,
11212 (uint8_t *)&slv3_config, 1);
11213 }
11214
11215 if (ret == 0)
11216 {
11217 slv3_config.slave3_numop = val->slv_len;
11218 ret = lsm6dsr_write_reg(ctx, LSM6DSR_SLV3_CONFIG,
11219 (uint8_t *)&slv3_config, 1);
11220 }
11221
11222 if (ret == 0)
11223 {
11224 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
11225 }
11226
11227 return ret;
11228 }
11229
11230 /**
11231 * @brief Sensor hub source register.[get]
11232 *
11233 * @param ctx Read / write interface definitions.(ptr)
11234 * @param val Registers from STATUS_MASTER
11235 * @retval Interface status (MANDATORY: return 0 -> no Error).
11236 *
11237 */
lsm6dsr_sh_status_get(stmdev_ctx_t * ctx,lsm6dsr_status_master_t * val)11238 int32_t lsm6dsr_sh_status_get(stmdev_ctx_t *ctx,
11239 lsm6dsr_status_master_t *val)
11240 {
11241 int32_t ret;
11242
11243 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_SENSOR_HUB_BANK);
11244
11245 if (ret == 0)
11246 {
11247 ret = lsm6dsr_read_reg(ctx, LSM6DSR_STATUS_MASTER, (uint8_t *)val, 1);
11248 }
11249
11250 if (ret == 0)
11251 {
11252 ret = lsm6dsr_mem_bank_set(ctx, LSM6DSR_USER_BANK);
11253 }
11254
11255 return ret;
11256 }
11257
11258 /**
11259 * @}
11260 *
11261 */
11262
11263 /**
11264 * @defgroup LSM6DSR_Sensors for Smart Mobile Devices
11265 * @brief This section groups all the functions that manage the
11266 * Sensors for Smart Mobile Devices.
11267 * @{
11268 *
11269 */
11270
11271 /**
11272 * @brief Sensor synchronization time frame resolution[set]
11273 *
11274 * @param ctx Read / write interface definitions.(ptr)
11275 * @param val Change the values of tph_h_sel in LSM6DSR_S4S_TPH_L
11276 * @retval Interface status (MANDATORY: return 0 -> no Error).
11277 *
11278 */
lsm6dsr_s4s_tph_res_set(stmdev_ctx_t * ctx,lsm6dsr_s4s_tph_res_t val)11279 int32_t lsm6dsr_s4s_tph_res_set(stmdev_ctx_t *ctx,
11280 lsm6dsr_s4s_tph_res_t val)
11281 {
11282 lsm6dsr_s4s_tph_l_t s4s_tph_l;
11283 int32_t ret;
11284
11285 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1);
11286
11287 if (ret == 0)
11288 {
11289 s4s_tph_l.tph_h_sel = (uint8_t)val;
11290 ret = lsm6dsr_write_reg(ctx, LSM6DSR_S4S_TPH_L,
11291 (uint8_t *)&s4s_tph_l, 1);
11292 }
11293
11294 return ret;
11295 }
11296
11297 /**
11298 * @brief Sensor synchronization time frame resolution.[get]
11299 *
11300 * @param ctx Read / write interface definitions.(ptr)
11301 * @param val Get the values of tph_h_sel in LSM6DSR_S4S_TPH_L
11302 * @retval Interface status (MANDATORY: return 0 -> no Error).
11303 *
11304 */
lsm6dsr_s4s_tph_res_get(stmdev_ctx_t * ctx,lsm6dsr_s4s_tph_res_t * val)11305 int32_t lsm6dsr_s4s_tph_res_get(stmdev_ctx_t *ctx,
11306 lsm6dsr_s4s_tph_res_t *val)
11307 {
11308 lsm6dsr_s4s_tph_l_t s4s_tph_l;
11309 int32_t ret;
11310
11311 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1);
11312
11313 switch (s4s_tph_l.tph_h_sel)
11314 {
11315 case LSM6DSR_S4S_TPH_7bit:
11316 *val = LSM6DSR_S4S_TPH_7bit;
11317 break;
11318
11319 case LSM6DSR_S4S_TPH_15bit:
11320 *val = LSM6DSR_S4S_TPH_15bit;
11321 break;
11322
11323 default:
11324 *val = LSM6DSR_S4S_TPH_7bit;
11325 break;
11326 }
11327
11328 return ret;
11329 }
11330
11331 /**
11332 * @brief Sensor synchronization time frame.[set]
11333 *
11334 * @param ctx Read / write interface definitions.(ptr)
11335 * @param val Change the values of tph_l in S4S_TPH_L and
11336 * tph_h in S4S_TPH_H
11337 * @retval Interface status (MANDATORY: return 0 -> no Error).
11338 *
11339 */
lsm6dsr_s4s_tph_val_set(stmdev_ctx_t * ctx,uint16_t val)11340 int32_t lsm6dsr_s4s_tph_val_set(stmdev_ctx_t *ctx, uint16_t val)
11341 {
11342 lsm6dsr_s4s_tph_l_t s4s_tph_l;
11343 lsm6dsr_s4s_tph_h_t s4s_tph_h;
11344 int32_t ret;
11345
11346 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1);
11347
11348 if (ret == 0)
11349 {
11350 s4s_tph_l.tph_l = (uint8_t)(val & 0x007FU);
11351 ret = lsm6dsr_write_reg(ctx, LSM6DSR_S4S_TPH_L,
11352 (uint8_t *)&s4s_tph_l, 1);
11353 }
11354
11355 if (ret == 0)
11356 {
11357 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_H,
11358 (uint8_t *)&s4s_tph_h, 1);
11359 }
11360
11361 if (ret == 0)
11362 {
11363 s4s_tph_h.tph_h = (uint8_t)((val & 0x7F80U) >> 7);
11364 ret = lsm6dsr_write_reg(ctx, LSM6DSR_S4S_TPH_H,
11365 (uint8_t *)&s4s_tph_h, 1);
11366 }
11367
11368 return ret;
11369 }
11370
11371 /**
11372 * @brief Sensor synchronization time frame.[get]
11373 *
11374 * @param ctx Read / write interface definitions.(ptr)
11375 * @param val Get the values of tph_l in S4S_TPH_L and tph_h in S4S_TPH_H
11376 * @retval Interface status (MANDATORY: return 0 -> no Error).
11377 *
11378 */
lsm6dsr_s4s_tph_val_get(stmdev_ctx_t * ctx,uint16_t * val)11379 int32_t lsm6dsr_s4s_tph_val_get(stmdev_ctx_t *ctx, uint16_t *val)
11380 {
11381 lsm6dsr_s4s_tph_l_t s4s_tph_l;
11382 lsm6dsr_s4s_tph_h_t s4s_tph_h;
11383 int32_t ret;
11384
11385 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_L, (uint8_t *)&s4s_tph_l, 1);
11386
11387 if (ret == 0)
11388 {
11389 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_TPH_H,
11390 (uint8_t *)&s4s_tph_h, 1);
11391 }
11392
11393 *val = s4s_tph_h.tph_h;
11394 *val = *val << 7;
11395 *val += s4s_tph_l.tph_l;
11396
11397 return ret;
11398 }
11399
11400 /**
11401 * @brief Sensor synchronization resolution ratio register.[set]
11402 *
11403 * @param ctx Read / write interface definitions.(ptr)
11404 * @param val Change the values of rr in S4S_RR.
11405 * @retval Interface status (MANDATORY: return 0 -> no Error).
11406 *
11407 */
lsm6dsr_s4s_res_ratio_set(stmdev_ctx_t * ctx,lsm6dsr_s4s_res_ratio_t val)11408 int32_t lsm6dsr_s4s_res_ratio_set(stmdev_ctx_t *ctx,
11409 lsm6dsr_s4s_res_ratio_t val)
11410 {
11411 lsm6dsr_s4s_rr_t s4s_rr;
11412 int32_t ret;
11413
11414 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_RR, (uint8_t *)&s4s_rr, 1);
11415
11416 if (ret == 0)
11417 {
11418 s4s_rr.rr = (uint8_t)val;
11419 ret = lsm6dsr_write_reg(ctx, LSM6DSR_S4S_RR, (uint8_t *)&s4s_rr, 1);
11420 }
11421
11422 return ret;
11423 }
11424
11425 /**
11426 * @brief Sensor synchronization resolution ratio register.[get]
11427 *
11428 * @param ctx Read / write interface definitions.(ptr)
11429 * @param val get the values of rr in S4S_RR
11430 * @retval Interface status (MANDATORY: return 0 -> no Error).
11431 *
11432 */
lsm6dsr_s4s_res_ratio_get(stmdev_ctx_t * ctx,lsm6dsr_s4s_res_ratio_t * val)11433 int32_t lsm6dsr_s4s_res_ratio_get(stmdev_ctx_t *ctx,
11434 lsm6dsr_s4s_res_ratio_t *val)
11435 {
11436 lsm6dsr_s4s_rr_t s4s_rr;
11437 int32_t ret;
11438
11439 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_RR, (uint8_t *)&s4s_rr, 1);
11440
11441 switch (s4s_rr.rr)
11442 {
11443 case LSM6DSR_S4S_DT_RES_11:
11444 *val = LSM6DSR_S4S_DT_RES_11;
11445 break;
11446
11447 case LSM6DSR_S4S_DT_RES_12:
11448 *val = LSM6DSR_S4S_DT_RES_12;
11449 break;
11450
11451 case LSM6DSR_S4S_DT_RES_13:
11452 *val = LSM6DSR_S4S_DT_RES_13;
11453 break;
11454
11455 case LSM6DSR_S4S_DT_RES_14:
11456 *val = LSM6DSR_S4S_DT_RES_14;
11457 break;
11458
11459 default:
11460 *val = LSM6DSR_S4S_DT_RES_11;
11461 break;
11462 }
11463
11464 return ret;
11465 }
11466
11467 /**
11468 * @brief s4s master command.[set]
11469 *
11470 * @param ctx Read / write interface definitions.(ptr)
11471 * @param val Change the values of S4S_ST_CMD_CODE.
11472 * @retval Interface status (MANDATORY: return 0 -> no Error).
11473 *
11474 */
lsm6dsr_s4s_command_set(stmdev_ctx_t * ctx,uint8_t val)11475 int32_t lsm6dsr_s4s_command_set(stmdev_ctx_t *ctx, uint8_t val)
11476 {
11477 lsm6dsr_s4s_st_cmd_code_t s4s_st_cmd_code;
11478 int32_t ret;
11479
11480 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_ST_CMD_CODE,
11481 (uint8_t *)&s4s_st_cmd_code, 1);
11482
11483 if (ret == 0)
11484 {
11485 s4s_st_cmd_code.s4s_st_cmd_code = (uint8_t)val;
11486 ret = lsm6dsr_write_reg(ctx, LSM6DSR_S4S_ST_CMD_CODE,
11487 (uint8_t *)&s4s_st_cmd_code, 1);
11488 }
11489
11490 return ret;
11491 }
11492
11493 /**
11494 * @brief s4s master command.[get]
11495 *
11496 * @param ctx Read / write interface definitions.(ptr)
11497 * @param val get the values of S4S_ST_CMD_CODE.
11498 * @retval Interface status (MANDATORY: return 0 -> no Error).
11499 *
11500 */
lsm6dsr_s4s_command_get(stmdev_ctx_t * ctx,uint8_t * val)11501 int32_t lsm6dsr_s4s_command_get(stmdev_ctx_t *ctx, uint8_t *val)
11502 {
11503 lsm6dsr_s4s_st_cmd_code_t s4s_st_cmd_code;
11504 int32_t ret;
11505
11506 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_ST_CMD_CODE,
11507 (uint8_t *)&s4s_st_cmd_code, 1);
11508 *val = s4s_st_cmd_code.s4s_st_cmd_code;
11509
11510 return ret;
11511 }
11512
11513 /**
11514 * @brief S4S DT register.[set]
11515 *
11516 * @param ctx Read / write interface definitions.(ptr)
11517 * @param val Change the values of S4S_DT_REG.
11518 * @retval Interface status (MANDATORY: return 0 -> no Error).
11519 *
11520 */
lsm6dsr_s4s_dt_set(stmdev_ctx_t * ctx,uint8_t val)11521 int32_t lsm6dsr_s4s_dt_set(stmdev_ctx_t *ctx, uint8_t val)
11522 {
11523 lsm6dsr_s4s_dt_reg_t s4s_dt_reg;
11524 int32_t ret;
11525
11526 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_DT_REG,
11527 (uint8_t *)&s4s_dt_reg, 1);
11528
11529 if (ret == 0)
11530 {
11531 s4s_dt_reg.dt = (uint8_t)val;
11532 ret = lsm6dsr_write_reg(ctx, LSM6DSR_S4S_DT_REG,
11533 (uint8_t *)&s4s_dt_reg, 1);
11534 }
11535
11536 return ret;
11537 }
11538
11539 /**
11540 * @brief S4S DT register.[get]
11541 *
11542 * @param ctx Read / write interface definitions.(ptr)
11543 * @param val get the values of S4S_DT_REG.
11544 * @retval Interface status (MANDATORY: return 0 -> no Error).
11545 *
11546 */
lsm6dsr_s4s_dt_get(stmdev_ctx_t * ctx,uint8_t * val)11547 int32_t lsm6dsr_s4s_dt_get(stmdev_ctx_t *ctx, uint8_t *val)
11548 {
11549 lsm6dsr_s4s_dt_reg_t s4s_dt_reg;
11550 int32_t ret;
11551
11552 ret = lsm6dsr_read_reg(ctx, LSM6DSR_S4S_DT_REG,
11553 (uint8_t *)&s4s_dt_reg, 1);
11554 *val = s4s_dt_reg.dt;
11555
11556 return ret;
11557 }
11558
11559 /**
11560 * @}
11561 *
11562 */
11563
11564 /**
11565 * @}
11566 *
11567 */
11568
11569 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
11570
