1 /**
2 ******************************************************************************
3 * @file lsm6dsox_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSOX driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dsox_reg.h"
21
22 /**
23 * @defgroup LSM6DSOX
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dsox enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LSM6DSOX_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx communication interface handler.(ptr)
43 * @param reg first register address to read.
44 * @param data buffer for data read.(ptr)
45 * @param len number of consecutive register to read.
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6dsox_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dsox_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx communication interface handler.(ptr)
69 * @param reg first register address to write.
70 * @param data the buffer contains data to be written.(ptr)
71 * @param len number of consecutive register to write.
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lsm6dsox_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lsm6dsox_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup LSM6DSOX_Private_functions
98 * @brief Section collect all the utility functions needed by APIs.
99 * @{
100 *
101 */
102
bytecpy(uint8_t * target,uint8_t * source)103 static void bytecpy(uint8_t *target, uint8_t *source)
104 {
105 if ((target != NULL) && (source != NULL))
106 {
107 *target = *source;
108 }
109 }
110
111 /**
112 * @}
113 *
114 */
115
116 /**
117 * @defgroup LSM6DSOX_Sensitivity
118 * @brief These functions convert raw-data into engineering units.
119 * @{
120 *
121 */
lsm6dsox_from_fs2_to_mg(int16_t lsb)122 float_t lsm6dsox_from_fs2_to_mg(int16_t lsb)
123 {
124 return ((float_t)lsb) * 0.061f;
125 }
126
lsm6dsox_from_fs4_to_mg(int16_t lsb)127 float_t lsm6dsox_from_fs4_to_mg(int16_t lsb)
128 {
129 return ((float_t)lsb) * 0.122f;
130 }
131
lsm6dsox_from_fs8_to_mg(int16_t lsb)132 float_t lsm6dsox_from_fs8_to_mg(int16_t lsb)
133 {
134 return ((float_t)lsb) * 0.244f;
135 }
136
lsm6dsox_from_fs16_to_mg(int16_t lsb)137 float_t lsm6dsox_from_fs16_to_mg(int16_t lsb)
138 {
139 return ((float_t)lsb) * 0.488f;
140 }
141
lsm6dsox_from_fs125_to_mdps(int16_t lsb)142 float_t lsm6dsox_from_fs125_to_mdps(int16_t lsb)
143 {
144 return ((float_t)lsb) * 4.375f;
145 }
146
lsm6dsox_from_fs500_to_mdps(int16_t lsb)147 float_t lsm6dsox_from_fs500_to_mdps(int16_t lsb)
148 {
149 return ((float_t)lsb) * 17.50f;
150 }
151
lsm6dsox_from_fs250_to_mdps(int16_t lsb)152 float_t lsm6dsox_from_fs250_to_mdps(int16_t lsb)
153 {
154 return ((float_t)lsb) * 8.750f;
155 }
156
lsm6dsox_from_fs1000_to_mdps(int16_t lsb)157 float_t lsm6dsox_from_fs1000_to_mdps(int16_t lsb)
158 {
159 return ((float_t)lsb) * 35.0f;
160 }
161
lsm6dsox_from_fs2000_to_mdps(int16_t lsb)162 float_t lsm6dsox_from_fs2000_to_mdps(int16_t lsb)
163 {
164 return ((float_t)lsb) * 70.0f;
165 }
166
lsm6dsox_from_lsb_to_celsius(int16_t lsb)167 float_t lsm6dsox_from_lsb_to_celsius(int16_t lsb)
168 {
169 return (((float_t)lsb / 256.0f) + 25.0f);
170 }
171
lsm6dsox_from_lsb_to_nsec(int16_t lsb)172 float_t lsm6dsox_from_lsb_to_nsec(int16_t lsb)
173 {
174 return ((float_t)lsb * 25000.0f);
175 }
176
177 /**
178 * @}
179 *
180 */
181
182 /**
183 * @defgroup LSM6DSOX_Data_Generation
184 * @brief This section groups all the functions concerning
185 * data generation.
186 *
187 */
188
189 /**
190 * @brief Accelerometer full-scale selection.[set]
191 *
192 * @param ctx read / write interface definitions
193 * @param val change the values of fs_xl in reg CTRL1_XL
194 * @retval interface status (MANDATORY: return 0 -> no Error)
195 *
196 */
lsm6dsox_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsox_fs_xl_t val)197 int32_t lsm6dsox_xl_full_scale_set(const stmdev_ctx_t *ctx,
198 lsm6dsox_fs_xl_t val)
199 {
200 lsm6dsox_ctrl1_xl_t reg;
201 int32_t ret;
202
203 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1);
204
205 if (ret == 0)
206 {
207 reg.fs_xl = (uint8_t) val;
208 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1);
209 }
210
211 return ret;
212 }
213
214 /**
215 * @brief Accelerometer full-scale selection.[get]
216 *
217 * @param ctx read / write interface definitions
218 * @param val Get the values of fs_xl in reg CTRL1_XL
219 * @retval interface status (MANDATORY: return 0 -> no Error)
220 *
221 */
lsm6dsox_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsox_fs_xl_t * val)222 int32_t lsm6dsox_xl_full_scale_get(const stmdev_ctx_t *ctx,
223 lsm6dsox_fs_xl_t *val)
224 {
225 lsm6dsox_ctrl1_xl_t reg;
226 int32_t ret;
227
228 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1);
229
230 switch (reg.fs_xl)
231 {
232 case LSM6DSOX_2g:
233 *val = LSM6DSOX_2g;
234 break;
235
236 case LSM6DSOX_16g:
237 *val = LSM6DSOX_16g;
238 break;
239
240 case LSM6DSOX_4g:
241 *val = LSM6DSOX_4g;
242 break;
243
244 case LSM6DSOX_8g:
245 *val = LSM6DSOX_8g;
246 break;
247
248 default:
249 *val = LSM6DSOX_2g;
250 break;
251 }
252
253 return ret;
254 }
255
256 /**
257 * @brief Accelerometer UI data rate selection.[set]
258 *
259 * @param ctx read / write interface definitions
260 * @param val change the values of odr_xl in reg CTRL1_XL
261 * @retval interface status (MANDATORY: return 0 -> no Error)
262 *
263 */
lsm6dsox_xl_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsox_odr_xl_t val)264 int32_t lsm6dsox_xl_data_rate_set(const stmdev_ctx_t *ctx,
265 lsm6dsox_odr_xl_t val)
266 {
267 lsm6dsox_odr_xl_t odr_xl = val;
268 lsm6dsox_emb_fsm_enable_t fsm_enable;
269 lsm6dsox_fsm_odr_t fsm_odr;
270 lsm6dsox_emb_sens_t emb_sens;
271 lsm6dsox_mlc_odr_t mlc_odr;
272 lsm6dsox_ctrl1_xl_t reg;
273 int32_t ret;
274
275 /* Check the Finite State Machine data rate constraints */
276 ret = lsm6dsox_fsm_enable_get(ctx, &fsm_enable);
277
278 if (ret == 0)
279 {
280 if ((fsm_enable.fsm_enable_a.fsm1_en |
281 fsm_enable.fsm_enable_a.fsm2_en |
282 fsm_enable.fsm_enable_a.fsm3_en |
283 fsm_enable.fsm_enable_a.fsm4_en |
284 fsm_enable.fsm_enable_a.fsm5_en |
285 fsm_enable.fsm_enable_a.fsm6_en |
286 fsm_enable.fsm_enable_a.fsm7_en |
287 fsm_enable.fsm_enable_a.fsm8_en |
288 fsm_enable.fsm_enable_b.fsm9_en |
289 fsm_enable.fsm_enable_b.fsm10_en |
290 fsm_enable.fsm_enable_b.fsm11_en |
291 fsm_enable.fsm_enable_b.fsm12_en |
292 fsm_enable.fsm_enable_b.fsm13_en |
293 fsm_enable.fsm_enable_b.fsm14_en |
294 fsm_enable.fsm_enable_b.fsm15_en |
295 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
296 {
297 ret = lsm6dsox_fsm_data_rate_get(ctx, &fsm_odr);
298
299 if (ret == 0)
300 {
301 switch (fsm_odr)
302 {
303 case LSM6DSOX_ODR_FSM_12Hz5:
304 if (val == LSM6DSOX_XL_ODR_OFF)
305 {
306 odr_xl = LSM6DSOX_XL_ODR_12Hz5;
307 }
308
309 else
310 {
311 odr_xl = val;
312 }
313
314 break;
315
316 case LSM6DSOX_ODR_FSM_26Hz:
317 if (val == LSM6DSOX_XL_ODR_OFF)
318 {
319 odr_xl = LSM6DSOX_XL_ODR_26Hz;
320 }
321
322 else if (val == LSM6DSOX_XL_ODR_12Hz5)
323 {
324 odr_xl = LSM6DSOX_XL_ODR_26Hz;
325 }
326
327 else
328 {
329 odr_xl = val;
330 }
331
332 break;
333
334 case LSM6DSOX_ODR_FSM_52Hz:
335 if (val == LSM6DSOX_XL_ODR_OFF)
336 {
337 odr_xl = LSM6DSOX_XL_ODR_52Hz;
338 }
339
340 else if (val == LSM6DSOX_XL_ODR_12Hz5)
341 {
342 odr_xl = LSM6DSOX_XL_ODR_52Hz;
343 }
344
345 else if (val == LSM6DSOX_XL_ODR_26Hz)
346 {
347 odr_xl = LSM6DSOX_XL_ODR_52Hz;
348 }
349
350 else
351 {
352 odr_xl = val;
353 }
354
355 break;
356
357 case LSM6DSOX_ODR_FSM_104Hz:
358 if (val == LSM6DSOX_XL_ODR_OFF)
359 {
360 odr_xl = LSM6DSOX_XL_ODR_104Hz;
361 }
362
363 else if (val == LSM6DSOX_XL_ODR_12Hz5)
364 {
365 odr_xl = LSM6DSOX_XL_ODR_104Hz;
366 }
367
368 else if (val == LSM6DSOX_XL_ODR_26Hz)
369 {
370 odr_xl = LSM6DSOX_XL_ODR_104Hz;
371 }
372
373 else if (val == LSM6DSOX_XL_ODR_52Hz)
374 {
375 odr_xl = LSM6DSOX_XL_ODR_104Hz;
376 }
377
378 else
379 {
380 odr_xl = val;
381 }
382
383 break;
384
385 default:
386 odr_xl = val;
387 break;
388 }
389 }
390 }
391 }
392
393 /* Check the Machine Learning Core data rate constraints */
394 emb_sens.mlc = PROPERTY_DISABLE;
395
396 if (ret == 0)
397 {
398 lsm6dsox_embedded_sens_get(ctx, &emb_sens);
399
400 if (emb_sens.mlc == PROPERTY_ENABLE)
401 {
402 ret = lsm6dsox_mlc_data_rate_get(ctx, &mlc_odr);
403
404 if (ret == 0)
405 {
406 switch (mlc_odr)
407 {
408 case LSM6DSOX_ODR_PRGS_12Hz5:
409 if (val == LSM6DSOX_XL_ODR_OFF)
410 {
411 odr_xl = LSM6DSOX_XL_ODR_12Hz5;
412 }
413
414 else
415 {
416 odr_xl = val;
417 }
418
419 break;
420
421 case LSM6DSOX_ODR_PRGS_26Hz:
422 if (val == LSM6DSOX_XL_ODR_OFF)
423 {
424 odr_xl = LSM6DSOX_XL_ODR_26Hz;
425 }
426
427 else if (val == LSM6DSOX_XL_ODR_12Hz5)
428 {
429 odr_xl = LSM6DSOX_XL_ODR_26Hz;
430 }
431
432 else
433 {
434 odr_xl = val;
435 }
436
437 break;
438
439 case LSM6DSOX_ODR_PRGS_52Hz:
440 if (val == LSM6DSOX_XL_ODR_OFF)
441 {
442 odr_xl = LSM6DSOX_XL_ODR_52Hz;
443 }
444
445 else if (val == LSM6DSOX_XL_ODR_12Hz5)
446 {
447 odr_xl = LSM6DSOX_XL_ODR_52Hz;
448 }
449
450 else if (val == LSM6DSOX_XL_ODR_26Hz)
451 {
452 odr_xl = LSM6DSOX_XL_ODR_52Hz;
453 }
454
455 else
456 {
457 odr_xl = val;
458 }
459
460 break;
461
462 case LSM6DSOX_ODR_PRGS_104Hz:
463 if (val == LSM6DSOX_XL_ODR_OFF)
464 {
465 odr_xl = LSM6DSOX_XL_ODR_104Hz;
466 }
467
468 else if (val == LSM6DSOX_XL_ODR_12Hz5)
469 {
470 odr_xl = LSM6DSOX_XL_ODR_104Hz;
471 }
472
473 else if (val == LSM6DSOX_XL_ODR_26Hz)
474 {
475 odr_xl = LSM6DSOX_XL_ODR_104Hz;
476 }
477
478 else if (val == LSM6DSOX_XL_ODR_52Hz)
479 {
480 odr_xl = LSM6DSOX_XL_ODR_104Hz;
481 }
482
483 else
484 {
485 odr_xl = val;
486 }
487
488 break;
489
490 default:
491 odr_xl = val;
492 break;
493 }
494 }
495 }
496 }
497
498 if (ret == 0)
499 {
500 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1);
501 }
502
503 if (ret == 0)
504 {
505 reg.odr_xl = (uint8_t) odr_xl;
506 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1);
507 }
508
509 return ret;
510 }
511
512 /**
513 * @brief Accelerometer UI data rate selection.[get]
514 *
515 * @param ctx read / write interface definitions
516 * @param val Get the values of odr_xl in reg CTRL1_XL
517 * @retval interface status (MANDATORY: return 0 -> no Error)
518 *
519 */
lsm6dsox_xl_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsox_odr_xl_t * val)520 int32_t lsm6dsox_xl_data_rate_get(const stmdev_ctx_t *ctx,
521 lsm6dsox_odr_xl_t *val)
522 {
523 lsm6dsox_ctrl1_xl_t reg;
524 int32_t ret;
525
526 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1);
527
528 switch (reg.odr_xl)
529 {
530 case LSM6DSOX_XL_ODR_OFF:
531 *val = LSM6DSOX_XL_ODR_OFF;
532 break;
533
534 case LSM6DSOX_XL_ODR_12Hz5:
535 *val = LSM6DSOX_XL_ODR_12Hz5;
536 break;
537
538 case LSM6DSOX_XL_ODR_26Hz:
539 *val = LSM6DSOX_XL_ODR_26Hz;
540 break;
541
542 case LSM6DSOX_XL_ODR_52Hz:
543 *val = LSM6DSOX_XL_ODR_52Hz;
544 break;
545
546 case LSM6DSOX_XL_ODR_104Hz:
547 *val = LSM6DSOX_XL_ODR_104Hz;
548 break;
549
550 case LSM6DSOX_XL_ODR_208Hz:
551 *val = LSM6DSOX_XL_ODR_208Hz;
552 break;
553
554 case LSM6DSOX_XL_ODR_417Hz:
555 *val = LSM6DSOX_XL_ODR_417Hz;
556 break;
557
558 case LSM6DSOX_XL_ODR_833Hz:
559 *val = LSM6DSOX_XL_ODR_833Hz;
560 break;
561
562 case LSM6DSOX_XL_ODR_1667Hz:
563 *val = LSM6DSOX_XL_ODR_1667Hz;
564 break;
565
566 case LSM6DSOX_XL_ODR_3333Hz:
567 *val = LSM6DSOX_XL_ODR_3333Hz;
568 break;
569
570 case LSM6DSOX_XL_ODR_6667Hz:
571 *val = LSM6DSOX_XL_ODR_6667Hz;
572 break;
573
574 case LSM6DSOX_XL_ODR_1Hz6:
575 *val = LSM6DSOX_XL_ODR_1Hz6;
576 break;
577
578 default:
579 *val = LSM6DSOX_XL_ODR_OFF;
580 break;
581 }
582
583 return ret;
584 }
585
586 /**
587 * @brief Gyroscope UI chain full-scale selection.[set]
588 *
589 * @param ctx read / write interface definitions
590 * @param val change the values of fs_g in reg CTRL2_G
591 * @retval interface status (MANDATORY: return 0 -> no Error)
592 *
593 */
lsm6dsox_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsox_fs_g_t val)594 int32_t lsm6dsox_gy_full_scale_set(const stmdev_ctx_t *ctx,
595 lsm6dsox_fs_g_t val)
596 {
597 lsm6dsox_ctrl2_g_t reg;
598 int32_t ret;
599
600 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t *)®, 1);
601
602 if (ret == 0)
603 {
604 reg.fs_g = (uint8_t) val;
605 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t *)®, 1);
606 }
607
608 return ret;
609 }
610
611 /**
612 * @brief Gyroscope UI chain full-scale selection.[get]
613 *
614 * @param ctx read / write interface definitions
615 * @param val Get the values of fs_g in reg CTRL2_G
616 * @retval interface status (MANDATORY: return 0 -> no Error)
617 *
618 */
lsm6dsox_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsox_fs_g_t * val)619 int32_t lsm6dsox_gy_full_scale_get(const stmdev_ctx_t *ctx,
620 lsm6dsox_fs_g_t *val)
621 {
622 lsm6dsox_ctrl2_g_t reg;
623 int32_t ret;
624
625 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t *)®, 1);
626
627 switch (reg.fs_g)
628 {
629 case LSM6DSOX_250dps:
630 *val = LSM6DSOX_250dps;
631 break;
632
633 case LSM6DSOX_125dps:
634 *val = LSM6DSOX_125dps;
635 break;
636
637 case LSM6DSOX_500dps:
638 *val = LSM6DSOX_500dps;
639 break;
640
641 case LSM6DSOX_1000dps:
642 *val = LSM6DSOX_1000dps;
643 break;
644
645 case LSM6DSOX_2000dps:
646 *val = LSM6DSOX_2000dps;
647 break;
648
649 default:
650 *val = LSM6DSOX_250dps;
651 break;
652 }
653
654 return ret;
655 }
656
657 /**
658 * @brief Gyroscope UI data rate selection.[set]
659 *
660 * @param ctx read / write interface definitions
661 * @param val change the values of odr_g in reg CTRL2_G
662 * @retval interface status (MANDATORY: return 0 -> no Error)
663 *
664 */
lsm6dsox_gy_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsox_odr_g_t val)665 int32_t lsm6dsox_gy_data_rate_set(const stmdev_ctx_t *ctx,
666 lsm6dsox_odr_g_t val)
667 {
668 lsm6dsox_odr_g_t odr_gy = val;
669 lsm6dsox_emb_fsm_enable_t fsm_enable;
670 lsm6dsox_fsm_odr_t fsm_odr;
671 lsm6dsox_emb_sens_t emb_sens;
672 lsm6dsox_mlc_odr_t mlc_odr;
673 lsm6dsox_ctrl2_g_t reg;
674 int32_t ret;
675
676 /* Check the Finite State Machine data rate constraints */
677 ret = lsm6dsox_fsm_enable_get(ctx, &fsm_enable);
678
679 if (ret == 0)
680 {
681 if ((fsm_enable.fsm_enable_a.fsm1_en |
682 fsm_enable.fsm_enable_a.fsm2_en |
683 fsm_enable.fsm_enable_a.fsm3_en |
684 fsm_enable.fsm_enable_a.fsm4_en |
685 fsm_enable.fsm_enable_a.fsm5_en |
686 fsm_enable.fsm_enable_a.fsm6_en |
687 fsm_enable.fsm_enable_a.fsm7_en |
688 fsm_enable.fsm_enable_a.fsm8_en |
689 fsm_enable.fsm_enable_b.fsm9_en |
690 fsm_enable.fsm_enable_b.fsm10_en |
691 fsm_enable.fsm_enable_b.fsm11_en |
692 fsm_enable.fsm_enable_b.fsm12_en |
693 fsm_enable.fsm_enable_b.fsm13_en |
694 fsm_enable.fsm_enable_b.fsm14_en |
695 fsm_enable.fsm_enable_b.fsm15_en |
696 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
697 {
698 ret = lsm6dsox_fsm_data_rate_get(ctx, &fsm_odr);
699
700 if (ret == 0)
701 {
702 switch (fsm_odr)
703 {
704 case LSM6DSOX_ODR_FSM_12Hz5:
705 if (val == LSM6DSOX_GY_ODR_OFF)
706 {
707 odr_gy = LSM6DSOX_GY_ODR_12Hz5;
708 }
709
710 else
711 {
712 odr_gy = val;
713 }
714
715 break;
716
717 case LSM6DSOX_ODR_FSM_26Hz:
718 if (val == LSM6DSOX_GY_ODR_OFF)
719 {
720 odr_gy = LSM6DSOX_GY_ODR_26Hz;
721 }
722
723 else if (val == LSM6DSOX_GY_ODR_12Hz5)
724 {
725 odr_gy = LSM6DSOX_GY_ODR_26Hz;
726 }
727
728 else
729 {
730 odr_gy = val;
731 }
732
733 break;
734
735 case LSM6DSOX_ODR_FSM_52Hz:
736 if (val == LSM6DSOX_GY_ODR_OFF)
737 {
738 odr_gy = LSM6DSOX_GY_ODR_52Hz;
739 }
740
741 else if (val == LSM6DSOX_GY_ODR_12Hz5)
742 {
743 odr_gy = LSM6DSOX_GY_ODR_52Hz;
744 }
745
746 else if (val == LSM6DSOX_GY_ODR_26Hz)
747 {
748 odr_gy = LSM6DSOX_GY_ODR_52Hz;
749 }
750
751 else
752 {
753 odr_gy = val;
754 }
755
756 break;
757
758 case LSM6DSOX_ODR_FSM_104Hz:
759 if (val == LSM6DSOX_GY_ODR_OFF)
760 {
761 odr_gy = LSM6DSOX_GY_ODR_104Hz;
762 }
763
764 else if (val == LSM6DSOX_GY_ODR_12Hz5)
765 {
766 odr_gy = LSM6DSOX_GY_ODR_104Hz;
767 }
768
769 else if (val == LSM6DSOX_GY_ODR_26Hz)
770 {
771 odr_gy = LSM6DSOX_GY_ODR_104Hz;
772 }
773
774 else if (val == LSM6DSOX_GY_ODR_52Hz)
775 {
776 odr_gy = LSM6DSOX_GY_ODR_104Hz;
777 }
778
779 else
780 {
781 odr_gy = val;
782 }
783
784 break;
785
786 default:
787 odr_gy = val;
788 break;
789 }
790 }
791 }
792 }
793
794 /* Check the Machine Learning Core data rate constraints */
795 emb_sens.mlc = PROPERTY_DISABLE;
796
797 if (ret == 0)
798 {
799 ret = lsm6dsox_embedded_sens_get(ctx, &emb_sens);
800
801 if (emb_sens.mlc == PROPERTY_ENABLE)
802 {
803 ret = lsm6dsox_mlc_data_rate_get(ctx, &mlc_odr);
804
805 if (ret == 0)
806 {
807 switch (mlc_odr)
808 {
809 case LSM6DSOX_ODR_PRGS_12Hz5:
810 if (val == LSM6DSOX_GY_ODR_OFF)
811 {
812 odr_gy = LSM6DSOX_GY_ODR_12Hz5;
813 }
814
815 else
816 {
817 odr_gy = val;
818 }
819
820 break;
821
822 case LSM6DSOX_ODR_PRGS_26Hz:
823 if (val == LSM6DSOX_GY_ODR_OFF)
824 {
825 odr_gy = LSM6DSOX_GY_ODR_26Hz;
826 }
827
828 else if (val == LSM6DSOX_GY_ODR_12Hz5)
829 {
830 odr_gy = LSM6DSOX_GY_ODR_26Hz;
831 }
832
833 else
834 {
835 odr_gy = val;
836 }
837
838 break;
839
840 case LSM6DSOX_ODR_PRGS_52Hz:
841 if (val == LSM6DSOX_GY_ODR_OFF)
842 {
843 odr_gy = LSM6DSOX_GY_ODR_52Hz;
844 }
845
846 else if (val == LSM6DSOX_GY_ODR_12Hz5)
847 {
848 odr_gy = LSM6DSOX_GY_ODR_52Hz;
849 }
850
851 else if (val == LSM6DSOX_GY_ODR_26Hz)
852 {
853 odr_gy = LSM6DSOX_GY_ODR_52Hz;
854 }
855
856 else
857 {
858 odr_gy = val;
859 }
860
861 break;
862
863 case LSM6DSOX_ODR_PRGS_104Hz:
864 if (val == LSM6DSOX_GY_ODR_OFF)
865 {
866 odr_gy = LSM6DSOX_GY_ODR_104Hz;
867 }
868
869 else if (val == LSM6DSOX_GY_ODR_12Hz5)
870 {
871 odr_gy = LSM6DSOX_GY_ODR_104Hz;
872 }
873
874 else if (val == LSM6DSOX_GY_ODR_26Hz)
875 {
876 odr_gy = LSM6DSOX_GY_ODR_104Hz;
877 }
878
879 else if (val == LSM6DSOX_GY_ODR_52Hz)
880 {
881 odr_gy = LSM6DSOX_GY_ODR_104Hz;
882 }
883
884 else
885 {
886 odr_gy = val;
887 }
888
889 break;
890
891 default:
892 odr_gy = val;
893 break;
894 }
895 }
896 }
897 }
898
899 if (ret == 0)
900 {
901 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t *)®, 1);
902 }
903
904 if (ret == 0)
905 {
906 reg.odr_g = (uint8_t) odr_gy;
907 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t *)®, 1);
908 }
909
910 return ret;
911 }
912
913 /**
914 * @brief Gyroscope UI data rate selection.[get]
915 *
916 * @param ctx read / write interface definitions
917 * @param val Get the values of odr_g in reg CTRL2_G
918 * @retval interface status (MANDATORY: return 0 -> no Error)
919 *
920 */
lsm6dsox_gy_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsox_odr_g_t * val)921 int32_t lsm6dsox_gy_data_rate_get(const stmdev_ctx_t *ctx,
922 lsm6dsox_odr_g_t *val)
923 {
924 lsm6dsox_ctrl2_g_t reg;
925 int32_t ret;
926
927 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL2_G, (uint8_t *)®, 1);
928
929 switch (reg.odr_g)
930 {
931 case LSM6DSOX_GY_ODR_OFF:
932 *val = LSM6DSOX_GY_ODR_OFF;
933 break;
934
935 case LSM6DSOX_GY_ODR_12Hz5:
936 *val = LSM6DSOX_GY_ODR_12Hz5;
937 break;
938
939 case LSM6DSOX_GY_ODR_26Hz:
940 *val = LSM6DSOX_GY_ODR_26Hz;
941 break;
942
943 case LSM6DSOX_GY_ODR_52Hz:
944 *val = LSM6DSOX_GY_ODR_52Hz;
945 break;
946
947 case LSM6DSOX_GY_ODR_104Hz:
948 *val = LSM6DSOX_GY_ODR_104Hz;
949 break;
950
951 case LSM6DSOX_GY_ODR_208Hz:
952 *val = LSM6DSOX_GY_ODR_208Hz;
953 break;
954
955 case LSM6DSOX_GY_ODR_417Hz:
956 *val = LSM6DSOX_GY_ODR_417Hz;
957 break;
958
959 case LSM6DSOX_GY_ODR_833Hz:
960 *val = LSM6DSOX_GY_ODR_833Hz;
961 break;
962
963 case LSM6DSOX_GY_ODR_1667Hz:
964 *val = LSM6DSOX_GY_ODR_1667Hz;
965 break;
966
967 case LSM6DSOX_GY_ODR_3333Hz:
968 *val = LSM6DSOX_GY_ODR_3333Hz;
969 break;
970
971 case LSM6DSOX_GY_ODR_6667Hz:
972 *val = LSM6DSOX_GY_ODR_6667Hz;
973 break;
974
975 default:
976 *val = LSM6DSOX_GY_ODR_OFF;
977 break;
978 }
979
980 return ret;
981 }
982
983 /**
984 * @brief Block data update.[set]
985 *
986 * @param ctx read / write interface definitions
987 * @param val change the values of bdu in reg CTRL3_C
988 * @retval interface status (MANDATORY: return 0 -> no Error)
989 *
990 */
lsm6dsox_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)991 int32_t lsm6dsox_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
992 {
993 lsm6dsox_ctrl3_c_t reg;
994 int32_t ret;
995
996 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
997
998 if (ret == 0)
999 {
1000 reg.bdu = val;
1001 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
1002 }
1003
1004 return ret;
1005 }
1006
1007 /**
1008 * @brief Block data update.[get]
1009 *
1010 * @param ctx read / write interface definitions
1011 * @param val change the values of bdu in reg CTRL3_C
1012 * @retval interface status (MANDATORY: return 0 -> no Error)
1013 *
1014 */
lsm6dsox_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)1015 int32_t lsm6dsox_block_data_update_get(const stmdev_ctx_t *ctx,
1016 uint8_t *val)
1017 {
1018 lsm6dsox_ctrl3_c_t reg;
1019 int32_t ret;
1020
1021 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
1022 *val = reg.bdu;
1023
1024 return ret;
1025 }
1026
1027 /**
1028 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
1029 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
1030 *
1031 * @param ctx read / write interface definitions
1032 * @param val change the values of usr_off_w in reg CTRL6_C
1033 * @retval interface status (MANDATORY: return 0 -> no Error)
1034 *
1035 */
lsm6dsox_xl_offset_weight_set(const stmdev_ctx_t * ctx,lsm6dsox_usr_off_w_t val)1036 int32_t lsm6dsox_xl_offset_weight_set(const stmdev_ctx_t *ctx,
1037 lsm6dsox_usr_off_w_t val)
1038 {
1039 lsm6dsox_ctrl6_c_t reg;
1040 int32_t ret;
1041
1042 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1);
1043
1044 if (ret == 0)
1045 {
1046 reg.usr_off_w = (uint8_t)val;
1047 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1);
1048 }
1049
1050 return ret;
1051 }
1052
1053 /**
1054 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
1055 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
1056 *
1057 * @param ctx read / write interface definitions
1058 * @param val Get the values of usr_off_w in reg CTRL6_C
1059 * @retval interface status (MANDATORY: return 0 -> no Error)
1060 *
1061 */
lsm6dsox_xl_offset_weight_get(const stmdev_ctx_t * ctx,lsm6dsox_usr_off_w_t * val)1062 int32_t lsm6dsox_xl_offset_weight_get(const stmdev_ctx_t *ctx,
1063 lsm6dsox_usr_off_w_t *val)
1064 {
1065 lsm6dsox_ctrl6_c_t reg;
1066 int32_t ret;
1067
1068 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1);
1069
1070 switch (reg.usr_off_w)
1071 {
1072 case LSM6DSOX_LSb_1mg:
1073 *val = LSM6DSOX_LSb_1mg;
1074 break;
1075
1076 case LSM6DSOX_LSb_16mg:
1077 *val = LSM6DSOX_LSb_16mg;
1078 break;
1079
1080 default:
1081 *val = LSM6DSOX_LSb_1mg;
1082 break;
1083 }
1084
1085 return ret;
1086 }
1087
1088 /**
1089 * @brief Accelerometer power mode.[set]
1090 *
1091 * @param ctx read / write interface definitions
1092 * @param val change the values of xl_hm_mode in
1093 * reg CTRL6_C
1094 * @retval interface status (MANDATORY: return 0 -> no Error)
1095 *
1096 */
lsm6dsox_xl_power_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_xl_hm_mode_t val)1097 int32_t lsm6dsox_xl_power_mode_set(const stmdev_ctx_t *ctx,
1098 lsm6dsox_xl_hm_mode_t val)
1099 {
1100 lsm6dsox_ctrl5_c_t ctrl5_c;
1101 lsm6dsox_ctrl6_c_t ctrl6_c;
1102 int32_t ret;
1103
1104 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
1105
1106 if (ret == 0)
1107 {
1108 ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x02U) >> 1;
1109 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
1110 }
1111
1112 if (ret == 0)
1113 {
1114 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
1115 }
1116
1117 if (ret == 0)
1118 {
1119 ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
1120 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
1121 }
1122
1123 return ret;
1124 }
1125
1126 /**
1127 * @brief Accelerometer power mode.[get]
1128 *
1129 * @param ctx read / write interface definitions
1130 * @param val Get the values of xl_hm_mode in reg CTRL6_C
1131 * @retval interface status (MANDATORY: return 0 -> no Error)
1132 *
1133 */
lsm6dsox_xl_power_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_xl_hm_mode_t * val)1134 int32_t lsm6dsox_xl_power_mode_get(const stmdev_ctx_t *ctx,
1135 lsm6dsox_xl_hm_mode_t *val)
1136 {
1137 lsm6dsox_ctrl5_c_t ctrl5_c;
1138 lsm6dsox_ctrl6_c_t ctrl6_c;
1139 int32_t ret;
1140
1141 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
1142
1143 if (ret == 0)
1144 {
1145 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
1146
1147 switch ((ctrl5_c.xl_ulp_en << 1) | ctrl6_c.xl_hm_mode)
1148 {
1149 case LSM6DSOX_HIGH_PERFORMANCE_MD:
1150 *val = LSM6DSOX_HIGH_PERFORMANCE_MD;
1151 break;
1152
1153 case LSM6DSOX_LOW_NORMAL_POWER_MD:
1154 *val = LSM6DSOX_LOW_NORMAL_POWER_MD;
1155 break;
1156
1157 case LSM6DSOX_ULTRA_LOW_POWER_MD:
1158 *val = LSM6DSOX_ULTRA_LOW_POWER_MD;
1159 break;
1160
1161 default:
1162 *val = LSM6DSOX_HIGH_PERFORMANCE_MD;
1163 break;
1164 }
1165 }
1166
1167 return ret;
1168 }
1169
1170 /**
1171 * @brief Operating mode for gyroscope.[set]
1172 *
1173 * @param ctx read / write interface definitions
1174 * @param val change the values of g_hm_mode in reg CTRL7_G
1175 * @retval interface status (MANDATORY: return 0 -> no Error)
1176 *
1177 */
lsm6dsox_gy_power_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_g_hm_mode_t val)1178 int32_t lsm6dsox_gy_power_mode_set(const stmdev_ctx_t *ctx,
1179 lsm6dsox_g_hm_mode_t val)
1180 {
1181 lsm6dsox_ctrl7_g_t reg;
1182 int32_t ret;
1183
1184 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
1185
1186 if (ret == 0)
1187 {
1188 reg.g_hm_mode = (uint8_t)val;
1189 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
1190 }
1191
1192 return ret;
1193 }
1194
1195 /**
1196 * @brief Operating mode for gyroscope.[get]
1197 *
1198 * @param ctx read / write interface definitions
1199 * @param val Get the values of g_hm_mode in reg CTRL7_G
1200 * @retval interface status (MANDATORY: return 0 -> no Error)
1201 *
1202 */
lsm6dsox_gy_power_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_g_hm_mode_t * val)1203 int32_t lsm6dsox_gy_power_mode_get(const stmdev_ctx_t *ctx,
1204 lsm6dsox_g_hm_mode_t *val)
1205 {
1206 lsm6dsox_ctrl7_g_t reg;
1207 int32_t ret;
1208
1209 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
1210
1211 switch (reg.g_hm_mode)
1212 {
1213 case LSM6DSOX_GY_HIGH_PERFORMANCE:
1214 *val = LSM6DSOX_GY_HIGH_PERFORMANCE;
1215 break;
1216
1217 case LSM6DSOX_GY_NORMAL:
1218 *val = LSM6DSOX_GY_NORMAL;
1219 break;
1220
1221 default:
1222 *val = LSM6DSOX_GY_HIGH_PERFORMANCE;
1223 break;
1224 }
1225
1226 return ret;
1227 }
1228
1229 /**
1230 * @brief The STATUS_REG register is read by the primary interface.[get]
1231 *
1232 * @param ctx read / write interface definitions
1233 * @param val register STATUS_REG
1234 * @retval interface status (MANDATORY: return 0 -> no Error)
1235 *
1236 */
lsm6dsox_status_reg_get(const stmdev_ctx_t * ctx,lsm6dsox_status_reg_t * val)1237 int32_t lsm6dsox_status_reg_get(const stmdev_ctx_t *ctx,
1238 lsm6dsox_status_reg_t *val)
1239 {
1240 int32_t ret;
1241
1242 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t *) val, 1);
1243
1244 return ret;
1245 }
1246
1247 /**
1248 * @brief Accelerometer new data available.[get]
1249 *
1250 * @param ctx read / write interface definitions
1251 * @param val change the values of xlda in reg STATUS_REG
1252 * @retval interface status (MANDATORY: return 0 -> no Error)
1253 *
1254 */
lsm6dsox_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1255 int32_t lsm6dsox_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
1256 uint8_t *val)
1257 {
1258 lsm6dsox_status_reg_t reg;
1259 int32_t ret;
1260
1261 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t *)®, 1);
1262 *val = reg.xlda;
1263
1264 return ret;
1265 }
1266
1267 /**
1268 * @brief Gyroscope new data available.[get]
1269 *
1270 * @param ctx read / write interface definitions
1271 * @param val change the values of gda in reg STATUS_REG
1272 * @retval interface status (MANDATORY: return 0 -> no Error)
1273 *
1274 */
lsm6dsox_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1275 int32_t lsm6dsox_gy_flag_data_ready_get(const stmdev_ctx_t *ctx,
1276 uint8_t *val)
1277 {
1278 lsm6dsox_status_reg_t reg;
1279 int32_t ret;
1280
1281 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t *)®, 1);
1282 *val = reg.gda;
1283
1284 return ret;
1285 }
1286
1287 /**
1288 * @brief Temperature new data available.[get]
1289 *
1290 * @param ctx read / write interface definitions
1291 * @param val change the values of tda in reg STATUS_REG
1292 * @retval interface status (MANDATORY: return 0 -> no Error)
1293 *
1294 */
lsm6dsox_temp_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1295 int32_t lsm6dsox_temp_flag_data_ready_get(const stmdev_ctx_t *ctx,
1296 uint8_t *val)
1297 {
1298 lsm6dsox_status_reg_t reg;
1299 int32_t ret;
1300
1301 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG, (uint8_t *)®, 1);
1302 *val = reg.tda;
1303
1304 return ret;
1305 }
1306
1307 /**
1308 * @brief Accelerometer X-axis user offset correction expressed in
1309 * two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1310 * The value must be in the range [-127 127].[set]
1311 *
1312 * @param ctx read / write interface definitions
1313 * @param buff buffer that contains data to write
1314 * @retval interface status (MANDATORY: return 0 -> no Error)
1315 *
1316 */
lsm6dsox_xl_usr_offset_x_set(const stmdev_ctx_t * ctx,uint8_t * buff)1317 int32_t lsm6dsox_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff)
1318 {
1319 int32_t ret;
1320
1321 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_X_OFS_USR, buff, 1);
1322
1323 return ret;
1324 }
1325
1326 /**
1327 * @brief Accelerometer X-axis user offset correction expressed in two’s
1328 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1329 * The value must be in the range [-127 127].[get]
1330 *
1331 * @param ctx read / write interface definitions
1332 * @param buff buffer that stores data read
1333 * @retval interface status (MANDATORY: return 0 -> no Error)
1334 *
1335 */
lsm6dsox_xl_usr_offset_x_get(const stmdev_ctx_t * ctx,uint8_t * buff)1336 int32_t lsm6dsox_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1337 {
1338 int32_t ret;
1339
1340 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_X_OFS_USR, buff, 1);
1341
1342 return ret;
1343 }
1344
1345 /**
1346 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1347 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1348 * The value must be in the range [-127 127].[set]
1349 *
1350 * @param ctx read / write interface definitions
1351 * @param buff buffer that contains data to write
1352 * @retval interface status (MANDATORY: return 0 -> no Error)
1353 *
1354 */
lsm6dsox_xl_usr_offset_y_set(const stmdev_ctx_t * ctx,uint8_t * buff)1355 int32_t lsm6dsox_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff)
1356 {
1357 int32_t ret;
1358
1359 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_Y_OFS_USR, buff, 1);
1360
1361 return ret;
1362 }
1363
1364 /**
1365 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1366 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1367 * The value must be in the range [-127 127].[get]
1368 *
1369 * @param ctx read / write interface definitions
1370 * @param buff buffer that stores data read
1371 * @retval interface status (MANDATORY: return 0 -> no Error)
1372 *
1373 */
lsm6dsox_xl_usr_offset_y_get(const stmdev_ctx_t * ctx,uint8_t * buff)1374 int32_t lsm6dsox_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1375 {
1376 int32_t ret;
1377
1378 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_Y_OFS_USR, buff, 1);
1379
1380 return ret;
1381 }
1382
1383 /**
1384 * @brief Accelerometer Z-axis user offset correction expressed in two’s
1385 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1386 * The value must be in the range [-127 127].[set]
1387 *
1388 * @param ctx read / write interface definitions
1389 * @param buff buffer that contains data to write
1390 * @retval interface status (MANDATORY: return 0 -> no Error)
1391 *
1392 */
lsm6dsox_xl_usr_offset_z_set(const stmdev_ctx_t * ctx,uint8_t * buff)1393 int32_t lsm6dsox_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff)
1394 {
1395 int32_t ret;
1396
1397 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_Z_OFS_USR, buff, 1);
1398
1399 return ret;
1400 }
1401
1402 /**
1403 * @brief Accelerometer Z-axis user offset correction expressed in two’s
1404 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1405 * The value must be in the range [-127 127].[get]
1406 *
1407 * @param ctx read / write interface definitions
1408 * @param buff buffer that stores data read
1409 * @retval interface status (MANDATORY: return 0 -> no Error)
1410 *
1411 */
lsm6dsox_xl_usr_offset_z_get(const stmdev_ctx_t * ctx,uint8_t * buff)1412 int32_t lsm6dsox_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1413 {
1414 int32_t ret;
1415
1416 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_Z_OFS_USR, buff, 1);
1417
1418 return ret;
1419 }
1420
1421 /**
1422 * @brief Enables user offset on out.[set]
1423 *
1424 * @param ctx read / write interface definitions
1425 * @param val change the values of usr_off_on_out in reg CTRL7_G
1426 * @retval interface status (MANDATORY: return 0 -> no Error)
1427 *
1428 */
lsm6dsox_xl_usr_offset_set(const stmdev_ctx_t * ctx,uint8_t val)1429 int32_t lsm6dsox_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val)
1430 {
1431 lsm6dsox_ctrl7_g_t reg;
1432 int32_t ret;
1433
1434 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
1435
1436 if (ret == 0)
1437 {
1438 reg.usr_off_on_out = val;
1439 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
1440 }
1441
1442 return ret;
1443 }
1444
1445 /**
1446 * @brief User offset on out flag.[get]
1447 *
1448 * @param ctx read / write interface definitions
1449 * @param val values of usr_off_on_out in reg CTRL7_G
1450 * @retval interface status (MANDATORY: return 0 -> no Error)
1451 *
1452 */
lsm6dsox_xl_usr_offset_get(const stmdev_ctx_t * ctx,uint8_t * val)1453 int32_t lsm6dsox_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val)
1454 {
1455 lsm6dsox_ctrl7_g_t reg;
1456 int32_t ret;
1457
1458 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
1459 *val = reg.usr_off_on_out;
1460
1461 return ret;
1462 }
1463
1464 /**
1465 * @}
1466 *
1467 */
1468
1469 /**
1470 * @defgroup LSM6DSOX_Timestamp
1471 * @brief This section groups all the functions that manage the
1472 * timestamp generation.
1473 * @{
1474 *
1475 */
1476
1477 /**
1478 * @brief Reset timestamp counter.[set]
1479 *
1480 * @param ctx Read / write interface definitions.(ptr)
1481 * @retval Interface status (MANDATORY: return 0 -> no Error)
1482 *
1483 */
lsm6dsox_timestamp_rst(const stmdev_ctx_t * ctx)1484 int32_t lsm6dsox_timestamp_rst(const stmdev_ctx_t *ctx)
1485 {
1486 uint8_t rst_val = 0xAA;
1487 return lsm6dsox_write_reg(ctx, LSM6DSOX_TIMESTAMP2, &rst_val, 1);
1488 }
1489
1490 /**
1491 * @brief Enables timestamp counter.[set]
1492 *
1493 * @param ctx read / write interface definitions
1494 * @param val change the values of timestamp_en in reg CTRL10_C
1495 * @retval interface status (MANDATORY: return 0 -> no Error)
1496 *
1497 */
lsm6dsox_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)1498 int32_t lsm6dsox_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
1499 {
1500 lsm6dsox_ctrl10_c_t reg;
1501 int32_t ret;
1502
1503 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t *)®, 1);
1504
1505 if (ret == 0)
1506 {
1507 reg.timestamp_en = val;
1508 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t *)®, 1);
1509 }
1510
1511 return ret;
1512 }
1513
1514 /**
1515 * @brief Enables timestamp counter.[get]
1516 *
1517 * @param ctx read / write interface definitions
1518 * @param val change the values of timestamp_en in reg CTRL10_C
1519 * @retval interface status (MANDATORY: return 0 -> no Error)
1520 *
1521 */
lsm6dsox_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)1522 int32_t lsm6dsox_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
1523 {
1524 lsm6dsox_ctrl10_c_t reg;
1525 int32_t ret;
1526
1527 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL10_C, (uint8_t *)®, 1);
1528 *val = reg.timestamp_en;
1529
1530 return ret;
1531 }
1532
1533 /**
1534 * @brief Timestamp first data output register (r).
1535 * The value is expressed as a 32-bit word and the bit
1536 * resolution is 25 μs.[get]
1537 *
1538 * @param ctx read / write interface definitions
1539 * @param buff buffer that stores data read
1540 * @retval interface status (MANDATORY: return 0 -> no Error)
1541 *
1542 */
lsm6dsox_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)1543 int32_t lsm6dsox_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
1544 {
1545 uint8_t buff[4];
1546 int32_t ret;
1547
1548 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TIMESTAMP0, buff, 4);
1549 *val = buff[3];
1550 *val = (*val * 256U) + buff[2];
1551 *val = (*val * 256U) + buff[1];
1552 *val = (*val * 256U) + buff[0];
1553
1554 return ret;
1555 }
1556
1557 /**
1558 * @}
1559 *
1560 */
1561
1562 /**
1563 * @defgroup LSM6DSOX_Data output
1564 * @brief This section groups all the data output functions.
1565 * @{
1566 *
1567 */
1568
1569 /**
1570 * @brief Circular burst-mode (rounding) read of the output
1571 * registers.[set]
1572 *
1573 * @param ctx read / write interface definitions
1574 * @param val change the values of rounding in reg CTRL5_C
1575 * @retval interface status (MANDATORY: return 0 -> no Error)
1576 *
1577 */
lsm6dsox_rounding_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_rounding_t val)1578 int32_t lsm6dsox_rounding_mode_set(const stmdev_ctx_t *ctx,
1579 lsm6dsox_rounding_t val)
1580 {
1581 lsm6dsox_ctrl5_c_t reg;
1582 int32_t ret;
1583
1584 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
1585
1586 if (ret == 0)
1587 {
1588 reg.rounding = (uint8_t)val;
1589 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
1590 }
1591
1592 return ret;
1593 }
1594
1595 /**
1596 * @brief Gyroscope UI chain full-scale selection.[get]
1597 *
1598 * @param ctx read / write interface definitions
1599 * @param val Get the values of rounding in reg CTRL5_C
1600 * @retval interface status (MANDATORY: return 0 -> no Error)
1601 *
1602 */
lsm6dsox_rounding_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_rounding_t * val)1603 int32_t lsm6dsox_rounding_mode_get(const stmdev_ctx_t *ctx,
1604 lsm6dsox_rounding_t *val)
1605 {
1606 lsm6dsox_ctrl5_c_t reg;
1607 int32_t ret;
1608
1609 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
1610
1611 switch (reg.rounding)
1612 {
1613 case LSM6DSOX_NO_ROUND:
1614 *val = LSM6DSOX_NO_ROUND;
1615 break;
1616
1617 case LSM6DSOX_ROUND_XL:
1618 *val = LSM6DSOX_ROUND_XL;
1619 break;
1620
1621 case LSM6DSOX_ROUND_GY:
1622 *val = LSM6DSOX_ROUND_GY;
1623 break;
1624
1625 case LSM6DSOX_ROUND_GY_XL:
1626 *val = LSM6DSOX_ROUND_GY_XL;
1627 break;
1628
1629 default:
1630 *val = LSM6DSOX_NO_ROUND;
1631 break;
1632 }
1633
1634 return ret;
1635 }
1636
1637 /**
1638 * @brief rounding_on_status: [set] Source register rounding function in
1639 * ALL_INT_SRC (1Ah), WAKE_UP_SRC(1Bh),
1640 * TAP_SRC (1Ch), D6D_SRC (1Dh),
1641 * STATUS_REG (1Eh) and
1642 * EMB_FUNC_STATUS_MAINPAGE(35h),
1643 * FSM_STATUS_A_MAINPAGE (36h),
1644 * FSM_STATUS_B_MAINPAGE (37h),
1645 * MLC_STATUS_MAINPAGE (38h),
1646 * STATUS_MASTER_MAINPAGE (39h),
1647 * FIFO_STATUS1 (3Ah), FIFO_STATUS2(3Bh).
1648 *
1649 * @param ctx read / write interface definitions
1650 * @param lsm6dsox_rounding_status_t: change the values of rounding_status
1651 * in reg CTRL7_G
1652 * @retval interface status (MANDATORY: return 0 -> no Error)
1653 *
1654 */
lsm6dsox_rounding_on_status_set(const stmdev_ctx_t * ctx,lsm6dsox_rounding_status_t val)1655 int32_t lsm6dsox_rounding_on_status_set(const stmdev_ctx_t *ctx,
1656 lsm6dsox_rounding_status_t val)
1657 {
1658 lsm6dsox_ctrl5_c_t reg;
1659 int32_t ret;
1660
1661 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
1662
1663 if (ret == 0)
1664 {
1665 reg.rounding_status = (uint8_t)val;
1666 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
1667 }
1668
1669 return ret;
1670 }
1671
1672 /**
1673 * @brief rounding_on_status: [get] Source register rounding function in
1674 * ALL_INT_SRC (1Ah), WAKE_UP_SRC(1Bh),
1675 * TAP_SRC (1Ch), D6D_SRC (1Dh),
1676 * STATUS_REG (1Eh) and
1677 * EMB_FUNC_STATUS_MAINPAGE(35h),
1678 * FSM_STATUS_A_MAINPAGE (36h),
1679 * FSM_STATUS_B_MAINPAGE (37h),
1680 * MLC_STATUS_MAINPAGE (38h),
1681 * STATUS_MASTER_MAINPAGE (39h),
1682 * FIFO_STATUS1 (3Ah), FIFO_STATUS2(3Bh).
1683 *
1684 * @param ctx read / write interface definitions
1685 * @param lsm6dsox_rounding_status_t: Get the values of rounding_status
1686 * in reg CTRL7_G
1687 * @retval interface status (MANDATORY: return 0 -> no Error)
1688 *
1689 */
lsm6dsox_rounding_on_status_get(const stmdev_ctx_t * ctx,lsm6dsox_rounding_status_t * val)1690 int32_t lsm6dsox_rounding_on_status_get(const stmdev_ctx_t *ctx,
1691 lsm6dsox_rounding_status_t *val)
1692 {
1693 lsm6dsox_ctrl5_c_t reg;
1694 int32_t ret;
1695
1696 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
1697
1698 switch (reg.rounding_status)
1699 {
1700 case LSM6DSOX_STAT_RND_DISABLE:
1701 *val = LSM6DSOX_STAT_RND_DISABLE;
1702 break;
1703
1704 case LSM6DSOX_STAT_RND_ENABLE:
1705 *val = LSM6DSOX_STAT_RND_ENABLE;
1706 break;
1707
1708 default:
1709 *val = LSM6DSOX_STAT_RND_DISABLE;
1710 break;
1711 }
1712
1713 return ret;
1714 }
1715
1716 /**
1717 * @brief Temperature data output register (r).
1718 * L and H registers together express a 16-bit word in two’s
1719 * complement.[get]
1720 *
1721 * @param ctx read / write interface definitions
1722 * @param buff buffer that stores data read
1723 * @retval interface status (MANDATORY: return 0 -> no Error)
1724 *
1725 */
lsm6dsox_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1726 int32_t lsm6dsox_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1727 {
1728 uint8_t buff[2];
1729 int32_t ret;
1730
1731 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUT_TEMP_L, buff, 2);
1732 *val = (int16_t)buff[1];
1733 *val = (*val * 256) + (int16_t)buff[0];
1734
1735 return ret;
1736 }
1737
1738 /**
1739 * @brief Angular rate sensor. The value is expressed as a 16-bit
1740 * word in two’s complement.[get]
1741 *
1742 * @param ctx read / write interface definitions
1743 * @param buff buffer that stores data read
1744 * @retval interface status (MANDATORY: return 0 -> no Error)
1745 *
1746 */
lsm6dsox_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1747 int32_t lsm6dsox_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1748 {
1749 uint8_t buff[6];
1750 int32_t ret;
1751
1752 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUTX_L_G, buff, 6);
1753 val[0] = (int16_t)buff[1];
1754 val[0] = (val[0] * 256) + (int16_t)buff[0];
1755 val[1] = (int16_t)buff[3];
1756 val[1] = (val[1] * 256) + (int16_t)buff[2];
1757 val[2] = (int16_t)buff[5];
1758 val[2] = (val[2] * 256) + (int16_t)buff[4];
1759
1760 return ret;
1761 }
1762
1763 /**
1764 * @brief Linear acceleration output register.
1765 * The value is expressed as a 16-bit word in two’s complement.[get]
1766 *
1767 * @param ctx read / write interface definitions
1768 * @param buff buffer that stores data read
1769 * @retval interface status (MANDATORY: return 0 -> no Error)
1770 *
1771 */
lsm6dsox_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1772 int32_t lsm6dsox_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1773 {
1774 uint8_t buff[6];
1775 int32_t ret;
1776
1777 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUTX_L_A, buff, 6);
1778 val[0] = (int16_t)buff[1];
1779 val[0] = (val[0] * 256) + (int16_t)buff[0];
1780 val[1] = (int16_t)buff[3];
1781 val[1] = (val[1] * 256) + (int16_t)buff[2];
1782 val[2] = (int16_t)buff[5];
1783 val[2] = (val[2] * 256) + (int16_t)buff[4];
1784
1785 return ret;
1786 }
1787
1788 /**
1789 * @brief FIFO data output [get]
1790 *
1791 * @param ctx read / write interface definitions
1792 * @param buff buffer that stores data read
1793 * @retval interface status (MANDATORY: return 0 -> no Error)
1794 *
1795 */
lsm6dsox_fifo_out_raw_get(const stmdev_ctx_t * ctx,uint8_t * buff)1796 int32_t lsm6dsox_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1797 {
1798 int32_t ret;
1799
1800 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_DATA_OUT_X_L, buff, 6);
1801
1802 return ret;
1803 }
1804
1805 /**
1806 * @brief ois_angular_rate_raw: [get] OIS angular rate sensor.
1807 * The value is expressed as a
1808 * 16-bit word in two’s complement.
1809 *
1810 * @param ctx read / write interface definitions
1811 * @param uint8_t * : buffer that stores data read
1812 * @retval interface status (MANDATORY: return 0 -> no Error)
1813 *
1814 */
lsm6dsox_ois_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1815 int32_t lsm6dsox_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx,
1816 int16_t *val)
1817 {
1818 uint8_t buff[6];
1819 int32_t ret;
1820
1821 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_G_OIS, buff, 6);
1822 val[0] = (int16_t)buff[1];
1823 val[0] = (val[0] * 256) + (int16_t)buff[0];
1824 val[1] = (int16_t)buff[3];
1825 val[1] = (val[1] * 256) + (int16_t)buff[2];
1826 val[2] = (int16_t)buff[5];
1827 val[2] = (val[2] * 256) + (int16_t)buff[4];
1828
1829 return ret;
1830 }
1831
1832 /**
1833 * @brief ois_acceleration_raw: [get] OIS Linear acceleration output register.
1834 * The value is expressed as a
1835 * 16-bit word in two’s complement.
1836 *
1837 * @param ctx read / write interface definitions
1838 * @param uint8_t * : buffer that stores data read
1839 * @retval interface status (MANDATORY: return 0 -> no Error)
1840 *
1841 */
lsm6dsox_ois_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1842 int32_t lsm6dsox_ois_acceleration_raw_get(const stmdev_ctx_t *ctx,
1843 int16_t *val)
1844 {
1845 uint8_t buff[6];
1846 int32_t ret;
1847
1848 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_A_OIS, buff, 6);
1849 val[0] = (int16_t)buff[1];
1850 val[0] = (val[0] * 256) + (int16_t)buff[0];
1851 val[1] = (int16_t)buff[3];
1852 val[1] = (val[1] * 256) + (int16_t)buff[2];
1853 val[2] = (int16_t)buff[5];
1854 val[2] = (val[2] * 256) + (int16_t)buff[4];
1855
1856 return ret;
1857 }
1858
1859 /**
1860 * @brief aux_temperature_raw: [get] Temperature from auxiliary
1861 * interface.
1862 * The value is expressed as a
1863 * 16-bit word in two’s complement.
1864 *
1865 * @param ctx read / write interface definitions
1866 * @param uint8_t * : buffer that stores data read
1867 * @retval interface status (MANDATORY: return 0 -> no Error)
1868 *
1869 */
lsm6dsox_aux_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1870 int32_t lsm6dsox_aux_temperature_raw_get(const stmdev_ctx_t *ctx,
1871 int16_t *val)
1872 {
1873 uint8_t buff[2];
1874 int32_t ret;
1875
1876 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUT_TEMP_L, buff, 2);
1877 *val = (int16_t)buff[1];
1878 *val = (*val * 256) + (int16_t)buff[0];
1879
1880 return ret;
1881 }
1882
1883 /**
1884 * @brief aux_ois_angular_rate_raw: [get] OIS angular rate sensor from
1885 * auxiliary interface.
1886 * The value is expressed as a
1887 * 16-bit word in two’s complement.
1888 *
1889 * @param ctx read / write interface definitions
1890 * @param uint8_t * : buffer that stores data read
1891 * @retval interface status (MANDATORY: return 0 -> no Error)
1892 *
1893 */
lsm6dsox_aux_ois_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1894 int32_t lsm6dsox_aux_ois_angular_rate_raw_get(const stmdev_ctx_t *ctx,
1895 int16_t *val)
1896 {
1897 uint8_t buff[6];
1898 int32_t ret;
1899
1900 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUTX_L_G_OIS, buff, 6);
1901 val[0] = (int16_t)buff[1];
1902 val[0] = (val[0] * 256) + (int16_t)buff[0];
1903 val[1] = (int16_t)buff[3];
1904 val[1] = (val[1] * 256) + (int16_t)buff[2];
1905 val[2] = (int16_t)buff[5];
1906 val[2] = (val[2] * 256) + (int16_t)buff[4];
1907
1908 return ret;
1909 }
1910
1911 /**
1912 * @brief aux_ois_acceleration_raw: [get] OIS linear acceleration output
1913 * register from auxiliary interface.
1914 * The value is expressed as a
1915 * 16-bit word in two’s complement.
1916 *
1917 * @param ctx read / write interface definitions
1918 * @param uint8_t * : buffer that stores data read
1919 * @retval interface status (MANDATORY: return 0 -> no Error)
1920 *
1921 */
lsm6dsox_aux_ois_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1922 int32_t lsm6dsox_aux_ois_acceleration_raw_get(const stmdev_ctx_t *ctx,
1923 int16_t *val)
1924 {
1925 uint8_t buff[6];
1926 int32_t ret;
1927
1928 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_OUTX_L_A_OIS, buff, 6);
1929 val[0] = (int16_t)buff[1];
1930 val[0] = (val[0] * 256) + (int16_t)buff[0];
1931 val[1] = (int16_t)buff[3];
1932 val[1] = (val[1] * 256) + (int16_t)buff[2];
1933 val[2] = (int16_t)buff[5];
1934 val[2] = (val[2] * 256) + (int16_t)buff[4];
1935
1936 return ret;
1937 }
1938
1939 /**
1940 * @brief Step counter output register.[get]
1941 *
1942 * @param ctx read / write interface definitions
1943 * @param buff buffer that stores data read
1944 * @retval interface status (MANDATORY: return 0 -> no Error)
1945 *
1946 */
lsm6dsox_number_of_steps_get(const stmdev_ctx_t * ctx,uint16_t * val)1947 int32_t lsm6dsox_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val)
1948 {
1949 uint8_t buff[2];
1950 int32_t ret;
1951
1952 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
1953
1954 if (ret == 0)
1955 {
1956 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STEP_COUNTER_L, buff, 2);
1957 *val = buff[1];
1958 *val = (*val * 256U) + buff[0];
1959 }
1960
1961 if (ret == 0)
1962 {
1963 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
1964 }
1965
1966 return ret;
1967 }
1968
1969 /**
1970 * @brief Reset step counter register.[get]
1971 *
1972 * @param ctx read / write interface definitions
1973 * @retval interface status (MANDATORY: return 0 -> no Error)
1974 *
1975 */
lsm6dsox_steps_reset(const stmdev_ctx_t * ctx)1976 int32_t lsm6dsox_steps_reset(const stmdev_ctx_t *ctx)
1977 {
1978 lsm6dsox_emb_func_src_t reg;
1979 int32_t ret;
1980
1981 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
1982
1983 if (ret == 0)
1984 {
1985 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_SRC, (uint8_t *)®, 1);
1986 }
1987
1988 if (ret == 0)
1989 {
1990 reg.pedo_rst_step = PROPERTY_ENABLE;
1991 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_SRC, (uint8_t *)®, 1);
1992 }
1993
1994 if (ret == 0)
1995 {
1996 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
1997 }
1998
1999 return ret;
2000 }
2001
2002 /**
2003 * @brief prgsens_out: [get] Output value of all MLCx decision trees.
2004 *
2005 * @param ctx_t *ctx: read / write interface definitions
2006 * @param uint8_t * : buffer that stores data read
2007 * @retval interface status (MANDATORY: return 0 -> no Error)
2008 *
2009 */
lsm6dsox_mlc_out_get(const stmdev_ctx_t * ctx,uint8_t * buff)2010 int32_t lsm6dsox_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff)
2011 {
2012 int32_t ret;
2013
2014 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
2015
2016 if (ret == 0)
2017 {
2018 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC0_SRC, buff, 8);
2019 }
2020
2021 if (ret == 0)
2022 {
2023 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
2024 }
2025
2026 return ret;
2027 }
2028
2029 /**
2030 * @}
2031 *
2032 */
2033
2034 /**
2035 * @defgroup LSM6DSOX_common
2036 * @brief This section groups common useful functions.
2037 * @{
2038 *
2039 */
2040
2041 /**
2042 * @brief Difference in percentage of the effective ODR(and timestamp rate)
2043 * with respect to the typical.
2044 * Step: 0.15%. 8-bit format, 2's complement.[set]
2045 *
2046 * @param ctx read / write interface definitions
2047 * @param val change the values of freq_fine in reg
2048 * INTERNAL_FREQ_FINE
2049 * @retval interface status (MANDATORY: return 0 -> no Error)
2050 *
2051 */
lsm6dsox_odr_cal_reg_set(const stmdev_ctx_t * ctx,uint8_t val)2052 int32_t lsm6dsox_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val)
2053 {
2054 lsm6dsox_internal_freq_fine_t reg;
2055 int32_t ret;
2056
2057 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE,
2058 (uint8_t *)®, 1);
2059
2060 if (ret == 0)
2061 {
2062 reg.freq_fine = val;
2063 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE,
2064 (uint8_t *)®, 1);
2065 }
2066
2067 return ret;
2068 }
2069
2070 /**
2071 * @brief Difference in percentage of the effective ODR(and timestamp rate)
2072 * with respect to the typical.
2073 * Step: 0.15%. 8-bit format, 2's complement.[get]
2074 *
2075 * @param ctx read / write interface definitions
2076 * @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE
2077 * @retval interface status (MANDATORY: return 0 -> no Error)
2078 *
2079 */
lsm6dsox_odr_cal_reg_get(const stmdev_ctx_t * ctx,uint8_t * val)2080 int32_t lsm6dsox_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val)
2081 {
2082 lsm6dsox_internal_freq_fine_t reg;
2083 int32_t ret;
2084
2085 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INTERNAL_FREQ_FINE,
2086 (uint8_t *)®, 1);
2087 *val = reg.freq_fine;
2088
2089 return ret;
2090 }
2091
2092
2093 /**
2094 * @brief Enable access to the embedded functions/sensor
2095 * hub configuration registers.[set]
2096 *
2097 * @param ctx read / write interface definitions
2098 * @param val change the values of reg_access in
2099 * reg FUNC_CFG_ACCESS
2100 * @retval interface status (MANDATORY: return 0 -> no Error)
2101 *
2102 */
lsm6dsox_mem_bank_set(const stmdev_ctx_t * ctx,lsm6dsox_reg_access_t val)2103 int32_t lsm6dsox_mem_bank_set(const stmdev_ctx_t *ctx,
2104 lsm6dsox_reg_access_t val)
2105 {
2106 lsm6dsox_func_cfg_access_t reg;
2107 int32_t ret;
2108
2109 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
2110 (uint8_t *)®, 1);
2111
2112 if (ret == 0)
2113 {
2114 reg.reg_access = (uint8_t)val;
2115 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
2116 (uint8_t *)®, 1);
2117 }
2118
2119 return ret;
2120 }
2121
2122 /**
2123 * @brief Enable access to the embedded functions/sensor
2124 * hub configuration registers.[get]
2125 *
2126 * @param ctx read / write interface definitions
2127 * @param val Get the values of reg_access in
2128 * reg FUNC_CFG_ACCESS
2129 * @retval interface status (MANDATORY: return 0 -> no Error)
2130 *
2131 */
lsm6dsox_mem_bank_get(const stmdev_ctx_t * ctx,lsm6dsox_reg_access_t * val)2132 int32_t lsm6dsox_mem_bank_get(const stmdev_ctx_t *ctx,
2133 lsm6dsox_reg_access_t *val)
2134 {
2135 lsm6dsox_func_cfg_access_t reg;
2136 int32_t ret;
2137
2138 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
2139 (uint8_t *)®, 1);
2140
2141 switch (reg.reg_access)
2142 {
2143 case LSM6DSOX_USER_BANK:
2144 *val = LSM6DSOX_USER_BANK;
2145 break;
2146
2147 case LSM6DSOX_SENSOR_HUB_BANK:
2148 *val = LSM6DSOX_SENSOR_HUB_BANK;
2149 break;
2150
2151 case LSM6DSOX_EMBEDDED_FUNC_BANK:
2152 *val = LSM6DSOX_EMBEDDED_FUNC_BANK;
2153 break;
2154
2155 default:
2156 *val = LSM6DSOX_USER_BANK;
2157 break;
2158 }
2159
2160 return ret;
2161 }
2162
2163 /**
2164 * @brief Write a line(byte) in a page.[set]
2165 *
2166 * @param ctx read / write interface definitions
2167 * @param uint8_t address: page line address
2168 * @param val value to write
2169 * @retval interface status (MANDATORY: return 0 -> no Error)
2170 *
2171 */
lsm6dsox_ln_pg_write_byte(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * val)2172 int32_t lsm6dsox_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address,
2173 uint8_t *val)
2174 {
2175 lsm6dsox_page_rw_t page_rw;
2176 lsm6dsox_page_sel_t page_sel;
2177 lsm6dsox_page_address_t page_address;
2178 int32_t ret;
2179
2180 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
2181
2182 if (ret == 0)
2183 {
2184 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
2185 }
2186
2187 if (ret == 0)
2188 {
2189 page_rw.page_rw = 0x02; /* page_write enable */
2190 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
2191 }
2192
2193 if (ret == 0)
2194 {
2195 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t *) &page_sel, 1);
2196 }
2197
2198 if (ret == 0)
2199 {
2200 page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
2201 page_sel.not_used_01 = 1;
2202 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL,
2203 (uint8_t *) &page_sel, 1);
2204 }
2205
2206 if (ret == 0)
2207 {
2208 page_address.page_addr = (uint8_t)address & 0xFFU;
2209 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS,
2210 (uint8_t *)&page_address, 1);
2211 }
2212
2213 if (ret == 0)
2214 {
2215 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_VALUE, val, 1);
2216 }
2217
2218 if (ret == 0)
2219 {
2220 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
2221 }
2222
2223 if (ret == 0)
2224 {
2225 page_rw.page_rw = 0x00; /* page_write disable */
2226 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
2227 }
2228
2229 if (ret == 0)
2230 {
2231 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
2232 }
2233
2234 return ret;
2235 }
2236
2237 /**
2238 * @brief Write buffer in a page.[set]
2239 *
2240 * @param ctx read / write interface definitions
2241 * @param uint8_t address: page line address
2242 * @param uint8_t *buf: buffer to write
2243 * @param uint8_t len: buffer len
2244 * @retval interface status (MANDATORY: return 0 -> no Error)
2245 *
2246 */
lsm6dsox_ln_pg_write(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)2247 int32_t lsm6dsox_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address,
2248 uint8_t *buf, uint8_t len)
2249 {
2250 lsm6dsox_page_rw_t page_rw;
2251 lsm6dsox_page_sel_t page_sel;
2252 lsm6dsox_page_address_t page_address;
2253 int32_t ret;
2254
2255 uint8_t msb, lsb;
2256 uint8_t i ;
2257 msb = ((uint8_t)(address >> 8) & 0x0FU);
2258 lsb = (uint8_t)address & 0xFFU;
2259 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
2260
2261 if (ret == 0)
2262 {
2263 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
2264 }
2265
2266 if (ret == 0)
2267 {
2268 page_rw.page_rw = 0x02; /* page_write enable*/
2269 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
2270 }
2271
2272 if (ret == 0)
2273 {
2274 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t *) &page_sel, 1);
2275 }
2276
2277 if (ret == 0)
2278 {
2279 page_sel.page_sel = msb;
2280 page_sel.not_used_01 = 1;
2281 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL,
2282 (uint8_t *) &page_sel, 1);
2283 }
2284
2285 if (ret == 0)
2286 {
2287 page_address.page_addr = lsb;
2288 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS,
2289 (uint8_t *)&page_address, 1);
2290 }
2291
2292 if (ret == 0)
2293 {
2294 for (i = 0; ((i < len) && (ret == 0)); i++)
2295 {
2296 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_VALUE, &buf[i], 1);
2297 lsb++;
2298
2299 /* Check if page wrap */
2300 if ((lsb == 0x00U) && (ret == 0))
2301 {
2302 msb++;
2303 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t *)&page_sel, 1);
2304
2305 if (ret == 0)
2306 {
2307 page_sel.page_sel = msb;
2308 page_sel.not_used_01 = 1;
2309 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL,
2310 (uint8_t *)&page_sel, 1);
2311 }
2312 }
2313 }
2314 }
2315
2316 page_sel.page_sel = 0;
2317 page_sel.not_used_01 = 1;
2318 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL,
2319 (uint8_t *) &page_sel, 1);
2320
2321 if (ret == 0)
2322 {
2323 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
2324 }
2325
2326 if (ret == 0)
2327 {
2328 page_rw.page_rw = 0x00; /* page_write disable */
2329 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
2330 }
2331
2332 if (ret == 0)
2333 {
2334 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
2335 }
2336
2337 return ret;
2338 }
2339
2340 /**
2341 * @brief Read a line(byte) in a page.[get]
2342 *
2343 * @param ctx read / write interface definitions
2344 * @param uint8_t address: page line address
2345 * @param val read value
2346 * @retval interface status (MANDATORY: return 0 -> no Error)
2347 *
2348 */
lsm6dsox_ln_pg_read_byte(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * val)2349 int32_t lsm6dsox_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t address,
2350 uint8_t *val)
2351 {
2352 lsm6dsox_page_rw_t page_rw;
2353 lsm6dsox_page_sel_t page_sel;
2354 lsm6dsox_page_address_t page_address;
2355 int32_t ret;
2356
2357 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
2358
2359 if (ret == 0)
2360 {
2361 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
2362 }
2363
2364 if (ret == 0)
2365 {
2366 page_rw.page_rw = 0x01; /* page_read enable*/
2367 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
2368 }
2369
2370 if (ret == 0)
2371 {
2372 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_SEL, (uint8_t *) &page_sel, 1);
2373 }
2374
2375 if (ret == 0)
2376 {
2377 page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
2378 page_sel.not_used_01 = 1;
2379 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_SEL,
2380 (uint8_t *) &page_sel, 1);
2381 }
2382
2383 if (ret == 0)
2384 {
2385 page_address.page_addr = (uint8_t)address & 0x00FFU;
2386 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_ADDRESS,
2387 (uint8_t *)&page_address, 1);
2388 }
2389
2390 if (ret == 0)
2391 {
2392 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_VALUE, val, 1);
2393 }
2394
2395 if (ret == 0)
2396 {
2397 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
2398 }
2399
2400 if (ret == 0)
2401 {
2402 page_rw.page_rw = 0x00; /* page_read disable */
2403 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
2404 }
2405
2406 if (ret == 0)
2407 {
2408 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
2409 }
2410
2411 return ret;
2412 }
2413
2414 /**
2415 * @brief Data-ready pulsed / letched mode.[set]
2416 *
2417 * @param ctx read / write interface definitions
2418 * @param val change the values of
2419 * dataready_pulsed in
2420 * reg COUNTER_BDR_REG1
2421 * @retval interface status (MANDATORY: return 0 -> no Error)
2422 *
2423 */
lsm6dsox_data_ready_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_dataready_pulsed_t val)2424 int32_t lsm6dsox_data_ready_mode_set(const stmdev_ctx_t *ctx,
2425 lsm6dsox_dataready_pulsed_t val)
2426 {
2427 lsm6dsox_counter_bdr_reg1_t reg;
2428 int32_t ret;
2429
2430 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
2431 (uint8_t *)®, 1);
2432
2433 if (ret == 0)
2434 {
2435 reg.dataready_pulsed = (uint8_t)val;
2436 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
2437 (uint8_t *)®, 1);
2438 }
2439
2440 return ret;
2441 }
2442
2443 /**
2444 * @brief Data-ready pulsed / letched mode.[get]
2445 *
2446 * @param ctx read / write interface definitions
2447 * @param val Get the values of
2448 * dataready_pulsed in
2449 * reg COUNTER_BDR_REG1
2450 * @retval interface status (MANDATORY: return 0 -> no Error)
2451 *
2452 */
lsm6dsox_data_ready_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_dataready_pulsed_t * val)2453 int32_t lsm6dsox_data_ready_mode_get(const stmdev_ctx_t *ctx,
2454 lsm6dsox_dataready_pulsed_t *val)
2455 {
2456 lsm6dsox_counter_bdr_reg1_t reg;
2457 int32_t ret;
2458
2459 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
2460 (uint8_t *)®, 1);
2461
2462 switch (reg.dataready_pulsed)
2463 {
2464 case LSM6DSOX_DRDY_LATCHED:
2465 *val = LSM6DSOX_DRDY_LATCHED;
2466 break;
2467
2468 case LSM6DSOX_DRDY_PULSED:
2469 *val = LSM6DSOX_DRDY_PULSED;
2470 break;
2471
2472 default:
2473 *val = LSM6DSOX_DRDY_LATCHED;
2474 break;
2475 }
2476
2477 return ret;
2478 }
2479
2480 /**
2481 * @brief Device "Who am I".[get]
2482 *
2483 * @param ctx read / write interface definitions
2484 * @param buff buffer that stores data read
2485 * @retval interface status (MANDATORY: return 0 -> no Error)
2486 *
2487 */
lsm6dsox_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)2488 int32_t lsm6dsox_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
2489 {
2490 int32_t ret;
2491
2492 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WHO_AM_I, buff, 1);
2493
2494 return ret;
2495 }
2496
2497 /**
2498 * @brief Software reset. Restore the default values
2499 * in user registers[set]
2500 *
2501 * @param ctx read / write interface definitions
2502 * @param val change the values of sw_reset in reg CTRL3_C
2503 * @retval interface status (MANDATORY: return 0 -> no Error)
2504 *
2505 */
lsm6dsox_reset_set(const stmdev_ctx_t * ctx,uint8_t val)2506 int32_t lsm6dsox_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
2507 {
2508 lsm6dsox_ctrl3_c_t reg;
2509 int32_t ret;
2510
2511 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
2512
2513 if (ret == 0)
2514 {
2515 reg.sw_reset = val;
2516 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
2517 }
2518
2519 return ret;
2520 }
2521
2522 /**
2523 * @brief Software reset. Restore the default values in user registers.[get]
2524 *
2525 * @param ctx read / write interface definitions
2526 * @param val change the values of sw_reset in reg CTRL3_C
2527 * @retval interface status (MANDATORY: return 0 -> no Error)
2528 *
2529 */
lsm6dsox_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)2530 int32_t lsm6dsox_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
2531 {
2532 lsm6dsox_ctrl3_c_t reg;
2533 int32_t ret;
2534
2535 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
2536 *val = reg.sw_reset;
2537
2538 return ret;
2539 }
2540
2541 /**
2542 * @brief Register address automatically incremented during a multiple byte
2543 * access with a serial interface.[set]
2544 *
2545 * @param ctx read / write interface definitions
2546 * @param val change the values of if_inc in reg CTRL3_C
2547 * @retval interface status (MANDATORY: return 0 -> no Error)
2548 *
2549 */
lsm6dsox_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)2550 int32_t lsm6dsox_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
2551 {
2552 lsm6dsox_ctrl3_c_t reg;
2553 int32_t ret;
2554
2555 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
2556
2557 if (ret == 0)
2558 {
2559 reg.if_inc = val;
2560 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
2561 }
2562
2563 return ret;
2564 }
2565
2566 /**
2567 * @brief Register address automatically incremented during a multiple byte
2568 * access with a serial interface.[get]
2569 *
2570 * @param ctx read / write interface definitions
2571 * @param val change the values of if_inc in reg CTRL3_C
2572 * @retval interface status (MANDATORY: return 0 -> no Error)
2573 *
2574 */
lsm6dsox_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)2575 int32_t lsm6dsox_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
2576 {
2577 lsm6dsox_ctrl3_c_t reg;
2578 int32_t ret;
2579
2580 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
2581 *val = reg.if_inc;
2582
2583 return ret;
2584 }
2585
2586 /**
2587 * @brief Reboot memory content. Reload the calibration parameters.[set]
2588 *
2589 * @param ctx read / write interface definitions
2590 * @param val change the values of boot in reg CTRL3_C
2591 * @retval interface status (MANDATORY: return 0 -> no Error)
2592 *
2593 */
lsm6dsox_boot_set(const stmdev_ctx_t * ctx,uint8_t val)2594 int32_t lsm6dsox_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
2595 {
2596 lsm6dsox_ctrl3_c_t reg;
2597 int32_t ret;
2598
2599 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
2600
2601 if (ret == 0)
2602 {
2603 reg.boot = val;
2604 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
2605 }
2606
2607 return ret;
2608 }
2609
2610 /**
2611 * @brief Reboot memory content. Reload the calibration parameters.[get]
2612 *
2613 * @param ctx read / write interface definitions
2614 * @param val change the values of boot in reg CTRL3_C
2615 * @retval interface status (MANDATORY: return 0 -> no Error)
2616 *
2617 */
lsm6dsox_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)2618 int32_t lsm6dsox_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
2619 {
2620 lsm6dsox_ctrl3_c_t reg;
2621 int32_t ret;
2622
2623 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
2624 *val = reg.boot;
2625
2626 return ret;
2627 }
2628
2629 /**
2630 * @brief Linear acceleration sensor self-test enable.[set]
2631 *
2632 * @param ctx read / write interface definitions
2633 * @param val change the values of st_xl in reg CTRL5_C
2634 * @retval interface status (MANDATORY: return 0 -> no Error)
2635 *
2636 */
lsm6dsox_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6dsox_st_xl_t val)2637 int32_t lsm6dsox_xl_self_test_set(const stmdev_ctx_t *ctx,
2638 lsm6dsox_st_xl_t val)
2639 {
2640 lsm6dsox_ctrl5_c_t reg;
2641 int32_t ret;
2642
2643 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
2644
2645 if (ret == 0)
2646 {
2647 reg.st_xl = (uint8_t)val;
2648 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
2649 }
2650
2651 return ret;
2652 }
2653
2654 /**
2655 * @brief Linear acceleration sensor self-test enable.[get]
2656 *
2657 * @param ctx read / write interface definitions
2658 * @param val Get the values of st_xl in reg CTRL5_C
2659 * @retval interface status (MANDATORY: return 0 -> no Error)
2660 *
2661 */
lsm6dsox_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6dsox_st_xl_t * val)2662 int32_t lsm6dsox_xl_self_test_get(const stmdev_ctx_t *ctx,
2663 lsm6dsox_st_xl_t *val)
2664 {
2665 lsm6dsox_ctrl5_c_t reg;
2666 int32_t ret;
2667
2668 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
2669
2670 switch (reg.st_xl)
2671 {
2672 case LSM6DSOX_XL_ST_DISABLE:
2673 *val = LSM6DSOX_XL_ST_DISABLE;
2674 break;
2675
2676 case LSM6DSOX_XL_ST_POSITIVE:
2677 *val = LSM6DSOX_XL_ST_POSITIVE;
2678 break;
2679
2680 case LSM6DSOX_XL_ST_NEGATIVE:
2681 *val = LSM6DSOX_XL_ST_NEGATIVE;
2682 break;
2683
2684 default:
2685 *val = LSM6DSOX_XL_ST_DISABLE;
2686 break;
2687 }
2688
2689 return ret;
2690 }
2691
2692 /**
2693 * @brief Angular rate sensor self-test enable.[set]
2694 *
2695 * @param ctx read / write interface definitions
2696 * @param val change the values of st_g in reg CTRL5_C
2697 * @retval interface status (MANDATORY: return 0 -> no Error)
2698 *
2699 */
lsm6dsox_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dsox_st_g_t val)2700 int32_t lsm6dsox_gy_self_test_set(const stmdev_ctx_t *ctx,
2701 lsm6dsox_st_g_t val)
2702 {
2703 lsm6dsox_ctrl5_c_t reg;
2704 int32_t ret;
2705
2706 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
2707
2708 if (ret == 0)
2709 {
2710 reg.st_g = (uint8_t)val;
2711 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
2712 }
2713
2714 return ret;
2715 }
2716
2717 /**
2718 * @brief Angular rate sensor self-test enable.[get]
2719 *
2720 * @param ctx read / write interface definitions
2721 * @param val Get the values of st_g in reg CTRL5_C
2722 * @retval interface status (MANDATORY: return 0 -> no Error)
2723 *
2724 */
lsm6dsox_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dsox_st_g_t * val)2725 int32_t lsm6dsox_gy_self_test_get(const stmdev_ctx_t *ctx,
2726 lsm6dsox_st_g_t *val)
2727 {
2728 lsm6dsox_ctrl5_c_t reg;
2729 int32_t ret;
2730
2731 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)®, 1);
2732
2733 switch (reg.st_g)
2734 {
2735 case LSM6DSOX_GY_ST_DISABLE:
2736 *val = LSM6DSOX_GY_ST_DISABLE;
2737 break;
2738
2739 case LSM6DSOX_GY_ST_POSITIVE:
2740 *val = LSM6DSOX_GY_ST_POSITIVE;
2741 break;
2742
2743 case LSM6DSOX_GY_ST_NEGATIVE:
2744 *val = LSM6DSOX_GY_ST_NEGATIVE;
2745 break;
2746
2747 default:
2748 *val = LSM6DSOX_GY_ST_DISABLE;
2749 break;
2750 }
2751
2752 return ret;
2753 }
2754
2755 /**
2756 * @}
2757 *
2758 */
2759
2760 /**
2761 * @defgroup LSM6DSOX_filters
2762 * @brief This section group all the functions concerning the
2763 * filters configuration
2764 * @{
2765 *
2766 */
2767
2768 /**
2769 * @brief Accelerometer output from LPF2 filtering stage selection.[set]
2770 *
2771 * @param ctx read / write interface definitions
2772 * @param val change the values of lpf2_xl_en in reg CTRL1_XL
2773 * @retval interface status (MANDATORY: return 0 -> no Error)
2774 *
2775 */
lsm6dsox_xl_filter_lp2_set(const stmdev_ctx_t * ctx,uint8_t val)2776 int32_t lsm6dsox_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val)
2777 {
2778 lsm6dsox_ctrl1_xl_t reg;
2779 int32_t ret;
2780
2781 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1);
2782
2783 if (ret == 0)
2784 {
2785 reg.lpf2_xl_en = val;
2786 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1);
2787 }
2788
2789 return ret;
2790 }
2791
2792 /**
2793 * @brief Accelerometer output from LPF2 filtering stage selection.[get]
2794 *
2795 * @param ctx read / write interface definitions
2796 * @param val change the values of lpf2_xl_en in reg CTRL1_XL
2797 * @retval interface status (MANDATORY: return 0 -> no Error)
2798 *
2799 */
lsm6dsox_xl_filter_lp2_get(const stmdev_ctx_t * ctx,uint8_t * val)2800 int32_t lsm6dsox_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val)
2801 {
2802 lsm6dsox_ctrl1_xl_t reg;
2803 int32_t ret;
2804
2805 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 1);
2806 *val = reg.lpf2_xl_en;
2807
2808 return ret;
2809 }
2810
2811 /**
2812 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2813 * the bandwidth can be selected through FTYPE [2:0]
2814 * in CTRL6_C (15h).[set]
2815 *
2816 * @param ctx read / write interface definitions
2817 * @param val change the values of lpf1_sel_g in reg CTRL4_C
2818 * @retval interface status (MANDATORY: return 0 -> no Error)
2819 *
2820 */
lsm6dsox_gy_filter_lp1_set(const stmdev_ctx_t * ctx,uint8_t val)2821 int32_t lsm6dsox_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val)
2822 {
2823 lsm6dsox_ctrl4_c_t reg;
2824 int32_t ret;
2825
2826 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
2827
2828 if (ret == 0)
2829 {
2830 reg.lpf1_sel_g = val;
2831 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
2832 }
2833
2834 return ret;
2835 }
2836
2837 /**
2838 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2839 * the bandwidth can be selected through FTYPE [2:0]
2840 * in CTRL6_C (15h).[get]
2841 *
2842 * @param ctx read / write interface definitions
2843 * @param val change the values of lpf1_sel_g in reg CTRL4_C
2844 * @retval interface status (MANDATORY: return 0 -> no Error)
2845 *
2846 */
lsm6dsox_gy_filter_lp1_get(const stmdev_ctx_t * ctx,uint8_t * val)2847 int32_t lsm6dsox_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val)
2848 {
2849 lsm6dsox_ctrl4_c_t reg;
2850 int32_t ret;
2851
2852 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
2853 *val = reg.lpf1_sel_g;
2854
2855 return ret;
2856 }
2857
2858 /**
2859 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2860 * (XL and Gyro independently masked).[set]
2861 *
2862 * @param ctx read / write interface definitions
2863 * @param val change the values of drdy_mask in reg CTRL4_C
2864 * @retval interface status (MANDATORY: return 0 -> no Error)
2865 *
2866 */
lsm6dsox_filter_settling_mask_set(const stmdev_ctx_t * ctx,uint8_t val)2867 int32_t lsm6dsox_filter_settling_mask_set(const stmdev_ctx_t *ctx,
2868 uint8_t val)
2869 {
2870 lsm6dsox_ctrl4_c_t reg;
2871 int32_t ret;
2872
2873 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
2874
2875 if (ret == 0)
2876 {
2877 reg.drdy_mask = val;
2878 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
2879 }
2880
2881 return ret;
2882 }
2883
2884 /**
2885 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2886 * (XL and Gyro independently masked).[get]
2887 *
2888 * @param ctx read / write interface definitions
2889 * @param val change the values of drdy_mask in reg CTRL4_C
2890 * @retval interface status (MANDATORY: return 0 -> no Error)
2891 *
2892 */
lsm6dsox_filter_settling_mask_get(const stmdev_ctx_t * ctx,uint8_t * val)2893 int32_t lsm6dsox_filter_settling_mask_get(const stmdev_ctx_t *ctx,
2894 uint8_t *val)
2895 {
2896 lsm6dsox_ctrl4_c_t reg;
2897 int32_t ret;
2898
2899 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
2900 *val = reg.drdy_mask;
2901
2902 return ret;
2903 }
2904
2905 /**
2906 * @brief Gyroscope lp1 bandwidth.[set]
2907 *
2908 * @param ctx read / write interface definitions
2909 * @param val change the values of ftype in reg CTRL6_C
2910 * @retval interface status (MANDATORY: return 0 -> no Error)
2911 *
2912 */
lsm6dsox_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsox_ftype_t val)2913 int32_t lsm6dsox_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
2914 lsm6dsox_ftype_t val)
2915 {
2916 lsm6dsox_ctrl6_c_t reg;
2917 int32_t ret;
2918
2919 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1);
2920
2921 if (ret == 0)
2922 {
2923 reg.ftype = (uint8_t)val;
2924 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1);
2925 }
2926
2927 return ret;
2928 }
2929
2930 /**
2931 * @brief Gyroscope lp1 bandwidth.[get]
2932 *
2933 * @param ctx read / write interface definitions
2934 * @param val Get the values of ftype in reg CTRL6_C
2935 * @retval interface status (MANDATORY: return 0 -> no Error)
2936 *
2937 */
lsm6dsox_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsox_ftype_t * val)2938 int32_t lsm6dsox_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
2939 lsm6dsox_ftype_t *val)
2940 {
2941 lsm6dsox_ctrl6_c_t reg;
2942 int32_t ret;
2943
2944 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1);
2945
2946 switch (reg.ftype)
2947 {
2948 case LSM6DSOX_ULTRA_LIGHT:
2949 *val = LSM6DSOX_ULTRA_LIGHT;
2950 break;
2951
2952 case LSM6DSOX_VERY_LIGHT:
2953 *val = LSM6DSOX_VERY_LIGHT;
2954 break;
2955
2956 case LSM6DSOX_LIGHT:
2957 *val = LSM6DSOX_LIGHT;
2958 break;
2959
2960 case LSM6DSOX_MEDIUM:
2961 *val = LSM6DSOX_MEDIUM;
2962 break;
2963
2964 case LSM6DSOX_STRONG:
2965 *val = LSM6DSOX_STRONG;
2966 break;
2967
2968 case LSM6DSOX_VERY_STRONG:
2969 *val = LSM6DSOX_VERY_STRONG;
2970 break;
2971
2972 case LSM6DSOX_AGGRESSIVE:
2973 *val = LSM6DSOX_AGGRESSIVE;
2974 break;
2975
2976 case LSM6DSOX_XTREME:
2977 *val = LSM6DSOX_XTREME;
2978 break;
2979
2980 default:
2981 *val = LSM6DSOX_ULTRA_LIGHT;
2982 break;
2983 }
2984
2985 return ret;
2986 }
2987
2988 /**
2989 * @brief Low pass filter 2 on 6D function selection.[set]
2990 *
2991 * @param ctx read / write interface definitions
2992 * @param val change the values of low_pass_on_6d in reg CTRL8_XL
2993 * @retval interface status (MANDATORY: return 0 -> no Error)
2994 *
2995 */
lsm6dsox_xl_lp2_on_6d_set(const stmdev_ctx_t * ctx,uint8_t val)2996 int32_t lsm6dsox_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val)
2997 {
2998 lsm6dsox_ctrl8_xl_t reg;
2999 int32_t ret;
3000
3001 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
3002
3003 if (ret == 0)
3004 {
3005 reg.low_pass_on_6d = val;
3006 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
3007 }
3008
3009 return ret;
3010 }
3011
3012 /**
3013 * @brief Low pass filter 2 on 6D function selection.[get]
3014 *
3015 * @param ctx read / write interface definitions
3016 * @param val change the values of low_pass_on_6d in reg CTRL8_XL
3017 * @retval interface status (MANDATORY: return 0 -> no Error)
3018 *
3019 */
lsm6dsox_xl_lp2_on_6d_get(const stmdev_ctx_t * ctx,uint8_t * val)3020 int32_t lsm6dsox_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val)
3021 {
3022 lsm6dsox_ctrl8_xl_t reg;
3023 int32_t ret;
3024
3025 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
3026 *val = reg.low_pass_on_6d;
3027
3028 return ret;
3029 }
3030
3031 /**
3032 * @brief Accelerometer slope filter / high-pass filter selection
3033 * on output.[set]
3034 *
3035 * @param ctx read / write interface definitions
3036 * @param val change the values of hp_slope_xl_en
3037 * in reg CTRL8_XL
3038 * @retval interface status (MANDATORY: return 0 -> no Error)
3039 *
3040 */
lsm6dsox_xl_hp_path_on_out_set(const stmdev_ctx_t * ctx,lsm6dsox_hp_slope_xl_en_t val)3041 int32_t lsm6dsox_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx,
3042 lsm6dsox_hp_slope_xl_en_t val)
3043 {
3044 lsm6dsox_ctrl8_xl_t reg;
3045 int32_t ret;
3046
3047 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
3048
3049 if (ret == 0)
3050 {
3051 reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4;
3052 reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5;
3053 reg.hpcf_xl = (uint8_t)val & 0x07U;
3054 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
3055 }
3056
3057 return ret;
3058 }
3059
3060 /**
3061 * @brief Accelerometer slope filter / high-pass filter selection
3062 * on output.[get]
3063 *
3064 * @param ctx read / write interface definitions
3065 * @param val Get the values of hp_slope_xl_en
3066 * in reg CTRL8_XL
3067 * @retval interface status (MANDATORY: return 0 -> no Error)
3068 *
3069 */
lsm6dsox_xl_hp_path_on_out_get(const stmdev_ctx_t * ctx,lsm6dsox_hp_slope_xl_en_t * val)3070 int32_t lsm6dsox_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx,
3071 lsm6dsox_hp_slope_xl_en_t *val)
3072 {
3073 lsm6dsox_ctrl8_xl_t reg;
3074 int32_t ret;
3075
3076 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
3077
3078 switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) |
3079 reg.hpcf_xl)
3080 {
3081 case LSM6DSOX_HP_PATH_DISABLE_ON_OUT:
3082 *val = LSM6DSOX_HP_PATH_DISABLE_ON_OUT;
3083 break;
3084
3085 case LSM6DSOX_SLOPE_ODR_DIV_4:
3086 *val = LSM6DSOX_SLOPE_ODR_DIV_4;
3087 break;
3088
3089 case LSM6DSOX_HP_ODR_DIV_10:
3090 *val = LSM6DSOX_HP_ODR_DIV_10;
3091 break;
3092
3093 case LSM6DSOX_HP_ODR_DIV_20:
3094 *val = LSM6DSOX_HP_ODR_DIV_20;
3095 break;
3096
3097 case LSM6DSOX_HP_ODR_DIV_45:
3098 *val = LSM6DSOX_HP_ODR_DIV_45;
3099 break;
3100
3101 case LSM6DSOX_HP_ODR_DIV_100:
3102 *val = LSM6DSOX_HP_ODR_DIV_100;
3103 break;
3104
3105 case LSM6DSOX_HP_ODR_DIV_200:
3106 *val = LSM6DSOX_HP_ODR_DIV_200;
3107 break;
3108
3109 case LSM6DSOX_HP_ODR_DIV_400:
3110 *val = LSM6DSOX_HP_ODR_DIV_400;
3111 break;
3112
3113 case LSM6DSOX_HP_ODR_DIV_800:
3114 *val = LSM6DSOX_HP_ODR_DIV_800;
3115 break;
3116
3117 case LSM6DSOX_HP_REF_MD_ODR_DIV_10:
3118 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_10;
3119 break;
3120
3121 case LSM6DSOX_HP_REF_MD_ODR_DIV_20:
3122 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_20;
3123 break;
3124
3125 case LSM6DSOX_HP_REF_MD_ODR_DIV_45:
3126 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_45;
3127 break;
3128
3129 case LSM6DSOX_HP_REF_MD_ODR_DIV_100:
3130 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_100;
3131 break;
3132
3133 case LSM6DSOX_HP_REF_MD_ODR_DIV_200:
3134 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_200;
3135 break;
3136
3137 case LSM6DSOX_HP_REF_MD_ODR_DIV_400:
3138 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_400;
3139 break;
3140
3141 case LSM6DSOX_HP_REF_MD_ODR_DIV_800:
3142 *val = LSM6DSOX_HP_REF_MD_ODR_DIV_800;
3143 break;
3144
3145 case LSM6DSOX_LP_ODR_DIV_10:
3146 *val = LSM6DSOX_LP_ODR_DIV_10;
3147 break;
3148
3149 case LSM6DSOX_LP_ODR_DIV_20:
3150 *val = LSM6DSOX_LP_ODR_DIV_20;
3151 break;
3152
3153 case LSM6DSOX_LP_ODR_DIV_45:
3154 *val = LSM6DSOX_LP_ODR_DIV_45;
3155 break;
3156
3157 case LSM6DSOX_LP_ODR_DIV_100:
3158 *val = LSM6DSOX_LP_ODR_DIV_100;
3159 break;
3160
3161 case LSM6DSOX_LP_ODR_DIV_200:
3162 *val = LSM6DSOX_LP_ODR_DIV_200;
3163 break;
3164
3165 case LSM6DSOX_LP_ODR_DIV_400:
3166 *val = LSM6DSOX_LP_ODR_DIV_400;
3167 break;
3168
3169 case LSM6DSOX_LP_ODR_DIV_800:
3170 *val = LSM6DSOX_LP_ODR_DIV_800;
3171 break;
3172
3173 default:
3174 *val = LSM6DSOX_HP_PATH_DISABLE_ON_OUT;
3175 break;
3176 }
3177
3178 return ret;
3179 }
3180
3181 /**
3182 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
3183 * The filter sets the second samples after writing this bit.
3184 * Active only during device exit from power-down mode.[set]
3185 *
3186 * @param ctx read / write interface definitions
3187 * @param val change the values of fastsettl_mode_xl in
3188 * reg CTRL8_XL
3189 * @retval interface status (MANDATORY: return 0 -> no Error)
3190 *
3191 */
lsm6dsox_xl_fast_settling_set(const stmdev_ctx_t * ctx,uint8_t val)3192 int32_t lsm6dsox_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val)
3193 {
3194 lsm6dsox_ctrl8_xl_t reg;
3195 int32_t ret;
3196
3197 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
3198
3199 if (ret == 0)
3200 {
3201 reg.fastsettl_mode_xl = val;
3202 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
3203 }
3204
3205 return ret;
3206 }
3207
3208 /**
3209 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
3210 * The filter sets the second samples after writing this bit.
3211 * Active only during device exit from power-down mode.[get]
3212 *
3213 * @param ctx read / write interface definitions
3214 * @param val change the values of fastsettl_mode_xl in reg CTRL8_XL
3215 * @retval interface status (MANDATORY: return 0 -> no Error)
3216 *
3217 */
lsm6dsox_xl_fast_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)3218 int32_t lsm6dsox_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val)
3219 {
3220 lsm6dsox_ctrl8_xl_t reg;
3221 int32_t ret;
3222
3223 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
3224 *val = reg.fastsettl_mode_xl;
3225
3226 return ret;
3227 }
3228
3229 /**
3230 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
3231 * functions.[set]
3232 *
3233 * @param ctx read / write interface definitions
3234 * @param val change the values of slope_fds in reg TAP_CFG0
3235 * @retval interface status (MANDATORY: return 0 -> no Error)
3236 *
3237 */
lsm6dsox_xl_hp_path_internal_set(const stmdev_ctx_t * ctx,lsm6dsox_slope_fds_t val)3238 int32_t lsm6dsox_xl_hp_path_internal_set(const stmdev_ctx_t *ctx,
3239 lsm6dsox_slope_fds_t val)
3240 {
3241 lsm6dsox_tap_cfg0_t reg;
3242 int32_t ret;
3243
3244 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
3245
3246 if (ret == 0)
3247 {
3248 reg.slope_fds = (uint8_t)val;
3249 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
3250 }
3251
3252 return ret;
3253 }
3254
3255 /**
3256 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
3257 * functions.[get]
3258 *
3259 * @param ctx read / write interface definitions
3260 * @param val Change the values of slope_fds in reg TAP_CFG0
3261 * @retval interface status (MANDATORY: return 0 -> no Error)
3262 *
3263 */
lsm6dsox_xl_hp_path_internal_get(const stmdev_ctx_t * ctx,lsm6dsox_slope_fds_t * val)3264 int32_t lsm6dsox_xl_hp_path_internal_get(const stmdev_ctx_t *ctx,
3265 lsm6dsox_slope_fds_t *val)
3266 {
3267 lsm6dsox_tap_cfg0_t reg;
3268 int32_t ret;
3269
3270 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
3271
3272 switch (reg.slope_fds)
3273 {
3274 case LSM6DSOX_USE_SLOPE:
3275 *val = LSM6DSOX_USE_SLOPE;
3276 break;
3277
3278 case LSM6DSOX_USE_HPF:
3279 *val = LSM6DSOX_USE_HPF;
3280 break;
3281
3282 default:
3283 *val = LSM6DSOX_USE_SLOPE;
3284 break;
3285 }
3286
3287 return ret;
3288 }
3289
3290 /**
3291 * @brief Enables gyroscope digital high-pass filter. The filter is
3292 * enabled only if the gyro is in HP mode.[set]
3293 *
3294 * @param ctx read / write interface definitions
3295 * @param val Get the values of hp_en_g and hp_en_g
3296 * in reg CTRL7_G
3297 * @retval interface status (MANDATORY: return 0 -> no Error)
3298 *
3299 */
lsm6dsox_gy_hp_path_internal_set(const stmdev_ctx_t * ctx,lsm6dsox_hpm_g_t val)3300 int32_t lsm6dsox_gy_hp_path_internal_set(const stmdev_ctx_t *ctx,
3301 lsm6dsox_hpm_g_t val)
3302 {
3303 lsm6dsox_ctrl7_g_t reg;
3304 int32_t ret;
3305
3306 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
3307
3308 if (ret == 0)
3309 {
3310 reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
3311 reg.hpm_g = (uint8_t)val & 0x03U;
3312 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
3313 }
3314
3315 return ret;
3316 }
3317
3318 /**
3319 * @brief Enables gyroscope digital high-pass filter. The filter is
3320 * enabled only if the gyro is in HP mode.[get]
3321 *
3322 * @param ctx read / write interface definitions
3323 * @param val Get the values of hp_en_g and hp_en_g
3324 * in reg CTRL7_G
3325 * @retval interface status (MANDATORY: return 0 -> no Error)
3326 *
3327 */
lsm6dsox_gy_hp_path_internal_get(const stmdev_ctx_t * ctx,lsm6dsox_hpm_g_t * val)3328 int32_t lsm6dsox_gy_hp_path_internal_get(const stmdev_ctx_t *ctx,
3329 lsm6dsox_hpm_g_t *val)
3330 {
3331 lsm6dsox_ctrl7_g_t reg;
3332 int32_t ret;
3333
3334 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
3335
3336 switch ((reg.hp_en_g << 7) + reg.hpm_g)
3337 {
3338 case LSM6DSOX_HP_FILTER_NONE:
3339 *val = LSM6DSOX_HP_FILTER_NONE;
3340 break;
3341
3342 case LSM6DSOX_HP_FILTER_16mHz:
3343 *val = LSM6DSOX_HP_FILTER_16mHz;
3344 break;
3345
3346 case LSM6DSOX_HP_FILTER_65mHz:
3347 *val = LSM6DSOX_HP_FILTER_65mHz;
3348 break;
3349
3350 case LSM6DSOX_HP_FILTER_260mHz:
3351 *val = LSM6DSOX_HP_FILTER_260mHz;
3352 break;
3353
3354 case LSM6DSOX_HP_FILTER_1Hz04:
3355 *val = LSM6DSOX_HP_FILTER_1Hz04;
3356 break;
3357
3358 default:
3359 *val = LSM6DSOX_HP_FILTER_NONE;
3360 break;
3361 }
3362
3363 return ret;
3364 }
3365
3366 /**
3367 * @}
3368 *
3369 */
3370
3371 /**
3372 * @defgroup LSM6DSOX_ Auxiliary_interface
3373 * @brief This section groups all the functions concerning
3374 * auxiliary interface.
3375 * @{
3376 *
3377 */
3378
3379 /**
3380 * @brief OIS data reading from Auxiliary / Main SPI.[set]
3381 *
3382 * @param ctx read / write interface definitions
3383 * @param val change the values of spi2_read_en in reg UI_INT_OIS
3384 * @retval interface status (MANDATORY: return 0 -> no Error)
3385 *
3386 */
lsm6dsox_ois_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_spi2_read_en_t val)3387 int32_t lsm6dsox_ois_mode_set(const stmdev_ctx_t *ctx,
3388 lsm6dsox_spi2_read_en_t val)
3389 {
3390 lsm6dsox_func_cfg_access_t func_cfg_access;
3391 lsm6dsox_ui_int_ois_t ui_int_ois;
3392 int32_t ret;
3393
3394 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS,
3395 (uint8_t *)&ui_int_ois, 1);
3396
3397 if (ret == 0)
3398 {
3399 ui_int_ois.spi2_read_en = ((uint8_t)val & 0x01U);
3400 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS,
3401 (uint8_t *)&ui_int_ois, 1);
3402 }
3403
3404 if (ret == 0)
3405 {
3406 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
3407 (uint8_t *)&func_cfg_access, 1);
3408 }
3409
3410 if (ret == 0)
3411 {
3412 func_cfg_access.ois_ctrl_from_ui = (((uint8_t)val & 0x02U) >> 1);
3413 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
3414 (uint8_t *)&func_cfg_access, 1);
3415 }
3416
3417 return ret;
3418 }
3419
3420 /**
3421 * @brief aux_ois_data: [get] OIS data reading from Auxiliary / Main SPI
3422 *
3423 * @param ctx read / write interface definitions
3424 * @param val Get the values of spi2_read_en
3425 * in reg UI_INT_OIS
3426 * @retval interface status (MANDATORY: return 0 -> no Error)
3427 *
3428 */
lsm6dsox_ois_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_spi2_read_en_t * val)3429 int32_t lsm6dsox_ois_mode_get(const stmdev_ctx_t *ctx,
3430 lsm6dsox_spi2_read_en_t *val)
3431 {
3432 lsm6dsox_func_cfg_access_t func_cfg_access;
3433 lsm6dsox_ui_int_ois_t ui_int_ois;
3434 int32_t ret;
3435
3436 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS,
3437 (uint8_t *)&ui_int_ois, 1);
3438
3439 if (ret == 0)
3440 {
3441 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
3442 (uint8_t *)&func_cfg_access, 1);
3443 }
3444
3445 switch ((func_cfg_access.ois_ctrl_from_ui << 1) +
3446 ui_int_ois.spi2_read_en)
3447 {
3448 case LSM6DSOX_OIS_CTRL_AUX_DATA_UI:
3449 *val = LSM6DSOX_OIS_CTRL_AUX_DATA_UI;
3450 break;
3451
3452 case LSM6DSOX_OIS_CTRL_AUX_DATA_UI_AUX:
3453 *val = LSM6DSOX_OIS_CTRL_AUX_DATA_UI_AUX;
3454 break;
3455
3456 case LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI:
3457 *val = LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI;
3458 break;
3459
3460 case LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI_AUX:
3461 *val = LSM6DSOX_OIS_CTRL_UI_AUX_DATA_UI_AUX;
3462 break;
3463
3464 default:
3465 *val = LSM6DSOX_OIS_CTRL_AUX_DATA_UI;
3466 break;
3467 }
3468
3469 return ret;
3470 }
3471
3472 /**
3473 * @brief aOn auxiliary interface connect/disconnect SDO and OCS
3474 * internal pull-up.[set]
3475 *
3476 * @param ctx read / write interface definitions
3477 * @param val change the values of ois_pu_dis in
3478 * reg PIN_CTRL
3479 * @retval interface status (MANDATORY: return 0 -> no Error)
3480 *
3481 */
lsm6dsox_aux_sdo_ocs_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_ois_pu_dis_t val)3482 int32_t lsm6dsox_aux_sdo_ocs_mode_set(const stmdev_ctx_t *ctx,
3483 lsm6dsox_ois_pu_dis_t val)
3484 {
3485 lsm6dsox_pin_ctrl_t reg;
3486 int32_t ret;
3487
3488 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)®, 1);
3489
3490 if (ret == 0)
3491 {
3492 reg.ois_pu_dis = (uint8_t)val;
3493 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)®, 1);
3494 }
3495
3496 return ret;
3497 }
3498
3499 /**
3500 * @brief On auxiliary interface connect/disconnect SDO and OCS
3501 * internal pull-up.[get]
3502 *
3503 * @param ctx read / write interface definitions
3504 * @param val Get the values of ois_pu_dis in reg PIN_CTRL
3505 * @retval interface status (MANDATORY: return 0 -> no Error)
3506 *
3507 */
lsm6dsox_aux_sdo_ocs_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_ois_pu_dis_t * val)3508 int32_t lsm6dsox_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx,
3509 lsm6dsox_ois_pu_dis_t *val)
3510 {
3511 lsm6dsox_pin_ctrl_t reg;
3512 int32_t ret;
3513
3514 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)®, 1);
3515
3516 switch (reg.ois_pu_dis)
3517 {
3518 case LSM6DSOX_AUX_PULL_UP_DISC:
3519 *val = LSM6DSOX_AUX_PULL_UP_DISC;
3520 break;
3521
3522 case LSM6DSOX_AUX_PULL_UP_CONNECT:
3523 *val = LSM6DSOX_AUX_PULL_UP_CONNECT;
3524 break;
3525
3526 default:
3527 *val = LSM6DSOX_AUX_PULL_UP_DISC;
3528 break;
3529 }
3530
3531 return ret;
3532 }
3533
3534 /**
3535 * @brief OIS chain on aux interface power on mode.[set]
3536 *
3537 * @param ctx read / write interface definitions
3538 * @param val change the values of ois_on in reg CTRL7_G
3539 * @retval interface status (MANDATORY: return 0 -> no Error)
3540 *
3541 */
lsm6dsox_aux_pw_on_ctrl_set(const stmdev_ctx_t * ctx,lsm6dsox_ois_on_t val)3542 int32_t lsm6dsox_aux_pw_on_ctrl_set(const stmdev_ctx_t *ctx,
3543 lsm6dsox_ois_on_t val)
3544 {
3545 lsm6dsox_ctrl7_g_t reg;
3546 int32_t ret;
3547
3548 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
3549
3550 if (ret == 0)
3551 {
3552 reg.ois_on_en = (uint8_t)val & 0x01U;
3553 reg.ois_on = (uint8_t)val & 0x01U;
3554 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
3555 }
3556
3557 return ret;
3558 }
3559
3560 /**
3561 * @brief aux_pw_on_ctrl: [get] OIS chain on aux interface power on mode
3562 *
3563 * @param ctx read / write interface definitions
3564 * @param val Get the values of ois_on in reg CTRL7_G
3565 * @retval interface status (MANDATORY: return 0 -> no Error)
3566 *
3567 */
lsm6dsox_aux_pw_on_ctrl_get(const stmdev_ctx_t * ctx,lsm6dsox_ois_on_t * val)3568 int32_t lsm6dsox_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx,
3569 lsm6dsox_ois_on_t *val)
3570 {
3571 lsm6dsox_ctrl7_g_t reg;
3572 int32_t ret;
3573
3574 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL7_G, (uint8_t *)®, 1);
3575
3576 switch (reg.ois_on)
3577 {
3578 case LSM6DSOX_AUX_ON:
3579 *val = LSM6DSOX_AUX_ON;
3580 break;
3581
3582 case LSM6DSOX_AUX_ON_BY_AUX_INTERFACE:
3583 *val = LSM6DSOX_AUX_ON_BY_AUX_INTERFACE;
3584 break;
3585
3586 default:
3587 *val = LSM6DSOX_AUX_ON;
3588 break;
3589 }
3590
3591 return ret;
3592 }
3593
3594 /**
3595 * @brief Accelerometer full-scale management between UI chain and
3596 * OIS chain. When XL UI is on, the full scale is the same
3597 * between UI/OIS and is chosen by the UI CTRL registers;
3598 * when XL UI is in PD, the OIS can choose the FS.
3599 * Full scales are independent between the UI/OIS chain
3600 * but both bound to 8 g.[set]
3601 *
3602 * @param ctx read / write interface definitions
3603 * @param val change the values of xl_fs_mode in
3604 * reg CTRL8_XL
3605 * @retval interface status (MANDATORY: return 0 -> no Error)
3606 *
3607 */
lsm6dsox_aux_xl_fs_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_xl_fs_mode_t val)3608 int32_t lsm6dsox_aux_xl_fs_mode_set(const stmdev_ctx_t *ctx,
3609 lsm6dsox_xl_fs_mode_t val)
3610 {
3611 lsm6dsox_ctrl8_xl_t reg;
3612 int32_t ret;
3613
3614 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
3615
3616 if (ret == 0)
3617 {
3618 reg.xl_fs_mode = (uint8_t)val;
3619 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
3620 }
3621
3622 return ret;
3623 }
3624
3625 /**
3626 * @brief Accelerometer full-scale management between UI chain and
3627 * OIS chain. When XL UI is on, the full scale is the same
3628 * between UI/OIS and is chosen by the UI CTRL registers;
3629 * when XL UI is in PD, the OIS can choose the FS.
3630 * Full scales are independent between the UI/OIS chain
3631 * but both bound to 8 g.[get]
3632 *
3633 * @param ctx read / write interface definitions
3634 * @param val Get the values of xl_fs_mode in reg CTRL8_XL
3635 * @retval interface status (MANDATORY: return 0 -> no Error)
3636 *
3637 */
lsm6dsox_aux_xl_fs_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_xl_fs_mode_t * val)3638 int32_t lsm6dsox_aux_xl_fs_mode_get(const stmdev_ctx_t *ctx,
3639 lsm6dsox_xl_fs_mode_t *val)
3640 {
3641 lsm6dsox_ctrl8_xl_t reg;
3642 int32_t ret;
3643
3644 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL8_XL, (uint8_t *)®, 1);
3645
3646 switch (reg.xl_fs_mode)
3647 {
3648 case LSM6DSOX_USE_SAME_XL_FS:
3649 *val = LSM6DSOX_USE_SAME_XL_FS;
3650 break;
3651
3652 case LSM6DSOX_USE_DIFFERENT_XL_FS:
3653 *val = LSM6DSOX_USE_DIFFERENT_XL_FS;
3654 break;
3655
3656 default:
3657 *val = LSM6DSOX_USE_SAME_XL_FS;
3658 break;
3659 }
3660
3661 return ret;
3662 }
3663
3664 /**
3665 * @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get]
3666 *
3667 * @param ctx read / write interface definitions
3668 * @param val Get registers STATUS_SPIAUX
3669 * @retval interface status (MANDATORY: return 0 -> no Error)
3670 *
3671 */
lsm6dsox_aux_status_reg_get(const stmdev_ctx_t * ctx,lsm6dsox_spi2_status_reg_ois_t * val)3672 int32_t lsm6dsox_aux_status_reg_get(const stmdev_ctx_t *ctx,
3673 lsm6dsox_spi2_status_reg_ois_t *val)
3674 {
3675 int32_t ret;
3676
3677 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS,
3678 (uint8_t *) val, 1);
3679
3680 return ret;
3681 }
3682
3683 /**
3684 * @brief aux_xl_flag_data_ready: [get] AUX accelerometer data available
3685 *
3686 * @param ctx read / write interface definitions
3687 * @param val change the values of xlda in reg STATUS_SPIAUX
3688 * @retval interface status (MANDATORY: return 0 -> no Error)
3689 *
3690 */
lsm6dsox_aux_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)3691 int32_t lsm6dsox_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
3692 uint8_t *val)
3693 {
3694 lsm6dsox_spi2_status_reg_ois_t reg;
3695 int32_t ret;
3696
3697 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS,
3698 (uint8_t *)®, 1);
3699 *val = reg.xlda;
3700
3701 return ret;
3702 }
3703
3704 /**
3705 * @brief aux_gy_flag_data_ready: [get] AUX gyroscope data available.
3706 *
3707 * @param ctx read / write interface definitions
3708 * @param val change the values of gda in reg STATUS_SPIAUX
3709 * @retval interface status (MANDATORY: return 0 -> no Error)
3710 *
3711 */
lsm6dsox_aux_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)3712 int32_t lsm6dsox_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx,
3713 uint8_t *val)
3714 {
3715 lsm6dsox_spi2_status_reg_ois_t reg;
3716 int32_t ret;
3717
3718 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS,
3719 (uint8_t *)®, 1);
3720 *val = reg.gda;
3721
3722 return ret;
3723 }
3724
3725 /**
3726 * @brief High when the gyroscope output is in the settling phase.[get]
3727 *
3728 * @param ctx read / write interface definitions
3729 * @param val change the values of gyro_settling in reg STATUS_SPIAUX
3730 * @retval interface status (MANDATORY: return 0 -> no Error)
3731 *
3732 */
lsm6dsox_aux_gy_flag_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)3733 int32_t lsm6dsox_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx,
3734 uint8_t *val)
3735 {
3736 lsm6dsox_spi2_status_reg_ois_t reg;
3737 int32_t ret;
3738
3739 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SPI2_STATUS_REG_OIS,
3740 (uint8_t *)®, 1);
3741 *val = reg.gyro_settling;
3742
3743 return ret;
3744 }
3745
3746 /**
3747 * @brief Indicates polarity of DEN signal on OIS chain.[set]
3748 *
3749 * @param ctx read / write interface definitions
3750 * @param val change the values of den_lh_ois in
3751 * reg INT_OIS
3752 * @retval interface status (MANDATORY: return 0 -> no Error)
3753 *
3754 */
lsm6dsox_aux_den_polarity_set(const stmdev_ctx_t * ctx,lsm6dsox_den_lh_ois_t val)3755 int32_t lsm6dsox_aux_den_polarity_set(const stmdev_ctx_t *ctx,
3756 lsm6dsox_den_lh_ois_t val)
3757 {
3758 lsm6dsox_ui_int_ois_t reg;
3759 int32_t ret;
3760
3761 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t *)®, 1);
3762
3763 if (ret == 0)
3764 {
3765 reg.den_lh_ois = (uint8_t)val;
3766 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t *)®, 1);
3767 }
3768
3769 return ret;
3770 }
3771
3772 /**
3773 * @brief Indicates polarity of DEN signal on OIS chain.[get]
3774 *
3775 * @param ctx read / write interface definitions
3776 * @param val Get the values of den_lh_ois in reg INT_OIS
3777 * @retval interface status (MANDATORY: return 0 -> no Error)
3778 *
3779 */
lsm6dsox_aux_den_polarity_get(const stmdev_ctx_t * ctx,lsm6dsox_den_lh_ois_t * val)3780 int32_t lsm6dsox_aux_den_polarity_get(const stmdev_ctx_t *ctx,
3781 lsm6dsox_den_lh_ois_t *val)
3782 {
3783 lsm6dsox_ui_int_ois_t reg;
3784 int32_t ret;
3785
3786 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t *)®, 1);
3787
3788 switch (reg.den_lh_ois)
3789 {
3790 case LSM6DSOX_AUX_DEN_ACTIVE_LOW:
3791 *val = LSM6DSOX_AUX_DEN_ACTIVE_LOW;
3792 break;
3793
3794 case LSM6DSOX_AUX_DEN_ACTIVE_HIGH:
3795 *val = LSM6DSOX_AUX_DEN_ACTIVE_HIGH;
3796 break;
3797
3798 default:
3799 *val = LSM6DSOX_AUX_DEN_ACTIVE_LOW;
3800 break;
3801 }
3802
3803 return ret;
3804 }
3805
3806 /**
3807 * @brief Configure DEN mode on the OIS chain.[set]
3808 *
3809 * @param ctx read / write interface definitions
3810 * @param val change the values of lvl2_ois in reg INT_OIS
3811 * @retval interface status (MANDATORY: return 0 -> no Error)
3812 *
3813 */
lsm6dsox_aux_den_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_lvl2_ois_t val)3814 int32_t lsm6dsox_aux_den_mode_set(const stmdev_ctx_t *ctx,
3815 lsm6dsox_lvl2_ois_t val)
3816 {
3817 lsm6dsox_ui_ctrl1_ois_t ctrl1_ois;
3818 lsm6dsox_ui_int_ois_t int_ois;
3819 int32_t ret;
3820
3821 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS,
3822 (uint8_t *) &int_ois, 1);
3823
3824 if (ret == 0)
3825 {
3826 int_ois.lvl2_ois = (uint8_t)val & 0x01U;
3827 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS,
3828 (uint8_t *) &int_ois, 1);
3829 }
3830
3831 if (ret == 0)
3832 {
3833 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS,
3834 (uint8_t *) &ctrl1_ois, 1);
3835 }
3836
3837 if (ret == 0)
3838 {
3839 ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
3840 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS,
3841 (uint8_t *) &ctrl1_ois, 1);
3842 }
3843
3844 return ret;
3845 }
3846
3847 /**
3848 * @brief Configure DEN mode on the OIS chain.[get]
3849 *
3850 * @param ctx read / write interface definitions
3851 * @param val Get the values of lvl2_ois in reg INT_OIS
3852 * @retval interface status (MANDATORY: return 0 -> no Error)
3853 *
3854 */
lsm6dsox_aux_den_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_lvl2_ois_t * val)3855 int32_t lsm6dsox_aux_den_mode_get(const stmdev_ctx_t *ctx,
3856 lsm6dsox_lvl2_ois_t *val)
3857 {
3858 lsm6dsox_ui_ctrl1_ois_t ctrl1_ois;
3859 lsm6dsox_ui_int_ois_t int_ois;
3860 int32_t ret;
3861
3862 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS,
3863 (uint8_t *) &int_ois, 1);
3864
3865 if (ret == 0)
3866 {
3867 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS,
3868 (uint8_t *) &ctrl1_ois, 1);
3869
3870 switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois)
3871 {
3872 case LSM6DSOX_AUX_DEN_DISABLE:
3873 *val = LSM6DSOX_AUX_DEN_DISABLE;
3874 break;
3875
3876 case LSM6DSOX_AUX_DEN_LEVEL_LATCH:
3877 *val = LSM6DSOX_AUX_DEN_LEVEL_LATCH;
3878 break;
3879
3880 case LSM6DSOX_AUX_DEN_LEVEL_TRIG:
3881 *val = LSM6DSOX_AUX_DEN_LEVEL_TRIG;
3882 break;
3883
3884 default:
3885 *val = LSM6DSOX_AUX_DEN_DISABLE;
3886 break;
3887 }
3888 }
3889
3890 return ret;
3891 }
3892
3893 /**
3894 * @brief Enables/Disable OIS chain DRDY on INT2 pin.
3895 * This setting has priority over all other INT2 settings.[set]
3896 *
3897 * @param ctx read / write interface definitions
3898 * @param val change the values of int2_drdy_ois in reg INT_OIS
3899 * @retval interface status (MANDATORY: return 0 -> no Error)
3900 *
3901 */
lsm6dsox_aux_drdy_on_int2_set(const stmdev_ctx_t * ctx,uint8_t val)3902 int32_t lsm6dsox_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val)
3903 {
3904 lsm6dsox_ui_int_ois_t reg;
3905 int32_t ret;
3906
3907 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t *)®, 1);
3908
3909 if (ret == 0)
3910 {
3911 reg.int2_drdy_ois = val;
3912 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t *)®, 1);
3913 }
3914
3915 return ret;
3916 }
3917
3918 /**
3919 * @brief Enables/Disable OIS chain DRDY on INT2 pin.
3920 * This setting has priority over all other INT2 settings.[get]
3921 *
3922 * @param ctx read / write interface definitions
3923 * @param val change the values of int2_drdy_ois in reg INT_OIS
3924 * @retval interface status (MANDATORY: return 0 -> no Error)
3925 *
3926 */
lsm6dsox_aux_drdy_on_int2_get(const stmdev_ctx_t * ctx,uint8_t * val)3927 int32_t lsm6dsox_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val)
3928 {
3929 lsm6dsox_ui_int_ois_t reg;
3930 int32_t ret;
3931
3932 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_INT_OIS, (uint8_t *)®, 1);
3933 *val = reg.int2_drdy_ois;
3934
3935 return ret;
3936 }
3937
3938 /**
3939 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
3940 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
3941 * When the OIS chain is enabled, the OIS outputs are available
3942 * through the SPI2 in registers OUTX_L_G (22h) through
3943 * OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
3944 * LPF1 is dedicated to this chain.[set]
3945 *
3946 * @param ctx read / write interface definitions
3947 * @param val change the values of ois_en_spi2 in
3948 * reg CTRL1_OIS
3949 * @retval interface status (MANDATORY: return 0 -> no Error)
3950 *
3951 */
lsm6dsox_aux_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_ois_en_spi2_t val)3952 int32_t lsm6dsox_aux_mode_set(const stmdev_ctx_t *ctx,
3953 lsm6dsox_ois_en_spi2_t val)
3954 {
3955 lsm6dsox_ui_ctrl1_ois_t reg;
3956 int32_t ret;
3957
3958 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1);
3959
3960 if (ret == 0)
3961 {
3962 reg.ois_en_spi2 = (uint8_t)val & 0x01U;
3963 reg.mode4_en = ((uint8_t)val & 0x02U) >> 1;
3964 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1);
3965 }
3966
3967 return ret;
3968 }
3969
3970 /**
3971 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
3972 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
3973 * When the OIS chain is enabled, the OIS outputs are available
3974 * through the SPI2 in registers OUTX_L_G (22h) through
3975 * OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
3976 * LPF1 is dedicated to this chain.[get]
3977 *
3978 * @param ctx read / write interface definitions
3979 * @param val Get the values of ois_en_spi2 in
3980 * reg CTRL1_OIS
3981 * @retval interface status (MANDATORY: return 0 -> no Error)
3982 *
3983 */
lsm6dsox_aux_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_ois_en_spi2_t * val)3984 int32_t lsm6dsox_aux_mode_get(const stmdev_ctx_t *ctx,
3985 lsm6dsox_ois_en_spi2_t *val)
3986 {
3987 lsm6dsox_ui_ctrl1_ois_t reg;
3988 int32_t ret;
3989
3990 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1);
3991
3992 switch ((reg.mode4_en << 1) | reg.ois_en_spi2)
3993 {
3994 case LSM6DSOX_AUX_DISABLE:
3995 *val = LSM6DSOX_AUX_DISABLE;
3996 break;
3997
3998 case LSM6DSOX_MODE_3_GY:
3999 *val = LSM6DSOX_MODE_3_GY;
4000 break;
4001
4002 case LSM6DSOX_MODE_4_GY_XL:
4003 *val = LSM6DSOX_MODE_4_GY_XL;
4004 break;
4005
4006 default:
4007 *val = LSM6DSOX_AUX_DISABLE;
4008 break;
4009 }
4010
4011 return ret;
4012 }
4013
4014 /**
4015 * @brief Selects gyroscope OIS chain full-scale.[set]
4016 *
4017 * @param ctx read / write interface definitions
4018 * @param val change the values of fs_g_ois in reg CTRL1_OIS
4019 * @retval interface status (MANDATORY: return 0 -> no Error)
4020 *
4021 */
lsm6dsox_aux_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsox_fs_g_ois_t val)4022 int32_t lsm6dsox_aux_gy_full_scale_set(const stmdev_ctx_t *ctx,
4023 lsm6dsox_fs_g_ois_t val)
4024 {
4025 lsm6dsox_ui_ctrl1_ois_t reg;
4026 int32_t ret;
4027
4028 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1);
4029
4030 if (ret == 0)
4031 {
4032 reg.fs_g_ois = (uint8_t)val;
4033 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1);
4034 }
4035
4036 return ret;
4037 }
4038
4039 /**
4040 * @brief Selects gyroscope OIS chain full-scale.[get]
4041 *
4042 * @param ctx read / write interface definitions
4043 * @param val Get the values of fs_g_ois in reg CTRL1_OIS
4044 * @retval interface status (MANDATORY: return 0 -> no Error)
4045 *
4046 */
lsm6dsox_aux_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsox_fs_g_ois_t * val)4047 int32_t lsm6dsox_aux_gy_full_scale_get(const stmdev_ctx_t *ctx,
4048 lsm6dsox_fs_g_ois_t *val)
4049 {
4050 lsm6dsox_ui_ctrl1_ois_t reg;
4051 int32_t ret;
4052
4053 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1);
4054
4055 switch (reg.fs_g_ois)
4056 {
4057 case LSM6DSOX_250dps_AUX:
4058 *val = LSM6DSOX_250dps_AUX;
4059 break;
4060
4061 case LSM6DSOX_125dps_AUX:
4062 *val = LSM6DSOX_125dps_AUX;
4063 break;
4064
4065 case LSM6DSOX_500dps_AUX:
4066 *val = LSM6DSOX_500dps_AUX;
4067 break;
4068
4069 case LSM6DSOX_1000dps_AUX:
4070 *val = LSM6DSOX_1000dps_AUX;
4071 break;
4072
4073 case LSM6DSOX_2000dps_AUX:
4074 *val = LSM6DSOX_2000dps_AUX;
4075 break;
4076
4077 default:
4078 *val = LSM6DSOX_250dps_AUX;
4079 break;
4080 }
4081
4082 return ret;
4083 }
4084
4085 /**
4086 * @brief SPI2 3- or 4-wire interface.[set]
4087 *
4088 * @param ctx read / write interface definitions
4089 * @param val change the values of sim_ois in reg CTRL1_OIS
4090 * @retval interface status (MANDATORY: return 0 -> no Error)
4091 *
4092 */
lsm6dsox_aux_spi_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_sim_ois_t val)4093 int32_t lsm6dsox_aux_spi_mode_set(const stmdev_ctx_t *ctx,
4094 lsm6dsox_sim_ois_t val)
4095 {
4096 lsm6dsox_ui_ctrl1_ois_t reg;
4097 int32_t ret;
4098
4099 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1);
4100
4101 if (ret == 0)
4102 {
4103 reg.sim_ois = (uint8_t)val;
4104 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1);
4105 }
4106
4107 return ret;
4108 }
4109
4110 /**
4111 * @brief SPI2 3- or 4-wire interface.[get]
4112 *
4113 * @param ctx read / write interface definitions
4114 * @param val Get the values of sim_ois in reg CTRL1_OIS
4115 * @retval interface status (MANDATORY: return 0 -> no Error)
4116 *
4117 */
lsm6dsox_aux_spi_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_sim_ois_t * val)4118 int32_t lsm6dsox_aux_spi_mode_get(const stmdev_ctx_t *ctx,
4119 lsm6dsox_sim_ois_t *val)
4120 {
4121 lsm6dsox_ui_ctrl1_ois_t reg;
4122 int32_t ret;
4123
4124 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, (uint8_t *)®, 1);
4125
4126 switch (reg.sim_ois)
4127 {
4128 case LSM6DSOX_AUX_SPI_4_WIRE:
4129 *val = LSM6DSOX_AUX_SPI_4_WIRE;
4130 break;
4131
4132 case LSM6DSOX_AUX_SPI_3_WIRE:
4133 *val = LSM6DSOX_AUX_SPI_3_WIRE;
4134 break;
4135
4136 default:
4137 *val = LSM6DSOX_AUX_SPI_4_WIRE;
4138 break;
4139 }
4140
4141 return ret;
4142 }
4143
4144 /**
4145 * @brief Selects gyroscope digital LPF1 filter bandwidth.[set]
4146 *
4147 * @param ctx read / write interface definitions
4148 * @param val change the values of ftype_ois in
4149 * reg CTRL2_OIS
4150 * @retval interface status (MANDATORY: return 0 -> no Error)
4151 *
4152 */
lsm6dsox_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsox_ftype_ois_t val)4153 int32_t lsm6dsox_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
4154 lsm6dsox_ftype_ois_t val)
4155 {
4156 lsm6dsox_ui_ctrl2_ois_t reg;
4157 int32_t ret;
4158
4159 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t *)®, 1);
4160
4161 if (ret == 0)
4162 {
4163 reg.ftype_ois = (uint8_t)val;
4164 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t *)®, 1);
4165 }
4166
4167 return ret;
4168 }
4169
4170 /**
4171 * @brief Selects gyroscope digital LPF1 filter bandwidth.[get]
4172 *
4173 * @param ctx read / write interface definitions
4174 * @param val Get the values of ftype_ois in reg CTRL2_OIS
4175 * @retval interface status (MANDATORY: return 0 -> no Error)
4176 *
4177 */
lsm6dsox_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsox_ftype_ois_t * val)4178 int32_t lsm6dsox_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
4179 lsm6dsox_ftype_ois_t *val)
4180 {
4181 lsm6dsox_ui_ctrl2_ois_t reg;
4182 int32_t ret;
4183
4184 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t *)®, 1);
4185
4186 switch (reg.ftype_ois)
4187 {
4188 case LSM6DSOX_351Hz39:
4189 *val = LSM6DSOX_351Hz39;
4190 break;
4191
4192 case LSM6DSOX_236Hz63:
4193 *val = LSM6DSOX_236Hz63;
4194 break;
4195
4196 case LSM6DSOX_172Hz70:
4197 *val = LSM6DSOX_172Hz70;
4198 break;
4199
4200 case LSM6DSOX_937Hz91:
4201 *val = LSM6DSOX_937Hz91;
4202 break;
4203
4204 default:
4205 *val = LSM6DSOX_351Hz39;
4206 break;
4207 }
4208
4209 return ret;
4210 }
4211
4212 /**
4213 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[set]
4214 *
4215 * @param ctx read / write interface definitions
4216 * @param val change the values of hpm_ois in reg CTRL2_OIS
4217 * @retval interface status (MANDATORY: return 0 -> no Error)
4218 *
4219 */
lsm6dsox_aux_gy_hp_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsox_hpm_ois_t val)4220 int32_t lsm6dsox_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx,
4221 lsm6dsox_hpm_ois_t val)
4222 {
4223 lsm6dsox_ui_ctrl2_ois_t reg;
4224 int32_t ret;
4225
4226 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t *)®, 1);
4227
4228 if (ret == 0)
4229 {
4230 reg.hpm_ois = (uint8_t)val & 0x03U;
4231 reg.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
4232 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t *)®, 1);
4233 }
4234
4235 return ret;
4236 }
4237
4238 /**
4239 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[get]
4240 *
4241 * @param ctx read / write interface definitions
4242 * @param val Get the values of hpm_ois in reg CTRL2_OIS
4243 * @retval interface status (MANDATORY: return 0 -> no Error)
4244 *
4245 */
lsm6dsox_aux_gy_hp_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsox_hpm_ois_t * val)4246 int32_t lsm6dsox_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx,
4247 lsm6dsox_hpm_ois_t *val)
4248 {
4249 lsm6dsox_ui_ctrl2_ois_t reg;
4250 int32_t ret;
4251
4252 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL2_OIS, (uint8_t *)®, 1);
4253
4254 switch ((reg.hp_en_ois << 4) | reg.hpm_ois)
4255 {
4256 case LSM6DSOX_AUX_HP_DISABLE:
4257 *val = LSM6DSOX_AUX_HP_DISABLE;
4258 break;
4259
4260 case LSM6DSOX_AUX_HP_Hz016:
4261 *val = LSM6DSOX_AUX_HP_Hz016;
4262 break;
4263
4264 case LSM6DSOX_AUX_HP_Hz065:
4265 *val = LSM6DSOX_AUX_HP_Hz065;
4266 break;
4267
4268 case LSM6DSOX_AUX_HP_Hz260:
4269 *val = LSM6DSOX_AUX_HP_Hz260;
4270 break;
4271
4272 case LSM6DSOX_AUX_HP_1Hz040:
4273 *val = LSM6DSOX_AUX_HP_1Hz040;
4274 break;
4275
4276 default:
4277 *val = LSM6DSOX_AUX_HP_DISABLE;
4278 break;
4279 }
4280
4281 return ret;
4282 }
4283
4284 /**
4285 * @brief Enable / Disables OIS chain clamp.
4286 * Enable: All OIS chain outputs = 8000h
4287 * during self-test; Disable: OIS chain self-test
4288 * outputs dependent from the aux gyro full
4289 * scale selected.[set]
4290 *
4291 * @param ctx read / write interface definitions
4292 * @param val change the values of st_ois_clampdis in
4293 * reg CTRL3_OIS
4294 * @retval interface status (MANDATORY: return 0 -> no Error)
4295 *
4296 */
lsm6dsox_aux_gy_clamp_set(const stmdev_ctx_t * ctx,lsm6dsox_st_ois_clampdis_t val)4297 int32_t lsm6dsox_aux_gy_clamp_set(const stmdev_ctx_t *ctx,
4298 lsm6dsox_st_ois_clampdis_t val)
4299 {
4300 lsm6dsox_ui_ctrl3_ois_t reg;
4301 int32_t ret;
4302
4303 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1);
4304
4305 if (ret == 0)
4306 {
4307 reg.st_ois_clampdis = (uint8_t)val;
4308 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1);
4309 }
4310
4311 return ret;
4312 }
4313
4314 /**
4315 * @brief Enable / Disables OIS chain clamp.
4316 * Enable: All OIS chain outputs = 8000h
4317 * during self-test; Disable: OIS chain self-test
4318 * outputs dependent from the aux gyro full
4319 * scale selected.[set]
4320 *
4321 * @param ctx read / write interface definitions
4322 * @param val Get the values of st_ois_clampdis in
4323 * reg CTRL3_OIS
4324 * @retval interface status (MANDATORY: return 0 -> no Error)
4325 *
4326 */
lsm6dsox_aux_gy_clamp_get(const stmdev_ctx_t * ctx,lsm6dsox_st_ois_clampdis_t * val)4327 int32_t lsm6dsox_aux_gy_clamp_get(const stmdev_ctx_t *ctx,
4328 lsm6dsox_st_ois_clampdis_t *val)
4329 {
4330 lsm6dsox_ui_ctrl3_ois_t reg;
4331 int32_t ret;
4332
4333 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1);
4334
4335 switch (reg.st_ois_clampdis)
4336 {
4337 case LSM6DSOX_ENABLE_CLAMP:
4338 *val = LSM6DSOX_ENABLE_CLAMP;
4339 break;
4340
4341 case LSM6DSOX_DISABLE_CLAMP:
4342 *val = LSM6DSOX_DISABLE_CLAMP;
4343 break;
4344
4345 default:
4346 *val = LSM6DSOX_ENABLE_CLAMP;
4347 break;
4348 }
4349
4350 return ret;
4351 }
4352
4353 /**
4354 * @brief Selects accelerometer OIS channel bandwidth.[set]
4355 *
4356 * @param ctx read / write interface definitions
4357 * @param val change the values of
4358 * filter_xl_conf_ois in reg CTRL3_OIS
4359 * @retval interface status (MANDATORY: return 0 -> no Error)
4360 *
4361 */
lsm6dsox_aux_xl_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsox_filter_xl_conf_ois_t val)4362 int32_t lsm6dsox_aux_xl_bandwidth_set(const stmdev_ctx_t *ctx,
4363 lsm6dsox_filter_xl_conf_ois_t val)
4364 {
4365 lsm6dsox_ui_ctrl3_ois_t reg;
4366 int32_t ret;
4367
4368 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1);
4369
4370 if (ret == 0)
4371 {
4372 reg.filter_xl_conf_ois = (uint8_t)val;
4373 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1);
4374 }
4375
4376 return ret;
4377 }
4378
4379 /**
4380 * @brief Selects accelerometer OIS channel bandwidth.[get]
4381 *
4382 * @param ctx read / write interface definitions
4383 * @param val Get the values of
4384 * filter_xl_conf_ois in reg CTRL3_OIS
4385 * @retval interface status (MANDATORY: return 0 -> no Error)
4386 *
4387 */
lsm6dsox_aux_xl_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsox_filter_xl_conf_ois_t * val)4388 int32_t lsm6dsox_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx,
4389 lsm6dsox_filter_xl_conf_ois_t *val)
4390 {
4391 lsm6dsox_ui_ctrl3_ois_t reg;
4392 int32_t ret;
4393
4394 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1);
4395
4396 switch (reg.filter_xl_conf_ois)
4397 {
4398 case LSM6DSOX_289Hz:
4399 *val = LSM6DSOX_289Hz;
4400 break;
4401
4402 case LSM6DSOX_258Hz:
4403 *val = LSM6DSOX_258Hz;
4404 break;
4405
4406 case LSM6DSOX_120Hz:
4407 *val = LSM6DSOX_120Hz;
4408 break;
4409
4410 case LSM6DSOX_65Hz2:
4411 *val = LSM6DSOX_65Hz2;
4412 break;
4413
4414 case LSM6DSOX_33Hz2:
4415 *val = LSM6DSOX_33Hz2;
4416 break;
4417
4418 case LSM6DSOX_16Hz6:
4419 *val = LSM6DSOX_16Hz6;
4420 break;
4421
4422 case LSM6DSOX_8Hz30:
4423 *val = LSM6DSOX_8Hz30;
4424 break;
4425
4426 case LSM6DSOX_4Hz15:
4427 *val = LSM6DSOX_4Hz15;
4428 break;
4429
4430 default:
4431 *val = LSM6DSOX_289Hz;
4432 break;
4433 }
4434
4435 return ret;
4436 }
4437
4438 /**
4439 * @brief Selects accelerometer OIS channel full-scale.[set]
4440 *
4441 * @param ctx read / write interface definitions
4442 * @param val change the values of fs_xl_ois in
4443 * reg CTRL3_OIS
4444 * @retval interface status (MANDATORY: return 0 -> no Error)
4445 *
4446 */
lsm6dsox_aux_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsox_fs_xl_ois_t val)4447 int32_t lsm6dsox_aux_xl_full_scale_set(const stmdev_ctx_t *ctx,
4448 lsm6dsox_fs_xl_ois_t val)
4449 {
4450 lsm6dsox_ui_ctrl3_ois_t reg;
4451 int32_t ret;
4452
4453 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1);
4454
4455 if (ret == 0)
4456 {
4457 reg.fs_xl_ois = (uint8_t)val;
4458 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1);
4459 }
4460
4461 return ret;
4462 }
4463
4464 /**
4465 * @brief Selects accelerometer OIS channel full-scale.[get]
4466 *
4467 * @param ctx read / write interface definitions
4468 * @param val Get the values of fs_xl_ois in reg CTRL3_OIS
4469 * @retval interface status (MANDATORY: return 0 -> no Error)
4470 *
4471 */
lsm6dsox_aux_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsox_fs_xl_ois_t * val)4472 int32_t lsm6dsox_aux_xl_full_scale_get(const stmdev_ctx_t *ctx,
4473 lsm6dsox_fs_xl_ois_t *val)
4474 {
4475 lsm6dsox_ui_ctrl3_ois_t reg;
4476 int32_t ret;
4477
4478 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL3_OIS, (uint8_t *)®, 1);
4479
4480 switch (reg.fs_xl_ois)
4481 {
4482 case LSM6DSOX_AUX_2g:
4483 *val = LSM6DSOX_AUX_2g;
4484 break;
4485
4486 case LSM6DSOX_AUX_16g:
4487 *val = LSM6DSOX_AUX_16g;
4488 break;
4489
4490 case LSM6DSOX_AUX_4g:
4491 *val = LSM6DSOX_AUX_4g;
4492 break;
4493
4494 case LSM6DSOX_AUX_8g:
4495 *val = LSM6DSOX_AUX_8g;
4496 break;
4497
4498 default:
4499 *val = LSM6DSOX_AUX_2g;
4500 break;
4501 }
4502
4503 return ret;
4504 }
4505
4506 /**
4507 * @}
4508 *
4509 */
4510
4511 /**
4512 * @defgroup LSM6DSOX_ main_serial_interface
4513 * @brief This section groups all the functions concerning main
4514 * serial interface management (not auxiliary)
4515 * @{
4516 *
4517 */
4518
4519 /**
4520 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
4521 *
4522 * @param ctx read / write interface definitions
4523 * @param val change the values of sdo_pu_en in
4524 * reg PIN_CTRL
4525 * @retval interface status (MANDATORY: return 0 -> no Error)
4526 *
4527 */
lsm6dsox_sdo_sa0_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_sdo_pu_en_t val)4528 int32_t lsm6dsox_sdo_sa0_mode_set(const stmdev_ctx_t *ctx,
4529 lsm6dsox_sdo_pu_en_t val)
4530 {
4531 lsm6dsox_pin_ctrl_t reg;
4532 int32_t ret;
4533
4534 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)®, 1);
4535
4536 if (ret == 0)
4537 {
4538 reg.sdo_pu_en = (uint8_t)val;
4539 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)®, 1);
4540 }
4541
4542 return ret;
4543 }
4544
4545 /**
4546 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
4547 *
4548 * @param ctx read / write interface definitions
4549 * @param val Get the values of sdo_pu_en in reg PIN_CTRL
4550 * @retval interface status (MANDATORY: return 0 -> no Error)
4551 *
4552 */
lsm6dsox_sdo_sa0_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_sdo_pu_en_t * val)4553 int32_t lsm6dsox_sdo_sa0_mode_get(const stmdev_ctx_t *ctx,
4554 lsm6dsox_sdo_pu_en_t *val)
4555 {
4556 lsm6dsox_pin_ctrl_t reg;
4557 int32_t ret;
4558
4559 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)®, 1);
4560
4561 switch (reg.sdo_pu_en)
4562 {
4563 case LSM6DSOX_PULL_UP_DISC:
4564 *val = LSM6DSOX_PULL_UP_DISC;
4565 break;
4566
4567 case LSM6DSOX_PULL_UP_CONNECT:
4568 *val = LSM6DSOX_PULL_UP_CONNECT;
4569 break;
4570
4571 default:
4572 *val = LSM6DSOX_PULL_UP_DISC;
4573 break;
4574 }
4575
4576 return ret;
4577 }
4578
4579 /**
4580 * @brief SPI Serial Interface Mode selection.[set]
4581 *
4582 * @param ctx read / write interface definitions
4583 * @param val change the values of sim in reg CTRL3_C
4584 * @retval interface status (MANDATORY: return 0 -> no Error)
4585 *
4586 */
lsm6dsox_spi_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_sim_t val)4587 int32_t lsm6dsox_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_sim_t val)
4588 {
4589 lsm6dsox_ctrl3_c_t reg;
4590 int32_t ret;
4591
4592 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
4593
4594 if (ret == 0)
4595 {
4596 reg.sim = (uint8_t)val;
4597 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
4598 }
4599
4600 return ret;
4601 }
4602
4603 /**
4604 * @brief SPI Serial Interface Mode selection.[get]
4605 *
4606 * @param ctx read / write interface definitions
4607 * @param val Get the values of sim in reg CTRL3_C
4608 * @retval interface status (MANDATORY: return 0 -> no Error)
4609 *
4610 */
lsm6dsox_spi_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_sim_t * val)4611 int32_t lsm6dsox_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsox_sim_t *val)
4612 {
4613 lsm6dsox_ctrl3_c_t reg;
4614 int32_t ret;
4615
4616 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
4617
4618 switch (reg.sim)
4619 {
4620 case LSM6DSOX_SPI_4_WIRE:
4621 *val = LSM6DSOX_SPI_4_WIRE;
4622 break;
4623
4624 case LSM6DSOX_SPI_3_WIRE:
4625 *val = LSM6DSOX_SPI_3_WIRE;
4626 break;
4627
4628 default:
4629 *val = LSM6DSOX_SPI_4_WIRE;
4630 break;
4631 }
4632
4633 return ret;
4634 }
4635
4636 /**
4637 * @brief Disable / Enable I2C interface.[set]
4638 *
4639 * @param ctx read / write interface definitions
4640 * @param val change the values of i2c_disable in
4641 * reg CTRL4_C
4642 * @retval interface status (MANDATORY: return 0 -> no Error)
4643 *
4644 */
lsm6dsox_i2c_interface_set(const stmdev_ctx_t * ctx,lsm6dsox_i2c_disable_t val)4645 int32_t lsm6dsox_i2c_interface_set(const stmdev_ctx_t *ctx,
4646 lsm6dsox_i2c_disable_t val)
4647 {
4648 lsm6dsox_ctrl4_c_t reg;
4649 int32_t ret;
4650
4651 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
4652
4653 if (ret == 0)
4654 {
4655 reg.i2c_disable = (uint8_t)val;
4656 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
4657 }
4658
4659 return ret;
4660 }
4661
4662 /**
4663 * @brief Disable / Enable I2C interface.[get]
4664 *
4665 * @param ctx read / write interface definitions
4666 * @param val Get the values of i2c_disable in
4667 * reg CTRL4_C
4668 * @retval interface status (MANDATORY: return 0 -> no Error)
4669 *
4670 */
lsm6dsox_i2c_interface_get(const stmdev_ctx_t * ctx,lsm6dsox_i2c_disable_t * val)4671 int32_t lsm6dsox_i2c_interface_get(const stmdev_ctx_t *ctx,
4672 lsm6dsox_i2c_disable_t *val)
4673 {
4674 lsm6dsox_ctrl4_c_t reg;
4675 int32_t ret;
4676
4677 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
4678
4679 switch (reg.i2c_disable)
4680 {
4681 case LSM6DSOX_I2C_ENABLE:
4682 *val = LSM6DSOX_I2C_ENABLE;
4683 break;
4684
4685 case LSM6DSOX_I2C_DISABLE:
4686 *val = LSM6DSOX_I2C_DISABLE;
4687 break;
4688
4689 default:
4690 *val = LSM6DSOX_I2C_ENABLE;
4691 break;
4692 }
4693
4694 return ret;
4695 }
4696
4697 /**
4698 * @brief I3C Enable/Disable communication protocol[.set]
4699 *
4700 * @param ctx read / write interface definitions
4701 * @param val change the values of i3c_disable
4702 * in reg CTRL9_XL
4703 * @retval interface status (MANDATORY: return 0 -> no Error)
4704 *
4705 */
lsm6dsox_i3c_disable_set(const stmdev_ctx_t * ctx,lsm6dsox_i3c_disable_t val)4706 int32_t lsm6dsox_i3c_disable_set(const stmdev_ctx_t *ctx,
4707 lsm6dsox_i3c_disable_t val)
4708 {
4709 lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
4710 lsm6dsox_ctrl9_xl_t ctrl9_xl;
4711 int32_t ret;
4712
4713 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
4714
4715 if (ret == 0)
4716 {
4717 ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
4718 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
4719 }
4720
4721 if (ret == 0)
4722 {
4723 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
4724 (uint8_t *)&i3c_bus_avb, 1);
4725 }
4726
4727 if (ret == 0)
4728 {
4729 i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
4730 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
4731 (uint8_t *)&i3c_bus_avb, 1);
4732 }
4733
4734 return ret;
4735 }
4736
4737 /**
4738 * @brief I3C Enable/Disable communication protocol.[get]
4739 *
4740 * @param ctx read / write interface definitions
4741 * @param val change the values of i3c_disable in
4742 * reg CTRL9_XL
4743 * @retval interface status (MANDATORY: return 0 -> no Error)
4744 *
4745 */
lsm6dsox_i3c_disable_get(const stmdev_ctx_t * ctx,lsm6dsox_i3c_disable_t * val)4746 int32_t lsm6dsox_i3c_disable_get(const stmdev_ctx_t *ctx,
4747 lsm6dsox_i3c_disable_t *val)
4748 {
4749 lsm6dsox_ctrl9_xl_t ctrl9_xl;
4750 lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
4751 int32_t ret;
4752
4753 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
4754
4755 if (ret == 0)
4756 {
4757 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
4758 (uint8_t *)&i3c_bus_avb, 1);
4759
4760 switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel)
4761 {
4762 case LSM6DSOX_I3C_DISABLE:
4763 *val = LSM6DSOX_I3C_DISABLE;
4764 break;
4765
4766 case LSM6DSOX_I3C_ENABLE_T_50us:
4767 *val = LSM6DSOX_I3C_ENABLE_T_50us;
4768 break;
4769
4770 case LSM6DSOX_I3C_ENABLE_T_2us:
4771 *val = LSM6DSOX_I3C_ENABLE_T_2us;
4772 break;
4773
4774 case LSM6DSOX_I3C_ENABLE_T_1ms:
4775 *val = LSM6DSOX_I3C_ENABLE_T_1ms;
4776 break;
4777
4778 case LSM6DSOX_I3C_ENABLE_T_25ms:
4779 *val = LSM6DSOX_I3C_ENABLE_T_25ms;
4780 break;
4781
4782 default:
4783 *val = LSM6DSOX_I3C_DISABLE;
4784 break;
4785 }
4786 }
4787
4788 return ret;
4789 }
4790
4791 /**
4792 * @}
4793 *
4794 */
4795
4796 /**
4797 * @defgroup LSM6DSOX_interrupt_pins
4798 * @brief This section groups all the functions that manage interrupt pins
4799 * @{
4800 *
4801 */
4802
4803 /**
4804 * @brief Push-pull/open drain selection on interrupt pads.[set]
4805 *
4806 * @param ctx read / write interface definitions
4807 * @param val change the values of pp_od in reg CTRL3_C
4808 * @retval interface status (MANDATORY: return 0 -> no Error)
4809 *
4810 */
lsm6dsox_pin_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_pp_od_t val)4811 int32_t lsm6dsox_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsox_pp_od_t val)
4812 {
4813 lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
4814 lsm6dsox_ctrl3_c_t ctrl3_c;
4815 int32_t ret;
4816
4817 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4818
4819 if (ret == 0)
4820 {
4821 ctrl3_c.pp_od = (uint8_t)val;
4822 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4823 }
4824
4825 if (ret == 0)
4826 {
4827 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
4828 (uint8_t *)&i3c_bus_avb, 1);
4829 }
4830
4831 if (ret == 0)
4832 {
4833 i3c_bus_avb.pd_dis_int1 = ((uint8_t) val & 0x02U) >> 1;
4834 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
4835 (uint8_t *)&i3c_bus_avb, 1);
4836 }
4837
4838 return ret;
4839 }
4840
4841 /**
4842 * @brief Push-pull/open drain selection on interrupt pads.[get]
4843 *
4844 * @param ctx read / write interface definitions
4845 * @param val Get the values of pp_od in reg CTRL3_C
4846 * @retval interface status (MANDATORY: return 0 -> no Error)
4847 *
4848 */
lsm6dsox_pin_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_pp_od_t * val)4849 int32_t lsm6dsox_pin_mode_get(const stmdev_ctx_t *ctx,
4850 lsm6dsox_pp_od_t *val)
4851 {
4852 lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
4853 lsm6dsox_ctrl3_c_t ctrl3_c;
4854 int32_t ret;
4855
4856 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4857
4858 if (ret == 0)
4859 {
4860 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
4861 (uint8_t *)&i3c_bus_avb, 1);
4862 }
4863
4864 switch ((i3c_bus_avb.pd_dis_int1 << 1) + ctrl3_c.pp_od)
4865 {
4866 case LSM6DSOX_PUSH_PULL:
4867 *val = LSM6DSOX_PUSH_PULL;
4868 break;
4869
4870 case LSM6DSOX_OPEN_DRAIN:
4871 *val = LSM6DSOX_OPEN_DRAIN;
4872 break;
4873
4874 case LSM6DSOX_INT1_NOPULL_DOWN_INT2_PUSH_PULL:
4875 *val = LSM6DSOX_INT1_NOPULL_DOWN_INT2_PUSH_PULL;
4876 break;
4877
4878 case LSM6DSOX_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN:
4879 *val = LSM6DSOX_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN;
4880 break;
4881
4882 default:
4883 *val = LSM6DSOX_PUSH_PULL;
4884 break;
4885 }
4886
4887 return ret;
4888 }
4889
4890 /**
4891 * @brief Interrupt active-high/low.[set]
4892 *
4893 * @param ctx read / write interface definitions
4894 * @param val change the values of h_lactive in reg CTRL3_C
4895 * @retval interface status (MANDATORY: return 0 -> no Error)
4896 *
4897 */
lsm6dsox_pin_polarity_set(const stmdev_ctx_t * ctx,lsm6dsox_h_lactive_t val)4898 int32_t lsm6dsox_pin_polarity_set(const stmdev_ctx_t *ctx,
4899 lsm6dsox_h_lactive_t val)
4900 {
4901 lsm6dsox_ctrl3_c_t reg;
4902 int32_t ret;
4903
4904 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
4905
4906 if (ret == 0)
4907 {
4908 reg.h_lactive = (uint8_t)val;
4909 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
4910 }
4911
4912 return ret;
4913 }
4914
4915 /**
4916 * @brief Interrupt active-high/low.[get]
4917 *
4918 * @param ctx read / write interface definitions
4919 * @param val Get the values of h_lactive in reg CTRL3_C
4920 * @retval interface status (MANDATORY: return 0 -> no Error)
4921 *
4922 */
lsm6dsox_pin_polarity_get(const stmdev_ctx_t * ctx,lsm6dsox_h_lactive_t * val)4923 int32_t lsm6dsox_pin_polarity_get(const stmdev_ctx_t *ctx,
4924 lsm6dsox_h_lactive_t *val)
4925 {
4926 lsm6dsox_ctrl3_c_t reg;
4927 int32_t ret;
4928
4929 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)®, 1);
4930
4931 switch (reg.h_lactive)
4932 {
4933 case LSM6DSOX_ACTIVE_HIGH:
4934 *val = LSM6DSOX_ACTIVE_HIGH;
4935 break;
4936
4937 case LSM6DSOX_ACTIVE_LOW:
4938 *val = LSM6DSOX_ACTIVE_LOW;
4939 break;
4940
4941 default:
4942 *val = LSM6DSOX_ACTIVE_HIGH;
4943 break;
4944 }
4945
4946 return ret;
4947 }
4948
4949 /**
4950 * @brief All interrupt signals become available on INT1 pin.[set]
4951 *
4952 * @param ctx read / write interface definitions
4953 * @param val change the values of int2_on_int1 in reg CTRL4_C
4954 * @retval interface status (MANDATORY: return 0 -> no Error)
4955 *
4956 */
lsm6dsox_all_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)4957 int32_t lsm6dsox_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
4958 {
4959 lsm6dsox_ctrl4_c_t reg;
4960 int32_t ret;
4961
4962 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
4963
4964 if (ret == 0)
4965 {
4966 reg.int2_on_int1 = val;
4967 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
4968 }
4969
4970 return ret;
4971 }
4972
4973 /**
4974 * @brief All interrupt signals become available on INT1 pin.[get]
4975 *
4976 * @param ctx read / write interface definitions
4977 * @param val change the values of int2_on_int1 in reg CTRL4_C
4978 * @retval interface status (MANDATORY: return 0 -> no Error)
4979 *
4980 */
lsm6dsox_all_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)4981 int32_t lsm6dsox_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
4982 {
4983 lsm6dsox_ctrl4_c_t reg;
4984 int32_t ret;
4985
4986 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
4987 *val = reg.int2_on_int1;
4988
4989 return ret;
4990 }
4991
4992 /**
4993 * @brief Interrupt notification mode.[set]
4994 *
4995 * @param ctx read / write interface definitions
4996 * @param val change the values of lir in reg TAP_CFG0
4997 * @retval interface status (MANDATORY: return 0 -> no Error)
4998 *
4999 */
lsm6dsox_int_notification_set(const stmdev_ctx_t * ctx,lsm6dsox_lir_t val)5000 int32_t lsm6dsox_int_notification_set(const stmdev_ctx_t *ctx,
5001 lsm6dsox_lir_t val)
5002 {
5003 lsm6dsox_tap_cfg0_t tap_cfg0;
5004 lsm6dsox_page_rw_t page_rw;
5005 int32_t ret;
5006
5007 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
5008
5009 if (ret == 0)
5010 {
5011 tap_cfg0.lir = (uint8_t)val & 0x01U;
5012 tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
5013 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0,
5014 (uint8_t *) &tap_cfg0, 1);
5015 }
5016
5017 if (ret == 0)
5018 {
5019 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
5020 }
5021
5022 if (ret == 0)
5023 {
5024 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
5025 }
5026
5027 if (ret == 0)
5028 {
5029 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
5030 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
5031 }
5032
5033 if (ret == 0)
5034 {
5035 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
5036 }
5037
5038 return ret;
5039 }
5040
5041 /**
5042 * @brief Interrupt notification mode.[get]
5043 *
5044 * @param ctx read / write interface definitions
5045 * @param val Get the values of lir in reg TAP_CFG0
5046 * @retval interface status (MANDATORY: return 0 -> no Error)
5047 *
5048 */
lsm6dsox_int_notification_get(const stmdev_ctx_t * ctx,lsm6dsox_lir_t * val)5049 int32_t lsm6dsox_int_notification_get(const stmdev_ctx_t *ctx,
5050 lsm6dsox_lir_t *val)
5051 {
5052 lsm6dsox_tap_cfg0_t tap_cfg0;
5053 lsm6dsox_page_rw_t page_rw;
5054 int32_t ret;
5055
5056 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
5057
5058 if (ret == 0)
5059 {
5060 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
5061 }
5062
5063 if (ret == 0)
5064 {
5065 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
5066 }
5067
5068 if (ret == 0)
5069 {
5070 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
5071 }
5072
5073 if (ret == 0)
5074 {
5075 switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir)
5076 {
5077 case LSM6DSOX_ALL_INT_PULSED:
5078 *val = LSM6DSOX_ALL_INT_PULSED;
5079 break;
5080
5081 case LSM6DSOX_BASE_LATCHED_EMB_PULSED:
5082 *val = LSM6DSOX_BASE_LATCHED_EMB_PULSED;
5083 break;
5084
5085 case LSM6DSOX_BASE_PULSED_EMB_LATCHED:
5086 *val = LSM6DSOX_BASE_PULSED_EMB_LATCHED;
5087 break;
5088
5089 case LSM6DSOX_ALL_INT_LATCHED:
5090 *val = LSM6DSOX_ALL_INT_LATCHED;
5091 break;
5092
5093 default:
5094 *val = LSM6DSOX_ALL_INT_PULSED;
5095 break;
5096 }
5097
5098 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
5099 }
5100
5101 if (ret == 0)
5102 {
5103 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
5104 }
5105
5106 if (ret == 0)
5107 {
5108 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
5109 }
5110
5111 return ret;
5112 }
5113
5114 /**
5115 * @}
5116 *
5117 */
5118
5119 /**
5120 * @defgroup LSM6DSOX_Wake_Up_event
5121 * @brief This section groups all the functions that manage the Wake Up
5122 * event generation.
5123 * @{
5124 *
5125 */
5126
5127 /**
5128 * @brief Weight of 1 LSB of wakeup threshold.[set]
5129 * 0: 1 LSB =FS_XL / 64
5130 * 1: 1 LSB = FS_XL / 256
5131 *
5132 * @param ctx read / write interface definitions
5133 * @param val change the values of wake_ths_w in
5134 * reg WAKE_UP_DUR
5135 * @retval interface status (MANDATORY: return 0 -> no Error)
5136 *
5137 */
lsm6dsox_wkup_ths_weight_set(const stmdev_ctx_t * ctx,lsm6dsox_wake_ths_w_t val)5138 int32_t lsm6dsox_wkup_ths_weight_set(const stmdev_ctx_t *ctx,
5139 lsm6dsox_wake_ths_w_t val)
5140 {
5141 lsm6dsox_wake_up_dur_t reg;
5142 int32_t ret;
5143
5144 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1);
5145
5146 if (ret == 0)
5147 {
5148 reg.wake_ths_w = (uint8_t)val;
5149 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1);
5150 }
5151
5152 return ret;
5153 }
5154
5155 /**
5156 * @brief Weight of 1 LSB of wakeup threshold.[get]
5157 * 0: 1 LSB =FS_XL / 64
5158 * 1: 1 LSB = FS_XL / 256
5159 *
5160 * @param ctx read / write interface definitions
5161 * @param val Get the values of wake_ths_w in
5162 * reg WAKE_UP_DUR
5163 * @retval interface status (MANDATORY: return 0 -> no Error)
5164 *
5165 */
lsm6dsox_wkup_ths_weight_get(const stmdev_ctx_t * ctx,lsm6dsox_wake_ths_w_t * val)5166 int32_t lsm6dsox_wkup_ths_weight_get(const stmdev_ctx_t *ctx,
5167 lsm6dsox_wake_ths_w_t *val)
5168 {
5169 lsm6dsox_wake_up_dur_t reg;
5170 int32_t ret;
5171
5172 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1);
5173
5174 switch (reg.wake_ths_w)
5175 {
5176 case LSM6DSOX_LSb_FS_DIV_64:
5177 *val = LSM6DSOX_LSb_FS_DIV_64;
5178 break;
5179
5180 case LSM6DSOX_LSb_FS_DIV_256:
5181 *val = LSM6DSOX_LSb_FS_DIV_256;
5182 break;
5183
5184 default:
5185 *val = LSM6DSOX_LSb_FS_DIV_64;
5186 break;
5187 }
5188
5189 return ret;
5190 }
5191
5192 /**
5193 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
5194 * WAKE_UP_DUR.[set]
5195 *
5196 * @param ctx read / write interface definitions
5197 * @param val change the values of wk_ths in reg WAKE_UP_THS
5198 * @retval interface status (MANDATORY: return 0 -> no Error)
5199 *
5200 */
lsm6dsox_wkup_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)5201 int32_t lsm6dsox_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
5202 {
5203 lsm6dsox_wake_up_ths_t reg;
5204 int32_t ret;
5205
5206 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1);
5207
5208 if (ret == 0)
5209 {
5210 reg.wk_ths = val;
5211 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1);
5212 }
5213
5214 return ret;
5215 }
5216
5217 /**
5218 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
5219 * WAKE_UP_DUR.[get]
5220 *
5221 * @param ctx read / write interface definitions
5222 * @param val change the values of wk_ths in reg WAKE_UP_THS
5223 * @retval interface status (MANDATORY: return 0 -> no Error)
5224 *
5225 */
lsm6dsox_wkup_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)5226 int32_t lsm6dsox_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
5227 {
5228 lsm6dsox_wake_up_ths_t reg;
5229 int32_t ret;
5230
5231 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1);
5232 *val = reg.wk_ths;
5233
5234 return ret;
5235 }
5236
5237 /**
5238 * @brief Wake up duration event.[set]
5239 * 1LSb = 1 / ODR
5240 *
5241 * @param ctx read / write interface definitions
5242 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
5243 * @retval interface status (MANDATORY: return 0 -> no Error)
5244 *
5245 */
lsm6dsox_xl_usr_offset_on_wkup_set(const stmdev_ctx_t * ctx,uint8_t val)5246 int32_t lsm6dsox_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx,
5247 uint8_t val)
5248 {
5249 lsm6dsox_wake_up_ths_t reg;
5250 int32_t ret;
5251
5252 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1);
5253
5254 if (ret == 0)
5255 {
5256 reg.usr_off_on_wu = val;
5257 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1);
5258 }
5259
5260 return ret;
5261 }
5262
5263 /**
5264 * @brief Wake up duration event.[get]
5265 * 1LSb = 1 / ODR
5266 *
5267 * @param ctx read / write interface definitions
5268 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
5269 * @retval interface status (MANDATORY: return 0 -> no Error)
5270 *
5271 */
lsm6dsox_xl_usr_offset_on_wkup_get(const stmdev_ctx_t * ctx,uint8_t * val)5272 int32_t lsm6dsox_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx,
5273 uint8_t *val)
5274 {
5275 lsm6dsox_wake_up_ths_t reg;
5276 int32_t ret;
5277
5278 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1);
5279 *val = reg.usr_off_on_wu;
5280
5281 return ret;
5282 }
5283
5284 /**
5285 * @brief Wake up duration event.[set]
5286 * 1LSb = 1 / ODR
5287 *
5288 * @param ctx read / write interface definitions
5289 * @param val change the values of wake_dur in reg WAKE_UP_DUR
5290 * @retval interface status (MANDATORY: return 0 -> no Error)
5291 *
5292 */
lsm6dsox_wkup_dur_set(const stmdev_ctx_t * ctx,uint8_t val)5293 int32_t lsm6dsox_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
5294 {
5295 lsm6dsox_wake_up_dur_t reg;
5296 int32_t ret;
5297
5298 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1);
5299
5300 if (ret == 0)
5301 {
5302 reg.wake_dur = val;
5303 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1);
5304 }
5305
5306 return ret;
5307 }
5308
5309 /**
5310 * @brief Wake up duration event.[get]
5311 * 1LSb = 1 / ODR
5312 *
5313 * @param ctx read / write interface definitions
5314 * @param val change the values of wake_dur in reg WAKE_UP_DUR
5315 * @retval interface status (MANDATORY: return 0 -> no Error)
5316 *
5317 */
lsm6dsox_wkup_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)5318 int32_t lsm6dsox_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
5319 {
5320 lsm6dsox_wake_up_dur_t reg;
5321 int32_t ret;
5322
5323 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1);
5324 *val = reg.wake_dur;
5325
5326 return ret;
5327 }
5328
5329 /**
5330 * @}
5331 *
5332 */
5333
5334 /**
5335 * @defgroup LSM6DSOX_ Activity/Inactivity_detection
5336 * @brief This section groups all the functions concerning
5337 * activity/inactivity detection.
5338 * @{
5339 *
5340 */
5341
5342 /**
5343 * @brief Enables gyroscope Sleep mode.[set]
5344 *
5345 * @param ctx read / write interface definitions
5346 * @param val change the values of sleep_g in reg CTRL4_C
5347 * @retval interface status (MANDATORY: return 0 -> no Error)
5348 *
5349 */
lsm6dsox_gy_sleep_mode_set(const stmdev_ctx_t * ctx,uint8_t val)5350 int32_t lsm6dsox_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
5351 {
5352 lsm6dsox_ctrl4_c_t reg;
5353 int32_t ret;
5354
5355 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
5356
5357 if (ret == 0)
5358 {
5359 reg.sleep_g = val;
5360 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
5361 }
5362
5363 return ret;
5364 }
5365
5366 /**
5367 * @brief Enables gyroscope Sleep mode.[get]
5368 *
5369 * @param ctx read / write interface definitions
5370 * @param val change the values of sleep_g in reg CTRL4_C
5371 * @retval interface status (MANDATORY: return 0 -> no Error)
5372 *
5373 */
lsm6dsox_gy_sleep_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)5374 int32_t lsm6dsox_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
5375 {
5376 lsm6dsox_ctrl4_c_t reg;
5377 int32_t ret;
5378
5379 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)®, 1);
5380 *val = reg.sleep_g;
5381
5382 return ret;
5383 }
5384
5385 /**
5386 * @brief Drives the sleep status instead of
5387 * sleep change on INT pins
5388 * (only if INT1_SLEEP_CHANGE or
5389 * INT2_SLEEP_CHANGE bits are enabled).[set]
5390 *
5391 * @param ctx read / write interface definitions
5392 * @param val change the values of sleep_status_on_int in reg TAP_CFG0
5393 * @retval interface status (MANDATORY: return 0 -> no Error)
5394 *
5395 */
lsm6dsox_act_pin_notification_set(const stmdev_ctx_t * ctx,lsm6dsox_sleep_status_on_int_t val)5396 int32_t lsm6dsox_act_pin_notification_set(const stmdev_ctx_t *ctx,
5397 lsm6dsox_sleep_status_on_int_t val)
5398 {
5399 lsm6dsox_tap_cfg0_t reg;
5400 int32_t ret;
5401
5402 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
5403
5404 if (ret == 0)
5405 {
5406 reg.sleep_status_on_int = (uint8_t)val;
5407 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
5408 }
5409
5410 return ret;
5411 }
5412
5413 /**
5414 * @brief Drives the sleep status instead of
5415 * sleep change on INT pins (only if
5416 * INT1_SLEEP_CHANGE or
5417 * INT2_SLEEP_CHANGE bits are enabled).[get]
5418 *
5419 * @param ctx read / write interface definitions
5420 * @param val Get the values of sleep_status_on_int in reg TAP_CFG0
5421 * @retval interface status (MANDATORY: return 0 -> no Error)
5422 *
5423 */
lsm6dsox_act_pin_notification_get(const stmdev_ctx_t * ctx,lsm6dsox_sleep_status_on_int_t * val)5424 int32_t lsm6dsox_act_pin_notification_get(const stmdev_ctx_t *ctx,
5425 lsm6dsox_sleep_status_on_int_t *val)
5426 {
5427 lsm6dsox_tap_cfg0_t reg;
5428 int32_t ret;
5429
5430 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
5431
5432 switch (reg.sleep_status_on_int)
5433 {
5434 case LSM6DSOX_DRIVE_SLEEP_CHG_EVENT:
5435 *val = LSM6DSOX_DRIVE_SLEEP_CHG_EVENT;
5436 break;
5437
5438 case LSM6DSOX_DRIVE_SLEEP_STATUS:
5439 *val = LSM6DSOX_DRIVE_SLEEP_STATUS;
5440 break;
5441
5442 default:
5443 *val = LSM6DSOX_DRIVE_SLEEP_CHG_EVENT;
5444 break;
5445 }
5446
5447 return ret;
5448 }
5449
5450 /**
5451 * @brief Enable inactivity function.[set]
5452 *
5453 * @param ctx read / write interface definitions
5454 * @param val change the values of inact_en in reg TAP_CFG2
5455 * @retval interface status (MANDATORY: return 0 -> no Error)
5456 *
5457 */
lsm6dsox_act_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_inact_en_t val)5458 int32_t lsm6dsox_act_mode_set(const stmdev_ctx_t *ctx,
5459 lsm6dsox_inact_en_t val)
5460 {
5461 lsm6dsox_tap_cfg2_t reg;
5462 int32_t ret;
5463
5464 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t *)®, 1);
5465
5466 if (ret == 0)
5467 {
5468 reg.inact_en = (uint8_t)val;
5469 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t *)®, 1);
5470 }
5471
5472 return ret;
5473 }
5474
5475 /**
5476 * @brief Enable inactivity function.[get]
5477 *
5478 * @param ctx read / write interface definitions
5479 * @param val Get the values of inact_en in reg TAP_CFG2
5480 * @retval interface status (MANDATORY: return 0 -> no Error)
5481 *
5482 */
lsm6dsox_act_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_inact_en_t * val)5483 int32_t lsm6dsox_act_mode_get(const stmdev_ctx_t *ctx,
5484 lsm6dsox_inact_en_t *val)
5485 {
5486 lsm6dsox_tap_cfg2_t reg;
5487 int32_t ret;
5488
5489 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t *)®, 1);
5490
5491 switch (reg.inact_en)
5492 {
5493 case LSM6DSOX_XL_AND_GY_NOT_AFFECTED:
5494 *val = LSM6DSOX_XL_AND_GY_NOT_AFFECTED;
5495 break;
5496
5497 case LSM6DSOX_XL_12Hz5_GY_NOT_AFFECTED:
5498 *val = LSM6DSOX_XL_12Hz5_GY_NOT_AFFECTED;
5499 break;
5500
5501 case LSM6DSOX_XL_12Hz5_GY_SLEEP:
5502 *val = LSM6DSOX_XL_12Hz5_GY_SLEEP;
5503 break;
5504
5505 case LSM6DSOX_XL_12Hz5_GY_PD:
5506 *val = LSM6DSOX_XL_12Hz5_GY_PD;
5507 break;
5508
5509 default:
5510 *val = LSM6DSOX_XL_AND_GY_NOT_AFFECTED;
5511 break;
5512 }
5513
5514 return ret;
5515 }
5516
5517 /**
5518 * @brief Duration to go in sleep mode.[set]
5519 * 1 LSb = 512 / ODR
5520 *
5521 * @param ctx read / write interface definitions
5522 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
5523 * @retval interface status (MANDATORY: return 0 -> no Error)
5524 *
5525 */
lsm6dsox_act_sleep_dur_set(const stmdev_ctx_t * ctx,uint8_t val)5526 int32_t lsm6dsox_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
5527 {
5528 lsm6dsox_wake_up_dur_t reg;
5529 int32_t ret;
5530
5531 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1);
5532
5533 if (ret == 0)
5534 {
5535 reg.sleep_dur = val;
5536 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1);
5537 }
5538
5539 return ret;
5540 }
5541
5542 /**
5543 * @brief Duration to go in sleep mode.[get]
5544 * 1 LSb = 512 / ODR
5545 *
5546 * @param ctx read / write interface definitions
5547 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
5548 * @retval interface status (MANDATORY: return 0 -> no Error)
5549 *
5550 */
lsm6dsox_act_sleep_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)5551 int32_t lsm6dsox_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
5552 {
5553 lsm6dsox_wake_up_dur_t reg;
5554 int32_t ret;
5555
5556 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR, (uint8_t *)®, 1);
5557 *val = reg.sleep_dur;
5558
5559 return ret;
5560 }
5561
5562 /**
5563 * @}
5564 *
5565 */
5566
5567 /**
5568 * @defgroup LSM6DSOX_tap_generator
5569 * @brief This section groups all the functions that manage the
5570 * tap and double tap event generation.
5571 * @{
5572 *
5573 */
5574
5575 /**
5576 * @brief Enable Z direction in tap recognition.[set]
5577 *
5578 * @param ctx read / write interface definitions
5579 * @param val change the values of tap_z_en in reg TAP_CFG0
5580 * @retval interface status (MANDATORY: return 0 -> no Error)
5581 *
5582 */
lsm6dsox_tap_detection_on_z_set(const stmdev_ctx_t * ctx,uint8_t val)5583 int32_t lsm6dsox_tap_detection_on_z_set(const stmdev_ctx_t *ctx,
5584 uint8_t val)
5585 {
5586 lsm6dsox_tap_cfg0_t reg;
5587 int32_t ret;
5588
5589 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
5590
5591 if (ret == 0)
5592 {
5593 reg.tap_z_en = val;
5594 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
5595 }
5596
5597 return ret;
5598 }
5599
5600 /**
5601 * @brief Enable Z direction in tap recognition.[get]
5602 *
5603 * @param ctx read / write interface definitions
5604 * @param val change the values of tap_z_en in reg TAP_CFG0
5605 * @retval interface status (MANDATORY: return 0 -> no Error)
5606 *
5607 */
lsm6dsox_tap_detection_on_z_get(const stmdev_ctx_t * ctx,uint8_t * val)5608 int32_t lsm6dsox_tap_detection_on_z_get(const stmdev_ctx_t *ctx,
5609 uint8_t *val)
5610 {
5611 lsm6dsox_tap_cfg0_t reg;
5612 int32_t ret;
5613
5614 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
5615 *val = reg.tap_z_en;
5616
5617 return ret;
5618 }
5619
5620 /**
5621 * @brief Enable Y direction in tap recognition.[set]
5622 *
5623 * @param ctx read / write interface definitions
5624 * @param val change the values of tap_y_en in reg TAP_CFG0
5625 * @retval interface status (MANDATORY: return 0 -> no Error)
5626 *
5627 */
lsm6dsox_tap_detection_on_y_set(const stmdev_ctx_t * ctx,uint8_t val)5628 int32_t lsm6dsox_tap_detection_on_y_set(const stmdev_ctx_t *ctx,
5629 uint8_t val)
5630 {
5631 lsm6dsox_tap_cfg0_t reg;
5632 int32_t ret;
5633
5634 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
5635
5636 if (ret == 0)
5637 {
5638 reg.tap_y_en = val;
5639 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
5640 }
5641
5642 return ret;
5643 }
5644
5645 /**
5646 * @brief Enable Y direction in tap recognition.[get]
5647 *
5648 * @param ctx read / write interface definitions
5649 * @param val change the values of tap_y_en in reg TAP_CFG0
5650 * @retval interface status (MANDATORY: return 0 -> no Error)
5651 *
5652 */
lsm6dsox_tap_detection_on_y_get(const stmdev_ctx_t * ctx,uint8_t * val)5653 int32_t lsm6dsox_tap_detection_on_y_get(const stmdev_ctx_t *ctx,
5654 uint8_t *val)
5655 {
5656 lsm6dsox_tap_cfg0_t reg;
5657 int32_t ret;
5658
5659 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
5660 *val = reg.tap_y_en;
5661
5662 return ret;
5663 }
5664
5665 /**
5666 * @brief Enable X direction in tap recognition.[set]
5667 *
5668 * @param ctx read / write interface definitions
5669 * @param val change the values of tap_x_en in reg TAP_CFG0
5670 * @retval interface status (MANDATORY: return 0 -> no Error)
5671 *
5672 */
lsm6dsox_tap_detection_on_x_set(const stmdev_ctx_t * ctx,uint8_t val)5673 int32_t lsm6dsox_tap_detection_on_x_set(const stmdev_ctx_t *ctx,
5674 uint8_t val)
5675 {
5676 lsm6dsox_tap_cfg0_t reg;
5677 int32_t ret;
5678
5679 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
5680
5681 if (ret == 0)
5682 {
5683 reg.tap_x_en = val;
5684 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
5685 }
5686
5687 return ret;
5688 }
5689
5690 /**
5691 * @brief Enable X direction in tap recognition.[get]
5692 *
5693 * @param ctx read / write interface definitions
5694 * @param val change the values of tap_x_en in reg TAP_CFG0
5695 * @retval interface status (MANDATORY: return 0 -> no Error)
5696 *
5697 */
lsm6dsox_tap_detection_on_x_get(const stmdev_ctx_t * ctx,uint8_t * val)5698 int32_t lsm6dsox_tap_detection_on_x_get(const stmdev_ctx_t *ctx,
5699 uint8_t *val)
5700 {
5701 lsm6dsox_tap_cfg0_t reg;
5702 int32_t ret;
5703
5704 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *)®, 1);
5705 *val = reg.tap_x_en;
5706
5707 return ret;
5708 }
5709
5710 /**
5711 * @brief X-axis tap recognition threshold.[set]
5712 *
5713 * @param ctx read / write interface definitions
5714 * @param val change the values of tap_ths_x in reg TAP_CFG1
5715 * @retval interface status (MANDATORY: return 0 -> no Error)
5716 *
5717 */
lsm6dsox_tap_threshold_x_set(const stmdev_ctx_t * ctx,uint8_t val)5718 int32_t lsm6dsox_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val)
5719 {
5720 lsm6dsox_tap_cfg1_t reg;
5721 int32_t ret;
5722
5723 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t *)®, 1);
5724
5725 if (ret == 0)
5726 {
5727 reg.tap_ths_x = val;
5728 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t *)®, 1);
5729 }
5730
5731 return ret;
5732 }
5733
5734 /**
5735 * @brief X-axis tap recognition threshold.[get]
5736 *
5737 * @param ctx read / write interface definitions
5738 * @param val change the values of tap_ths_x in reg TAP_CFG1
5739 * @retval interface status (MANDATORY: return 0 -> no Error)
5740 *
5741 */
lsm6dsox_tap_threshold_x_get(const stmdev_ctx_t * ctx,uint8_t * val)5742 int32_t lsm6dsox_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val)
5743 {
5744 lsm6dsox_tap_cfg1_t reg;
5745 int32_t ret;
5746
5747 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t *)®, 1);
5748 *val = reg.tap_ths_x;
5749
5750 return ret;
5751 }
5752
5753 /**
5754 * @brief Selection of axis priority for TAP detection.[set]
5755 *
5756 * @param ctx read / write interface definitions
5757 * @param val change the values of tap_priority in
5758 * reg TAP_CFG1
5759 * @retval interface status (MANDATORY: return 0 -> no Error)
5760 *
5761 */
lsm6dsox_tap_axis_priority_set(const stmdev_ctx_t * ctx,lsm6dsox_tap_priority_t val)5762 int32_t lsm6dsox_tap_axis_priority_set(const stmdev_ctx_t *ctx,
5763 lsm6dsox_tap_priority_t val)
5764 {
5765 lsm6dsox_tap_cfg1_t reg;
5766 int32_t ret;
5767
5768 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t *)®, 1);
5769
5770 if (ret == 0)
5771 {
5772 reg.tap_priority = (uint8_t)val;
5773 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t *)®, 1);
5774 }
5775
5776 return ret;
5777 }
5778
5779 /**
5780 * @brief Selection of axis priority for TAP detection.[get]
5781 *
5782 * @param ctx read / write interface definitions
5783 * @param val Get the values of tap_priority in
5784 * reg TAP_CFG1
5785 * @retval interface status (MANDATORY: return 0 -> no Error)
5786 *
5787 */
lsm6dsox_tap_axis_priority_get(const stmdev_ctx_t * ctx,lsm6dsox_tap_priority_t * val)5788 int32_t lsm6dsox_tap_axis_priority_get(const stmdev_ctx_t *ctx,
5789 lsm6dsox_tap_priority_t *val)
5790 {
5791 lsm6dsox_tap_cfg1_t reg;
5792 int32_t ret;
5793
5794 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG1, (uint8_t *)®, 1);
5795
5796 switch (reg.tap_priority)
5797 {
5798 case LSM6DSOX_XYZ:
5799 *val = LSM6DSOX_XYZ;
5800 break;
5801
5802 case LSM6DSOX_YXZ:
5803 *val = LSM6DSOX_YXZ;
5804 break;
5805
5806 case LSM6DSOX_XZY:
5807 *val = LSM6DSOX_XZY;
5808 break;
5809
5810 case LSM6DSOX_ZYX:
5811 *val = LSM6DSOX_ZYX;
5812 break;
5813
5814 case LSM6DSOX_YZX:
5815 *val = LSM6DSOX_YZX;
5816 break;
5817
5818 case LSM6DSOX_ZXY:
5819 *val = LSM6DSOX_ZXY;
5820 break;
5821
5822 default:
5823 *val = LSM6DSOX_XYZ;
5824 break;
5825 }
5826
5827 return ret;
5828 }
5829
5830 /**
5831 * @brief Y-axis tap recognition threshold.[set]
5832 *
5833 * @param ctx read / write interface definitions
5834 * @param val change the values of tap_ths_y in reg TAP_CFG2
5835 * @retval interface status (MANDATORY: return 0 -> no Error)
5836 *
5837 */
lsm6dsox_tap_threshold_y_set(const stmdev_ctx_t * ctx,uint8_t val)5838 int32_t lsm6dsox_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val)
5839 {
5840 lsm6dsox_tap_cfg2_t reg;
5841 int32_t ret;
5842
5843 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t *)®, 1);
5844
5845 if (ret == 0)
5846 {
5847 reg.tap_ths_y = val;
5848 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t *)®, 1);
5849 }
5850
5851 return ret;
5852 }
5853
5854 /**
5855 * @brief Y-axis tap recognition threshold.[get]
5856 *
5857 * @param ctx read / write interface definitions
5858 * @param val change the values of tap_ths_y in reg TAP_CFG2
5859 * @retval interface status (MANDATORY: return 0 -> no Error)
5860 *
5861 */
lsm6dsox_tap_threshold_y_get(const stmdev_ctx_t * ctx,uint8_t * val)5862 int32_t lsm6dsox_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val)
5863 {
5864 lsm6dsox_tap_cfg2_t reg;
5865 int32_t ret;
5866
5867 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t *)®, 1);
5868 *val = reg.tap_ths_y;
5869
5870 return ret;
5871 }
5872
5873 /**
5874 * @brief Z-axis recognition threshold.[set]
5875 *
5876 * @param ctx read / write interface definitions
5877 * @param val change the values of tap_ths_z in reg TAP_THS_6D
5878 * @retval interface status (MANDATORY: return 0 -> no Error)
5879 *
5880 */
lsm6dsox_tap_threshold_z_set(const stmdev_ctx_t * ctx,uint8_t val)5881 int32_t lsm6dsox_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val)
5882 {
5883 lsm6dsox_tap_ths_6d_t reg;
5884 int32_t ret;
5885
5886 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1);
5887
5888 if (ret == 0)
5889 {
5890 reg.tap_ths_z = val;
5891 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1);
5892 }
5893
5894 return ret;
5895 }
5896
5897 /**
5898 * @brief Z-axis recognition threshold.[get]
5899 *
5900 * @param ctx read / write interface definitions
5901 * @param val change the values of tap_ths_z in reg TAP_THS_6D
5902 * @retval interface status (MANDATORY: return 0 -> no Error)
5903 *
5904 */
lsm6dsox_tap_threshold_z_get(const stmdev_ctx_t * ctx,uint8_t * val)5905 int32_t lsm6dsox_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val)
5906 {
5907 lsm6dsox_tap_ths_6d_t reg;
5908 int32_t ret;
5909
5910 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1);
5911 *val = reg.tap_ths_z;
5912
5913 return ret;
5914 }
5915
5916 /**
5917 * @brief Maximum duration is the maximum time of an
5918 * over threshold signal detection to be recognized
5919 * as a tap event. The default value of these bits
5920 * is 00b which corresponds to 4*ODR_XL time.
5921 * If the SHOCK[1:0] bits are set to a different
5922 * value, 1LSB corresponds to 8*ODR_XL time.[set]
5923 *
5924 * @param ctx read / write interface definitions
5925 * @param val change the values of shock in reg INT_DUR2
5926 * @retval interface status (MANDATORY: return 0 -> no Error)
5927 *
5928 */
lsm6dsox_tap_shock_set(const stmdev_ctx_t * ctx,uint8_t val)5929 int32_t lsm6dsox_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val)
5930 {
5931 lsm6dsox_int_dur2_t reg;
5932 int32_t ret;
5933
5934 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1);
5935
5936 if (ret == 0)
5937 {
5938 reg.shock = val;
5939 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1);
5940 }
5941
5942 return ret;
5943 }
5944
5945 /**
5946 * @brief Maximum duration is the maximum time of an
5947 * over threshold signal detection to be recognized
5948 * as a tap event. The default value of these bits
5949 * is 00b which corresponds to 4*ODR_XL time.
5950 * If the SHOCK[1:0] bits are set to a different
5951 * value, 1LSB corresponds to 8*ODR_XL time.[get]
5952 *
5953 * @param ctx read / write interface definitions
5954 * @param val change the values of shock in reg INT_DUR2
5955 * @retval interface status (MANDATORY: return 0 -> no Error)
5956 *
5957 */
lsm6dsox_tap_shock_get(const stmdev_ctx_t * ctx,uint8_t * val)5958 int32_t lsm6dsox_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val)
5959 {
5960 lsm6dsox_int_dur2_t reg;
5961 int32_t ret;
5962
5963 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1);
5964 *val = reg.shock;
5965
5966 return ret;
5967 }
5968
5969 /**
5970 * @brief Quiet time is the time after the first detected
5971 * tap in which there must not be any over threshold
5972 * event.
5973 * The default value of these bits is 00b which
5974 * corresponds to 2*ODR_XL time. If the QUIET[1:0]
5975 * bits are set to a different value,
5976 * 1LSB corresponds to 4*ODR_XL time.[set]
5977 *
5978 * @param ctx read / write interface definitions
5979 * @param val change the values of quiet in reg INT_DUR2
5980 * @retval interface status (MANDATORY: return 0 -> no Error)
5981 *
5982 */
lsm6dsox_tap_quiet_set(const stmdev_ctx_t * ctx,uint8_t val)5983 int32_t lsm6dsox_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val)
5984 {
5985 lsm6dsox_int_dur2_t reg;
5986 int32_t ret;
5987
5988 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1);
5989
5990 if (ret == 0)
5991 {
5992 reg.quiet = val;
5993 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1);
5994 }
5995
5996 return ret;
5997 }
5998
5999 /**
6000 * @brief Quiet time is the time after the first detected
6001 * tap in which there must not be any over threshold
6002 * event.
6003 * The default value of these bits is 00b which
6004 * corresponds to 2*ODR_XL time.
6005 * If the QUIET[1:0] bits are set to a different
6006 * value, 1LSB corresponds to 4*ODR_XL time.[get]
6007 *
6008 * @param ctx read / write interface definitions
6009 * @param val change the values of quiet in reg INT_DUR2
6010 * @retval interface status (MANDATORY: return 0 -> no Error)
6011 *
6012 */
lsm6dsox_tap_quiet_get(const stmdev_ctx_t * ctx,uint8_t * val)6013 int32_t lsm6dsox_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val)
6014 {
6015 lsm6dsox_int_dur2_t reg;
6016 int32_t ret;
6017
6018 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1);
6019 *val = reg.quiet;
6020
6021 return ret;
6022 }
6023
6024 /**
6025 * @brief When double tap recognition is enabled,
6026 * this register expresses the maximum time
6027 * between two consecutive detected taps to
6028 * determine a double tap event.
6029 * The default value of these bits is 0000b which
6030 * corresponds to 16*ODR_XL time.
6031 * If the DUR[3:0] bits are set to a different value,
6032 * 1LSB corresponds to 32*ODR_XL time.[set]
6033 *
6034 * @param ctx read / write interface definitions
6035 * @param val change the values of dur in reg INT_DUR2
6036 * @retval interface status (MANDATORY: return 0 -> no Error)
6037 *
6038 */
lsm6dsox_tap_dur_set(const stmdev_ctx_t * ctx,uint8_t val)6039 int32_t lsm6dsox_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
6040 {
6041 lsm6dsox_int_dur2_t reg;
6042 int32_t ret;
6043
6044 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1);
6045
6046 if (ret == 0)
6047 {
6048 reg.dur = val;
6049 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1);
6050 }
6051
6052 return ret;
6053 }
6054
6055 /**
6056 * @brief When double tap recognition is enabled,
6057 * this register expresses the maximum time
6058 * between two consecutive detected taps to
6059 * determine a double tap event.
6060 * The default value of these bits is 0000b which
6061 * corresponds to 16*ODR_XL time. If the DUR[3:0]
6062 * bits are set to a different value,
6063 * 1LSB corresponds to 32*ODR_XL time.[get]
6064 *
6065 * @param ctx read / write interface definitions
6066 * @param val change the values of dur in reg INT_DUR2
6067 * @retval interface status (MANDATORY: return 0 -> no Error)
6068 *
6069 */
lsm6dsox_tap_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)6070 int32_t lsm6dsox_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
6071 {
6072 lsm6dsox_int_dur2_t reg;
6073 int32_t ret;
6074
6075 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT_DUR2, (uint8_t *)®, 1);
6076 *val = reg.dur;
6077
6078 return ret;
6079 }
6080
6081 /**
6082 * @brief Single/double-tap event enable.[set]
6083 *
6084 * @param ctx read / write interface definitions
6085 * @param val change the values of single_double_tap in reg WAKE_UP_THS
6086 * @retval interface status (MANDATORY: return 0 -> no Error)
6087 *
6088 */
lsm6dsox_tap_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_single_double_tap_t val)6089 int32_t lsm6dsox_tap_mode_set(const stmdev_ctx_t *ctx,
6090 lsm6dsox_single_double_tap_t val)
6091 {
6092 lsm6dsox_wake_up_ths_t reg;
6093 int32_t ret;
6094
6095 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1);
6096
6097 if (ret == 0)
6098 {
6099 reg.single_double_tap = (uint8_t)val;
6100 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1);
6101 }
6102
6103 return ret;
6104 }
6105
6106 /**
6107 * @brief Single/double-tap event enable.[get]
6108 *
6109 * @param ctx read / write interface definitions
6110 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
6111 * @retval interface status (MANDATORY: return 0 -> no Error)
6112 *
6113 */
lsm6dsox_tap_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_single_double_tap_t * val)6114 int32_t lsm6dsox_tap_mode_get(const stmdev_ctx_t *ctx,
6115 lsm6dsox_single_double_tap_t *val)
6116 {
6117 lsm6dsox_wake_up_ths_t reg;
6118 int32_t ret;
6119
6120 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_THS, (uint8_t *)®, 1);
6121
6122 switch (reg.single_double_tap)
6123 {
6124 case LSM6DSOX_ONLY_SINGLE:
6125 *val = LSM6DSOX_ONLY_SINGLE;
6126 break;
6127
6128 case LSM6DSOX_BOTH_SINGLE_DOUBLE:
6129 *val = LSM6DSOX_BOTH_SINGLE_DOUBLE;
6130 break;
6131
6132 default:
6133 *val = LSM6DSOX_ONLY_SINGLE;
6134 break;
6135 }
6136
6137 return ret;
6138 }
6139
6140 /**
6141 * @}
6142 *
6143 */
6144
6145 /**
6146 * @defgroup LSM6DSOX_ Six_position_detection(6D/4D)
6147 * @brief This section groups all the functions concerning six position
6148 * detection (6D).
6149 * @{
6150 *
6151 */
6152
6153 /**
6154 * @brief Threshold for 4D/6D function.[set]
6155 *
6156 * @param ctx read / write interface definitions
6157 * @param val change the values of sixd_ths in reg TAP_THS_6D
6158 * @retval interface status (MANDATORY: return 0 -> no Error)
6159 *
6160 */
lsm6dsox_6d_threshold_set(const stmdev_ctx_t * ctx,lsm6dsox_sixd_ths_t val)6161 int32_t lsm6dsox_6d_threshold_set(const stmdev_ctx_t *ctx,
6162 lsm6dsox_sixd_ths_t val)
6163 {
6164 lsm6dsox_tap_ths_6d_t reg;
6165 int32_t ret;
6166
6167 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1);
6168
6169 if (ret == 0)
6170 {
6171 reg.sixd_ths = (uint8_t)val;
6172 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1);
6173 }
6174
6175 return ret;
6176 }
6177
6178 /**
6179 * @brief Threshold for 4D/6D function.[get]
6180 *
6181 * @param ctx read / write interface definitions
6182 * @param val Get the values of sixd_ths in reg TAP_THS_6D
6183 * @retval interface status (MANDATORY: return 0 -> no Error)
6184 *
6185 */
lsm6dsox_6d_threshold_get(const stmdev_ctx_t * ctx,lsm6dsox_sixd_ths_t * val)6186 int32_t lsm6dsox_6d_threshold_get(const stmdev_ctx_t *ctx,
6187 lsm6dsox_sixd_ths_t *val)
6188 {
6189 lsm6dsox_tap_ths_6d_t reg;
6190 int32_t ret;
6191
6192 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1);
6193
6194 switch (reg.sixd_ths)
6195 {
6196 case LSM6DSOX_DEG_80:
6197 *val = LSM6DSOX_DEG_80;
6198 break;
6199
6200 case LSM6DSOX_DEG_70:
6201 *val = LSM6DSOX_DEG_70;
6202 break;
6203
6204 case LSM6DSOX_DEG_60:
6205 *val = LSM6DSOX_DEG_60;
6206 break;
6207
6208 case LSM6DSOX_DEG_50:
6209 *val = LSM6DSOX_DEG_50;
6210 break;
6211
6212 default:
6213 *val = LSM6DSOX_DEG_80;
6214 break;
6215 }
6216
6217 return ret;
6218 }
6219
6220 /**
6221 * @brief 4D orientation detection enable.[set]
6222 *
6223 * @param ctx read / write interface definitions
6224 * @param val change the values of d4d_en in reg TAP_THS_6D
6225 * @retval interface status (MANDATORY: return 0 -> no Error)
6226 *
6227 */
lsm6dsox_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)6228 int32_t lsm6dsox_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
6229 {
6230 lsm6dsox_tap_ths_6d_t reg;
6231 int32_t ret;
6232
6233 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1);
6234
6235 if (ret == 0)
6236 {
6237 reg.d4d_en = val;
6238 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1);
6239 }
6240
6241 return ret;
6242 }
6243
6244 /**
6245 * @brief 4D orientation detection enable.[get]
6246 *
6247 * @param ctx read / write interface definitions
6248 * @param val change the values of d4d_en in reg TAP_THS_6D
6249 * @retval interface status (MANDATORY: return 0 -> no Error)
6250 *
6251 */
lsm6dsox_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)6252 int32_t lsm6dsox_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
6253 {
6254 lsm6dsox_tap_ths_6d_t reg;
6255 int32_t ret;
6256
6257 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_THS_6D, (uint8_t *)®, 1);
6258 *val = reg.d4d_en;
6259
6260 return ret;
6261 }
6262
6263 /**
6264 * @}
6265 *
6266 */
6267
6268 /**
6269 * @defgroup LSM6DSOX_free_fall
6270 * @brief This section group all the functions concerning the free
6271 * fall detection.
6272 * @{
6273 *
6274 */
6275 /**
6276 * @brief Free fall threshold setting.[set]
6277 *
6278 * @param ctx read / write interface definitions
6279 * @param val change the values of ff_ths in reg FREE_FALL
6280 * @retval interface status (MANDATORY: return 0 -> no Error)
6281 *
6282 */
lsm6dsox_ff_threshold_set(const stmdev_ctx_t * ctx,lsm6dsox_ff_ths_t val)6283 int32_t lsm6dsox_ff_threshold_set(const stmdev_ctx_t *ctx,
6284 lsm6dsox_ff_ths_t val)
6285 {
6286 lsm6dsox_free_fall_t reg;
6287 int32_t ret;
6288
6289 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t *)®, 1);
6290
6291 if (ret == 0)
6292 {
6293 reg.ff_ths = (uint8_t)val;
6294 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t *)®, 1);
6295 }
6296
6297 return ret;
6298 }
6299
6300 /**
6301 * @brief Free fall threshold setting.[get]
6302 *
6303 * @param ctx read / write interface definitions
6304 * @param val Get the values of ff_ths in reg FREE_FALL
6305 * @retval interface status (MANDATORY: return 0 -> no Error)
6306 *
6307 */
lsm6dsox_ff_threshold_get(const stmdev_ctx_t * ctx,lsm6dsox_ff_ths_t * val)6308 int32_t lsm6dsox_ff_threshold_get(const stmdev_ctx_t *ctx,
6309 lsm6dsox_ff_ths_t *val)
6310 {
6311 lsm6dsox_free_fall_t reg;
6312 int32_t ret;
6313
6314 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL, (uint8_t *)®, 1);
6315
6316 switch (reg.ff_ths)
6317 {
6318 case LSM6DSOX_FF_TSH_156mg:
6319 *val = LSM6DSOX_FF_TSH_156mg;
6320 break;
6321
6322 case LSM6DSOX_FF_TSH_219mg:
6323 *val = LSM6DSOX_FF_TSH_219mg;
6324 break;
6325
6326 case LSM6DSOX_FF_TSH_250mg:
6327 *val = LSM6DSOX_FF_TSH_250mg;
6328 break;
6329
6330 case LSM6DSOX_FF_TSH_312mg:
6331 *val = LSM6DSOX_FF_TSH_312mg;
6332 break;
6333
6334 case LSM6DSOX_FF_TSH_344mg:
6335 *val = LSM6DSOX_FF_TSH_344mg;
6336 break;
6337
6338 case LSM6DSOX_FF_TSH_406mg:
6339 *val = LSM6DSOX_FF_TSH_406mg;
6340 break;
6341
6342 case LSM6DSOX_FF_TSH_469mg:
6343 *val = LSM6DSOX_FF_TSH_469mg;
6344 break;
6345
6346 case LSM6DSOX_FF_TSH_500mg:
6347 *val = LSM6DSOX_FF_TSH_500mg;
6348 break;
6349
6350 default:
6351 *val = LSM6DSOX_FF_TSH_156mg;
6352 break;
6353 }
6354
6355 return ret;
6356 }
6357
6358 /**
6359 * @brief Free-fall duration event.[set]
6360 * 1LSb = 1 / ODR
6361 *
6362 * @param ctx read / write interface definitions
6363 * @param val change the values of ff_dur in reg FREE_FALL
6364 * @retval interface status (MANDATORY: return 0 -> no Error)
6365 *
6366 */
lsm6dsox_ff_dur_set(const stmdev_ctx_t * ctx,uint8_t val)6367 int32_t lsm6dsox_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
6368 {
6369 lsm6dsox_wake_up_dur_t wake_up_dur;
6370 lsm6dsox_free_fall_t free_fall;
6371 int32_t ret;
6372
6373 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR,
6374 (uint8_t *)&wake_up_dur, 1);
6375
6376 if (ret == 0)
6377 {
6378 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL,
6379 (uint8_t *)&free_fall, 1);
6380 }
6381
6382 if (ret == 0)
6383 {
6384 wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
6385 free_fall.ff_dur = (uint8_t)val & 0x1FU;
6386 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_WAKE_UP_DUR,
6387 (uint8_t *)&wake_up_dur, 1);
6388 }
6389
6390 if (ret == 0)
6391 {
6392 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FREE_FALL,
6393 (uint8_t *)&free_fall, 1);
6394 }
6395
6396 return ret;
6397 }
6398
6399 /**
6400 * @brief Free-fall duration event.[get]
6401 * 1LSb = 1 / ODR
6402 *
6403 * @param ctx read / write interface definitions
6404 * @param val change the values of ff_dur in reg FREE_FALL
6405 * @retval interface status (MANDATORY: return 0 -> no Error)
6406 *
6407 */
lsm6dsox_ff_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)6408 int32_t lsm6dsox_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
6409 {
6410 lsm6dsox_wake_up_dur_t wake_up_dur;
6411 lsm6dsox_free_fall_t free_fall;
6412 int32_t ret;
6413
6414 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WAKE_UP_DUR,
6415 (uint8_t *)&wake_up_dur, 1);
6416
6417 if (ret == 0)
6418 {
6419 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FREE_FALL,
6420 (uint8_t *)&free_fall, 1);
6421 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
6422 }
6423
6424 return ret;
6425 }
6426
6427 /**
6428 * @}
6429 *
6430 */
6431
6432 /**
6433 * @defgroup LSM6DSOX_fifo
6434 * @brief This section group all the functions concerning the fifo usage
6435 * @{
6436 *
6437 */
6438
6439 /**
6440 * @brief FIFO watermark level selection.[set]
6441 *
6442 * @param ctx read / write interface definitions
6443 * @param val change the values of wtm in reg FIFO_CTRL1
6444 * @retval interface status (MANDATORY: return 0 -> no Error)
6445 *
6446 */
lsm6dsox_fifo_watermark_set(const stmdev_ctx_t * ctx,uint16_t val)6447 int32_t lsm6dsox_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val)
6448 {
6449 lsm6dsox_fifo_ctrl1_t fifo_ctrl1;
6450 lsm6dsox_fifo_ctrl2_t fifo_ctrl2;
6451 int32_t ret;
6452
6453 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2,
6454 (uint8_t *)&fifo_ctrl2, 1);
6455
6456 if (ret == 0)
6457 {
6458 fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val;
6459 fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8);
6460 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL1,
6461 (uint8_t *)&fifo_ctrl1, 1);
6462 }
6463
6464 if (ret == 0)
6465 {
6466 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2,
6467 (uint8_t *)&fifo_ctrl2, 1);
6468 }
6469
6470 return ret;
6471 }
6472
6473 /**
6474 * @brief FIFO watermark level selection.[get]
6475 *
6476 * @param ctx read / write interface definitions
6477 * @param val change the values of wtm in reg FIFO_CTRL1
6478 * @retval interface status (MANDATORY: return 0 -> no Error)
6479 *
6480 */
lsm6dsox_fifo_watermark_get(const stmdev_ctx_t * ctx,uint16_t * val)6481 int32_t lsm6dsox_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val)
6482 {
6483 lsm6dsox_fifo_ctrl1_t fifo_ctrl1;
6484 lsm6dsox_fifo_ctrl2_t fifo_ctrl2;
6485 int32_t ret;
6486
6487 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL1,
6488 (uint8_t *)&fifo_ctrl1, 1);
6489
6490 if (ret == 0)
6491 {
6492 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2,
6493 (uint8_t *)&fifo_ctrl2, 1);
6494 *val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm;
6495 }
6496
6497 return ret;
6498 }
6499
6500 /**
6501 * @brief FIFO compression feature initialization request [set].
6502 *
6503 * @param ctx read / write interface definitions
6504 * @param val change the values of FIFO_COMPR_INIT in
6505 * reg EMB_FUNC_INIT_B
6506 * @retval interface status (MANDATORY: return 0 -> no Error)
6507 *
6508 */
lsm6dsox_compression_algo_init_set(const stmdev_ctx_t * ctx,uint8_t val)6509 int32_t lsm6dsox_compression_algo_init_set(const stmdev_ctx_t *ctx,
6510 uint8_t val)
6511 {
6512 lsm6dsox_emb_func_init_b_t reg;
6513 int32_t ret;
6514
6515 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
6516
6517 if (ret == 0)
6518 {
6519 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
6520 (uint8_t *)®, 1);
6521 }
6522
6523 if (ret == 0)
6524 {
6525 reg.fifo_compr_init = val;
6526 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
6527 (uint8_t *)®, 1);
6528 }
6529
6530 if (ret == 0)
6531 {
6532 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
6533 }
6534
6535 return ret;
6536 }
6537
6538 /**
6539 * @brief FIFO compression feature initialization request [get].
6540 *
6541 * @param ctx read / write interface definitions
6542 * @param val change the values of FIFO_COMPR_INIT in
6543 * reg EMB_FUNC_INIT_B
6544 * @retval interface status (MANDATORY: return 0 -> no Error)
6545 *
6546 */
lsm6dsox_compression_algo_init_get(const stmdev_ctx_t * ctx,uint8_t * val)6547 int32_t lsm6dsox_compression_algo_init_get(const stmdev_ctx_t *ctx,
6548 uint8_t *val)
6549 {
6550 lsm6dsox_emb_func_init_b_t reg;
6551 int32_t ret;
6552
6553 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
6554
6555 if (ret == 0)
6556 {
6557 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
6558 (uint8_t *)®, 1);
6559 }
6560
6561 if (ret == 0)
6562 {
6563 *val = reg.fifo_compr_init;
6564 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
6565 }
6566
6567 return ret;
6568 }
6569
6570 /**
6571 * @brief Enable and configure compression algo.[set]
6572 *
6573 * @param ctx read / write interface definitions
6574 * @param val change the values of uncoptr_rate in
6575 * reg FIFO_CTRL2
6576 * @retval interface status (MANDATORY: return 0 -> no Error)
6577 *
6578 */
lsm6dsox_compression_algo_set(const stmdev_ctx_t * ctx,lsm6dsox_uncoptr_rate_t val)6579 int32_t lsm6dsox_compression_algo_set(const stmdev_ctx_t *ctx,
6580 lsm6dsox_uncoptr_rate_t val)
6581 {
6582 lsm6dsox_fifo_ctrl2_t fifo_ctrl2;
6583 int32_t ret;
6584
6585 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2,
6586 (uint8_t *)&fifo_ctrl2, 1);
6587
6588 if (ret == 0)
6589 {
6590 fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
6591 fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
6592 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2,
6593 (uint8_t *)&fifo_ctrl2, 1);
6594 }
6595
6596 return ret;
6597 }
6598
6599 /**
6600 * @brief Enable and configure compression algo.[get]
6601 *
6602 * @param ctx read / write interface definitions
6603 * @param val Get the values of uncoptr_rate in
6604 * reg FIFO_CTRL2
6605 * @retval interface status (MANDATORY: return 0 -> no Error)
6606 *
6607 */
lsm6dsox_compression_algo_get(const stmdev_ctx_t * ctx,lsm6dsox_uncoptr_rate_t * val)6608 int32_t lsm6dsox_compression_algo_get(const stmdev_ctx_t *ctx,
6609 lsm6dsox_uncoptr_rate_t *val)
6610 {
6611 lsm6dsox_fifo_ctrl2_t reg;
6612 int32_t ret;
6613
6614 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
6615
6616 switch ((reg.fifo_compr_rt_en << 2) | reg.uncoptr_rate)
6617 {
6618 case LSM6DSOX_CMP_DISABLE:
6619 *val = LSM6DSOX_CMP_DISABLE;
6620 break;
6621
6622 case LSM6DSOX_CMP_ALWAYS:
6623 *val = LSM6DSOX_CMP_ALWAYS;
6624 break;
6625
6626 case LSM6DSOX_CMP_8_TO_1:
6627 *val = LSM6DSOX_CMP_8_TO_1;
6628 break;
6629
6630 case LSM6DSOX_CMP_16_TO_1:
6631 *val = LSM6DSOX_CMP_16_TO_1;
6632 break;
6633
6634 case LSM6DSOX_CMP_32_TO_1:
6635 *val = LSM6DSOX_CMP_32_TO_1;
6636 break;
6637
6638 default:
6639 *val = LSM6DSOX_CMP_DISABLE;
6640 break;
6641 }
6642
6643 return ret;
6644 }
6645
6646 /**
6647 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
6648 *
6649 * @param ctx read / write interface definitions
6650 * @param val change the values of odrchg_en in reg FIFO_CTRL2
6651 * @retval interface status (MANDATORY: return 0 -> no Error)
6652 *
6653 */
lsm6dsox_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t * ctx,uint8_t val)6654 int32_t lsm6dsox_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx,
6655 uint8_t val)
6656 {
6657 lsm6dsox_fifo_ctrl2_t reg;
6658 int32_t ret;
6659
6660 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
6661
6662 if (ret == 0)
6663 {
6664 reg.odrchg_en = val;
6665 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
6666 }
6667
6668 return ret;
6669 }
6670
6671 /**
6672 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
6673 *
6674 * @param ctx read / write interface definitions
6675 * @param val change the values of odrchg_en in reg FIFO_CTRL2
6676 * @retval interface status (MANDATORY: return 0 -> no Error)
6677 *
6678 */
lsm6dsox_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t * ctx,uint8_t * val)6679 int32_t lsm6dsox_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx,
6680 uint8_t *val)
6681 {
6682 lsm6dsox_fifo_ctrl2_t reg;
6683 int32_t ret;
6684
6685 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
6686 *val = reg.odrchg_en;
6687
6688 return ret;
6689 }
6690
6691 /**
6692 * @brief Enables/Disables compression algorithm runtime.[set]
6693 *
6694 * @param ctx read / write interface definitions
6695 * @param val change the values of fifo_compr_rt_en in
6696 * reg FIFO_CTRL2
6697 * @retval interface status (MANDATORY: return 0 -> no Error)
6698 *
6699 */
lsm6dsox_compression_algo_real_time_set(const stmdev_ctx_t * ctx,uint8_t val)6700 int32_t lsm6dsox_compression_algo_real_time_set(const stmdev_ctx_t *ctx,
6701 uint8_t val)
6702 {
6703 lsm6dsox_fifo_ctrl2_t reg;
6704 int32_t ret;
6705
6706 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
6707
6708 if (ret == 0)
6709 {
6710 reg.fifo_compr_rt_en = val;
6711 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
6712 }
6713
6714 return ret;
6715 }
6716
6717 /**
6718 * @brief Enables/Disables compression algorithm runtime. [get]
6719 *
6720 * @param ctx read / write interface definitions
6721 * @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2
6722 * @retval interface status (MANDATORY: return 0 -> no Error)
6723 *
6724 */
lsm6dsox_compression_algo_real_time_get(const stmdev_ctx_t * ctx,uint8_t * val)6725 int32_t lsm6dsox_compression_algo_real_time_get(const stmdev_ctx_t *ctx,
6726 uint8_t *val)
6727 {
6728 lsm6dsox_fifo_ctrl2_t reg;
6729 int32_t ret;
6730
6731 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
6732 *val = reg.fifo_compr_rt_en;
6733
6734 return ret;
6735 }
6736
6737 /**
6738 * @brief Sensing chain FIFO stop values memorization at
6739 * threshold level.[set]
6740 *
6741 * @param ctx read / write interface definitions
6742 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2
6743 * @retval interface status (MANDATORY: return 0 -> no Error)
6744 *
6745 */
lsm6dsox_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)6746 int32_t lsm6dsox_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
6747 {
6748 lsm6dsox_fifo_ctrl2_t reg;
6749 int32_t ret;
6750
6751 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
6752
6753 if (ret == 0)
6754 {
6755 reg.stop_on_wtm = val;
6756 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
6757 }
6758
6759 return ret;
6760 }
6761
6762 /**
6763 * @brief Sensing chain FIFO stop values memorization at
6764 * threshold level.[get]
6765 *
6766 * @param ctx read / write interface definitions
6767 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2
6768 * @retval interface status (MANDATORY: return 0 -> no Error)
6769 *
6770 */
lsm6dsox_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)6771 int32_t lsm6dsox_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val)
6772 {
6773 lsm6dsox_fifo_ctrl2_t reg;
6774 int32_t ret;
6775
6776 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL2, (uint8_t *)®, 1);
6777 *val = reg.stop_on_wtm;
6778
6779 return ret;
6780 }
6781
6782 /**
6783 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6784 * for accelerometer data.[set]
6785 *
6786 * @param ctx read / write interface definitions
6787 * @param val change the values of bdr_xl in reg FIFO_CTRL3
6788 * @retval interface status (MANDATORY: return 0 -> no Error)
6789 *
6790 */
lsm6dsox_fifo_xl_batch_set(const stmdev_ctx_t * ctx,lsm6dsox_bdr_xl_t val)6791 int32_t lsm6dsox_fifo_xl_batch_set(const stmdev_ctx_t *ctx,
6792 lsm6dsox_bdr_xl_t val)
6793 {
6794 lsm6dsox_fifo_ctrl3_t reg;
6795 int32_t ret;
6796
6797 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t *)®, 1);
6798
6799 if (ret == 0)
6800 {
6801 reg.bdr_xl = (uint8_t)val;
6802 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t *)®, 1);
6803 }
6804
6805 return ret;
6806 }
6807
6808 /**
6809 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6810 * for accelerometer data.[get]
6811 *
6812 * @param ctx read / write interface definitions
6813 * @param val Get the values of bdr_xl in reg FIFO_CTRL3
6814 * @retval interface status (MANDATORY: return 0 -> no Error)
6815 *
6816 */
lsm6dsox_fifo_xl_batch_get(const stmdev_ctx_t * ctx,lsm6dsox_bdr_xl_t * val)6817 int32_t lsm6dsox_fifo_xl_batch_get(const stmdev_ctx_t *ctx,
6818 lsm6dsox_bdr_xl_t *val)
6819 {
6820 lsm6dsox_fifo_ctrl3_t reg;
6821 int32_t ret;
6822
6823 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t *)®, 1);
6824
6825 switch (reg.bdr_xl)
6826 {
6827 case LSM6DSOX_XL_NOT_BATCHED:
6828 *val = LSM6DSOX_XL_NOT_BATCHED;
6829 break;
6830
6831 case LSM6DSOX_XL_BATCHED_AT_12Hz5:
6832 *val = LSM6DSOX_XL_BATCHED_AT_12Hz5;
6833 break;
6834
6835 case LSM6DSOX_XL_BATCHED_AT_26Hz:
6836 *val = LSM6DSOX_XL_BATCHED_AT_26Hz;
6837 break;
6838
6839 case LSM6DSOX_XL_BATCHED_AT_52Hz:
6840 *val = LSM6DSOX_XL_BATCHED_AT_52Hz;
6841 break;
6842
6843 case LSM6DSOX_XL_BATCHED_AT_104Hz:
6844 *val = LSM6DSOX_XL_BATCHED_AT_104Hz;
6845 break;
6846
6847 case LSM6DSOX_XL_BATCHED_AT_208Hz:
6848 *val = LSM6DSOX_XL_BATCHED_AT_208Hz;
6849 break;
6850
6851 case LSM6DSOX_XL_BATCHED_AT_417Hz:
6852 *val = LSM6DSOX_XL_BATCHED_AT_417Hz;
6853 break;
6854
6855 case LSM6DSOX_XL_BATCHED_AT_833Hz:
6856 *val = LSM6DSOX_XL_BATCHED_AT_833Hz;
6857 break;
6858
6859 case LSM6DSOX_XL_BATCHED_AT_1667Hz:
6860 *val = LSM6DSOX_XL_BATCHED_AT_1667Hz;
6861 break;
6862
6863 case LSM6DSOX_XL_BATCHED_AT_3333Hz:
6864 *val = LSM6DSOX_XL_BATCHED_AT_3333Hz;
6865 break;
6866
6867 case LSM6DSOX_XL_BATCHED_AT_6667Hz:
6868 *val = LSM6DSOX_XL_BATCHED_AT_6667Hz;
6869 break;
6870
6871 case LSM6DSOX_XL_BATCHED_AT_6Hz5:
6872 *val = LSM6DSOX_XL_BATCHED_AT_6Hz5;
6873 break;
6874
6875 default:
6876 *val = LSM6DSOX_XL_NOT_BATCHED;
6877 break;
6878 }
6879
6880 return ret;
6881 }
6882
6883 /**
6884 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6885 * for gyroscope data.[set]
6886 *
6887 * @param ctx read / write interface definitions
6888 * @param val change the values of bdr_gy in reg FIFO_CTRL3
6889 * @retval interface status (MANDATORY: return 0 -> no Error)
6890 *
6891 */
lsm6dsox_fifo_gy_batch_set(const stmdev_ctx_t * ctx,lsm6dsox_bdr_gy_t val)6892 int32_t lsm6dsox_fifo_gy_batch_set(const stmdev_ctx_t *ctx,
6893 lsm6dsox_bdr_gy_t val)
6894 {
6895 lsm6dsox_fifo_ctrl3_t reg;
6896 int32_t ret;
6897
6898 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t *)®, 1);
6899
6900 if (ret == 0)
6901 {
6902 reg.bdr_gy = (uint8_t)val;
6903 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t *)®, 1);
6904 }
6905
6906 return ret;
6907 }
6908
6909 /**
6910 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6911 * for gyroscope data.[get]
6912 *
6913 * @param ctx read / write interface definitions
6914 * @param val Get the values of bdr_gy in reg FIFO_CTRL3
6915 * @retval interface status (MANDATORY: return 0 -> no Error)
6916 *
6917 */
lsm6dsox_fifo_gy_batch_get(const stmdev_ctx_t * ctx,lsm6dsox_bdr_gy_t * val)6918 int32_t lsm6dsox_fifo_gy_batch_get(const stmdev_ctx_t *ctx,
6919 lsm6dsox_bdr_gy_t *val)
6920 {
6921 lsm6dsox_fifo_ctrl3_t reg;
6922 int32_t ret;
6923
6924 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL3, (uint8_t *)®, 1);
6925
6926 switch (reg.bdr_gy)
6927 {
6928 case LSM6DSOX_GY_NOT_BATCHED:
6929 *val = LSM6DSOX_GY_NOT_BATCHED;
6930 break;
6931
6932 case LSM6DSOX_GY_BATCHED_AT_12Hz5:
6933 *val = LSM6DSOX_GY_BATCHED_AT_12Hz5;
6934 break;
6935
6936 case LSM6DSOX_GY_BATCHED_AT_26Hz:
6937 *val = LSM6DSOX_GY_BATCHED_AT_26Hz;
6938 break;
6939
6940 case LSM6DSOX_GY_BATCHED_AT_52Hz:
6941 *val = LSM6DSOX_GY_BATCHED_AT_52Hz;
6942 break;
6943
6944 case LSM6DSOX_GY_BATCHED_AT_104Hz:
6945 *val = LSM6DSOX_GY_BATCHED_AT_104Hz;
6946 break;
6947
6948 case LSM6DSOX_GY_BATCHED_AT_208Hz:
6949 *val = LSM6DSOX_GY_BATCHED_AT_208Hz;
6950 break;
6951
6952 case LSM6DSOX_GY_BATCHED_AT_417Hz:
6953 *val = LSM6DSOX_GY_BATCHED_AT_417Hz;
6954 break;
6955
6956 case LSM6DSOX_GY_BATCHED_AT_833Hz:
6957 *val = LSM6DSOX_GY_BATCHED_AT_833Hz;
6958 break;
6959
6960 case LSM6DSOX_GY_BATCHED_AT_1667Hz:
6961 *val = LSM6DSOX_GY_BATCHED_AT_1667Hz;
6962 break;
6963
6964 case LSM6DSOX_GY_BATCHED_AT_3333Hz:
6965 *val = LSM6DSOX_GY_BATCHED_AT_3333Hz;
6966 break;
6967
6968 case LSM6DSOX_GY_BATCHED_AT_6667Hz:
6969 *val = LSM6DSOX_GY_BATCHED_AT_6667Hz;
6970 break;
6971
6972 case LSM6DSOX_GY_BATCHED_AT_6Hz5:
6973 *val = LSM6DSOX_GY_BATCHED_AT_6Hz5;
6974 break;
6975
6976 default:
6977 *val = LSM6DSOX_GY_NOT_BATCHED;
6978 break;
6979 }
6980
6981 return ret;
6982 }
6983
6984 /**
6985 * @brief FIFO mode selection.[set]
6986 *
6987 * @param ctx read / write interface definitions
6988 * @param val change the values of fifo_mode in reg FIFO_CTRL4
6989 * @retval interface status (MANDATORY: return 0 -> no Error)
6990 *
6991 */
lsm6dsox_fifo_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_fifo_mode_t val)6992 int32_t lsm6dsox_fifo_mode_set(const stmdev_ctx_t *ctx,
6993 lsm6dsox_fifo_mode_t val)
6994 {
6995 lsm6dsox_fifo_ctrl4_t reg;
6996 int32_t ret;
6997
6998 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1);
6999
7000 if (ret == 0)
7001 {
7002 reg.fifo_mode = (uint8_t)val;
7003 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1);
7004 }
7005
7006 return ret;
7007 }
7008
7009 /**
7010 * @brief FIFO mode selection.[get]
7011 *
7012 * @param ctx read / write interface definitions
7013 * @param val Get the values of fifo_mode in reg FIFO_CTRL4
7014 * @retval interface status (MANDATORY: return 0 -> no Error)
7015 *
7016 */
lsm6dsox_fifo_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_fifo_mode_t * val)7017 int32_t lsm6dsox_fifo_mode_get(const stmdev_ctx_t *ctx,
7018 lsm6dsox_fifo_mode_t *val)
7019 {
7020 lsm6dsox_fifo_ctrl4_t reg;
7021 int32_t ret;
7022
7023 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1);
7024
7025 switch (reg.fifo_mode)
7026 {
7027 case LSM6DSOX_BYPASS_MODE:
7028 *val = LSM6DSOX_BYPASS_MODE;
7029 break;
7030
7031 case LSM6DSOX_FIFO_MODE:
7032 *val = LSM6DSOX_FIFO_MODE;
7033 break;
7034
7035 case LSM6DSOX_STREAM_TO_FIFO_MODE:
7036 *val = LSM6DSOX_STREAM_TO_FIFO_MODE;
7037 break;
7038
7039 case LSM6DSOX_BYPASS_TO_STREAM_MODE:
7040 *val = LSM6DSOX_BYPASS_TO_STREAM_MODE;
7041 break;
7042
7043 case LSM6DSOX_STREAM_MODE:
7044 *val = LSM6DSOX_STREAM_MODE;
7045 break;
7046
7047 case LSM6DSOX_BYPASS_TO_FIFO_MODE:
7048 *val = LSM6DSOX_BYPASS_TO_FIFO_MODE;
7049 break;
7050
7051 default:
7052 *val = LSM6DSOX_BYPASS_MODE;
7053 break;
7054 }
7055
7056 return ret;
7057 }
7058
7059 /**
7060 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7061 * for temperature data.[set]
7062 *
7063 * @param ctx read / write interface definitions
7064 * @param val change the values of odr_t_batch in reg FIFO_CTRL4
7065 * @retval interface status (MANDATORY: return 0 -> no Error)
7066 *
7067 */
lsm6dsox_fifo_temp_batch_set(const stmdev_ctx_t * ctx,lsm6dsox_odr_t_batch_t val)7068 int32_t lsm6dsox_fifo_temp_batch_set(const stmdev_ctx_t *ctx,
7069 lsm6dsox_odr_t_batch_t val)
7070 {
7071 lsm6dsox_fifo_ctrl4_t reg;
7072 int32_t ret;
7073
7074 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1);
7075
7076 if (ret == 0)
7077 {
7078 reg.odr_t_batch = (uint8_t)val;
7079 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1);
7080 }
7081
7082 return ret;
7083 }
7084
7085 /**
7086 * @brief Selects Batching Data Rate (writing frequency in FIFO)
7087 * for temperature data.[get]
7088 *
7089 * @param ctx read / write interface definitions
7090 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4
7091 * @retval interface status (MANDATORY: return 0 -> no Error)
7092 *
7093 */
lsm6dsox_fifo_temp_batch_get(const stmdev_ctx_t * ctx,lsm6dsox_odr_t_batch_t * val)7094 int32_t lsm6dsox_fifo_temp_batch_get(const stmdev_ctx_t *ctx,
7095 lsm6dsox_odr_t_batch_t *val)
7096 {
7097 lsm6dsox_fifo_ctrl4_t reg;
7098 int32_t ret;
7099
7100 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1);
7101
7102 switch (reg.odr_t_batch)
7103 {
7104 case LSM6DSOX_TEMP_NOT_BATCHED:
7105 *val = LSM6DSOX_TEMP_NOT_BATCHED;
7106 break;
7107
7108 case LSM6DSOX_TEMP_BATCHED_AT_1Hz6:
7109 *val = LSM6DSOX_TEMP_BATCHED_AT_1Hz6;
7110 break;
7111
7112 case LSM6DSOX_TEMP_BATCHED_AT_12Hz5:
7113 *val = LSM6DSOX_TEMP_BATCHED_AT_12Hz5;
7114 break;
7115
7116 case LSM6DSOX_TEMP_BATCHED_AT_52Hz:
7117 *val = LSM6DSOX_TEMP_BATCHED_AT_52Hz;
7118 break;
7119
7120 default:
7121 *val = LSM6DSOX_TEMP_NOT_BATCHED;
7122 break;
7123 }
7124
7125 return ret;
7126 }
7127
7128 /**
7129 * @brief Selects decimation for timestamp batching in FIFO.
7130 * Writing rate will be the maximum rate between XL and
7131 * GYRO BDR divided by decimation decoder.[set]
7132 *
7133 * @param ctx read / write interface definitions
7134 * @param val change the values of odr_ts_batch in reg FIFO_CTRL4
7135 * @retval interface status (MANDATORY: return 0 -> no Error)
7136 *
7137 */
lsm6dsox_fifo_timestamp_decimation_set(const stmdev_ctx_t * ctx,lsm6dsox_odr_ts_batch_t val)7138 int32_t lsm6dsox_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx,
7139 lsm6dsox_odr_ts_batch_t val)
7140 {
7141 lsm6dsox_fifo_ctrl4_t reg;
7142 int32_t ret;
7143
7144 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1);
7145
7146 if (ret == 0)
7147 {
7148 reg.odr_ts_batch = (uint8_t)val;
7149 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1);
7150 }
7151
7152 return ret;
7153 }
7154
7155 /**
7156 * @brief Selects decimation for timestamp batching in FIFO.
7157 * Writing rate will be the maximum rate between XL and
7158 * GYRO BDR divided by decimation decoder.[get]
7159 *
7160 * @param ctx read / write interface definitions
7161 * @param val Get the values of odr_ts_batch in reg FIFO_CTRL4
7162 * @retval interface status (MANDATORY: return 0 -> no Error)
7163 *
7164 */
lsm6dsox_fifo_timestamp_decimation_get(const stmdev_ctx_t * ctx,lsm6dsox_odr_ts_batch_t * val)7165 int32_t lsm6dsox_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx,
7166 lsm6dsox_odr_ts_batch_t *val)
7167 {
7168 lsm6dsox_fifo_ctrl4_t reg;
7169 int32_t ret;
7170
7171 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_CTRL4, (uint8_t *)®, 1);
7172
7173 switch (reg.odr_ts_batch)
7174 {
7175 case LSM6DSOX_NO_DECIMATION:
7176 *val = LSM6DSOX_NO_DECIMATION;
7177 break;
7178
7179 case LSM6DSOX_DEC_1:
7180 *val = LSM6DSOX_DEC_1;
7181 break;
7182
7183 case LSM6DSOX_DEC_8:
7184 *val = LSM6DSOX_DEC_8;
7185 break;
7186
7187 case LSM6DSOX_DEC_32:
7188 *val = LSM6DSOX_DEC_32;
7189 break;
7190
7191 default:
7192 *val = LSM6DSOX_NO_DECIMATION;
7193 break;
7194 }
7195
7196 return ret;
7197 }
7198
7199 /**
7200 * @brief Selects the trigger for the internal counter of batching events
7201 * between XL and gyro.[set]
7202 *
7203 * @param ctx read / write interface definitions
7204 * @param val change the values of trig_counter_bdr
7205 * in reg COUNTER_BDR_REG1
7206 * @retval interface status (MANDATORY: return 0 -> no Error)
7207 *
7208 */
lsm6dsox_fifo_cnt_event_batch_set(const stmdev_ctx_t * ctx,lsm6dsox_trig_counter_bdr_t val)7209 int32_t lsm6dsox_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx,
7210 lsm6dsox_trig_counter_bdr_t val)
7211 {
7212 lsm6dsox_counter_bdr_reg1_t reg;
7213 int32_t ret;
7214
7215 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
7216 (uint8_t *)®, 1);
7217
7218 if (ret == 0)
7219 {
7220 reg.trig_counter_bdr = (uint8_t)val;
7221 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
7222 (uint8_t *)®, 1);
7223 }
7224
7225 return ret;
7226 }
7227
7228 /**
7229 * @brief Selects the trigger for the internal counter of batching events
7230 * between XL and gyro.[get]
7231 *
7232 * @param ctx read / write interface definitions
7233 * @param val Get the values of trig_counter_bdr
7234 * in reg COUNTER_BDR_REG1
7235 * @retval interface status (MANDATORY: return 0 -> no Error)
7236 *
7237 */
lsm6dsox_fifo_cnt_event_batch_get(const stmdev_ctx_t * ctx,lsm6dsox_trig_counter_bdr_t * val)7238 int32_t lsm6dsox_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx,
7239 lsm6dsox_trig_counter_bdr_t *val)
7240 {
7241 lsm6dsox_counter_bdr_reg1_t reg;
7242 int32_t ret;
7243
7244 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
7245 (uint8_t *)®, 1);
7246
7247 switch (reg.trig_counter_bdr)
7248 {
7249 case LSM6DSOX_XL_BATCH_EVENT:
7250 *val = LSM6DSOX_XL_BATCH_EVENT;
7251 break;
7252
7253 case LSM6DSOX_GYRO_BATCH_EVENT:
7254 *val = LSM6DSOX_GYRO_BATCH_EVENT;
7255 break;
7256
7257 default:
7258 *val = LSM6DSOX_XL_BATCH_EVENT;
7259 break;
7260 }
7261
7262 return ret;
7263 }
7264
7265 /**
7266 * @brief Resets the internal counter of batching vents for a single sensor.
7267 * This bit is automatically reset to zero if it was set to ‘1’.[set]
7268 *
7269 * @param ctx read / write interface definitions
7270 * @param val change the values of rst_counter_bdr in
7271 * reg COUNTER_BDR_REG1
7272 * @retval interface status (MANDATORY: return 0 -> no Error)
7273 *
7274 */
lsm6dsox_rst_batch_counter_set(const stmdev_ctx_t * ctx,uint8_t val)7275 int32_t lsm6dsox_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val)
7276 {
7277 lsm6dsox_counter_bdr_reg1_t reg;
7278 int32_t ret;
7279
7280 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
7281 (uint8_t *)®, 1);
7282
7283 if (ret == 0)
7284 {
7285 reg.rst_counter_bdr = val;
7286 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
7287 (uint8_t *)®, 1);
7288 }
7289
7290 return ret;
7291 }
7292
7293 /**
7294 * @brief Resets the internal counter of batching events for a single sensor.
7295 * This bit is automatically reset to zero if it was set to ‘1’.[get]
7296 *
7297 * @param ctx read / write interface definitions
7298 * @param val change the values of rst_counter_bdr in
7299 * reg COUNTER_BDR_REG1
7300 * @retval interface status (MANDATORY: return 0 -> no Error)
7301 *
7302 */
lsm6dsox_rst_batch_counter_get(const stmdev_ctx_t * ctx,uint8_t * val)7303 int32_t lsm6dsox_rst_batch_counter_get(const stmdev_ctx_t *ctx,
7304 uint8_t *val)
7305 {
7306 lsm6dsox_counter_bdr_reg1_t reg;
7307 int32_t ret;
7308
7309 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
7310 (uint8_t *)®, 1);
7311 *val = reg.rst_counter_bdr;
7312
7313 return ret;
7314 }
7315
7316 /**
7317 * @brief Batch data rate counter.[set]
7318 *
7319 * @param ctx read / write interface definitions
7320 * @param val change the values of cnt_bdr_th in
7321 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
7322 * @retval interface status (MANDATORY: return 0 -> no Error)
7323 *
7324 */
lsm6dsox_batch_counter_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)7325 int32_t lsm6dsox_batch_counter_threshold_set(const stmdev_ctx_t *ctx,
7326 uint16_t val)
7327 {
7328 lsm6dsox_counter_bdr_reg1_t counter_bdr_reg1;
7329 lsm6dsox_counter_bdr_reg2_t counter_bdr_reg2;
7330 int32_t ret;
7331
7332 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
7333 (uint8_t *)&counter_bdr_reg1, 1);
7334
7335 if (ret == 0)
7336 {
7337 counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val;
7338 counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8;
7339 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
7340 (uint8_t *)&counter_bdr_reg1, 1);
7341 }
7342
7343 if (ret == 0)
7344 {
7345 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_COUNTER_BDR_REG2,
7346 (uint8_t *)&counter_bdr_reg2, 1);
7347 }
7348
7349 return ret;
7350 }
7351
7352 /**
7353 * @brief Batch data rate counter.[get]
7354 *
7355 * @param ctx read / write interface definitions
7356 * @param val change the values of cnt_bdr_th in
7357 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
7358 * @retval interface status (MANDATORY: return 0 -> no Error)
7359 *
7360 */
lsm6dsox_batch_counter_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)7361 int32_t lsm6dsox_batch_counter_threshold_get(const stmdev_ctx_t *ctx,
7362 uint16_t *val)
7363 {
7364 lsm6dsox_counter_bdr_reg1_t counter_bdr_reg1;
7365 lsm6dsox_counter_bdr_reg2_t counter_bdr_reg2;
7366 int32_t ret;
7367
7368 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG1,
7369 (uint8_t *)&counter_bdr_reg1, 1);
7370
7371 if (ret == 0)
7372 {
7373 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_COUNTER_BDR_REG2,
7374 (uint8_t *)&counter_bdr_reg2, 1);
7375 *val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8)
7376 + (uint16_t)counter_bdr_reg2.cnt_bdr_th;
7377 }
7378
7379 return ret;
7380 }
7381
7382 /**
7383 * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
7384 *
7385 * @param ctx Read / write interface definitions.(ptr)
7386 * @param val Read the value of diff_fifo in reg FIFO_STATUS1 and FIFO_STATUS2
7387 * @retval Interface status (MANDATORY: return 0 -> no Error).
7388 *
7389 */
lsm6dsox_fifo_data_level_get(const stmdev_ctx_t * ctx,uint16_t * val)7390 int32_t lsm6dsox_fifo_data_level_get(const stmdev_ctx_t *ctx,
7391 uint16_t *val)
7392 {
7393 uint8_t reg[2];
7394 lsm6dsox_fifo_status1_t *fifo_status1 = (lsm6dsox_fifo_status1_t *)®[0];
7395 lsm6dsox_fifo_status2_t *fifo_status2 = (lsm6dsox_fifo_status2_t *)®[1];
7396 int32_t ret;
7397
7398 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7399 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS1, (uint8_t *)reg, 2);
7400 if (ret == 0)
7401 {
7402 *val = fifo_status2->diff_fifo;
7403 *val = (*val * 256U) + fifo_status1->diff_fifo;
7404 }
7405
7406 return ret;
7407 }
7408
7409 /**
7410 * @brief Smart FIFO status.[get]
7411 *
7412 * @param ctx Read / write interface definitions.(ptr)
7413 * @param val Read registers FIFO_STATUS2
7414 * @retval Interface status (MANDATORY: return 0 -> no Error).
7415 *
7416 */
lsm6dsox_fifo_status_get(const stmdev_ctx_t * ctx,lsm6dsox_fifo_status2_t * val)7417 int32_t lsm6dsox_fifo_status_get(const stmdev_ctx_t *ctx,
7418 lsm6dsox_fifo_status2_t *val)
7419 {
7420 uint8_t reg[2];
7421 lsm6dsox_fifo_status2_t *fifo_status2 = (lsm6dsox_fifo_status2_t *)®[1];
7422 int32_t ret;
7423
7424 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7425 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS1, (uint8_t *)reg, 2);
7426 if (ret == 0)
7427 {
7428 *val = *fifo_status2;
7429 }
7430
7431 return ret;
7432 }
7433
7434 /**
7435 * @brief Smart FIFO full status.[get]
7436 *
7437 * @param ctx Read / write interface definitions.(ptr)
7438 * @param val Read the values of fifo_full_ia in reg FIFO_STATUS2
7439 * @retval Interface status (MANDATORY: return 0 -> no Error).
7440 *
7441 */
lsm6dsox_fifo_full_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)7442 int32_t lsm6dsox_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
7443 {
7444 uint8_t reg[2];
7445 lsm6dsox_fifo_status2_t *fifo_status2 = (lsm6dsox_fifo_status2_t *)®[1];
7446 int32_t ret;
7447
7448 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7449 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS1, (uint8_t *)reg, 2);
7450 if (ret == 0)
7451 {
7452 *val = fifo_status2->fifo_full_ia;
7453 }
7454
7455 return ret;
7456 }
7457
7458 /**
7459 * @brief FIFO overrun status.[get]
7460 *
7461 * @param ctx Read / write interface definitions.(ptr)
7462 * @param val Read the values of fifo_over_run_latched in
7463 * reg FIFO_STATUS2
7464 * @retval Interface status (MANDATORY: return 0 -> no Error).
7465 *
7466 */
lsm6dsox_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)7467 int32_t lsm6dsox_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
7468 {
7469 uint8_t reg[2];
7470 lsm6dsox_fifo_status2_t *fifo_status2 = (lsm6dsox_fifo_status2_t *)®[1];
7471 int32_t ret;
7472
7473 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7474 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS1, (uint8_t *)reg, 2);
7475 if (ret == 0)
7476 {
7477 *val = fifo_status2->fifo_ovr_ia;
7478 }
7479
7480 return ret;
7481 }
7482
7483 /**
7484 * @brief FIFO watermark status.[get]
7485 *
7486 * @param ctx Read / write interface definitions.(ptr)
7487 * @param val Read the values of fifo_wtm_ia in reg FIFO_STATUS2
7488 * @retval Interface status (MANDATORY: return 0 -> no Error).
7489 *
7490 */
lsm6dsox_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)7491 int32_t lsm6dsox_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
7492 {
7493 uint8_t reg[2];
7494 lsm6dsox_fifo_status2_t *fifo_status2 = (lsm6dsox_fifo_status2_t *)®[1];
7495 int32_t ret;
7496
7497 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
7498 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_STATUS1, (uint8_t *)reg, 2);
7499 if (ret == 0)
7500 {
7501 *val = fifo_status2->fifo_wtm_ia;
7502 }
7503
7504 return ret;
7505 }
7506
7507 /**
7508 * @brief Identifies the sensor in FIFO_DATA_OUT.[get]
7509 *
7510 * @param ctx read / write interface definitions
7511 * @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
7512 * @retval interface status (MANDATORY: return 0 -> no Error)
7513 *
7514 */
lsm6dsox_fifo_sensor_tag_get(const stmdev_ctx_t * ctx,lsm6dsox_fifo_tag_t * val)7515 int32_t lsm6dsox_fifo_sensor_tag_get(const stmdev_ctx_t *ctx,
7516 lsm6dsox_fifo_tag_t *val)
7517 {
7518 lsm6dsox_fifo_data_out_tag_t reg;
7519 int32_t ret;
7520
7521 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FIFO_DATA_OUT_TAG,
7522 (uint8_t *)®, 1);
7523
7524 switch (reg.tag_sensor)
7525 {
7526 case LSM6DSOX_GYRO_NC_TAG:
7527 *val = LSM6DSOX_GYRO_NC_TAG;
7528 break;
7529
7530 case LSM6DSOX_XL_NC_TAG:
7531 *val = LSM6DSOX_XL_NC_TAG;
7532 break;
7533
7534 case LSM6DSOX_TEMPERATURE_TAG:
7535 *val = LSM6DSOX_TEMPERATURE_TAG;
7536 break;
7537
7538 case LSM6DSOX_TIMESTAMP_TAG:
7539 *val = LSM6DSOX_TIMESTAMP_TAG;
7540 break;
7541
7542 case LSM6DSOX_CFG_CHANGE_TAG:
7543 *val = LSM6DSOX_CFG_CHANGE_TAG;
7544 break;
7545
7546 case LSM6DSOX_XL_NC_T_2_TAG:
7547 *val = LSM6DSOX_XL_NC_T_2_TAG;
7548 break;
7549
7550 case LSM6DSOX_XL_NC_T_1_TAG:
7551 *val = LSM6DSOX_XL_NC_T_1_TAG;
7552 break;
7553
7554 case LSM6DSOX_XL_2XC_TAG:
7555 *val = LSM6DSOX_XL_2XC_TAG;
7556 break;
7557
7558 case LSM6DSOX_XL_3XC_TAG:
7559 *val = LSM6DSOX_XL_3XC_TAG;
7560 break;
7561
7562 case LSM6DSOX_GYRO_NC_T_2_TAG:
7563 *val = LSM6DSOX_GYRO_NC_T_2_TAG;
7564 break;
7565
7566 case LSM6DSOX_GYRO_NC_T_1_TAG:
7567 *val = LSM6DSOX_GYRO_NC_T_1_TAG;
7568 break;
7569
7570 case LSM6DSOX_GYRO_2XC_TAG:
7571 *val = LSM6DSOX_GYRO_2XC_TAG;
7572 break;
7573
7574 case LSM6DSOX_GYRO_3XC_TAG:
7575 *val = LSM6DSOX_GYRO_3XC_TAG;
7576 break;
7577
7578 case LSM6DSOX_SENSORHUB_SLAVE0_TAG:
7579 *val = LSM6DSOX_SENSORHUB_SLAVE0_TAG;
7580 break;
7581
7582 case LSM6DSOX_SENSORHUB_SLAVE1_TAG:
7583 *val = LSM6DSOX_SENSORHUB_SLAVE1_TAG;
7584 break;
7585
7586 case LSM6DSOX_SENSORHUB_SLAVE2_TAG:
7587 *val = LSM6DSOX_SENSORHUB_SLAVE2_TAG;
7588 break;
7589
7590 case LSM6DSOX_SENSORHUB_SLAVE3_TAG:
7591 *val = LSM6DSOX_SENSORHUB_SLAVE3_TAG;
7592 break;
7593
7594 case LSM6DSOX_STEP_CPUNTER_TAG:
7595 *val = LSM6DSOX_STEP_CPUNTER_TAG;
7596 break;
7597
7598 case LSM6DSOX_GAME_ROTATION_TAG:
7599 *val = LSM6DSOX_GAME_ROTATION_TAG;
7600 break;
7601
7602 case LSM6DSOX_GEOMAG_ROTATION_TAG:
7603 *val = LSM6DSOX_GEOMAG_ROTATION_TAG;
7604 break;
7605
7606 case LSM6DSOX_ROTATION_TAG:
7607 *val = LSM6DSOX_ROTATION_TAG;
7608 break;
7609
7610 case LSM6DSOX_SENSORHUB_NACK_TAG:
7611 *val = LSM6DSOX_SENSORHUB_NACK_TAG;
7612 break;
7613
7614 default:
7615 *val = LSM6DSOX_GYRO_NC_TAG;
7616 break;
7617 }
7618
7619 return ret;
7620 }
7621
7622 /**
7623 * @brief : Enable FIFO batching of pedometer embedded
7624 * function values.[set]
7625 *
7626 * @param ctx read / write interface definitions
7627 * @param val change the values of gbias_fifo_en in
7628 * reg LSM6DSOX_EMB_FUNC_FIFO_CFG
7629 * @retval interface status (MANDATORY: return 0 -> no Error)
7630 *
7631 */
lsm6dsox_fifo_pedo_batch_set(const stmdev_ctx_t * ctx,uint8_t val)7632 int32_t lsm6dsox_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
7633 {
7634 lsm6dsox_emb_func_fifo_cfg_t reg;
7635 int32_t ret;
7636
7637 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
7638
7639 if (ret == 0)
7640 {
7641 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG,
7642 (uint8_t *)®, 1);
7643 }
7644
7645 if (ret == 0)
7646 {
7647 reg.pedo_fifo_en = val;
7648 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG,
7649 (uint8_t *)®, 1);
7650 }
7651
7652 if (ret == 0)
7653 {
7654 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
7655 }
7656
7657 return ret;
7658 }
7659
7660 /**
7661 * @brief Enable FIFO batching of pedometer embedded function values.[get]
7662 *
7663 * @param ctx read / write interface definitions
7664 * @param val change the values of pedo_fifo_en in
7665 * reg LSM6DSOX_EMB_FUNC_FIFO_CFG
7666 * @retval interface status (MANDATORY: return 0 -> no Error)
7667 *
7668 */
lsm6dsox_fifo_pedo_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)7669 int32_t lsm6dsox_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
7670 {
7671 lsm6dsox_emb_func_fifo_cfg_t reg;
7672 int32_t ret;
7673
7674 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
7675
7676 if (ret == 0)
7677 {
7678 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_FIFO_CFG,
7679 (uint8_t *)®, 1);
7680 }
7681
7682 if (ret == 0)
7683 {
7684 *val = reg.pedo_fifo_en;
7685 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
7686 }
7687
7688 return ret;
7689 }
7690
7691 /**
7692 * @brief Enable FIFO batching data of first slave.[set]
7693 *
7694 * @param ctx read / write interface definitions
7695 * @param val change the values of batch_ext_sens_0_en in
7696 * reg SLV0_CONFIG
7697 * @retval interface status (MANDATORY: return 0 -> no Error)
7698 *
7699 */
lsm6dsox_sh_batch_slave_0_set(const stmdev_ctx_t * ctx,uint8_t val)7700 int32_t lsm6dsox_sh_batch_slave_0_set(const stmdev_ctx_t *ctx, uint8_t val)
7701 {
7702 lsm6dsox_slv0_config_t reg;
7703 int32_t ret;
7704
7705 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
7706
7707 if (ret == 0)
7708 {
7709 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t *)®, 1);
7710 }
7711
7712 if (ret == 0)
7713 {
7714 reg.batch_ext_sens_0_en = val;
7715 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t *)®, 1);
7716 }
7717
7718 if (ret == 0)
7719 {
7720 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
7721 }
7722
7723 return ret;
7724 }
7725
7726 /**
7727 * @brief Enable FIFO batching data of first slave.[get]
7728 *
7729 * @param ctx read / write interface definitions
7730 * @param val change the values of batch_ext_sens_0_en in
7731 * reg SLV0_CONFIG
7732 * @retval interface status (MANDATORY: return 0 -> no Error)
7733 *
7734 */
lsm6dsox_sh_batch_slave_0_get(const stmdev_ctx_t * ctx,uint8_t * val)7735 int32_t lsm6dsox_sh_batch_slave_0_get(const stmdev_ctx_t *ctx, uint8_t *val)
7736 {
7737 lsm6dsox_slv0_config_t reg;
7738 int32_t ret;
7739
7740 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
7741
7742 if (ret == 0)
7743 {
7744 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t *)®, 1);
7745 }
7746
7747 if (ret == 0)
7748 {
7749 *val = reg.batch_ext_sens_0_en;
7750 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
7751 }
7752
7753 return ret;
7754 }
7755
7756 /**
7757 * @brief Enable FIFO batching data of second slave.[set]
7758 *
7759 * @param ctx read / write interface definitions
7760 * @param val change the values of batch_ext_sens_1_en in
7761 * reg SLV1_CONFIG
7762 * @retval interface status (MANDATORY: return 0 -> no Error)
7763 *
7764 */
lsm6dsox_sh_batch_slave_1_set(const stmdev_ctx_t * ctx,uint8_t val)7765 int32_t lsm6dsox_sh_batch_slave_1_set(const stmdev_ctx_t *ctx, uint8_t val)
7766 {
7767 lsm6dsox_slv1_config_t reg;
7768 int32_t ret;
7769
7770 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
7771
7772 if (ret == 0)
7773 {
7774 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t *)®, 1);
7775 }
7776
7777 if (ret == 0)
7778 {
7779 reg.batch_ext_sens_1_en = val;
7780 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t *)®, 1);
7781 }
7782
7783 if (ret == 0)
7784 {
7785 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
7786 }
7787
7788 return ret;
7789 }
7790
7791 /**
7792 * @brief Enable FIFO batching data of second slave.[get]
7793 *
7794 * @param ctx read / write interface definitions
7795 * @param val change the values of batch_ext_sens_1_en in
7796 * reg SLV1_CONFIG
7797 * @retval interface status (MANDATORY: return 0 -> no Error)
7798 *
7799 */
lsm6dsox_sh_batch_slave_1_get(const stmdev_ctx_t * ctx,uint8_t * val)7800 int32_t lsm6dsox_sh_batch_slave_1_get(const stmdev_ctx_t *ctx, uint8_t *val)
7801 {
7802 lsm6dsox_slv1_config_t reg;
7803 int32_t ret;
7804
7805 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
7806
7807 if (ret == 0)
7808 {
7809 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG, (uint8_t *)®, 1);
7810 *val = reg.batch_ext_sens_1_en;
7811 }
7812
7813 if (ret == 0)
7814 {
7815 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
7816 }
7817
7818 return ret;
7819 }
7820
7821 /**
7822 * @brief Enable FIFO batching data of third slave.[set]
7823 *
7824 * @param ctx read / write interface definitions
7825 * @param val change the values of batch_ext_sens_2_en in
7826 * reg SLV2_CONFIG
7827 * @retval interface status (MANDATORY: return 0 -> no Error)
7828 *
7829 */
lsm6dsox_sh_batch_slave_2_set(const stmdev_ctx_t * ctx,uint8_t val)7830 int32_t lsm6dsox_sh_batch_slave_2_set(const stmdev_ctx_t *ctx, uint8_t val)
7831 {
7832 lsm6dsox_slv2_config_t reg;
7833 int32_t ret;
7834
7835 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
7836
7837 if (ret == 0)
7838 {
7839 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t *)®, 1);
7840 }
7841
7842 if (ret == 0)
7843 {
7844 reg.batch_ext_sens_2_en = val;
7845 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t *)®, 1);
7846 }
7847
7848 if (ret == 0)
7849 {
7850 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
7851 }
7852
7853 return ret;
7854 }
7855
7856 /**
7857 * @brief Enable FIFO batching data of third slave.[get]
7858 *
7859 * @param ctx read / write interface definitions
7860 * @param val change the values of batch_ext_sens_2_en in
7861 * reg SLV2_CONFIG
7862 * @retval interface status (MANDATORY: return 0 -> no Error)
7863 *
7864 */
lsm6dsox_sh_batch_slave_2_get(const stmdev_ctx_t * ctx,uint8_t * val)7865 int32_t lsm6dsox_sh_batch_slave_2_get(const stmdev_ctx_t *ctx, uint8_t *val)
7866 {
7867 lsm6dsox_slv2_config_t reg;
7868 int32_t ret;
7869
7870 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
7871
7872 if (ret == 0)
7873 {
7874 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG, (uint8_t *)®, 1);
7875 }
7876
7877 if (ret == 0)
7878 {
7879 *val = reg.batch_ext_sens_2_en;
7880 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
7881 }
7882
7883 return ret;
7884 }
7885
7886 /**
7887 * @brief Enable FIFO batching data of fourth slave.[set]
7888 *
7889 * @param ctx read / write interface definitions
7890 * @param val change the values of batch_ext_sens_3_en
7891 * in reg SLV3_CONFIG
7892 * @retval interface status (MANDATORY: return 0 -> no Error)
7893 *
7894 */
lsm6dsox_sh_batch_slave_3_set(const stmdev_ctx_t * ctx,uint8_t val)7895 int32_t lsm6dsox_sh_batch_slave_3_set(const stmdev_ctx_t *ctx, uint8_t val)
7896 {
7897 lsm6dsox_slv3_config_t reg;
7898 int32_t ret;
7899
7900 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
7901
7902 if (ret == 0)
7903 {
7904 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t *)®, 1);
7905 }
7906
7907 if (ret == 0)
7908 {
7909 reg.batch_ext_sens_3_en = val;
7910 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t *)®, 1);
7911 }
7912
7913 if (ret == 0)
7914 {
7915 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
7916 }
7917
7918 return ret;
7919 }
7920
7921 /**
7922 * @brief Enable FIFO batching data of fourth slave.[get]
7923 *
7924 * @param ctx read / write interface definitions
7925 * @param val change the values of batch_ext_sens_3_en in
7926 * reg SLV3_CONFIG
7927 * @retval interface status (MANDATORY: return 0 -> no Error)
7928 *
7929 */
lsm6dsox_sh_batch_slave_3_get(const stmdev_ctx_t * ctx,uint8_t * val)7930 int32_t lsm6dsox_sh_batch_slave_3_get(const stmdev_ctx_t *ctx, uint8_t *val)
7931 {
7932 lsm6dsox_slv3_config_t reg;
7933 int32_t ret;
7934
7935 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
7936
7937 if (ret == 0)
7938 {
7939 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG, (uint8_t *)®, 1);
7940 }
7941
7942 if (ret == 0)
7943 {
7944 *val = reg.batch_ext_sens_3_en;
7945 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
7946 }
7947
7948 return ret;
7949 }
7950
7951 /**
7952 * @}
7953 *
7954 */
7955
7956 /**
7957 * @defgroup LSM6DSOX_DEN_functionality
7958 * @brief This section groups all the functions concerning
7959 * DEN functionality.
7960 * @{
7961 *
7962 */
7963
7964 /**
7965 * @brief DEN functionality marking mode.[set]
7966 *
7967 * @param ctx read / write interface definitions
7968 * @param val change the values of den_mode in reg CTRL6_C
7969 * @retval interface status (MANDATORY: return 0 -> no Error)
7970 *
7971 */
lsm6dsox_den_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_den_mode_t val)7972 int32_t lsm6dsox_den_mode_set(const stmdev_ctx_t *ctx,
7973 lsm6dsox_den_mode_t val)
7974 {
7975 lsm6dsox_ctrl6_c_t reg;
7976 int32_t ret;
7977
7978 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1);
7979
7980 if (ret == 0)
7981 {
7982 reg.den_mode = (uint8_t)val;
7983 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1);
7984 }
7985
7986 return ret;
7987 }
7988
7989 /**
7990 * @brief DEN functionality marking mode.[get]
7991 *
7992 * @param ctx read / write interface definitions
7993 * @param val Get the values of den_mode in reg CTRL6_C
7994 * @retval interface status (MANDATORY: return 0 -> no Error)
7995 *
7996 */
lsm6dsox_den_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_den_mode_t * val)7997 int32_t lsm6dsox_den_mode_get(const stmdev_ctx_t *ctx,
7998 lsm6dsox_den_mode_t *val)
7999 {
8000 lsm6dsox_ctrl6_c_t reg;
8001 int32_t ret;
8002
8003 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL6_C, (uint8_t *)®, 1);
8004
8005 switch (reg.den_mode)
8006 {
8007 case LSM6DSOX_DEN_DISABLE:
8008 *val = LSM6DSOX_DEN_DISABLE;
8009 break;
8010
8011 case LSM6DSOX_LEVEL_FIFO:
8012 *val = LSM6DSOX_LEVEL_FIFO;
8013 break;
8014
8015 case LSM6DSOX_LEVEL_LETCHED:
8016 *val = LSM6DSOX_LEVEL_LETCHED;
8017 break;
8018
8019 case LSM6DSOX_LEVEL_TRIGGER:
8020 *val = LSM6DSOX_LEVEL_TRIGGER;
8021 break;
8022
8023 case LSM6DSOX_EDGE_TRIGGER:
8024 *val = LSM6DSOX_EDGE_TRIGGER;
8025 break;
8026
8027 default:
8028 *val = LSM6DSOX_DEN_DISABLE;
8029 break;
8030 }
8031
8032 return ret;
8033 }
8034
8035 /**
8036 * @brief DEN active level configuration.[set]
8037 *
8038 * @param ctx read / write interface definitions
8039 * @param val change the values of den_lh in reg CTRL9_XL
8040 * @retval interface status (MANDATORY: return 0 -> no Error)
8041 *
8042 */
lsm6dsox_den_polarity_set(const stmdev_ctx_t * ctx,lsm6dsox_den_lh_t val)8043 int32_t lsm6dsox_den_polarity_set(const stmdev_ctx_t *ctx,
8044 lsm6dsox_den_lh_t val)
8045 {
8046 lsm6dsox_ctrl9_xl_t reg;
8047 int32_t ret;
8048
8049 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
8050
8051 if (ret == 0)
8052 {
8053 reg.den_lh = (uint8_t)val;
8054 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
8055 }
8056
8057 return ret;
8058 }
8059
8060 /**
8061 * @brief DEN active level configuration.[get]
8062 *
8063 * @param ctx read / write interface definitions
8064 * @param val Get the values of den_lh in reg CTRL9_XL
8065 * @retval interface status (MANDATORY: return 0 -> no Error)
8066 *
8067 */
lsm6dsox_den_polarity_get(const stmdev_ctx_t * ctx,lsm6dsox_den_lh_t * val)8068 int32_t lsm6dsox_den_polarity_get(const stmdev_ctx_t *ctx,
8069 lsm6dsox_den_lh_t *val)
8070 {
8071 lsm6dsox_ctrl9_xl_t reg;
8072 int32_t ret;
8073
8074 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
8075
8076 switch (reg.den_lh)
8077 {
8078 case LSM6DSOX_DEN_ACT_LOW:
8079 *val = LSM6DSOX_DEN_ACT_LOW;
8080 break;
8081
8082 case LSM6DSOX_DEN_ACT_HIGH:
8083 *val = LSM6DSOX_DEN_ACT_HIGH;
8084 break;
8085
8086 default:
8087 *val = LSM6DSOX_DEN_ACT_LOW;
8088 break;
8089 }
8090
8091 return ret;
8092 }
8093
8094 /**
8095 * @brief DEN enable.[set]
8096 *
8097 * @param ctx read / write interface definitions
8098 * @param val change the values of den_xl_g in reg CTRL9_XL
8099 * @retval interface status (MANDATORY: return 0 -> no Error)
8100 *
8101 */
lsm6dsox_den_enable_set(const stmdev_ctx_t * ctx,lsm6dsox_den_xl_g_t val)8102 int32_t lsm6dsox_den_enable_set(const stmdev_ctx_t *ctx,
8103 lsm6dsox_den_xl_g_t val)
8104 {
8105 lsm6dsox_ctrl9_xl_t reg;
8106 int32_t ret;
8107
8108 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
8109
8110 if (ret == 0)
8111 {
8112 reg.den_xl_g = (uint8_t)val;
8113 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
8114 }
8115
8116 return ret;
8117 }
8118
8119 /**
8120 * @brief DEN enable.[get]
8121 *
8122 * @param ctx read / write interface definitions
8123 * @param val Get the values of den_xl_g in reg CTRL9_XL
8124 * @retval interface status (MANDATORY: return 0 -> no Error)
8125 *
8126 */
lsm6dsox_den_enable_get(const stmdev_ctx_t * ctx,lsm6dsox_den_xl_g_t * val)8127 int32_t lsm6dsox_den_enable_get(const stmdev_ctx_t *ctx,
8128 lsm6dsox_den_xl_g_t *val)
8129 {
8130 lsm6dsox_ctrl9_xl_t reg;
8131 int32_t ret;
8132
8133 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
8134
8135 switch (reg.den_xl_g)
8136 {
8137 case LSM6DSOX_STAMP_IN_GY_DATA:
8138 *val = LSM6DSOX_STAMP_IN_GY_DATA;
8139 break;
8140
8141 case LSM6DSOX_STAMP_IN_XL_DATA:
8142 *val = LSM6DSOX_STAMP_IN_XL_DATA;
8143 break;
8144
8145 case LSM6DSOX_STAMP_IN_GY_XL_DATA:
8146 *val = LSM6DSOX_STAMP_IN_GY_XL_DATA;
8147 break;
8148
8149 default:
8150 *val = LSM6DSOX_STAMP_IN_GY_DATA;
8151 break;
8152 }
8153
8154 return ret;
8155 }
8156
8157 /**
8158 * @brief DEN value stored in LSB of X-axis.[set]
8159 *
8160 * @param ctx read / write interface definitions
8161 * @param val change the values of den_z in reg CTRL9_XL
8162 * @retval interface status (MANDATORY: return 0 -> no Error)
8163 *
8164 */
lsm6dsox_den_mark_axis_x_set(const stmdev_ctx_t * ctx,uint8_t val)8165 int32_t lsm6dsox_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val)
8166 {
8167 lsm6dsox_ctrl9_xl_t reg;
8168 int32_t ret;
8169
8170 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
8171
8172 if (ret == 0)
8173 {
8174 reg.den_z = val;
8175 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
8176 }
8177
8178 return ret;
8179 }
8180
8181 /**
8182 * @brief DEN value stored in LSB of X-axis.[get]
8183 *
8184 * @param ctx read / write interface definitions
8185 * @param val change the values of den_z in reg CTRL9_XL
8186 * @retval interface status (MANDATORY: return 0 -> no Error)
8187 *
8188 */
lsm6dsox_den_mark_axis_x_get(const stmdev_ctx_t * ctx,uint8_t * val)8189 int32_t lsm6dsox_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val)
8190 {
8191 lsm6dsox_ctrl9_xl_t reg;
8192 int32_t ret;
8193
8194 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
8195 *val = reg.den_z;
8196
8197 return ret;
8198 }
8199
8200 /**
8201 * @brief DEN value stored in LSB of Y-axis.[set]
8202 *
8203 * @param ctx read / write interface definitions
8204 * @param val change the values of den_y in reg CTRL9_XL
8205 * @retval interface status (MANDATORY: return 0 -> no Error)
8206 *
8207 */
lsm6dsox_den_mark_axis_y_set(const stmdev_ctx_t * ctx,uint8_t val)8208 int32_t lsm6dsox_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val)
8209 {
8210 lsm6dsox_ctrl9_xl_t reg;
8211 int32_t ret;
8212
8213 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
8214
8215 if (ret == 0)
8216 {
8217 reg.den_y = val;
8218 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
8219 }
8220
8221 return ret;
8222 }
8223
8224 /**
8225 * @brief DEN value stored in LSB of Y-axis.[get]
8226 *
8227 * @param ctx read / write interface definitions
8228 * @param val change the values of den_y in reg CTRL9_XL
8229 * @retval interface status (MANDATORY: return 0 -> no Error)
8230 *
8231 */
lsm6dsox_den_mark_axis_y_get(const stmdev_ctx_t * ctx,uint8_t * val)8232 int32_t lsm6dsox_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val)
8233 {
8234 lsm6dsox_ctrl9_xl_t reg;
8235 int32_t ret;
8236
8237 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
8238 *val = reg.den_y;
8239
8240 return ret;
8241 }
8242
8243 /**
8244 * @brief DEN value stored in LSB of Z-axis.[set]
8245 *
8246 * @param ctx read / write interface definitions
8247 * @param val change the values of den_x in reg CTRL9_XL
8248 * @retval interface status (MANDATORY: return 0 -> no Error)
8249 *
8250 */
lsm6dsox_den_mark_axis_z_set(const stmdev_ctx_t * ctx,uint8_t val)8251 int32_t lsm6dsox_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val)
8252 {
8253 lsm6dsox_ctrl9_xl_t reg;
8254 int32_t ret;
8255
8256 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
8257
8258 if (ret == 0)
8259 {
8260 reg.den_x = val;
8261 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
8262 }
8263
8264 return ret;
8265 }
8266
8267 /**
8268 * @brief DEN value stored in LSB of Z-axis.[get]
8269 *
8270 * @param ctx read / write interface definitions
8271 * @param val change the values of den_x in reg CTRL9_XL
8272 * @retval interface status (MANDATORY: return 0 -> no Error)
8273 *
8274 */
lsm6dsox_den_mark_axis_z_get(const stmdev_ctx_t * ctx,uint8_t * val)8275 int32_t lsm6dsox_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val)
8276 {
8277 lsm6dsox_ctrl9_xl_t reg;
8278 int32_t ret;
8279
8280 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL, (uint8_t *)®, 1);
8281 *val = reg.den_x;
8282
8283 return ret;
8284 }
8285
8286 /**
8287 * @}
8288 *
8289 */
8290
8291 /**
8292 * @defgroup LSM6DSOX_Pedometer
8293 * @brief This section groups all the functions that manage pedometer.
8294 * @{
8295 *
8296 */
8297
8298 /**
8299 * @brief Enable pedometer algorithm.[set]
8300 *
8301 * @param ctx read / write interface definitions
8302 * @param val turn on and configure pedometer
8303 * @retval interface status (MANDATORY: return 0 -> no Error)
8304 *
8305 */
lsm6dsox_pedo_sens_set(const stmdev_ctx_t * ctx,lsm6dsox_pedo_md_t val)8306 int32_t lsm6dsox_pedo_sens_set(const stmdev_ctx_t *ctx,
8307 lsm6dsox_pedo_md_t val)
8308 {
8309 lsm6dsox_pedo_cmd_reg_t pedo_cmd_reg;
8310 int32_t ret;
8311
8312 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
8313 (uint8_t *)&pedo_cmd_reg);
8314
8315 if (ret == 0)
8316 {
8317 pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U) >> 4;
8318 pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U) >> 5;
8319 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
8320 (uint8_t *)&pedo_cmd_reg);
8321 }
8322
8323 return ret;
8324 }
8325
8326 /**
8327 * @brief Enable pedometer algorithm.[get]
8328 *
8329 * @param ctx read / write interface definitions
8330 * @param val turn on and configure pedometer
8331 * @retval interface status (MANDATORY: return 0 -> no Error)
8332 *
8333 */
lsm6dsox_pedo_sens_get(const stmdev_ctx_t * ctx,lsm6dsox_pedo_md_t * val)8334 int32_t lsm6dsox_pedo_sens_get(const stmdev_ctx_t *ctx,
8335 lsm6dsox_pedo_md_t *val)
8336 {
8337 lsm6dsox_pedo_cmd_reg_t pedo_cmd_reg;
8338 int32_t ret;
8339
8340 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
8341 (uint8_t *)&pedo_cmd_reg);
8342
8343 switch ((pedo_cmd_reg.ad_det_en << 5) | (pedo_cmd_reg.fp_rejection_en
8344 << 4))
8345 {
8346 case LSM6DSOX_PEDO_BASE_MODE:
8347 *val = LSM6DSOX_PEDO_BASE_MODE;
8348 break;
8349
8350 case LSM6DSOX_FALSE_STEP_REJ:
8351 *val = LSM6DSOX_FALSE_STEP_REJ;
8352 break;
8353
8354 case LSM6DSOX_FALSE_STEP_REJ_ADV_MODE:
8355 *val = LSM6DSOX_FALSE_STEP_REJ_ADV_MODE;
8356 break;
8357
8358 default:
8359 *val = LSM6DSOX_PEDO_BASE_MODE;
8360 break;
8361 }
8362
8363 return ret;
8364 }
8365
8366 /**
8367 * @brief Interrupt status bit for step detection.[get]
8368 *
8369 * @param ctx read / write interface definitions
8370 * @param val change the values of is_step_det in reg EMB_FUNC_STATUS
8371 * @retval interface status (MANDATORY: return 0 -> no Error)
8372 *
8373 */
lsm6dsox_pedo_step_detect_get(const stmdev_ctx_t * ctx,uint8_t * val)8374 int32_t lsm6dsox_pedo_step_detect_get(const stmdev_ctx_t *ctx, uint8_t *val)
8375 {
8376 lsm6dsox_emb_func_status_t reg;
8377 int32_t ret;
8378
8379 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
8380
8381 if (ret == 0)
8382 {
8383 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS,
8384 (uint8_t *)®, 1);
8385 }
8386
8387 if (ret == 0)
8388 {
8389 *val = reg.is_step_det;
8390 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
8391 }
8392
8393 return ret;
8394 }
8395
8396 /**
8397 * @brief Pedometer debounce configuration register (r/w).[set]
8398 *
8399 * @param ctx read / write interface definitions
8400 * @param buff buffer that contains data to write
8401 * @retval interface status (MANDATORY: return 0 -> no Error)
8402 *
8403 */
lsm6dsox_pedo_debounce_steps_set(const stmdev_ctx_t * ctx,uint8_t * buff)8404 int32_t lsm6dsox_pedo_debounce_steps_set(const stmdev_ctx_t *ctx,
8405 uint8_t *buff)
8406 {
8407 int32_t ret;
8408
8409 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_DEB_STEPS_CONF,
8410 buff);
8411
8412 return ret;
8413 }
8414
8415 /**
8416 * @brief Pedometer debounce configuration register (r/w).[get]
8417 *
8418 * @param ctx read / write interface definitions
8419 * @param buff buffer that stores data read
8420 * @retval interface status (MANDATORY: return 0 -> no Error)
8421 *
8422 */
lsm6dsox_pedo_debounce_steps_get(const stmdev_ctx_t * ctx,uint8_t * buff)8423 int32_t lsm6dsox_pedo_debounce_steps_get(const stmdev_ctx_t *ctx,
8424 uint8_t *buff)
8425 {
8426 int32_t ret;
8427
8428 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_DEB_STEPS_CONF,
8429 buff);
8430
8431 return ret;
8432 }
8433
8434 /**
8435 * @brief Time period register for step detection on delta time (r/w).[set]
8436 *
8437 * @param ctx read / write interface definitions
8438 * @param buff buffer that contains data to write
8439 * @retval interface status (MANDATORY: return 0 -> no Error)
8440 *
8441 */
lsm6dsox_pedo_steps_period_set(const stmdev_ctx_t * ctx,uint16_t val)8442 int32_t lsm6dsox_pedo_steps_period_set(const stmdev_ctx_t *ctx,
8443 uint16_t val)
8444 {
8445 uint8_t buff[2];
8446 int32_t ret;
8447
8448 buff[1] = (uint8_t)(val / 256U);
8449 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8450 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_L,
8451 &buff[0]);
8452
8453 if (ret == 0)
8454 {
8455 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_H,
8456 &buff[1]);
8457 }
8458
8459 return ret;
8460 }
8461
8462 /**
8463 * @brief Time period register for step detection on delta time (r/w).[get]
8464 *
8465 * @param ctx read / write interface definitions
8466 * @param buff buffer that stores data read
8467 * @retval interface status (MANDATORY: return 0 -> no Error)
8468 *
8469 */
lsm6dsox_pedo_steps_period_get(const stmdev_ctx_t * ctx,uint16_t * val)8470 int32_t lsm6dsox_pedo_steps_period_get(const stmdev_ctx_t *ctx,
8471 uint16_t *val)
8472 {
8473 uint8_t buff[2];
8474 int32_t ret;
8475
8476 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_L,
8477 &buff[0]);
8478
8479 if (ret == 0)
8480 {
8481 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_SC_DELTAT_H,
8482 &buff[1]);
8483 *val = buff[1];
8484 *val = (*val * 256U) + buff[0];
8485 }
8486
8487 return ret;
8488 }
8489
8490 /**
8491 * @brief Set when user wants to generate interrupt on count overflow
8492 * event/every step.[set]
8493 *
8494 * @param ctx read / write interface definitions
8495 * @param val change the values of carry_count_en in reg PEDO_CMD_REG
8496 * @retval interface status (MANDATORY: return 0 -> no Error)
8497 *
8498 */
lsm6dsox_pedo_int_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_carry_count_en_t val)8499 int32_t lsm6dsox_pedo_int_mode_set(const stmdev_ctx_t *ctx,
8500 lsm6dsox_carry_count_en_t val)
8501 {
8502 lsm6dsox_pedo_cmd_reg_t reg;
8503 int32_t ret;
8504
8505 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
8506 (uint8_t *)®);
8507
8508 if (ret == 0)
8509 {
8510 reg.carry_count_en = (uint8_t)val;
8511 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
8512 (uint8_t *)®);
8513 }
8514
8515 return ret;
8516 }
8517
8518 /**
8519 * @brief Set when user wants to generate interrupt on count overflow
8520 * event/every step.[get]
8521 *
8522 * @param ctx read / write interface definitions
8523 * @param val Get the values of carry_count_en in reg PEDO_CMD_REG
8524 * @retval interface status (MANDATORY: return 0 -> no Error)
8525 *
8526 */
lsm6dsox_pedo_int_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_carry_count_en_t * val)8527 int32_t lsm6dsox_pedo_int_mode_get(const stmdev_ctx_t *ctx,
8528 lsm6dsox_carry_count_en_t *val)
8529 {
8530 lsm6dsox_pedo_cmd_reg_t reg;
8531 int32_t ret;
8532
8533 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_PEDO_CMD_REG,
8534 (uint8_t *)®);
8535
8536 switch (reg.carry_count_en)
8537 {
8538 case LSM6DSOX_EVERY_STEP:
8539 *val = LSM6DSOX_EVERY_STEP;
8540 break;
8541
8542 case LSM6DSOX_COUNT_OVERFLOW:
8543 *val = LSM6DSOX_COUNT_OVERFLOW;
8544 break;
8545
8546 default:
8547 *val = LSM6DSOX_EVERY_STEP;
8548 break;
8549 }
8550
8551 return ret;
8552 }
8553
8554 /**
8555 * @}
8556 *
8557 */
8558
8559 /**
8560 * @defgroup LSM6DSOX_significant_motion
8561 * @brief This section groups all the functions that manage the
8562 * significant motion detection.
8563 * @{
8564 *
8565 */
8566
8567 /**
8568 * @brief Interrupt status bit for significant motion detection.[get]
8569 *
8570 * @param ctx read / write interface definitions
8571 * @param val change the values of is_sigmot in reg EMB_FUNC_STATUS
8572 * @retval interface status (MANDATORY: return 0 -> no Error)
8573 *
8574 */
lsm6dsox_motion_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)8575 int32_t lsm6dsox_motion_flag_data_ready_get(const stmdev_ctx_t *ctx,
8576 uint8_t *val)
8577 {
8578 lsm6dsox_emb_func_status_t reg;
8579 int32_t ret;
8580
8581 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
8582
8583 if (ret == 0)
8584 {
8585 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS,
8586 (uint8_t *)®, 1);
8587 }
8588
8589 if (ret == 0)
8590 {
8591 *val = reg.is_sigmot;
8592 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
8593 }
8594
8595 return ret;
8596 }
8597
8598 /**
8599 * @}
8600 *
8601 */
8602
8603 /**
8604 * @defgroup LSM6DSOX_tilt_detection
8605 * @brief This section groups all the functions that manage the tilt
8606 * event detection.
8607 * @{
8608 *
8609 */
8610
8611 /**
8612 * @brief Interrupt status bit for tilt detection.[get]
8613 *
8614 * @param ctx read / write interface definitions
8615 * @param val change the values of is_tilt in reg EMB_FUNC_STATUS
8616 * @retval interface status (MANDATORY: return 0 -> no Error)
8617 *
8618 */
lsm6dsox_tilt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)8619 int32_t lsm6dsox_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx,
8620 uint8_t *val)
8621 {
8622 lsm6dsox_emb_func_status_t reg;
8623 int32_t ret;
8624
8625 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
8626
8627 if (ret == 0)
8628 {
8629 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS,
8630 (uint8_t *)®, 1);
8631 }
8632
8633 if (ret == 0)
8634 {
8635 *val = reg.is_tilt;
8636 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
8637 }
8638
8639 return ret;
8640 }
8641
8642 /**
8643 * @}
8644 *
8645 */
8646
8647 /**
8648 * @defgroup LSM6DSOX_ magnetometer_sensor
8649 * @brief This section groups all the functions that manage additional
8650 * magnetometer sensor.
8651 * @{
8652 *
8653 */
8654
8655 /**
8656 * @brief External magnetometer sensitivity value register for
8657 * Sensor hub.[set]
8658 *
8659 * @param ctx read / write interface definitions
8660 * @param buff buffer that contains data to write
8661 * @retval interface status (MANDATORY: return 0 -> no Error)
8662 *
8663 */
lsm6dsox_sh_mag_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)8664 int32_t lsm6dsox_sh_mag_sensitivity_set(const stmdev_ctx_t *ctx,
8665 uint16_t val)
8666 {
8667 uint8_t buff[2];
8668 int32_t ret;
8669
8670 buff[1] = (uint8_t)(val / 256U);
8671 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8672 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_L,
8673 &buff[0]);
8674
8675 if (ret == 0)
8676 {
8677 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_H,
8678 &buff[1]);
8679 }
8680
8681 return ret;
8682 }
8683
8684 /**
8685 * @brief External magnetometer sensitivity value register for
8686 * Sensor hub.[get]
8687 *
8688 * @param ctx read / write interface definitions
8689 * @param buff buffer that stores data read
8690 * @retval interface status (MANDATORY: return 0 -> no Error)
8691 *
8692 */
lsm6dsox_sh_mag_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)8693 int32_t lsm6dsox_sh_mag_sensitivity_get(const stmdev_ctx_t *ctx,
8694 uint16_t *val)
8695 {
8696 uint8_t buff[2];
8697 int32_t ret;
8698
8699 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_L,
8700 &buff[0]);
8701
8702 if (ret == 0)
8703 {
8704 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SENSITIVITY_H,
8705 &buff[1]);
8706 *val = buff[1];
8707 *val = (*val * 256U) + buff[0];
8708 }
8709
8710 return ret;
8711 }
8712
8713 /**
8714 * @brief External magnetometer sensitivity value register for
8715 * Machine Learning Core.[set]
8716 *
8717 * @param ctx read / write interface definitions
8718 * @param buff buffer that contains data to write
8719 * @retval interface status (MANDATORY: return 0 -> no Error)
8720 *
8721 */
lsm6dsox_mlc_mag_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)8722 int32_t lsm6dsox_mlc_mag_sensitivity_set(const stmdev_ctx_t *ctx,
8723 uint16_t val)
8724 {
8725 uint8_t buff[2];
8726 int32_t ret;
8727
8728 buff[1] = (uint8_t)(val / 256U);
8729 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8730 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_L,
8731 &buff[0]);
8732
8733 if (ret == 0)
8734 {
8735 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_H,
8736 &buff[1]);
8737 }
8738
8739 return ret;
8740 }
8741
8742 /**
8743 * @brief External magnetometer sensitivity value register for
8744 * Machine Learning Core.[get]
8745 *
8746 * @param ctx read / write interface definitions
8747 * @param buff buffer that stores data read
8748 * @retval interface status (MANDATORY: return 0 -> no Error)
8749 *
8750 */
lsm6dsox_mlc_mag_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)8751 int32_t lsm6dsox_mlc_mag_sensitivity_get(const stmdev_ctx_t *ctx,
8752 uint16_t *val)
8753 {
8754 uint8_t buff[2];
8755 int32_t ret;
8756
8757 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_L,
8758 &buff[0]);
8759
8760 if (ret == 0)
8761 {
8762 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MLC_MAG_SENSITIVITY_H,
8763 &buff[1]);
8764 *val = buff[1];
8765 *val = (*val * 256U) + buff[0];
8766 }
8767
8768 return ret;
8769 }
8770
8771
8772 /**
8773 * @brief Offset for hard-iron compensation register (r/w).[set]
8774 *
8775 * @param ctx read / write interface definitions
8776 * @param buff buffer that contains data to write
8777 * @retval interface status (MANDATORY: return 0 -> no Error)
8778 *
8779 */
lsm6dsox_mag_offset_set(const stmdev_ctx_t * ctx,int16_t * val)8780 int32_t lsm6dsox_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val)
8781 {
8782 uint8_t buff[6];
8783 int32_t ret;
8784
8785 uint8_t i;
8786 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
8787 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
8788 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
8789 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
8790 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
8791 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
8792 i = 0x00U;
8793 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFX_L,
8794 &buff[i]);
8795
8796 if (ret == 0)
8797 {
8798 i++;
8799 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFX_H,
8800 &buff[i]);
8801 }
8802
8803 if (ret == 0)
8804 {
8805 i++;
8806 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFY_L,
8807 &buff[i]);
8808 }
8809
8810 if (ret == 0)
8811 {
8812 i++;
8813 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFY_H,
8814 &buff[i]);
8815 }
8816
8817 if (ret == 0)
8818 {
8819 i++;
8820 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFZ_L,
8821 &buff[i]);
8822 }
8823
8824 if (ret == 0)
8825 {
8826 i++;
8827 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_OFFZ_H,
8828 &buff[i]);
8829 }
8830
8831 return ret;
8832 }
8833
8834 /**
8835 * @brief Offset for hard-iron compensation register (r/w).[get]
8836 *
8837 * @param ctx read / write interface definitions
8838 * @param buff buffer that stores data read
8839 * @retval interface status (MANDATORY: return 0 -> no Error)
8840 *
8841 */
lsm6dsox_mag_offset_get(const stmdev_ctx_t * ctx,int16_t * val)8842 int32_t lsm6dsox_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
8843 {
8844 uint8_t buff[6];
8845 int32_t ret;
8846
8847 uint8_t i;
8848 i = 0x00U;
8849 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFX_L,
8850 &buff[i]);
8851
8852 if (ret == 0)
8853 {
8854 i++;
8855 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFX_H,
8856 &buff[i]);
8857 }
8858
8859 if (ret == 0)
8860 {
8861 i++;
8862 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFY_L,
8863 &buff[i]);
8864 }
8865
8866 if (ret == 0)
8867 {
8868 i++;
8869 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFY_H,
8870 &buff[i]);
8871 }
8872
8873 if (ret == 0)
8874 {
8875 i++;
8876 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFZ_L,
8877 &buff[i]);
8878 }
8879
8880 if (ret == 0)
8881 {
8882 i++;
8883 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_OFFZ_H,
8884 &buff[i]);
8885 }
8886
8887 val[0] = (int16_t)buff[1];
8888 val[0] = (val[0] * 256) + (int16_t)buff[0];
8889 val[1] = (int16_t)buff[3];
8890 val[1] = (val[1] * 256) + (int16_t)buff[2];
8891 val[2] = (int16_t)buff[5];
8892 val[2] = (val[2] * 256) + (int16_t)buff[4];
8893
8894 return ret;
8895 }
8896
8897 /**
8898 * @brief Soft-iron (3x3 symmetric) matrix correction
8899 * register (r/w). The value is expressed as
8900 * half-precision floating-point format:
8901 * SEEEEEFFFFFFFFFF
8902 * S: 1 sign bit;
8903 * E: 5 exponent bits;
8904 * F: 10 fraction bits).[set]
8905 *
8906 * @param ctx read / write interface definitions
8907 * @param buff buffer that contains data to write
8908 * @retval interface status (MANDATORY: return 0 -> no Error)
8909 *
8910 */
lsm6dsox_mag_soft_iron_set(const stmdev_ctx_t * ctx,uint16_t * val)8911 int32_t lsm6dsox_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint16_t *val)
8912 {
8913 uint8_t buff[12];
8914 uint8_t index;
8915 int32_t ret;
8916
8917 buff[1] = (uint8_t)(val[0] / 256U);
8918 buff[0] = (uint8_t)(val[0] - (buff[1] * 256U));
8919 buff[3] = (uint8_t)(val[1] / 256U);
8920 buff[2] = (uint8_t)(val[1] - (buff[3] * 256U));
8921 buff[5] = (uint8_t)(val[2] / 256U);
8922 buff[4] = (uint8_t)(val[2] - (buff[5] * 256U));
8923 buff[7] = (uint8_t)(val[3] / 256U);
8924 buff[6] = (uint8_t)(val[3] - (buff[1] * 256U));
8925 buff[9] = (uint8_t)(val[4] / 256U);
8926 buff[8] = (uint8_t)(val[4] - (buff[3] * 256U));
8927 buff[11] = (uint8_t)(val[5] / 256U);
8928 buff[10] = (uint8_t)(val[5] - (buff[5] * 256U));
8929 index = 0x00U;
8930 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XX_L,
8931 &buff[index]);
8932
8933 if (ret == 0)
8934 {
8935 index++;
8936 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XX_H,
8937 &buff[index]);
8938 }
8939
8940 if (ret == 0)
8941 {
8942 index++;
8943 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XY_L,
8944 &buff[index]);
8945 }
8946
8947 if (ret == 0)
8948 {
8949 index++;
8950 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XY_H,
8951 &buff[index]);
8952 }
8953
8954 if (ret == 0)
8955 {
8956 index++;
8957 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XZ_L,
8958 &buff[index]);
8959 }
8960
8961 if (ret == 0)
8962 {
8963 index++;
8964 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_XZ_H,
8965 &buff[index]);
8966 }
8967
8968 if (ret == 0)
8969 {
8970 index++;
8971 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YY_L,
8972 &buff[index]);
8973 }
8974
8975 if (ret == 0)
8976 {
8977 index++;
8978 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YY_H,
8979 &buff[index]);
8980 }
8981
8982 if (ret == 0)
8983 {
8984 index++;
8985 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YZ_L,
8986 &buff[index]);
8987 }
8988
8989 if (ret == 0)
8990 {
8991 index++;
8992 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_YZ_H,
8993 &buff[index]);
8994 }
8995
8996 if (ret == 0)
8997 {
8998 index++;
8999 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_ZZ_L,
9000 &buff[index]);
9001 }
9002
9003 if (ret == 0)
9004 {
9005 index++;
9006 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_SI_ZZ_H,
9007 &buff[index]);
9008 }
9009
9010 return ret;
9011 }
9012
9013 /**
9014 * @brief Soft-iron (3x3 symmetric) matrix
9015 * correction register (r/w).
9016 * The value is expressed as half-precision
9017 * floating-point format:
9018 * SEEEEEFFFFFFFFFF
9019 * S: 1 sign bit;
9020 * E: 5 exponent bits;
9021 * F: 10 fraction bits.[get]
9022 *
9023 * @param ctx read / write interface definitions
9024 * @param buff buffer that stores data read
9025 * @retval interface status (MANDATORY: return 0 -> no Error)
9026 *
9027 */
lsm6dsox_mag_soft_iron_get(const stmdev_ctx_t * ctx,uint16_t * val)9028 int32_t lsm6dsox_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint16_t *val)
9029 {
9030 uint8_t buff[12];
9031 uint8_t index;
9032 int32_t ret;
9033
9034 index = 0x00U;
9035 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XX_L,
9036 &buff[index]);
9037
9038 if (ret == 0)
9039 {
9040 index++;
9041 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XX_H,
9042 &buff[index]);
9043 }
9044
9045 if (ret == 0)
9046 {
9047 index++;
9048 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XY_L,
9049 &buff[index]);
9050 }
9051
9052 if (ret == 0)
9053 {
9054 index++;
9055 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XY_H,
9056 &buff[index]);
9057 }
9058
9059 if (ret == 0)
9060 {
9061 index++;
9062 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XZ_L,
9063 &buff[index]);
9064 }
9065
9066 if (ret == 0)
9067 {
9068 index++;
9069 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_XZ_H,
9070 &buff[index]);
9071 }
9072
9073 if (ret == 0)
9074 {
9075 index++;
9076 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YY_L,
9077 &buff[index]);
9078 }
9079
9080 if (ret == 0)
9081 {
9082 index++;
9083 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YY_H,
9084 &buff[index]);
9085 }
9086
9087 if (ret == 0)
9088 {
9089 index++;
9090 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YZ_L,
9091 &buff[index]);
9092 }
9093
9094 if (ret == 0)
9095 {
9096 index++;
9097 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_YZ_H,
9098 &buff[index]);
9099 }
9100
9101 if (ret == 0)
9102 {
9103 index++;
9104 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_ZZ_L,
9105 &buff[index]);
9106 }
9107
9108 if (ret == 0)
9109 {
9110 index++;
9111 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_SI_ZZ_H,
9112 &buff[index]);
9113 }
9114
9115 val[0] = buff[1];
9116 val[0] = (val[0] * 256U) + buff[0];
9117 val[1] = buff[3];
9118 val[1] = (val[1] * 256U) + buff[2];
9119 val[2] = buff[5];
9120 val[2] = (val[2] * 256U) + buff[4];
9121 val[3] = buff[7];
9122 val[3] = (val[3] * 256U) + buff[6];
9123 val[4] = buff[9];
9124 val[4] = (val[4] * 256U) + buff[8];
9125 val[5] = buff[11];
9126 val[6] = (val[5] * 256U) + buff[10];
9127
9128 return ret;
9129 }
9130
9131 /**
9132 * @brief Magnetometer Z-axis coordinates
9133 * rotation (to be aligned to
9134 * accelerometer/gyroscope axes
9135 * orientation).[set]
9136 *
9137 * @param ctx read / write interface definitions
9138 * @param val change the values of mag_z_axis in reg MAG_CFG_A
9139 * @retval interface status (MANDATORY: return 0 -> no Error)
9140 *
9141 */
lsm6dsox_mag_z_orient_set(const stmdev_ctx_t * ctx,lsm6dsox_mag_z_axis_t val)9142 int32_t lsm6dsox_mag_z_orient_set(const stmdev_ctx_t *ctx,
9143 lsm6dsox_mag_z_axis_t val)
9144 {
9145 lsm6dsox_mag_cfg_a_t reg;
9146 int32_t ret;
9147
9148 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A,
9149 (uint8_t *)®);
9150
9151 if (ret == 0)
9152 {
9153 reg.mag_z_axis = (uint8_t) val;
9154 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_A,
9155 (uint8_t *)®);
9156 }
9157
9158 return ret;
9159 }
9160
9161 /**
9162 * @brief Magnetometer Z-axis coordinates
9163 * rotation (to be aligned to
9164 * accelerometer/gyroscope axes
9165 * orientation).[get]
9166 *
9167 * @param ctx read / write interface definitions
9168 * @param val Get the values of mag_z_axis in reg MAG_CFG_A
9169 * @retval interface status (MANDATORY: return 0 -> no Error)
9170 *
9171 */
lsm6dsox_mag_z_orient_get(const stmdev_ctx_t * ctx,lsm6dsox_mag_z_axis_t * val)9172 int32_t lsm6dsox_mag_z_orient_get(const stmdev_ctx_t *ctx,
9173 lsm6dsox_mag_z_axis_t *val)
9174 {
9175 lsm6dsox_mag_cfg_a_t reg;
9176 int32_t ret;
9177
9178 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A,
9179 (uint8_t *)®);
9180
9181 switch (reg.mag_z_axis)
9182 {
9183 case LSM6DSOX_Z_EQ_Y:
9184 *val = LSM6DSOX_Z_EQ_Y;
9185 break;
9186
9187 case LSM6DSOX_Z_EQ_MIN_Y:
9188 *val = LSM6DSOX_Z_EQ_MIN_Y;
9189 break;
9190
9191 case LSM6DSOX_Z_EQ_X:
9192 *val = LSM6DSOX_Z_EQ_X;
9193 break;
9194
9195 case LSM6DSOX_Z_EQ_MIN_X:
9196 *val = LSM6DSOX_Z_EQ_MIN_X;
9197 break;
9198
9199 case LSM6DSOX_Z_EQ_MIN_Z:
9200 *val = LSM6DSOX_Z_EQ_MIN_Z;
9201 break;
9202
9203 case LSM6DSOX_Z_EQ_Z:
9204 *val = LSM6DSOX_Z_EQ_Z;
9205 break;
9206
9207 default:
9208 *val = LSM6DSOX_Z_EQ_Y;
9209 break;
9210 }
9211
9212 return ret;
9213 }
9214
9215 /**
9216 * @brief Magnetometer Y-axis coordinates
9217 * rotation (to be aligned to
9218 * accelerometer/gyroscope axes
9219 * orientation).[set]
9220 *
9221 * @param ctx read / write interface definitions
9222 * @param val change the values of mag_y_axis in reg MAG_CFG_A
9223 * @retval interface status (MANDATORY: return 0 -> no Error)
9224 *
9225 */
lsm6dsox_mag_y_orient_set(const stmdev_ctx_t * ctx,lsm6dsox_mag_y_axis_t val)9226 int32_t lsm6dsox_mag_y_orient_set(const stmdev_ctx_t *ctx,
9227 lsm6dsox_mag_y_axis_t val)
9228 {
9229 lsm6dsox_mag_cfg_a_t reg;
9230 int32_t ret;
9231
9232 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A,
9233 (uint8_t *)®);
9234
9235 if (ret == 0)
9236 {
9237 reg.mag_y_axis = (uint8_t)val;
9238 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_A,
9239 (uint8_t *) ®);
9240 }
9241
9242 return ret;
9243 }
9244
9245 /**
9246 * @brief Magnetometer Y-axis coordinates
9247 * rotation (to be aligned to
9248 * accelerometer/gyroscope axes
9249 * orientation).[get]
9250 *
9251 * @param ctx read / write interface definitions
9252 * @param val Get the values of mag_y_axis in reg MAG_CFG_A
9253 * @retval interface status (MANDATORY: return 0 -> no Error)
9254 *
9255 */
lsm6dsox_mag_y_orient_get(const stmdev_ctx_t * ctx,lsm6dsox_mag_y_axis_t * val)9256 int32_t lsm6dsox_mag_y_orient_get(const stmdev_ctx_t *ctx,
9257 lsm6dsox_mag_y_axis_t *val)
9258 {
9259 lsm6dsox_mag_cfg_a_t reg;
9260 int32_t ret;
9261
9262 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_A,
9263 (uint8_t *)®);
9264
9265 switch (reg.mag_y_axis)
9266 {
9267 case LSM6DSOX_Y_EQ_Y:
9268 *val = LSM6DSOX_Y_EQ_Y;
9269 break;
9270
9271 case LSM6DSOX_Y_EQ_MIN_Y:
9272 *val = LSM6DSOX_Y_EQ_MIN_Y;
9273 break;
9274
9275 case LSM6DSOX_Y_EQ_X:
9276 *val = LSM6DSOX_Y_EQ_X;
9277 break;
9278
9279 case LSM6DSOX_Y_EQ_MIN_X:
9280 *val = LSM6DSOX_Y_EQ_MIN_X;
9281 break;
9282
9283 case LSM6DSOX_Y_EQ_MIN_Z:
9284 *val = LSM6DSOX_Y_EQ_MIN_Z;
9285 break;
9286
9287 case LSM6DSOX_Y_EQ_Z:
9288 *val = LSM6DSOX_Y_EQ_Z;
9289 break;
9290
9291 default:
9292 *val = LSM6DSOX_Y_EQ_Y;
9293 break;
9294 }
9295
9296 return ret;
9297 }
9298
9299 /**
9300 * @brief Magnetometer X-axis coordinates
9301 * rotation (to be aligned to
9302 * accelerometer/gyroscope axes
9303 * orientation).[set]
9304 *
9305 * @param ctx read / write interface definitions
9306 * @param val change the values of mag_x_axis in reg MAG_CFG_B
9307 * @retval interface status (MANDATORY: return 0 -> no Error)
9308 *
9309 */
lsm6dsox_mag_x_orient_set(const stmdev_ctx_t * ctx,lsm6dsox_mag_x_axis_t val)9310 int32_t lsm6dsox_mag_x_orient_set(const stmdev_ctx_t *ctx,
9311 lsm6dsox_mag_x_axis_t val)
9312 {
9313 lsm6dsox_mag_cfg_b_t reg;
9314 int32_t ret;
9315
9316 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_B,
9317 (uint8_t *)®);
9318
9319 if (ret == 0)
9320 {
9321 reg.mag_x_axis = (uint8_t)val;
9322 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_MAG_CFG_B,
9323 (uint8_t *)®);
9324 }
9325
9326 return ret;
9327 }
9328
9329 /**
9330 * @brief Magnetometer X-axis coordinates
9331 * rotation (to be aligned to
9332 * accelerometer/gyroscope axes
9333 * orientation).[get]
9334 *
9335 * @param ctx read / write interface definitions
9336 * @param val Get the values of mag_x_axis in reg MAG_CFG_B
9337 * @retval interface status (MANDATORY: return 0 -> no Error)
9338 *
9339 */
lsm6dsox_mag_x_orient_get(const stmdev_ctx_t * ctx,lsm6dsox_mag_x_axis_t * val)9340 int32_t lsm6dsox_mag_x_orient_get(const stmdev_ctx_t *ctx,
9341 lsm6dsox_mag_x_axis_t *val)
9342 {
9343 lsm6dsox_mag_cfg_b_t reg;
9344 int32_t ret;
9345
9346 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_MAG_CFG_B,
9347 (uint8_t *)®);
9348
9349 switch (reg.mag_x_axis)
9350 {
9351 case LSM6DSOX_X_EQ_Y:
9352 *val = LSM6DSOX_X_EQ_Y;
9353 break;
9354
9355 case LSM6DSOX_X_EQ_MIN_Y:
9356 *val = LSM6DSOX_X_EQ_MIN_Y;
9357 break;
9358
9359 case LSM6DSOX_X_EQ_X:
9360 *val = LSM6DSOX_X_EQ_X;
9361 break;
9362
9363 case LSM6DSOX_X_EQ_MIN_X:
9364 *val = LSM6DSOX_X_EQ_MIN_X;
9365 break;
9366
9367 case LSM6DSOX_X_EQ_MIN_Z:
9368 *val = LSM6DSOX_X_EQ_MIN_Z;
9369 break;
9370
9371 case LSM6DSOX_X_EQ_Z:
9372 *val = LSM6DSOX_X_EQ_Z;
9373 break;
9374
9375 default:
9376 *val = LSM6DSOX_X_EQ_Y;
9377 break;
9378 }
9379
9380 return ret;
9381 }
9382
9383 /**
9384 * @}
9385 *
9386 */
9387
9388 /**
9389 * @defgroup LSM6DSOX_finite_state_machine
9390 * @brief This section groups all the functions that manage the
9391 * state_machine.
9392 * @{
9393 *
9394 */
9395
9396 /**
9397 * @brief Interrupt status bit for FSM long counter
9398 * timeout interrupt event.[get]
9399 *
9400 * @param ctx read / write interface definitions
9401 * @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS
9402 * @retval interface status (MANDATORY: return 0 -> no Error)
9403 *
9404 */
lsm6dsox_long_cnt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)9405 int32_t lsm6dsox_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx,
9406 uint8_t *val)
9407 {
9408 lsm6dsox_emb_func_status_t reg;
9409 int32_t ret;
9410
9411 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
9412
9413 if (ret == 0)
9414 {
9415 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_STATUS,
9416 (uint8_t *)®, 1);
9417 }
9418
9419 if (ret == 0)
9420 {
9421 *val = reg.is_fsm_lc;
9422 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
9423 }
9424
9425 return ret;
9426 }
9427
9428 /**
9429 * @brief Finite State Machine enable.[set]
9430 *
9431 * @param ctx read / write interface definitions
9432 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
9433 * @retval interface status (MANDATORY: return 0 -> no Error)
9434 *
9435 */
lsm6dsox_fsm_enable_set(const stmdev_ctx_t * ctx,lsm6dsox_emb_fsm_enable_t * val)9436 int32_t lsm6dsox_fsm_enable_set(const stmdev_ctx_t *ctx,
9437 lsm6dsox_emb_fsm_enable_t *val)
9438 {
9439 int32_t ret;
9440
9441 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
9442
9443 if (ret == 0)
9444 {
9445 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_ENABLE_A,
9446 (uint8_t *)&val->fsm_enable_a, 1);
9447 }
9448
9449 if (ret == 0)
9450 {
9451 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_ENABLE_B,
9452 (uint8_t *)&val->fsm_enable_b, 1);
9453 }
9454
9455 if (ret == 0)
9456 {
9457 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
9458 }
9459
9460 return ret;
9461 }
9462
9463 /**
9464 * @brief Finite State Machine enable.[get]
9465 *
9466 * @param ctx read / write interface definitions
9467 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
9468 * @retval interface status (MANDATORY: return 0 -> no Error)
9469 *
9470 */
lsm6dsox_fsm_enable_get(const stmdev_ctx_t * ctx,lsm6dsox_emb_fsm_enable_t * val)9471 int32_t lsm6dsox_fsm_enable_get(const stmdev_ctx_t *ctx,
9472 lsm6dsox_emb_fsm_enable_t *val)
9473 {
9474 int32_t ret;
9475
9476 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
9477
9478 if (ret == 0)
9479 {
9480 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_ENABLE_A, (uint8_t *) val,
9481 2);
9482 }
9483
9484 if (ret == 0)
9485 {
9486 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
9487 }
9488
9489 return ret;
9490 }
9491
9492 /**
9493 * @brief FSM long counter status register. Long counter value is an
9494 * unsigned integer value (16-bit format).[set]
9495 *
9496 * @param ctx read / write interface definitions
9497 * @param buff buffer that contains data to write
9498 * @retval interface status (MANDATORY: return 0 -> no Error)
9499 *
9500 */
lsm6dsox_long_cnt_set(const stmdev_ctx_t * ctx,uint16_t val)9501 int32_t lsm6dsox_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val)
9502 {
9503 uint8_t buff[2];
9504 int32_t ret;
9505
9506 buff[1] = (uint8_t)(val / 256U);
9507 buff[0] = (uint8_t)(val - (buff[1] * 256U));
9508 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
9509
9510 if (ret == 0)
9511 {
9512 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_L, buff, 2);
9513 }
9514
9515 if (ret == 0)
9516 {
9517 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
9518 }
9519
9520 return ret;
9521 }
9522
9523 /**
9524 * @brief FSM long counter status register. Long counter value is an
9525 * unsigned integer value (16-bit format).[get]
9526 *
9527 * @param ctx read / write interface definitions
9528 * @param buff buffer that stores data read
9529 * @retval interface status (MANDATORY: return 0 -> no Error)
9530 *
9531 */
lsm6dsox_long_cnt_get(const stmdev_ctx_t * ctx,uint16_t * val)9532 int32_t lsm6dsox_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val)
9533 {
9534 uint8_t buff[2];
9535 int32_t ret;
9536
9537 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
9538
9539 if (ret == 0)
9540 {
9541 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_L, buff, 2);
9542 *val = buff[1];
9543 *val = (*val * 256U) + buff[0];
9544 }
9545
9546 if (ret == 0)
9547 {
9548 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
9549 }
9550
9551 return ret;
9552 }
9553
9554 /**
9555 * @brief Clear FSM long counter value.[set]
9556 *
9557 * @param ctx read / write interface definitions
9558 * @param val change the values of fsm_lc_clr in
9559 * reg FSM_LONG_COUNTER_CLEAR
9560 * @retval interface status (MANDATORY: return 0 -> no Error)
9561 *
9562 */
lsm6dsox_long_clr_set(const stmdev_ctx_t * ctx,lsm6dsox_fsm_lc_clr_t val)9563 int32_t lsm6dsox_long_clr_set(const stmdev_ctx_t *ctx,
9564 lsm6dsox_fsm_lc_clr_t val)
9565 {
9566 lsm6dsox_fsm_long_counter_clear_t reg;
9567 int32_t ret;
9568
9569 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
9570
9571 if (ret == 0)
9572 {
9573 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_CLEAR,
9574 (uint8_t *)®, 1);
9575 }
9576
9577 if (ret == 0)
9578 {
9579 reg. fsm_lc_clr = (uint8_t)val;
9580 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_CLEAR,
9581 (uint8_t *)®, 1);
9582 }
9583
9584 if (ret == 0)
9585 {
9586 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
9587 }
9588
9589 return ret;
9590 }
9591
9592 /**
9593 * @brief Clear FSM long counter value.[get]
9594 *
9595 * @param ctx read / write interface definitions
9596 * @param val Get the values of fsm_lc_clr in
9597 * reg FSM_LONG_COUNTER_CLEAR
9598 * @retval interface status (MANDATORY: return 0 -> no Error)
9599 *
9600 */
lsm6dsox_long_clr_get(const stmdev_ctx_t * ctx,lsm6dsox_fsm_lc_clr_t * val)9601 int32_t lsm6dsox_long_clr_get(const stmdev_ctx_t *ctx,
9602 lsm6dsox_fsm_lc_clr_t *val)
9603 {
9604 lsm6dsox_fsm_long_counter_clear_t reg;
9605 int32_t ret;
9606
9607 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
9608
9609 if (ret == 0)
9610 {
9611 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_LONG_COUNTER_CLEAR,
9612 (uint8_t *)®, 1);
9613 }
9614
9615 if (ret == 0)
9616 {
9617 switch (reg.fsm_lc_clr)
9618 {
9619 case LSM6DSOX_LC_NORMAL:
9620 *val = LSM6DSOX_LC_NORMAL;
9621 break;
9622
9623 case LSM6DSOX_LC_CLEAR:
9624 *val = LSM6DSOX_LC_CLEAR;
9625 break;
9626
9627 case LSM6DSOX_LC_CLEAR_DONE:
9628 *val = LSM6DSOX_LC_CLEAR_DONE;
9629 break;
9630
9631 default:
9632 *val = LSM6DSOX_LC_NORMAL;
9633 break;
9634 }
9635 }
9636
9637 if (ret == 0)
9638 {
9639 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
9640 }
9641
9642 return ret;
9643 }
9644
9645 /**
9646 * @brief FSM output registers[get]
9647 *
9648 * @param ctx read / write interface definitions
9649 * @param val struct of registers from FSM_OUTS1 to FSM_OUTS16
9650 * @retval interface status (MANDATORY: return 0 -> no Error)
9651 *
9652 */
lsm6dsox_fsm_out_get(const stmdev_ctx_t * ctx,lsm6dsox_fsm_out_t * val)9653 int32_t lsm6dsox_fsm_out_get(const stmdev_ctx_t *ctx,
9654 lsm6dsox_fsm_out_t *val)
9655 {
9656 int32_t ret;
9657
9658 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
9659
9660 if (ret == 0)
9661 {
9662 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_OUTS1, (uint8_t *)val, 16);
9663 }
9664
9665 if (ret == 0)
9666 {
9667 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
9668 }
9669
9670 return ret;
9671 }
9672
9673 /**
9674 * @brief Finite State Machine ODR configuration.[set]
9675 *
9676 * @param ctx read / write interface definitions
9677 * @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
9678 * @retval interface status (MANDATORY: return 0 -> no Error)
9679 *
9680 */
lsm6dsox_fsm_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsox_fsm_odr_t val)9681 int32_t lsm6dsox_fsm_data_rate_set(const stmdev_ctx_t *ctx,
9682 lsm6dsox_fsm_odr_t val)
9683 {
9684 lsm6dsox_emb_func_odr_cfg_b_t reg;
9685 int32_t ret;
9686
9687 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
9688
9689 if (ret == 0)
9690 {
9691 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B,
9692 (uint8_t *)®, 1);
9693 }
9694
9695 if (ret == 0)
9696 {
9697 reg.not_used_01 = 3; /* set default values */
9698 reg.not_used_02 = 2; /* set default values */
9699 reg.fsm_odr = (uint8_t)val;
9700 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B,
9701 (uint8_t *)®, 1);
9702 }
9703
9704 if (ret == 0)
9705 {
9706 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
9707 }
9708
9709 return ret;
9710 }
9711
9712 /**
9713 * @brief Finite State Machine ODR configuration.[get]
9714 *
9715 * @param ctx read / write interface definitions
9716 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
9717 * @retval interface status (MANDATORY: return 0 -> no Error)
9718 *
9719 */
lsm6dsox_fsm_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsox_fsm_odr_t * val)9720 int32_t lsm6dsox_fsm_data_rate_get(const stmdev_ctx_t *ctx,
9721 lsm6dsox_fsm_odr_t *val)
9722 {
9723 lsm6dsox_emb_func_odr_cfg_b_t reg;
9724 int32_t ret;
9725
9726 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
9727
9728 if (ret == 0)
9729 {
9730 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B,
9731 (uint8_t *)®, 1);
9732 }
9733
9734 if (ret == 0)
9735 {
9736 switch (reg.fsm_odr)
9737 {
9738 case LSM6DSOX_ODR_FSM_12Hz5:
9739 *val = LSM6DSOX_ODR_FSM_12Hz5;
9740 break;
9741
9742 case LSM6DSOX_ODR_FSM_26Hz:
9743 *val = LSM6DSOX_ODR_FSM_26Hz;
9744 break;
9745
9746 case LSM6DSOX_ODR_FSM_52Hz:
9747 *val = LSM6DSOX_ODR_FSM_52Hz;
9748 break;
9749
9750 case LSM6DSOX_ODR_FSM_104Hz:
9751 *val = LSM6DSOX_ODR_FSM_104Hz;
9752 break;
9753
9754 default:
9755 *val = LSM6DSOX_ODR_FSM_12Hz5;
9756 break;
9757 }
9758
9759 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
9760 }
9761
9762 return ret;
9763 }
9764
9765 /**
9766 * @brief FSM initialization request.[set]
9767 *
9768 * @param ctx read / write interface definitions
9769 * @param val change the values of fsm_init in reg FSM_INIT
9770 * @retval interface status (MANDATORY: return 0 -> no Error)
9771 *
9772 */
lsm6dsox_fsm_init_set(const stmdev_ctx_t * ctx,uint8_t val)9773 int32_t lsm6dsox_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val)
9774 {
9775 lsm6dsox_emb_func_init_b_t reg;
9776 int32_t ret;
9777
9778 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
9779
9780 if (ret == 0)
9781 {
9782 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
9783 (uint8_t *)®, 1);
9784 }
9785
9786 if (ret == 0)
9787 {
9788 reg.fsm_init = val;
9789 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
9790 (uint8_t *)®, 1);
9791 }
9792
9793 if (ret == 0)
9794 {
9795 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
9796 }
9797
9798 return ret;
9799 }
9800
9801 /**
9802 * @brief FSM initialization request.[get]
9803 *
9804 * @param ctx read / write interface definitions
9805 * @param val change the values of fsm_init in reg FSM_INIT
9806 * @retval interface status (MANDATORY: return 0 -> no Error)
9807 *
9808 */
lsm6dsox_fsm_init_get(const stmdev_ctx_t * ctx,uint8_t * val)9809 int32_t lsm6dsox_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val)
9810 {
9811 lsm6dsox_emb_func_init_b_t reg;
9812 int32_t ret;
9813
9814 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
9815
9816 if (ret == 0)
9817 {
9818 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
9819 (uint8_t *)®, 1);
9820 }
9821
9822 if (ret == 0)
9823 {
9824 *val = reg.fsm_init;
9825 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
9826 }
9827
9828 return ret;
9829 }
9830
9831 /**
9832 * @brief FSM long counter timeout register (r/w). The long counter
9833 * timeout value is an unsigned integer value (16-bit format).
9834 * When the long counter value reached this value,
9835 * the FSM generates an interrupt.[set]
9836 *
9837 * @param ctx read / write interface definitions
9838 * @param val the value of long counter
9839 * @retval interface status (MANDATORY: return 0 -> no Error)
9840 *
9841 */
lsm6dsox_long_cnt_int_value_set(const stmdev_ctx_t * ctx,uint16_t val)9842 int32_t lsm6dsox_long_cnt_int_value_set(const stmdev_ctx_t *ctx,
9843 uint16_t val)
9844 {
9845 int32_t ret;
9846
9847 uint8_t add_l;
9848 uint8_t add_h;
9849 add_h = (uint8_t)((val & 0xFF00U) >> 8);
9850 add_l = (uint8_t)(val & 0x00FFU);
9851 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_L,
9852 &add_l);
9853
9854 if (ret == 0)
9855 {
9856 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_H,
9857 &add_h);
9858 }
9859
9860 return ret;
9861 }
9862
9863 /**
9864 * @brief FSM long counter timeout register (r/w). The long counter
9865 * timeout value is an unsigned integer value (16-bit format).
9866 * When the long counter value reached this value,
9867 * the FSM generates an interrupt.[get]
9868 *
9869 * @param ctx read / write interface definitions
9870 * @param val buffer that stores the value of long counter
9871 * @retval interface status (MANDATORY: return 0 -> no Error)
9872 *
9873 */
lsm6dsox_long_cnt_int_value_get(const stmdev_ctx_t * ctx,uint16_t * val)9874 int32_t lsm6dsox_long_cnt_int_value_get(const stmdev_ctx_t *ctx,
9875 uint16_t *val)
9876 {
9877 int32_t ret;
9878
9879 uint8_t add_l;
9880 uint8_t add_h;
9881 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_L,
9882 &add_l);
9883
9884 if (ret == 0)
9885 {
9886 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_LC_TIMEOUT_H,
9887 &add_h);
9888 *val = add_h;
9889 *val = *val << 8;
9890 *val += add_l;
9891 }
9892
9893 return ret;
9894 }
9895
9896 /**
9897 * @brief FSM number of programs register.[set]
9898 *
9899 * @param ctx read / write interface definitions
9900 * @param val value to write
9901 * @retval interface status (MANDATORY: return 0 -> no Error)
9902 *
9903 */
lsm6dsox_fsm_number_of_programs_set(const stmdev_ctx_t * ctx,uint8_t val)9904 int32_t lsm6dsox_fsm_number_of_programs_set(const stmdev_ctx_t *ctx,
9905 uint8_t val)
9906 {
9907 int32_t ret;
9908
9909 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_PROGRAMS, &val);
9910
9911 return ret;
9912 }
9913
9914 /**
9915 * @brief FSM number of programs register.[get]
9916 *
9917 * @param ctx read / write interface definitions
9918 * @param val buffer that stores data read.
9919 * @retval interface status (MANDATORY: return 0 -> no Error)
9920 *
9921 */
lsm6dsox_fsm_number_of_programs_get(const stmdev_ctx_t * ctx,uint8_t * val)9922 int32_t lsm6dsox_fsm_number_of_programs_get(const stmdev_ctx_t *ctx,
9923 uint8_t *val)
9924 {
9925 int32_t ret;
9926
9927 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_PROGRAMS, val);
9928
9929 return ret;
9930 }
9931
9932 /**
9933 * @brief FSM start address register (r/w).
9934 * First available address is 0x033C.[set]
9935 *
9936 * @param ctx read / write interface definitions
9937 * @param val the value of start address
9938 * @retval interface status (MANDATORY: return 0 -> no Error)
9939 *
9940 */
lsm6dsox_fsm_start_address_set(const stmdev_ctx_t * ctx,uint16_t val)9941 int32_t lsm6dsox_fsm_start_address_set(const stmdev_ctx_t *ctx,
9942 uint16_t val)
9943 {
9944 int32_t ret;
9945
9946 uint8_t add_l;
9947 uint8_t add_h;
9948 add_h = (uint8_t)((val & 0xFF00U) >> 8);
9949 add_l = (uint8_t)(val & 0x00FFU);
9950 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_START_ADD_L,
9951 &add_l);
9952
9953 if (ret == 0)
9954 {
9955 ret = lsm6dsox_ln_pg_write_byte(ctx, LSM6DSOX_FSM_START_ADD_H,
9956 &add_h);
9957 }
9958
9959 return ret;
9960 }
9961
9962 /**
9963 * @brief FSM start address register (r/w).
9964 * First available address is 0x033C.[get]
9965 *
9966 * @param ctx read / write interface definitions
9967 * @param val buffer the value of start address.
9968 * @retval interface status (MANDATORY: return 0 -> no Error)
9969 *
9970 */
lsm6dsox_fsm_start_address_get(const stmdev_ctx_t * ctx,uint16_t * val)9971 int32_t lsm6dsox_fsm_start_address_get(const stmdev_ctx_t *ctx,
9972 uint16_t *val)
9973 {
9974 int32_t ret;
9975
9976 uint8_t add_l;
9977 uint8_t add_h;
9978 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_START_ADD_L, &add_l);
9979
9980 if (ret == 0)
9981 {
9982 ret = lsm6dsox_ln_pg_read_byte(ctx, LSM6DSOX_FSM_START_ADD_H, &add_h);
9983 *val = add_h;
9984 *val = *val << 8;
9985 *val += add_l;
9986 }
9987
9988 return ret;
9989 }
9990
9991 /**
9992 * @}
9993 *
9994 */
9995
9996 /**
9997 * @addtogroup Machine Learning Core
9998 * @brief This section group all the functions concerning the
9999 * usage of Machine Learning Core
10000 * @{
10001 *
10002 */
10003
10004 /**
10005 * @brief Machine Learning Core status register[get]
10006 *
10007 * @param ctx read / write interface definitions
10008 * @param val register MLC_STATUS_MAINPAGE
10009 * @retval interface status (MANDATORY: return 0 -> no Error)
10010 *
10011 */
lsm6dsox_mlc_status_get(const stmdev_ctx_t * ctx,lsm6dsox_mlc_status_mainpage_t * val)10012 int32_t lsm6dsox_mlc_status_get(const stmdev_ctx_t *ctx,
10013 lsm6dsox_mlc_status_mainpage_t *val)
10014 {
10015 return lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_STATUS_MAINPAGE,
10016 (uint8_t *) val, 1);
10017 }
10018
10019 /**
10020 * @brief Machine Learning Core data rate selection.[set]
10021 *
10022 * @param ctx read / write interface definitions
10023 * @param val get the values of mlc_odr in
10024 * reg EMB_FUNC_ODR_CFG_C
10025 * @retval interface status (MANDATORY: return 0 -> no Error)
10026 *
10027 */
lsm6dsox_mlc_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsox_mlc_odr_t val)10028 int32_t lsm6dsox_mlc_data_rate_set(const stmdev_ctx_t *ctx,
10029 lsm6dsox_mlc_odr_t val)
10030 {
10031 lsm6dsox_emb_func_odr_cfg_c_t reg;
10032 int32_t ret;
10033
10034 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
10035
10036 if (ret == 0)
10037 {
10038 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_C,
10039 (uint8_t *)®, 1);
10040 }
10041
10042 if (ret == 0)
10043 {
10044 reg.mlc_odr = (uint8_t)val;
10045 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_C,
10046 (uint8_t *)®, 1);
10047 }
10048
10049 if (ret == 0)
10050 {
10051 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10052 }
10053
10054 return ret;
10055 }
10056
10057 /**
10058 * @brief Machine Learning Core data rate selection.[get]
10059 *
10060 * @param ctx read / write interface definitions
10061 * @param val change the values of mlc_odr in
10062 * reg EMB_FUNC_ODR_CFG_C
10063 * @retval interface status (MANDATORY: return 0 -> no Error)
10064 *
10065 */
lsm6dsox_mlc_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsox_mlc_odr_t * val)10066 int32_t lsm6dsox_mlc_data_rate_get(const stmdev_ctx_t *ctx,
10067 lsm6dsox_mlc_odr_t *val)
10068 {
10069 lsm6dsox_emb_func_odr_cfg_c_t reg;
10070 int32_t ret;
10071
10072 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
10073
10074 if (ret == 0)
10075 {
10076 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_C,
10077 (uint8_t *)®, 1);
10078 }
10079
10080 if (ret == 0)
10081 {
10082 switch (reg.mlc_odr)
10083 {
10084 case LSM6DSOX_ODR_PRGS_12Hz5:
10085 *val = LSM6DSOX_ODR_PRGS_12Hz5;
10086 break;
10087
10088 case LSM6DSOX_ODR_PRGS_26Hz:
10089 *val = LSM6DSOX_ODR_PRGS_26Hz;
10090 break;
10091
10092 case LSM6DSOX_ODR_PRGS_52Hz:
10093 *val = LSM6DSOX_ODR_PRGS_52Hz;
10094 break;
10095
10096 case LSM6DSOX_ODR_PRGS_104Hz:
10097 *val = LSM6DSOX_ODR_PRGS_104Hz;
10098 break;
10099
10100 default:
10101 *val = LSM6DSOX_ODR_PRGS_12Hz5;
10102 break;
10103 }
10104
10105 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10106 }
10107
10108 return ret;
10109 }
10110
10111 /**
10112 * @}
10113 *
10114 */
10115
10116 /**
10117 * @defgroup LSM6DSOX_Sensor_hub
10118 * @brief This section groups all the functions that manage the
10119 * sensor hub.
10120 * @{
10121 *
10122 */
10123
10124 /**
10125 * @brief Sensor hub output registers.[get]
10126 *
10127 * @param ctx read / write interface definitions
10128 * @param val union of registers from SENSOR_HUB_1 to SENSOR_HUB_18
10129 *
10130 */
lsm6dsox_sh_read_data_raw_get(const stmdev_ctx_t * ctx,lsm6dsox_emb_sh_read_t * val,uint8_t len)10131 int32_t lsm6dsox_sh_read_data_raw_get(const stmdev_ctx_t *ctx,
10132 lsm6dsox_emb_sh_read_t *val,
10133 uint8_t len)
10134 {
10135 int32_t ret;
10136
10137 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10138
10139 if (ret == 0)
10140 {
10141 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SENSOR_HUB_1, (uint8_t *) val,
10142 len);
10143 }
10144
10145 if (ret == 0)
10146 {
10147 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10148 }
10149
10150 return ret;
10151 }
10152
10153 /**
10154 * @brief Number of external sensors to be read by the sensor hub.[set]
10155 *
10156 * @param ctx read / write interface definitions
10157 * @param val change the values of aux_sens_on in reg MASTER_CONFIG
10158 * @retval interface status (MANDATORY: return 0 -> no Error)
10159 *
10160 */
lsm6dsox_sh_slave_connected_set(const stmdev_ctx_t * ctx,lsm6dsox_aux_sens_on_t val)10161 int32_t lsm6dsox_sh_slave_connected_set(const stmdev_ctx_t *ctx,
10162 lsm6dsox_aux_sens_on_t val)
10163 {
10164 lsm6dsox_master_config_t reg;
10165 int32_t ret;
10166
10167 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10168
10169 if (ret == 0)
10170 {
10171 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10172 }
10173
10174 if (ret == 0)
10175 {
10176 reg.aux_sens_on = (uint8_t)val;
10177 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10178 }
10179
10180 if (ret == 0)
10181 {
10182 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10183 }
10184
10185 return ret;
10186 }
10187
10188 /**
10189 * @brief Number of external sensors to be read by the sensor hub.[get]
10190 *
10191 * @param ctx read / write interface definitions
10192 * @param val Get the values of aux_sens_on in reg MASTER_CONFIG
10193 * @retval interface status (MANDATORY: return 0 -> no Error)
10194 *
10195 */
lsm6dsox_sh_slave_connected_get(const stmdev_ctx_t * ctx,lsm6dsox_aux_sens_on_t * val)10196 int32_t lsm6dsox_sh_slave_connected_get(const stmdev_ctx_t *ctx,
10197 lsm6dsox_aux_sens_on_t *val)
10198 {
10199 lsm6dsox_master_config_t reg;
10200 int32_t ret;
10201
10202 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10203
10204 if (ret == 0)
10205 {
10206 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10207 }
10208
10209 if (ret == 0)
10210 {
10211 switch (reg.aux_sens_on)
10212 {
10213 case LSM6DSOX_SLV_0:
10214 *val = LSM6DSOX_SLV_0;
10215 break;
10216
10217 case LSM6DSOX_SLV_0_1:
10218 *val = LSM6DSOX_SLV_0_1;
10219 break;
10220
10221 case LSM6DSOX_SLV_0_1_2:
10222 *val = LSM6DSOX_SLV_0_1_2;
10223 break;
10224
10225 case LSM6DSOX_SLV_0_1_2_3:
10226 *val = LSM6DSOX_SLV_0_1_2_3;
10227 break;
10228
10229 default:
10230 *val = LSM6DSOX_SLV_0;
10231 break;
10232 }
10233
10234 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10235 }
10236
10237 return ret;
10238 }
10239
10240 /**
10241 * @brief Sensor hub I2C master enable.[set]
10242 *
10243 * @param ctx read / write interface definitions
10244 * @param val change the values of master_on in reg MASTER_CONFIG
10245 * @retval interface status (MANDATORY: return 0 -> no Error)
10246 *
10247 */
lsm6dsox_sh_master_set(const stmdev_ctx_t * ctx,uint8_t val)10248 int32_t lsm6dsox_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val)
10249 {
10250 lsm6dsox_master_config_t reg;
10251 int32_t ret;
10252
10253 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10254
10255 if (ret == 0)
10256 {
10257 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10258 }
10259
10260 if (ret == 0)
10261 {
10262 reg.master_on = val;
10263 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10264 }
10265
10266 if (ret == 0)
10267 {
10268 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10269 }
10270
10271 return ret;
10272 }
10273
10274 /**
10275 * @brief Sensor hub I2C master enable.[get]
10276 *
10277 * @param ctx read / write interface definitions
10278 * @param val change the values of master_on in reg MASTER_CONFIG
10279 * @retval interface status (MANDATORY: return 0 -> no Error)
10280 *
10281 */
lsm6dsox_sh_master_get(const stmdev_ctx_t * ctx,uint8_t * val)10282 int32_t lsm6dsox_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val)
10283 {
10284 lsm6dsox_master_config_t reg;
10285 int32_t ret;
10286
10287 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10288
10289 if (ret == 0)
10290 {
10291 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10292 }
10293
10294 if (ret == 0)
10295 {
10296 *val = reg.master_on;
10297 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10298 }
10299
10300 return ret;
10301 }
10302
10303 /**
10304 * @brief Master I2C pull-up enable.[set]
10305 *
10306 * @param ctx read / write interface definitions
10307 * @param val change the values of shub_pu_en in reg MASTER_CONFIG
10308 * @retval interface status (MANDATORY: return 0 -> no Error)
10309 *
10310 */
lsm6dsox_sh_pin_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_shub_pu_en_t val)10311 int32_t lsm6dsox_sh_pin_mode_set(const stmdev_ctx_t *ctx,
10312 lsm6dsox_shub_pu_en_t val)
10313 {
10314 lsm6dsox_master_config_t reg;
10315 int32_t ret;
10316
10317 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10318
10319 if (ret == 0)
10320 {
10321 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10322 }
10323
10324 if (ret == 0)
10325 {
10326 reg.shub_pu_en = (uint8_t)val;
10327 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10328 }
10329
10330 if (ret == 0)
10331 {
10332 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10333 }
10334
10335 return ret;
10336 }
10337
10338 /**
10339 * @brief Master I2C pull-up enable.[get]
10340 *
10341 * @param ctx read / write interface definitions
10342 * @param val Get the values of shub_pu_en in reg MASTER_CONFIG
10343 * @retval interface status (MANDATORY: return 0 -> no Error)
10344 *
10345 */
lsm6dsox_sh_pin_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_shub_pu_en_t * val)10346 int32_t lsm6dsox_sh_pin_mode_get(const stmdev_ctx_t *ctx,
10347 lsm6dsox_shub_pu_en_t *val)
10348 {
10349 lsm6dsox_master_config_t reg;
10350 int32_t ret;
10351
10352 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10353
10354 if (ret == 0)
10355 {
10356 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10357 }
10358
10359 if (ret == 0)
10360 {
10361 switch (reg.shub_pu_en)
10362 {
10363 case LSM6DSOX_EXT_PULL_UP:
10364 *val = LSM6DSOX_EXT_PULL_UP;
10365 break;
10366
10367 case LSM6DSOX_INTERNAL_PULL_UP:
10368 *val = LSM6DSOX_INTERNAL_PULL_UP;
10369 break;
10370
10371 default:
10372 *val = LSM6DSOX_EXT_PULL_UP;
10373 break;
10374 }
10375
10376 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10377 }
10378
10379 return ret;
10380 }
10381
10382 /**
10383 * @brief I2C interface pass-through.[set]
10384 *
10385 * @param ctx read / write interface definitions
10386 * @param val change the values of pass_through_mode in
10387 * reg MASTER_CONFIG
10388 * @retval interface status (MANDATORY: return 0 -> no Error)
10389 *
10390 */
lsm6dsox_sh_pass_through_set(const stmdev_ctx_t * ctx,uint8_t val)10391 int32_t lsm6dsox_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val)
10392 {
10393 lsm6dsox_master_config_t reg;
10394 int32_t ret;
10395
10396 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10397
10398 if (ret == 0)
10399 {
10400 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10401 }
10402
10403 if (ret == 0)
10404 {
10405 reg.pass_through_mode = val;
10406 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10407 }
10408
10409 if (ret == 0)
10410 {
10411 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10412 }
10413
10414 return ret;
10415 }
10416
10417 /**
10418 * @brief I2C interface pass-through.[get]
10419 *
10420 * @param ctx read / write interface definitions
10421 * @param val change the values of pass_through_mode in
10422 * reg MASTER_CONFIG
10423 * @retval interface status (MANDATORY: return 0 -> no Error)
10424 *
10425 */
lsm6dsox_sh_pass_through_get(const stmdev_ctx_t * ctx,uint8_t * val)10426 int32_t lsm6dsox_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val)
10427 {
10428 lsm6dsox_master_config_t reg;
10429 int32_t ret;
10430
10431 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10432
10433 if (ret == 0)
10434 {
10435 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10436 }
10437
10438 if (ret == 0)
10439 {
10440 *val = reg.pass_through_mode;
10441 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10442 }
10443
10444 return ret;
10445 }
10446
10447 /**
10448 * @brief Sensor hub trigger signal selection.[set]
10449 *
10450 * @param ctx read / write interface definitions
10451 * @param val change the values of start_config in reg MASTER_CONFIG
10452 * @retval interface status (MANDATORY: return 0 -> no Error)
10453 *
10454 */
lsm6dsox_sh_syncro_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_start_config_t val)10455 int32_t lsm6dsox_sh_syncro_mode_set(const stmdev_ctx_t *ctx,
10456 lsm6dsox_start_config_t val)
10457 {
10458 lsm6dsox_master_config_t reg;
10459 int32_t ret;
10460
10461 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10462
10463 if (ret == 0)
10464 {
10465 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10466 }
10467
10468 if (ret == 0)
10469 {
10470 reg.start_config = (uint8_t)val;
10471 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10472 }
10473
10474 if (ret == 0)
10475 {
10476 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10477 }
10478
10479 return ret;
10480 }
10481
10482 /**
10483 * @brief Sensor hub trigger signal selection.[get]
10484 *
10485 * @param ctx read / write interface definitions
10486 * @param val Get the values of start_config in reg MASTER_CONFIG
10487 * @retval interface status (MANDATORY: return 0 -> no Error)
10488 *
10489 */
lsm6dsox_sh_syncro_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_start_config_t * val)10490 int32_t lsm6dsox_sh_syncro_mode_get(const stmdev_ctx_t *ctx,
10491 lsm6dsox_start_config_t *val)
10492 {
10493 lsm6dsox_master_config_t reg;
10494 int32_t ret;
10495
10496 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10497
10498 if (ret == 0)
10499 {
10500 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10501 }
10502
10503 if (ret == 0)
10504 {
10505 switch (reg.start_config)
10506 {
10507 case LSM6DSOX_EXT_ON_INT2_PIN:
10508 *val = LSM6DSOX_EXT_ON_INT2_PIN;
10509 break;
10510
10511 case LSM6DSOX_XL_GY_DRDY:
10512 *val = LSM6DSOX_XL_GY_DRDY;
10513 break;
10514
10515 default:
10516 *val = LSM6DSOX_EXT_ON_INT2_PIN;
10517 break;
10518 }
10519
10520 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10521 }
10522
10523 return ret;
10524 }
10525
10526 /**
10527 * @brief Slave 0 write operation is performed only at the first
10528 * sensor hub cycle.[set]
10529 *
10530 * @param ctx read / write interface definitions
10531 * @param val change the values of write_once in reg MASTER_CONFIG
10532 * @retval interface status (MANDATORY: return 0 -> no Error)
10533 *
10534 */
lsm6dsox_sh_write_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_write_once_t val)10535 int32_t lsm6dsox_sh_write_mode_set(const stmdev_ctx_t *ctx,
10536 lsm6dsox_write_once_t val)
10537 {
10538 lsm6dsox_master_config_t reg;
10539 int32_t ret;
10540
10541 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10542
10543 if (ret == 0)
10544 {
10545 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10546 }
10547
10548 if (ret == 0)
10549 {
10550 reg.write_once = (uint8_t)val;
10551 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10552 }
10553
10554 if (ret == 0)
10555 {
10556 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10557 }
10558
10559 return ret;
10560 }
10561
10562 /**
10563 * @brief Slave 0 write operation is performed only at the first sensor
10564 * hub cycle.[get]
10565 *
10566 * @param ctx read / write interface definitions
10567 * @param val Get the values of write_once in reg MASTER_CONFIG
10568 * @retval interface status (MANDATORY: return 0 -> no Error)
10569 *
10570 */
lsm6dsox_sh_write_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_write_once_t * val)10571 int32_t lsm6dsox_sh_write_mode_get(const stmdev_ctx_t *ctx,
10572 lsm6dsox_write_once_t *val)
10573 {
10574 lsm6dsox_master_config_t reg;
10575 int32_t ret;
10576
10577 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10578
10579 if (ret == 0)
10580 {
10581 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10582 }
10583
10584 if (ret == 0)
10585 {
10586 switch (reg.write_once)
10587 {
10588 case LSM6DSOX_EACH_SH_CYCLE:
10589 *val = LSM6DSOX_EACH_SH_CYCLE;
10590 break;
10591
10592 case LSM6DSOX_ONLY_FIRST_CYCLE:
10593 *val = LSM6DSOX_ONLY_FIRST_CYCLE;
10594 break;
10595
10596 default:
10597 *val = LSM6DSOX_EACH_SH_CYCLE;
10598 break;
10599 }
10600
10601 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10602 }
10603
10604 return ret;
10605 }
10606
10607 /**
10608 * @brief Reset Master logic and output registers.[set]
10609 *
10610 * @param ctx read / write interface definitions
10611 * @retval interface status (MANDATORY: return 0 -> no Error)
10612 *
10613 */
lsm6dsox_sh_reset_set(const stmdev_ctx_t * ctx)10614 int32_t lsm6dsox_sh_reset_set(const stmdev_ctx_t *ctx)
10615 {
10616 lsm6dsox_master_config_t reg;
10617 int32_t ret;
10618
10619 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10620
10621 if (ret == 0)
10622 {
10623 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10624 }
10625
10626 if (ret == 0)
10627 {
10628 reg.rst_master_regs = PROPERTY_ENABLE;
10629 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10630 }
10631
10632 if (ret == 0)
10633 {
10634 reg.rst_master_regs = PROPERTY_DISABLE;
10635 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10636 }
10637
10638 if (ret == 0)
10639 {
10640 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10641 }
10642
10643 return ret;
10644 }
10645
10646 /**
10647 * @brief Reset Master logic and output registers.[get]
10648 *
10649 * @param ctx read / write interface definitions
10650 * @param val change the values of rst_master_regs in reg MASTER_CONFIG
10651 * @retval interface status (MANDATORY: return 0 -> no Error)
10652 *
10653 */
lsm6dsox_sh_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)10654 int32_t lsm6dsox_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
10655 {
10656 lsm6dsox_master_config_t reg;
10657 int32_t ret;
10658
10659 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10660
10661 if (ret == 0)
10662 {
10663 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MASTER_CONFIG, (uint8_t *)®, 1);
10664 }
10665
10666 if (ret == 0)
10667 {
10668 *val = reg.rst_master_regs;
10669 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10670 }
10671
10672 return ret;
10673 }
10674
10675 /**
10676 * @brief Rate at which the master communicates.[set]
10677 *
10678 * @param ctx read / write interface definitions
10679 * @param val change the values of shub_odr in reg slv1_CONFIG
10680 * @retval interface status (MANDATORY: return 0 -> no Error)
10681 *
10682 */
lsm6dsox_sh_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsox_shub_odr_t val)10683 int32_t lsm6dsox_sh_data_rate_set(const stmdev_ctx_t *ctx,
10684 lsm6dsox_shub_odr_t val)
10685 {
10686 lsm6dsox_slv0_config_t reg;
10687 int32_t ret;
10688
10689 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10690
10691 if (ret == 0)
10692 {
10693 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t *)®, 1);
10694 }
10695
10696 if (ret == 0)
10697 {
10698 reg.shub_odr = (uint8_t)val;
10699 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t *)®, 1);
10700 }
10701
10702 if (ret == 0)
10703 {
10704 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10705 }
10706
10707 return ret;
10708 }
10709
10710 /**
10711 * @brief Rate at which the master communicates.[get]
10712 *
10713 * @param ctx read / write interface definitions
10714 * @param val Get the values of shub_odr in reg slv1_CONFIG
10715 * @retval interface status (MANDATORY: return 0 -> no Error)
10716 *
10717 */
lsm6dsox_sh_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsox_shub_odr_t * val)10718 int32_t lsm6dsox_sh_data_rate_get(const stmdev_ctx_t *ctx,
10719 lsm6dsox_shub_odr_t *val)
10720 {
10721 lsm6dsox_slv0_config_t reg;
10722 int32_t ret;
10723
10724 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10725
10726 if (ret == 0)
10727 {
10728 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG, (uint8_t *)®, 1);
10729 }
10730
10731 if (ret == 0)
10732 {
10733 switch (reg.shub_odr)
10734 {
10735 case LSM6DSOX_SH_ODR_104Hz:
10736 *val = LSM6DSOX_SH_ODR_104Hz;
10737 break;
10738
10739 case LSM6DSOX_SH_ODR_52Hz:
10740 *val = LSM6DSOX_SH_ODR_52Hz;
10741 break;
10742
10743 case LSM6DSOX_SH_ODR_26Hz:
10744 *val = LSM6DSOX_SH_ODR_26Hz;
10745 break;
10746
10747 case LSM6DSOX_SH_ODR_13Hz:
10748 *val = LSM6DSOX_SH_ODR_13Hz;
10749 break;
10750
10751 default:
10752 *val = LSM6DSOX_SH_ODR_104Hz;
10753 break;
10754 }
10755
10756 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10757 }
10758
10759 return ret;
10760 }
10761
10762 /**
10763 * @brief Configure slave 0 for perform a write.[set]
10764 *
10765 * @param ctx read / write interface definitions
10766 * @param val a structure that contain
10767 * - uint8_t slv1_add; 8 bit i2c device address
10768 * - uint8_t slv1_subadd; 8 bit register device address
10769 * - uint8_t slv1_data; 8 bit data to write
10770 * @retval interface status (MANDATORY: return 0 -> no Error)
10771 *
10772 */
lsm6dsox_sh_cfg_write(const stmdev_ctx_t * ctx,lsm6dsox_sh_cfg_write_t * val)10773 int32_t lsm6dsox_sh_cfg_write(const stmdev_ctx_t *ctx,
10774 lsm6dsox_sh_cfg_write_t *val)
10775 {
10776 lsm6dsox_slv0_add_t reg;
10777 int32_t ret;
10778
10779 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10780
10781 if (ret == 0)
10782 {
10783 reg.slave0 = val->slv0_add;
10784 reg.rw_0 = 0;
10785 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_ADD, (uint8_t *)®, 1);
10786 }
10787
10788 if (ret == 0)
10789 {
10790 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_SUBADD,
10791 &(val->slv0_subadd), 1);
10792 }
10793
10794 if (ret == 0)
10795 {
10796 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_DATAWRITE_SLV0,
10797 &(val->slv0_data), 1);
10798 }
10799
10800 if (ret == 0)
10801 {
10802 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10803 }
10804
10805 return ret;
10806 }
10807
10808 /**
10809 * @brief Configure slave 0 for perform a read.[set]
10810 *
10811 * @param ctx read / write interface definitions
10812 * @param val Structure that contain
10813 * - uint8_t slv1_add; 8 bit i2c device address
10814 * - uint8_t slv1_subadd; 8 bit register device address
10815 * - uint8_t slv1_len; num of bit to read
10816 * @retval interface status (MANDATORY: return 0 -> no Error)
10817 *
10818 */
lsm6dsox_sh_slv0_cfg_read(const stmdev_ctx_t * ctx,lsm6dsox_sh_cfg_read_t * val)10819 int32_t lsm6dsox_sh_slv0_cfg_read(const stmdev_ctx_t *ctx,
10820 lsm6dsox_sh_cfg_read_t *val)
10821 {
10822 lsm6dsox_slv0_add_t slv0_add;
10823 lsm6dsox_slv0_config_t slv0_config;
10824 int32_t ret;
10825
10826 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10827
10828 if (ret == 0)
10829 {
10830 slv0_add.slave0 = val->slv_add;
10831 slv0_add.rw_0 = 1;
10832 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_ADD, (uint8_t *)&slv0_add, 1);
10833 }
10834
10835 if (ret == 0)
10836 {
10837 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_SUBADD,
10838 &(val->slv_subadd), 1);
10839 }
10840
10841 if (ret == 0)
10842 {
10843 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV0_CONFIG,
10844 (uint8_t *)&slv0_config, 1);
10845 }
10846
10847 if (ret == 0)
10848 {
10849 slv0_config.slave0_numop = val->slv_len;
10850 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV0_CONFIG,
10851 (uint8_t *)&slv0_config, 1);
10852 }
10853
10854 if (ret == 0)
10855 {
10856 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10857 }
10858
10859 return ret;
10860 }
10861
10862 /**
10863 * @brief Configure slave 0 for perform a write/read.[set]
10864 *
10865 * @param ctx read / write interface definitions
10866 * @param val Structure that contain
10867 * - uint8_t slv1_add; 8 bit i2c device address
10868 * - uint8_t slv1_subadd; 8 bit register device address
10869 * - uint8_t slv1_len; num of bit to read
10870 * @retval interface status (MANDATORY: return 0 -> no Error)
10871 *
10872 */
lsm6dsox_sh_slv1_cfg_read(const stmdev_ctx_t * ctx,lsm6dsox_sh_cfg_read_t * val)10873 int32_t lsm6dsox_sh_slv1_cfg_read(const stmdev_ctx_t *ctx,
10874 lsm6dsox_sh_cfg_read_t *val)
10875 {
10876 lsm6dsox_slv1_add_t slv1_add;
10877 lsm6dsox_slv1_config_t slv1_config;
10878 int32_t ret;
10879
10880 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10881
10882 if (ret == 0)
10883 {
10884 slv1_add.slave1_add = val->slv_add;
10885 slv1_add.r_1 = 1;
10886 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_ADD, (uint8_t *)&slv1_add, 1);
10887 }
10888
10889 if (ret == 0)
10890 {
10891 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_SUBADD,
10892 &(val->slv_subadd), 1);
10893 }
10894
10895 if (ret == 0)
10896 {
10897 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV1_CONFIG,
10898 (uint8_t *)&slv1_config, 1);
10899 }
10900
10901 if (ret == 0)
10902 {
10903 slv1_config.slave1_numop = val->slv_len;
10904 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV1_CONFIG,
10905 (uint8_t *)&slv1_config, 1);
10906 }
10907
10908 if (ret == 0)
10909 {
10910 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10911 }
10912
10913 return ret;
10914 }
10915
10916 /**
10917 * @brief Configure slave 0 for perform a write/read.[set]
10918 *
10919 * @param ctx read / write interface definitions
10920 * @param val Structure that contain
10921 * - uint8_t slv2_add; 8 bit i2c device address
10922 * - uint8_t slv2_subadd; 8 bit register device address
10923 * - uint8_t slv2_len; num of bit to read
10924 * @retval interface status (MANDATORY: return 0 -> no Error)
10925 *
10926 */
lsm6dsox_sh_slv2_cfg_read(const stmdev_ctx_t * ctx,lsm6dsox_sh_cfg_read_t * val)10927 int32_t lsm6dsox_sh_slv2_cfg_read(const stmdev_ctx_t *ctx,
10928 lsm6dsox_sh_cfg_read_t *val)
10929 {
10930 lsm6dsox_slv2_add_t slv2_add;
10931 lsm6dsox_slv2_config_t slv2_config;
10932 int32_t ret;
10933
10934 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10935
10936 if (ret == 0)
10937 {
10938 slv2_add.slave2_add = val->slv_add;
10939 slv2_add.r_2 = 1;
10940 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_ADD, (uint8_t *)&slv2_add, 1);
10941 }
10942
10943 if (ret == 0)
10944 {
10945 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_SUBADD,
10946 &(val->slv_subadd), 1);
10947 }
10948
10949 if (ret == 0)
10950 {
10951 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV2_CONFIG,
10952 (uint8_t *)&slv2_config, 1);
10953 }
10954
10955 if (ret == 0)
10956 {
10957 slv2_config.slave2_numop = val->slv_len;
10958 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV2_CONFIG,
10959 (uint8_t *)&slv2_config, 1);
10960 }
10961
10962 if (ret == 0)
10963 {
10964 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
10965 }
10966
10967 return ret;
10968 }
10969
10970 /**
10971 * @brief Configure slave 0 for perform a write/read.[set]
10972 *
10973 * @param ctx read / write interface definitions
10974 * @param val Structure that contain
10975 * - uint8_t slv3_add; 8 bit i2c device address
10976 * - uint8_t slv3_subadd; 8 bit register device address
10977 * - uint8_t slv3_len; num of bit to read
10978 * @retval interface status (MANDATORY: return 0 -> no Error)
10979 *
10980 */
lsm6dsox_sh_slv3_cfg_read(const stmdev_ctx_t * ctx,lsm6dsox_sh_cfg_read_t * val)10981 int32_t lsm6dsox_sh_slv3_cfg_read(const stmdev_ctx_t *ctx,
10982 lsm6dsox_sh_cfg_read_t *val)
10983 {
10984 lsm6dsox_slv3_add_t slv3_add;
10985 lsm6dsox_slv3_config_t slv3_config;
10986 int32_t ret;
10987
10988 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
10989
10990 if (ret == 0)
10991 {
10992 slv3_add.slave3_add = val->slv_add;
10993 slv3_add.r_3 = 1;
10994 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_ADD, (uint8_t *)&slv3_add, 1);
10995 }
10996
10997 if (ret == 0)
10998 {
10999 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_SUBADD,
11000 &(val->slv_subadd), 1);
11001 }
11002
11003 if (ret == 0)
11004 {
11005 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_SLV3_CONFIG,
11006 (uint8_t *)&slv3_config, 1);
11007 }
11008
11009 if (ret == 0)
11010 {
11011 slv3_config.slave3_numop = val->slv_len;
11012 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_SLV3_CONFIG,
11013 (uint8_t *)&slv3_config, 1);
11014 }
11015
11016 if (ret == 0)
11017 {
11018 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
11019 }
11020
11021 return ret;
11022 }
11023
11024 /**
11025 * @brief Sensor hub source register.[get]
11026 *
11027 * @param ctx read / write interface definitions
11028 * @param val union of registers from STATUS_MASTER to
11029 * @retval interface status (MANDATORY: return 0 -> no Error)
11030 *
11031 */
lsm6dsox_sh_status_get(const stmdev_ctx_t * ctx,lsm6dsox_status_master_t * val)11032 int32_t lsm6dsox_sh_status_get(const stmdev_ctx_t *ctx,
11033 lsm6dsox_status_master_t *val)
11034 {
11035 int32_t ret;
11036
11037 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_SENSOR_HUB_BANK);
11038
11039 if (ret == 0)
11040 {
11041 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_MASTER, (uint8_t *) val, 1);
11042 }
11043
11044 if (ret == 0)
11045 {
11046 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
11047 }
11048
11049 return ret;
11050 }
11051
11052 /**
11053 * @}
11054 *
11055 */
11056
11057 /**
11058 * @addtogroup Sensors for Smart Mobile Devices
11059 * @brief This section groups all the functions that manage the
11060 * Sensors for Smart Mobile Devices.
11061 * @{
11062 *
11063 */
11064
11065 /**
11066 * @brief s4s_tph_res: [set] Sensor synchronization time frame resolution
11067 *
11068 * @param *ctx read / write interface definitions
11069 * @param val change the values of tph_h_sel in LSM6DSOX_S4S_TPH_L
11070 * @retval interface status (MANDATORY: return 0 -> no Error)
11071 *
11072 */
lsm6dsox_s4s_tph_res_set(const stmdev_ctx_t * ctx,lsm6dsox_s4s_tph_res_t val)11073 int32_t lsm6dsox_s4s_tph_res_set(const stmdev_ctx_t *ctx,
11074 lsm6dsox_s4s_tph_res_t val)
11075 {
11076 lsm6dsox_s4s_tph_l_t reg;
11077 int32_t ret;
11078
11079 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t *)®, 1);
11080
11081 if (ret == 0)
11082 {
11083 reg.tph_h_sel = (uint8_t)val;
11084 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t *)®, 1);
11085 }
11086
11087 return ret;
11088 }
11089
11090 /**
11091 * @brief s4s_tph_res: [get] Sensor synchronization time frame resolution
11092 *
11093 * @param *ctx read / write interface definitions
11094 * @param val get the values of tph_h_sel in LSM6DSOX_S4S_TPH_L
11095 * @retval interface status (MANDATORY: return 0 -> no Error)
11096 *
11097 */
lsm6dsox_s4s_tph_res_get(const stmdev_ctx_t * ctx,lsm6dsox_s4s_tph_res_t * val)11098 int32_t lsm6dsox_s4s_tph_res_get(const stmdev_ctx_t *ctx,
11099 lsm6dsox_s4s_tph_res_t *val)
11100 {
11101 lsm6dsox_s4s_tph_l_t reg;
11102 int32_t ret;
11103
11104 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L, (uint8_t *)®, 1);
11105
11106 switch (reg.tph_h_sel)
11107 {
11108 case LSM6DSOX_S4S_TPH_7bit:
11109 *val = LSM6DSOX_S4S_TPH_7bit;
11110 break;
11111
11112 case LSM6DSOX_S4S_TPH_15bit:
11113 *val = LSM6DSOX_S4S_TPH_15bit;
11114 break;
11115
11116 default:
11117 *val = LSM6DSOX_S4S_TPH_7bit;
11118 break;
11119 }
11120
11121 return ret;
11122 }
11123
11124 /**
11125 * @brief s4s_tph_val: [set] Sensor synchronization time frame
11126 *
11127 * @param *ctx read / write interface definitions
11128 * @param val change the values of tph_l in S4S_TPH_L and
11129 * tph_h in S4S_TPH_H
11130 * @retval interface status (MANDATORY: return 0 -> no Error)
11131 *
11132 */
lsm6dsox_s4s_tph_val_set(const stmdev_ctx_t * ctx,uint16_t val)11133 int32_t lsm6dsox_s4s_tph_val_set(const stmdev_ctx_t *ctx, uint16_t val)
11134 {
11135 lsm6dsox_s4s_tph_l_t s4s_tph_l;
11136 lsm6dsox_s4s_tph_h_t s4s_tph_h;
11137 int32_t ret;
11138
11139 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L,
11140 (uint8_t *)&s4s_tph_l, 1);
11141
11142 if (ret == 0)
11143 {
11144 s4s_tph_l.tph_l = (uint8_t)(val & 0x007FU);
11145 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_L,
11146 (uint8_t *)&s4s_tph_l, 1);
11147 }
11148
11149 if (ret == 0)
11150 {
11151 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_H,
11152 (uint8_t *)&s4s_tph_h, 1);
11153 s4s_tph_h.tph_h = (uint8_t)(val & 0x7F80U) >> 7;
11154 }
11155
11156 if (ret == 0)
11157 {
11158 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_TPH_H,
11159 (uint8_t *)&s4s_tph_h, 1);
11160 }
11161
11162 return ret;
11163 }
11164
11165 /**
11166 * @brief s4s_tph_val: [get] Sensor synchronization time frame.
11167 *
11168 * @param *ctx read / write interface definitions
11169 * @param val get the values of tph_l in S4S_TPH_L and
11170 * tph_h in S4S_TPH_H
11171 * @retval interface status (MANDATORY: return 0 -> no Error)
11172 *
11173 */
lsm6dsox_s4s_tph_val_get(const stmdev_ctx_t * ctx,uint16_t * val)11174 int32_t lsm6dsox_s4s_tph_val_get(const stmdev_ctx_t *ctx, uint16_t *val)
11175 {
11176 lsm6dsox_s4s_tph_l_t s4s_tph_l;
11177 lsm6dsox_s4s_tph_h_t s4s_tph_h;
11178 int32_t ret;
11179
11180 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_L,
11181 (uint8_t *)&s4s_tph_l, 1);
11182
11183 if (ret == 0)
11184 {
11185 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_TPH_H,
11186 (uint8_t *)&s4s_tph_h, 1);
11187 *val = s4s_tph_h.tph_h;
11188 *val = *val << 7;
11189 *val += s4s_tph_l.tph_l;
11190 }
11191
11192 return ret;
11193 }
11194
11195 /**
11196 * @brief s4s_res_ratio: [set]Sensor synchronization resolution
11197 * ratio register.
11198 *
11199 * @param *ctx read / write interface definitions.
11200 * @param val change the values of rr in S4S_RR.
11201 * @retval interface status (MANDATORY: return 0 -> no Error)
11202 *
11203 */
lsm6dsox_s4s_res_ratio_set(const stmdev_ctx_t * ctx,lsm6dsox_s4s_res_ratio_t val)11204 int32_t lsm6dsox_s4s_res_ratio_set(const stmdev_ctx_t *ctx,
11205 lsm6dsox_s4s_res_ratio_t val)
11206 {
11207 lsm6dsox_s4s_rr_t reg;
11208 int32_t ret;
11209
11210 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t *)®, 1);
11211
11212 if (ret == 0)
11213 {
11214 reg.rr = (uint8_t)val;
11215 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t *)®, 1);
11216 }
11217
11218 return ret;
11219 }
11220
11221 /**
11222 * @brief s4s_res_ratio: [get]Sensor synchronization resolution
11223 * ratio register.
11224 *
11225 * @param *ctx read / write interface definitions
11226 * @param val get the values of rr in S4S_RR
11227 * @retval interface status (MANDATORY: return 0 -> no Error)
11228 *
11229 */
lsm6dsox_s4s_res_ratio_get(const stmdev_ctx_t * ctx,lsm6dsox_s4s_res_ratio_t * val)11230 int32_t lsm6dsox_s4s_res_ratio_get(const stmdev_ctx_t *ctx,
11231 lsm6dsox_s4s_res_ratio_t *val)
11232 {
11233 lsm6dsox_s4s_rr_t reg;
11234 int32_t ret;
11235
11236 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_RR, (uint8_t *)®, 1);
11237
11238 switch (reg.rr)
11239 {
11240 case LSM6DSOX_S4S_DT_RES_11:
11241 *val = LSM6DSOX_S4S_DT_RES_11;
11242 break;
11243
11244 case LSM6DSOX_S4S_DT_RES_12:
11245 *val = LSM6DSOX_S4S_DT_RES_12;
11246 break;
11247
11248 case LSM6DSOX_S4S_DT_RES_13:
11249 *val = LSM6DSOX_S4S_DT_RES_13;
11250 break;
11251
11252 case LSM6DSOX_S4S_DT_RES_14:
11253 *val = LSM6DSOX_S4S_DT_RES_14;
11254 break;
11255
11256 default:
11257 *val = LSM6DSOX_S4S_DT_RES_11;
11258 break;
11259 }
11260
11261 return ret;
11262 }
11263
11264 /**
11265 * @brief s4s_command: [set] s4s master command.
11266 *
11267 * @param *ctx read / write interface definitions.
11268 * @param val change the values of S4S_ST_CMD_CODE.
11269 * @retval interface status (MANDATORY: return 0 -> no Error)
11270 *
11271 */
lsm6dsox_s4s_command_set(const stmdev_ctx_t * ctx,uint8_t val)11272 int32_t lsm6dsox_s4s_command_set(const stmdev_ctx_t *ctx, uint8_t val)
11273 {
11274 lsm6dsox_s4s_st_cmd_code_t reg;
11275 int32_t ret;
11276
11277 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE,
11278 (uint8_t *)®, 1);
11279
11280 if (ret == 0)
11281 {
11282 reg.s4s_st_cmd_code = val;
11283 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE,
11284 (uint8_t *)®, 1);
11285 }
11286
11287 return ret;
11288 }
11289
11290 /**
11291 * @brief s4s_command: [get] s4s master command.
11292 *
11293 * @param *ctx read / write interface definitions.
11294 * @param val get the values of S4S_ST_CMD_CODE.
11295 * @retval interface status (MANDATORY: return 0 -> no Error)
11296 *
11297 */
lsm6dsox_s4s_command_get(const stmdev_ctx_t * ctx,uint8_t * val)11298 int32_t lsm6dsox_s4s_command_get(const stmdev_ctx_t *ctx, uint8_t *val)
11299 {
11300 lsm6dsox_s4s_st_cmd_code_t reg;
11301 int32_t ret;
11302
11303 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_ST_CMD_CODE,
11304 (uint8_t *)®, 1);
11305 *val = reg.s4s_st_cmd_code;
11306
11307 return ret;
11308 }
11309
11310 /**
11311 * @brief s4s_dt: [set] S4S DT register.
11312 *
11313 * @param *ctx read / write interface definitions.
11314 * @param val change the values of S4S_DT_REG.
11315 * @retval interface status (MANDATORY: return 0 -> no Error)
11316 *
11317 */
lsm6dsox_s4s_dt_set(const stmdev_ctx_t * ctx,uint8_t val)11318 int32_t lsm6dsox_s4s_dt_set(const stmdev_ctx_t *ctx, uint8_t val)
11319 {
11320 lsm6dsox_s4s_dt_reg_t reg;
11321 int32_t ret;
11322
11323 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t *)®, 1);
11324
11325 if (ret == 0)
11326 {
11327 reg.dt = val;
11328 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t *)®, 1);
11329 }
11330
11331 return ret;
11332 }
11333
11334 /**
11335 * @brief s4s_dt: [get] S4S DT register.
11336 *
11337 * @param *ctx read / write interface definitions.
11338 * @param val get the values of S4S_DT_REG.
11339 * @retval interface status (MANDATORY: return 0 -> no Error)
11340 *
11341 */
lsm6dsox_s4s_dt_get(const stmdev_ctx_t * ctx,uint8_t * val)11342 int32_t lsm6dsox_s4s_dt_get(const stmdev_ctx_t *ctx, uint8_t *val)
11343 {
11344 lsm6dsox_s4s_dt_reg_t reg;
11345 int32_t ret;
11346
11347 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_S4S_DT_REG, (uint8_t *)®, 1);
11348 *val = reg.dt;
11349
11350 return ret;
11351 }
11352
11353 /**
11354 * @}
11355 *
11356 */
11357
11358 /**
11359 * @defgroup Basic configuration
11360 * @brief This section groups all the functions concerning
11361 * device basic configuration.
11362 * @{
11363 *
11364 */
11365
11366 /**
11367 * @brief Device "Who am I".[get]
11368 *
11369 * @param ctx communication interface handler. Use NULL to ignore
11370 * this interface.(ptr)
11371 * @param aux_ctx auxiliary communication interface handler. Use NULL
11372 * to ignore this interface.(ptr)
11373 * @param val ID values read from the two interfaces. ID values
11374 * will be the same.(ptr)
11375 * @retval interface status (MANDATORY: return 0 -> no Error)
11376 *
11377 */
lsm6dsox_id_get(const stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dsox_id_t * val)11378 int32_t lsm6dsox_id_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
11379 lsm6dsox_id_t *val)
11380 {
11381 int32_t ret = 0;
11382
11383 if (ctx != NULL)
11384 {
11385 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_WHO_AM_I,
11386 (uint8_t *) & (val->ui), 1);
11387 }
11388
11389 if (aux_ctx != NULL)
11390 {
11391 if (ret == 0)
11392 {
11393 ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_WHO_AM_I,
11394 (uint8_t *) & (val->aux), 1);
11395 }
11396 }
11397
11398 return ret;
11399 }
11400
11401 /**
11402 * @brief Re-initialize the device.[set]
11403 *
11404 * @param ctx communication interface handler.(ptr)
11405 * @param val re-initialization mode. Refer to datasheet
11406 * and application note for more information
11407 * about differencies between boot and sw_reset
11408 * procedure.
11409 * @retval interface status (MANDATORY: return 0 -> no Error)
11410 *
11411 */
lsm6dsox_init_set(const stmdev_ctx_t * ctx,lsm6dsox_init_t val)11412 int32_t lsm6dsox_init_set(const stmdev_ctx_t *ctx, lsm6dsox_init_t val)
11413 {
11414 lsm6dsox_emb_func_init_a_t emb_func_init_a;
11415 lsm6dsox_emb_func_init_b_t emb_func_init_b;
11416 lsm6dsox_ctrl3_c_t ctrl3_c;
11417 int32_t ret;
11418
11419 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
11420
11421 if (ret == 0)
11422 {
11423 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
11424 (uint8_t *)&emb_func_init_b, 1);
11425 }
11426
11427 if (ret == 0)
11428 {
11429 emb_func_init_b.fifo_compr_init = (uint8_t)val
11430 & ((uint8_t)LSM6DSOX_FIFO_COMP >> 2);
11431 emb_func_init_b.fsm_init = (uint8_t)val
11432 & ((uint8_t)LSM6DSOX_FSM >> 3);
11433 emb_func_init_b.mlc_init = (uint8_t)val
11434 & ((uint8_t)LSM6DSOX_MLC >> 4);
11435 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_B,
11436 (uint8_t *)&emb_func_init_b, 1);
11437 }
11438
11439 if (ret == 0)
11440 {
11441 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_A,
11442 (uint8_t *)&emb_func_init_a, 1);
11443 }
11444
11445 if (ret == 0)
11446 {
11447 emb_func_init_a.step_det_init = ((uint8_t)val
11448 & (uint8_t)LSM6DSOX_PEDO) >> 5;
11449 emb_func_init_a.tilt_init = ((uint8_t)val
11450 & (uint8_t)LSM6DSOX_TILT) >> 6;
11451 emb_func_init_a.sig_mot_init = ((uint8_t)val
11452 & (uint8_t)LSM6DSOX_SMOTION) >> 7;
11453 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INIT_A,
11454 (uint8_t *)&emb_func_init_a, 1);
11455 }
11456
11457 if (ret == 0)
11458 {
11459 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
11460 }
11461
11462 if (ret == 0)
11463 {
11464 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
11465 }
11466
11467 if (((val == LSM6DSOX_BOOT) || (val == LSM6DSOX_RESET)) &&
11468 (ret == 0))
11469 {
11470 ctrl3_c.boot = (uint8_t)val & (uint8_t)LSM6DSOX_BOOT;
11471 ctrl3_c.sw_reset = ((uint8_t)val & (uint8_t)LSM6DSOX_RESET) >> 1;
11472 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
11473 }
11474
11475 if ((val == LSM6DSOX_DRV_RDY)
11476 && ((ctrl3_c.bdu == PROPERTY_DISABLE)
11477 || (ctrl3_c.if_inc == PROPERTY_DISABLE)) && (ret == 0))
11478 {
11479 ctrl3_c.bdu = PROPERTY_ENABLE;
11480 ctrl3_c.if_inc = PROPERTY_ENABLE;
11481 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
11482 }
11483
11484 return ret;
11485 }
11486
11487 /**
11488 * @brief Configures the bus operating mode.[set]
11489 *
11490 * @param ctx communication interface handler. Use NULL to ignore
11491 * this interface.(ptr)
11492 * @param aux_ctx auxiliary communication interface handler. Use NULL
11493 * to ignore this interface.(ptr)
11494 * @param val configures the bus operating mode for both the
11495 * main and the auxiliary interface.
11496 * @retval interface status (MANDATORY: return 0 -> no Error)
11497 *
11498 */
lsm6dsox_bus_mode_set(const stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dsox_bus_mode_t val)11499 int32_t lsm6dsox_bus_mode_set(const stmdev_ctx_t *ctx,
11500 stmdev_ctx_t *aux_ctx,
11501 lsm6dsox_bus_mode_t val)
11502 {
11503 lsm6dsox_spi2_ctrl1_ois_t spi2_ctrl1_ois;
11504 lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
11505 lsm6dsox_ctrl9_xl_t ctrl9_xl;
11506 lsm6dsox_ctrl3_c_t ctrl3_c;
11507 lsm6dsox_ctrl4_c_t ctrl4_c;
11508 uint8_t bit_val;
11509 int32_t ret;
11510
11511 ret = 0;
11512
11513 if (aux_ctx != NULL)
11514 {
11515 ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS,
11516 (uint8_t *)&spi2_ctrl1_ois, 1);
11517 bit_val = ((uint8_t)val.aux_bus_md & 0x04U) >> 2;
11518
11519 if ((ret == 0) && (spi2_ctrl1_ois.sim_ois != bit_val))
11520 {
11521 spi2_ctrl1_ois.sim_ois = bit_val;
11522 ret = lsm6dsox_write_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS,
11523 (uint8_t *)&spi2_ctrl1_ois, 1);
11524 }
11525 }
11526
11527 if (ctx != NULL)
11528 {
11529 if (ret == 0)
11530 {
11531 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL,
11532 (uint8_t *)&ctrl9_xl, 1);
11533 }
11534
11535 bit_val = ((uint8_t)val.ui_bus_md & 0x04U) >> 2;
11536
11537 if ((ret == 0) && (ctrl9_xl.i3c_disable != bit_val))
11538 {
11539 ctrl9_xl.i3c_disable = bit_val;
11540 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL9_XL,
11541 (uint8_t *)&ctrl9_xl, 1);
11542 }
11543
11544 if (ret == 0)
11545 {
11546 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
11547 (uint8_t *)&i3c_bus_avb, 1);
11548 }
11549
11550 bit_val = ((uint8_t)val.ui_bus_md & 0x30U) >> 4;
11551
11552 if ((ret == 0) && (i3c_bus_avb.i3c_bus_avb_sel != bit_val))
11553 {
11554 i3c_bus_avb.i3c_bus_avb_sel = bit_val;
11555 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
11556 (uint8_t *)&i3c_bus_avb, 1);
11557 }
11558
11559 if (ret == 0)
11560 {
11561 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C,
11562 (uint8_t *)&ctrl4_c, 1);
11563 }
11564
11565 bit_val = ((uint8_t)val.ui_bus_md & 0x02U) >> 1;
11566
11567 if ((ret == 0) && (ctrl4_c.i2c_disable != bit_val))
11568 {
11569 ctrl4_c.i2c_disable = bit_val;
11570 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C,
11571 (uint8_t *)&ctrl4_c, 1);
11572 }
11573
11574 if (ret == 0)
11575 {
11576 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C,
11577 (uint8_t *)&ctrl3_c, 1);
11578 }
11579
11580 bit_val = (uint8_t)val.ui_bus_md & 0x01U;
11581
11582 if ((ret == 0) && (ctrl3_c.sim != bit_val))
11583 {
11584 ctrl3_c.sim = bit_val;
11585 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C,
11586 (uint8_t *)&ctrl3_c, 1);
11587 }
11588 }
11589
11590 return ret;
11591 }
11592
11593 /**
11594 * @brief Get the bus operating mode.[get]
11595 *
11596 * @param ctx communication interface handler. Use NULL to ignore
11597 * this interface.(ptr)
11598 * @param aux_ctx auxiliary communication interface handler. Use NULL
11599 * to ignore this interface.(ptr)
11600 * @param val retrieves the bus operating mode for both the main
11601 * and the auxiliary interface.(ptr)
11602 * @retval interface status (MANDATORY: return 0 -> no Error)
11603 *
11604 */
lsm6dsox_bus_mode_get(const stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dsox_bus_mode_t * val)11605 int32_t lsm6dsox_bus_mode_get(const stmdev_ctx_t *ctx,
11606 stmdev_ctx_t *aux_ctx,
11607 lsm6dsox_bus_mode_t *val)
11608 {
11609 lsm6dsox_spi2_ctrl1_ois_t spi2_ctrl1_ois;
11610 lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
11611 lsm6dsox_ctrl9_xl_t ctrl9_xl;
11612 lsm6dsox_ctrl3_c_t ctrl3_c;
11613 lsm6dsox_ctrl4_c_t ctrl4_c;
11614 int32_t ret = 0;
11615
11616 if (aux_ctx != NULL)
11617 {
11618 ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS,
11619 (uint8_t *)&spi2_ctrl1_ois, 1);
11620
11621 switch (spi2_ctrl1_ois.sim_ois)
11622 {
11623 case LSM6DSOX_SPI_4W_AUX:
11624 val->aux_bus_md = LSM6DSOX_SPI_4W_AUX;
11625 break;
11626
11627 case LSM6DSOX_SPI_3W_AUX:
11628 val->aux_bus_md = LSM6DSOX_SPI_3W_AUX;
11629 break;
11630
11631 default:
11632 val->aux_bus_md = LSM6DSOX_SPI_4W_AUX;
11633 break;
11634 }
11635 }
11636
11637 if (ctx != NULL)
11638 {
11639 if (ret == 0)
11640 {
11641 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL9_XL,
11642 (uint8_t *)&ctrl9_xl, 1);
11643 }
11644
11645 if (ret == 0)
11646 {
11647 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
11648 (uint8_t *)&i3c_bus_avb, 1);
11649 }
11650
11651 if (ret == 0)
11652 {
11653 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C,
11654 (uint8_t *)&ctrl4_c, 1);
11655 }
11656
11657 if (ret == 0)
11658 {
11659 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C,
11660 (uint8_t *)&ctrl3_c, 1);
11661
11662 switch ((i3c_bus_avb.i3c_bus_avb_sel << 4) &
11663 (ctrl9_xl.i3c_disable << 2) &
11664 (ctrl4_c.i2c_disable << 1) & ctrl3_c.sim)
11665 {
11666 case LSM6DSOX_SEL_BY_HW:
11667 val->ui_bus_md = LSM6DSOX_SEL_BY_HW;
11668 break;
11669
11670 case LSM6DSOX_SPI_4W:
11671 val->ui_bus_md = LSM6DSOX_SPI_4W;
11672 break;
11673
11674 case LSM6DSOX_SPI_3W:
11675 val->ui_bus_md = LSM6DSOX_SPI_3W;
11676 break;
11677
11678 case LSM6DSOX_I2C:
11679 val->ui_bus_md = LSM6DSOX_I2C;
11680 break;
11681
11682 case LSM6DSOX_I3C_T_50us:
11683 val->ui_bus_md = LSM6DSOX_I3C_T_50us;
11684 break;
11685
11686 case LSM6DSOX_I3C_T_2us:
11687 val->ui_bus_md = LSM6DSOX_I3C_T_2us;
11688 break;
11689
11690 case LSM6DSOX_I3C_T_1ms:
11691 val->ui_bus_md = LSM6DSOX_I3C_T_1ms;
11692 break;
11693
11694 case LSM6DSOX_I3C_T_25ms:
11695 val->ui_bus_md = LSM6DSOX_I3C_T_25ms;
11696 break;
11697
11698 default:
11699 val->ui_bus_md = LSM6DSOX_SEL_BY_HW;
11700 break;
11701 }
11702 }
11703 }
11704
11705 return ret;
11706 }
11707
11708 /**
11709 * @brief Get the status of the device.[get]
11710 *
11711 * @param ctx communication interface handler. Use NULL to ignore
11712 * this interface.(ptr)
11713 * @param aux_ctx auxiliary communication interface handler. Use NULL
11714 * to ignore this interface.(ptr)
11715 * @param val the status of the device.(ptr)
11716 * @retval interface status (MANDATORY: return 0 -> no Error)
11717 *
11718 */
lsm6dsox_status_get(const stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dsox_status_t * val)11719 int32_t lsm6dsox_status_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
11720 lsm6dsox_status_t *val)
11721 {
11722 lsm6dsox_spi2_status_reg_ois_t spi2_status_reg_ois;
11723 lsm6dsox_ui_status_reg_ois_t ui_status_reg_ois;
11724 lsm6dsox_status_reg_t status_reg;
11725 lsm6dsox_ctrl3_c_t ctrl3_c;
11726 int32_t ret;
11727 ret = 0;
11728
11729 if (aux_ctx != NULL)
11730 {
11731 ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_STATUS_REG_OIS,
11732 (uint8_t *)&spi2_status_reg_ois, 1);
11733 val->ois_drdy_xl = spi2_status_reg_ois.xlda;
11734 val->ois_drdy_g = spi2_status_reg_ois.gda;
11735 val->ois_gyro_settling = spi2_status_reg_ois.gyro_settling;
11736 }
11737
11738 if (ctx != NULL)
11739 {
11740 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
11741 val->sw_reset = ctrl3_c.sw_reset;
11742 val->boot = ctrl3_c.boot;
11743
11744 if ((ret == 0) && (ctrl3_c.sw_reset == PROPERTY_DISABLE) &&
11745 (ctrl3_c.boot == PROPERTY_DISABLE))
11746 {
11747 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_STATUS_REG,
11748 (uint8_t *)&status_reg, 1);
11749 val->drdy_xl = status_reg.xlda;
11750 val->drdy_g = status_reg.gda;
11751 val->drdy_temp = status_reg.tda;
11752 }
11753
11754 if (aux_ctx == NULL)
11755 {
11756 if (ret == 0)
11757 {
11758 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_STATUS_REG_OIS,
11759 (uint8_t *)&ui_status_reg_ois, 1);
11760 val->ois_drdy_xl = ui_status_reg_ois.xlda;
11761 val->ois_drdy_g = ui_status_reg_ois.gda;
11762 val->ois_gyro_settling = ui_status_reg_ois.gyro_settling;
11763 }
11764 }
11765 }
11766
11767 return ret;
11768 }
11769
11770 /**
11771 * @brief Electrical pin configuration.[set]
11772 *
11773 * @param ctx communication interface handler.(ptr)
11774 * @param val the electrical settings for the configurable
11775 * pins.
11776 * @retval interface status (MANDATORY: return 0 -> no Error)
11777 *
11778 */
lsm6dsox_pin_conf_set(const stmdev_ctx_t * ctx,lsm6dsox_pin_conf_t val)11779 int32_t lsm6dsox_pin_conf_set(const stmdev_ctx_t *ctx,
11780 lsm6dsox_pin_conf_t val)
11781 {
11782 lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
11783 lsm6dsox_pin_ctrl_t pin_ctrl;
11784 lsm6dsox_ctrl3_c_t ctrl3_c;
11785 int32_t ret;
11786
11787 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
11788
11789 if (ret == 0)
11790 {
11791 pin_ctrl.ois_pu_dis = ~val.aux_sdo_ocs_pull_up;
11792 pin_ctrl.sdo_pu_en = val.sdo_sa0_pull_up;
11793 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
11794 }
11795
11796 if (ret == 0)
11797 {
11798 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
11799 }
11800
11801 if (ret == 0)
11802 {
11803 ctrl3_c.pp_od = ~val.int1_int2_push_pull;
11804 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
11805 }
11806
11807 if (ret == 0)
11808 {
11809 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
11810 (uint8_t *)&i3c_bus_avb, 1);
11811 }
11812
11813 if (ret == 0)
11814 {
11815 i3c_bus_avb.pd_dis_int1 = ~val.int1_pull_down;
11816 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
11817 (uint8_t *)&i3c_bus_avb, 1);
11818 }
11819
11820 return ret;
11821 }
11822
11823 /**
11824 * @brief Electrical pin configuration.[get]
11825 *
11826 * @param ctx communication interface handler.(ptr)
11827 * @param val the electrical settings for the configurable
11828 * pins.(ptr)
11829 * @retval interface status (MANDATORY: return 0 -> no Error)
11830 *
11831 */
lsm6dsox_pin_conf_get(const stmdev_ctx_t * ctx,lsm6dsox_pin_conf_t * val)11832 int32_t lsm6dsox_pin_conf_get(const stmdev_ctx_t *ctx,
11833 lsm6dsox_pin_conf_t *val)
11834 {
11835 lsm6dsox_i3c_bus_avb_t i3c_bus_avb;
11836 lsm6dsox_pin_ctrl_t pin_ctrl;
11837 lsm6dsox_ctrl3_c_t ctrl3_c;
11838 int32_t ret;
11839
11840 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
11841
11842 if (ret == 0)
11843 {
11844 val->aux_sdo_ocs_pull_up = ~pin_ctrl.ois_pu_dis;
11845 val->aux_sdo_ocs_pull_up = pin_ctrl.sdo_pu_en;
11846 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
11847 }
11848
11849 if (ret == 0)
11850 {
11851 val->int1_int2_push_pull = ~ctrl3_c.pp_od;
11852 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_I3C_BUS_AVB,
11853 (uint8_t *)&i3c_bus_avb, 1);
11854 }
11855
11856 if (ret == 0)
11857 {
11858 val->int1_pull_down = ~i3c_bus_avb.pd_dis_int1;
11859 }
11860
11861 return ret;
11862 }
11863
11864 /**
11865 * @brief Interrupt pins hardware signal configuration.[set]
11866 *
11867 * @param ctx communication interface handler.(ptr)
11868 * @param val the pins hardware signal settings.
11869 * @retval interface status (MANDATORY: return 0 -> no Error)
11870 *
11871 */
lsm6dsox_interrupt_mode_set(const stmdev_ctx_t * ctx,lsm6dsox_int_mode_t val)11872 int32_t lsm6dsox_interrupt_mode_set(const stmdev_ctx_t *ctx,
11873 lsm6dsox_int_mode_t val)
11874 {
11875 lsm6dsox_tap_cfg0_t tap_cfg0;
11876 lsm6dsox_page_rw_t page_rw;
11877 lsm6dsox_ctrl3_c_t ctrl3_c;
11878 int32_t ret;
11879
11880 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
11881
11882 if (ret == 0)
11883 {
11884 ctrl3_c.h_lactive = val.active_low;
11885 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
11886 }
11887
11888 if (ret == 0)
11889 {
11890 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
11891 }
11892
11893 if (ret == 0)
11894 {
11895 tap_cfg0.lir = val.base_latched;
11896 tap_cfg0.int_clr_on_read = val.base_latched | val.emb_latched;
11897 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG0,
11898 (uint8_t *) &tap_cfg0, 1);
11899 }
11900
11901 if (ret == 0)
11902 {
11903 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
11904 }
11905
11906 if (ret == 0)
11907 {
11908 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
11909 }
11910
11911 if (ret == 0)
11912 {
11913 page_rw.emb_func_lir = val.emb_latched;
11914 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
11915 }
11916
11917 if (ret == 0)
11918 {
11919 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
11920 }
11921
11922 return ret;
11923 }
11924
11925 /**
11926 * @brief Interrupt pins hardware signal configuration.[get]
11927 *
11928 * @param ctx communication interface handler.(ptr)
11929 * @param val the pins hardware signal settings.(ptr)
11930 * @retval interface status (MANDATORY: return 0 -> no Error)
11931 *
11932 */
lsm6dsox_interrupt_mode_get(const stmdev_ctx_t * ctx,lsm6dsox_int_mode_t * val)11933 int32_t lsm6dsox_interrupt_mode_get(const stmdev_ctx_t *ctx,
11934 lsm6dsox_int_mode_t *val)
11935 {
11936 lsm6dsox_tap_cfg0_t tap_cfg0;
11937 lsm6dsox_page_rw_t page_rw;
11938 lsm6dsox_ctrl3_c_t ctrl3_c;
11939 int32_t ret;
11940
11941 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
11942
11943 if (ret == 0)
11944 {
11945 val->active_low = ctrl3_c.h_lactive;
11946 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
11947 }
11948
11949 if (ret == 0)
11950 {
11951 val->base_latched = (tap_cfg0.lir & tap_cfg0.int_clr_on_read);
11952 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
11953 }
11954
11955 if (ret == 0)
11956 {
11957 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_PAGE_RW, (uint8_t *) &page_rw, 1);
11958 }
11959
11960 if (ret == 0)
11961 {
11962 val->emb_latched = (page_rw.emb_func_lir & tap_cfg0.int_clr_on_read);
11963 }
11964
11965 if (ret == 0)
11966 {
11967 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
11968 }
11969
11970 return ret;
11971 }
11972
11973 /**
11974 * @brief Route interrupt signals on int1 pin.[set]
11975 *
11976 * @param ctx communication interface handler.(ptr)
11977 * @param val the signals to route on int1 pin.
11978 * @retval interface status (MANDATORY: return 0 -> no Error)
11979 *
11980 */
lsm6dsox_pin_int1_route_set(const stmdev_ctx_t * ctx,lsm6dsox_pin_int1_route_t val)11981 int32_t lsm6dsox_pin_int1_route_set(const stmdev_ctx_t *ctx,
11982 lsm6dsox_pin_int1_route_t val)
11983 {
11984 lsm6dsox_pin_int2_route_t pin_int2_route;
11985 lsm6dsox_emb_func_int1_t emb_func_int1 = {0};
11986 lsm6dsox_fsm_int1_a_t fsm_int1_a = {0};
11987 lsm6dsox_fsm_int1_b_t fsm_int1_b = {0};
11988 lsm6dsox_int1_ctrl_t int1_ctrl = {0};
11989 lsm6dsox_int2_ctrl_t int2_ctrl;
11990 lsm6dsox_mlc_int1_t mlc_int1 = {0};
11991 lsm6dsox_tap_cfg2_t tap_cfg2;
11992 lsm6dsox_md2_cfg_t md2_cfg;
11993 lsm6dsox_md1_cfg_t md1_cfg = {0};
11994 lsm6dsox_ctrl4_c_t ctrl4_c;
11995 int32_t ret;
11996
11997 int1_ctrl.int1_drdy_xl = val.drdy_xl;
11998 int1_ctrl.int1_drdy_g = val.drdy_g;
11999 int1_ctrl.int1_boot = val.boot;
12000 int1_ctrl.int1_fifo_th = val.fifo_th;
12001 int1_ctrl.int1_fifo_ovr = val.fifo_ovr;
12002 int1_ctrl.int1_fifo_full = val.fifo_full;
12003 int1_ctrl.int1_cnt_bdr = val.fifo_bdr;
12004 int1_ctrl.den_drdy_flag = val.den_flag;
12005 md1_cfg.int1_shub = val.sh_endop;
12006 md1_cfg.int1_6d = val.six_d;
12007 md1_cfg.int1_double_tap = val.double_tap;
12008 md1_cfg.int1_ff = val.free_fall;
12009 md1_cfg.int1_wu = val.wake_up;
12010 md1_cfg.int1_single_tap = val.single_tap;
12011 md1_cfg.int1_sleep_change = val.sleep_change;
12012 emb_func_int1.not_used_01 = 0;
12013 emb_func_int1.int1_step_detector = val.step_detector;
12014 emb_func_int1.int1_tilt = val.tilt;
12015 emb_func_int1.int1_sig_mot = val.sig_mot;
12016 emb_func_int1.not_used_02 = 0;
12017 emb_func_int1.int1_fsm_lc = val.fsm_lc;
12018 fsm_int1_a.int1_fsm1 = val.fsm1;
12019 fsm_int1_a.int1_fsm2 = val.fsm2;
12020 fsm_int1_a.int1_fsm3 = val.fsm3;
12021 fsm_int1_a.int1_fsm4 = val.fsm4;
12022 fsm_int1_a.int1_fsm5 = val.fsm5;
12023 fsm_int1_a.int1_fsm6 = val.fsm6;
12024 fsm_int1_a.int1_fsm7 = val.fsm7;
12025 fsm_int1_a.int1_fsm8 = val.fsm8;
12026 fsm_int1_b.int1_fsm9 = val.fsm9 ;
12027 fsm_int1_b.int1_fsm10 = val.fsm10;
12028 fsm_int1_b.int1_fsm11 = val.fsm11;
12029 fsm_int1_b.int1_fsm12 = val.fsm12;
12030 fsm_int1_b.int1_fsm13 = val.fsm13;
12031 fsm_int1_b.int1_fsm14 = val.fsm14;
12032 fsm_int1_b.int1_fsm15 = val.fsm15;
12033 fsm_int1_b.int1_fsm16 = val.fsm16;
12034 mlc_int1.int1_mlc1 = val.mlc1;
12035 mlc_int1.int1_mlc2 = val.mlc2;
12036 mlc_int1.int1_mlc3 = val.mlc3;
12037 mlc_int1.int1_mlc4 = val.mlc4;
12038 mlc_int1.int1_mlc5 = val.mlc5;
12039 mlc_int1.int1_mlc6 = val.mlc6;
12040 mlc_int1.int1_mlc7 = val.mlc7;
12041 mlc_int1.int1_mlc8 = val.mlc8;
12042 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
12043
12044 if (ret == 0)
12045 {
12046 if ((val.drdy_temp | val.timestamp) != PROPERTY_DISABLE)
12047 {
12048 ctrl4_c.int2_on_int1 = PROPERTY_ENABLE;
12049 }
12050
12051 else
12052 {
12053 ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
12054 }
12055
12056 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
12057 }
12058
12059 if (ret == 0)
12060 {
12061 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
12062 }
12063
12064 if (ret == 0)
12065 {
12066 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MLC_INT1,
12067 (uint8_t *)&mlc_int1, 1);
12068 }
12069
12070 if (ret == 0)
12071 {
12072 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INT1,
12073 (uint8_t *)&emb_func_int1, 1);
12074 }
12075
12076 if (ret == 0)
12077 {
12078 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT1_A,
12079 (uint8_t *)&fsm_int1_a, 1);
12080 }
12081
12082 if (ret == 0)
12083 {
12084 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT1_B,
12085 (uint8_t *)&fsm_int1_b, 1);
12086 }
12087
12088 if (ret == 0)
12089 {
12090 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
12091 }
12092
12093 if (ret == 0)
12094 {
12095 if ((emb_func_int1.int1_fsm_lc
12096 | emb_func_int1.int1_sig_mot
12097 | emb_func_int1.int1_step_detector
12098 | emb_func_int1.int1_tilt
12099 | fsm_int1_a.int1_fsm1
12100 | fsm_int1_a.int1_fsm2
12101 | fsm_int1_a.int1_fsm3
12102 | fsm_int1_a.int1_fsm4
12103 | fsm_int1_a.int1_fsm5
12104 | fsm_int1_a.int1_fsm6
12105 | fsm_int1_a.int1_fsm7
12106 | fsm_int1_a.int1_fsm8
12107 | fsm_int1_b.int1_fsm9
12108 | fsm_int1_b.int1_fsm10
12109 | fsm_int1_b.int1_fsm11
12110 | fsm_int1_b.int1_fsm12
12111 | fsm_int1_b.int1_fsm13
12112 | fsm_int1_b.int1_fsm14
12113 | fsm_int1_b.int1_fsm15
12114 | fsm_int1_b.int1_fsm16
12115 | mlc_int1.int1_mlc1
12116 | mlc_int1.int1_mlc2
12117 | mlc_int1.int1_mlc3
12118 | mlc_int1.int1_mlc4
12119 | mlc_int1.int1_mlc5
12120 | mlc_int1.int1_mlc6
12121 | mlc_int1.int1_mlc7
12122 | mlc_int1.int1_mlc8) != PROPERTY_DISABLE)
12123 {
12124 md1_cfg.int1_emb_func = PROPERTY_ENABLE;
12125 }
12126
12127 else
12128 {
12129 md1_cfg.int1_emb_func = PROPERTY_DISABLE;
12130 }
12131
12132 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT1_CTRL,
12133 (uint8_t *)&int1_ctrl, 1);
12134 }
12135
12136 if (ret == 0)
12137 {
12138 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MD1_CFG, (uint8_t *)&md1_cfg, 1);
12139 }
12140
12141 if (ret == 0)
12142 {
12143 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL,
12144 (uint8_t *)&int2_ctrl, 1);
12145 }
12146
12147 if (ret == 0)
12148 {
12149 int2_ctrl.int2_drdy_temp = val.drdy_temp;
12150 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT2_CTRL,
12151 (uint8_t *)&int2_ctrl, 1);
12152 }
12153
12154 if (ret == 0)
12155 {
12156 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
12157 }
12158
12159 if (ret == 0)
12160 {
12161 md2_cfg.int2_timestamp = val.timestamp;
12162 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
12163 }
12164
12165 if (ret == 0)
12166 {
12167 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
12168 }
12169
12170 if (ret == 0)
12171 {
12172 ret = lsm6dsox_pin_int2_route_get(ctx, NULL, &pin_int2_route);
12173 }
12174
12175 if (ret == 0)
12176 {
12177 if ((pin_int2_route.fifo_bdr
12178 | pin_int2_route.drdy_g
12179 | pin_int2_route.drdy_temp
12180 | pin_int2_route.drdy_xl
12181 | pin_int2_route.fifo_full
12182 | pin_int2_route.fifo_ovr
12183 | pin_int2_route.fifo_th
12184 | pin_int2_route.six_d
12185 | pin_int2_route.double_tap
12186 | pin_int2_route.free_fall
12187 | pin_int2_route.wake_up
12188 | pin_int2_route.single_tap
12189 | pin_int2_route.sleep_change
12190 | int1_ctrl.den_drdy_flag
12191 | int1_ctrl.int1_boot
12192 | int1_ctrl.int1_cnt_bdr
12193 | int1_ctrl.int1_drdy_g
12194 | int1_ctrl.int1_drdy_xl
12195 | int1_ctrl.int1_fifo_full
12196 | int1_ctrl.int1_fifo_ovr
12197 | int1_ctrl.int1_fifo_th
12198 | md1_cfg.int1_shub
12199 | md1_cfg.int1_6d
12200 | md1_cfg.int1_double_tap
12201 | md1_cfg.int1_ff
12202 | md1_cfg.int1_wu
12203 | md1_cfg.int1_single_tap
12204 | md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
12205 {
12206 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
12207 }
12208
12209 else
12210 {
12211 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
12212 }
12213
12214 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2,
12215 (uint8_t *) &tap_cfg2, 1);
12216 }
12217
12218 return ret;
12219 }
12220
12221 /**
12222 * @brief Route interrupt signals on int1 pin.[get]
12223 *
12224 * @param ctx communication interface handler.(ptr)
12225 * @param val the signals that are routed on int1 pin.(ptr)
12226 * @retval interface status (MANDATORY: return 0 -> no Error)
12227 *
12228 */
lsm6dsox_pin_int1_route_get(const stmdev_ctx_t * ctx,lsm6dsox_pin_int1_route_t * val)12229 int32_t lsm6dsox_pin_int1_route_get(const stmdev_ctx_t *ctx,
12230 lsm6dsox_pin_int1_route_t *val)
12231 {
12232 lsm6dsox_emb_func_int1_t emb_func_int1;
12233 lsm6dsox_fsm_int1_a_t fsm_int1_a;
12234 lsm6dsox_fsm_int1_b_t fsm_int1_b;
12235 lsm6dsox_int1_ctrl_t int1_ctrl;
12236 lsm6dsox_int2_ctrl_t int2_ctrl;
12237 lsm6dsox_mlc_int1_t mlc_int1;
12238 lsm6dsox_md2_cfg_t md2_cfg;
12239 lsm6dsox_md1_cfg_t md1_cfg;
12240 lsm6dsox_ctrl4_c_t ctrl4_c;
12241 int32_t ret;
12242 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
12243
12244 if (ret == 0)
12245 {
12246 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_INT1,
12247 (uint8_t *)&mlc_int1, 1);
12248 }
12249
12250 if (ret == 0)
12251 {
12252 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INT1,
12253 (uint8_t *)&emb_func_int1, 1);
12254 }
12255
12256 if (ret == 0)
12257 {
12258 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT1_A,
12259 (uint8_t *)&fsm_int1_a, 1);
12260 }
12261
12262 if (ret == 0)
12263 {
12264 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT1_B,
12265 (uint8_t *)&fsm_int1_b, 1);
12266 }
12267
12268 if (ret == 0)
12269 {
12270 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
12271 }
12272
12273 if (ret == 0)
12274 {
12275 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT1_CTRL,
12276 (uint8_t *)&int1_ctrl, 1);
12277 }
12278
12279 if (ret == 0)
12280 {
12281 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD1_CFG, (uint8_t *)&md1_cfg, 1);
12282 }
12283
12284 if (ret == 0)
12285 {
12286 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
12287 }
12288
12289 if (ctrl4_c.int2_on_int1 == PROPERTY_ENABLE)
12290 {
12291 if (ret == 0)
12292 {
12293 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL,
12294 (uint8_t *)&int2_ctrl, 1);
12295 val->drdy_temp = int2_ctrl.int2_drdy_temp;
12296 }
12297
12298 if (ret == 0)
12299 {
12300 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
12301 val->timestamp = md2_cfg.int2_timestamp;
12302 }
12303 }
12304
12305 else
12306 {
12307 val->drdy_temp = PROPERTY_DISABLE;
12308 val->timestamp = PROPERTY_DISABLE;
12309 }
12310
12311 val->drdy_xl = int1_ctrl.int1_drdy_xl;
12312 val->drdy_g = int1_ctrl.int1_drdy_g;
12313 val->boot = int1_ctrl.int1_boot;
12314 val->fifo_th = int1_ctrl.int1_fifo_th;
12315 val->fifo_ovr = int1_ctrl.int1_fifo_ovr;
12316 val->fifo_full = int1_ctrl.int1_fifo_full;
12317 val->fifo_bdr = int1_ctrl.int1_cnt_bdr;
12318 val->den_flag = int1_ctrl.den_drdy_flag;
12319 val->sh_endop = md1_cfg.int1_shub;
12320 val->six_d = md1_cfg.int1_6d;
12321 val->double_tap = md1_cfg.int1_double_tap;
12322 val->free_fall = md1_cfg.int1_ff;
12323 val->wake_up = md1_cfg.int1_wu;
12324 val->single_tap = md1_cfg.int1_single_tap;
12325 val->sleep_change = md1_cfg.int1_sleep_change;
12326 val->step_detector = emb_func_int1.int1_step_detector;
12327 val->tilt = emb_func_int1.int1_tilt;
12328 val->sig_mot = emb_func_int1.int1_sig_mot;
12329 val->fsm_lc = emb_func_int1.int1_fsm_lc;
12330 val->fsm1 = fsm_int1_a.int1_fsm1;
12331 val->fsm2 = fsm_int1_a.int1_fsm2;
12332 val->fsm3 = fsm_int1_a.int1_fsm3;
12333 val->fsm4 = fsm_int1_a.int1_fsm4;
12334 val->fsm5 = fsm_int1_a.int1_fsm5;
12335 val->fsm6 = fsm_int1_a.int1_fsm6;
12336 val->fsm7 = fsm_int1_a.int1_fsm7;
12337 val->fsm8 = fsm_int1_a.int1_fsm8;
12338 val->fsm9 = fsm_int1_b.int1_fsm9;
12339 val->fsm10 = fsm_int1_b.int1_fsm10;
12340 val->fsm11 = fsm_int1_b.int1_fsm11;
12341 val->fsm12 = fsm_int1_b.int1_fsm12;
12342 val->fsm13 = fsm_int1_b.int1_fsm13;
12343 val->fsm14 = fsm_int1_b.int1_fsm14;
12344 val->fsm15 = fsm_int1_b.int1_fsm15;
12345 val->fsm16 = fsm_int1_b.int1_fsm16;
12346 val->mlc1 = mlc_int1.int1_mlc1;
12347 val->mlc2 = mlc_int1.int1_mlc2;
12348 val->mlc3 = mlc_int1.int1_mlc3;
12349 val->mlc4 = mlc_int1.int1_mlc4;
12350 val->mlc5 = mlc_int1.int1_mlc5;
12351 val->mlc6 = mlc_int1.int1_mlc6;
12352 val->mlc7 = mlc_int1.int1_mlc7;
12353 val->mlc8 = mlc_int1.int1_mlc8;
12354
12355 return ret;
12356 }
12357
12358 /**
12359 * @brief Route interrupt signals on int2 pin.[set]
12360 *
12361 * @param ctx communication interface handler. Use NULL to ignore
12362 * this interface.(ptr)
12363 * @param aux_ctx auxiliary communication interface handler. Use NULL
12364 * to ignore this interface.(ptr)
12365 * @param val the signals to route on int2 pin.
12366 * @retval interface status (MANDATORY: return 0 -> no Error)
12367 *
12368 */
lsm6dsox_pin_int2_route_set(const stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dsox_pin_int2_route_t val)12369 int32_t lsm6dsox_pin_int2_route_set(const stmdev_ctx_t *ctx,
12370 stmdev_ctx_t *aux_ctx,
12371 lsm6dsox_pin_int2_route_t val)
12372 {
12373 lsm6dsox_pin_int1_route_t pin_int1_route;
12374 lsm6dsox_emb_func_int2_t emb_func_int2;
12375 lsm6dsox_spi2_int_ois_t spi2_int_ois;
12376 lsm6dsox_fsm_int2_a_t fsm_int2_a;
12377 lsm6dsox_fsm_int2_b_t fsm_int2_b;
12378 lsm6dsox_int2_ctrl_t int2_ctrl;
12379 lsm6dsox_mlc_int2_t mlc_int2;
12380 lsm6dsox_tap_cfg2_t tap_cfg2;
12381 lsm6dsox_md2_cfg_t md2_cfg;
12382 lsm6dsox_ctrl4_c_t ctrl4_c;
12383 int32_t ret;
12384 ret = 0;
12385
12386 if (aux_ctx != NULL)
12387 {
12388 ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_INT_OIS,
12389 (uint8_t *)&spi2_int_ois, 1);
12390
12391 if (ret == 0)
12392 {
12393 spi2_int_ois.int2_drdy_ois = val.drdy_ois;
12394 ret = lsm6dsox_write_reg(aux_ctx, LSM6DSOX_SPI2_INT_OIS,
12395 (uint8_t *)&spi2_int_ois, 1);
12396 }
12397 }
12398
12399 if (ctx != NULL)
12400 {
12401 int2_ctrl.int2_drdy_xl = val.drdy_xl;
12402 int2_ctrl.int2_drdy_g = val.drdy_g;
12403 int2_ctrl.int2_drdy_temp = val.drdy_temp;
12404 int2_ctrl.int2_fifo_th = val.fifo_th;
12405 int2_ctrl.int2_fifo_ovr = val.fifo_ovr;
12406 int2_ctrl.int2_fifo_full = val.fifo_full;
12407 int2_ctrl.int2_cnt_bdr = val.fifo_bdr;
12408 int2_ctrl.not_used_01 = 0;
12409 md2_cfg.int2_timestamp = val.timestamp;
12410 md2_cfg.int2_6d = val.six_d;
12411 md2_cfg.int2_double_tap = val.double_tap;
12412 md2_cfg.int2_ff = val.free_fall;
12413 md2_cfg.int2_wu = val.wake_up;
12414 md2_cfg.int2_single_tap = val.single_tap;
12415 md2_cfg.int2_sleep_change = val.sleep_change;
12416 emb_func_int2.not_used_01 = 0;
12417 emb_func_int2. int2_step_detector = val.step_detector;
12418 emb_func_int2.int2_tilt = val.tilt;
12419 emb_func_int2.int2_sig_mot = val.sig_mot;
12420 emb_func_int2.not_used_02 = 0;
12421 emb_func_int2.int2_fsm_lc = val.fsm_lc;
12422 fsm_int2_a.int2_fsm1 = val.fsm1;
12423 fsm_int2_a.int2_fsm2 = val.fsm2;
12424 fsm_int2_a.int2_fsm3 = val.fsm3;
12425 fsm_int2_a.int2_fsm4 = val.fsm4;
12426 fsm_int2_a.int2_fsm5 = val.fsm5;
12427 fsm_int2_a.int2_fsm6 = val.fsm6;
12428 fsm_int2_a.int2_fsm7 = val.fsm7;
12429 fsm_int2_a.int2_fsm8 = val.fsm8;
12430 fsm_int2_b.int2_fsm9 = val.fsm9 ;
12431 fsm_int2_b.int2_fsm10 = val.fsm10;
12432 fsm_int2_b.int2_fsm11 = val.fsm11;
12433 fsm_int2_b.int2_fsm12 = val.fsm12;
12434 fsm_int2_b.int2_fsm13 = val.fsm13;
12435 fsm_int2_b.int2_fsm14 = val.fsm14;
12436 fsm_int2_b.int2_fsm15 = val.fsm15;
12437 fsm_int2_b.int2_fsm16 = val.fsm16;
12438 mlc_int2.int2_mlc1 = val.mlc1;
12439 mlc_int2.int2_mlc2 = val.mlc2;
12440 mlc_int2.int2_mlc3 = val.mlc3;
12441 mlc_int2.int2_mlc4 = val.mlc4;
12442 mlc_int2.int2_mlc5 = val.mlc5;
12443 mlc_int2.int2_mlc6 = val.mlc6;
12444 mlc_int2.int2_mlc7 = val.mlc7;
12445 mlc_int2.int2_mlc8 = val.mlc8;
12446
12447 if (ret == 0)
12448 {
12449 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
12450
12451 if (ret == 0)
12452 {
12453 if ((val.drdy_temp | val.timestamp) != PROPERTY_DISABLE)
12454 {
12455 ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
12456 }
12457
12458 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
12459 }
12460 }
12461
12462 if (ret == 0)
12463 {
12464 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
12465 }
12466
12467 if (ret == 0)
12468 {
12469 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MLC_INT2,
12470 (uint8_t *)&mlc_int2, 1);
12471 }
12472
12473 if (ret == 0)
12474 {
12475 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_INT2,
12476 (uint8_t *)&emb_func_int2, 1);
12477 }
12478
12479 if (ret == 0)
12480 {
12481 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT2_A,
12482 (uint8_t *)&fsm_int2_a, 1);
12483 }
12484
12485 if (ret == 0)
12486 {
12487 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FSM_INT2_B,
12488 (uint8_t *)&fsm_int2_b, 1);
12489 }
12490
12491 if (ret == 0)
12492 {
12493 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
12494 }
12495
12496 if (ret == 0)
12497 {
12498 if ((emb_func_int2.int2_fsm_lc
12499 | emb_func_int2.int2_sig_mot
12500 | emb_func_int2.int2_step_detector
12501 | emb_func_int2.int2_tilt
12502 | fsm_int2_a.int2_fsm1
12503 | fsm_int2_a.int2_fsm2
12504 | fsm_int2_a.int2_fsm3
12505 | fsm_int2_a.int2_fsm4
12506 | fsm_int2_a.int2_fsm5
12507 | fsm_int2_a.int2_fsm6
12508 | fsm_int2_a.int2_fsm7
12509 | fsm_int2_a.int2_fsm8
12510 | fsm_int2_b.int2_fsm9
12511 | fsm_int2_b.int2_fsm10
12512 | fsm_int2_b.int2_fsm11
12513 | fsm_int2_b.int2_fsm12
12514 | fsm_int2_b.int2_fsm13
12515 | fsm_int2_b.int2_fsm14
12516 | fsm_int2_b.int2_fsm15
12517 | fsm_int2_b.int2_fsm16
12518 | mlc_int2.int2_mlc1
12519 | mlc_int2.int2_mlc2
12520 | mlc_int2.int2_mlc3
12521 | mlc_int2.int2_mlc4
12522 | mlc_int2.int2_mlc5
12523 | mlc_int2.int2_mlc6
12524 | mlc_int2.int2_mlc7
12525 | mlc_int2.int2_mlc8) != PROPERTY_DISABLE)
12526 {
12527 md2_cfg.int2_emb_func = PROPERTY_ENABLE;
12528 }
12529
12530 else
12531 {
12532 md2_cfg.int2_emb_func = PROPERTY_DISABLE;
12533 }
12534
12535 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_INT2_CTRL,
12536 (uint8_t *)&int2_ctrl, 1);
12537 }
12538
12539 if (ret == 0)
12540 {
12541 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
12542 }
12543
12544 if (ret == 0)
12545 {
12546 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
12547 }
12548
12549 if (ret == 0)
12550 {
12551 ret = lsm6dsox_pin_int1_route_get(ctx, &pin_int1_route);
12552 }
12553
12554 if (ret == 0)
12555 {
12556 if ((val.fifo_bdr
12557 | val.drdy_g
12558 | val.drdy_temp
12559 | val.drdy_xl
12560 | val.fifo_full
12561 | val.fifo_ovr
12562 | val.fifo_th
12563 | val.six_d
12564 | val.double_tap
12565 | val.free_fall
12566 | val.wake_up
12567 | val.single_tap
12568 | val.sleep_change
12569 | pin_int1_route.den_flag
12570 | pin_int1_route.boot
12571 | pin_int1_route.fifo_bdr
12572 | pin_int1_route.drdy_g
12573 | pin_int1_route.drdy_xl
12574 | pin_int1_route.fifo_full
12575 | pin_int1_route.fifo_ovr
12576 | pin_int1_route.fifo_th
12577 | pin_int1_route.six_d
12578 | pin_int1_route.double_tap
12579 | pin_int1_route.free_fall
12580 | pin_int1_route.wake_up
12581 | pin_int1_route.single_tap
12582 | pin_int1_route.sleep_change) != PROPERTY_DISABLE)
12583 {
12584 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
12585 }
12586
12587 else
12588 {
12589 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
12590 }
12591
12592 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_TAP_CFG2,
12593 (uint8_t *) &tap_cfg2, 1);
12594 }
12595 }
12596
12597 return ret;
12598 }
12599
12600 /**
12601 * @brief Route interrupt signals on int2 pin.[get]
12602 *
12603 * @param ctx communication interface handler. Use NULL to ignore
12604 * this interface.(ptr)
12605 * @param aux_ctx auxiliary communication interface handler. Use NULL
12606 * to ignore this interface.(ptr)
12607 * @param val the signals that are routed on int2 pin.(ptr)
12608 * @retval interface status (MANDATORY: return 0 -> no Error)
12609 *
12610 */
lsm6dsox_pin_int2_route_get(const stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dsox_pin_int2_route_t * val)12611 int32_t lsm6dsox_pin_int2_route_get(const stmdev_ctx_t *ctx,
12612 stmdev_ctx_t *aux_ctx,
12613 lsm6dsox_pin_int2_route_t *val)
12614 {
12615 lsm6dsox_emb_func_int2_t emb_func_int2;
12616 lsm6dsox_spi2_int_ois_t spi2_int_ois;
12617 lsm6dsox_fsm_int2_a_t fsm_int2_a;
12618 lsm6dsox_fsm_int2_b_t fsm_int2_b;
12619 lsm6dsox_int2_ctrl_t int2_ctrl;
12620 lsm6dsox_mlc_int2_t mlc_int2;
12621 lsm6dsox_md2_cfg_t md2_cfg;
12622 lsm6dsox_ctrl4_c_t ctrl4_c;
12623 int32_t ret;
12624 ret = 0;
12625
12626 if (aux_ctx != NULL)
12627 {
12628 ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_INT_OIS,
12629 (uint8_t *)&spi2_int_ois, 1);
12630 val->drdy_ois = spi2_int_ois.int2_drdy_ois;
12631 }
12632
12633 if (ctx != NULL)
12634 {
12635 if (ret == 0)
12636 {
12637 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
12638 }
12639
12640 if (ret == 0)
12641 {
12642 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MLC_INT2,
12643 (uint8_t *)&mlc_int2, 1);
12644 }
12645
12646 if (ret == 0)
12647 {
12648 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_INT2,
12649 (uint8_t *)&emb_func_int2, 1);
12650 }
12651
12652 if (ret == 0)
12653 {
12654 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT2_A,
12655 (uint8_t *)&fsm_int2_a, 1);
12656 }
12657
12658 if (ret == 0)
12659 {
12660 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_INT2_B,
12661 (uint8_t *)&fsm_int2_b, 1);
12662 }
12663
12664 if (ret == 0)
12665 {
12666 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
12667 }
12668
12669 if (ret == 0)
12670 {
12671 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL,
12672 (uint8_t *)&int2_ctrl, 1);
12673 }
12674
12675 if (ret == 0)
12676 {
12677 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG,
12678 (uint8_t *)&md2_cfg, 1);
12679 }
12680
12681 if (ret == 0)
12682 {
12683 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
12684 }
12685
12686 if (ctrl4_c.int2_on_int1 == PROPERTY_DISABLE)
12687 {
12688 if (ret == 0)
12689 {
12690 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_INT2_CTRL,
12691 (uint8_t *)&int2_ctrl, 1);
12692 val->drdy_temp = int2_ctrl.int2_drdy_temp;
12693 }
12694
12695 if (ret == 0)
12696 {
12697 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_MD2_CFG, (uint8_t *)&md2_cfg, 1);
12698 val->timestamp = md2_cfg.int2_timestamp;
12699 }
12700 }
12701
12702 else
12703 {
12704 val->drdy_temp = PROPERTY_DISABLE;
12705 val->timestamp = PROPERTY_DISABLE;
12706 }
12707
12708 val->drdy_xl = int2_ctrl.int2_drdy_xl;
12709 val->drdy_g = int2_ctrl.int2_drdy_g;
12710 val->drdy_temp = int2_ctrl.int2_drdy_temp;
12711 val->fifo_th = int2_ctrl.int2_fifo_th;
12712 val->fifo_ovr = int2_ctrl.int2_fifo_ovr;
12713 val->fifo_full = int2_ctrl.int2_fifo_full;
12714 val->fifo_bdr = int2_ctrl.int2_cnt_bdr;
12715 val->timestamp = md2_cfg.int2_timestamp;
12716 val->six_d = md2_cfg.int2_6d;
12717 val->double_tap = md2_cfg.int2_double_tap;
12718 val->free_fall = md2_cfg.int2_ff;
12719 val->wake_up = md2_cfg.int2_wu;
12720 val->single_tap = md2_cfg.int2_single_tap;
12721 val->sleep_change = md2_cfg.int2_sleep_change;
12722 val->step_detector = emb_func_int2. int2_step_detector;
12723 val->tilt = emb_func_int2.int2_tilt;
12724 val->fsm_lc = emb_func_int2.int2_fsm_lc;
12725 val->fsm1 = fsm_int2_a.int2_fsm1;
12726 val->fsm2 = fsm_int2_a.int2_fsm2;
12727 val->fsm3 = fsm_int2_a.int2_fsm3;
12728 val->fsm4 = fsm_int2_a.int2_fsm4;
12729 val->fsm5 = fsm_int2_a.int2_fsm5;
12730 val->fsm6 = fsm_int2_a.int2_fsm6;
12731 val->fsm7 = fsm_int2_a.int2_fsm7;
12732 val->fsm8 = fsm_int2_a.int2_fsm8;
12733 val->fsm9 = fsm_int2_b.int2_fsm9;
12734 val->fsm10 = fsm_int2_b.int2_fsm10;
12735 val->fsm11 = fsm_int2_b.int2_fsm11;
12736 val->fsm12 = fsm_int2_b.int2_fsm12;
12737 val->fsm13 = fsm_int2_b.int2_fsm13;
12738 val->fsm14 = fsm_int2_b.int2_fsm14;
12739 val->fsm15 = fsm_int2_b.int2_fsm15;
12740 val->fsm16 = fsm_int2_b.int2_fsm16;
12741 val->mlc1 = mlc_int2.int2_mlc1;
12742 val->mlc2 = mlc_int2.int2_mlc2;
12743 val->mlc3 = mlc_int2.int2_mlc3;
12744 val->mlc4 = mlc_int2.int2_mlc4;
12745 val->mlc5 = mlc_int2.int2_mlc5;
12746 val->mlc6 = mlc_int2.int2_mlc6;
12747 val->mlc7 = mlc_int2.int2_mlc7;
12748 val->mlc8 = mlc_int2.int2_mlc8;
12749 }
12750
12751 return ret;
12752 }
12753
12754 /**
12755 * @brief Get the status of all the interrupt sources.[get]
12756 *
12757 * @param ctx communication interface handler.(ptr)
12758 * @param val the status of all the interrupt sources.(ptr)
12759 * @retval interface status (MANDATORY: return 0 -> no Error)
12760 *
12761 */
lsm6dsox_all_sources_get(const stmdev_ctx_t * ctx,lsm6dsox_all_sources_t * val)12762 int32_t lsm6dsox_all_sources_get(const stmdev_ctx_t *ctx,
12763 lsm6dsox_all_sources_t *val)
12764 {
12765 lsm6dsox_emb_func_status_mainpage_t emb_func_status_mainpage;
12766 lsm6dsox_status_master_mainpage_t status_master_mainpage;
12767 lsm6dsox_fsm_status_a_mainpage_t fsm_status_a_mainpage;
12768 lsm6dsox_fsm_status_b_mainpage_t fsm_status_b_mainpage;
12769 lsm6dsox_mlc_status_mainpage_t mlc_status_mainpage;
12770 lsm6dsox_fifo_status1_t fifo_status1;
12771 lsm6dsox_fifo_status2_t fifo_status2;
12772 lsm6dsox_all_int_src_t all_int_src;
12773 lsm6dsox_wake_up_src_t wake_up_src;
12774 lsm6dsox_status_reg_t status_reg;
12775 lsm6dsox_tap_src_t tap_src;
12776 lsm6dsox_d6d_src_t d6d_src;
12777 lsm6dsox_ctrl5_c_t ctrl5_c;
12778 uint8_t reg[12];
12779 int32_t ret;
12780 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
12781
12782 if (ret == 0)
12783 {
12784 ctrl5_c.rounding_status = PROPERTY_ENABLE;
12785 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
12786 }
12787
12788 if (ret == 0)
12789 {
12790 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_ALL_INT_SRC, reg, 12);
12791 }
12792
12793 if (ret == 0)
12794 {
12795 bytecpy((uint8_t *)&all_int_src, ®[0]);
12796 bytecpy((uint8_t *)&wake_up_src, ®[1]);
12797 bytecpy((uint8_t *)&tap_src, ®[2]);
12798 bytecpy((uint8_t *)&d6d_src, ®[3]);
12799 bytecpy((uint8_t *)&status_reg, ®[4]);
12800 bytecpy((uint8_t *)&emb_func_status_mainpage, ®[5]);
12801 bytecpy((uint8_t *)&fsm_status_a_mainpage, ®[6]);
12802 bytecpy((uint8_t *)&fsm_status_b_mainpage, ®[7]);
12803 bytecpy((uint8_t *)&mlc_status_mainpage, ®[8]);
12804 bytecpy((uint8_t *)&status_master_mainpage, ®[9]);
12805 bytecpy((uint8_t *)&fifo_status1, ®[10]);
12806 bytecpy((uint8_t *)&fifo_status2, ®[11]);
12807 val->timestamp = all_int_src.timestamp_endcount;
12808 val->wake_up_z = wake_up_src.z_wu;
12809 val->wake_up_y = wake_up_src.y_wu;
12810 val->wake_up_x = wake_up_src.x_wu;
12811 val->wake_up = wake_up_src.wu_ia;
12812 val->sleep_state = wake_up_src.sleep_state;
12813 val->free_fall = wake_up_src.ff_ia;
12814 val->sleep_change = wake_up_src.sleep_change_ia;
12815 val->tap_x = tap_src.x_tap;
12816 val->tap_y = tap_src.y_tap;
12817 val->tap_z = tap_src.z_tap;
12818 val->tap_sign = tap_src.tap_sign;
12819 val->double_tap = tap_src.double_tap;
12820 val->single_tap = tap_src.single_tap;
12821 val->six_d_xl = d6d_src.xl;
12822 val->six_d_xh = d6d_src.xh;
12823 val->six_d_yl = d6d_src.yl;
12824 val->six_d_yh = d6d_src.yh;
12825 val->six_d_zl = d6d_src.zl;
12826 val->six_d_zh = d6d_src.zh;
12827 val->six_d = d6d_src.d6d_ia;
12828 val->den_flag = d6d_src.den_drdy;
12829 val->drdy_xl = status_reg.xlda;
12830 val->drdy_g = status_reg.gda;
12831 val->drdy_temp = status_reg.tda;
12832 val->step_detector = emb_func_status_mainpage.is_step_det;
12833 val->tilt = emb_func_status_mainpage.is_tilt;
12834 val->sig_mot = emb_func_status_mainpage.is_sigmot;
12835 val->fsm_lc = emb_func_status_mainpage.is_fsm_lc;
12836 val->fsm1 = fsm_status_a_mainpage.is_fsm1;
12837 val->fsm2 = fsm_status_a_mainpage.is_fsm2;
12838 val->fsm3 = fsm_status_a_mainpage.is_fsm3;
12839 val->fsm4 = fsm_status_a_mainpage.is_fsm4;
12840 val->fsm5 = fsm_status_a_mainpage.is_fsm5;
12841 val->fsm6 = fsm_status_a_mainpage.is_fsm6;
12842 val->fsm7 = fsm_status_a_mainpage.is_fsm7;
12843 val->fsm8 = fsm_status_a_mainpage.is_fsm8;
12844 val->fsm9 = fsm_status_b_mainpage.is_fsm9;
12845 val->fsm10 = fsm_status_b_mainpage.is_fsm10;
12846 val->fsm11 = fsm_status_b_mainpage.is_fsm11;
12847 val->fsm12 = fsm_status_b_mainpage.is_fsm12;
12848 val->fsm13 = fsm_status_b_mainpage.is_fsm13;
12849 val->fsm14 = fsm_status_b_mainpage.is_fsm14;
12850 val->fsm15 = fsm_status_b_mainpage.is_fsm15;
12851 val->fsm16 = fsm_status_b_mainpage.is_fsm16;
12852 val->mlc1 = mlc_status_mainpage.is_mlc1;
12853 val->mlc2 = mlc_status_mainpage.is_mlc2;
12854 val->mlc3 = mlc_status_mainpage.is_mlc3;
12855 val->mlc4 = mlc_status_mainpage.is_mlc4;
12856 val->mlc5 = mlc_status_mainpage.is_mlc5;
12857 val->mlc6 = mlc_status_mainpage.is_mlc6;
12858 val->mlc7 = mlc_status_mainpage.is_mlc7;
12859 val->mlc8 = mlc_status_mainpage.is_mlc8;
12860 val->sh_endop = status_master_mainpage.sens_hub_endop;
12861 val->sh_slave0_nack = status_master_mainpage.slave0_nack;
12862 val->sh_slave1_nack = status_master_mainpage.slave1_nack;
12863 val->sh_slave2_nack = status_master_mainpage.slave2_nack;
12864 val->sh_slave3_nack = status_master_mainpage.slave3_nack;
12865 val->sh_wr_once = status_master_mainpage.wr_once_done;
12866 val->fifo_diff = (256U * fifo_status2.diff_fifo) +
12867 fifo_status1.diff_fifo;
12868 val->fifo_ovr_latched = fifo_status2.over_run_latched;
12869 val->fifo_bdr = fifo_status2.counter_bdr_ia;
12870 val->fifo_full = fifo_status2.fifo_full_ia;
12871 val->fifo_ovr = fifo_status2.fifo_ovr_ia;
12872 val->fifo_th = fifo_status2.fifo_wtm_ia;
12873 ctrl5_c.rounding_status = PROPERTY_DISABLE;
12874 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
12875 }
12876
12877 return ret;
12878 }
12879
12880 /**
12881 * @brief Sensor conversion parameters selection.[set]
12882 *
12883 * @param ctx communication interface handler. Use NULL to ignore
12884 * this interface.(ptr)
12885 * @param aux_ctx auxiliary communication interface handler. Use NULL
12886 * to ignore this interface.(ptr)
12887 * @param val set the sensor conversion parameters by checking
12888 * the constraints of the device.(ptr)
12889 * @retval interface status (MANDATORY: return 0 -> no Error)
12890 *
12891 */
lsm6dsox_mode_set(const stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dsox_md_t * val)12892 int32_t lsm6dsox_mode_set(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
12893 lsm6dsox_md_t *val)
12894 {
12895 lsm6dsox_func_cfg_access_t func_cfg_access;
12896 lsm6dsox_spi2_ctrl1_ois_t spi2_ctrl1_ois = {0};
12897 lsm6dsox_spi2_ctrl2_ois_t spi2_ctrl2_ois = {0};
12898 lsm6dsox_spi2_ctrl3_ois_t spi2_ctrl3_ois = {0};
12899 lsm6dsox_ui_ctrl1_ois_t ui_ctrl1_ois = {0};
12900 lsm6dsox_ui_ctrl2_ois_t ui_ctrl2_ois = {0};
12901 lsm6dsox_ui_ctrl3_ois_t ui_ctrl3_ois = {0};
12902 lsm6dsox_ctrl1_xl_t ctrl1_xl = {0};
12903 lsm6dsox_ctrl8_xl_t ctrl8_xl = {0};
12904 lsm6dsox_ctrl2_g_t ctrl2_g = {0};
12905 lsm6dsox_ctrl3_c_t ctrl3_c = {0};
12906 lsm6dsox_ctrl4_c_t ctrl4_c = {0};
12907 lsm6dsox_ctrl5_c_t ctrl5_c = {0};
12908 lsm6dsox_ctrl6_c_t ctrl6_c = {0};
12909 lsm6dsox_ctrl7_g_t ctrl7_g = {0};
12910 uint8_t xl_hm_mode;
12911 uint8_t g_hm_mode;
12912 uint8_t xl_ulp_en;
12913 uint8_t odr_gy;
12914 uint8_t odr_xl;
12915 uint8_t reg[8];
12916 int32_t ret;
12917
12918 ret = 0;
12919 /* FIXME: Remove warnings with STM32CubeIDE */
12920 ctrl3_c.not_used_01 = 0;
12921 ctrl4_c.not_used_01 = 0;
12922 /* reading input configuration */
12923 xl_hm_mode = ((uint8_t)val->ui.xl.odr & 0x10U) >> 4;
12924 xl_ulp_en = ((uint8_t)val->ui.xl.odr & 0x20U) >> 5;
12925 odr_xl = (uint8_t)val->ui.xl.odr & 0x0FU;
12926
12927 /* if enable xl ultra low power mode disable gy and OIS chain */
12928 if (xl_ulp_en == PROPERTY_ENABLE)
12929 {
12930 val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
12931 val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
12932 val->ui.gy.odr = LSM6DSOX_GY_UI_OFF;
12933 }
12934
12935 /* if OIS xl is enabled also gyro OIS is enabled */
12936 if (val->ois.xl.odr == LSM6DSOX_XL_OIS_6667Hz_HP)
12937 {
12938 val->ois.gy.odr = LSM6DSOX_GY_OIS_6667Hz_HP;
12939 }
12940
12941 g_hm_mode = ((uint8_t)val->ui.gy.odr & 0x10U) >> 4;
12942 odr_gy = (uint8_t)val->ui.gy.odr & 0x0FU;
12943
12944 /* reading registers to be configured */
12945 if (ctx != NULL)
12946 {
12947 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, reg, 8);
12948 bytecpy((uint8_t *)&ctrl1_xl, ®[0]);
12949 bytecpy((uint8_t *)&ctrl2_g, ®[1]);
12950 bytecpy((uint8_t *)&ctrl3_c, ®[2]);
12951 bytecpy((uint8_t *)&ctrl4_c, ®[3]);
12952 bytecpy((uint8_t *)&ctrl5_c, ®[4]);
12953 bytecpy((uint8_t *)&ctrl6_c, ®[5]);
12954 bytecpy((uint8_t *)&ctrl7_g, ®[6]);
12955 bytecpy((uint8_t *)&ctrl8_xl, ®[7]);
12956
12957 if (ret == 0)
12958 {
12959 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
12960 (uint8_t *)&func_cfg_access, 1);
12961 }
12962
12963 /* if toggle xl ultra low power mode, turn off xl before reconfigure */
12964 if (ctrl5_c.xl_ulp_en != xl_ulp_en)
12965 {
12966 ctrl1_xl.odr_xl = (uint8_t) 0x00U;
12967 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL,
12968 (uint8_t *)&ctrl1_xl, 1);
12969 }
12970 }
12971
12972 /* reading OIS registers to be configured */
12973 if (aux_ctx != NULL)
12974 {
12975 if (ret == 0)
12976 {
12977 ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS, reg, 3);
12978 }
12979
12980 bytecpy((uint8_t *)&spi2_ctrl1_ois, ®[0]);
12981 bytecpy((uint8_t *)&spi2_ctrl2_ois, ®[1]);
12982 bytecpy((uint8_t *)&spi2_ctrl3_ois, ®[2]);
12983 }
12984
12985 else
12986 {
12987 if (ctx != NULL)
12988 {
12989 if (ret == 0)
12990 {
12991 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, reg, 3);
12992 }
12993
12994 bytecpy((uint8_t *)&ui_ctrl1_ois, ®[0]);
12995 bytecpy((uint8_t *)&ui_ctrl2_ois, ®[1]);
12996 bytecpy((uint8_t *)&ui_ctrl3_ois, ®[2]);
12997 }
12998 }
12999
13000 /* Check the Finite State Machine data rate constraints */
13001 if (val->fsm.sens != LSM6DSOX_FSM_DISABLE)
13002 {
13003 switch (val->fsm.odr)
13004 {
13005 case LSM6DSOX_ODR_FSM_12Hz5:
13006 if ((val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl == 0x00U))
13007 {
13008 odr_xl = 0x01U;
13009 }
13010
13011 if ((val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy == 0x00U))
13012 {
13013 xl_ulp_en = PROPERTY_DISABLE;
13014 odr_gy = 0x01U;
13015 }
13016
13017 break;
13018
13019 case LSM6DSOX_ODR_FSM_26Hz:
13020 if ((val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl < 0x02U))
13021 {
13022 odr_xl = 0x02U;
13023 }
13024
13025 if ((val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy < 0x02U))
13026 {
13027 xl_ulp_en = PROPERTY_DISABLE;
13028 odr_gy = 0x02U;
13029 }
13030
13031 break;
13032
13033 case LSM6DSOX_ODR_FSM_52Hz:
13034 if ((val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl < 0x03U))
13035 {
13036 odr_xl = 0x03U;
13037 }
13038
13039 if ((val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy < 0x03U))
13040 {
13041 xl_ulp_en = PROPERTY_DISABLE;
13042 odr_gy = 0x03U;
13043 }
13044
13045 break;
13046
13047 case LSM6DSOX_ODR_FSM_104Hz:
13048 if ((val->fsm.sens != LSM6DSOX_FSM_GY) && (odr_xl < 0x04U))
13049 {
13050 odr_xl = 0x04U;
13051 }
13052
13053 if ((val->fsm.sens != LSM6DSOX_FSM_XL) && (odr_gy < 0x04U))
13054 {
13055 xl_ulp_en = PROPERTY_DISABLE;
13056 odr_gy = 0x04U;
13057 }
13058
13059 break;
13060
13061 default:
13062 odr_xl = 0x00U;
13063 odr_gy = 0x00U;
13064 break;
13065 }
13066 }
13067
13068 /* Check the Machine Learning Core data rate constraints */
13069 if (val->mlc.sens != LSM6DSOX_MLC_DISABLE)
13070 {
13071 switch (val->mlc.odr)
13072 {
13073 case LSM6DSOX_ODR_PRGS_12Hz5:
13074 if (odr_xl == 0x00U)
13075 {
13076 odr_xl = 0x01U;
13077 }
13078
13079 if ((val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy == 0x00U))
13080 {
13081 xl_ulp_en = PROPERTY_DISABLE;
13082 odr_gy = 0x01U;
13083 }
13084
13085 break;
13086
13087 case LSM6DSOX_ODR_PRGS_26Hz:
13088 if (odr_xl < 0x02U)
13089 {
13090 odr_xl = 0x02U;
13091 }
13092
13093 if ((val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy < 0x02U))
13094 {
13095 xl_ulp_en = PROPERTY_DISABLE;
13096 odr_gy = 0x02U;
13097 }
13098
13099 break;
13100
13101 case LSM6DSOX_ODR_PRGS_52Hz:
13102 if (odr_xl < 0x03U)
13103 {
13104 odr_xl = 0x03U;
13105 }
13106
13107 if ((val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy < 0x03U))
13108 {
13109 xl_ulp_en = PROPERTY_DISABLE;
13110 odr_gy = 0x03U;
13111 }
13112
13113 break;
13114
13115 case LSM6DSOX_ODR_PRGS_104Hz:
13116 if (odr_xl < 0x04U)
13117 {
13118 odr_xl = 0x04U;
13119 }
13120
13121 if ((val->mlc.sens != LSM6DSOX_MLC_XL) && (odr_gy < 0x04U))
13122 {
13123 xl_ulp_en = PROPERTY_DISABLE;
13124 odr_gy = 0x04U;
13125 }
13126
13127 break;
13128
13129 default:
13130 odr_xl = 0x00U;
13131 odr_gy = 0x00U;
13132 break;
13133 }
13134 }
13135
13136 /* Updating the accelerometer data rate configuration */
13137 switch ((ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
13138 ctrl1_xl.odr_xl)
13139 {
13140 case LSM6DSOX_XL_UI_OFF:
13141 val->ui.xl.odr = LSM6DSOX_XL_UI_OFF;
13142 break;
13143
13144 case LSM6DSOX_XL_UI_12Hz5_HP:
13145 val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_HP;
13146 break;
13147
13148 case LSM6DSOX_XL_UI_26Hz_HP:
13149 val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_HP;
13150 break;
13151
13152 case LSM6DSOX_XL_UI_52Hz_HP:
13153 val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_HP;
13154 break;
13155
13156 case LSM6DSOX_XL_UI_104Hz_HP:
13157 val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_HP;
13158 break;
13159
13160 case LSM6DSOX_XL_UI_208Hz_HP:
13161 val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_HP;
13162 break;
13163
13164 case LSM6DSOX_XL_UI_416Hz_HP:
13165 val->ui.xl.odr = LSM6DSOX_XL_UI_416Hz_HP;
13166 break;
13167
13168 case LSM6DSOX_XL_UI_833Hz_HP:
13169 val->ui.xl.odr = LSM6DSOX_XL_UI_833Hz_HP;
13170 break;
13171
13172 case LSM6DSOX_XL_UI_1667Hz_HP:
13173 val->ui.xl.odr = LSM6DSOX_XL_UI_1667Hz_HP;
13174 break;
13175
13176 case LSM6DSOX_XL_UI_3333Hz_HP:
13177 val->ui.xl.odr = LSM6DSOX_XL_UI_3333Hz_HP;
13178 break;
13179
13180 case LSM6DSOX_XL_UI_6667Hz_HP:
13181 val->ui.xl.odr = LSM6DSOX_XL_UI_6667Hz_HP;
13182 break;
13183
13184 case LSM6DSOX_XL_UI_1Hz6_LP:
13185 val->ui.xl.odr = LSM6DSOX_XL_UI_1Hz6_LP;
13186 break;
13187
13188 case LSM6DSOX_XL_UI_12Hz5_LP:
13189 val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_LP;
13190 break;
13191
13192 case LSM6DSOX_XL_UI_26Hz_LP:
13193 val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_LP;
13194 break;
13195
13196 case LSM6DSOX_XL_UI_52Hz_LP:
13197 val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_LP;
13198 break;
13199
13200 case LSM6DSOX_XL_UI_104Hz_NM:
13201 val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_NM;
13202 break;
13203
13204 case LSM6DSOX_XL_UI_208Hz_NM:
13205 val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_NM;
13206 break;
13207
13208 case LSM6DSOX_XL_UI_1Hz6_ULP:
13209 val->ui.xl.odr = LSM6DSOX_XL_UI_1Hz6_ULP;
13210 break;
13211
13212 case LSM6DSOX_XL_UI_12Hz5_ULP:
13213 val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_ULP;
13214 break;
13215
13216 case LSM6DSOX_XL_UI_26Hz_ULP:
13217 val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_ULP;
13218 break;
13219
13220 case LSM6DSOX_XL_UI_52Hz_ULP:
13221 val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_ULP;
13222 break;
13223
13224 case LSM6DSOX_XL_UI_104Hz_ULP:
13225 val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_ULP;
13226 break;
13227
13228 case LSM6DSOX_XL_UI_208Hz_ULP:
13229 val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_ULP;
13230 break;
13231
13232 default:
13233 val->ui.xl.odr = LSM6DSOX_XL_UI_OFF;
13234 break;
13235 }
13236
13237 /* Updating the accelerometer data rate configuration */
13238 switch ((ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g)
13239 {
13240 case LSM6DSOX_GY_UI_OFF:
13241 val->ui.gy.odr = LSM6DSOX_GY_UI_OFF;
13242 break;
13243
13244 case LSM6DSOX_GY_UI_12Hz5_LP:
13245 val->ui.gy.odr = LSM6DSOX_GY_UI_12Hz5_LP;
13246 break;
13247
13248 case LSM6DSOX_GY_UI_12Hz5_HP:
13249 val->ui.gy.odr = LSM6DSOX_GY_UI_12Hz5_HP;
13250 break;
13251
13252 case LSM6DSOX_GY_UI_26Hz_LP:
13253 val->ui.gy.odr = LSM6DSOX_GY_UI_26Hz_LP;
13254 break;
13255
13256 case LSM6DSOX_GY_UI_26Hz_HP:
13257 val->ui.gy.odr = LSM6DSOX_GY_UI_26Hz_HP;
13258 break;
13259
13260 case LSM6DSOX_GY_UI_52Hz_LP:
13261 val->ui.gy.odr = LSM6DSOX_GY_UI_52Hz_LP;
13262 break;
13263
13264 case LSM6DSOX_GY_UI_52Hz_HP:
13265 val->ui.gy.odr = LSM6DSOX_GY_UI_52Hz_HP;
13266 break;
13267
13268 case LSM6DSOX_GY_UI_104Hz_NM:
13269 val->ui.gy.odr = LSM6DSOX_GY_UI_104Hz_NM;
13270 break;
13271
13272 case LSM6DSOX_GY_UI_104Hz_HP:
13273 val->ui.gy.odr = LSM6DSOX_GY_UI_104Hz_HP;
13274 break;
13275
13276 case LSM6DSOX_GY_UI_208Hz_NM:
13277 val->ui.gy.odr = LSM6DSOX_GY_UI_208Hz_NM;
13278 break;
13279
13280 case LSM6DSOX_GY_UI_208Hz_HP:
13281 val->ui.gy.odr = LSM6DSOX_GY_UI_208Hz_HP;
13282 break;
13283
13284 case LSM6DSOX_GY_UI_416Hz_HP:
13285 val->ui.gy.odr = LSM6DSOX_GY_UI_416Hz_HP;
13286 break;
13287
13288 case LSM6DSOX_GY_UI_833Hz_HP:
13289 val->ui.gy.odr = LSM6DSOX_GY_UI_833Hz_HP;
13290 break;
13291
13292 case LSM6DSOX_GY_UI_1667Hz_HP:
13293 val->ui.gy.odr = LSM6DSOX_GY_UI_1667Hz_HP;
13294 break;
13295
13296 case LSM6DSOX_GY_UI_3333Hz_HP:
13297 val->ui.gy.odr = LSM6DSOX_GY_UI_3333Hz_HP;
13298 break;
13299
13300 case LSM6DSOX_GY_UI_6667Hz_HP:
13301 val->ui.gy.odr = LSM6DSOX_GY_UI_6667Hz_HP;
13302 break;
13303
13304 default:
13305 val->ui.gy.odr = LSM6DSOX_GY_UI_OFF;
13306 break;
13307 }
13308
13309 /* Check accelerometer full scale constraints */
13310 /* Full scale of 16g must be the same for UI and OIS */
13311 if ((val->ui.xl.fs == LSM6DSOX_XL_UI_16g) ||
13312 (val->ois.xl.fs == LSM6DSOX_XL_OIS_16g))
13313 {
13314 val->ui.xl.fs = LSM6DSOX_XL_UI_16g;
13315 val->ois.xl.fs = LSM6DSOX_XL_OIS_16g;
13316 }
13317
13318 /* prapare new configuration */
13319
13320 /* Full scale of 16g must be the same for UI and OIS */
13321 if (val->ui.xl.fs == LSM6DSOX_XL_UI_16g)
13322 {
13323 ctrl8_xl.xl_fs_mode = PROPERTY_DISABLE;
13324 }
13325
13326 else
13327 {
13328 ctrl8_xl.xl_fs_mode = PROPERTY_ENABLE;
13329 }
13330
13331 /* OIS new configuration */
13332 ctrl7_g.ois_on_en = val->ois.ctrl_md & 0x01U;
13333 func_cfg_access.ois_ctrl_from_ui = (val->ois.ctrl_md & 0x02U) >> 1;
13334
13335 switch (val->ois.ctrl_md)
13336 {
13337 case LSM6DSOX_OIS_ONLY_AUX:
13338 spi2_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
13339 spi2_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr |
13340 (uint8_t)val->ois.xl.odr;
13341 spi2_ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
13342 spi2_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
13343 break;
13344
13345 case LSM6DSOX_OIS_ONLY_UI:
13346 ui_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
13347 ui_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr |
13348 (uint8_t)val->ois.xl.odr;
13349 ui_ctrl1_ois.mode4_en = (uint8_t)val->ois.xl.odr;
13350 ui_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
13351 break;
13352
13353 case LSM6DSOX_OIS_MIXED:
13354 spi2_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
13355 ctrl7_g.ois_on = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr;
13356 spi2_ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
13357 spi2_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
13358 break;
13359
13360 default:
13361 spi2_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
13362 spi2_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr |
13363 (uint8_t)val->ois.xl.odr;
13364 spi2_ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
13365 spi2_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
13366 break;
13367 }
13368
13369 /* UI new configuration */
13370 ctrl1_xl.odr_xl = odr_xl;
13371 ctrl1_xl.fs_xl = (uint8_t)val->ui.xl.fs;
13372 ctrl5_c.xl_ulp_en = xl_ulp_en;
13373 ctrl6_c.xl_hm_mode = xl_hm_mode;
13374 ctrl7_g.g_hm_mode = g_hm_mode;
13375 ctrl2_g.odr_g = odr_gy;
13376 ctrl2_g.fs_g = (uint8_t) val->ui.gy.fs;
13377
13378 /* writing checked configuration */
13379 if (ctx != NULL)
13380 {
13381 bytecpy(®[0], (uint8_t *)&ctrl1_xl);
13382 bytecpy(®[1], (uint8_t *)&ctrl2_g);
13383 bytecpy(®[2], (uint8_t *)&ctrl3_c);
13384 bytecpy(®[3], (uint8_t *)&ctrl4_c);
13385 bytecpy(®[4], (uint8_t *)&ctrl5_c);
13386 bytecpy(®[5], (uint8_t *)&ctrl6_c);
13387 bytecpy(®[6], (uint8_t *)&ctrl7_g);
13388 bytecpy(®[7], (uint8_t *)&ctrl8_xl);
13389
13390 if (ret == 0)
13391 {
13392 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_CTRL1_XL, (uint8_t *)®, 8);
13393 }
13394
13395 if (ret == 0)
13396 {
13397 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
13398 (uint8_t *)&func_cfg_access, 1);
13399 }
13400 }
13401
13402 /* writing OIS checked configuration */
13403 if (aux_ctx != NULL)
13404 {
13405 bytecpy(®[0], (uint8_t *)&spi2_ctrl1_ois);
13406 bytecpy(®[1], (uint8_t *)&spi2_ctrl2_ois);
13407 bytecpy(®[2], (uint8_t *)&spi2_ctrl3_ois);
13408
13409 if (ret == 0)
13410 {
13411 ret = lsm6dsox_write_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS, reg, 3);
13412 }
13413 }
13414
13415 else
13416 {
13417 if (ctx != NULL)
13418 {
13419 bytecpy(®[0], (uint8_t *)&ui_ctrl1_ois);
13420 bytecpy(®[1], (uint8_t *)&ui_ctrl2_ois);
13421 bytecpy(®[2], (uint8_t *)&ui_ctrl3_ois);
13422
13423 if (ret == 0)
13424 {
13425 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, reg, 3);
13426 }
13427 }
13428 }
13429
13430 return ret;
13431 }
13432
13433 /**
13434 * @brief Sensor conversion parameters selection.[get]
13435 *
13436 * @param ctx communication interface handler. Use NULL to ignore
13437 * this interface.(ptr)
13438 * @param aux_ctx auxiliary communication interface handler. Use NULL
13439 * to ignore this interface.(ptr)
13440 * @param val get the sensor conversion parameters.(ptr)
13441 * @retval interface status (MANDATORY: return 0 -> no Error)
13442 *
13443 */
lsm6dsox_mode_get(const stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dsox_md_t * val)13444 int32_t lsm6dsox_mode_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
13445 lsm6dsox_md_t *val)
13446 {
13447 lsm6dsox_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
13448 lsm6dsox_emb_func_odr_cfg_c_t emb_func_odr_cfg_c;
13449 lsm6dsox_func_cfg_access_t func_cfg_access;
13450 lsm6dsox_spi2_ctrl1_ois_t spi2_ctrl1_ois;
13451 lsm6dsox_spi2_ctrl2_ois_t spi2_ctrl2_ois;
13452 lsm6dsox_spi2_ctrl3_ois_t spi2_ctrl3_ois;
13453 lsm6dsox_emb_func_en_b_t emb_func_en_b;
13454 lsm6dsox_ui_ctrl1_ois_t ui_ctrl1_ois;
13455 lsm6dsox_ui_ctrl2_ois_t ui_ctrl2_ois;
13456 lsm6dsox_ui_ctrl3_ois_t ui_ctrl3_ois;
13457 lsm6dsox_fsm_enable_a_t fsm_enable_a;
13458 lsm6dsox_fsm_enable_b_t fsm_enable_b;
13459 lsm6dsox_ctrl1_xl_t ctrl1_xl;
13460 lsm6dsox_ctrl2_g_t ctrl2_g;
13461 lsm6dsox_ctrl3_c_t ctrl3_c;
13462 lsm6dsox_ctrl4_c_t ctrl4_c;
13463 lsm6dsox_ctrl5_c_t ctrl5_c;
13464 lsm6dsox_ctrl6_c_t ctrl6_c;
13465 lsm6dsox_ctrl7_g_t ctrl7_g;
13466 uint8_t reg[8];
13467 int32_t ret;
13468
13469 ret = 0;
13470
13471 /* reading the registers of the device */
13472 if (ctx != NULL)
13473 {
13474 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_CTRL1_XL, reg, 7);
13475 bytecpy((uint8_t *)&ctrl1_xl, ®[0]);
13476 bytecpy((uint8_t *)&ctrl2_g, ®[1]);
13477 bytecpy((uint8_t *)&ctrl3_c, ®[2]);
13478 bytecpy((uint8_t *)&ctrl4_c, ®[3]);
13479 bytecpy((uint8_t *)&ctrl5_c, ®[4]);
13480 bytecpy((uint8_t *)&ctrl6_c, ®[5]);
13481 bytecpy((uint8_t *)&ctrl7_g, ®[6]);
13482
13483 if (ret == 0)
13484 {
13485 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FUNC_CFG_ACCESS,
13486 (uint8_t *)&func_cfg_access, 1);
13487 }
13488
13489 if (ret == 0)
13490 {
13491 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
13492 }
13493
13494 if (ret == 0)
13495 {
13496 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_ODR_CFG_B, reg, 2);
13497 bytecpy((uint8_t *)&emb_func_odr_cfg_b, ®[0]);
13498 bytecpy((uint8_t *)&emb_func_odr_cfg_c, ®[1]);
13499 }
13500
13501 if (ret == 0)
13502 {
13503 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
13504 (uint8_t *)&emb_func_en_b, 1);
13505 }
13506
13507 if (ret == 0)
13508 {
13509 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_FSM_ENABLE_A, reg, 2);
13510 bytecpy((uint8_t *)&fsm_enable_a, ®[0]);
13511 bytecpy((uint8_t *)&fsm_enable_b, ®[1]);
13512 }
13513
13514 if (ret == 0)
13515 {
13516 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
13517 }
13518 }
13519
13520 if (aux_ctx != NULL)
13521 {
13522 if (ret == 0)
13523 {
13524 ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_CTRL1_OIS, reg, 3);
13525 }
13526
13527 bytecpy((uint8_t *)&spi2_ctrl1_ois, ®[0]);
13528 bytecpy((uint8_t *)&spi2_ctrl2_ois, ®[1]);
13529 bytecpy((uint8_t *)&spi2_ctrl3_ois, ®[2]);
13530 }
13531
13532 else
13533 {
13534 if (ctx != NULL)
13535 {
13536 if (ret == 0)
13537 {
13538 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_CTRL1_OIS, reg, 3);
13539 }
13540
13541 bytecpy((uint8_t *)&ui_ctrl1_ois, ®[0]);
13542 bytecpy((uint8_t *)&ui_ctrl2_ois, ®[1]);
13543 bytecpy((uint8_t *)&ui_ctrl3_ois, ®[2]);
13544 }
13545 }
13546
13547 /* fill the input structure */
13548
13549 /* get accelerometer configuration */
13550 switch ((ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
13551 ctrl1_xl.odr_xl)
13552 {
13553 case LSM6DSOX_XL_UI_OFF:
13554 val->ui.xl.odr = LSM6DSOX_XL_UI_OFF;
13555 break;
13556
13557 case LSM6DSOX_XL_UI_12Hz5_HP:
13558 val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_HP;
13559 break;
13560
13561 case LSM6DSOX_XL_UI_26Hz_HP:
13562 val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_HP;
13563 break;
13564
13565 case LSM6DSOX_XL_UI_52Hz_HP:
13566 val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_HP;
13567 break;
13568
13569 case LSM6DSOX_XL_UI_104Hz_HP:
13570 val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_HP;
13571 break;
13572
13573 case LSM6DSOX_XL_UI_208Hz_HP:
13574 val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_HP;
13575 break;
13576
13577 case LSM6DSOX_XL_UI_416Hz_HP:
13578 val->ui.xl.odr = LSM6DSOX_XL_UI_416Hz_HP;
13579 break;
13580
13581 case LSM6DSOX_XL_UI_833Hz_HP:
13582 val->ui.xl.odr = LSM6DSOX_XL_UI_833Hz_HP;
13583 break;
13584
13585 case LSM6DSOX_XL_UI_1667Hz_HP:
13586 val->ui.xl.odr = LSM6DSOX_XL_UI_1667Hz_HP;
13587 break;
13588
13589 case LSM6DSOX_XL_UI_3333Hz_HP:
13590 val->ui.xl.odr = LSM6DSOX_XL_UI_3333Hz_HP;
13591 break;
13592
13593 case LSM6DSOX_XL_UI_6667Hz_HP:
13594 val->ui.xl.odr = LSM6DSOX_XL_UI_6667Hz_HP;
13595 break;
13596
13597 case LSM6DSOX_XL_UI_1Hz6_LP:
13598 val->ui.xl.odr = LSM6DSOX_XL_UI_1Hz6_LP;
13599 break;
13600
13601 case LSM6DSOX_XL_UI_12Hz5_LP:
13602 val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_LP;
13603 break;
13604
13605 case LSM6DSOX_XL_UI_26Hz_LP:
13606 val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_LP;
13607 break;
13608
13609 case LSM6DSOX_XL_UI_52Hz_LP:
13610 val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_LP;
13611 break;
13612
13613 case LSM6DSOX_XL_UI_104Hz_NM:
13614 val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_NM;
13615 break;
13616
13617 case LSM6DSOX_XL_UI_208Hz_NM:
13618 val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_NM;
13619 break;
13620
13621 case LSM6DSOX_XL_UI_1Hz6_ULP:
13622 val->ui.xl.odr = LSM6DSOX_XL_UI_1Hz6_ULP;
13623 break;
13624
13625 case LSM6DSOX_XL_UI_12Hz5_ULP:
13626 val->ui.xl.odr = LSM6DSOX_XL_UI_12Hz5_ULP;
13627 break;
13628
13629 case LSM6DSOX_XL_UI_26Hz_ULP:
13630 val->ui.xl.odr = LSM6DSOX_XL_UI_26Hz_ULP;
13631 break;
13632
13633 case LSM6DSOX_XL_UI_52Hz_ULP:
13634 val->ui.xl.odr = LSM6DSOX_XL_UI_52Hz_ULP;
13635 break;
13636
13637 case LSM6DSOX_XL_UI_104Hz_ULP:
13638 val->ui.xl.odr = LSM6DSOX_XL_UI_104Hz_ULP;
13639 break;
13640
13641 case LSM6DSOX_XL_UI_208Hz_ULP:
13642 val->ui.xl.odr = LSM6DSOX_XL_UI_208Hz_ULP;
13643 break;
13644
13645 default:
13646 val->ui.xl.odr = LSM6DSOX_XL_UI_OFF;
13647 break;
13648 }
13649
13650 switch (ctrl1_xl.fs_xl)
13651 {
13652 case LSM6DSOX_XL_UI_2g:
13653 val->ui.xl.fs = LSM6DSOX_XL_UI_2g;
13654 break;
13655
13656 case LSM6DSOX_XL_UI_4g:
13657 val->ui.xl.fs = LSM6DSOX_XL_UI_4g;
13658 break;
13659
13660 case LSM6DSOX_XL_UI_8g:
13661 val->ui.xl.fs = LSM6DSOX_XL_UI_8g;
13662 break;
13663
13664 case LSM6DSOX_XL_UI_16g:
13665 val->ui.xl.fs = LSM6DSOX_XL_UI_16g;
13666 break;
13667
13668 default:
13669 val->ui.xl.fs = LSM6DSOX_XL_UI_2g;
13670 break;
13671 }
13672
13673 /* get gyroscope configuration */
13674 switch ((ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g)
13675 {
13676 case LSM6DSOX_GY_UI_OFF:
13677 val->ui.gy.odr = LSM6DSOX_GY_UI_OFF;
13678 break;
13679
13680 case LSM6DSOX_GY_UI_12Hz5_LP:
13681 val->ui.gy.odr = LSM6DSOX_GY_UI_12Hz5_LP;
13682 break;
13683
13684 case LSM6DSOX_GY_UI_12Hz5_HP:
13685 val->ui.gy.odr = LSM6DSOX_GY_UI_12Hz5_HP;
13686 break;
13687
13688 case LSM6DSOX_GY_UI_26Hz_LP:
13689 val->ui.gy.odr = LSM6DSOX_GY_UI_26Hz_LP;
13690 break;
13691
13692 case LSM6DSOX_GY_UI_26Hz_HP:
13693 val->ui.gy.odr = LSM6DSOX_GY_UI_26Hz_HP;
13694 break;
13695
13696 case LSM6DSOX_GY_UI_52Hz_LP:
13697 val->ui.gy.odr = LSM6DSOX_GY_UI_52Hz_LP;
13698 break;
13699
13700 case LSM6DSOX_GY_UI_52Hz_HP:
13701 val->ui.gy.odr = LSM6DSOX_GY_UI_52Hz_HP;
13702 break;
13703
13704 case LSM6DSOX_GY_UI_104Hz_NM:
13705 val->ui.gy.odr = LSM6DSOX_GY_UI_104Hz_NM;
13706 break;
13707
13708 case LSM6DSOX_GY_UI_104Hz_HP:
13709 val->ui.gy.odr = LSM6DSOX_GY_UI_104Hz_HP;
13710 break;
13711
13712 case LSM6DSOX_GY_UI_208Hz_NM:
13713 val->ui.gy.odr = LSM6DSOX_GY_UI_208Hz_NM;
13714 break;
13715
13716 case LSM6DSOX_GY_UI_208Hz_HP:
13717 val->ui.gy.odr = LSM6DSOX_GY_UI_208Hz_HP;
13718 break;
13719
13720 case LSM6DSOX_GY_UI_416Hz_HP:
13721 val->ui.gy.odr = LSM6DSOX_GY_UI_416Hz_HP;
13722 break;
13723
13724 case LSM6DSOX_GY_UI_833Hz_HP:
13725 val->ui.gy.odr = LSM6DSOX_GY_UI_833Hz_HP;
13726 break;
13727
13728 case LSM6DSOX_GY_UI_1667Hz_HP:
13729 val->ui.gy.odr = LSM6DSOX_GY_UI_1667Hz_HP;
13730 break;
13731
13732 case LSM6DSOX_GY_UI_3333Hz_HP:
13733 val->ui.gy.odr = LSM6DSOX_GY_UI_3333Hz_HP;
13734 break;
13735
13736 case LSM6DSOX_GY_UI_6667Hz_HP:
13737 val->ui.gy.odr = LSM6DSOX_GY_UI_6667Hz_HP;
13738 break;
13739
13740 default:
13741 val->ui.gy.odr = LSM6DSOX_GY_UI_OFF;
13742 break;
13743 }
13744
13745 switch (ctrl2_g.fs_g)
13746 {
13747 case LSM6DSOX_GY_UI_125dps:
13748 val->ui.gy.fs = LSM6DSOX_GY_UI_125dps;
13749 break;
13750
13751 case LSM6DSOX_GY_UI_250dps:
13752 val->ui.gy.fs = LSM6DSOX_GY_UI_250dps;
13753 break;
13754
13755 case LSM6DSOX_GY_UI_500dps:
13756 val->ui.gy.fs = LSM6DSOX_GY_UI_500dps;
13757 break;
13758
13759 case LSM6DSOX_GY_UI_1000dps:
13760 val->ui.gy.fs = LSM6DSOX_GY_UI_1000dps;
13761 break;
13762
13763 case LSM6DSOX_GY_UI_2000dps:
13764 val->ui.gy.fs = LSM6DSOX_GY_UI_2000dps;
13765 break;
13766
13767 default:
13768 val->ui.gy.fs = LSM6DSOX_GY_UI_125dps;
13769 break;
13770 }
13771
13772 /* get finite state machine configuration */
13773 if ((fsm_enable_a.fsm1_en | fsm_enable_a.fsm2_en |
13774 fsm_enable_a.fsm3_en |
13775 fsm_enable_a.fsm4_en | fsm_enable_a.fsm5_en | fsm_enable_a.fsm6_en |
13776 fsm_enable_a.fsm7_en | fsm_enable_a.fsm8_en | fsm_enable_b.fsm9_en |
13777 fsm_enable_b.fsm10_en | fsm_enable_b.fsm11_en |
13778 fsm_enable_b.fsm12_en | fsm_enable_b.fsm13_en |
13779 fsm_enable_b.fsm14_en | fsm_enable_b.fsm15_en |
13780 fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
13781 {
13782 switch (emb_func_odr_cfg_b.fsm_odr)
13783 {
13784 case LSM6DSOX_ODR_FSM_12Hz5:
13785 val->fsm.odr = LSM6DSOX_ODR_FSM_12Hz5;
13786 break;
13787
13788 case LSM6DSOX_ODR_FSM_26Hz:
13789 val->fsm.odr = LSM6DSOX_ODR_FSM_26Hz;
13790 break;
13791
13792 case LSM6DSOX_ODR_FSM_52Hz:
13793 val->fsm.odr = LSM6DSOX_ODR_FSM_52Hz;
13794 break;
13795
13796 case LSM6DSOX_ODR_FSM_104Hz:
13797 val->fsm.odr = LSM6DSOX_ODR_FSM_104Hz;
13798 break;
13799
13800 default:
13801 val->fsm.odr = LSM6DSOX_ODR_FSM_12Hz5;
13802 break;
13803 }
13804
13805 val->fsm.sens = LSM6DSOX_FSM_XL_GY;
13806
13807 if (val->ui.gy.odr == LSM6DSOX_GY_UI_OFF)
13808 {
13809 val->fsm.sens = LSM6DSOX_FSM_XL;
13810 }
13811
13812 if (val->ui.xl.odr == LSM6DSOX_XL_UI_OFF)
13813 {
13814 val->fsm.sens = LSM6DSOX_FSM_GY;
13815 }
13816 }
13817
13818 else
13819 {
13820 val->fsm.sens = LSM6DSOX_FSM_DISABLE;
13821 }
13822
13823 /* get machine learning core configuration */
13824 if (emb_func_en_b.mlc_en == PROPERTY_ENABLE)
13825 {
13826 switch (emb_func_odr_cfg_c.mlc_odr)
13827 {
13828 case LSM6DSOX_ODR_PRGS_12Hz5:
13829 val->mlc.odr = LSM6DSOX_ODR_PRGS_12Hz5;
13830 break;
13831
13832 case LSM6DSOX_ODR_PRGS_26Hz:
13833 val->mlc.odr = LSM6DSOX_ODR_PRGS_26Hz;
13834 break;
13835
13836 case LSM6DSOX_ODR_PRGS_52Hz:
13837 val->mlc.odr = LSM6DSOX_ODR_PRGS_52Hz;
13838 break;
13839
13840 case LSM6DSOX_ODR_PRGS_104Hz:
13841 val->mlc.odr = LSM6DSOX_ODR_PRGS_104Hz;
13842 break;
13843
13844 default:
13845 val->mlc.odr = LSM6DSOX_ODR_PRGS_12Hz5;
13846 break;
13847 }
13848
13849 val->mlc.sens = LSM6DSOX_MLC_XL_GY;
13850
13851 if (val->ui.gy.odr == LSM6DSOX_GY_UI_OFF)
13852 {
13853 val->mlc.sens = LSM6DSOX_MLC_XL;
13854 }
13855
13856 if (val->ui.xl.odr == LSM6DSOX_XL_UI_OFF)
13857 {
13858 val->mlc.sens = LSM6DSOX_MLC_DISABLE;
13859 }
13860 }
13861
13862 else
13863 {
13864 val->mlc.sens = LSM6DSOX_MLC_DISABLE;
13865 }
13866
13867 /* get ois configuration */
13868
13869 /* OIS configuration mode */
13870 switch ((func_cfg_access.ois_ctrl_from_ui << 1) +
13871 ctrl7_g.ois_on_en)
13872 {
13873 case LSM6DSOX_OIS_ONLY_AUX:
13874 switch (spi2_ctrl3_ois.fs_xl_ois)
13875 {
13876 case LSM6DSOX_XL_OIS_2g:
13877 val->ois.xl.fs = LSM6DSOX_XL_OIS_2g;
13878 break;
13879
13880 case LSM6DSOX_XL_OIS_4g:
13881 val->ois.xl.fs = LSM6DSOX_XL_OIS_4g;
13882 break;
13883
13884 case LSM6DSOX_XL_OIS_8g:
13885 val->ois.xl.fs = LSM6DSOX_XL_OIS_8g;
13886 break;
13887
13888 case LSM6DSOX_XL_OIS_16g:
13889 val->ois.xl.fs = LSM6DSOX_XL_OIS_16g;
13890 break;
13891
13892 default:
13893 val->ois.xl.fs = LSM6DSOX_XL_OIS_2g;
13894 break;
13895 }
13896
13897 switch (spi2_ctrl1_ois.mode4_en)
13898 {
13899 case LSM6DSOX_XL_OIS_OFF:
13900 val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
13901 break;
13902
13903 case LSM6DSOX_XL_OIS_6667Hz_HP:
13904 val->ois.xl.odr = LSM6DSOX_XL_OIS_6667Hz_HP;
13905 break;
13906
13907 default:
13908 val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
13909 break;
13910 }
13911
13912 switch (spi2_ctrl1_ois.fs_g_ois)
13913 {
13914 case LSM6DSOX_GY_OIS_250dps:
13915 val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps;
13916 break;
13917
13918 case LSM6DSOX_GY_OIS_500dps:
13919 val->ois.gy.fs = LSM6DSOX_GY_OIS_500dps;
13920 break;
13921
13922 case LSM6DSOX_GY_OIS_1000dps:
13923 val->ois.gy.fs = LSM6DSOX_GY_OIS_1000dps;
13924 break;
13925
13926 case LSM6DSOX_GY_OIS_2000dps:
13927 val->ois.gy.fs = LSM6DSOX_GY_OIS_2000dps;
13928 break;
13929
13930 default:
13931 val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps;
13932 break;
13933 }
13934
13935 switch (spi2_ctrl1_ois.ois_en_spi2)
13936 {
13937 case LSM6DSOX_GY_OIS_OFF:
13938 val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
13939 break;
13940
13941 case LSM6DSOX_GY_OIS_6667Hz_HP:
13942 val->ois.gy.odr = LSM6DSOX_GY_OIS_6667Hz_HP;
13943 break;
13944
13945 default:
13946 val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
13947 break;
13948 }
13949
13950 val->ois.ctrl_md = LSM6DSOX_OIS_ONLY_AUX;
13951 break;
13952
13953 case LSM6DSOX_OIS_ONLY_UI:
13954 switch (ui_ctrl3_ois.fs_xl_ois)
13955 {
13956 case LSM6DSOX_XL_OIS_2g:
13957 val->ois.xl.fs = LSM6DSOX_XL_OIS_2g;
13958 break;
13959
13960 case LSM6DSOX_XL_OIS_4g:
13961 val->ois.xl.fs = LSM6DSOX_XL_OIS_4g;
13962 break;
13963
13964 case LSM6DSOX_XL_OIS_8g:
13965 val->ois.xl.fs = LSM6DSOX_XL_OIS_8g;
13966 break;
13967
13968 case LSM6DSOX_XL_OIS_16g:
13969 val->ois.xl.fs = LSM6DSOX_XL_OIS_16g;
13970 break;
13971
13972 default:
13973 val->ois.xl.fs = LSM6DSOX_XL_OIS_2g;
13974 break;
13975 }
13976
13977 switch (ui_ctrl1_ois.ois_en_spi2)
13978 {
13979 case LSM6DSOX_GY_OIS_OFF:
13980 val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
13981 break;
13982
13983 case LSM6DSOX_GY_OIS_6667Hz_HP:
13984 val->ois.gy.odr = LSM6DSOX_GY_OIS_6667Hz_HP;
13985 break;
13986
13987 default:
13988 val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
13989 break;
13990 }
13991
13992 switch (ui_ctrl1_ois.fs_g_ois)
13993 {
13994 case LSM6DSOX_GY_OIS_250dps:
13995 val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps;
13996 break;
13997
13998 case LSM6DSOX_GY_OIS_125dps:
13999 val->ois.gy.fs = LSM6DSOX_GY_OIS_125dps;
14000 break;
14001
14002 case LSM6DSOX_GY_OIS_500dps:
14003 val->ois.gy.fs = LSM6DSOX_GY_OIS_500dps;
14004 break;
14005
14006 case LSM6DSOX_GY_OIS_1000dps:
14007 val->ois.gy.fs = LSM6DSOX_GY_OIS_1000dps;
14008 break;
14009
14010 case LSM6DSOX_GY_OIS_2000dps:
14011 val->ois.gy.fs = LSM6DSOX_GY_OIS_2000dps;
14012 break;
14013
14014 default:
14015 val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps;
14016 break;
14017 }
14018
14019 switch (ui_ctrl1_ois.mode4_en)
14020 {
14021 case LSM6DSOX_XL_OIS_OFF:
14022 val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
14023 break;
14024
14025 case LSM6DSOX_XL_OIS_6667Hz_HP:
14026 val->ois.xl.odr = LSM6DSOX_XL_OIS_6667Hz_HP;
14027 break;
14028
14029 default:
14030 val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
14031 break;
14032 }
14033
14034 val->ois.ctrl_md = LSM6DSOX_OIS_ONLY_UI;
14035 break;
14036
14037 case LSM6DSOX_OIS_MIXED:
14038 switch (spi2_ctrl3_ois.fs_xl_ois)
14039 {
14040 case LSM6DSOX_XL_OIS_2g:
14041 val->ois.xl.fs = LSM6DSOX_XL_OIS_2g;
14042 break;
14043
14044 case LSM6DSOX_XL_OIS_4g:
14045 val->ois.xl.fs = LSM6DSOX_XL_OIS_4g;
14046 break;
14047
14048 case LSM6DSOX_XL_OIS_8g:
14049 val->ois.xl.fs = LSM6DSOX_XL_OIS_8g;
14050 break;
14051
14052 case LSM6DSOX_XL_OIS_16g:
14053 val->ois.xl.fs = LSM6DSOX_XL_OIS_16g;
14054 break;
14055
14056 default:
14057 val->ois.xl.fs = LSM6DSOX_XL_OIS_2g;
14058 break;
14059 }
14060
14061 switch (spi2_ctrl1_ois.mode4_en)
14062 {
14063 case LSM6DSOX_XL_OIS_OFF:
14064 val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
14065 break;
14066
14067 case LSM6DSOX_XL_OIS_6667Hz_HP:
14068 val->ois.xl.odr = LSM6DSOX_XL_OIS_6667Hz_HP;
14069 break;
14070
14071 default:
14072 val->ois.xl.odr = LSM6DSOX_XL_OIS_OFF;
14073 break;
14074 }
14075
14076 switch (spi2_ctrl1_ois.fs_g_ois)
14077 {
14078 case LSM6DSOX_GY_OIS_250dps:
14079 val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps;
14080 break;
14081
14082 case LSM6DSOX_GY_OIS_500dps:
14083 val->ois.gy.fs = LSM6DSOX_GY_OIS_500dps;
14084 break;
14085
14086 case LSM6DSOX_GY_OIS_1000dps:
14087 val->ois.gy.fs = LSM6DSOX_GY_OIS_1000dps;
14088 break;
14089
14090 case LSM6DSOX_GY_OIS_2000dps:
14091 val->ois.gy.fs = LSM6DSOX_GY_OIS_2000dps;
14092 break;
14093
14094 default:
14095 val->ois.gy.fs = LSM6DSOX_GY_OIS_250dps;
14096 break;
14097 }
14098
14099 switch (ui_ctrl1_ois.ois_en_spi2)
14100 {
14101 case LSM6DSOX_GY_OIS_OFF:
14102 val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
14103 break;
14104
14105 case LSM6DSOX_GY_OIS_6667Hz_HP:
14106 val->ois.gy.odr = LSM6DSOX_GY_OIS_6667Hz_HP;
14107 break;
14108
14109 default:
14110 val->ois.gy.odr = LSM6DSOX_GY_OIS_OFF;
14111 break;
14112 }
14113
14114 val->ois.ctrl_md = LSM6DSOX_OIS_MIXED;
14115 break;
14116
14117 default:
14118 spi2_ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
14119 spi2_ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr |
14120 (uint8_t)val->ois.xl.odr;
14121 spi2_ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
14122 spi2_ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
14123 val->ois.ctrl_md = LSM6DSOX_OIS_ONLY_AUX;
14124 break;
14125 }
14126
14127 return ret;
14128 }
14129
14130 /**
14131 * @brief Read data in engineering unit.[get]
14132 *
14133 * @param ctx communication interface handler.(ptr)
14134 * @param md the sensor conversion parameters.(ptr)
14135 * @retval interface status (MANDATORY: return 0 -> no Error)
14136 *
14137 */
lsm6dsox_data_get(const stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dsox_md_t * md,lsm6dsox_data_t * data)14138 int32_t lsm6dsox_data_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
14139 lsm6dsox_md_t *md, lsm6dsox_data_t *data)
14140 {
14141 uint8_t buff[14];
14142 int32_t ret;
14143
14144 uint8_t i;
14145 uint8_t j;
14146 ret = 0;
14147
14148 /* read data */
14149 if (ctx != NULL)
14150 {
14151 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_OUT_TEMP_L, buff, 14);
14152 }
14153
14154 j = 0;
14155 /* temperature conversion */
14156 data->ui.heat.raw = (int16_t)buff[j + 1U];
14157 data->ui.heat.raw = (((int16_t)data->ui.heat.raw * (int16_t)256) +
14158 (int16_t)buff[j]);
14159 j += 2U;
14160 data->ui.heat.deg_c = lsm6dsox_from_lsb_to_celsius((
14161 int16_t)data->ui.heat.raw);
14162
14163 /* angular rate conversion */
14164 for (i = 0U; i < 3U; i++)
14165 {
14166 data->ui.gy.raw[i] = (int16_t)buff[j + 1U];
14167 data->ui.gy.raw[i] = (data->ui.gy.raw[i] * 256) + (int16_t) buff[j];
14168 j += 2U;
14169
14170 switch (md->ui.gy.fs)
14171 {
14172 case LSM6DSOX_GY_UI_250dps:
14173 data->ui.gy.mdps[i] = lsm6dsox_from_fs250_to_mdps(data->ui.gy.raw[i]);
14174 break;
14175
14176 case LSM6DSOX_GY_UI_125dps:
14177 data->ui.gy.mdps[i] = lsm6dsox_from_fs125_to_mdps(data->ui.gy.raw[i]);
14178 break;
14179
14180 case LSM6DSOX_GY_UI_500dps:
14181 data->ui.gy.mdps[i] = lsm6dsox_from_fs500_to_mdps(data->ui.gy.raw[i]);
14182 break;
14183
14184 case LSM6DSOX_GY_UI_1000dps:
14185 data->ui.gy.mdps[i] = lsm6dsox_from_fs1000_to_mdps(
14186 data->ui.gy.raw[i]);
14187 break;
14188
14189 case LSM6DSOX_GY_UI_2000dps:
14190 data->ui.gy.mdps[i] = lsm6dsox_from_fs2000_to_mdps(
14191 data->ui.gy.raw[i]);
14192 break;
14193
14194 default:
14195 data->ui.gy.mdps[i] = 0.0f;
14196 break;
14197 }
14198 }
14199
14200 /* acceleration conversion */
14201 for (i = 0U; i < 3U; i++)
14202 {
14203 data->ui.xl.raw[i] = (int16_t)buff[j + 1U];
14204 data->ui.xl.raw[i] = (data->ui.xl.raw[i] * 256) + (int16_t) buff[j];
14205 j += 2U;
14206
14207 switch (md->ui.xl.fs)
14208 {
14209 case LSM6DSOX_XL_UI_2g:
14210 data->ui.xl.mg[i] = lsm6dsox_from_fs2_to_mg(data->ui.xl.raw[i]);
14211 break;
14212
14213 case LSM6DSOX_XL_UI_4g:
14214 data->ui.xl.mg[i] = lsm6dsox_from_fs4_to_mg(data->ui.xl.raw[i]);
14215 break;
14216
14217 case LSM6DSOX_XL_UI_8g:
14218 data->ui.xl.mg[i] = lsm6dsox_from_fs8_to_mg(data->ui.xl.raw[i]);
14219 break;
14220
14221 case LSM6DSOX_XL_UI_16g:
14222 data->ui.xl.mg[i] = lsm6dsox_from_fs16_to_mg(data->ui.xl.raw[i]);
14223 break;
14224
14225 default:
14226 data->ui.xl.mg[i] = 0.0f;
14227 break;
14228 }
14229 }
14230
14231 /* read data from ois chain */
14232 if (aux_ctx != NULL)
14233 {
14234 if (ret == 0)
14235 {
14236 ret = lsm6dsox_read_reg(aux_ctx, LSM6DSOX_SPI2_OUTX_L_G_OIS, buff,
14237 12);
14238 }
14239 }
14240
14241 else
14242 {
14243 if ((ctx != NULL) && (md->ois.ctrl_md == LSM6DSOX_OIS_ONLY_UI))
14244 {
14245 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_UI_OUTX_L_G_OIS, buff, 12);
14246 }
14247 }
14248
14249 j = 0;
14250
14251 /* ois angular rate conversion */
14252 for (i = 0U; i < 3U; i++)
14253 {
14254 data->ois.gy.raw[i] = (int16_t) buff[j + 1U];
14255 data->ois.gy.raw[i] = (data->ois.gy.raw[i] * 256) + (int16_t) buff[j];
14256 j += 2U;
14257
14258 switch (md->ois.gy.fs)
14259 {
14260 case LSM6DSOX_GY_UI_250dps:
14261 data->ois.gy.mdps[i] = lsm6dsox_from_fs250_to_mdps(
14262 data->ois.gy.raw[i]);
14263 break;
14264
14265 case LSM6DSOX_GY_UI_125dps:
14266 data->ois.gy.mdps[i] = lsm6dsox_from_fs125_to_mdps(
14267 data->ois.gy.raw[i]);
14268 break;
14269
14270 case LSM6DSOX_GY_UI_500dps:
14271 data->ois.gy.mdps[i] = lsm6dsox_from_fs500_to_mdps(
14272 data->ois.gy.raw[i]);
14273 break;
14274
14275 case LSM6DSOX_GY_UI_1000dps:
14276 data->ois.gy.mdps[i] = lsm6dsox_from_fs1000_to_mdps(
14277 data->ois.gy.raw[i]);
14278 break;
14279
14280 case LSM6DSOX_GY_UI_2000dps:
14281 data->ois.gy.mdps[i] = lsm6dsox_from_fs2000_to_mdps(
14282 data->ois.gy.raw[i]);
14283 break;
14284
14285 default:
14286 data->ois.gy.mdps[i] = 0.0f;
14287 break;
14288 }
14289 }
14290
14291 /* ois acceleration conversion */
14292 for (i = 0U; i < 3U; i++)
14293 {
14294 data->ois.xl.raw[i] = (int16_t) buff[j + 1U];
14295 data->ois.xl.raw[i] = (data->ois.xl.raw[i] * 256) + (int16_t) buff[j];
14296 j += 2U;
14297
14298 switch (md->ois.xl.fs)
14299 {
14300 case LSM6DSOX_XL_UI_2g:
14301 data->ois.xl.mg[i] = lsm6dsox_from_fs2_to_mg(data->ois.xl.raw[i]);
14302 break;
14303
14304 case LSM6DSOX_XL_UI_4g:
14305 data->ois.xl.mg[i] = lsm6dsox_from_fs4_to_mg(data->ois.xl.raw[i]);
14306 break;
14307
14308 case LSM6DSOX_XL_UI_8g:
14309 data->ois.xl.mg[i] = lsm6dsox_from_fs8_to_mg(data->ois.xl.raw[i]);
14310 break;
14311
14312 case LSM6DSOX_XL_UI_16g:
14313 data->ois.xl.mg[i] = lsm6dsox_from_fs16_to_mg(data->ois.xl.raw[i]);
14314 break;
14315
14316 default:
14317 data->ois.xl.mg[i] = 0.0f;
14318 break;
14319 }
14320 }
14321
14322 return ret;
14323 }
14324
14325 /**
14326 * @brief Embedded functions.[set]
14327 *
14328 * @param ctx read / write interface definitions
14329 * @param val change the values of registers
14330 * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
14331 * @retval interface status (MANDATORY: return 0 -> no Error)
14332 *
14333 */
lsm6dsox_embedded_sens_set(const stmdev_ctx_t * ctx,lsm6dsox_emb_sens_t * val)14334 int32_t lsm6dsox_embedded_sens_set(const stmdev_ctx_t *ctx,
14335 lsm6dsox_emb_sens_t *val)
14336 {
14337 lsm6dsox_emb_func_en_a_t emb_func_en_a;
14338 lsm6dsox_emb_func_en_b_t emb_func_en_b;
14339 int32_t ret;
14340
14341 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
14342
14343 if (ret == 0)
14344 {
14345 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
14346 (uint8_t *)&emb_func_en_a, 1);
14347 }
14348
14349 if (ret == 0)
14350 {
14351 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
14352 (uint8_t *)&emb_func_en_b, 1);
14353 emb_func_en_b.mlc_en = val->mlc;
14354 emb_func_en_b.fsm_en = val->fsm;
14355 emb_func_en_a.tilt_en = val->tilt;
14356 emb_func_en_a.pedo_en = val->step;
14357 emb_func_en_a.sign_motion_en = val->sig_mot;
14358 emb_func_en_b.fifo_compr_en = val->fifo_compr;
14359 }
14360
14361 if (ret == 0)
14362 {
14363 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
14364 (uint8_t *)&emb_func_en_a, 1);
14365 }
14366
14367 if (ret == 0)
14368 {
14369 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
14370 (uint8_t *)&emb_func_en_b, 1);
14371 }
14372
14373 if (ret == 0)
14374 {
14375 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
14376 }
14377
14378 return ret;
14379 }
14380
14381 /**
14382 * @brief Embedded functions.[get]
14383 *
14384 * @param ctx read / write interface definitions
14385 * @param val get the values of registers
14386 * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
14387 * @retval interface status (MANDATORY: return 0 -> no Error)
14388 *
14389 */
lsm6dsox_embedded_sens_get(const stmdev_ctx_t * ctx,lsm6dsox_emb_sens_t * emb_sens)14390 int32_t lsm6dsox_embedded_sens_get(const stmdev_ctx_t *ctx,
14391 lsm6dsox_emb_sens_t *emb_sens)
14392 {
14393 lsm6dsox_emb_func_en_a_t emb_func_en_a;
14394 lsm6dsox_emb_func_en_b_t emb_func_en_b;
14395 int32_t ret;
14396
14397 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
14398
14399 if (ret == 0)
14400 {
14401 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
14402 (uint8_t *)&emb_func_en_a, 1);
14403 }
14404
14405 if (ret == 0)
14406 {
14407 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
14408 (uint8_t *)&emb_func_en_b, 1);
14409 emb_sens->mlc = emb_func_en_b.mlc_en;
14410 emb_sens->fsm = emb_func_en_b.fsm_en;
14411 emb_sens->tilt = emb_func_en_a.tilt_en;
14412 emb_sens->step = emb_func_en_a.pedo_en;
14413 emb_sens->sig_mot = emb_func_en_a.sign_motion_en;
14414 emb_sens->fifo_compr = emb_func_en_b.fifo_compr_en;
14415 }
14416
14417 if (ret == 0)
14418 {
14419 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
14420 }
14421
14422 return ret;
14423 }
14424
14425 /**
14426 * @brief turn off all embedded functions.[get]
14427 *
14428 * @param ctx read / write interface definitions
14429 * @param val get the values of registers
14430 * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
14431 * @retval interface status (MANDATORY: return 0 -> no Error)
14432 *
14433 */
lsm6dsox_embedded_sens_off(const stmdev_ctx_t * ctx)14434 int32_t lsm6dsox_embedded_sens_off(const stmdev_ctx_t *ctx)
14435 {
14436 lsm6dsox_emb_func_en_a_t emb_func_en_a;
14437 lsm6dsox_emb_func_en_b_t emb_func_en_b;
14438 int32_t ret;
14439
14440 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_EMBEDDED_FUNC_BANK);
14441
14442 if (ret == 0)
14443 {
14444 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
14445 (uint8_t *)&emb_func_en_a, 1);
14446 }
14447
14448 if (ret == 0)
14449 {
14450 ret = lsm6dsox_read_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
14451 (uint8_t *)&emb_func_en_b, 1);
14452 emb_func_en_b.mlc_en = PROPERTY_DISABLE;
14453 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
14454 emb_func_en_a.tilt_en = PROPERTY_DISABLE;
14455 emb_func_en_a.pedo_en = PROPERTY_DISABLE;
14456 emb_func_en_a.sign_motion_en = PROPERTY_DISABLE;
14457 emb_func_en_b.fifo_compr_en = PROPERTY_DISABLE;
14458 }
14459
14460 if (ret == 0)
14461 {
14462 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_A,
14463 (uint8_t *)&emb_func_en_a, 1);
14464 }
14465
14466 if (ret == 0)
14467 {
14468 ret = lsm6dsox_write_reg(ctx, LSM6DSOX_EMB_FUNC_EN_B,
14469 (uint8_t *)&emb_func_en_b, 1);
14470 }
14471
14472 if (ret == 0)
14473 {
14474 ret = lsm6dsox_mem_bank_set(ctx, LSM6DSOX_USER_BANK);
14475 }
14476
14477 return ret;
14478 }
14479
14480 /**
14481 * @}
14482 *
14483 */
14484
14485 /**
14486 * @}
14487 *
14488 */
14489
14490 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
14491
