1 /**
2 ******************************************************************************
3 * @file lsm6dso_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSO driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dso_reg.h"
21 #include <stddef.h>
22
23 /**
24 * @defgroup LSM6DSO
25 * @brief This file provides a set of functions needed to drive the
26 * lsm6dso enhanced inertial module.
27 * @{
28 *
29 */
30
31 /**
32 * @defgroup LSM6DSO_Interfaces_Functions
33 * @brief This section provide a set of functions used to read and
34 * write a generic register of the device.
35 * MANDATORY: return 0 -> no Error.
36 * @{
37 *
38 */
39
40 /**
41 * @brief Read generic device register
42 *
43 * @param ctx read / write interface definitions(ptr)
44 * @param reg register to read
45 * @param data pointer to buffer that store the data read(ptr)
46 * @param len number of consecutive register to read
47 * @retval interface status (MANDATORY: return 0 -> no Error)
48 *
49 */
lsm6dso_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)50 int32_t __weak lsm6dso_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
51 uint8_t *data,
52 uint16_t len)
53 {
54 int32_t ret;
55
56 if (ctx == NULL) return -1;
57
58 ret = ctx->read_reg(ctx->handle, reg, data, len);
59
60 return ret;
61 }
62
63 /**
64 * @brief Write generic device register
65 *
66 * @param ctx read / write interface definitions(ptr)
67 * @param reg register to write
68 * @param data pointer to data to write in register reg(ptr)
69 * @param len number of consecutive register to write
70 * @retval interface status (MANDATORY: return 0 -> no Error)
71 *
72 */
lsm6dso_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)73 int32_t __weak lsm6dso_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
74 uint8_t *data,
75 uint16_t len)
76 {
77 int32_t ret;
78
79 if (ctx == NULL) return -1;
80
81 ret = ctx->write_reg(ctx->handle, reg, data, len);
82
83 return ret;
84 }
85
86 /**
87 * @}
88 *
89 */
90
91 /**
92 * @defgroup LSM6DSOX_Private_functions
93 * @brief Section collect all the utility functions needed by APIs.
94 * @{
95 *
96 */
97
bytecpy(uint8_t * target,uint8_t * source)98 static void bytecpy(uint8_t *target, uint8_t *source)
99 {
100 if ((target != NULL) && (source != NULL))
101 {
102 *target = *source;
103 }
104 }
105
106 /**
107 * @defgroup LSM6DSO_Sensitivity
108 * @brief These functions convert raw-data into engineering units.
109 * @{
110 *
111 */
lsm6dso_from_fs2_to_mg(int16_t lsb)112 float_t lsm6dso_from_fs2_to_mg(int16_t lsb)
113 {
114 return ((float_t)lsb) * 0.061f;
115 }
116
lsm6dso_from_fs4_to_mg(int16_t lsb)117 float_t lsm6dso_from_fs4_to_mg(int16_t lsb)
118 {
119 return ((float_t)lsb) * 0.122f;
120 }
121
lsm6dso_from_fs8_to_mg(int16_t lsb)122 float_t lsm6dso_from_fs8_to_mg(int16_t lsb)
123 {
124 return ((float_t)lsb) * 0.244f;
125 }
126
lsm6dso_from_fs16_to_mg(int16_t lsb)127 float_t lsm6dso_from_fs16_to_mg(int16_t lsb)
128 {
129 return ((float_t)lsb) * 0.488f;
130 }
131
lsm6dso_from_fs125_to_mdps(int16_t lsb)132 float_t lsm6dso_from_fs125_to_mdps(int16_t lsb)
133 {
134 return ((float_t)lsb) * 4.375f;
135 }
136
lsm6dso_from_fs500_to_mdps(int16_t lsb)137 float_t lsm6dso_from_fs500_to_mdps(int16_t lsb)
138 {
139 return ((float_t)lsb) * 17.50f;
140 }
141
lsm6dso_from_fs250_to_mdps(int16_t lsb)142 float_t lsm6dso_from_fs250_to_mdps(int16_t lsb)
143 {
144 return ((float_t)lsb) * 8.750f;
145 }
146
lsm6dso_from_fs1000_to_mdps(int16_t lsb)147 float_t lsm6dso_from_fs1000_to_mdps(int16_t lsb)
148 {
149 return ((float_t)lsb) * 35.0f;
150 }
151
lsm6dso_from_fs2000_to_mdps(int16_t lsb)152 float_t lsm6dso_from_fs2000_to_mdps(int16_t lsb)
153 {
154 return ((float_t)lsb) * 70.0f;
155 }
156
lsm6dso_from_lsb_to_celsius(int16_t lsb)157 float_t lsm6dso_from_lsb_to_celsius(int16_t lsb)
158 {
159 return (((float_t)lsb / 256.0f) + 25.0f);
160 }
161
lsm6dso_from_lsb_to_nsec(int16_t lsb)162 float_t lsm6dso_from_lsb_to_nsec(int16_t lsb)
163 {
164 return ((float_t)lsb * 25000.0f);
165 }
166
167 /**
168 * @}
169 *
170 */
171
172 /**
173 * @defgroup LSM6DSO_Data_Generation
174 * @brief This section groups all the functions concerning
175 * data generation.
176 *
177 */
178
179 /**
180 * @brief Accelerometer full-scale selection.[set]
181 *
182 * @param ctx read / write interface definitions
183 * @param val change the values of fs_xl in reg CTRL1_XL
184 * @retval interface status (MANDATORY: return 0 -> no Error)
185 *
186 */
lsm6dso_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dso_fs_xl_t val)187 int32_t lsm6dso_xl_full_scale_set(const stmdev_ctx_t *ctx,
188 lsm6dso_fs_xl_t val)
189 {
190 lsm6dso_ctrl1_xl_t reg;
191 int32_t ret;
192
193 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
194
195 if (ret == 0)
196 {
197 reg.fs_xl = (uint8_t) val;
198 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
199 }
200
201 return ret;
202 }
203
204 /**
205 * @brief Accelerometer full-scale selection.[get]
206 *
207 * @param ctx read / write interface definitions
208 * @param val Get the values of fs_xl in reg CTRL1_XL
209 * @retval interface status (MANDATORY: return 0 -> no Error)
210 *
211 */
lsm6dso_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dso_fs_xl_t * val)212 int32_t lsm6dso_xl_full_scale_get(const stmdev_ctx_t *ctx,
213 lsm6dso_fs_xl_t *val)
214 {
215 lsm6dso_ctrl1_xl_t reg;
216 int32_t ret;
217
218 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
219
220 switch (reg.fs_xl)
221 {
222 case LSM6DSO_2g:
223 *val = LSM6DSO_2g;
224 break;
225
226 case LSM6DSO_16g:
227 *val = LSM6DSO_16g;
228 break;
229
230 case LSM6DSO_4g:
231 *val = LSM6DSO_4g;
232 break;
233
234 case LSM6DSO_8g:
235 *val = LSM6DSO_8g;
236 break;
237
238 default:
239 *val = LSM6DSO_2g;
240 break;
241 }
242
243 return ret;
244 }
245
246 /**
247 * @brief Accelerometer UI data rate selection.[set]
248 *
249 * @param ctx read / write interface definitions
250 * @param val change the values of odr_xl in reg CTRL1_XL
251 * @retval interface status (MANDATORY: return 0 -> no Error)
252 *
253 */
lsm6dso_xl_data_rate_set(const stmdev_ctx_t * ctx,lsm6dso_odr_xl_t val)254 int32_t lsm6dso_xl_data_rate_set(const stmdev_ctx_t *ctx,
255 lsm6dso_odr_xl_t val)
256 {
257 lsm6dso_odr_xl_t odr_xl = val;
258 lsm6dso_emb_fsm_enable_t fsm_enable;
259 lsm6dso_fsm_odr_t fsm_odr;
260 lsm6dso_ctrl1_xl_t reg;
261 int32_t ret;
262
263 /* Check the Finite State Machine data rate constraints */
264 ret = lsm6dso_fsm_enable_get(ctx, &fsm_enable);
265 if (ret != 0) { return ret; }
266
267 if ((fsm_enable.fsm_enable_a.fsm1_en |
268 fsm_enable.fsm_enable_a.fsm2_en |
269 fsm_enable.fsm_enable_a.fsm3_en |
270 fsm_enable.fsm_enable_a.fsm4_en |
271 fsm_enable.fsm_enable_a.fsm5_en |
272 fsm_enable.fsm_enable_a.fsm6_en |
273 fsm_enable.fsm_enable_a.fsm7_en |
274 fsm_enable.fsm_enable_a.fsm8_en |
275 fsm_enable.fsm_enable_b.fsm9_en |
276 fsm_enable.fsm_enable_b.fsm10_en |
277 fsm_enable.fsm_enable_b.fsm11_en |
278 fsm_enable.fsm_enable_b.fsm12_en |
279 fsm_enable.fsm_enable_b.fsm13_en |
280 fsm_enable.fsm_enable_b.fsm14_en |
281 fsm_enable.fsm_enable_b.fsm15_en |
282 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
283 {
284 ret = lsm6dso_fsm_data_rate_get(ctx, &fsm_odr);
285 if (ret != 0) { return ret; }
286
287 switch (fsm_odr)
288 {
289 case LSM6DSO_ODR_FSM_12Hz5:
290 if (val == LSM6DSO_XL_ODR_OFF)
291 {
292 odr_xl = LSM6DSO_XL_ODR_12Hz5;
293 }
294 else
295 {
296 odr_xl = val;
297 }
298
299 break;
300
301 case LSM6DSO_ODR_FSM_26Hz:
302 if (val == LSM6DSO_XL_ODR_OFF)
303 {
304 odr_xl = LSM6DSO_XL_ODR_26Hz;
305 }
306 else if (val == LSM6DSO_XL_ODR_12Hz5)
307 {
308 odr_xl = LSM6DSO_XL_ODR_26Hz;
309 }
310 else
311 {
312 odr_xl = val;
313 }
314
315 break;
316
317 case LSM6DSO_ODR_FSM_52Hz:
318 if (val == LSM6DSO_XL_ODR_OFF)
319 {
320 odr_xl = LSM6DSO_XL_ODR_52Hz;
321 }
322 else if (val == LSM6DSO_XL_ODR_12Hz5)
323 {
324 odr_xl = LSM6DSO_XL_ODR_52Hz;
325 }
326 else if (val == LSM6DSO_XL_ODR_26Hz)
327 {
328 odr_xl = LSM6DSO_XL_ODR_52Hz;
329 }
330 else
331 {
332 odr_xl = val;
333 }
334
335 break;
336
337 case LSM6DSO_ODR_FSM_104Hz:
338 if (val == LSM6DSO_XL_ODR_OFF)
339 {
340 odr_xl = LSM6DSO_XL_ODR_104Hz;
341 }
342 else if (val == LSM6DSO_XL_ODR_12Hz5)
343 {
344 odr_xl = LSM6DSO_XL_ODR_104Hz;
345 }
346 else if (val == LSM6DSO_XL_ODR_26Hz)
347 {
348 odr_xl = LSM6DSO_XL_ODR_104Hz;
349 }
350 else if (val == LSM6DSO_XL_ODR_52Hz)
351 {
352 odr_xl = LSM6DSO_XL_ODR_104Hz;
353 }
354 else
355 {
356 odr_xl = val;
357 }
358
359 break;
360
361 default:
362 odr_xl = val;
363 break;
364 }
365 }
366
367 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
368 reg.odr_xl = (uint8_t) odr_xl;
369 ret += lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
370
371 return ret;
372 }
373
374 /**
375 * @brief Accelerometer UI data rate selection.[get]
376 *
377 * @param ctx read / write interface definitions
378 * @param val Get the values of odr_xl in reg CTRL1_XL
379 * @retval interface status (MANDATORY: return 0 -> no Error)
380 *
381 */
lsm6dso_xl_data_rate_get(const stmdev_ctx_t * ctx,lsm6dso_odr_xl_t * val)382 int32_t lsm6dso_xl_data_rate_get(const stmdev_ctx_t *ctx,
383 lsm6dso_odr_xl_t *val)
384 {
385 lsm6dso_ctrl1_xl_t reg;
386 int32_t ret;
387
388 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
389
390 switch (reg.odr_xl)
391 {
392 case LSM6DSO_XL_ODR_OFF:
393 *val = LSM6DSO_XL_ODR_OFF;
394 break;
395
396 case LSM6DSO_XL_ODR_12Hz5:
397 *val = LSM6DSO_XL_ODR_12Hz5;
398 break;
399
400 case LSM6DSO_XL_ODR_26Hz:
401 *val = LSM6DSO_XL_ODR_26Hz;
402 break;
403
404 case LSM6DSO_XL_ODR_52Hz:
405 *val = LSM6DSO_XL_ODR_52Hz;
406 break;
407
408 case LSM6DSO_XL_ODR_104Hz:
409 *val = LSM6DSO_XL_ODR_104Hz;
410 break;
411
412 case LSM6DSO_XL_ODR_208Hz:
413 *val = LSM6DSO_XL_ODR_208Hz;
414 break;
415
416 case LSM6DSO_XL_ODR_417Hz:
417 *val = LSM6DSO_XL_ODR_417Hz;
418 break;
419
420 case LSM6DSO_XL_ODR_833Hz:
421 *val = LSM6DSO_XL_ODR_833Hz;
422 break;
423
424 case LSM6DSO_XL_ODR_1667Hz:
425 *val = LSM6DSO_XL_ODR_1667Hz;
426 break;
427
428 case LSM6DSO_XL_ODR_3333Hz:
429 *val = LSM6DSO_XL_ODR_3333Hz;
430 break;
431
432 case LSM6DSO_XL_ODR_6667Hz:
433 *val = LSM6DSO_XL_ODR_6667Hz;
434 break;
435
436 case LSM6DSO_XL_ODR_1Hz6:
437 *val = LSM6DSO_XL_ODR_1Hz6;
438 break;
439
440 default:
441 *val = LSM6DSO_XL_ODR_OFF;
442 break;
443 }
444
445 return ret;
446 }
447
448 /**
449 * @brief Gyroscope UI chain full-scale selection.[set]
450 *
451 * @param ctx read / write interface definitions
452 * @param val change the values of fs_g in reg CTRL2_G
453 * @retval interface status (MANDATORY: return 0 -> no Error)
454 *
455 */
lsm6dso_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dso_fs_g_t val)456 int32_t lsm6dso_gy_full_scale_set(const stmdev_ctx_t *ctx,
457 lsm6dso_fs_g_t val)
458 {
459 lsm6dso_ctrl2_g_t reg;
460 int32_t ret;
461
462 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1);
463
464 if (ret == 0)
465 {
466 reg.fs_g = (uint8_t) val;
467 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1);
468 }
469
470 return ret;
471 }
472
473 /**
474 * @brief Gyroscope UI chain full-scale selection.[get]
475 *
476 * @param ctx read / write interface definitions
477 * @param val Get the values of fs_g in reg CTRL2_G
478 * @retval interface status (MANDATORY: return 0 -> no Error)
479 *
480 */
lsm6dso_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dso_fs_g_t * val)481 int32_t lsm6dso_gy_full_scale_get(const stmdev_ctx_t *ctx,
482 lsm6dso_fs_g_t *val)
483 {
484 lsm6dso_ctrl2_g_t reg;
485 int32_t ret;
486
487 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1);
488
489 switch (reg.fs_g)
490 {
491 case LSM6DSO_250dps:
492 *val = LSM6DSO_250dps;
493 break;
494
495 case LSM6DSO_125dps:
496 *val = LSM6DSO_125dps;
497 break;
498
499 case LSM6DSO_500dps:
500 *val = LSM6DSO_500dps;
501 break;
502
503 case LSM6DSO_1000dps:
504 *val = LSM6DSO_1000dps;
505 break;
506
507 case LSM6DSO_2000dps:
508 *val = LSM6DSO_2000dps;
509 break;
510
511 default:
512 *val = LSM6DSO_250dps;
513 break;
514 }
515
516 return ret;
517 }
518
519 /**
520 * @brief Gyroscope UI data rate selection.[set]
521 *
522 * @param ctx read / write interface definitions
523 * @param val change the values of odr_g in reg CTRL2_G
524 * @retval interface status (MANDATORY: return 0 -> no Error)
525 *
526 */
lsm6dso_gy_data_rate_set(const stmdev_ctx_t * ctx,lsm6dso_odr_g_t val)527 int32_t lsm6dso_gy_data_rate_set(const stmdev_ctx_t *ctx,
528 lsm6dso_odr_g_t val)
529 {
530 lsm6dso_odr_g_t odr_gy = val;
531 lsm6dso_emb_fsm_enable_t fsm_enable;
532 lsm6dso_fsm_odr_t fsm_odr;
533 lsm6dso_ctrl2_g_t reg;
534 int32_t ret;
535
536 /* Check the Finite State Machine data rate constraints */
537 ret = lsm6dso_fsm_enable_get(ctx, &fsm_enable);
538 if (ret != 0) { return ret; }
539
540 if ((fsm_enable.fsm_enable_a.fsm1_en |
541 fsm_enable.fsm_enable_a.fsm2_en |
542 fsm_enable.fsm_enable_a.fsm3_en |
543 fsm_enable.fsm_enable_a.fsm4_en |
544 fsm_enable.fsm_enable_a.fsm5_en |
545 fsm_enable.fsm_enable_a.fsm6_en |
546 fsm_enable.fsm_enable_a.fsm7_en |
547 fsm_enable.fsm_enable_a.fsm8_en |
548 fsm_enable.fsm_enable_b.fsm9_en |
549 fsm_enable.fsm_enable_b.fsm10_en |
550 fsm_enable.fsm_enable_b.fsm11_en |
551 fsm_enable.fsm_enable_b.fsm12_en |
552 fsm_enable.fsm_enable_b.fsm13_en |
553 fsm_enable.fsm_enable_b.fsm14_en |
554 fsm_enable.fsm_enable_b.fsm15_en |
555 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
556 {
557 ret = lsm6dso_fsm_data_rate_get(ctx, &fsm_odr);
558 if (ret != 0) { return ret; }
559
560 switch (fsm_odr)
561 {
562 case LSM6DSO_ODR_FSM_12Hz5:
563 if (val == LSM6DSO_GY_ODR_OFF)
564 {
565 odr_gy = LSM6DSO_GY_ODR_12Hz5;
566 }
567 else
568 {
569 odr_gy = val;
570 }
571
572 break;
573
574 case LSM6DSO_ODR_FSM_26Hz:
575 if (val == LSM6DSO_GY_ODR_OFF)
576 {
577 odr_gy = LSM6DSO_GY_ODR_26Hz;
578 }
579 else if (val == LSM6DSO_GY_ODR_12Hz5)
580 {
581 odr_gy = LSM6DSO_GY_ODR_26Hz;
582 }
583 else
584 {
585 odr_gy = val;
586 }
587
588 break;
589
590 case LSM6DSO_ODR_FSM_52Hz:
591 if (val == LSM6DSO_GY_ODR_OFF)
592 {
593 odr_gy = LSM6DSO_GY_ODR_52Hz;
594 }
595 else if (val == LSM6DSO_GY_ODR_12Hz5)
596 {
597 odr_gy = LSM6DSO_GY_ODR_52Hz;
598 }
599 else if (val == LSM6DSO_GY_ODR_26Hz)
600 {
601 odr_gy = LSM6DSO_GY_ODR_52Hz;
602 }
603 else
604 {
605 odr_gy = val;
606 }
607
608 break;
609
610 case LSM6DSO_ODR_FSM_104Hz:
611 if (val == LSM6DSO_GY_ODR_OFF)
612 {
613 odr_gy = LSM6DSO_GY_ODR_104Hz;
614 }
615 else if (val == LSM6DSO_GY_ODR_12Hz5)
616 {
617 odr_gy = LSM6DSO_GY_ODR_104Hz;
618 }
619 else if (val == LSM6DSO_GY_ODR_26Hz)
620 {
621 odr_gy = LSM6DSO_GY_ODR_104Hz;
622 }
623 else if (val == LSM6DSO_GY_ODR_52Hz)
624 {
625 odr_gy = LSM6DSO_GY_ODR_104Hz;
626 }
627 else
628 {
629 odr_gy = val;
630 }
631
632 break;
633
634 default:
635 odr_gy = val;
636 break;
637 }
638 }
639
640 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1);
641 reg.odr_g = (uint8_t) odr_gy;
642 ret += lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1);
643
644 return ret;
645 }
646
647 /**
648 * @brief Gyroscope UI data rate selection.[get]
649 *
650 * @param ctx read / write interface definitions
651 * @param val Get the values of odr_g in reg CTRL2_G
652 * @retval interface status (MANDATORY: return 0 -> no Error)
653 *
654 */
lsm6dso_gy_data_rate_get(const stmdev_ctx_t * ctx,lsm6dso_odr_g_t * val)655 int32_t lsm6dso_gy_data_rate_get(const stmdev_ctx_t *ctx,
656 lsm6dso_odr_g_t *val)
657 {
658 lsm6dso_ctrl2_g_t reg;
659 int32_t ret;
660
661 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1);
662
663 switch (reg.odr_g)
664 {
665 case LSM6DSO_GY_ODR_OFF:
666 *val = LSM6DSO_GY_ODR_OFF;
667 break;
668
669 case LSM6DSO_GY_ODR_12Hz5:
670 *val = LSM6DSO_GY_ODR_12Hz5;
671 break;
672
673 case LSM6DSO_GY_ODR_26Hz:
674 *val = LSM6DSO_GY_ODR_26Hz;
675 break;
676
677 case LSM6DSO_GY_ODR_52Hz:
678 *val = LSM6DSO_GY_ODR_52Hz;
679 break;
680
681 case LSM6DSO_GY_ODR_104Hz:
682 *val = LSM6DSO_GY_ODR_104Hz;
683 break;
684
685 case LSM6DSO_GY_ODR_208Hz:
686 *val = LSM6DSO_GY_ODR_208Hz;
687 break;
688
689 case LSM6DSO_GY_ODR_417Hz:
690 *val = LSM6DSO_GY_ODR_417Hz;
691 break;
692
693 case LSM6DSO_GY_ODR_833Hz:
694 *val = LSM6DSO_GY_ODR_833Hz;
695 break;
696
697 case LSM6DSO_GY_ODR_1667Hz:
698 *val = LSM6DSO_GY_ODR_1667Hz;
699 break;
700
701 case LSM6DSO_GY_ODR_3333Hz:
702 *val = LSM6DSO_GY_ODR_3333Hz;
703 break;
704
705 case LSM6DSO_GY_ODR_6667Hz:
706 *val = LSM6DSO_GY_ODR_6667Hz;
707 break;
708
709 default:
710 *val = LSM6DSO_GY_ODR_OFF;
711 break;
712 }
713
714 return ret;
715 }
716
717 /**
718 * @brief Block data update.[set]
719 *
720 * @param ctx read / write interface definitions
721 * @param val change the values of bdu in reg CTRL3_C
722 * @retval interface status (MANDATORY: return 0 -> no Error)
723 *
724 */
lsm6dso_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)725 int32_t lsm6dso_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
726 {
727 lsm6dso_ctrl3_c_t reg;
728 int32_t ret;
729
730 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
731
732 if (ret == 0)
733 {
734 reg.bdu = val;
735 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
736 }
737
738 return ret;
739 }
740
741 /**
742 * @brief Block data update.[get]
743 *
744 * @param ctx read / write interface definitions
745 * @param val Get the values of bdu in reg CTRL3_C
746 * @retval interface status (MANDATORY: return 0 -> no Error)
747 *
748 */
lsm6dso_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)749 int32_t lsm6dso_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
750 {
751 lsm6dso_ctrl3_c_t reg;
752 int32_t ret;
753
754 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
755 *val = reg.bdu;
756
757 return ret;
758 }
759
760 /**
761 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
762 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
763 *
764 * @param ctx read / write interface definitions
765 * @param val change the values of usr_off_w in reg CTRL6_C
766 * @retval interface status (MANDATORY: return 0 -> no Error)
767 *
768 */
lsm6dso_xl_offset_weight_set(const stmdev_ctx_t * ctx,lsm6dso_usr_off_w_t val)769 int32_t lsm6dso_xl_offset_weight_set(const stmdev_ctx_t *ctx,
770 lsm6dso_usr_off_w_t val)
771 {
772 lsm6dso_ctrl6_c_t reg;
773 int32_t ret;
774
775 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
776
777 if (ret == 0)
778 {
779 reg.usr_off_w = (uint8_t)val;
780 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
781 }
782
783 return ret;
784 }
785
786 /**
787 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
788 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
789 *
790 * @param ctx read / write interface definitions
791 * @param val Get the values of usr_off_w in reg CTRL6_C
792 * @retval interface status (MANDATORY: return 0 -> no Error)
793 *
794 */
lsm6dso_xl_offset_weight_get(const stmdev_ctx_t * ctx,lsm6dso_usr_off_w_t * val)795 int32_t lsm6dso_xl_offset_weight_get(const stmdev_ctx_t *ctx,
796 lsm6dso_usr_off_w_t *val)
797 {
798 lsm6dso_ctrl6_c_t reg;
799 int32_t ret;
800
801 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
802
803 switch (reg.usr_off_w)
804 {
805 case LSM6DSO_LSb_1mg:
806 *val = LSM6DSO_LSb_1mg;
807 break;
808
809 case LSM6DSO_LSb_16mg:
810 *val = LSM6DSO_LSb_16mg;
811 break;
812
813 default:
814 *val = LSM6DSO_LSb_1mg;
815 break;
816 }
817
818 return ret;
819 }
820
821 /**
822 * @brief Accelerometer power mode.[set]
823 *
824 * @param ctx read / write interface definitions
825 * @param val change the values of xl_hm_mode in
826 * reg CTRL6_C
827 * @retval interface status (MANDATORY: return 0 -> no Error)
828 *
829 */
lsm6dso_xl_power_mode_set(const stmdev_ctx_t * ctx,lsm6dso_xl_hm_mode_t val)830 int32_t lsm6dso_xl_power_mode_set(const stmdev_ctx_t *ctx,
831 lsm6dso_xl_hm_mode_t val)
832 {
833 lsm6dso_ctrl5_c_t ctrl5_c;
834 lsm6dso_ctrl6_c_t ctrl6_c;
835 int32_t ret;
836
837 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
838 if (ret != 0) { return ret; }
839
840 ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x02U) >> 1;
841 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
842 if (ret != 0) { return ret; }
843
844 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
845 if (ret != 0) { return ret; }
846
847 ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
848 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
849
850 return ret;
851 }
852
853 /**
854 * @brief Accelerometer power mode.[get]
855 *
856 * @param ctx read / write interface definitions
857 * @param val Get the values of xl_hm_mode in reg CTRL6_C
858 * @retval interface status (MANDATORY: return 0 -> no Error)
859 *
860 */
lsm6dso_xl_power_mode_get(const stmdev_ctx_t * ctx,lsm6dso_xl_hm_mode_t * val)861 int32_t lsm6dso_xl_power_mode_get(const stmdev_ctx_t *ctx,
862 lsm6dso_xl_hm_mode_t *val)
863 {
864 lsm6dso_ctrl5_c_t ctrl5_c;
865 lsm6dso_ctrl6_c_t ctrl6_c;
866 int32_t ret;
867
868 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
869
870 if (ret == 0)
871 {
872 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
873
874 switch ((ctrl5_c.xl_ulp_en << 1) | ctrl6_c.xl_hm_mode)
875 {
876 case LSM6DSO_HIGH_PERFORMANCE_MD:
877 *val = LSM6DSO_HIGH_PERFORMANCE_MD;
878 break;
879
880 case LSM6DSO_LOW_NORMAL_POWER_MD:
881 *val = LSM6DSO_LOW_NORMAL_POWER_MD;
882 break;
883
884 case LSM6DSO_ULTRA_LOW_POWER_MD:
885 *val = LSM6DSO_ULTRA_LOW_POWER_MD;
886 break;
887
888 default:
889 *val = LSM6DSO_HIGH_PERFORMANCE_MD;
890 break;
891 }
892 }
893
894 return ret;
895 }
896
897 /**
898 * @brief Operating mode for gyroscope.[set]
899 *
900 * @param ctx read / write interface definitions
901 * @param val change the values of g_hm_mode in reg CTRL7_G
902 * @retval interface status (MANDATORY: return 0 -> no Error)
903 *
904 */
lsm6dso_gy_power_mode_set(const stmdev_ctx_t * ctx,lsm6dso_g_hm_mode_t val)905 int32_t lsm6dso_gy_power_mode_set(const stmdev_ctx_t *ctx,
906 lsm6dso_g_hm_mode_t val)
907 {
908 lsm6dso_ctrl7_g_t reg;
909 int32_t ret;
910
911 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
912
913 if (ret == 0)
914 {
915 reg.g_hm_mode = (uint8_t)val;
916 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
917 }
918
919 return ret;
920 }
921
922 /**
923 * @brief Operating mode for gyroscope.[get]
924 *
925 * @param ctx read / write interface definitions
926 * @param val Get the values of g_hm_mode in reg CTRL7_G
927 * @retval interface status (MANDATORY: return 0 -> no Error)
928 *
929 */
lsm6dso_gy_power_mode_get(const stmdev_ctx_t * ctx,lsm6dso_g_hm_mode_t * val)930 int32_t lsm6dso_gy_power_mode_get(const stmdev_ctx_t *ctx,
931 lsm6dso_g_hm_mode_t *val)
932 {
933 lsm6dso_ctrl7_g_t reg;
934 int32_t ret;
935
936 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
937
938 switch (reg.g_hm_mode)
939 {
940 case LSM6DSO_GY_HIGH_PERFORMANCE:
941 *val = LSM6DSO_GY_HIGH_PERFORMANCE;
942 break;
943
944 case LSM6DSO_GY_NORMAL:
945 *val = LSM6DSO_GY_NORMAL;
946 break;
947
948 default:
949 *val = LSM6DSO_GY_HIGH_PERFORMANCE;
950 break;
951 }
952
953 return ret;
954 }
955
956 /**
957 * @brief The STATUS_REG register is read by the primary interface.[get]
958 *
959 * @param ctx read / write interface definitions
960 * @param val register STATUS_REG
961 * @retval interface status (MANDATORY: return 0 -> no Error)
962 *
963 */
lsm6dso_status_reg_get(const stmdev_ctx_t * ctx,lsm6dso_status_reg_t * val)964 int32_t lsm6dso_status_reg_get(const stmdev_ctx_t *ctx,
965 lsm6dso_status_reg_t *val)
966 {
967 int32_t ret;
968
969 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *) val, 1);
970
971 return ret;
972 }
973
974 /**
975 * @brief Accelerometer new data available.[get]
976 *
977 * @param ctx read / write interface definitions
978 * @param val Get the values of xlda in reg STATUS_REG
979 * @retval interface status (MANDATORY: return 0 -> no Error)
980 *
981 */
lsm6dso_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)982 int32_t lsm6dso_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
983 uint8_t *val)
984 {
985 lsm6dso_status_reg_t reg;
986 int32_t ret;
987
988 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *)®, 1);
989 *val = reg.xlda;
990
991 return ret;
992 }
993
994 /**
995 * @brief Gyroscope new data available.[get]
996 *
997 * @param ctx read / write interface definitions
998 * @param val Get the values of gda in reg STATUS_REG
999 * @retval interface status (MANDATORY: return 0 -> no Error)
1000 *
1001 */
lsm6dso_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1002 int32_t lsm6dso_gy_flag_data_ready_get(const stmdev_ctx_t *ctx,
1003 uint8_t *val)
1004 {
1005 lsm6dso_status_reg_t reg;
1006 int32_t ret;
1007
1008 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *)®, 1);
1009 *val = reg.gda;
1010
1011 return ret;
1012 }
1013
1014 /**
1015 * @brief Temperature new data available.[get]
1016 *
1017 * @param ctx read / write interface definitions
1018 * @param val Get the values of tda in reg STATUS_REG
1019 * @retval interface status (MANDATORY: return 0 -> no Error)
1020 *
1021 */
lsm6dso_temp_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1022 int32_t lsm6dso_temp_flag_data_ready_get(const stmdev_ctx_t *ctx,
1023 uint8_t *val)
1024 {
1025 lsm6dso_status_reg_t reg;
1026 int32_t ret;
1027
1028 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *)®, 1);
1029 *val = reg.tda;
1030
1031 return ret;
1032 }
1033
1034 /**
1035 * @brief Accelerometer X-axis user offset correction expressed in
1036 * two's complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1037 * The value must be in the range [-127 127].[set]
1038 *
1039 * @param ctx read / write interface definitions
1040 * @param buff buffer that contains data to write
1041 * @retval interface status (MANDATORY: return 0 -> no Error)
1042 *
1043 */
lsm6dso_xl_usr_offset_x_set(const stmdev_ctx_t * ctx,uint8_t * buff)1044 int32_t lsm6dso_xl_usr_offset_x_set(const stmdev_ctx_t *ctx, uint8_t *buff)
1045 {
1046 int32_t ret;
1047
1048 ret = lsm6dso_write_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1);
1049
1050 return ret;
1051 }
1052
1053 /**
1054 * @brief Accelerometer X-axis user offset correction expressed in two's
1055 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1056 * The value must be in the range [-127 127].[get]
1057 *
1058 * @param ctx read / write interface definitions
1059 * @param buff buffer that stores data read
1060 * @retval interface status (MANDATORY: return 0 -> no Error)
1061 *
1062 */
lsm6dso_xl_usr_offset_x_get(const stmdev_ctx_t * ctx,uint8_t * buff)1063 int32_t lsm6dso_xl_usr_offset_x_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1064 {
1065 int32_t ret;
1066
1067 ret = lsm6dso_read_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1);
1068
1069 return ret;
1070 }
1071
1072 /**
1073 * @brief Accelerometer Y-axis user offset correction expressed in two's
1074 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1075 * The value must be in the range [-127 127].[set]
1076 *
1077 * @param ctx read / write interface definitions
1078 * @param buff buffer that contains data to write
1079 * @retval interface status (MANDATORY: return 0 -> no Error)
1080 *
1081 */
lsm6dso_xl_usr_offset_y_set(const stmdev_ctx_t * ctx,uint8_t * buff)1082 int32_t lsm6dso_xl_usr_offset_y_set(const stmdev_ctx_t *ctx, uint8_t *buff)
1083 {
1084 int32_t ret;
1085
1086 ret = lsm6dso_write_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1);
1087
1088 return ret;
1089 }
1090
1091 /**
1092 * @brief Accelerometer Y-axis user offset correction expressed in two's
1093 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1094 * The value must be in the range [-127 127].[get]
1095 *
1096 * @param ctx read / write interface definitions
1097 * @param buff buffer that stores data read
1098 * @retval interface status (MANDATORY: return 0 -> no Error)
1099 *
1100 */
lsm6dso_xl_usr_offset_y_get(const stmdev_ctx_t * ctx,uint8_t * buff)1101 int32_t lsm6dso_xl_usr_offset_y_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1102 {
1103 int32_t ret;
1104
1105 ret = lsm6dso_read_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1);
1106
1107 return ret;
1108 }
1109
1110 /**
1111 * @brief Accelerometer Z-axis user offset correction expressed in two's
1112 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1113 * The value must be in the range [-127 127].[set]
1114 *
1115 * @param ctx read / write interface definitions
1116 * @param buff buffer that contains data to write
1117 * @retval interface status (MANDATORY: return 0 -> no Error)
1118 *
1119 */
lsm6dso_xl_usr_offset_z_set(const stmdev_ctx_t * ctx,uint8_t * buff)1120 int32_t lsm6dso_xl_usr_offset_z_set(const stmdev_ctx_t *ctx, uint8_t *buff)
1121 {
1122 int32_t ret;
1123
1124 ret = lsm6dso_write_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1);
1125
1126 return ret;
1127 }
1128
1129 /**
1130 * @brief Accelerometer Z-axis user offset correction expressed in two's
1131 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1132 * The value must be in the range [-127 127].[get]
1133 *
1134 * @param ctx read / write interface definitions
1135 * @param buff buffer that stores data read
1136 * @retval interface status (MANDATORY: return 0 -> no Error)
1137 *
1138 */
lsm6dso_xl_usr_offset_z_get(const stmdev_ctx_t * ctx,uint8_t * buff)1139 int32_t lsm6dso_xl_usr_offset_z_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1140 {
1141 int32_t ret;
1142
1143 ret = lsm6dso_read_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1);
1144
1145 return ret;
1146 }
1147
1148 /**
1149 * @brief Enables user offset on out.[set]
1150 *
1151 * @param ctx read / write interface definitions
1152 * @param val change the values of usr_off_on_out in reg CTRL7_G
1153 * @retval interface status (MANDATORY: return 0 -> no Error)
1154 *
1155 */
lsm6dso_xl_usr_offset_set(const stmdev_ctx_t * ctx,uint8_t val)1156 int32_t lsm6dso_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t val)
1157 {
1158 lsm6dso_ctrl7_g_t reg;
1159 int32_t ret;
1160
1161 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
1162
1163 if (ret == 0)
1164 {
1165 reg.usr_off_on_out = val;
1166 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
1167 }
1168
1169 return ret;
1170 }
1171
1172 /**
1173 * @brief User offset on out flag.[get]
1174 *
1175 * @param ctx read / write interface definitions
1176 * @param val values of usr_off_on_out in reg CTRL7_G
1177 * @retval interface status (MANDATORY: return 0 -> no Error)
1178 *
1179 */
lsm6dso_xl_usr_offset_get(const stmdev_ctx_t * ctx,uint8_t * val)1180 int32_t lsm6dso_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *val)
1181 {
1182 lsm6dso_ctrl7_g_t reg;
1183 int32_t ret;
1184
1185 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
1186 *val = reg.usr_off_on_out;
1187
1188 return ret;
1189 }
1190
1191 /**
1192 * @}
1193 *
1194 */
1195
1196 /**
1197 * @defgroup LSM6DSO_Timestamp
1198 * @brief This section groups all the functions that manage the
1199 * timestamp generation.
1200 * @{
1201 *
1202 */
1203
1204 /**
1205 * @brief Reset timestamp counter.[set]
1206 *
1207 * @param ctx Read / write interface definitions.(ptr)
1208 * @retval Interface status (MANDATORY: return 0 -> no Error)
1209 *
1210 */
lsm6dso_timestamp_rst(const stmdev_ctx_t * ctx)1211 int32_t lsm6dso_timestamp_rst(const stmdev_ctx_t *ctx)
1212 {
1213 uint8_t rst_val = 0xAA;
1214 return lsm6dso_write_reg(ctx, LSM6DSO_TIMESTAMP2, &rst_val, 1);
1215 }
1216
1217 /**
1218 * @brief Enables timestamp counter.[set]
1219 *
1220 * @param ctx read / write interface definitions
1221 * @param val change the values of timestamp_en in reg CTRL10_C
1222 * @retval interface status (MANDATORY: return 0 -> no Error)
1223 *
1224 */
lsm6dso_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)1225 int32_t lsm6dso_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
1226 {
1227 lsm6dso_ctrl10_c_t reg;
1228 int32_t ret;
1229
1230 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t *)®, 1);
1231
1232 if (ret == 0)
1233 {
1234 reg.timestamp_en = val;
1235 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t *)®, 1);
1236 }
1237
1238 return ret;
1239 }
1240
1241 /**
1242 * @brief Enables timestamp counter.[get]
1243 *
1244 * @param ctx read / write interface definitions
1245 * @param val Get the values of timestamp_en in reg CTRL10_C
1246 * @retval interface status (MANDATORY: return 0 -> no Error)
1247 *
1248 */
lsm6dso_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)1249 int32_t lsm6dso_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
1250 {
1251 lsm6dso_ctrl10_c_t reg;
1252 int32_t ret;
1253
1254 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t *)®, 1);
1255 *val = reg.timestamp_en;
1256
1257 return ret;
1258 }
1259
1260 /**
1261 * @brief Timestamp first data output register (r).
1262 * The value is expressed as a 32-bit word and the bit
1263 * resolution is 25 us.[get]
1264 *
1265 * @param ctx read / write interface definitions
1266 * @param buff buffer that stores data read
1267 * @retval interface status (MANDATORY: return 0 -> no Error)
1268 *
1269 */
lsm6dso_timestamp_raw_get(const stmdev_ctx_t * ctx,uint32_t * val)1270 int32_t lsm6dso_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val)
1271 {
1272 uint8_t buff[4];
1273 int32_t ret;
1274
1275 ret = lsm6dso_read_reg(ctx, LSM6DSO_TIMESTAMP0, buff, 4);
1276 *val = buff[3];
1277 *val = (*val * 256U) + buff[2];
1278 *val = (*val * 256U) + buff[1];
1279 *val = (*val * 256U) + buff[0];
1280
1281 return ret;
1282 }
1283
1284 /**
1285 * @}
1286 *
1287 */
1288
1289 /**
1290 * @defgroup LSM6DSO_Data output
1291 * @brief This section groups all the data output functions.
1292 * @{
1293 *
1294 */
1295
1296 /**
1297 * @brief Circular burst-mode (rounding) read of the output
1298 * registers.[set]
1299 *
1300 * @param ctx read / write interface definitions
1301 * @param val change the values of rounding in reg CTRL5_C
1302 * @retval interface status (MANDATORY: return 0 -> no Error)
1303 *
1304 */
lsm6dso_rounding_mode_set(const stmdev_ctx_t * ctx,lsm6dso_rounding_t val)1305 int32_t lsm6dso_rounding_mode_set(const stmdev_ctx_t *ctx,
1306 lsm6dso_rounding_t val)
1307 {
1308 lsm6dso_ctrl5_c_t reg;
1309 int32_t ret;
1310
1311 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
1312
1313 if (ret == 0)
1314 {
1315 reg.rounding = (uint8_t)val;
1316 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
1317 }
1318
1319 return ret;
1320 }
1321
1322 /**
1323 * @brief Gyroscope UI chain full-scale selection.[get]
1324 *
1325 * @param ctx read / write interface definitions
1326 * @param val Get the values of rounding in reg CTRL5_C
1327 * @retval interface status (MANDATORY: return 0 -> no Error)
1328 *
1329 */
lsm6dso_rounding_mode_get(const stmdev_ctx_t * ctx,lsm6dso_rounding_t * val)1330 int32_t lsm6dso_rounding_mode_get(const stmdev_ctx_t *ctx,
1331 lsm6dso_rounding_t *val)
1332 {
1333 lsm6dso_ctrl5_c_t reg;
1334 int32_t ret;
1335
1336 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
1337
1338 switch (reg.rounding)
1339 {
1340 case LSM6DSO_NO_ROUND:
1341 *val = LSM6DSO_NO_ROUND;
1342 break;
1343
1344 case LSM6DSO_ROUND_XL:
1345 *val = LSM6DSO_ROUND_XL;
1346 break;
1347
1348 case LSM6DSO_ROUND_GY:
1349 *val = LSM6DSO_ROUND_GY;
1350 break;
1351
1352 case LSM6DSO_ROUND_GY_XL:
1353 *val = LSM6DSO_ROUND_GY_XL;
1354 break;
1355
1356 default:
1357 *val = LSM6DSO_NO_ROUND;
1358 break;
1359 }
1360
1361 return ret;
1362 }
1363
1364 /**
1365 * @brief Temperature data output register (r).
1366 * L and H registers together express a 16-bit word in two's
1367 * complement.[get]
1368 *
1369 * @param ctx read / write interface definitions
1370 * @param buff buffer that stores data read
1371 * @retval interface status (MANDATORY: return 0 -> no Error)
1372 *
1373 */
lsm6dso_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1374 int32_t lsm6dso_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1375 {
1376 uint8_t buff[2];
1377 int32_t ret;
1378
1379 ret = lsm6dso_read_reg(ctx, LSM6DSO_OUT_TEMP_L, buff, 2);
1380 val[0] = (int16_t)buff[1];
1381 val[0] = (val[0] * 256) + (int16_t)buff[0];
1382
1383 return ret;
1384 }
1385
1386 /**
1387 * @brief Angular rate sensor. The value is expressed as a 16-bit
1388 * word in two's complement.[get]
1389 *
1390 * @param ctx read / write interface definitions
1391 * @param buff buffer that stores data read
1392 * @retval interface status (MANDATORY: return 0 -> no Error)
1393 *
1394 */
lsm6dso_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1395 int32_t lsm6dso_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1396 {
1397 uint8_t buff[6];
1398 int32_t ret;
1399
1400 ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_G, buff, 6);
1401 val[0] = (int16_t)buff[1];
1402 val[0] = (val[0] * 256) + (int16_t)buff[0];
1403 val[1] = (int16_t)buff[3];
1404 val[1] = (val[1] * 256) + (int16_t)buff[2];
1405 val[2] = (int16_t)buff[5];
1406 val[2] = (val[2] * 256) + (int16_t)buff[4];
1407
1408 return ret;
1409 }
1410
1411 /**
1412 * @brief Linear acceleration output register.
1413 * The value is expressed as a 16-bit word in two's complement.[get]
1414 *
1415 * @param ctx read / write interface definitions
1416 * @param buff buffer that stores data read
1417 * @retval interface status (MANDATORY: return 0 -> no Error)
1418 *
1419 */
lsm6dso_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1420 int32_t lsm6dso_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1421 {
1422 uint8_t buff[6];
1423 int32_t ret;
1424
1425 ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_A, buff, 6);
1426 val[0] = (int16_t)buff[1];
1427 val[0] = (val[0] * 256) + (int16_t)buff[0];
1428 val[1] = (int16_t)buff[3];
1429 val[1] = (val[1] * 256) + (int16_t)buff[2];
1430 val[2] = (int16_t)buff[5];
1431 val[2] = (val[2] * 256) + (int16_t)buff[4];
1432
1433 return ret;
1434 }
1435
1436 /**
1437 * @brief FIFO data output [get]
1438 *
1439 * @param ctx read / write interface definitions
1440 * @param buff buffer that stores data read
1441 * @retval interface status (MANDATORY: return 0 -> no Error)
1442 *
1443 */
lsm6dso_fifo_out_raw_get(const stmdev_ctx_t * ctx,uint8_t * buff)1444 int32_t lsm6dso_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1445 {
1446 int32_t ret;
1447
1448 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_X_L, buff, 6);
1449
1450 return ret;
1451 }
1452
1453 /**
1454 * @brief Step counter output register.[get]
1455 *
1456 * @param ctx read / write interface definitions
1457 * @param buff buffer that stores data read
1458 * @retval interface status (MANDATORY: return 0 -> no Error)
1459 *
1460 */
lsm6dso_number_of_steps_get(const stmdev_ctx_t * ctx,uint16_t * val)1461 int32_t lsm6dso_number_of_steps_get(const stmdev_ctx_t *ctx, uint16_t *val)
1462 {
1463 uint8_t buff[2];
1464 int32_t ret;
1465
1466 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
1467 if (ret != 0) { return ret; }
1468
1469 ret = lsm6dso_read_reg(ctx, LSM6DSO_STEP_COUNTER_L, buff, 2);
1470 if (ret != 0) { goto exit; }
1471
1472 *val = buff[1];
1473 *val = (*val * 256U) + buff[0];
1474
1475 exit:
1476 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
1477
1478 return ret;
1479 }
1480
1481 /**
1482 * @brief Reset step counter register.[get]
1483 *
1484 * @param ctx read / write interface definitions
1485 * @retval interface status (MANDATORY: return 0 -> no Error)
1486 *
1487 */
lsm6dso_steps_reset(const stmdev_ctx_t * ctx)1488 int32_t lsm6dso_steps_reset(const stmdev_ctx_t *ctx)
1489 {
1490 lsm6dso_emb_func_src_t reg;
1491 int32_t ret;
1492
1493 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
1494 if (ret != 0) { return ret; }
1495
1496 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t *)®, 1);
1497 if (ret != 0) { goto exit; }
1498
1499 reg.pedo_rst_step = PROPERTY_ENABLE;
1500 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t *)®, 1);
1501
1502 exit:
1503 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
1504
1505 return ret;
1506 }
1507
1508 /**
1509 * @}
1510 *
1511 */
1512
1513 /**
1514 * @defgroup LSM6DSO_common
1515 * @brief This section groups common useful functions.
1516 * @{
1517 *
1518 */
1519
1520 /**
1521 * @brief Difference in percentage of the effective ODR(and timestamp rate)
1522 * with respect to the typical.
1523 * Step: 0.15%. 8-bit format, 2's complement.[set]
1524 *
1525 * @param ctx read / write interface definitions
1526 * @param val change the values of freq_fine in reg
1527 * INTERNAL_FREQ_FINE
1528 * @retval interface status (MANDATORY: return 0 -> no Error)
1529 *
1530 */
lsm6dso_odr_cal_reg_set(const stmdev_ctx_t * ctx,uint8_t val)1531 int32_t lsm6dso_odr_cal_reg_set(const stmdev_ctx_t *ctx, uint8_t val)
1532 {
1533 lsm6dso_internal_freq_fine_t reg;
1534 int32_t ret;
1535
1536 ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE,
1537 (uint8_t *)®, 1);
1538
1539 if (ret == 0)
1540 {
1541 reg.freq_fine = val;
1542 ret = lsm6dso_write_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE,
1543 (uint8_t *)®, 1);
1544 }
1545
1546 return ret;
1547 }
1548
1549 /**
1550 * @brief Difference in percentage of the effective ODR(and timestamp rate)
1551 * with respect to the typical.
1552 * Step: 0.15%. 8-bit format, 2's complement.[get]
1553 *
1554 * @param ctx read / write interface definitions
1555 * @param val Get the values of freq_fine in reg INTERNAL_FREQ_FINE
1556 * @retval interface status (MANDATORY: return 0 -> no Error)
1557 *
1558 */
lsm6dso_odr_cal_reg_get(const stmdev_ctx_t * ctx,uint8_t * val)1559 int32_t lsm6dso_odr_cal_reg_get(const stmdev_ctx_t *ctx, uint8_t *val)
1560 {
1561 lsm6dso_internal_freq_fine_t reg;
1562 int32_t ret;
1563
1564 ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE,
1565 (uint8_t *)®, 1);
1566 *val = reg.freq_fine;
1567
1568 return ret;
1569 }
1570
1571
1572 /**
1573 * @brief Enable access to the embedded functions/sensor
1574 * hub configuration registers.[set]
1575 *
1576 * @param ctx read / write interface definitions
1577 * @param val change register page (reg_access in FUNC_CFG_ACCESS)
1578 * @retval interface status (MANDATORY: return 0 -> no Error)
1579 *
1580 */
lsm6dso_mem_bank_set(const stmdev_ctx_t * ctx,lsm6dso_reg_access_t val)1581 int32_t lsm6dso_mem_bank_set(const stmdev_ctx_t *ctx,
1582 lsm6dso_reg_access_t val)
1583 {
1584 lsm6dso_func_cfg_access_t reg = {0};
1585 int32_t ret;
1586
1587 /* no need to read it first as the pther bits are reserved and must be zero */
1588 reg.reg_access = (uint8_t)val;
1589 ret = lsm6dso_write_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)®, 1);
1590
1591 return ret;
1592 }
1593
1594 /**
1595 * @brief Enable access to the embedded functions/sensor
1596 * hub configuration registers.[get]
1597 *
1598 * @param ctx read / write interface definitions
1599 * @param val Get the values of reg_access in reg FUNC_CFG_ACCESS
1600 * @retval interface status (MANDATORY: return 0 -> no Error)
1601 *
1602 */
lsm6dso_mem_bank_get(const stmdev_ctx_t * ctx,lsm6dso_reg_access_t * val)1603 int32_t lsm6dso_mem_bank_get(const stmdev_ctx_t *ctx,
1604 lsm6dso_reg_access_t *val)
1605 {
1606 lsm6dso_func_cfg_access_t reg;
1607 int32_t ret;
1608
1609 ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)®, 1);
1610
1611 switch (reg.reg_access)
1612 {
1613 case LSM6DSO_USER_BANK:
1614 *val = LSM6DSO_USER_BANK;
1615 break;
1616
1617 case LSM6DSO_SENSOR_HUB_BANK:
1618 *val = LSM6DSO_SENSOR_HUB_BANK;
1619 break;
1620
1621 case LSM6DSO_EMBEDDED_FUNC_BANK:
1622 *val = LSM6DSO_EMBEDDED_FUNC_BANK;
1623 break;
1624
1625 default:
1626 *val = LSM6DSO_USER_BANK;
1627 break;
1628 }
1629
1630 return ret;
1631 }
1632
1633 /**
1634 * @brief Write a line(byte) in a page.[set]
1635 *
1636 * @param ctx read / write interface definitions
1637 * @param uint8_t address: page line address
1638 * @param val value to write
1639 * @retval interface status (MANDATORY: return 0 -> no Error)
1640 *
1641 */
lsm6dso_ln_pg_write_byte(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * val)1642 int32_t lsm6dso_ln_pg_write_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val)
1643 {
1644 return lsm6dso_ln_pg_write(ctx, address, val, 1);
1645 }
1646
1647 /**
1648 * @brief Write buffer in a page.[set]
1649 *
1650 * @param ctx read / write interface definitions
1651 * @param uint8_t address: page line address
1652 * @param uint8_t *buf: buffer to write
1653 * @param uint8_t len: buffer len
1654 * @retval interface status (MANDATORY: return 0 -> no Error)
1655 *
1656 */
lsm6dso_ln_pg_write(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1657 int32_t lsm6dso_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address,
1658 uint8_t *buf, uint8_t len)
1659 {
1660 lsm6dso_page_rw_t page_rw;
1661 lsm6dso_page_sel_t page_sel;
1662 lsm6dso_page_address_t page_address;
1663 uint8_t msb;
1664 uint8_t lsb;
1665 int32_t ret;
1666 uint8_t i ;
1667
1668 msb = ((uint8_t)(address >> 8) & 0x0FU);
1669 lsb = (uint8_t)address & 0xFFU;
1670
1671 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
1672 if (ret != 0) { return ret; }
1673
1674 /* set page write */
1675 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1676 page_rw.page_rw = 0x02; /* page_write enable*/
1677 ret += lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1678 if (ret != 0) { goto exit; }
1679
1680 /* select page */
1681 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
1682 page_sel.page_sel = msb;
1683 page_sel.not_used_01 = 1;
1684 ret += lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
1685 if (ret != 0) { goto exit; }
1686
1687 /* set page addr */
1688 page_address.page_addr = lsb;
1689 ret += lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
1690 (uint8_t *)&page_address, 1);
1691 if (ret != 0) { goto exit; }
1692
1693 for (i = 0; ((i < len) && (ret == 0)); i++)
1694 {
1695 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_VALUE, &buf[i], 1);
1696 if (ret != 0) { goto exit; }
1697
1698 lsb++;
1699
1700 /* Check if page wrap */
1701 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
1702 {
1703 msb++;
1704 ret += lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *)&page_sel, 1);
1705 if (ret != 0) { goto exit; }
1706
1707 page_sel.page_sel = msb;
1708 page_sel.not_used_01 = 1;
1709 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *)&page_sel, 1);
1710 if (ret != 0) { goto exit; }
1711 }
1712 }
1713
1714 page_sel.page_sel = 0;
1715 page_sel.not_used_01 = 1;
1716 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
1717 if (ret != 0) { goto exit; }
1718
1719 /* unset page write */
1720 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1721 page_rw.page_rw = 0x00; /* page_write disable */
1722 ret += lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1723
1724 exit:
1725 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
1726
1727 return ret;
1728 }
1729
1730 /**
1731 * @brief Read a line(byte) in a page.[get]
1732 *
1733 * @param ctx read / write interface definitions
1734 * @param uint8_t address: page line address
1735 * @param val read value
1736 * @retval interface status (MANDATORY: return 0 -> no Error)
1737 *
1738 */
lsm6dso_ln_pg_read_byte(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * val)1739 int32_t lsm6dso_ln_pg_read_byte(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *val)
1740 {
1741 return lsm6dso_ln_pg_read(ctx, address, val, 1);
1742 }
1743
lsm6dso_ln_pg_read(const stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1744 int32_t lsm6dso_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, uint8_t *buf,
1745 uint8_t len)
1746 {
1747 lsm6dso_page_rw_t page_rw;
1748 lsm6dso_page_sel_t page_sel;
1749 lsm6dso_page_address_t page_address;
1750 uint8_t msb;
1751 uint8_t lsb;
1752 int32_t ret;
1753 uint8_t i ;
1754
1755 msb = ((uint8_t)(address >> 8) & 0x0FU);
1756 lsb = (uint8_t)address & 0xFFU;
1757
1758 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
1759 if (ret != 0) { return ret; }
1760
1761 /* set page write */
1762 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1763 page_rw.page_rw = 0x01; /* page_read enable*/
1764 ret += lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1765 if (ret != 0) { goto exit; }
1766
1767 /* select page */
1768 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
1769 page_sel.page_sel = msb;
1770 page_sel.not_used_01 = 1;
1771 ret += lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
1772 if (ret != 0) { goto exit; }
1773
1774 for (i = 0; ((i < len) && (ret == 0)); i++)
1775 {
1776 /* set page addr */
1777 page_address.page_addr = lsb;
1778 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
1779 (uint8_t *)&page_address, 1);
1780 if (ret != 0) { goto exit; }
1781
1782 ret += lsm6dso_read_reg(ctx, LSM6DSO_PAGE_VALUE, &buf[i], 1);
1783 if (ret != 0) { goto exit; }
1784
1785 lsb++;
1786
1787 /* Check if page wrap */
1788 if (((lsb & 0xFFU) == 0x00U) && (ret == 0))
1789 {
1790 msb++;
1791 ret += lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *)&page_sel, 1);
1792 if (ret != 0) { goto exit; }
1793
1794 page_sel.page_sel = msb;
1795 page_sel.not_used_01 = 1;
1796 ret += lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *)&page_sel, 1);
1797 if (ret != 0) { goto exit; }
1798 }
1799 }
1800
1801 page_sel.page_sel = 0;
1802 page_sel.not_used_01 = 1;
1803 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
1804 if (ret != 0) { goto exit; }
1805
1806 /* unset page write */
1807 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1808 page_rw.page_rw = 0x00; /* page_write disable */
1809 ret += lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1810
1811 exit:
1812 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
1813
1814 return ret;
1815 }
1816
1817 /**
1818 * @brief Data-ready pulsed / letched mode.[set]
1819 *
1820 * @param ctx read / write interface definitions
1821 * @param val change the values of
1822 * dataready_pulsed in
1823 * reg COUNTER_BDR_REG1
1824 * @retval interface status (MANDATORY: return 0 -> no Error)
1825 *
1826 */
lsm6dso_data_ready_mode_set(const stmdev_ctx_t * ctx,lsm6dso_dataready_pulsed_t val)1827 int32_t lsm6dso_data_ready_mode_set(const stmdev_ctx_t *ctx,
1828 lsm6dso_dataready_pulsed_t val)
1829 {
1830 lsm6dso_counter_bdr_reg1_t reg;
1831 int32_t ret;
1832
1833 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1);
1834
1835 if (ret == 0)
1836 {
1837 reg.dataready_pulsed = (uint8_t)val;
1838 ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
1839 (uint8_t *)®, 1);
1840 }
1841
1842 return ret;
1843 }
1844
1845 /**
1846 * @brief Data-ready pulsed / letched mode.[get]
1847 *
1848 * @param ctx read / write interface definitions
1849 * @param val Get the values of
1850 * dataready_pulsed in
1851 * reg COUNTER_BDR_REG1
1852 * @retval interface status (MANDATORY: return 0 -> no Error)
1853 *
1854 */
lsm6dso_data_ready_mode_get(const stmdev_ctx_t * ctx,lsm6dso_dataready_pulsed_t * val)1855 int32_t lsm6dso_data_ready_mode_get(const stmdev_ctx_t *ctx,
1856 lsm6dso_dataready_pulsed_t *val)
1857 {
1858 lsm6dso_counter_bdr_reg1_t reg;
1859 int32_t ret;
1860
1861 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1);
1862
1863 switch (reg.dataready_pulsed)
1864 {
1865 case LSM6DSO_DRDY_LATCHED:
1866 *val = LSM6DSO_DRDY_LATCHED;
1867 break;
1868
1869 case LSM6DSO_DRDY_PULSED:
1870 *val = LSM6DSO_DRDY_PULSED;
1871 break;
1872
1873 default:
1874 *val = LSM6DSO_DRDY_LATCHED;
1875 break;
1876 }
1877
1878 return ret;
1879 }
1880
1881 /**
1882 * @brief Device "Who am I".[get]
1883 *
1884 * @param ctx read / write interface definitions
1885 * @param buff buffer that stores data read
1886 * @retval interface status (MANDATORY: return 0 -> no Error)
1887 *
1888 */
lsm6dso_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)1889 int32_t lsm6dso_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1890 {
1891 int32_t ret;
1892
1893 ret = lsm6dso_read_reg(ctx, LSM6DSO_WHO_AM_I, buff, 1);
1894
1895 return ret;
1896 }
1897
1898 /**
1899 * @brief Software reset. Restore the default values
1900 * in user registers[set]
1901 *
1902 * @param ctx read / write interface definitions
1903 * @param val change the values of sw_reset in reg CTRL3_C
1904 * @retval interface status (MANDATORY: return 0 -> no Error)
1905 *
1906 */
lsm6dso_reset_set(const stmdev_ctx_t * ctx,uint8_t val)1907 int32_t lsm6dso_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
1908 {
1909 lsm6dso_ctrl3_c_t reg;
1910 int32_t ret;
1911
1912 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
1913
1914 if (ret == 0)
1915 {
1916 reg.sw_reset = val;
1917 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
1918 }
1919
1920 return ret;
1921 }
1922
1923 /**
1924 * @brief Software reset. Restore the default values in user registers.[get]
1925 *
1926 * @param ctx read / write interface definitions
1927 * @param val Get the values of sw_reset in reg CTRL3_C
1928 * @retval interface status (MANDATORY: return 0 -> no Error)
1929 *
1930 */
lsm6dso_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)1931 int32_t lsm6dso_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
1932 {
1933 lsm6dso_ctrl3_c_t reg;
1934 int32_t ret;
1935
1936 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
1937 *val = reg.sw_reset;
1938
1939 return ret;
1940 }
1941
1942 /**
1943 * @brief Register address automatically incremented during a multiple byte
1944 * access with a serial interface.[set]
1945 *
1946 * @param ctx read / write interface definitions
1947 * @param val change the values of if_inc in reg CTRL3_C
1948 * @retval interface status (MANDATORY: return 0 -> no Error)
1949 *
1950 */
lsm6dso_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)1951 int32_t lsm6dso_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
1952 {
1953 lsm6dso_ctrl3_c_t reg;
1954 int32_t ret;
1955
1956 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
1957
1958 if (ret == 0)
1959 {
1960 reg.if_inc = val;
1961 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
1962 }
1963
1964 return ret;
1965 }
1966
1967 /**
1968 * @brief Register address automatically incremented during a multiple byte
1969 * access with a serial interface.[get]
1970 *
1971 * @param ctx read / write interface definitions
1972 * @param val Get the values of if_inc in reg CTRL3_C
1973 * @retval interface status (MANDATORY: return 0 -> no Error)
1974 *
1975 */
lsm6dso_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)1976 int32_t lsm6dso_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
1977 {
1978 lsm6dso_ctrl3_c_t reg;
1979 int32_t ret;
1980
1981 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
1982 *val = reg.if_inc;
1983
1984 return ret;
1985 }
1986
1987 /**
1988 * @brief Reboot memory content. Reload the calibration parameters.[set]
1989 *
1990 * @param ctx read / write interface definitions
1991 * @param val change the values of boot in reg CTRL3_C
1992 * @retval interface status (MANDATORY: return 0 -> no Error)
1993 *
1994 */
lsm6dso_boot_set(const stmdev_ctx_t * ctx,uint8_t val)1995 int32_t lsm6dso_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
1996 {
1997 lsm6dso_ctrl3_c_t reg;
1998 int32_t ret;
1999
2000 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
2001
2002 if (ret == 0)
2003 {
2004 reg.boot = val;
2005 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
2006 }
2007
2008 return ret;
2009 }
2010
2011 /**
2012 * @brief Reboot memory content. Reload the calibration parameters.[get]
2013 *
2014 * @param ctx read / write interface definitions
2015 * @param val Get the values of boot in reg CTRL3_C
2016 * @retval interface status (MANDATORY: return 0 -> no Error)
2017 *
2018 */
lsm6dso_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)2019 int32_t lsm6dso_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
2020 {
2021 lsm6dso_ctrl3_c_t reg;
2022 int32_t ret;
2023
2024 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
2025 *val = reg.boot;
2026
2027 return ret;
2028 }
2029
2030 /**
2031 * @brief Linear acceleration sensor self-test enable.[set]
2032 *
2033 * @param ctx read / write interface definitions
2034 * @param val change the values of st_xl in reg CTRL5_C
2035 * @retval interface status (MANDATORY: return 0 -> no Error)
2036 *
2037 */
lsm6dso_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6dso_st_xl_t val)2038 int32_t lsm6dso_xl_self_test_set(const stmdev_ctx_t *ctx,
2039 lsm6dso_st_xl_t val)
2040 {
2041 lsm6dso_ctrl5_c_t reg;
2042 int32_t ret;
2043
2044 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
2045
2046 if (ret == 0)
2047 {
2048 reg.st_xl = (uint8_t)val;
2049 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
2050 }
2051
2052 return ret;
2053 }
2054
2055 /**
2056 * @brief Linear acceleration sensor self-test enable.[get]
2057 *
2058 * @param ctx read / write interface definitions
2059 * @param val Get the values of st_xl in reg CTRL5_C
2060 * @retval interface status (MANDATORY: return 0 -> no Error)
2061 *
2062 */
lsm6dso_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6dso_st_xl_t * val)2063 int32_t lsm6dso_xl_self_test_get(const stmdev_ctx_t *ctx,
2064 lsm6dso_st_xl_t *val)
2065 {
2066 lsm6dso_ctrl5_c_t reg;
2067 int32_t ret;
2068
2069 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
2070
2071 switch (reg.st_xl)
2072 {
2073 case LSM6DSO_XL_ST_DISABLE:
2074 *val = LSM6DSO_XL_ST_DISABLE;
2075 break;
2076
2077 case LSM6DSO_XL_ST_POSITIVE:
2078 *val = LSM6DSO_XL_ST_POSITIVE;
2079 break;
2080
2081 case LSM6DSO_XL_ST_NEGATIVE:
2082 *val = LSM6DSO_XL_ST_NEGATIVE;
2083 break;
2084
2085 default:
2086 *val = LSM6DSO_XL_ST_DISABLE;
2087 break;
2088 }
2089
2090 return ret;
2091 }
2092
2093 /**
2094 * @brief Angular rate sensor self-test enable.[set]
2095 *
2096 * @param ctx read / write interface definitions
2097 * @param val change the values of st_g in reg CTRL5_C
2098 * @retval interface status (MANDATORY: return 0 -> no Error)
2099 *
2100 */
lsm6dso_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dso_st_g_t val)2101 int32_t lsm6dso_gy_self_test_set(const stmdev_ctx_t *ctx,
2102 lsm6dso_st_g_t val)
2103 {
2104 lsm6dso_ctrl5_c_t reg;
2105 int32_t ret;
2106
2107 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
2108
2109 if (ret == 0)
2110 {
2111 reg.st_g = (uint8_t)val;
2112 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
2113 }
2114
2115 return ret;
2116 }
2117
2118 /**
2119 * @brief Angular rate sensor self-test enable.[get]
2120 *
2121 * @param ctx read / write interface definitions
2122 * @param val Get the values of st_g in reg CTRL5_C
2123 * @retval interface status (MANDATORY: return 0 -> no Error)
2124 *
2125 */
lsm6dso_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dso_st_g_t * val)2126 int32_t lsm6dso_gy_self_test_get(const stmdev_ctx_t *ctx,
2127 lsm6dso_st_g_t *val)
2128 {
2129 lsm6dso_ctrl5_c_t reg;
2130 int32_t ret;
2131
2132 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
2133
2134 switch (reg.st_g)
2135 {
2136 case LSM6DSO_GY_ST_DISABLE:
2137 *val = LSM6DSO_GY_ST_DISABLE;
2138 break;
2139
2140 case LSM6DSO_GY_ST_POSITIVE:
2141 *val = LSM6DSO_GY_ST_POSITIVE;
2142 break;
2143
2144 case LSM6DSO_GY_ST_NEGATIVE:
2145 *val = LSM6DSO_GY_ST_NEGATIVE;
2146 break;
2147
2148 default:
2149 *val = LSM6DSO_GY_ST_DISABLE;
2150 break;
2151 }
2152
2153 return ret;
2154 }
2155
2156 /**
2157 * @}
2158 *
2159 */
2160
2161 /**
2162 * @defgroup LSM6DSO_filters
2163 * @brief This section group all the functions concerning the
2164 * filters configuration
2165 * @{
2166 *
2167 */
2168
2169 /**
2170 * @brief Accelerometer output from LPF2 filtering stage selection.[set]
2171 *
2172 * @param ctx read / write interface definitions
2173 * @param val change the values of lpf2_xl_en in reg CTRL1_XL
2174 * @retval interface status (MANDATORY: return 0 -> no Error)
2175 *
2176 */
lsm6dso_xl_filter_lp2_set(const stmdev_ctx_t * ctx,uint8_t val)2177 int32_t lsm6dso_xl_filter_lp2_set(const stmdev_ctx_t *ctx, uint8_t val)
2178 {
2179 lsm6dso_ctrl1_xl_t reg;
2180 int32_t ret;
2181
2182 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
2183
2184 if (ret == 0)
2185 {
2186 reg.lpf2_xl_en = val;
2187 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
2188 }
2189
2190 return ret;
2191 }
2192
2193 /**
2194 * @brief Accelerometer output from LPF2 filtering stage selection.[get]
2195 *
2196 * @param ctx read / write interface definitions
2197 * @param val Get the values of lpf2_xl_en in reg CTRL1_XL
2198 * @retval interface status (MANDATORY: return 0 -> no Error)
2199 *
2200 */
lsm6dso_xl_filter_lp2_get(const stmdev_ctx_t * ctx,uint8_t * val)2201 int32_t lsm6dso_xl_filter_lp2_get(const stmdev_ctx_t *ctx, uint8_t *val)
2202 {
2203 lsm6dso_ctrl1_xl_t reg;
2204 int32_t ret;
2205
2206 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
2207 *val = reg.lpf2_xl_en;
2208
2209 return ret;
2210 }
2211
2212 /**
2213 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2214 * the bandwidth can be selected through FTYPE [2:0]
2215 * in CTRL6_C (15h).[set]
2216 *
2217 * @param ctx read / write interface definitions
2218 * @param val change the values of lpf1_sel_g in reg CTRL4_C
2219 * @retval interface status (MANDATORY: return 0 -> no Error)
2220 *
2221 */
lsm6dso_gy_filter_lp1_set(const stmdev_ctx_t * ctx,uint8_t val)2222 int32_t lsm6dso_gy_filter_lp1_set(const stmdev_ctx_t *ctx, uint8_t val)
2223 {
2224 lsm6dso_ctrl4_c_t reg;
2225 int32_t ret;
2226
2227 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
2228
2229 if (ret == 0)
2230 {
2231 reg.lpf1_sel_g = val;
2232 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
2233 }
2234
2235 return ret;
2236 }
2237
2238 /**
2239 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2240 * the bandwidth can be selected through FTYPE [2:0]
2241 * in CTRL6_C (15h).[get]
2242 *
2243 * @param ctx read / write interface definitions
2244 * @param val Get the values of lpf1_sel_g in reg CTRL4_C
2245 * @retval interface status (MANDATORY: return 0 -> no Error)
2246 *
2247 */
lsm6dso_gy_filter_lp1_get(const stmdev_ctx_t * ctx,uint8_t * val)2248 int32_t lsm6dso_gy_filter_lp1_get(const stmdev_ctx_t *ctx, uint8_t *val)
2249 {
2250 lsm6dso_ctrl4_c_t reg;
2251 int32_t ret;
2252
2253 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
2254 *val = reg.lpf1_sel_g;
2255
2256 return ret;
2257 }
2258
2259 /**
2260 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2261 * (XL and Gyro independently masked).[set]
2262 *
2263 * @param ctx read / write interface definitions
2264 * @param val change the values of drdy_mask in reg CTRL4_C
2265 * @retval interface status (MANDATORY: return 0 -> no Error)
2266 *
2267 */
lsm6dso_filter_settling_mask_set(const stmdev_ctx_t * ctx,uint8_t val)2268 int32_t lsm6dso_filter_settling_mask_set(const stmdev_ctx_t *ctx,
2269 uint8_t val)
2270 {
2271 lsm6dso_ctrl4_c_t reg;
2272 int32_t ret;
2273
2274 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
2275
2276 if (ret == 0)
2277 {
2278 reg.drdy_mask = val;
2279 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
2280 }
2281
2282 return ret;
2283 }
2284
2285 /**
2286 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2287 * (XL and Gyro independently masked).[get]
2288 *
2289 * @param ctx read / write interface definitions
2290 * @param val Get the values of drdy_mask in reg CTRL4_C
2291 * @retval interface status (MANDATORY: return 0 -> no Error)
2292 *
2293 */
lsm6dso_filter_settling_mask_get(const stmdev_ctx_t * ctx,uint8_t * val)2294 int32_t lsm6dso_filter_settling_mask_get(const stmdev_ctx_t *ctx,
2295 uint8_t *val)
2296 {
2297 lsm6dso_ctrl4_c_t reg;
2298 int32_t ret;
2299
2300 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
2301 *val = reg.drdy_mask;
2302
2303 return ret;
2304 }
2305
2306 /**
2307 * @brief Gyroscope lp1 bandwidth.[set]
2308 *
2309 * @param ctx read / write interface definitions
2310 * @param val change the values of ftype in reg CTRL6_C
2311 * @retval interface status (MANDATORY: return 0 -> no Error)
2312 *
2313 */
lsm6dso_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dso_ftype_t val)2314 int32_t lsm6dso_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
2315 lsm6dso_ftype_t val)
2316 {
2317 lsm6dso_ctrl6_c_t reg;
2318 int32_t ret;
2319
2320 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
2321
2322 if (ret == 0)
2323 {
2324 reg.ftype = (uint8_t)val;
2325 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
2326 }
2327
2328 return ret;
2329 }
2330
2331 /**
2332 * @brief Gyroscope lp1 bandwidth.[get]
2333 *
2334 * @param ctx read / write interface definitions
2335 * @param val Get the values of ftype in reg CTRL6_C
2336 * @retval interface status (MANDATORY: return 0 -> no Error)
2337 *
2338 */
lsm6dso_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dso_ftype_t * val)2339 int32_t lsm6dso_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
2340 lsm6dso_ftype_t *val)
2341 {
2342 lsm6dso_ctrl6_c_t reg;
2343 int32_t ret;
2344
2345 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
2346
2347 switch (reg.ftype)
2348 {
2349 case LSM6DSO_ULTRA_LIGHT:
2350 *val = LSM6DSO_ULTRA_LIGHT;
2351 break;
2352
2353 case LSM6DSO_VERY_LIGHT:
2354 *val = LSM6DSO_VERY_LIGHT;
2355 break;
2356
2357 case LSM6DSO_LIGHT:
2358 *val = LSM6DSO_LIGHT;
2359 break;
2360
2361 case LSM6DSO_MEDIUM:
2362 *val = LSM6DSO_MEDIUM;
2363 break;
2364
2365 case LSM6DSO_STRONG:
2366 *val = LSM6DSO_STRONG;
2367 break;
2368
2369 case LSM6DSO_VERY_STRONG:
2370 *val = LSM6DSO_VERY_STRONG;
2371 break;
2372
2373 case LSM6DSO_AGGRESSIVE:
2374 *val = LSM6DSO_AGGRESSIVE;
2375 break;
2376
2377 case LSM6DSO_XTREME:
2378 *val = LSM6DSO_XTREME;
2379 break;
2380
2381 default:
2382 *val = LSM6DSO_ULTRA_LIGHT;
2383 break;
2384 }
2385
2386 return ret;
2387 }
2388
2389 /**
2390 * @brief Low pass filter 2 on 6D function selection.[set]
2391 *
2392 * @param ctx read / write interface definitions
2393 * @param val change the values of low_pass_on_6d in reg CTRL8_XL
2394 * @retval interface status (MANDATORY: return 0 -> no Error)
2395 *
2396 */
lsm6dso_xl_lp2_on_6d_set(const stmdev_ctx_t * ctx,uint8_t val)2397 int32_t lsm6dso_xl_lp2_on_6d_set(const stmdev_ctx_t *ctx, uint8_t val)
2398 {
2399 lsm6dso_ctrl8_xl_t reg;
2400 int32_t ret;
2401
2402 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2403
2404 if (ret == 0)
2405 {
2406 reg.low_pass_on_6d = val;
2407 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2408 }
2409
2410 return ret;
2411 }
2412
2413 /**
2414 * @brief Low pass filter 2 on 6D function selection.[get]
2415 *
2416 * @param ctx read / write interface definitions
2417 * @param val Get the values of low_pass_on_6d in reg CTRL8_XL
2418 * @retval interface status (MANDATORY: return 0 -> no Error)
2419 *
2420 */
lsm6dso_xl_lp2_on_6d_get(const stmdev_ctx_t * ctx,uint8_t * val)2421 int32_t lsm6dso_xl_lp2_on_6d_get(const stmdev_ctx_t *ctx, uint8_t *val)
2422 {
2423 lsm6dso_ctrl8_xl_t reg;
2424 int32_t ret;
2425
2426 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2427 *val = reg.low_pass_on_6d;
2428
2429 return ret;
2430 }
2431
2432 /**
2433 * @brief Accelerometer slope filter / high-pass filter selection
2434 * on output.[set]
2435 *
2436 * @param ctx read / write interface definitions
2437 * @param val change the values of hp_slope_xl_en
2438 * in reg CTRL8_XL
2439 * @retval interface status (MANDATORY: return 0 -> no Error)
2440 *
2441 */
lsm6dso_xl_hp_path_on_out_set(const stmdev_ctx_t * ctx,lsm6dso_hp_slope_xl_en_t val)2442 int32_t lsm6dso_xl_hp_path_on_out_set(const stmdev_ctx_t *ctx,
2443 lsm6dso_hp_slope_xl_en_t val)
2444 {
2445 lsm6dso_ctrl8_xl_t reg;
2446 int32_t ret;
2447
2448 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2449
2450 if (ret == 0)
2451 {
2452 reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4;
2453 reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5;
2454 reg.hpcf_xl = (uint8_t)val & 0x07U;
2455 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2456 }
2457
2458 return ret;
2459 }
2460
2461 /**
2462 * @brief Accelerometer slope filter / high-pass filter selection
2463 * on output.[get]
2464 *
2465 * @param ctx read / write interface definitions
2466 * @param val Get the values of hp_slope_xl_en
2467 * in reg CTRL8_XL
2468 * @retval interface status (MANDATORY: return 0 -> no Error)
2469 *
2470 */
lsm6dso_xl_hp_path_on_out_get(const stmdev_ctx_t * ctx,lsm6dso_hp_slope_xl_en_t * val)2471 int32_t lsm6dso_xl_hp_path_on_out_get(const stmdev_ctx_t *ctx,
2472 lsm6dso_hp_slope_xl_en_t *val)
2473 {
2474 lsm6dso_ctrl8_xl_t reg;
2475 int32_t ret;
2476
2477 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2478
2479 switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) |
2480 reg.hpcf_xl)
2481 {
2482 case LSM6DSO_HP_PATH_DISABLE_ON_OUT:
2483 *val = LSM6DSO_HP_PATH_DISABLE_ON_OUT;
2484 break;
2485
2486 case LSM6DSO_SLOPE_ODR_DIV_4:
2487 *val = LSM6DSO_SLOPE_ODR_DIV_4;
2488 break;
2489
2490 case LSM6DSO_HP_ODR_DIV_10:
2491 *val = LSM6DSO_HP_ODR_DIV_10;
2492 break;
2493
2494 case LSM6DSO_HP_ODR_DIV_20:
2495 *val = LSM6DSO_HP_ODR_DIV_20;
2496 break;
2497
2498 case LSM6DSO_HP_ODR_DIV_45:
2499 *val = LSM6DSO_HP_ODR_DIV_45;
2500 break;
2501
2502 case LSM6DSO_HP_ODR_DIV_100:
2503 *val = LSM6DSO_HP_ODR_DIV_100;
2504 break;
2505
2506 case LSM6DSO_HP_ODR_DIV_200:
2507 *val = LSM6DSO_HP_ODR_DIV_200;
2508 break;
2509
2510 case LSM6DSO_HP_ODR_DIV_400:
2511 *val = LSM6DSO_HP_ODR_DIV_400;
2512 break;
2513
2514 case LSM6DSO_HP_ODR_DIV_800:
2515 *val = LSM6DSO_HP_ODR_DIV_800;
2516 break;
2517
2518 case LSM6DSO_HP_REF_MD_ODR_DIV_10:
2519 *val = LSM6DSO_HP_REF_MD_ODR_DIV_10;
2520 break;
2521
2522 case LSM6DSO_HP_REF_MD_ODR_DIV_20:
2523 *val = LSM6DSO_HP_REF_MD_ODR_DIV_20;
2524 break;
2525
2526 case LSM6DSO_HP_REF_MD_ODR_DIV_45:
2527 *val = LSM6DSO_HP_REF_MD_ODR_DIV_45;
2528 break;
2529
2530 case LSM6DSO_HP_REF_MD_ODR_DIV_100:
2531 *val = LSM6DSO_HP_REF_MD_ODR_DIV_100;
2532 break;
2533
2534 case LSM6DSO_HP_REF_MD_ODR_DIV_200:
2535 *val = LSM6DSO_HP_REF_MD_ODR_DIV_200;
2536 break;
2537
2538 case LSM6DSO_HP_REF_MD_ODR_DIV_400:
2539 *val = LSM6DSO_HP_REF_MD_ODR_DIV_400;
2540 break;
2541
2542 case LSM6DSO_HP_REF_MD_ODR_DIV_800:
2543 *val = LSM6DSO_HP_REF_MD_ODR_DIV_800;
2544 break;
2545
2546 case LSM6DSO_LP_ODR_DIV_10:
2547 *val = LSM6DSO_LP_ODR_DIV_10;
2548 break;
2549
2550 case LSM6DSO_LP_ODR_DIV_20:
2551 *val = LSM6DSO_LP_ODR_DIV_20;
2552 break;
2553
2554 case LSM6DSO_LP_ODR_DIV_45:
2555 *val = LSM6DSO_LP_ODR_DIV_45;
2556 break;
2557
2558 case LSM6DSO_LP_ODR_DIV_100:
2559 *val = LSM6DSO_LP_ODR_DIV_100;
2560 break;
2561
2562 case LSM6DSO_LP_ODR_DIV_200:
2563 *val = LSM6DSO_LP_ODR_DIV_200;
2564 break;
2565
2566 case LSM6DSO_LP_ODR_DIV_400:
2567 *val = LSM6DSO_LP_ODR_DIV_400;
2568 break;
2569
2570 case LSM6DSO_LP_ODR_DIV_800:
2571 *val = LSM6DSO_LP_ODR_DIV_800;
2572 break;
2573
2574 default:
2575 *val = LSM6DSO_HP_PATH_DISABLE_ON_OUT;
2576 break;
2577 }
2578
2579 return ret;
2580 }
2581
2582 /**
2583 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2584 * The filter sets the second samples after writing this bit.
2585 * Active only during device exit from power-down mode.[set]
2586 *
2587 * @param ctx read / write interface definitions
2588 * @param val change the values of fastsettl_mode_xl in
2589 * reg CTRL8_XL
2590 * @retval interface status (MANDATORY: return 0 -> no Error)
2591 *
2592 */
lsm6dso_xl_fast_settling_set(const stmdev_ctx_t * ctx,uint8_t val)2593 int32_t lsm6dso_xl_fast_settling_set(const stmdev_ctx_t *ctx, uint8_t val)
2594 {
2595 lsm6dso_ctrl8_xl_t reg;
2596 int32_t ret;
2597
2598 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2599
2600 if (ret == 0)
2601 {
2602 reg.fastsettl_mode_xl = val;
2603 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2604 }
2605
2606 return ret;
2607 }
2608
2609 /**
2610 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2611 * The filter sets the second samples after writing this bit.
2612 * Active only during device exit from power-down mode.[get]
2613 *
2614 * @param ctx read / write interface definitions
2615 * @param val Get the values of fastsettl_mode_xl in reg CTRL8_XL
2616 * @retval interface status (MANDATORY: return 0 -> no Error)
2617 *
2618 */
lsm6dso_xl_fast_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)2619 int32_t lsm6dso_xl_fast_settling_get(const stmdev_ctx_t *ctx, uint8_t *val)
2620 {
2621 lsm6dso_ctrl8_xl_t reg;
2622 int32_t ret;
2623
2624 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2625 *val = reg.fastsettl_mode_xl;
2626
2627 return ret;
2628 }
2629
2630 /**
2631 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2632 * functions.[set]
2633 *
2634 * @param ctx read / write interface definitions
2635 * @param val change the values of slope_fds in reg TAP_CFG0
2636 * @retval interface status (MANDATORY: return 0 -> no Error)
2637 *
2638 */
lsm6dso_xl_hp_path_internal_set(const stmdev_ctx_t * ctx,lsm6dso_slope_fds_t val)2639 int32_t lsm6dso_xl_hp_path_internal_set(const stmdev_ctx_t *ctx,
2640 lsm6dso_slope_fds_t val)
2641 {
2642 lsm6dso_tap_cfg0_t reg;
2643 int32_t ret;
2644
2645 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
2646
2647 if (ret == 0)
2648 {
2649 reg.slope_fds = (uint8_t)val;
2650 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
2651 }
2652
2653 return ret;
2654 }
2655
2656 /**
2657 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2658 * functions.[get]
2659 *
2660 * @param ctx read / write interface definitions
2661 * @param val Get the values of slope_fds in reg TAP_CFG0
2662 * @retval interface status (MANDATORY: return 0 -> no Error)
2663 *
2664 */
lsm6dso_xl_hp_path_internal_get(const stmdev_ctx_t * ctx,lsm6dso_slope_fds_t * val)2665 int32_t lsm6dso_xl_hp_path_internal_get(const stmdev_ctx_t *ctx,
2666 lsm6dso_slope_fds_t *val)
2667 {
2668 lsm6dso_tap_cfg0_t reg;
2669 int32_t ret;
2670
2671 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
2672
2673 switch (reg.slope_fds)
2674 {
2675 case LSM6DSO_USE_SLOPE:
2676 *val = LSM6DSO_USE_SLOPE;
2677 break;
2678
2679 case LSM6DSO_USE_HPF:
2680 *val = LSM6DSO_USE_HPF;
2681 break;
2682
2683 default:
2684 *val = LSM6DSO_USE_SLOPE;
2685 break;
2686 }
2687
2688 return ret;
2689 }
2690
2691 /**
2692 * @brief Enables gyroscope digital high-pass filter. The filter is
2693 * enabled only if the gyro is in HP mode.[set]
2694 *
2695 * @param ctx read / write interface definitions
2696 * @param val change the values of hp_en_g and hp_en_g
2697 * in reg CTRL7_G
2698 * @retval interface status (MANDATORY: return 0 -> no Error)
2699 *
2700 */
lsm6dso_gy_hp_path_internal_set(const stmdev_ctx_t * ctx,lsm6dso_hpm_g_t val)2701 int32_t lsm6dso_gy_hp_path_internal_set(const stmdev_ctx_t *ctx,
2702 lsm6dso_hpm_g_t val)
2703 {
2704 lsm6dso_ctrl7_g_t reg;
2705 int32_t ret;
2706
2707 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
2708
2709 if (ret == 0)
2710 {
2711 reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
2712 reg.hpm_g = (uint8_t)val & 0x03U;
2713 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
2714 }
2715
2716 return ret;
2717 }
2718
2719 /**
2720 * @brief Enables gyroscope digital high-pass filter. The filter is
2721 * enabled only if the gyro is in HP mode.[get]
2722 *
2723 * @param ctx read / write interface definitions
2724 * @param val Get the values of hp_en_g and hp_en_g
2725 * in reg CTRL7_G
2726 * @retval interface status (MANDATORY: return 0 -> no Error)
2727 *
2728 */
lsm6dso_gy_hp_path_internal_get(const stmdev_ctx_t * ctx,lsm6dso_hpm_g_t * val)2729 int32_t lsm6dso_gy_hp_path_internal_get(const stmdev_ctx_t *ctx,
2730 lsm6dso_hpm_g_t *val)
2731 {
2732 lsm6dso_ctrl7_g_t reg;
2733 int32_t ret;
2734
2735 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
2736
2737 switch ((reg.hp_en_g << 7) + reg.hpm_g)
2738 {
2739 case LSM6DSO_HP_FILTER_NONE:
2740 *val = LSM6DSO_HP_FILTER_NONE;
2741 break;
2742
2743 case LSM6DSO_HP_FILTER_16mHz:
2744 *val = LSM6DSO_HP_FILTER_16mHz;
2745 break;
2746
2747 case LSM6DSO_HP_FILTER_65mHz:
2748 *val = LSM6DSO_HP_FILTER_65mHz;
2749 break;
2750
2751 case LSM6DSO_HP_FILTER_260mHz:
2752 *val = LSM6DSO_HP_FILTER_260mHz;
2753 break;
2754
2755 case LSM6DSO_HP_FILTER_1Hz04:
2756 *val = LSM6DSO_HP_FILTER_1Hz04;
2757 break;
2758
2759 default:
2760 *val = LSM6DSO_HP_FILTER_NONE;
2761 break;
2762 }
2763
2764 return ret;
2765 }
2766
2767 /**
2768 * @}
2769 *
2770 */
2771
2772 /**
2773 * @defgroup LSM6DSO_ Auxiliary_interface
2774 * @brief This section groups all the functions concerning
2775 * auxiliary interface.
2776 * @{
2777 *
2778 */
2779
2780 /**
2781 * @brief aOn auxiliary interface connect/disconnect SDO and OCS
2782 * internal pull-up.[set]
2783 *
2784 * @param ctx read / write interface definitions
2785 * @param val change the values of ois_pu_dis in
2786 * reg PIN_CTRL
2787 * @retval interface status (MANDATORY: return 0 -> no Error)
2788 *
2789 */
lsm6dso_aux_sdo_ocs_mode_set(const stmdev_ctx_t * ctx,lsm6dso_ois_pu_dis_t val)2790 int32_t lsm6dso_aux_sdo_ocs_mode_set(const stmdev_ctx_t *ctx,
2791 lsm6dso_ois_pu_dis_t val)
2792 {
2793 lsm6dso_pin_ctrl_t reg;
2794 int32_t ret;
2795
2796 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1);
2797
2798 if (ret == 0)
2799 {
2800 reg.ois_pu_dis = (uint8_t)val;
2801 ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1);
2802 }
2803
2804 return ret;
2805 }
2806
2807 /**
2808 * @brief On auxiliary interface connect/disconnect SDO and OCS
2809 * internal pull-up.[get]
2810 *
2811 * @param ctx read / write interface definitions
2812 * @param val Get the values of ois_pu_dis in reg PIN_CTRL
2813 * @retval interface status (MANDATORY: return 0 -> no Error)
2814 *
2815 */
lsm6dso_aux_sdo_ocs_mode_get(const stmdev_ctx_t * ctx,lsm6dso_ois_pu_dis_t * val)2816 int32_t lsm6dso_aux_sdo_ocs_mode_get(const stmdev_ctx_t *ctx,
2817 lsm6dso_ois_pu_dis_t *val)
2818 {
2819 lsm6dso_pin_ctrl_t reg;
2820 int32_t ret;
2821
2822 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1);
2823
2824 switch (reg.ois_pu_dis)
2825 {
2826 case LSM6DSO_AUX_PULL_UP_DISC:
2827 *val = LSM6DSO_AUX_PULL_UP_DISC;
2828 break;
2829
2830 case LSM6DSO_AUX_PULL_UP_CONNECT:
2831 *val = LSM6DSO_AUX_PULL_UP_CONNECT;
2832 break;
2833
2834 default:
2835 *val = LSM6DSO_AUX_PULL_UP_DISC;
2836 break;
2837 }
2838
2839 return ret;
2840 }
2841
2842 /**
2843 * @brief OIS chain on aux interface power on mode.[set]
2844 *
2845 * @param ctx read / write interface definitions
2846 * @param val change the values of ois_on in reg CTRL7_G
2847 * @retval interface status (MANDATORY: return 0 -> no Error)
2848 *
2849 */
lsm6dso_aux_pw_on_ctrl_set(const stmdev_ctx_t * ctx,lsm6dso_ois_on_t val)2850 int32_t lsm6dso_aux_pw_on_ctrl_set(const stmdev_ctx_t *ctx,
2851 lsm6dso_ois_on_t val)
2852 {
2853 lsm6dso_ctrl7_g_t reg;
2854 int32_t ret;
2855
2856 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
2857
2858 if (ret == 0)
2859 {
2860 reg.ois_on_en = (uint8_t)val & 0x01U;
2861 reg.ois_on = (uint8_t)val & 0x01U;
2862 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
2863 }
2864
2865 return ret;
2866 }
2867
2868 /**
2869 * @brief aux_pw_on_ctrl: [get] OIS chain on aux interface power on mode
2870 *
2871 * @param ctx read / write interface definitions
2872 * @param val Get the values of ois_on in reg CTRL7_G
2873 * @retval interface status (MANDATORY: return 0 -> no Error)
2874 *
2875 */
lsm6dso_aux_pw_on_ctrl_get(const stmdev_ctx_t * ctx,lsm6dso_ois_on_t * val)2876 int32_t lsm6dso_aux_pw_on_ctrl_get(const stmdev_ctx_t *ctx,
2877 lsm6dso_ois_on_t *val)
2878 {
2879 lsm6dso_ctrl7_g_t reg;
2880 int32_t ret;
2881
2882 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
2883
2884 switch (reg.ois_on)
2885 {
2886 case LSM6DSO_AUX_ON:
2887 *val = LSM6DSO_AUX_ON;
2888 break;
2889
2890 case LSM6DSO_AUX_ON_BY_AUX_INTERFACE:
2891 *val = LSM6DSO_AUX_ON_BY_AUX_INTERFACE;
2892 break;
2893
2894 default:
2895 *val = LSM6DSO_AUX_ON;
2896 break;
2897 }
2898
2899 return ret;
2900 }
2901
2902 /**
2903 * @brief Accelerometer full-scale management between UI chain and
2904 * OIS chain. When XL UI is on, the full scale is the same
2905 * between UI/OIS and is chosen by the UI CTRL registers;
2906 * when XL UI is in PD, the OIS can choose the FS.
2907 * Full scales are independent between the UI/OIS chain
2908 * but both bound to 8 g.[set]
2909 *
2910 * @param ctx read / write interface definitions
2911 * @param val change the values of xl_fs_mode in
2912 * reg CTRL8_XL
2913 * @retval interface status (MANDATORY: return 0 -> no Error)
2914 *
2915 */
lsm6dso_aux_xl_fs_mode_set(const stmdev_ctx_t * ctx,lsm6dso_xl_fs_mode_t val)2916 int32_t lsm6dso_aux_xl_fs_mode_set(const stmdev_ctx_t *ctx,
2917 lsm6dso_xl_fs_mode_t val)
2918 {
2919 lsm6dso_ctrl8_xl_t reg;
2920 int32_t ret;
2921
2922 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2923
2924 if (ret == 0)
2925 {
2926 reg.xl_fs_mode = (uint8_t)val;
2927 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2928 }
2929
2930 return ret;
2931 }
2932
2933 /**
2934 * @brief Accelerometer full-scale management between UI chain and
2935 * OIS chain. When XL UI is on, the full scale is the same
2936 * between UI/OIS and is chosen by the UI CTRL registers;
2937 * when XL UI is in PD, the OIS can choose the FS.
2938 * Full scales are independent between the UI/OIS chain
2939 * but both bound to 8 g.[get]
2940 *
2941 * @param ctx read / write interface definitions
2942 * @param val Get the values of xl_fs_mode in reg CTRL8_XL
2943 * @retval interface status (MANDATORY: return 0 -> no Error)
2944 *
2945 */
lsm6dso_aux_xl_fs_mode_get(const stmdev_ctx_t * ctx,lsm6dso_xl_fs_mode_t * val)2946 int32_t lsm6dso_aux_xl_fs_mode_get(const stmdev_ctx_t *ctx,
2947 lsm6dso_xl_fs_mode_t *val)
2948 {
2949 lsm6dso_ctrl8_xl_t reg;
2950 int32_t ret;
2951
2952 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2953
2954 switch (reg.xl_fs_mode)
2955 {
2956 case LSM6DSO_USE_SAME_XL_FS:
2957 *val = LSM6DSO_USE_SAME_XL_FS;
2958 break;
2959
2960 case LSM6DSO_USE_DIFFERENT_XL_FS:
2961 *val = LSM6DSO_USE_DIFFERENT_XL_FS;
2962 break;
2963
2964 default:
2965 *val = LSM6DSO_USE_SAME_XL_FS;
2966 break;
2967 }
2968
2969 return ret;
2970 }
2971
2972 /**
2973 * @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get]
2974 *
2975 * @param ctx read / write interface definitions
2976 * @param lsm6dso_status_spiaux_t: registers STATUS_SPIAUX
2977 * @retval interface status (MANDATORY: return 0 -> no Error)
2978 *
2979 */
lsm6dso_aux_status_reg_get(const stmdev_ctx_t * ctx,lsm6dso_status_spiaux_t * val)2980 int32_t lsm6dso_aux_status_reg_get(const stmdev_ctx_t *ctx,
2981 lsm6dso_status_spiaux_t *val)
2982 {
2983 int32_t ret;
2984
2985 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *) val, 1);
2986
2987 return ret;
2988 }
2989
2990 /**
2991 * @brief aux_xl_flag_data_ready: [get] AUX accelerometer data available
2992 *
2993 * @param ctx read / write interface definitions
2994 * @param val Get the values of xlda in reg STATUS_SPIAUX
2995 * @retval interface status (MANDATORY: return 0 -> no Error)
2996 *
2997 */
lsm6dso_aux_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)2998 int32_t lsm6dso_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
2999 uint8_t *val)
3000 {
3001 lsm6dso_status_spiaux_t reg;
3002 int32_t ret;
3003
3004 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *)®, 1);
3005 *val = reg.xlda;
3006
3007 return ret;
3008 }
3009
3010 /**
3011 * @brief aux_gy_flag_data_ready: [get] AUX gyroscope data available.
3012 *
3013 * @param ctx read / write interface definitions
3014 * @param val Get the values of gda in reg STATUS_SPIAUX
3015 * @retval interface status (MANDATORY: return 0 -> no Error)
3016 *
3017 */
lsm6dso_aux_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)3018 int32_t lsm6dso_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx,
3019 uint8_t *val)
3020 {
3021 lsm6dso_status_spiaux_t reg;
3022 int32_t ret;
3023
3024 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *)®, 1);
3025 *val = reg.gda;
3026
3027 return ret;
3028 }
3029
3030 /**
3031 * @brief High when the gyroscope output is in the settling phase.[get]
3032 *
3033 * @param ctx read / write interface definitions
3034 * @param val Get the values of gyro_settling in reg STATUS_SPIAUX
3035 * @retval interface status (MANDATORY: return 0 -> no Error)
3036 *
3037 */
lsm6dso_aux_gy_flag_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)3038 int32_t lsm6dso_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx,
3039 uint8_t *val)
3040 {
3041 lsm6dso_status_spiaux_t reg;
3042 int32_t ret;
3043
3044 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *)®, 1);
3045 *val = reg.gyro_settling;
3046
3047 return ret;
3048 }
3049
3050 /**
3051 * @brief Selects accelerometer self-test. Effective only if XL OIS
3052 * chain is enabled.[set]
3053 *
3054 * @param ctx read / write interface definitions
3055 * @param val change the values of st_xl_ois in reg INT_OIS
3056 * @retval interface status (MANDATORY: return 0 -> no Error)
3057 *
3058 */
lsm6dso_aux_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6dso_st_xl_ois_t val)3059 int32_t lsm6dso_aux_xl_self_test_set(const stmdev_ctx_t *ctx,
3060 lsm6dso_st_xl_ois_t val)
3061 {
3062 lsm6dso_int_ois_t reg;
3063 int32_t ret;
3064
3065 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
3066
3067 if (ret == 0)
3068 {
3069 reg.st_xl_ois = (uint8_t)val;
3070 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
3071 }
3072
3073 return ret;
3074 }
3075
3076 /**
3077 * @brief Selects accelerometer self-test. Effective only if XL OIS
3078 * chain is enabled.[get]
3079 *
3080 * @param ctx read / write interface definitions
3081 * @param val Get the values of st_xl_ois in reg INT_OIS
3082 * @retval interface status (MANDATORY: return 0 -> no Error)
3083 *
3084 */
lsm6dso_aux_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6dso_st_xl_ois_t * val)3085 int32_t lsm6dso_aux_xl_self_test_get(const stmdev_ctx_t *ctx,
3086 lsm6dso_st_xl_ois_t *val)
3087 {
3088 lsm6dso_int_ois_t reg;
3089 int32_t ret;
3090
3091 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
3092
3093 switch (reg.st_xl_ois)
3094 {
3095 case LSM6DSO_AUX_XL_DISABLE:
3096 *val = LSM6DSO_AUX_XL_DISABLE;
3097 break;
3098
3099 case LSM6DSO_AUX_XL_POS:
3100 *val = LSM6DSO_AUX_XL_POS;
3101 break;
3102
3103 case LSM6DSO_AUX_XL_NEG:
3104 *val = LSM6DSO_AUX_XL_NEG;
3105 break;
3106
3107 default:
3108 *val = LSM6DSO_AUX_XL_DISABLE;
3109 break;
3110 }
3111
3112 return ret;
3113 }
3114
3115 /**
3116 * @brief Indicates polarity of DEN signal on OIS chain.[set]
3117 *
3118 * @param ctx read / write interface definitions
3119 * @param val change the values of den_lh_ois in
3120 * reg INT_OIS
3121 * @retval interface status (MANDATORY: return 0 -> no Error)
3122 *
3123 */
lsm6dso_aux_den_polarity_set(const stmdev_ctx_t * ctx,lsm6dso_den_lh_ois_t val)3124 int32_t lsm6dso_aux_den_polarity_set(const stmdev_ctx_t *ctx,
3125 lsm6dso_den_lh_ois_t val)
3126 {
3127 lsm6dso_int_ois_t reg;
3128 int32_t ret;
3129
3130 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
3131
3132 if (ret == 0)
3133 {
3134 reg.den_lh_ois = (uint8_t)val;
3135 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
3136 }
3137
3138 return ret;
3139 }
3140
3141 /**
3142 * @brief Indicates polarity of DEN signal on OIS chain.[get]
3143 *
3144 * @param ctx read / write interface definitions
3145 * @param val Get the values of den_lh_ois in reg INT_OIS
3146 * @retval interface status (MANDATORY: return 0 -> no Error)
3147 *
3148 */
lsm6dso_aux_den_polarity_get(const stmdev_ctx_t * ctx,lsm6dso_den_lh_ois_t * val)3149 int32_t lsm6dso_aux_den_polarity_get(const stmdev_ctx_t *ctx,
3150 lsm6dso_den_lh_ois_t *val)
3151 {
3152 lsm6dso_int_ois_t reg;
3153 int32_t ret;
3154
3155 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
3156
3157 switch (reg.den_lh_ois)
3158 {
3159 case LSM6DSO_AUX_DEN_ACTIVE_LOW:
3160 *val = LSM6DSO_AUX_DEN_ACTIVE_LOW;
3161 break;
3162
3163 case LSM6DSO_AUX_DEN_ACTIVE_HIGH:
3164 *val = LSM6DSO_AUX_DEN_ACTIVE_HIGH;
3165 break;
3166
3167 default:
3168 *val = LSM6DSO_AUX_DEN_ACTIVE_LOW;
3169 break;
3170 }
3171
3172 return ret;
3173 }
3174
3175 /**
3176 * @brief Configure DEN mode on the OIS chain.[set]
3177 *
3178 * @param ctx read / write interface definitions
3179 * @param val change the values of lvl2_ois in reg INT_OIS
3180 * @retval interface status (MANDATORY: return 0 -> no Error)
3181 *
3182 */
lsm6dso_aux_den_mode_set(const stmdev_ctx_t * ctx,lsm6dso_lvl2_ois_t val)3183 int32_t lsm6dso_aux_den_mode_set(const stmdev_ctx_t *ctx,
3184 lsm6dso_lvl2_ois_t val)
3185 {
3186 lsm6dso_ctrl1_ois_t ctrl1_ois;
3187 lsm6dso_int_ois_t int_ois;
3188 int32_t ret;
3189
3190 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *) &int_ois, 1);
3191 int_ois.lvl2_ois = (uint8_t)val & 0x01U;
3192 ret += lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *) &int_ois, 1);
3193 if (ret != 0) { return ret; }
3194
3195 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *) &ctrl1_ois, 1);
3196 ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
3197 ret += lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS,
3198 (uint8_t *) &ctrl1_ois, 1);
3199
3200 return ret;
3201 }
3202
3203 /**
3204 * @brief Configure DEN mode on the OIS chain.[get]
3205 *
3206 * @param ctx read / write interface definitions
3207 * @param val Get the values of lvl2_ois in reg INT_OIS
3208 * @retval interface status (MANDATORY: return 0 -> no Error)
3209 *
3210 */
lsm6dso_aux_den_mode_get(const stmdev_ctx_t * ctx,lsm6dso_lvl2_ois_t * val)3211 int32_t lsm6dso_aux_den_mode_get(const stmdev_ctx_t *ctx,
3212 lsm6dso_lvl2_ois_t *val)
3213 {
3214 lsm6dso_ctrl1_ois_t ctrl1_ois;
3215 lsm6dso_int_ois_t int_ois;
3216 int32_t ret;
3217
3218 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *) &int_ois, 1);
3219 if (ret != 0) { return ret; }
3220
3221 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *) &ctrl1_ois, 1);
3222 if (ret != 0) { return ret; }
3223
3224 switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois)
3225 {
3226 case LSM6DSO_AUX_DEN_DISABLE:
3227 *val = LSM6DSO_AUX_DEN_DISABLE;
3228 break;
3229
3230 case LSM6DSO_AUX_DEN_LEVEL_LATCH:
3231 *val = LSM6DSO_AUX_DEN_LEVEL_LATCH;
3232 break;
3233
3234 case LSM6DSO_AUX_DEN_LEVEL_TRIG:
3235 *val = LSM6DSO_AUX_DEN_LEVEL_TRIG;
3236 break;
3237
3238 default:
3239 *val = LSM6DSO_AUX_DEN_DISABLE;
3240 break;
3241 }
3242
3243 return ret;
3244 }
3245
3246 /**
3247 * @brief Enables/Disable OIS chain DRDY on INT2 pin.
3248 * This setting has priority over all other INT2 settings.[set]
3249 *
3250 * @param ctx read / write interface definitions
3251 * @param val change the values of int2_drdy_ois in reg INT_OIS
3252 * @retval interface status (MANDATORY: return 0 -> no Error)
3253 *
3254 */
lsm6dso_aux_drdy_on_int2_set(const stmdev_ctx_t * ctx,uint8_t val)3255 int32_t lsm6dso_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val)
3256 {
3257 lsm6dso_int_ois_t reg;
3258 int32_t ret;
3259
3260 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
3261
3262 if (ret == 0)
3263 {
3264 reg.int2_drdy_ois = val;
3265 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
3266 }
3267
3268 return ret;
3269 }
3270
3271 /**
3272 * @brief Enables/Disable OIS chain DRDY on INT2 pin.
3273 * This setting has priority over all other INT2 settings.[get]
3274 *
3275 * @param ctx read / write interface definitions
3276 * @param val Get the values of int2_drdy_ois in reg INT_OIS
3277 * @retval interface status (MANDATORY: return 0 -> no Error)
3278 *
3279 */
lsm6dso_aux_drdy_on_int2_get(const stmdev_ctx_t * ctx,uint8_t * val)3280 int32_t lsm6dso_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val)
3281 {
3282 lsm6dso_int_ois_t reg;
3283 int32_t ret;
3284
3285 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
3286 *val = reg.int2_drdy_ois;
3287
3288 return ret;
3289 }
3290
3291 /**
3292 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
3293 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
3294 * When the OIS chain is enabled, the OIS outputs are available
3295 * through the SPI2 in registers OUTX_L_G (22h) through
3296 * OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
3297 * LPF1 is dedicated to this chain.[set]
3298 *
3299 * @param ctx read / write interface definitions
3300 * @param val change the values of ois_en_spi2 in
3301 * reg CTRL1_OIS
3302 * @retval interface status (MANDATORY: return 0 -> no Error)
3303 *
3304 */
lsm6dso_aux_mode_set(const stmdev_ctx_t * ctx,lsm6dso_ois_en_spi2_t val)3305 int32_t lsm6dso_aux_mode_set(const stmdev_ctx_t *ctx,
3306 lsm6dso_ois_en_spi2_t val)
3307 {
3308 lsm6dso_ctrl1_ois_t reg;
3309 int32_t ret;
3310
3311 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
3312
3313 if (ret == 0)
3314 {
3315 reg.ois_en_spi2 = (uint8_t)val & 0x01U;
3316 reg.mode4_en = ((uint8_t)val & 0x02U) >> 1;
3317 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
3318 }
3319
3320 return ret;
3321 }
3322
3323 /**
3324 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
3325 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
3326 * When the OIS chain is enabled, the OIS outputs are available
3327 * through the SPI2 in registers OUTX_L_G (22h) through
3328 * OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
3329 * LPF1 is dedicated to this chain.[get]
3330 *
3331 * @param ctx read / write interface definitions
3332 * @param val Get the values of ois_en_spi2 in
3333 * reg CTRL1_OIS
3334 * @retval interface status (MANDATORY: return 0 -> no Error)
3335 *
3336 */
lsm6dso_aux_mode_get(const stmdev_ctx_t * ctx,lsm6dso_ois_en_spi2_t * val)3337 int32_t lsm6dso_aux_mode_get(const stmdev_ctx_t *ctx,
3338 lsm6dso_ois_en_spi2_t *val)
3339 {
3340 lsm6dso_ctrl1_ois_t reg;
3341 int32_t ret;
3342
3343 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
3344
3345 switch ((reg.mode4_en << 1) | reg.ois_en_spi2)
3346 {
3347 case LSM6DSO_AUX_DISABLE:
3348 *val = LSM6DSO_AUX_DISABLE;
3349 break;
3350
3351 case LSM6DSO_MODE_3_GY:
3352 *val = LSM6DSO_MODE_3_GY;
3353 break;
3354
3355 case LSM6DSO_MODE_4_GY_XL:
3356 *val = LSM6DSO_MODE_4_GY_XL;
3357 break;
3358
3359 default:
3360 *val = LSM6DSO_AUX_DISABLE;
3361 break;
3362 }
3363
3364 return ret;
3365 }
3366
3367 /**
3368 * @brief Selects gyroscope OIS chain full-scale.[set]
3369 *
3370 * @param ctx read / write interface definitions
3371 * @param val change the values of fs_g_ois in reg CTRL1_OIS
3372 * @retval interface status (MANDATORY: return 0 -> no Error)
3373 *
3374 */
lsm6dso_aux_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dso_fs_g_ois_t val)3375 int32_t lsm6dso_aux_gy_full_scale_set(const stmdev_ctx_t *ctx,
3376 lsm6dso_fs_g_ois_t val)
3377 {
3378 lsm6dso_ctrl1_ois_t reg;
3379 int32_t ret;
3380
3381 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
3382
3383 if (ret == 0)
3384 {
3385 reg.fs_g_ois = (uint8_t)val;
3386 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
3387 }
3388
3389 return ret;
3390 }
3391
3392 /**
3393 * @brief Selects gyroscope OIS chain full-scale.[get]
3394 *
3395 * @param ctx read / write interface definitions
3396 * @param val Get the values of fs_g_ois in reg CTRL1_OIS
3397 * @retval interface status (MANDATORY: return 0 -> no Error)
3398 *
3399 */
lsm6dso_aux_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dso_fs_g_ois_t * val)3400 int32_t lsm6dso_aux_gy_full_scale_get(const stmdev_ctx_t *ctx,
3401 lsm6dso_fs_g_ois_t *val)
3402 {
3403 lsm6dso_ctrl1_ois_t reg;
3404 int32_t ret;
3405
3406 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
3407
3408 switch (reg.fs_g_ois)
3409 {
3410 case LSM6DSO_250dps_AUX:
3411 *val = LSM6DSO_250dps_AUX;
3412 break;
3413
3414 case LSM6DSO_125dps_AUX:
3415 *val = LSM6DSO_125dps_AUX;
3416 break;
3417
3418 case LSM6DSO_500dps_AUX:
3419 *val = LSM6DSO_500dps_AUX;
3420 break;
3421
3422 case LSM6DSO_1000dps_AUX:
3423 *val = LSM6DSO_1000dps_AUX;
3424 break;
3425
3426 case LSM6DSO_2000dps_AUX:
3427 *val = LSM6DSO_2000dps_AUX;
3428 break;
3429
3430 default:
3431 *val = LSM6DSO_250dps_AUX;
3432 break;
3433 }
3434
3435 return ret;
3436 }
3437
3438 /**
3439 * @brief SPI2 3- or 4-wire interface.[set]
3440 *
3441 * @param ctx read / write interface definitions
3442 * @param val change the values of sim_ois in reg CTRL1_OIS
3443 * @retval interface status (MANDATORY: return 0 -> no Error)
3444 *
3445 */
lsm6dso_aux_spi_mode_set(const stmdev_ctx_t * ctx,lsm6dso_sim_ois_t val)3446 int32_t lsm6dso_aux_spi_mode_set(const stmdev_ctx_t *ctx,
3447 lsm6dso_sim_ois_t val)
3448 {
3449 lsm6dso_ctrl1_ois_t reg;
3450 int32_t ret;
3451
3452 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
3453
3454 if (ret == 0)
3455 {
3456 reg.sim_ois = (uint8_t)val;
3457 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
3458 }
3459
3460 return ret;
3461 }
3462
3463 /**
3464 * @brief SPI2 3- or 4-wire interface.[get]
3465 *
3466 * @param ctx read / write interface definitions
3467 * @param val Get the values of sim_ois in reg CTRL1_OIS
3468 * @retval interface status (MANDATORY: return 0 -> no Error)
3469 *
3470 */
lsm6dso_aux_spi_mode_get(const stmdev_ctx_t * ctx,lsm6dso_sim_ois_t * val)3471 int32_t lsm6dso_aux_spi_mode_get(const stmdev_ctx_t *ctx,
3472 lsm6dso_sim_ois_t *val)
3473 {
3474 lsm6dso_ctrl1_ois_t reg;
3475 int32_t ret;
3476
3477 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
3478
3479 switch (reg.sim_ois)
3480 {
3481 case LSM6DSO_AUX_SPI_4_WIRE:
3482 *val = LSM6DSO_AUX_SPI_4_WIRE;
3483 break;
3484
3485 case LSM6DSO_AUX_SPI_3_WIRE:
3486 *val = LSM6DSO_AUX_SPI_3_WIRE;
3487 break;
3488
3489 default:
3490 *val = LSM6DSO_AUX_SPI_4_WIRE;
3491 break;
3492 }
3493
3494 return ret;
3495 }
3496
3497 /**
3498 * @brief Selects gyroscope digital LPF1 filter bandwidth.[set]
3499 *
3500 * @param ctx read / write interface definitions
3501 * @param val change the values of ftype_ois in
3502 * reg CTRL2_OIS
3503 * @retval interface status (MANDATORY: return 0 -> no Error)
3504 *
3505 */
lsm6dso_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dso_ftype_ois_t val)3506 int32_t lsm6dso_aux_gy_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
3507 lsm6dso_ftype_ois_t val)
3508 {
3509 lsm6dso_ctrl2_ois_t reg;
3510 int32_t ret;
3511
3512 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1);
3513
3514 if (ret == 0)
3515 {
3516 reg.ftype_ois = (uint8_t)val;
3517 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1);
3518 }
3519
3520 return ret;
3521 }
3522
3523 /**
3524 * @brief Selects gyroscope digital LPF1 filter bandwidth.[get]
3525 *
3526 * @param ctx read / write interface definitions
3527 * @param val Get the values of ftype_ois in reg CTRL2_OIS
3528 * @retval interface status (MANDATORY: return 0 -> no Error)
3529 *
3530 */
lsm6dso_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dso_ftype_ois_t * val)3531 int32_t lsm6dso_aux_gy_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
3532 lsm6dso_ftype_ois_t *val)
3533 {
3534 lsm6dso_ctrl2_ois_t reg;
3535 int32_t ret;
3536
3537 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1);
3538
3539 switch (reg.ftype_ois)
3540 {
3541 case LSM6DSO_351Hz39:
3542 *val = LSM6DSO_351Hz39;
3543 break;
3544
3545 case LSM6DSO_236Hz63:
3546 *val = LSM6DSO_236Hz63;
3547 break;
3548
3549 case LSM6DSO_172Hz70:
3550 *val = LSM6DSO_172Hz70;
3551 break;
3552
3553 case LSM6DSO_937Hz91:
3554 *val = LSM6DSO_937Hz91;
3555 break;
3556
3557 default:
3558 *val = LSM6DSO_351Hz39;
3559 break;
3560 }
3561
3562 return ret;
3563 }
3564
3565 /**
3566 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[set]
3567 *
3568 * @param ctx read / write interface definitions
3569 * @param val change the values of hpm_ois in reg CTRL2_OIS
3570 * @retval interface status (MANDATORY: return 0 -> no Error)
3571 *
3572 */
lsm6dso_aux_gy_hp_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dso_hpm_ois_t val)3573 int32_t lsm6dso_aux_gy_hp_bandwidth_set(const stmdev_ctx_t *ctx,
3574 lsm6dso_hpm_ois_t val)
3575 {
3576 lsm6dso_ctrl2_ois_t reg;
3577 int32_t ret;
3578
3579 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1);
3580
3581 if (ret == 0)
3582 {
3583 reg.hpm_ois = (uint8_t)val & 0x03U;
3584 reg.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
3585 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1);
3586 }
3587
3588 return ret;
3589 }
3590
3591 /**
3592 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[get]
3593 *
3594 * @param ctx read / write interface definitions
3595 * @param val Get the values of hpm_ois in reg CTRL2_OIS
3596 * @retval interface status (MANDATORY: return 0 -> no Error)
3597 *
3598 */
lsm6dso_aux_gy_hp_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dso_hpm_ois_t * val)3599 int32_t lsm6dso_aux_gy_hp_bandwidth_get(const stmdev_ctx_t *ctx,
3600 lsm6dso_hpm_ois_t *val)
3601 {
3602 lsm6dso_ctrl2_ois_t reg;
3603 int32_t ret;
3604
3605 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1);
3606
3607 switch ((reg.hp_en_ois << 4) | reg.hpm_ois)
3608 {
3609 case LSM6DSO_AUX_HP_DISABLE:
3610 *val = LSM6DSO_AUX_HP_DISABLE;
3611 break;
3612
3613 case LSM6DSO_AUX_HP_Hz016:
3614 *val = LSM6DSO_AUX_HP_Hz016;
3615 break;
3616
3617 case LSM6DSO_AUX_HP_Hz065:
3618 *val = LSM6DSO_AUX_HP_Hz065;
3619 break;
3620
3621 case LSM6DSO_AUX_HP_Hz260:
3622 *val = LSM6DSO_AUX_HP_Hz260;
3623 break;
3624
3625 case LSM6DSO_AUX_HP_1Hz040:
3626 *val = LSM6DSO_AUX_HP_1Hz040;
3627 break;
3628
3629 default:
3630 *val = LSM6DSO_AUX_HP_DISABLE;
3631 break;
3632 }
3633
3634 return ret;
3635 }
3636
3637 /**
3638 * @brief Enable / Disables OIS chain clamp.
3639 * Enable: All OIS chain outputs = 8000h
3640 * during self-test; Disable: OIS chain self-test
3641 * outputs dependent from the aux gyro full
3642 * scale selected.[set]
3643 *
3644 * @param ctx read / write interface definitions
3645 * @param val change the values of st_ois_clampdis in
3646 * reg CTRL3_OIS
3647 * @retval interface status (MANDATORY: return 0 -> no Error)
3648 *
3649 */
lsm6dso_aux_gy_clamp_set(const stmdev_ctx_t * ctx,lsm6dso_st_ois_clampdis_t val)3650 int32_t lsm6dso_aux_gy_clamp_set(const stmdev_ctx_t *ctx,
3651 lsm6dso_st_ois_clampdis_t val)
3652 {
3653 lsm6dso_ctrl3_ois_t reg;
3654 int32_t ret;
3655
3656 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3657
3658 if (ret == 0)
3659 {
3660 reg.st_ois_clampdis = (uint8_t)val;
3661 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3662 }
3663
3664 return ret;
3665 }
3666
3667 /**
3668 * @brief Enable / Disables OIS chain clamp.
3669 * Enable: All OIS chain outputs = 8000h
3670 * during self-test; Disable: OIS chain self-test
3671 * outputs dependent from the aux gyro full
3672 * scale selected.[set]
3673 *
3674 * @param ctx read / write interface definitions
3675 * @param val Get the values of st_ois_clampdis in
3676 * reg CTRL3_OIS
3677 * @retval interface status (MANDATORY: return 0 -> no Error)
3678 *
3679 */
lsm6dso_aux_gy_clamp_get(const stmdev_ctx_t * ctx,lsm6dso_st_ois_clampdis_t * val)3680 int32_t lsm6dso_aux_gy_clamp_get(const stmdev_ctx_t *ctx,
3681 lsm6dso_st_ois_clampdis_t *val)
3682 {
3683 lsm6dso_ctrl3_ois_t reg;
3684 int32_t ret;
3685
3686 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3687
3688 switch (reg.st_ois_clampdis)
3689 {
3690 case LSM6DSO_ENABLE_CLAMP:
3691 *val = LSM6DSO_ENABLE_CLAMP;
3692 break;
3693
3694 case LSM6DSO_DISABLE_CLAMP:
3695 *val = LSM6DSO_DISABLE_CLAMP;
3696 break;
3697
3698 default:
3699 *val = LSM6DSO_ENABLE_CLAMP;
3700 break;
3701 }
3702
3703 return ret;
3704 }
3705
3706 /**
3707 * @brief Selects gyroscope OIS chain self-test.[set]
3708 *
3709 * @param ctx read / write interface definitions
3710 * @param val change the values of st_ois in reg CTRL3_OIS
3711 * @retval interface status (MANDATORY: return 0 -> no Error)
3712 *
3713 */
lsm6dso_aux_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dso_st_ois_t val)3714 int32_t lsm6dso_aux_gy_self_test_set(const stmdev_ctx_t *ctx,
3715 lsm6dso_st_ois_t val)
3716 {
3717 lsm6dso_ctrl3_ois_t reg;
3718 int32_t ret;
3719
3720 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3721
3722 if (ret == 0)
3723 {
3724 reg.st_ois = (uint8_t)val;
3725 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3726 }
3727
3728 return ret;
3729 }
3730
3731 /**
3732 * @brief Selects gyroscope OIS chain self-test.[get]
3733 *
3734 * @param ctx read / write interface definitions
3735 * @param val Get the values of st_ois in reg CTRL3_OIS
3736 * @retval interface status (MANDATORY: return 0 -> no Error)
3737 *
3738 */
lsm6dso_aux_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dso_st_ois_t * val)3739 int32_t lsm6dso_aux_gy_self_test_get(const stmdev_ctx_t *ctx,
3740 lsm6dso_st_ois_t *val)
3741 {
3742 lsm6dso_ctrl3_ois_t reg;
3743 int32_t ret;
3744
3745 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3746
3747 switch (reg.st_ois)
3748 {
3749 case LSM6DSO_AUX_GY_DISABLE:
3750 *val = LSM6DSO_AUX_GY_DISABLE;
3751 break;
3752
3753 case LSM6DSO_AUX_GY_POS:
3754 *val = LSM6DSO_AUX_GY_POS;
3755 break;
3756
3757 case LSM6DSO_AUX_GY_NEG:
3758 *val = LSM6DSO_AUX_GY_NEG;
3759 break;
3760
3761 default:
3762 *val = LSM6DSO_AUX_GY_DISABLE;
3763 break;
3764 }
3765
3766 return ret;
3767 }
3768
3769 /**
3770 * @brief Selects accelerometer OIS channel bandwidth.[set]
3771 *
3772 * @param ctx read / write interface definitions
3773 * @param val change the values of
3774 * filter_xl_conf_ois in reg CTRL3_OIS
3775 * @retval interface status (MANDATORY: return 0 -> no Error)
3776 *
3777 */
lsm6dso_aux_xl_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dso_filter_xl_conf_ois_t val)3778 int32_t lsm6dso_aux_xl_bandwidth_set(const stmdev_ctx_t *ctx,
3779 lsm6dso_filter_xl_conf_ois_t val)
3780 {
3781 lsm6dso_ctrl3_ois_t reg;
3782 int32_t ret;
3783
3784 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3785
3786 if (ret == 0)
3787 {
3788 reg.filter_xl_conf_ois = (uint8_t)val;
3789 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3790 }
3791
3792 return ret;
3793 }
3794
3795 /**
3796 * @brief Selects accelerometer OIS channel bandwidth.[get]
3797 *
3798 * @param ctx read / write interface definitions
3799 * @param val Get the values of
3800 * filter_xl_conf_ois in reg CTRL3_OIS
3801 * @retval interface status (MANDATORY: return 0 -> no Error)
3802 *
3803 */
lsm6dso_aux_xl_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dso_filter_xl_conf_ois_t * val)3804 int32_t lsm6dso_aux_xl_bandwidth_get(const stmdev_ctx_t *ctx,
3805 lsm6dso_filter_xl_conf_ois_t *val)
3806 {
3807 lsm6dso_ctrl3_ois_t reg;
3808 int32_t ret;
3809
3810 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3811
3812 switch (reg.filter_xl_conf_ois)
3813 {
3814 case LSM6DSO_289Hz:
3815 *val = LSM6DSO_289Hz;
3816 break;
3817
3818 case LSM6DSO_258Hz:
3819 *val = LSM6DSO_258Hz;
3820 break;
3821
3822 case LSM6DSO_120Hz:
3823 *val = LSM6DSO_120Hz;
3824 break;
3825
3826 case LSM6DSO_65Hz2:
3827 *val = LSM6DSO_65Hz2;
3828 break;
3829
3830 case LSM6DSO_33Hz2:
3831 *val = LSM6DSO_33Hz2;
3832 break;
3833
3834 case LSM6DSO_16Hz6:
3835 *val = LSM6DSO_16Hz6;
3836 break;
3837
3838 case LSM6DSO_8Hz30:
3839 *val = LSM6DSO_8Hz30;
3840 break;
3841
3842 case LSM6DSO_4Hz15:
3843 *val = LSM6DSO_4Hz15;
3844 break;
3845
3846 default:
3847 *val = LSM6DSO_289Hz;
3848 break;
3849 }
3850
3851 return ret;
3852 }
3853
3854 /**
3855 * @brief Selects accelerometer OIS channel full-scale.[set]
3856 *
3857 * @param ctx read / write interface definitions
3858 * @param val change the values of fs_xl_ois in
3859 * reg CTRL3_OIS
3860 * @retval interface status (MANDATORY: return 0 -> no Error)
3861 *
3862 */
lsm6dso_aux_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dso_fs_xl_ois_t val)3863 int32_t lsm6dso_aux_xl_full_scale_set(const stmdev_ctx_t *ctx,
3864 lsm6dso_fs_xl_ois_t val)
3865 {
3866 lsm6dso_ctrl3_ois_t reg;
3867 int32_t ret;
3868
3869 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3870
3871 if (ret == 0)
3872 {
3873 reg.fs_xl_ois = (uint8_t)val;
3874 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3875 }
3876
3877 return ret;
3878 }
3879
3880 /**
3881 * @brief Selects accelerometer OIS channel full-scale.[get]
3882 *
3883 * @param ctx read / write interface definitions
3884 * @param val Get the values of fs_xl_ois in reg CTRL3_OIS
3885 * @retval interface status (MANDATORY: return 0 -> no Error)
3886 *
3887 */
lsm6dso_aux_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dso_fs_xl_ois_t * val)3888 int32_t lsm6dso_aux_xl_full_scale_get(const stmdev_ctx_t *ctx,
3889 lsm6dso_fs_xl_ois_t *val)
3890 {
3891 lsm6dso_ctrl3_ois_t reg;
3892 int32_t ret;
3893
3894 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3895
3896 switch (reg.fs_xl_ois)
3897 {
3898 case LSM6DSO_AUX_2g:
3899 *val = LSM6DSO_AUX_2g;
3900 break;
3901
3902 case LSM6DSO_AUX_16g:
3903 *val = LSM6DSO_AUX_16g;
3904 break;
3905
3906 case LSM6DSO_AUX_4g:
3907 *val = LSM6DSO_AUX_4g;
3908 break;
3909
3910 case LSM6DSO_AUX_8g:
3911 *val = LSM6DSO_AUX_8g;
3912 break;
3913
3914 default:
3915 *val = LSM6DSO_AUX_2g;
3916 break;
3917 }
3918
3919 return ret;
3920 }
3921
3922 /**
3923 * @}
3924 *
3925 */
3926
3927 /**
3928 * @defgroup LSM6DSO_ main_serial_interface
3929 * @brief This section groups all the functions concerning main
3930 * serial interface management (not auxiliary)
3931 * @{
3932 *
3933 */
3934
3935 /**
3936 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
3937 *
3938 * @param ctx read / write interface definitions
3939 * @param val change the values of sdo_pu_en in
3940 * reg PIN_CTRL
3941 * @retval interface status (MANDATORY: return 0 -> no Error)
3942 *
3943 */
lsm6dso_sdo_sa0_mode_set(const stmdev_ctx_t * ctx,lsm6dso_sdo_pu_en_t val)3944 int32_t lsm6dso_sdo_sa0_mode_set(const stmdev_ctx_t *ctx,
3945 lsm6dso_sdo_pu_en_t val)
3946 {
3947 lsm6dso_pin_ctrl_t reg;
3948 int32_t ret;
3949
3950 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1);
3951
3952 if (ret == 0)
3953 {
3954 reg.sdo_pu_en = (uint8_t)val;
3955 ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1);
3956 }
3957
3958 return ret;
3959 }
3960
3961 /**
3962 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
3963 *
3964 * @param ctx read / write interface definitions
3965 * @param val Get the values of sdo_pu_en in reg PIN_CTRL
3966 * @retval interface status (MANDATORY: return 0 -> no Error)
3967 *
3968 */
lsm6dso_sdo_sa0_mode_get(const stmdev_ctx_t * ctx,lsm6dso_sdo_pu_en_t * val)3969 int32_t lsm6dso_sdo_sa0_mode_get(const stmdev_ctx_t *ctx,
3970 lsm6dso_sdo_pu_en_t *val)
3971 {
3972 lsm6dso_pin_ctrl_t reg;
3973 int32_t ret;
3974
3975 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1);
3976
3977 switch (reg.sdo_pu_en)
3978 {
3979 case LSM6DSO_PULL_UP_DISC:
3980 *val = LSM6DSO_PULL_UP_DISC;
3981 break;
3982
3983 case LSM6DSO_PULL_UP_CONNECT:
3984 *val = LSM6DSO_PULL_UP_CONNECT;
3985 break;
3986
3987 default:
3988 *val = LSM6DSO_PULL_UP_DISC;
3989 break;
3990 }
3991
3992 return ret;
3993 }
3994
3995 /**
3996 * @brief SPI Serial Interface Mode selection.[set]
3997 *
3998 * @param ctx read / write interface definitions
3999 * @param val change the values of sim in reg CTRL3_C
4000 * @retval interface status (MANDATORY: return 0 -> no Error)
4001 *
4002 */
lsm6dso_spi_mode_set(const stmdev_ctx_t * ctx,lsm6dso_sim_t val)4003 int32_t lsm6dso_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dso_sim_t val)
4004 {
4005 lsm6dso_ctrl3_c_t reg;
4006 int32_t ret;
4007
4008 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
4009
4010 if (ret == 0)
4011 {
4012 reg.sim = (uint8_t)val;
4013 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
4014 }
4015
4016 return ret;
4017 }
4018
4019 /**
4020 * @brief SPI Serial Interface Mode selection.[get]
4021 *
4022 * @param ctx read / write interface definitions
4023 * @param val Get the values of sim in reg CTRL3_C
4024 * @retval interface status (MANDATORY: return 0 -> no Error)
4025 *
4026 */
lsm6dso_spi_mode_get(const stmdev_ctx_t * ctx,lsm6dso_sim_t * val)4027 int32_t lsm6dso_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dso_sim_t *val)
4028 {
4029 lsm6dso_ctrl3_c_t reg;
4030 int32_t ret;
4031
4032 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
4033
4034 switch (reg.sim)
4035 {
4036 case LSM6DSO_SPI_4_WIRE:
4037 *val = LSM6DSO_SPI_4_WIRE;
4038 break;
4039
4040 case LSM6DSO_SPI_3_WIRE:
4041 *val = LSM6DSO_SPI_3_WIRE;
4042 break;
4043
4044 default:
4045 *val = LSM6DSO_SPI_4_WIRE;
4046 break;
4047 }
4048
4049 return ret;
4050 }
4051
4052 /**
4053 * @brief Disable / Enable I2C interface.[set]
4054 *
4055 * @param ctx read / write interface definitions
4056 * @param val change the values of i2c_disable in
4057 * reg CTRL4_C
4058 * @retval interface status (MANDATORY: return 0 -> no Error)
4059 *
4060 */
lsm6dso_i2c_interface_set(const stmdev_ctx_t * ctx,lsm6dso_i2c_disable_t val)4061 int32_t lsm6dso_i2c_interface_set(const stmdev_ctx_t *ctx,
4062 lsm6dso_i2c_disable_t val)
4063 {
4064 lsm6dso_ctrl4_c_t reg;
4065 int32_t ret;
4066
4067 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
4068
4069 if (ret == 0)
4070 {
4071 reg.i2c_disable = (uint8_t)val;
4072 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
4073 }
4074
4075 return ret;
4076 }
4077
4078 /**
4079 * @brief Disable / Enable I2C interface.[get]
4080 *
4081 * @param ctx read / write interface definitions
4082 * @param val Get the values of i2c_disable in
4083 * reg CTRL4_C
4084 * @retval interface status (MANDATORY: return 0 -> no Error)
4085 *
4086 */
lsm6dso_i2c_interface_get(const stmdev_ctx_t * ctx,lsm6dso_i2c_disable_t * val)4087 int32_t lsm6dso_i2c_interface_get(const stmdev_ctx_t *ctx,
4088 lsm6dso_i2c_disable_t *val)
4089 {
4090 lsm6dso_ctrl4_c_t reg;
4091 int32_t ret;
4092
4093 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
4094
4095 switch (reg.i2c_disable)
4096 {
4097 case LSM6DSO_I2C_ENABLE:
4098 *val = LSM6DSO_I2C_ENABLE;
4099 break;
4100
4101 case LSM6DSO_I2C_DISABLE:
4102 *val = LSM6DSO_I2C_DISABLE;
4103 break;
4104
4105 default:
4106 *val = LSM6DSO_I2C_ENABLE;
4107 break;
4108 }
4109
4110 return ret;
4111 }
4112
4113 /**
4114 * @brief I3C Enable/Disable communication protocol[.set]
4115 *
4116 * @param ctx read / write interface definitions
4117 * @param val change the values of i3c_disable
4118 * in reg CTRL9_XL
4119 * @retval interface status (MANDATORY: return 0 -> no Error)
4120 *
4121 */
lsm6dso_i3c_disable_set(const stmdev_ctx_t * ctx,lsm6dso_i3c_disable_t val)4122 int32_t lsm6dso_i3c_disable_set(const stmdev_ctx_t *ctx,
4123 lsm6dso_i3c_disable_t val)
4124 {
4125 lsm6dso_i3c_bus_avb_t i3c_bus_avb;
4126 lsm6dso_ctrl9_xl_t ctrl9_xl;
4127 int32_t ret;
4128
4129 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
4130 ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
4131 ret += lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
4132 if (ret != 0) { return ret; }
4133
4134 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1);
4135 i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
4136 ret += lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1);
4137
4138 return ret;
4139 }
4140
4141 /**
4142 * @brief I3C Enable/Disable communication protocol.[get]
4143 *
4144 * @param ctx read / write interface definitions
4145 * @param val Get the values of i3c_disable in
4146 * reg CTRL9_XL
4147 * @retval interface status (MANDATORY: return 0 -> no Error)
4148 *
4149 */
lsm6dso_i3c_disable_get(const stmdev_ctx_t * ctx,lsm6dso_i3c_disable_t * val)4150 int32_t lsm6dso_i3c_disable_get(const stmdev_ctx_t *ctx,
4151 lsm6dso_i3c_disable_t *val)
4152 {
4153 lsm6dso_ctrl9_xl_t ctrl9_xl;
4154 lsm6dso_i3c_bus_avb_t i3c_bus_avb;
4155 int32_t ret;
4156
4157 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
4158 ret += lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1);
4159 if (ret != 0) { return ret; }
4160
4161 switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel)
4162 {
4163 case LSM6DSO_I3C_DISABLE:
4164 *val = LSM6DSO_I3C_DISABLE;
4165 break;
4166
4167 case LSM6DSO_I3C_ENABLE_T_50us:
4168 *val = LSM6DSO_I3C_ENABLE_T_50us;
4169 break;
4170
4171 case LSM6DSO_I3C_ENABLE_T_2us:
4172 *val = LSM6DSO_I3C_ENABLE_T_2us;
4173 break;
4174
4175 case LSM6DSO_I3C_ENABLE_T_1ms:
4176 *val = LSM6DSO_I3C_ENABLE_T_1ms;
4177 break;
4178
4179 case LSM6DSO_I3C_ENABLE_T_25ms:
4180 *val = LSM6DSO_I3C_ENABLE_T_25ms;
4181 break;
4182
4183 default:
4184 *val = LSM6DSO_I3C_DISABLE;
4185 break;
4186 }
4187
4188 return ret;
4189 }
4190
4191 /**
4192 * @}
4193 *
4194 */
4195
4196 /**
4197 * @defgroup LSM6DSO_interrupt_pins
4198 * @brief This section groups all the functions that manage interrupt pins
4199 * @{
4200 *
4201 */
4202
4203 /**
4204 * @brief Connect/Disconnect INT1 internal pull-down.[set]
4205 *
4206 * @param ctx read / write interface definitions
4207 * @param val change the values of pd_dis_int1 in reg I3C_BUS_AVB
4208 * @retval interface status (MANDATORY: return 0 -> no Error)
4209 *
4210 */
lsm6dso_int1_mode_set(const stmdev_ctx_t * ctx,lsm6dso_int1_pd_en_t val)4211 int32_t lsm6dso_int1_mode_set(const stmdev_ctx_t *ctx,
4212 lsm6dso_int1_pd_en_t val)
4213 {
4214 lsm6dso_i3c_bus_avb_t reg;
4215 int32_t ret;
4216
4217 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)®, 1);
4218
4219 if (ret == 0)
4220 {
4221 reg.pd_dis_int1 = (uint8_t)val;
4222 ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)®, 1);
4223 }
4224
4225 return ret;
4226 }
4227
4228 /**
4229 * @brief Connect/Disconnect INT1 internal pull-down.[get]
4230 *
4231 * @param ctx read / write interface definitions
4232 * @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB
4233 * @retval interface status (MANDATORY: return 0 -> no Error)
4234 *
4235 */
lsm6dso_int1_mode_get(const stmdev_ctx_t * ctx,lsm6dso_int1_pd_en_t * val)4236 int32_t lsm6dso_int1_mode_get(const stmdev_ctx_t *ctx,
4237 lsm6dso_int1_pd_en_t *val)
4238 {
4239 lsm6dso_i3c_bus_avb_t reg;
4240 int32_t ret;
4241
4242 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)®, 1);
4243
4244 switch (reg.pd_dis_int1)
4245 {
4246 case LSM6DSO_PULL_DOWN_DISC:
4247 *val = LSM6DSO_PULL_DOWN_DISC;
4248 break;
4249
4250 case LSM6DSO_PULL_DOWN_CONNECT:
4251 *val = LSM6DSO_PULL_DOWN_CONNECT;
4252 break;
4253
4254 default:
4255 *val = LSM6DSO_PULL_DOWN_DISC;
4256 break;
4257 }
4258
4259 return ret;
4260 }
4261
4262 /**
4263 * @brief Push-pull/open drain selection on interrupt pads.[set]
4264 *
4265 * @param ctx read / write interface definitions
4266 * @param val change the values of pp_od in reg CTRL3_C
4267 * @retval interface status (MANDATORY: return 0 -> no Error)
4268 *
4269 */
lsm6dso_pin_mode_set(const stmdev_ctx_t * ctx,lsm6dso_pp_od_t val)4270 int32_t lsm6dso_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dso_pp_od_t val)
4271 {
4272 lsm6dso_ctrl3_c_t reg;
4273 int32_t ret;
4274
4275 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
4276
4277 if (ret == 0)
4278 {
4279 reg.pp_od = (uint8_t)val;
4280 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
4281 }
4282
4283 return ret;
4284 }
4285
4286 /**
4287 * @brief Push-pull/open drain selection on interrupt pads.[get]
4288 *
4289 * @param ctx read / write interface definitions
4290 * @param val Get the values of pp_od in reg CTRL3_C
4291 * @retval interface status (MANDATORY: return 0 -> no Error)
4292 *
4293 */
lsm6dso_pin_mode_get(const stmdev_ctx_t * ctx,lsm6dso_pp_od_t * val)4294 int32_t lsm6dso_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dso_pp_od_t *val)
4295 {
4296 lsm6dso_ctrl3_c_t reg;
4297 int32_t ret;
4298
4299 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
4300
4301 switch (reg.pp_od)
4302 {
4303 case LSM6DSO_PUSH_PULL:
4304 *val = LSM6DSO_PUSH_PULL;
4305 break;
4306
4307 case LSM6DSO_OPEN_DRAIN:
4308 *val = LSM6DSO_OPEN_DRAIN;
4309 break;
4310
4311 default:
4312 *val = LSM6DSO_PUSH_PULL;
4313 break;
4314 }
4315
4316 return ret;
4317 }
4318
4319 /**
4320 * @brief Interrupt active-high/low.[set]
4321 *
4322 * @param ctx read / write interface definitions
4323 * @param val change the values of h_lactive in reg CTRL3_C
4324 * @retval interface status (MANDATORY: return 0 -> no Error)
4325 *
4326 */
lsm6dso_pin_polarity_set(const stmdev_ctx_t * ctx,lsm6dso_h_lactive_t val)4327 int32_t lsm6dso_pin_polarity_set(const stmdev_ctx_t *ctx,
4328 lsm6dso_h_lactive_t val)
4329 {
4330 lsm6dso_ctrl3_c_t reg;
4331 int32_t ret;
4332
4333 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
4334
4335 if (ret == 0)
4336 {
4337 reg.h_lactive = (uint8_t)val;
4338 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
4339 }
4340
4341 return ret;
4342 }
4343
4344 /**
4345 * @brief Interrupt active-high/low.[get]
4346 *
4347 * @param ctx read / write interface definitions
4348 * @param val Get the values of h_lactive in reg CTRL3_C
4349 * @retval interface status (MANDATORY: return 0 -> no Error)
4350 *
4351 */
lsm6dso_pin_polarity_get(const stmdev_ctx_t * ctx,lsm6dso_h_lactive_t * val)4352 int32_t lsm6dso_pin_polarity_get(const stmdev_ctx_t *ctx,
4353 lsm6dso_h_lactive_t *val)
4354 {
4355 lsm6dso_ctrl3_c_t reg;
4356 int32_t ret;
4357
4358 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
4359
4360 switch (reg.h_lactive)
4361 {
4362 case LSM6DSO_ACTIVE_HIGH:
4363 *val = LSM6DSO_ACTIVE_HIGH;
4364 break;
4365
4366 case LSM6DSO_ACTIVE_LOW:
4367 *val = LSM6DSO_ACTIVE_LOW;
4368 break;
4369
4370 default:
4371 *val = LSM6DSO_ACTIVE_HIGH;
4372 break;
4373 }
4374
4375 return ret;
4376 }
4377
4378 /**
4379 * @brief All interrupt signals become available on INT1 pin.[set]
4380 *
4381 * @param ctx read / write interface definitions
4382 * @param val change the values of int2_on_int1 in reg CTRL4_C
4383 * @retval interface status (MANDATORY: return 0 -> no Error)
4384 *
4385 */
lsm6dso_all_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)4386 int32_t lsm6dso_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
4387 {
4388 lsm6dso_ctrl4_c_t reg;
4389 int32_t ret;
4390
4391 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
4392
4393 if (ret == 0)
4394 {
4395 reg.int2_on_int1 = val;
4396 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
4397 }
4398
4399 return ret;
4400 }
4401
4402 /**
4403 * @brief All interrupt signals become available on INT1 pin.[get]
4404 *
4405 * @param ctx read / write interface definitions
4406 * @param val Get the values of int2_on_int1 in reg CTRL4_C
4407 * @retval interface status (MANDATORY: return 0 -> no Error)
4408 *
4409 */
lsm6dso_all_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)4410 int32_t lsm6dso_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
4411 {
4412 lsm6dso_ctrl4_c_t reg;
4413 int32_t ret;
4414
4415 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
4416 *val = reg.int2_on_int1;
4417
4418 return ret;
4419 }
4420
4421 /**
4422 * @brief Interrupt notification mode.[set]
4423 *
4424 * @param ctx read / write interface definitions
4425 * @param val change the values of lir in reg TAP_CFG0
4426 * @retval interface status (MANDATORY: return 0 -> no Error)
4427 *
4428 */
lsm6dso_int_notification_set(const stmdev_ctx_t * ctx,lsm6dso_lir_t val)4429 int32_t lsm6dso_int_notification_set(const stmdev_ctx_t *ctx,
4430 lsm6dso_lir_t val)
4431 {
4432 lsm6dso_tap_cfg0_t tap_cfg0;
4433 lsm6dso_page_rw_t page_rw;
4434 int32_t ret;
4435
4436 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
4437 tap_cfg0.lir = (uint8_t)val & 0x01U;
4438 tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
4439 ret += lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
4440 if (ret != 0) { return ret; }
4441
4442 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
4443 if (ret != 0) { return ret; }
4444
4445 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
4446 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
4447 ret += lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
4448
4449 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
4450
4451 return ret;
4452 }
4453
4454 /**
4455 * @brief Interrupt notification mode.[get]
4456 *
4457 * @param ctx read / write interface definitions
4458 * @param val Get the values of lir in reg TAP_CFG0
4459 * @retval interface status (MANDATORY: return 0 -> no Error)
4460 *
4461 */
lsm6dso_int_notification_get(const stmdev_ctx_t * ctx,lsm6dso_lir_t * val)4462 int32_t lsm6dso_int_notification_get(const stmdev_ctx_t *ctx,
4463 lsm6dso_lir_t *val)
4464 {
4465 lsm6dso_tap_cfg0_t tap_cfg0;
4466 lsm6dso_page_rw_t page_rw;
4467 int32_t ret;
4468
4469 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
4470 if (ret != 0) { return ret; }
4471
4472 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
4473 ret += lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
4474 if (ret != 0) { goto exit; }
4475
4476 switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir)
4477 {
4478 case LSM6DSO_ALL_INT_PULSED:
4479 *val = LSM6DSO_ALL_INT_PULSED;
4480 break;
4481
4482 case LSM6DSO_BASE_LATCHED_EMB_PULSED:
4483 *val = LSM6DSO_BASE_LATCHED_EMB_PULSED;
4484 break;
4485
4486 case LSM6DSO_BASE_PULSED_EMB_LATCHED:
4487 *val = LSM6DSO_BASE_PULSED_EMB_LATCHED;
4488 break;
4489
4490 case LSM6DSO_ALL_INT_LATCHED:
4491 *val = LSM6DSO_ALL_INT_LATCHED;
4492 break;
4493
4494 default:
4495 *val = LSM6DSO_ALL_INT_PULSED;
4496 break;
4497 }
4498
4499 ret += lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
4500
4501 exit:
4502 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
4503
4504 return ret;
4505 }
4506
4507 /**
4508 * @}
4509 *
4510 */
4511
4512 /**
4513 * @defgroup LSM6DSO_Wake_Up_event
4514 * @brief This section groups all the functions that manage the Wake Up
4515 * event generation.
4516 * @{
4517 *
4518 */
4519
4520 /**
4521 * @brief Weight of 1 LSB of wakeup threshold.[set]
4522 * 0: 1 LSB =FS_XL / 64
4523 * 1: 1 LSB = FS_XL / 256
4524 *
4525 * @param ctx read / write interface definitions
4526 * @param val change the values of wake_ths_w in
4527 * reg WAKE_UP_DUR
4528 * @retval interface status (MANDATORY: return 0 -> no Error)
4529 *
4530 */
lsm6dso_wkup_ths_weight_set(const stmdev_ctx_t * ctx,lsm6dso_wake_ths_w_t val)4531 int32_t lsm6dso_wkup_ths_weight_set(const stmdev_ctx_t *ctx,
4532 lsm6dso_wake_ths_w_t val)
4533 {
4534 lsm6dso_wake_up_dur_t reg;
4535 int32_t ret;
4536
4537 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
4538
4539 if (ret == 0)
4540 {
4541 reg.wake_ths_w = (uint8_t)val;
4542 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
4543 }
4544
4545 return ret;
4546 }
4547
4548 /**
4549 * @brief Weight of 1 LSB of wakeup threshold.[get]
4550 * 0: 1 LSB =FS_XL / 64
4551 * 1: 1 LSB = FS_XL / 256
4552 *
4553 * @param ctx read / write interface definitions
4554 * @param val Get the values of wake_ths_w in
4555 * reg WAKE_UP_DUR
4556 * @retval interface status (MANDATORY: return 0 -> no Error)
4557 *
4558 */
lsm6dso_wkup_ths_weight_get(const stmdev_ctx_t * ctx,lsm6dso_wake_ths_w_t * val)4559 int32_t lsm6dso_wkup_ths_weight_get(const stmdev_ctx_t *ctx,
4560 lsm6dso_wake_ths_w_t *val)
4561 {
4562 lsm6dso_wake_up_dur_t reg;
4563 int32_t ret;
4564
4565 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
4566
4567 switch (reg.wake_ths_w)
4568 {
4569 case LSM6DSO_LSb_FS_DIV_64:
4570 *val = LSM6DSO_LSb_FS_DIV_64;
4571 break;
4572
4573 case LSM6DSO_LSb_FS_DIV_256:
4574 *val = LSM6DSO_LSb_FS_DIV_256;
4575 break;
4576
4577 default:
4578 *val = LSM6DSO_LSb_FS_DIV_64;
4579 break;
4580 }
4581
4582 return ret;
4583 }
4584
4585 /**
4586 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
4587 * WAKE_UP_DUR.[set]
4588 *
4589 * @param ctx read / write interface definitions
4590 * @param val change the values of wk_ths in reg WAKE_UP_THS
4591 * @retval interface status (MANDATORY: return 0 -> no Error)
4592 *
4593 */
lsm6dso_wkup_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)4594 int32_t lsm6dso_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
4595 {
4596 lsm6dso_wake_up_ths_t reg;
4597 int32_t ret;
4598
4599 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
4600
4601 if (ret == 0)
4602 {
4603 reg.wk_ths = val;
4604 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
4605 }
4606
4607 return ret;
4608 }
4609
4610 /**
4611 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
4612 * WAKE_UP_DUR.[get]
4613 *
4614 * @param ctx read / write interface definitions
4615 * @param val Get the values of wk_ths in reg WAKE_UP_THS
4616 * @retval interface status (MANDATORY: return 0 -> no Error)
4617 *
4618 */
lsm6dso_wkup_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)4619 int32_t lsm6dso_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
4620 {
4621 lsm6dso_wake_up_ths_t reg;
4622 int32_t ret;
4623
4624 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
4625 *val = reg.wk_ths;
4626
4627 return ret;
4628 }
4629
4630 /**
4631 * @brief Wake up duration event.[set]
4632 * 1LSb = 1 / ODR
4633 *
4634 * @param ctx read / write interface definitions
4635 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
4636 * @retval interface status (MANDATORY: return 0 -> no Error)
4637 *
4638 */
lsm6dso_xl_usr_offset_on_wkup_set(const stmdev_ctx_t * ctx,uint8_t val)4639 int32_t lsm6dso_xl_usr_offset_on_wkup_set(const stmdev_ctx_t *ctx,
4640 uint8_t val)
4641 {
4642 lsm6dso_wake_up_ths_t reg;
4643 int32_t ret;
4644
4645 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
4646
4647 if (ret == 0)
4648 {
4649 reg.usr_off_on_wu = val;
4650 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
4651 }
4652
4653 return ret;
4654 }
4655
4656 /**
4657 * @brief Wake up duration event.[get]
4658 * 1LSb = 1 / ODR
4659 *
4660 * @param ctx read / write interface definitions
4661 * @param val Get the values of usr_off_on_wu in reg WAKE_UP_THS
4662 * @retval interface status (MANDATORY: return 0 -> no Error)
4663 *
4664 */
lsm6dso_xl_usr_offset_on_wkup_get(const stmdev_ctx_t * ctx,uint8_t * val)4665 int32_t lsm6dso_xl_usr_offset_on_wkup_get(const stmdev_ctx_t *ctx,
4666 uint8_t *val)
4667 {
4668 lsm6dso_wake_up_ths_t reg;
4669 int32_t ret;
4670
4671 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
4672 *val = reg.usr_off_on_wu;
4673
4674 return ret;
4675 }
4676
4677 /**
4678 * @brief Wake up duration event.[set]
4679 * 1LSb = 1 / ODR
4680 *
4681 * @param ctx read / write interface definitions
4682 * @param val change the values of wake_dur in reg WAKE_UP_DUR
4683 * @retval interface status (MANDATORY: return 0 -> no Error)
4684 *
4685 */
lsm6dso_wkup_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4686 int32_t lsm6dso_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4687 {
4688 lsm6dso_wake_up_dur_t reg;
4689 int32_t ret;
4690
4691 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
4692
4693 if (ret == 0)
4694 {
4695 reg.wake_dur = val;
4696 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
4697 }
4698
4699 return ret;
4700 }
4701
4702 /**
4703 * @brief Wake up duration event.[get]
4704 * 1LSb = 1 / ODR
4705 *
4706 * @param ctx read / write interface definitions
4707 * @param val Get the values of wake_dur in reg WAKE_UP_DUR
4708 * @retval interface status (MANDATORY: return 0 -> no Error)
4709 *
4710 */
lsm6dso_wkup_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4711 int32_t lsm6dso_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4712 {
4713 lsm6dso_wake_up_dur_t reg;
4714 int32_t ret;
4715
4716 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
4717 *val = reg.wake_dur;
4718
4719 return ret;
4720 }
4721
4722 /**
4723 * @}
4724 *
4725 */
4726
4727 /**
4728 * @defgroup LSM6DSO_ Activity/Inactivity_detection
4729 * @brief This section groups all the functions concerning
4730 * activity/inactivity detection.
4731 * @{
4732 *
4733 */
4734
4735 /**
4736 * @brief Enables gyroscope Sleep mode.[set]
4737 *
4738 * @param ctx read / write interface definitions
4739 * @param val change the values of sleep_g in reg CTRL4_C
4740 * @retval interface status (MANDATORY: return 0 -> no Error)
4741 *
4742 */
lsm6dso_gy_sleep_mode_set(const stmdev_ctx_t * ctx,uint8_t val)4743 int32_t lsm6dso_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
4744 {
4745 lsm6dso_ctrl4_c_t reg;
4746 int32_t ret;
4747
4748 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
4749
4750 if (ret == 0)
4751 {
4752 reg.sleep_g = val;
4753 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
4754 }
4755
4756 return ret;
4757 }
4758
4759 /**
4760 * @brief Enables gyroscope Sleep mode.[get]
4761 *
4762 * @param ctx read / write interface definitions
4763 * @param val Get the values of sleep_g in reg CTRL4_C
4764 * @retval interface status (MANDATORY: return 0 -> no Error)
4765 *
4766 */
lsm6dso_gy_sleep_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)4767 int32_t lsm6dso_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
4768 {
4769 lsm6dso_ctrl4_c_t reg;
4770 int32_t ret;
4771
4772 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
4773 *val = reg.sleep_g;
4774
4775 return ret;
4776 }
4777
4778 /**
4779 * @brief Drives the sleep status instead of
4780 * sleep change on INT pins
4781 * (only if INT1_SLEEP_CHANGE or
4782 * INT2_SLEEP_CHANGE bits are enabled).[set]
4783 *
4784 * @param ctx read / write interface definitions
4785 * @param val change the values of sleep_status_on_int in reg TAP_CFG0
4786 * @retval interface status (MANDATORY: return 0 -> no Error)
4787 *
4788 */
lsm6dso_act_pin_notification_set(const stmdev_ctx_t * ctx,lsm6dso_sleep_status_on_int_t val)4789 int32_t lsm6dso_act_pin_notification_set(const stmdev_ctx_t *ctx,
4790 lsm6dso_sleep_status_on_int_t val)
4791 {
4792 lsm6dso_tap_cfg0_t reg;
4793 int32_t ret;
4794
4795 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
4796
4797 if (ret == 0)
4798 {
4799 reg.sleep_status_on_int = (uint8_t)val;
4800 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
4801 }
4802
4803 return ret;
4804 }
4805
4806 /**
4807 * @brief Drives the sleep status instead of
4808 * sleep change on INT pins (only if
4809 * INT1_SLEEP_CHANGE or
4810 * INT2_SLEEP_CHANGE bits are enabled).[get]
4811 *
4812 * @param ctx read / write interface definitions
4813 * @param val Get the values of sleep_status_on_int in reg TAP_CFG0
4814 * @retval interface status (MANDATORY: return 0 -> no Error)
4815 *
4816 */
lsm6dso_act_pin_notification_get(const stmdev_ctx_t * ctx,lsm6dso_sleep_status_on_int_t * val)4817 int32_t lsm6dso_act_pin_notification_get(const stmdev_ctx_t *ctx,
4818 lsm6dso_sleep_status_on_int_t *val)
4819 {
4820 lsm6dso_tap_cfg0_t reg;
4821 int32_t ret;
4822
4823 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
4824
4825 switch (reg.sleep_status_on_int)
4826 {
4827 case LSM6DSO_DRIVE_SLEEP_CHG_EVENT:
4828 *val = LSM6DSO_DRIVE_SLEEP_CHG_EVENT;
4829 break;
4830
4831 case LSM6DSO_DRIVE_SLEEP_STATUS:
4832 *val = LSM6DSO_DRIVE_SLEEP_STATUS;
4833 break;
4834
4835 default:
4836 *val = LSM6DSO_DRIVE_SLEEP_CHG_EVENT;
4837 break;
4838 }
4839
4840 return ret;
4841 }
4842
4843 /**
4844 * @brief Enable inactivity function.[set]
4845 *
4846 * @param ctx read / write interface definitions
4847 * @param val change the values of inact_en in reg TAP_CFG2
4848 * @retval interface status (MANDATORY: return 0 -> no Error)
4849 *
4850 */
lsm6dso_act_mode_set(const stmdev_ctx_t * ctx,lsm6dso_inact_en_t val)4851 int32_t lsm6dso_act_mode_set(const stmdev_ctx_t *ctx,
4852 lsm6dso_inact_en_t val)
4853 {
4854 lsm6dso_tap_cfg2_t reg;
4855 int32_t ret;
4856
4857 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1);
4858
4859 if (ret == 0)
4860 {
4861 reg.inact_en = (uint8_t)val;
4862 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1);
4863 }
4864
4865 return ret;
4866 }
4867
4868 /**
4869 * @brief Enable inactivity function.[get]
4870 *
4871 * @param ctx read / write interface definitions
4872 * @param val Get the values of inact_en in reg TAP_CFG2
4873 * @retval interface status (MANDATORY: return 0 -> no Error)
4874 *
4875 */
lsm6dso_act_mode_get(const stmdev_ctx_t * ctx,lsm6dso_inact_en_t * val)4876 int32_t lsm6dso_act_mode_get(const stmdev_ctx_t *ctx,
4877 lsm6dso_inact_en_t *val)
4878 {
4879 lsm6dso_tap_cfg2_t reg;
4880 int32_t ret;
4881
4882 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1);
4883
4884 switch (reg.inact_en)
4885 {
4886 case LSM6DSO_XL_AND_GY_NOT_AFFECTED:
4887 *val = LSM6DSO_XL_AND_GY_NOT_AFFECTED;
4888 break;
4889
4890 case LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED:
4891 *val = LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED;
4892 break;
4893
4894 case LSM6DSO_XL_12Hz5_GY_SLEEP:
4895 *val = LSM6DSO_XL_12Hz5_GY_SLEEP;
4896 break;
4897
4898 case LSM6DSO_XL_12Hz5_GY_PD:
4899 *val = LSM6DSO_XL_12Hz5_GY_PD;
4900 break;
4901
4902 default:
4903 *val = LSM6DSO_XL_AND_GY_NOT_AFFECTED;
4904 break;
4905 }
4906
4907 return ret;
4908 }
4909
4910 /**
4911 * @brief Duration to go in sleep mode.[set]
4912 * 1 LSb = 512 / ODR
4913 *
4914 * @param ctx read / write interface definitions
4915 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
4916 * @retval interface status (MANDATORY: return 0 -> no Error)
4917 *
4918 */
lsm6dso_act_sleep_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4919 int32_t lsm6dso_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4920 {
4921 lsm6dso_wake_up_dur_t reg;
4922 int32_t ret;
4923
4924 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
4925
4926 if (ret == 0)
4927 {
4928 reg.sleep_dur = val;
4929 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
4930 }
4931
4932 return ret;
4933 }
4934
4935 /**
4936 * @brief Duration to go in sleep mode.[get]
4937 * 1 LSb = 512 / ODR
4938 *
4939 * @param ctx read / write interface definitions
4940 * @param val Get the values of sleep_dur in reg WAKE_UP_DUR
4941 * @retval interface status (MANDATORY: return 0 -> no Error)
4942 *
4943 */
lsm6dso_act_sleep_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4944 int32_t lsm6dso_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4945 {
4946 lsm6dso_wake_up_dur_t reg;
4947 int32_t ret;
4948
4949 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
4950 *val = reg.sleep_dur;
4951
4952 return ret;
4953 }
4954
4955 /**
4956 * @}
4957 *
4958 */
4959
4960 /**
4961 * @defgroup LSM6DSO_tap_generator
4962 * @brief This section groups all the functions that manage the
4963 * tap and double tap event generation.
4964 * @{
4965 *
4966 */
4967
4968 /**
4969 * @brief Enable Z direction in tap recognition.[set]
4970 *
4971 * @param ctx read / write interface definitions
4972 * @param val change the values of tap_z_en in reg TAP_CFG0
4973 * @retval interface status (MANDATORY: return 0 -> no Error)
4974 *
4975 */
lsm6dso_tap_detection_on_z_set(const stmdev_ctx_t * ctx,uint8_t val)4976 int32_t lsm6dso_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val)
4977 {
4978 lsm6dso_tap_cfg0_t reg;
4979 int32_t ret;
4980
4981 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
4982
4983 if (ret == 0)
4984 {
4985 reg.tap_z_en = val;
4986 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
4987 }
4988
4989 return ret;
4990 }
4991
4992 /**
4993 * @brief Enable Z direction in tap recognition.[get]
4994 *
4995 * @param ctx read / write interface definitions
4996 * @param val Get the values of tap_z_en in reg TAP_CFG0
4997 * @retval interface status (MANDATORY: return 0 -> no Error)
4998 *
4999 */
lsm6dso_tap_detection_on_z_get(const stmdev_ctx_t * ctx,uint8_t * val)5000 int32_t lsm6dso_tap_detection_on_z_get(const stmdev_ctx_t *ctx,
5001 uint8_t *val)
5002 {
5003 lsm6dso_tap_cfg0_t reg;
5004 int32_t ret;
5005
5006 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
5007 *val = reg.tap_z_en;
5008
5009 return ret;
5010 }
5011
5012 /**
5013 * @brief Enable Y direction in tap recognition.[set]
5014 *
5015 * @param ctx read / write interface definitions
5016 * @param val change the values of tap_y_en in reg TAP_CFG0
5017 * @retval interface status (MANDATORY: return 0 -> no Error)
5018 *
5019 */
lsm6dso_tap_detection_on_y_set(const stmdev_ctx_t * ctx,uint8_t val)5020 int32_t lsm6dso_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val)
5021 {
5022 lsm6dso_tap_cfg0_t reg;
5023 int32_t ret;
5024
5025 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
5026
5027 if (ret == 0)
5028 {
5029 reg.tap_y_en = val;
5030 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
5031 }
5032
5033 return ret;
5034 }
5035
5036 /**
5037 * @brief Enable Y direction in tap recognition.[get]
5038 *
5039 * @param ctx read / write interface definitions
5040 * @param val Get the values of tap_y_en in reg TAP_CFG0
5041 * @retval interface status (MANDATORY: return 0 -> no Error)
5042 *
5043 */
lsm6dso_tap_detection_on_y_get(const stmdev_ctx_t * ctx,uint8_t * val)5044 int32_t lsm6dso_tap_detection_on_y_get(const stmdev_ctx_t *ctx,
5045 uint8_t *val)
5046 {
5047 lsm6dso_tap_cfg0_t reg;
5048 int32_t ret;
5049
5050 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
5051 *val = reg.tap_y_en;
5052
5053 return ret;
5054 }
5055
5056 /**
5057 * @brief Enable X direction in tap recognition.[set]
5058 *
5059 * @param ctx read / write interface definitions
5060 * @param val change the values of tap_x_en in reg TAP_CFG0
5061 * @retval interface status (MANDATORY: return 0 -> no Error)
5062 *
5063 */
lsm6dso_tap_detection_on_x_set(const stmdev_ctx_t * ctx,uint8_t val)5064 int32_t lsm6dso_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val)
5065 {
5066 lsm6dso_tap_cfg0_t reg;
5067 int32_t ret;
5068
5069 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
5070
5071 if (ret == 0)
5072 {
5073 reg.tap_x_en = val;
5074 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
5075 }
5076
5077 return ret;
5078 }
5079
5080 /**
5081 * @brief Enable X direction in tap recognition.[get]
5082 *
5083 * @param ctx read / write interface definitions
5084 * @param val Get the values of tap_x_en in reg TAP_CFG0
5085 * @retval interface status (MANDATORY: return 0 -> no Error)
5086 *
5087 */
lsm6dso_tap_detection_on_x_get(const stmdev_ctx_t * ctx,uint8_t * val)5088 int32_t lsm6dso_tap_detection_on_x_get(const stmdev_ctx_t *ctx,
5089 uint8_t *val)
5090 {
5091 lsm6dso_tap_cfg0_t reg;
5092 int32_t ret;
5093
5094 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
5095 *val = reg.tap_x_en;
5096
5097 return ret;
5098 }
5099
5100 /**
5101 * @brief X-axis tap recognition threshold.[set]
5102 *
5103 * @param ctx read / write interface definitions
5104 * @param val change the values of tap_ths_x in reg TAP_CFG1
5105 * @retval interface status (MANDATORY: return 0 -> no Error)
5106 *
5107 */
lsm6dso_tap_threshold_x_set(const stmdev_ctx_t * ctx,uint8_t val)5108 int32_t lsm6dso_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val)
5109 {
5110 lsm6dso_tap_cfg1_t reg;
5111 int32_t ret;
5112
5113 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1);
5114
5115 if (ret == 0)
5116 {
5117 reg.tap_ths_x = val;
5118 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1);
5119 }
5120
5121 return ret;
5122 }
5123
5124 /**
5125 * @brief X-axis tap recognition threshold.[get]
5126 *
5127 * @param ctx read / write interface definitions
5128 * @param val Get the values of tap_ths_x in reg TAP_CFG1
5129 * @retval interface status (MANDATORY: return 0 -> no Error)
5130 *
5131 */
lsm6dso_tap_threshold_x_get(const stmdev_ctx_t * ctx,uint8_t * val)5132 int32_t lsm6dso_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val)
5133 {
5134 lsm6dso_tap_cfg1_t reg;
5135 int32_t ret;
5136
5137 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1);
5138 *val = reg.tap_ths_x;
5139
5140 return ret;
5141 }
5142
5143 /**
5144 * @brief Selection of axis priority for TAP detection.[set]
5145 *
5146 * @param ctx read / write interface definitions
5147 * @param val change the values of tap_priority in
5148 * reg TAP_CFG1
5149 * @retval interface status (MANDATORY: return 0 -> no Error)
5150 *
5151 */
lsm6dso_tap_axis_priority_set(const stmdev_ctx_t * ctx,lsm6dso_tap_priority_t val)5152 int32_t lsm6dso_tap_axis_priority_set(const stmdev_ctx_t *ctx,
5153 lsm6dso_tap_priority_t val)
5154 {
5155 lsm6dso_tap_cfg1_t reg;
5156 int32_t ret;
5157
5158 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1);
5159
5160 if (ret == 0)
5161 {
5162 reg.tap_priority = (uint8_t)val;
5163 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1);
5164 }
5165
5166 return ret;
5167 }
5168
5169 /**
5170 * @brief Selection of axis priority for TAP detection.[get]
5171 *
5172 * @param ctx read / write interface definitions
5173 * @param val Get the values of tap_priority in
5174 * reg TAP_CFG1
5175 * @retval interface status (MANDATORY: return 0 -> no Error)
5176 *
5177 */
lsm6dso_tap_axis_priority_get(const stmdev_ctx_t * ctx,lsm6dso_tap_priority_t * val)5178 int32_t lsm6dso_tap_axis_priority_get(const stmdev_ctx_t *ctx,
5179 lsm6dso_tap_priority_t *val)
5180 {
5181 lsm6dso_tap_cfg1_t reg;
5182 int32_t ret;
5183
5184 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1);
5185
5186 switch (reg.tap_priority)
5187 {
5188 case LSM6DSO_XYZ:
5189 *val = LSM6DSO_XYZ;
5190 break;
5191
5192 case LSM6DSO_YXZ:
5193 *val = LSM6DSO_YXZ;
5194 break;
5195
5196 case LSM6DSO_XZY:
5197 *val = LSM6DSO_XZY;
5198 break;
5199
5200 case LSM6DSO_ZYX:
5201 *val = LSM6DSO_ZYX;
5202 break;
5203
5204 case LSM6DSO_YZX:
5205 *val = LSM6DSO_YZX;
5206 break;
5207
5208 case LSM6DSO_ZXY:
5209 *val = LSM6DSO_ZXY;
5210 break;
5211
5212 default:
5213 *val = LSM6DSO_XYZ;
5214 break;
5215 }
5216
5217 return ret;
5218 }
5219
5220 /**
5221 * @brief Y-axis tap recognition threshold.[set]
5222 *
5223 * @param ctx read / write interface definitions
5224 * @param val change the values of tap_ths_y in reg TAP_CFG2
5225 * @retval interface status (MANDATORY: return 0 -> no Error)
5226 *
5227 */
lsm6dso_tap_threshold_y_set(const stmdev_ctx_t * ctx,uint8_t val)5228 int32_t lsm6dso_tap_threshold_y_set(const stmdev_ctx_t *ctx, uint8_t val)
5229 {
5230 lsm6dso_tap_cfg2_t reg;
5231 int32_t ret;
5232
5233 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1);
5234
5235 if (ret == 0)
5236 {
5237 reg.tap_ths_y = val;
5238 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1);
5239 }
5240
5241 return ret;
5242 }
5243
5244 /**
5245 * @brief Y-axis tap recognition threshold.[get]
5246 *
5247 * @param ctx read / write interface definitions
5248 * @param val Get the values of tap_ths_y in reg TAP_CFG2
5249 * @retval interface status (MANDATORY: return 0 -> no Error)
5250 *
5251 */
lsm6dso_tap_threshold_y_get(const stmdev_ctx_t * ctx,uint8_t * val)5252 int32_t lsm6dso_tap_threshold_y_get(const stmdev_ctx_t *ctx, uint8_t *val)
5253 {
5254 lsm6dso_tap_cfg2_t reg;
5255 int32_t ret;
5256
5257 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1);
5258 *val = reg.tap_ths_y;
5259
5260 return ret;
5261 }
5262
5263 /**
5264 * @brief Z-axis recognition threshold.[set]
5265 *
5266 * @param ctx read / write interface definitions
5267 * @param val change the values of tap_ths_z in reg TAP_THS_6D
5268 * @retval interface status (MANDATORY: return 0 -> no Error)
5269 *
5270 */
lsm6dso_tap_threshold_z_set(const stmdev_ctx_t * ctx,uint8_t val)5271 int32_t lsm6dso_tap_threshold_z_set(const stmdev_ctx_t *ctx, uint8_t val)
5272 {
5273 lsm6dso_tap_ths_6d_t reg;
5274 int32_t ret;
5275
5276 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
5277
5278 if (ret == 0)
5279 {
5280 reg.tap_ths_z = val;
5281 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
5282 }
5283
5284 return ret;
5285 }
5286
5287 /**
5288 * @brief Z-axis recognition threshold.[get]
5289 *
5290 * @param ctx read / write interface definitions
5291 * @param val Get the values of tap_ths_z in reg TAP_THS_6D
5292 * @retval interface status (MANDATORY: return 0 -> no Error)
5293 *
5294 */
lsm6dso_tap_threshold_z_get(const stmdev_ctx_t * ctx,uint8_t * val)5295 int32_t lsm6dso_tap_threshold_z_get(const stmdev_ctx_t *ctx, uint8_t *val)
5296 {
5297 lsm6dso_tap_ths_6d_t reg;
5298 int32_t ret;
5299
5300 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
5301 *val = reg.tap_ths_z;
5302
5303 return ret;
5304 }
5305
5306 /**
5307 * @brief Maximum duration is the maximum time of an
5308 * over threshold signal detection to be recognized
5309 * as a tap event. The default value of these bits
5310 * is 00b which corresponds to 4*ODR_XL time.
5311 * If the SHOCK[1:0] bits are set to a different
5312 * value, 1LSB corresponds to 8*ODR_XL time.[set]
5313 *
5314 * @param ctx read / write interface definitions
5315 * @param val change the values of shock in reg INT_DUR2
5316 * @retval interface status (MANDATORY: return 0 -> no Error)
5317 *
5318 */
lsm6dso_tap_shock_set(const stmdev_ctx_t * ctx,uint8_t val)5319 int32_t lsm6dso_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val)
5320 {
5321 lsm6dso_int_dur2_t reg;
5322 int32_t ret;
5323
5324 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
5325
5326 if (ret == 0)
5327 {
5328 reg.shock = val;
5329 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
5330 }
5331
5332 return ret;
5333 }
5334
5335 /**
5336 * @brief Maximum duration is the maximum time of an
5337 * over threshold signal detection to be recognized
5338 * as a tap event. The default value of these bits
5339 * is 00b which corresponds to 4*ODR_XL time.
5340 * If the SHOCK[1:0] bits are set to a different
5341 * value, 1LSB corresponds to 8*ODR_XL time.[get]
5342 *
5343 * @param ctx read / write interface definitions
5344 * @param val Get the values of shock in reg INT_DUR2
5345 * @retval interface status (MANDATORY: return 0 -> no Error)
5346 *
5347 */
lsm6dso_tap_shock_get(const stmdev_ctx_t * ctx,uint8_t * val)5348 int32_t lsm6dso_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val)
5349 {
5350 lsm6dso_int_dur2_t reg;
5351 int32_t ret;
5352
5353 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
5354 *val = reg.shock;
5355
5356 return ret;
5357 }
5358
5359 /**
5360 * @brief Quiet time is the time after the first detected
5361 * tap in which there must not be any over threshold
5362 * event.
5363 * The default value of these bits is 00b which
5364 * corresponds to 2*ODR_XL time. If the QUIET[1:0]
5365 * bits are set to a different value,
5366 * 1LSB corresponds to 4*ODR_XL time.[set]
5367 *
5368 * @param ctx read / write interface definitions
5369 * @param val change the values of quiet in reg INT_DUR2
5370 * @retval interface status (MANDATORY: return 0 -> no Error)
5371 *
5372 */
lsm6dso_tap_quiet_set(const stmdev_ctx_t * ctx,uint8_t val)5373 int32_t lsm6dso_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val)
5374 {
5375 lsm6dso_int_dur2_t reg;
5376 int32_t ret;
5377
5378 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
5379
5380 if (ret == 0)
5381 {
5382 reg.quiet = val;
5383 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
5384 }
5385
5386 return ret;
5387 }
5388
5389 /**
5390 * @brief Quiet time is the time after the first detected
5391 * tap in which there must not be any over threshold
5392 * event.
5393 * The default value of these bits is 00b which
5394 * corresponds to 2*ODR_XL time.
5395 * If the QUIET[1:0] bits are set to a different
5396 * value, 1LSB corresponds to 4*ODR_XL time.[get]
5397 *
5398 * @param ctx read / write interface definitions
5399 * @param val Get the values of quiet in reg INT_DUR2
5400 * @retval interface status (MANDATORY: return 0 -> no Error)
5401 *
5402 */
lsm6dso_tap_quiet_get(const stmdev_ctx_t * ctx,uint8_t * val)5403 int32_t lsm6dso_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val)
5404 {
5405 lsm6dso_int_dur2_t reg;
5406 int32_t ret;
5407
5408 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
5409 *val = reg.quiet;
5410
5411 return ret;
5412 }
5413
5414 /**
5415 * @brief When double tap recognition is enabled,
5416 * this register expresses the maximum time
5417 * between two consecutive detected taps to
5418 * determine a double tap event.
5419 * The default value of these bits is 0000b which
5420 * corresponds to 16*ODR_XL time.
5421 * If the DUR[3:0] bits are set to a different value,
5422 * 1LSB corresponds to 32*ODR_XL time.[set]
5423 *
5424 * @param ctx read / write interface definitions
5425 * @param val change the values of dur in reg INT_DUR2
5426 * @retval interface status (MANDATORY: return 0 -> no Error)
5427 *
5428 */
lsm6dso_tap_dur_set(const stmdev_ctx_t * ctx,uint8_t val)5429 int32_t lsm6dso_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
5430 {
5431 lsm6dso_int_dur2_t reg;
5432 int32_t ret;
5433
5434 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
5435
5436 if (ret == 0)
5437 {
5438 reg.dur = val;
5439 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
5440 }
5441
5442 return ret;
5443 }
5444
5445 /**
5446 * @brief When double tap recognition is enabled,
5447 * this register expresses the maximum time
5448 * between two consecutive detected taps to
5449 * determine a double tap event.
5450 * The default value of these bits is 0000b which
5451 * corresponds to 16*ODR_XL time. If the DUR[3:0]
5452 * bits are set to a different value,
5453 * 1LSB corresponds to 32*ODR_XL time.[get]
5454 *
5455 * @param ctx read / write interface definitions
5456 * @param val Get the values of dur in reg INT_DUR2
5457 * @retval interface status (MANDATORY: return 0 -> no Error)
5458 *
5459 */
lsm6dso_tap_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)5460 int32_t lsm6dso_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
5461 {
5462 lsm6dso_int_dur2_t reg;
5463 int32_t ret;
5464
5465 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
5466 *val = reg.dur;
5467
5468 return ret;
5469 }
5470
5471 /**
5472 * @brief Single/double-tap event enable.[set]
5473 *
5474 * @param ctx read / write interface definitions
5475 * @param val change the values of single_double_tap in reg WAKE_UP_THS
5476 * @retval interface status (MANDATORY: return 0 -> no Error)
5477 *
5478 */
lsm6dso_tap_mode_set(const stmdev_ctx_t * ctx,lsm6dso_single_double_tap_t val)5479 int32_t lsm6dso_tap_mode_set(const stmdev_ctx_t *ctx,
5480 lsm6dso_single_double_tap_t val)
5481 {
5482 lsm6dso_wake_up_ths_t reg;
5483 int32_t ret;
5484
5485 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
5486
5487 if (ret == 0)
5488 {
5489 reg.single_double_tap = (uint8_t)val;
5490 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
5491 }
5492
5493 return ret;
5494 }
5495
5496 /**
5497 * @brief Single/double-tap event enable.[get]
5498 *
5499 * @param ctx read / write interface definitions
5500 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
5501 * @retval interface status (MANDATORY: return 0 -> no Error)
5502 *
5503 */
lsm6dso_tap_mode_get(const stmdev_ctx_t * ctx,lsm6dso_single_double_tap_t * val)5504 int32_t lsm6dso_tap_mode_get(const stmdev_ctx_t *ctx,
5505 lsm6dso_single_double_tap_t *val)
5506 {
5507 lsm6dso_wake_up_ths_t reg;
5508 int32_t ret;
5509
5510 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
5511
5512 switch (reg.single_double_tap)
5513 {
5514 case LSM6DSO_ONLY_SINGLE:
5515 *val = LSM6DSO_ONLY_SINGLE;
5516 break;
5517
5518 case LSM6DSO_BOTH_SINGLE_DOUBLE:
5519 *val = LSM6DSO_BOTH_SINGLE_DOUBLE;
5520 break;
5521
5522 default:
5523 *val = LSM6DSO_ONLY_SINGLE;
5524 break;
5525 }
5526
5527 return ret;
5528 }
5529
5530 /**
5531 * @}
5532 *
5533 */
5534
5535 /**
5536 * @defgroup LSM6DSO_ Six_position_detection(6D/4D)
5537 * @brief This section groups all the functions concerning six position
5538 * detection (6D).
5539 * @{
5540 *
5541 */
5542
5543 /**
5544 * @brief Threshold for 4D/6D function.[set]
5545 *
5546 * @param ctx read / write interface definitions
5547 * @param val change the values of sixd_ths in reg TAP_THS_6D
5548 * @retval interface status (MANDATORY: return 0 -> no Error)
5549 *
5550 */
lsm6dso_6d_threshold_set(const stmdev_ctx_t * ctx,lsm6dso_sixd_ths_t val)5551 int32_t lsm6dso_6d_threshold_set(const stmdev_ctx_t *ctx,
5552 lsm6dso_sixd_ths_t val)
5553 {
5554 lsm6dso_tap_ths_6d_t reg;
5555 int32_t ret;
5556
5557 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
5558
5559 if (ret == 0)
5560 {
5561 reg.sixd_ths = (uint8_t)val;
5562 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
5563 }
5564
5565 return ret;
5566 }
5567
5568 /**
5569 * @brief Threshold for 4D/6D function.[get]
5570 *
5571 * @param ctx read / write interface definitions
5572 * @param val Get the values of sixd_ths in reg TAP_THS_6D
5573 * @retval interface status (MANDATORY: return 0 -> no Error)
5574 *
5575 */
lsm6dso_6d_threshold_get(const stmdev_ctx_t * ctx,lsm6dso_sixd_ths_t * val)5576 int32_t lsm6dso_6d_threshold_get(const stmdev_ctx_t *ctx,
5577 lsm6dso_sixd_ths_t *val)
5578 {
5579 lsm6dso_tap_ths_6d_t reg;
5580 int32_t ret;
5581
5582 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
5583
5584 switch (reg.sixd_ths)
5585 {
5586 case LSM6DSO_DEG_80:
5587 *val = LSM6DSO_DEG_80;
5588 break;
5589
5590 case LSM6DSO_DEG_70:
5591 *val = LSM6DSO_DEG_70;
5592 break;
5593
5594 case LSM6DSO_DEG_60:
5595 *val = LSM6DSO_DEG_60;
5596 break;
5597
5598 case LSM6DSO_DEG_50:
5599 *val = LSM6DSO_DEG_50;
5600 break;
5601
5602 default:
5603 *val = LSM6DSO_DEG_80;
5604 break;
5605 }
5606
5607 return ret;
5608 }
5609
5610 /**
5611 * @brief 4D orientation detection enable.[set]
5612 *
5613 * @param ctx read / write interface definitions
5614 * @param val change the values of d4d_en in reg TAP_THS_6D
5615 * @retval interface status (MANDATORY: return 0 -> no Error)
5616 *
5617 */
lsm6dso_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)5618 int32_t lsm6dso_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
5619 {
5620 lsm6dso_tap_ths_6d_t reg;
5621 int32_t ret;
5622
5623 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
5624
5625 if (ret == 0)
5626 {
5627 reg.d4d_en = val;
5628 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
5629 }
5630
5631 return ret;
5632 }
5633
5634 /**
5635 * @brief 4D orientation detection enable.[get]
5636 *
5637 * @param ctx read / write interface definitions
5638 * @param val Get the values of d4d_en in reg TAP_THS_6D
5639 * @retval interface status (MANDATORY: return 0 -> no Error)
5640 *
5641 */
lsm6dso_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)5642 int32_t lsm6dso_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
5643 {
5644 lsm6dso_tap_ths_6d_t reg;
5645 int32_t ret;
5646
5647 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
5648 *val = reg.d4d_en;
5649
5650 return ret;
5651 }
5652
5653 /**
5654 * @}
5655 *
5656 */
5657
5658 /**
5659 * @defgroup LSM6DSO_free_fall
5660 * @brief This section group all the functions concerning the free
5661 * fall detection.
5662 * @{
5663 *
5664 */
5665 /**
5666 * @brief Free fall threshold setting.[set]
5667 *
5668 * @param ctx read / write interface definitions
5669 * @param val change the values of ff_ths in reg FREE_FALL
5670 * @retval interface status (MANDATORY: return 0 -> no Error)
5671 *
5672 */
lsm6dso_ff_threshold_set(const stmdev_ctx_t * ctx,lsm6dso_ff_ths_t val)5673 int32_t lsm6dso_ff_threshold_set(const stmdev_ctx_t *ctx,
5674 lsm6dso_ff_ths_t val)
5675 {
5676 lsm6dso_free_fall_t reg;
5677 int32_t ret;
5678
5679 ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)®, 1);
5680
5681 if (ret == 0)
5682 {
5683 reg.ff_ths = (uint8_t)val;
5684 ret = lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)®, 1);
5685 }
5686
5687 return ret;
5688 }
5689
5690 /**
5691 * @brief Free fall threshold setting.[get]
5692 *
5693 * @param ctx read / write interface definitions
5694 * @param val Get the values of ff_ths in reg FREE_FALL
5695 * @retval interface status (MANDATORY: return 0 -> no Error)
5696 *
5697 */
lsm6dso_ff_threshold_get(const stmdev_ctx_t * ctx,lsm6dso_ff_ths_t * val)5698 int32_t lsm6dso_ff_threshold_get(const stmdev_ctx_t *ctx,
5699 lsm6dso_ff_ths_t *val)
5700 {
5701 lsm6dso_free_fall_t reg;
5702 int32_t ret;
5703
5704 ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)®, 1);
5705
5706 switch (reg.ff_ths)
5707 {
5708 case LSM6DSO_FF_TSH_156mg:
5709 *val = LSM6DSO_FF_TSH_156mg;
5710 break;
5711
5712 case LSM6DSO_FF_TSH_219mg:
5713 *val = LSM6DSO_FF_TSH_219mg;
5714 break;
5715
5716 case LSM6DSO_FF_TSH_250mg:
5717 *val = LSM6DSO_FF_TSH_250mg;
5718 break;
5719
5720 case LSM6DSO_FF_TSH_312mg:
5721 *val = LSM6DSO_FF_TSH_312mg;
5722 break;
5723
5724 case LSM6DSO_FF_TSH_344mg:
5725 *val = LSM6DSO_FF_TSH_344mg;
5726 break;
5727
5728 case LSM6DSO_FF_TSH_406mg:
5729 *val = LSM6DSO_FF_TSH_406mg;
5730 break;
5731
5732 case LSM6DSO_FF_TSH_469mg:
5733 *val = LSM6DSO_FF_TSH_469mg;
5734 break;
5735
5736 case LSM6DSO_FF_TSH_500mg:
5737 *val = LSM6DSO_FF_TSH_500mg;
5738 break;
5739
5740 default:
5741 *val = LSM6DSO_FF_TSH_156mg;
5742 break;
5743 }
5744
5745 return ret;
5746 }
5747
5748 /**
5749 * @brief Free-fall duration event.[set]
5750 * 1LSb = 1 / ODR
5751 *
5752 * @param ctx read / write interface definitions
5753 * @param val change the values of ff_dur in reg FREE_FALL
5754 * @retval interface status (MANDATORY: return 0 -> no Error)
5755 *
5756 */
lsm6dso_ff_dur_set(const stmdev_ctx_t * ctx,uint8_t val)5757 int32_t lsm6dso_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
5758 {
5759 lsm6dso_wake_up_dur_t wake_up_dur;
5760 lsm6dso_free_fall_t free_fall;
5761 int32_t ret;
5762
5763 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
5764 ret += lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&free_fall, 1);
5765 if (ret != 0) { return ret; }
5766
5767 wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
5768 free_fall.ff_dur = (uint8_t)val & 0x1FU;
5769
5770 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)&wake_up_dur, 1);
5771 ret += lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&free_fall, 1);
5772
5773 return ret;
5774 }
5775
5776 /**
5777 * @brief Free-fall duration event.[get]
5778 * 1LSb = 1 / ODR
5779 *
5780 * @param ctx read / write interface definitions
5781 * @param val Get the values of ff_dur in reg FREE_FALL
5782 * @retval interface status (MANDATORY: return 0 -> no Error)
5783 *
5784 */
lsm6dso_ff_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)5785 int32_t lsm6dso_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
5786 {
5787 lsm6dso_wake_up_dur_t wake_up_dur;
5788 lsm6dso_free_fall_t free_fall;
5789 int32_t ret;
5790
5791 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR,
5792 (uint8_t *)&wake_up_dur, 1);
5793
5794 if (ret == 0)
5795 {
5796 ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&free_fall, 1);
5797 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
5798 }
5799
5800 return ret;
5801 }
5802
5803 /**
5804 * @}
5805 *
5806 */
5807
5808 /**
5809 * @defgroup LSM6DSO_fifo
5810 * @brief This section group all the functions concerning the fifo usage
5811 * @{
5812 *
5813 */
5814
5815 /**
5816 * @brief FIFO watermark level selection.[set]
5817 *
5818 * @param ctx read / write interface definitions
5819 * @param val change the values of wtm in reg FIFO_CTRL1
5820 * @retval interface status (MANDATORY: return 0 -> no Error)
5821 *
5822 */
lsm6dso_fifo_watermark_set(const stmdev_ctx_t * ctx,uint16_t val)5823 int32_t lsm6dso_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val)
5824 {
5825 lsm6dso_fifo_ctrl1_t fifo_ctrl1;
5826 lsm6dso_fifo_ctrl2_t fifo_ctrl2;
5827 int32_t ret;
5828
5829 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
5830 if (ret != 0) { return ret; }
5831
5832 fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val;
5833 fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8);
5834
5835 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
5836 ret += lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
5837
5838 return ret;
5839 }
5840
5841 /**
5842 * @brief FIFO watermark level selection.[get]
5843 *
5844 * @param ctx read / write interface definitions
5845 * @param val Get the values of wtm in reg FIFO_CTRL1
5846 * @retval interface status (MANDATORY: return 0 -> no Error)
5847 *
5848 */
lsm6dso_fifo_watermark_get(const stmdev_ctx_t * ctx,uint16_t * val)5849 int32_t lsm6dso_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val)
5850 {
5851 lsm6dso_fifo_ctrl1_t fifo_ctrl1;
5852 lsm6dso_fifo_ctrl2_t fifo_ctrl2;
5853 int32_t ret;
5854
5855 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL1, (uint8_t *)&fifo_ctrl1, 1);
5856
5857 if (ret == 0)
5858 {
5859 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)&fifo_ctrl2, 1);
5860 *val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm;
5861 }
5862
5863 return ret;
5864 }
5865
5866 /**
5867 * @brief FIFO compression feature initialization request [set].
5868 *
5869 * @param ctx read / write interface definitions
5870 * @param val change the values of FIFO_COMPR_INIT in
5871 * reg EMB_FUNC_INIT_B
5872 * @retval interface status (MANDATORY: return 0 -> no Error)
5873 *
5874 */
lsm6dso_compression_algo_init_set(const stmdev_ctx_t * ctx,uint8_t val)5875 int32_t lsm6dso_compression_algo_init_set(const stmdev_ctx_t *ctx,
5876 uint8_t val)
5877 {
5878 lsm6dso_emb_func_init_b_t reg;
5879 int32_t ret;
5880
5881 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
5882 if (ret != 0) { return ret; }
5883
5884 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1);
5885 reg.fifo_compr_init = val;
5886 ret += lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1);
5887
5888 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
5889
5890 return ret;
5891 }
5892
5893 /**
5894 * @brief FIFO compression feature initialization request [get].
5895 *
5896 * @param ctx read / write interface definitions
5897 * @param val Get the values of FIFO_COMPR_INIT in
5898 * reg EMB_FUNC_INIT_B
5899 * @retval interface status (MANDATORY: return 0 -> no Error)
5900 *
5901 */
lsm6dso_compression_algo_init_get(const stmdev_ctx_t * ctx,uint8_t * val)5902 int32_t lsm6dso_compression_algo_init_get(const stmdev_ctx_t *ctx,
5903 uint8_t *val)
5904 {
5905 lsm6dso_emb_func_init_b_t reg;
5906 int32_t ret;
5907
5908 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
5909 ret += lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1);
5910 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
5911
5912 *val = reg.fifo_compr_init;
5913
5914 return ret;
5915 }
5916
5917 /**
5918 * @brief Enable and configure compression algo.[set]
5919 *
5920 * @param ctx read / write interface definitions
5921 * @param val change the values of uncoptr_rate in
5922 * reg FIFO_CTRL2
5923 * @retval interface status (MANDATORY: return 0 -> no Error)
5924 *
5925 */
lsm6dso_compression_algo_set(const stmdev_ctx_t * ctx,lsm6dso_uncoptr_rate_t val)5926 int32_t lsm6dso_compression_algo_set(const stmdev_ctx_t *ctx,
5927 lsm6dso_uncoptr_rate_t val)
5928 {
5929 lsm6dso_fifo_ctrl2_t fifo_ctrl2;
5930 int32_t ret;
5931
5932 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2,
5933 (uint8_t *)&fifo_ctrl2, 1);
5934
5935 if (ret == 0)
5936 {
5937 fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
5938 fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
5939 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2,
5940 (uint8_t *)&fifo_ctrl2, 1);
5941 }
5942
5943 return ret;
5944 }
5945
5946 /**
5947 * @brief Enable and configure compression algo.[get]
5948 *
5949 * @param ctx read / write interface definitions
5950 * @param val Get the values of uncoptr_rate in
5951 * reg FIFO_CTRL2
5952 * @retval interface status (MANDATORY: return 0 -> no Error)
5953 *
5954 */
lsm6dso_compression_algo_get(const stmdev_ctx_t * ctx,lsm6dso_uncoptr_rate_t * val)5955 int32_t lsm6dso_compression_algo_get(const stmdev_ctx_t *ctx,
5956 lsm6dso_uncoptr_rate_t *val)
5957 {
5958 lsm6dso_fifo_ctrl2_t reg;
5959 int32_t ret;
5960
5961 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
5962
5963 switch ((reg.fifo_compr_rt_en << 2) | reg.uncoptr_rate)
5964 {
5965 case LSM6DSO_CMP_DISABLE:
5966 *val = LSM6DSO_CMP_DISABLE;
5967 break;
5968
5969 case LSM6DSO_CMP_ALWAYS:
5970 *val = LSM6DSO_CMP_ALWAYS;
5971 break;
5972
5973 case LSM6DSO_CMP_8_TO_1:
5974 *val = LSM6DSO_CMP_8_TO_1;
5975 break;
5976
5977 case LSM6DSO_CMP_16_TO_1:
5978 *val = LSM6DSO_CMP_16_TO_1;
5979 break;
5980
5981 case LSM6DSO_CMP_32_TO_1:
5982 *val = LSM6DSO_CMP_32_TO_1;
5983 break;
5984
5985 default:
5986 *val = LSM6DSO_CMP_DISABLE;
5987 break;
5988 }
5989
5990 return ret;
5991 }
5992
5993 /**
5994 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
5995 *
5996 * @param ctx read / write interface definitions
5997 * @param val change the values of odrchg_en in reg FIFO_CTRL2
5998 * @retval interface status (MANDATORY: return 0 -> no Error)
5999 *
6000 */
lsm6dso_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t * ctx,uint8_t val)6001 int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(const stmdev_ctx_t *ctx,
6002 uint8_t val)
6003 {
6004 lsm6dso_fifo_ctrl2_t reg;
6005 int32_t ret;
6006
6007 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
6008
6009 if (ret == 0)
6010 {
6011 reg.odrchg_en = val;
6012 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
6013 }
6014
6015 return ret;
6016 }
6017
6018 /**
6019 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
6020 *
6021 * @param ctx read / write interface definitions
6022 * @param val Get the values of odrchg_en in reg FIFO_CTRL2
6023 * @retval interface status (MANDATORY: return 0 -> no Error)
6024 *
6025 */
lsm6dso_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t * ctx,uint8_t * val)6026 int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(const stmdev_ctx_t *ctx,
6027 uint8_t *val)
6028 {
6029 lsm6dso_fifo_ctrl2_t reg;
6030 int32_t ret;
6031
6032 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
6033 *val = reg.odrchg_en;
6034
6035 return ret;
6036 }
6037
6038 /**
6039 * @brief Enables/Disables compression algorithm runtime.[set]
6040 *
6041 * @param ctx read / write interface definitions
6042 * @param val change the values of fifo_compr_rt_en in
6043 * reg FIFO_CTRL2
6044 * @retval interface status (MANDATORY: return 0 -> no Error)
6045 *
6046 */
lsm6dso_compression_algo_real_time_set(const stmdev_ctx_t * ctx,uint8_t val)6047 int32_t lsm6dso_compression_algo_real_time_set(const stmdev_ctx_t *ctx,
6048 uint8_t val)
6049 {
6050 lsm6dso_fifo_ctrl2_t reg;
6051 int32_t ret;
6052
6053 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
6054
6055 if (ret == 0)
6056 {
6057 reg.fifo_compr_rt_en = val;
6058 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
6059 }
6060
6061 return ret;
6062 }
6063
6064 /**
6065 * @brief Enables/Disables compression algorithm runtime. [get]
6066 *
6067 * @param ctx read / write interface definitions
6068 * @param val Get the values of fifo_compr_rt_en in reg FIFO_CTRL2
6069 * @retval interface status (MANDATORY: return 0 -> no Error)
6070 *
6071 */
lsm6dso_compression_algo_real_time_get(const stmdev_ctx_t * ctx,uint8_t * val)6072 int32_t lsm6dso_compression_algo_real_time_get(const stmdev_ctx_t *ctx,
6073 uint8_t *val)
6074 {
6075 lsm6dso_fifo_ctrl2_t reg;
6076 int32_t ret;
6077
6078 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
6079 *val = reg.fifo_compr_rt_en;
6080
6081 return ret;
6082 }
6083
6084 /**
6085 * @brief Sensing chain FIFO stop values memorization at
6086 * threshold level.[set]
6087 *
6088 * @param ctx read / write interface definitions
6089 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2
6090 * @retval interface status (MANDATORY: return 0 -> no Error)
6091 *
6092 */
lsm6dso_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)6093 int32_t lsm6dso_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
6094 {
6095 lsm6dso_fifo_ctrl2_t reg;
6096 int32_t ret;
6097
6098 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
6099
6100 if (ret == 0)
6101 {
6102 reg.stop_on_wtm = val;
6103 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
6104 }
6105
6106 return ret;
6107 }
6108
6109 /**
6110 * @brief Sensing chain FIFO stop values memorization at
6111 * threshold level.[get]
6112 *
6113 * @param ctx read / write interface definitions
6114 * @param val Get the values of stop_on_wtm in reg FIFO_CTRL2
6115 * @retval interface status (MANDATORY: return 0 -> no Error)
6116 *
6117 */
lsm6dso_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)6118 int32_t lsm6dso_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val)
6119 {
6120 lsm6dso_fifo_ctrl2_t reg;
6121 int32_t ret;
6122
6123 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
6124 *val = reg.stop_on_wtm;
6125
6126 return ret;
6127 }
6128
6129 /**
6130 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6131 * for accelerometer data.[set]
6132 *
6133 * @param ctx read / write interface definitions
6134 * @param val change the values of bdr_xl in reg FIFO_CTRL3
6135 * @retval interface status (MANDATORY: return 0 -> no Error)
6136 *
6137 */
lsm6dso_fifo_xl_batch_set(const stmdev_ctx_t * ctx,lsm6dso_bdr_xl_t val)6138 int32_t lsm6dso_fifo_xl_batch_set(const stmdev_ctx_t *ctx,
6139 lsm6dso_bdr_xl_t val)
6140 {
6141 lsm6dso_fifo_ctrl3_t reg;
6142 int32_t ret;
6143
6144 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1);
6145
6146 if (ret == 0)
6147 {
6148 reg.bdr_xl = (uint8_t)val;
6149 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1);
6150 }
6151
6152 return ret;
6153 }
6154
6155 /**
6156 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6157 * for accelerometer data.[get]
6158 *
6159 * @param ctx read / write interface definitions
6160 * @param val Get the values of bdr_xl in reg FIFO_CTRL3
6161 * @retval interface status (MANDATORY: return 0 -> no Error)
6162 *
6163 */
lsm6dso_fifo_xl_batch_get(const stmdev_ctx_t * ctx,lsm6dso_bdr_xl_t * val)6164 int32_t lsm6dso_fifo_xl_batch_get(const stmdev_ctx_t *ctx,
6165 lsm6dso_bdr_xl_t *val)
6166 {
6167 lsm6dso_fifo_ctrl3_t reg;
6168 int32_t ret;
6169
6170 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1);
6171
6172 switch (reg.bdr_xl)
6173 {
6174 case LSM6DSO_XL_NOT_BATCHED:
6175 *val = LSM6DSO_XL_NOT_BATCHED;
6176 break;
6177
6178 case LSM6DSO_XL_BATCHED_AT_12Hz5:
6179 *val = LSM6DSO_XL_BATCHED_AT_12Hz5;
6180 break;
6181
6182 case LSM6DSO_XL_BATCHED_AT_26Hz:
6183 *val = LSM6DSO_XL_BATCHED_AT_26Hz;
6184 break;
6185
6186 case LSM6DSO_XL_BATCHED_AT_52Hz:
6187 *val = LSM6DSO_XL_BATCHED_AT_52Hz;
6188 break;
6189
6190 case LSM6DSO_XL_BATCHED_AT_104Hz:
6191 *val = LSM6DSO_XL_BATCHED_AT_104Hz;
6192 break;
6193
6194 case LSM6DSO_XL_BATCHED_AT_208Hz:
6195 *val = LSM6DSO_XL_BATCHED_AT_208Hz;
6196 break;
6197
6198 case LSM6DSO_XL_BATCHED_AT_417Hz:
6199 *val = LSM6DSO_XL_BATCHED_AT_417Hz;
6200 break;
6201
6202 case LSM6DSO_XL_BATCHED_AT_833Hz:
6203 *val = LSM6DSO_XL_BATCHED_AT_833Hz;
6204 break;
6205
6206 case LSM6DSO_XL_BATCHED_AT_1667Hz:
6207 *val = LSM6DSO_XL_BATCHED_AT_1667Hz;
6208 break;
6209
6210 case LSM6DSO_XL_BATCHED_AT_3333Hz:
6211 *val = LSM6DSO_XL_BATCHED_AT_3333Hz;
6212 break;
6213
6214 case LSM6DSO_XL_BATCHED_AT_6667Hz:
6215 *val = LSM6DSO_XL_BATCHED_AT_6667Hz;
6216 break;
6217
6218 case LSM6DSO_XL_BATCHED_AT_6Hz5:
6219 *val = LSM6DSO_XL_BATCHED_AT_6Hz5;
6220 break;
6221
6222 default:
6223 *val = LSM6DSO_XL_NOT_BATCHED;
6224 break;
6225 }
6226
6227 return ret;
6228 }
6229
6230 /**
6231 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6232 * for gyroscope data.[set]
6233 *
6234 * @param ctx read / write interface definitions
6235 * @param val change the values of bdr_gy in reg FIFO_CTRL3
6236 * @retval interface status (MANDATORY: return 0 -> no Error)
6237 *
6238 */
lsm6dso_fifo_gy_batch_set(const stmdev_ctx_t * ctx,lsm6dso_bdr_gy_t val)6239 int32_t lsm6dso_fifo_gy_batch_set(const stmdev_ctx_t *ctx,
6240 lsm6dso_bdr_gy_t val)
6241 {
6242 lsm6dso_fifo_ctrl3_t reg;
6243 int32_t ret;
6244
6245 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1);
6246
6247 if (ret == 0)
6248 {
6249 reg.bdr_gy = (uint8_t)val;
6250 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1);
6251 }
6252
6253 return ret;
6254 }
6255
6256 /**
6257 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6258 * for gyroscope data.[get]
6259 *
6260 * @param ctx read / write interface definitions
6261 * @param val Get the values of bdr_gy in reg FIFO_CTRL3
6262 * @retval interface status (MANDATORY: return 0 -> no Error)
6263 *
6264 */
lsm6dso_fifo_gy_batch_get(const stmdev_ctx_t * ctx,lsm6dso_bdr_gy_t * val)6265 int32_t lsm6dso_fifo_gy_batch_get(const stmdev_ctx_t *ctx,
6266 lsm6dso_bdr_gy_t *val)
6267 {
6268 lsm6dso_fifo_ctrl3_t reg;
6269 int32_t ret;
6270
6271 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1);
6272
6273 switch (reg.bdr_gy)
6274 {
6275 case LSM6DSO_GY_NOT_BATCHED:
6276 *val = LSM6DSO_GY_NOT_BATCHED;
6277 break;
6278
6279 case LSM6DSO_GY_BATCHED_AT_12Hz5:
6280 *val = LSM6DSO_GY_BATCHED_AT_12Hz5;
6281 break;
6282
6283 case LSM6DSO_GY_BATCHED_AT_26Hz:
6284 *val = LSM6DSO_GY_BATCHED_AT_26Hz;
6285 break;
6286
6287 case LSM6DSO_GY_BATCHED_AT_52Hz:
6288 *val = LSM6DSO_GY_BATCHED_AT_52Hz;
6289 break;
6290
6291 case LSM6DSO_GY_BATCHED_AT_104Hz:
6292 *val = LSM6DSO_GY_BATCHED_AT_104Hz;
6293 break;
6294
6295 case LSM6DSO_GY_BATCHED_AT_208Hz:
6296 *val = LSM6DSO_GY_BATCHED_AT_208Hz;
6297 break;
6298
6299 case LSM6DSO_GY_BATCHED_AT_417Hz:
6300 *val = LSM6DSO_GY_BATCHED_AT_417Hz;
6301 break;
6302
6303 case LSM6DSO_GY_BATCHED_AT_833Hz:
6304 *val = LSM6DSO_GY_BATCHED_AT_833Hz;
6305 break;
6306
6307 case LSM6DSO_GY_BATCHED_AT_1667Hz:
6308 *val = LSM6DSO_GY_BATCHED_AT_1667Hz;
6309 break;
6310
6311 case LSM6DSO_GY_BATCHED_AT_3333Hz:
6312 *val = LSM6DSO_GY_BATCHED_AT_3333Hz;
6313 break;
6314
6315 case LSM6DSO_GY_BATCHED_AT_6667Hz:
6316 *val = LSM6DSO_GY_BATCHED_AT_6667Hz;
6317 break;
6318
6319 case LSM6DSO_GY_BATCHED_AT_6Hz5:
6320 *val = LSM6DSO_GY_BATCHED_AT_6Hz5;
6321 break;
6322
6323 default:
6324 *val = LSM6DSO_GY_NOT_BATCHED;
6325 break;
6326 }
6327
6328 return ret;
6329 }
6330
6331 /**
6332 * @brief FIFO mode selection.[set]
6333 *
6334 * @param ctx read / write interface definitions
6335 * @param val change the values of fifo_mode in reg FIFO_CTRL4
6336 * @retval interface status (MANDATORY: return 0 -> no Error)
6337 *
6338 */
lsm6dso_fifo_mode_set(const stmdev_ctx_t * ctx,lsm6dso_fifo_mode_t val)6339 int32_t lsm6dso_fifo_mode_set(const stmdev_ctx_t *ctx,
6340 lsm6dso_fifo_mode_t val)
6341 {
6342 lsm6dso_fifo_ctrl4_t reg;
6343 int32_t ret;
6344
6345 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
6346
6347 if (ret == 0)
6348 {
6349 reg.fifo_mode = (uint8_t)val;
6350 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
6351 }
6352
6353 return ret;
6354 }
6355
6356 /**
6357 * @brief FIFO mode selection.[get]
6358 *
6359 * @param ctx read / write interface definitions
6360 * @param val Get the values of fifo_mode in reg FIFO_CTRL4
6361 * @retval interface status (MANDATORY: return 0 -> no Error)
6362 *
6363 */
lsm6dso_fifo_mode_get(const stmdev_ctx_t * ctx,lsm6dso_fifo_mode_t * val)6364 int32_t lsm6dso_fifo_mode_get(const stmdev_ctx_t *ctx,
6365 lsm6dso_fifo_mode_t *val)
6366 {
6367 lsm6dso_fifo_ctrl4_t reg;
6368 int32_t ret;
6369
6370 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
6371
6372 switch (reg.fifo_mode)
6373 {
6374 case LSM6DSO_BYPASS_MODE:
6375 *val = LSM6DSO_BYPASS_MODE;
6376 break;
6377
6378 case LSM6DSO_FIFO_MODE:
6379 *val = LSM6DSO_FIFO_MODE;
6380 break;
6381
6382 case LSM6DSO_STREAM_TO_FIFO_MODE:
6383 *val = LSM6DSO_STREAM_TO_FIFO_MODE;
6384 break;
6385
6386 case LSM6DSO_BYPASS_TO_STREAM_MODE:
6387 *val = LSM6DSO_BYPASS_TO_STREAM_MODE;
6388 break;
6389
6390 case LSM6DSO_STREAM_MODE:
6391 *val = LSM6DSO_STREAM_MODE;
6392 break;
6393
6394 case LSM6DSO_BYPASS_TO_FIFO_MODE:
6395 *val = LSM6DSO_BYPASS_TO_FIFO_MODE;
6396 break;
6397
6398 default:
6399 *val = LSM6DSO_BYPASS_MODE;
6400 break;
6401 }
6402
6403 return ret;
6404 }
6405
6406 /**
6407 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6408 * for temperature data.[set]
6409 *
6410 * @param ctx read / write interface definitions
6411 * @param val change the values of odr_t_batch in reg FIFO_CTRL4
6412 * @retval interface status (MANDATORY: return 0 -> no Error)
6413 *
6414 */
lsm6dso_fifo_temp_batch_set(const stmdev_ctx_t * ctx,lsm6dso_odr_t_batch_t val)6415 int32_t lsm6dso_fifo_temp_batch_set(const stmdev_ctx_t *ctx,
6416 lsm6dso_odr_t_batch_t val)
6417 {
6418 lsm6dso_fifo_ctrl4_t reg;
6419 int32_t ret;
6420
6421 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
6422
6423 if (ret == 0)
6424 {
6425 reg.odr_t_batch = (uint8_t)val;
6426 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
6427 }
6428
6429 return ret;
6430 }
6431
6432 /**
6433 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6434 * for temperature data.[get]
6435 *
6436 * @param ctx read / write interface definitions
6437 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4
6438 * @retval interface status (MANDATORY: return 0 -> no Error)
6439 *
6440 */
lsm6dso_fifo_temp_batch_get(const stmdev_ctx_t * ctx,lsm6dso_odr_t_batch_t * val)6441 int32_t lsm6dso_fifo_temp_batch_get(const stmdev_ctx_t *ctx,
6442 lsm6dso_odr_t_batch_t *val)
6443 {
6444 lsm6dso_fifo_ctrl4_t reg;
6445 int32_t ret;
6446
6447 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
6448
6449 switch (reg.odr_t_batch)
6450 {
6451 case LSM6DSO_TEMP_NOT_BATCHED:
6452 *val = LSM6DSO_TEMP_NOT_BATCHED;
6453 break;
6454
6455 case LSM6DSO_TEMP_BATCHED_AT_1Hz6:
6456 *val = LSM6DSO_TEMP_BATCHED_AT_1Hz6;
6457 break;
6458
6459 case LSM6DSO_TEMP_BATCHED_AT_12Hz5:
6460 *val = LSM6DSO_TEMP_BATCHED_AT_12Hz5;
6461 break;
6462
6463 case LSM6DSO_TEMP_BATCHED_AT_52Hz:
6464 *val = LSM6DSO_TEMP_BATCHED_AT_52Hz;
6465 break;
6466
6467 default:
6468 *val = LSM6DSO_TEMP_NOT_BATCHED;
6469 break;
6470 }
6471
6472 return ret;
6473 }
6474
6475 /**
6476 * @brief Selects decimation for timestamp batching in FIFO.
6477 * Writing rate will be the maximum rate between XL and
6478 * GYRO BDR divided by decimation decoder.[set]
6479 *
6480 * @param ctx read / write interface definitions
6481 * @param val change the values of odr_ts_batch in reg FIFO_CTRL4
6482 * @retval interface status (MANDATORY: return 0 -> no Error)
6483 *
6484 */
lsm6dso_fifo_timestamp_decimation_set(const stmdev_ctx_t * ctx,lsm6dso_odr_ts_batch_t val)6485 int32_t lsm6dso_fifo_timestamp_decimation_set(const stmdev_ctx_t *ctx,
6486 lsm6dso_odr_ts_batch_t val)
6487 {
6488 lsm6dso_fifo_ctrl4_t reg;
6489 int32_t ret;
6490
6491 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
6492
6493 if (ret == 0)
6494 {
6495 reg.odr_ts_batch = (uint8_t)val;
6496 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
6497 }
6498
6499 return ret;
6500 }
6501
6502 /**
6503 * @brief Selects decimation for timestamp batching in FIFO.
6504 * Writing rate will be the maximum rate between XL and
6505 * GYRO BDR divided by decimation decoder.[get]
6506 *
6507 * @param ctx read / write interface definitions
6508 * @param val Get the values of odr_ts_batch in reg FIFO_CTRL4
6509 * @retval interface status (MANDATORY: return 0 -> no Error)
6510 *
6511 */
lsm6dso_fifo_timestamp_decimation_get(const stmdev_ctx_t * ctx,lsm6dso_odr_ts_batch_t * val)6512 int32_t lsm6dso_fifo_timestamp_decimation_get(const stmdev_ctx_t *ctx,
6513 lsm6dso_odr_ts_batch_t *val)
6514 {
6515 lsm6dso_fifo_ctrl4_t reg;
6516 int32_t ret;
6517
6518 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
6519
6520 switch (reg.odr_ts_batch)
6521 {
6522 case LSM6DSO_NO_DECIMATION:
6523 *val = LSM6DSO_NO_DECIMATION;
6524 break;
6525
6526 case LSM6DSO_DEC_1:
6527 *val = LSM6DSO_DEC_1;
6528 break;
6529
6530 case LSM6DSO_DEC_8:
6531 *val = LSM6DSO_DEC_8;
6532 break;
6533
6534 case LSM6DSO_DEC_32:
6535 *val = LSM6DSO_DEC_32;
6536 break;
6537
6538 default:
6539 *val = LSM6DSO_NO_DECIMATION;
6540 break;
6541 }
6542
6543 return ret;
6544 }
6545
6546 /**
6547 * @brief Selects the trigger for the internal counter of batching events
6548 * between XL and gyro.[set]
6549 *
6550 * @param ctx read / write interface definitions
6551 * @param val change the values of trig_counter_bdr
6552 * in reg COUNTER_BDR_REG1
6553 * @retval interface status (MANDATORY: return 0 -> no Error)
6554 *
6555 */
lsm6dso_fifo_cnt_event_batch_set(const stmdev_ctx_t * ctx,lsm6dso_trig_counter_bdr_t val)6556 int32_t lsm6dso_fifo_cnt_event_batch_set(const stmdev_ctx_t *ctx,
6557 lsm6dso_trig_counter_bdr_t val)
6558 {
6559 lsm6dso_counter_bdr_reg1_t reg;
6560 int32_t ret;
6561
6562 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1);
6563
6564 if (ret == 0)
6565 {
6566 reg.trig_counter_bdr = (uint8_t)val;
6567 ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
6568 (uint8_t *)®, 1);
6569 }
6570
6571 return ret;
6572 }
6573
6574 /**
6575 * @brief Selects the trigger for the internal counter of batching events
6576 * between XL and gyro.[get]
6577 *
6578 * @param ctx read / write interface definitions
6579 * @param val Get the values of trig_counter_bdr
6580 * in reg COUNTER_BDR_REG1
6581 * @retval interface status (MANDATORY: return 0 -> no Error)
6582 *
6583 */
lsm6dso_fifo_cnt_event_batch_get(const stmdev_ctx_t * ctx,lsm6dso_trig_counter_bdr_t * val)6584 int32_t lsm6dso_fifo_cnt_event_batch_get(const stmdev_ctx_t *ctx,
6585 lsm6dso_trig_counter_bdr_t *val)
6586 {
6587 lsm6dso_counter_bdr_reg1_t reg;
6588 int32_t ret;
6589
6590 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1);
6591
6592 switch (reg.trig_counter_bdr)
6593 {
6594 case LSM6DSO_XL_BATCH_EVENT:
6595 *val = LSM6DSO_XL_BATCH_EVENT;
6596 break;
6597
6598 case LSM6DSO_GYRO_BATCH_EVENT:
6599 *val = LSM6DSO_GYRO_BATCH_EVENT;
6600 break;
6601
6602 default:
6603 *val = LSM6DSO_XL_BATCH_EVENT;
6604 break;
6605 }
6606
6607 return ret;
6608 }
6609
6610 /**
6611 * @brief Resets the internal counter of batching vents for a single sensor.
6612 * This bit is automatically reset to zero if it was set to '1'.[set]
6613 *
6614 * @param ctx read / write interface definitions
6615 * @param val change the values of rst_counter_bdr in
6616 * reg COUNTER_BDR_REG1
6617 * @retval interface status (MANDATORY: return 0 -> no Error)
6618 *
6619 */
lsm6dso_rst_batch_counter_set(const stmdev_ctx_t * ctx,uint8_t val)6620 int32_t lsm6dso_rst_batch_counter_set(const stmdev_ctx_t *ctx, uint8_t val)
6621 {
6622 lsm6dso_counter_bdr_reg1_t reg;
6623 int32_t ret;
6624
6625 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1);
6626
6627 if (ret == 0)
6628 {
6629 reg.rst_counter_bdr = val;
6630 ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
6631 (uint8_t *)®, 1);
6632 }
6633
6634 return ret;
6635 }
6636
6637 /**
6638 * @brief Resets the internal counter of batching events for a single sensor.
6639 * This bit is automatically reset to zero if it was set to '1'.[get]
6640 *
6641 * @param ctx read / write interface definitions
6642 * @param val Get the values of rst_counter_bdr in
6643 * reg COUNTER_BDR_REG1
6644 * @retval interface status (MANDATORY: return 0 -> no Error)
6645 *
6646 */
lsm6dso_rst_batch_counter_get(const stmdev_ctx_t * ctx,uint8_t * val)6647 int32_t lsm6dso_rst_batch_counter_get(const stmdev_ctx_t *ctx, uint8_t *val)
6648 {
6649 lsm6dso_counter_bdr_reg1_t reg;
6650 int32_t ret;
6651
6652 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1);
6653 *val = reg.rst_counter_bdr;
6654
6655 return ret;
6656 }
6657
6658 /**
6659 * @brief Batch data rate counter.[set]
6660 *
6661 * @param ctx read / write interface definitions
6662 * @param val change the values of cnt_bdr_th in
6663 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
6664 * @retval interface status (MANDATORY: return 0 -> no Error)
6665 *
6666 */
lsm6dso_batch_counter_threshold_set(const stmdev_ctx_t * ctx,uint16_t val)6667 int32_t lsm6dso_batch_counter_threshold_set(const stmdev_ctx_t *ctx,
6668 uint16_t val)
6669 {
6670 lsm6dso_counter_bdr_reg1_t counter_bdr_reg1;
6671 lsm6dso_counter_bdr_reg2_t counter_bdr_reg2;
6672 int32_t ret;
6673
6674 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
6675 if (ret != 0) { return ret; }
6676
6677 counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val;
6678 counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8;
6679
6680 ret += lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)&counter_bdr_reg1, 1);
6681 ret += lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG2, (uint8_t *)&counter_bdr_reg2, 1);
6682
6683 return ret;
6684 }
6685
6686 /**
6687 * @brief Batch data rate counter.[get]
6688 *
6689 * @param ctx read / write interface definitions
6690 * @param val Get the values of cnt_bdr_th in
6691 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
6692 * @retval interface status (MANDATORY: return 0 -> no Error)
6693 *
6694 */
lsm6dso_batch_counter_threshold_get(const stmdev_ctx_t * ctx,uint16_t * val)6695 int32_t lsm6dso_batch_counter_threshold_get(const stmdev_ctx_t *ctx,
6696 uint16_t *val)
6697 {
6698 lsm6dso_counter_bdr_reg1_t counter_bdr_reg1;
6699 lsm6dso_counter_bdr_reg2_t counter_bdr_reg2;
6700 int32_t ret;
6701
6702 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
6703 (uint8_t *)&counter_bdr_reg1, 1);
6704
6705 if (ret == 0)
6706 {
6707 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG2,
6708 (uint8_t *)&counter_bdr_reg2, 1);
6709 *val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8)
6710 + (uint16_t)counter_bdr_reg2.cnt_bdr_th;
6711 }
6712
6713 return ret;
6714 }
6715
6716 /**
6717 * @brief Number of unread sensor data (TAG + 6 bytes) stored in FIFO.[get]
6718 *
6719 * @param ctx Read / write interface definitions.(ptr)
6720 * @param val Read the value of diff_fifo in reg FIFO_STATUS1 and FIFO_STATUS2
6721 * @retval Interface status (MANDATORY: return 0 -> no Error).
6722 *
6723 */
lsm6dso_fifo_data_level_get(const stmdev_ctx_t * ctx,uint16_t * val)6724 int32_t lsm6dso_fifo_data_level_get(const stmdev_ctx_t *ctx,
6725 uint16_t *val)
6726 {
6727 uint8_t reg[2];
6728 lsm6dso_fifo_status1_t *fifo_status1 = (lsm6dso_fifo_status1_t *)®[0];
6729 lsm6dso_fifo_status2_t *fifo_status2 = (lsm6dso_fifo_status2_t *)®[1];
6730 int32_t ret;
6731
6732 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
6733 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS1, (uint8_t *)reg, 2);
6734 if (ret == 0)
6735 {
6736 *val = fifo_status2->diff_fifo;
6737 *val = (*val * 256U) + fifo_status1->diff_fifo;
6738 }
6739
6740 return ret;
6741 }
6742
6743 /**
6744 * @brief Smart FIFO status.[get]
6745 *
6746 * @param ctx Read / write interface definitions.(ptr)
6747 * @param val Read registers FIFO_STATUS2
6748 * @retval Interface status (MANDATORY: return 0 -> no Error).
6749 *
6750 */
lsm6dso_fifo_status_get(const stmdev_ctx_t * ctx,lsm6dso_fifo_status2_t * val)6751 int32_t lsm6dso_fifo_status_get(const stmdev_ctx_t *ctx,
6752 lsm6dso_fifo_status2_t *val)
6753 {
6754 uint8_t reg[2];
6755 lsm6dso_fifo_status2_t *fifo_status2 = (lsm6dso_fifo_status2_t *)®[1];
6756 int32_t ret;
6757
6758 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
6759 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS1, (uint8_t *)reg, 2);
6760 if (ret == 0)
6761 {
6762 *val = *fifo_status2;
6763 }
6764
6765 return ret;
6766 }
6767
6768 /**
6769 * @brief Smart FIFO full status.[get]
6770 *
6771 * @param ctx Read / write interface definitions.(ptr)
6772 * @param val Read the values of fifo_full_ia in reg FIFO_STATUS2
6773 * @retval Interface status (MANDATORY: return 0 -> no Error).
6774 *
6775 */
lsm6dso_fifo_full_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)6776 int32_t lsm6dso_fifo_full_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
6777 {
6778 uint8_t reg[2];
6779 lsm6dso_fifo_status2_t *fifo_status2 = (lsm6dso_fifo_status2_t *)®[1];
6780 int32_t ret;
6781
6782 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
6783 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS1, (uint8_t *)reg, 2);
6784 if (ret == 0)
6785 {
6786 *val = fifo_status2->fifo_full_ia;
6787 }
6788
6789 return ret;
6790 }
6791
6792 /**
6793 * @brief FIFO overrun status.[get]
6794 *
6795 * @param ctx Read / write interface definitions.(ptr)
6796 * @param val Read the values of fifo_over_run_latched in
6797 * reg FIFO_STATUS2
6798 * @retval Interface status (MANDATORY: return 0 -> no Error).
6799 *
6800 */
lsm6dso_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)6801 int32_t lsm6dso_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
6802 {
6803 uint8_t reg[2];
6804 lsm6dso_fifo_status2_t *fifo_status2 = (lsm6dso_fifo_status2_t *)®[1];
6805 int32_t ret;
6806
6807 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
6808 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS1, (uint8_t *)reg, 2);
6809 if (ret == 0)
6810 {
6811 *val = fifo_status2->fifo_ovr_ia;
6812 }
6813
6814 return ret;
6815 }
6816
6817 /**
6818 * @brief FIFO watermark status.[get]
6819 *
6820 * @param ctx Read / write interface definitions.(ptr)
6821 * @param val Read the values of fifo_wtm_ia in reg FIFO_STATUS2
6822 * @retval Interface status (MANDATORY: return 0 -> no Error).
6823 *
6824 */
lsm6dso_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)6825 int32_t lsm6dso_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
6826 {
6827 uint8_t reg[2];
6828 lsm6dso_fifo_status2_t *fifo_status2 = (lsm6dso_fifo_status2_t *)®[1];
6829 int32_t ret;
6830
6831 /* read both FIFO_STATUS1 + FIFO_STATUS2 regs */
6832 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS1, (uint8_t *)reg, 2);
6833 if (ret == 0)
6834 {
6835 *val = fifo_status2->fifo_wtm_ia;
6836 }
6837
6838 return ret;
6839 }
6840
6841 /**
6842 * @brief Identifies the sensor in FIFO_DATA_OUT.[get]
6843 *
6844 * @param ctx read / write interface definitions
6845 * @param val Get the values of tag_sensor in reg FIFO_DATA_OUT_TAG
6846 * @retval interface status (MANDATORY: return 0 -> no Error)
6847 *
6848 */
lsm6dso_fifo_sensor_tag_get(const stmdev_ctx_t * ctx,lsm6dso_fifo_tag_t * val)6849 int32_t lsm6dso_fifo_sensor_tag_get(const stmdev_ctx_t *ctx,
6850 lsm6dso_fifo_tag_t *val)
6851 {
6852 lsm6dso_fifo_data_out_tag_t reg;
6853 int32_t ret;
6854
6855 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_TAG,
6856 (uint8_t *)®, 1);
6857
6858 switch (reg.tag_sensor)
6859 {
6860 case LSM6DSO_GYRO_NC_TAG:
6861 *val = LSM6DSO_GYRO_NC_TAG;
6862 break;
6863
6864 case LSM6DSO_XL_NC_TAG:
6865 *val = LSM6DSO_XL_NC_TAG;
6866 break;
6867
6868 case LSM6DSO_TEMPERATURE_TAG:
6869 *val = LSM6DSO_TEMPERATURE_TAG;
6870 break;
6871
6872 case LSM6DSO_TIMESTAMP_TAG:
6873 *val = LSM6DSO_TIMESTAMP_TAG;
6874 break;
6875
6876 case LSM6DSO_CFG_CHANGE_TAG:
6877 *val = LSM6DSO_CFG_CHANGE_TAG;
6878 break;
6879
6880 case LSM6DSO_XL_NC_T_2_TAG:
6881 *val = LSM6DSO_XL_NC_T_2_TAG;
6882 break;
6883
6884 case LSM6DSO_XL_NC_T_1_TAG:
6885 *val = LSM6DSO_XL_NC_T_1_TAG;
6886 break;
6887
6888 case LSM6DSO_XL_2XC_TAG:
6889 *val = LSM6DSO_XL_2XC_TAG;
6890 break;
6891
6892 case LSM6DSO_XL_3XC_TAG:
6893 *val = LSM6DSO_XL_3XC_TAG;
6894 break;
6895
6896 case LSM6DSO_GYRO_NC_T_2_TAG:
6897 *val = LSM6DSO_GYRO_NC_T_2_TAG;
6898 break;
6899
6900 case LSM6DSO_GYRO_NC_T_1_TAG:
6901 *val = LSM6DSO_GYRO_NC_T_1_TAG;
6902 break;
6903
6904 case LSM6DSO_GYRO_2XC_TAG:
6905 *val = LSM6DSO_GYRO_2XC_TAG;
6906 break;
6907
6908 case LSM6DSO_GYRO_3XC_TAG:
6909 *val = LSM6DSO_GYRO_3XC_TAG;
6910 break;
6911
6912 case LSM6DSO_SENSORHUB_SLAVE0_TAG:
6913 *val = LSM6DSO_SENSORHUB_SLAVE0_TAG;
6914 break;
6915
6916 case LSM6DSO_SENSORHUB_SLAVE1_TAG:
6917 *val = LSM6DSO_SENSORHUB_SLAVE1_TAG;
6918 break;
6919
6920 case LSM6DSO_SENSORHUB_SLAVE2_TAG:
6921 *val = LSM6DSO_SENSORHUB_SLAVE2_TAG;
6922 break;
6923
6924 case LSM6DSO_SENSORHUB_SLAVE3_TAG:
6925 *val = LSM6DSO_SENSORHUB_SLAVE3_TAG;
6926 break;
6927
6928 case LSM6DSO_STEP_COUNTER_TAG:
6929 *val = LSM6DSO_STEP_COUNTER_TAG;
6930 break;
6931
6932 case LSM6DSO_GAME_ROTATION_TAG:
6933 *val = LSM6DSO_GAME_ROTATION_TAG;
6934 break;
6935
6936 case LSM6DSO_GEOMAG_ROTATION_TAG:
6937 *val = LSM6DSO_GEOMAG_ROTATION_TAG;
6938 break;
6939
6940 case LSM6DSO_ROTATION_TAG:
6941 *val = LSM6DSO_ROTATION_TAG;
6942 break;
6943
6944 case LSM6DSO_SENSORHUB_NACK_TAG:
6945 *val = LSM6DSO_SENSORHUB_NACK_TAG;
6946 break;
6947
6948 default:
6949 *val = LSM6DSO_GYRO_NC_TAG;
6950 break;
6951 }
6952
6953 return ret;
6954 }
6955
6956 /**
6957 * @brief : Enable FIFO batching of pedometer embedded
6958 * function values.[set]
6959 *
6960 * @param ctx read / write interface definitions
6961 * @param val change the values of gbias_fifo_en in
6962 * reg LSM6DSO_EMB_FUNC_FIFO_CFG
6963 * @retval interface status (MANDATORY: return 0 -> no Error)
6964 *
6965 */
lsm6dso_fifo_pedo_batch_set(const stmdev_ctx_t * ctx,uint8_t val)6966 int32_t lsm6dso_fifo_pedo_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
6967 {
6968 lsm6dso_emb_func_fifo_cfg_t reg;
6969 int32_t ret;
6970
6971 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
6972 if (ret != 0) { return ret; }
6973
6974 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG, (uint8_t *)®, 1);
6975 reg.pedo_fifo_en = val;
6976 ret += lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG, (uint8_t *)®, 1);
6977
6978 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
6979
6980 return ret;
6981 }
6982
6983 /**
6984 * @brief Enable FIFO batching of pedometer embedded function values.[get]
6985 *
6986 * @param ctx read / write interface definitions
6987 * @param val Get the values of pedo_fifo_en in
6988 * reg LSM6DSO_EMB_FUNC_FIFO_CFG
6989 * @retval interface status (MANDATORY: return 0 -> no Error)
6990 *
6991 */
lsm6dso_fifo_pedo_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)6992 int32_t lsm6dso_fifo_pedo_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
6993 {
6994 lsm6dso_emb_func_fifo_cfg_t reg;
6995 int32_t ret;
6996
6997 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
6998 if (ret != 0) { return ret; }
6999
7000 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG, (uint8_t *)®, 1);
7001 *val = reg.pedo_fifo_en;
7002
7003 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
7004
7005 return ret;
7006 }
7007
7008 /**
7009 * @brief Enable FIFO batching data of slave idx.[set]
7010 *
7011 * @param ctx read / write interface definitions
7012 * @param val Enable FIFO data batching of slave idx
7013 * @retval interface status (MANDATORY: return 0 -> no Error)
7014 *
7015 */
lsm6dso_sh_batch_slave_set(const stmdev_ctx_t * ctx,uint8_t idx,uint8_t val)7016 int32_t lsm6dso_sh_batch_slave_set(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t val)
7017 {
7018 lsm6dso_slv0_config_t reg;
7019 int32_t ret;
7020
7021 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
7022 if (ret != 0) { return ret; }
7023
7024 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG + 3U*idx, (uint8_t *)®, 1);
7025 reg.batch_ext_sens_0_en = val;
7026 ret += lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG + 3U*idx, (uint8_t *)®, 1);
7027
7028 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
7029
7030 return ret;
7031 }
7032
7033 /**
7034 * @brief Enable FIFO batching data of slave idx.[get]
7035 *
7036 * @param ctx read / write interface definitions
7037 * @param val Enable FIFO data batching of slave idx
7038 * @retval interface status (MANDATORY: return 0 -> no Error)
7039 *
7040 */
lsm6dso_sh_batch_slave_get(const stmdev_ctx_t * ctx,uint8_t idx,uint8_t * val)7041 int32_t lsm6dso_sh_batch_slave_get(const stmdev_ctx_t *ctx, uint8_t idx, uint8_t *val)
7042 {
7043 lsm6dso_slv0_config_t reg;
7044 int32_t ret;
7045
7046 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
7047 if (ret != 0) { return ret; }
7048
7049 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG + 3U*idx, (uint8_t *)®, 1);
7050 *val = reg.batch_ext_sens_0_en;
7051
7052 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
7053
7054 return ret;
7055 }
7056
7057 /**
7058 * @}
7059 *
7060 */
7061
7062 /**
7063 * @defgroup LSM6DSO_DEN_functionality
7064 * @brief This section groups all the functions concerning
7065 * DEN functionality.
7066 * @{
7067 *
7068 */
7069
7070 /**
7071 * @brief DEN functionality marking mode.[set]
7072 *
7073 * @param ctx read / write interface definitions
7074 * @param val change the values of den_mode in reg CTRL6_C
7075 * @retval interface status (MANDATORY: return 0 -> no Error)
7076 *
7077 */
lsm6dso_den_mode_set(const stmdev_ctx_t * ctx,lsm6dso_den_mode_t val)7078 int32_t lsm6dso_den_mode_set(const stmdev_ctx_t *ctx,
7079 lsm6dso_den_mode_t val)
7080 {
7081 lsm6dso_ctrl6_c_t reg;
7082 int32_t ret;
7083
7084 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
7085
7086 if (ret == 0)
7087 {
7088 reg.den_mode = (uint8_t)val;
7089 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
7090 }
7091
7092 return ret;
7093 }
7094
7095 /**
7096 * @brief DEN functionality marking mode.[get]
7097 *
7098 * @param ctx read / write interface definitions
7099 * @param val Get the values of den_mode in reg CTRL6_C
7100 * @retval interface status (MANDATORY: return 0 -> no Error)
7101 *
7102 */
lsm6dso_den_mode_get(const stmdev_ctx_t * ctx,lsm6dso_den_mode_t * val)7103 int32_t lsm6dso_den_mode_get(const stmdev_ctx_t *ctx,
7104 lsm6dso_den_mode_t *val)
7105 {
7106 lsm6dso_ctrl6_c_t reg;
7107 int32_t ret;
7108
7109 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
7110
7111 switch (reg.den_mode)
7112 {
7113 case LSM6DSO_DEN_DISABLE:
7114 *val = LSM6DSO_DEN_DISABLE;
7115 break;
7116
7117 case LSM6DSO_LEVEL_FIFO:
7118 *val = LSM6DSO_LEVEL_FIFO;
7119 break;
7120
7121 case LSM6DSO_LEVEL_LETCHED:
7122 *val = LSM6DSO_LEVEL_LETCHED;
7123 break;
7124
7125 case LSM6DSO_LEVEL_TRIGGER:
7126 *val = LSM6DSO_LEVEL_TRIGGER;
7127 break;
7128
7129 case LSM6DSO_EDGE_TRIGGER:
7130 *val = LSM6DSO_EDGE_TRIGGER;
7131 break;
7132
7133 default:
7134 *val = LSM6DSO_DEN_DISABLE;
7135 break;
7136 }
7137
7138 return ret;
7139 }
7140
7141 /**
7142 * @brief DEN active level configuration.[set]
7143 *
7144 * @param ctx read / write interface definitions
7145 * @param val change the values of den_lh in reg CTRL9_XL
7146 * @retval interface status (MANDATORY: return 0 -> no Error)
7147 *
7148 */
lsm6dso_den_polarity_set(const stmdev_ctx_t * ctx,lsm6dso_den_lh_t val)7149 int32_t lsm6dso_den_polarity_set(const stmdev_ctx_t *ctx,
7150 lsm6dso_den_lh_t val)
7151 {
7152 lsm6dso_ctrl9_xl_t reg;
7153 int32_t ret;
7154
7155 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7156
7157 if (ret == 0)
7158 {
7159 reg.den_lh = (uint8_t)val;
7160 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7161 }
7162
7163 return ret;
7164 }
7165
7166 /**
7167 * @brief DEN active level configuration.[get]
7168 *
7169 * @param ctx read / write interface definitions
7170 * @param val Get the values of den_lh in reg CTRL9_XL
7171 * @retval interface status (MANDATORY: return 0 -> no Error)
7172 *
7173 */
lsm6dso_den_polarity_get(const stmdev_ctx_t * ctx,lsm6dso_den_lh_t * val)7174 int32_t lsm6dso_den_polarity_get(const stmdev_ctx_t *ctx,
7175 lsm6dso_den_lh_t *val)
7176 {
7177 lsm6dso_ctrl9_xl_t reg;
7178 int32_t ret;
7179
7180 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7181
7182 switch (reg.den_lh)
7183 {
7184 case LSM6DSO_DEN_ACT_LOW:
7185 *val = LSM6DSO_DEN_ACT_LOW;
7186 break;
7187
7188 case LSM6DSO_DEN_ACT_HIGH:
7189 *val = LSM6DSO_DEN_ACT_HIGH;
7190 break;
7191
7192 default:
7193 *val = LSM6DSO_DEN_ACT_LOW;
7194 break;
7195 }
7196
7197 return ret;
7198 }
7199
7200 /**
7201 * @brief DEN enable.[set]
7202 *
7203 * @param ctx read / write interface definitions
7204 * @param val change the values of den_xl_g in reg CTRL9_XL
7205 * @retval interface status (MANDATORY: return 0 -> no Error)
7206 *
7207 */
lsm6dso_den_enable_set(const stmdev_ctx_t * ctx,lsm6dso_den_xl_g_t val)7208 int32_t lsm6dso_den_enable_set(const stmdev_ctx_t *ctx,
7209 lsm6dso_den_xl_g_t val)
7210 {
7211 lsm6dso_ctrl9_xl_t reg;
7212 int32_t ret;
7213
7214 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7215
7216 if (ret == 0)
7217 {
7218 reg.den_xl_g = (uint8_t)val;
7219 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7220 }
7221
7222 return ret;
7223 }
7224
7225 /**
7226 * @brief DEN enable.[get]
7227 *
7228 * @param ctx read / write interface definitions
7229 * @param val Get the values of den_xl_g in reg CTRL9_XL
7230 * @retval interface status (MANDATORY: return 0 -> no Error)
7231 *
7232 */
lsm6dso_den_enable_get(const stmdev_ctx_t * ctx,lsm6dso_den_xl_g_t * val)7233 int32_t lsm6dso_den_enable_get(const stmdev_ctx_t *ctx,
7234 lsm6dso_den_xl_g_t *val)
7235 {
7236 lsm6dso_ctrl9_xl_t reg;
7237 int32_t ret;
7238
7239 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7240
7241 switch (reg.den_xl_g)
7242 {
7243 case LSM6DSO_STAMP_IN_GY_DATA:
7244 *val = LSM6DSO_STAMP_IN_GY_DATA;
7245 break;
7246
7247 case LSM6DSO_STAMP_IN_XL_DATA:
7248 *val = LSM6DSO_STAMP_IN_XL_DATA;
7249 break;
7250
7251 case LSM6DSO_STAMP_IN_GY_XL_DATA:
7252 *val = LSM6DSO_STAMP_IN_GY_XL_DATA;
7253 break;
7254
7255 default:
7256 *val = LSM6DSO_STAMP_IN_GY_DATA;
7257 break;
7258 }
7259
7260 return ret;
7261 }
7262
7263 /**
7264 * @brief DEN value stored in LSB of X-axis.[set]
7265 *
7266 * @param ctx read / write interface definitions
7267 * @param val change the values of den_z in reg CTRL9_XL
7268 * @retval interface status (MANDATORY: return 0 -> no Error)
7269 *
7270 */
lsm6dso_den_mark_axis_x_set(const stmdev_ctx_t * ctx,uint8_t val)7271 int32_t lsm6dso_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val)
7272 {
7273 lsm6dso_ctrl9_xl_t reg;
7274 int32_t ret;
7275
7276 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7277
7278 if (ret == 0)
7279 {
7280 reg.den_z = val;
7281 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7282 }
7283
7284 return ret;
7285 }
7286
7287 /**
7288 * @brief DEN value stored in LSB of X-axis.[get]
7289 *
7290 * @param ctx read / write interface definitions
7291 * @param val Get the values of den_z in reg CTRL9_XL
7292 * @retval interface status (MANDATORY: return 0 -> no Error)
7293 *
7294 */
lsm6dso_den_mark_axis_x_get(const stmdev_ctx_t * ctx,uint8_t * val)7295 int32_t lsm6dso_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val)
7296 {
7297 lsm6dso_ctrl9_xl_t reg;
7298 int32_t ret;
7299
7300 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7301 *val = reg.den_z;
7302
7303 return ret;
7304 }
7305
7306 /**
7307 * @brief DEN value stored in LSB of Y-axis.[set]
7308 *
7309 * @param ctx read / write interface definitions
7310 * @param val change the values of den_y in reg CTRL9_XL
7311 * @retval interface status (MANDATORY: return 0 -> no Error)
7312 *
7313 */
lsm6dso_den_mark_axis_y_set(const stmdev_ctx_t * ctx,uint8_t val)7314 int32_t lsm6dso_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val)
7315 {
7316 lsm6dso_ctrl9_xl_t reg;
7317 int32_t ret;
7318
7319 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7320
7321 if (ret == 0)
7322 {
7323 reg.den_y = val;
7324 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7325 }
7326
7327 return ret;
7328 }
7329
7330 /**
7331 * @brief DEN value stored in LSB of Y-axis.[get]
7332 *
7333 * @param ctx read / write interface definitions
7334 * @param val Get the values of den_y in reg CTRL9_XL
7335 * @retval interface status (MANDATORY: return 0 -> no Error)
7336 *
7337 */
lsm6dso_den_mark_axis_y_get(const stmdev_ctx_t * ctx,uint8_t * val)7338 int32_t lsm6dso_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val)
7339 {
7340 lsm6dso_ctrl9_xl_t reg;
7341 int32_t ret;
7342
7343 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7344 *val = reg.den_y;
7345
7346 return ret;
7347 }
7348
7349 /**
7350 * @brief DEN value stored in LSB of Z-axis.[set]
7351 *
7352 * @param ctx read / write interface definitions
7353 * @param val change the values of den_x in reg CTRL9_XL
7354 * @retval interface status (MANDATORY: return 0 -> no Error)
7355 *
7356 */
lsm6dso_den_mark_axis_z_set(const stmdev_ctx_t * ctx,uint8_t val)7357 int32_t lsm6dso_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val)
7358 {
7359 lsm6dso_ctrl9_xl_t reg;
7360 int32_t ret;
7361
7362 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7363
7364 if (ret == 0)
7365 {
7366 reg.den_x = val;
7367 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7368 }
7369
7370 return ret;
7371 }
7372
7373 /**
7374 * @brief DEN value stored in LSB of Z-axis.[get]
7375 *
7376 * @param ctx read / write interface definitions
7377 * @param val Get the values of den_x in reg CTRL9_XL
7378 * @retval interface status (MANDATORY: return 0 -> no Error)
7379 *
7380 */
lsm6dso_den_mark_axis_z_get(const stmdev_ctx_t * ctx,uint8_t * val)7381 int32_t lsm6dso_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val)
7382 {
7383 lsm6dso_ctrl9_xl_t reg;
7384 int32_t ret;
7385
7386 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7387 *val = reg.den_x;
7388
7389 return ret;
7390 }
7391
7392 /**
7393 * @}
7394 *
7395 */
7396
7397 /**
7398 * @defgroup LSM6DSO_Pedometer
7399 * @brief This section groups all the functions that manage pedometer.
7400 * @{
7401 *
7402 */
7403
7404 /**
7405 * @brief Enable pedometer algorithm.[set]
7406 *
7407 * @param ctx read / write interface definitions
7408 * @param val turn on and configure pedometer
7409 * @retval interface status (MANDATORY: return 0 -> no Error)
7410 *
7411 */
lsm6dso_pedo_sens_set(const stmdev_ctx_t * ctx,lsm6dso_pedo_md_t val)7412 int32_t lsm6dso_pedo_sens_set(const stmdev_ctx_t *ctx,
7413 lsm6dso_pedo_md_t val)
7414 {
7415 lsm6dso_pedo_cmd_reg_t pedo_cmd_reg;
7416 int32_t ret;
7417
7418 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
7419 (uint8_t *)&pedo_cmd_reg);
7420
7421 if (ret == 0)
7422 {
7423 pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U) >> 4;
7424 pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U) >> 5;
7425 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_CMD_REG,
7426 (uint8_t *)&pedo_cmd_reg);
7427 }
7428
7429 return ret;
7430 }
7431
7432 /**
7433 * @brief Enable pedometer algorithm.[get]
7434 *
7435 * @param ctx read / write interface definitions
7436 * @param val turn on and configure pedometer
7437 * @retval interface status (MANDATORY: return 0 -> no Error)
7438 *
7439 */
lsm6dso_pedo_sens_get(const stmdev_ctx_t * ctx,lsm6dso_pedo_md_t * val)7440 int32_t lsm6dso_pedo_sens_get(const stmdev_ctx_t *ctx,
7441 lsm6dso_pedo_md_t *val)
7442 {
7443 lsm6dso_pedo_cmd_reg_t pedo_cmd_reg;
7444 int32_t ret;
7445
7446 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
7447 (uint8_t *)&pedo_cmd_reg);
7448
7449 switch ((pedo_cmd_reg.ad_det_en << 5) | (pedo_cmd_reg.fp_rejection_en
7450 << 4))
7451 {
7452 case LSM6DSO_PEDO_BASE_MODE:
7453 *val = LSM6DSO_PEDO_BASE_MODE;
7454 break;
7455
7456 case LSM6DSO_FALSE_STEP_REJ:
7457 *val = LSM6DSO_FALSE_STEP_REJ;
7458 break;
7459
7460 case LSM6DSO_FALSE_STEP_REJ_ADV_MODE:
7461 *val = LSM6DSO_FALSE_STEP_REJ_ADV_MODE;
7462 break;
7463
7464 default:
7465 *val = LSM6DSO_PEDO_BASE_MODE;
7466 break;
7467 }
7468
7469 return ret;
7470 }
7471
7472 /**
7473 * @brief Interrupt status bit for step detection.[get]
7474 *
7475 * @param ctx read / write interface definitions
7476 * @param val Get the values of is_step_det in reg EMB_FUNC_STATUS
7477 * @retval interface status (MANDATORY: return 0 -> no Error)
7478 *
7479 */
lsm6dso_pedo_step_detect_get(const stmdev_ctx_t * ctx,uint8_t * val)7480 int32_t lsm6dso_pedo_step_detect_get(const stmdev_ctx_t *ctx, uint8_t *val)
7481 {
7482 lsm6dso_emb_func_status_t reg;
7483 int32_t ret;
7484
7485 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
7486 if (ret != 0) { return ret; }
7487
7488 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)®, 1);
7489 *val = reg.is_step_det;
7490
7491 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
7492
7493 return ret;
7494 }
7495
7496 /**
7497 * @brief Pedometer debounce configuration register (r/w).[set]
7498 *
7499 * @param ctx read / write interface definitions
7500 * @param buff buffer that contains data to write
7501 * @retval interface status (MANDATORY: return 0 -> no Error)
7502 *
7503 */
lsm6dso_pedo_debounce_steps_set(const stmdev_ctx_t * ctx,uint8_t * buff)7504 int32_t lsm6dso_pedo_debounce_steps_set(const stmdev_ctx_t *ctx,
7505 uint8_t *buff)
7506 {
7507 int32_t ret;
7508
7509 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_DEB_STEPS_CONF,
7510 buff);
7511
7512 return ret;
7513 }
7514
7515 /**
7516 * @brief Pedometer debounce configuration register (r/w).[get]
7517 *
7518 * @param ctx read / write interface definitions
7519 * @param buff buffer that stores data read
7520 * @retval interface status (MANDATORY: return 0 -> no Error)
7521 *
7522 */
lsm6dso_pedo_debounce_steps_get(const stmdev_ctx_t * ctx,uint8_t * buff)7523 int32_t lsm6dso_pedo_debounce_steps_get(const stmdev_ctx_t *ctx,
7524 uint8_t *buff)
7525 {
7526 int32_t ret;
7527
7528 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_DEB_STEPS_CONF, buff);
7529
7530 return ret;
7531 }
7532
7533 /**
7534 * @brief Time period register for step detection on delta time (r/w).[set]
7535 *
7536 * @param ctx read / write interface definitions
7537 * @param buff buffer that contains data to write
7538 * @retval interface status (MANDATORY: return 0 -> no Error)
7539 *
7540 */
lsm6dso_pedo_steps_period_set(const stmdev_ctx_t * ctx,uint16_t val)7541 int32_t lsm6dso_pedo_steps_period_set(const stmdev_ctx_t *ctx, uint16_t val)
7542 {
7543 uint8_t buff[2];
7544 int32_t ret;
7545
7546 buff[1] = (uint8_t)(val / 256U);
7547 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7548 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L, &buff[0]);
7549 ret += lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_H, &buff[1]);
7550
7551 return ret;
7552 }
7553
7554 /**
7555 * @brief Time period register for step detection on delta time (r/w).[get]
7556 *
7557 * @param ctx read / write interface definitions
7558 * @param buff buffer that stores data read
7559 * @retval interface status (MANDATORY: return 0 -> no Error)
7560 *
7561 */
lsm6dso_pedo_steps_period_get(const stmdev_ctx_t * ctx,uint16_t * val)7562 int32_t lsm6dso_pedo_steps_period_get(const stmdev_ctx_t *ctx,
7563 uint16_t *val)
7564 {
7565 uint8_t buff[2];
7566 int32_t ret;
7567
7568 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L, &buff[0]);
7569 ret += lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_H, &buff[1]);
7570
7571 *val = buff[1];
7572 *val = (*val * 256U) + buff[0];
7573
7574 return ret;
7575 }
7576
7577 /**
7578 * @brief Set when user wants to generate interrupt on count overflow
7579 * event/every step.[set]
7580 *
7581 * @param ctx read / write interface definitions
7582 * @param val change the values of carry_count_en in reg PEDO_CMD_REG
7583 * @retval interface status (MANDATORY: return 0 -> no Error)
7584 *
7585 */
lsm6dso_pedo_int_mode_set(const stmdev_ctx_t * ctx,lsm6dso_carry_count_en_t val)7586 int32_t lsm6dso_pedo_int_mode_set(const stmdev_ctx_t *ctx,
7587 lsm6dso_carry_count_en_t val)
7588 {
7589 lsm6dso_pedo_cmd_reg_t reg;
7590 int32_t ret;
7591
7592 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
7593 (uint8_t *)®);
7594
7595 if (ret == 0)
7596 {
7597 reg.carry_count_en = (uint8_t)val;
7598 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_CMD_REG,
7599 (uint8_t *)®);
7600 }
7601
7602 return ret;
7603 }
7604
7605 /**
7606 * @brief Set when user wants to generate interrupt on count overflow
7607 * event/every step.[get]
7608 *
7609 * @param ctx read / write interface definitions
7610 * @param val Get the values of carry_count_en in reg PEDO_CMD_REG
7611 * @retval interface status (MANDATORY: return 0 -> no Error)
7612 *
7613 */
lsm6dso_pedo_int_mode_get(const stmdev_ctx_t * ctx,lsm6dso_carry_count_en_t * val)7614 int32_t lsm6dso_pedo_int_mode_get(const stmdev_ctx_t *ctx,
7615 lsm6dso_carry_count_en_t *val)
7616 {
7617 lsm6dso_pedo_cmd_reg_t reg;
7618 int32_t ret;
7619
7620 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
7621 (uint8_t *)®);
7622
7623 switch (reg.carry_count_en)
7624 {
7625 case LSM6DSO_EVERY_STEP:
7626 *val = LSM6DSO_EVERY_STEP;
7627 break;
7628
7629 case LSM6DSO_COUNT_OVERFLOW:
7630 *val = LSM6DSO_COUNT_OVERFLOW;
7631 break;
7632
7633 default:
7634 *val = LSM6DSO_EVERY_STEP;
7635 break;
7636 }
7637
7638 return ret;
7639 }
7640
7641 /**
7642 * @}
7643 *
7644 */
7645
7646 /**
7647 * @defgroup LSM6DSO_significant_motion
7648 * @brief This section groups all the functions that manage the
7649 * significant motion detection.
7650 * @{
7651 *
7652 */
7653
7654 /**
7655 * @brief Interrupt status bit for significant motion detection.[get]
7656 *
7657 * @param ctx read / write interface definitions
7658 * @param val Get the values of is_sigmot in reg EMB_FUNC_STATUS
7659 * @retval interface status (MANDATORY: return 0 -> no Error)
7660 *
7661 */
lsm6dso_motion_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)7662 int32_t lsm6dso_motion_flag_data_ready_get(const stmdev_ctx_t *ctx,
7663 uint8_t *val)
7664 {
7665 lsm6dso_emb_func_status_t reg;
7666 int32_t ret;
7667
7668 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
7669 if (ret != 0) { return ret; }
7670
7671 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)®, 1);
7672 *val = reg.is_sigmot;
7673
7674 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
7675
7676 return ret;
7677 }
7678
7679 /**
7680 * @}
7681 *
7682 */
7683
7684 /**
7685 * @defgroup LSM6DSO_tilt_detection
7686 * @brief This section groups all the functions that manage the tilt
7687 * event detection.
7688 * @{
7689 *
7690 */
7691
7692 /**
7693 * @brief Interrupt status bit for tilt detection.[get]
7694 *
7695 * @param ctx read / write interface definitions
7696 * @param val Get the values of is_tilt in reg EMB_FUNC_STATUS
7697 * @retval interface status (MANDATORY: return 0 -> no Error)
7698 *
7699 */
lsm6dso_tilt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)7700 int32_t lsm6dso_tilt_flag_data_ready_get(const stmdev_ctx_t *ctx,
7701 uint8_t *val)
7702 {
7703 lsm6dso_emb_func_status_t reg;
7704 int32_t ret;
7705
7706 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
7707 if (ret != 0) { return ret; }
7708
7709 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)®, 1);
7710 *val = reg.is_tilt;
7711
7712 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
7713
7714 return ret;
7715 }
7716
7717 /**
7718 * @}
7719 *
7720 */
7721
7722 /**
7723 * @defgroup LSM6DSO_ magnetometer_sensor
7724 * @brief This section groups all the functions that manage additional
7725 * magnetometer sensor.
7726 * @{
7727 *
7728 */
7729
7730 /**
7731 * @brief External magnetometer sensitivity value register.[set]
7732 *
7733 * @param ctx read / write interface definitions
7734 * @param buff buffer that contains data to write
7735 * @retval interface status (MANDATORY: return 0 -> no Error)
7736 *
7737 */
lsm6dso_mag_sensitivity_set(const stmdev_ctx_t * ctx,uint16_t val)7738 int32_t lsm6dso_mag_sensitivity_set(const stmdev_ctx_t *ctx, uint16_t val)
7739 {
7740 uint8_t buff[2];
7741 int32_t ret;
7742
7743 buff[1] = (uint8_t)(val / 256U);
7744 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7745
7746 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SENSITIVITY_L, &buff[0]);
7747 ret += lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SENSITIVITY_H, &buff[1]);
7748
7749 return ret;
7750 }
7751
7752 /**
7753 * @brief External magnetometer sensitivity value register.[get]
7754 *
7755 * @param ctx read / write interface definitions
7756 * @param buff buffer that stores data read
7757 * @retval interface status (MANDATORY: return 0 -> no Error)
7758 *
7759 */
lsm6dso_mag_sensitivity_get(const stmdev_ctx_t * ctx,uint16_t * val)7760 int32_t lsm6dso_mag_sensitivity_get(const stmdev_ctx_t *ctx, uint16_t *val)
7761 {
7762 uint8_t buff[2];
7763 int32_t ret;
7764
7765 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SENSITIVITY_L, &buff[0]);
7766 ret += lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SENSITIVITY_H, &buff[1]);
7767
7768 *val = buff[1];
7769 *val = (*val * 256U) + buff[0];
7770
7771 return ret;
7772 }
7773
7774 /**
7775 * @brief Offset for hard-iron compensation register (r/w).[set]
7776 *
7777 * @param ctx read / write interface definitions
7778 * @param buff buffer that contains data to write
7779 * @retval interface status (MANDATORY: return 0 -> no Error)
7780 *
7781 */
lsm6dso_mag_offset_set(const stmdev_ctx_t * ctx,int16_t * val)7782 int32_t lsm6dso_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val)
7783 {
7784 uint8_t buff[6];
7785
7786 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
7787 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
7788 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
7789 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
7790 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
7791 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
7792
7793 return lsm6dso_ln_pg_write(ctx, LSM6DSO_MAG_OFFX_L, &buff[0], 6);
7794 }
7795
7796 /**
7797 * @brief Offset for hard-iron compensation register (r/w).[get]
7798 *
7799 * @param ctx read / write interface definitions
7800 * @param buff buffer that stores data read
7801 * @retval interface status (MANDATORY: return 0 -> no Error)
7802 *
7803 */
lsm6dso_mag_offset_get(const stmdev_ctx_t * ctx,int16_t * val)7804 int32_t lsm6dso_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
7805 {
7806 uint8_t buff[6];
7807 int32_t ret;
7808
7809 ret = lsm6dso_ln_pg_read(ctx, LSM6DSO_MAG_OFFX_L, &buff[0], 6);
7810
7811 val[0] = (int16_t)buff[1];
7812 val[0] = (val[0] * 256) + (int16_t)buff[0];
7813 val[1] = (int16_t)buff[3];
7814 val[1] = (val[1] * 256) + (int16_t)buff[2];
7815 val[2] = (int16_t)buff[5];
7816 val[2] = (val[2] * 256) + (int16_t)buff[4];
7817
7818 return ret;
7819 }
7820
7821 /**
7822 * @brief Soft-iron (3x3 symmetric) matrix correction
7823 * register (r/w). The value is expressed as
7824 * half-precision floating-point format:
7825 * SEEEEEFFFFFFFFFF
7826 * S: 1 sign bit;
7827 * E: 5 exponent bits;
7828 * F: 10 fraction bits).[set]
7829 *
7830 * @param ctx read / write interface definitions
7831 * @param buff buffer that contains data to write
7832 * @retval interface status (MANDATORY: return 0 -> no Error)
7833 *
7834 */
lsm6dso_mag_soft_iron_set(const stmdev_ctx_t * ctx,int16_t * val)7835 int32_t lsm6dso_mag_soft_iron_set(const stmdev_ctx_t *ctx, int16_t *val)
7836 {
7837 uint8_t buff[12];
7838
7839 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
7840 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
7841 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
7842 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
7843 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
7844 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
7845 buff[7] = (uint8_t)((uint16_t)val[3] / 256U);
7846 buff[6] = (uint8_t)((uint16_t)val[3] - (buff[7] * 256U));
7847 buff[9] = (uint8_t)((uint16_t)val[4] / 256U);
7848 buff[8] = (uint8_t)((uint16_t)val[4] - (buff[9] * 256U));
7849 buff[11] = (uint8_t)((uint16_t)val[5] / 256U);
7850 buff[10] = (uint8_t)((uint16_t)val[5] - (buff[11] * 256U));
7851
7852 return lsm6dso_ln_pg_write(ctx, LSM6DSO_MAG_SI_XX_L, &buff[0], 12);
7853 }
7854
7855 /**
7856 * @brief Soft-iron (3x3 symmetric) matrix
7857 * correction register (r/w).
7858 * The value is expressed as half-precision
7859 * floating-point format:
7860 * SEEEEEFFFFFFFFFF
7861 * S: 1 sign bit;
7862 * E: 5 exponent bits;
7863 * F: 10 fraction bits.[get]
7864 *
7865 * @param ctx read / write interface definitions
7866 * @param buff buffer that stores data read
7867 * @retval interface status (MANDATORY: return 0 -> no Error)
7868 *
7869 */
lsm6dso_mag_soft_iron_get(const stmdev_ctx_t * ctx,int16_t * val)7870 int32_t lsm6dso_mag_soft_iron_get(const stmdev_ctx_t *ctx, int16_t *val)
7871 {
7872 uint8_t buff[12];
7873 int32_t ret;
7874
7875 ret = lsm6dso_ln_pg_read(ctx, LSM6DSO_MAG_SI_XX_L, &buff[0], 12);
7876
7877 val[0] = (int16_t)buff[1];
7878 val[0] = (val[0] * 256) + (int16_t)buff[0];
7879 val[1] = (int16_t)buff[3];
7880 val[1] = (val[1] * 256) + (int16_t)buff[2];
7881 val[2] = (int16_t)buff[5];
7882 val[2] = (val[2] * 256) + (int16_t)buff[4];
7883 val[3] = (int16_t)buff[7];
7884 val[3] = (val[3] * 256) + (int16_t)buff[6];
7885 val[4] = (int16_t)buff[9];
7886 val[4] = (val[4] * 256) + (int16_t)buff[8];
7887 val[5] = (int16_t)buff[11];
7888 val[5] = (val[5] * 256) + (int16_t)buff[10];
7889
7890 return ret;
7891 }
7892
7893 /**
7894 * @brief Magnetometer Z-axis coordinates
7895 * rotation (to be aligned to
7896 * accelerometer/gyroscope axes
7897 * orientation).[set]
7898 *
7899 * @param ctx read / write interface definitions
7900 * @param val change the values of mag_z_axis in reg MAG_CFG_A
7901 * @retval interface status (MANDATORY: return 0 -> no Error)
7902 *
7903 */
lsm6dso_mag_z_orient_set(const stmdev_ctx_t * ctx,lsm6dso_mag_z_axis_t val)7904 int32_t lsm6dso_mag_z_orient_set(const stmdev_ctx_t *ctx,
7905 lsm6dso_mag_z_axis_t val)
7906 {
7907 lsm6dso_mag_cfg_a_t reg;
7908 int32_t ret;
7909
7910 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t *)®);
7911
7912 if (ret == 0)
7913 {
7914 reg.mag_z_axis = (uint8_t) val;
7915 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t *)®);
7916 }
7917
7918 return ret;
7919 }
7920
7921 /**
7922 * @brief Magnetometer Z-axis coordinates
7923 * rotation (to be aligned to
7924 * accelerometer/gyroscope axes
7925 * orientation).[get]
7926 *
7927 * @param ctx read / write interface definitions
7928 * @param val Get the values of mag_z_axis in reg MAG_CFG_A
7929 * @retval interface status (MANDATORY: return 0 -> no Error)
7930 *
7931 */
lsm6dso_mag_z_orient_get(const stmdev_ctx_t * ctx,lsm6dso_mag_z_axis_t * val)7932 int32_t lsm6dso_mag_z_orient_get(const stmdev_ctx_t *ctx,
7933 lsm6dso_mag_z_axis_t *val)
7934 {
7935 lsm6dso_mag_cfg_a_t reg;
7936 int32_t ret;
7937
7938 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A,
7939 (uint8_t *)®);
7940
7941 switch (reg.mag_z_axis)
7942 {
7943 case LSM6DSO_Z_EQ_Y:
7944 *val = LSM6DSO_Z_EQ_Y;
7945 break;
7946
7947 case LSM6DSO_Z_EQ_MIN_Y:
7948 *val = LSM6DSO_Z_EQ_MIN_Y;
7949 break;
7950
7951 case LSM6DSO_Z_EQ_X:
7952 *val = LSM6DSO_Z_EQ_X;
7953 break;
7954
7955 case LSM6DSO_Z_EQ_MIN_X:
7956 *val = LSM6DSO_Z_EQ_MIN_X;
7957 break;
7958
7959 case LSM6DSO_Z_EQ_MIN_Z:
7960 *val = LSM6DSO_Z_EQ_MIN_Z;
7961 break;
7962
7963 case LSM6DSO_Z_EQ_Z:
7964 *val = LSM6DSO_Z_EQ_Z;
7965 break;
7966
7967 default:
7968 *val = LSM6DSO_Z_EQ_Y;
7969 break;
7970 }
7971
7972 return ret;
7973 }
7974
7975 /**
7976 * @brief Magnetometer Y-axis coordinates
7977 * rotation (to be aligned to
7978 * accelerometer/gyroscope axes
7979 * orientation).[set]
7980 *
7981 * @param ctx read / write interface definitions
7982 * @param val change the values of mag_y_axis in reg MAG_CFG_A
7983 * @retval interface status (MANDATORY: return 0 -> no Error)
7984 *
7985 */
lsm6dso_mag_y_orient_set(const stmdev_ctx_t * ctx,lsm6dso_mag_y_axis_t val)7986 int32_t lsm6dso_mag_y_orient_set(const stmdev_ctx_t *ctx,
7987 lsm6dso_mag_y_axis_t val)
7988 {
7989 lsm6dso_mag_cfg_a_t reg;
7990 int32_t ret;
7991
7992 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t *)®);
7993
7994 if (ret == 0)
7995 {
7996 reg.mag_y_axis = (uint8_t)val;
7997 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A, (uint8_t *) ®);
7998 }
7999
8000 return ret;
8001 }
8002
8003 /**
8004 * @brief Magnetometer Y-axis coordinates
8005 * rotation (to be aligned to
8006 * accelerometer/gyroscope axes
8007 * orientation).[get]
8008 *
8009 * @param ctx read / write interface definitions
8010 * @param val Get the values of mag_y_axis in reg MAG_CFG_A
8011 * @retval interface status (MANDATORY: return 0 -> no Error)
8012 *
8013 */
lsm6dso_mag_y_orient_get(const stmdev_ctx_t * ctx,lsm6dso_mag_y_axis_t * val)8014 int32_t lsm6dso_mag_y_orient_get(const stmdev_ctx_t *ctx,
8015 lsm6dso_mag_y_axis_t *val)
8016 {
8017 lsm6dso_mag_cfg_a_t reg;
8018 int32_t ret;
8019
8020 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A,
8021 (uint8_t *)®);
8022
8023 switch (reg.mag_y_axis)
8024 {
8025 case LSM6DSO_Y_EQ_Y:
8026 *val = LSM6DSO_Y_EQ_Y;
8027 break;
8028
8029 case LSM6DSO_Y_EQ_MIN_Y:
8030 *val = LSM6DSO_Y_EQ_MIN_Y;
8031 break;
8032
8033 case LSM6DSO_Y_EQ_X:
8034 *val = LSM6DSO_Y_EQ_X;
8035 break;
8036
8037 case LSM6DSO_Y_EQ_MIN_X:
8038 *val = LSM6DSO_Y_EQ_MIN_X;
8039 break;
8040
8041 case LSM6DSO_Y_EQ_MIN_Z:
8042 *val = LSM6DSO_Y_EQ_MIN_Z;
8043 break;
8044
8045 case LSM6DSO_Y_EQ_Z:
8046 *val = LSM6DSO_Y_EQ_Z;
8047 break;
8048
8049 default:
8050 *val = LSM6DSO_Y_EQ_Y;
8051 break;
8052 }
8053
8054 return ret;
8055 }
8056
8057 /**
8058 * @brief Magnetometer X-axis coordinates
8059 * rotation (to be aligned to
8060 * accelerometer/gyroscope axes
8061 * orientation).[set]
8062 *
8063 * @param ctx read / write interface definitions
8064 * @param val change the values of mag_x_axis in reg MAG_CFG_B
8065 * @retval interface status (MANDATORY: return 0 -> no Error)
8066 *
8067 */
lsm6dso_mag_x_orient_set(const stmdev_ctx_t * ctx,lsm6dso_mag_x_axis_t val)8068 int32_t lsm6dso_mag_x_orient_set(const stmdev_ctx_t *ctx,
8069 lsm6dso_mag_x_axis_t val)
8070 {
8071 lsm6dso_mag_cfg_b_t reg;
8072 int32_t ret;
8073
8074 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t *)®);
8075
8076 if (ret == 0)
8077 {
8078 reg.mag_x_axis = (uint8_t)val;
8079 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_B, (uint8_t *)®);
8080 }
8081
8082 return ret;
8083 }
8084
8085 /**
8086 * @brief Magnetometer X-axis coordinates
8087 * rotation (to be aligned to
8088 * accelerometer/gyroscope axes
8089 * orientation).[get]
8090 *
8091 * @param ctx read / write interface definitions
8092 * @param val Get the values of mag_x_axis in reg MAG_CFG_B
8093 * @retval interface status (MANDATORY: return 0 -> no Error)
8094 *
8095 */
lsm6dso_mag_x_orient_get(const stmdev_ctx_t * ctx,lsm6dso_mag_x_axis_t * val)8096 int32_t lsm6dso_mag_x_orient_get(const stmdev_ctx_t *ctx,
8097 lsm6dso_mag_x_axis_t *val)
8098 {
8099 lsm6dso_mag_cfg_b_t reg;
8100 int32_t ret;
8101
8102 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B,
8103 (uint8_t *)®);
8104
8105 switch (reg.mag_x_axis)
8106 {
8107 case LSM6DSO_X_EQ_Y:
8108 *val = LSM6DSO_X_EQ_Y;
8109 break;
8110
8111 case LSM6DSO_X_EQ_MIN_Y:
8112 *val = LSM6DSO_X_EQ_MIN_Y;
8113 break;
8114
8115 case LSM6DSO_X_EQ_X:
8116 *val = LSM6DSO_X_EQ_X;
8117 break;
8118
8119 case LSM6DSO_X_EQ_MIN_X:
8120 *val = LSM6DSO_X_EQ_MIN_X;
8121 break;
8122
8123 case LSM6DSO_X_EQ_MIN_Z:
8124 *val = LSM6DSO_X_EQ_MIN_Z;
8125 break;
8126
8127 case LSM6DSO_X_EQ_Z:
8128 *val = LSM6DSO_X_EQ_Z;
8129 break;
8130
8131 default:
8132 *val = LSM6DSO_X_EQ_Y;
8133 break;
8134 }
8135
8136 return ret;
8137 }
8138
8139 /**
8140 * @}
8141 *
8142 */
8143
8144 /**
8145 * @defgroup LSM6DSO_finite_state_machine
8146 * @brief This section groups all the functions that manage the
8147 * state_machine.
8148 * @{
8149 *
8150 */
8151
8152 /**
8153 * @brief Interrupt status bit for FSM long counter
8154 * timeout interrupt event.[get]
8155 *
8156 * @param ctx read / write interface definitions
8157 * @param val Get the values of is_fsm_lc in reg EMB_FUNC_STATUS
8158 * @retval interface status (MANDATORY: return 0 -> no Error)
8159 *
8160 */
lsm6dso_long_cnt_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)8161 int32_t lsm6dso_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx,
8162 uint8_t *val)
8163 {
8164 lsm6dso_emb_func_status_t reg;
8165 int32_t ret;
8166
8167 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8168 if (ret != 0) { return ret; }
8169
8170 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)®, 1);
8171 *val = reg.is_fsm_lc;
8172
8173 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8174
8175 return ret;
8176 }
8177
8178 /**
8179 * @brief Final State Machine enable.[set]
8180 *
8181 * @param ctx read / write interface definitions
8182 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
8183 * @retval interface status (MANDATORY: return 0 -> no Error)
8184 *
8185 */
lsm6dso_fsm_enable_set(const stmdev_ctx_t * ctx,lsm6dso_emb_fsm_enable_t * val)8186 int32_t lsm6dso_fsm_enable_set(const stmdev_ctx_t *ctx,
8187 lsm6dso_emb_fsm_enable_t *val)
8188 {
8189 int32_t ret;
8190
8191 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8192 if (ret != 0) { return ret; }
8193
8194 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_A, (uint8_t *)&val->fsm_enable_a, 1);
8195 ret += lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_B, (uint8_t *)&val->fsm_enable_b, 1);
8196
8197 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8198
8199 return ret;
8200 }
8201
8202 /**
8203 * @brief Final State Machine enable.[get]
8204 *
8205 * @param ctx read / write interface definitions
8206 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
8207 * @retval interface status (MANDATORY: return 0 -> no Error)
8208 *
8209 */
lsm6dso_fsm_enable_get(const stmdev_ctx_t * ctx,lsm6dso_emb_fsm_enable_t * val)8210 int32_t lsm6dso_fsm_enable_get(const stmdev_ctx_t *ctx,
8211 lsm6dso_emb_fsm_enable_t *val)
8212 {
8213 int32_t ret;
8214
8215 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8216 ret += lsm6dso_read_reg(ctx, LSM6DSO_FSM_ENABLE_A, (uint8_t *) val, 2);
8217 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8218
8219 return ret;
8220 }
8221
8222 /**
8223 * @brief FSM long counter status register. Long counter value is an
8224 * unsigned integer value (16-bit format).[set]
8225 *
8226 * @param ctx read / write interface definitions
8227 * @param buff buffer that contains data to write
8228 * @retval interface status (MANDATORY: return 0 -> no Error)
8229 *
8230 */
lsm6dso_long_cnt_set(const stmdev_ctx_t * ctx,uint16_t val)8231 int32_t lsm6dso_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val)
8232 {
8233 uint8_t buff[2];
8234 int32_t ret;
8235
8236 buff[1] = (uint8_t)(val / 256U);
8237 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8238
8239 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8240 ret += lsm6dso_write_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_L, buff, 2);
8241 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8242
8243 return ret;
8244 }
8245
8246 /**
8247 * @brief FSM long counter status register. Long counter value is an
8248 * unsigned integer value (16-bit format).[get]
8249 *
8250 * @param ctx read / write interface definitions
8251 * @param buff buffer that stores data read
8252 * @retval interface status (MANDATORY: return 0 -> no Error)
8253 *
8254 */
lsm6dso_long_cnt_get(const stmdev_ctx_t * ctx,uint16_t * val)8255 int32_t lsm6dso_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val)
8256 {
8257 uint8_t buff[2];
8258 int32_t ret;
8259
8260 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8261 ret += lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_L, buff, 2);
8262 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8263
8264 *val = buff[1];
8265 *val = (*val * 256U) + buff[0];
8266
8267 return ret;
8268 }
8269
8270 /**
8271 * @brief Clear FSM long counter value.[set]
8272 *
8273 * @param ctx read / write interface definitions
8274 * @param val change the values of fsm_lc_clr in
8275 * reg FSM_LONG_COUNTER_CLEAR
8276 * @retval interface status (MANDATORY: return 0 -> no Error)
8277 *
8278 */
lsm6dso_long_clr_set(const stmdev_ctx_t * ctx,lsm6dso_fsm_lc_clr_t val)8279 int32_t lsm6dso_long_clr_set(const stmdev_ctx_t *ctx,
8280 lsm6dso_fsm_lc_clr_t val)
8281 {
8282 lsm6dso_fsm_long_counter_clear_t reg;
8283 int32_t ret;
8284
8285 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8286 if (ret != 0) { return ret; }
8287
8288 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR, (uint8_t *)®, 1);
8289 reg. fsm_lc_clr = (uint8_t)val;
8290 ret += lsm6dso_write_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR, (uint8_t *)®, 1);
8291
8292 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8293
8294 return ret;
8295 }
8296
8297 /**
8298 * @brief Clear FSM long counter value.[get]
8299 *
8300 * @param ctx read / write interface definitions
8301 * @param val Get the values of fsm_lc_clr in
8302 * reg FSM_LONG_COUNTER_CLEAR
8303 * @retval interface status (MANDATORY: return 0 -> no Error)
8304 *
8305 */
lsm6dso_long_clr_get(const stmdev_ctx_t * ctx,lsm6dso_fsm_lc_clr_t * val)8306 int32_t lsm6dso_long_clr_get(const stmdev_ctx_t *ctx,
8307 lsm6dso_fsm_lc_clr_t *val)
8308 {
8309 lsm6dso_fsm_long_counter_clear_t reg;
8310 int32_t ret;
8311
8312 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8313 if (ret != 0) { return ret; }
8314
8315 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR, (uint8_t *)®, 1);
8316 if (ret != 0) { goto exit; }
8317
8318 switch (reg.fsm_lc_clr)
8319 {
8320 case LSM6DSO_LC_NORMAL:
8321 *val = LSM6DSO_LC_NORMAL;
8322 break;
8323
8324 case LSM6DSO_LC_CLEAR:
8325 *val = LSM6DSO_LC_CLEAR;
8326 break;
8327
8328 case LSM6DSO_LC_CLEAR_DONE:
8329 *val = LSM6DSO_LC_CLEAR_DONE;
8330 break;
8331
8332 default:
8333 *val = LSM6DSO_LC_NORMAL;
8334 break;
8335 }
8336
8337 exit:
8338 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8339
8340 return ret;
8341 }
8342
8343 /**
8344 * @brief FSM output registers[get]
8345 *
8346 * @param ctx read / write interface definitions
8347 * @param val struct of registers from FSM_OUTS1 to FSM_OUTS16
8348 * @retval interface status (MANDATORY: return 0 -> no Error)
8349 *
8350 */
lsm6dso_fsm_out_get(const stmdev_ctx_t * ctx,lsm6dso_fsm_out_t * val)8351 int32_t lsm6dso_fsm_out_get(const stmdev_ctx_t *ctx, lsm6dso_fsm_out_t *val)
8352 {
8353 int32_t ret;
8354
8355 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8356 ret += lsm6dso_read_reg(ctx, LSM6DSO_FSM_OUTS1, (uint8_t *)val, 16);
8357 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8358
8359 return ret;
8360 }
8361
8362 /**
8363 * @brief Finite State Machine ODR configuration.[set]
8364 *
8365 * @param ctx read / write interface definitions
8366 * @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
8367 * @retval interface status (MANDATORY: return 0 -> no Error)
8368 *
8369 */
lsm6dso_fsm_data_rate_set(const stmdev_ctx_t * ctx,lsm6dso_fsm_odr_t val)8370 int32_t lsm6dso_fsm_data_rate_set(const stmdev_ctx_t *ctx,
8371 lsm6dso_fsm_odr_t val)
8372 {
8373 lsm6dso_emb_func_odr_cfg_b_t reg;
8374 int32_t ret;
8375
8376 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8377 if (ret != 0) { return ret; }
8378
8379 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B, (uint8_t *)®, 1);
8380 if (ret != 0) { goto exit; }
8381
8382 reg.not_used_01 = 3; /* set default values */
8383 reg.not_used_02 = 2; /* set default values */
8384 reg.fsm_odr = (uint8_t)val;
8385 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B, (uint8_t *)®, 1);
8386
8387 exit:
8388 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8389
8390 return ret;
8391 }
8392
8393 /**
8394 * @brief Finite State Machine ODR configuration.[get]
8395 *
8396 * @param ctx read / write interface definitions
8397 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
8398 * @retval interface status (MANDATORY: return 0 -> no Error)
8399 *
8400 */
lsm6dso_fsm_data_rate_get(const stmdev_ctx_t * ctx,lsm6dso_fsm_odr_t * val)8401 int32_t lsm6dso_fsm_data_rate_get(const stmdev_ctx_t *ctx,
8402 lsm6dso_fsm_odr_t *val)
8403 {
8404 lsm6dso_emb_func_odr_cfg_b_t reg;
8405 int32_t ret;
8406
8407 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8408 if (ret != 0) { return ret; }
8409
8410 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B, (uint8_t *)®, 1);
8411 if (ret != 0) { goto exit; }
8412
8413 switch (reg.fsm_odr)
8414 {
8415 case LSM6DSO_ODR_FSM_12Hz5:
8416 *val = LSM6DSO_ODR_FSM_12Hz5;
8417 break;
8418
8419 case LSM6DSO_ODR_FSM_26Hz:
8420 *val = LSM6DSO_ODR_FSM_26Hz;
8421 break;
8422
8423 case LSM6DSO_ODR_FSM_52Hz:
8424 *val = LSM6DSO_ODR_FSM_52Hz;
8425 break;
8426
8427 case LSM6DSO_ODR_FSM_104Hz:
8428 *val = LSM6DSO_ODR_FSM_104Hz;
8429 break;
8430
8431 default:
8432 *val = LSM6DSO_ODR_FSM_12Hz5;
8433 break;
8434 }
8435
8436 exit:
8437 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8438
8439 return ret;
8440 }
8441
8442 /**
8443 * @brief FSM initialization request.[set]
8444 *
8445 * @param ctx read / write interface definitions
8446 * @param val change the values of fsm_init in reg FSM_INIT
8447 * @retval interface status (MANDATORY: return 0 -> no Error)
8448 *
8449 */
lsm6dso_fsm_init_set(const stmdev_ctx_t * ctx,uint8_t val)8450 int32_t lsm6dso_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val)
8451 {
8452 lsm6dso_emb_func_init_b_t reg;
8453 int32_t ret;
8454
8455 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8456 if (ret != 0) { return ret; }
8457
8458 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1);
8459 if (ret != 0) { goto exit; }
8460
8461 reg.fsm_init = val;
8462 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1);
8463
8464 exit:
8465 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8466
8467 return ret;
8468 }
8469
8470 /**
8471 * @brief FSM initialization request.[get]
8472 *
8473 * @param ctx read / write interface definitions
8474 * @param val Get the values of fsm_init in reg FSM_INIT
8475 * @retval interface status (MANDATORY: return 0 -> no Error)
8476 *
8477 */
lsm6dso_fsm_init_get(const stmdev_ctx_t * ctx,uint8_t * val)8478 int32_t lsm6dso_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val)
8479 {
8480 lsm6dso_emb_func_init_b_t reg;
8481 int32_t ret;
8482
8483 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8484 if (ret != 0) { return ret; }
8485
8486 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1);
8487
8488 *val = reg.fsm_init;
8489 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8490
8491 return ret;
8492 }
8493
8494 /**
8495 * @brief FSM long counter timeout register (r/w). The long counter
8496 * timeout value is an unsigned integer value (16-bit format).
8497 * When the long counter value reached this value,
8498 * the FSM generates an interrupt.[set]
8499 *
8500 * @param ctx read / write interface definitions
8501 * @param val the value of long counter
8502 * @retval interface status (MANDATORY: return 0 -> no Error)
8503 *
8504 */
lsm6dso_long_cnt_int_value_set(const stmdev_ctx_t * ctx,uint16_t val)8505 int32_t lsm6dso_long_cnt_int_value_set(const stmdev_ctx_t *ctx,
8506 uint16_t val)
8507 {
8508 uint8_t buff[2];
8509 int32_t ret;
8510
8511 buff[1] = (uint8_t)(val / 256U);
8512 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8513
8514 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L, &buff[0]);
8515 ret += lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H, &buff[1]);
8516
8517 return ret;
8518 }
8519
8520 /**
8521 * @brief FSM long counter timeout register (r/w). The long counter
8522 * timeout value is an unsigned integer value (16-bit format).
8523 * When the long counter value reached this value,
8524 * the FSM generates an interrupt.[get]
8525 *
8526 * @param ctx read / write interface definitions
8527 * @param val buffer that stores the value of long counter
8528 * @retval interface status (MANDATORY: return 0 -> no Error)
8529 *
8530 */
lsm6dso_long_cnt_int_value_get(const stmdev_ctx_t * ctx,uint16_t * val)8531 int32_t lsm6dso_long_cnt_int_value_get(const stmdev_ctx_t *ctx,
8532 uint16_t *val)
8533 {
8534 uint8_t buff[2];
8535 int32_t ret;
8536
8537 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L, &buff[0]);
8538 ret += lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H, &buff[1]);
8539
8540 *val = buff[1];
8541 *val = (*val * 256U) + buff[0];
8542
8543 return ret;
8544 }
8545
8546 /**
8547 * @brief FSM number of programs register.[set]
8548 *
8549 * @param ctx read / write interface definitions
8550 * @param val value to write
8551 * @retval interface status (MANDATORY: return 0 -> no Error)
8552 *
8553 */
lsm6dso_fsm_number_of_programs_set(const stmdev_ctx_t * ctx,uint8_t val)8554 int32_t lsm6dso_fsm_number_of_programs_set(const stmdev_ctx_t *ctx,
8555 uint8_t val)
8556 {
8557 int32_t ret;
8558
8559 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_PROGRAMS, &val);
8560
8561 return ret;
8562 }
8563
8564 /**
8565 * @brief FSM number of programs register.[get]
8566 *
8567 * @param ctx read / write interface definitions
8568 * @param val buffer that stores data read.
8569 * @retval interface status (MANDATORY: return 0 -> no Error)
8570 *
8571 */
lsm6dso_fsm_number_of_programs_get(const stmdev_ctx_t * ctx,uint8_t * val)8572 int32_t lsm6dso_fsm_number_of_programs_get(const stmdev_ctx_t *ctx,
8573 uint8_t *val)
8574 {
8575 int32_t ret;
8576
8577 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_PROGRAMS, val);
8578
8579 return ret;
8580 }
8581
8582 /**
8583 * @brief FSM start address register (r/w).
8584 * First available address is 0x033C.[set]
8585 *
8586 * @param ctx read / write interface definitions
8587 * @param val the value of start address
8588 * @retval interface status (MANDATORY: return 0 -> no Error)
8589 *
8590 */
lsm6dso_fsm_start_address_set(const stmdev_ctx_t * ctx,uint16_t val)8591 int32_t lsm6dso_fsm_start_address_set(const stmdev_ctx_t *ctx, uint16_t val)
8592 {
8593 uint8_t buff[2];
8594 int32_t ret;
8595
8596 buff[1] = (uint8_t)(val / 256U);
8597 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8598
8599 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_L, &buff[0]);
8600 ret += lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_H, &buff[1]);
8601
8602 return ret;
8603 }
8604
8605 /**
8606 * @brief FSM start address register (r/w).
8607 * First available address is 0x033C.[get]
8608 *
8609 * @param ctx read / write interface definitions
8610 * @param val buffer the value of start address.
8611 * @retval interface status (MANDATORY: return 0 -> no Error)
8612 *
8613 */
lsm6dso_fsm_start_address_get(const stmdev_ctx_t * ctx,uint16_t * val)8614 int32_t lsm6dso_fsm_start_address_get(const stmdev_ctx_t *ctx,
8615 uint16_t *val)
8616 {
8617 uint8_t buff[2];
8618 int32_t ret;
8619
8620 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_L, &buff[0]);
8621 ret += lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_H, &buff[1]);
8622
8623 *val = buff[1];
8624 *val = (*val * 256U) + buff[0];
8625
8626 return ret;
8627 }
8628
8629 /**
8630 * @}
8631 *
8632 */
8633
8634 /**
8635 * @defgroup LSM6DSO_Sensor_hub
8636 * @brief This section groups all the functions that manage the
8637 * sensor hub.
8638 * @{
8639 *
8640 */
8641
8642 /**
8643 * @brief Sensor hub output registers.[get]
8644 *
8645 * @param ctx read / write interface definitions
8646 * @param val values read from registers SENSOR_HUB_1 to SENSOR_HUB_18
8647 * @param len number of consecutive register to read (max 18)
8648 * @retval interface status (MANDATORY: return 0 -> no Error)
8649 *
8650 */
lsm6dso_sh_read_data_raw_get(const stmdev_ctx_t * ctx,uint8_t * val,uint8_t len)8651 int32_t lsm6dso_sh_read_data_raw_get(const stmdev_ctx_t *ctx, uint8_t *val,
8652 uint8_t len)
8653 {
8654 int32_t ret;
8655
8656 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
8657 ret += lsm6dso_read_reg(ctx, LSM6DSO_SENSOR_HUB_1, (uint8_t *) val, len);
8658 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8659
8660 return ret;
8661 }
8662
8663 /**
8664 * @brief Number of external sensors to be read by the sensor hub.[set]
8665 *
8666 * @param ctx read / write interface definitions
8667 * @param val change the values of aux_sens_on in reg MASTER_CONFIG
8668 * @retval interface status (MANDATORY: return 0 -> no Error)
8669 *
8670 */
lsm6dso_sh_slave_connected_set(const stmdev_ctx_t * ctx,lsm6dso_aux_sens_on_t val)8671 int32_t lsm6dso_sh_slave_connected_set(const stmdev_ctx_t *ctx,
8672 lsm6dso_aux_sens_on_t val)
8673 {
8674 lsm6dso_master_config_t reg;
8675 int32_t ret;
8676
8677 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
8678 if (ret != 0) { return ret; }
8679
8680 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
8681 reg.aux_sens_on = (uint8_t)val;
8682 ret += lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
8683
8684 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8685
8686 return ret;
8687 }
8688
8689 /**
8690 * @brief Number of external sensors to be read by the sensor hub.[get]
8691 *
8692 * @param ctx read / write interface definitions
8693 * @param val Get the values of aux_sens_on in reg MASTER_CONFIG
8694 * @retval interface status (MANDATORY: return 0 -> no Error)
8695 *
8696 */
lsm6dso_sh_slave_connected_get(const stmdev_ctx_t * ctx,lsm6dso_aux_sens_on_t * val)8697 int32_t lsm6dso_sh_slave_connected_get(const stmdev_ctx_t *ctx,
8698 lsm6dso_aux_sens_on_t *val)
8699 {
8700 lsm6dso_master_config_t reg;
8701 int32_t ret;
8702
8703 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
8704 if (ret != 0) { return ret; }
8705
8706 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
8707
8708 switch (reg.aux_sens_on)
8709 {
8710 case LSM6DSO_SLV_0:
8711 *val = LSM6DSO_SLV_0;
8712 break;
8713
8714 case LSM6DSO_SLV_0_1:
8715 *val = LSM6DSO_SLV_0_1;
8716 break;
8717
8718 case LSM6DSO_SLV_0_1_2:
8719 *val = LSM6DSO_SLV_0_1_2;
8720 break;
8721
8722 case LSM6DSO_SLV_0_1_2_3:
8723 *val = LSM6DSO_SLV_0_1_2_3;
8724 break;
8725
8726 default:
8727 *val = LSM6DSO_SLV_0;
8728 break;
8729 }
8730
8731 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8732
8733 return ret;
8734 }
8735
8736 /**
8737 * @brief Sensor hub I2C master enable.[set]
8738 *
8739 * @param ctx read / write interface definitions
8740 * @param val change the values of master_on in reg MASTER_CONFIG
8741 * @retval interface status (MANDATORY: return 0 -> no Error)
8742 *
8743 */
lsm6dso_sh_master_set(const stmdev_ctx_t * ctx,uint8_t val)8744 int32_t lsm6dso_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val)
8745 {
8746 lsm6dso_master_config_t reg;
8747 int32_t ret;
8748
8749 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
8750 if (ret != 0) { return ret; }
8751
8752 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
8753 reg.master_on = val;
8754 ret += lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
8755
8756 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8757
8758 return ret;
8759 }
8760
8761 /**
8762 * @brief Sensor hub I2C master enable.[get]
8763 *
8764 * @param ctx read / write interface definitions
8765 * @param val Get the values of master_on in reg MASTER_CONFIG
8766 * @retval interface status (MANDATORY: return 0 -> no Error)
8767 *
8768 */
lsm6dso_sh_master_get(const stmdev_ctx_t * ctx,uint8_t * val)8769 int32_t lsm6dso_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val)
8770 {
8771 lsm6dso_master_config_t reg;
8772 int32_t ret;
8773
8774 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
8775 if (ret != 0) { return ret; }
8776
8777 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
8778 *val = reg.master_on;
8779 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8780
8781 return ret;
8782 }
8783
8784 /**
8785 * @brief Master I2C pull-up enable.[set]
8786 *
8787 * @param ctx read / write interface definitions
8788 * @param val change the values of shub_pu_en in reg MASTER_CONFIG
8789 * @retval interface status (MANDATORY: return 0 -> no Error)
8790 *
8791 */
lsm6dso_sh_pin_mode_set(const stmdev_ctx_t * ctx,lsm6dso_shub_pu_en_t val)8792 int32_t lsm6dso_sh_pin_mode_set(const stmdev_ctx_t *ctx,
8793 lsm6dso_shub_pu_en_t val)
8794 {
8795 lsm6dso_master_config_t reg;
8796 int32_t ret;
8797
8798 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
8799 if (ret != 0) { return ret; }
8800
8801 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
8802 reg.shub_pu_en = (uint8_t)val;
8803 ret += lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
8804
8805 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8806
8807 return ret;
8808 }
8809
8810 /**
8811 * @brief Master I2C pull-up enable.[get]
8812 *
8813 * @param ctx read / write interface definitions
8814 * @param val Get the values of shub_pu_en in reg MASTER_CONFIG
8815 * @retval interface status (MANDATORY: return 0 -> no Error)
8816 *
8817 */
lsm6dso_sh_pin_mode_get(const stmdev_ctx_t * ctx,lsm6dso_shub_pu_en_t * val)8818 int32_t lsm6dso_sh_pin_mode_get(const stmdev_ctx_t *ctx,
8819 lsm6dso_shub_pu_en_t *val)
8820 {
8821 lsm6dso_master_config_t reg;
8822 int32_t ret;
8823
8824 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
8825 if (ret != 0) { return ret; }
8826
8827 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
8828
8829 switch (reg.shub_pu_en)
8830 {
8831 case LSM6DSO_EXT_PULL_UP:
8832 *val = LSM6DSO_EXT_PULL_UP;
8833 break;
8834
8835 case LSM6DSO_INTERNAL_PULL_UP:
8836 *val = LSM6DSO_INTERNAL_PULL_UP;
8837 break;
8838
8839 default:
8840 *val = LSM6DSO_EXT_PULL_UP;
8841 break;
8842 }
8843
8844 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8845
8846 return ret;
8847 }
8848
8849 /**
8850 * @brief I2C interface pass-through.[set]
8851 *
8852 * @param ctx read / write interface definitions
8853 * @param val change the values of pass_through_mode in
8854 * reg MASTER_CONFIG
8855 * @retval interface status (MANDATORY: return 0 -> no Error)
8856 *
8857 */
lsm6dso_sh_pass_through_set(const stmdev_ctx_t * ctx,uint8_t val)8858 int32_t lsm6dso_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val)
8859 {
8860 lsm6dso_master_config_t reg;
8861 int32_t ret;
8862
8863 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
8864 if (ret != 0) { return ret; }
8865
8866 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
8867 reg.pass_through_mode = val;
8868 ret += lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
8869
8870 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8871
8872 return ret;
8873 }
8874
8875 /**
8876 * @brief I2C interface pass-through.[get]
8877 *
8878 * @param ctx read / write interface definitions
8879 * @param val Get the values of pass_through_mode in
8880 * reg MASTER_CONFIG
8881 * @retval interface status (MANDATORY: return 0 -> no Error)
8882 *
8883 */
lsm6dso_sh_pass_through_get(const stmdev_ctx_t * ctx,uint8_t * val)8884 int32_t lsm6dso_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val)
8885 {
8886 lsm6dso_master_config_t reg;
8887 int32_t ret;
8888
8889 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
8890 if (ret != 0) { return ret; }
8891
8892 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
8893 *val = reg.pass_through_mode;
8894
8895 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8896
8897 return ret;
8898 }
8899
8900 /**
8901 * @brief Sensor hub trigger signal selection.[set]
8902 *
8903 * @param ctx read / write interface definitions
8904 * @param val change the values of start_config in reg MASTER_CONFIG
8905 * @retval interface status (MANDATORY: return 0 -> no Error)
8906 *
8907 */
lsm6dso_sh_syncro_mode_set(const stmdev_ctx_t * ctx,lsm6dso_start_config_t val)8908 int32_t lsm6dso_sh_syncro_mode_set(const stmdev_ctx_t *ctx,
8909 lsm6dso_start_config_t val)
8910 {
8911 lsm6dso_master_config_t reg;
8912 int32_t ret;
8913
8914 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
8915 if (ret != 0) { return ret; }
8916
8917 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
8918 reg.start_config = (uint8_t)val;
8919 ret += lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
8920
8921 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8922
8923 return ret;
8924 }
8925
8926 /**
8927 * @brief Sensor hub trigger signal selection.[get]
8928 *
8929 * @param ctx read / write interface definitions
8930 * @param val Get the values of start_config in reg MASTER_CONFIG
8931 * @retval interface status (MANDATORY: return 0 -> no Error)
8932 *
8933 */
lsm6dso_sh_syncro_mode_get(const stmdev_ctx_t * ctx,lsm6dso_start_config_t * val)8934 int32_t lsm6dso_sh_syncro_mode_get(const stmdev_ctx_t *ctx,
8935 lsm6dso_start_config_t *val)
8936 {
8937 lsm6dso_master_config_t reg;
8938 int32_t ret;
8939
8940 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
8941 if (ret != 0) { return ret; }
8942
8943 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
8944
8945 switch (reg.start_config)
8946 {
8947 case LSM6DSO_EXT_ON_INT2_PIN:
8948 *val = LSM6DSO_EXT_ON_INT2_PIN;
8949 break;
8950
8951 case LSM6DSO_XL_GY_DRDY:
8952 *val = LSM6DSO_XL_GY_DRDY;
8953 break;
8954
8955 default:
8956 *val = LSM6DSO_EXT_ON_INT2_PIN;
8957 break;
8958 }
8959
8960 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8961
8962 return ret;
8963 }
8964
8965 /**
8966 * @brief Slave 0 write operation is performed only at the first
8967 * sensor hub cycle.[set]
8968 *
8969 * @param ctx read / write interface definitions
8970 * @param val change the values of write_once in reg MASTER_CONFIG
8971 * @retval interface status (MANDATORY: return 0 -> no Error)
8972 *
8973 */
lsm6dso_sh_write_mode_set(const stmdev_ctx_t * ctx,lsm6dso_write_once_t val)8974 int32_t lsm6dso_sh_write_mode_set(const stmdev_ctx_t *ctx,
8975 lsm6dso_write_once_t val)
8976 {
8977 lsm6dso_master_config_t reg;
8978 int32_t ret;
8979
8980 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
8981 if (ret != 0) { return ret; }
8982
8983 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
8984 reg.write_once = (uint8_t)val;
8985 ret += lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
8986
8987 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8988
8989 return ret;
8990 }
8991
8992 /**
8993 * @brief Slave 0 write operation is performed only at the first sensor
8994 * hub cycle.[get]
8995 *
8996 * @param ctx read / write interface definitions
8997 * @param val Get the values of write_once in reg MASTER_CONFIG
8998 * @retval interface status (MANDATORY: return 0 -> no Error)
8999 *
9000 */
lsm6dso_sh_write_mode_get(const stmdev_ctx_t * ctx,lsm6dso_write_once_t * val)9001 int32_t lsm6dso_sh_write_mode_get(const stmdev_ctx_t *ctx,
9002 lsm6dso_write_once_t *val)
9003 {
9004 lsm6dso_master_config_t reg;
9005 int32_t ret;
9006
9007 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9008 if (ret != 0) { return ret; }
9009
9010 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9011
9012 switch (reg.write_once)
9013 {
9014 case LSM6DSO_EACH_SH_CYCLE:
9015 *val = LSM6DSO_EACH_SH_CYCLE;
9016 break;
9017
9018 case LSM6DSO_ONLY_FIRST_CYCLE:
9019 *val = LSM6DSO_ONLY_FIRST_CYCLE;
9020 break;
9021
9022 default:
9023 *val = LSM6DSO_EACH_SH_CYCLE;
9024 break;
9025 }
9026
9027 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9028
9029 return ret;
9030 }
9031
9032 /**
9033 * @brief Reset Master logic and output registers.[set]
9034 *
9035 * @param ctx read / write interface definitions
9036 * @retval interface status (MANDATORY: return 0 -> no Error)
9037 *
9038 */
lsm6dso_sh_reset_set(const stmdev_ctx_t * ctx)9039 int32_t lsm6dso_sh_reset_set(const stmdev_ctx_t *ctx)
9040 {
9041 lsm6dso_master_config_t reg;
9042 int32_t ret;
9043
9044 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9045 if (ret != 0) { return ret; }
9046
9047 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9048 reg.rst_master_regs = PROPERTY_ENABLE;
9049 ret += lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9050 if (ret != 0) { return ret; }
9051
9052 reg.rst_master_regs = PROPERTY_DISABLE;
9053 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9054
9055 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9056
9057 return ret;
9058 }
9059
9060 /**
9061 * @brief Reset Master logic and output registers.[get]
9062 *
9063 * @param ctx read / write interface definitions
9064 * @param val Get the values of rst_master_regs in reg MASTER_CONFIG
9065 * @retval interface status (MANDATORY: return 0 -> no Error)
9066 *
9067 */
lsm6dso_sh_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)9068 int32_t lsm6dso_sh_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
9069 {
9070 lsm6dso_master_config_t reg;
9071 int32_t ret;
9072
9073 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9074 if (ret != 0) { return ret; }
9075
9076 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9077 *val = reg.rst_master_regs;
9078
9079 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9080
9081 return ret;
9082 }
9083
9084 /**
9085 * @brief Rate at which the master communicates.[set]
9086 *
9087 * @param ctx read / write interface definitions
9088 * @param val change the values of shub_odr in reg slv1_CONFIG
9089 * @retval interface status (MANDATORY: return 0 -> no Error)
9090 *
9091 */
lsm6dso_sh_data_rate_set(const stmdev_ctx_t * ctx,lsm6dso_shub_odr_t val)9092 int32_t lsm6dso_sh_data_rate_set(const stmdev_ctx_t *ctx,
9093 lsm6dso_shub_odr_t val)
9094 {
9095 lsm6dso_slv0_config_t reg;
9096 int32_t ret;
9097
9098 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9099 if (ret != 0) { return ret; }
9100
9101 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)®, 1);
9102 reg.shub_odr = (uint8_t)val;
9103 ret += lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)®, 1);
9104
9105 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9106
9107 return ret;
9108 }
9109
9110 /**
9111 * @brief Rate at which the master communicates.[get]
9112 *
9113 * @param ctx read / write interface definitions
9114 * @param val Get the values of shub_odr in reg slv1_CONFIG
9115 * @retval interface status (MANDATORY: return 0 -> no Error)
9116 *
9117 */
lsm6dso_sh_data_rate_get(const stmdev_ctx_t * ctx,lsm6dso_shub_odr_t * val)9118 int32_t lsm6dso_sh_data_rate_get(const stmdev_ctx_t *ctx,
9119 lsm6dso_shub_odr_t *val)
9120 {
9121 lsm6dso_slv0_config_t reg;
9122 int32_t ret;
9123
9124 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9125 if (ret != 0) { return ret; }
9126
9127 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)®, 1);
9128
9129 switch (reg.shub_odr)
9130 {
9131 case LSM6DSO_SH_ODR_104Hz:
9132 *val = LSM6DSO_SH_ODR_104Hz;
9133 break;
9134
9135 case LSM6DSO_SH_ODR_52Hz:
9136 *val = LSM6DSO_SH_ODR_52Hz;
9137 break;
9138
9139 case LSM6DSO_SH_ODR_26Hz:
9140 *val = LSM6DSO_SH_ODR_26Hz;
9141 break;
9142
9143 case LSM6DSO_SH_ODR_13Hz:
9144 *val = LSM6DSO_SH_ODR_13Hz;
9145 break;
9146
9147 default:
9148 *val = LSM6DSO_SH_ODR_104Hz;
9149 break;
9150 }
9151
9152 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9153
9154 return ret;
9155 }
9156
9157 /**
9158 * @brief Configure slave 0 for perform a write.[set]
9159 *
9160 * @param ctx read / write interface definitions
9161 * @param val a structure that contain
9162 * - uint8_t slv1_add; 8 bit i2c device address
9163 * - uint8_t slv1_subadd; 8 bit register device address
9164 * - uint8_t slv1_data; 8 bit data to write
9165 * @retval interface status (MANDATORY: return 0 -> no Error)
9166 *
9167 */
lsm6dso_sh_cfg_write(const stmdev_ctx_t * ctx,lsm6dso_sh_cfg_write_t * val)9168 int32_t lsm6dso_sh_cfg_write(const stmdev_ctx_t *ctx,
9169 lsm6dso_sh_cfg_write_t *val)
9170 {
9171 lsm6dso_slv0_add_t reg;
9172 int32_t ret;
9173
9174 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9175 if (ret != 0) { return ret; }
9176
9177 reg.slave0 = val->slv0_add;
9178 reg.rw_0 = 0;
9179 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD, (uint8_t *)®, 1);
9180 if (ret != 0) { goto exit; }
9181
9182 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_SUBADD, &(val->slv0_subadd), 1);
9183 if (ret != 0) { goto exit; }
9184
9185 ret = lsm6dso_write_reg(ctx, LSM6DSO_DATAWRITE_SLV0, &(val->slv0_data), 1);
9186
9187 exit:
9188 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9189
9190 return ret;
9191 }
9192
9193 /**
9194 * @brief Configure slave idx to perform a read.[set]
9195 *
9196 * @param ctx read / write interface definitions
9197 * @param val Structure that contain
9198 * - uint8_t slv1_add; 8 bit i2c device address
9199 * - uint8_t slv1_subadd; 8 bit register device address
9200 * - uint8_t slv1_len; num of bit to read
9201 * @retval interface status (MANDATORY: return 0 -> no Error)
9202 *
9203 */
lsm6dso_sh_slv_cfg_read(const stmdev_ctx_t * ctx,uint8_t idx,lsm6dso_sh_cfg_read_t * val)9204 int32_t lsm6dso_sh_slv_cfg_read(const stmdev_ctx_t *ctx, uint8_t idx,
9205 lsm6dso_sh_cfg_read_t *val)
9206 {
9207 lsm6dso_slv0_add_t slv0_add;
9208 lsm6dso_slv0_config_t slv0_config;
9209 int32_t ret;
9210
9211 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9212 if (ret != 0) { return ret; }
9213
9214 slv0_add.slave0 = val->slv_add;
9215 slv0_add.rw_0 = 1;
9216 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD + idx*3U, (uint8_t *)&slv0_add, 1);
9217 if (ret != 0) { goto exit; }
9218
9219 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_SUBADD + idx*3U, &(val->slv_subadd), 1);
9220 if (ret != 0) { goto exit; }
9221
9222 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG + idx*3U, (uint8_t *)&slv0_config, 1);
9223 slv0_config.slave0_numop = val->slv_len;
9224 ret += lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG + idx*3U, (uint8_t *)&slv0_config, 1);
9225
9226 exit:
9227 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9228
9229 return ret;
9230 }
9231
9232 /**
9233 * @brief Sensor hub source register.[get]
9234 *
9235 * @param ctx read / write interface definitions
9236 * @param val union of registers from STATUS_MASTER to
9237 * @retval interface status (MANDATORY: return 0 -> no Error)
9238 *
9239 */
lsm6dso_sh_status_get(const stmdev_ctx_t * ctx,lsm6dso_status_master_t * val)9240 int32_t lsm6dso_sh_status_get(const stmdev_ctx_t *ctx,
9241 lsm6dso_status_master_t *val)
9242 {
9243 int32_t ret;
9244
9245 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_MASTER_MAINPAGE, (uint8_t *) val, 1);
9246
9247 return ret;
9248 }
9249
9250 /**
9251 * @}
9252 *
9253 */
9254
9255 /**
9256 * @defgroup Basic configuration
9257 * @brief This section groups all the functions concerning
9258 * device basic configuration.
9259 * @{
9260 *
9261 */
9262
9263 /**
9264 * @brief Device "Who am I".[get]
9265 *
9266 * @param ctx communication interface handler. Use NULL to ignore
9267 * this interface.(ptr)
9268 * @param aux_ctx auxiliary communication interface handler. Use NULL
9269 * to ignore this interface.(ptr)
9270 * @param val ID values read from the two interfaces. ID values
9271 * will be the same.(ptr)
9272 * @retval interface status (MANDATORY: return 0 -> no Error)
9273 *
9274 */
lsm6dso_id_get(const stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dso_id_t * val)9275 int32_t lsm6dso_id_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
9276 lsm6dso_id_t *val)
9277 {
9278 int32_t ret = 0;
9279
9280 if (ctx != NULL)
9281 {
9282 ret = lsm6dso_read_reg(ctx, LSM6DSO_WHO_AM_I, (uint8_t *) & (val->ui), 1);
9283 }
9284
9285 if (aux_ctx != NULL)
9286 {
9287 ret += lsm6dso_read_reg(aux_ctx, LSM6DSO_WHO_AM_I, (uint8_t *) & (val->aux), 1);
9288 }
9289
9290 return ret;
9291 }
9292
9293 /**
9294 * @brief Re-initialize the device.[set]
9295 *
9296 * @param ctx communication interface handler.(ptr)
9297 * @param val re-initialization mode. Refer to datasheet
9298 * and application note for more information
9299 * about differences between boot and sw_reset
9300 * procedure.
9301 * @retval interface status (MANDATORY: return 0 -> no Error)
9302 *
9303 */
lsm6dso_init_set(const stmdev_ctx_t * ctx,lsm6dso_init_t val)9304 int32_t lsm6dso_init_set(const stmdev_ctx_t *ctx, lsm6dso_init_t val)
9305 {
9306 lsm6dso_emb_func_init_a_t emb_func_init_a;
9307 lsm6dso_emb_func_init_b_t emb_func_init_b;
9308 lsm6dso_ctrl3_c_t ctrl3_c;
9309 int32_t ret;
9310
9311 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
9312 if (ret != 0) { return ret; }
9313
9314 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)&emb_func_init_b, 1);
9315 emb_func_init_b.fifo_compr_init = (uint8_t)val & ((uint8_t)LSM6DSO_FIFO_COMP >> 2);
9316 emb_func_init_b.fsm_init = (uint8_t)val & ((uint8_t)LSM6DSO_FSM >> 3);
9317 ret += lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)&emb_func_init_b, 1);
9318
9319 ret += lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_A, (uint8_t *)&emb_func_init_a, 1);
9320 emb_func_init_a.step_det_init = ((uint8_t)val & (uint8_t)LSM6DSO_PEDO) >> 5;
9321 emb_func_init_a.tilt_init = ((uint8_t)val & (uint8_t)LSM6DSO_TILT) >> 6;
9322 emb_func_init_a.sig_mot_init = ((uint8_t)val & (uint8_t)LSM6DSO_SMOTION) >> 7;
9323 ret += lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_A, (uint8_t *)&emb_func_init_a, 1);
9324
9325 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9326 if (ret != 0) { return ret; }
9327
9328 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
9329
9330 if (((val == LSM6DSO_BOOT) || (val == LSM6DSO_RESET)) && (ret == 0))
9331 {
9332 ctrl3_c.boot = (uint8_t)val & (uint8_t)LSM6DSO_BOOT;
9333 ctrl3_c.sw_reset = ((uint8_t)val & (uint8_t)LSM6DSO_RESET) >> 1;
9334 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
9335 }
9336
9337 if ((val == LSM6DSO_DRV_RDY)
9338 && ((ctrl3_c.bdu == PROPERTY_DISABLE)
9339 || (ctrl3_c.if_inc == PROPERTY_DISABLE)) && (ret == 0))
9340 {
9341 ctrl3_c.bdu = PROPERTY_ENABLE;
9342 ctrl3_c.if_inc = PROPERTY_ENABLE;
9343 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
9344 }
9345
9346 return ret;
9347 }
9348
9349 /**
9350 * @brief Configures the bus operating mode.[set]
9351 *
9352 * @param ctx communication interface handler. Use NULL to ignore
9353 * this interface.(ptr)
9354 * @param aux_ctx auxiliary communication interface handler. Use NULL
9355 * to ignore this interface.(ptr)
9356 * @param val configures the bus operating mode for both the
9357 * main and the auxiliary interface.
9358 * @retval interface status (MANDATORY: return 0 -> no Error)
9359 *
9360 */
lsm6dso_bus_mode_set(const stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dso_bus_mode_t val)9361 int32_t lsm6dso_bus_mode_set(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
9362 lsm6dso_bus_mode_t val)
9363 {
9364 lsm6dso_ctrl1_ois_t ctrl1_ois;
9365 lsm6dso_i3c_bus_avb_t i3c_bus_avb;
9366 lsm6dso_ctrl9_xl_t ctrl9_xl;
9367 lsm6dso_ctrl3_c_t ctrl3_c;
9368 lsm6dso_ctrl4_c_t ctrl4_c;
9369 uint8_t bit_val;
9370 int32_t ret;
9371
9372 ret = 0;
9373
9374 if (aux_ctx != NULL)
9375 {
9376 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS,
9377 (uint8_t *)&ctrl1_ois, 1);
9378 bit_val = ((uint8_t)val.aux_bus_md & 0x04U) >> 2;
9379
9380 if ((ret == 0) && (ctrl1_ois.sim_ois != bit_val))
9381 {
9382 ctrl1_ois.sim_ois = bit_val;
9383 ret = lsm6dso_write_reg(aux_ctx, LSM6DSO_CTRL1_OIS,
9384 (uint8_t *)&ctrl1_ois, 1);
9385 }
9386 }
9387
9388 if (ctx != NULL)
9389 {
9390 if (ret == 0)
9391 {
9392 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL,
9393 (uint8_t *)&ctrl9_xl, 1);
9394 }
9395
9396 bit_val = ((uint8_t)val.ui_bus_md & 0x04U) >> 2;
9397
9398 if ((ret == 0) && (ctrl9_xl.i3c_disable != bit_val))
9399 {
9400 ctrl9_xl.i3c_disable = bit_val;
9401 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL,
9402 (uint8_t *)&ctrl9_xl, 1);
9403 }
9404
9405 if (ret == 0)
9406 {
9407 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
9408 (uint8_t *)&i3c_bus_avb, 1);
9409 }
9410
9411 bit_val = ((uint8_t)val.ui_bus_md & 0x30U) >> 4;
9412
9413 if ((ret == 0) && (i3c_bus_avb.i3c_bus_avb_sel != bit_val))
9414 {
9415 i3c_bus_avb.i3c_bus_avb_sel = bit_val;
9416 ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB,
9417 (uint8_t *)&i3c_bus_avb, 1);
9418 }
9419
9420 if (ret == 0)
9421 {
9422 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C,
9423 (uint8_t *)&ctrl4_c, 1);
9424 }
9425
9426 bit_val = ((uint8_t)val.ui_bus_md & 0x02U) >> 1;
9427
9428 if ((ret == 0) && (ctrl4_c.i2c_disable != bit_val))
9429 {
9430 ctrl4_c.i2c_disable = bit_val;
9431 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C,
9432 (uint8_t *)&ctrl4_c, 1);
9433 }
9434
9435 if (ret == 0)
9436 {
9437 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C,
9438 (uint8_t *)&ctrl3_c, 1);
9439 }
9440
9441 bit_val = (uint8_t)val.ui_bus_md & 0x01U;
9442
9443 if ((ret == 0) && (ctrl3_c.sim != bit_val))
9444 {
9445 ctrl3_c.sim = bit_val;
9446 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C,
9447 (uint8_t *)&ctrl3_c, 1);
9448 }
9449 }
9450
9451 return ret;
9452 }
9453
9454 /**
9455 * @brief Get the bus operating mode.[get]
9456 *
9457 * @param ctx communication interface handler. Use NULL to ignore
9458 * this interface.(ptr)
9459 * @param aux_ctx auxiliary communication interface handler. Use NULL
9460 * to ignore this interface.(ptr)
9461 * @param val retrieves the bus operating mode for both the main
9462 * and the auxiliary interface.(ptr)
9463 * @retval interface status (MANDATORY: return 0 -> no Error)
9464 *
9465 */
lsm6dso_bus_mode_get(const stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dso_bus_mode_t * val)9466 int32_t lsm6dso_bus_mode_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
9467 lsm6dso_bus_mode_t *val)
9468 {
9469 lsm6dso_ctrl1_ois_t ctrl1_ois;
9470 lsm6dso_i3c_bus_avb_t i3c_bus_avb;
9471 lsm6dso_ctrl9_xl_t ctrl9_xl;
9472 lsm6dso_ctrl3_c_t ctrl3_c;
9473 lsm6dso_ctrl4_c_t ctrl4_c;
9474 int32_t ret = 0;
9475
9476 if (aux_ctx != NULL)
9477 {
9478 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS,
9479 (uint8_t *)&ctrl1_ois, 1);
9480
9481 switch (ctrl1_ois.sim_ois)
9482 {
9483 case LSM6DSO_SPI_4W_AUX:
9484 val->aux_bus_md = LSM6DSO_SPI_4W_AUX;
9485 break;
9486
9487 case LSM6DSO_SPI_3W_AUX:
9488 val->aux_bus_md = LSM6DSO_SPI_3W_AUX;
9489 break;
9490
9491 default:
9492 val->aux_bus_md = LSM6DSO_SPI_4W_AUX;
9493 break;
9494 }
9495 }
9496
9497 if (ctx != NULL)
9498 {
9499 if (ret == 0)
9500 {
9501 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL,
9502 (uint8_t *)&ctrl9_xl, 1);
9503 }
9504
9505 if (ret == 0)
9506 {
9507 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
9508 (uint8_t *)&i3c_bus_avb, 1);
9509 }
9510
9511 if (ret == 0)
9512 {
9513 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C,
9514 (uint8_t *)&ctrl4_c, 1);
9515 }
9516
9517 if (ret == 0)
9518 {
9519 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C,
9520 (uint8_t *)&ctrl3_c, 1);
9521
9522 switch ((i3c_bus_avb.i3c_bus_avb_sel << 4) &
9523 (ctrl9_xl.i3c_disable << 2) &
9524 (ctrl4_c.i2c_disable << 1) & ctrl3_c.sim)
9525 {
9526 case LSM6DSO_SEL_BY_HW:
9527 val->ui_bus_md = LSM6DSO_SEL_BY_HW;
9528 break;
9529
9530 case LSM6DSO_SPI_4W:
9531 val->ui_bus_md = LSM6DSO_SPI_4W;
9532 break;
9533
9534 case LSM6DSO_SPI_3W:
9535 val->ui_bus_md = LSM6DSO_SPI_3W;
9536 break;
9537
9538 case LSM6DSO_I2C:
9539 val->ui_bus_md = LSM6DSO_I2C;
9540 break;
9541
9542 case LSM6DSO_I3C_T_50us:
9543 val->ui_bus_md = LSM6DSO_I3C_T_50us;
9544 break;
9545
9546 case LSM6DSO_I3C_T_2us:
9547 val->ui_bus_md = LSM6DSO_I3C_T_2us;
9548 break;
9549
9550 case LSM6DSO_I3C_T_1ms:
9551 val->ui_bus_md = LSM6DSO_I3C_T_1ms;
9552 break;
9553
9554 case LSM6DSO_I3C_T_25ms:
9555 val->ui_bus_md = LSM6DSO_I3C_T_25ms;
9556 break;
9557
9558 default:
9559 val->ui_bus_md = LSM6DSO_SEL_BY_HW;
9560 break;
9561 }
9562 }
9563 }
9564
9565 return ret;
9566 }
9567
9568 /**
9569 * @brief Get the status of the device.[get]
9570 *
9571 * @param ctx communication interface handler. Use NULL to ignore
9572 * this interface.(ptr)
9573 * @param aux_ctx auxiliary communication interface handler. Use NULL
9574 * to ignore this interface.(ptr)
9575 * @param val the status of the device.(ptr)
9576 * @retval interface status (MANDATORY: return 0 -> no Error)
9577 *
9578 */
lsm6dso_status_get(const stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dso_status_t * val)9579 int32_t lsm6dso_status_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
9580 lsm6dso_status_t *val)
9581 {
9582 lsm6dso_status_spiaux_t status_spiaux;
9583 lsm6dso_status_reg_t status_reg;
9584 lsm6dso_ctrl3_c_t ctrl3_c;
9585 int32_t ret;
9586 ret = 0;
9587
9588 if (aux_ctx != NULL)
9589 {
9590 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_STATUS_SPIAUX,
9591 (uint8_t *)&status_spiaux, 1);
9592 val->ois_drdy_xl = status_spiaux.xlda;
9593 val->ois_drdy_g = status_spiaux.gda;
9594 val->ois_gyro_settling = status_spiaux.gyro_settling;
9595 }
9596
9597 if (ctx != NULL)
9598 {
9599 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
9600 val->sw_reset = ctrl3_c.sw_reset;
9601 val->boot = ctrl3_c.boot;
9602
9603 if ((ret == 0) && (ctrl3_c.sw_reset == PROPERTY_DISABLE) &&
9604 (ctrl3_c.boot == PROPERTY_DISABLE))
9605 {
9606 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG,
9607 (uint8_t *)&status_reg, 1);
9608 val->drdy_xl = status_reg.xlda;
9609 val->drdy_g = status_reg.gda;
9610 val->drdy_temp = status_reg.tda;
9611 }
9612 }
9613
9614 return ret;
9615 }
9616
9617 /**
9618 * @brief Electrical pin configuration.[set]
9619 *
9620 * @param ctx communication interface handler.(ptr)
9621 * @param val the electrical settings for the configurable
9622 * pins.
9623 * @retval interface status (MANDATORY: return 0 -> no Error)
9624 *
9625 */
lsm6dso_pin_conf_set(const stmdev_ctx_t * ctx,lsm6dso_pin_conf_t val)9626 int32_t lsm6dso_pin_conf_set(const stmdev_ctx_t *ctx,
9627 lsm6dso_pin_conf_t val)
9628 {
9629 lsm6dso_i3c_bus_avb_t i3c_bus_avb;
9630 lsm6dso_pin_ctrl_t pin_ctrl;
9631 lsm6dso_ctrl3_c_t ctrl3_c;
9632 int32_t ret;
9633
9634 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
9635 pin_ctrl.ois_pu_dis = ~val.aux_sdo_ocs_pull_up;
9636 pin_ctrl.sdo_pu_en = val.sdo_sa0_pull_up;
9637 ret += lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
9638 if (ret != 0) { return ret; }
9639
9640 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
9641 ctrl3_c.pp_od = ~val.int1_int2_push_pull;
9642 ret += lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
9643 if (ret != 0) { return ret; }
9644
9645 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1);
9646 i3c_bus_avb.pd_dis_int1 = ~val.int1_pull_down;
9647 ret += lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1);
9648
9649 return ret;
9650 }
9651
9652 /**
9653 * @brief Electrical pin configuration.[get]
9654 *
9655 * @param ctx communication interface handler.(ptr)
9656 * @param val the electrical settings for the configurable
9657 * pins.(ptr)
9658 * @retval interface status (MANDATORY: return 0 -> no Error)
9659 *
9660 */
lsm6dso_pin_conf_get(const stmdev_ctx_t * ctx,lsm6dso_pin_conf_t * val)9661 int32_t lsm6dso_pin_conf_get(const stmdev_ctx_t *ctx,
9662 lsm6dso_pin_conf_t *val)
9663 {
9664 lsm6dso_i3c_bus_avb_t i3c_bus_avb;
9665 lsm6dso_pin_ctrl_t pin_ctrl;
9666 lsm6dso_ctrl3_c_t ctrl3_c;
9667 int32_t ret;
9668
9669 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
9670 if (ret != 0) { return ret; }
9671
9672 val->aux_sdo_ocs_pull_up = ~pin_ctrl.ois_pu_dis;
9673 val->aux_sdo_ocs_pull_up = pin_ctrl.sdo_pu_en;
9674
9675 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
9676 if (ret != 0) { return ret; }
9677
9678 val->int1_int2_push_pull = ~ctrl3_c.pp_od;
9679
9680 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)&i3c_bus_avb, 1);
9681 val->int1_pull_down = ~i3c_bus_avb.pd_dis_int1;
9682
9683 return ret;
9684 }
9685
9686 /**
9687 * @brief Interrupt pins hardware signal configuration.[set]
9688 *
9689 * @param ctx communication interface handler.(ptr)
9690 * @param val the pins hardware signal settings.
9691 * @retval interface status (MANDATORY: return 0 -> no Error)
9692 *
9693 */
lsm6dso_interrupt_mode_set(const stmdev_ctx_t * ctx,lsm6dso_int_mode_t val)9694 int32_t lsm6dso_interrupt_mode_set(const stmdev_ctx_t *ctx,
9695 lsm6dso_int_mode_t val)
9696 {
9697 lsm6dso_tap_cfg0_t tap_cfg0;
9698 lsm6dso_page_rw_t page_rw;
9699 lsm6dso_ctrl3_c_t ctrl3_c;
9700 int32_t ret;
9701
9702 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
9703 ctrl3_c.h_lactive = val.active_low;
9704 ret += lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
9705 if (ret != 0) { return ret; }
9706
9707 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
9708 tap_cfg0.lir = val.base_latched;
9709 tap_cfg0.int_clr_on_read = val.base_latched | val.emb_latched;
9710 ret += lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
9711 if (ret != 0) { return ret; }
9712
9713 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
9714 if (ret != 0) { return ret; }
9715
9716 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
9717 page_rw.emb_func_lir = val.emb_latched;
9718 ret += lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
9719
9720 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9721
9722 return ret;
9723 }
9724
9725 /**
9726 * @brief Interrupt pins hardware signal configuration.[get]
9727 *
9728 * @param ctx communication interface handler.(ptr)
9729 * @param val the pins hardware signal settings.(ptr)
9730 * @retval interface status (MANDATORY: return 0 -> no Error)
9731 *
9732 */
lsm6dso_interrupt_mode_get(const stmdev_ctx_t * ctx,lsm6dso_int_mode_t * val)9733 int32_t lsm6dso_interrupt_mode_get(const stmdev_ctx_t *ctx,
9734 lsm6dso_int_mode_t *val)
9735 {
9736 lsm6dso_tap_cfg0_t tap_cfg0;
9737 lsm6dso_page_rw_t page_rw;
9738 lsm6dso_ctrl3_c_t ctrl3_c;
9739 int32_t ret;
9740
9741 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
9742 if (ret != 0) { return ret; }
9743
9744 val->active_low = ctrl3_c.h_lactive;
9745
9746 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
9747 if (ret != 0) { return ret; }
9748
9749 val->base_latched = (tap_cfg0.lir & tap_cfg0.int_clr_on_read);
9750
9751 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
9752 if (ret != 0) { return ret; }
9753
9754 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
9755 val->emb_latched = (page_rw.emb_func_lir & tap_cfg0.int_clr_on_read);
9756
9757 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9758
9759 return ret;
9760 }
9761
9762 /**
9763 * @brief Route interrupt signals on int1 pin.[set]
9764 *
9765 * @param ctx communication interface handler.(ptr)
9766 * @param val the signals to route on int1 pin.
9767 * @retval interface status (MANDATORY: return 0 -> no Error)
9768 *
9769 */
lsm6dso_pin_int1_route_set(const stmdev_ctx_t * ctx,lsm6dso_pin_int1_route_t val)9770 int32_t lsm6dso_pin_int1_route_set(const stmdev_ctx_t *ctx,
9771 lsm6dso_pin_int1_route_t val)
9772 {
9773 lsm6dso_pin_int2_route_t pin_int2_route;
9774 lsm6dso_emb_func_int1_t emb_func_int1;
9775 lsm6dso_fsm_int1_a_t fsm_int1_a;
9776 lsm6dso_fsm_int1_b_t fsm_int1_b;
9777 lsm6dso_int1_ctrl_t int1_ctrl = {0};
9778 lsm6dso_int2_ctrl_t int2_ctrl;
9779 lsm6dso_tap_cfg2_t tap_cfg2;
9780 lsm6dso_md2_cfg_t md2_cfg;
9781 lsm6dso_md1_cfg_t md1_cfg;
9782 lsm6dso_ctrl4_c_t ctrl4_c;
9783 int32_t ret;
9784
9785 /* INT1_CTRL */
9786 int1_ctrl.int1_drdy_xl = val.drdy_xl;
9787 int1_ctrl.int1_drdy_g = val.drdy_g;
9788 int1_ctrl.int1_boot = val.boot;
9789 int1_ctrl.int1_fifo_th = val.fifo_th;
9790 int1_ctrl.int1_fifo_ovr = val.fifo_ovr;
9791 int1_ctrl.int1_fifo_full = val.fifo_full;
9792 int1_ctrl.int1_cnt_bdr = val.fifo_bdr;
9793 int1_ctrl.den_drdy_flag = val.den_flag;
9794 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
9795 if (ret != 0) { return ret; }
9796
9797 /* DRDY for temperature and/or timestamp */
9798 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
9799 if (ret != 0) { return ret; }
9800
9801 if ((val.drdy_temp | val.timestamp) != PROPERTY_DISABLE)
9802 {
9803 ctrl4_c.int2_on_int1 = PROPERTY_ENABLE;
9804 }
9805 else
9806 {
9807 ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
9808 }
9809
9810 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
9811 if (ret != 0) { return ret; }
9812
9813 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
9814 int2_ctrl.int2_drdy_temp = val.drdy_temp;
9815 ret += lsm6dso_write_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
9816 if (ret != 0) { return ret; }
9817
9818 ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
9819 md2_cfg.int2_timestamp = val.timestamp;
9820 ret += lsm6dso_write_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
9821 if (ret != 0) { return ret; }
9822
9823 /* emmbedded and FSM events */
9824 emb_func_int1.not_used_01 = 0;
9825 emb_func_int1.int1_step_detector = val.step_detector;
9826 emb_func_int1.int1_tilt = val.tilt;
9827 emb_func_int1.int1_sig_mot = val.sig_mot;
9828 emb_func_int1.not_used_02 = 0;
9829 emb_func_int1.int1_fsm_lc = val.fsm_lc;
9830 fsm_int1_a.int1_fsm1 = val.fsm1;
9831 fsm_int1_a.int1_fsm2 = val.fsm2;
9832 fsm_int1_a.int1_fsm3 = val.fsm3;
9833 fsm_int1_a.int1_fsm4 = val.fsm4;
9834 fsm_int1_a.int1_fsm5 = val.fsm5;
9835 fsm_int1_a.int1_fsm6 = val.fsm6;
9836 fsm_int1_a.int1_fsm7 = val.fsm7;
9837 fsm_int1_a.int1_fsm8 = val.fsm8;
9838 fsm_int1_b.int1_fsm9 = val.fsm9 ;
9839 fsm_int1_b.int1_fsm10 = val.fsm10;
9840 fsm_int1_b.int1_fsm11 = val.fsm11;
9841 fsm_int1_b.int1_fsm12 = val.fsm12;
9842 fsm_int1_b.int1_fsm13 = val.fsm13;
9843 fsm_int1_b.int1_fsm14 = val.fsm14;
9844 fsm_int1_b.int1_fsm15 = val.fsm15;
9845 fsm_int1_b.int1_fsm16 = val.fsm16;
9846
9847 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
9848 if (ret != 0) { return ret; }
9849
9850 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
9851 ret += lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT1_A, (uint8_t *)&fsm_int1_a, 1);
9852 ret += lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT1_B, (uint8_t *)&fsm_int1_b, 1);
9853
9854 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9855 if (ret != 0) { return ret; }
9856
9857 /* MD1_CFG */
9858 md1_cfg.int1_shub = val.sh_endop;
9859 md1_cfg.int1_6d = val.six_d;
9860 md1_cfg.int1_double_tap = val.double_tap;
9861 md1_cfg.int1_ff = val.free_fall;
9862 md1_cfg.int1_wu = val.wake_up;
9863 md1_cfg.int1_single_tap = val.single_tap;
9864 md1_cfg.int1_sleep_change = val.sleep_change;
9865
9866 if ((emb_func_int1.int1_fsm_lc
9867 | emb_func_int1.int1_sig_mot
9868 | emb_func_int1.int1_step_detector
9869 | emb_func_int1.int1_tilt
9870 | fsm_int1_a.int1_fsm1
9871 | fsm_int1_a.int1_fsm2
9872 | fsm_int1_a.int1_fsm3
9873 | fsm_int1_a.int1_fsm4
9874 | fsm_int1_a.int1_fsm5
9875 | fsm_int1_a.int1_fsm6
9876 | fsm_int1_a.int1_fsm7
9877 | fsm_int1_a.int1_fsm8
9878 | fsm_int1_b.int1_fsm9
9879 | fsm_int1_b.int1_fsm10
9880 | fsm_int1_b.int1_fsm11
9881 | fsm_int1_b.int1_fsm12
9882 | fsm_int1_b.int1_fsm13
9883 | fsm_int1_b.int1_fsm14
9884 | fsm_int1_b.int1_fsm15
9885 | fsm_int1_b.int1_fsm16) != PROPERTY_DISABLE)
9886 {
9887 md1_cfg.int1_emb_func = PROPERTY_ENABLE;
9888 }
9889 else
9890 {
9891 md1_cfg.int1_emb_func = PROPERTY_DISABLE;
9892 }
9893
9894 ret = lsm6dso_write_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t *)&md1_cfg, 1);
9895 if (ret != 0) { return ret; }
9896
9897 /* set interrupts_enable = 1 in TAP_CFG2 if it is the case */
9898 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
9899 ret += lsm6dso_pin_int2_route_get(ctx, NULL, &pin_int2_route);
9900 if (ret != 0) { return ret; }
9901
9902 if ((pin_int2_route.fifo_bdr
9903 | pin_int2_route.drdy_g
9904 | pin_int2_route.drdy_temp
9905 | pin_int2_route.drdy_xl
9906 | pin_int2_route.fifo_full
9907 | pin_int2_route.fifo_ovr
9908 | pin_int2_route.fifo_th
9909 | pin_int2_route.six_d
9910 | pin_int2_route.double_tap
9911 | pin_int2_route.free_fall
9912 | pin_int2_route.wake_up
9913 | pin_int2_route.single_tap
9914 | pin_int2_route.sleep_change
9915 | int1_ctrl.den_drdy_flag
9916 | int1_ctrl.int1_boot
9917 | int1_ctrl.int1_cnt_bdr
9918 | int1_ctrl.int1_drdy_g
9919 | int1_ctrl.int1_drdy_xl
9920 | int1_ctrl.int1_fifo_full
9921 | int1_ctrl.int1_fifo_ovr
9922 | int1_ctrl.int1_fifo_th
9923 | md1_cfg.int1_shub
9924 | md1_cfg.int1_6d
9925 | md1_cfg.int1_double_tap
9926 | md1_cfg.int1_ff
9927 | md1_cfg.int1_wu
9928 | md1_cfg.int1_single_tap
9929 | md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
9930 {
9931 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
9932 }
9933 else
9934 {
9935 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
9936 }
9937
9938 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
9939
9940 return ret;
9941 }
9942
9943 /**
9944 * @brief Route interrupt signals on int1 pin.[get]
9945 *
9946 * @param ctx communication interface handler.(ptr)
9947 * @param val the signals that are routed on int1 pin.(ptr)
9948 * @retval interface status (MANDATORY: return 0 -> no Error)
9949 *
9950 */
lsm6dso_pin_int1_route_get(const stmdev_ctx_t * ctx,lsm6dso_pin_int1_route_t * val)9951 int32_t lsm6dso_pin_int1_route_get(const stmdev_ctx_t *ctx,
9952 lsm6dso_pin_int1_route_t *val)
9953 {
9954 lsm6dso_emb_func_int1_t emb_func_int1;
9955 lsm6dso_fsm_int1_a_t fsm_int1_a;
9956 lsm6dso_fsm_int1_b_t fsm_int1_b;
9957 lsm6dso_int1_ctrl_t int1_ctrl;
9958 lsm6dso_int2_ctrl_t int2_ctrl;
9959 lsm6dso_md2_cfg_t md2_cfg;
9960 lsm6dso_md1_cfg_t md1_cfg;
9961 lsm6dso_ctrl4_c_t ctrl4_c;
9962 int32_t ret;
9963
9964 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
9965 if (ret != 0) { return ret; }
9966
9967 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INT1, (uint8_t *)&emb_func_int1, 1);
9968 ret += lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT1_A, (uint8_t *)&fsm_int1_a, 1);
9969 ret += lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT1_B, (uint8_t *)&fsm_int1_b, 1);
9970
9971 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9972 if (ret != 0) { return ret; }
9973
9974 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
9975 if (ret != 0) { return ret; }
9976
9977 ret = lsm6dso_read_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t *)&md1_cfg, 1);
9978 if (ret != 0) { return ret; }
9979
9980 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
9981 if (ret != 0) { return ret; }
9982
9983 if (ctrl4_c.int2_on_int1 == PROPERTY_ENABLE)
9984 {
9985 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
9986 val->drdy_temp = int2_ctrl.int2_drdy_temp;
9987
9988 ret += lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
9989 val->timestamp = md2_cfg.int2_timestamp;
9990 }
9991 else
9992 {
9993 val->drdy_temp = PROPERTY_DISABLE;
9994 val->timestamp = PROPERTY_DISABLE;
9995 }
9996 if (ret != 0) { return ret; }
9997
9998 val->drdy_xl = int1_ctrl.int1_drdy_xl;
9999 val->drdy_g = int1_ctrl.int1_drdy_g;
10000 val->boot = int1_ctrl.int1_boot;
10001 val->fifo_th = int1_ctrl.int1_fifo_th;
10002 val->fifo_ovr = int1_ctrl.int1_fifo_ovr;
10003 val->fifo_full = int1_ctrl.int1_fifo_full;
10004 val->fifo_bdr = int1_ctrl.int1_cnt_bdr;
10005 val->den_flag = int1_ctrl.den_drdy_flag;
10006 val->sh_endop = md1_cfg.int1_shub;
10007 val->six_d = md1_cfg.int1_6d;
10008 val->double_tap = md1_cfg.int1_double_tap;
10009 val->free_fall = md1_cfg.int1_ff;
10010 val->wake_up = md1_cfg.int1_wu;
10011 val->single_tap = md1_cfg.int1_single_tap;
10012 val->sleep_change = md1_cfg.int1_sleep_change;
10013 val->step_detector = emb_func_int1.int1_step_detector;
10014 val->tilt = emb_func_int1.int1_tilt;
10015 val->sig_mot = emb_func_int1.int1_sig_mot;
10016 val->fsm_lc = emb_func_int1.int1_fsm_lc;
10017 val->fsm1 = fsm_int1_a.int1_fsm1;
10018 val->fsm2 = fsm_int1_a.int1_fsm2;
10019 val->fsm3 = fsm_int1_a.int1_fsm3;
10020 val->fsm4 = fsm_int1_a.int1_fsm4;
10021 val->fsm5 = fsm_int1_a.int1_fsm5;
10022 val->fsm6 = fsm_int1_a.int1_fsm6;
10023 val->fsm7 = fsm_int1_a.int1_fsm7;
10024 val->fsm8 = fsm_int1_a.int1_fsm8;
10025 val->fsm9 = fsm_int1_b.int1_fsm9;
10026 val->fsm10 = fsm_int1_b.int1_fsm10;
10027 val->fsm11 = fsm_int1_b.int1_fsm11;
10028 val->fsm12 = fsm_int1_b.int1_fsm12;
10029 val->fsm13 = fsm_int1_b.int1_fsm13;
10030 val->fsm14 = fsm_int1_b.int1_fsm14;
10031 val->fsm15 = fsm_int1_b.int1_fsm15;
10032 val->fsm16 = fsm_int1_b.int1_fsm16;
10033
10034 return ret;
10035 }
10036
10037 /**
10038 * @brief Route interrupt signals on int2 pin.[set]
10039 *
10040 * @param ctx communication interface handler. Use NULL to ignore
10041 * this interface.(ptr)
10042 * @param aux_ctx auxiliary communication interface handler. Use NULL
10043 * to ignore this interface.(ptr)
10044 * @param val the signals to route on int2 pin.
10045 * @retval interface status (MANDATORY: return 0 -> no Error)
10046 *
10047 */
lsm6dso_pin_int2_route_set(const stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dso_pin_int2_route_t val)10048 int32_t lsm6dso_pin_int2_route_set(const stmdev_ctx_t *ctx,
10049 stmdev_ctx_t *aux_ctx,
10050 lsm6dso_pin_int2_route_t val)
10051 {
10052 lsm6dso_pin_int1_route_t pin_int1_route;
10053 lsm6dso_emb_func_int2_t emb_func_int2;
10054 lsm6dso_fsm_int2_a_t fsm_int2_a;
10055 lsm6dso_fsm_int2_b_t fsm_int2_b;
10056 lsm6dso_int2_ctrl_t int2_ctrl;
10057 lsm6dso_tap_cfg2_t tap_cfg2;
10058 lsm6dso_md2_cfg_t md2_cfg;
10059 lsm6dso_ctrl4_c_t ctrl4_c;
10060 lsm6dso_int_ois_t int_ois;
10061 int32_t ret;
10062 ret = 0;
10063
10064 if (aux_ctx != NULL)
10065 {
10066 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_INT_OIS, (uint8_t *)&int_ois, 1);
10067 int_ois.int2_drdy_ois = val.drdy_ois;
10068 ret += lsm6dso_write_reg(aux_ctx, LSM6DSO_INT_OIS, (uint8_t *)&int_ois, 1);
10069 if (ret != 0) { return ret; }
10070 }
10071
10072 if (ctx != NULL)
10073 {
10074 int2_ctrl.int2_drdy_xl = val.drdy_xl;
10075 int2_ctrl.int2_drdy_g = val.drdy_g;
10076 int2_ctrl.int2_drdy_temp = val.drdy_temp;
10077 int2_ctrl.int2_fifo_th = val.fifo_th;
10078 int2_ctrl.int2_fifo_ovr = val.fifo_ovr;
10079 int2_ctrl.int2_fifo_full = val.fifo_full;
10080 int2_ctrl.int2_cnt_bdr = val.fifo_bdr;
10081 int2_ctrl.not_used_01 = 0;
10082 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
10083 if (ret != 0) { return ret; }
10084
10085 md2_cfg.int2_timestamp = val.timestamp;
10086 md2_cfg.int2_6d = val.six_d;
10087 md2_cfg.int2_double_tap = val.double_tap;
10088 md2_cfg.int2_ff = val.free_fall;
10089 md2_cfg.int2_wu = val.wake_up;
10090 md2_cfg.int2_single_tap = val.single_tap;
10091 md2_cfg.int2_sleep_change = val.sleep_change;
10092 emb_func_int2.not_used_01 = 0;
10093 emb_func_int2. int2_step_detector = val.step_detector;
10094 emb_func_int2.int2_tilt = val.tilt;
10095 emb_func_int2.int2_sig_mot = val.sig_mot;
10096 emb_func_int2.not_used_02 = 0;
10097 emb_func_int2.int2_fsm_lc = val.fsm_lc;
10098 fsm_int2_a.int2_fsm1 = val.fsm1;
10099 fsm_int2_a.int2_fsm2 = val.fsm2;
10100 fsm_int2_a.int2_fsm3 = val.fsm3;
10101 fsm_int2_a.int2_fsm4 = val.fsm4;
10102 fsm_int2_a.int2_fsm5 = val.fsm5;
10103 fsm_int2_a.int2_fsm6 = val.fsm6;
10104 fsm_int2_a.int2_fsm7 = val.fsm7;
10105 fsm_int2_a.int2_fsm8 = val.fsm8;
10106 fsm_int2_b.int2_fsm9 = val.fsm9 ;
10107 fsm_int2_b.int2_fsm10 = val.fsm10;
10108 fsm_int2_b.int2_fsm11 = val.fsm11;
10109 fsm_int2_b.int2_fsm12 = val.fsm12;
10110 fsm_int2_b.int2_fsm13 = val.fsm13;
10111 fsm_int2_b.int2_fsm14 = val.fsm14;
10112 fsm_int2_b.int2_fsm15 = val.fsm15;
10113 fsm_int2_b.int2_fsm16 = val.fsm16;
10114
10115 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
10116
10117 if ((val.drdy_temp | val.timestamp) != PROPERTY_DISABLE)
10118 {
10119 ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
10120 }
10121
10122 ret += lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
10123 if (ret != 0) { return ret; }
10124
10125 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
10126
10127 ret += lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INT2, (uint8_t *)&emb_func_int2, 1);
10128 ret += lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT2_A, (uint8_t *)&fsm_int2_a, 1);
10129 ret += lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT2_B, (uint8_t *)&fsm_int2_b, 1);
10130
10131 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
10132 if (ret != 0) { return ret; }
10133
10134 if ((emb_func_int2.int2_fsm_lc
10135 | emb_func_int2.int2_sig_mot
10136 | emb_func_int2.int2_step_detector
10137 | emb_func_int2.int2_tilt
10138 | fsm_int2_a.int2_fsm1
10139 | fsm_int2_a.int2_fsm2
10140 | fsm_int2_a.int2_fsm3
10141 | fsm_int2_a.int2_fsm4
10142 | fsm_int2_a.int2_fsm5
10143 | fsm_int2_a.int2_fsm6
10144 | fsm_int2_a.int2_fsm7
10145 | fsm_int2_a.int2_fsm8
10146 | fsm_int2_b.int2_fsm9
10147 | fsm_int2_b.int2_fsm10
10148 | fsm_int2_b.int2_fsm11
10149 | fsm_int2_b.int2_fsm12
10150 | fsm_int2_b.int2_fsm13
10151 | fsm_int2_b.int2_fsm14
10152 | fsm_int2_b.int2_fsm15
10153 | fsm_int2_b.int2_fsm16) != PROPERTY_DISABLE)
10154 {
10155 md2_cfg.int2_emb_func = PROPERTY_ENABLE;
10156 }
10157 else
10158 {
10159 md2_cfg.int2_emb_func = PROPERTY_DISABLE;
10160 }
10161
10162 ret = lsm6dso_write_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
10163 if (ret != 0) { return ret; }
10164
10165 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
10166 ret += lsm6dso_pin_int1_route_get(ctx, &pin_int1_route);
10167
10168 if ((val.fifo_bdr
10169 | val.drdy_g
10170 | val.drdy_temp
10171 | val.drdy_xl
10172 | val.fifo_full
10173 | val.fifo_ovr
10174 | val.fifo_th
10175 | val.six_d
10176 | val.double_tap
10177 | val.free_fall
10178 | val.wake_up
10179 | val.single_tap
10180 | val.sleep_change
10181 | pin_int1_route.den_flag
10182 | pin_int1_route.boot
10183 | pin_int1_route.fifo_bdr
10184 | pin_int1_route.drdy_g
10185 | pin_int1_route.drdy_xl
10186 | pin_int1_route.fifo_full
10187 | pin_int1_route.fifo_ovr
10188 | pin_int1_route.fifo_th
10189 | pin_int1_route.six_d
10190 | pin_int1_route.double_tap
10191 | pin_int1_route.free_fall
10192 | pin_int1_route.wake_up
10193 | pin_int1_route.single_tap
10194 | pin_int1_route.sleep_change) != PROPERTY_DISABLE)
10195 {
10196 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
10197 }
10198 else
10199 {
10200 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
10201 }
10202
10203 ret += lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
10204 }
10205
10206 return ret;
10207 }
10208
10209 /**
10210 * @brief Route interrupt signals on int2 pin.[get]
10211 *
10212 * @param ctx communication interface handler. Use NULL to ignore
10213 * this interface.(ptr)
10214 * @param aux_ctx auxiliary communication interface handler. Use NULL
10215 * to ignore this interface.(ptr)
10216 * @param val the signals that are routed on int2 pin.(ptr)
10217 * @retval interface status (MANDATORY: return 0 -> no Error)
10218 *
10219 */
lsm6dso_pin_int2_route_get(const stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dso_pin_int2_route_t * val)10220 int32_t lsm6dso_pin_int2_route_get(const stmdev_ctx_t *ctx,
10221 stmdev_ctx_t *aux_ctx,
10222 lsm6dso_pin_int2_route_t *val)
10223 {
10224 lsm6dso_emb_func_int2_t emb_func_int2;
10225 lsm6dso_fsm_int2_a_t fsm_int2_a;
10226 lsm6dso_fsm_int2_b_t fsm_int2_b;
10227 lsm6dso_int2_ctrl_t int2_ctrl;
10228 lsm6dso_md2_cfg_t md2_cfg;
10229 lsm6dso_ctrl4_c_t ctrl4_c;
10230 lsm6dso_int_ois_t int_ois;
10231 int32_t ret;
10232 ret = 0;
10233
10234 if (aux_ctx != NULL)
10235 {
10236 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_INT_OIS,
10237 (uint8_t *)&int_ois, 1);
10238 val->drdy_ois = int_ois.int2_drdy_ois;
10239 }
10240
10241 if (ctx != NULL)
10242 {
10243 if (ret == 0)
10244 {
10245 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
10246 }
10247
10248 if (ret == 0)
10249 {
10250 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INT2,
10251 (uint8_t *)&emb_func_int2, 1);
10252 }
10253
10254 if (ret == 0)
10255 {
10256 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT2_A,
10257 (uint8_t *)&fsm_int2_a, 1);
10258 }
10259
10260 if (ret == 0)
10261 {
10262 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT2_B,
10263 (uint8_t *)&fsm_int2_b, 1);
10264 }
10265
10266 if (ret == 0)
10267 {
10268 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
10269 }
10270
10271 if (ret == 0)
10272 {
10273 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL,
10274 (uint8_t *)&int2_ctrl, 1);
10275 }
10276
10277 if (ret == 0)
10278 {
10279 ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG,
10280 (uint8_t *)&md2_cfg, 1);
10281 }
10282
10283 if (ret == 0)
10284 {
10285 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
10286 }
10287
10288 if (ctrl4_c.int2_on_int1 == PROPERTY_DISABLE)
10289 {
10290 if (ret == 0)
10291 {
10292 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL,
10293 (uint8_t *)&int2_ctrl, 1);
10294 val->drdy_temp = int2_ctrl.int2_drdy_temp;
10295 }
10296
10297 if (ret == 0)
10298 {
10299 ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
10300 val->timestamp = md2_cfg.int2_timestamp;
10301 }
10302 }
10303
10304 else
10305 {
10306 val->drdy_temp = PROPERTY_DISABLE;
10307 val->timestamp = PROPERTY_DISABLE;
10308 }
10309
10310 val->drdy_xl = int2_ctrl.int2_drdy_xl;
10311 val->drdy_g = int2_ctrl.int2_drdy_g;
10312 val->drdy_temp = int2_ctrl.int2_drdy_temp;
10313 val->fifo_th = int2_ctrl.int2_fifo_th;
10314 val->fifo_ovr = int2_ctrl.int2_fifo_ovr;
10315 val->fifo_full = int2_ctrl.int2_fifo_full;
10316 val->fifo_bdr = int2_ctrl.int2_cnt_bdr;
10317 val->timestamp = md2_cfg.int2_timestamp;
10318 val->six_d = md2_cfg.int2_6d;
10319 val->double_tap = md2_cfg.int2_double_tap;
10320 val->free_fall = md2_cfg.int2_ff;
10321 val->wake_up = md2_cfg.int2_wu;
10322 val->single_tap = md2_cfg.int2_single_tap;
10323 val->sleep_change = md2_cfg.int2_sleep_change;
10324 val->step_detector = emb_func_int2. int2_step_detector;
10325 val->tilt = emb_func_int2.int2_tilt;
10326 val->fsm_lc = emb_func_int2.int2_fsm_lc;
10327 val->fsm1 = fsm_int2_a.int2_fsm1;
10328 val->fsm2 = fsm_int2_a.int2_fsm2;
10329 val->fsm3 = fsm_int2_a.int2_fsm3;
10330 val->fsm4 = fsm_int2_a.int2_fsm4;
10331 val->fsm5 = fsm_int2_a.int2_fsm5;
10332 val->fsm6 = fsm_int2_a.int2_fsm6;
10333 val->fsm7 = fsm_int2_a.int2_fsm7;
10334 val->fsm8 = fsm_int2_a.int2_fsm8;
10335 val->fsm9 = fsm_int2_b.int2_fsm9;
10336 val->fsm10 = fsm_int2_b.int2_fsm10;
10337 val->fsm11 = fsm_int2_b.int2_fsm11;
10338 val->fsm12 = fsm_int2_b.int2_fsm12;
10339 val->fsm13 = fsm_int2_b.int2_fsm13;
10340 val->fsm14 = fsm_int2_b.int2_fsm14;
10341 val->fsm15 = fsm_int2_b.int2_fsm15;
10342 val->fsm16 = fsm_int2_b.int2_fsm16;
10343 }
10344
10345 return ret;
10346 }
10347
10348 /**
10349 * @brief Get the status of all the interrupt sources.[get]
10350 *
10351 * @param ctx communication interface handler.(ptr)
10352 * @param val the status of all the interrupt sources.(ptr)
10353 * @retval interface status (MANDATORY: return 0 -> no Error)
10354 *
10355 */
lsm6dso_all_sources_get(const stmdev_ctx_t * ctx,lsm6dso_all_sources_t * val)10356 int32_t lsm6dso_all_sources_get(const stmdev_ctx_t *ctx,
10357 lsm6dso_all_sources_t *val)
10358 {
10359 lsm6dso_emb_func_status_mainpage_t emb_func_status_mainpage;
10360 lsm6dso_status_master_mainpage_t status_master_mainpage;
10361 lsm6dso_fsm_status_a_mainpage_t fsm_status_a_mainpage;
10362 lsm6dso_fsm_status_b_mainpage_t fsm_status_b_mainpage;
10363 lsm6dso_fifo_status1_t fifo_status1;
10364 lsm6dso_fifo_status2_t fifo_status2;
10365 lsm6dso_all_int_src_t all_int_src;
10366 lsm6dso_wake_up_src_t wake_up_src;
10367 lsm6dso_status_reg_t status_reg;
10368 lsm6dso_tap_src_t tap_src;
10369 lsm6dso_d6d_src_t d6d_src;
10370 uint8_t reg[5];
10371 int32_t ret;
10372
10373 ret = lsm6dso_read_reg(ctx, LSM6DSO_ALL_INT_SRC, reg, 5);
10374 if (ret != 0) { return ret; }
10375
10376 bytecpy((uint8_t *)&all_int_src, ®[0]);
10377 bytecpy((uint8_t *)&wake_up_src, ®[1]);
10378 bytecpy((uint8_t *)&tap_src, ®[2]);
10379 bytecpy((uint8_t *)&d6d_src, ®[3]);
10380 bytecpy((uint8_t *)&status_reg, ®[4]);
10381 val->timestamp = all_int_src.timestamp_endcount;
10382 val->wake_up_z = wake_up_src.z_wu;
10383 val->wake_up_y = wake_up_src.y_wu;
10384 val->wake_up_x = wake_up_src.x_wu;
10385 val->wake_up = wake_up_src.wu_ia;
10386 val->sleep_state = wake_up_src.sleep_state;
10387 val->free_fall = wake_up_src.ff_ia;
10388 val->sleep_change = wake_up_src.sleep_change_ia;
10389 val->tap_x = tap_src.x_tap;
10390 val->tap_y = tap_src.y_tap;
10391 val->tap_z = tap_src.z_tap;
10392 val->tap_sign = tap_src.tap_sign;
10393 val->double_tap = tap_src.double_tap;
10394 val->single_tap = tap_src.single_tap;
10395 val->six_d_xl = d6d_src.xl;
10396 val->six_d_xh = d6d_src.xh;
10397 val->six_d_yl = d6d_src.yl;
10398 val->six_d_yh = d6d_src.yh;
10399 val->six_d_zl = d6d_src.zl;
10400 val->six_d_zh = d6d_src.zh;
10401 val->six_d = d6d_src.d6d_ia;
10402 val->den_flag = d6d_src.den_drdy;
10403 val->drdy_xl = status_reg.xlda;
10404 val->drdy_g = status_reg.gda;
10405 val->drdy_temp = status_reg.tda;
10406
10407 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS_MAINPAGE, reg, 3);
10408 if (ret != 0) { return ret; }
10409
10410 bytecpy((uint8_t *)&emb_func_status_mainpage, ®[0]);
10411 bytecpy((uint8_t *)&fsm_status_a_mainpage, ®[1]);
10412 bytecpy((uint8_t *)&fsm_status_b_mainpage, ®[2]);
10413 val->step_detector = emb_func_status_mainpage.is_step_det;
10414 val->tilt = emb_func_status_mainpage.is_tilt;
10415 val->sig_mot = emb_func_status_mainpage.is_sigmot;
10416 val->fsm_lc = emb_func_status_mainpage.is_fsm_lc;
10417 val->fsm1 = fsm_status_a_mainpage.is_fsm1;
10418 val->fsm2 = fsm_status_a_mainpage.is_fsm2;
10419 val->fsm3 = fsm_status_a_mainpage.is_fsm3;
10420 val->fsm4 = fsm_status_a_mainpage.is_fsm4;
10421 val->fsm5 = fsm_status_a_mainpage.is_fsm5;
10422 val->fsm6 = fsm_status_a_mainpage.is_fsm6;
10423 val->fsm7 = fsm_status_a_mainpage.is_fsm7;
10424 val->fsm8 = fsm_status_a_mainpage.is_fsm8;
10425 val->fsm9 = fsm_status_b_mainpage.is_fsm9;
10426 val->fsm10 = fsm_status_b_mainpage.is_fsm10;
10427 val->fsm11 = fsm_status_b_mainpage.is_fsm11;
10428 val->fsm12 = fsm_status_b_mainpage.is_fsm12;
10429 val->fsm13 = fsm_status_b_mainpage.is_fsm13;
10430 val->fsm14 = fsm_status_b_mainpage.is_fsm14;
10431 val->fsm15 = fsm_status_b_mainpage.is_fsm15;
10432 val->fsm16 = fsm_status_b_mainpage.is_fsm16;
10433
10434 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_MASTER_MAINPAGE, reg, 3);
10435 if (ret != 0) { return ret; }
10436
10437 bytecpy((uint8_t *)&status_master_mainpage, ®[0]);
10438 bytecpy((uint8_t *)&fifo_status1, ®[1]);
10439 bytecpy((uint8_t *)&fifo_status2, ®[2]);
10440 val->sh_endop = status_master_mainpage.sens_hub_endop;
10441 val->sh_slave0_nack = status_master_mainpage.slave0_nack;
10442 val->sh_slave1_nack = status_master_mainpage.slave1_nack;
10443 val->sh_slave2_nack = status_master_mainpage.slave2_nack;
10444 val->sh_slave3_nack = status_master_mainpage.slave3_nack;
10445 val->sh_wr_once = status_master_mainpage.wr_once_done;
10446 val->fifo_diff = (256U * fifo_status2.diff_fifo) +
10447 fifo_status1.diff_fifo;
10448 val->fifo_ovr_latched = fifo_status2.over_run_latched;
10449 val->fifo_bdr = fifo_status2.counter_bdr_ia;
10450 val->fifo_full = fifo_status2.fifo_full_ia;
10451 val->fifo_ovr = fifo_status2.fifo_ovr_ia;
10452 val->fifo_th = fifo_status2.fifo_wtm_ia;
10453
10454 return ret;
10455 }
10456
10457 /**
10458 * @brief Sensor conversion parameters selection.[set]
10459 *
10460 * @param ctx communication interface handler. Use NULL to ignore
10461 * this interface.(ptr)
10462 * @param aux_ctx auxiliary communication interface handler. Use NULL
10463 * to ignore this interface.(ptr)
10464 * @param val set the sensor conversion parameters by checking
10465 * the constraints of the device.(ptr)
10466 * @retval interface status (MANDATORY: return 0 -> no Error)
10467 *
10468 */
lsm6dso_mode_set(const stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dso_md_t * val)10469 int32_t lsm6dso_mode_set(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
10470 lsm6dso_md_t *val)
10471 {
10472 lsm6dso_func_cfg_access_t func_cfg_access;
10473 lsm6dso_ctrl1_ois_t ctrl1_ois;
10474 lsm6dso_ctrl2_ois_t ctrl2_ois = {0};
10475 lsm6dso_ctrl3_ois_t ctrl3_ois;
10476 lsm6dso_ctrl1_xl_t ctrl1_xl;
10477 lsm6dso_ctrl8_xl_t ctrl8_xl;
10478 lsm6dso_ctrl2_g_t ctrl2_g;
10479 lsm6dso_ctrl3_c_t ctrl3_c = {0};
10480 lsm6dso_ctrl4_c_t ctrl4_c = {0};
10481 lsm6dso_ctrl5_c_t ctrl5_c;
10482 lsm6dso_ctrl6_c_t ctrl6_c;
10483 lsm6dso_ctrl7_g_t ctrl7_g;
10484 uint8_t xl_hm_mode;
10485 uint8_t g_hm_mode;
10486 uint8_t xl_ulp_en;
10487 uint8_t odr_gy;
10488 uint8_t odr_xl;
10489 uint8_t reg[8];
10490 int32_t ret;
10491
10492 ret = 0;
10493 /* FIXME: Remove warnings with STM32CubeIDE */
10494 ctrl3_c.not_used_01 = 0;
10495 ctrl4_c.not_used_01 = 0;
10496 /* reading input configuration */
10497 xl_hm_mode = ((uint8_t)val->ui.xl.odr & 0x10U) >> 4;
10498 xl_ulp_en = ((uint8_t)val->ui.xl.odr & 0x20U) >> 5;
10499 odr_xl = (uint8_t)val->ui.xl.odr & 0x0FU;
10500
10501 /* if enable xl ultra low power mode disable gy and OIS chain */
10502 if (xl_ulp_en == PROPERTY_ENABLE)
10503 {
10504 val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
10505 val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
10506 val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
10507 }
10508
10509 /* if OIS xl is enabled also gyro OIS is enabled */
10510 if (val->ois.xl.odr == LSM6DSO_XL_OIS_6667Hz_HP)
10511 {
10512 val->ois.gy.odr = LSM6DSO_GY_OIS_6667Hz_HP;
10513 }
10514
10515 g_hm_mode = ((uint8_t)val->ui.gy.odr & 0x10U) >> 4;
10516 odr_gy = (uint8_t)val->ui.gy.odr & 0x0FU;
10517
10518 /* reading registers to be configured */
10519 if (ctx != NULL)
10520 {
10521 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, reg, 8);
10522 if (ret != 0) { return ret; }
10523
10524 bytecpy((uint8_t *)&ctrl1_xl, ®[0]);
10525 bytecpy((uint8_t *)&ctrl2_g, ®[1]);
10526 bytecpy((uint8_t *)&ctrl3_c, ®[2]);
10527 bytecpy((uint8_t *)&ctrl4_c, ®[3]);
10528 bytecpy((uint8_t *)&ctrl5_c, ®[4]);
10529 bytecpy((uint8_t *)&ctrl6_c, ®[5]);
10530 bytecpy((uint8_t *)&ctrl7_g, ®[6]);
10531 bytecpy((uint8_t *)&ctrl8_xl, ®[7]);
10532
10533 ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
10534
10535 /* if toggle xl ultra low power mode, turn off xl before reconfigure */
10536 if (ctrl5_c.xl_ulp_en != xl_ulp_en)
10537 {
10538 ctrl1_xl.odr_xl = (uint8_t) 0x00U;
10539 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
10540 }
10541 }
10542
10543 /* reading OIS registers to be configured */
10544 if (aux_ctx != NULL)
10545 {
10546 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS, reg, 3);
10547 if (ret != 0) { return ret; }
10548
10549 bytecpy((uint8_t *)&ctrl1_ois, ®[0]);
10550 bytecpy((uint8_t *)&ctrl2_ois, ®[1]);
10551 bytecpy((uint8_t *)&ctrl3_ois, ®[2]);
10552 }
10553 else
10554 {
10555 if (ctx != NULL)
10556 {
10557 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, reg, 3);
10558 if (ret != 0) { return ret; }
10559
10560 bytecpy((uint8_t *)&ctrl1_ois, ®[0]);
10561 bytecpy((uint8_t *)&ctrl2_ois, ®[1]);
10562 bytecpy((uint8_t *)&ctrl3_ois, ®[2]);
10563 }
10564 }
10565
10566 /* Check the Finite State Machine data rate constraints */
10567 if (val->fsm.sens != LSM6DSO_FSM_DISABLE)
10568 {
10569 switch (val->fsm.odr)
10570 {
10571 case LSM6DSO_FSM_12Hz5:
10572 if ((val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl == 0x00U))
10573 {
10574 odr_xl = 0x01U;
10575 }
10576
10577 if ((val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy == 0x00U))
10578 {
10579 xl_ulp_en = PROPERTY_DISABLE;
10580 odr_gy = 0x01U;
10581 }
10582
10583 break;
10584
10585 case LSM6DSO_FSM_26Hz:
10586 if ((val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x02U))
10587 {
10588 odr_xl = 0x02U;
10589 }
10590
10591 if ((val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x02U))
10592 {
10593 xl_ulp_en = PROPERTY_DISABLE;
10594 odr_gy = 0x02U;
10595 }
10596
10597 break;
10598
10599 case LSM6DSO_FSM_52Hz:
10600 if ((val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x03U))
10601 {
10602 odr_xl = 0x03U;
10603 }
10604
10605 if ((val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x03U))
10606 {
10607 xl_ulp_en = PROPERTY_DISABLE;
10608 odr_gy = 0x03U;
10609 }
10610
10611 break;
10612
10613 case LSM6DSO_FSM_104Hz:
10614 if ((val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x04U))
10615 {
10616 odr_xl = 0x04U;
10617 }
10618
10619 if ((val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x04U))
10620 {
10621 xl_ulp_en = PROPERTY_DISABLE;
10622 odr_gy = 0x04U;
10623 }
10624
10625 break;
10626
10627 default:
10628 odr_xl = 0x00U;
10629 odr_gy = 0x00U;
10630 break;
10631 }
10632 }
10633
10634 /* Updating the accelerometer data rate configuration */
10635 switch ((ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
10636 ctrl1_xl.odr_xl)
10637 {
10638 case LSM6DSO_XL_UI_OFF:
10639 val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
10640 break;
10641
10642 case LSM6DSO_XL_UI_12Hz5_HP:
10643 val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_HP;
10644 break;
10645
10646 case LSM6DSO_XL_UI_26Hz_HP:
10647 val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_HP;
10648 break;
10649
10650 case LSM6DSO_XL_UI_52Hz_HP:
10651 val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_HP;
10652 break;
10653
10654 case LSM6DSO_XL_UI_104Hz_HP:
10655 val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_HP;
10656 break;
10657
10658 case LSM6DSO_XL_UI_208Hz_HP:
10659 val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_HP;
10660 break;
10661
10662 case LSM6DSO_XL_UI_416Hz_HP:
10663 val->ui.xl.odr = LSM6DSO_XL_UI_416Hz_HP;
10664 break;
10665
10666 case LSM6DSO_XL_UI_833Hz_HP:
10667 val->ui.xl.odr = LSM6DSO_XL_UI_833Hz_HP;
10668 break;
10669
10670 case LSM6DSO_XL_UI_1667Hz_HP:
10671 val->ui.xl.odr = LSM6DSO_XL_UI_1667Hz_HP;
10672 break;
10673
10674 case LSM6DSO_XL_UI_3333Hz_HP:
10675 val->ui.xl.odr = LSM6DSO_XL_UI_3333Hz_HP;
10676 break;
10677
10678 case LSM6DSO_XL_UI_6667Hz_HP:
10679 val->ui.xl.odr = LSM6DSO_XL_UI_6667Hz_HP;
10680 break;
10681
10682 case LSM6DSO_XL_UI_1Hz6_LP:
10683 val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_LP;
10684 break;
10685
10686 case LSM6DSO_XL_UI_12Hz5_LP:
10687 val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_LP;
10688 break;
10689
10690 case LSM6DSO_XL_UI_26Hz_LP:
10691 val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_LP;
10692 break;
10693
10694 case LSM6DSO_XL_UI_52Hz_LP:
10695 val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_LP;
10696 break;
10697
10698 case LSM6DSO_XL_UI_104Hz_NM:
10699 val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_NM;
10700 break;
10701
10702 case LSM6DSO_XL_UI_208Hz_NM:
10703 val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_NM;
10704 break;
10705
10706 case LSM6DSO_XL_UI_1Hz6_ULP:
10707 val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_ULP;
10708 break;
10709
10710 case LSM6DSO_XL_UI_12Hz5_ULP:
10711 val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_ULP;
10712 break;
10713
10714 case LSM6DSO_XL_UI_26Hz_ULP:
10715 val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_ULP;
10716 break;
10717
10718 case LSM6DSO_XL_UI_52Hz_ULP:
10719 val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_ULP;
10720 break;
10721
10722 case LSM6DSO_XL_UI_104Hz_ULP:
10723 val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_ULP;
10724 break;
10725
10726 case LSM6DSO_XL_UI_208Hz_ULP:
10727 val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_ULP;
10728 break;
10729
10730 default:
10731 val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
10732 break;
10733 }
10734
10735 /* Updating the accelerometer data rate configuration */
10736 switch ((ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g)
10737 {
10738 case LSM6DSO_GY_UI_OFF:
10739 val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
10740 break;
10741
10742 case LSM6DSO_GY_UI_12Hz5_LP:
10743 val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_LP;
10744 break;
10745
10746 case LSM6DSO_GY_UI_12Hz5_HP:
10747 val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_HP;
10748 break;
10749
10750 case LSM6DSO_GY_UI_26Hz_LP:
10751 val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_LP;
10752 break;
10753
10754 case LSM6DSO_GY_UI_26Hz_HP:
10755 val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_HP;
10756 break;
10757
10758 case LSM6DSO_GY_UI_52Hz_LP:
10759 val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_LP;
10760 break;
10761
10762 case LSM6DSO_GY_UI_52Hz_HP:
10763 val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_HP;
10764 break;
10765
10766 case LSM6DSO_GY_UI_104Hz_NM:
10767 val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_NM;
10768 break;
10769
10770 case LSM6DSO_GY_UI_104Hz_HP:
10771 val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_HP;
10772 break;
10773
10774 case LSM6DSO_GY_UI_208Hz_NM:
10775 val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_NM;
10776 break;
10777
10778 case LSM6DSO_GY_UI_208Hz_HP:
10779 val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_HP;
10780 break;
10781
10782 case LSM6DSO_GY_UI_416Hz_HP:
10783 val->ui.gy.odr = LSM6DSO_GY_UI_416Hz_HP;
10784 break;
10785
10786 case LSM6DSO_GY_UI_833Hz_HP:
10787 val->ui.gy.odr = LSM6DSO_GY_UI_833Hz_HP;
10788 break;
10789
10790 case LSM6DSO_GY_UI_1667Hz_HP:
10791 val->ui.gy.odr = LSM6DSO_GY_UI_1667Hz_HP;
10792 break;
10793
10794 case LSM6DSO_GY_UI_3333Hz_HP:
10795 val->ui.gy.odr = LSM6DSO_GY_UI_3333Hz_HP;
10796 break;
10797
10798 case LSM6DSO_GY_UI_6667Hz_HP:
10799 val->ui.gy.odr = LSM6DSO_GY_UI_6667Hz_HP;
10800 break;
10801
10802 default:
10803 val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
10804 break;
10805 }
10806
10807 /* Check accelerometer full scale constraints */
10808 /* Full scale of 16g must be the same for UI and OIS */
10809 if ((val->ui.xl.fs == LSM6DSO_XL_UI_16g) ||
10810 (val->ois.xl.fs == LSM6DSO_XL_OIS_16g))
10811 {
10812 val->ui.xl.fs = LSM6DSO_XL_UI_16g;
10813 val->ois.xl.fs = LSM6DSO_XL_OIS_16g;
10814 }
10815
10816 /* prapare new configuration */
10817
10818 /* Full scale of 16g must be the same for UI and OIS */
10819 if (val->ui.xl.fs == LSM6DSO_XL_UI_16g)
10820 {
10821 ctrl8_xl.xl_fs_mode = PROPERTY_DISABLE;
10822 }
10823
10824 else
10825 {
10826 ctrl8_xl.xl_fs_mode = PROPERTY_ENABLE;
10827 }
10828
10829 /* OIS new configuration */
10830 ctrl7_g.ois_on_en = (val->ois.ctrl_md == LSM6DSO_OIS_MIXED) ? 1U : 0U;
10831
10832 switch (val->ois.ctrl_md)
10833 {
10834 case LSM6DSO_OIS_ONLY_AUX:
10835 ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
10836 ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr |
10837 (uint8_t)val->ois.xl.odr;
10838 ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
10839 ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
10840 break;
10841
10842 case LSM6DSO_OIS_MIXED:
10843 ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
10844 ctrl7_g.ois_on = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr;
10845 ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
10846 ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
10847 break;
10848
10849 default:
10850 ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
10851 ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr |
10852 (uint8_t)val->ois.xl.odr;
10853 ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
10854 ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
10855 break;
10856 }
10857
10858 /* UI new configuration */
10859 ctrl1_xl.odr_xl = odr_xl;
10860 ctrl1_xl.fs_xl = (uint8_t)val->ui.xl.fs;
10861 ctrl5_c.xl_ulp_en = xl_ulp_en;
10862 ctrl6_c.xl_hm_mode = xl_hm_mode;
10863 ctrl7_g.g_hm_mode = g_hm_mode;
10864 ctrl2_g.odr_g = odr_gy;
10865 ctrl2_g.fs_g = (uint8_t) val->ui.gy.fs;
10866
10867 /* writing checked configuration */
10868 if (ctx != NULL)
10869 {
10870 bytecpy(®[0], (uint8_t *)&ctrl1_xl);
10871 bytecpy(®[1], (uint8_t *)&ctrl2_g);
10872 bytecpy(®[2], (uint8_t *)&ctrl3_c);
10873 bytecpy(®[3], (uint8_t *)&ctrl4_c);
10874 bytecpy(®[4], (uint8_t *)&ctrl5_c);
10875 bytecpy(®[5], (uint8_t *)&ctrl6_c);
10876 bytecpy(®[6], (uint8_t *)&ctrl7_g);
10877 bytecpy(®[7], (uint8_t *)&ctrl8_xl);
10878
10879 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 8);
10880 ret += lsm6dso_write_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
10881 if (ret != 0) { return ret; }
10882 }
10883
10884 /* writing OIS checked configuration */
10885 if (aux_ctx != NULL)
10886 {
10887 bytecpy(®[0], (uint8_t *)&ctrl1_ois);
10888 bytecpy(®[1], (uint8_t *)&ctrl2_ois);
10889 bytecpy(®[2], (uint8_t *)&ctrl3_ois);
10890
10891 ret = lsm6dso_write_reg(aux_ctx, LSM6DSO_CTRL1_OIS, reg, 3);
10892 }
10893
10894 return ret;
10895 }
10896
10897 /**
10898 * @brief Sensor conversion parameters selection.[get]
10899 *
10900 * @param ctx communication interface handler. Use NULL to ignore
10901 * this interface.(ptr)
10902 * @param aux_ctx auxiliary communication interface handler. Use NULL
10903 * to ignore this interface.(ptr)
10904 * @param val get the sensor conversion parameters.(ptr)
10905 * @retval interface status (MANDATORY: return 0 -> no Error)
10906 *
10907 */
lsm6dso_mode_get(const stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dso_md_t * val)10908 int32_t lsm6dso_mode_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
10909 lsm6dso_md_t *val)
10910 {
10911 lsm6dso_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
10912 lsm6dso_func_cfg_access_t func_cfg_access;
10913 lsm6dso_emb_func_en_b_t emb_func_en_b;
10914 lsm6dso_fsm_enable_a_t fsm_enable_a;
10915 lsm6dso_fsm_enable_b_t fsm_enable_b;
10916 lsm6dso_ctrl1_ois_t ctrl1_ois;
10917 lsm6dso_ctrl2_ois_t ctrl2_ois;
10918 lsm6dso_ctrl3_ois_t ctrl3_ois;
10919 lsm6dso_ctrl1_xl_t ctrl1_xl;
10920 lsm6dso_ctrl2_g_t ctrl2_g;
10921 lsm6dso_ctrl3_c_t ctrl3_c;
10922 lsm6dso_ctrl4_c_t ctrl4_c;
10923 lsm6dso_ctrl5_c_t ctrl5_c;
10924 lsm6dso_ctrl6_c_t ctrl6_c;
10925 lsm6dso_ctrl7_g_t ctrl7_g;
10926 uint8_t reg[8];
10927 int32_t ret;
10928
10929 ret = 0;
10930
10931 /* reading the registers of the device */
10932 if (ctx != NULL)
10933 {
10934 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, reg, 7);
10935 if (ret != 0) { return ret; }
10936
10937 bytecpy((uint8_t *)&ctrl1_xl, ®[0]);
10938 bytecpy((uint8_t *)&ctrl2_g, ®[1]);
10939 bytecpy((uint8_t *)&ctrl3_c, ®[2]);
10940 bytecpy((uint8_t *)&ctrl4_c, ®[3]);
10941 bytecpy((uint8_t *)&ctrl5_c, ®[4]);
10942 bytecpy((uint8_t *)&ctrl6_c, ®[5]);
10943 bytecpy((uint8_t *)&ctrl7_g, ®[6]);
10944
10945 ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)&func_cfg_access, 1);
10946 if (ret != 0) { return ret; }
10947
10948 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
10949 if (ret != 0) { return ret; }
10950
10951 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B, reg, 1);
10952 bytecpy((uint8_t *)&emb_func_odr_cfg_b, ®[0]);
10953
10954 ret += lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
10955 bytecpy((uint8_t *)&fsm_enable_b, ®[1]);
10956
10957 ret += lsm6dso_read_reg(ctx, LSM6DSO_FSM_ENABLE_A, reg, 2);
10958 bytecpy((uint8_t *)&fsm_enable_a, ®[0]);
10959
10960 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
10961 if (ret != 0) { return ret; }
10962 }
10963
10964 if (aux_ctx != NULL)
10965 {
10966 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS, reg, 3);
10967 if (ret != 0) { return ret; }
10968
10969 bytecpy((uint8_t *)&ctrl1_ois, ®[0]);
10970 bytecpy((uint8_t *)&ctrl2_ois, ®[1]);
10971 bytecpy((uint8_t *)&ctrl3_ois, ®[2]);
10972 }
10973
10974 else
10975 {
10976 if (ctx != NULL)
10977 {
10978 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, reg, 3);
10979 if (ret != 0) { return ret; }
10980
10981 bytecpy((uint8_t *)&ctrl1_ois, ®[0]);
10982 bytecpy((uint8_t *)&ctrl2_ois, ®[1]);
10983 bytecpy((uint8_t *)&ctrl3_ois, ®[2]);
10984 }
10985 }
10986
10987 /* fill the input structure */
10988
10989 /* get accelerometer configuration */
10990 switch ((ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
10991 ctrl1_xl.odr_xl)
10992 {
10993 case LSM6DSO_XL_UI_OFF:
10994 val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
10995 break;
10996
10997 case LSM6DSO_XL_UI_12Hz5_HP:
10998 val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_HP;
10999 break;
11000
11001 case LSM6DSO_XL_UI_26Hz_HP:
11002 val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_HP;
11003 break;
11004
11005 case LSM6DSO_XL_UI_52Hz_HP:
11006 val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_HP;
11007 break;
11008
11009 case LSM6DSO_XL_UI_104Hz_HP:
11010 val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_HP;
11011 break;
11012
11013 case LSM6DSO_XL_UI_208Hz_HP:
11014 val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_HP;
11015 break;
11016
11017 case LSM6DSO_XL_UI_416Hz_HP:
11018 val->ui.xl.odr = LSM6DSO_XL_UI_416Hz_HP;
11019 break;
11020
11021 case LSM6DSO_XL_UI_833Hz_HP:
11022 val->ui.xl.odr = LSM6DSO_XL_UI_833Hz_HP;
11023 break;
11024
11025 case LSM6DSO_XL_UI_1667Hz_HP:
11026 val->ui.xl.odr = LSM6DSO_XL_UI_1667Hz_HP;
11027 break;
11028
11029 case LSM6DSO_XL_UI_3333Hz_HP:
11030 val->ui.xl.odr = LSM6DSO_XL_UI_3333Hz_HP;
11031 break;
11032
11033 case LSM6DSO_XL_UI_6667Hz_HP:
11034 val->ui.xl.odr = LSM6DSO_XL_UI_6667Hz_HP;
11035 break;
11036
11037 case LSM6DSO_XL_UI_1Hz6_LP:
11038 val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_LP;
11039 break;
11040
11041 case LSM6DSO_XL_UI_12Hz5_LP:
11042 val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_LP;
11043 break;
11044
11045 case LSM6DSO_XL_UI_26Hz_LP:
11046 val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_LP;
11047 break;
11048
11049 case LSM6DSO_XL_UI_52Hz_LP:
11050 val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_LP;
11051 break;
11052
11053 case LSM6DSO_XL_UI_104Hz_NM:
11054 val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_NM;
11055 break;
11056
11057 case LSM6DSO_XL_UI_208Hz_NM:
11058 val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_NM;
11059 break;
11060
11061 case LSM6DSO_XL_UI_1Hz6_ULP:
11062 val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_ULP;
11063 break;
11064
11065 case LSM6DSO_XL_UI_12Hz5_ULP:
11066 val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_ULP;
11067 break;
11068
11069 case LSM6DSO_XL_UI_26Hz_ULP:
11070 val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_ULP;
11071 break;
11072
11073 case LSM6DSO_XL_UI_52Hz_ULP:
11074 val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_ULP;
11075 break;
11076
11077 case LSM6DSO_XL_UI_104Hz_ULP:
11078 val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_ULP;
11079 break;
11080
11081 case LSM6DSO_XL_UI_208Hz_ULP:
11082 val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_ULP;
11083 break;
11084
11085 default:
11086 val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
11087 break;
11088 }
11089
11090 switch (ctrl1_xl.fs_xl)
11091 {
11092 case LSM6DSO_XL_UI_2g:
11093 val->ui.xl.fs = LSM6DSO_XL_UI_2g;
11094 break;
11095
11096 case LSM6DSO_XL_UI_4g:
11097 val->ui.xl.fs = LSM6DSO_XL_UI_4g;
11098 break;
11099
11100 case LSM6DSO_XL_UI_8g:
11101 val->ui.xl.fs = LSM6DSO_XL_UI_8g;
11102 break;
11103
11104 case LSM6DSO_XL_UI_16g:
11105 val->ui.xl.fs = LSM6DSO_XL_UI_16g;
11106 break;
11107
11108 default:
11109 val->ui.xl.fs = LSM6DSO_XL_UI_2g;
11110 break;
11111 }
11112
11113 /* get gyroscope configuration */
11114 switch ((ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g)
11115 {
11116 case LSM6DSO_GY_UI_OFF:
11117 val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
11118 break;
11119
11120 case LSM6DSO_GY_UI_12Hz5_LP:
11121 val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_LP;
11122 break;
11123
11124 case LSM6DSO_GY_UI_12Hz5_HP:
11125 val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_HP;
11126 break;
11127
11128 case LSM6DSO_GY_UI_26Hz_LP:
11129 val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_LP;
11130 break;
11131
11132 case LSM6DSO_GY_UI_26Hz_HP:
11133 val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_HP;
11134 break;
11135
11136 case LSM6DSO_GY_UI_52Hz_LP:
11137 val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_LP;
11138 break;
11139
11140 case LSM6DSO_GY_UI_52Hz_HP:
11141 val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_HP;
11142 break;
11143
11144 case LSM6DSO_GY_UI_104Hz_NM:
11145 val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_NM;
11146 break;
11147
11148 case LSM6DSO_GY_UI_104Hz_HP:
11149 val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_HP;
11150 break;
11151
11152 case LSM6DSO_GY_UI_208Hz_NM:
11153 val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_NM;
11154 break;
11155
11156 case LSM6DSO_GY_UI_208Hz_HP:
11157 val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_HP;
11158 break;
11159
11160 case LSM6DSO_GY_UI_416Hz_HP:
11161 val->ui.gy.odr = LSM6DSO_GY_UI_416Hz_HP;
11162 break;
11163
11164 case LSM6DSO_GY_UI_833Hz_HP:
11165 val->ui.gy.odr = LSM6DSO_GY_UI_833Hz_HP;
11166 break;
11167
11168 case LSM6DSO_GY_UI_1667Hz_HP:
11169 val->ui.gy.odr = LSM6DSO_GY_UI_1667Hz_HP;
11170 break;
11171
11172 case LSM6DSO_GY_UI_3333Hz_HP:
11173 val->ui.gy.odr = LSM6DSO_GY_UI_3333Hz_HP;
11174 break;
11175
11176 case LSM6DSO_GY_UI_6667Hz_HP:
11177 val->ui.gy.odr = LSM6DSO_GY_UI_6667Hz_HP;
11178 break;
11179
11180 default:
11181 val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
11182 break;
11183 }
11184
11185 switch (ctrl2_g.fs_g)
11186 {
11187 case LSM6DSO_GY_UI_125dps:
11188 val->ui.gy.fs = LSM6DSO_GY_UI_125dps;
11189 break;
11190
11191 case LSM6DSO_GY_UI_250dps:
11192 val->ui.gy.fs = LSM6DSO_GY_UI_250dps;
11193 break;
11194
11195 case LSM6DSO_GY_UI_500dps:
11196 val->ui.gy.fs = LSM6DSO_GY_UI_500dps;
11197 break;
11198
11199 case LSM6DSO_GY_UI_1000dps:
11200 val->ui.gy.fs = LSM6DSO_GY_UI_1000dps;
11201 break;
11202
11203 case LSM6DSO_GY_UI_2000dps:
11204 val->ui.gy.fs = LSM6DSO_GY_UI_2000dps;
11205 break;
11206
11207 default:
11208 val->ui.gy.fs = LSM6DSO_GY_UI_125dps;
11209 break;
11210 }
11211
11212 /* get finite state machine configuration */
11213 if ((fsm_enable_a.fsm1_en | fsm_enable_a.fsm2_en |
11214 fsm_enable_a.fsm3_en |
11215 fsm_enable_a.fsm4_en | fsm_enable_a.fsm5_en | fsm_enable_a.fsm6_en |
11216 fsm_enable_a.fsm7_en | fsm_enable_a.fsm8_en | fsm_enable_b.fsm9_en |
11217 fsm_enable_b.fsm10_en | fsm_enable_b.fsm11_en |
11218 fsm_enable_b.fsm12_en | fsm_enable_b.fsm13_en |
11219 fsm_enable_b.fsm14_en | fsm_enable_b.fsm15_en |
11220 fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
11221 {
11222 switch (emb_func_odr_cfg_b.fsm_odr)
11223 {
11224 case LSM6DSO_FSM_12Hz5:
11225 val->fsm.odr = LSM6DSO_FSM_12Hz5;
11226 break;
11227
11228 case LSM6DSO_FSM_26Hz:
11229 val->fsm.odr = LSM6DSO_FSM_26Hz;
11230 break;
11231
11232 case LSM6DSO_FSM_52Hz:
11233 val->fsm.odr = LSM6DSO_FSM_52Hz;
11234 break;
11235
11236 case LSM6DSO_FSM_104Hz:
11237 val->fsm.odr = LSM6DSO_FSM_104Hz;
11238 break;
11239
11240 default:
11241 val->fsm.odr = LSM6DSO_FSM_12Hz5;
11242 break;
11243 }
11244
11245 val->fsm.sens = LSM6DSO_FSM_XL_GY;
11246
11247 if (val->ui.gy.odr == LSM6DSO_GY_UI_OFF)
11248 {
11249 val->fsm.sens = LSM6DSO_FSM_XL;
11250 }
11251
11252 if (val->ui.xl.odr == LSM6DSO_XL_UI_OFF)
11253 {
11254 val->fsm.sens = LSM6DSO_FSM_GY;
11255 }
11256 }
11257
11258 else
11259 {
11260 val->fsm.sens = LSM6DSO_FSM_DISABLE;
11261 }
11262
11263 /* get ois configuration */
11264
11265 /* OIS configuration mode */
11266 switch (ctrl7_g.ois_on_en)
11267 {
11268 case LSM6DSO_OIS_ONLY_AUX:
11269 switch (ctrl3_ois.fs_xl_ois)
11270 {
11271 case LSM6DSO_XL_OIS_2g:
11272 val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
11273 break;
11274
11275 case LSM6DSO_XL_OIS_4g:
11276 val->ois.xl.fs = LSM6DSO_XL_OIS_4g;
11277 break;
11278
11279 case LSM6DSO_XL_OIS_8g:
11280 val->ois.xl.fs = LSM6DSO_XL_OIS_8g;
11281 break;
11282
11283 case LSM6DSO_XL_OIS_16g:
11284 val->ois.xl.fs = LSM6DSO_XL_OIS_16g;
11285 break;
11286
11287 default:
11288 val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
11289 break;
11290 }
11291
11292 switch (ctrl1_ois.mode4_en)
11293 {
11294 case LSM6DSO_XL_OIS_OFF:
11295 val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
11296 break;
11297
11298 case LSM6DSO_XL_OIS_6667Hz_HP:
11299 val->ois.xl.odr = LSM6DSO_XL_OIS_6667Hz_HP;
11300 break;
11301
11302 default:
11303 val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
11304 break;
11305 }
11306
11307 switch (ctrl1_ois.fs_g_ois)
11308 {
11309 case LSM6DSO_GY_OIS_250dps:
11310 val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
11311 break;
11312
11313 case LSM6DSO_GY_OIS_500dps:
11314 val->ois.gy.fs = LSM6DSO_GY_OIS_500dps;
11315 break;
11316
11317 case LSM6DSO_GY_OIS_1000dps:
11318 val->ois.gy.fs = LSM6DSO_GY_OIS_1000dps;
11319 break;
11320
11321 case LSM6DSO_GY_OIS_2000dps:
11322 val->ois.gy.fs = LSM6DSO_GY_OIS_2000dps;
11323 break;
11324
11325 default:
11326 val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
11327 break;
11328 }
11329
11330 switch (ctrl1_ois.ois_en_spi2)
11331 {
11332 case LSM6DSO_GY_OIS_OFF:
11333 val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
11334 break;
11335
11336 case LSM6DSO_GY_OIS_6667Hz_HP:
11337 val->ois.gy.odr = LSM6DSO_GY_OIS_6667Hz_HP;
11338 break;
11339
11340 default:
11341 val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
11342 break;
11343 }
11344
11345 val->ois.ctrl_md = LSM6DSO_OIS_ONLY_AUX;
11346 break;
11347
11348 case LSM6DSO_OIS_MIXED:
11349 switch (ctrl3_ois.fs_xl_ois)
11350 {
11351 case LSM6DSO_XL_OIS_2g:
11352 val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
11353 break;
11354
11355 case LSM6DSO_XL_OIS_4g:
11356 val->ois.xl.fs = LSM6DSO_XL_OIS_4g;
11357 break;
11358
11359 case LSM6DSO_XL_OIS_8g:
11360 val->ois.xl.fs = LSM6DSO_XL_OIS_8g;
11361 break;
11362
11363 case LSM6DSO_XL_OIS_16g:
11364 val->ois.xl.fs = LSM6DSO_XL_OIS_16g;
11365 break;
11366
11367 default:
11368 val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
11369 break;
11370 }
11371
11372 switch (ctrl1_ois.mode4_en)
11373 {
11374 case LSM6DSO_XL_OIS_OFF:
11375 val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
11376 break;
11377
11378 case LSM6DSO_XL_OIS_6667Hz_HP:
11379 val->ois.xl.odr = LSM6DSO_XL_OIS_6667Hz_HP;
11380 break;
11381
11382 default:
11383 val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
11384 break;
11385 }
11386
11387 switch (ctrl1_ois.fs_g_ois)
11388 {
11389 case LSM6DSO_GY_OIS_250dps:
11390 val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
11391 break;
11392
11393 case LSM6DSO_GY_OIS_500dps:
11394 val->ois.gy.fs = LSM6DSO_GY_OIS_500dps;
11395 break;
11396
11397 case LSM6DSO_GY_OIS_1000dps:
11398 val->ois.gy.fs = LSM6DSO_GY_OIS_1000dps;
11399 break;
11400
11401 case LSM6DSO_GY_OIS_2000dps:
11402 val->ois.gy.fs = LSM6DSO_GY_OIS_2000dps;
11403 break;
11404
11405 default:
11406 val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
11407 break;
11408 }
11409
11410 switch (ctrl1_ois.ois_en_spi2)
11411 {
11412 case LSM6DSO_GY_OIS_OFF:
11413 val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
11414 break;
11415
11416 case LSM6DSO_GY_OIS_6667Hz_HP:
11417 val->ois.gy.odr = LSM6DSO_GY_OIS_6667Hz_HP;
11418 break;
11419
11420 default:
11421 val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
11422 break;
11423 }
11424
11425 val->ois.ctrl_md = LSM6DSO_OIS_MIXED;
11426 break;
11427
11428 default:
11429 val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
11430 val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
11431 val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
11432 val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
11433 val->ois.ctrl_md = LSM6DSO_OIS_ONLY_AUX;
11434 break;
11435 }
11436
11437 return ret;
11438 }
11439
11440 /**
11441 * @brief Read data in engineering unit.[get]
11442 *
11443 * @param ctx communication interface handler.(ptr)
11444 * @param md the sensor conversion parameters.(ptr)
11445 * @retval interface status (MANDATORY: return 0 -> no Error)
11446 *
11447 */
lsm6dso_data_get(const stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dso_md_t * md,lsm6dso_data_t * data)11448 int32_t lsm6dso_data_get(const stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
11449 lsm6dso_md_t *md, lsm6dso_data_t *data)
11450 {
11451 uint8_t buff[14];
11452 int32_t ret;
11453
11454 uint8_t i;
11455 uint8_t j;
11456 ret = 0;
11457
11458 /* read data */
11459 if (ctx != NULL)
11460 {
11461 ret = lsm6dso_read_reg(ctx, LSM6DSO_OUT_TEMP_L, buff, 14);
11462 if (ret != 0) { return ret; }
11463 }
11464
11465 j = 0;
11466 /* temperature conversion */
11467 data->ui.heat.raw = (int16_t)buff[j + 1U];
11468 data->ui.heat.raw = (((int16_t)data->ui.heat.raw * (int16_t)256) +
11469 (int16_t)buff[j]);
11470 j += 2U;
11471 data->ui.heat.deg_c = lsm6dso_from_lsb_to_celsius((
11472 int16_t)data->ui.heat.raw);
11473
11474 /* angular rate conversion */
11475 for (i = 0U; i < 3U; i++)
11476 {
11477 data->ui.gy.raw[i] = (int16_t)buff[j + 1U];
11478 data->ui.gy.raw[i] = (data->ui.gy.raw[i] * 256) + (int16_t) buff[j];
11479 j += 2U;
11480
11481 switch (md->ui.gy.fs)
11482 {
11483 case LSM6DSO_GY_UI_250dps:
11484 data->ui.gy.mdps[i] = lsm6dso_from_fs250_to_mdps(data->ui.gy.raw[i]);
11485 break;
11486
11487 case LSM6DSO_GY_UI_125dps:
11488 data->ui.gy.mdps[i] = lsm6dso_from_fs125_to_mdps(data->ui.gy.raw[i]);
11489 break;
11490
11491 case LSM6DSO_GY_UI_500dps:
11492 data->ui.gy.mdps[i] = lsm6dso_from_fs500_to_mdps(data->ui.gy.raw[i]);
11493 break;
11494
11495 case LSM6DSO_GY_UI_1000dps:
11496 data->ui.gy.mdps[i] = lsm6dso_from_fs1000_to_mdps(data->ui.gy.raw[i]);
11497 break;
11498
11499 case LSM6DSO_GY_UI_2000dps:
11500 data->ui.gy.mdps[i] = lsm6dso_from_fs2000_to_mdps(data->ui.gy.raw[i]);
11501 break;
11502
11503 default:
11504 data->ui.gy.mdps[i] = 0.0f;
11505 break;
11506 }
11507 }
11508
11509 /* acceleration conversion */
11510 for (i = 0U; i < 3U; i++)
11511 {
11512 data->ui.xl.raw[i] = (int16_t)buff[j + 1U];
11513 data->ui.xl.raw[i] = (data->ui.xl.raw[i] * 256) + (int16_t) buff[j];
11514 j += 2U;
11515
11516 switch (md->ui.xl.fs)
11517 {
11518 case LSM6DSO_XL_UI_2g:
11519 data->ui.xl.mg[i] = lsm6dso_from_fs2_to_mg(data->ui.xl.raw[i]);
11520 break;
11521
11522 case LSM6DSO_XL_UI_4g:
11523 data->ui.xl.mg[i] = lsm6dso_from_fs4_to_mg(data->ui.xl.raw[i]);
11524 break;
11525
11526 case LSM6DSO_XL_UI_8g:
11527 data->ui.xl.mg[i] = lsm6dso_from_fs8_to_mg(data->ui.xl.raw[i]);
11528 break;
11529
11530 case LSM6DSO_XL_UI_16g:
11531 data->ui.xl.mg[i] = lsm6dso_from_fs16_to_mg(data->ui.xl.raw[i]);
11532 break;
11533
11534 default:
11535 data->ui.xl.mg[i] = 0.0f;
11536 break;
11537 }
11538 }
11539
11540 /* read data from ois chain */
11541 if (aux_ctx != NULL)
11542 {
11543 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_OUTX_L_G, buff, 12);
11544 if (ret != 0) { return ret; }
11545 }
11546
11547 j = 0;
11548
11549 /* ois angular rate conversion */
11550 for (i = 0U; i < 3U; i++)
11551 {
11552 data->ois.gy.raw[i] = (int16_t) buff[j + 1U];
11553 data->ois.gy.raw[i] = (data->ois.gy.raw[i] * 256) + (int16_t) buff[j];
11554 j += 2U;
11555
11556 switch (md->ois.gy.fs)
11557 {
11558 case LSM6DSO_GY_UI_250dps:
11559 data->ois.gy.mdps[i] = lsm6dso_from_fs250_to_mdps(data->ois.gy.raw[i]);
11560 break;
11561
11562 case LSM6DSO_GY_UI_125dps:
11563 data->ois.gy.mdps[i] = lsm6dso_from_fs125_to_mdps(data->ois.gy.raw[i]);
11564 break;
11565
11566 case LSM6DSO_GY_UI_500dps:
11567 data->ois.gy.mdps[i] = lsm6dso_from_fs500_to_mdps(data->ois.gy.raw[i]);
11568 break;
11569
11570 case LSM6DSO_GY_UI_1000dps:
11571 data->ois.gy.mdps[i] = lsm6dso_from_fs1000_to_mdps(data->ois.gy.raw[i]);
11572 break;
11573
11574 case LSM6DSO_GY_UI_2000dps:
11575 data->ois.gy.mdps[i] = lsm6dso_from_fs2000_to_mdps(data->ois.gy.raw[i]);
11576 break;
11577
11578 default:
11579 data->ois.gy.mdps[i] = 0.0f;
11580 break;
11581 }
11582 }
11583
11584 /* ois acceleration conversion */
11585 for (i = 0U; i < 3U; i++)
11586 {
11587 data->ois.xl.raw[i] = (int16_t) buff[j + 1U];
11588 data->ois.xl.raw[i] = (data->ois.xl.raw[i] * 256) + (int16_t) buff[j];
11589 j += 2U;
11590
11591 switch (md->ois.xl.fs)
11592 {
11593 case LSM6DSO_XL_UI_2g:
11594 data->ois.xl.mg[i] = lsm6dso_from_fs2_to_mg(data->ois.xl.raw[i]);
11595 break;
11596
11597 case LSM6DSO_XL_UI_4g:
11598 data->ois.xl.mg[i] = lsm6dso_from_fs4_to_mg(data->ois.xl.raw[i]);
11599 break;
11600
11601 case LSM6DSO_XL_UI_8g:
11602 data->ois.xl.mg[i] = lsm6dso_from_fs8_to_mg(data->ois.xl.raw[i]);
11603 break;
11604
11605 case LSM6DSO_XL_UI_16g:
11606 data->ois.xl.mg[i] = lsm6dso_from_fs16_to_mg(data->ois.xl.raw[i]);
11607 break;
11608
11609 default:
11610 data->ois.xl.mg[i] = 0.0f;
11611 break;
11612 }
11613 }
11614
11615 return ret;
11616 }
11617 /**
11618 * @brief Embedded functions.[set]
11619 *
11620 * @param ctx read / write interface definitions
11621 * @param val change the values of registers
11622 * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
11623 * @retval interface status (MANDATORY: return 0 -> no Error)
11624 *
11625 */
lsm6dso_embedded_sens_set(const stmdev_ctx_t * ctx,lsm6dso_emb_sens_t * val)11626 int32_t lsm6dso_embedded_sens_set(const stmdev_ctx_t *ctx,
11627 lsm6dso_emb_sens_t *val)
11628 {
11629 lsm6dso_emb_func_en_a_t emb_func_en_a;
11630 lsm6dso_emb_func_en_b_t emb_func_en_b;
11631 int32_t ret;
11632
11633 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
11634 if (ret != 0) { return ret; }
11635
11636 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
11637 ret += lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
11638 if (ret != 0) { goto exit; }
11639
11640 emb_func_en_b.fsm_en = val->fsm;
11641 emb_func_en_a.tilt_en = val->tilt;
11642 emb_func_en_a.pedo_en = val->step;
11643 emb_func_en_b.pedo_adv_en = val->step_adv;
11644 emb_func_en_a.sign_motion_en = val->sig_mot;
11645 emb_func_en_b.fifo_compr_en = val->fifo_compr;
11646
11647 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
11648 ret += lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
11649
11650 exit:
11651 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
11652
11653 return ret;
11654 }
11655
11656 /**
11657 * @brief Embedded functions.[get]
11658 *
11659 * @param ctx read / write interface definitions
11660 * @param val get the values of registers
11661 * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
11662 * @retval interface status (MANDATORY: return 0 -> no Error)
11663 *
11664 */
lsm6dso_embedded_sens_get(const stmdev_ctx_t * ctx,lsm6dso_emb_sens_t * emb_sens)11665 int32_t lsm6dso_embedded_sens_get(const stmdev_ctx_t *ctx,
11666 lsm6dso_emb_sens_t *emb_sens)
11667 {
11668 lsm6dso_emb_func_en_a_t emb_func_en_a;
11669 lsm6dso_emb_func_en_b_t emb_func_en_b;
11670 int32_t ret;
11671
11672 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
11673 if (ret != 0) { return ret; }
11674
11675 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
11676 ret += lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
11677
11678 emb_sens->fsm = emb_func_en_b.fsm_en;
11679 emb_sens->tilt = emb_func_en_a.tilt_en;
11680 emb_sens->step = emb_func_en_a.pedo_en;
11681 emb_sens->step_adv = emb_func_en_b.pedo_adv_en;
11682 emb_sens->sig_mot = emb_func_en_a.sign_motion_en;
11683 emb_sens->fifo_compr = emb_func_en_b.fifo_compr_en;
11684
11685 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
11686
11687 return ret;
11688 }
11689
11690 /**
11691 * @brief turn off all embedded functions.[get]
11692 *
11693 * @param ctx read / write interface definitions
11694 * @param val get the values of registers
11695 * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
11696 * @retval interface status (MANDATORY: return 0 -> no Error)
11697 *
11698 */
lsm6dso_embedded_sens_off(const stmdev_ctx_t * ctx)11699 int32_t lsm6dso_embedded_sens_off(const stmdev_ctx_t *ctx)
11700 {
11701 lsm6dso_emb_func_en_a_t emb_func_en_a;
11702 lsm6dso_emb_func_en_b_t emb_func_en_b;
11703 int32_t ret;
11704
11705 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
11706 if (ret != 0) { return ret; }
11707
11708 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
11709 ret += lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
11710 if (ret != 0) { goto exit; }
11711
11712 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
11713 emb_func_en_a.tilt_en = PROPERTY_DISABLE;
11714 emb_func_en_a.pedo_en = PROPERTY_DISABLE;
11715 emb_func_en_b.pedo_adv_en = PROPERTY_DISABLE;
11716 emb_func_en_a.sign_motion_en = PROPERTY_DISABLE;
11717 emb_func_en_b.fifo_compr_en = PROPERTY_DISABLE;
11718
11719 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A, (uint8_t *)&emb_func_en_a, 1);
11720 ret += lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B, (uint8_t *)&emb_func_en_b, 1);
11721
11722 exit:
11723 ret += lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
11724
11725 return ret;
11726 }
11727
11728 /**
11729 * @}
11730 *
11731 */
11732
11733 /**
11734 * @}
11735 *
11736 */
11737
11738 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
11739
