1 /**
2 ******************************************************************************
3 * @file lsm6dso_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSO driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dso_reg.h"
21 #include <stddef.h>
22
23 /**
24 * @defgroup LSM6DSO
25 * @brief This file provides a set of functions needed to drive the
26 * lsm6dso enhanced inertial module.
27 * @{
28 *
29 */
30
31 /**
32 * @defgroup LSM6DSO_Interfaces_Functions
33 * @brief This section provide a set of functions used to read and
34 * write a generic register of the device.
35 * MANDATORY: return 0 -> no Error.
36 * @{
37 *
38 */
39
40 /**
41 * @brief Read generic device register
42 *
43 * @param ctx read / write interface definitions(ptr)
44 * @param reg register to read
45 * @param data pointer to buffer that store the data read(ptr)
46 * @param len number of consecutive register to read
47 * @retval interface status (MANDATORY: return 0 -> no Error)
48 *
49 */
lsm6dso_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)50 int32_t lsm6dso_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
51 uint8_t *data,
52 uint16_t len)
53 {
54 int32_t ret;
55
56 ret = ctx->read_reg(ctx->handle, reg, data, len);
57
58 return ret;
59 }
60
61 /**
62 * @brief Write generic device register
63 *
64 * @param ctx read / write interface definitions(ptr)
65 * @param reg register to write
66 * @param data pointer to data to write in register reg(ptr)
67 * @param len number of consecutive register to write
68 * @retval interface status (MANDATORY: return 0 -> no Error)
69 *
70 */
lsm6dso_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)71 int32_t lsm6dso_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
72 uint8_t *data,
73 uint16_t len)
74 {
75 int32_t ret;
76
77 ret = ctx->write_reg(ctx->handle, reg, data, len);
78
79 return ret;
80 }
81
82 /**
83 * @}
84 *
85 */
86
87 /**
88 * @defgroup LSM6DSOX_Private_functions
89 * @brief Section collect all the utility functions needed by APIs.
90 * @{
91 *
92 */
93
bytecpy(uint8_t * target,uint8_t * source)94 static void bytecpy(uint8_t *target, uint8_t *source)
95 {
96 if ((target != NULL) && (source != NULL))
97 {
98 *target = *source;
99 }
100 }
101
102 /**
103 * @defgroup LSM6DSO_Sensitivity
104 * @brief These functions convert raw-data into engineering units.
105 * @{
106 *
107 */
lsm6dso_from_fs2_to_mg(int16_t lsb)108 float_t lsm6dso_from_fs2_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb) * 0.061f;
111 }
112
lsm6dso_from_fs4_to_mg(int16_t lsb)113 float_t lsm6dso_from_fs4_to_mg(int16_t lsb)
114 {
115 return ((float_t)lsb) * 0.122f;
116 }
117
lsm6dso_from_fs8_to_mg(int16_t lsb)118 float_t lsm6dso_from_fs8_to_mg(int16_t lsb)
119 {
120 return ((float_t)lsb) * 0.244f;
121 }
122
lsm6dso_from_fs16_to_mg(int16_t lsb)123 float_t lsm6dso_from_fs16_to_mg(int16_t lsb)
124 {
125 return ((float_t)lsb) * 0.488f;
126 }
127
lsm6dso_from_fs125_to_mdps(int16_t lsb)128 float_t lsm6dso_from_fs125_to_mdps(int16_t lsb)
129 {
130 return ((float_t)lsb) * 4.375f;
131 }
132
lsm6dso_from_fs500_to_mdps(int16_t lsb)133 float_t lsm6dso_from_fs500_to_mdps(int16_t lsb)
134 {
135 return ((float_t)lsb) * 17.50f;
136 }
137
lsm6dso_from_fs250_to_mdps(int16_t lsb)138 float_t lsm6dso_from_fs250_to_mdps(int16_t lsb)
139 {
140 return ((float_t)lsb) * 8.750f;
141 }
142
lsm6dso_from_fs1000_to_mdps(int16_t lsb)143 float_t lsm6dso_from_fs1000_to_mdps(int16_t lsb)
144 {
145 return ((float_t)lsb) * 35.0f;
146 }
147
lsm6dso_from_fs2000_to_mdps(int16_t lsb)148 float_t lsm6dso_from_fs2000_to_mdps(int16_t lsb)
149 {
150 return ((float_t)lsb) * 70.0f;
151 }
152
lsm6dso_from_lsb_to_celsius(int16_t lsb)153 float_t lsm6dso_from_lsb_to_celsius(int16_t lsb)
154 {
155 return (((float_t)lsb / 256.0f) + 25.0f);
156 }
157
lsm6dso_from_lsb_to_nsec(int16_t lsb)158 float_t lsm6dso_from_lsb_to_nsec(int16_t lsb)
159 {
160 return ((float_t)lsb * 25000.0f);
161 }
162
163 /**
164 * @}
165 *
166 */
167
168 /**
169 * @defgroup LSM6DSO_Data_Generation
170 * @brief This section groups all the functions concerning
171 * data generation.
172 *
173 */
174
175 /**
176 * @brief Accelerometer full-scale selection.[set]
177 *
178 * @param ctx read / write interface definitions
179 * @param val change the values of fs_xl in reg CTRL1_XL
180 * @retval interface status (MANDATORY: return 0 -> no Error)
181 *
182 */
lsm6dso_xl_full_scale_set(stmdev_ctx_t * ctx,lsm6dso_fs_xl_t val)183 int32_t lsm6dso_xl_full_scale_set(stmdev_ctx_t *ctx,
184 lsm6dso_fs_xl_t val)
185 {
186 lsm6dso_ctrl1_xl_t reg;
187 int32_t ret;
188
189 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
190
191 if (ret == 0)
192 {
193 reg.fs_xl = (uint8_t) val;
194 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
195 }
196
197 return ret;
198 }
199
200 /**
201 * @brief Accelerometer full-scale selection.[get]
202 *
203 * @param ctx read / write interface definitions
204 * @param val Get the values of fs_xl in reg CTRL1_XL
205 * @retval interface status (MANDATORY: return 0 -> no Error)
206 *
207 */
lsm6dso_xl_full_scale_get(stmdev_ctx_t * ctx,lsm6dso_fs_xl_t * val)208 int32_t lsm6dso_xl_full_scale_get(stmdev_ctx_t *ctx,
209 lsm6dso_fs_xl_t *val)
210 {
211 lsm6dso_ctrl1_xl_t reg;
212 int32_t ret;
213
214 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
215
216 switch (reg.fs_xl)
217 {
218 case LSM6DSO_2g:
219 *val = LSM6DSO_2g;
220 break;
221
222 case LSM6DSO_16g:
223 *val = LSM6DSO_16g;
224 break;
225
226 case LSM6DSO_4g:
227 *val = LSM6DSO_4g;
228 break;
229
230 case LSM6DSO_8g:
231 *val = LSM6DSO_8g;
232 break;
233
234 default:
235 *val = LSM6DSO_2g;
236 break;
237 }
238
239 return ret;
240 }
241
242 /**
243 * @brief Accelerometer UI data rate selection.[set]
244 *
245 * @param ctx read / write interface definitions
246 * @param val change the values of odr_xl in reg CTRL1_XL
247 * @retval interface status (MANDATORY: return 0 -> no Error)
248 *
249 */
lsm6dso_xl_data_rate_set(stmdev_ctx_t * ctx,lsm6dso_odr_xl_t val)250 int32_t lsm6dso_xl_data_rate_set(stmdev_ctx_t *ctx,
251 lsm6dso_odr_xl_t val)
252 {
253 lsm6dso_odr_xl_t odr_xl = val;
254 lsm6dso_emb_fsm_enable_t fsm_enable;
255 lsm6dso_fsm_odr_t fsm_odr;
256 lsm6dso_ctrl1_xl_t reg;
257 int32_t ret;
258
259 /* Check the Finite State Machine data rate constraints */
260 ret = lsm6dso_fsm_enable_get(ctx, &fsm_enable);
261
262 if (ret == 0)
263 {
264 if ((fsm_enable.fsm_enable_a.fsm1_en |
265 fsm_enable.fsm_enable_a.fsm2_en |
266 fsm_enable.fsm_enable_a.fsm3_en |
267 fsm_enable.fsm_enable_a.fsm4_en |
268 fsm_enable.fsm_enable_a.fsm5_en |
269 fsm_enable.fsm_enable_a.fsm6_en |
270 fsm_enable.fsm_enable_a.fsm7_en |
271 fsm_enable.fsm_enable_a.fsm8_en |
272 fsm_enable.fsm_enable_b.fsm9_en |
273 fsm_enable.fsm_enable_b.fsm10_en |
274 fsm_enable.fsm_enable_b.fsm11_en |
275 fsm_enable.fsm_enable_b.fsm12_en |
276 fsm_enable.fsm_enable_b.fsm13_en |
277 fsm_enable.fsm_enable_b.fsm14_en |
278 fsm_enable.fsm_enable_b.fsm15_en |
279 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
280 {
281 ret = lsm6dso_fsm_data_rate_get(ctx, &fsm_odr);
282
283 if (ret == 0)
284 {
285 switch (fsm_odr)
286 {
287 case LSM6DSO_ODR_FSM_12Hz5:
288 if (val == LSM6DSO_XL_ODR_OFF)
289 {
290 odr_xl = LSM6DSO_XL_ODR_12Hz5;
291 }
292
293 else
294 {
295 odr_xl = val;
296 }
297
298 break;
299
300 case LSM6DSO_ODR_FSM_26Hz:
301 if (val == LSM6DSO_XL_ODR_OFF)
302 {
303 odr_xl = LSM6DSO_XL_ODR_26Hz;
304 }
305
306 else if (val == LSM6DSO_XL_ODR_12Hz5)
307 {
308 odr_xl = LSM6DSO_XL_ODR_26Hz;
309 }
310
311 else
312 {
313 odr_xl = val;
314 }
315
316 break;
317
318 case LSM6DSO_ODR_FSM_52Hz:
319 if (val == LSM6DSO_XL_ODR_OFF)
320 {
321 odr_xl = LSM6DSO_XL_ODR_52Hz;
322 }
323
324 else if (val == LSM6DSO_XL_ODR_12Hz5)
325 {
326 odr_xl = LSM6DSO_XL_ODR_52Hz;
327 }
328
329 else if (val == LSM6DSO_XL_ODR_26Hz)
330 {
331 odr_xl = LSM6DSO_XL_ODR_52Hz;
332 }
333
334 else
335 {
336 odr_xl = val;
337 }
338
339 break;
340
341 case LSM6DSO_ODR_FSM_104Hz:
342 if (val == LSM6DSO_XL_ODR_OFF)
343 {
344 odr_xl = LSM6DSO_XL_ODR_104Hz;
345 }
346
347 else if (val == LSM6DSO_XL_ODR_12Hz5)
348 {
349 odr_xl = LSM6DSO_XL_ODR_104Hz;
350 }
351
352 else if (val == LSM6DSO_XL_ODR_26Hz)
353 {
354 odr_xl = LSM6DSO_XL_ODR_104Hz;
355 }
356
357 else if (val == LSM6DSO_XL_ODR_52Hz)
358 {
359 odr_xl = LSM6DSO_XL_ODR_104Hz;
360 }
361
362 else
363 {
364 odr_xl = val;
365 }
366
367 break;
368
369 default:
370 odr_xl = val;
371 break;
372 }
373 }
374 }
375 }
376
377 if (ret == 0)
378 {
379 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
380 }
381
382 if (ret == 0)
383 {
384 reg.odr_xl = (uint8_t) odr_xl;
385 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
386 }
387
388 return ret;
389 }
390
391 /**
392 * @brief Accelerometer UI data rate selection.[get]
393 *
394 * @param ctx read / write interface definitions
395 * @param val Get the values of odr_xl in reg CTRL1_XL
396 * @retval interface status (MANDATORY: return 0 -> no Error)
397 *
398 */
lsm6dso_xl_data_rate_get(stmdev_ctx_t * ctx,lsm6dso_odr_xl_t * val)399 int32_t lsm6dso_xl_data_rate_get(stmdev_ctx_t *ctx,
400 lsm6dso_odr_xl_t *val)
401 {
402 lsm6dso_ctrl1_xl_t reg;
403 int32_t ret;
404
405 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
406
407 switch (reg.odr_xl)
408 {
409 case LSM6DSO_XL_ODR_OFF:
410 *val = LSM6DSO_XL_ODR_OFF;
411 break;
412
413 case LSM6DSO_XL_ODR_12Hz5:
414 *val = LSM6DSO_XL_ODR_12Hz5;
415 break;
416
417 case LSM6DSO_XL_ODR_26Hz:
418 *val = LSM6DSO_XL_ODR_26Hz;
419 break;
420
421 case LSM6DSO_XL_ODR_52Hz:
422 *val = LSM6DSO_XL_ODR_52Hz;
423 break;
424
425 case LSM6DSO_XL_ODR_104Hz:
426 *val = LSM6DSO_XL_ODR_104Hz;
427 break;
428
429 case LSM6DSO_XL_ODR_208Hz:
430 *val = LSM6DSO_XL_ODR_208Hz;
431 break;
432
433 case LSM6DSO_XL_ODR_417Hz:
434 *val = LSM6DSO_XL_ODR_417Hz;
435 break;
436
437 case LSM6DSO_XL_ODR_833Hz:
438 *val = LSM6DSO_XL_ODR_833Hz;
439 break;
440
441 case LSM6DSO_XL_ODR_1667Hz:
442 *val = LSM6DSO_XL_ODR_1667Hz;
443 break;
444
445 case LSM6DSO_XL_ODR_3333Hz:
446 *val = LSM6DSO_XL_ODR_3333Hz;
447 break;
448
449 case LSM6DSO_XL_ODR_6667Hz:
450 *val = LSM6DSO_XL_ODR_6667Hz;
451 break;
452
453 case LSM6DSO_XL_ODR_1Hz6:
454 *val = LSM6DSO_XL_ODR_1Hz6;
455 break;
456
457 default:
458 *val = LSM6DSO_XL_ODR_OFF;
459 break;
460 }
461
462 return ret;
463 }
464
465 /**
466 * @brief Gyroscope UI chain full-scale selection.[set]
467 *
468 * @param ctx read / write interface definitions
469 * @param val change the values of fs_g in reg CTRL2_G
470 * @retval interface status (MANDATORY: return 0 -> no Error)
471 *
472 */
lsm6dso_gy_full_scale_set(stmdev_ctx_t * ctx,lsm6dso_fs_g_t val)473 int32_t lsm6dso_gy_full_scale_set(stmdev_ctx_t *ctx,
474 lsm6dso_fs_g_t val)
475 {
476 lsm6dso_ctrl2_g_t reg;
477 int32_t ret;
478
479 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1);
480
481 if (ret == 0)
482 {
483 reg.fs_g = (uint8_t) val;
484 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1);
485 }
486
487 return ret;
488 }
489
490 /**
491 * @brief Gyroscope UI chain full-scale selection.[get]
492 *
493 * @param ctx read / write interface definitions
494 * @param val Get the values of fs_g in reg CTRL2_G
495 * @retval interface status (MANDATORY: return 0 -> no Error)
496 *
497 */
lsm6dso_gy_full_scale_get(stmdev_ctx_t * ctx,lsm6dso_fs_g_t * val)498 int32_t lsm6dso_gy_full_scale_get(stmdev_ctx_t *ctx,
499 lsm6dso_fs_g_t *val)
500 {
501 lsm6dso_ctrl2_g_t reg;
502 int32_t ret;
503
504 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1);
505
506 switch (reg.fs_g)
507 {
508 case LSM6DSO_250dps:
509 *val = LSM6DSO_250dps;
510 break;
511
512 case LSM6DSO_125dps:
513 *val = LSM6DSO_125dps;
514 break;
515
516 case LSM6DSO_500dps:
517 *val = LSM6DSO_500dps;
518 break;
519
520 case LSM6DSO_1000dps:
521 *val = LSM6DSO_1000dps;
522 break;
523
524 case LSM6DSO_2000dps:
525 *val = LSM6DSO_2000dps;
526 break;
527
528 default:
529 *val = LSM6DSO_250dps;
530 break;
531 }
532
533 return ret;
534 }
535
536 /**
537 * @brief Gyroscope UI data rate selection.[set]
538 *
539 * @param ctx read / write interface definitions
540 * @param val change the values of odr_g in reg CTRL2_G
541 * @retval interface status (MANDATORY: return 0 -> no Error)
542 *
543 */
lsm6dso_gy_data_rate_set(stmdev_ctx_t * ctx,lsm6dso_odr_g_t val)544 int32_t lsm6dso_gy_data_rate_set(stmdev_ctx_t *ctx,
545 lsm6dso_odr_g_t val)
546 {
547 lsm6dso_odr_g_t odr_gy = val;
548 lsm6dso_emb_fsm_enable_t fsm_enable;
549 lsm6dso_fsm_odr_t fsm_odr;
550 lsm6dso_ctrl2_g_t reg;
551 int32_t ret;
552
553 /* Check the Finite State Machine data rate constraints */
554 ret = lsm6dso_fsm_enable_get(ctx, &fsm_enable);
555
556 if (ret == 0)
557 {
558 if ((fsm_enable.fsm_enable_a.fsm1_en |
559 fsm_enable.fsm_enable_a.fsm2_en |
560 fsm_enable.fsm_enable_a.fsm3_en |
561 fsm_enable.fsm_enable_a.fsm4_en |
562 fsm_enable.fsm_enable_a.fsm5_en |
563 fsm_enable.fsm_enable_a.fsm6_en |
564 fsm_enable.fsm_enable_a.fsm7_en |
565 fsm_enable.fsm_enable_a.fsm8_en |
566 fsm_enable.fsm_enable_b.fsm9_en |
567 fsm_enable.fsm_enable_b.fsm10_en |
568 fsm_enable.fsm_enable_b.fsm11_en |
569 fsm_enable.fsm_enable_b.fsm12_en |
570 fsm_enable.fsm_enable_b.fsm13_en |
571 fsm_enable.fsm_enable_b.fsm14_en |
572 fsm_enable.fsm_enable_b.fsm15_en |
573 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
574 {
575 ret = lsm6dso_fsm_data_rate_get(ctx, &fsm_odr);
576
577 if (ret == 0)
578 {
579 switch (fsm_odr)
580 {
581 case LSM6DSO_ODR_FSM_12Hz5:
582 if (val == LSM6DSO_GY_ODR_OFF)
583 {
584 odr_gy = LSM6DSO_GY_ODR_12Hz5;
585 }
586
587 else
588 {
589 odr_gy = val;
590 }
591
592 break;
593
594 case LSM6DSO_ODR_FSM_26Hz:
595 if (val == LSM6DSO_GY_ODR_OFF)
596 {
597 odr_gy = LSM6DSO_GY_ODR_26Hz;
598 }
599
600 else if (val == LSM6DSO_GY_ODR_12Hz5)
601 {
602 odr_gy = LSM6DSO_GY_ODR_26Hz;
603 }
604
605 else
606 {
607 odr_gy = val;
608 }
609
610 break;
611
612 case LSM6DSO_ODR_FSM_52Hz:
613 if (val == LSM6DSO_GY_ODR_OFF)
614 {
615 odr_gy = LSM6DSO_GY_ODR_52Hz;
616 }
617
618 else if (val == LSM6DSO_GY_ODR_12Hz5)
619 {
620 odr_gy = LSM6DSO_GY_ODR_52Hz;
621 }
622
623 else if (val == LSM6DSO_GY_ODR_26Hz)
624 {
625 odr_gy = LSM6DSO_GY_ODR_52Hz;
626 }
627
628 else
629 {
630 odr_gy = val;
631 }
632
633 break;
634
635 case LSM6DSO_ODR_FSM_104Hz:
636 if (val == LSM6DSO_GY_ODR_OFF)
637 {
638 odr_gy = LSM6DSO_GY_ODR_104Hz;
639 }
640
641 else if (val == LSM6DSO_GY_ODR_12Hz5)
642 {
643 odr_gy = LSM6DSO_GY_ODR_104Hz;
644 }
645
646 else if (val == LSM6DSO_GY_ODR_26Hz)
647 {
648 odr_gy = LSM6DSO_GY_ODR_104Hz;
649 }
650
651 else if (val == LSM6DSO_GY_ODR_52Hz)
652 {
653 odr_gy = LSM6DSO_GY_ODR_104Hz;
654 }
655
656 else
657 {
658 odr_gy = val;
659 }
660
661 break;
662
663 default:
664 odr_gy = val;
665 break;
666 }
667 }
668 }
669 }
670
671 if (ret == 0)
672 {
673 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1);
674 }
675
676 if (ret == 0)
677 {
678 reg.odr_g = (uint8_t) odr_gy;
679 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1);
680 }
681
682 return ret;
683 }
684
685 /**
686 * @brief Gyroscope UI data rate selection.[get]
687 *
688 * @param ctx read / write interface definitions
689 * @param val Get the values of odr_g in reg CTRL2_G
690 * @retval interface status (MANDATORY: return 0 -> no Error)
691 *
692 */
lsm6dso_gy_data_rate_get(stmdev_ctx_t * ctx,lsm6dso_odr_g_t * val)693 int32_t lsm6dso_gy_data_rate_get(stmdev_ctx_t *ctx,
694 lsm6dso_odr_g_t *val)
695 {
696 lsm6dso_ctrl2_g_t reg;
697 int32_t ret;
698
699 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_G, (uint8_t *)®, 1);
700
701 switch (reg.odr_g)
702 {
703 case LSM6DSO_GY_ODR_OFF:
704 *val = LSM6DSO_GY_ODR_OFF;
705 break;
706
707 case LSM6DSO_GY_ODR_12Hz5:
708 *val = LSM6DSO_GY_ODR_12Hz5;
709 break;
710
711 case LSM6DSO_GY_ODR_26Hz:
712 *val = LSM6DSO_GY_ODR_26Hz;
713 break;
714
715 case LSM6DSO_GY_ODR_52Hz:
716 *val = LSM6DSO_GY_ODR_52Hz;
717 break;
718
719 case LSM6DSO_GY_ODR_104Hz:
720 *val = LSM6DSO_GY_ODR_104Hz;
721 break;
722
723 case LSM6DSO_GY_ODR_208Hz:
724 *val = LSM6DSO_GY_ODR_208Hz;
725 break;
726
727 case LSM6DSO_GY_ODR_417Hz:
728 *val = LSM6DSO_GY_ODR_417Hz;
729 break;
730
731 case LSM6DSO_GY_ODR_833Hz:
732 *val = LSM6DSO_GY_ODR_833Hz;
733 break;
734
735 case LSM6DSO_GY_ODR_1667Hz:
736 *val = LSM6DSO_GY_ODR_1667Hz;
737 break;
738
739 case LSM6DSO_GY_ODR_3333Hz:
740 *val = LSM6DSO_GY_ODR_3333Hz;
741 break;
742
743 case LSM6DSO_GY_ODR_6667Hz:
744 *val = LSM6DSO_GY_ODR_6667Hz;
745 break;
746
747 default:
748 *val = LSM6DSO_GY_ODR_OFF;
749 break;
750 }
751
752 return ret;
753 }
754
755 /**
756 * @brief Block data update.[set]
757 *
758 * @param ctx read / write interface definitions
759 * @param val change the values of bdu in reg CTRL3_C
760 * @retval interface status (MANDATORY: return 0 -> no Error)
761 *
762 */
lsm6dso_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)763 int32_t lsm6dso_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
764 {
765 lsm6dso_ctrl3_c_t reg;
766 int32_t ret;
767
768 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
769
770 if (ret == 0)
771 {
772 reg.bdu = val;
773 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
774 }
775
776 return ret;
777 }
778
779 /**
780 * @brief Block data update.[get]
781 *
782 * @param ctx read / write interface definitions
783 * @param val change the values of bdu in reg CTRL3_C
784 * @retval interface status (MANDATORY: return 0 -> no Error)
785 *
786 */
lsm6dso_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)787 int32_t lsm6dso_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
788 {
789 lsm6dso_ctrl3_c_t reg;
790 int32_t ret;
791
792 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
793 *val = reg.bdu;
794
795 return ret;
796 }
797
798 /**
799 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
800 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
801 *
802 * @param ctx read / write interface definitions
803 * @param val change the values of usr_off_w in reg CTRL6_C
804 * @retval interface status (MANDATORY: return 0 -> no Error)
805 *
806 */
lsm6dso_xl_offset_weight_set(stmdev_ctx_t * ctx,lsm6dso_usr_off_w_t val)807 int32_t lsm6dso_xl_offset_weight_set(stmdev_ctx_t *ctx,
808 lsm6dso_usr_off_w_t val)
809 {
810 lsm6dso_ctrl6_c_t reg;
811 int32_t ret;
812
813 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
814
815 if (ret == 0)
816 {
817 reg.usr_off_w = (uint8_t)val;
818 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
819 }
820
821 return ret;
822 }
823
824 /**
825 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
826 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
827 *
828 * @param ctx read / write interface definitions
829 * @param val Get the values of usr_off_w in reg CTRL6_C
830 * @retval interface status (MANDATORY: return 0 -> no Error)
831 *
832 */
lsm6dso_xl_offset_weight_get(stmdev_ctx_t * ctx,lsm6dso_usr_off_w_t * val)833 int32_t lsm6dso_xl_offset_weight_get(stmdev_ctx_t *ctx,
834 lsm6dso_usr_off_w_t *val)
835 {
836 lsm6dso_ctrl6_c_t reg;
837 int32_t ret;
838
839 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
840
841 switch (reg.usr_off_w)
842 {
843 case LSM6DSO_LSb_1mg:
844 *val = LSM6DSO_LSb_1mg;
845 break;
846
847 case LSM6DSO_LSb_16mg:
848 *val = LSM6DSO_LSb_16mg;
849 break;
850
851 default:
852 *val = LSM6DSO_LSb_1mg;
853 break;
854 }
855
856 return ret;
857 }
858
859 /**
860 * @brief Accelerometer power mode.[set]
861 *
862 * @param ctx read / write interface definitions
863 * @param val change the values of xl_hm_mode in
864 * reg CTRL6_C
865 * @retval interface status (MANDATORY: return 0 -> no Error)
866 *
867 */
lsm6dso_xl_power_mode_set(stmdev_ctx_t * ctx,lsm6dso_xl_hm_mode_t val)868 int32_t lsm6dso_xl_power_mode_set(stmdev_ctx_t *ctx,
869 lsm6dso_xl_hm_mode_t val)
870 {
871 lsm6dso_ctrl5_c_t ctrl5_c;
872 lsm6dso_ctrl6_c_t ctrl6_c;
873 int32_t ret;
874
875 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
876
877 if (ret == 0)
878 {
879 ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x02U) >> 1;
880 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
881 }
882
883 if (ret == 0)
884 {
885 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
886 }
887
888 if (ret == 0)
889 {
890 ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
891 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
892 }
893
894 return ret;
895 }
896
897 /**
898 * @brief Accelerometer power mode.[get]
899 *
900 * @param ctx read / write interface definitions
901 * @param val Get the values of xl_hm_mode in reg CTRL6_C
902 * @retval interface status (MANDATORY: return 0 -> no Error)
903 *
904 */
lsm6dso_xl_power_mode_get(stmdev_ctx_t * ctx,lsm6dso_xl_hm_mode_t * val)905 int32_t lsm6dso_xl_power_mode_get(stmdev_ctx_t *ctx,
906 lsm6dso_xl_hm_mode_t *val)
907 {
908 lsm6dso_ctrl5_c_t ctrl5_c;
909 lsm6dso_ctrl6_c_t ctrl6_c;
910 int32_t ret;
911
912 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
913
914 if (ret == 0)
915 {
916 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
917
918 switch ((ctrl5_c.xl_ulp_en << 1) | ctrl6_c.xl_hm_mode)
919 {
920 case LSM6DSO_HIGH_PERFORMANCE_MD:
921 *val = LSM6DSO_HIGH_PERFORMANCE_MD;
922 break;
923
924 case LSM6DSO_LOW_NORMAL_POWER_MD:
925 *val = LSM6DSO_LOW_NORMAL_POWER_MD;
926 break;
927
928 case LSM6DSO_ULTRA_LOW_POWER_MD:
929 *val = LSM6DSO_ULTRA_LOW_POWER_MD;
930 break;
931
932 default:
933 *val = LSM6DSO_HIGH_PERFORMANCE_MD;
934 break;
935 }
936 }
937
938 return ret;
939 }
940
941 /**
942 * @brief Operating mode for gyroscope.[set]
943 *
944 * @param ctx read / write interface definitions
945 * @param val change the values of g_hm_mode in reg CTRL7_G
946 * @retval interface status (MANDATORY: return 0 -> no Error)
947 *
948 */
lsm6dso_gy_power_mode_set(stmdev_ctx_t * ctx,lsm6dso_g_hm_mode_t val)949 int32_t lsm6dso_gy_power_mode_set(stmdev_ctx_t *ctx,
950 lsm6dso_g_hm_mode_t val)
951 {
952 lsm6dso_ctrl7_g_t reg;
953 int32_t ret;
954
955 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
956
957 if (ret == 0)
958 {
959 reg.g_hm_mode = (uint8_t)val;
960 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
961 }
962
963 return ret;
964 }
965
966 /**
967 * @brief Operating mode for gyroscope.[get]
968 *
969 * @param ctx read / write interface definitions
970 * @param val Get the values of g_hm_mode in reg CTRL7_G
971 * @retval interface status (MANDATORY: return 0 -> no Error)
972 *
973 */
lsm6dso_gy_power_mode_get(stmdev_ctx_t * ctx,lsm6dso_g_hm_mode_t * val)974 int32_t lsm6dso_gy_power_mode_get(stmdev_ctx_t *ctx,
975 lsm6dso_g_hm_mode_t *val)
976 {
977 lsm6dso_ctrl7_g_t reg;
978 int32_t ret;
979
980 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
981
982 switch (reg.g_hm_mode)
983 {
984 case LSM6DSO_GY_HIGH_PERFORMANCE:
985 *val = LSM6DSO_GY_HIGH_PERFORMANCE;
986 break;
987
988 case LSM6DSO_GY_NORMAL:
989 *val = LSM6DSO_GY_NORMAL;
990 break;
991
992 default:
993 *val = LSM6DSO_GY_HIGH_PERFORMANCE;
994 break;
995 }
996
997 return ret;
998 }
999
1000 /**
1001 * @brief The STATUS_REG register is read by the primary interface.[get]
1002 *
1003 * @param ctx read / write interface definitions
1004 * @param val register STATUS_REG
1005 * @retval interface status (MANDATORY: return 0 -> no Error)
1006 *
1007 */
lsm6dso_status_reg_get(stmdev_ctx_t * ctx,lsm6dso_status_reg_t * val)1008 int32_t lsm6dso_status_reg_get(stmdev_ctx_t *ctx,
1009 lsm6dso_status_reg_t *val)
1010 {
1011 int32_t ret;
1012
1013 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *) val, 1);
1014
1015 return ret;
1016 }
1017
1018 /**
1019 * @brief Accelerometer new data available.[get]
1020 *
1021 * @param ctx read / write interface definitions
1022 * @param val change the values of xlda in reg STATUS_REG
1023 * @retval interface status (MANDATORY: return 0 -> no Error)
1024 *
1025 */
lsm6dso_xl_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1026 int32_t lsm6dso_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
1027 uint8_t *val)
1028 {
1029 lsm6dso_status_reg_t reg;
1030 int32_t ret;
1031
1032 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *)®, 1);
1033 *val = reg.xlda;
1034
1035 return ret;
1036 }
1037
1038 /**
1039 * @brief Gyroscope new data available.[get]
1040 *
1041 * @param ctx read / write interface definitions
1042 * @param val change the values of gda in reg STATUS_REG
1043 * @retval interface status (MANDATORY: return 0 -> no Error)
1044 *
1045 */
lsm6dso_gy_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1046 int32_t lsm6dso_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
1047 uint8_t *val)
1048 {
1049 lsm6dso_status_reg_t reg;
1050 int32_t ret;
1051
1052 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *)®, 1);
1053 *val = reg.gda;
1054
1055 return ret;
1056 }
1057
1058 /**
1059 * @brief Temperature new data available.[get]
1060 *
1061 * @param ctx read / write interface definitions
1062 * @param val change the values of tda in reg STATUS_REG
1063 * @retval interface status (MANDATORY: return 0 -> no Error)
1064 *
1065 */
lsm6dso_temp_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1066 int32_t lsm6dso_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
1067 uint8_t *val)
1068 {
1069 lsm6dso_status_reg_t reg;
1070 int32_t ret;
1071
1072 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG, (uint8_t *)®, 1);
1073 *val = reg.tda;
1074
1075 return ret;
1076 }
1077
1078 /**
1079 * @brief Accelerometer X-axis user offset correction expressed in
1080 * two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1081 * The value must be in the range [-127 127].[set]
1082 *
1083 * @param ctx read / write interface definitions
1084 * @param buff buffer that contains data to write
1085 * @retval interface status (MANDATORY: return 0 -> no Error)
1086 *
1087 */
lsm6dso_xl_usr_offset_x_set(stmdev_ctx_t * ctx,uint8_t * buff)1088 int32_t lsm6dso_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
1089 {
1090 int32_t ret;
1091
1092 ret = lsm6dso_write_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1);
1093
1094 return ret;
1095 }
1096
1097 /**
1098 * @brief Accelerometer X-axis user offset correction expressed in two’s
1099 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1100 * The value must be in the range [-127 127].[get]
1101 *
1102 * @param ctx read / write interface definitions
1103 * @param buff buffer that stores data read
1104 * @retval interface status (MANDATORY: return 0 -> no Error)
1105 *
1106 */
lsm6dso_xl_usr_offset_x_get(stmdev_ctx_t * ctx,uint8_t * buff)1107 int32_t lsm6dso_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
1108 {
1109 int32_t ret;
1110
1111 ret = lsm6dso_read_reg(ctx, LSM6DSO_X_OFS_USR, buff, 1);
1112
1113 return ret;
1114 }
1115
1116 /**
1117 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1118 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1119 * The value must be in the range [-127 127].[set]
1120 *
1121 * @param ctx read / write interface definitions
1122 * @param buff buffer that contains data to write
1123 * @retval interface status (MANDATORY: return 0 -> no Error)
1124 *
1125 */
lsm6dso_xl_usr_offset_y_set(stmdev_ctx_t * ctx,uint8_t * buff)1126 int32_t lsm6dso_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
1127 {
1128 int32_t ret;
1129
1130 ret = lsm6dso_write_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1);
1131
1132 return ret;
1133 }
1134
1135 /**
1136 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1137 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1138 * The value must be in the range [-127 127].[get]
1139 *
1140 * @param ctx read / write interface definitions
1141 * @param buff buffer that stores data read
1142 * @retval interface status (MANDATORY: return 0 -> no Error)
1143 *
1144 */
lsm6dso_xl_usr_offset_y_get(stmdev_ctx_t * ctx,uint8_t * buff)1145 int32_t lsm6dso_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
1146 {
1147 int32_t ret;
1148
1149 ret = lsm6dso_read_reg(ctx, LSM6DSO_Y_OFS_USR, buff, 1);
1150
1151 return ret;
1152 }
1153
1154 /**
1155 * @brief Accelerometer Z-axis user offset correction expressed in two’s
1156 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1157 * The value must be in the range [-127 127].[set]
1158 *
1159 * @param ctx read / write interface definitions
1160 * @param buff buffer that contains data to write
1161 * @retval interface status (MANDATORY: return 0 -> no Error)
1162 *
1163 */
lsm6dso_xl_usr_offset_z_set(stmdev_ctx_t * ctx,uint8_t * buff)1164 int32_t lsm6dso_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
1165 {
1166 int32_t ret;
1167
1168 ret = lsm6dso_write_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1);
1169
1170 return ret;
1171 }
1172
1173 /**
1174 * @brief Accelerometer Z-axis user offset correction expressed in two’s
1175 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1176 * The value must be in the range [-127 127].[get]
1177 *
1178 * @param ctx read / write interface definitions
1179 * @param buff buffer that stores data read
1180 * @retval interface status (MANDATORY: return 0 -> no Error)
1181 *
1182 */
lsm6dso_xl_usr_offset_z_get(stmdev_ctx_t * ctx,uint8_t * buff)1183 int32_t lsm6dso_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
1184 {
1185 int32_t ret;
1186
1187 ret = lsm6dso_read_reg(ctx, LSM6DSO_Z_OFS_USR, buff, 1);
1188
1189 return ret;
1190 }
1191
1192 /**
1193 * @brief Enables user offset on out.[set]
1194 *
1195 * @param ctx read / write interface definitions
1196 * @param val change the values of usr_off_on_out in reg CTRL7_G
1197 * @retval interface status (MANDATORY: return 0 -> no Error)
1198 *
1199 */
lsm6dso_xl_usr_offset_set(stmdev_ctx_t * ctx,uint8_t val)1200 int32_t lsm6dso_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
1201 {
1202 lsm6dso_ctrl7_g_t reg;
1203 int32_t ret;
1204
1205 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
1206
1207 if (ret == 0)
1208 {
1209 reg.usr_off_on_out = val;
1210 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
1211 }
1212
1213 return ret;
1214 }
1215
1216 /**
1217 * @brief User offset on out flag.[get]
1218 *
1219 * @param ctx read / write interface definitions
1220 * @param val values of usr_off_on_out in reg CTRL7_G
1221 * @retval interface status (MANDATORY: return 0 -> no Error)
1222 *
1223 */
lsm6dso_xl_usr_offset_get(stmdev_ctx_t * ctx,uint8_t * val)1224 int32_t lsm6dso_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
1225 {
1226 lsm6dso_ctrl7_g_t reg;
1227 int32_t ret;
1228
1229 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
1230 *val = reg.usr_off_on_out;
1231
1232 return ret;
1233 }
1234
1235 /**
1236 * @}
1237 *
1238 */
1239
1240 /**
1241 * @defgroup LSM6DSO_Timestamp
1242 * @brief This section groups all the functions that manage the
1243 * timestamp generation.
1244 * @{
1245 *
1246 */
1247
1248 /**
1249 * @brief Reset timestamp counter.[set]
1250 *
1251 * @param ctx Read / write interface definitions.(ptr)
1252 * @retval Interface status (MANDATORY: return 0 -> no Error)
1253 *
1254 */
lsm6dso_timestamp_rst(stmdev_ctx_t * ctx)1255 int32_t lsm6dso_timestamp_rst(stmdev_ctx_t *ctx)
1256 {
1257 uint8_t rst_val = 0xAA;
1258 return lsm6dso_write_reg(ctx, LSM6DSO_TIMESTAMP2, &rst_val, 1);
1259 }
1260
1261 /**
1262 * @brief Enables timestamp counter.[set]
1263 *
1264 * @param ctx read / write interface definitions
1265 * @param val change the values of timestamp_en in reg CTRL10_C
1266 * @retval interface status (MANDATORY: return 0 -> no Error)
1267 *
1268 */
lsm6dso_timestamp_set(stmdev_ctx_t * ctx,uint8_t val)1269 int32_t lsm6dso_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
1270 {
1271 lsm6dso_ctrl10_c_t reg;
1272 int32_t ret;
1273
1274 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t *)®, 1);
1275
1276 if (ret == 0)
1277 {
1278 reg.timestamp_en = val;
1279 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t *)®, 1);
1280 }
1281
1282 return ret;
1283 }
1284
1285 /**
1286 * @brief Enables timestamp counter.[get]
1287 *
1288 * @param ctx read / write interface definitions
1289 * @param val change the values of timestamp_en in reg CTRL10_C
1290 * @retval interface status (MANDATORY: return 0 -> no Error)
1291 *
1292 */
lsm6dso_timestamp_get(stmdev_ctx_t * ctx,uint8_t * val)1293 int32_t lsm6dso_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
1294 {
1295 lsm6dso_ctrl10_c_t reg;
1296 int32_t ret;
1297
1298 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL10_C, (uint8_t *)®, 1);
1299 *val = reg.timestamp_en;
1300
1301 return ret;
1302 }
1303
1304 /**
1305 * @brief Timestamp first data output register (r).
1306 * The value is expressed as a 32-bit word and the bit
1307 * resolution is 25 μs.[get]
1308 *
1309 * @param ctx read / write interface definitions
1310 * @param buff buffer that stores data read
1311 * @retval interface status (MANDATORY: return 0 -> no Error)
1312 *
1313 */
lsm6dso_timestamp_raw_get(stmdev_ctx_t * ctx,uint32_t * val)1314 int32_t lsm6dso_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
1315 {
1316 uint8_t buff[4];
1317 int32_t ret;
1318
1319 ret = lsm6dso_read_reg(ctx, LSM6DSO_TIMESTAMP0, buff, 4);
1320 *val = buff[3];
1321 *val = (*val * 256U) + buff[2];
1322 *val = (*val * 256U) + buff[1];
1323 *val = (*val * 256U) + buff[0];
1324
1325 return ret;
1326 }
1327
1328 /**
1329 * @}
1330 *
1331 */
1332
1333 /**
1334 * @defgroup LSM6DSO_Data output
1335 * @brief This section groups all the data output functions.
1336 * @{
1337 *
1338 */
1339
1340 /**
1341 * @brief Circular burst-mode (rounding) read of the output
1342 * registers.[set]
1343 *
1344 * @param ctx read / write interface definitions
1345 * @param val change the values of rounding in reg CTRL5_C
1346 * @retval interface status (MANDATORY: return 0 -> no Error)
1347 *
1348 */
lsm6dso_rounding_mode_set(stmdev_ctx_t * ctx,lsm6dso_rounding_t val)1349 int32_t lsm6dso_rounding_mode_set(stmdev_ctx_t *ctx,
1350 lsm6dso_rounding_t val)
1351 {
1352 lsm6dso_ctrl5_c_t reg;
1353 int32_t ret;
1354
1355 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
1356
1357 if (ret == 0)
1358 {
1359 reg.rounding = (uint8_t)val;
1360 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
1361 }
1362
1363 return ret;
1364 }
1365
1366 /**
1367 * @brief Gyroscope UI chain full-scale selection.[get]
1368 *
1369 * @param ctx read / write interface definitions
1370 * @param val Get the values of rounding in reg CTRL5_C
1371 * @retval interface status (MANDATORY: return 0 -> no Error)
1372 *
1373 */
lsm6dso_rounding_mode_get(stmdev_ctx_t * ctx,lsm6dso_rounding_t * val)1374 int32_t lsm6dso_rounding_mode_get(stmdev_ctx_t *ctx,
1375 lsm6dso_rounding_t *val)
1376 {
1377 lsm6dso_ctrl5_c_t reg;
1378 int32_t ret;
1379
1380 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
1381
1382 switch (reg.rounding)
1383 {
1384 case LSM6DSO_NO_ROUND:
1385 *val = LSM6DSO_NO_ROUND;
1386 break;
1387
1388 case LSM6DSO_ROUND_XL:
1389 *val = LSM6DSO_ROUND_XL;
1390 break;
1391
1392 case LSM6DSO_ROUND_GY:
1393 *val = LSM6DSO_ROUND_GY;
1394 break;
1395
1396 case LSM6DSO_ROUND_GY_XL:
1397 *val = LSM6DSO_ROUND_GY_XL;
1398 break;
1399
1400 default:
1401 *val = LSM6DSO_NO_ROUND;
1402 break;
1403 }
1404
1405 return ret;
1406 }
1407
1408 /**
1409 * @brief Temperature data output register (r).
1410 * L and H registers together express a 16-bit word in two’s
1411 * complement.[get]
1412 *
1413 * @param ctx read / write interface definitions
1414 * @param buff buffer that stores data read
1415 * @retval interface status (MANDATORY: return 0 -> no Error)
1416 *
1417 */
lsm6dso_temperature_raw_get(stmdev_ctx_t * ctx,int16_t * val)1418 int32_t lsm6dso_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1419 {
1420 uint8_t buff[2];
1421 int32_t ret;
1422
1423 ret = lsm6dso_read_reg(ctx, LSM6DSO_OUT_TEMP_L, buff, 2);
1424 val[0] = (int16_t)buff[1];
1425 val[0] = (val[0] * 256) + (int16_t)buff[0];
1426
1427 return ret;
1428 }
1429
1430 /**
1431 * @brief Angular rate sensor. The value is expressed as a 16-bit
1432 * word in two’s complement.[get]
1433 *
1434 * @param ctx read / write interface definitions
1435 * @param buff buffer that stores data read
1436 * @retval interface status (MANDATORY: return 0 -> no Error)
1437 *
1438 */
lsm6dso_angular_rate_raw_get(stmdev_ctx_t * ctx,int16_t * val)1439 int32_t lsm6dso_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1440 {
1441 uint8_t buff[6];
1442 int32_t ret;
1443
1444 ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_G, buff, 6);
1445 val[0] = (int16_t)buff[1];
1446 val[0] = (val[0] * 256) + (int16_t)buff[0];
1447 val[1] = (int16_t)buff[3];
1448 val[1] = (val[1] * 256) + (int16_t)buff[2];
1449 val[2] = (int16_t)buff[5];
1450 val[2] = (val[2] * 256) + (int16_t)buff[4];
1451
1452 return ret;
1453 }
1454
1455 /**
1456 * @brief Linear acceleration output register.
1457 * The value is expressed as a 16-bit word in two’s complement.[get]
1458 *
1459 * @param ctx read / write interface definitions
1460 * @param buff buffer that stores data read
1461 * @retval interface status (MANDATORY: return 0 -> no Error)
1462 *
1463 */
lsm6dso_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)1464 int32_t lsm6dso_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1465 {
1466 uint8_t buff[6];
1467 int32_t ret;
1468
1469 ret = lsm6dso_read_reg(ctx, LSM6DSO_OUTX_L_A, buff, 6);
1470 val[0] = (int16_t)buff[1];
1471 val[0] = (val[0] * 256) + (int16_t)buff[0];
1472 val[1] = (int16_t)buff[3];
1473 val[1] = (val[1] * 256) + (int16_t)buff[2];
1474 val[2] = (int16_t)buff[5];
1475 val[2] = (val[2] * 256) + (int16_t)buff[4];
1476
1477 return ret;
1478 }
1479
1480 /**
1481 * @brief FIFO data output [get]
1482 *
1483 * @param ctx read / write interface definitions
1484 * @param buff buffer that stores data read
1485 * @retval interface status (MANDATORY: return 0 -> no Error)
1486 *
1487 */
lsm6dso_fifo_out_raw_get(stmdev_ctx_t * ctx,uint8_t * buff)1488 int32_t lsm6dso_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
1489 {
1490 int32_t ret;
1491
1492 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_X_L, buff, 6);
1493
1494 return ret;
1495 }
1496
1497 /**
1498 * @brief Step counter output register.[get]
1499 *
1500 * @param ctx read / write interface definitions
1501 * @param buff buffer that stores data read
1502 * @retval interface status (MANDATORY: return 0 -> no Error)
1503 *
1504 */
lsm6dso_number_of_steps_get(stmdev_ctx_t * ctx,uint16_t * val)1505 int32_t lsm6dso_number_of_steps_get(stmdev_ctx_t *ctx, uint16_t *val)
1506 {
1507 uint8_t buff[2];
1508 int32_t ret;
1509
1510 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
1511
1512 if (ret == 0)
1513 {
1514 ret = lsm6dso_read_reg(ctx, LSM6DSO_STEP_COUNTER_L, buff, 2);
1515 }
1516
1517 if (ret == 0)
1518 {
1519 *val = buff[1];
1520 *val = (*val * 256U) + buff[0];
1521 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
1522 }
1523
1524 return ret;
1525 }
1526
1527 /**
1528 * @brief Reset step counter register.[get]
1529 *
1530 * @param ctx read / write interface definitions
1531 * @retval interface status (MANDATORY: return 0 -> no Error)
1532 *
1533 */
lsm6dso_steps_reset(stmdev_ctx_t * ctx)1534 int32_t lsm6dso_steps_reset(stmdev_ctx_t *ctx)
1535 {
1536 lsm6dso_emb_func_src_t reg;
1537 int32_t ret;
1538
1539 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
1540
1541 if (ret == 0)
1542 {
1543 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t *)®, 1);
1544 }
1545
1546 if (ret == 0)
1547 {
1548 reg.pedo_rst_step = PROPERTY_ENABLE;
1549 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_SRC, (uint8_t *)®, 1);
1550 }
1551
1552 if (ret == 0)
1553 {
1554 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
1555 }
1556
1557 return ret;
1558 }
1559
1560 /**
1561 * @}
1562 *
1563 */
1564
1565 /**
1566 * @defgroup LSM6DSO_common
1567 * @brief This section groups common useful functions.
1568 * @{
1569 *
1570 */
1571
1572 /**
1573 * @brief Difference in percentage of the effective ODR(and timestamp rate)
1574 * with respect to the typical.
1575 * Step: 0.15%. 8-bit format, 2's complement.[set]
1576 *
1577 * @param ctx read / write interface definitions
1578 * @param val change the values of freq_fine in reg
1579 * INTERNAL_FREQ_FINE
1580 * @retval interface status (MANDATORY: return 0 -> no Error)
1581 *
1582 */
lsm6dso_odr_cal_reg_set(stmdev_ctx_t * ctx,uint8_t val)1583 int32_t lsm6dso_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
1584 {
1585 lsm6dso_internal_freq_fine_t reg;
1586 int32_t ret;
1587
1588 ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE,
1589 (uint8_t *)®, 1);
1590
1591 if (ret == 0)
1592 {
1593 reg.freq_fine = val;
1594 ret = lsm6dso_write_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE,
1595 (uint8_t *)®, 1);
1596 }
1597
1598 return ret;
1599 }
1600
1601 /**
1602 * @brief Difference in percentage of the effective ODR(and timestamp rate)
1603 * with respect to the typical.
1604 * Step: 0.15%. 8-bit format, 2's complement.[get]
1605 *
1606 * @param ctx read / write interface definitions
1607 * @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE
1608 * @retval interface status (MANDATORY: return 0 -> no Error)
1609 *
1610 */
lsm6dso_odr_cal_reg_get(stmdev_ctx_t * ctx,uint8_t * val)1611 int32_t lsm6dso_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
1612 {
1613 lsm6dso_internal_freq_fine_t reg;
1614 int32_t ret;
1615
1616 ret = lsm6dso_read_reg(ctx, LSM6DSO_INTERNAL_FREQ_FINE,
1617 (uint8_t *)®, 1);
1618 *val = reg.freq_fine;
1619
1620 return ret;
1621 }
1622
1623
1624 /**
1625 * @brief Enable access to the embedded functions/sensor
1626 * hub configuration registers.[set]
1627 *
1628 * @param ctx read / write interface definitions
1629 * @param val change the values of reg_access in
1630 * reg FUNC_CFG_ACCESS
1631 * @retval interface status (MANDATORY: return 0 -> no Error)
1632 *
1633 */
lsm6dso_mem_bank_set(stmdev_ctx_t * ctx,lsm6dso_reg_access_t val)1634 int32_t lsm6dso_mem_bank_set(stmdev_ctx_t *ctx,
1635 lsm6dso_reg_access_t val)
1636 {
1637 lsm6dso_func_cfg_access_t reg;
1638 int32_t ret;
1639
1640 ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)®, 1);
1641
1642 if (ret == 0)
1643 {
1644 reg.reg_access = (uint8_t)val;
1645 ret = lsm6dso_write_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)®, 1);
1646 }
1647
1648 return ret;
1649 }
1650
1651 /**
1652 * @brief Enable access to the embedded functions/sensor
1653 * hub configuration registers.[get]
1654 *
1655 * @param ctx read / write interface definitions
1656 * @param val Get the values of reg_access in
1657 * reg FUNC_CFG_ACCESS
1658 * @retval interface status (MANDATORY: return 0 -> no Error)
1659 *
1660 */
lsm6dso_mem_bank_get(stmdev_ctx_t * ctx,lsm6dso_reg_access_t * val)1661 int32_t lsm6dso_mem_bank_get(stmdev_ctx_t *ctx,
1662 lsm6dso_reg_access_t *val)
1663 {
1664 lsm6dso_func_cfg_access_t reg;
1665 int32_t ret;
1666
1667 ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS, (uint8_t *)®, 1);
1668
1669 switch (reg.reg_access)
1670 {
1671 case LSM6DSO_USER_BANK:
1672 *val = LSM6DSO_USER_BANK;
1673 break;
1674
1675 case LSM6DSO_SENSOR_HUB_BANK:
1676 *val = LSM6DSO_SENSOR_HUB_BANK;
1677 break;
1678
1679 case LSM6DSO_EMBEDDED_FUNC_BANK:
1680 *val = LSM6DSO_EMBEDDED_FUNC_BANK;
1681 break;
1682
1683 default:
1684 *val = LSM6DSO_USER_BANK;
1685 break;
1686 }
1687
1688 return ret;
1689 }
1690
1691 /**
1692 * @brief Write a line(byte) in a page.[set]
1693 *
1694 * @param ctx read / write interface definitions
1695 * @param uint8_t address: page line address
1696 * @param val value to write
1697 * @retval interface status (MANDATORY: return 0 -> no Error)
1698 *
1699 */
lsm6dso_ln_pg_write_byte(stmdev_ctx_t * ctx,uint16_t address,uint8_t * val)1700 int32_t lsm6dso_ln_pg_write_byte(stmdev_ctx_t *ctx, uint16_t address,
1701 uint8_t *val)
1702 {
1703 lsm6dso_page_rw_t page_rw;
1704 lsm6dso_page_sel_t page_sel;
1705 lsm6dso_page_address_t page_address;
1706 int32_t ret;
1707
1708 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
1709
1710 if (ret == 0)
1711 {
1712 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1713 }
1714
1715 if (ret == 0)
1716 {
1717 page_rw.page_rw = 0x02; /* page_write enable */
1718 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1719 }
1720
1721 if (ret == 0)
1722 {
1723 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
1724 }
1725
1726 if (ret == 0)
1727 {
1728 page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
1729 page_sel.not_used_01 = 1;
1730 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
1731 }
1732
1733 if (ret == 0)
1734 {
1735 page_address.page_addr = (uint8_t)address & 0xFFU;
1736 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
1737 (uint8_t *)&page_address, 1);
1738 }
1739
1740 if (ret == 0)
1741 {
1742 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_VALUE, val, 1);
1743 }
1744
1745 if (ret == 0)
1746 {
1747 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1748 }
1749
1750 if (ret == 0)
1751 {
1752 page_rw.page_rw = 0x00; /* page_write disable */
1753 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1754 }
1755
1756 if (ret == 0)
1757 {
1758 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
1759 }
1760
1761 return ret;
1762 }
1763
1764 /**
1765 * @brief Write buffer in a page.[set]
1766 *
1767 * @param ctx read / write interface definitions
1768 * @param uint8_t address: page line address
1769 * @param uint8_t *buf: buffer to write
1770 * @param uint8_t len: buffer len
1771 * @retval interface status (MANDATORY: return 0 -> no Error)
1772 *
1773 */
lsm6dso_ln_pg_write(stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1774 int32_t lsm6dso_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
1775 uint8_t *buf, uint8_t len)
1776 {
1777 lsm6dso_page_rw_t page_rw;
1778 lsm6dso_page_sel_t page_sel;
1779 lsm6dso_page_address_t page_address;
1780 uint16_t addr_pointed;
1781 int32_t ret;
1782
1783 uint8_t i ;
1784 addr_pointed = address;
1785 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
1786
1787 if (ret == 0)
1788 {
1789 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1790 }
1791
1792 if (ret == 0)
1793 {
1794 page_rw.page_rw = 0x02; /* page_write enable*/
1795 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1796 }
1797
1798 if (ret == 0)
1799 {
1800 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
1801 }
1802
1803 if (ret == 0)
1804 {
1805 page_sel.page_sel = ((uint8_t)(addr_pointed >> 8) & 0x0FU);
1806 page_sel.not_used_01 = 1;
1807 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
1808 }
1809
1810 if (ret == 0)
1811 {
1812 page_address.page_addr = (uint8_t)(addr_pointed & 0x00FFU);
1813 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
1814 (uint8_t *)&page_address, 1);
1815 }
1816
1817 if (ret == 0)
1818 {
1819 for (i = 0; ((i < len) && (ret == 0)); i++)
1820 {
1821 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_VALUE, &buf[i], 1);
1822 addr_pointed++;
1823
1824 /* Check if page wrap */
1825 if (((addr_pointed % 0x0100U) == 0x00U) && (ret == 0))
1826 {
1827 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *)&page_sel, 1);
1828
1829 if (ret == 0)
1830 {
1831 page_sel.page_sel = ((uint8_t)(addr_pointed >> 8) & 0x0FU);
1832 page_sel.not_used_01 = 1;
1833 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL,
1834 (uint8_t *)&page_sel, 1);
1835 }
1836 }
1837 }
1838
1839 page_sel.page_sel = 0;
1840 page_sel.not_used_01 = 1;
1841 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
1842 }
1843
1844 if (ret == 0)
1845 {
1846 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1847 }
1848
1849 if (ret == 0)
1850 {
1851 page_rw.page_rw = 0x00; /* page_write disable */
1852 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1853 }
1854
1855 if (ret == 0)
1856 {
1857 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
1858 }
1859
1860 return ret;
1861 }
1862
1863 /**
1864 * @brief Read a line(byte) in a page.[get]
1865 *
1866 * @param ctx read / write interface definitions
1867 * @param uint8_t address: page line address
1868 * @param val read value
1869 * @retval interface status (MANDATORY: return 0 -> no Error)
1870 *
1871 */
lsm6dso_ln_pg_read_byte(stmdev_ctx_t * ctx,uint16_t address,uint8_t * val)1872 int32_t lsm6dso_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address,
1873 uint8_t *val)
1874 {
1875 lsm6dso_page_rw_t page_rw;
1876 lsm6dso_page_sel_t page_sel;
1877 lsm6dso_page_address_t page_address;
1878 int32_t ret;
1879
1880 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
1881
1882 if (ret == 0)
1883 {
1884 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1885 }
1886
1887 if (ret == 0)
1888 {
1889 page_rw.page_rw = 0x01; /* page_read enable*/
1890 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1891 }
1892
1893 if (ret == 0)
1894 {
1895 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
1896 }
1897
1898 if (ret == 0)
1899 {
1900 page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
1901 page_sel.not_used_01 = 1;
1902 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_SEL, (uint8_t *) &page_sel, 1);
1903 }
1904
1905 if (ret == 0)
1906 {
1907 page_address.page_addr = (uint8_t)address & 0x00FFU;
1908 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_ADDRESS,
1909 (uint8_t *)&page_address, 1);
1910 }
1911
1912 if (ret == 0)
1913 {
1914 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_VALUE, val, 1);
1915 }
1916
1917 if (ret == 0)
1918 {
1919 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1920 }
1921
1922 if (ret == 0)
1923 {
1924 page_rw.page_rw = 0x00; /* page_read disable */
1925 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
1926 }
1927
1928 if (ret == 0)
1929 {
1930 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
1931 }
1932
1933 return ret;
1934 }
1935
1936 /**
1937 * @brief Data-ready pulsed / letched mode.[set]
1938 *
1939 * @param ctx read / write interface definitions
1940 * @param val change the values of
1941 * dataready_pulsed in
1942 * reg COUNTER_BDR_REG1
1943 * @retval interface status (MANDATORY: return 0 -> no Error)
1944 *
1945 */
lsm6dso_data_ready_mode_set(stmdev_ctx_t * ctx,lsm6dso_dataready_pulsed_t val)1946 int32_t lsm6dso_data_ready_mode_set(stmdev_ctx_t *ctx,
1947 lsm6dso_dataready_pulsed_t val)
1948 {
1949 lsm6dso_counter_bdr_reg1_t reg;
1950 int32_t ret;
1951
1952 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1);
1953
1954 if (ret == 0)
1955 {
1956 reg.dataready_pulsed = (uint8_t)val;
1957 ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
1958 (uint8_t *)®, 1);
1959 }
1960
1961 return ret;
1962 }
1963
1964 /**
1965 * @brief Data-ready pulsed / letched mode.[get]
1966 *
1967 * @param ctx read / write interface definitions
1968 * @param val Get the values of
1969 * dataready_pulsed in
1970 * reg COUNTER_BDR_REG1
1971 * @retval interface status (MANDATORY: return 0 -> no Error)
1972 *
1973 */
lsm6dso_data_ready_mode_get(stmdev_ctx_t * ctx,lsm6dso_dataready_pulsed_t * val)1974 int32_t lsm6dso_data_ready_mode_get(stmdev_ctx_t *ctx,
1975 lsm6dso_dataready_pulsed_t *val)
1976 {
1977 lsm6dso_counter_bdr_reg1_t reg;
1978 int32_t ret;
1979
1980 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1);
1981
1982 switch (reg.dataready_pulsed)
1983 {
1984 case LSM6DSO_DRDY_LATCHED:
1985 *val = LSM6DSO_DRDY_LATCHED;
1986 break;
1987
1988 case LSM6DSO_DRDY_PULSED:
1989 *val = LSM6DSO_DRDY_PULSED;
1990 break;
1991
1992 default:
1993 *val = LSM6DSO_DRDY_LATCHED;
1994 break;
1995 }
1996
1997 return ret;
1998 }
1999
2000 /**
2001 * @brief Device "Who am I".[get]
2002 *
2003 * @param ctx read / write interface definitions
2004 * @param buff buffer that stores data read
2005 * @retval interface status (MANDATORY: return 0 -> no Error)
2006 *
2007 */
lsm6dso_device_id_get(stmdev_ctx_t * ctx,uint8_t * buff)2008 int32_t lsm6dso_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
2009 {
2010 int32_t ret;
2011
2012 ret = lsm6dso_read_reg(ctx, LSM6DSO_WHO_AM_I, buff, 1);
2013
2014 return ret;
2015 }
2016
2017 /**
2018 * @brief Software reset. Restore the default values
2019 * in user registers[set]
2020 *
2021 * @param ctx read / write interface definitions
2022 * @param val change the values of sw_reset in reg CTRL3_C
2023 * @retval interface status (MANDATORY: return 0 -> no Error)
2024 *
2025 */
lsm6dso_reset_set(stmdev_ctx_t * ctx,uint8_t val)2026 int32_t lsm6dso_reset_set(stmdev_ctx_t *ctx, uint8_t val)
2027 {
2028 lsm6dso_ctrl3_c_t reg;
2029 int32_t ret;
2030
2031 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
2032
2033 if (ret == 0)
2034 {
2035 reg.sw_reset = val;
2036 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
2037 }
2038
2039 return ret;
2040 }
2041
2042 /**
2043 * @brief Software reset. Restore the default values in user registers.[get]
2044 *
2045 * @param ctx read / write interface definitions
2046 * @param val change the values of sw_reset in reg CTRL3_C
2047 * @retval interface status (MANDATORY: return 0 -> no Error)
2048 *
2049 */
lsm6dso_reset_get(stmdev_ctx_t * ctx,uint8_t * val)2050 int32_t lsm6dso_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
2051 {
2052 lsm6dso_ctrl3_c_t reg;
2053 int32_t ret;
2054
2055 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
2056 *val = reg.sw_reset;
2057
2058 return ret;
2059 }
2060
2061 /**
2062 * @brief Register address automatically incremented during a multiple byte
2063 * access with a serial interface.[set]
2064 *
2065 * @param ctx read / write interface definitions
2066 * @param val change the values of if_inc in reg CTRL3_C
2067 * @retval interface status (MANDATORY: return 0 -> no Error)
2068 *
2069 */
lsm6dso_auto_increment_set(stmdev_ctx_t * ctx,uint8_t val)2070 int32_t lsm6dso_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
2071 {
2072 lsm6dso_ctrl3_c_t reg;
2073 int32_t ret;
2074
2075 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
2076
2077 if (ret == 0)
2078 {
2079 reg.if_inc = val;
2080 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
2081 }
2082
2083 return ret;
2084 }
2085
2086 /**
2087 * @brief Register address automatically incremented during a multiple byte
2088 * access with a serial interface.[get]
2089 *
2090 * @param ctx read / write interface definitions
2091 * @param val change the values of if_inc in reg CTRL3_C
2092 * @retval interface status (MANDATORY: return 0 -> no Error)
2093 *
2094 */
lsm6dso_auto_increment_get(stmdev_ctx_t * ctx,uint8_t * val)2095 int32_t lsm6dso_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
2096 {
2097 lsm6dso_ctrl3_c_t reg;
2098 int32_t ret;
2099
2100 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
2101 *val = reg.if_inc;
2102
2103 return ret;
2104 }
2105
2106 /**
2107 * @brief Reboot memory content. Reload the calibration parameters.[set]
2108 *
2109 * @param ctx read / write interface definitions
2110 * @param val change the values of boot in reg CTRL3_C
2111 * @retval interface status (MANDATORY: return 0 -> no Error)
2112 *
2113 */
lsm6dso_boot_set(stmdev_ctx_t * ctx,uint8_t val)2114 int32_t lsm6dso_boot_set(stmdev_ctx_t *ctx, uint8_t val)
2115 {
2116 lsm6dso_ctrl3_c_t reg;
2117 int32_t ret;
2118
2119 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
2120
2121 if (ret == 0)
2122 {
2123 reg.boot = val;
2124 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
2125 }
2126
2127 return ret;
2128 }
2129
2130 /**
2131 * @brief Reboot memory content. Reload the calibration parameters.[get]
2132 *
2133 * @param ctx read / write interface definitions
2134 * @param val change the values of boot in reg CTRL3_C
2135 * @retval interface status (MANDATORY: return 0 -> no Error)
2136 *
2137 */
lsm6dso_boot_get(stmdev_ctx_t * ctx,uint8_t * val)2138 int32_t lsm6dso_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
2139 {
2140 lsm6dso_ctrl3_c_t reg;
2141 int32_t ret;
2142
2143 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
2144 *val = reg.boot;
2145
2146 return ret;
2147 }
2148
2149 /**
2150 * @brief Linear acceleration sensor self-test enable.[set]
2151 *
2152 * @param ctx read / write interface definitions
2153 * @param val change the values of st_xl in reg CTRL5_C
2154 * @retval interface status (MANDATORY: return 0 -> no Error)
2155 *
2156 */
lsm6dso_xl_self_test_set(stmdev_ctx_t * ctx,lsm6dso_st_xl_t val)2157 int32_t lsm6dso_xl_self_test_set(stmdev_ctx_t *ctx,
2158 lsm6dso_st_xl_t val)
2159 {
2160 lsm6dso_ctrl5_c_t reg;
2161 int32_t ret;
2162
2163 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
2164
2165 if (ret == 0)
2166 {
2167 reg.st_xl = (uint8_t)val;
2168 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
2169 }
2170
2171 return ret;
2172 }
2173
2174 /**
2175 * @brief Linear acceleration sensor self-test enable.[get]
2176 *
2177 * @param ctx read / write interface definitions
2178 * @param val Get the values of st_xl in reg CTRL5_C
2179 * @retval interface status (MANDATORY: return 0 -> no Error)
2180 *
2181 */
lsm6dso_xl_self_test_get(stmdev_ctx_t * ctx,lsm6dso_st_xl_t * val)2182 int32_t lsm6dso_xl_self_test_get(stmdev_ctx_t *ctx,
2183 lsm6dso_st_xl_t *val)
2184 {
2185 lsm6dso_ctrl5_c_t reg;
2186 int32_t ret;
2187
2188 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
2189
2190 switch (reg.st_xl)
2191 {
2192 case LSM6DSO_XL_ST_DISABLE:
2193 *val = LSM6DSO_XL_ST_DISABLE;
2194 break;
2195
2196 case LSM6DSO_XL_ST_POSITIVE:
2197 *val = LSM6DSO_XL_ST_POSITIVE;
2198 break;
2199
2200 case LSM6DSO_XL_ST_NEGATIVE:
2201 *val = LSM6DSO_XL_ST_NEGATIVE;
2202 break;
2203
2204 default:
2205 *val = LSM6DSO_XL_ST_DISABLE;
2206 break;
2207 }
2208
2209 return ret;
2210 }
2211
2212 /**
2213 * @brief Angular rate sensor self-test enable.[set]
2214 *
2215 * @param ctx read / write interface definitions
2216 * @param val change the values of st_g in reg CTRL5_C
2217 * @retval interface status (MANDATORY: return 0 -> no Error)
2218 *
2219 */
lsm6dso_gy_self_test_set(stmdev_ctx_t * ctx,lsm6dso_st_g_t val)2220 int32_t lsm6dso_gy_self_test_set(stmdev_ctx_t *ctx,
2221 lsm6dso_st_g_t val)
2222 {
2223 lsm6dso_ctrl5_c_t reg;
2224 int32_t ret;
2225
2226 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
2227
2228 if (ret == 0)
2229 {
2230 reg.st_g = (uint8_t)val;
2231 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
2232 }
2233
2234 return ret;
2235 }
2236
2237 /**
2238 * @brief Angular rate sensor self-test enable.[get]
2239 *
2240 * @param ctx read / write interface definitions
2241 * @param val Get the values of st_g in reg CTRL5_C
2242 * @retval interface status (MANDATORY: return 0 -> no Error)
2243 *
2244 */
lsm6dso_gy_self_test_get(stmdev_ctx_t * ctx,lsm6dso_st_g_t * val)2245 int32_t lsm6dso_gy_self_test_get(stmdev_ctx_t *ctx,
2246 lsm6dso_st_g_t *val)
2247 {
2248 lsm6dso_ctrl5_c_t reg;
2249 int32_t ret;
2250
2251 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL5_C, (uint8_t *)®, 1);
2252
2253 switch (reg.st_g)
2254 {
2255 case LSM6DSO_GY_ST_DISABLE:
2256 *val = LSM6DSO_GY_ST_DISABLE;
2257 break;
2258
2259 case LSM6DSO_GY_ST_POSITIVE:
2260 *val = LSM6DSO_GY_ST_POSITIVE;
2261 break;
2262
2263 case LSM6DSO_GY_ST_NEGATIVE:
2264 *val = LSM6DSO_GY_ST_NEGATIVE;
2265 break;
2266
2267 default:
2268 *val = LSM6DSO_GY_ST_DISABLE;
2269 break;
2270 }
2271
2272 return ret;
2273 }
2274
2275 /**
2276 * @}
2277 *
2278 */
2279
2280 /**
2281 * @defgroup LSM6DSO_filters
2282 * @brief This section group all the functions concerning the
2283 * filters configuration
2284 * @{
2285 *
2286 */
2287
2288 /**
2289 * @brief Accelerometer output from LPF2 filtering stage selection.[set]
2290 *
2291 * @param ctx read / write interface definitions
2292 * @param val change the values of lpf2_xl_en in reg CTRL1_XL
2293 * @retval interface status (MANDATORY: return 0 -> no Error)
2294 *
2295 */
lsm6dso_xl_filter_lp2_set(stmdev_ctx_t * ctx,uint8_t val)2296 int32_t lsm6dso_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
2297 {
2298 lsm6dso_ctrl1_xl_t reg;
2299 int32_t ret;
2300
2301 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
2302
2303 if (ret == 0)
2304 {
2305 reg.lpf2_xl_en = val;
2306 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
2307 }
2308
2309 return ret;
2310 }
2311
2312 /**
2313 * @brief Accelerometer output from LPF2 filtering stage selection.[get]
2314 *
2315 * @param ctx read / write interface definitions
2316 * @param val change the values of lpf2_xl_en in reg CTRL1_XL
2317 * @retval interface status (MANDATORY: return 0 -> no Error)
2318 *
2319 */
lsm6dso_xl_filter_lp2_get(stmdev_ctx_t * ctx,uint8_t * val)2320 int32_t lsm6dso_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
2321 {
2322 lsm6dso_ctrl1_xl_t reg;
2323 int32_t ret;
2324
2325 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 1);
2326 *val = reg.lpf2_xl_en;
2327
2328 return ret;
2329 }
2330
2331 /**
2332 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2333 * the bandwidth can be selected through FTYPE [2:0]
2334 * in CTRL6_C (15h).[set]
2335 *
2336 * @param ctx read / write interface definitions
2337 * @param val change the values of lpf1_sel_g in reg CTRL4_C
2338 * @retval interface status (MANDATORY: return 0 -> no Error)
2339 *
2340 */
lsm6dso_gy_filter_lp1_set(stmdev_ctx_t * ctx,uint8_t val)2341 int32_t lsm6dso_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
2342 {
2343 lsm6dso_ctrl4_c_t reg;
2344 int32_t ret;
2345
2346 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
2347
2348 if (ret == 0)
2349 {
2350 reg.lpf1_sel_g = val;
2351 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
2352 }
2353
2354 return ret;
2355 }
2356
2357 /**
2358 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2359 * the bandwidth can be selected through FTYPE [2:0]
2360 * in CTRL6_C (15h).[get]
2361 *
2362 * @param ctx read / write interface definitions
2363 * @param val change the values of lpf1_sel_g in reg CTRL4_C
2364 * @retval interface status (MANDATORY: return 0 -> no Error)
2365 *
2366 */
lsm6dso_gy_filter_lp1_get(stmdev_ctx_t * ctx,uint8_t * val)2367 int32_t lsm6dso_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
2368 {
2369 lsm6dso_ctrl4_c_t reg;
2370 int32_t ret;
2371
2372 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
2373 *val = reg.lpf1_sel_g;
2374
2375 return ret;
2376 }
2377
2378 /**
2379 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2380 * (XL and Gyro independently masked).[set]
2381 *
2382 * @param ctx read / write interface definitions
2383 * @param val change the values of drdy_mask in reg CTRL4_C
2384 * @retval interface status (MANDATORY: return 0 -> no Error)
2385 *
2386 */
lsm6dso_filter_settling_mask_set(stmdev_ctx_t * ctx,uint8_t val)2387 int32_t lsm6dso_filter_settling_mask_set(stmdev_ctx_t *ctx,
2388 uint8_t val)
2389 {
2390 lsm6dso_ctrl4_c_t reg;
2391 int32_t ret;
2392
2393 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
2394
2395 if (ret == 0)
2396 {
2397 reg.drdy_mask = val;
2398 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
2399 }
2400
2401 return ret;
2402 }
2403
2404 /**
2405 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2406 * (XL and Gyro independently masked).[get]
2407 *
2408 * @param ctx read / write interface definitions
2409 * @param val change the values of drdy_mask in reg CTRL4_C
2410 * @retval interface status (MANDATORY: return 0 -> no Error)
2411 *
2412 */
lsm6dso_filter_settling_mask_get(stmdev_ctx_t * ctx,uint8_t * val)2413 int32_t lsm6dso_filter_settling_mask_get(stmdev_ctx_t *ctx,
2414 uint8_t *val)
2415 {
2416 lsm6dso_ctrl4_c_t reg;
2417 int32_t ret;
2418
2419 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
2420 *val = reg.drdy_mask;
2421
2422 return ret;
2423 }
2424
2425 /**
2426 * @brief Gyroscope lp1 bandwidth.[set]
2427 *
2428 * @param ctx read / write interface definitions
2429 * @param val change the values of ftype in reg CTRL6_C
2430 * @retval interface status (MANDATORY: return 0 -> no Error)
2431 *
2432 */
lsm6dso_gy_lp1_bandwidth_set(stmdev_ctx_t * ctx,lsm6dso_ftype_t val)2433 int32_t lsm6dso_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
2434 lsm6dso_ftype_t val)
2435 {
2436 lsm6dso_ctrl6_c_t reg;
2437 int32_t ret;
2438
2439 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
2440
2441 if (ret == 0)
2442 {
2443 reg.ftype = (uint8_t)val;
2444 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
2445 }
2446
2447 return ret;
2448 }
2449
2450 /**
2451 * @brief Gyroscope lp1 bandwidth.[get]
2452 *
2453 * @param ctx read / write interface definitions
2454 * @param val Get the values of ftype in reg CTRL6_C
2455 * @retval interface status (MANDATORY: return 0 -> no Error)
2456 *
2457 */
lsm6dso_gy_lp1_bandwidth_get(stmdev_ctx_t * ctx,lsm6dso_ftype_t * val)2458 int32_t lsm6dso_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
2459 lsm6dso_ftype_t *val)
2460 {
2461 lsm6dso_ctrl6_c_t reg;
2462 int32_t ret;
2463
2464 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
2465
2466 switch (reg.ftype)
2467 {
2468 case LSM6DSO_ULTRA_LIGHT:
2469 *val = LSM6DSO_ULTRA_LIGHT;
2470 break;
2471
2472 case LSM6DSO_VERY_LIGHT:
2473 *val = LSM6DSO_VERY_LIGHT;
2474 break;
2475
2476 case LSM6DSO_LIGHT:
2477 *val = LSM6DSO_LIGHT;
2478 break;
2479
2480 case LSM6DSO_MEDIUM:
2481 *val = LSM6DSO_MEDIUM;
2482 break;
2483
2484 case LSM6DSO_STRONG:
2485 *val = LSM6DSO_STRONG;
2486 break;
2487
2488 case LSM6DSO_VERY_STRONG:
2489 *val = LSM6DSO_VERY_STRONG;
2490 break;
2491
2492 case LSM6DSO_AGGRESSIVE:
2493 *val = LSM6DSO_AGGRESSIVE;
2494 break;
2495
2496 case LSM6DSO_XTREME:
2497 *val = LSM6DSO_XTREME;
2498 break;
2499
2500 default:
2501 *val = LSM6DSO_ULTRA_LIGHT;
2502 break;
2503 }
2504
2505 return ret;
2506 }
2507
2508 /**
2509 * @brief Low pass filter 2 on 6D function selection.[set]
2510 *
2511 * @param ctx read / write interface definitions
2512 * @param val change the values of low_pass_on_6d in reg CTRL8_XL
2513 * @retval interface status (MANDATORY: return 0 -> no Error)
2514 *
2515 */
lsm6dso_xl_lp2_on_6d_set(stmdev_ctx_t * ctx,uint8_t val)2516 int32_t lsm6dso_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
2517 {
2518 lsm6dso_ctrl8_xl_t reg;
2519 int32_t ret;
2520
2521 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2522
2523 if (ret == 0)
2524 {
2525 reg.low_pass_on_6d = val;
2526 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2527 }
2528
2529 return ret;
2530 }
2531
2532 /**
2533 * @brief Low pass filter 2 on 6D function selection.[get]
2534 *
2535 * @param ctx read / write interface definitions
2536 * @param val change the values of low_pass_on_6d in reg CTRL8_XL
2537 * @retval interface status (MANDATORY: return 0 -> no Error)
2538 *
2539 */
lsm6dso_xl_lp2_on_6d_get(stmdev_ctx_t * ctx,uint8_t * val)2540 int32_t lsm6dso_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
2541 {
2542 lsm6dso_ctrl8_xl_t reg;
2543 int32_t ret;
2544
2545 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2546 *val = reg.low_pass_on_6d;
2547
2548 return ret;
2549 }
2550
2551 /**
2552 * @brief Accelerometer slope filter / high-pass filter selection
2553 * on output.[set]
2554 *
2555 * @param ctx read / write interface definitions
2556 * @param val change the values of hp_slope_xl_en
2557 * in reg CTRL8_XL
2558 * @retval interface status (MANDATORY: return 0 -> no Error)
2559 *
2560 */
lsm6dso_xl_hp_path_on_out_set(stmdev_ctx_t * ctx,lsm6dso_hp_slope_xl_en_t val)2561 int32_t lsm6dso_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
2562 lsm6dso_hp_slope_xl_en_t val)
2563 {
2564 lsm6dso_ctrl8_xl_t reg;
2565 int32_t ret;
2566
2567 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2568
2569 if (ret == 0)
2570 {
2571 reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4;
2572 reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5;
2573 reg.hpcf_xl = (uint8_t)val & 0x07U;
2574 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2575 }
2576
2577 return ret;
2578 }
2579
2580 /**
2581 * @brief Accelerometer slope filter / high-pass filter selection
2582 * on output.[get]
2583 *
2584 * @param ctx read / write interface definitions
2585 * @param val Get the values of hp_slope_xl_en
2586 * in reg CTRL8_XL
2587 * @retval interface status (MANDATORY: return 0 -> no Error)
2588 *
2589 */
lsm6dso_xl_hp_path_on_out_get(stmdev_ctx_t * ctx,lsm6dso_hp_slope_xl_en_t * val)2590 int32_t lsm6dso_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
2591 lsm6dso_hp_slope_xl_en_t *val)
2592 {
2593 lsm6dso_ctrl8_xl_t reg;
2594 int32_t ret;
2595
2596 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2597
2598 switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) |
2599 reg.hpcf_xl)
2600 {
2601 case LSM6DSO_HP_PATH_DISABLE_ON_OUT:
2602 *val = LSM6DSO_HP_PATH_DISABLE_ON_OUT;
2603 break;
2604
2605 case LSM6DSO_SLOPE_ODR_DIV_4:
2606 *val = LSM6DSO_SLOPE_ODR_DIV_4;
2607 break;
2608
2609 case LSM6DSO_HP_ODR_DIV_10:
2610 *val = LSM6DSO_HP_ODR_DIV_10;
2611 break;
2612
2613 case LSM6DSO_HP_ODR_DIV_20:
2614 *val = LSM6DSO_HP_ODR_DIV_20;
2615 break;
2616
2617 case LSM6DSO_HP_ODR_DIV_45:
2618 *val = LSM6DSO_HP_ODR_DIV_45;
2619 break;
2620
2621 case LSM6DSO_HP_ODR_DIV_100:
2622 *val = LSM6DSO_HP_ODR_DIV_100;
2623 break;
2624
2625 case LSM6DSO_HP_ODR_DIV_200:
2626 *val = LSM6DSO_HP_ODR_DIV_200;
2627 break;
2628
2629 case LSM6DSO_HP_ODR_DIV_400:
2630 *val = LSM6DSO_HP_ODR_DIV_400;
2631 break;
2632
2633 case LSM6DSO_HP_ODR_DIV_800:
2634 *val = LSM6DSO_HP_ODR_DIV_800;
2635 break;
2636
2637 case LSM6DSO_HP_REF_MD_ODR_DIV_10:
2638 *val = LSM6DSO_HP_REF_MD_ODR_DIV_10;
2639 break;
2640
2641 case LSM6DSO_HP_REF_MD_ODR_DIV_20:
2642 *val = LSM6DSO_HP_REF_MD_ODR_DIV_20;
2643 break;
2644
2645 case LSM6DSO_HP_REF_MD_ODR_DIV_45:
2646 *val = LSM6DSO_HP_REF_MD_ODR_DIV_45;
2647 break;
2648
2649 case LSM6DSO_HP_REF_MD_ODR_DIV_100:
2650 *val = LSM6DSO_HP_REF_MD_ODR_DIV_100;
2651 break;
2652
2653 case LSM6DSO_HP_REF_MD_ODR_DIV_200:
2654 *val = LSM6DSO_HP_REF_MD_ODR_DIV_200;
2655 break;
2656
2657 case LSM6DSO_HP_REF_MD_ODR_DIV_400:
2658 *val = LSM6DSO_HP_REF_MD_ODR_DIV_400;
2659 break;
2660
2661 case LSM6DSO_HP_REF_MD_ODR_DIV_800:
2662 *val = LSM6DSO_HP_REF_MD_ODR_DIV_800;
2663 break;
2664
2665 case LSM6DSO_LP_ODR_DIV_10:
2666 *val = LSM6DSO_LP_ODR_DIV_10;
2667 break;
2668
2669 case LSM6DSO_LP_ODR_DIV_20:
2670 *val = LSM6DSO_LP_ODR_DIV_20;
2671 break;
2672
2673 case LSM6DSO_LP_ODR_DIV_45:
2674 *val = LSM6DSO_LP_ODR_DIV_45;
2675 break;
2676
2677 case LSM6DSO_LP_ODR_DIV_100:
2678 *val = LSM6DSO_LP_ODR_DIV_100;
2679 break;
2680
2681 case LSM6DSO_LP_ODR_DIV_200:
2682 *val = LSM6DSO_LP_ODR_DIV_200;
2683 break;
2684
2685 case LSM6DSO_LP_ODR_DIV_400:
2686 *val = LSM6DSO_LP_ODR_DIV_400;
2687 break;
2688
2689 case LSM6DSO_LP_ODR_DIV_800:
2690 *val = LSM6DSO_LP_ODR_DIV_800;
2691 break;
2692
2693 default:
2694 *val = LSM6DSO_HP_PATH_DISABLE_ON_OUT;
2695 break;
2696 }
2697
2698 return ret;
2699 }
2700
2701 /**
2702 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2703 * The filter sets the second samples after writing this bit.
2704 * Active only during device exit from power-down mode.[set]
2705 *
2706 * @param ctx read / write interface definitions
2707 * @param val change the values of fastsettl_mode_xl in
2708 * reg CTRL8_XL
2709 * @retval interface status (MANDATORY: return 0 -> no Error)
2710 *
2711 */
lsm6dso_xl_fast_settling_set(stmdev_ctx_t * ctx,uint8_t val)2712 int32_t lsm6dso_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
2713 {
2714 lsm6dso_ctrl8_xl_t reg;
2715 int32_t ret;
2716
2717 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2718
2719 if (ret == 0)
2720 {
2721 reg.fastsettl_mode_xl = val;
2722 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2723 }
2724
2725 return ret;
2726 }
2727
2728 /**
2729 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2730 * The filter sets the second samples after writing this bit.
2731 * Active only during device exit from power-down mode.[get]
2732 *
2733 * @param ctx read / write interface definitions
2734 * @param val change the values of fastsettl_mode_xl in reg CTRL8_XL
2735 * @retval interface status (MANDATORY: return 0 -> no Error)
2736 *
2737 */
lsm6dso_xl_fast_settling_get(stmdev_ctx_t * ctx,uint8_t * val)2738 int32_t lsm6dso_xl_fast_settling_get(stmdev_ctx_t *ctx, uint8_t *val)
2739 {
2740 lsm6dso_ctrl8_xl_t reg;
2741 int32_t ret;
2742
2743 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
2744 *val = reg.fastsettl_mode_xl;
2745
2746 return ret;
2747 }
2748
2749 /**
2750 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2751 * functions.[set]
2752 *
2753 * @param ctx read / write interface definitions
2754 * @param val change the values of slope_fds in reg TAP_CFG0
2755 * @retval interface status (MANDATORY: return 0 -> no Error)
2756 *
2757 */
lsm6dso_xl_hp_path_internal_set(stmdev_ctx_t * ctx,lsm6dso_slope_fds_t val)2758 int32_t lsm6dso_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
2759 lsm6dso_slope_fds_t val)
2760 {
2761 lsm6dso_tap_cfg0_t reg;
2762 int32_t ret;
2763
2764 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
2765
2766 if (ret == 0)
2767 {
2768 reg.slope_fds = (uint8_t)val;
2769 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
2770 }
2771
2772 return ret;
2773 }
2774
2775 /**
2776 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2777 * functions.[get]
2778 *
2779 * @param ctx read / write interface definitions
2780 * @param val Get the values of slope_fds in reg TAP_CFG0
2781 * @retval interface status (MANDATORY: return 0 -> no Error)
2782 *
2783 */
lsm6dso_xl_hp_path_internal_get(stmdev_ctx_t * ctx,lsm6dso_slope_fds_t * val)2784 int32_t lsm6dso_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
2785 lsm6dso_slope_fds_t *val)
2786 {
2787 lsm6dso_tap_cfg0_t reg;
2788 int32_t ret;
2789
2790 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
2791
2792 switch (reg.slope_fds)
2793 {
2794 case LSM6DSO_USE_SLOPE:
2795 *val = LSM6DSO_USE_SLOPE;
2796 break;
2797
2798 case LSM6DSO_USE_HPF:
2799 *val = LSM6DSO_USE_HPF;
2800 break;
2801
2802 default:
2803 *val = LSM6DSO_USE_SLOPE;
2804 break;
2805 }
2806
2807 return ret;
2808 }
2809
2810 /**
2811 * @brief Enables gyroscope digital high-pass filter. The filter is
2812 * enabled only if the gyro is in HP mode.[set]
2813 *
2814 * @param ctx read / write interface definitions
2815 * @param val Get the values of hp_en_g and hp_en_g
2816 * in reg CTRL7_G
2817 * @retval interface status (MANDATORY: return 0 -> no Error)
2818 *
2819 */
lsm6dso_gy_hp_path_internal_set(stmdev_ctx_t * ctx,lsm6dso_hpm_g_t val)2820 int32_t lsm6dso_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
2821 lsm6dso_hpm_g_t val)
2822 {
2823 lsm6dso_ctrl7_g_t reg;
2824 int32_t ret;
2825
2826 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
2827
2828 if (ret == 0)
2829 {
2830 reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
2831 reg.hpm_g = (uint8_t)val & 0x03U;
2832 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
2833 }
2834
2835 return ret;
2836 }
2837
2838 /**
2839 * @brief Enables gyroscope digital high-pass filter. The filter is
2840 * enabled only if the gyro is in HP mode.[get]
2841 *
2842 * @param ctx read / write interface definitions
2843 * @param val Get the values of hp_en_g and hp_en_g
2844 * in reg CTRL7_G
2845 * @retval interface status (MANDATORY: return 0 -> no Error)
2846 *
2847 */
lsm6dso_gy_hp_path_internal_get(stmdev_ctx_t * ctx,lsm6dso_hpm_g_t * val)2848 int32_t lsm6dso_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
2849 lsm6dso_hpm_g_t *val)
2850 {
2851 lsm6dso_ctrl7_g_t reg;
2852 int32_t ret;
2853
2854 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
2855
2856 switch ((reg.hp_en_g << 7) + reg.hpm_g)
2857 {
2858 case LSM6DSO_HP_FILTER_NONE:
2859 *val = LSM6DSO_HP_FILTER_NONE;
2860 break;
2861
2862 case LSM6DSO_HP_FILTER_16mHz:
2863 *val = LSM6DSO_HP_FILTER_16mHz;
2864 break;
2865
2866 case LSM6DSO_HP_FILTER_65mHz:
2867 *val = LSM6DSO_HP_FILTER_65mHz;
2868 break;
2869
2870 case LSM6DSO_HP_FILTER_260mHz:
2871 *val = LSM6DSO_HP_FILTER_260mHz;
2872 break;
2873
2874 case LSM6DSO_HP_FILTER_1Hz04:
2875 *val = LSM6DSO_HP_FILTER_1Hz04;
2876 break;
2877
2878 default:
2879 *val = LSM6DSO_HP_FILTER_NONE;
2880 break;
2881 }
2882
2883 return ret;
2884 }
2885
2886 /**
2887 * @}
2888 *
2889 */
2890
2891 /**
2892 * @defgroup LSM6DSO_ Auxiliary_interface
2893 * @brief This section groups all the functions concerning
2894 * auxiliary interface.
2895 * @{
2896 *
2897 */
2898
2899 /**
2900 * @brief aOn auxiliary interface connect/disconnect SDO and OCS
2901 * internal pull-up.[set]
2902 *
2903 * @param ctx read / write interface definitions
2904 * @param val change the values of ois_pu_dis in
2905 * reg PIN_CTRL
2906 * @retval interface status (MANDATORY: return 0 -> no Error)
2907 *
2908 */
lsm6dso_aux_sdo_ocs_mode_set(stmdev_ctx_t * ctx,lsm6dso_ois_pu_dis_t val)2909 int32_t lsm6dso_aux_sdo_ocs_mode_set(stmdev_ctx_t *ctx,
2910 lsm6dso_ois_pu_dis_t val)
2911 {
2912 lsm6dso_pin_ctrl_t reg;
2913 int32_t ret;
2914
2915 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1);
2916
2917 if (ret == 0)
2918 {
2919 reg.ois_pu_dis = (uint8_t)val;
2920 ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1);
2921 }
2922
2923 return ret;
2924 }
2925
2926 /**
2927 * @brief On auxiliary interface connect/disconnect SDO and OCS
2928 * internal pull-up.[get]
2929 *
2930 * @param ctx read / write interface definitions
2931 * @param val Get the values of ois_pu_dis in reg PIN_CTRL
2932 * @retval interface status (MANDATORY: return 0 -> no Error)
2933 *
2934 */
lsm6dso_aux_sdo_ocs_mode_get(stmdev_ctx_t * ctx,lsm6dso_ois_pu_dis_t * val)2935 int32_t lsm6dso_aux_sdo_ocs_mode_get(stmdev_ctx_t *ctx,
2936 lsm6dso_ois_pu_dis_t *val)
2937 {
2938 lsm6dso_pin_ctrl_t reg;
2939 int32_t ret;
2940
2941 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1);
2942
2943 switch (reg.ois_pu_dis)
2944 {
2945 case LSM6DSO_AUX_PULL_UP_DISC:
2946 *val = LSM6DSO_AUX_PULL_UP_DISC;
2947 break;
2948
2949 case LSM6DSO_AUX_PULL_UP_CONNECT:
2950 *val = LSM6DSO_AUX_PULL_UP_CONNECT;
2951 break;
2952
2953 default:
2954 *val = LSM6DSO_AUX_PULL_UP_DISC;
2955 break;
2956 }
2957
2958 return ret;
2959 }
2960
2961 /**
2962 * @brief OIS chain on aux interface power on mode.[set]
2963 *
2964 * @param ctx read / write interface definitions
2965 * @param val change the values of ois_on in reg CTRL7_G
2966 * @retval interface status (MANDATORY: return 0 -> no Error)
2967 *
2968 */
lsm6dso_aux_pw_on_ctrl_set(stmdev_ctx_t * ctx,lsm6dso_ois_on_t val)2969 int32_t lsm6dso_aux_pw_on_ctrl_set(stmdev_ctx_t *ctx,
2970 lsm6dso_ois_on_t val)
2971 {
2972 lsm6dso_ctrl7_g_t reg;
2973 int32_t ret;
2974
2975 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
2976
2977 if (ret == 0)
2978 {
2979 reg.ois_on_en = (uint8_t)val & 0x01U;
2980 reg.ois_on = (uint8_t)val & 0x01U;
2981 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
2982 }
2983
2984 return ret;
2985 }
2986
2987 /**
2988 * @brief aux_pw_on_ctrl: [get] OIS chain on aux interface power on mode
2989 *
2990 * @param ctx read / write interface definitions
2991 * @param val Get the values of ois_on in reg CTRL7_G
2992 * @retval interface status (MANDATORY: return 0 -> no Error)
2993 *
2994 */
lsm6dso_aux_pw_on_ctrl_get(stmdev_ctx_t * ctx,lsm6dso_ois_on_t * val)2995 int32_t lsm6dso_aux_pw_on_ctrl_get(stmdev_ctx_t *ctx,
2996 lsm6dso_ois_on_t *val)
2997 {
2998 lsm6dso_ctrl7_g_t reg;
2999 int32_t ret;
3000
3001 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL7_G, (uint8_t *)®, 1);
3002
3003 switch (reg.ois_on)
3004 {
3005 case LSM6DSO_AUX_ON:
3006 *val = LSM6DSO_AUX_ON;
3007 break;
3008
3009 case LSM6DSO_AUX_ON_BY_AUX_INTERFACE:
3010 *val = LSM6DSO_AUX_ON_BY_AUX_INTERFACE;
3011 break;
3012
3013 default:
3014 *val = LSM6DSO_AUX_ON;
3015 break;
3016 }
3017
3018 return ret;
3019 }
3020
3021 /**
3022 * @brief Accelerometer full-scale management between UI chain and
3023 * OIS chain. When XL UI is on, the full scale is the same
3024 * between UI/OIS and is chosen by the UI CTRL registers;
3025 * when XL UI is in PD, the OIS can choose the FS.
3026 * Full scales are independent between the UI/OIS chain
3027 * but both bound to 8 g.[set]
3028 *
3029 * @param ctx read / write interface definitions
3030 * @param val change the values of xl_fs_mode in
3031 * reg CTRL8_XL
3032 * @retval interface status (MANDATORY: return 0 -> no Error)
3033 *
3034 */
lsm6dso_aux_xl_fs_mode_set(stmdev_ctx_t * ctx,lsm6dso_xl_fs_mode_t val)3035 int32_t lsm6dso_aux_xl_fs_mode_set(stmdev_ctx_t *ctx,
3036 lsm6dso_xl_fs_mode_t val)
3037 {
3038 lsm6dso_ctrl8_xl_t reg;
3039 int32_t ret;
3040
3041 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
3042
3043 if (ret == 0)
3044 {
3045 reg.xl_fs_mode = (uint8_t)val;
3046 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
3047 }
3048
3049 return ret;
3050 }
3051
3052 /**
3053 * @brief Accelerometer full-scale management between UI chain and
3054 * OIS chain. When XL UI is on, the full scale is the same
3055 * between UI/OIS and is chosen by the UI CTRL registers;
3056 * when XL UI is in PD, the OIS can choose the FS.
3057 * Full scales are independent between the UI/OIS chain
3058 * but both bound to 8 g.[get]
3059 *
3060 * @param ctx read / write interface definitions
3061 * @param val Get the values of xl_fs_mode in reg CTRL8_XL
3062 * @retval interface status (MANDATORY: return 0 -> no Error)
3063 *
3064 */
lsm6dso_aux_xl_fs_mode_get(stmdev_ctx_t * ctx,lsm6dso_xl_fs_mode_t * val)3065 int32_t lsm6dso_aux_xl_fs_mode_get(stmdev_ctx_t *ctx,
3066 lsm6dso_xl_fs_mode_t *val)
3067 {
3068 lsm6dso_ctrl8_xl_t reg;
3069 int32_t ret;
3070
3071 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL8_XL, (uint8_t *)®, 1);
3072
3073 switch (reg.xl_fs_mode)
3074 {
3075 case LSM6DSO_USE_SAME_XL_FS:
3076 *val = LSM6DSO_USE_SAME_XL_FS;
3077 break;
3078
3079 case LSM6DSO_USE_DIFFERENT_XL_FS:
3080 *val = LSM6DSO_USE_DIFFERENT_XL_FS;
3081 break;
3082
3083 default:
3084 *val = LSM6DSO_USE_SAME_XL_FS;
3085 break;
3086 }
3087
3088 return ret;
3089 }
3090
3091 /**
3092 * @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get]
3093 *
3094 * @param ctx read / write interface definitions
3095 * @param lsm6dso_status_spiaux_t: registers STATUS_SPIAUX
3096 * @retval interface status (MANDATORY: return 0 -> no Error)
3097 *
3098 */
lsm6dso_aux_status_reg_get(stmdev_ctx_t * ctx,lsm6dso_status_spiaux_t * val)3099 int32_t lsm6dso_aux_status_reg_get(stmdev_ctx_t *ctx,
3100 lsm6dso_status_spiaux_t *val)
3101 {
3102 int32_t ret;
3103
3104 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *) val, 1);
3105
3106 return ret;
3107 }
3108
3109 /**
3110 * @brief aux_xl_flag_data_ready: [get] AUX accelerometer data available
3111 *
3112 * @param ctx read / write interface definitions
3113 * @param val change the values of xlda in reg STATUS_SPIAUX
3114 * @retval interface status (MANDATORY: return 0 -> no Error)
3115 *
3116 */
lsm6dso_aux_xl_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)3117 int32_t lsm6dso_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
3118 uint8_t *val)
3119 {
3120 lsm6dso_status_spiaux_t reg;
3121 int32_t ret;
3122
3123 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *)®, 1);
3124 *val = reg.xlda;
3125
3126 return ret;
3127 }
3128
3129 /**
3130 * @brief aux_gy_flag_data_ready: [get] AUX gyroscope data available.
3131 *
3132 * @param ctx read / write interface definitions
3133 * @param val change the values of gda in reg STATUS_SPIAUX
3134 * @retval interface status (MANDATORY: return 0 -> no Error)
3135 *
3136 */
lsm6dso_aux_gy_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)3137 int32_t lsm6dso_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
3138 uint8_t *val)
3139 {
3140 lsm6dso_status_spiaux_t reg;
3141 int32_t ret;
3142
3143 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *)®, 1);
3144 *val = reg.gda;
3145
3146 return ret;
3147 }
3148
3149 /**
3150 * @brief High when the gyroscope output is in the settling phase.[get]
3151 *
3152 * @param ctx read / write interface definitions
3153 * @param val change the values of gyro_settling in reg STATUS_SPIAUX
3154 * @retval interface status (MANDATORY: return 0 -> no Error)
3155 *
3156 */
lsm6dso_aux_gy_flag_settling_get(stmdev_ctx_t * ctx,uint8_t * val)3157 int32_t lsm6dso_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
3158 uint8_t *val)
3159 {
3160 lsm6dso_status_spiaux_t reg;
3161 int32_t ret;
3162
3163 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_SPIAUX, (uint8_t *)®, 1);
3164 *val = reg.gyro_settling;
3165
3166 return ret;
3167 }
3168
3169 /**
3170 * @brief Selects accelerometer self-test. Effective only if XL OIS
3171 * chain is enabled.[set]
3172 *
3173 * @param ctx read / write interface definitions
3174 * @param val change the values of st_xl_ois in reg INT_OIS
3175 * @retval interface status (MANDATORY: return 0 -> no Error)
3176 *
3177 */
lsm6dso_aux_xl_self_test_set(stmdev_ctx_t * ctx,lsm6dso_st_xl_ois_t val)3178 int32_t lsm6dso_aux_xl_self_test_set(stmdev_ctx_t *ctx,
3179 lsm6dso_st_xl_ois_t val)
3180 {
3181 lsm6dso_int_ois_t reg;
3182 int32_t ret;
3183
3184 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
3185
3186 if (ret == 0)
3187 {
3188 reg.st_xl_ois = (uint8_t)val;
3189 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
3190 }
3191
3192 return ret;
3193 }
3194
3195 /**
3196 * @brief Selects accelerometer self-test. Effective only if XL OIS
3197 * chain is enabled.[get]
3198 *
3199 * @param ctx read / write interface definitions
3200 * @param val Get the values of st_xl_ois in reg INT_OIS
3201 * @retval interface status (MANDATORY: return 0 -> no Error)
3202 *
3203 */
lsm6dso_aux_xl_self_test_get(stmdev_ctx_t * ctx,lsm6dso_st_xl_ois_t * val)3204 int32_t lsm6dso_aux_xl_self_test_get(stmdev_ctx_t *ctx,
3205 lsm6dso_st_xl_ois_t *val)
3206 {
3207 lsm6dso_int_ois_t reg;
3208 int32_t ret;
3209
3210 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
3211
3212 switch (reg.st_xl_ois)
3213 {
3214 case LSM6DSO_AUX_XL_DISABLE:
3215 *val = LSM6DSO_AUX_XL_DISABLE;
3216 break;
3217
3218 case LSM6DSO_AUX_XL_POS:
3219 *val = LSM6DSO_AUX_XL_POS;
3220 break;
3221
3222 case LSM6DSO_AUX_XL_NEG:
3223 *val = LSM6DSO_AUX_XL_NEG;
3224 break;
3225
3226 default:
3227 *val = LSM6DSO_AUX_XL_DISABLE;
3228 break;
3229 }
3230
3231 return ret;
3232 }
3233
3234 /**
3235 * @brief Indicates polarity of DEN signal on OIS chain.[set]
3236 *
3237 * @param ctx read / write interface definitions
3238 * @param val change the values of den_lh_ois in
3239 * reg INT_OIS
3240 * @retval interface status (MANDATORY: return 0 -> no Error)
3241 *
3242 */
lsm6dso_aux_den_polarity_set(stmdev_ctx_t * ctx,lsm6dso_den_lh_ois_t val)3243 int32_t lsm6dso_aux_den_polarity_set(stmdev_ctx_t *ctx,
3244 lsm6dso_den_lh_ois_t val)
3245 {
3246 lsm6dso_int_ois_t reg;
3247 int32_t ret;
3248
3249 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
3250
3251 if (ret == 0)
3252 {
3253 reg.den_lh_ois = (uint8_t)val;
3254 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
3255 }
3256
3257 return ret;
3258 }
3259
3260 /**
3261 * @brief Indicates polarity of DEN signal on OIS chain.[get]
3262 *
3263 * @param ctx read / write interface definitions
3264 * @param val Get the values of den_lh_ois in reg INT_OIS
3265 * @retval interface status (MANDATORY: return 0 -> no Error)
3266 *
3267 */
lsm6dso_aux_den_polarity_get(stmdev_ctx_t * ctx,lsm6dso_den_lh_ois_t * val)3268 int32_t lsm6dso_aux_den_polarity_get(stmdev_ctx_t *ctx,
3269 lsm6dso_den_lh_ois_t *val)
3270 {
3271 lsm6dso_int_ois_t reg;
3272 int32_t ret;
3273
3274 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
3275
3276 switch (reg.den_lh_ois)
3277 {
3278 case LSM6DSO_AUX_DEN_ACTIVE_LOW:
3279 *val = LSM6DSO_AUX_DEN_ACTIVE_LOW;
3280 break;
3281
3282 case LSM6DSO_AUX_DEN_ACTIVE_HIGH:
3283 *val = LSM6DSO_AUX_DEN_ACTIVE_HIGH;
3284 break;
3285
3286 default:
3287 *val = LSM6DSO_AUX_DEN_ACTIVE_LOW;
3288 break;
3289 }
3290
3291 return ret;
3292 }
3293
3294 /**
3295 * @brief Configure DEN mode on the OIS chain.[set]
3296 *
3297 * @param ctx read / write interface definitions
3298 * @param val change the values of lvl2_ois in reg INT_OIS
3299 * @retval interface status (MANDATORY: return 0 -> no Error)
3300 *
3301 */
lsm6dso_aux_den_mode_set(stmdev_ctx_t * ctx,lsm6dso_lvl2_ois_t val)3302 int32_t lsm6dso_aux_den_mode_set(stmdev_ctx_t *ctx,
3303 lsm6dso_lvl2_ois_t val)
3304 {
3305 lsm6dso_ctrl1_ois_t ctrl1_ois;
3306 lsm6dso_int_ois_t int_ois;
3307 int32_t ret;
3308
3309 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *) &int_ois, 1);
3310
3311 if (ret == 0)
3312 {
3313 int_ois.lvl2_ois = (uint8_t)val & 0x01U;
3314 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *) &int_ois, 1);
3315 }
3316
3317 if (ret == 0)
3318 {
3319 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *) &ctrl1_ois, 1);
3320 }
3321
3322 if (ret == 0)
3323 {
3324 ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
3325 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS,
3326 (uint8_t *) &ctrl1_ois, 1);
3327 }
3328
3329 return ret;
3330 }
3331
3332 /**
3333 * @brief Configure DEN mode on the OIS chain.[get]
3334 *
3335 * @param ctx read / write interface definitions
3336 * @param val Get the values of lvl2_ois in reg INT_OIS
3337 * @retval interface status (MANDATORY: return 0 -> no Error)
3338 *
3339 */
lsm6dso_aux_den_mode_get(stmdev_ctx_t * ctx,lsm6dso_lvl2_ois_t * val)3340 int32_t lsm6dso_aux_den_mode_get(stmdev_ctx_t *ctx,
3341 lsm6dso_lvl2_ois_t *val)
3342 {
3343 lsm6dso_ctrl1_ois_t ctrl1_ois;
3344 lsm6dso_int_ois_t int_ois;
3345 int32_t ret;
3346
3347 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *) &int_ois, 1);
3348
3349 if (ret == 0)
3350 {
3351 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *) &ctrl1_ois, 1);
3352
3353 switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois)
3354 {
3355 case LSM6DSO_AUX_DEN_DISABLE:
3356 *val = LSM6DSO_AUX_DEN_DISABLE;
3357 break;
3358
3359 case LSM6DSO_AUX_DEN_LEVEL_LATCH:
3360 *val = LSM6DSO_AUX_DEN_LEVEL_LATCH;
3361 break;
3362
3363 case LSM6DSO_AUX_DEN_LEVEL_TRIG:
3364 *val = LSM6DSO_AUX_DEN_LEVEL_TRIG;
3365 break;
3366
3367 default:
3368 *val = LSM6DSO_AUX_DEN_DISABLE;
3369 break;
3370 }
3371 }
3372
3373 return ret;
3374 }
3375
3376 /**
3377 * @brief Enables/Disable OIS chain DRDY on INT2 pin.
3378 * This setting has priority over all other INT2 settings.[set]
3379 *
3380 * @param ctx read / write interface definitions
3381 * @param val change the values of int2_drdy_ois in reg INT_OIS
3382 * @retval interface status (MANDATORY: return 0 -> no Error)
3383 *
3384 */
lsm6dso_aux_drdy_on_int2_set(stmdev_ctx_t * ctx,uint8_t val)3385 int32_t lsm6dso_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
3386 {
3387 lsm6dso_int_ois_t reg;
3388 int32_t ret;
3389
3390 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
3391
3392 if (ret == 0)
3393 {
3394 reg.int2_drdy_ois = val;
3395 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
3396 }
3397
3398 return ret;
3399 }
3400
3401 /**
3402 * @brief Enables/Disable OIS chain DRDY on INT2 pin.
3403 * This setting has priority over all other INT2 settings.[get]
3404 *
3405 * @param ctx read / write interface definitions
3406 * @param val change the values of int2_drdy_ois in reg INT_OIS
3407 * @retval interface status (MANDATORY: return 0 -> no Error)
3408 *
3409 */
lsm6dso_aux_drdy_on_int2_get(stmdev_ctx_t * ctx,uint8_t * val)3410 int32_t lsm6dso_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
3411 {
3412 lsm6dso_int_ois_t reg;
3413 int32_t ret;
3414
3415 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_OIS, (uint8_t *)®, 1);
3416 *val = reg.int2_drdy_ois;
3417
3418 return ret;
3419 }
3420
3421 /**
3422 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
3423 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
3424 * When the OIS chain is enabled, the OIS outputs are available
3425 * through the SPI2 in registers OUTX_L_G (22h) through
3426 * OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
3427 * LPF1 is dedicated to this chain.[set]
3428 *
3429 * @param ctx read / write interface definitions
3430 * @param val change the values of ois_en_spi2 in
3431 * reg CTRL1_OIS
3432 * @retval interface status (MANDATORY: return 0 -> no Error)
3433 *
3434 */
lsm6dso_aux_mode_set(stmdev_ctx_t * ctx,lsm6dso_ois_en_spi2_t val)3435 int32_t lsm6dso_aux_mode_set(stmdev_ctx_t *ctx,
3436 lsm6dso_ois_en_spi2_t val)
3437 {
3438 lsm6dso_ctrl1_ois_t reg;
3439 int32_t ret;
3440
3441 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
3442
3443 if (ret == 0)
3444 {
3445 reg.ois_en_spi2 = (uint8_t)val & 0x01U;
3446 reg.mode4_en = ((uint8_t)val & 0x02U) >> 1;
3447 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
3448 }
3449
3450 return ret;
3451 }
3452
3453 /**
3454 * @brief Enables OIS chain data processing for gyro in Mode 3 and Mode 4
3455 * (mode4_en = 1) and accelerometer data in and Mode 4 (mode4_en = 1).
3456 * When the OIS chain is enabled, the OIS outputs are available
3457 * through the SPI2 in registers OUTX_L_G (22h) through
3458 * OUTZ_H_G (27h) and STATUS_REG (1Eh) / STATUS_SPIAux, and
3459 * LPF1 is dedicated to this chain.[get]
3460 *
3461 * @param ctx read / write interface definitions
3462 * @param val Get the values of ois_en_spi2 in
3463 * reg CTRL1_OIS
3464 * @retval interface status (MANDATORY: return 0 -> no Error)
3465 *
3466 */
lsm6dso_aux_mode_get(stmdev_ctx_t * ctx,lsm6dso_ois_en_spi2_t * val)3467 int32_t lsm6dso_aux_mode_get(stmdev_ctx_t *ctx,
3468 lsm6dso_ois_en_spi2_t *val)
3469 {
3470 lsm6dso_ctrl1_ois_t reg;
3471 int32_t ret;
3472
3473 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
3474
3475 switch ((reg.mode4_en << 1) | reg.ois_en_spi2)
3476 {
3477 case LSM6DSO_AUX_DISABLE:
3478 *val = LSM6DSO_AUX_DISABLE;
3479 break;
3480
3481 case LSM6DSO_MODE_3_GY:
3482 *val = LSM6DSO_MODE_3_GY;
3483 break;
3484
3485 case LSM6DSO_MODE_4_GY_XL:
3486 *val = LSM6DSO_MODE_4_GY_XL;
3487 break;
3488
3489 default:
3490 *val = LSM6DSO_AUX_DISABLE;
3491 break;
3492 }
3493
3494 return ret;
3495 }
3496
3497 /**
3498 * @brief Selects gyroscope OIS chain full-scale.[set]
3499 *
3500 * @param ctx read / write interface definitions
3501 * @param val change the values of fs_g_ois in reg CTRL1_OIS
3502 * @retval interface status (MANDATORY: return 0 -> no Error)
3503 *
3504 */
lsm6dso_aux_gy_full_scale_set(stmdev_ctx_t * ctx,lsm6dso_fs_g_ois_t val)3505 int32_t lsm6dso_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
3506 lsm6dso_fs_g_ois_t val)
3507 {
3508 lsm6dso_ctrl1_ois_t reg;
3509 int32_t ret;
3510
3511 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
3512
3513 if (ret == 0)
3514 {
3515 reg.fs_g_ois = (uint8_t)val;
3516 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
3517 }
3518
3519 return ret;
3520 }
3521
3522 /**
3523 * @brief Selects gyroscope OIS chain full-scale.[get]
3524 *
3525 * @param ctx read / write interface definitions
3526 * @param val Get the values of fs_g_ois in reg CTRL1_OIS
3527 * @retval interface status (MANDATORY: return 0 -> no Error)
3528 *
3529 */
lsm6dso_aux_gy_full_scale_get(stmdev_ctx_t * ctx,lsm6dso_fs_g_ois_t * val)3530 int32_t lsm6dso_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
3531 lsm6dso_fs_g_ois_t *val)
3532 {
3533 lsm6dso_ctrl1_ois_t reg;
3534 int32_t ret;
3535
3536 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
3537
3538 switch (reg.fs_g_ois)
3539 {
3540 case LSM6DSO_250dps_AUX:
3541 *val = LSM6DSO_250dps_AUX;
3542 break;
3543
3544 case LSM6DSO_125dps_AUX:
3545 *val = LSM6DSO_125dps_AUX;
3546 break;
3547
3548 case LSM6DSO_500dps_AUX:
3549 *val = LSM6DSO_500dps_AUX;
3550 break;
3551
3552 case LSM6DSO_1000dps_AUX:
3553 *val = LSM6DSO_1000dps_AUX;
3554 break;
3555
3556 case LSM6DSO_2000dps_AUX:
3557 *val = LSM6DSO_2000dps_AUX;
3558 break;
3559
3560 default:
3561 *val = LSM6DSO_250dps_AUX;
3562 break;
3563 }
3564
3565 return ret;
3566 }
3567
3568 /**
3569 * @brief SPI2 3- or 4-wire interface.[set]
3570 *
3571 * @param ctx read / write interface definitions
3572 * @param val change the values of sim_ois in reg CTRL1_OIS
3573 * @retval interface status (MANDATORY: return 0 -> no Error)
3574 *
3575 */
lsm6dso_aux_spi_mode_set(stmdev_ctx_t * ctx,lsm6dso_sim_ois_t val)3576 int32_t lsm6dso_aux_spi_mode_set(stmdev_ctx_t *ctx,
3577 lsm6dso_sim_ois_t val)
3578 {
3579 lsm6dso_ctrl1_ois_t reg;
3580 int32_t ret;
3581
3582 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
3583
3584 if (ret == 0)
3585 {
3586 reg.sim_ois = (uint8_t)val;
3587 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
3588 }
3589
3590 return ret;
3591 }
3592
3593 /**
3594 * @brief SPI2 3- or 4-wire interface.[get]
3595 *
3596 * @param ctx read / write interface definitions
3597 * @param val Get the values of sim_ois in reg CTRL1_OIS
3598 * @retval interface status (MANDATORY: return 0 -> no Error)
3599 *
3600 */
lsm6dso_aux_spi_mode_get(stmdev_ctx_t * ctx,lsm6dso_sim_ois_t * val)3601 int32_t lsm6dso_aux_spi_mode_get(stmdev_ctx_t *ctx,
3602 lsm6dso_sim_ois_t *val)
3603 {
3604 lsm6dso_ctrl1_ois_t reg;
3605 int32_t ret;
3606
3607 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, (uint8_t *)®, 1);
3608
3609 switch (reg.sim_ois)
3610 {
3611 case LSM6DSO_AUX_SPI_4_WIRE:
3612 *val = LSM6DSO_AUX_SPI_4_WIRE;
3613 break;
3614
3615 case LSM6DSO_AUX_SPI_3_WIRE:
3616 *val = LSM6DSO_AUX_SPI_3_WIRE;
3617 break;
3618
3619 default:
3620 *val = LSM6DSO_AUX_SPI_4_WIRE;
3621 break;
3622 }
3623
3624 return ret;
3625 }
3626
3627 /**
3628 * @brief Selects gyroscope digital LPF1 filter bandwidth.[set]
3629 *
3630 * @param ctx read / write interface definitions
3631 * @param val change the values of ftype_ois in
3632 * reg CTRL2_OIS
3633 * @retval interface status (MANDATORY: return 0 -> no Error)
3634 *
3635 */
lsm6dso_aux_gy_lp1_bandwidth_set(stmdev_ctx_t * ctx,lsm6dso_ftype_ois_t val)3636 int32_t lsm6dso_aux_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
3637 lsm6dso_ftype_ois_t val)
3638 {
3639 lsm6dso_ctrl2_ois_t reg;
3640 int32_t ret;
3641
3642 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1);
3643
3644 if (ret == 0)
3645 {
3646 reg.ftype_ois = (uint8_t)val;
3647 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1);
3648 }
3649
3650 return ret;
3651 }
3652
3653 /**
3654 * @brief Selects gyroscope digital LPF1 filter bandwidth.[get]
3655 *
3656 * @param ctx read / write interface definitions
3657 * @param val Get the values of ftype_ois in reg CTRL2_OIS
3658 * @retval interface status (MANDATORY: return 0 -> no Error)
3659 *
3660 */
lsm6dso_aux_gy_lp1_bandwidth_get(stmdev_ctx_t * ctx,lsm6dso_ftype_ois_t * val)3661 int32_t lsm6dso_aux_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
3662 lsm6dso_ftype_ois_t *val)
3663 {
3664 lsm6dso_ctrl2_ois_t reg;
3665 int32_t ret;
3666
3667 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1);
3668
3669 switch (reg.ftype_ois)
3670 {
3671 case LSM6DSO_351Hz39:
3672 *val = LSM6DSO_351Hz39;
3673 break;
3674
3675 case LSM6DSO_236Hz63:
3676 *val = LSM6DSO_236Hz63;
3677 break;
3678
3679 case LSM6DSO_172Hz70:
3680 *val = LSM6DSO_172Hz70;
3681 break;
3682
3683 case LSM6DSO_937Hz91:
3684 *val = LSM6DSO_937Hz91;
3685 break;
3686
3687 default:
3688 *val = LSM6DSO_351Hz39;
3689 break;
3690 }
3691
3692 return ret;
3693 }
3694
3695 /**
3696 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[set]
3697 *
3698 * @param ctx read / write interface definitions
3699 * @param val change the values of hpm_ois in reg CTRL2_OIS
3700 * @retval interface status (MANDATORY: return 0 -> no Error)
3701 *
3702 */
lsm6dso_aux_gy_hp_bandwidth_set(stmdev_ctx_t * ctx,lsm6dso_hpm_ois_t val)3703 int32_t lsm6dso_aux_gy_hp_bandwidth_set(stmdev_ctx_t *ctx,
3704 lsm6dso_hpm_ois_t val)
3705 {
3706 lsm6dso_ctrl2_ois_t reg;
3707 int32_t ret;
3708
3709 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1);
3710
3711 if (ret == 0)
3712 {
3713 reg.hpm_ois = (uint8_t)val & 0x03U;
3714 reg.hp_en_ois = ((uint8_t)val & 0x10U) >> 4;
3715 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1);
3716 }
3717
3718 return ret;
3719 }
3720
3721 /**
3722 * @brief Selects gyroscope OIS chain digital high-pass filter cutoff.[get]
3723 *
3724 * @param ctx read / write interface definitions
3725 * @param val Get the values of hpm_ois in reg CTRL2_OIS
3726 * @retval interface status (MANDATORY: return 0 -> no Error)
3727 *
3728 */
lsm6dso_aux_gy_hp_bandwidth_get(stmdev_ctx_t * ctx,lsm6dso_hpm_ois_t * val)3729 int32_t lsm6dso_aux_gy_hp_bandwidth_get(stmdev_ctx_t *ctx,
3730 lsm6dso_hpm_ois_t *val)
3731 {
3732 lsm6dso_ctrl2_ois_t reg;
3733 int32_t ret;
3734
3735 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL2_OIS, (uint8_t *)®, 1);
3736
3737 switch ((reg.hp_en_ois << 4) | reg.hpm_ois)
3738 {
3739 case LSM6DSO_AUX_HP_DISABLE:
3740 *val = LSM6DSO_AUX_HP_DISABLE;
3741 break;
3742
3743 case LSM6DSO_AUX_HP_Hz016:
3744 *val = LSM6DSO_AUX_HP_Hz016;
3745 break;
3746
3747 case LSM6DSO_AUX_HP_Hz065:
3748 *val = LSM6DSO_AUX_HP_Hz065;
3749 break;
3750
3751 case LSM6DSO_AUX_HP_Hz260:
3752 *val = LSM6DSO_AUX_HP_Hz260;
3753 break;
3754
3755 case LSM6DSO_AUX_HP_1Hz040:
3756 *val = LSM6DSO_AUX_HP_1Hz040;
3757 break;
3758
3759 default:
3760 *val = LSM6DSO_AUX_HP_DISABLE;
3761 break;
3762 }
3763
3764 return ret;
3765 }
3766
3767 /**
3768 * @brief Enable / Disables OIS chain clamp.
3769 * Enable: All OIS chain outputs = 8000h
3770 * during self-test; Disable: OIS chain self-test
3771 * outputs dependent from the aux gyro full
3772 * scale selected.[set]
3773 *
3774 * @param ctx read / write interface definitions
3775 * @param val change the values of st_ois_clampdis in
3776 * reg CTRL3_OIS
3777 * @retval interface status (MANDATORY: return 0 -> no Error)
3778 *
3779 */
lsm6dso_aux_gy_clamp_set(stmdev_ctx_t * ctx,lsm6dso_st_ois_clampdis_t val)3780 int32_t lsm6dso_aux_gy_clamp_set(stmdev_ctx_t *ctx,
3781 lsm6dso_st_ois_clampdis_t val)
3782 {
3783 lsm6dso_ctrl3_ois_t reg;
3784 int32_t ret;
3785
3786 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3787
3788 if (ret == 0)
3789 {
3790 reg.st_ois_clampdis = (uint8_t)val;
3791 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3792 }
3793
3794 return ret;
3795 }
3796
3797 /**
3798 * @brief Enable / Disables OIS chain clamp.
3799 * Enable: All OIS chain outputs = 8000h
3800 * during self-test; Disable: OIS chain self-test
3801 * outputs dependent from the aux gyro full
3802 * scale selected.[set]
3803 *
3804 * @param ctx read / write interface definitions
3805 * @param val Get the values of st_ois_clampdis in
3806 * reg CTRL3_OIS
3807 * @retval interface status (MANDATORY: return 0 -> no Error)
3808 *
3809 */
lsm6dso_aux_gy_clamp_get(stmdev_ctx_t * ctx,lsm6dso_st_ois_clampdis_t * val)3810 int32_t lsm6dso_aux_gy_clamp_get(stmdev_ctx_t *ctx,
3811 lsm6dso_st_ois_clampdis_t *val)
3812 {
3813 lsm6dso_ctrl3_ois_t reg;
3814 int32_t ret;
3815
3816 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3817
3818 switch (reg.st_ois_clampdis)
3819 {
3820 case LSM6DSO_ENABLE_CLAMP:
3821 *val = LSM6DSO_ENABLE_CLAMP;
3822 break;
3823
3824 case LSM6DSO_DISABLE_CLAMP:
3825 *val = LSM6DSO_DISABLE_CLAMP;
3826 break;
3827
3828 default:
3829 *val = LSM6DSO_ENABLE_CLAMP;
3830 break;
3831 }
3832
3833 return ret;
3834 }
3835
3836 /**
3837 * @brief Selects gyroscope OIS chain self-test.[set]
3838 *
3839 * @param ctx read / write interface definitions
3840 * @param val change the values of st_ois in reg CTRL3_OIS
3841 * @retval interface status (MANDATORY: return 0 -> no Error)
3842 *
3843 */
lsm6dso_aux_gy_self_test_set(stmdev_ctx_t * ctx,lsm6dso_st_ois_t val)3844 int32_t lsm6dso_aux_gy_self_test_set(stmdev_ctx_t *ctx,
3845 lsm6dso_st_ois_t val)
3846 {
3847 lsm6dso_ctrl3_ois_t reg;
3848 int32_t ret;
3849
3850 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3851
3852 if (ret == 0)
3853 {
3854 reg.st_ois = (uint8_t)val;
3855 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3856 }
3857
3858 return ret;
3859 }
3860
3861 /**
3862 * @brief Selects gyroscope OIS chain self-test.[get]
3863 *
3864 * @param ctx read / write interface definitions
3865 * @param val Get the values of st_ois in reg CTRL3_OIS
3866 * @retval interface status (MANDATORY: return 0 -> no Error)
3867 *
3868 */
lsm6dso_aux_gy_self_test_get(stmdev_ctx_t * ctx,lsm6dso_st_ois_t * val)3869 int32_t lsm6dso_aux_gy_self_test_get(stmdev_ctx_t *ctx,
3870 lsm6dso_st_ois_t *val)
3871 {
3872 lsm6dso_ctrl3_ois_t reg;
3873 int32_t ret;
3874
3875 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3876
3877 switch (reg.st_ois)
3878 {
3879 case LSM6DSO_AUX_GY_DISABLE:
3880 *val = LSM6DSO_AUX_GY_DISABLE;
3881 break;
3882
3883 case LSM6DSO_AUX_GY_POS:
3884 *val = LSM6DSO_AUX_GY_POS;
3885 break;
3886
3887 case LSM6DSO_AUX_GY_NEG:
3888 *val = LSM6DSO_AUX_GY_NEG;
3889 break;
3890
3891 default:
3892 *val = LSM6DSO_AUX_GY_DISABLE;
3893 break;
3894 }
3895
3896 return ret;
3897 }
3898
3899 /**
3900 * @brief Selects accelerometer OIS channel bandwidth.[set]
3901 *
3902 * @param ctx read / write interface definitions
3903 * @param val change the values of
3904 * filter_xl_conf_ois in reg CTRL3_OIS
3905 * @retval interface status (MANDATORY: return 0 -> no Error)
3906 *
3907 */
lsm6dso_aux_xl_bandwidth_set(stmdev_ctx_t * ctx,lsm6dso_filter_xl_conf_ois_t val)3908 int32_t lsm6dso_aux_xl_bandwidth_set(stmdev_ctx_t *ctx,
3909 lsm6dso_filter_xl_conf_ois_t val)
3910 {
3911 lsm6dso_ctrl3_ois_t reg;
3912 int32_t ret;
3913
3914 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3915
3916 if (ret == 0)
3917 {
3918 reg.filter_xl_conf_ois = (uint8_t)val;
3919 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3920 }
3921
3922 return ret;
3923 }
3924
3925 /**
3926 * @brief Selects accelerometer OIS channel bandwidth.[get]
3927 *
3928 * @param ctx read / write interface definitions
3929 * @param val Get the values of
3930 * filter_xl_conf_ois in reg CTRL3_OIS
3931 * @retval interface status (MANDATORY: return 0 -> no Error)
3932 *
3933 */
lsm6dso_aux_xl_bandwidth_get(stmdev_ctx_t * ctx,lsm6dso_filter_xl_conf_ois_t * val)3934 int32_t lsm6dso_aux_xl_bandwidth_get(stmdev_ctx_t *ctx,
3935 lsm6dso_filter_xl_conf_ois_t *val)
3936 {
3937 lsm6dso_ctrl3_ois_t reg;
3938 int32_t ret;
3939
3940 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
3941
3942 switch (reg.filter_xl_conf_ois)
3943 {
3944 case LSM6DSO_289Hz:
3945 *val = LSM6DSO_289Hz;
3946 break;
3947
3948 case LSM6DSO_258Hz:
3949 *val = LSM6DSO_258Hz;
3950 break;
3951
3952 case LSM6DSO_120Hz:
3953 *val = LSM6DSO_120Hz;
3954 break;
3955
3956 case LSM6DSO_65Hz2:
3957 *val = LSM6DSO_65Hz2;
3958 break;
3959
3960 case LSM6DSO_33Hz2:
3961 *val = LSM6DSO_33Hz2;
3962 break;
3963
3964 case LSM6DSO_16Hz6:
3965 *val = LSM6DSO_16Hz6;
3966 break;
3967
3968 case LSM6DSO_8Hz30:
3969 *val = LSM6DSO_8Hz30;
3970 break;
3971
3972 case LSM6DSO_4Hz15:
3973 *val = LSM6DSO_4Hz15;
3974 break;
3975
3976 default:
3977 *val = LSM6DSO_289Hz;
3978 break;
3979 }
3980
3981 return ret;
3982 }
3983
3984 /**
3985 * @brief Selects accelerometer OIS channel full-scale.[set]
3986 *
3987 * @param ctx read / write interface definitions
3988 * @param val change the values of fs_xl_ois in
3989 * reg CTRL3_OIS
3990 * @retval interface status (MANDATORY: return 0 -> no Error)
3991 *
3992 */
lsm6dso_aux_xl_full_scale_set(stmdev_ctx_t * ctx,lsm6dso_fs_xl_ois_t val)3993 int32_t lsm6dso_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
3994 lsm6dso_fs_xl_ois_t val)
3995 {
3996 lsm6dso_ctrl3_ois_t reg;
3997 int32_t ret;
3998
3999 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
4000
4001 if (ret == 0)
4002 {
4003 reg.fs_xl_ois = (uint8_t)val;
4004 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
4005 }
4006
4007 return ret;
4008 }
4009
4010 /**
4011 * @brief Selects accelerometer OIS channel full-scale.[get]
4012 *
4013 * @param ctx read / write interface definitions
4014 * @param val Get the values of fs_xl_ois in reg CTRL3_OIS
4015 * @retval interface status (MANDATORY: return 0 -> no Error)
4016 *
4017 */
lsm6dso_aux_xl_full_scale_get(stmdev_ctx_t * ctx,lsm6dso_fs_xl_ois_t * val)4018 int32_t lsm6dso_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
4019 lsm6dso_fs_xl_ois_t *val)
4020 {
4021 lsm6dso_ctrl3_ois_t reg;
4022 int32_t ret;
4023
4024 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_OIS, (uint8_t *)®, 1);
4025
4026 switch (reg.fs_xl_ois)
4027 {
4028 case LSM6DSO_AUX_2g:
4029 *val = LSM6DSO_AUX_2g;
4030 break;
4031
4032 case LSM6DSO_AUX_16g:
4033 *val = LSM6DSO_AUX_16g;
4034 break;
4035
4036 case LSM6DSO_AUX_4g:
4037 *val = LSM6DSO_AUX_4g;
4038 break;
4039
4040 case LSM6DSO_AUX_8g:
4041 *val = LSM6DSO_AUX_8g;
4042 break;
4043
4044 default:
4045 *val = LSM6DSO_AUX_2g;
4046 break;
4047 }
4048
4049 return ret;
4050 }
4051
4052 /**
4053 * @}
4054 *
4055 */
4056
4057 /**
4058 * @defgroup LSM6DSO_ main_serial_interface
4059 * @brief This section groups all the functions concerning main
4060 * serial interface management (not auxiliary)
4061 * @{
4062 *
4063 */
4064
4065 /**
4066 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
4067 *
4068 * @param ctx read / write interface definitions
4069 * @param val change the values of sdo_pu_en in
4070 * reg PIN_CTRL
4071 * @retval interface status (MANDATORY: return 0 -> no Error)
4072 *
4073 */
lsm6dso_sdo_sa0_mode_set(stmdev_ctx_t * ctx,lsm6dso_sdo_pu_en_t val)4074 int32_t lsm6dso_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
4075 lsm6dso_sdo_pu_en_t val)
4076 {
4077 lsm6dso_pin_ctrl_t reg;
4078 int32_t ret;
4079
4080 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1);
4081
4082 if (ret == 0)
4083 {
4084 reg.sdo_pu_en = (uint8_t)val;
4085 ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1);
4086 }
4087
4088 return ret;
4089 }
4090
4091 /**
4092 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
4093 *
4094 * @param ctx read / write interface definitions
4095 * @param val Get the values of sdo_pu_en in reg PIN_CTRL
4096 * @retval interface status (MANDATORY: return 0 -> no Error)
4097 *
4098 */
lsm6dso_sdo_sa0_mode_get(stmdev_ctx_t * ctx,lsm6dso_sdo_pu_en_t * val)4099 int32_t lsm6dso_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
4100 lsm6dso_sdo_pu_en_t *val)
4101 {
4102 lsm6dso_pin_ctrl_t reg;
4103 int32_t ret;
4104
4105 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)®, 1);
4106
4107 switch (reg.sdo_pu_en)
4108 {
4109 case LSM6DSO_PULL_UP_DISC:
4110 *val = LSM6DSO_PULL_UP_DISC;
4111 break;
4112
4113 case LSM6DSO_PULL_UP_CONNECT:
4114 *val = LSM6DSO_PULL_UP_CONNECT;
4115 break;
4116
4117 default:
4118 *val = LSM6DSO_PULL_UP_DISC;
4119 break;
4120 }
4121
4122 return ret;
4123 }
4124
4125 /**
4126 * @brief SPI Serial Interface Mode selection.[set]
4127 *
4128 * @param ctx read / write interface definitions
4129 * @param val change the values of sim in reg CTRL3_C
4130 * @retval interface status (MANDATORY: return 0 -> no Error)
4131 *
4132 */
lsm6dso_spi_mode_set(stmdev_ctx_t * ctx,lsm6dso_sim_t val)4133 int32_t lsm6dso_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso_sim_t val)
4134 {
4135 lsm6dso_ctrl3_c_t reg;
4136 int32_t ret;
4137
4138 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
4139
4140 if (ret == 0)
4141 {
4142 reg.sim = (uint8_t)val;
4143 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
4144 }
4145
4146 return ret;
4147 }
4148
4149 /**
4150 * @brief SPI Serial Interface Mode selection.[get]
4151 *
4152 * @param ctx read / write interface definitions
4153 * @param val Get the values of sim in reg CTRL3_C
4154 * @retval interface status (MANDATORY: return 0 -> no Error)
4155 *
4156 */
lsm6dso_spi_mode_get(stmdev_ctx_t * ctx,lsm6dso_sim_t * val)4157 int32_t lsm6dso_spi_mode_get(stmdev_ctx_t *ctx, lsm6dso_sim_t *val)
4158 {
4159 lsm6dso_ctrl3_c_t reg;
4160 int32_t ret;
4161
4162 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
4163
4164 switch (reg.sim)
4165 {
4166 case LSM6DSO_SPI_4_WIRE:
4167 *val = LSM6DSO_SPI_4_WIRE;
4168 break;
4169
4170 case LSM6DSO_SPI_3_WIRE:
4171 *val = LSM6DSO_SPI_3_WIRE;
4172 break;
4173
4174 default:
4175 *val = LSM6DSO_SPI_4_WIRE;
4176 break;
4177 }
4178
4179 return ret;
4180 }
4181
4182 /**
4183 * @brief Disable / Enable I2C interface.[set]
4184 *
4185 * @param ctx read / write interface definitions
4186 * @param val change the values of i2c_disable in
4187 * reg CTRL4_C
4188 * @retval interface status (MANDATORY: return 0 -> no Error)
4189 *
4190 */
lsm6dso_i2c_interface_set(stmdev_ctx_t * ctx,lsm6dso_i2c_disable_t val)4191 int32_t lsm6dso_i2c_interface_set(stmdev_ctx_t *ctx,
4192 lsm6dso_i2c_disable_t val)
4193 {
4194 lsm6dso_ctrl4_c_t reg;
4195 int32_t ret;
4196
4197 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
4198
4199 if (ret == 0)
4200 {
4201 reg.i2c_disable = (uint8_t)val;
4202 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
4203 }
4204
4205 return ret;
4206 }
4207
4208 /**
4209 * @brief Disable / Enable I2C interface.[get]
4210 *
4211 * @param ctx read / write interface definitions
4212 * @param val Get the values of i2c_disable in
4213 * reg CTRL4_C
4214 * @retval interface status (MANDATORY: return 0 -> no Error)
4215 *
4216 */
lsm6dso_i2c_interface_get(stmdev_ctx_t * ctx,lsm6dso_i2c_disable_t * val)4217 int32_t lsm6dso_i2c_interface_get(stmdev_ctx_t *ctx,
4218 lsm6dso_i2c_disable_t *val)
4219 {
4220 lsm6dso_ctrl4_c_t reg;
4221 int32_t ret;
4222
4223 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
4224
4225 switch (reg.i2c_disable)
4226 {
4227 case LSM6DSO_I2C_ENABLE:
4228 *val = LSM6DSO_I2C_ENABLE;
4229 break;
4230
4231 case LSM6DSO_I2C_DISABLE:
4232 *val = LSM6DSO_I2C_DISABLE;
4233 break;
4234
4235 default:
4236 *val = LSM6DSO_I2C_ENABLE;
4237 break;
4238 }
4239
4240 return ret;
4241 }
4242
4243 /**
4244 * @brief I3C Enable/Disable communication protocol[.set]
4245 *
4246 * @param ctx read / write interface definitions
4247 * @param val change the values of i3c_disable
4248 * in reg CTRL9_XL
4249 * @retval interface status (MANDATORY: return 0 -> no Error)
4250 *
4251 */
lsm6dso_i3c_disable_set(stmdev_ctx_t * ctx,lsm6dso_i3c_disable_t val)4252 int32_t lsm6dso_i3c_disable_set(stmdev_ctx_t *ctx,
4253 lsm6dso_i3c_disable_t val)
4254 {
4255 lsm6dso_i3c_bus_avb_t i3c_bus_avb;
4256 lsm6dso_ctrl9_xl_t ctrl9_xl;
4257 int32_t ret;
4258
4259 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
4260
4261 if (ret == 0)
4262 {
4263 ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
4264 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
4265 }
4266
4267 if (ret == 0)
4268 {
4269 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
4270 (uint8_t *)&i3c_bus_avb, 1);
4271 }
4272
4273 if (ret == 0)
4274 {
4275 i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
4276 ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB,
4277 (uint8_t *)&i3c_bus_avb, 1);
4278 }
4279
4280 return ret;
4281 }
4282
4283 /**
4284 * @brief I3C Enable/Disable communication protocol.[get]
4285 *
4286 * @param ctx read / write interface definitions
4287 * @param val change the values of i3c_disable in
4288 * reg CTRL9_XL
4289 * @retval interface status (MANDATORY: return 0 -> no Error)
4290 *
4291 */
lsm6dso_i3c_disable_get(stmdev_ctx_t * ctx,lsm6dso_i3c_disable_t * val)4292 int32_t lsm6dso_i3c_disable_get(stmdev_ctx_t *ctx,
4293 lsm6dso_i3c_disable_t *val)
4294 {
4295 lsm6dso_ctrl9_xl_t ctrl9_xl;
4296 lsm6dso_i3c_bus_avb_t i3c_bus_avb;
4297 int32_t ret;
4298
4299 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
4300
4301 if (ret == 0)
4302 {
4303 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
4304 (uint8_t *)&i3c_bus_avb, 1);
4305
4306 switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel)
4307 {
4308 case LSM6DSO_I3C_DISABLE:
4309 *val = LSM6DSO_I3C_DISABLE;
4310 break;
4311
4312 case LSM6DSO_I3C_ENABLE_T_50us:
4313 *val = LSM6DSO_I3C_ENABLE_T_50us;
4314 break;
4315
4316 case LSM6DSO_I3C_ENABLE_T_2us:
4317 *val = LSM6DSO_I3C_ENABLE_T_2us;
4318 break;
4319
4320 case LSM6DSO_I3C_ENABLE_T_1ms:
4321 *val = LSM6DSO_I3C_ENABLE_T_1ms;
4322 break;
4323
4324 case LSM6DSO_I3C_ENABLE_T_25ms:
4325 *val = LSM6DSO_I3C_ENABLE_T_25ms;
4326 break;
4327
4328 default:
4329 *val = LSM6DSO_I3C_DISABLE;
4330 break;
4331 }
4332 }
4333
4334 return ret;
4335 }
4336
4337 /**
4338 * @}
4339 *
4340 */
4341
4342 /**
4343 * @defgroup LSM6DSO_interrupt_pins
4344 * @brief This section groups all the functions that manage interrupt pins
4345 * @{
4346 *
4347 */
4348
4349 /**
4350 * @brief Connect/Disconnect INT1 internal pull-down.[set]
4351 *
4352 * @param ctx read / write interface definitions
4353 * @param val change the values of pd_dis_int1 in reg I3C_BUS_AVB
4354 * @retval interface status (MANDATORY: return 0 -> no Error)
4355 *
4356 */
lsm6dso_int1_mode_set(stmdev_ctx_t * ctx,lsm6dso_int1_pd_en_t val)4357 int32_t lsm6dso_int1_mode_set(stmdev_ctx_t *ctx,
4358 lsm6dso_int1_pd_en_t val)
4359 {
4360 lsm6dso_i3c_bus_avb_t reg;
4361 int32_t ret;
4362
4363 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)®, 1);
4364
4365 if (ret == 0)
4366 {
4367 reg.pd_dis_int1 = (uint8_t)val;
4368 ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)®, 1);
4369 }
4370
4371 return ret;
4372 }
4373
4374 /**
4375 * @brief Connect/Disconnect INT1 internal pull-down.[get]
4376 *
4377 * @param ctx read / write interface definitions
4378 * @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB
4379 * @retval interface status (MANDATORY: return 0 -> no Error)
4380 *
4381 */
lsm6dso_int1_mode_get(stmdev_ctx_t * ctx,lsm6dso_int1_pd_en_t * val)4382 int32_t lsm6dso_int1_mode_get(stmdev_ctx_t *ctx,
4383 lsm6dso_int1_pd_en_t *val)
4384 {
4385 lsm6dso_i3c_bus_avb_t reg;
4386 int32_t ret;
4387
4388 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB, (uint8_t *)®, 1);
4389
4390 switch (reg.pd_dis_int1)
4391 {
4392 case LSM6DSO_PULL_DOWN_DISC:
4393 *val = LSM6DSO_PULL_DOWN_DISC;
4394 break;
4395
4396 case LSM6DSO_PULL_DOWN_CONNECT:
4397 *val = LSM6DSO_PULL_DOWN_CONNECT;
4398 break;
4399
4400 default:
4401 *val = LSM6DSO_PULL_DOWN_DISC;
4402 break;
4403 }
4404
4405 return ret;
4406 }
4407
4408 /**
4409 * @brief Push-pull/open drain selection on interrupt pads.[set]
4410 *
4411 * @param ctx read / write interface definitions
4412 * @param val change the values of pp_od in reg CTRL3_C
4413 * @retval interface status (MANDATORY: return 0 -> no Error)
4414 *
4415 */
lsm6dso_pin_mode_set(stmdev_ctx_t * ctx,lsm6dso_pp_od_t val)4416 int32_t lsm6dso_pin_mode_set(stmdev_ctx_t *ctx, lsm6dso_pp_od_t val)
4417 {
4418 lsm6dso_ctrl3_c_t reg;
4419 int32_t ret;
4420
4421 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
4422
4423 if (ret == 0)
4424 {
4425 reg.pp_od = (uint8_t)val;
4426 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
4427 }
4428
4429 return ret;
4430 }
4431
4432 /**
4433 * @brief Push-pull/open drain selection on interrupt pads.[get]
4434 *
4435 * @param ctx read / write interface definitions
4436 * @param val Get the values of pp_od in reg CTRL3_C
4437 * @retval interface status (MANDATORY: return 0 -> no Error)
4438 *
4439 */
lsm6dso_pin_mode_get(stmdev_ctx_t * ctx,lsm6dso_pp_od_t * val)4440 int32_t lsm6dso_pin_mode_get(stmdev_ctx_t *ctx, lsm6dso_pp_od_t *val)
4441 {
4442 lsm6dso_ctrl3_c_t reg;
4443 int32_t ret;
4444
4445 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
4446
4447 switch (reg.pp_od)
4448 {
4449 case LSM6DSO_PUSH_PULL:
4450 *val = LSM6DSO_PUSH_PULL;
4451 break;
4452
4453 case LSM6DSO_OPEN_DRAIN:
4454 *val = LSM6DSO_OPEN_DRAIN;
4455 break;
4456
4457 default:
4458 *val = LSM6DSO_PUSH_PULL;
4459 break;
4460 }
4461
4462 return ret;
4463 }
4464
4465 /**
4466 * @brief Interrupt active-high/low.[set]
4467 *
4468 * @param ctx read / write interface definitions
4469 * @param val change the values of h_lactive in reg CTRL3_C
4470 * @retval interface status (MANDATORY: return 0 -> no Error)
4471 *
4472 */
lsm6dso_pin_polarity_set(stmdev_ctx_t * ctx,lsm6dso_h_lactive_t val)4473 int32_t lsm6dso_pin_polarity_set(stmdev_ctx_t *ctx,
4474 lsm6dso_h_lactive_t val)
4475 {
4476 lsm6dso_ctrl3_c_t reg;
4477 int32_t ret;
4478
4479 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
4480
4481 if (ret == 0)
4482 {
4483 reg.h_lactive = (uint8_t)val;
4484 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
4485 }
4486
4487 return ret;
4488 }
4489
4490 /**
4491 * @brief Interrupt active-high/low.[get]
4492 *
4493 * @param ctx read / write interface definitions
4494 * @param val Get the values of h_lactive in reg CTRL3_C
4495 * @retval interface status (MANDATORY: return 0 -> no Error)
4496 *
4497 */
lsm6dso_pin_polarity_get(stmdev_ctx_t * ctx,lsm6dso_h_lactive_t * val)4498 int32_t lsm6dso_pin_polarity_get(stmdev_ctx_t *ctx,
4499 lsm6dso_h_lactive_t *val)
4500 {
4501 lsm6dso_ctrl3_c_t reg;
4502 int32_t ret;
4503
4504 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)®, 1);
4505
4506 switch (reg.h_lactive)
4507 {
4508 case LSM6DSO_ACTIVE_HIGH:
4509 *val = LSM6DSO_ACTIVE_HIGH;
4510 break;
4511
4512 case LSM6DSO_ACTIVE_LOW:
4513 *val = LSM6DSO_ACTIVE_LOW;
4514 break;
4515
4516 default:
4517 *val = LSM6DSO_ACTIVE_HIGH;
4518 break;
4519 }
4520
4521 return ret;
4522 }
4523
4524 /**
4525 * @brief All interrupt signals become available on INT1 pin.[set]
4526 *
4527 * @param ctx read / write interface definitions
4528 * @param val change the values of int2_on_int1 in reg CTRL4_C
4529 * @retval interface status (MANDATORY: return 0 -> no Error)
4530 *
4531 */
lsm6dso_all_on_int1_set(stmdev_ctx_t * ctx,uint8_t val)4532 int32_t lsm6dso_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
4533 {
4534 lsm6dso_ctrl4_c_t reg;
4535 int32_t ret;
4536
4537 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
4538
4539 if (ret == 0)
4540 {
4541 reg.int2_on_int1 = val;
4542 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
4543 }
4544
4545 return ret;
4546 }
4547
4548 /**
4549 * @brief All interrupt signals become available on INT1 pin.[get]
4550 *
4551 * @param ctx read / write interface definitions
4552 * @param val change the values of int2_on_int1 in reg CTRL4_C
4553 * @retval interface status (MANDATORY: return 0 -> no Error)
4554 *
4555 */
lsm6dso_all_on_int1_get(stmdev_ctx_t * ctx,uint8_t * val)4556 int32_t lsm6dso_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
4557 {
4558 lsm6dso_ctrl4_c_t reg;
4559 int32_t ret;
4560
4561 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
4562 *val = reg.int2_on_int1;
4563
4564 return ret;
4565 }
4566
4567 /**
4568 * @brief Interrupt notification mode.[set]
4569 *
4570 * @param ctx read / write interface definitions
4571 * @param val change the values of lir in reg TAP_CFG0
4572 * @retval interface status (MANDATORY: return 0 -> no Error)
4573 *
4574 */
lsm6dso_int_notification_set(stmdev_ctx_t * ctx,lsm6dso_lir_t val)4575 int32_t lsm6dso_int_notification_set(stmdev_ctx_t *ctx,
4576 lsm6dso_lir_t val)
4577 {
4578 lsm6dso_tap_cfg0_t tap_cfg0;
4579 lsm6dso_page_rw_t page_rw;
4580 int32_t ret;
4581
4582 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
4583
4584 if (ret == 0)
4585 {
4586 tap_cfg0.lir = (uint8_t)val & 0x01U;
4587 tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
4588 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
4589 }
4590
4591 if (ret == 0)
4592 {
4593 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
4594 }
4595
4596 if (ret == 0)
4597 {
4598 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
4599 }
4600
4601 if (ret == 0)
4602 {
4603 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
4604 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
4605 }
4606
4607 if (ret == 0)
4608 {
4609 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
4610 }
4611
4612 return ret;
4613 }
4614
4615 /**
4616 * @brief Interrupt notification mode.[get]
4617 *
4618 * @param ctx read / write interface definitions
4619 * @param val Get the values of lir in reg TAP_CFG0
4620 * @retval interface status (MANDATORY: return 0 -> no Error)
4621 *
4622 */
lsm6dso_int_notification_get(stmdev_ctx_t * ctx,lsm6dso_lir_t * val)4623 int32_t lsm6dso_int_notification_get(stmdev_ctx_t *ctx,
4624 lsm6dso_lir_t *val)
4625 {
4626 lsm6dso_tap_cfg0_t tap_cfg0;
4627 lsm6dso_page_rw_t page_rw;
4628 int32_t ret;
4629
4630 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
4631
4632 if (ret == 0)
4633 {
4634 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
4635 }
4636
4637 if (ret == 0)
4638 {
4639 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
4640 }
4641
4642 if (ret == 0)
4643 {
4644 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
4645 }
4646
4647 if (ret == 0)
4648 {
4649 switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir)
4650 {
4651 case LSM6DSO_ALL_INT_PULSED:
4652 *val = LSM6DSO_ALL_INT_PULSED;
4653 break;
4654
4655 case LSM6DSO_BASE_LATCHED_EMB_PULSED:
4656 *val = LSM6DSO_BASE_LATCHED_EMB_PULSED;
4657 break;
4658
4659 case LSM6DSO_BASE_PULSED_EMB_LATCHED:
4660 *val = LSM6DSO_BASE_PULSED_EMB_LATCHED;
4661 break;
4662
4663 case LSM6DSO_ALL_INT_LATCHED:
4664 *val = LSM6DSO_ALL_INT_LATCHED;
4665 break;
4666
4667 default:
4668 *val = LSM6DSO_ALL_INT_PULSED;
4669 break;
4670 }
4671
4672 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
4673 }
4674
4675 if (ret == 0)
4676 {
4677 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
4678 }
4679
4680 if (ret == 0)
4681 {
4682 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
4683 }
4684
4685 return ret;
4686 }
4687
4688 /**
4689 * @}
4690 *
4691 */
4692
4693 /**
4694 * @defgroup LSM6DSO_Wake_Up_event
4695 * @brief This section groups all the functions that manage the Wake Up
4696 * event generation.
4697 * @{
4698 *
4699 */
4700
4701 /**
4702 * @brief Weight of 1 LSB of wakeup threshold.[set]
4703 * 0: 1 LSB =FS_XL / 64
4704 * 1: 1 LSB = FS_XL / 256
4705 *
4706 * @param ctx read / write interface definitions
4707 * @param val change the values of wake_ths_w in
4708 * reg WAKE_UP_DUR
4709 * @retval interface status (MANDATORY: return 0 -> no Error)
4710 *
4711 */
lsm6dso_wkup_ths_weight_set(stmdev_ctx_t * ctx,lsm6dso_wake_ths_w_t val)4712 int32_t lsm6dso_wkup_ths_weight_set(stmdev_ctx_t *ctx,
4713 lsm6dso_wake_ths_w_t val)
4714 {
4715 lsm6dso_wake_up_dur_t reg;
4716 int32_t ret;
4717
4718 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
4719
4720 if (ret == 0)
4721 {
4722 reg.wake_ths_w = (uint8_t)val;
4723 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
4724 }
4725
4726 return ret;
4727 }
4728
4729 /**
4730 * @brief Weight of 1 LSB of wakeup threshold.[get]
4731 * 0: 1 LSB =FS_XL / 64
4732 * 1: 1 LSB = FS_XL / 256
4733 *
4734 * @param ctx read / write interface definitions
4735 * @param val Get the values of wake_ths_w in
4736 * reg WAKE_UP_DUR
4737 * @retval interface status (MANDATORY: return 0 -> no Error)
4738 *
4739 */
lsm6dso_wkup_ths_weight_get(stmdev_ctx_t * ctx,lsm6dso_wake_ths_w_t * val)4740 int32_t lsm6dso_wkup_ths_weight_get(stmdev_ctx_t *ctx,
4741 lsm6dso_wake_ths_w_t *val)
4742 {
4743 lsm6dso_wake_up_dur_t reg;
4744 int32_t ret;
4745
4746 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
4747
4748 switch (reg.wake_ths_w)
4749 {
4750 case LSM6DSO_LSb_FS_DIV_64:
4751 *val = LSM6DSO_LSb_FS_DIV_64;
4752 break;
4753
4754 case LSM6DSO_LSb_FS_DIV_256:
4755 *val = LSM6DSO_LSb_FS_DIV_256;
4756 break;
4757
4758 default:
4759 *val = LSM6DSO_LSb_FS_DIV_64;
4760 break;
4761 }
4762
4763 return ret;
4764 }
4765
4766 /**
4767 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
4768 * WAKE_UP_DUR.[set]
4769 *
4770 * @param ctx read / write interface definitions
4771 * @param val change the values of wk_ths in reg WAKE_UP_THS
4772 * @retval interface status (MANDATORY: return 0 -> no Error)
4773 *
4774 */
lsm6dso_wkup_threshold_set(stmdev_ctx_t * ctx,uint8_t val)4775 int32_t lsm6dso_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
4776 {
4777 lsm6dso_wake_up_ths_t reg;
4778 int32_t ret;
4779
4780 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
4781
4782 if (ret == 0)
4783 {
4784 reg.wk_ths = val;
4785 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
4786 }
4787
4788 return ret;
4789 }
4790
4791 /**
4792 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
4793 * WAKE_UP_DUR.[get]
4794 *
4795 * @param ctx read / write interface definitions
4796 * @param val change the values of wk_ths in reg WAKE_UP_THS
4797 * @retval interface status (MANDATORY: return 0 -> no Error)
4798 *
4799 */
lsm6dso_wkup_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)4800 int32_t lsm6dso_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
4801 {
4802 lsm6dso_wake_up_ths_t reg;
4803 int32_t ret;
4804
4805 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
4806 *val = reg.wk_ths;
4807
4808 return ret;
4809 }
4810
4811 /**
4812 * @brief Wake up duration event.[set]
4813 * 1LSb = 1 / ODR
4814 *
4815 * @param ctx read / write interface definitions
4816 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
4817 * @retval interface status (MANDATORY: return 0 -> no Error)
4818 *
4819 */
lsm6dso_xl_usr_offset_on_wkup_set(stmdev_ctx_t * ctx,uint8_t val)4820 int32_t lsm6dso_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
4821 uint8_t val)
4822 {
4823 lsm6dso_wake_up_ths_t reg;
4824 int32_t ret;
4825
4826 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
4827
4828 if (ret == 0)
4829 {
4830 reg.usr_off_on_wu = val;
4831 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
4832 }
4833
4834 return ret;
4835 }
4836
4837 /**
4838 * @brief Wake up duration event.[get]
4839 * 1LSb = 1 / ODR
4840 *
4841 * @param ctx read / write interface definitions
4842 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
4843 * @retval interface status (MANDATORY: return 0 -> no Error)
4844 *
4845 */
lsm6dso_xl_usr_offset_on_wkup_get(stmdev_ctx_t * ctx,uint8_t * val)4846 int32_t lsm6dso_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
4847 uint8_t *val)
4848 {
4849 lsm6dso_wake_up_ths_t reg;
4850 int32_t ret;
4851
4852 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
4853 *val = reg.usr_off_on_wu;
4854
4855 return ret;
4856 }
4857
4858 /**
4859 * @brief Wake up duration event.[set]
4860 * 1LSb = 1 / ODR
4861 *
4862 * @param ctx read / write interface definitions
4863 * @param val change the values of wake_dur in reg WAKE_UP_DUR
4864 * @retval interface status (MANDATORY: return 0 -> no Error)
4865 *
4866 */
lsm6dso_wkup_dur_set(stmdev_ctx_t * ctx,uint8_t val)4867 int32_t lsm6dso_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
4868 {
4869 lsm6dso_wake_up_dur_t reg;
4870 int32_t ret;
4871
4872 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
4873
4874 if (ret == 0)
4875 {
4876 reg.wake_dur = val;
4877 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
4878 }
4879
4880 return ret;
4881 }
4882
4883 /**
4884 * @brief Wake up duration event.[get]
4885 * 1LSb = 1 / ODR
4886 *
4887 * @param ctx read / write interface definitions
4888 * @param val change the values of wake_dur in reg WAKE_UP_DUR
4889 * @retval interface status (MANDATORY: return 0 -> no Error)
4890 *
4891 */
lsm6dso_wkup_dur_get(stmdev_ctx_t * ctx,uint8_t * val)4892 int32_t lsm6dso_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
4893 {
4894 lsm6dso_wake_up_dur_t reg;
4895 int32_t ret;
4896
4897 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
4898 *val = reg.wake_dur;
4899
4900 return ret;
4901 }
4902
4903 /**
4904 * @}
4905 *
4906 */
4907
4908 /**
4909 * @defgroup LSM6DSO_ Activity/Inactivity_detection
4910 * @brief This section groups all the functions concerning
4911 * activity/inactivity detection.
4912 * @{
4913 *
4914 */
4915
4916 /**
4917 * @brief Enables gyroscope Sleep mode.[set]
4918 *
4919 * @param ctx read / write interface definitions
4920 * @param val change the values of sleep_g in reg CTRL4_C
4921 * @retval interface status (MANDATORY: return 0 -> no Error)
4922 *
4923 */
lsm6dso_gy_sleep_mode_set(stmdev_ctx_t * ctx,uint8_t val)4924 int32_t lsm6dso_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
4925 {
4926 lsm6dso_ctrl4_c_t reg;
4927 int32_t ret;
4928
4929 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
4930
4931 if (ret == 0)
4932 {
4933 reg.sleep_g = val;
4934 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
4935 }
4936
4937 return ret;
4938 }
4939
4940 /**
4941 * @brief Enables gyroscope Sleep mode.[get]
4942 *
4943 * @param ctx read / write interface definitions
4944 * @param val change the values of sleep_g in reg CTRL4_C
4945 * @retval interface status (MANDATORY: return 0 -> no Error)
4946 *
4947 */
lsm6dso_gy_sleep_mode_get(stmdev_ctx_t * ctx,uint8_t * val)4948 int32_t lsm6dso_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
4949 {
4950 lsm6dso_ctrl4_c_t reg;
4951 int32_t ret;
4952
4953 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)®, 1);
4954 *val = reg.sleep_g;
4955
4956 return ret;
4957 }
4958
4959 /**
4960 * @brief Drives the sleep status instead of
4961 * sleep change on INT pins
4962 * (only if INT1_SLEEP_CHANGE or
4963 * INT2_SLEEP_CHANGE bits are enabled).[set]
4964 *
4965 * @param ctx read / write interface definitions
4966 * @param val change the values of sleep_status_on_int in reg TAP_CFG0
4967 * @retval interface status (MANDATORY: return 0 -> no Error)
4968 *
4969 */
lsm6dso_act_pin_notification_set(stmdev_ctx_t * ctx,lsm6dso_sleep_status_on_int_t val)4970 int32_t lsm6dso_act_pin_notification_set(stmdev_ctx_t *ctx,
4971 lsm6dso_sleep_status_on_int_t val)
4972 {
4973 lsm6dso_tap_cfg0_t reg;
4974 int32_t ret;
4975
4976 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
4977
4978 if (ret == 0)
4979 {
4980 reg.sleep_status_on_int = (uint8_t)val;
4981 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
4982 }
4983
4984 return ret;
4985 }
4986
4987 /**
4988 * @brief Drives the sleep status instead of
4989 * sleep change on INT pins (only if
4990 * INT1_SLEEP_CHANGE or
4991 * INT2_SLEEP_CHANGE bits are enabled).[get]
4992 *
4993 * @param ctx read / write interface definitions
4994 * @param val Get the values of sleep_status_on_int in reg TAP_CFG0
4995 * @retval interface status (MANDATORY: return 0 -> no Error)
4996 *
4997 */
lsm6dso_act_pin_notification_get(stmdev_ctx_t * ctx,lsm6dso_sleep_status_on_int_t * val)4998 int32_t lsm6dso_act_pin_notification_get(stmdev_ctx_t *ctx,
4999 lsm6dso_sleep_status_on_int_t *val)
5000 {
5001 lsm6dso_tap_cfg0_t reg;
5002 int32_t ret;
5003
5004 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
5005
5006 switch (reg.sleep_status_on_int)
5007 {
5008 case LSM6DSO_DRIVE_SLEEP_CHG_EVENT:
5009 *val = LSM6DSO_DRIVE_SLEEP_CHG_EVENT;
5010 break;
5011
5012 case LSM6DSO_DRIVE_SLEEP_STATUS:
5013 *val = LSM6DSO_DRIVE_SLEEP_STATUS;
5014 break;
5015
5016 default:
5017 *val = LSM6DSO_DRIVE_SLEEP_CHG_EVENT;
5018 break;
5019 }
5020
5021 return ret;
5022 }
5023
5024 /**
5025 * @brief Enable inactivity function.[set]
5026 *
5027 * @param ctx read / write interface definitions
5028 * @param val change the values of inact_en in reg TAP_CFG2
5029 * @retval interface status (MANDATORY: return 0 -> no Error)
5030 *
5031 */
lsm6dso_act_mode_set(stmdev_ctx_t * ctx,lsm6dso_inact_en_t val)5032 int32_t lsm6dso_act_mode_set(stmdev_ctx_t *ctx,
5033 lsm6dso_inact_en_t val)
5034 {
5035 lsm6dso_tap_cfg2_t reg;
5036 int32_t ret;
5037
5038 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1);
5039
5040 if (ret == 0)
5041 {
5042 reg.inact_en = (uint8_t)val;
5043 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1);
5044 }
5045
5046 return ret;
5047 }
5048
5049 /**
5050 * @brief Enable inactivity function.[get]
5051 *
5052 * @param ctx read / write interface definitions
5053 * @param val Get the values of inact_en in reg TAP_CFG2
5054 * @retval interface status (MANDATORY: return 0 -> no Error)
5055 *
5056 */
lsm6dso_act_mode_get(stmdev_ctx_t * ctx,lsm6dso_inact_en_t * val)5057 int32_t lsm6dso_act_mode_get(stmdev_ctx_t *ctx,
5058 lsm6dso_inact_en_t *val)
5059 {
5060 lsm6dso_tap_cfg2_t reg;
5061 int32_t ret;
5062
5063 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1);
5064
5065 switch (reg.inact_en)
5066 {
5067 case LSM6DSO_XL_AND_GY_NOT_AFFECTED:
5068 *val = LSM6DSO_XL_AND_GY_NOT_AFFECTED;
5069 break;
5070
5071 case LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED:
5072 *val = LSM6DSO_XL_12Hz5_GY_NOT_AFFECTED;
5073 break;
5074
5075 case LSM6DSO_XL_12Hz5_GY_SLEEP:
5076 *val = LSM6DSO_XL_12Hz5_GY_SLEEP;
5077 break;
5078
5079 case LSM6DSO_XL_12Hz5_GY_PD:
5080 *val = LSM6DSO_XL_12Hz5_GY_PD;
5081 break;
5082
5083 default:
5084 *val = LSM6DSO_XL_AND_GY_NOT_AFFECTED;
5085 break;
5086 }
5087
5088 return ret;
5089 }
5090
5091 /**
5092 * @brief Duration to go in sleep mode.[set]
5093 * 1 LSb = 512 / ODR
5094 *
5095 * @param ctx read / write interface definitions
5096 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
5097 * @retval interface status (MANDATORY: return 0 -> no Error)
5098 *
5099 */
lsm6dso_act_sleep_dur_set(stmdev_ctx_t * ctx,uint8_t val)5100 int32_t lsm6dso_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
5101 {
5102 lsm6dso_wake_up_dur_t reg;
5103 int32_t ret;
5104
5105 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
5106
5107 if (ret == 0)
5108 {
5109 reg.sleep_dur = val;
5110 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
5111 }
5112
5113 return ret;
5114 }
5115
5116 /**
5117 * @brief Duration to go in sleep mode.[get]
5118 * 1 LSb = 512 / ODR
5119 *
5120 * @param ctx read / write interface definitions
5121 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
5122 * @retval interface status (MANDATORY: return 0 -> no Error)
5123 *
5124 */
lsm6dso_act_sleep_dur_get(stmdev_ctx_t * ctx,uint8_t * val)5125 int32_t lsm6dso_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
5126 {
5127 lsm6dso_wake_up_dur_t reg;
5128 int32_t ret;
5129
5130 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR, (uint8_t *)®, 1);
5131 *val = reg.sleep_dur;
5132
5133 return ret;
5134 }
5135
5136 /**
5137 * @}
5138 *
5139 */
5140
5141 /**
5142 * @defgroup LSM6DSO_tap_generator
5143 * @brief This section groups all the functions that manage the
5144 * tap and double tap event generation.
5145 * @{
5146 *
5147 */
5148
5149 /**
5150 * @brief Enable Z direction in tap recognition.[set]
5151 *
5152 * @param ctx read / write interface definitions
5153 * @param val change the values of tap_z_en in reg TAP_CFG0
5154 * @retval interface status (MANDATORY: return 0 -> no Error)
5155 *
5156 */
lsm6dso_tap_detection_on_z_set(stmdev_ctx_t * ctx,uint8_t val)5157 int32_t lsm6dso_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
5158 {
5159 lsm6dso_tap_cfg0_t reg;
5160 int32_t ret;
5161
5162 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
5163
5164 if (ret == 0)
5165 {
5166 reg.tap_z_en = val;
5167 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
5168 }
5169
5170 return ret;
5171 }
5172
5173 /**
5174 * @brief Enable Z direction in tap recognition.[get]
5175 *
5176 * @param ctx read / write interface definitions
5177 * @param val change the values of tap_z_en in reg TAP_CFG0
5178 * @retval interface status (MANDATORY: return 0 -> no Error)
5179 *
5180 */
lsm6dso_tap_detection_on_z_get(stmdev_ctx_t * ctx,uint8_t * val)5181 int32_t lsm6dso_tap_detection_on_z_get(stmdev_ctx_t *ctx,
5182 uint8_t *val)
5183 {
5184 lsm6dso_tap_cfg0_t reg;
5185 int32_t ret;
5186
5187 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
5188 *val = reg.tap_z_en;
5189
5190 return ret;
5191 }
5192
5193 /**
5194 * @brief Enable Y direction in tap recognition.[set]
5195 *
5196 * @param ctx read / write interface definitions
5197 * @param val change the values of tap_y_en in reg TAP_CFG0
5198 * @retval interface status (MANDATORY: return 0 -> no Error)
5199 *
5200 */
lsm6dso_tap_detection_on_y_set(stmdev_ctx_t * ctx,uint8_t val)5201 int32_t lsm6dso_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
5202 {
5203 lsm6dso_tap_cfg0_t reg;
5204 int32_t ret;
5205
5206 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
5207
5208 if (ret == 0)
5209 {
5210 reg.tap_y_en = val;
5211 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
5212 }
5213
5214 return ret;
5215 }
5216
5217 /**
5218 * @brief Enable Y direction in tap recognition.[get]
5219 *
5220 * @param ctx read / write interface definitions
5221 * @param val change the values of tap_y_en in reg TAP_CFG0
5222 * @retval interface status (MANDATORY: return 0 -> no Error)
5223 *
5224 */
lsm6dso_tap_detection_on_y_get(stmdev_ctx_t * ctx,uint8_t * val)5225 int32_t lsm6dso_tap_detection_on_y_get(stmdev_ctx_t *ctx,
5226 uint8_t *val)
5227 {
5228 lsm6dso_tap_cfg0_t reg;
5229 int32_t ret;
5230
5231 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
5232 *val = reg.tap_y_en;
5233
5234 return ret;
5235 }
5236
5237 /**
5238 * @brief Enable X direction in tap recognition.[set]
5239 *
5240 * @param ctx read / write interface definitions
5241 * @param val change the values of tap_x_en in reg TAP_CFG0
5242 * @retval interface status (MANDATORY: return 0 -> no Error)
5243 *
5244 */
lsm6dso_tap_detection_on_x_set(stmdev_ctx_t * ctx,uint8_t val)5245 int32_t lsm6dso_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
5246 {
5247 lsm6dso_tap_cfg0_t reg;
5248 int32_t ret;
5249
5250 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
5251
5252 if (ret == 0)
5253 {
5254 reg.tap_x_en = val;
5255 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
5256 }
5257
5258 return ret;
5259 }
5260
5261 /**
5262 * @brief Enable X direction in tap recognition.[get]
5263 *
5264 * @param ctx read / write interface definitions
5265 * @param val change the values of tap_x_en in reg TAP_CFG0
5266 * @retval interface status (MANDATORY: return 0 -> no Error)
5267 *
5268 */
lsm6dso_tap_detection_on_x_get(stmdev_ctx_t * ctx,uint8_t * val)5269 int32_t lsm6dso_tap_detection_on_x_get(stmdev_ctx_t *ctx,
5270 uint8_t *val)
5271 {
5272 lsm6dso_tap_cfg0_t reg;
5273 int32_t ret;
5274
5275 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *)®, 1);
5276 *val = reg.tap_x_en;
5277
5278 return ret;
5279 }
5280
5281 /**
5282 * @brief X-axis tap recognition threshold.[set]
5283 *
5284 * @param ctx read / write interface definitions
5285 * @param val change the values of tap_ths_x in reg TAP_CFG1
5286 * @retval interface status (MANDATORY: return 0 -> no Error)
5287 *
5288 */
lsm6dso_tap_threshold_x_set(stmdev_ctx_t * ctx,uint8_t val)5289 int32_t lsm6dso_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
5290 {
5291 lsm6dso_tap_cfg1_t reg;
5292 int32_t ret;
5293
5294 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1);
5295
5296 if (ret == 0)
5297 {
5298 reg.tap_ths_x = val;
5299 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1);
5300 }
5301
5302 return ret;
5303 }
5304
5305 /**
5306 * @brief X-axis tap recognition threshold.[get]
5307 *
5308 * @param ctx read / write interface definitions
5309 * @param val change the values of tap_ths_x in reg TAP_CFG1
5310 * @retval interface status (MANDATORY: return 0 -> no Error)
5311 *
5312 */
lsm6dso_tap_threshold_x_get(stmdev_ctx_t * ctx,uint8_t * val)5313 int32_t lsm6dso_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
5314 {
5315 lsm6dso_tap_cfg1_t reg;
5316 int32_t ret;
5317
5318 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1);
5319 *val = reg.tap_ths_x;
5320
5321 return ret;
5322 }
5323
5324 /**
5325 * @brief Selection of axis priority for TAP detection.[set]
5326 *
5327 * @param ctx read / write interface definitions
5328 * @param val change the values of tap_priority in
5329 * reg TAP_CFG1
5330 * @retval interface status (MANDATORY: return 0 -> no Error)
5331 *
5332 */
lsm6dso_tap_axis_priority_set(stmdev_ctx_t * ctx,lsm6dso_tap_priority_t val)5333 int32_t lsm6dso_tap_axis_priority_set(stmdev_ctx_t *ctx,
5334 lsm6dso_tap_priority_t val)
5335 {
5336 lsm6dso_tap_cfg1_t reg;
5337 int32_t ret;
5338
5339 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1);
5340
5341 if (ret == 0)
5342 {
5343 reg.tap_priority = (uint8_t)val;
5344 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1);
5345 }
5346
5347 return ret;
5348 }
5349
5350 /**
5351 * @brief Selection of axis priority for TAP detection.[get]
5352 *
5353 * @param ctx read / write interface definitions
5354 * @param val Get the values of tap_priority in
5355 * reg TAP_CFG1
5356 * @retval interface status (MANDATORY: return 0 -> no Error)
5357 *
5358 */
lsm6dso_tap_axis_priority_get(stmdev_ctx_t * ctx,lsm6dso_tap_priority_t * val)5359 int32_t lsm6dso_tap_axis_priority_get(stmdev_ctx_t *ctx,
5360 lsm6dso_tap_priority_t *val)
5361 {
5362 lsm6dso_tap_cfg1_t reg;
5363 int32_t ret;
5364
5365 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG1, (uint8_t *)®, 1);
5366
5367 switch (reg.tap_priority)
5368 {
5369 case LSM6DSO_XYZ:
5370 *val = LSM6DSO_XYZ;
5371 break;
5372
5373 case LSM6DSO_YXZ:
5374 *val = LSM6DSO_YXZ;
5375 break;
5376
5377 case LSM6DSO_XZY:
5378 *val = LSM6DSO_XZY;
5379 break;
5380
5381 case LSM6DSO_ZYX:
5382 *val = LSM6DSO_ZYX;
5383 break;
5384
5385 case LSM6DSO_YZX:
5386 *val = LSM6DSO_YZX;
5387 break;
5388
5389 case LSM6DSO_ZXY:
5390 *val = LSM6DSO_ZXY;
5391 break;
5392
5393 default:
5394 *val = LSM6DSO_XYZ;
5395 break;
5396 }
5397
5398 return ret;
5399 }
5400
5401 /**
5402 * @brief Y-axis tap recognition threshold.[set]
5403 *
5404 * @param ctx read / write interface definitions
5405 * @param val change the values of tap_ths_y in reg TAP_CFG2
5406 * @retval interface status (MANDATORY: return 0 -> no Error)
5407 *
5408 */
lsm6dso_tap_threshold_y_set(stmdev_ctx_t * ctx,uint8_t val)5409 int32_t lsm6dso_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
5410 {
5411 lsm6dso_tap_cfg2_t reg;
5412 int32_t ret;
5413
5414 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1);
5415
5416 if (ret == 0)
5417 {
5418 reg.tap_ths_y = val;
5419 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1);
5420 }
5421
5422 return ret;
5423 }
5424
5425 /**
5426 * @brief Y-axis tap recognition threshold.[get]
5427 *
5428 * @param ctx read / write interface definitions
5429 * @param val change the values of tap_ths_y in reg TAP_CFG2
5430 * @retval interface status (MANDATORY: return 0 -> no Error)
5431 *
5432 */
lsm6dso_tap_threshold_y_get(stmdev_ctx_t * ctx,uint8_t * val)5433 int32_t lsm6dso_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
5434 {
5435 lsm6dso_tap_cfg2_t reg;
5436 int32_t ret;
5437
5438 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *)®, 1);
5439 *val = reg.tap_ths_y;
5440
5441 return ret;
5442 }
5443
5444 /**
5445 * @brief Z-axis recognition threshold.[set]
5446 *
5447 * @param ctx read / write interface definitions
5448 * @param val change the values of tap_ths_z in reg TAP_THS_6D
5449 * @retval interface status (MANDATORY: return 0 -> no Error)
5450 *
5451 */
lsm6dso_tap_threshold_z_set(stmdev_ctx_t * ctx,uint8_t val)5452 int32_t lsm6dso_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
5453 {
5454 lsm6dso_tap_ths_6d_t reg;
5455 int32_t ret;
5456
5457 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
5458
5459 if (ret == 0)
5460 {
5461 reg.tap_ths_z = val;
5462 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
5463 }
5464
5465 return ret;
5466 }
5467
5468 /**
5469 * @brief Z-axis recognition threshold.[get]
5470 *
5471 * @param ctx read / write interface definitions
5472 * @param val change the values of tap_ths_z in reg TAP_THS_6D
5473 * @retval interface status (MANDATORY: return 0 -> no Error)
5474 *
5475 */
lsm6dso_tap_threshold_z_get(stmdev_ctx_t * ctx,uint8_t * val)5476 int32_t lsm6dso_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
5477 {
5478 lsm6dso_tap_ths_6d_t reg;
5479 int32_t ret;
5480
5481 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
5482 *val = reg.tap_ths_z;
5483
5484 return ret;
5485 }
5486
5487 /**
5488 * @brief Maximum duration is the maximum time of an
5489 * over threshold signal detection to be recognized
5490 * as a tap event. The default value of these bits
5491 * is 00b which corresponds to 4*ODR_XL time.
5492 * If the SHOCK[1:0] bits are set to a different
5493 * value, 1LSB corresponds to 8*ODR_XL time.[set]
5494 *
5495 * @param ctx read / write interface definitions
5496 * @param val change the values of shock in reg INT_DUR2
5497 * @retval interface status (MANDATORY: return 0 -> no Error)
5498 *
5499 */
lsm6dso_tap_shock_set(stmdev_ctx_t * ctx,uint8_t val)5500 int32_t lsm6dso_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
5501 {
5502 lsm6dso_int_dur2_t reg;
5503 int32_t ret;
5504
5505 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
5506
5507 if (ret == 0)
5508 {
5509 reg.shock = val;
5510 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
5511 }
5512
5513 return ret;
5514 }
5515
5516 /**
5517 * @brief Maximum duration is the maximum time of an
5518 * over threshold signal detection to be recognized
5519 * as a tap event. The default value of these bits
5520 * is 00b which corresponds to 4*ODR_XL time.
5521 * If the SHOCK[1:0] bits are set to a different
5522 * value, 1LSB corresponds to 8*ODR_XL time.[get]
5523 *
5524 * @param ctx read / write interface definitions
5525 * @param val change the values of shock in reg INT_DUR2
5526 * @retval interface status (MANDATORY: return 0 -> no Error)
5527 *
5528 */
lsm6dso_tap_shock_get(stmdev_ctx_t * ctx,uint8_t * val)5529 int32_t lsm6dso_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
5530 {
5531 lsm6dso_int_dur2_t reg;
5532 int32_t ret;
5533
5534 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
5535 *val = reg.shock;
5536
5537 return ret;
5538 }
5539
5540 /**
5541 * @brief Quiet time is the time after the first detected
5542 * tap in which there must not be any over threshold
5543 * event.
5544 * The default value of these bits is 00b which
5545 * corresponds to 2*ODR_XL time. If the QUIET[1:0]
5546 * bits are set to a different value,
5547 * 1LSB corresponds to 4*ODR_XL time.[set]
5548 *
5549 * @param ctx read / write interface definitions
5550 * @param val change the values of quiet in reg INT_DUR2
5551 * @retval interface status (MANDATORY: return 0 -> no Error)
5552 *
5553 */
lsm6dso_tap_quiet_set(stmdev_ctx_t * ctx,uint8_t val)5554 int32_t lsm6dso_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
5555 {
5556 lsm6dso_int_dur2_t reg;
5557 int32_t ret;
5558
5559 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
5560
5561 if (ret == 0)
5562 {
5563 reg.quiet = val;
5564 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
5565 }
5566
5567 return ret;
5568 }
5569
5570 /**
5571 * @brief Quiet time is the time after the first detected
5572 * tap in which there must not be any over threshold
5573 * event.
5574 * The default value of these bits is 00b which
5575 * corresponds to 2*ODR_XL time.
5576 * If the QUIET[1:0] bits are set to a different
5577 * value, 1LSB corresponds to 4*ODR_XL time.[get]
5578 *
5579 * @param ctx read / write interface definitions
5580 * @param val change the values of quiet in reg INT_DUR2
5581 * @retval interface status (MANDATORY: return 0 -> no Error)
5582 *
5583 */
lsm6dso_tap_quiet_get(stmdev_ctx_t * ctx,uint8_t * val)5584 int32_t lsm6dso_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
5585 {
5586 lsm6dso_int_dur2_t reg;
5587 int32_t ret;
5588
5589 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
5590 *val = reg.quiet;
5591
5592 return ret;
5593 }
5594
5595 /**
5596 * @brief When double tap recognition is enabled,
5597 * this register expresses the maximum time
5598 * between two consecutive detected taps to
5599 * determine a double tap event.
5600 * The default value of these bits is 0000b which
5601 * corresponds to 16*ODR_XL time.
5602 * If the DUR[3:0] bits are set to a different value,
5603 * 1LSB corresponds to 32*ODR_XL time.[set]
5604 *
5605 * @param ctx read / write interface definitions
5606 * @param val change the values of dur in reg INT_DUR2
5607 * @retval interface status (MANDATORY: return 0 -> no Error)
5608 *
5609 */
lsm6dso_tap_dur_set(stmdev_ctx_t * ctx,uint8_t val)5610 int32_t lsm6dso_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
5611 {
5612 lsm6dso_int_dur2_t reg;
5613 int32_t ret;
5614
5615 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
5616
5617 if (ret == 0)
5618 {
5619 reg.dur = val;
5620 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
5621 }
5622
5623 return ret;
5624 }
5625
5626 /**
5627 * @brief When double tap recognition is enabled,
5628 * this register expresses the maximum time
5629 * between two consecutive detected taps to
5630 * determine a double tap event.
5631 * The default value of these bits is 0000b which
5632 * corresponds to 16*ODR_XL time. If the DUR[3:0]
5633 * bits are set to a different value,
5634 * 1LSB corresponds to 32*ODR_XL time.[get]
5635 *
5636 * @param ctx read / write interface definitions
5637 * @param val change the values of dur in reg INT_DUR2
5638 * @retval interface status (MANDATORY: return 0 -> no Error)
5639 *
5640 */
lsm6dso_tap_dur_get(stmdev_ctx_t * ctx,uint8_t * val)5641 int32_t lsm6dso_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
5642 {
5643 lsm6dso_int_dur2_t reg;
5644 int32_t ret;
5645
5646 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT_DUR2, (uint8_t *)®, 1);
5647 *val = reg.dur;
5648
5649 return ret;
5650 }
5651
5652 /**
5653 * @brief Single/double-tap event enable.[set]
5654 *
5655 * @param ctx read / write interface definitions
5656 * @param val change the values of single_double_tap in reg WAKE_UP_THS
5657 * @retval interface status (MANDATORY: return 0 -> no Error)
5658 *
5659 */
lsm6dso_tap_mode_set(stmdev_ctx_t * ctx,lsm6dso_single_double_tap_t val)5660 int32_t lsm6dso_tap_mode_set(stmdev_ctx_t *ctx,
5661 lsm6dso_single_double_tap_t val)
5662 {
5663 lsm6dso_wake_up_ths_t reg;
5664 int32_t ret;
5665
5666 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
5667
5668 if (ret == 0)
5669 {
5670 reg.single_double_tap = (uint8_t)val;
5671 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
5672 }
5673
5674 return ret;
5675 }
5676
5677 /**
5678 * @brief Single/double-tap event enable.[get]
5679 *
5680 * @param ctx read / write interface definitions
5681 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
5682 * @retval interface status (MANDATORY: return 0 -> no Error)
5683 *
5684 */
lsm6dso_tap_mode_get(stmdev_ctx_t * ctx,lsm6dso_single_double_tap_t * val)5685 int32_t lsm6dso_tap_mode_get(stmdev_ctx_t *ctx,
5686 lsm6dso_single_double_tap_t *val)
5687 {
5688 lsm6dso_wake_up_ths_t reg;
5689 int32_t ret;
5690
5691 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_THS, (uint8_t *)®, 1);
5692
5693 switch (reg.single_double_tap)
5694 {
5695 case LSM6DSO_ONLY_SINGLE:
5696 *val = LSM6DSO_ONLY_SINGLE;
5697 break;
5698
5699 case LSM6DSO_BOTH_SINGLE_DOUBLE:
5700 *val = LSM6DSO_BOTH_SINGLE_DOUBLE;
5701 break;
5702
5703 default:
5704 *val = LSM6DSO_ONLY_SINGLE;
5705 break;
5706 }
5707
5708 return ret;
5709 }
5710
5711 /**
5712 * @}
5713 *
5714 */
5715
5716 /**
5717 * @defgroup LSM6DSO_ Six_position_detection(6D/4D)
5718 * @brief This section groups all the functions concerning six position
5719 * detection (6D).
5720 * @{
5721 *
5722 */
5723
5724 /**
5725 * @brief Threshold for 4D/6D function.[set]
5726 *
5727 * @param ctx read / write interface definitions
5728 * @param val change the values of sixd_ths in reg TAP_THS_6D
5729 * @retval interface status (MANDATORY: return 0 -> no Error)
5730 *
5731 */
lsm6dso_6d_threshold_set(stmdev_ctx_t * ctx,lsm6dso_sixd_ths_t val)5732 int32_t lsm6dso_6d_threshold_set(stmdev_ctx_t *ctx,
5733 lsm6dso_sixd_ths_t val)
5734 {
5735 lsm6dso_tap_ths_6d_t reg;
5736 int32_t ret;
5737
5738 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
5739
5740 if (ret == 0)
5741 {
5742 reg.sixd_ths = (uint8_t)val;
5743 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
5744 }
5745
5746 return ret;
5747 }
5748
5749 /**
5750 * @brief Threshold for 4D/6D function.[get]
5751 *
5752 * @param ctx read / write interface definitions
5753 * @param val Get the values of sixd_ths in reg TAP_THS_6D
5754 * @retval interface status (MANDATORY: return 0 -> no Error)
5755 *
5756 */
lsm6dso_6d_threshold_get(stmdev_ctx_t * ctx,lsm6dso_sixd_ths_t * val)5757 int32_t lsm6dso_6d_threshold_get(stmdev_ctx_t *ctx,
5758 lsm6dso_sixd_ths_t *val)
5759 {
5760 lsm6dso_tap_ths_6d_t reg;
5761 int32_t ret;
5762
5763 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
5764
5765 switch (reg.sixd_ths)
5766 {
5767 case LSM6DSO_DEG_80:
5768 *val = LSM6DSO_DEG_80;
5769 break;
5770
5771 case LSM6DSO_DEG_70:
5772 *val = LSM6DSO_DEG_70;
5773 break;
5774
5775 case LSM6DSO_DEG_60:
5776 *val = LSM6DSO_DEG_60;
5777 break;
5778
5779 case LSM6DSO_DEG_50:
5780 *val = LSM6DSO_DEG_50;
5781 break;
5782
5783 default:
5784 *val = LSM6DSO_DEG_80;
5785 break;
5786 }
5787
5788 return ret;
5789 }
5790
5791 /**
5792 * @brief 4D orientation detection enable.[set]
5793 *
5794 * @param ctx read / write interface definitions
5795 * @param val change the values of d4d_en in reg TAP_THS_6D
5796 * @retval interface status (MANDATORY: return 0 -> no Error)
5797 *
5798 */
lsm6dso_4d_mode_set(stmdev_ctx_t * ctx,uint8_t val)5799 int32_t lsm6dso_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
5800 {
5801 lsm6dso_tap_ths_6d_t reg;
5802 int32_t ret;
5803
5804 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
5805
5806 if (ret == 0)
5807 {
5808 reg.d4d_en = val;
5809 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
5810 }
5811
5812 return ret;
5813 }
5814
5815 /**
5816 * @brief 4D orientation detection enable.[get]
5817 *
5818 * @param ctx read / write interface definitions
5819 * @param val change the values of d4d_en in reg TAP_THS_6D
5820 * @retval interface status (MANDATORY: return 0 -> no Error)
5821 *
5822 */
lsm6dso_4d_mode_get(stmdev_ctx_t * ctx,uint8_t * val)5823 int32_t lsm6dso_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
5824 {
5825 lsm6dso_tap_ths_6d_t reg;
5826 int32_t ret;
5827
5828 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_THS_6D, (uint8_t *)®, 1);
5829 *val = reg.d4d_en;
5830
5831 return ret;
5832 }
5833
5834 /**
5835 * @}
5836 *
5837 */
5838
5839 /**
5840 * @defgroup LSM6DSO_free_fall
5841 * @brief This section group all the functions concerning the free
5842 * fall detection.
5843 * @{
5844 *
5845 */
5846 /**
5847 * @brief Free fall threshold setting.[set]
5848 *
5849 * @param ctx read / write interface definitions
5850 * @param val change the values of ff_ths in reg FREE_FALL
5851 * @retval interface status (MANDATORY: return 0 -> no Error)
5852 *
5853 */
lsm6dso_ff_threshold_set(stmdev_ctx_t * ctx,lsm6dso_ff_ths_t val)5854 int32_t lsm6dso_ff_threshold_set(stmdev_ctx_t *ctx,
5855 lsm6dso_ff_ths_t val)
5856 {
5857 lsm6dso_free_fall_t reg;
5858 int32_t ret;
5859
5860 ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)®, 1);
5861
5862 if (ret == 0)
5863 {
5864 reg.ff_ths = (uint8_t)val;
5865 ret = lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)®, 1);
5866 }
5867
5868 return ret;
5869 }
5870
5871 /**
5872 * @brief Free fall threshold setting.[get]
5873 *
5874 * @param ctx read / write interface definitions
5875 * @param val Get the values of ff_ths in reg FREE_FALL
5876 * @retval interface status (MANDATORY: return 0 -> no Error)
5877 *
5878 */
lsm6dso_ff_threshold_get(stmdev_ctx_t * ctx,lsm6dso_ff_ths_t * val)5879 int32_t lsm6dso_ff_threshold_get(stmdev_ctx_t *ctx,
5880 lsm6dso_ff_ths_t *val)
5881 {
5882 lsm6dso_free_fall_t reg;
5883 int32_t ret;
5884
5885 ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)®, 1);
5886
5887 switch (reg.ff_ths)
5888 {
5889 case LSM6DSO_FF_TSH_156mg:
5890 *val = LSM6DSO_FF_TSH_156mg;
5891 break;
5892
5893 case LSM6DSO_FF_TSH_219mg:
5894 *val = LSM6DSO_FF_TSH_219mg;
5895 break;
5896
5897 case LSM6DSO_FF_TSH_250mg:
5898 *val = LSM6DSO_FF_TSH_250mg;
5899 break;
5900
5901 case LSM6DSO_FF_TSH_312mg:
5902 *val = LSM6DSO_FF_TSH_312mg;
5903 break;
5904
5905 case LSM6DSO_FF_TSH_344mg:
5906 *val = LSM6DSO_FF_TSH_344mg;
5907 break;
5908
5909 case LSM6DSO_FF_TSH_406mg:
5910 *val = LSM6DSO_FF_TSH_406mg;
5911 break;
5912
5913 case LSM6DSO_FF_TSH_469mg:
5914 *val = LSM6DSO_FF_TSH_469mg;
5915 break;
5916
5917 case LSM6DSO_FF_TSH_500mg:
5918 *val = LSM6DSO_FF_TSH_500mg;
5919 break;
5920
5921 default:
5922 *val = LSM6DSO_FF_TSH_156mg;
5923 break;
5924 }
5925
5926 return ret;
5927 }
5928
5929 /**
5930 * @brief Free-fall duration event.[set]
5931 * 1LSb = 1 / ODR
5932 *
5933 * @param ctx read / write interface definitions
5934 * @param val change the values of ff_dur in reg FREE_FALL
5935 * @retval interface status (MANDATORY: return 0 -> no Error)
5936 *
5937 */
lsm6dso_ff_dur_set(stmdev_ctx_t * ctx,uint8_t val)5938 int32_t lsm6dso_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
5939 {
5940 lsm6dso_wake_up_dur_t wake_up_dur;
5941 lsm6dso_free_fall_t free_fall;
5942 int32_t ret;
5943
5944 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR,
5945 (uint8_t *)&wake_up_dur, 1);
5946
5947 if (ret == 0)
5948 {
5949 ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&free_fall, 1);
5950 }
5951
5952 if (ret == 0)
5953 {
5954 wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
5955 free_fall.ff_dur = (uint8_t)val & 0x1FU;
5956 ret = lsm6dso_write_reg(ctx, LSM6DSO_WAKE_UP_DUR,
5957 (uint8_t *)&wake_up_dur, 1);
5958 }
5959
5960 if (ret == 0)
5961 {
5962 ret = lsm6dso_write_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&free_fall, 1);
5963 }
5964
5965 return ret;
5966 }
5967
5968 /**
5969 * @brief Free-fall duration event.[get]
5970 * 1LSb = 1 / ODR
5971 *
5972 * @param ctx read / write interface definitions
5973 * @param val change the values of ff_dur in reg FREE_FALL
5974 * @retval interface status (MANDATORY: return 0 -> no Error)
5975 *
5976 */
lsm6dso_ff_dur_get(stmdev_ctx_t * ctx,uint8_t * val)5977 int32_t lsm6dso_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
5978 {
5979 lsm6dso_wake_up_dur_t wake_up_dur;
5980 lsm6dso_free_fall_t free_fall;
5981 int32_t ret;
5982
5983 ret = lsm6dso_read_reg(ctx, LSM6DSO_WAKE_UP_DUR,
5984 (uint8_t *)&wake_up_dur, 1);
5985
5986 if (ret == 0)
5987 {
5988 ret = lsm6dso_read_reg(ctx, LSM6DSO_FREE_FALL, (uint8_t *)&free_fall, 1);
5989 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
5990 }
5991
5992 return ret;
5993 }
5994
5995 /**
5996 * @}
5997 *
5998 */
5999
6000 /**
6001 * @defgroup LSM6DSO_fifo
6002 * @brief This section group all the functions concerning the fifo usage
6003 * @{
6004 *
6005 */
6006
6007 /**
6008 * @brief FIFO watermark level selection.[set]
6009 *
6010 * @param ctx read / write interface definitions
6011 * @param val change the values of wtm in reg FIFO_CTRL1
6012 * @retval interface status (MANDATORY: return 0 -> no Error)
6013 *
6014 */
lsm6dso_fifo_watermark_set(stmdev_ctx_t * ctx,uint16_t val)6015 int32_t lsm6dso_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
6016 {
6017 lsm6dso_fifo_ctrl1_t fifo_ctrl1;
6018 lsm6dso_fifo_ctrl2_t fifo_ctrl2;
6019 int32_t ret;
6020
6021 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2,
6022 (uint8_t *)&fifo_ctrl2, 1);
6023
6024 if (ret == 0)
6025 {
6026 fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val;
6027 fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8);
6028 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL1,
6029 (uint8_t *)&fifo_ctrl1, 1);
6030 }
6031
6032 if (ret == 0)
6033 {
6034 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2,
6035 (uint8_t *)&fifo_ctrl2, 1);
6036 }
6037
6038 return ret;
6039 }
6040
6041 /**
6042 * @brief FIFO watermark level selection.[get]
6043 *
6044 * @param ctx read / write interface definitions
6045 * @param val change the values of wtm in reg FIFO_CTRL1
6046 * @retval interface status (MANDATORY: return 0 -> no Error)
6047 *
6048 */
lsm6dso_fifo_watermark_get(stmdev_ctx_t * ctx,uint16_t * val)6049 int32_t lsm6dso_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
6050 {
6051 lsm6dso_fifo_ctrl1_t fifo_ctrl1;
6052 lsm6dso_fifo_ctrl2_t fifo_ctrl2;
6053 int32_t ret;
6054
6055 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL1,
6056 (uint8_t *)&fifo_ctrl1, 1);
6057
6058 if (ret == 0)
6059 {
6060 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2,
6061 (uint8_t *)&fifo_ctrl2, 1);
6062 *val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm;
6063 }
6064
6065 return ret;
6066 }
6067
6068 /**
6069 * @brief FIFO compression feature initialization request [set].
6070 *
6071 * @param ctx read / write interface definitions
6072 * @param val change the values of FIFO_COMPR_INIT in
6073 * reg EMB_FUNC_INIT_B
6074 * @retval interface status (MANDATORY: return 0 -> no Error)
6075 *
6076 */
lsm6dso_compression_algo_init_set(stmdev_ctx_t * ctx,uint8_t val)6077 int32_t lsm6dso_compression_algo_init_set(stmdev_ctx_t *ctx,
6078 uint8_t val)
6079 {
6080 lsm6dso_emb_func_init_b_t reg;
6081 int32_t ret;
6082
6083 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
6084
6085 if (ret == 0)
6086 {
6087 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1);
6088 }
6089
6090 if (ret == 0)
6091 {
6092 reg.fifo_compr_init = val;
6093 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1);
6094 }
6095
6096 if (ret == 0)
6097 {
6098 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
6099 }
6100
6101 return ret;
6102 }
6103
6104 /**
6105 * @brief FIFO compression feature initialization request [get].
6106 *
6107 * @param ctx read / write interface definitions
6108 * @param val change the values of FIFO_COMPR_INIT in
6109 * reg EMB_FUNC_INIT_B
6110 * @retval interface status (MANDATORY: return 0 -> no Error)
6111 *
6112 */
lsm6dso_compression_algo_init_get(stmdev_ctx_t * ctx,uint8_t * val)6113 int32_t lsm6dso_compression_algo_init_get(stmdev_ctx_t *ctx,
6114 uint8_t *val)
6115 {
6116 lsm6dso_emb_func_init_b_t reg;
6117 int32_t ret;
6118
6119 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
6120
6121 if (ret == 0)
6122 {
6123 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1);
6124 }
6125
6126 if (ret == 0)
6127 {
6128 *val = reg.fifo_compr_init;
6129 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
6130 }
6131
6132 return ret;
6133 }
6134
6135 /**
6136 * @brief Enable and configure compression algo.[set]
6137 *
6138 * @param ctx read / write interface definitions
6139 * @param val change the values of uncoptr_rate in
6140 * reg FIFO_CTRL2
6141 * @retval interface status (MANDATORY: return 0 -> no Error)
6142 *
6143 */
lsm6dso_compression_algo_set(stmdev_ctx_t * ctx,lsm6dso_uncoptr_rate_t val)6144 int32_t lsm6dso_compression_algo_set(stmdev_ctx_t *ctx,
6145 lsm6dso_uncoptr_rate_t val)
6146 {
6147 lsm6dso_fifo_ctrl2_t fifo_ctrl2;
6148 int32_t ret;
6149
6150 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2,
6151 (uint8_t *)&fifo_ctrl2, 1);
6152
6153 if (ret == 0)
6154 {
6155 fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
6156 fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
6157 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2,
6158 (uint8_t *)&fifo_ctrl2, 1);
6159 }
6160
6161 return ret;
6162 }
6163
6164 /**
6165 * @brief Enable and configure compression algo.[get]
6166 *
6167 * @param ctx read / write interface definitions
6168 * @param val Get the values of uncoptr_rate in
6169 * reg FIFO_CTRL2
6170 * @retval interface status (MANDATORY: return 0 -> no Error)
6171 *
6172 */
lsm6dso_compression_algo_get(stmdev_ctx_t * ctx,lsm6dso_uncoptr_rate_t * val)6173 int32_t lsm6dso_compression_algo_get(stmdev_ctx_t *ctx,
6174 lsm6dso_uncoptr_rate_t *val)
6175 {
6176 lsm6dso_fifo_ctrl2_t reg;
6177 int32_t ret;
6178
6179 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
6180
6181 switch ((reg.fifo_compr_rt_en << 2) | reg.uncoptr_rate)
6182 {
6183 case LSM6DSO_CMP_DISABLE:
6184 *val = LSM6DSO_CMP_DISABLE;
6185 break;
6186
6187 case LSM6DSO_CMP_ALWAYS:
6188 *val = LSM6DSO_CMP_ALWAYS;
6189 break;
6190
6191 case LSM6DSO_CMP_8_TO_1:
6192 *val = LSM6DSO_CMP_8_TO_1;
6193 break;
6194
6195 case LSM6DSO_CMP_16_TO_1:
6196 *val = LSM6DSO_CMP_16_TO_1;
6197 break;
6198
6199 case LSM6DSO_CMP_32_TO_1:
6200 *val = LSM6DSO_CMP_32_TO_1;
6201 break;
6202
6203 default:
6204 *val = LSM6DSO_CMP_DISABLE;
6205 break;
6206 }
6207
6208 return ret;
6209 }
6210
6211 /**
6212 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
6213 *
6214 * @param ctx read / write interface definitions
6215 * @param val change the values of odrchg_en in reg FIFO_CTRL2
6216 * @retval interface status (MANDATORY: return 0 -> no Error)
6217 *
6218 */
lsm6dso_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t * ctx,uint8_t val)6219 int32_t lsm6dso_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
6220 uint8_t val)
6221 {
6222 lsm6dso_fifo_ctrl2_t reg;
6223 int32_t ret;
6224
6225 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
6226
6227 if (ret == 0)
6228 {
6229 reg.odrchg_en = val;
6230 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
6231 }
6232
6233 return ret;
6234 }
6235
6236 /**
6237 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
6238 *
6239 * @param ctx read / write interface definitions
6240 * @param val change the values of odrchg_en in reg FIFO_CTRL2
6241 * @retval interface status (MANDATORY: return 0 -> no Error)
6242 *
6243 */
lsm6dso_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t * ctx,uint8_t * val)6244 int32_t lsm6dso_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
6245 uint8_t *val)
6246 {
6247 lsm6dso_fifo_ctrl2_t reg;
6248 int32_t ret;
6249
6250 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
6251 *val = reg.odrchg_en;
6252
6253 return ret;
6254 }
6255
6256 /**
6257 * @brief Enables/Disables compression algorithm runtime.[set]
6258 *
6259 * @param ctx read / write interface definitions
6260 * @param val change the values of fifo_compr_rt_en in
6261 * reg FIFO_CTRL2
6262 * @retval interface status (MANDATORY: return 0 -> no Error)
6263 *
6264 */
lsm6dso_compression_algo_real_time_set(stmdev_ctx_t * ctx,uint8_t val)6265 int32_t lsm6dso_compression_algo_real_time_set(stmdev_ctx_t *ctx,
6266 uint8_t val)
6267 {
6268 lsm6dso_fifo_ctrl2_t reg;
6269 int32_t ret;
6270
6271 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
6272
6273 if (ret == 0)
6274 {
6275 reg.fifo_compr_rt_en = val;
6276 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
6277 }
6278
6279 return ret;
6280 }
6281
6282 /**
6283 * @brief Enables/Disables compression algorithm runtime. [get]
6284 *
6285 * @param ctx read / write interface definitions
6286 * @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2
6287 * @retval interface status (MANDATORY: return 0 -> no Error)
6288 *
6289 */
lsm6dso_compression_algo_real_time_get(stmdev_ctx_t * ctx,uint8_t * val)6290 int32_t lsm6dso_compression_algo_real_time_get(stmdev_ctx_t *ctx,
6291 uint8_t *val)
6292 {
6293 lsm6dso_fifo_ctrl2_t reg;
6294 int32_t ret;
6295
6296 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
6297 *val = reg.fifo_compr_rt_en;
6298
6299 return ret;
6300 }
6301
6302 /**
6303 * @brief Sensing chain FIFO stop values memorization at
6304 * threshold level.[set]
6305 *
6306 * @param ctx read / write interface definitions
6307 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2
6308 * @retval interface status (MANDATORY: return 0 -> no Error)
6309 *
6310 */
lsm6dso_fifo_stop_on_wtm_set(stmdev_ctx_t * ctx,uint8_t val)6311 int32_t lsm6dso_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
6312 {
6313 lsm6dso_fifo_ctrl2_t reg;
6314 int32_t ret;
6315
6316 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
6317
6318 if (ret == 0)
6319 {
6320 reg.stop_on_wtm = val;
6321 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
6322 }
6323
6324 return ret;
6325 }
6326
6327 /**
6328 * @brief Sensing chain FIFO stop values memorization at
6329 * threshold level.[get]
6330 *
6331 * @param ctx read / write interface definitions
6332 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2
6333 * @retval interface status (MANDATORY: return 0 -> no Error)
6334 *
6335 */
lsm6dso_fifo_stop_on_wtm_get(stmdev_ctx_t * ctx,uint8_t * val)6336 int32_t lsm6dso_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
6337 {
6338 lsm6dso_fifo_ctrl2_t reg;
6339 int32_t ret;
6340
6341 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL2, (uint8_t *)®, 1);
6342 *val = reg.stop_on_wtm;
6343
6344 return ret;
6345 }
6346
6347 /**
6348 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6349 * for accelerometer data.[set]
6350 *
6351 * @param ctx read / write interface definitions
6352 * @param val change the values of bdr_xl in reg FIFO_CTRL3
6353 * @retval interface status (MANDATORY: return 0 -> no Error)
6354 *
6355 */
lsm6dso_fifo_xl_batch_set(stmdev_ctx_t * ctx,lsm6dso_bdr_xl_t val)6356 int32_t lsm6dso_fifo_xl_batch_set(stmdev_ctx_t *ctx,
6357 lsm6dso_bdr_xl_t val)
6358 {
6359 lsm6dso_fifo_ctrl3_t reg;
6360 int32_t ret;
6361
6362 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1);
6363
6364 if (ret == 0)
6365 {
6366 reg.bdr_xl = (uint8_t)val;
6367 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1);
6368 }
6369
6370 return ret;
6371 }
6372
6373 /**
6374 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6375 * for accelerometer data.[get]
6376 *
6377 * @param ctx read / write interface definitions
6378 * @param val Get the values of bdr_xl in reg FIFO_CTRL3
6379 * @retval interface status (MANDATORY: return 0 -> no Error)
6380 *
6381 */
lsm6dso_fifo_xl_batch_get(stmdev_ctx_t * ctx,lsm6dso_bdr_xl_t * val)6382 int32_t lsm6dso_fifo_xl_batch_get(stmdev_ctx_t *ctx,
6383 lsm6dso_bdr_xl_t *val)
6384 {
6385 lsm6dso_fifo_ctrl3_t reg;
6386 int32_t ret;
6387
6388 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1);
6389
6390 switch (reg.bdr_xl)
6391 {
6392 case LSM6DSO_XL_NOT_BATCHED:
6393 *val = LSM6DSO_XL_NOT_BATCHED;
6394 break;
6395
6396 case LSM6DSO_XL_BATCHED_AT_12Hz5:
6397 *val = LSM6DSO_XL_BATCHED_AT_12Hz5;
6398 break;
6399
6400 case LSM6DSO_XL_BATCHED_AT_26Hz:
6401 *val = LSM6DSO_XL_BATCHED_AT_26Hz;
6402 break;
6403
6404 case LSM6DSO_XL_BATCHED_AT_52Hz:
6405 *val = LSM6DSO_XL_BATCHED_AT_52Hz;
6406 break;
6407
6408 case LSM6DSO_XL_BATCHED_AT_104Hz:
6409 *val = LSM6DSO_XL_BATCHED_AT_104Hz;
6410 break;
6411
6412 case LSM6DSO_XL_BATCHED_AT_208Hz:
6413 *val = LSM6DSO_XL_BATCHED_AT_208Hz;
6414 break;
6415
6416 case LSM6DSO_XL_BATCHED_AT_417Hz:
6417 *val = LSM6DSO_XL_BATCHED_AT_417Hz;
6418 break;
6419
6420 case LSM6DSO_XL_BATCHED_AT_833Hz:
6421 *val = LSM6DSO_XL_BATCHED_AT_833Hz;
6422 break;
6423
6424 case LSM6DSO_XL_BATCHED_AT_1667Hz:
6425 *val = LSM6DSO_XL_BATCHED_AT_1667Hz;
6426 break;
6427
6428 case LSM6DSO_XL_BATCHED_AT_3333Hz:
6429 *val = LSM6DSO_XL_BATCHED_AT_3333Hz;
6430 break;
6431
6432 case LSM6DSO_XL_BATCHED_AT_6667Hz:
6433 *val = LSM6DSO_XL_BATCHED_AT_6667Hz;
6434 break;
6435
6436 case LSM6DSO_XL_BATCHED_AT_6Hz5:
6437 *val = LSM6DSO_XL_BATCHED_AT_6Hz5;
6438 break;
6439
6440 default:
6441 *val = LSM6DSO_XL_NOT_BATCHED;
6442 break;
6443 }
6444
6445 return ret;
6446 }
6447
6448 /**
6449 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6450 * for gyroscope data.[set]
6451 *
6452 * @param ctx read / write interface definitions
6453 * @param val change the values of bdr_gy in reg FIFO_CTRL3
6454 * @retval interface status (MANDATORY: return 0 -> no Error)
6455 *
6456 */
lsm6dso_fifo_gy_batch_set(stmdev_ctx_t * ctx,lsm6dso_bdr_gy_t val)6457 int32_t lsm6dso_fifo_gy_batch_set(stmdev_ctx_t *ctx,
6458 lsm6dso_bdr_gy_t val)
6459 {
6460 lsm6dso_fifo_ctrl3_t reg;
6461 int32_t ret;
6462
6463 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1);
6464
6465 if (ret == 0)
6466 {
6467 reg.bdr_gy = (uint8_t)val;
6468 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1);
6469 }
6470
6471 return ret;
6472 }
6473
6474 /**
6475 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6476 * for gyroscope data.[get]
6477 *
6478 * @param ctx read / write interface definitions
6479 * @param val Get the values of bdr_gy in reg FIFO_CTRL3
6480 * @retval interface status (MANDATORY: return 0 -> no Error)
6481 *
6482 */
lsm6dso_fifo_gy_batch_get(stmdev_ctx_t * ctx,lsm6dso_bdr_gy_t * val)6483 int32_t lsm6dso_fifo_gy_batch_get(stmdev_ctx_t *ctx,
6484 lsm6dso_bdr_gy_t *val)
6485 {
6486 lsm6dso_fifo_ctrl3_t reg;
6487 int32_t ret;
6488
6489 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL3, (uint8_t *)®, 1);
6490
6491 switch (reg.bdr_gy)
6492 {
6493 case LSM6DSO_GY_NOT_BATCHED:
6494 *val = LSM6DSO_GY_NOT_BATCHED;
6495 break;
6496
6497 case LSM6DSO_GY_BATCHED_AT_12Hz5:
6498 *val = LSM6DSO_GY_BATCHED_AT_12Hz5;
6499 break;
6500
6501 case LSM6DSO_GY_BATCHED_AT_26Hz:
6502 *val = LSM6DSO_GY_BATCHED_AT_26Hz;
6503 break;
6504
6505 case LSM6DSO_GY_BATCHED_AT_52Hz:
6506 *val = LSM6DSO_GY_BATCHED_AT_52Hz;
6507 break;
6508
6509 case LSM6DSO_GY_BATCHED_AT_104Hz:
6510 *val = LSM6DSO_GY_BATCHED_AT_104Hz;
6511 break;
6512
6513 case LSM6DSO_GY_BATCHED_AT_208Hz:
6514 *val = LSM6DSO_GY_BATCHED_AT_208Hz;
6515 break;
6516
6517 case LSM6DSO_GY_BATCHED_AT_417Hz:
6518 *val = LSM6DSO_GY_BATCHED_AT_417Hz;
6519 break;
6520
6521 case LSM6DSO_GY_BATCHED_AT_833Hz:
6522 *val = LSM6DSO_GY_BATCHED_AT_833Hz;
6523 break;
6524
6525 case LSM6DSO_GY_BATCHED_AT_1667Hz:
6526 *val = LSM6DSO_GY_BATCHED_AT_1667Hz;
6527 break;
6528
6529 case LSM6DSO_GY_BATCHED_AT_3333Hz:
6530 *val = LSM6DSO_GY_BATCHED_AT_3333Hz;
6531 break;
6532
6533 case LSM6DSO_GY_BATCHED_AT_6667Hz:
6534 *val = LSM6DSO_GY_BATCHED_AT_6667Hz;
6535 break;
6536
6537 case LSM6DSO_GY_BATCHED_AT_6Hz5:
6538 *val = LSM6DSO_GY_BATCHED_AT_6Hz5;
6539 break;
6540
6541 default:
6542 *val = LSM6DSO_GY_NOT_BATCHED;
6543 break;
6544 }
6545
6546 return ret;
6547 }
6548
6549 /**
6550 * @brief FIFO mode selection.[set]
6551 *
6552 * @param ctx read / write interface definitions
6553 * @param val change the values of fifo_mode in reg FIFO_CTRL4
6554 * @retval interface status (MANDATORY: return 0 -> no Error)
6555 *
6556 */
lsm6dso_fifo_mode_set(stmdev_ctx_t * ctx,lsm6dso_fifo_mode_t val)6557 int32_t lsm6dso_fifo_mode_set(stmdev_ctx_t *ctx,
6558 lsm6dso_fifo_mode_t val)
6559 {
6560 lsm6dso_fifo_ctrl4_t reg;
6561 int32_t ret;
6562
6563 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
6564
6565 if (ret == 0)
6566 {
6567 reg.fifo_mode = (uint8_t)val;
6568 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
6569 }
6570
6571 return ret;
6572 }
6573
6574 /**
6575 * @brief FIFO mode selection.[get]
6576 *
6577 * @param ctx read / write interface definitions
6578 * @param val Get the values of fifo_mode in reg FIFO_CTRL4
6579 * @retval interface status (MANDATORY: return 0 -> no Error)
6580 *
6581 */
lsm6dso_fifo_mode_get(stmdev_ctx_t * ctx,lsm6dso_fifo_mode_t * val)6582 int32_t lsm6dso_fifo_mode_get(stmdev_ctx_t *ctx,
6583 lsm6dso_fifo_mode_t *val)
6584 {
6585 lsm6dso_fifo_ctrl4_t reg;
6586 int32_t ret;
6587
6588 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
6589
6590 switch (reg.fifo_mode)
6591 {
6592 case LSM6DSO_BYPASS_MODE:
6593 *val = LSM6DSO_BYPASS_MODE;
6594 break;
6595
6596 case LSM6DSO_FIFO_MODE:
6597 *val = LSM6DSO_FIFO_MODE;
6598 break;
6599
6600 case LSM6DSO_STREAM_TO_FIFO_MODE:
6601 *val = LSM6DSO_STREAM_TO_FIFO_MODE;
6602 break;
6603
6604 case LSM6DSO_BYPASS_TO_STREAM_MODE:
6605 *val = LSM6DSO_BYPASS_TO_STREAM_MODE;
6606 break;
6607
6608 case LSM6DSO_STREAM_MODE:
6609 *val = LSM6DSO_STREAM_MODE;
6610 break;
6611
6612 case LSM6DSO_BYPASS_TO_FIFO_MODE:
6613 *val = LSM6DSO_BYPASS_TO_FIFO_MODE;
6614 break;
6615
6616 default:
6617 *val = LSM6DSO_BYPASS_MODE;
6618 break;
6619 }
6620
6621 return ret;
6622 }
6623
6624 /**
6625 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6626 * for temperature data.[set]
6627 *
6628 * @param ctx read / write interface definitions
6629 * @param val change the values of odr_t_batch in reg FIFO_CTRL4
6630 * @retval interface status (MANDATORY: return 0 -> no Error)
6631 *
6632 */
lsm6dso_fifo_temp_batch_set(stmdev_ctx_t * ctx,lsm6dso_odr_t_batch_t val)6633 int32_t lsm6dso_fifo_temp_batch_set(stmdev_ctx_t *ctx,
6634 lsm6dso_odr_t_batch_t val)
6635 {
6636 lsm6dso_fifo_ctrl4_t reg;
6637 int32_t ret;
6638
6639 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
6640
6641 if (ret == 0)
6642 {
6643 reg.odr_t_batch = (uint8_t)val;
6644 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
6645 }
6646
6647 return ret;
6648 }
6649
6650 /**
6651 * @brief Selects Batching Data Rate (writing frequency in FIFO)
6652 * for temperature data.[get]
6653 *
6654 * @param ctx read / write interface definitions
6655 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4
6656 * @retval interface status (MANDATORY: return 0 -> no Error)
6657 *
6658 */
lsm6dso_fifo_temp_batch_get(stmdev_ctx_t * ctx,lsm6dso_odr_t_batch_t * val)6659 int32_t lsm6dso_fifo_temp_batch_get(stmdev_ctx_t *ctx,
6660 lsm6dso_odr_t_batch_t *val)
6661 {
6662 lsm6dso_fifo_ctrl4_t reg;
6663 int32_t ret;
6664
6665 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
6666
6667 switch (reg.odr_t_batch)
6668 {
6669 case LSM6DSO_TEMP_NOT_BATCHED:
6670 *val = LSM6DSO_TEMP_NOT_BATCHED;
6671 break;
6672
6673 case LSM6DSO_TEMP_BATCHED_AT_1Hz6:
6674 *val = LSM6DSO_TEMP_BATCHED_AT_1Hz6;
6675 break;
6676
6677 case LSM6DSO_TEMP_BATCHED_AT_12Hz5:
6678 *val = LSM6DSO_TEMP_BATCHED_AT_12Hz5;
6679 break;
6680
6681 case LSM6DSO_TEMP_BATCHED_AT_52Hz:
6682 *val = LSM6DSO_TEMP_BATCHED_AT_52Hz;
6683 break;
6684
6685 default:
6686 *val = LSM6DSO_TEMP_NOT_BATCHED;
6687 break;
6688 }
6689
6690 return ret;
6691 }
6692
6693 /**
6694 * @brief Selects decimation for timestamp batching in FIFO.
6695 * Writing rate will be the maximum rate between XL and
6696 * GYRO BDR divided by decimation decoder.[set]
6697 *
6698 * @param ctx read / write interface definitions
6699 * @param val change the values of odr_ts_batch in reg FIFO_CTRL4
6700 * @retval interface status (MANDATORY: return 0 -> no Error)
6701 *
6702 */
lsm6dso_fifo_timestamp_decimation_set(stmdev_ctx_t * ctx,lsm6dso_odr_ts_batch_t val)6703 int32_t lsm6dso_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
6704 lsm6dso_odr_ts_batch_t val)
6705 {
6706 lsm6dso_fifo_ctrl4_t reg;
6707 int32_t ret;
6708
6709 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
6710
6711 if (ret == 0)
6712 {
6713 reg.odr_ts_batch = (uint8_t)val;
6714 ret = lsm6dso_write_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
6715 }
6716
6717 return ret;
6718 }
6719
6720 /**
6721 * @brief Selects decimation for timestamp batching in FIFO.
6722 * Writing rate will be the maximum rate between XL and
6723 * GYRO BDR divided by decimation decoder.[get]
6724 *
6725 * @param ctx read / write interface definitions
6726 * @param val Get the values of odr_ts_batch in reg FIFO_CTRL4
6727 * @retval interface status (MANDATORY: return 0 -> no Error)
6728 *
6729 */
lsm6dso_fifo_timestamp_decimation_get(stmdev_ctx_t * ctx,lsm6dso_odr_ts_batch_t * val)6730 int32_t lsm6dso_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
6731 lsm6dso_odr_ts_batch_t *val)
6732 {
6733 lsm6dso_fifo_ctrl4_t reg;
6734 int32_t ret;
6735
6736 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_CTRL4, (uint8_t *)®, 1);
6737
6738 switch (reg.odr_ts_batch)
6739 {
6740 case LSM6DSO_NO_DECIMATION:
6741 *val = LSM6DSO_NO_DECIMATION;
6742 break;
6743
6744 case LSM6DSO_DEC_1:
6745 *val = LSM6DSO_DEC_1;
6746 break;
6747
6748 case LSM6DSO_DEC_8:
6749 *val = LSM6DSO_DEC_8;
6750 break;
6751
6752 case LSM6DSO_DEC_32:
6753 *val = LSM6DSO_DEC_32;
6754 break;
6755
6756 default:
6757 *val = LSM6DSO_NO_DECIMATION;
6758 break;
6759 }
6760
6761 return ret;
6762 }
6763
6764 /**
6765 * @brief Selects the trigger for the internal counter of batching events
6766 * between XL and gyro.[set]
6767 *
6768 * @param ctx read / write interface definitions
6769 * @param val change the values of trig_counter_bdr
6770 * in reg COUNTER_BDR_REG1
6771 * @retval interface status (MANDATORY: return 0 -> no Error)
6772 *
6773 */
lsm6dso_fifo_cnt_event_batch_set(stmdev_ctx_t * ctx,lsm6dso_trig_counter_bdr_t val)6774 int32_t lsm6dso_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
6775 lsm6dso_trig_counter_bdr_t val)
6776 {
6777 lsm6dso_counter_bdr_reg1_t reg;
6778 int32_t ret;
6779
6780 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1);
6781
6782 if (ret == 0)
6783 {
6784 reg.trig_counter_bdr = (uint8_t)val;
6785 ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
6786 (uint8_t *)®, 1);
6787 }
6788
6789 return ret;
6790 }
6791
6792 /**
6793 * @brief Selects the trigger for the internal counter of batching events
6794 * between XL and gyro.[get]
6795 *
6796 * @param ctx read / write interface definitions
6797 * @param val Get the values of trig_counter_bdr
6798 * in reg COUNTER_BDR_REG1
6799 * @retval interface status (MANDATORY: return 0 -> no Error)
6800 *
6801 */
lsm6dso_fifo_cnt_event_batch_get(stmdev_ctx_t * ctx,lsm6dso_trig_counter_bdr_t * val)6802 int32_t lsm6dso_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
6803 lsm6dso_trig_counter_bdr_t *val)
6804 {
6805 lsm6dso_counter_bdr_reg1_t reg;
6806 int32_t ret;
6807
6808 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1);
6809
6810 switch (reg.trig_counter_bdr)
6811 {
6812 case LSM6DSO_XL_BATCH_EVENT:
6813 *val = LSM6DSO_XL_BATCH_EVENT;
6814 break;
6815
6816 case LSM6DSO_GYRO_BATCH_EVENT:
6817 *val = LSM6DSO_GYRO_BATCH_EVENT;
6818 break;
6819
6820 default:
6821 *val = LSM6DSO_XL_BATCH_EVENT;
6822 break;
6823 }
6824
6825 return ret;
6826 }
6827
6828 /**
6829 * @brief Resets the internal counter of batching vents for a single sensor.
6830 * This bit is automatically reset to zero if it was set to ‘1’.[set]
6831 *
6832 * @param ctx read / write interface definitions
6833 * @param val change the values of rst_counter_bdr in
6834 * reg COUNTER_BDR_REG1
6835 * @retval interface status (MANDATORY: return 0 -> no Error)
6836 *
6837 */
lsm6dso_rst_batch_counter_set(stmdev_ctx_t * ctx,uint8_t val)6838 int32_t lsm6dso_rst_batch_counter_set(stmdev_ctx_t *ctx, uint8_t val)
6839 {
6840 lsm6dso_counter_bdr_reg1_t reg;
6841 int32_t ret;
6842
6843 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1);
6844
6845 if (ret == 0)
6846 {
6847 reg.rst_counter_bdr = val;
6848 ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
6849 (uint8_t *)®, 1);
6850 }
6851
6852 return ret;
6853 }
6854
6855 /**
6856 * @brief Resets the internal counter of batching events for a single sensor.
6857 * This bit is automatically reset to zero if it was set to ‘1’.[get]
6858 *
6859 * @param ctx read / write interface definitions
6860 * @param val change the values of rst_counter_bdr in
6861 * reg COUNTER_BDR_REG1
6862 * @retval interface status (MANDATORY: return 0 -> no Error)
6863 *
6864 */
lsm6dso_rst_batch_counter_get(stmdev_ctx_t * ctx,uint8_t * val)6865 int32_t lsm6dso_rst_batch_counter_get(stmdev_ctx_t *ctx, uint8_t *val)
6866 {
6867 lsm6dso_counter_bdr_reg1_t reg;
6868 int32_t ret;
6869
6870 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1, (uint8_t *)®, 1);
6871 *val = reg.rst_counter_bdr;
6872
6873 return ret;
6874 }
6875
6876 /**
6877 * @brief Batch data rate counter.[set]
6878 *
6879 * @param ctx read / write interface definitions
6880 * @param val change the values of cnt_bdr_th in
6881 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
6882 * @retval interface status (MANDATORY: return 0 -> no Error)
6883 *
6884 */
lsm6dso_batch_counter_threshold_set(stmdev_ctx_t * ctx,uint16_t val)6885 int32_t lsm6dso_batch_counter_threshold_set(stmdev_ctx_t *ctx,
6886 uint16_t val)
6887 {
6888 lsm6dso_counter_bdr_reg1_t counter_bdr_reg1;
6889 lsm6dso_counter_bdr_reg2_t counter_bdr_reg2;
6890 int32_t ret;
6891
6892 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
6893 (uint8_t *)&counter_bdr_reg1, 1);
6894
6895 if (ret == 0)
6896 {
6897 counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val;
6898 counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8;
6899 ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
6900 (uint8_t *)&counter_bdr_reg1, 1);
6901 }
6902
6903 if (ret == 0)
6904 {
6905 ret = lsm6dso_write_reg(ctx, LSM6DSO_COUNTER_BDR_REG2,
6906 (uint8_t *)&counter_bdr_reg2, 1);
6907 }
6908
6909 return ret;
6910 }
6911
6912 /**
6913 * @brief Batch data rate counter.[get]
6914 *
6915 * @param ctx read / write interface definitions
6916 * @param val change the values of cnt_bdr_th in
6917 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
6918 * @retval interface status (MANDATORY: return 0 -> no Error)
6919 *
6920 */
lsm6dso_batch_counter_threshold_get(stmdev_ctx_t * ctx,uint16_t * val)6921 int32_t lsm6dso_batch_counter_threshold_get(stmdev_ctx_t *ctx,
6922 uint16_t *val)
6923 {
6924 lsm6dso_counter_bdr_reg1_t counter_bdr_reg1;
6925 lsm6dso_counter_bdr_reg2_t counter_bdr_reg2;
6926 int32_t ret;
6927
6928 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG1,
6929 (uint8_t *)&counter_bdr_reg1, 1);
6930
6931 if (ret == 0)
6932 {
6933 ret = lsm6dso_read_reg(ctx, LSM6DSO_COUNTER_BDR_REG2,
6934 (uint8_t *)&counter_bdr_reg2, 1);
6935 *val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8)
6936 + (uint16_t)counter_bdr_reg2.cnt_bdr_th;
6937 }
6938
6939 return ret;
6940 }
6941
6942 /**
6943 * @brief Number of unread sensor data(TAG + 6 bytes) stored in FIFO.[get]
6944 *
6945 * @param ctx read / write interface definitions
6946 * @param val change the values of diff_fifo in reg FIFO_STATUS1
6947 * @retval interface status (MANDATORY: return 0 -> no Error)
6948 *
6949 */
lsm6dso_fifo_data_level_get(stmdev_ctx_t * ctx,uint16_t * val)6950 int32_t lsm6dso_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
6951 {
6952 lsm6dso_fifo_status1_t fifo_status1;
6953 lsm6dso_fifo_status2_t fifo_status2;
6954 int32_t ret;
6955
6956 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS1,
6957 (uint8_t *)&fifo_status1, 1);
6958
6959 if (ret == 0)
6960 {
6961 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2,
6962 (uint8_t *)&fifo_status2, 1);
6963 *val = ((uint16_t)fifo_status2.diff_fifo << 8) +
6964 (uint16_t)fifo_status1.diff_fifo;
6965 }
6966
6967 return ret;
6968 }
6969
6970 /**
6971 * @brief FIFO status.[get]
6972 *
6973 * @param ctx read / write interface definitions
6974 * @param val registers FIFO_STATUS2
6975 * @retval interface status (MANDATORY: return 0 -> no Error)
6976 *
6977 */
lsm6dso_fifo_status_get(stmdev_ctx_t * ctx,lsm6dso_fifo_status2_t * val)6978 int32_t lsm6dso_fifo_status_get(stmdev_ctx_t *ctx,
6979 lsm6dso_fifo_status2_t *val)
6980 {
6981 int32_t ret;
6982
6983 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *) val, 1);
6984
6985 return ret;
6986 }
6987
6988 /**
6989 * @brief Smart FIFO full status.[get]
6990 *
6991 * @param ctx read / write interface definitions
6992 * @param val change the values of fifo_full_ia in reg FIFO_STATUS2
6993 * @retval interface status (MANDATORY: return 0 -> no Error)
6994 *
6995 */
lsm6dso_fifo_full_flag_get(stmdev_ctx_t * ctx,uint8_t * val)6996 int32_t lsm6dso_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
6997 {
6998 lsm6dso_fifo_status2_t reg;
6999 int32_t ret;
7000
7001 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *)®, 1);
7002 *val = reg.fifo_full_ia;
7003
7004 return ret;
7005 }
7006
7007 /**
7008 * @brief FIFO overrun status.[get]
7009 *
7010 * @param ctx read / write interface definitions
7011 * @param val change the values of fifo_over_run_latched in
7012 * reg FIFO_STATUS2
7013 * @retval interface status (MANDATORY: return 0 -> no Error)
7014 *
7015 */
lsm6dso_fifo_ovr_flag_get(stmdev_ctx_t * ctx,uint8_t * val)7016 int32_t lsm6dso_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
7017 {
7018 lsm6dso_fifo_status2_t reg;
7019 int32_t ret;
7020
7021 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *)®, 1);
7022 *val = reg.fifo_ovr_ia;
7023
7024 return ret;
7025 }
7026
7027 /**
7028 * @brief FIFO watermark status.[get]
7029 *
7030 * @param ctx read / write interface definitions
7031 * @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2
7032 * @retval interface status (MANDATORY: return 0 -> no Error)
7033 *
7034 */
lsm6dso_fifo_wtm_flag_get(stmdev_ctx_t * ctx,uint8_t * val)7035 int32_t lsm6dso_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
7036 {
7037 lsm6dso_fifo_status2_t reg;
7038 int32_t ret;
7039
7040 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_STATUS2, (uint8_t *)®, 1);
7041 *val = reg.fifo_wtm_ia;
7042
7043 return ret;
7044 }
7045
7046 /**
7047 * @brief Identifies the sensor in FIFO_DATA_OUT.[get]
7048 *
7049 * @param ctx read / write interface definitions
7050 * @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
7051 * @retval interface status (MANDATORY: return 0 -> no Error)
7052 *
7053 */
lsm6dso_fifo_sensor_tag_get(stmdev_ctx_t * ctx,lsm6dso_fifo_tag_t * val)7054 int32_t lsm6dso_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
7055 lsm6dso_fifo_tag_t *val)
7056 {
7057 lsm6dso_fifo_data_out_tag_t reg;
7058 int32_t ret;
7059
7060 ret = lsm6dso_read_reg(ctx, LSM6DSO_FIFO_DATA_OUT_TAG,
7061 (uint8_t *)®, 1);
7062
7063 switch (reg.tag_sensor)
7064 {
7065 case LSM6DSO_GYRO_NC_TAG:
7066 *val = LSM6DSO_GYRO_NC_TAG;
7067 break;
7068
7069 case LSM6DSO_XL_NC_TAG:
7070 *val = LSM6DSO_XL_NC_TAG;
7071 break;
7072
7073 case LSM6DSO_TEMPERATURE_TAG:
7074 *val = LSM6DSO_TEMPERATURE_TAG;
7075 break;
7076
7077 case LSM6DSO_CFG_CHANGE_TAG:
7078 *val = LSM6DSO_CFG_CHANGE_TAG;
7079 break;
7080
7081 case LSM6DSO_XL_NC_T_2_TAG:
7082 *val = LSM6DSO_XL_NC_T_2_TAG;
7083 break;
7084
7085 case LSM6DSO_XL_NC_T_1_TAG:
7086 *val = LSM6DSO_XL_NC_T_1_TAG;
7087 break;
7088
7089 case LSM6DSO_XL_2XC_TAG:
7090 *val = LSM6DSO_XL_2XC_TAG;
7091 break;
7092
7093 case LSM6DSO_XL_3XC_TAG:
7094 *val = LSM6DSO_XL_3XC_TAG;
7095 break;
7096
7097 case LSM6DSO_GYRO_NC_T_2_TAG:
7098 *val = LSM6DSO_GYRO_NC_T_2_TAG;
7099 break;
7100
7101 case LSM6DSO_GYRO_NC_T_1_TAG:
7102 *val = LSM6DSO_GYRO_NC_T_1_TAG;
7103 break;
7104
7105 case LSM6DSO_GYRO_2XC_TAG:
7106 *val = LSM6DSO_GYRO_2XC_TAG;
7107 break;
7108
7109 case LSM6DSO_GYRO_3XC_TAG:
7110 *val = LSM6DSO_GYRO_3XC_TAG;
7111 break;
7112
7113 case LSM6DSO_SENSORHUB_SLAVE0_TAG:
7114 *val = LSM6DSO_SENSORHUB_SLAVE0_TAG;
7115 break;
7116
7117 case LSM6DSO_SENSORHUB_SLAVE1_TAG:
7118 *val = LSM6DSO_SENSORHUB_SLAVE1_TAG;
7119 break;
7120
7121 case LSM6DSO_SENSORHUB_SLAVE2_TAG:
7122 *val = LSM6DSO_SENSORHUB_SLAVE2_TAG;
7123 break;
7124
7125 case LSM6DSO_SENSORHUB_SLAVE3_TAG:
7126 *val = LSM6DSO_SENSORHUB_SLAVE3_TAG;
7127 break;
7128
7129 case LSM6DSO_STEP_CPUNTER_TAG:
7130 *val = LSM6DSO_STEP_CPUNTER_TAG;
7131 break;
7132
7133 case LSM6DSO_GAME_ROTATION_TAG:
7134 *val = LSM6DSO_GAME_ROTATION_TAG;
7135 break;
7136
7137 case LSM6DSO_GEOMAG_ROTATION_TAG:
7138 *val = LSM6DSO_GEOMAG_ROTATION_TAG;
7139 break;
7140
7141 case LSM6DSO_ROTATION_TAG:
7142 *val = LSM6DSO_ROTATION_TAG;
7143 break;
7144
7145 case LSM6DSO_SENSORHUB_NACK_TAG:
7146 *val = LSM6DSO_SENSORHUB_NACK_TAG;
7147 break;
7148
7149 default:
7150 *val = LSM6DSO_GYRO_NC_TAG;
7151 break;
7152 }
7153
7154 return ret;
7155 }
7156
7157 /**
7158 * @brief : Enable FIFO batching of pedometer embedded
7159 * function values.[set]
7160 *
7161 * @param ctx read / write interface definitions
7162 * @param val change the values of gbias_fifo_en in
7163 * reg LSM6DSO_EMB_FUNC_FIFO_CFG
7164 * @retval interface status (MANDATORY: return 0 -> no Error)
7165 *
7166 */
lsm6dso_fifo_pedo_batch_set(stmdev_ctx_t * ctx,uint8_t val)7167 int32_t lsm6dso_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
7168 {
7169 lsm6dso_emb_func_fifo_cfg_t reg;
7170 int32_t ret;
7171
7172 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
7173
7174 if (ret == 0)
7175 {
7176 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG,
7177 (uint8_t *)®, 1);
7178 }
7179
7180 if (ret == 0)
7181 {
7182 reg.pedo_fifo_en = val;
7183 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG,
7184 (uint8_t *)®, 1);
7185 }
7186
7187 if (ret == 0)
7188 {
7189 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
7190 }
7191
7192 return ret;
7193 }
7194
7195 /**
7196 * @brief Enable FIFO batching of pedometer embedded function values.[get]
7197 *
7198 * @param ctx read / write interface definitions
7199 * @param val change the values of pedo_fifo_en in
7200 * reg LSM6DSO_EMB_FUNC_FIFO_CFG
7201 * @retval interface status (MANDATORY: return 0 -> no Error)
7202 *
7203 */
lsm6dso_fifo_pedo_batch_get(stmdev_ctx_t * ctx,uint8_t * val)7204 int32_t lsm6dso_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
7205 {
7206 lsm6dso_emb_func_fifo_cfg_t reg;
7207 int32_t ret;
7208
7209 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
7210
7211 if (ret == 0)
7212 {
7213 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_FIFO_CFG,
7214 (uint8_t *)®, 1);
7215 }
7216
7217 if (ret == 0)
7218 {
7219 *val = reg.pedo_fifo_en;
7220 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
7221 }
7222
7223 return ret;
7224 }
7225
7226 /**
7227 * @brief Enable FIFO batching data of first slave.[set]
7228 *
7229 * @param ctx read / write interface definitions
7230 * @param val change the values of batch_ext_sens_0_en in
7231 * reg SLV0_CONFIG
7232 * @retval interface status (MANDATORY: return 0 -> no Error)
7233 *
7234 */
lsm6dso_sh_batch_slave_0_set(stmdev_ctx_t * ctx,uint8_t val)7235 int32_t lsm6dso_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
7236 {
7237 lsm6dso_slv0_config_t reg;
7238 int32_t ret;
7239
7240 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
7241
7242 if (ret == 0)
7243 {
7244 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)®, 1);
7245 }
7246
7247 if (ret == 0)
7248 {
7249 reg.batch_ext_sens_0_en = val;
7250 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)®, 1);
7251 }
7252
7253 if (ret == 0)
7254 {
7255 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
7256 }
7257
7258 return ret;
7259 }
7260
7261 /**
7262 * @brief Enable FIFO batching data of first slave.[get]
7263 *
7264 * @param ctx read / write interface definitions
7265 * @param val change the values of batch_ext_sens_0_en in
7266 * reg SLV0_CONFIG
7267 * @retval interface status (MANDATORY: return 0 -> no Error)
7268 *
7269 */
lsm6dso_sh_batch_slave_0_get(stmdev_ctx_t * ctx,uint8_t * val)7270 int32_t lsm6dso_sh_batch_slave_0_get(stmdev_ctx_t *ctx, uint8_t *val)
7271 {
7272 lsm6dso_slv0_config_t reg;
7273 int32_t ret;
7274
7275 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
7276
7277 if (ret == 0)
7278 {
7279 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)®, 1);
7280 }
7281
7282 if (ret == 0)
7283 {
7284 *val = reg.batch_ext_sens_0_en;
7285 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
7286 }
7287
7288 return ret;
7289 }
7290
7291 /**
7292 * @brief Enable FIFO batching data of second slave.[set]
7293 *
7294 * @param ctx read / write interface definitions
7295 * @param val change the values of batch_ext_sens_1_en in
7296 * reg SLV1_CONFIG
7297 * @retval interface status (MANDATORY: return 0 -> no Error)
7298 *
7299 */
lsm6dso_sh_batch_slave_1_set(stmdev_ctx_t * ctx,uint8_t val)7300 int32_t lsm6dso_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
7301 {
7302 lsm6dso_slv1_config_t reg;
7303 int32_t ret;
7304
7305 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
7306
7307 if (ret == 0)
7308 {
7309 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)®, 1);
7310 }
7311
7312 if (ret == 0)
7313 {
7314 reg.batch_ext_sens_1_en = val;
7315 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)®, 1);
7316 }
7317
7318 if (ret == 0)
7319 {
7320 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
7321 }
7322
7323 return ret;
7324 }
7325
7326 /**
7327 * @brief Enable FIFO batching data of second slave.[get]
7328 *
7329 * @param ctx read / write interface definitions
7330 * @param val change the values of batch_ext_sens_1_en in
7331 * reg SLV1_CONFIG
7332 * @retval interface status (MANDATORY: return 0 -> no Error)
7333 *
7334 */
lsm6dso_sh_batch_slave_1_get(stmdev_ctx_t * ctx,uint8_t * val)7335 int32_t lsm6dso_sh_batch_slave_1_get(stmdev_ctx_t *ctx, uint8_t *val)
7336 {
7337 lsm6dso_slv1_config_t reg;
7338 int32_t ret;
7339
7340 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
7341
7342 if (ret == 0)
7343 {
7344 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG, (uint8_t *)®, 1);
7345 *val = reg.batch_ext_sens_1_en;
7346 }
7347
7348 if (ret == 0)
7349 {
7350 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
7351 }
7352
7353 return ret;
7354 }
7355
7356 /**
7357 * @brief Enable FIFO batching data of third slave.[set]
7358 *
7359 * @param ctx read / write interface definitions
7360 * @param val change the values of batch_ext_sens_2_en in
7361 * reg SLV2_CONFIG
7362 * @retval interface status (MANDATORY: return 0 -> no Error)
7363 *
7364 */
lsm6dso_sh_batch_slave_2_set(stmdev_ctx_t * ctx,uint8_t val)7365 int32_t lsm6dso_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
7366 {
7367 lsm6dso_slv2_config_t reg;
7368 int32_t ret;
7369
7370 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
7371
7372 if (ret == 0)
7373 {
7374 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t *)®, 1);
7375 }
7376
7377 if (ret == 0)
7378 {
7379 reg.batch_ext_sens_2_en = val;
7380 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t *)®, 1);
7381 }
7382
7383 if (ret == 0)
7384 {
7385 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
7386 }
7387
7388 return ret;
7389 }
7390
7391 /**
7392 * @brief Enable FIFO batching data of third slave.[get]
7393 *
7394 * @param ctx read / write interface definitions
7395 * @param val change the values of batch_ext_sens_2_en in
7396 * reg SLV2_CONFIG
7397 * @retval interface status (MANDATORY: return 0 -> no Error)
7398 *
7399 */
lsm6dso_sh_batch_slave_2_get(stmdev_ctx_t * ctx,uint8_t * val)7400 int32_t lsm6dso_sh_batch_slave_2_get(stmdev_ctx_t *ctx, uint8_t *val)
7401 {
7402 lsm6dso_slv2_config_t reg;
7403 int32_t ret;
7404
7405 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
7406
7407 if (ret == 0)
7408 {
7409 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG, (uint8_t *)®, 1);
7410 }
7411
7412 if (ret == 0)
7413 {
7414 *val = reg.batch_ext_sens_2_en;
7415 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
7416 }
7417
7418 return ret;
7419 }
7420
7421 /**
7422 * @brief Enable FIFO batching data of fourth slave.[set]
7423 *
7424 * @param ctx read / write interface definitions
7425 * @param val change the values of batch_ext_sens_3_en
7426 * in reg SLV3_CONFIG
7427 * @retval interface status (MANDATORY: return 0 -> no Error)
7428 *
7429 */
lsm6dso_sh_batch_slave_3_set(stmdev_ctx_t * ctx,uint8_t val)7430 int32_t lsm6dso_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
7431 {
7432 lsm6dso_slv3_config_t reg;
7433 int32_t ret;
7434
7435 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
7436
7437 if (ret == 0)
7438 {
7439 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t *)®, 1);
7440 }
7441
7442 if (ret == 0)
7443 {
7444 reg.batch_ext_sens_3_en = val;
7445 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t *)®, 1);
7446 }
7447
7448 if (ret == 0)
7449 {
7450 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
7451 }
7452
7453 return ret;
7454 }
7455
7456 /**
7457 * @brief Enable FIFO batching data of fourth slave.[get]
7458 *
7459 * @param ctx read / write interface definitions
7460 * @param val change the values of batch_ext_sens_3_en in
7461 * reg SLV3_CONFIG
7462 * @retval interface status (MANDATORY: return 0 -> no Error)
7463 *
7464 */
lsm6dso_sh_batch_slave_3_get(stmdev_ctx_t * ctx,uint8_t * val)7465 int32_t lsm6dso_sh_batch_slave_3_get(stmdev_ctx_t *ctx, uint8_t *val)
7466 {
7467 lsm6dso_slv3_config_t reg;
7468 int32_t ret;
7469
7470 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
7471
7472 if (ret == 0)
7473 {
7474 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG, (uint8_t *)®, 1);
7475 }
7476
7477 if (ret == 0)
7478 {
7479 *val = reg.batch_ext_sens_3_en;
7480 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
7481 }
7482
7483 return ret;
7484 }
7485
7486 /**
7487 * @}
7488 *
7489 */
7490
7491 /**
7492 * @defgroup LSM6DSO_DEN_functionality
7493 * @brief This section groups all the functions concerning
7494 * DEN functionality.
7495 * @{
7496 *
7497 */
7498
7499 /**
7500 * @brief DEN functionality marking mode.[set]
7501 *
7502 * @param ctx read / write interface definitions
7503 * @param val change the values of den_mode in reg CTRL6_C
7504 * @retval interface status (MANDATORY: return 0 -> no Error)
7505 *
7506 */
lsm6dso_den_mode_set(stmdev_ctx_t * ctx,lsm6dso_den_mode_t val)7507 int32_t lsm6dso_den_mode_set(stmdev_ctx_t *ctx,
7508 lsm6dso_den_mode_t val)
7509 {
7510 lsm6dso_ctrl6_c_t reg;
7511 int32_t ret;
7512
7513 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
7514
7515 if (ret == 0)
7516 {
7517 reg.den_mode = (uint8_t)val;
7518 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
7519 }
7520
7521 return ret;
7522 }
7523
7524 /**
7525 * @brief DEN functionality marking mode.[get]
7526 *
7527 * @param ctx read / write interface definitions
7528 * @param val Get the values of den_mode in reg CTRL6_C
7529 * @retval interface status (MANDATORY: return 0 -> no Error)
7530 *
7531 */
lsm6dso_den_mode_get(stmdev_ctx_t * ctx,lsm6dso_den_mode_t * val)7532 int32_t lsm6dso_den_mode_get(stmdev_ctx_t *ctx,
7533 lsm6dso_den_mode_t *val)
7534 {
7535 lsm6dso_ctrl6_c_t reg;
7536 int32_t ret;
7537
7538 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL6_C, (uint8_t *)®, 1);
7539
7540 switch (reg.den_mode)
7541 {
7542 case LSM6DSO_DEN_DISABLE:
7543 *val = LSM6DSO_DEN_DISABLE;
7544 break;
7545
7546 case LSM6DSO_LEVEL_FIFO:
7547 *val = LSM6DSO_LEVEL_FIFO;
7548 break;
7549
7550 case LSM6DSO_LEVEL_LETCHED:
7551 *val = LSM6DSO_LEVEL_LETCHED;
7552 break;
7553
7554 case LSM6DSO_LEVEL_TRIGGER:
7555 *val = LSM6DSO_LEVEL_TRIGGER;
7556 break;
7557
7558 case LSM6DSO_EDGE_TRIGGER:
7559 *val = LSM6DSO_EDGE_TRIGGER;
7560 break;
7561
7562 default:
7563 *val = LSM6DSO_DEN_DISABLE;
7564 break;
7565 }
7566
7567 return ret;
7568 }
7569
7570 /**
7571 * @brief DEN active level configuration.[set]
7572 *
7573 * @param ctx read / write interface definitions
7574 * @param val change the values of den_lh in reg CTRL9_XL
7575 * @retval interface status (MANDATORY: return 0 -> no Error)
7576 *
7577 */
lsm6dso_den_polarity_set(stmdev_ctx_t * ctx,lsm6dso_den_lh_t val)7578 int32_t lsm6dso_den_polarity_set(stmdev_ctx_t *ctx,
7579 lsm6dso_den_lh_t val)
7580 {
7581 lsm6dso_ctrl9_xl_t reg;
7582 int32_t ret;
7583
7584 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7585
7586 if (ret == 0)
7587 {
7588 reg.den_lh = (uint8_t)val;
7589 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7590 }
7591
7592 return ret;
7593 }
7594
7595 /**
7596 * @brief DEN active level configuration.[get]
7597 *
7598 * @param ctx read / write interface definitions
7599 * @param val Get the values of den_lh in reg CTRL9_XL
7600 * @retval interface status (MANDATORY: return 0 -> no Error)
7601 *
7602 */
lsm6dso_den_polarity_get(stmdev_ctx_t * ctx,lsm6dso_den_lh_t * val)7603 int32_t lsm6dso_den_polarity_get(stmdev_ctx_t *ctx,
7604 lsm6dso_den_lh_t *val)
7605 {
7606 lsm6dso_ctrl9_xl_t reg;
7607 int32_t ret;
7608
7609 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7610
7611 switch (reg.den_lh)
7612 {
7613 case LSM6DSO_DEN_ACT_LOW:
7614 *val = LSM6DSO_DEN_ACT_LOW;
7615 break;
7616
7617 case LSM6DSO_DEN_ACT_HIGH:
7618 *val = LSM6DSO_DEN_ACT_HIGH;
7619 break;
7620
7621 default:
7622 *val = LSM6DSO_DEN_ACT_LOW;
7623 break;
7624 }
7625
7626 return ret;
7627 }
7628
7629 /**
7630 * @brief DEN enable.[set]
7631 *
7632 * @param ctx read / write interface definitions
7633 * @param val change the values of den_xl_g in reg CTRL9_XL
7634 * @retval interface status (MANDATORY: return 0 -> no Error)
7635 *
7636 */
lsm6dso_den_enable_set(stmdev_ctx_t * ctx,lsm6dso_den_xl_g_t val)7637 int32_t lsm6dso_den_enable_set(stmdev_ctx_t *ctx,
7638 lsm6dso_den_xl_g_t val)
7639 {
7640 lsm6dso_ctrl9_xl_t reg;
7641 int32_t ret;
7642
7643 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7644
7645 if (ret == 0)
7646 {
7647 reg.den_xl_g = (uint8_t)val;
7648 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7649 }
7650
7651 return ret;
7652 }
7653
7654 /**
7655 * @brief DEN enable.[get]
7656 *
7657 * @param ctx read / write interface definitions
7658 * @param val Get the values of den_xl_g in reg CTRL9_XL
7659 * @retval interface status (MANDATORY: return 0 -> no Error)
7660 *
7661 */
lsm6dso_den_enable_get(stmdev_ctx_t * ctx,lsm6dso_den_xl_g_t * val)7662 int32_t lsm6dso_den_enable_get(stmdev_ctx_t *ctx,
7663 lsm6dso_den_xl_g_t *val)
7664 {
7665 lsm6dso_ctrl9_xl_t reg;
7666 int32_t ret;
7667
7668 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7669
7670 switch (reg.den_xl_g)
7671 {
7672 case LSM6DSO_STAMP_IN_GY_DATA:
7673 *val = LSM6DSO_STAMP_IN_GY_DATA;
7674 break;
7675
7676 case LSM6DSO_STAMP_IN_XL_DATA:
7677 *val = LSM6DSO_STAMP_IN_XL_DATA;
7678 break;
7679
7680 case LSM6DSO_STAMP_IN_GY_XL_DATA:
7681 *val = LSM6DSO_STAMP_IN_GY_XL_DATA;
7682 break;
7683
7684 default:
7685 *val = LSM6DSO_STAMP_IN_GY_DATA;
7686 break;
7687 }
7688
7689 return ret;
7690 }
7691
7692 /**
7693 * @brief DEN value stored in LSB of X-axis.[set]
7694 *
7695 * @param ctx read / write interface definitions
7696 * @param val change the values of den_z in reg CTRL9_XL
7697 * @retval interface status (MANDATORY: return 0 -> no Error)
7698 *
7699 */
lsm6dso_den_mark_axis_x_set(stmdev_ctx_t * ctx,uint8_t val)7700 int32_t lsm6dso_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
7701 {
7702 lsm6dso_ctrl9_xl_t reg;
7703 int32_t ret;
7704
7705 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7706
7707 if (ret == 0)
7708 {
7709 reg.den_z = val;
7710 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7711 }
7712
7713 return ret;
7714 }
7715
7716 /**
7717 * @brief DEN value stored in LSB of X-axis.[get]
7718 *
7719 * @param ctx read / write interface definitions
7720 * @param val change the values of den_z in reg CTRL9_XL
7721 * @retval interface status (MANDATORY: return 0 -> no Error)
7722 *
7723 */
lsm6dso_den_mark_axis_x_get(stmdev_ctx_t * ctx,uint8_t * val)7724 int32_t lsm6dso_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
7725 {
7726 lsm6dso_ctrl9_xl_t reg;
7727 int32_t ret;
7728
7729 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7730 *val = reg.den_z;
7731
7732 return ret;
7733 }
7734
7735 /**
7736 * @brief DEN value stored in LSB of Y-axis.[set]
7737 *
7738 * @param ctx read / write interface definitions
7739 * @param val change the values of den_y in reg CTRL9_XL
7740 * @retval interface status (MANDATORY: return 0 -> no Error)
7741 *
7742 */
lsm6dso_den_mark_axis_y_set(stmdev_ctx_t * ctx,uint8_t val)7743 int32_t lsm6dso_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
7744 {
7745 lsm6dso_ctrl9_xl_t reg;
7746 int32_t ret;
7747
7748 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7749
7750 if (ret == 0)
7751 {
7752 reg.den_y = val;
7753 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7754 }
7755
7756 return ret;
7757 }
7758
7759 /**
7760 * @brief DEN value stored in LSB of Y-axis.[get]
7761 *
7762 * @param ctx read / write interface definitions
7763 * @param val change the values of den_y in reg CTRL9_XL
7764 * @retval interface status (MANDATORY: return 0 -> no Error)
7765 *
7766 */
lsm6dso_den_mark_axis_y_get(stmdev_ctx_t * ctx,uint8_t * val)7767 int32_t lsm6dso_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
7768 {
7769 lsm6dso_ctrl9_xl_t reg;
7770 int32_t ret;
7771
7772 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7773 *val = reg.den_y;
7774
7775 return ret;
7776 }
7777
7778 /**
7779 * @brief DEN value stored in LSB of Z-axis.[set]
7780 *
7781 * @param ctx read / write interface definitions
7782 * @param val change the values of den_x in reg CTRL9_XL
7783 * @retval interface status (MANDATORY: return 0 -> no Error)
7784 *
7785 */
lsm6dso_den_mark_axis_z_set(stmdev_ctx_t * ctx,uint8_t val)7786 int32_t lsm6dso_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
7787 {
7788 lsm6dso_ctrl9_xl_t reg;
7789 int32_t ret;
7790
7791 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7792
7793 if (ret == 0)
7794 {
7795 reg.den_x = val;
7796 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7797 }
7798
7799 return ret;
7800 }
7801
7802 /**
7803 * @brief DEN value stored in LSB of Z-axis.[get]
7804 *
7805 * @param ctx read / write interface definitions
7806 * @param val change the values of den_x in reg CTRL9_XL
7807 * @retval interface status (MANDATORY: return 0 -> no Error)
7808 *
7809 */
lsm6dso_den_mark_axis_z_get(stmdev_ctx_t * ctx,uint8_t * val)7810 int32_t lsm6dso_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
7811 {
7812 lsm6dso_ctrl9_xl_t reg;
7813 int32_t ret;
7814
7815 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL, (uint8_t *)®, 1);
7816 *val = reg.den_x;
7817
7818 return ret;
7819 }
7820
7821 /**
7822 * @}
7823 *
7824 */
7825
7826 /**
7827 * @defgroup LSM6DSO_Pedometer
7828 * @brief This section groups all the functions that manage pedometer.
7829 * @{
7830 *
7831 */
7832
7833 /**
7834 * @brief Enable pedometer algorithm.[set]
7835 *
7836 * @param ctx read / write interface definitions
7837 * @param val turn on and configure pedometer
7838 * @retval interface status (MANDATORY: return 0 -> no Error)
7839 *
7840 */
lsm6dso_pedo_sens_set(stmdev_ctx_t * ctx,lsm6dso_pedo_md_t val)7841 int32_t lsm6dso_pedo_sens_set(stmdev_ctx_t *ctx,
7842 lsm6dso_pedo_md_t val)
7843 {
7844 lsm6dso_pedo_cmd_reg_t pedo_cmd_reg;
7845 int32_t ret;
7846
7847 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
7848 (uint8_t *)&pedo_cmd_reg);
7849
7850 if (ret == 0)
7851 {
7852 pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U) >> 4;
7853 pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U) >> 5;
7854 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_CMD_REG,
7855 (uint8_t *)&pedo_cmd_reg);
7856 }
7857
7858 return ret;
7859 }
7860
7861 /**
7862 * @brief Enable pedometer algorithm.[get]
7863 *
7864 * @param ctx read / write interface definitions
7865 * @param val turn on and configure pedometer
7866 * @retval interface status (MANDATORY: return 0 -> no Error)
7867 *
7868 */
lsm6dso_pedo_sens_get(stmdev_ctx_t * ctx,lsm6dso_pedo_md_t * val)7869 int32_t lsm6dso_pedo_sens_get(stmdev_ctx_t *ctx,
7870 lsm6dso_pedo_md_t *val)
7871 {
7872 lsm6dso_pedo_cmd_reg_t pedo_cmd_reg;
7873 int32_t ret;
7874
7875 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
7876 (uint8_t *)&pedo_cmd_reg);
7877
7878 switch ((pedo_cmd_reg.ad_det_en << 5) | (pedo_cmd_reg.fp_rejection_en
7879 << 4))
7880 {
7881 case LSM6DSO_PEDO_BASE_MODE:
7882 *val = LSM6DSO_PEDO_BASE_MODE;
7883 break;
7884
7885 case LSM6DSO_FALSE_STEP_REJ:
7886 *val = LSM6DSO_FALSE_STEP_REJ;
7887 break;
7888
7889 case LSM6DSO_FALSE_STEP_REJ_ADV_MODE:
7890 *val = LSM6DSO_FALSE_STEP_REJ_ADV_MODE;
7891 break;
7892
7893 default:
7894 *val = LSM6DSO_PEDO_BASE_MODE;
7895 break;
7896 }
7897
7898 return ret;
7899 }
7900
7901 /**
7902 * @brief Interrupt status bit for step detection.[get]
7903 *
7904 * @param ctx read / write interface definitions
7905 * @param val change the values of is_step_det in reg EMB_FUNC_STATUS
7906 * @retval interface status (MANDATORY: return 0 -> no Error)
7907 *
7908 */
lsm6dso_pedo_step_detect_get(stmdev_ctx_t * ctx,uint8_t * val)7909 int32_t lsm6dso_pedo_step_detect_get(stmdev_ctx_t *ctx, uint8_t *val)
7910 {
7911 lsm6dso_emb_func_status_t reg;
7912 int32_t ret;
7913
7914 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
7915
7916 if (ret == 0)
7917 {
7918 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)®, 1);
7919 }
7920
7921 if (ret == 0)
7922 {
7923 *val = reg.is_step_det;
7924 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
7925 }
7926
7927 return ret;
7928 }
7929
7930 /**
7931 * @brief Pedometer debounce configuration register (r/w).[set]
7932 *
7933 * @param ctx read / write interface definitions
7934 * @param buff buffer that contains data to write
7935 * @retval interface status (MANDATORY: return 0 -> no Error)
7936 *
7937 */
lsm6dso_pedo_debounce_steps_set(stmdev_ctx_t * ctx,uint8_t * buff)7938 int32_t lsm6dso_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
7939 uint8_t *buff)
7940 {
7941 int32_t ret;
7942
7943 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_DEB_STEPS_CONF,
7944 buff);
7945
7946 return ret;
7947 }
7948
7949 /**
7950 * @brief Pedometer debounce configuration register (r/w).[get]
7951 *
7952 * @param ctx read / write interface definitions
7953 * @param buff buffer that stores data read
7954 * @retval interface status (MANDATORY: return 0 -> no Error)
7955 *
7956 */
lsm6dso_pedo_debounce_steps_get(stmdev_ctx_t * ctx,uint8_t * buff)7957 int32_t lsm6dso_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
7958 uint8_t *buff)
7959 {
7960 int32_t ret;
7961
7962 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_DEB_STEPS_CONF, buff);
7963
7964 return ret;
7965 }
7966
7967 /**
7968 * @brief Time period register for step detection on delta time (r/w).[set]
7969 *
7970 * @param ctx read / write interface definitions
7971 * @param buff buffer that contains data to write
7972 * @retval interface status (MANDATORY: return 0 -> no Error)
7973 *
7974 */
lsm6dso_pedo_steps_period_set(stmdev_ctx_t * ctx,uint16_t val)7975 int32_t lsm6dso_pedo_steps_period_set(stmdev_ctx_t *ctx, uint16_t val)
7976 {
7977 uint8_t buff[2];
7978 int32_t ret;
7979
7980 buff[1] = (uint8_t)(val / 256U);
7981 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7982 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L,
7983 &buff[0]);
7984
7985 if (ret == 0)
7986 {
7987 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_H,
7988 &buff[1]);
7989 }
7990
7991 return ret;
7992 }
7993
7994 /**
7995 * @brief Time period register for step detection on delta time (r/w).[get]
7996 *
7997 * @param ctx read / write interface definitions
7998 * @param buff buffer that stores data read
7999 * @retval interface status (MANDATORY: return 0 -> no Error)
8000 *
8001 */
lsm6dso_pedo_steps_period_get(stmdev_ctx_t * ctx,uint16_t * val)8002 int32_t lsm6dso_pedo_steps_period_get(stmdev_ctx_t *ctx,
8003 uint16_t *val)
8004 {
8005 uint8_t buff[2];
8006 int32_t ret;
8007
8008 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_L,
8009 &buff[0]);
8010
8011 if (ret == 0)
8012 {
8013 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_SC_DELTAT_H,
8014 &buff[1]);
8015 *val = buff[1];
8016 *val = (*val * 256U) + buff[0];
8017 }
8018
8019 return ret;
8020 }
8021
8022 /**
8023 * @brief Set when user wants to generate interrupt on count overflow
8024 * event/every step.[set]
8025 *
8026 * @param ctx read / write interface definitions
8027 * @param val change the values of carry_count_en in reg PEDO_CMD_REG
8028 * @retval interface status (MANDATORY: return 0 -> no Error)
8029 *
8030 */
lsm6dso_pedo_int_mode_set(stmdev_ctx_t * ctx,lsm6dso_carry_count_en_t val)8031 int32_t lsm6dso_pedo_int_mode_set(stmdev_ctx_t *ctx,
8032 lsm6dso_carry_count_en_t val)
8033 {
8034 lsm6dso_pedo_cmd_reg_t reg;
8035 int32_t ret;
8036
8037 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
8038 (uint8_t *)®);
8039
8040 if (ret == 0)
8041 {
8042 reg.carry_count_en = (uint8_t)val;
8043 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_PEDO_CMD_REG,
8044 (uint8_t *)®);
8045 }
8046
8047 return ret;
8048 }
8049
8050 /**
8051 * @brief Set when user wants to generate interrupt on count overflow
8052 * event/every step.[get]
8053 *
8054 * @param ctx read / write interface definitions
8055 * @param val Get the values of carry_count_en in reg PEDO_CMD_REG
8056 * @retval interface status (MANDATORY: return 0 -> no Error)
8057 *
8058 */
lsm6dso_pedo_int_mode_get(stmdev_ctx_t * ctx,lsm6dso_carry_count_en_t * val)8059 int32_t lsm6dso_pedo_int_mode_get(stmdev_ctx_t *ctx,
8060 lsm6dso_carry_count_en_t *val)
8061 {
8062 lsm6dso_pedo_cmd_reg_t reg;
8063 int32_t ret;
8064
8065 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_PEDO_CMD_REG,
8066 (uint8_t *)®);
8067
8068 switch (reg.carry_count_en)
8069 {
8070 case LSM6DSO_EVERY_STEP:
8071 *val = LSM6DSO_EVERY_STEP;
8072 break;
8073
8074 case LSM6DSO_COUNT_OVERFLOW:
8075 *val = LSM6DSO_COUNT_OVERFLOW;
8076 break;
8077
8078 default:
8079 *val = LSM6DSO_EVERY_STEP;
8080 break;
8081 }
8082
8083 return ret;
8084 }
8085
8086 /**
8087 * @}
8088 *
8089 */
8090
8091 /**
8092 * @defgroup LSM6DSO_significant_motion
8093 * @brief This section groups all the functions that manage the
8094 * significant motion detection.
8095 * @{
8096 *
8097 */
8098
8099 /**
8100 * @brief Interrupt status bit for significant motion detection.[get]
8101 *
8102 * @param ctx read / write interface definitions
8103 * @param val change the values of is_sigmot in reg EMB_FUNC_STATUS
8104 * @retval interface status (MANDATORY: return 0 -> no Error)
8105 *
8106 */
lsm6dso_motion_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)8107 int32_t lsm6dso_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
8108 uint8_t *val)
8109 {
8110 lsm6dso_emb_func_status_t reg;
8111 int32_t ret;
8112
8113 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8114
8115 if (ret == 0)
8116 {
8117 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)®, 1);
8118 }
8119
8120 if (ret == 0)
8121 {
8122 *val = reg.is_sigmot;
8123 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8124 }
8125
8126 return ret;
8127 }
8128
8129 /**
8130 * @}
8131 *
8132 */
8133
8134 /**
8135 * @defgroup LSM6DSO_tilt_detection
8136 * @brief This section groups all the functions that manage the tilt
8137 * event detection.
8138 * @{
8139 *
8140 */
8141
8142 /**
8143 * @brief Interrupt status bit for tilt detection.[get]
8144 *
8145 * @param ctx read / write interface definitions
8146 * @param val change the values of is_tilt in reg EMB_FUNC_STATUS
8147 * @retval interface status (MANDATORY: return 0 -> no Error)
8148 *
8149 */
lsm6dso_tilt_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)8150 int32_t lsm6dso_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
8151 uint8_t *val)
8152 {
8153 lsm6dso_emb_func_status_t reg;
8154 int32_t ret;
8155
8156 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8157
8158 if (ret == 0)
8159 {
8160 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)®, 1);
8161 }
8162
8163 if (ret == 0)
8164 {
8165 *val = reg.is_tilt;
8166 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8167 }
8168
8169 return ret;
8170 }
8171
8172 /**
8173 * @}
8174 *
8175 */
8176
8177 /**
8178 * @defgroup LSM6DSO_ magnetometer_sensor
8179 * @brief This section groups all the functions that manage additional
8180 * magnetometer sensor.
8181 * @{
8182 *
8183 */
8184
8185 /**
8186 * @brief External magnetometer sensitivity value register.[set]
8187 *
8188 * @param ctx read / write interface definitions
8189 * @param buff buffer that contains data to write
8190 * @retval interface status (MANDATORY: return 0 -> no Error)
8191 *
8192 */
lsm6dso_mag_sensitivity_set(stmdev_ctx_t * ctx,uint16_t val)8193 int32_t lsm6dso_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val)
8194 {
8195 uint8_t buff[2];
8196 int32_t ret;
8197
8198 buff[1] = (uint8_t)(val / 256U);
8199 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8200 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SENSITIVITY_L,
8201 &buff[0]);
8202
8203 if (ret == 0)
8204 {
8205 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SENSITIVITY_H,
8206 &buff[1]);
8207 }
8208
8209 return ret;
8210 }
8211
8212 /**
8213 * @brief External magnetometer sensitivity value register.[get]
8214 *
8215 * @param ctx read / write interface definitions
8216 * @param buff buffer that stores data read
8217 * @retval interface status (MANDATORY: return 0 -> no Error)
8218 *
8219 */
lsm6dso_mag_sensitivity_get(stmdev_ctx_t * ctx,uint16_t * val)8220 int32_t lsm6dso_mag_sensitivity_get(stmdev_ctx_t *ctx, uint16_t *val)
8221 {
8222 uint8_t buff[2];
8223 int32_t ret;
8224
8225 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SENSITIVITY_L,
8226 &buff[0]);
8227
8228 if (ret == 0)
8229 {
8230 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SENSITIVITY_H,
8231 &buff[1]);
8232 *val = buff[1];
8233 *val = (*val * 256U) + buff[0];
8234 }
8235
8236 return ret;
8237 }
8238
8239 /**
8240 * @brief Offset for hard-iron compensation register (r/w).[set]
8241 *
8242 * @param ctx read / write interface definitions
8243 * @param buff buffer that contains data to write
8244 * @retval interface status (MANDATORY: return 0 -> no Error)
8245 *
8246 */
lsm6dso_mag_offset_set(stmdev_ctx_t * ctx,int16_t * val)8247 int32_t lsm6dso_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
8248 {
8249 uint8_t buff[6];
8250 int32_t ret;
8251
8252 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
8253 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
8254 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
8255 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
8256 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
8257 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
8258 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFX_L, &buff[0]);
8259
8260 if (ret == 0)
8261 {
8262 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFX_H, &buff[1]);
8263 }
8264
8265 if (ret == 0)
8266 {
8267 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFY_L, &buff[2]);
8268 }
8269
8270 if (ret == 0)
8271 {
8272 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFY_H, &buff[3]);
8273 }
8274
8275 if (ret == 0)
8276 {
8277 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFZ_L, &buff[4]);
8278 }
8279
8280 if (ret == 0)
8281 {
8282 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_OFFZ_H, &buff[5]);
8283 }
8284
8285 return ret;
8286 }
8287
8288 /**
8289 * @brief Offset for hard-iron compensation register (r/w).[get]
8290 *
8291 * @param ctx read / write interface definitions
8292 * @param buff buffer that stores data read
8293 * @retval interface status (MANDATORY: return 0 -> no Error)
8294 *
8295 */
lsm6dso_mag_offset_get(stmdev_ctx_t * ctx,int16_t * val)8296 int32_t lsm6dso_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
8297 {
8298 uint8_t buff[6];
8299 int32_t ret;
8300
8301 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFX_L, &buff[0]);
8302
8303 if (ret == 0)
8304 {
8305 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFX_H, &buff[1]);
8306 }
8307
8308 if (ret == 0)
8309 {
8310 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFY_L, &buff[2]);
8311 }
8312
8313 if (ret == 0)
8314 {
8315 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFY_H, &buff[3]);
8316 }
8317
8318 if (ret == 0)
8319 {
8320 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFZ_L, &buff[4]);
8321 }
8322
8323 if (ret == 0)
8324 {
8325 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_OFFZ_H, &buff[5]);
8326 val[0] = (int16_t)buff[1];
8327 val[0] = (val[0] * 256) + (int16_t)buff[0];
8328 val[1] = (int16_t)buff[3];
8329 val[1] = (val[1] * 256) + (int16_t)buff[2];
8330 val[2] = (int16_t)buff[5];
8331 val[2] = (val[2] * 256) + (int16_t)buff[4];
8332 }
8333
8334 return ret;
8335 }
8336
8337 /**
8338 * @brief Soft-iron (3x3 symmetric) matrix correction
8339 * register (r/w). The value is expressed as
8340 * half-precision floating-point format:
8341 * SEEEEEFFFFFFFFFF
8342 * S: 1 sign bit;
8343 * E: 5 exponent bits;
8344 * F: 10 fraction bits).[set]
8345 *
8346 * @param ctx read / write interface definitions
8347 * @param buff buffer that contains data to write
8348 * @retval interface status (MANDATORY: return 0 -> no Error)
8349 *
8350 */
lsm6dso_mag_soft_iron_set(stmdev_ctx_t * ctx,int16_t * val)8351 int32_t lsm6dso_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val)
8352 {
8353 uint8_t buff[12];
8354 int32_t ret;
8355
8356 uint8_t index;
8357 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
8358 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
8359 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
8360 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
8361 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
8362 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
8363 buff[7] = (uint8_t)((uint16_t)val[3] / 256U);
8364 buff[6] = (uint8_t)((uint16_t)val[3] - (buff[7] * 256U));
8365 buff[9] = (uint8_t)((uint16_t)val[4] / 256U);
8366 buff[8] = (uint8_t)((uint16_t)val[4] - (buff[9] * 256U));
8367 buff[11] = (uint8_t)((uint16_t)val[5] / 256U);
8368 buff[10] = (uint8_t)((uint16_t)val[5] - (buff[11] * 256U));
8369 index = 0x00U;
8370 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XX_L,
8371 &buff[index]);
8372
8373 if (ret == 0)
8374 {
8375 index++;
8376 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XX_H,
8377 &buff[index]);
8378 }
8379
8380 if (ret == 0)
8381 {
8382 index++;
8383 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XY_L,
8384 &buff[index]);
8385 }
8386
8387 if (ret == 0)
8388 {
8389 index++;
8390 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XY_H,
8391 &buff[index]);
8392 }
8393
8394 if (ret == 0)
8395 {
8396 index++;
8397 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XZ_L,
8398 &buff[index]);
8399 }
8400
8401 if (ret == 0)
8402 {
8403 index++;
8404 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_XZ_H,
8405 &buff[index]);
8406 }
8407
8408 if (ret == 0)
8409 {
8410 index++;
8411 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YY_L,
8412 &buff[index]);
8413 }
8414
8415 if (ret == 0)
8416 {
8417 index++;
8418 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YY_H,
8419 &buff[index]);
8420 }
8421
8422 if (ret == 0)
8423 {
8424 index++;
8425 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YZ_L,
8426 &buff[index]);
8427 }
8428
8429 if (ret == 0)
8430 {
8431 index++;
8432 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_YZ_H,
8433 &buff[index]);
8434 }
8435
8436 if (ret == 0)
8437 {
8438 index++;
8439 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_ZZ_L,
8440 &buff[index]);
8441 }
8442
8443 if (ret == 0)
8444 {
8445 index++;
8446 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_SI_ZZ_H,
8447 &buff[index]);
8448 }
8449
8450 return ret;
8451 }
8452
8453 /**
8454 * @brief Soft-iron (3x3 symmetric) matrix
8455 * correction register (r/w).
8456 * The value is expressed as half-precision
8457 * floating-point format:
8458 * SEEEEEFFFFFFFFFF
8459 * S: 1 sign bit;
8460 * E: 5 exponent bits;
8461 * F: 10 fraction bits.[get]
8462 *
8463 * @param ctx read / write interface definitions
8464 * @param buff buffer that stores data read
8465 * @retval interface status (MANDATORY: return 0 -> no Error)
8466 *
8467 */
lsm6dso_mag_soft_iron_get(stmdev_ctx_t * ctx,int16_t * val)8468 int32_t lsm6dso_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val)
8469 {
8470 uint8_t buff[12];
8471 int32_t ret;
8472
8473 uint8_t index;
8474 index = 0x00U;
8475 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XX_L, &buff[index]);
8476
8477 if (ret == 0)
8478 {
8479 index++;
8480 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XX_H, &buff[index]);
8481 }
8482
8483 if (ret == 0)
8484 {
8485 index++;
8486 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XY_L, &buff[index]);
8487 }
8488
8489 if (ret == 0)
8490 {
8491 index++;
8492 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XY_H, &buff[index]);
8493 }
8494
8495 if (ret == 0)
8496 {
8497 index++;
8498 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XZ_L, &buff[index]);
8499 }
8500
8501 if (ret == 0)
8502 {
8503 index++;
8504 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_XZ_H, &buff[index]);
8505 }
8506
8507 if (ret == 0)
8508 {
8509 index++;
8510 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YY_L, &buff[index]);
8511 }
8512
8513 if (ret == 0)
8514 {
8515 index++;
8516 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YY_H, &buff[index]);
8517 }
8518
8519 if (ret == 0)
8520 {
8521 index++;
8522 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YZ_L, &buff[index]);
8523 }
8524
8525 if (ret == 0)
8526 {
8527 index++;
8528 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_YZ_H, &buff[index]);
8529 }
8530
8531 if (ret == 0)
8532 {
8533 index++;
8534 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_ZZ_L, &buff[index]);
8535 }
8536
8537 if (ret == 0)
8538 {
8539 index++;
8540 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_SI_ZZ_H, &buff[index]);
8541 }
8542
8543 val[0] = (int16_t)buff[1];
8544 val[0] = (val[0] * 256) + (int16_t)buff[0];
8545 val[1] = (int16_t)buff[3];
8546 val[1] = (val[1] * 256) + (int16_t)buff[2];
8547 val[2] = (int16_t)buff[5];
8548 val[2] = (val[2] * 256) + (int16_t)buff[4];
8549 val[3] = (int16_t)buff[7];
8550 val[3] = (val[3] * 256) + (int16_t)buff[6];
8551 val[4] = (int16_t)buff[9];
8552 val[4] = (val[4] * 256) + (int16_t)buff[8];
8553 val[5] = (int16_t)buff[11];
8554 val[5] = (val[5] * 256) + (int16_t)buff[10];
8555
8556 return ret;
8557 }
8558
8559 /**
8560 * @brief Magnetometer Z-axis coordinates
8561 * rotation (to be aligned to
8562 * accelerometer/gyroscope axes
8563 * orientation).[set]
8564 *
8565 * @param ctx read / write interface definitions
8566 * @param val change the values of mag_z_axis in reg MAG_CFG_A
8567 * @retval interface status (MANDATORY: return 0 -> no Error)
8568 *
8569 */
lsm6dso_mag_z_orient_set(stmdev_ctx_t * ctx,lsm6dso_mag_z_axis_t val)8570 int32_t lsm6dso_mag_z_orient_set(stmdev_ctx_t *ctx,
8571 lsm6dso_mag_z_axis_t val)
8572 {
8573 lsm6dso_mag_cfg_a_t reg;
8574 int32_t ret;
8575
8576 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A,
8577 (uint8_t *)®);
8578
8579 if (ret == 0)
8580 {
8581 reg.mag_z_axis = (uint8_t) val;
8582 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A,
8583 (uint8_t *)®);
8584 }
8585
8586 return ret;
8587 }
8588
8589 /**
8590 * @brief Magnetometer Z-axis coordinates
8591 * rotation (to be aligned to
8592 * accelerometer/gyroscope axes
8593 * orientation).[get]
8594 *
8595 * @param ctx read / write interface definitions
8596 * @param val Get the values of mag_z_axis in reg MAG_CFG_A
8597 * @retval interface status (MANDATORY: return 0 -> no Error)
8598 *
8599 */
lsm6dso_mag_z_orient_get(stmdev_ctx_t * ctx,lsm6dso_mag_z_axis_t * val)8600 int32_t lsm6dso_mag_z_orient_get(stmdev_ctx_t *ctx,
8601 lsm6dso_mag_z_axis_t *val)
8602 {
8603 lsm6dso_mag_cfg_a_t reg;
8604 int32_t ret;
8605
8606 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A,
8607 (uint8_t *)®);
8608
8609 switch (reg.mag_z_axis)
8610 {
8611 case LSM6DSO_Z_EQ_Y:
8612 *val = LSM6DSO_Z_EQ_Y;
8613 break;
8614
8615 case LSM6DSO_Z_EQ_MIN_Y:
8616 *val = LSM6DSO_Z_EQ_MIN_Y;
8617 break;
8618
8619 case LSM6DSO_Z_EQ_X:
8620 *val = LSM6DSO_Z_EQ_X;
8621 break;
8622
8623 case LSM6DSO_Z_EQ_MIN_X:
8624 *val = LSM6DSO_Z_EQ_MIN_X;
8625 break;
8626
8627 case LSM6DSO_Z_EQ_MIN_Z:
8628 *val = LSM6DSO_Z_EQ_MIN_Z;
8629 break;
8630
8631 case LSM6DSO_Z_EQ_Z:
8632 *val = LSM6DSO_Z_EQ_Z;
8633 break;
8634
8635 default:
8636 *val = LSM6DSO_Z_EQ_Y;
8637 break;
8638 }
8639
8640 return ret;
8641 }
8642
8643 /**
8644 * @brief Magnetometer Y-axis coordinates
8645 * rotation (to be aligned to
8646 * accelerometer/gyroscope axes
8647 * orientation).[set]
8648 *
8649 * @param ctx read / write interface definitions
8650 * @param val change the values of mag_y_axis in reg MAG_CFG_A
8651 * @retval interface status (MANDATORY: return 0 -> no Error)
8652 *
8653 */
lsm6dso_mag_y_orient_set(stmdev_ctx_t * ctx,lsm6dso_mag_y_axis_t val)8654 int32_t lsm6dso_mag_y_orient_set(stmdev_ctx_t *ctx,
8655 lsm6dso_mag_y_axis_t val)
8656 {
8657 lsm6dso_mag_cfg_a_t reg;
8658 int32_t ret;
8659
8660 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A,
8661 (uint8_t *)®);
8662
8663 if (ret == 0)
8664 {
8665 reg.mag_y_axis = (uint8_t)val;
8666 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_A,
8667 (uint8_t *) ®);
8668 }
8669
8670 return ret;
8671 }
8672
8673 /**
8674 * @brief Magnetometer Y-axis coordinates
8675 * rotation (to be aligned to
8676 * accelerometer/gyroscope axes
8677 * orientation).[get]
8678 *
8679 * @param ctx read / write interface definitions
8680 * @param val Get the values of mag_y_axis in reg MAG_CFG_A
8681 * @retval interface status (MANDATORY: return 0 -> no Error)
8682 *
8683 */
lsm6dso_mag_y_orient_get(stmdev_ctx_t * ctx,lsm6dso_mag_y_axis_t * val)8684 int32_t lsm6dso_mag_y_orient_get(stmdev_ctx_t *ctx,
8685 lsm6dso_mag_y_axis_t *val)
8686 {
8687 lsm6dso_mag_cfg_a_t reg;
8688 int32_t ret;
8689
8690 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_A,
8691 (uint8_t *)®);
8692
8693 switch (reg.mag_y_axis)
8694 {
8695 case LSM6DSO_Y_EQ_Y:
8696 *val = LSM6DSO_Y_EQ_Y;
8697 break;
8698
8699 case LSM6DSO_Y_EQ_MIN_Y:
8700 *val = LSM6DSO_Y_EQ_MIN_Y;
8701 break;
8702
8703 case LSM6DSO_Y_EQ_X:
8704 *val = LSM6DSO_Y_EQ_X;
8705 break;
8706
8707 case LSM6DSO_Y_EQ_MIN_X:
8708 *val = LSM6DSO_Y_EQ_MIN_X;
8709 break;
8710
8711 case LSM6DSO_Y_EQ_MIN_Z:
8712 *val = LSM6DSO_Y_EQ_MIN_Z;
8713 break;
8714
8715 case LSM6DSO_Y_EQ_Z:
8716 *val = LSM6DSO_Y_EQ_Z;
8717 break;
8718
8719 default:
8720 *val = LSM6DSO_Y_EQ_Y;
8721 break;
8722 }
8723
8724 return ret;
8725 }
8726
8727 /**
8728 * @brief Magnetometer X-axis coordinates
8729 * rotation (to be aligned to
8730 * accelerometer/gyroscope axes
8731 * orientation).[set]
8732 *
8733 * @param ctx read / write interface definitions
8734 * @param val change the values of mag_x_axis in reg MAG_CFG_B
8735 * @retval interface status (MANDATORY: return 0 -> no Error)
8736 *
8737 */
lsm6dso_mag_x_orient_set(stmdev_ctx_t * ctx,lsm6dso_mag_x_axis_t val)8738 int32_t lsm6dso_mag_x_orient_set(stmdev_ctx_t *ctx,
8739 lsm6dso_mag_x_axis_t val)
8740 {
8741 lsm6dso_mag_cfg_b_t reg;
8742 int32_t ret;
8743
8744 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B,
8745 (uint8_t *)®);
8746
8747 if (ret == 0)
8748 {
8749 reg.mag_x_axis = (uint8_t)val;
8750 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_MAG_CFG_B,
8751 (uint8_t *)®);
8752 }
8753
8754 return ret;
8755 }
8756
8757 /**
8758 * @brief Magnetometer X-axis coordinates
8759 * rotation (to be aligned to
8760 * accelerometer/gyroscope axes
8761 * orientation).[get]
8762 *
8763 * @param ctx read / write interface definitions
8764 * @param val Get the values of mag_x_axis in reg MAG_CFG_B
8765 * @retval interface status (MANDATORY: return 0 -> no Error)
8766 *
8767 */
lsm6dso_mag_x_orient_get(stmdev_ctx_t * ctx,lsm6dso_mag_x_axis_t * val)8768 int32_t lsm6dso_mag_x_orient_get(stmdev_ctx_t *ctx,
8769 lsm6dso_mag_x_axis_t *val)
8770 {
8771 lsm6dso_mag_cfg_b_t reg;
8772 int32_t ret;
8773
8774 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_MAG_CFG_B,
8775 (uint8_t *)®);
8776
8777 switch (reg.mag_x_axis)
8778 {
8779 case LSM6DSO_X_EQ_Y:
8780 *val = LSM6DSO_X_EQ_Y;
8781 break;
8782
8783 case LSM6DSO_X_EQ_MIN_Y:
8784 *val = LSM6DSO_X_EQ_MIN_Y;
8785 break;
8786
8787 case LSM6DSO_X_EQ_X:
8788 *val = LSM6DSO_X_EQ_X;
8789 break;
8790
8791 case LSM6DSO_X_EQ_MIN_X:
8792 *val = LSM6DSO_X_EQ_MIN_X;
8793 break;
8794
8795 case LSM6DSO_X_EQ_MIN_Z:
8796 *val = LSM6DSO_X_EQ_MIN_Z;
8797 break;
8798
8799 case LSM6DSO_X_EQ_Z:
8800 *val = LSM6DSO_X_EQ_Z;
8801 break;
8802
8803 default:
8804 *val = LSM6DSO_X_EQ_Y;
8805 break;
8806 }
8807
8808 return ret;
8809 }
8810
8811 /**
8812 * @}
8813 *
8814 */
8815
8816 /**
8817 * @defgroup LSM6DSO_finite_state_machine
8818 * @brief This section groups all the functions that manage the
8819 * state_machine.
8820 * @{
8821 *
8822 */
8823
8824 /**
8825 * @brief Interrupt status bit for FSM long counter
8826 * timeout interrupt event.[get]
8827 *
8828 * @param ctx read / write interface definitions
8829 * @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS
8830 * @retval interface status (MANDATORY: return 0 -> no Error)
8831 *
8832 */
lsm6dso_long_cnt_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)8833 int32_t lsm6dso_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
8834 uint8_t *val)
8835 {
8836 lsm6dso_emb_func_status_t reg;
8837 int32_t ret;
8838
8839 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8840
8841 if (ret == 0)
8842 {
8843 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS, (uint8_t *)®, 1);
8844 }
8845
8846 if (ret == 0)
8847 {
8848 *val = reg.is_fsm_lc;
8849 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8850 }
8851
8852 return ret;
8853 }
8854
8855 /**
8856 * @brief Final State Machine enable.[set]
8857 *
8858 * @param ctx read / write interface definitions
8859 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
8860 * @retval interface status (MANDATORY: return 0 -> no Error)
8861 *
8862 */
lsm6dso_fsm_enable_set(stmdev_ctx_t * ctx,lsm6dso_emb_fsm_enable_t * val)8863 int32_t lsm6dso_fsm_enable_set(stmdev_ctx_t *ctx,
8864 lsm6dso_emb_fsm_enable_t *val)
8865 {
8866 int32_t ret;
8867
8868 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8869
8870 if (ret == 0)
8871 {
8872 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_A,
8873 (uint8_t *)&val->fsm_enable_a, 1);
8874 }
8875
8876 if (ret == 0)
8877 {
8878 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_ENABLE_B,
8879 (uint8_t *)&val->fsm_enable_b, 1);
8880 }
8881
8882 if (ret == 0)
8883 {
8884 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8885 }
8886
8887 return ret;
8888 }
8889
8890 /**
8891 * @brief Final State Machine enable.[get]
8892 *
8893 * @param ctx read / write interface definitions
8894 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
8895 * @retval interface status (MANDATORY: return 0 -> no Error)
8896 *
8897 */
lsm6dso_fsm_enable_get(stmdev_ctx_t * ctx,lsm6dso_emb_fsm_enable_t * val)8898 int32_t lsm6dso_fsm_enable_get(stmdev_ctx_t *ctx,
8899 lsm6dso_emb_fsm_enable_t *val)
8900 {
8901 int32_t ret;
8902
8903 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8904
8905 if (ret == 0)
8906 {
8907 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_ENABLE_A, (uint8_t *) val, 2);
8908 }
8909
8910 if (ret == 0)
8911 {
8912 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8913 }
8914
8915 return ret;
8916 }
8917
8918 /**
8919 * @brief FSM long counter status register. Long counter value is an
8920 * unsigned integer value (16-bit format).[set]
8921 *
8922 * @param ctx read / write interface definitions
8923 * @param buff buffer that contains data to write
8924 * @retval interface status (MANDATORY: return 0 -> no Error)
8925 *
8926 */
lsm6dso_long_cnt_set(stmdev_ctx_t * ctx,uint16_t val)8927 int32_t lsm6dso_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
8928 {
8929 uint8_t buff[2];
8930 int32_t ret;
8931
8932 buff[1] = (uint8_t)(val / 256U);
8933 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8934 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8935
8936 if (ret == 0)
8937 {
8938 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_L, buff, 2);
8939 }
8940
8941 if (ret == 0)
8942 {
8943 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8944 }
8945
8946 return ret;
8947 }
8948
8949 /**
8950 * @brief FSM long counter status register. Long counter value is an
8951 * unsigned integer value (16-bit format).[get]
8952 *
8953 * @param ctx read / write interface definitions
8954 * @param buff buffer that stores data read
8955 * @retval interface status (MANDATORY: return 0 -> no Error)
8956 *
8957 */
lsm6dso_long_cnt_get(stmdev_ctx_t * ctx,uint16_t * val)8958 int32_t lsm6dso_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
8959 {
8960 uint8_t buff[2];
8961 int32_t ret;
8962
8963 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8964
8965 if (ret == 0)
8966 {
8967 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_L, buff, 2);
8968 }
8969
8970 if (ret == 0)
8971 {
8972 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
8973 *val = buff[1];
8974 *val = (*val * 256U) + buff[0];
8975 }
8976
8977 return ret;
8978 }
8979
8980 /**
8981 * @brief Clear FSM long counter value.[set]
8982 *
8983 * @param ctx read / write interface definitions
8984 * @param val change the values of fsm_lc_clr in
8985 * reg FSM_LONG_COUNTER_CLEAR
8986 * @retval interface status (MANDATORY: return 0 -> no Error)
8987 *
8988 */
lsm6dso_long_clr_set(stmdev_ctx_t * ctx,lsm6dso_fsm_lc_clr_t val)8989 int32_t lsm6dso_long_clr_set(stmdev_ctx_t *ctx,
8990 lsm6dso_fsm_lc_clr_t val)
8991 {
8992 lsm6dso_fsm_long_counter_clear_t reg;
8993 int32_t ret;
8994
8995 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
8996
8997 if (ret == 0)
8998 {
8999 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR,
9000 (uint8_t *)®, 1);
9001 }
9002
9003 if (ret == 0)
9004 {
9005 reg. fsm_lc_clr = (uint8_t)val;
9006 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR,
9007 (uint8_t *)®, 1);
9008 }
9009
9010 if (ret == 0)
9011 {
9012 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9013 }
9014
9015 return ret;
9016 }
9017
9018 /**
9019 * @brief Clear FSM long counter value.[get]
9020 *
9021 * @param ctx read / write interface definitions
9022 * @param val Get the values of fsm_lc_clr in
9023 * reg FSM_LONG_COUNTER_CLEAR
9024 * @retval interface status (MANDATORY: return 0 -> no Error)
9025 *
9026 */
lsm6dso_long_clr_get(stmdev_ctx_t * ctx,lsm6dso_fsm_lc_clr_t * val)9027 int32_t lsm6dso_long_clr_get(stmdev_ctx_t *ctx,
9028 lsm6dso_fsm_lc_clr_t *val)
9029 {
9030 lsm6dso_fsm_long_counter_clear_t reg;
9031 int32_t ret;
9032
9033 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
9034
9035 if (ret == 0)
9036 {
9037 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_LONG_COUNTER_CLEAR,
9038 (uint8_t *)®, 1);
9039 }
9040
9041 if (ret == 0)
9042 {
9043 switch (reg.fsm_lc_clr)
9044 {
9045 case LSM6DSO_LC_NORMAL:
9046 *val = LSM6DSO_LC_NORMAL;
9047 break;
9048
9049 case LSM6DSO_LC_CLEAR:
9050 *val = LSM6DSO_LC_CLEAR;
9051 break;
9052
9053 case LSM6DSO_LC_CLEAR_DONE:
9054 *val = LSM6DSO_LC_CLEAR_DONE;
9055 break;
9056
9057 default:
9058 *val = LSM6DSO_LC_NORMAL;
9059 break;
9060 }
9061 }
9062
9063 if (ret == 0)
9064 {
9065 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9066 }
9067
9068 return ret;
9069 }
9070
9071 /**
9072 * @brief FSM output registers[get]
9073 *
9074 * @param ctx read / write interface definitions
9075 * @param val struct of registers from FSM_OUTS1 to FSM_OUTS16
9076 * @retval interface status (MANDATORY: return 0 -> no Error)
9077 *
9078 */
lsm6dso_fsm_out_get(stmdev_ctx_t * ctx,lsm6dso_fsm_out_t * val)9079 int32_t lsm6dso_fsm_out_get(stmdev_ctx_t *ctx, lsm6dso_fsm_out_t *val)
9080 {
9081 int32_t ret;
9082
9083 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
9084
9085 if (ret == 0)
9086 {
9087 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_OUTS1, (uint8_t *)val, 16);
9088 }
9089
9090 if (ret == 0)
9091 {
9092 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9093 }
9094
9095 return ret;
9096 }
9097
9098 /**
9099 * @brief Finite State Machine ODR configuration.[set]
9100 *
9101 * @param ctx read / write interface definitions
9102 * @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
9103 * @retval interface status (MANDATORY: return 0 -> no Error)
9104 *
9105 */
lsm6dso_fsm_data_rate_set(stmdev_ctx_t * ctx,lsm6dso_fsm_odr_t val)9106 int32_t lsm6dso_fsm_data_rate_set(stmdev_ctx_t *ctx,
9107 lsm6dso_fsm_odr_t val)
9108 {
9109 lsm6dso_emb_func_odr_cfg_b_t reg;
9110 int32_t ret;
9111
9112 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
9113
9114 if (ret == 0)
9115 {
9116 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B,
9117 (uint8_t *)®, 1);
9118 }
9119
9120 if (ret == 0)
9121 {
9122 reg.not_used_01 = 3; /* set default values */
9123 reg.not_used_02 = 2; /* set default values */
9124 reg.fsm_odr = (uint8_t)val;
9125 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B,
9126 (uint8_t *)®, 1);
9127 }
9128
9129 if (ret == 0)
9130 {
9131 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9132 }
9133
9134 return ret;
9135 }
9136
9137 /**
9138 * @brief Finite State Machine ODR configuration.[get]
9139 *
9140 * @param ctx read / write interface definitions
9141 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
9142 * @retval interface status (MANDATORY: return 0 -> no Error)
9143 *
9144 */
lsm6dso_fsm_data_rate_get(stmdev_ctx_t * ctx,lsm6dso_fsm_odr_t * val)9145 int32_t lsm6dso_fsm_data_rate_get(stmdev_ctx_t *ctx,
9146 lsm6dso_fsm_odr_t *val)
9147 {
9148 lsm6dso_emb_func_odr_cfg_b_t reg;
9149 int32_t ret;
9150
9151 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
9152
9153 if (ret == 0)
9154 {
9155 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B,
9156 (uint8_t *)®, 1);
9157 }
9158
9159 if (ret == 0)
9160 {
9161 switch (reg.fsm_odr)
9162 {
9163 case LSM6DSO_ODR_FSM_12Hz5:
9164 *val = LSM6DSO_ODR_FSM_12Hz5;
9165 break;
9166
9167 case LSM6DSO_ODR_FSM_26Hz:
9168 *val = LSM6DSO_ODR_FSM_26Hz;
9169 break;
9170
9171 case LSM6DSO_ODR_FSM_52Hz:
9172 *val = LSM6DSO_ODR_FSM_52Hz;
9173 break;
9174
9175 case LSM6DSO_ODR_FSM_104Hz:
9176 *val = LSM6DSO_ODR_FSM_104Hz;
9177 break;
9178
9179 default:
9180 *val = LSM6DSO_ODR_FSM_12Hz5;
9181 break;
9182 }
9183
9184 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9185 }
9186
9187 return ret;
9188 }
9189
9190 /**
9191 * @brief FSM initialization request.[set]
9192 *
9193 * @param ctx read / write interface definitions
9194 * @param val change the values of fsm_init in reg FSM_INIT
9195 * @retval interface status (MANDATORY: return 0 -> no Error)
9196 *
9197 */
lsm6dso_fsm_init_set(stmdev_ctx_t * ctx,uint8_t val)9198 int32_t lsm6dso_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
9199 {
9200 lsm6dso_emb_func_init_b_t reg;
9201 int32_t ret;
9202
9203 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
9204
9205 if (ret == 0)
9206 {
9207 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1);
9208 }
9209
9210 if (ret == 0)
9211 {
9212 reg.fsm_init = val;
9213 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1);
9214 }
9215
9216 if (ret == 0)
9217 {
9218 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9219 }
9220
9221 return ret;
9222 }
9223
9224 /**
9225 * @brief FSM initialization request.[get]
9226 *
9227 * @param ctx read / write interface definitions
9228 * @param val change the values of fsm_init in reg FSM_INIT
9229 * @retval interface status (MANDATORY: return 0 -> no Error)
9230 *
9231 */
lsm6dso_fsm_init_get(stmdev_ctx_t * ctx,uint8_t * val)9232 int32_t lsm6dso_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
9233 {
9234 lsm6dso_emb_func_init_b_t reg;
9235 int32_t ret;
9236
9237 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
9238
9239 if (ret == 0)
9240 {
9241 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B, (uint8_t *)®, 1);
9242 }
9243
9244 if (ret == 0)
9245 {
9246 *val = reg.fsm_init;
9247 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9248 }
9249
9250 return ret;
9251 }
9252
9253 /**
9254 * @brief FSM long counter timeout register (r/w). The long counter
9255 * timeout value is an unsigned integer value (16-bit format).
9256 * When the long counter value reached this value,
9257 * the FSM generates an interrupt.[set]
9258 *
9259 * @param ctx read / write interface definitions
9260 * @param val the value of long counter
9261 * @retval interface status (MANDATORY: return 0 -> no Error)
9262 *
9263 */
lsm6dso_long_cnt_int_value_set(stmdev_ctx_t * ctx,uint16_t val)9264 int32_t lsm6dso_long_cnt_int_value_set(stmdev_ctx_t *ctx,
9265 uint16_t val)
9266 {
9267 uint8_t buff[2];
9268 int32_t ret;
9269
9270 buff[1] = (uint8_t)(val / 256U);
9271 buff[0] = (uint8_t)(val - (buff[1] * 256U));
9272 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L,
9273 &buff[0]);
9274
9275 if (ret == 0)
9276 {
9277 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H,
9278 &buff[1]);
9279 }
9280
9281 return ret;
9282 }
9283
9284 /**
9285 * @brief FSM long counter timeout register (r/w). The long counter
9286 * timeout value is an unsigned integer value (16-bit format).
9287 * When the long counter value reached this value,
9288 * the FSM generates an interrupt.[get]
9289 *
9290 * @param ctx read / write interface definitions
9291 * @param val buffer that stores the value of long counter
9292 * @retval interface status (MANDATORY: return 0 -> no Error)
9293 *
9294 */
lsm6dso_long_cnt_int_value_get(stmdev_ctx_t * ctx,uint16_t * val)9295 int32_t lsm6dso_long_cnt_int_value_get(stmdev_ctx_t *ctx,
9296 uint16_t *val)
9297 {
9298 uint8_t buff[2];
9299 int32_t ret;
9300
9301 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_L,
9302 &buff[0]);
9303
9304 if (ret == 0)
9305 {
9306 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_LC_TIMEOUT_H,
9307 &buff[1]);
9308 *val = buff[1];
9309 *val = (*val * 256U) + buff[0];
9310 }
9311
9312 return ret;
9313 }
9314
9315 /**
9316 * @brief FSM number of programs register.[set]
9317 *
9318 * @param ctx read / write interface definitions
9319 * @param val value to write
9320 * @retval interface status (MANDATORY: return 0 -> no Error)
9321 *
9322 */
lsm6dso_fsm_number_of_programs_set(stmdev_ctx_t * ctx,uint8_t val)9323 int32_t lsm6dso_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
9324 uint8_t val)
9325 {
9326 int32_t ret;
9327
9328 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_PROGRAMS, &val);
9329
9330 return ret;
9331 }
9332
9333 /**
9334 * @brief FSM number of programs register.[get]
9335 *
9336 * @param ctx read / write interface definitions
9337 * @param val buffer that stores data read.
9338 * @retval interface status (MANDATORY: return 0 -> no Error)
9339 *
9340 */
lsm6dso_fsm_number_of_programs_get(stmdev_ctx_t * ctx,uint8_t * val)9341 int32_t lsm6dso_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
9342 uint8_t *val)
9343 {
9344 int32_t ret;
9345
9346 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_PROGRAMS, val);
9347
9348 return ret;
9349 }
9350
9351 /**
9352 * @brief FSM start address register (r/w).
9353 * First available address is 0x033C.[set]
9354 *
9355 * @param ctx read / write interface definitions
9356 * @param val the value of start address
9357 * @retval interface status (MANDATORY: return 0 -> no Error)
9358 *
9359 */
lsm6dso_fsm_start_address_set(stmdev_ctx_t * ctx,uint16_t val)9360 int32_t lsm6dso_fsm_start_address_set(stmdev_ctx_t *ctx, uint16_t val)
9361 {
9362 uint8_t buff[2];
9363 int32_t ret;
9364
9365 buff[1] = (uint8_t)(val / 256U);
9366 buff[0] = (uint8_t)(val - (buff[1] * 256U));
9367 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_L,
9368 &buff[0]);
9369
9370 if (ret == 0)
9371 {
9372 ret = lsm6dso_ln_pg_write_byte(ctx, LSM6DSO_FSM_START_ADD_H,
9373 &buff[1]);
9374 }
9375
9376 return ret;
9377 }
9378
9379 /**
9380 * @brief FSM start address register (r/w).
9381 * First available address is 0x033C.[get]
9382 *
9383 * @param ctx read / write interface definitions
9384 * @param val buffer the value of start address.
9385 * @retval interface status (MANDATORY: return 0 -> no Error)
9386 *
9387 */
lsm6dso_fsm_start_address_get(stmdev_ctx_t * ctx,uint16_t * val)9388 int32_t lsm6dso_fsm_start_address_get(stmdev_ctx_t *ctx,
9389 uint16_t *val)
9390 {
9391 uint8_t buff[2];
9392 int32_t ret;
9393
9394 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_L, &buff[0]);
9395
9396 if (ret == 0)
9397 {
9398 ret = lsm6dso_ln_pg_read_byte(ctx, LSM6DSO_FSM_START_ADD_H, &buff[1]);
9399 *val = buff[1];
9400 *val = (*val * 256U) + buff[0];
9401 }
9402
9403 return ret;
9404 }
9405
9406 /**
9407 * @}
9408 *
9409 */
9410
9411 /**
9412 * @defgroup LSM6DSO_Sensor_hub
9413 * @brief This section groups all the functions that manage the
9414 * sensor hub.
9415 * @{
9416 *
9417 */
9418
9419 /**
9420 * @brief Sensor hub output registers.[get]
9421 *
9422 * @param ctx read / write interface definitions
9423 * @param val values read from registers SENSOR_HUB_1 to SENSOR_HUB_18
9424 * @param len number of consecutive register to read (max 18)
9425 * @retval interface status (MANDATORY: return 0 -> no Error)
9426 *
9427 */
lsm6dso_sh_read_data_raw_get(stmdev_ctx_t * ctx,uint8_t * val,uint8_t len)9428 int32_t lsm6dso_sh_read_data_raw_get(stmdev_ctx_t *ctx, uint8_t *val,
9429 uint8_t len)
9430 {
9431 int32_t ret;
9432
9433 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9434
9435 if (ret == 0)
9436 {
9437 ret = lsm6dso_read_reg(ctx, LSM6DSO_SENSOR_HUB_1, (uint8_t *) val,
9438 len);
9439 }
9440
9441 if (ret == 0)
9442 {
9443 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9444 }
9445
9446 return ret;
9447 }
9448
9449 /**
9450 * @brief Number of external sensors to be read by the sensor hub.[set]
9451 *
9452 * @param ctx read / write interface definitions
9453 * @param val change the values of aux_sens_on in reg MASTER_CONFIG
9454 * @retval interface status (MANDATORY: return 0 -> no Error)
9455 *
9456 */
lsm6dso_sh_slave_connected_set(stmdev_ctx_t * ctx,lsm6dso_aux_sens_on_t val)9457 int32_t lsm6dso_sh_slave_connected_set(stmdev_ctx_t *ctx,
9458 lsm6dso_aux_sens_on_t val)
9459 {
9460 lsm6dso_master_config_t reg;
9461 int32_t ret;
9462
9463 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9464
9465 if (ret == 0)
9466 {
9467 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9468 }
9469
9470 if (ret == 0)
9471 {
9472 reg.aux_sens_on = (uint8_t)val;
9473 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9474 }
9475
9476 if (ret == 0)
9477 {
9478 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9479 }
9480
9481 return ret;
9482 }
9483
9484 /**
9485 * @brief Number of external sensors to be read by the sensor hub.[get]
9486 *
9487 * @param ctx read / write interface definitions
9488 * @param val Get the values of aux_sens_on in reg MASTER_CONFIG
9489 * @retval interface status (MANDATORY: return 0 -> no Error)
9490 *
9491 */
lsm6dso_sh_slave_connected_get(stmdev_ctx_t * ctx,lsm6dso_aux_sens_on_t * val)9492 int32_t lsm6dso_sh_slave_connected_get(stmdev_ctx_t *ctx,
9493 lsm6dso_aux_sens_on_t *val)
9494 {
9495 lsm6dso_master_config_t reg;
9496 int32_t ret;
9497
9498 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9499
9500 if (ret == 0)
9501 {
9502 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9503 }
9504
9505 if (ret == 0)
9506 {
9507 switch (reg.aux_sens_on)
9508 {
9509 case LSM6DSO_SLV_0:
9510 *val = LSM6DSO_SLV_0;
9511 break;
9512
9513 case LSM6DSO_SLV_0_1:
9514 *val = LSM6DSO_SLV_0_1;
9515 break;
9516
9517 case LSM6DSO_SLV_0_1_2:
9518 *val = LSM6DSO_SLV_0_1_2;
9519 break;
9520
9521 case LSM6DSO_SLV_0_1_2_3:
9522 *val = LSM6DSO_SLV_0_1_2_3;
9523 break;
9524
9525 default:
9526 *val = LSM6DSO_SLV_0;
9527 break;
9528 }
9529
9530 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9531 }
9532
9533 return ret;
9534 }
9535
9536 /**
9537 * @brief Sensor hub I2C master enable.[set]
9538 *
9539 * @param ctx read / write interface definitions
9540 * @param val change the values of master_on in reg MASTER_CONFIG
9541 * @retval interface status (MANDATORY: return 0 -> no Error)
9542 *
9543 */
lsm6dso_sh_master_set(stmdev_ctx_t * ctx,uint8_t val)9544 int32_t lsm6dso_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
9545 {
9546 lsm6dso_master_config_t reg;
9547 int32_t ret;
9548
9549 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9550
9551 if (ret == 0)
9552 {
9553 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9554 }
9555
9556 if (ret == 0)
9557 {
9558 reg.master_on = val;
9559 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9560 }
9561
9562 if (ret == 0)
9563 {
9564 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9565 }
9566
9567 return ret;
9568 }
9569
9570 /**
9571 * @brief Sensor hub I2C master enable.[get]
9572 *
9573 * @param ctx read / write interface definitions
9574 * @param val change the values of master_on in reg MASTER_CONFIG
9575 * @retval interface status (MANDATORY: return 0 -> no Error)
9576 *
9577 */
lsm6dso_sh_master_get(stmdev_ctx_t * ctx,uint8_t * val)9578 int32_t lsm6dso_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
9579 {
9580 lsm6dso_master_config_t reg;
9581 int32_t ret;
9582
9583 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9584
9585 if (ret == 0)
9586 {
9587 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9588 }
9589
9590 if (ret == 0)
9591 {
9592 *val = reg.master_on;
9593 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9594 }
9595
9596 return ret;
9597 }
9598
9599 /**
9600 * @brief Master I2C pull-up enable.[set]
9601 *
9602 * @param ctx read / write interface definitions
9603 * @param val change the values of shub_pu_en in reg MASTER_CONFIG
9604 * @retval interface status (MANDATORY: return 0 -> no Error)
9605 *
9606 */
lsm6dso_sh_pin_mode_set(stmdev_ctx_t * ctx,lsm6dso_shub_pu_en_t val)9607 int32_t lsm6dso_sh_pin_mode_set(stmdev_ctx_t *ctx,
9608 lsm6dso_shub_pu_en_t val)
9609 {
9610 lsm6dso_master_config_t reg;
9611 int32_t ret;
9612
9613 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9614
9615 if (ret == 0)
9616 {
9617 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9618 }
9619
9620 if (ret == 0)
9621 {
9622 reg.shub_pu_en = (uint8_t)val;
9623 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9624 }
9625
9626 if (ret == 0)
9627 {
9628 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9629 }
9630
9631 return ret;
9632 }
9633
9634 /**
9635 * @brief Master I2C pull-up enable.[get]
9636 *
9637 * @param ctx read / write interface definitions
9638 * @param val Get the values of shub_pu_en in reg MASTER_CONFIG
9639 * @retval interface status (MANDATORY: return 0 -> no Error)
9640 *
9641 */
lsm6dso_sh_pin_mode_get(stmdev_ctx_t * ctx,lsm6dso_shub_pu_en_t * val)9642 int32_t lsm6dso_sh_pin_mode_get(stmdev_ctx_t *ctx,
9643 lsm6dso_shub_pu_en_t *val)
9644 {
9645 lsm6dso_master_config_t reg;
9646 int32_t ret;
9647
9648 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9649
9650 if (ret == 0)
9651 {
9652 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9653 }
9654
9655 if (ret == 0)
9656 {
9657 switch (reg.shub_pu_en)
9658 {
9659 case LSM6DSO_EXT_PULL_UP:
9660 *val = LSM6DSO_EXT_PULL_UP;
9661 break;
9662
9663 case LSM6DSO_INTERNAL_PULL_UP:
9664 *val = LSM6DSO_INTERNAL_PULL_UP;
9665 break;
9666
9667 default:
9668 *val = LSM6DSO_EXT_PULL_UP;
9669 break;
9670 }
9671
9672 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9673 }
9674
9675 return ret;
9676 }
9677
9678 /**
9679 * @brief I2C interface pass-through.[set]
9680 *
9681 * @param ctx read / write interface definitions
9682 * @param val change the values of pass_through_mode in
9683 * reg MASTER_CONFIG
9684 * @retval interface status (MANDATORY: return 0 -> no Error)
9685 *
9686 */
lsm6dso_sh_pass_through_set(stmdev_ctx_t * ctx,uint8_t val)9687 int32_t lsm6dso_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
9688 {
9689 lsm6dso_master_config_t reg;
9690 int32_t ret;
9691
9692 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9693
9694 if (ret == 0)
9695 {
9696 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9697 }
9698
9699 if (ret == 0)
9700 {
9701 reg.pass_through_mode = val;
9702 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9703 }
9704
9705 if (ret == 0)
9706 {
9707 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9708 }
9709
9710 return ret;
9711 }
9712
9713 /**
9714 * @brief I2C interface pass-through.[get]
9715 *
9716 * @param ctx read / write interface definitions
9717 * @param val change the values of pass_through_mode in
9718 * reg MASTER_CONFIG
9719 * @retval interface status (MANDATORY: return 0 -> no Error)
9720 *
9721 */
lsm6dso_sh_pass_through_get(stmdev_ctx_t * ctx,uint8_t * val)9722 int32_t lsm6dso_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
9723 {
9724 lsm6dso_master_config_t reg;
9725 int32_t ret;
9726
9727 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9728
9729 if (ret == 0)
9730 {
9731 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9732 }
9733
9734 if (ret == 0)
9735 {
9736 *val = reg.pass_through_mode;
9737 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9738 }
9739
9740 return ret;
9741 }
9742
9743 /**
9744 * @brief Sensor hub trigger signal selection.[set]
9745 *
9746 * @param ctx read / write interface definitions
9747 * @param val change the values of start_config in reg MASTER_CONFIG
9748 * @retval interface status (MANDATORY: return 0 -> no Error)
9749 *
9750 */
lsm6dso_sh_syncro_mode_set(stmdev_ctx_t * ctx,lsm6dso_start_config_t val)9751 int32_t lsm6dso_sh_syncro_mode_set(stmdev_ctx_t *ctx,
9752 lsm6dso_start_config_t val)
9753 {
9754 lsm6dso_master_config_t reg;
9755 int32_t ret;
9756
9757 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9758
9759 if (ret == 0)
9760 {
9761 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9762 }
9763
9764 if (ret == 0)
9765 {
9766 reg.start_config = (uint8_t)val;
9767 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9768 }
9769
9770 if (ret == 0)
9771 {
9772 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9773 }
9774
9775 return ret;
9776 }
9777
9778 /**
9779 * @brief Sensor hub trigger signal selection.[get]
9780 *
9781 * @param ctx read / write interface definitions
9782 * @param val Get the values of start_config in reg MASTER_CONFIG
9783 * @retval interface status (MANDATORY: return 0 -> no Error)
9784 *
9785 */
lsm6dso_sh_syncro_mode_get(stmdev_ctx_t * ctx,lsm6dso_start_config_t * val)9786 int32_t lsm6dso_sh_syncro_mode_get(stmdev_ctx_t *ctx,
9787 lsm6dso_start_config_t *val)
9788 {
9789 lsm6dso_master_config_t reg;
9790 int32_t ret;
9791
9792 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9793
9794 if (ret == 0)
9795 {
9796 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9797 }
9798
9799 if (ret == 0)
9800 {
9801 switch (reg.start_config)
9802 {
9803 case LSM6DSO_EXT_ON_INT2_PIN:
9804 *val = LSM6DSO_EXT_ON_INT2_PIN;
9805 break;
9806
9807 case LSM6DSO_XL_GY_DRDY:
9808 *val = LSM6DSO_XL_GY_DRDY;
9809 break;
9810
9811 default:
9812 *val = LSM6DSO_EXT_ON_INT2_PIN;
9813 break;
9814 }
9815
9816 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9817 }
9818
9819 return ret;
9820 }
9821
9822 /**
9823 * @brief Slave 0 write operation is performed only at the first
9824 * sensor hub cycle.[set]
9825 *
9826 * @param ctx read / write interface definitions
9827 * @param val change the values of write_once in reg MASTER_CONFIG
9828 * @retval interface status (MANDATORY: return 0 -> no Error)
9829 *
9830 */
lsm6dso_sh_write_mode_set(stmdev_ctx_t * ctx,lsm6dso_write_once_t val)9831 int32_t lsm6dso_sh_write_mode_set(stmdev_ctx_t *ctx,
9832 lsm6dso_write_once_t val)
9833 {
9834 lsm6dso_master_config_t reg;
9835 int32_t ret;
9836
9837 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9838
9839 if (ret == 0)
9840 {
9841 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9842 }
9843
9844 if (ret == 0)
9845 {
9846 reg.write_once = (uint8_t)val;
9847 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9848 }
9849
9850 if (ret == 0)
9851 {
9852 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9853 }
9854
9855 return ret;
9856 }
9857
9858 /**
9859 * @brief Slave 0 write operation is performed only at the first sensor
9860 * hub cycle.[get]
9861 *
9862 * @param ctx read / write interface definitions
9863 * @param val Get the values of write_once in reg MASTER_CONFIG
9864 * @retval interface status (MANDATORY: return 0 -> no Error)
9865 *
9866 */
lsm6dso_sh_write_mode_get(stmdev_ctx_t * ctx,lsm6dso_write_once_t * val)9867 int32_t lsm6dso_sh_write_mode_get(stmdev_ctx_t *ctx,
9868 lsm6dso_write_once_t *val)
9869 {
9870 lsm6dso_master_config_t reg;
9871 int32_t ret;
9872
9873 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9874
9875 if (ret == 0)
9876 {
9877 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9878 }
9879
9880 if (ret == 0)
9881 {
9882 switch (reg.write_once)
9883 {
9884 case LSM6DSO_EACH_SH_CYCLE:
9885 *val = LSM6DSO_EACH_SH_CYCLE;
9886 break;
9887
9888 case LSM6DSO_ONLY_FIRST_CYCLE:
9889 *val = LSM6DSO_ONLY_FIRST_CYCLE;
9890 break;
9891
9892 default:
9893 *val = LSM6DSO_EACH_SH_CYCLE;
9894 break;
9895 }
9896
9897 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9898 }
9899
9900 return ret;
9901 }
9902
9903 /**
9904 * @brief Reset Master logic and output registers.[set]
9905 *
9906 * @param ctx read / write interface definitions
9907 * @retval interface status (MANDATORY: return 0 -> no Error)
9908 *
9909 */
lsm6dso_sh_reset_set(stmdev_ctx_t * ctx)9910 int32_t lsm6dso_sh_reset_set(stmdev_ctx_t *ctx)
9911 {
9912 lsm6dso_master_config_t reg;
9913 int32_t ret;
9914
9915 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9916
9917 if (ret == 0)
9918 {
9919 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9920 }
9921
9922 if (ret == 0)
9923 {
9924 reg.rst_master_regs = PROPERTY_ENABLE;
9925 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9926 }
9927
9928 if (ret == 0)
9929 {
9930 reg.rst_master_regs = PROPERTY_DISABLE;
9931 ret = lsm6dso_write_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9932 }
9933
9934 if (ret == 0)
9935 {
9936 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9937 }
9938
9939 return ret;
9940 }
9941
9942 /**
9943 * @brief Reset Master logic and output registers.[get]
9944 *
9945 * @param ctx read / write interface definitions
9946 * @param val change the values of rst_master_regs in reg MASTER_CONFIG
9947 * @retval interface status (MANDATORY: return 0 -> no Error)
9948 *
9949 */
lsm6dso_sh_reset_get(stmdev_ctx_t * ctx,uint8_t * val)9950 int32_t lsm6dso_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
9951 {
9952 lsm6dso_master_config_t reg;
9953 int32_t ret;
9954
9955 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9956
9957 if (ret == 0)
9958 {
9959 ret = lsm6dso_read_reg(ctx, LSM6DSO_MASTER_CONFIG, (uint8_t *)®, 1);
9960 }
9961
9962 if (ret == 0)
9963 {
9964 *val = reg.rst_master_regs;
9965 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
9966 }
9967
9968 return ret;
9969 }
9970
9971 /**
9972 * @brief Rate at which the master communicates.[set]
9973 *
9974 * @param ctx read / write interface definitions
9975 * @param val change the values of shub_odr in reg slv1_CONFIG
9976 * @retval interface status (MANDATORY: return 0 -> no Error)
9977 *
9978 */
lsm6dso_sh_data_rate_set(stmdev_ctx_t * ctx,lsm6dso_shub_odr_t val)9979 int32_t lsm6dso_sh_data_rate_set(stmdev_ctx_t *ctx,
9980 lsm6dso_shub_odr_t val)
9981 {
9982 lsm6dso_slv0_config_t reg;
9983 int32_t ret;
9984
9985 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
9986
9987 if (ret == 0)
9988 {
9989 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)®, 1);
9990 }
9991
9992 if (ret == 0)
9993 {
9994 reg.shub_odr = (uint8_t)val;
9995 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)®, 1);
9996 }
9997
9998 if (ret == 0)
9999 {
10000 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
10001 }
10002
10003 return ret;
10004 }
10005
10006 /**
10007 * @brief Rate at which the master communicates.[get]
10008 *
10009 * @param ctx read / write interface definitions
10010 * @param val Get the values of shub_odr in reg slv1_CONFIG
10011 * @retval interface status (MANDATORY: return 0 -> no Error)
10012 *
10013 */
lsm6dso_sh_data_rate_get(stmdev_ctx_t * ctx,lsm6dso_shub_odr_t * val)10014 int32_t lsm6dso_sh_data_rate_get(stmdev_ctx_t *ctx,
10015 lsm6dso_shub_odr_t *val)
10016 {
10017 lsm6dso_slv0_config_t reg;
10018 int32_t ret;
10019
10020 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
10021
10022 if (ret == 0)
10023 {
10024 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG, (uint8_t *)®, 1);
10025 }
10026
10027 if (ret == 0)
10028 {
10029 switch (reg.shub_odr)
10030 {
10031 case LSM6DSO_SH_ODR_104Hz:
10032 *val = LSM6DSO_SH_ODR_104Hz;
10033 break;
10034
10035 case LSM6DSO_SH_ODR_52Hz:
10036 *val = LSM6DSO_SH_ODR_52Hz;
10037 break;
10038
10039 case LSM6DSO_SH_ODR_26Hz:
10040 *val = LSM6DSO_SH_ODR_26Hz;
10041 break;
10042
10043 case LSM6DSO_SH_ODR_13Hz:
10044 *val = LSM6DSO_SH_ODR_13Hz;
10045 break;
10046
10047 default:
10048 *val = LSM6DSO_SH_ODR_104Hz;
10049 break;
10050 }
10051
10052 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
10053 }
10054
10055 return ret;
10056 }
10057
10058 /**
10059 * @brief Configure slave 0 for perform a write.[set]
10060 *
10061 * @param ctx read / write interface definitions
10062 * @param val a structure that contain
10063 * - uint8_t slv1_add; 8 bit i2c device address
10064 * - uint8_t slv1_subadd; 8 bit register device address
10065 * - uint8_t slv1_data; 8 bit data to write
10066 * @retval interface status (MANDATORY: return 0 -> no Error)
10067 *
10068 */
lsm6dso_sh_cfg_write(stmdev_ctx_t * ctx,lsm6dso_sh_cfg_write_t * val)10069 int32_t lsm6dso_sh_cfg_write(stmdev_ctx_t *ctx,
10070 lsm6dso_sh_cfg_write_t *val)
10071 {
10072 lsm6dso_slv0_add_t reg;
10073 int32_t ret;
10074
10075 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
10076
10077 if (ret == 0)
10078 {
10079 reg.slave0 = val->slv0_add;
10080 reg.rw_0 = 0;
10081 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD, (uint8_t *)®, 1);
10082 }
10083
10084 if (ret == 0)
10085 {
10086 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_SUBADD,
10087 &(val->slv0_subadd), 1);
10088 }
10089
10090 if (ret == 0)
10091 {
10092 ret = lsm6dso_write_reg(ctx, LSM6DSO_DATAWRITE_SLV0,
10093 &(val->slv0_data), 1);
10094 }
10095
10096 if (ret == 0)
10097 {
10098 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
10099 }
10100
10101 return ret;
10102 }
10103
10104 /**
10105 * @brief Configure slave 0 for perform a read.[set]
10106 *
10107 * @param ctx read / write interface definitions
10108 * @param val Structure that contain
10109 * - uint8_t slv1_add; 8 bit i2c device address
10110 * - uint8_t slv1_subadd; 8 bit register device address
10111 * - uint8_t slv1_len; num of bit to read
10112 * @retval interface status (MANDATORY: return 0 -> no Error)
10113 *
10114 */
lsm6dso_sh_slv0_cfg_read(stmdev_ctx_t * ctx,lsm6dso_sh_cfg_read_t * val)10115 int32_t lsm6dso_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
10116 lsm6dso_sh_cfg_read_t *val)
10117 {
10118 lsm6dso_slv0_add_t slv0_add;
10119 lsm6dso_slv0_config_t slv0_config;
10120 int32_t ret;
10121
10122 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
10123
10124 if (ret == 0)
10125 {
10126 slv0_add.slave0 = val->slv_add;
10127 slv0_add.rw_0 = 1;
10128 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_ADD, (uint8_t *)&slv0_add, 1);
10129 }
10130
10131 if (ret == 0)
10132 {
10133 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_SUBADD,
10134 &(val->slv_subadd), 1);
10135 }
10136
10137 if (ret == 0)
10138 {
10139 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV0_CONFIG,
10140 (uint8_t *)&slv0_config, 1);
10141 }
10142
10143 if (ret == 0)
10144 {
10145 slv0_config.slave0_numop = val->slv_len;
10146 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV0_CONFIG,
10147 (uint8_t *)&slv0_config, 1);
10148 }
10149
10150 if (ret == 0)
10151 {
10152 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
10153 }
10154
10155 return ret;
10156 }
10157
10158 /**
10159 * @brief Configure slave 0 for perform a write/read.[set]
10160 *
10161 * @param ctx read / write interface definitions
10162 * @param val Structure that contain
10163 * - uint8_t slv1_add; 8 bit i2c device address
10164 * - uint8_t slv1_subadd; 8 bit register device address
10165 * - uint8_t slv1_len; num of bit to read
10166 * @retval interface status (MANDATORY: return 0 -> no Error)
10167 *
10168 */
lsm6dso_sh_slv1_cfg_read(stmdev_ctx_t * ctx,lsm6dso_sh_cfg_read_t * val)10169 int32_t lsm6dso_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
10170 lsm6dso_sh_cfg_read_t *val)
10171 {
10172 lsm6dso_slv1_add_t slv1_add;
10173 lsm6dso_slv1_config_t slv1_config;
10174 int32_t ret;
10175
10176 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
10177
10178 if (ret == 0)
10179 {
10180 slv1_add.slave1_add = val->slv_add;
10181 slv1_add.r_1 = 1;
10182 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_ADD, (uint8_t *)&slv1_add, 1);
10183 }
10184
10185 if (ret == 0)
10186 {
10187 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_SUBADD,
10188 &(val->slv_subadd), 1);
10189 }
10190
10191 if (ret == 0)
10192 {
10193 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV1_CONFIG,
10194 (uint8_t *)&slv1_config, 1);
10195 }
10196
10197 if (ret == 0)
10198 {
10199 slv1_config.slave1_numop = val->slv_len;
10200 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV1_CONFIG,
10201 (uint8_t *)&slv1_config, 1);
10202 }
10203
10204 if (ret == 0)
10205 {
10206 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
10207 }
10208
10209 return ret;
10210 }
10211
10212 /**
10213 * @brief Configure slave 0 for perform a write/read.[set]
10214 *
10215 * @param ctx read / write interface definitions
10216 * @param val Structure that contain
10217 * - uint8_t slv2_add; 8 bit i2c device address
10218 * - uint8_t slv2_subadd; 8 bit register device address
10219 * - uint8_t slv2_len; num of bit to read
10220 * @retval interface status (MANDATORY: return 0 -> no Error)
10221 *
10222 */
lsm6dso_sh_slv2_cfg_read(stmdev_ctx_t * ctx,lsm6dso_sh_cfg_read_t * val)10223 int32_t lsm6dso_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
10224 lsm6dso_sh_cfg_read_t *val)
10225 {
10226 lsm6dso_slv2_add_t slv2_add;
10227 lsm6dso_slv2_config_t slv2_config;
10228 int32_t ret;
10229
10230 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
10231
10232 if (ret == 0)
10233 {
10234 slv2_add.slave2_add = val->slv_add;
10235 slv2_add.r_2 = 1;
10236 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_ADD, (uint8_t *)&slv2_add, 1);
10237 }
10238
10239 if (ret == 0)
10240 {
10241 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_SUBADD,
10242 &(val->slv_subadd), 1);
10243 }
10244
10245 if (ret == 0)
10246 {
10247 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV2_CONFIG,
10248 (uint8_t *)&slv2_config, 1);
10249 }
10250
10251 if (ret == 0)
10252 {
10253 slv2_config.slave2_numop = val->slv_len;
10254 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV2_CONFIG,
10255 (uint8_t *)&slv2_config, 1);
10256 }
10257
10258 if (ret == 0)
10259 {
10260 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
10261 }
10262
10263 return ret;
10264 }
10265
10266 /**
10267 * @brief Configure slave 0 for perform a write/read.[set]
10268 *
10269 * @param ctx read / write interface definitions
10270 * @param val Structure that contain
10271 * - uint8_t slv3_add; 8 bit i2c device address
10272 * - uint8_t slv3_subadd; 8 bit register device address
10273 * - uint8_t slv3_len; num of bit to read
10274 * @retval interface status (MANDATORY: return 0 -> no Error)
10275 *
10276 */
lsm6dso_sh_slv3_cfg_read(stmdev_ctx_t * ctx,lsm6dso_sh_cfg_read_t * val)10277 int32_t lsm6dso_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
10278 lsm6dso_sh_cfg_read_t *val)
10279 {
10280 lsm6dso_slv3_add_t slv3_add;
10281 lsm6dso_slv3_config_t slv3_config;
10282 int32_t ret;
10283
10284 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
10285
10286 if (ret == 0)
10287 {
10288 slv3_add.slave3_add = val->slv_add;
10289 slv3_add.r_3 = 1;
10290 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_ADD, (uint8_t *)&slv3_add, 1);
10291 }
10292
10293 if (ret == 0)
10294 {
10295 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_SUBADD,
10296 &(val->slv_subadd), 1);
10297 }
10298
10299 if (ret == 0)
10300 {
10301 ret = lsm6dso_read_reg(ctx, LSM6DSO_SLV3_CONFIG,
10302 (uint8_t *)&slv3_config, 1);
10303 }
10304
10305 if (ret == 0)
10306 {
10307 slv3_config.slave3_numop = val->slv_len;
10308 ret = lsm6dso_write_reg(ctx, LSM6DSO_SLV3_CONFIG,
10309 (uint8_t *)&slv3_config, 1);
10310 }
10311
10312 if (ret == 0)
10313 {
10314 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
10315 }
10316
10317 return ret;
10318 }
10319
10320 /**
10321 * @brief Sensor hub source register.[get]
10322 *
10323 * @param ctx read / write interface definitions
10324 * @param val union of registers from STATUS_MASTER to
10325 * @retval interface status (MANDATORY: return 0 -> no Error)
10326 *
10327 */
lsm6dso_sh_status_get(stmdev_ctx_t * ctx,lsm6dso_status_master_t * val)10328 int32_t lsm6dso_sh_status_get(stmdev_ctx_t *ctx,
10329 lsm6dso_status_master_t *val)
10330 {
10331 int32_t ret;
10332
10333 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_SENSOR_HUB_BANK);
10334
10335 if (ret == 0)
10336 {
10337 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_MASTER, (uint8_t *) val, 1);
10338 }
10339
10340 if (ret == 0)
10341 {
10342 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
10343 }
10344
10345 return ret;
10346 }
10347
10348 /**
10349 * @}
10350 *
10351 */
10352
10353 /**
10354 * @defgroup Basic configuration
10355 * @brief This section groups all the functions concerning
10356 * device basic configuration.
10357 * @{
10358 *
10359 */
10360
10361 /**
10362 * @brief Device "Who am I".[get]
10363 *
10364 * @param ctx communication interface handler. Use NULL to ignore
10365 * this interface.(ptr)
10366 * @param aux_ctx auxiliary communication interface handler. Use NULL
10367 * to ignore this interface.(ptr)
10368 * @param val ID values read from the two interfaces. ID values
10369 * will be the same.(ptr)
10370 * @retval interface status (MANDATORY: return 0 -> no Error)
10371 *
10372 */
lsm6dso_id_get(stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dso_id_t * val)10373 int32_t lsm6dso_id_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
10374 lsm6dso_id_t *val)
10375 {
10376 int32_t ret = 0;
10377
10378 if (ctx != NULL)
10379 {
10380 ret = lsm6dso_read_reg(ctx, LSM6DSO_WHO_AM_I,
10381 (uint8_t *) & (val->ui), 1);
10382 }
10383
10384 if (aux_ctx != NULL)
10385 {
10386 if (ret == 0)
10387 {
10388 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_WHO_AM_I,
10389 (uint8_t *) & (val->aux), 1);
10390 }
10391 }
10392
10393 return ret;
10394 }
10395
10396 /**
10397 * @brief Re-initialize the device.[set]
10398 *
10399 * @param ctx communication interface handler.(ptr)
10400 * @param val re-initialization mode. Refer to datasheet
10401 * and application note for more information
10402 * about differencies between boot and sw_reset
10403 * procedure.
10404 * @retval interface status (MANDATORY: return 0 -> no Error)
10405 *
10406 */
lsm6dso_init_set(stmdev_ctx_t * ctx,lsm6dso_init_t val)10407 int32_t lsm6dso_init_set(stmdev_ctx_t *ctx, lsm6dso_init_t val)
10408 {
10409 lsm6dso_emb_func_init_a_t emb_func_init_a;
10410 lsm6dso_emb_func_init_b_t emb_func_init_b;
10411 lsm6dso_ctrl3_c_t ctrl3_c;
10412 int32_t ret;
10413
10414 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
10415
10416 if (ret == 0)
10417 {
10418 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B,
10419 (uint8_t *)&emb_func_init_b, 1);
10420 }
10421
10422 if (ret == 0)
10423 {
10424 emb_func_init_b.fifo_compr_init = (uint8_t)val
10425 & ((uint8_t)LSM6DSO_FIFO_COMP >> 2);
10426 emb_func_init_b.fsm_init = (uint8_t)val
10427 & ((uint8_t)LSM6DSO_FSM >> 3);
10428 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_B,
10429 (uint8_t *)&emb_func_init_b, 1);
10430 }
10431
10432 if (ret == 0)
10433 {
10434 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INIT_A,
10435 (uint8_t *)&emb_func_init_a, 1);
10436 }
10437
10438 if (ret == 0)
10439 {
10440 emb_func_init_a.step_det_init = ((uint8_t)val
10441 & (uint8_t)LSM6DSO_PEDO) >> 5;
10442 emb_func_init_a.tilt_init = ((uint8_t)val
10443 & (uint8_t)LSM6DSO_TILT) >> 6;
10444 emb_func_init_a.sig_mot_init = ((uint8_t)val
10445 & (uint8_t)LSM6DSO_SMOTION) >> 7;
10446 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INIT_A,
10447 (uint8_t *)&emb_func_init_a, 1);
10448 }
10449
10450 if (ret == 0)
10451 {
10452 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
10453 }
10454
10455 if (ret == 0)
10456 {
10457 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
10458 }
10459
10460 if (((val == LSM6DSO_BOOT) || (val == LSM6DSO_RESET)) &&
10461 (ret == 0))
10462 {
10463 ctrl3_c.boot = (uint8_t)val & (uint8_t)LSM6DSO_BOOT;
10464 ctrl3_c.sw_reset = ((uint8_t)val & (uint8_t)LSM6DSO_RESET) >> 1;
10465 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
10466 }
10467
10468 if ((val == LSM6DSO_DRV_RDY)
10469 && ((ctrl3_c.bdu == PROPERTY_DISABLE)
10470 || (ctrl3_c.if_inc == PROPERTY_DISABLE)) && (ret == 0))
10471 {
10472 ctrl3_c.bdu = PROPERTY_ENABLE;
10473 ctrl3_c.if_inc = PROPERTY_ENABLE;
10474 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
10475 }
10476
10477 return ret;
10478 }
10479
10480 /**
10481 * @brief Configures the bus operating mode.[set]
10482 *
10483 * @param ctx communication interface handler. Use NULL to ignore
10484 * this interface.(ptr)
10485 * @param aux_ctx auxiliary communication interface handler. Use NULL
10486 * to ignore this interface.(ptr)
10487 * @param val configures the bus operating mode for both the
10488 * main and the auxiliary interface.
10489 * @retval interface status (MANDATORY: return 0 -> no Error)
10490 *
10491 */
lsm6dso_bus_mode_set(stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dso_bus_mode_t val)10492 int32_t lsm6dso_bus_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
10493 lsm6dso_bus_mode_t val)
10494 {
10495 lsm6dso_ctrl1_ois_t ctrl1_ois;
10496 lsm6dso_i3c_bus_avb_t i3c_bus_avb;
10497 lsm6dso_ctrl9_xl_t ctrl9_xl;
10498 lsm6dso_ctrl3_c_t ctrl3_c;
10499 lsm6dso_ctrl4_c_t ctrl4_c;
10500 uint8_t bit_val;
10501 int32_t ret;
10502
10503 ret = 0;
10504
10505 if (aux_ctx != NULL)
10506 {
10507 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS,
10508 (uint8_t *)&ctrl1_ois, 1);
10509 bit_val = ((uint8_t)val.aux_bus_md & 0x04U) >> 2;
10510
10511 if ((ret == 0) && (ctrl1_ois.sim_ois != bit_val))
10512 {
10513 ctrl1_ois.sim_ois = bit_val;
10514 ret = lsm6dso_write_reg(aux_ctx, LSM6DSO_CTRL1_OIS,
10515 (uint8_t *)&ctrl1_ois, 1);
10516 }
10517 }
10518
10519 if (ctx != NULL)
10520 {
10521 if (ret == 0)
10522 {
10523 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL,
10524 (uint8_t *)&ctrl9_xl, 1);
10525 }
10526
10527 bit_val = ((uint8_t)val.ui_bus_md & 0x04U) >> 2;
10528
10529 if ((ret == 0) && (ctrl9_xl.i3c_disable != bit_val))
10530 {
10531 ctrl9_xl.i3c_disable = bit_val;
10532 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL9_XL,
10533 (uint8_t *)&ctrl9_xl, 1);
10534 }
10535
10536 if (ret == 0)
10537 {
10538 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
10539 (uint8_t *)&i3c_bus_avb, 1);
10540 }
10541
10542 bit_val = ((uint8_t)val.ui_bus_md & 0x30U) >> 4;
10543
10544 if ((ret == 0) && (i3c_bus_avb.i3c_bus_avb_sel != bit_val))
10545 {
10546 i3c_bus_avb.i3c_bus_avb_sel = bit_val;
10547 ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB,
10548 (uint8_t *)&i3c_bus_avb, 1);
10549 }
10550
10551 if (ret == 0)
10552 {
10553 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C,
10554 (uint8_t *)&ctrl4_c, 1);
10555 }
10556
10557 bit_val = ((uint8_t)val.ui_bus_md & 0x02U) >> 1;
10558
10559 if ((ret == 0) && (ctrl4_c.i2c_disable != bit_val))
10560 {
10561 ctrl4_c.i2c_disable = bit_val;
10562 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C,
10563 (uint8_t *)&ctrl4_c, 1);
10564 }
10565
10566 if (ret == 0)
10567 {
10568 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C,
10569 (uint8_t *)&ctrl3_c, 1);
10570 }
10571
10572 bit_val = (uint8_t)val.ui_bus_md & 0x01U;
10573
10574 if ((ret == 0) && (ctrl3_c.sim != bit_val))
10575 {
10576 ctrl3_c.sim = bit_val;
10577 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C,
10578 (uint8_t *)&ctrl3_c, 1);
10579 }
10580 }
10581
10582 return ret;
10583 }
10584
10585 /**
10586 * @brief Get the bus operating mode.[get]
10587 *
10588 * @param ctx communication interface handler. Use NULL to ignore
10589 * this interface.(ptr)
10590 * @param aux_ctx auxiliary communication interface handler. Use NULL
10591 * to ignore this interface.(ptr)
10592 * @param val retrieves the bus operating mode for both the main
10593 * and the auxiliary interface.(ptr)
10594 * @retval interface status (MANDATORY: return 0 -> no Error)
10595 *
10596 */
lsm6dso_bus_mode_get(stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dso_bus_mode_t * val)10597 int32_t lsm6dso_bus_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
10598 lsm6dso_bus_mode_t *val)
10599 {
10600 lsm6dso_ctrl1_ois_t ctrl1_ois;
10601 lsm6dso_i3c_bus_avb_t i3c_bus_avb;
10602 lsm6dso_ctrl9_xl_t ctrl9_xl;
10603 lsm6dso_ctrl3_c_t ctrl3_c;
10604 lsm6dso_ctrl4_c_t ctrl4_c;
10605 int32_t ret = 0;
10606
10607 if (aux_ctx != NULL)
10608 {
10609 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS,
10610 (uint8_t *)&ctrl1_ois, 1);
10611
10612 switch (ctrl1_ois.sim_ois)
10613 {
10614 case LSM6DSO_SPI_4W_AUX:
10615 val->aux_bus_md = LSM6DSO_SPI_4W_AUX;
10616 break;
10617
10618 case LSM6DSO_SPI_3W_AUX:
10619 val->aux_bus_md = LSM6DSO_SPI_3W_AUX;
10620 break;
10621
10622 default:
10623 val->aux_bus_md = LSM6DSO_SPI_4W_AUX;
10624 break;
10625 }
10626 }
10627
10628 if (ctx != NULL)
10629 {
10630 if (ret == 0)
10631 {
10632 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL9_XL,
10633 (uint8_t *)&ctrl9_xl, 1);
10634 }
10635
10636 if (ret == 0)
10637 {
10638 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
10639 (uint8_t *)&i3c_bus_avb, 1);
10640 }
10641
10642 if (ret == 0)
10643 {
10644 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C,
10645 (uint8_t *)&ctrl4_c, 1);
10646 }
10647
10648 if (ret == 0)
10649 {
10650 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C,
10651 (uint8_t *)&ctrl3_c, 1);
10652
10653 switch ((i3c_bus_avb.i3c_bus_avb_sel << 4) &
10654 (ctrl9_xl.i3c_disable << 2) &
10655 (ctrl4_c.i2c_disable << 1) & ctrl3_c.sim)
10656 {
10657 case LSM6DSO_SEL_BY_HW:
10658 val->ui_bus_md = LSM6DSO_SEL_BY_HW;
10659 break;
10660
10661 case LSM6DSO_SPI_4W:
10662 val->ui_bus_md = LSM6DSO_SPI_4W;
10663 break;
10664
10665 case LSM6DSO_SPI_3W:
10666 val->ui_bus_md = LSM6DSO_SPI_3W;
10667 break;
10668
10669 case LSM6DSO_I2C:
10670 val->ui_bus_md = LSM6DSO_I2C;
10671 break;
10672
10673 case LSM6DSO_I3C_T_50us:
10674 val->ui_bus_md = LSM6DSO_I3C_T_50us;
10675 break;
10676
10677 case LSM6DSO_I3C_T_2us:
10678 val->ui_bus_md = LSM6DSO_I3C_T_2us;
10679 break;
10680
10681 case LSM6DSO_I3C_T_1ms:
10682 val->ui_bus_md = LSM6DSO_I3C_T_1ms;
10683 break;
10684
10685 case LSM6DSO_I3C_T_25ms:
10686 val->ui_bus_md = LSM6DSO_I3C_T_25ms;
10687 break;
10688
10689 default:
10690 val->ui_bus_md = LSM6DSO_SEL_BY_HW;
10691 break;
10692 }
10693 }
10694 }
10695
10696 return ret;
10697 }
10698
10699 /**
10700 * @brief Get the status of the device.[get]
10701 *
10702 * @param ctx communication interface handler. Use NULL to ignore
10703 * this interface.(ptr)
10704 * @param aux_ctx auxiliary communication interface handler. Use NULL
10705 * to ignore this interface.(ptr)
10706 * @param val the status of the device.(ptr)
10707 * @retval interface status (MANDATORY: return 0 -> no Error)
10708 *
10709 */
lsm6dso_status_get(stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dso_status_t * val)10710 int32_t lsm6dso_status_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
10711 lsm6dso_status_t *val)
10712 {
10713 lsm6dso_status_spiaux_t status_spiaux;
10714 lsm6dso_status_reg_t status_reg;
10715 lsm6dso_ctrl3_c_t ctrl3_c;
10716 int32_t ret;
10717 ret = 0;
10718
10719 if (aux_ctx != NULL)
10720 {
10721 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_STATUS_SPIAUX,
10722 (uint8_t *)&status_spiaux, 1);
10723 val->ois_drdy_xl = status_spiaux.xlda;
10724 val->ois_drdy_g = status_spiaux.gda;
10725 val->ois_gyro_settling = status_spiaux.gyro_settling;
10726 }
10727
10728 if (ctx != NULL)
10729 {
10730 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
10731 val->sw_reset = ctrl3_c.sw_reset;
10732 val->boot = ctrl3_c.boot;
10733
10734 if ((ret == 0) && (ctrl3_c.sw_reset == PROPERTY_DISABLE) &&
10735 (ctrl3_c.boot == PROPERTY_DISABLE))
10736 {
10737 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_REG,
10738 (uint8_t *)&status_reg, 1);
10739 val->drdy_xl = status_reg.xlda;
10740 val->drdy_g = status_reg.gda;
10741 val->drdy_temp = status_reg.tda;
10742 }
10743 }
10744
10745 return ret;
10746 }
10747
10748 /**
10749 * @brief Electrical pin configuration.[set]
10750 *
10751 * @param ctx communication interface handler.(ptr)
10752 * @param val the electrical settings for the configurable
10753 * pins.
10754 * @retval interface status (MANDATORY: return 0 -> no Error)
10755 *
10756 */
lsm6dso_pin_conf_set(stmdev_ctx_t * ctx,lsm6dso_pin_conf_t val)10757 int32_t lsm6dso_pin_conf_set(stmdev_ctx_t *ctx,
10758 lsm6dso_pin_conf_t val)
10759 {
10760 lsm6dso_i3c_bus_avb_t i3c_bus_avb;
10761 lsm6dso_pin_ctrl_t pin_ctrl;
10762 lsm6dso_ctrl3_c_t ctrl3_c;
10763 int32_t ret;
10764
10765 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
10766
10767 if (ret == 0)
10768 {
10769 pin_ctrl.ois_pu_dis = ~val.aux_sdo_ocs_pull_up;
10770 pin_ctrl.sdo_pu_en = val.sdo_sa0_pull_up;
10771 ret = lsm6dso_write_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
10772 }
10773
10774 if (ret == 0)
10775 {
10776 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
10777 }
10778
10779 if (ret == 0)
10780 {
10781 ctrl3_c.pp_od = ~val.int1_int2_push_pull;
10782 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
10783 }
10784
10785 if (ret == 0)
10786 {
10787 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
10788 (uint8_t *)&i3c_bus_avb, 1);
10789 }
10790
10791 if (ret == 0)
10792 {
10793 i3c_bus_avb.pd_dis_int1 = ~val.int1_pull_down;
10794 ret = lsm6dso_write_reg(ctx, LSM6DSO_I3C_BUS_AVB,
10795 (uint8_t *)&i3c_bus_avb, 1);
10796 }
10797
10798 return ret;
10799 }
10800
10801 /**
10802 * @brief Electrical pin configuration.[get]
10803 *
10804 * @param ctx communication interface handler.(ptr)
10805 * @param val the electrical settings for the configurable
10806 * pins.(ptr)
10807 * @retval interface status (MANDATORY: return 0 -> no Error)
10808 *
10809 */
lsm6dso_pin_conf_get(stmdev_ctx_t * ctx,lsm6dso_pin_conf_t * val)10810 int32_t lsm6dso_pin_conf_get(stmdev_ctx_t *ctx,
10811 lsm6dso_pin_conf_t *val)
10812 {
10813 lsm6dso_i3c_bus_avb_t i3c_bus_avb;
10814 lsm6dso_pin_ctrl_t pin_ctrl;
10815 lsm6dso_ctrl3_c_t ctrl3_c;
10816 int32_t ret;
10817
10818 ret = lsm6dso_read_reg(ctx, LSM6DSO_PIN_CTRL, (uint8_t *)&pin_ctrl, 1);
10819
10820 if (ret == 0)
10821 {
10822 val->aux_sdo_ocs_pull_up = ~pin_ctrl.ois_pu_dis;
10823 val->aux_sdo_ocs_pull_up = pin_ctrl.sdo_pu_en;
10824 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
10825 }
10826
10827 if (ret == 0)
10828 {
10829 val->int1_int2_push_pull = ~ctrl3_c.pp_od;
10830 ret = lsm6dso_read_reg(ctx, LSM6DSO_I3C_BUS_AVB,
10831 (uint8_t *)&i3c_bus_avb, 1);
10832 }
10833
10834 if (ret == 0)
10835 {
10836 val->int1_pull_down = ~i3c_bus_avb.pd_dis_int1;
10837 }
10838
10839 return ret;
10840 }
10841
10842 /**
10843 * @brief Interrupt pins hardware signal configuration.[set]
10844 *
10845 * @param ctx communication interface handler.(ptr)
10846 * @param val the pins hardware signal settings.
10847 * @retval interface status (MANDATORY: return 0 -> no Error)
10848 *
10849 */
lsm6dso_interrupt_mode_set(stmdev_ctx_t * ctx,lsm6dso_int_mode_t val)10850 int32_t lsm6dso_interrupt_mode_set(stmdev_ctx_t *ctx,
10851 lsm6dso_int_mode_t val)
10852 {
10853 lsm6dso_tap_cfg0_t tap_cfg0;
10854 lsm6dso_page_rw_t page_rw;
10855 lsm6dso_ctrl3_c_t ctrl3_c;
10856 int32_t ret;
10857
10858 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
10859
10860 if (ret == 0)
10861 {
10862 ctrl3_c.h_lactive = val.active_low;
10863 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
10864 }
10865
10866 if (ret == 0)
10867 {
10868 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
10869 }
10870
10871 if (ret == 0)
10872 {
10873 tap_cfg0.lir = val.base_latched;
10874 tap_cfg0.int_clr_on_read = val.base_latched | val.emb_latched;
10875 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
10876 }
10877
10878 if (ret == 0)
10879 {
10880 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
10881 }
10882
10883 if (ret == 0)
10884 {
10885 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
10886 }
10887
10888 if (ret == 0)
10889 {
10890 page_rw.emb_func_lir = val.emb_latched;
10891 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
10892 }
10893
10894 if (ret == 0)
10895 {
10896 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
10897 }
10898
10899 return ret;
10900 }
10901
10902 /**
10903 * @brief Interrupt pins hardware signal configuration.[get]
10904 *
10905 * @param ctx communication interface handler.(ptr)
10906 * @param val the pins hardware signal settings.(ptr)
10907 * @retval interface status (MANDATORY: return 0 -> no Error)
10908 *
10909 */
lsm6dso_interrupt_mode_get(stmdev_ctx_t * ctx,lsm6dso_int_mode_t * val)10910 int32_t lsm6dso_interrupt_mode_get(stmdev_ctx_t *ctx,
10911 lsm6dso_int_mode_t *val)
10912 {
10913 lsm6dso_tap_cfg0_t tap_cfg0;
10914 lsm6dso_page_rw_t page_rw;
10915 lsm6dso_ctrl3_c_t ctrl3_c;
10916 int32_t ret;
10917
10918 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
10919
10920 if (ret == 0)
10921 {
10922 ctrl3_c.h_lactive = val->active_low;
10923 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG0, (uint8_t *) &tap_cfg0, 1);
10924 }
10925
10926 if (ret == 0)
10927 {
10928 tap_cfg0.lir = val->base_latched;
10929 tap_cfg0.int_clr_on_read = val->base_latched | val->emb_latched;
10930 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
10931 }
10932
10933 if (ret == 0)
10934 {
10935 ret = lsm6dso_read_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
10936 }
10937
10938 if (ret == 0)
10939 {
10940 page_rw.emb_func_lir = val->emb_latched;
10941 ret = lsm6dso_write_reg(ctx, LSM6DSO_PAGE_RW, (uint8_t *) &page_rw, 1);
10942 }
10943
10944 if (ret == 0)
10945 {
10946 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
10947 }
10948
10949 return ret;
10950 }
10951
10952 /**
10953 * @brief Route interrupt signals on int1 pin.[set]
10954 *
10955 * @param ctx communication interface handler.(ptr)
10956 * @param val the signals to route on int1 pin.
10957 * @retval interface status (MANDATORY: return 0 -> no Error)
10958 *
10959 */
lsm6dso_pin_int1_route_set(stmdev_ctx_t * ctx,lsm6dso_pin_int1_route_t val)10960 int32_t lsm6dso_pin_int1_route_set(stmdev_ctx_t *ctx,
10961 lsm6dso_pin_int1_route_t val)
10962 {
10963 lsm6dso_pin_int2_route_t pin_int2_route;
10964 lsm6dso_emb_func_int1_t emb_func_int1;
10965 lsm6dso_fsm_int1_a_t fsm_int1_a;
10966 lsm6dso_fsm_int1_b_t fsm_int1_b;
10967 lsm6dso_int1_ctrl_t int1_ctrl;
10968 lsm6dso_int2_ctrl_t int2_ctrl;
10969 lsm6dso_tap_cfg2_t tap_cfg2;
10970 lsm6dso_md2_cfg_t md2_cfg;
10971 lsm6dso_md1_cfg_t md1_cfg;
10972 lsm6dso_ctrl4_c_t ctrl4_c;
10973 int32_t ret;
10974 int1_ctrl.int1_drdy_xl = val.drdy_xl;
10975 int1_ctrl.int1_drdy_g = val.drdy_g;
10976 int1_ctrl.int1_boot = val.boot;
10977 int1_ctrl.int1_fifo_th = val.fifo_th;
10978 int1_ctrl.int1_fifo_ovr = val.fifo_ovr;
10979 int1_ctrl.int1_fifo_full = val.fifo_full;
10980 int1_ctrl.int1_cnt_bdr = val.fifo_bdr;
10981 int1_ctrl.den_drdy_flag = val.den_flag;
10982 md1_cfg.int1_shub = val.sh_endop;
10983 md1_cfg.int1_6d = val.six_d;
10984 md1_cfg.int1_double_tap = val.double_tap;
10985 md1_cfg.int1_ff = val.free_fall;
10986 md1_cfg.int1_wu = val.wake_up;
10987 md1_cfg.int1_single_tap = val.single_tap;
10988 md1_cfg.int1_sleep_change = val.sleep_change;
10989 emb_func_int1.not_used_01 = 0;
10990 emb_func_int1.int1_step_detector = val.step_detector;
10991 emb_func_int1.int1_tilt = val.tilt;
10992 emb_func_int1.int1_sig_mot = val.sig_mot;
10993 emb_func_int1.not_used_02 = 0;
10994 emb_func_int1.int1_fsm_lc = val.fsm_lc;
10995 fsm_int1_a.int1_fsm1 = val.fsm1;
10996 fsm_int1_a.int1_fsm2 = val.fsm2;
10997 fsm_int1_a.int1_fsm3 = val.fsm3;
10998 fsm_int1_a.int1_fsm4 = val.fsm4;
10999 fsm_int1_a.int1_fsm5 = val.fsm5;
11000 fsm_int1_a.int1_fsm6 = val.fsm6;
11001 fsm_int1_a.int1_fsm7 = val.fsm7;
11002 fsm_int1_a.int1_fsm8 = val.fsm8;
11003 fsm_int1_b.int1_fsm9 = val.fsm9 ;
11004 fsm_int1_b.int1_fsm10 = val.fsm10;
11005 fsm_int1_b.int1_fsm11 = val.fsm11;
11006 fsm_int1_b.int1_fsm12 = val.fsm12;
11007 fsm_int1_b.int1_fsm13 = val.fsm13;
11008 fsm_int1_b.int1_fsm14 = val.fsm14;
11009 fsm_int1_b.int1_fsm15 = val.fsm15;
11010 fsm_int1_b.int1_fsm16 = val.fsm16;
11011 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
11012
11013 if (ret == 0)
11014 {
11015 if ((val.drdy_temp | val.timestamp) != PROPERTY_DISABLE)
11016 {
11017 ctrl4_c.int2_on_int1 = PROPERTY_ENABLE;
11018 }
11019
11020 else
11021 {
11022 ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
11023 }
11024
11025 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
11026 }
11027
11028 if (ret == 0)
11029 {
11030 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
11031 }
11032
11033 if (ret == 0)
11034 {
11035 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INT1,
11036 (uint8_t *)&emb_func_int1, 1);
11037 }
11038
11039 if (ret == 0)
11040 {
11041 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT1_A,
11042 (uint8_t *)&fsm_int1_a, 1);
11043 }
11044
11045 if (ret == 0)
11046 {
11047 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT1_B,
11048 (uint8_t *)&fsm_int1_b, 1);
11049 }
11050
11051 if (ret == 0)
11052 {
11053 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
11054 }
11055
11056 if (ret == 0)
11057 {
11058 if ((emb_func_int1.int1_fsm_lc
11059 | emb_func_int1.int1_sig_mot
11060 | emb_func_int1.int1_step_detector
11061 | emb_func_int1.int1_tilt
11062 | fsm_int1_a.int1_fsm1
11063 | fsm_int1_a.int1_fsm2
11064 | fsm_int1_a.int1_fsm3
11065 | fsm_int1_a.int1_fsm4
11066 | fsm_int1_a.int1_fsm5
11067 | fsm_int1_a.int1_fsm6
11068 | fsm_int1_a.int1_fsm7
11069 | fsm_int1_a.int1_fsm8
11070 | fsm_int1_b.int1_fsm9
11071 | fsm_int1_b.int1_fsm10
11072 | fsm_int1_b.int1_fsm11
11073 | fsm_int1_b.int1_fsm12
11074 | fsm_int1_b.int1_fsm13
11075 | fsm_int1_b.int1_fsm14
11076 | fsm_int1_b.int1_fsm15
11077 | fsm_int1_b.int1_fsm16) != PROPERTY_DISABLE)
11078 {
11079 md1_cfg.int1_emb_func = PROPERTY_ENABLE;
11080 }
11081
11082 else
11083 {
11084 md1_cfg.int1_emb_func = PROPERTY_DISABLE;
11085 }
11086
11087 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT1_CTRL,
11088 (uint8_t *)&int1_ctrl, 1);
11089 }
11090
11091 if (ret == 0)
11092 {
11093 ret = lsm6dso_write_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t *)&md1_cfg, 1);
11094 }
11095
11096 if (ret == 0)
11097 {
11098 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
11099 }
11100
11101 if (ret == 0)
11102 {
11103 int2_ctrl.int2_drdy_temp = val.drdy_temp;
11104 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
11105 }
11106
11107 if (ret == 0)
11108 {
11109 ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
11110 }
11111
11112 if (ret == 0)
11113 {
11114 md2_cfg.int2_timestamp = val.timestamp;
11115 ret = lsm6dso_write_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
11116 }
11117
11118 if (ret == 0)
11119 {
11120 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
11121 }
11122
11123 if (ret == 0)
11124 {
11125 ret = lsm6dso_pin_int2_route_get(ctx, NULL, &pin_int2_route);
11126 }
11127
11128 if (ret == 0)
11129 {
11130 if ((pin_int2_route.fifo_bdr
11131 | pin_int2_route.drdy_g
11132 | pin_int2_route.drdy_temp
11133 | pin_int2_route.drdy_xl
11134 | pin_int2_route.fifo_full
11135 | pin_int2_route.fifo_ovr
11136 | pin_int2_route.fifo_th
11137 | pin_int2_route.six_d
11138 | pin_int2_route.double_tap
11139 | pin_int2_route.free_fall
11140 | pin_int2_route.wake_up
11141 | pin_int2_route.single_tap
11142 | pin_int2_route.sleep_change
11143 | int1_ctrl.den_drdy_flag
11144 | int1_ctrl.int1_boot
11145 | int1_ctrl.int1_cnt_bdr
11146 | int1_ctrl.int1_drdy_g
11147 | int1_ctrl.int1_drdy_xl
11148 | int1_ctrl.int1_fifo_full
11149 | int1_ctrl.int1_fifo_ovr
11150 | int1_ctrl.int1_fifo_th
11151 | md1_cfg.int1_shub
11152 | md1_cfg.int1_6d
11153 | md1_cfg.int1_double_tap
11154 | md1_cfg.int1_ff
11155 | md1_cfg.int1_wu
11156 | md1_cfg.int1_single_tap
11157 | md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
11158 {
11159 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
11160 }
11161
11162 else
11163 {
11164 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
11165 }
11166
11167 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
11168 }
11169
11170 return ret;
11171 }
11172
11173 /**
11174 * @brief Route interrupt signals on int1 pin.[get]
11175 *
11176 * @param ctx communication interface handler.(ptr)
11177 * @param val the signals that are routed on int1 pin.(ptr)
11178 * @retval interface status (MANDATORY: return 0 -> no Error)
11179 *
11180 */
lsm6dso_pin_int1_route_get(stmdev_ctx_t * ctx,lsm6dso_pin_int1_route_t * val)11181 int32_t lsm6dso_pin_int1_route_get(stmdev_ctx_t *ctx,
11182 lsm6dso_pin_int1_route_t *val)
11183 {
11184 lsm6dso_emb_func_int1_t emb_func_int1;
11185 lsm6dso_fsm_int1_a_t fsm_int1_a;
11186 lsm6dso_fsm_int1_b_t fsm_int1_b;
11187 lsm6dso_int1_ctrl_t int1_ctrl;
11188 lsm6dso_int2_ctrl_t int2_ctrl;
11189 lsm6dso_md2_cfg_t md2_cfg;
11190 lsm6dso_md1_cfg_t md1_cfg;
11191 lsm6dso_ctrl4_c_t ctrl4_c;
11192 int32_t ret;
11193 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
11194
11195 if (ret == 0)
11196 {
11197 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INT1,
11198 (uint8_t *)&emb_func_int1, 1);
11199 }
11200
11201 if (ret == 0)
11202 {
11203 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT1_A,
11204 (uint8_t *)&fsm_int1_a, 1);
11205 }
11206
11207 if (ret == 0)
11208 {
11209 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT1_B,
11210 (uint8_t *)&fsm_int1_b, 1);
11211 }
11212
11213 if (ret == 0)
11214 {
11215 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
11216 }
11217
11218 if (ret == 0)
11219 {
11220 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT1_CTRL,
11221 (uint8_t *)&int1_ctrl, 1);
11222 }
11223
11224 if (ret == 0)
11225 {
11226 ret = lsm6dso_read_reg(ctx, LSM6DSO_MD1_CFG, (uint8_t *)&md1_cfg, 1);
11227 }
11228
11229 if (ret == 0)
11230 {
11231 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
11232 }
11233
11234 if (ctrl4_c.int2_on_int1 == PROPERTY_ENABLE)
11235 {
11236 if (ret == 0)
11237 {
11238 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
11239 val->drdy_temp = int2_ctrl.int2_drdy_temp;
11240 }
11241
11242 if (ret == 0)
11243 {
11244 ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
11245 val->timestamp = md2_cfg.int2_timestamp;
11246 }
11247 }
11248
11249 else
11250 {
11251 val->drdy_temp = PROPERTY_DISABLE;
11252 val->timestamp = PROPERTY_DISABLE;
11253 }
11254
11255 val->drdy_xl = int1_ctrl.int1_drdy_xl;
11256 val->drdy_g = int1_ctrl.int1_drdy_g;
11257 val->boot = int1_ctrl.int1_boot;
11258 val->fifo_th = int1_ctrl.int1_fifo_th;
11259 val->fifo_ovr = int1_ctrl.int1_fifo_ovr;
11260 val->fifo_full = int1_ctrl.int1_fifo_full;
11261 val->fifo_bdr = int1_ctrl.int1_cnt_bdr;
11262 val->den_flag = int1_ctrl.den_drdy_flag;
11263 val->sh_endop = md1_cfg.int1_shub;
11264 val->six_d = md1_cfg.int1_6d;
11265 val->double_tap = md1_cfg.int1_double_tap;
11266 val->free_fall = md1_cfg.int1_ff;
11267 val->wake_up = md1_cfg.int1_wu;
11268 val->single_tap = md1_cfg.int1_single_tap;
11269 val->sleep_change = md1_cfg.int1_sleep_change;
11270 val->step_detector = emb_func_int1.int1_step_detector;
11271 val->tilt = emb_func_int1.int1_tilt;
11272 val->sig_mot = emb_func_int1.int1_sig_mot;
11273 val->fsm_lc = emb_func_int1.int1_fsm_lc;
11274 val->fsm1 = fsm_int1_a.int1_fsm1;
11275 val->fsm2 = fsm_int1_a.int1_fsm2;
11276 val->fsm3 = fsm_int1_a.int1_fsm3;
11277 val->fsm4 = fsm_int1_a.int1_fsm4;
11278 val->fsm5 = fsm_int1_a.int1_fsm5;
11279 val->fsm6 = fsm_int1_a.int1_fsm6;
11280 val->fsm7 = fsm_int1_a.int1_fsm7;
11281 val->fsm8 = fsm_int1_a.int1_fsm8;
11282 val->fsm9 = fsm_int1_b.int1_fsm9;
11283 val->fsm10 = fsm_int1_b.int1_fsm10;
11284 val->fsm11 = fsm_int1_b.int1_fsm11;
11285 val->fsm12 = fsm_int1_b.int1_fsm12;
11286 val->fsm13 = fsm_int1_b.int1_fsm13;
11287 val->fsm14 = fsm_int1_b.int1_fsm14;
11288 val->fsm15 = fsm_int1_b.int1_fsm15;
11289 val->fsm16 = fsm_int1_b.int1_fsm16;
11290
11291 return ret;
11292 }
11293
11294 /**
11295 * @brief Route interrupt signals on int2 pin.[set]
11296 *
11297 * @param ctx communication interface handler. Use NULL to ignore
11298 * this interface.(ptr)
11299 * @param aux_ctx auxiliary communication interface handler. Use NULL
11300 * to ignore this interface.(ptr)
11301 * @param val the signals to route on int2 pin.
11302 * @retval interface status (MANDATORY: return 0 -> no Error)
11303 *
11304 */
lsm6dso_pin_int2_route_set(stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dso_pin_int2_route_t val)11305 int32_t lsm6dso_pin_int2_route_set(stmdev_ctx_t *ctx,
11306 stmdev_ctx_t *aux_ctx,
11307 lsm6dso_pin_int2_route_t val)
11308 {
11309 lsm6dso_pin_int1_route_t pin_int1_route;
11310 lsm6dso_emb_func_int2_t emb_func_int2;
11311 lsm6dso_fsm_int2_a_t fsm_int2_a;
11312 lsm6dso_fsm_int2_b_t fsm_int2_b;
11313 lsm6dso_int2_ctrl_t int2_ctrl;
11314 lsm6dso_tap_cfg2_t tap_cfg2;
11315 lsm6dso_md2_cfg_t md2_cfg;
11316 lsm6dso_ctrl4_c_t ctrl4_c;
11317 lsm6dso_int_ois_t int_ois;
11318 int32_t ret;
11319 ret = 0;
11320
11321 if (aux_ctx != NULL)
11322 {
11323 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_INT_OIS,
11324 (uint8_t *)&int_ois, 1);
11325
11326 if (ret == 0)
11327 {
11328 int_ois.int2_drdy_ois = val.drdy_ois;
11329 ret = lsm6dso_write_reg(aux_ctx, LSM6DSO_INT_OIS,
11330 (uint8_t *)&int_ois, 1);
11331 }
11332 }
11333
11334 if (ctx != NULL)
11335 {
11336 int2_ctrl.int2_drdy_xl = val.drdy_xl;
11337 int2_ctrl.int2_drdy_g = val.drdy_g;
11338 int2_ctrl.int2_drdy_temp = val.drdy_temp;
11339 int2_ctrl.int2_fifo_th = val.fifo_th;
11340 int2_ctrl.int2_fifo_ovr = val.fifo_ovr;
11341 int2_ctrl.int2_fifo_full = val.fifo_full;
11342 int2_ctrl.int2_cnt_bdr = val.fifo_bdr;
11343 int2_ctrl.not_used_01 = 0;
11344 md2_cfg.int2_timestamp = val.timestamp;
11345 md2_cfg.int2_6d = val.six_d;
11346 md2_cfg.int2_double_tap = val.double_tap;
11347 md2_cfg.int2_ff = val.free_fall;
11348 md2_cfg.int2_wu = val.wake_up;
11349 md2_cfg.int2_single_tap = val.single_tap;
11350 md2_cfg.int2_sleep_change = val.sleep_change;
11351 emb_func_int2.not_used_01 = 0;
11352 emb_func_int2. int2_step_detector = val.step_detector;
11353 emb_func_int2.int2_tilt = val.tilt;
11354 emb_func_int2.int2_sig_mot = val.sig_mot;
11355 emb_func_int2.not_used_02 = 0;
11356 emb_func_int2.int2_fsm_lc = val.fsm_lc;
11357 fsm_int2_a.int2_fsm1 = val.fsm1;
11358 fsm_int2_a.int2_fsm2 = val.fsm2;
11359 fsm_int2_a.int2_fsm3 = val.fsm3;
11360 fsm_int2_a.int2_fsm4 = val.fsm4;
11361 fsm_int2_a.int2_fsm5 = val.fsm5;
11362 fsm_int2_a.int2_fsm6 = val.fsm6;
11363 fsm_int2_a.int2_fsm7 = val.fsm7;
11364 fsm_int2_a.int2_fsm8 = val.fsm8;
11365 fsm_int2_b.int2_fsm9 = val.fsm9 ;
11366 fsm_int2_b.int2_fsm10 = val.fsm10;
11367 fsm_int2_b.int2_fsm11 = val.fsm11;
11368 fsm_int2_b.int2_fsm12 = val.fsm12;
11369 fsm_int2_b.int2_fsm13 = val.fsm13;
11370 fsm_int2_b.int2_fsm14 = val.fsm14;
11371 fsm_int2_b.int2_fsm15 = val.fsm15;
11372 fsm_int2_b.int2_fsm16 = val.fsm16;
11373
11374 if (ret == 0)
11375 {
11376 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
11377
11378 if (ret == 0)
11379 {
11380 if ((val.drdy_temp | val.timestamp) != PROPERTY_DISABLE)
11381 {
11382 ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
11383 }
11384
11385 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
11386 }
11387 }
11388
11389 if (ret == 0)
11390 {
11391 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
11392 }
11393
11394 if (ret == 0)
11395 {
11396 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_INT2,
11397 (uint8_t *)&emb_func_int2, 1);
11398 }
11399
11400 if (ret == 0)
11401 {
11402 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT2_A,
11403 (uint8_t *)&fsm_int2_a, 1);
11404 }
11405
11406 if (ret == 0)
11407 {
11408 ret = lsm6dso_write_reg(ctx, LSM6DSO_FSM_INT2_B,
11409 (uint8_t *)&fsm_int2_b, 1);
11410 }
11411
11412 if (ret == 0)
11413 {
11414 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
11415 }
11416
11417 if (ret == 0)
11418 {
11419 if ((emb_func_int2.int2_fsm_lc
11420 | emb_func_int2.int2_sig_mot
11421 | emb_func_int2.int2_step_detector
11422 | emb_func_int2.int2_tilt
11423 | fsm_int2_a.int2_fsm1
11424 | fsm_int2_a.int2_fsm2
11425 | fsm_int2_a.int2_fsm3
11426 | fsm_int2_a.int2_fsm4
11427 | fsm_int2_a.int2_fsm5
11428 | fsm_int2_a.int2_fsm6
11429 | fsm_int2_a.int2_fsm7
11430 | fsm_int2_a.int2_fsm8
11431 | fsm_int2_b.int2_fsm9
11432 | fsm_int2_b.int2_fsm10
11433 | fsm_int2_b.int2_fsm11
11434 | fsm_int2_b.int2_fsm12
11435 | fsm_int2_b.int2_fsm13
11436 | fsm_int2_b.int2_fsm14
11437 | fsm_int2_b.int2_fsm15
11438 | fsm_int2_b.int2_fsm16) != PROPERTY_DISABLE)
11439 {
11440 md2_cfg.int2_emb_func = PROPERTY_ENABLE;
11441 }
11442
11443 else
11444 {
11445 md2_cfg.int2_emb_func = PROPERTY_DISABLE;
11446 }
11447
11448 ret = lsm6dso_write_reg(ctx, LSM6DSO_INT2_CTRL,
11449 (uint8_t *)&int2_ctrl, 1);
11450 }
11451
11452 if (ret == 0)
11453 {
11454 ret = lsm6dso_write_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
11455 }
11456
11457 if (ret == 0)
11458 {
11459 ret = lsm6dso_read_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
11460 }
11461
11462 if (ret == 0)
11463 {
11464 ret = lsm6dso_pin_int1_route_get(ctx, &pin_int1_route);
11465 }
11466
11467 if (ret == 0)
11468 {
11469 if ((val.fifo_bdr
11470 | val.drdy_g
11471 | val.drdy_temp
11472 | val.drdy_xl
11473 | val.fifo_full
11474 | val.fifo_ovr
11475 | val.fifo_th
11476 | val.six_d
11477 | val.double_tap
11478 | val.free_fall
11479 | val.wake_up
11480 | val.single_tap
11481 | val.sleep_change
11482 | pin_int1_route.den_flag
11483 | pin_int1_route.boot
11484 | pin_int1_route.fifo_bdr
11485 | pin_int1_route.drdy_g
11486 | pin_int1_route.drdy_xl
11487 | pin_int1_route.fifo_full
11488 | pin_int1_route.fifo_ovr
11489 | pin_int1_route.fifo_th
11490 | pin_int1_route.six_d
11491 | pin_int1_route.double_tap
11492 | pin_int1_route.free_fall
11493 | pin_int1_route.wake_up
11494 | pin_int1_route.single_tap
11495 | pin_int1_route.sleep_change) != PROPERTY_DISABLE)
11496 {
11497 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
11498 }
11499
11500 else
11501 {
11502 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
11503 }
11504
11505 ret = lsm6dso_write_reg(ctx, LSM6DSO_TAP_CFG2, (uint8_t *) &tap_cfg2, 1);
11506 }
11507 }
11508
11509 return ret;
11510 }
11511
11512 /**
11513 * @brief Route interrupt signals on int2 pin.[get]
11514 *
11515 * @param ctx communication interface handler. Use NULL to ignore
11516 * this interface.(ptr)
11517 * @param aux_ctx auxiliary communication interface handler. Use NULL
11518 * to ignore this interface.(ptr)
11519 * @param val the signals that are routed on int2 pin.(ptr)
11520 * @retval interface status (MANDATORY: return 0 -> no Error)
11521 *
11522 */
lsm6dso_pin_int2_route_get(stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dso_pin_int2_route_t * val)11523 int32_t lsm6dso_pin_int2_route_get(stmdev_ctx_t *ctx,
11524 stmdev_ctx_t *aux_ctx,
11525 lsm6dso_pin_int2_route_t *val)
11526 {
11527 lsm6dso_emb_func_int2_t emb_func_int2;
11528 lsm6dso_fsm_int2_a_t fsm_int2_a;
11529 lsm6dso_fsm_int2_b_t fsm_int2_b;
11530 lsm6dso_int2_ctrl_t int2_ctrl;
11531 lsm6dso_md2_cfg_t md2_cfg;
11532 lsm6dso_ctrl4_c_t ctrl4_c;
11533 lsm6dso_int_ois_t int_ois;
11534 int32_t ret;
11535 ret = 0;
11536
11537 if (aux_ctx != NULL)
11538 {
11539 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_INT_OIS,
11540 (uint8_t *)&int_ois, 1);
11541 val->drdy_ois = int_ois.int2_drdy_ois;
11542 }
11543
11544 if (ctx != NULL)
11545 {
11546 if (ret == 0)
11547 {
11548 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
11549 }
11550
11551 if (ret == 0)
11552 {
11553 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_INT2,
11554 (uint8_t *)&emb_func_int2, 1);
11555 }
11556
11557 if (ret == 0)
11558 {
11559 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT2_A,
11560 (uint8_t *)&fsm_int2_a, 1);
11561 }
11562
11563 if (ret == 0)
11564 {
11565 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_INT2_B,
11566 (uint8_t *)&fsm_int2_b, 1);
11567 }
11568
11569 if (ret == 0)
11570 {
11571 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
11572 }
11573
11574 if (ret == 0)
11575 {
11576 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL,
11577 (uint8_t *)&int2_ctrl, 1);
11578 }
11579
11580 if (ret == 0)
11581 {
11582 ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG,
11583 (uint8_t *)&md2_cfg, 1);
11584 }
11585
11586 if (ret == 0)
11587 {
11588 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
11589 }
11590
11591 if (ctrl4_c.int2_on_int1 == PROPERTY_DISABLE)
11592 {
11593 if (ret == 0)
11594 {
11595 ret = lsm6dso_read_reg(ctx, LSM6DSO_INT2_CTRL,
11596 (uint8_t *)&int2_ctrl, 1);
11597 val->drdy_temp = int2_ctrl.int2_drdy_temp;
11598 }
11599
11600 if (ret == 0)
11601 {
11602 ret = lsm6dso_read_reg(ctx, LSM6DSO_MD2_CFG, (uint8_t *)&md2_cfg, 1);
11603 val->timestamp = md2_cfg.int2_timestamp;
11604 }
11605 }
11606
11607 else
11608 {
11609 val->drdy_temp = PROPERTY_DISABLE;
11610 val->timestamp = PROPERTY_DISABLE;
11611 }
11612
11613 val->drdy_xl = int2_ctrl.int2_drdy_xl;
11614 val->drdy_g = int2_ctrl.int2_drdy_g;
11615 val->drdy_temp = int2_ctrl.int2_drdy_temp;
11616 val->fifo_th = int2_ctrl.int2_fifo_th;
11617 val->fifo_ovr = int2_ctrl.int2_fifo_ovr;
11618 val->fifo_full = int2_ctrl.int2_fifo_full;
11619 val->fifo_bdr = int2_ctrl.int2_cnt_bdr;
11620 val->timestamp = md2_cfg.int2_timestamp;
11621 val->six_d = md2_cfg.int2_6d;
11622 val->double_tap = md2_cfg.int2_double_tap;
11623 val->free_fall = md2_cfg.int2_ff;
11624 val->wake_up = md2_cfg.int2_wu;
11625 val->single_tap = md2_cfg.int2_single_tap;
11626 val->sleep_change = md2_cfg.int2_sleep_change;
11627 val->step_detector = emb_func_int2. int2_step_detector;
11628 val->tilt = emb_func_int2.int2_tilt;
11629 val->fsm_lc = emb_func_int2.int2_fsm_lc;
11630 val->fsm1 = fsm_int2_a.int2_fsm1;
11631 val->fsm2 = fsm_int2_a.int2_fsm2;
11632 val->fsm3 = fsm_int2_a.int2_fsm3;
11633 val->fsm4 = fsm_int2_a.int2_fsm4;
11634 val->fsm5 = fsm_int2_a.int2_fsm5;
11635 val->fsm6 = fsm_int2_a.int2_fsm6;
11636 val->fsm7 = fsm_int2_a.int2_fsm7;
11637 val->fsm8 = fsm_int2_a.int2_fsm8;
11638 val->fsm9 = fsm_int2_b.int2_fsm9;
11639 val->fsm10 = fsm_int2_b.int2_fsm10;
11640 val->fsm11 = fsm_int2_b.int2_fsm11;
11641 val->fsm12 = fsm_int2_b.int2_fsm12;
11642 val->fsm13 = fsm_int2_b.int2_fsm13;
11643 val->fsm14 = fsm_int2_b.int2_fsm14;
11644 val->fsm15 = fsm_int2_b.int2_fsm15;
11645 val->fsm16 = fsm_int2_b.int2_fsm16;
11646 }
11647
11648 return ret;
11649 }
11650
11651 /**
11652 * @brief Get the status of all the interrupt sources.[get]
11653 *
11654 * @param ctx communication interface handler.(ptr)
11655 * @param val the status of all the interrupt sources.(ptr)
11656 * @retval interface status (MANDATORY: return 0 -> no Error)
11657 *
11658 */
lsm6dso_all_sources_get(stmdev_ctx_t * ctx,lsm6dso_all_sources_t * val)11659 int32_t lsm6dso_all_sources_get(stmdev_ctx_t *ctx,
11660 lsm6dso_all_sources_t *val)
11661 {
11662 lsm6dso_emb_func_status_mainpage_t emb_func_status_mainpage;
11663 lsm6dso_status_master_mainpage_t status_master_mainpage;
11664 lsm6dso_fsm_status_a_mainpage_t fsm_status_a_mainpage;
11665 lsm6dso_fsm_status_b_mainpage_t fsm_status_b_mainpage;
11666 lsm6dso_fifo_status1_t fifo_status1;
11667 lsm6dso_fifo_status2_t fifo_status2;
11668 lsm6dso_all_int_src_t all_int_src;
11669 lsm6dso_wake_up_src_t wake_up_src;
11670 lsm6dso_status_reg_t status_reg;
11671 lsm6dso_tap_src_t tap_src;
11672 lsm6dso_d6d_src_t d6d_src;
11673 uint8_t reg[5];
11674 int32_t ret;
11675 ret = lsm6dso_read_reg(ctx, LSM6DSO_ALL_INT_SRC, reg, 5);
11676
11677 if (ret == 0)
11678 {
11679 bytecpy((uint8_t *)&all_int_src, ®[0]);
11680 bytecpy((uint8_t *)&wake_up_src, ®[1]);
11681 bytecpy((uint8_t *)&tap_src, ®[2]);
11682 bytecpy((uint8_t *)&d6d_src, ®[3]);
11683 bytecpy((uint8_t *)&status_reg, ®[4]);
11684 val->timestamp = all_int_src.timestamp_endcount;
11685 val->wake_up_z = wake_up_src.z_wu;
11686 val->wake_up_y = wake_up_src.y_wu;
11687 val->wake_up_x = wake_up_src.x_wu;
11688 val->wake_up = wake_up_src.wu_ia;
11689 val->sleep_state = wake_up_src.sleep_state;
11690 val->free_fall = wake_up_src.ff_ia;
11691 val->sleep_change = wake_up_src.sleep_change_ia;
11692 val->tap_x = tap_src.x_tap;
11693 val->tap_y = tap_src.y_tap;
11694 val->tap_z = tap_src.z_tap;
11695 val->tap_sign = tap_src.tap_sign;
11696 val->double_tap = tap_src.double_tap;
11697 val->single_tap = tap_src.single_tap;
11698 val->six_d_xl = d6d_src.xl;
11699 val->six_d_xh = d6d_src.xh;
11700 val->six_d_yl = d6d_src.yl;
11701 val->six_d_yh = d6d_src.yh;
11702 val->six_d_zl = d6d_src.zl;
11703 val->six_d_zh = d6d_src.zh;
11704 val->six_d = d6d_src.d6d_ia;
11705 val->den_flag = d6d_src.den_drdy;
11706 val->drdy_xl = status_reg.xlda;
11707 val->drdy_g = status_reg.gda;
11708 val->drdy_temp = status_reg.tda;
11709 }
11710
11711 if (ret == 0)
11712 {
11713 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_STATUS_MAINPAGE, reg, 3);
11714 }
11715
11716 if (ret == 0)
11717 {
11718 bytecpy((uint8_t *)&emb_func_status_mainpage, ®[0]);
11719 bytecpy((uint8_t *)&fsm_status_a_mainpage, ®[1]);
11720 bytecpy((uint8_t *)&fsm_status_b_mainpage, ®[2]);
11721 val->step_detector = emb_func_status_mainpage.is_step_det;
11722 val->tilt = emb_func_status_mainpage.is_tilt;
11723 val->sig_mot = emb_func_status_mainpage.is_sigmot;
11724 val->fsm_lc = emb_func_status_mainpage.is_fsm_lc;
11725 val->fsm1 = fsm_status_a_mainpage.is_fsm1;
11726 val->fsm2 = fsm_status_a_mainpage.is_fsm2;
11727 val->fsm3 = fsm_status_a_mainpage.is_fsm3;
11728 val->fsm4 = fsm_status_a_mainpage.is_fsm4;
11729 val->fsm5 = fsm_status_a_mainpage.is_fsm5;
11730 val->fsm6 = fsm_status_a_mainpage.is_fsm6;
11731 val->fsm7 = fsm_status_a_mainpage.is_fsm7;
11732 val->fsm8 = fsm_status_a_mainpage.is_fsm8;
11733 val->fsm9 = fsm_status_b_mainpage.is_fsm9;
11734 val->fsm10 = fsm_status_b_mainpage.is_fsm10;
11735 val->fsm11 = fsm_status_b_mainpage.is_fsm11;
11736 val->fsm12 = fsm_status_b_mainpage.is_fsm12;
11737 val->fsm13 = fsm_status_b_mainpage.is_fsm13;
11738 val->fsm14 = fsm_status_b_mainpage.is_fsm14;
11739 val->fsm15 = fsm_status_b_mainpage.is_fsm15;
11740 val->fsm16 = fsm_status_b_mainpage.is_fsm16;
11741 }
11742
11743 if (ret == 0)
11744 {
11745 ret = lsm6dso_read_reg(ctx, LSM6DSO_STATUS_MASTER_MAINPAGE, reg, 3);
11746 }
11747
11748 if (ret == 0)
11749 {
11750 bytecpy((uint8_t *)&status_master_mainpage, ®[0]);
11751 bytecpy((uint8_t *)&fifo_status1, ®[1]);
11752 bytecpy((uint8_t *)&fifo_status2, ®[2]);
11753 val->sh_endop = status_master_mainpage.sens_hub_endop;
11754 val->sh_slave0_nack = status_master_mainpage.slave0_nack;
11755 val->sh_slave1_nack = status_master_mainpage.slave1_nack;
11756 val->sh_slave2_nack = status_master_mainpage.slave2_nack;
11757 val->sh_slave3_nack = status_master_mainpage.slave3_nack;
11758 val->sh_wr_once = status_master_mainpage.wr_once_done;
11759 val->fifo_diff = (256U * fifo_status2.diff_fifo) +
11760 fifo_status1.diff_fifo;
11761 val->fifo_ovr_latched = fifo_status2.over_run_latched;
11762 val->fifo_bdr = fifo_status2.counter_bdr_ia;
11763 val->fifo_full = fifo_status2.fifo_full_ia;
11764 val->fifo_ovr = fifo_status2.fifo_ovr_ia;
11765 val->fifo_th = fifo_status2.fifo_wtm_ia;
11766 }
11767
11768 return ret;
11769 }
11770
11771 /**
11772 * @brief Sensor conversion parameters selection.[set]
11773 *
11774 * @param ctx communication interface handler. Use NULL to ignore
11775 * this interface.(ptr)
11776 * @param aux_ctx auxiliary communication interface handler. Use NULL
11777 * to ignore this interface.(ptr)
11778 * @param val set the sensor conversion parameters by checking
11779 * the constraints of the device.(ptr)
11780 * @retval interface status (MANDATORY: return 0 -> no Error)
11781 *
11782 */
lsm6dso_mode_set(stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dso_md_t * val)11783 int32_t lsm6dso_mode_set(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
11784 lsm6dso_md_t *val)
11785 {
11786 lsm6dso_func_cfg_access_t func_cfg_access;
11787 lsm6dso_ctrl1_ois_t ctrl1_ois;
11788 lsm6dso_ctrl2_ois_t ctrl2_ois;
11789 lsm6dso_ctrl3_ois_t ctrl3_ois;
11790 lsm6dso_ctrl1_xl_t ctrl1_xl;
11791 lsm6dso_ctrl8_xl_t ctrl8_xl;
11792 lsm6dso_ctrl2_g_t ctrl2_g;
11793 lsm6dso_ctrl3_c_t ctrl3_c;
11794 lsm6dso_ctrl4_c_t ctrl4_c;
11795 lsm6dso_ctrl5_c_t ctrl5_c;
11796 lsm6dso_ctrl6_c_t ctrl6_c;
11797 lsm6dso_ctrl7_g_t ctrl7_g;
11798 uint8_t xl_hm_mode;
11799 uint8_t g_hm_mode;
11800 uint8_t xl_ulp_en;
11801 uint8_t odr_gy;
11802 uint8_t odr_xl;
11803 uint8_t reg[8];
11804 int32_t ret;
11805
11806 ret = 0;
11807 /* FIXME: Remove warnings with STM32CubeIDE */
11808 ctrl3_c.not_used_01 = 0;
11809 ctrl4_c.not_used_01 = 0;
11810 /* reading input configuration */
11811 xl_hm_mode = ((uint8_t)val->ui.xl.odr & 0x10U) >> 4;
11812 xl_ulp_en = ((uint8_t)val->ui.xl.odr & 0x20U) >> 5;
11813 odr_xl = (uint8_t)val->ui.xl.odr & 0x0FU;
11814
11815 /* if enable xl ultra low power mode disable gy and OIS chain */
11816 if (xl_ulp_en == PROPERTY_ENABLE)
11817 {
11818 val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
11819 val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
11820 val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
11821 }
11822
11823 /* if OIS xl is enabled also gyro OIS is enabled */
11824 if (val->ois.xl.odr == LSM6DSO_XL_OIS_6667Hz_HP)
11825 {
11826 val->ois.gy.odr = LSM6DSO_GY_OIS_6667Hz_HP;
11827 }
11828
11829 g_hm_mode = ((uint8_t)val->ui.gy.odr & 0x10U) >> 4;
11830 odr_gy = (uint8_t)val->ui.gy.odr & 0x0FU;
11831
11832 /* reading registers to be configured */
11833 if (ctx != NULL)
11834 {
11835 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, reg, 8);
11836 bytecpy((uint8_t *)&ctrl1_xl, ®[0]);
11837 bytecpy((uint8_t *)&ctrl2_g, ®[1]);
11838 bytecpy((uint8_t *)&ctrl3_c, ®[2]);
11839 bytecpy((uint8_t *)&ctrl4_c, ®[3]);
11840 bytecpy((uint8_t *)&ctrl5_c, ®[4]);
11841 bytecpy((uint8_t *)&ctrl6_c, ®[5]);
11842 bytecpy((uint8_t *)&ctrl7_g, ®[6]);
11843 bytecpy((uint8_t *)&ctrl8_xl, ®[7]);
11844
11845 if (ret == 0)
11846 {
11847 ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS,
11848 (uint8_t *)&func_cfg_access, 1);
11849 }
11850
11851 /* if toggle xl ultra low power mode, turn off xl before reconfigure */
11852 if (ctrl5_c.xl_ulp_en != xl_ulp_en)
11853 {
11854 ctrl1_xl.odr_xl = (uint8_t) 0x00U;
11855 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL,
11856 (uint8_t *)&ctrl1_xl, 1);
11857 }
11858 }
11859
11860 /* reading OIS registers to be configured */
11861 if (aux_ctx != NULL)
11862 {
11863 if (ret == 0)
11864 {
11865 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS, reg, 3);
11866 }
11867
11868 bytecpy((uint8_t *)&ctrl1_ois, ®[0]);
11869 bytecpy((uint8_t *)&ctrl2_ois, ®[1]);
11870 bytecpy((uint8_t *)&ctrl3_ois, ®[2]);
11871 }
11872
11873 else
11874 {
11875 if (ctx != NULL)
11876 {
11877 if (ret == 0)
11878 {
11879 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, reg, 3);
11880 }
11881
11882 bytecpy((uint8_t *)&ctrl1_ois, ®[0]);
11883 bytecpy((uint8_t *)&ctrl2_ois, ®[1]);
11884 bytecpy((uint8_t *)&ctrl3_ois, ®[2]);
11885 }
11886 }
11887
11888 /* Check the Finite State Machine data rate constraints */
11889 if (val->fsm.sens != LSM6DSO_FSM_DISABLE)
11890 {
11891 switch (val->fsm.odr)
11892 {
11893 case LSM6DSO_FSM_12Hz5:
11894 if ((val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl == 0x00U))
11895 {
11896 odr_xl = 0x01U;
11897 }
11898
11899 if ((val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy == 0x00U))
11900 {
11901 xl_ulp_en = PROPERTY_DISABLE;
11902 odr_gy = 0x01U;
11903 }
11904
11905 break;
11906
11907 case LSM6DSO_FSM_26Hz:
11908 if ((val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x02U))
11909 {
11910 odr_xl = 0x02U;
11911 }
11912
11913 if ((val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x02U))
11914 {
11915 xl_ulp_en = PROPERTY_DISABLE;
11916 odr_gy = 0x02U;
11917 }
11918
11919 break;
11920
11921 case LSM6DSO_FSM_52Hz:
11922 if ((val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x03U))
11923 {
11924 odr_xl = 0x03U;
11925 }
11926
11927 if ((val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x03U))
11928 {
11929 xl_ulp_en = PROPERTY_DISABLE;
11930 odr_gy = 0x03U;
11931 }
11932
11933 break;
11934
11935 case LSM6DSO_FSM_104Hz:
11936 if ((val->fsm.sens != LSM6DSO_FSM_GY) && (odr_xl < 0x04U))
11937 {
11938 odr_xl = 0x04U;
11939 }
11940
11941 if ((val->fsm.sens != LSM6DSO_FSM_XL) && (odr_gy < 0x04U))
11942 {
11943 xl_ulp_en = PROPERTY_DISABLE;
11944 odr_gy = 0x04U;
11945 }
11946
11947 break;
11948
11949 default:
11950 odr_xl = 0x00U;
11951 odr_gy = 0x00U;
11952 break;
11953 }
11954 }
11955
11956 /* Updating the accelerometer data rate configuration */
11957 switch ((ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
11958 ctrl1_xl.odr_xl)
11959 {
11960 case LSM6DSO_XL_UI_OFF:
11961 val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
11962 break;
11963
11964 case LSM6DSO_XL_UI_12Hz5_HP:
11965 val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_HP;
11966 break;
11967
11968 case LSM6DSO_XL_UI_26Hz_HP:
11969 val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_HP;
11970 break;
11971
11972 case LSM6DSO_XL_UI_52Hz_HP:
11973 val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_HP;
11974 break;
11975
11976 case LSM6DSO_XL_UI_104Hz_HP:
11977 val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_HP;
11978 break;
11979
11980 case LSM6DSO_XL_UI_208Hz_HP:
11981 val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_HP;
11982 break;
11983
11984 case LSM6DSO_XL_UI_416Hz_HP:
11985 val->ui.xl.odr = LSM6DSO_XL_UI_416Hz_HP;
11986 break;
11987
11988 case LSM6DSO_XL_UI_833Hz_HP:
11989 val->ui.xl.odr = LSM6DSO_XL_UI_833Hz_HP;
11990 break;
11991
11992 case LSM6DSO_XL_UI_1667Hz_HP:
11993 val->ui.xl.odr = LSM6DSO_XL_UI_1667Hz_HP;
11994 break;
11995
11996 case LSM6DSO_XL_UI_3333Hz_HP:
11997 val->ui.xl.odr = LSM6DSO_XL_UI_3333Hz_HP;
11998 break;
11999
12000 case LSM6DSO_XL_UI_6667Hz_HP:
12001 val->ui.xl.odr = LSM6DSO_XL_UI_6667Hz_HP;
12002 break;
12003
12004 case LSM6DSO_XL_UI_1Hz6_LP:
12005 val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_LP;
12006 break;
12007
12008 case LSM6DSO_XL_UI_12Hz5_LP:
12009 val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_LP;
12010 break;
12011
12012 case LSM6DSO_XL_UI_26Hz_LP:
12013 val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_LP;
12014 break;
12015
12016 case LSM6DSO_XL_UI_52Hz_LP:
12017 val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_LP;
12018 break;
12019
12020 case LSM6DSO_XL_UI_104Hz_NM:
12021 val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_NM;
12022 break;
12023
12024 case LSM6DSO_XL_UI_208Hz_NM:
12025 val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_NM;
12026 break;
12027
12028 case LSM6DSO_XL_UI_1Hz6_ULP:
12029 val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_ULP;
12030 break;
12031
12032 case LSM6DSO_XL_UI_12Hz5_ULP:
12033 val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_ULP;
12034 break;
12035
12036 case LSM6DSO_XL_UI_26Hz_ULP:
12037 val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_ULP;
12038 break;
12039
12040 case LSM6DSO_XL_UI_52Hz_ULP:
12041 val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_ULP;
12042 break;
12043
12044 case LSM6DSO_XL_UI_104Hz_ULP:
12045 val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_ULP;
12046 break;
12047
12048 case LSM6DSO_XL_UI_208Hz_ULP:
12049 val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_ULP;
12050 break;
12051
12052 default:
12053 val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
12054 break;
12055 }
12056
12057 /* Updating the accelerometer data rate configuration */
12058 switch ((ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g)
12059 {
12060 case LSM6DSO_GY_UI_OFF:
12061 val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
12062 break;
12063
12064 case LSM6DSO_GY_UI_12Hz5_LP:
12065 val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_LP;
12066 break;
12067
12068 case LSM6DSO_GY_UI_12Hz5_HP:
12069 val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_HP;
12070 break;
12071
12072 case LSM6DSO_GY_UI_26Hz_LP:
12073 val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_LP;
12074 break;
12075
12076 case LSM6DSO_GY_UI_26Hz_HP:
12077 val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_HP;
12078 break;
12079
12080 case LSM6DSO_GY_UI_52Hz_LP:
12081 val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_LP;
12082 break;
12083
12084 case LSM6DSO_GY_UI_52Hz_HP:
12085 val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_HP;
12086 break;
12087
12088 case LSM6DSO_GY_UI_104Hz_NM:
12089 val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_NM;
12090 break;
12091
12092 case LSM6DSO_GY_UI_104Hz_HP:
12093 val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_HP;
12094 break;
12095
12096 case LSM6DSO_GY_UI_208Hz_NM:
12097 val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_NM;
12098 break;
12099
12100 case LSM6DSO_GY_UI_208Hz_HP:
12101 val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_HP;
12102 break;
12103
12104 case LSM6DSO_GY_UI_416Hz_HP:
12105 val->ui.gy.odr = LSM6DSO_GY_UI_416Hz_HP;
12106 break;
12107
12108 case LSM6DSO_GY_UI_833Hz_HP:
12109 val->ui.gy.odr = LSM6DSO_GY_UI_833Hz_HP;
12110 break;
12111
12112 case LSM6DSO_GY_UI_1667Hz_HP:
12113 val->ui.gy.odr = LSM6DSO_GY_UI_1667Hz_HP;
12114 break;
12115
12116 case LSM6DSO_GY_UI_3333Hz_HP:
12117 val->ui.gy.odr = LSM6DSO_GY_UI_3333Hz_HP;
12118 break;
12119
12120 case LSM6DSO_GY_UI_6667Hz_HP:
12121 val->ui.gy.odr = LSM6DSO_GY_UI_6667Hz_HP;
12122 break;
12123
12124 default:
12125 val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
12126 break;
12127 }
12128
12129 /* Check accelerometer full scale constraints */
12130 /* Full scale of 16g must be the same for UI and OIS */
12131 if ((val->ui.xl.fs == LSM6DSO_XL_UI_16g) ||
12132 (val->ois.xl.fs == LSM6DSO_XL_OIS_16g))
12133 {
12134 val->ui.xl.fs = LSM6DSO_XL_UI_16g;
12135 val->ois.xl.fs = LSM6DSO_XL_OIS_16g;
12136 }
12137
12138 /* prapare new configuration */
12139
12140 /* Full scale of 16g must be the same for UI and OIS */
12141 if (val->ui.xl.fs == LSM6DSO_XL_UI_16g)
12142 {
12143 ctrl8_xl.xl_fs_mode = PROPERTY_DISABLE;
12144 }
12145
12146 else
12147 {
12148 ctrl8_xl.xl_fs_mode = PROPERTY_ENABLE;
12149 }
12150
12151 /* OIS new configuration */
12152 ctrl7_g.ois_on_en = val->ois.ctrl_md & 0x01U;
12153
12154 switch (val->ois.ctrl_md)
12155 {
12156 case LSM6DSO_OIS_ONLY_AUX:
12157 ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
12158 ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr |
12159 (uint8_t)val->ois.xl.odr;
12160 ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
12161 ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
12162 break;
12163
12164 case LSM6DSO_OIS_MIXED:
12165 ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
12166 ctrl7_g.ois_on = (uint8_t)val->ois.gy.odr | (uint8_t)val->ois.xl.odr;
12167 ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
12168 ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
12169 break;
12170
12171 default:
12172 ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
12173 ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr |
12174 (uint8_t)val->ois.xl.odr;
12175 ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
12176 ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
12177 break;
12178 }
12179
12180 /* UI new configuration */
12181 ctrl1_xl.odr_xl = odr_xl;
12182 ctrl1_xl.fs_xl = (uint8_t)val->ui.xl.fs;
12183 ctrl5_c.xl_ulp_en = xl_ulp_en;
12184 ctrl6_c.xl_hm_mode = xl_hm_mode;
12185 ctrl7_g.g_hm_mode = g_hm_mode;
12186 ctrl2_g.odr_g = odr_gy;
12187 ctrl2_g.fs_g = (uint8_t) val->ui.gy.fs;
12188
12189 /* writing checked configuration */
12190 if (ctx != NULL)
12191 {
12192 bytecpy(®[0], (uint8_t *)&ctrl1_xl);
12193 bytecpy(®[1], (uint8_t *)&ctrl2_g);
12194 bytecpy(®[2], (uint8_t *)&ctrl3_c);
12195 bytecpy(®[3], (uint8_t *)&ctrl4_c);
12196 bytecpy(®[4], (uint8_t *)&ctrl5_c);
12197 bytecpy(®[5], (uint8_t *)&ctrl6_c);
12198 bytecpy(®[6], (uint8_t *)&ctrl7_g);
12199 bytecpy(®[7], (uint8_t *)&ctrl8_xl);
12200
12201 if (ret == 0)
12202 {
12203 ret = lsm6dso_write_reg(ctx, LSM6DSO_CTRL1_XL, (uint8_t *)®, 8);
12204 }
12205
12206 if (ret == 0)
12207 {
12208 ret = lsm6dso_write_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS,
12209 (uint8_t *)&func_cfg_access, 1);
12210 }
12211 }
12212
12213 /* writing OIS checked configuration */
12214 if (aux_ctx != NULL)
12215 {
12216 bytecpy(®[0], (uint8_t *)&ctrl1_ois);
12217 bytecpy(®[1], (uint8_t *)&ctrl2_ois);
12218 bytecpy(®[2], (uint8_t *)&ctrl3_ois);
12219
12220 if (ret == 0)
12221 {
12222 ret = lsm6dso_write_reg(aux_ctx, LSM6DSO_CTRL1_OIS, reg, 3);
12223 }
12224 }
12225
12226 return ret;
12227 }
12228
12229 /**
12230 * @brief Sensor conversion parameters selection.[get]
12231 *
12232 * @param ctx communication interface handler. Use NULL to ignore
12233 * this interface.(ptr)
12234 * @param aux_ctx auxiliary communication interface handler. Use NULL
12235 * to ignore this interface.(ptr)
12236 * @param val get the sensor conversion parameters.(ptr)
12237 * @retval interface status (MANDATORY: return 0 -> no Error)
12238 *
12239 */
lsm6dso_mode_get(stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dso_md_t * val)12240 int32_t lsm6dso_mode_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
12241 lsm6dso_md_t *val)
12242 {
12243 lsm6dso_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
12244 lsm6dso_func_cfg_access_t func_cfg_access;
12245 lsm6dso_emb_func_en_b_t emb_func_en_b;
12246 lsm6dso_fsm_enable_a_t fsm_enable_a;
12247 lsm6dso_fsm_enable_b_t fsm_enable_b;
12248 lsm6dso_ctrl1_ois_t ctrl1_ois;
12249 lsm6dso_ctrl2_ois_t ctrl2_ois;
12250 lsm6dso_ctrl3_ois_t ctrl3_ois;
12251 lsm6dso_ctrl1_xl_t ctrl1_xl;
12252 lsm6dso_ctrl2_g_t ctrl2_g;
12253 lsm6dso_ctrl3_c_t ctrl3_c;
12254 lsm6dso_ctrl4_c_t ctrl4_c;
12255 lsm6dso_ctrl5_c_t ctrl5_c;
12256 lsm6dso_ctrl6_c_t ctrl6_c;
12257 lsm6dso_ctrl7_g_t ctrl7_g;
12258 uint8_t reg[8];
12259 int32_t ret;
12260
12261 ret = 0;
12262
12263 /* reading the registers of the device */
12264 if (ctx != NULL)
12265 {
12266 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_XL, reg, 7);
12267 bytecpy((uint8_t *)&ctrl1_xl, ®[0]);
12268 bytecpy((uint8_t *)&ctrl2_g, ®[1]);
12269 bytecpy((uint8_t *)&ctrl3_c, ®[2]);
12270 bytecpy((uint8_t *)&ctrl4_c, ®[3]);
12271 bytecpy((uint8_t *)&ctrl5_c, ®[4]);
12272 bytecpy((uint8_t *)&ctrl6_c, ®[5]);
12273 bytecpy((uint8_t *)&ctrl7_g, ®[6]);
12274
12275 if (ret == 0)
12276 {
12277 ret = lsm6dso_read_reg(ctx, LSM6DSO_FUNC_CFG_ACCESS,
12278 (uint8_t *)&func_cfg_access, 1);
12279 }
12280
12281 if (ret == 0)
12282 {
12283 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
12284 }
12285
12286 if (ret == 0)
12287 {
12288 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_ODR_CFG_B, reg, 1);
12289 bytecpy((uint8_t *)&emb_func_odr_cfg_b, ®[0]);
12290 }
12291
12292 if (ret == 0)
12293 {
12294 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
12295 (uint8_t *)&emb_func_en_b, 1);
12296 }
12297
12298 if (ret == 0)
12299 {
12300 ret = lsm6dso_read_reg(ctx, LSM6DSO_FSM_ENABLE_A, reg, 2);
12301 bytecpy((uint8_t *)&fsm_enable_a, ®[0]);
12302 bytecpy((uint8_t *)&fsm_enable_b, ®[1]);
12303 }
12304
12305 if (ret == 0)
12306 {
12307 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
12308 }
12309 }
12310
12311 if (aux_ctx != NULL)
12312 {
12313 if (ret == 0)
12314 {
12315 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_CTRL1_OIS, reg, 3);
12316 }
12317
12318 bytecpy((uint8_t *)&ctrl1_ois, ®[0]);
12319 bytecpy((uint8_t *)&ctrl2_ois, ®[1]);
12320 bytecpy((uint8_t *)&ctrl3_ois, ®[2]);
12321 }
12322
12323 else
12324 {
12325 if (ctx != NULL)
12326 {
12327 if (ret == 0)
12328 {
12329 ret = lsm6dso_read_reg(ctx, LSM6DSO_CTRL1_OIS, reg, 3);
12330 }
12331
12332 bytecpy((uint8_t *)&ctrl1_ois, ®[0]);
12333 bytecpy((uint8_t *)&ctrl2_ois, ®[1]);
12334 bytecpy((uint8_t *)&ctrl3_ois, ®[2]);
12335 }
12336 }
12337
12338 /* fill the input structure */
12339
12340 /* get accelerometer configuration */
12341 switch ((ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
12342 ctrl1_xl.odr_xl)
12343 {
12344 case LSM6DSO_XL_UI_OFF:
12345 val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
12346 break;
12347
12348 case LSM6DSO_XL_UI_12Hz5_HP:
12349 val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_HP;
12350 break;
12351
12352 case LSM6DSO_XL_UI_26Hz_HP:
12353 val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_HP;
12354 break;
12355
12356 case LSM6DSO_XL_UI_52Hz_HP:
12357 val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_HP;
12358 break;
12359
12360 case LSM6DSO_XL_UI_104Hz_HP:
12361 val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_HP;
12362 break;
12363
12364 case LSM6DSO_XL_UI_208Hz_HP:
12365 val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_HP;
12366 break;
12367
12368 case LSM6DSO_XL_UI_416Hz_HP:
12369 val->ui.xl.odr = LSM6DSO_XL_UI_416Hz_HP;
12370 break;
12371
12372 case LSM6DSO_XL_UI_833Hz_HP:
12373 val->ui.xl.odr = LSM6DSO_XL_UI_833Hz_HP;
12374 break;
12375
12376 case LSM6DSO_XL_UI_1667Hz_HP:
12377 val->ui.xl.odr = LSM6DSO_XL_UI_1667Hz_HP;
12378 break;
12379
12380 case LSM6DSO_XL_UI_3333Hz_HP:
12381 val->ui.xl.odr = LSM6DSO_XL_UI_3333Hz_HP;
12382 break;
12383
12384 case LSM6DSO_XL_UI_6667Hz_HP:
12385 val->ui.xl.odr = LSM6DSO_XL_UI_6667Hz_HP;
12386 break;
12387
12388 case LSM6DSO_XL_UI_1Hz6_LP:
12389 val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_LP;
12390 break;
12391
12392 case LSM6DSO_XL_UI_12Hz5_LP:
12393 val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_LP;
12394 break;
12395
12396 case LSM6DSO_XL_UI_26Hz_LP:
12397 val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_LP;
12398 break;
12399
12400 case LSM6DSO_XL_UI_52Hz_LP:
12401 val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_LP;
12402 break;
12403
12404 case LSM6DSO_XL_UI_104Hz_NM:
12405 val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_NM;
12406 break;
12407
12408 case LSM6DSO_XL_UI_208Hz_NM:
12409 val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_NM;
12410 break;
12411
12412 case LSM6DSO_XL_UI_1Hz6_ULP:
12413 val->ui.xl.odr = LSM6DSO_XL_UI_1Hz6_ULP;
12414 break;
12415
12416 case LSM6DSO_XL_UI_12Hz5_ULP:
12417 val->ui.xl.odr = LSM6DSO_XL_UI_12Hz5_ULP;
12418 break;
12419
12420 case LSM6DSO_XL_UI_26Hz_ULP:
12421 val->ui.xl.odr = LSM6DSO_XL_UI_26Hz_ULP;
12422 break;
12423
12424 case LSM6DSO_XL_UI_52Hz_ULP:
12425 val->ui.xl.odr = LSM6DSO_XL_UI_52Hz_ULP;
12426 break;
12427
12428 case LSM6DSO_XL_UI_104Hz_ULP:
12429 val->ui.xl.odr = LSM6DSO_XL_UI_104Hz_ULP;
12430 break;
12431
12432 case LSM6DSO_XL_UI_208Hz_ULP:
12433 val->ui.xl.odr = LSM6DSO_XL_UI_208Hz_ULP;
12434 break;
12435
12436 default:
12437 val->ui.xl.odr = LSM6DSO_XL_UI_OFF;
12438 break;
12439 }
12440
12441 switch (ctrl1_xl.fs_xl)
12442 {
12443 case LSM6DSO_XL_UI_2g:
12444 val->ui.xl.fs = LSM6DSO_XL_UI_2g;
12445 break;
12446
12447 case LSM6DSO_XL_UI_4g:
12448 val->ui.xl.fs = LSM6DSO_XL_UI_4g;
12449 break;
12450
12451 case LSM6DSO_XL_UI_8g:
12452 val->ui.xl.fs = LSM6DSO_XL_UI_8g;
12453 break;
12454
12455 case LSM6DSO_XL_UI_16g:
12456 val->ui.xl.fs = LSM6DSO_XL_UI_16g;
12457 break;
12458
12459 default:
12460 val->ui.xl.fs = LSM6DSO_XL_UI_2g;
12461 break;
12462 }
12463
12464 /* get gyroscope configuration */
12465 switch ((ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g)
12466 {
12467 case LSM6DSO_GY_UI_OFF:
12468 val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
12469 break;
12470
12471 case LSM6DSO_GY_UI_12Hz5_LP:
12472 val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_LP;
12473 break;
12474
12475 case LSM6DSO_GY_UI_12Hz5_HP:
12476 val->ui.gy.odr = LSM6DSO_GY_UI_12Hz5_HP;
12477 break;
12478
12479 case LSM6DSO_GY_UI_26Hz_LP:
12480 val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_LP;
12481 break;
12482
12483 case LSM6DSO_GY_UI_26Hz_HP:
12484 val->ui.gy.odr = LSM6DSO_GY_UI_26Hz_HP;
12485 break;
12486
12487 case LSM6DSO_GY_UI_52Hz_LP:
12488 val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_LP;
12489 break;
12490
12491 case LSM6DSO_GY_UI_52Hz_HP:
12492 val->ui.gy.odr = LSM6DSO_GY_UI_52Hz_HP;
12493 break;
12494
12495 case LSM6DSO_GY_UI_104Hz_NM:
12496 val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_NM;
12497 break;
12498
12499 case LSM6DSO_GY_UI_104Hz_HP:
12500 val->ui.gy.odr = LSM6DSO_GY_UI_104Hz_HP;
12501 break;
12502
12503 case LSM6DSO_GY_UI_208Hz_NM:
12504 val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_NM;
12505 break;
12506
12507 case LSM6DSO_GY_UI_208Hz_HP:
12508 val->ui.gy.odr = LSM6DSO_GY_UI_208Hz_HP;
12509 break;
12510
12511 case LSM6DSO_GY_UI_416Hz_HP:
12512 val->ui.gy.odr = LSM6DSO_GY_UI_416Hz_HP;
12513 break;
12514
12515 case LSM6DSO_GY_UI_833Hz_HP:
12516 val->ui.gy.odr = LSM6DSO_GY_UI_833Hz_HP;
12517 break;
12518
12519 case LSM6DSO_GY_UI_1667Hz_HP:
12520 val->ui.gy.odr = LSM6DSO_GY_UI_1667Hz_HP;
12521 break;
12522
12523 case LSM6DSO_GY_UI_3333Hz_HP:
12524 val->ui.gy.odr = LSM6DSO_GY_UI_3333Hz_HP;
12525 break;
12526
12527 case LSM6DSO_GY_UI_6667Hz_HP:
12528 val->ui.gy.odr = LSM6DSO_GY_UI_6667Hz_HP;
12529 break;
12530
12531 default:
12532 val->ui.gy.odr = LSM6DSO_GY_UI_OFF;
12533 break;
12534 }
12535
12536 switch (ctrl2_g.fs_g)
12537 {
12538 case LSM6DSO_GY_UI_125dps:
12539 val->ui.gy.fs = LSM6DSO_GY_UI_125dps;
12540 break;
12541
12542 case LSM6DSO_GY_UI_250dps:
12543 val->ui.gy.fs = LSM6DSO_GY_UI_250dps;
12544 break;
12545
12546 case LSM6DSO_GY_UI_500dps:
12547 val->ui.gy.fs = LSM6DSO_GY_UI_500dps;
12548 break;
12549
12550 case LSM6DSO_GY_UI_1000dps:
12551 val->ui.gy.fs = LSM6DSO_GY_UI_1000dps;
12552 break;
12553
12554 case LSM6DSO_GY_UI_2000dps:
12555 val->ui.gy.fs = LSM6DSO_GY_UI_2000dps;
12556 break;
12557
12558 default:
12559 val->ui.gy.fs = LSM6DSO_GY_UI_125dps;
12560 break;
12561 }
12562
12563 /* get finite state machine configuration */
12564 if ((fsm_enable_a.fsm1_en | fsm_enable_a.fsm2_en |
12565 fsm_enable_a.fsm3_en |
12566 fsm_enable_a.fsm4_en | fsm_enable_a.fsm5_en | fsm_enable_a.fsm6_en |
12567 fsm_enable_a.fsm7_en | fsm_enable_a.fsm8_en | fsm_enable_b.fsm9_en |
12568 fsm_enable_b.fsm10_en | fsm_enable_b.fsm11_en |
12569 fsm_enable_b.fsm12_en | fsm_enable_b.fsm13_en |
12570 fsm_enable_b.fsm14_en | fsm_enable_b.fsm15_en |
12571 fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
12572 {
12573 switch (emb_func_odr_cfg_b.fsm_odr)
12574 {
12575 case LSM6DSO_FSM_12Hz5:
12576 val->fsm.odr = LSM6DSO_FSM_12Hz5;
12577 break;
12578
12579 case LSM6DSO_FSM_26Hz:
12580 val->fsm.odr = LSM6DSO_FSM_26Hz;
12581 break;
12582
12583 case LSM6DSO_FSM_52Hz:
12584 val->fsm.odr = LSM6DSO_FSM_52Hz;
12585 break;
12586
12587 case LSM6DSO_FSM_104Hz:
12588 val->fsm.odr = LSM6DSO_FSM_104Hz;
12589 break;
12590
12591 default:
12592 val->fsm.odr = LSM6DSO_FSM_12Hz5;
12593 break;
12594 }
12595
12596 val->fsm.sens = LSM6DSO_FSM_XL_GY;
12597
12598 if (val->ui.gy.odr == LSM6DSO_GY_UI_OFF)
12599 {
12600 val->fsm.sens = LSM6DSO_FSM_XL;
12601 }
12602
12603 if (val->ui.xl.odr == LSM6DSO_XL_UI_OFF)
12604 {
12605 val->fsm.sens = LSM6DSO_FSM_GY;
12606 }
12607 }
12608
12609 else
12610 {
12611 val->fsm.sens = LSM6DSO_FSM_DISABLE;
12612 }
12613
12614 /* get ois configuration */
12615
12616 /* OIS configuration mode */
12617 switch (ctrl7_g.ois_on_en)
12618 {
12619 case LSM6DSO_OIS_ONLY_AUX:
12620 switch (ctrl3_ois.fs_xl_ois)
12621 {
12622 case LSM6DSO_XL_OIS_2g:
12623 val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
12624 break;
12625
12626 case LSM6DSO_XL_OIS_4g:
12627 val->ois.xl.fs = LSM6DSO_XL_OIS_4g;
12628 break;
12629
12630 case LSM6DSO_XL_OIS_8g:
12631 val->ois.xl.fs = LSM6DSO_XL_OIS_8g;
12632 break;
12633
12634 case LSM6DSO_XL_OIS_16g:
12635 val->ois.xl.fs = LSM6DSO_XL_OIS_16g;
12636 break;
12637
12638 default:
12639 val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
12640 break;
12641 }
12642
12643 switch (ctrl1_ois.mode4_en)
12644 {
12645 case LSM6DSO_XL_OIS_OFF:
12646 val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
12647 break;
12648
12649 case LSM6DSO_XL_OIS_6667Hz_HP:
12650 val->ois.xl.odr = LSM6DSO_XL_OIS_6667Hz_HP;
12651 break;
12652
12653 default:
12654 val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
12655 break;
12656 }
12657
12658 switch (ctrl1_ois.fs_g_ois)
12659 {
12660 case LSM6DSO_GY_OIS_250dps:
12661 val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
12662 break;
12663
12664 case LSM6DSO_GY_OIS_500dps:
12665 val->ois.gy.fs = LSM6DSO_GY_OIS_500dps;
12666 break;
12667
12668 case LSM6DSO_GY_OIS_1000dps:
12669 val->ois.gy.fs = LSM6DSO_GY_OIS_1000dps;
12670 break;
12671
12672 case LSM6DSO_GY_OIS_2000dps:
12673 val->ois.gy.fs = LSM6DSO_GY_OIS_2000dps;
12674 break;
12675
12676 default:
12677 val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
12678 break;
12679 }
12680
12681 switch (ctrl1_ois.ois_en_spi2)
12682 {
12683 case LSM6DSO_GY_OIS_OFF:
12684 val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
12685 break;
12686
12687 case LSM6DSO_GY_OIS_6667Hz_HP:
12688 val->ois.gy.odr = LSM6DSO_GY_OIS_6667Hz_HP;
12689 break;
12690
12691 default:
12692 val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
12693 break;
12694 }
12695
12696 val->ois.ctrl_md = LSM6DSO_OIS_ONLY_AUX;
12697 break;
12698
12699 case LSM6DSO_OIS_MIXED:
12700 switch (ctrl3_ois.fs_xl_ois)
12701 {
12702 case LSM6DSO_XL_OIS_2g:
12703 val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
12704 break;
12705
12706 case LSM6DSO_XL_OIS_4g:
12707 val->ois.xl.fs = LSM6DSO_XL_OIS_4g;
12708 break;
12709
12710 case LSM6DSO_XL_OIS_8g:
12711 val->ois.xl.fs = LSM6DSO_XL_OIS_8g;
12712 break;
12713
12714 case LSM6DSO_XL_OIS_16g:
12715 val->ois.xl.fs = LSM6DSO_XL_OIS_16g;
12716 break;
12717
12718 default:
12719 val->ois.xl.fs = LSM6DSO_XL_OIS_2g;
12720 break;
12721 }
12722
12723 switch (ctrl1_ois.mode4_en)
12724 {
12725 case LSM6DSO_XL_OIS_OFF:
12726 val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
12727 break;
12728
12729 case LSM6DSO_XL_OIS_6667Hz_HP:
12730 val->ois.xl.odr = LSM6DSO_XL_OIS_6667Hz_HP;
12731 break;
12732
12733 default:
12734 val->ois.xl.odr = LSM6DSO_XL_OIS_OFF;
12735 break;
12736 }
12737
12738 switch (ctrl1_ois.fs_g_ois)
12739 {
12740 case LSM6DSO_GY_OIS_250dps:
12741 val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
12742 break;
12743
12744 case LSM6DSO_GY_OIS_500dps:
12745 val->ois.gy.fs = LSM6DSO_GY_OIS_500dps;
12746 break;
12747
12748 case LSM6DSO_GY_OIS_1000dps:
12749 val->ois.gy.fs = LSM6DSO_GY_OIS_1000dps;
12750 break;
12751
12752 case LSM6DSO_GY_OIS_2000dps:
12753 val->ois.gy.fs = LSM6DSO_GY_OIS_2000dps;
12754 break;
12755
12756 default:
12757 val->ois.gy.fs = LSM6DSO_GY_OIS_250dps;
12758 break;
12759 }
12760
12761 switch (ctrl1_ois.ois_en_spi2)
12762 {
12763 case LSM6DSO_GY_OIS_OFF:
12764 val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
12765 break;
12766
12767 case LSM6DSO_GY_OIS_6667Hz_HP:
12768 val->ois.gy.odr = LSM6DSO_GY_OIS_6667Hz_HP;
12769 break;
12770
12771 default:
12772 val->ois.gy.odr = LSM6DSO_GY_OIS_OFF;
12773 break;
12774 }
12775
12776 val->ois.ctrl_md = LSM6DSO_OIS_MIXED;
12777 break;
12778
12779 default:
12780 ctrl1_ois.fs_g_ois = (uint8_t)val->ois.gy.fs;
12781 ctrl1_ois.ois_en_spi2 = (uint8_t)val->ois.gy.odr |
12782 (uint8_t)val->ois.xl.odr;
12783 ctrl1_ois.mode4_en = (uint8_t) val->ois.xl.odr;
12784 ctrl3_ois.fs_xl_ois = (uint8_t)val->ois.xl.fs;
12785 val->ois.ctrl_md = LSM6DSO_OIS_ONLY_AUX;
12786 break;
12787 }
12788
12789 return ret;
12790 }
12791
12792 /**
12793 * @brief Read data in engineering unit.[get]
12794 *
12795 * @param ctx communication interface handler.(ptr)
12796 * @param md the sensor conversion parameters.(ptr)
12797 * @retval interface status (MANDATORY: return 0 -> no Error)
12798 *
12799 */
lsm6dso_data_get(stmdev_ctx_t * ctx,stmdev_ctx_t * aux_ctx,lsm6dso_md_t * md,lsm6dso_data_t * data)12800 int32_t lsm6dso_data_get(stmdev_ctx_t *ctx, stmdev_ctx_t *aux_ctx,
12801 lsm6dso_md_t *md, lsm6dso_data_t *data)
12802 {
12803 uint8_t buff[14];
12804 int32_t ret;
12805
12806 uint8_t i;
12807 uint8_t j;
12808 ret = 0;
12809
12810 /* read data */
12811 if (ctx != NULL)
12812 {
12813 ret = lsm6dso_read_reg(ctx, LSM6DSO_OUT_TEMP_L, buff, 14);
12814 }
12815
12816 j = 0;
12817 /* temperature conversion */
12818 data->ui.heat.raw = (int16_t)buff[j + 1U];
12819 data->ui.heat.raw = (((int16_t)data->ui.heat.raw * (int16_t)256) +
12820 (int16_t)buff[j]);
12821 j += 2U;
12822 data->ui.heat.deg_c = lsm6dso_from_lsb_to_celsius((
12823 int16_t)data->ui.heat.raw);
12824
12825 /* angular rate conversion */
12826 for (i = 0U; i < 3U; i++)
12827 {
12828 data->ui.gy.raw[i] = (int16_t)buff[j + 1U];
12829 data->ui.gy.raw[i] = (data->ui.gy.raw[i] * 256) + (int16_t) buff[j];
12830 j += 2U;
12831
12832 switch (md->ui.gy.fs)
12833 {
12834 case LSM6DSO_GY_UI_250dps:
12835 data->ui.gy.mdps[i] = lsm6dso_from_fs250_to_mdps(data->ui.gy.raw[i]);
12836 break;
12837
12838 case LSM6DSO_GY_UI_125dps:
12839 data->ui.gy.mdps[i] = lsm6dso_from_fs125_to_mdps(data->ui.gy.raw[i]);
12840 break;
12841
12842 case LSM6DSO_GY_UI_500dps:
12843 data->ui.gy.mdps[i] = lsm6dso_from_fs500_to_mdps(data->ui.gy.raw[i]);
12844 break;
12845
12846 case LSM6DSO_GY_UI_1000dps:
12847 data->ui.gy.mdps[i] = lsm6dso_from_fs1000_to_mdps(data->ui.gy.raw[i]);
12848 break;
12849
12850 case LSM6DSO_GY_UI_2000dps:
12851 data->ui.gy.mdps[i] = lsm6dso_from_fs2000_to_mdps(data->ui.gy.raw[i]);
12852 break;
12853
12854 default:
12855 data->ui.gy.mdps[i] = 0.0f;
12856 break;
12857 }
12858 }
12859
12860 /* acceleration conversion */
12861 for (i = 0U; i < 3U; i++)
12862 {
12863 data->ui.xl.raw[i] = (int16_t)buff[j + 1U];
12864 data->ui.xl.raw[i] = (data->ui.xl.raw[i] * 256) + (int16_t) buff[j];
12865 j += 2U;
12866
12867 switch (md->ui.xl.fs)
12868 {
12869 case LSM6DSO_XL_UI_2g:
12870 data->ui.xl.mg[i] = lsm6dso_from_fs2_to_mg(data->ui.xl.raw[i]);
12871 break;
12872
12873 case LSM6DSO_XL_UI_4g:
12874 data->ui.xl.mg[i] = lsm6dso_from_fs4_to_mg(data->ui.xl.raw[i]);
12875 break;
12876
12877 case LSM6DSO_XL_UI_8g:
12878 data->ui.xl.mg[i] = lsm6dso_from_fs8_to_mg(data->ui.xl.raw[i]);
12879 break;
12880
12881 case LSM6DSO_XL_UI_16g:
12882 data->ui.xl.mg[i] = lsm6dso_from_fs16_to_mg(data->ui.xl.raw[i]);
12883 break;
12884
12885 default:
12886 data->ui.xl.mg[i] = 0.0f;
12887 break;
12888 }
12889 }
12890
12891 /* read data from ois chain */
12892 if (aux_ctx != NULL)
12893 {
12894 if (ret == 0)
12895 {
12896 ret = lsm6dso_read_reg(aux_ctx, LSM6DSO_OUTX_L_G, buff, 12);
12897 }
12898 }
12899
12900 j = 0;
12901
12902 /* ois angular rate conversion */
12903 for (i = 0U; i < 3U; i++)
12904 {
12905 data->ois.gy.raw[i] = (int16_t) buff[j + 1U];
12906 data->ois.gy.raw[i] = (data->ois.gy.raw[i] * 256) + (int16_t) buff[j];
12907 j += 2U;
12908
12909 switch (md->ois.gy.fs)
12910 {
12911 case LSM6DSO_GY_UI_250dps:
12912 data->ois.gy.mdps[i] = lsm6dso_from_fs250_to_mdps(
12913 data->ois.gy.raw[i]);
12914 break;
12915
12916 case LSM6DSO_GY_UI_125dps:
12917 data->ois.gy.mdps[i] = lsm6dso_from_fs125_to_mdps(
12918 data->ois.gy.raw[i]);
12919 break;
12920
12921 case LSM6DSO_GY_UI_500dps:
12922 data->ois.gy.mdps[i] = lsm6dso_from_fs500_to_mdps(
12923 data->ois.gy.raw[i]);
12924 break;
12925
12926 case LSM6DSO_GY_UI_1000dps:
12927 data->ois.gy.mdps[i] = lsm6dso_from_fs1000_to_mdps(
12928 data->ois.gy.raw[i]);
12929 break;
12930
12931 case LSM6DSO_GY_UI_2000dps:
12932 data->ois.gy.mdps[i] = lsm6dso_from_fs2000_to_mdps(
12933 data->ois.gy.raw[i]);
12934 break;
12935
12936 default:
12937 data->ois.gy.mdps[i] = 0.0f;
12938 break;
12939 }
12940 }
12941
12942 /* ois acceleration conversion */
12943 for (i = 0U; i < 3U; i++)
12944 {
12945 data->ois.xl.raw[i] = (int16_t) buff[j + 1U];
12946 data->ois.xl.raw[i] = (data->ois.xl.raw[i] * 256) + (int16_t) buff[j];
12947 j += 2U;
12948
12949 switch (md->ois.xl.fs)
12950 {
12951 case LSM6DSO_XL_UI_2g:
12952 data->ois.xl.mg[i] = lsm6dso_from_fs2_to_mg(data->ois.xl.raw[i]);
12953 break;
12954
12955 case LSM6DSO_XL_UI_4g:
12956 data->ois.xl.mg[i] = lsm6dso_from_fs4_to_mg(data->ois.xl.raw[i]);
12957 break;
12958
12959 case LSM6DSO_XL_UI_8g:
12960 data->ois.xl.mg[i] = lsm6dso_from_fs8_to_mg(data->ois.xl.raw[i]);
12961 break;
12962
12963 case LSM6DSO_XL_UI_16g:
12964 data->ois.xl.mg[i] = lsm6dso_from_fs16_to_mg(data->ois.xl.raw[i]);
12965 break;
12966
12967 default:
12968 data->ois.xl.mg[i] = 0.0f;
12969 break;
12970 }
12971 }
12972
12973 return ret;
12974 }
12975
12976 /**
12977 * @brief Embedded functions.[set]
12978 *
12979 * @param ctx read / write interface definitions
12980 * @param val change the values of registers
12981 * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
12982 * @retval interface status (MANDATORY: return 0 -> no Error)
12983 *
12984 */
lsm6dso_embedded_sens_set(stmdev_ctx_t * ctx,lsm6dso_emb_sens_t * val)12985 int32_t lsm6dso_embedded_sens_set(stmdev_ctx_t *ctx,
12986 lsm6dso_emb_sens_t *val)
12987 {
12988 lsm6dso_emb_func_en_a_t emb_func_en_a;
12989 lsm6dso_emb_func_en_b_t emb_func_en_b;
12990 int32_t ret;
12991
12992 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
12993
12994 if (ret == 0)
12995 {
12996 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
12997 (uint8_t *)&emb_func_en_a, 1);
12998 }
12999
13000 if (ret == 0)
13001 {
13002 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
13003 (uint8_t *)&emb_func_en_b, 1);
13004 emb_func_en_b.fsm_en = val->fsm;
13005 emb_func_en_a.tilt_en = val->tilt;
13006 emb_func_en_a.pedo_en = val->step;
13007 emb_func_en_b.pedo_adv_en = val->step_adv;
13008 emb_func_en_a.sign_motion_en = val->sig_mot;
13009 emb_func_en_b.fifo_compr_en = val->fifo_compr;
13010 }
13011
13012 if (ret == 0)
13013 {
13014 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
13015 (uint8_t *)&emb_func_en_a, 1);
13016 }
13017
13018 if (ret == 0)
13019 {
13020 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
13021 (uint8_t *)&emb_func_en_b, 1);
13022 }
13023
13024 if (ret == 0)
13025 {
13026 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
13027 }
13028
13029 return ret;
13030 }
13031
13032 /**
13033 * @brief Embedded functions.[get]
13034 *
13035 * @param ctx read / write interface definitions
13036 * @param val get the values of registers
13037 * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
13038 * @retval interface status (MANDATORY: return 0 -> no Error)
13039 *
13040 */
lsm6dso_embedded_sens_get(stmdev_ctx_t * ctx,lsm6dso_emb_sens_t * emb_sens)13041 int32_t lsm6dso_embedded_sens_get(stmdev_ctx_t *ctx,
13042 lsm6dso_emb_sens_t *emb_sens)
13043 {
13044 lsm6dso_emb_func_en_a_t emb_func_en_a;
13045 lsm6dso_emb_func_en_b_t emb_func_en_b;
13046 int32_t ret;
13047
13048 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
13049
13050 if (ret == 0)
13051 {
13052 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
13053 (uint8_t *)&emb_func_en_a, 1);
13054 }
13055
13056 if (ret == 0)
13057 {
13058 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
13059 (uint8_t *)&emb_func_en_b, 1);
13060 emb_sens->fsm = emb_func_en_b.fsm_en;
13061 emb_sens->tilt = emb_func_en_a.tilt_en;
13062 emb_sens->step = emb_func_en_a.pedo_en;
13063 emb_sens->step_adv = emb_func_en_b.pedo_adv_en;
13064 emb_sens->sig_mot = emb_func_en_a.sign_motion_en;
13065 emb_sens->fifo_compr = emb_func_en_b.fifo_compr_en;
13066 }
13067
13068 if (ret == 0)
13069 {
13070 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
13071 }
13072
13073 return ret;
13074 }
13075
13076 /**
13077 * @brief turn off all embedded functions.[get]
13078 *
13079 * @param ctx read / write interface definitions
13080 * @param val get the values of registers
13081 * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
13082 * @retval interface status (MANDATORY: return 0 -> no Error)
13083 *
13084 */
lsm6dso_embedded_sens_off(stmdev_ctx_t * ctx)13085 int32_t lsm6dso_embedded_sens_off(stmdev_ctx_t *ctx)
13086 {
13087 lsm6dso_emb_func_en_a_t emb_func_en_a;
13088 lsm6dso_emb_func_en_b_t emb_func_en_b;
13089 int32_t ret;
13090
13091 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_EMBEDDED_FUNC_BANK);
13092
13093 if (ret == 0)
13094 {
13095 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
13096 (uint8_t *)&emb_func_en_a, 1);
13097 }
13098
13099 if (ret == 0)
13100 {
13101 ret = lsm6dso_read_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
13102 (uint8_t *)&emb_func_en_b, 1);
13103 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
13104 emb_func_en_a.tilt_en = PROPERTY_DISABLE;
13105 emb_func_en_a.pedo_en = PROPERTY_DISABLE;
13106 emb_func_en_b.pedo_adv_en = PROPERTY_DISABLE;
13107 emb_func_en_a.sign_motion_en = PROPERTY_DISABLE;
13108 emb_func_en_b.fifo_compr_en = PROPERTY_DISABLE;
13109 }
13110
13111 if (ret == 0)
13112 {
13113 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_A,
13114 (uint8_t *)&emb_func_en_a, 1);
13115 }
13116
13117 if (ret == 0)
13118 {
13119 ret = lsm6dso_write_reg(ctx, LSM6DSO_EMB_FUNC_EN_B,
13120 (uint8_t *)&emb_func_en_b, 1);
13121 }
13122
13123 if (ret == 0)
13124 {
13125 ret = lsm6dso_mem_bank_set(ctx, LSM6DSO_USER_BANK);
13126 }
13127
13128 return ret;
13129 }
13130
13131 /**
13132 * @}
13133 *
13134 */
13135
13136 /**
13137 * @}
13138 *
13139 */
13140
13141 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
13142
