1 /**
2 ******************************************************************************
3 * @file lsm6dso32x_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSO32X driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dso32x_reg.h"
21
22 /**
23 * @defgroup LSM6DSO32X
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dso32x enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LSM6DSO32X_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx communication interface handler.(ptr)
43 * @param reg first register address to read.
44 * @param data buffer for data read.(ptr)
45 * @param len number of consecutive register to read.
46 * @retval interface status (MANDATORY: return 0 -> no Error).
47 *
48 */
lsm6dso32x_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dso32x_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 ret = ctx->read_reg(ctx->handle, reg, data, len);
56
57 return ret;
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx communication interface handler.(ptr)
64 * @param reg first register address to write.
65 * @param data the buffer contains data to be written.(ptr)
66 * @param len number of consecutive register to write.
67 * @retval interface status (MANDATORY: return 0 -> no Error).
68 *
69 */
lsm6dso32x_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak lsm6dso32x_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
71 uint8_t *data,
72 uint16_t len)
73 {
74 int32_t ret;
75
76 ret = ctx->write_reg(ctx->handle, reg, data, len);
77
78 return ret;
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup LSM6DSO32X_Private_functions
88 * @brief Section collect all the utility functions needed by APIs.
89 * @{
90 *
91 */
92
bytecpy(uint8_t * target,uint8_t * source)93 static void bytecpy(uint8_t *target, uint8_t *source)
94 {
95 if ((target != NULL) && (source != NULL))
96 {
97 *target = *source;
98 }
99 }
100
101 /**
102 * @}
103 *
104 */
105
106 /**
107 * @defgroup LSM6DSO32X_Sensitivity
108 * @brief These functions convert raw-data into engineering units.
109 * @{
110 *
111 */
lsm6dso32x_from_fs4_to_mg(int16_t lsb)112 float_t lsm6dso32x_from_fs4_to_mg(int16_t lsb)
113 {
114 return ((float_t)lsb) * 0.122f;
115 }
116
lsm6dso32x_from_fs8_to_mg(int16_t lsb)117 float_t lsm6dso32x_from_fs8_to_mg(int16_t lsb)
118 {
119 return ((float_t)lsb) * 0.244f;
120 }
121
lsm6dso32x_from_fs16_to_mg(int16_t lsb)122 float_t lsm6dso32x_from_fs16_to_mg(int16_t lsb)
123 {
124 return ((float_t)lsb) * 0.488f;
125 }
126
lsm6dso32x_from_fs32_to_mg(int16_t lsb)127 float_t lsm6dso32x_from_fs32_to_mg(int16_t lsb)
128 {
129 return ((float_t)lsb) * 0.976f;
130 }
131
lsm6dso32x_from_fs125_to_mdps(int16_t lsb)132 float_t lsm6dso32x_from_fs125_to_mdps(int16_t lsb)
133 {
134 return ((float_t)lsb) * 4.375f;
135 }
136
lsm6dso32x_from_fs500_to_mdps(int16_t lsb)137 float_t lsm6dso32x_from_fs500_to_mdps(int16_t lsb)
138 {
139 return ((float_t)lsb) * 17.50f;
140 }
141
lsm6dso32x_from_fs250_to_mdps(int16_t lsb)142 float_t lsm6dso32x_from_fs250_to_mdps(int16_t lsb)
143 {
144 return ((float_t)lsb) * 8.750f;
145 }
146
lsm6dso32x_from_fs1000_to_mdps(int16_t lsb)147 float_t lsm6dso32x_from_fs1000_to_mdps(int16_t lsb)
148 {
149 return ((float_t)lsb) * 35.0f;
150 }
151
lsm6dso32x_from_fs2000_to_mdps(int16_t lsb)152 float_t lsm6dso32x_from_fs2000_to_mdps(int16_t lsb)
153 {
154 return ((float_t)lsb) * 70.0f;
155 }
156
lsm6dso32x_from_lsb_to_celsius(int16_t lsb)157 float_t lsm6dso32x_from_lsb_to_celsius(int16_t lsb)
158 {
159 return (((float_t)lsb / 256.0f) + 25.0f);
160 }
161
lsm6dso32x_from_lsb_to_nsec(int16_t lsb)162 float_t lsm6dso32x_from_lsb_to_nsec(int16_t lsb)
163 {
164 return ((float_t)lsb * 25000.0f);
165 }
166
167 /**
168 * @}
169 *
170 */
171
172 /**
173 * @defgroup LSM6DSO32X_Data_Generation
174 * @brief This section groups all the functions concerning
175 * data generation.
176 *
177 */
178
179 /**
180 * @brief Accelerometer full-scale selection.[set]
181 *
182 * @param ctx read / write interface definitions
183 * @param val change the values of fs_xl in reg CTRL1_XL
184 * @retval interface status (MANDATORY: return 0 -> no Error).
185 *
186 */
lsm6dso32x_xl_full_scale_set(stmdev_ctx_t * ctx,lsm6dso32x_fs_xl_t val)187 int32_t lsm6dso32x_xl_full_scale_set(stmdev_ctx_t *ctx, lsm6dso32x_fs_xl_t val)
188 {
189 lsm6dso32x_ctrl1_xl_t reg;
190 int32_t ret;
191
192 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
193
194 if (ret == 0)
195 {
196 reg.fs_xl = (uint8_t) val;
197 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
198 }
199
200 return ret;
201 }
202
203 /**
204 * @brief Accelerometer full-scale selection.[get]
205 *
206 * @param ctx read / write interface definitions
207 * @param val Get the values of fs_xl in reg CTRL1_XL
208 * @retval interface status (MANDATORY: return 0 -> no Error).
209 *
210 */
lsm6dso32x_xl_full_scale_get(stmdev_ctx_t * ctx,lsm6dso32x_fs_xl_t * val)211 int32_t lsm6dso32x_xl_full_scale_get(stmdev_ctx_t *ctx,
212 lsm6dso32x_fs_xl_t *val)
213 {
214 lsm6dso32x_ctrl1_xl_t reg;
215 int32_t ret;
216
217 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
218
219 switch (reg.fs_xl)
220 {
221 case LSM6DSO32X_16g:
222 *val = LSM6DSO32X_16g;
223 break;
224
225 case LSM6DSO32X_4g:
226 *val = LSM6DSO32X_4g;
227 break;
228
229 case LSM6DSO32X_8g:
230 *val = LSM6DSO32X_8g;
231 break;
232
233 case LSM6DSO32X_32g:
234 *val = LSM6DSO32X_32g;
235 break;
236
237 default:
238 *val = LSM6DSO32X_4g;
239 break;
240 }
241
242 return ret;
243 }
244
245 /**
246 * @brief Accelerometer UI data rate selection.[set]
247 *
248 * @param ctx read / write interface definitions
249 * @param val change the values of odr_xl in reg CTRL1_XL
250 * @retval interface status (MANDATORY: return 0 -> no Error).
251 *
252 */
lsm6dso32x_xl_data_rate_set(stmdev_ctx_t * ctx,lsm6dso32x_odr_xl_t val)253 int32_t lsm6dso32x_xl_data_rate_set(stmdev_ctx_t *ctx, lsm6dso32x_odr_xl_t val)
254 {
255 lsm6dso32x_odr_xl_t odr_xl = val;
256 lsm6dso32x_emb_fsm_enable_t fsm_enable;
257 lsm6dso32x_fsm_odr_t fsm_odr;
258 lsm6dso32x_emb_sens_t emb_sens;
259 lsm6dso32x_mlc_odr_t mlc_odr;
260 lsm6dso32x_ctrl1_xl_t reg;
261 int32_t ret;
262
263 /* Check the Finite State Machine data rate constraints */
264 ret = lsm6dso32x_fsm_enable_get(ctx, &fsm_enable);
265
266 if (ret == 0)
267 {
268 if ((fsm_enable.fsm_enable_a.fsm1_en |
269 fsm_enable.fsm_enable_a.fsm2_en |
270 fsm_enable.fsm_enable_a.fsm3_en |
271 fsm_enable.fsm_enable_a.fsm4_en |
272 fsm_enable.fsm_enable_a.fsm5_en |
273 fsm_enable.fsm_enable_a.fsm6_en |
274 fsm_enable.fsm_enable_a.fsm7_en |
275 fsm_enable.fsm_enable_a.fsm8_en |
276 fsm_enable.fsm_enable_b.fsm9_en |
277 fsm_enable.fsm_enable_b.fsm10_en |
278 fsm_enable.fsm_enable_b.fsm11_en |
279 fsm_enable.fsm_enable_b.fsm12_en |
280 fsm_enable.fsm_enable_b.fsm13_en |
281 fsm_enable.fsm_enable_b.fsm14_en |
282 fsm_enable.fsm_enable_b.fsm15_en |
283 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
284 {
285 ret = lsm6dso32x_fsm_data_rate_get(ctx, &fsm_odr);
286
287 if (ret == 0)
288 {
289 switch (fsm_odr)
290 {
291 case LSM6DSO32X_ODR_FSM_12Hz5:
292 if (val == LSM6DSO32X_XL_ODR_OFF)
293 {
294 odr_xl = LSM6DSO32X_XL_ODR_12Hz5;
295 }
296
297 else
298 {
299 odr_xl = val;
300 }
301
302 break;
303
304 case LSM6DSO32X_ODR_FSM_26Hz:
305 if (val == LSM6DSO32X_XL_ODR_OFF)
306 {
307 odr_xl = LSM6DSO32X_XL_ODR_26Hz;
308 }
309
310 else if (val == LSM6DSO32X_XL_ODR_12Hz5)
311 {
312 odr_xl = LSM6DSO32X_XL_ODR_26Hz;
313 }
314
315 else
316 {
317 odr_xl = val;
318 }
319
320 break;
321
322 case LSM6DSO32X_ODR_FSM_52Hz:
323 if (val == LSM6DSO32X_XL_ODR_OFF)
324 {
325 odr_xl = LSM6DSO32X_XL_ODR_52Hz;
326 }
327
328 else if (val == LSM6DSO32X_XL_ODR_12Hz5)
329 {
330 odr_xl = LSM6DSO32X_XL_ODR_52Hz;
331 }
332
333 else if (val == LSM6DSO32X_XL_ODR_26Hz)
334 {
335 odr_xl = LSM6DSO32X_XL_ODR_52Hz;
336 }
337
338 else
339 {
340 odr_xl = val;
341 }
342
343 break;
344
345 case LSM6DSO32X_ODR_FSM_104Hz:
346 if (val == LSM6DSO32X_XL_ODR_OFF)
347 {
348 odr_xl = LSM6DSO32X_XL_ODR_104Hz;
349 }
350
351 else if (val == LSM6DSO32X_XL_ODR_12Hz5)
352 {
353 odr_xl = LSM6DSO32X_XL_ODR_104Hz;
354 }
355
356 else if (val == LSM6DSO32X_XL_ODR_26Hz)
357 {
358 odr_xl = LSM6DSO32X_XL_ODR_104Hz;
359 }
360
361 else if (val == LSM6DSO32X_XL_ODR_52Hz)
362 {
363 odr_xl = LSM6DSO32X_XL_ODR_104Hz;
364 }
365
366 else
367 {
368 odr_xl = val;
369 }
370
371 break;
372
373 default:
374 odr_xl = val;
375 break;
376 }
377 }
378 }
379 }
380
381 /* Check the Machine Learning Core data rate constraints */
382 emb_sens.mlc = PROPERTY_DISABLE;
383
384 if (ret == 0)
385 {
386 ret = lsm6dso32x_embedded_sens_get(ctx, &emb_sens);
387
388 if ((ret == 0) && (emb_sens.mlc == PROPERTY_ENABLE))
389 {
390 ret = lsm6dso32x_mlc_data_rate_get(ctx, &mlc_odr);
391
392 if (ret == 0)
393 {
394 switch (mlc_odr)
395 {
396 case LSM6DSO32X_ODR_PRGS_12Hz5:
397 if (val == LSM6DSO32X_XL_ODR_OFF)
398 {
399 odr_xl = LSM6DSO32X_XL_ODR_12Hz5;
400 }
401
402 else
403 {
404 odr_xl = val;
405 }
406
407 break;
408
409 case LSM6DSO32X_ODR_PRGS_26Hz:
410 if (val == LSM6DSO32X_XL_ODR_OFF)
411 {
412 odr_xl = LSM6DSO32X_XL_ODR_26Hz;
413 }
414
415 else if (val == LSM6DSO32X_XL_ODR_12Hz5)
416 {
417 odr_xl = LSM6DSO32X_XL_ODR_26Hz;
418 }
419
420 else
421 {
422 odr_xl = val;
423 }
424
425 break;
426
427 case LSM6DSO32X_ODR_PRGS_52Hz:
428 if (val == LSM6DSO32X_XL_ODR_OFF)
429 {
430 odr_xl = LSM6DSO32X_XL_ODR_52Hz;
431 }
432
433 else if (val == LSM6DSO32X_XL_ODR_12Hz5)
434 {
435 odr_xl = LSM6DSO32X_XL_ODR_52Hz;
436 }
437
438 else if (val == LSM6DSO32X_XL_ODR_26Hz)
439 {
440 odr_xl = LSM6DSO32X_XL_ODR_52Hz;
441 }
442
443 else
444 {
445 odr_xl = val;
446 }
447
448 break;
449
450 case LSM6DSO32X_ODR_PRGS_104Hz:
451 if (val == LSM6DSO32X_XL_ODR_OFF)
452 {
453 odr_xl = LSM6DSO32X_XL_ODR_104Hz;
454 }
455
456 else if (val == LSM6DSO32X_XL_ODR_12Hz5)
457 {
458 odr_xl = LSM6DSO32X_XL_ODR_104Hz;
459 }
460
461 else if (val == LSM6DSO32X_XL_ODR_26Hz)
462 {
463 odr_xl = LSM6DSO32X_XL_ODR_104Hz;
464 }
465
466 else if (val == LSM6DSO32X_XL_ODR_52Hz)
467 {
468 odr_xl = LSM6DSO32X_XL_ODR_104Hz;
469 }
470
471 else
472 {
473 odr_xl = val;
474 }
475
476 break;
477
478 default:
479 odr_xl = val;
480 break;
481 }
482 }
483 }
484 }
485
486 if (ret == 0)
487 {
488 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
489 }
490
491 if (ret == 0)
492 {
493 reg.odr_xl = (uint8_t) odr_xl;
494 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
495 }
496
497 return ret;
498 }
499
500 /**
501 * @brief Accelerometer UI data rate selection.[get]
502 *
503 * @param ctx read / write interface definitions
504 * @param val Get the values of odr_xl in reg CTRL1_XL
505 * @retval interface status (MANDATORY: return 0 -> no Error).
506 *
507 */
lsm6dso32x_xl_data_rate_get(stmdev_ctx_t * ctx,lsm6dso32x_odr_xl_t * val)508 int32_t lsm6dso32x_xl_data_rate_get(stmdev_ctx_t *ctx, lsm6dso32x_odr_xl_t *val)
509 {
510 lsm6dso32x_ctrl1_xl_t reg;
511 int32_t ret;
512
513 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
514
515 switch (reg.odr_xl)
516 {
517 case LSM6DSO32X_XL_ODR_OFF:
518 *val = LSM6DSO32X_XL_ODR_OFF;
519 break;
520
521 case LSM6DSO32X_XL_ODR_12Hz5:
522 *val = LSM6DSO32X_XL_ODR_12Hz5;
523 break;
524
525 case LSM6DSO32X_XL_ODR_26Hz:
526 *val = LSM6DSO32X_XL_ODR_26Hz;
527 break;
528
529 case LSM6DSO32X_XL_ODR_52Hz:
530 *val = LSM6DSO32X_XL_ODR_52Hz;
531 break;
532
533 case LSM6DSO32X_XL_ODR_104Hz:
534 *val = LSM6DSO32X_XL_ODR_104Hz;
535 break;
536
537 case LSM6DSO32X_XL_ODR_208Hz:
538 *val = LSM6DSO32X_XL_ODR_208Hz;
539 break;
540
541 case LSM6DSO32X_XL_ODR_417Hz:
542 *val = LSM6DSO32X_XL_ODR_417Hz;
543 break;
544
545 case LSM6DSO32X_XL_ODR_833Hz:
546 *val = LSM6DSO32X_XL_ODR_833Hz;
547 break;
548
549 case LSM6DSO32X_XL_ODR_1667Hz:
550 *val = LSM6DSO32X_XL_ODR_1667Hz;
551 break;
552
553 case LSM6DSO32X_XL_ODR_3333Hz:
554 *val = LSM6DSO32X_XL_ODR_3333Hz;
555 break;
556
557 case LSM6DSO32X_XL_ODR_6667Hz:
558 *val = LSM6DSO32X_XL_ODR_6667Hz;
559 break;
560
561 case LSM6DSO32X_XL_ODR_1Hz6:
562 *val = LSM6DSO32X_XL_ODR_1Hz6;
563 break;
564
565 default:
566 *val = LSM6DSO32X_XL_ODR_OFF;
567 break;
568 }
569
570 return ret;
571 }
572
573 /**
574 * @brief Gyroscope UI chain full-scale selection.[set]
575 *
576 * @param ctx read / write interface definitions
577 * @param val change the values of fs_g in reg CTRL2_G
578 * @retval interface status (MANDATORY: return 0 -> no Error).
579 *
580 */
lsm6dso32x_gy_full_scale_set(stmdev_ctx_t * ctx,lsm6dso32x_fs_g_t val)581 int32_t lsm6dso32x_gy_full_scale_set(stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t val)
582 {
583 lsm6dso32x_ctrl2_g_t reg;
584 int32_t ret;
585
586 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1);
587
588 if (ret == 0)
589 {
590 reg.fs_g = (uint8_t) val;
591 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1);
592 }
593
594 return ret;
595 }
596
597 /**
598 * @brief Gyroscope UI chain full-scale selection.[get]
599 *
600 * @param ctx read / write interface definitions
601 * @param val Get the values of fs_g in reg CTRL2_G
602 * @retval interface status (MANDATORY: return 0 -> no Error).
603 *
604 */
lsm6dso32x_gy_full_scale_get(stmdev_ctx_t * ctx,lsm6dso32x_fs_g_t * val)605 int32_t lsm6dso32x_gy_full_scale_get(stmdev_ctx_t *ctx, lsm6dso32x_fs_g_t *val)
606 {
607 lsm6dso32x_ctrl2_g_t reg;
608 int32_t ret;
609
610 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1);
611
612 switch (reg.fs_g)
613 {
614 case LSM6DSO32X_250dps:
615 *val = LSM6DSO32X_250dps;
616 break;
617
618 case LSM6DSO32X_125dps:
619 *val = LSM6DSO32X_125dps;
620 break;
621
622 case LSM6DSO32X_500dps:
623 *val = LSM6DSO32X_500dps;
624 break;
625
626 case LSM6DSO32X_1000dps:
627 *val = LSM6DSO32X_1000dps;
628 break;
629
630 case LSM6DSO32X_2000dps:
631 *val = LSM6DSO32X_2000dps;
632 break;
633
634 default:
635 *val = LSM6DSO32X_250dps;
636 break;
637 }
638
639 return ret;
640 }
641
642 /**
643 * @brief Gyroscope UI data rate selection.[set]
644 *
645 * @param ctx read / write interface definitions
646 * @param val change the values of odr_g in reg CTRL2_G
647 * @retval interface status (MANDATORY: return 0 -> no Error).
648 *
649 */
lsm6dso32x_gy_data_rate_set(stmdev_ctx_t * ctx,lsm6dso32x_odr_g_t val)650 int32_t lsm6dso32x_gy_data_rate_set(stmdev_ctx_t *ctx, lsm6dso32x_odr_g_t val)
651 {
652 lsm6dso32x_odr_g_t odr_gy = val;
653 lsm6dso32x_emb_fsm_enable_t fsm_enable;
654 lsm6dso32x_fsm_odr_t fsm_odr;
655 lsm6dso32x_emb_sens_t emb_sens;
656 lsm6dso32x_mlc_odr_t mlc_odr;
657 lsm6dso32x_ctrl2_g_t reg;
658 int32_t ret;
659
660 /* Check the Finite State Machine data rate constraints */
661 ret = lsm6dso32x_fsm_enable_get(ctx, &fsm_enable);
662
663 if (ret == 0)
664 {
665 if ((fsm_enable.fsm_enable_a.fsm1_en |
666 fsm_enable.fsm_enable_a.fsm2_en |
667 fsm_enable.fsm_enable_a.fsm3_en |
668 fsm_enable.fsm_enable_a.fsm4_en |
669 fsm_enable.fsm_enable_a.fsm5_en |
670 fsm_enable.fsm_enable_a.fsm6_en |
671 fsm_enable.fsm_enable_a.fsm7_en |
672 fsm_enable.fsm_enable_a.fsm8_en |
673 fsm_enable.fsm_enable_b.fsm9_en |
674 fsm_enable.fsm_enable_b.fsm10_en |
675 fsm_enable.fsm_enable_b.fsm11_en |
676 fsm_enable.fsm_enable_b.fsm12_en |
677 fsm_enable.fsm_enable_b.fsm13_en |
678 fsm_enable.fsm_enable_b.fsm14_en |
679 fsm_enable.fsm_enable_b.fsm15_en |
680 fsm_enable.fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
681 {
682 ret = lsm6dso32x_fsm_data_rate_get(ctx, &fsm_odr);
683
684 if (ret == 0)
685 {
686 switch (fsm_odr)
687 {
688 case LSM6DSO32X_ODR_FSM_12Hz5:
689 if (val == LSM6DSO32X_GY_ODR_OFF)
690 {
691 odr_gy = LSM6DSO32X_GY_ODR_12Hz5;
692 }
693
694 else
695 {
696 odr_gy = val;
697 }
698
699 break;
700
701 case LSM6DSO32X_ODR_FSM_26Hz:
702 if (val == LSM6DSO32X_GY_ODR_OFF)
703 {
704 odr_gy = LSM6DSO32X_GY_ODR_26Hz;
705 }
706
707 else if (val == LSM6DSO32X_GY_ODR_12Hz5)
708 {
709 odr_gy = LSM6DSO32X_GY_ODR_26Hz;
710 }
711
712 else
713 {
714 odr_gy = val;
715 }
716
717 break;
718
719 case LSM6DSO32X_ODR_FSM_52Hz:
720 if (val == LSM6DSO32X_GY_ODR_OFF)
721 {
722 odr_gy = LSM6DSO32X_GY_ODR_52Hz;
723 }
724
725 else if (val == LSM6DSO32X_GY_ODR_12Hz5)
726 {
727 odr_gy = LSM6DSO32X_GY_ODR_52Hz;
728 }
729
730 else if (val == LSM6DSO32X_GY_ODR_26Hz)
731 {
732 odr_gy = LSM6DSO32X_GY_ODR_52Hz;
733 }
734
735 else
736 {
737 odr_gy = val;
738 }
739
740 break;
741
742 case LSM6DSO32X_ODR_FSM_104Hz:
743 if (val == LSM6DSO32X_GY_ODR_OFF)
744 {
745 odr_gy = LSM6DSO32X_GY_ODR_104Hz;
746 }
747
748 else if (val == LSM6DSO32X_GY_ODR_12Hz5)
749 {
750 odr_gy = LSM6DSO32X_GY_ODR_104Hz;
751 }
752
753 else if (val == LSM6DSO32X_GY_ODR_26Hz)
754 {
755 odr_gy = LSM6DSO32X_GY_ODR_104Hz;
756 }
757
758 else if (val == LSM6DSO32X_GY_ODR_52Hz)
759 {
760 odr_gy = LSM6DSO32X_GY_ODR_104Hz;
761 }
762
763 else
764 {
765 odr_gy = val;
766 }
767
768 break;
769
770 default:
771 odr_gy = val;
772 break;
773 }
774 }
775 }
776 }
777
778 /* Check the Machine Learning Core data rate constraints */
779 emb_sens.mlc = PROPERTY_DISABLE;
780
781 if (ret == 0)
782 {
783 ret = lsm6dso32x_embedded_sens_get(ctx, &emb_sens);
784
785 if (emb_sens.mlc == PROPERTY_ENABLE)
786 {
787 ret = lsm6dso32x_mlc_data_rate_get(ctx, &mlc_odr);
788
789 if (ret == 0)
790 {
791 switch (mlc_odr)
792 {
793 case LSM6DSO32X_ODR_PRGS_12Hz5:
794 if (val == LSM6DSO32X_GY_ODR_OFF)
795 {
796 odr_gy = LSM6DSO32X_GY_ODR_12Hz5;
797 }
798
799 else
800 {
801 odr_gy = val;
802 }
803
804 break;
805
806 case LSM6DSO32X_ODR_PRGS_26Hz:
807 if (val == LSM6DSO32X_GY_ODR_OFF)
808 {
809 odr_gy = LSM6DSO32X_GY_ODR_26Hz;
810 }
811
812 else if (val == LSM6DSO32X_GY_ODR_12Hz5)
813 {
814 odr_gy = LSM6DSO32X_GY_ODR_26Hz;
815 }
816
817 else
818 {
819 odr_gy = val;
820 }
821
822 break;
823
824 case LSM6DSO32X_ODR_PRGS_52Hz:
825 if (val == LSM6DSO32X_GY_ODR_OFF)
826 {
827 odr_gy = LSM6DSO32X_GY_ODR_52Hz;
828 }
829
830 else if (val == LSM6DSO32X_GY_ODR_12Hz5)
831 {
832 odr_gy = LSM6DSO32X_GY_ODR_52Hz;
833 }
834
835 else if (val == LSM6DSO32X_GY_ODR_26Hz)
836 {
837 odr_gy = LSM6DSO32X_GY_ODR_52Hz;
838 }
839
840 else
841 {
842 odr_gy = val;
843 }
844
845 break;
846
847 case LSM6DSO32X_ODR_PRGS_104Hz:
848 if (val == LSM6DSO32X_GY_ODR_OFF)
849 {
850 odr_gy = LSM6DSO32X_GY_ODR_104Hz;
851 }
852
853 else if (val == LSM6DSO32X_GY_ODR_12Hz5)
854 {
855 odr_gy = LSM6DSO32X_GY_ODR_104Hz;
856 }
857
858 else if (val == LSM6DSO32X_GY_ODR_26Hz)
859 {
860 odr_gy = LSM6DSO32X_GY_ODR_104Hz;
861 }
862
863 else if (val == LSM6DSO32X_GY_ODR_52Hz)
864 {
865 odr_gy = LSM6DSO32X_GY_ODR_104Hz;
866 }
867
868 else
869 {
870 odr_gy = val;
871 }
872
873 break;
874
875 default:
876 odr_gy = val;
877 break;
878 }
879 }
880 }
881 }
882
883 if (ret == 0)
884 {
885 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1);
886 }
887
888 if (ret == 0)
889 {
890 reg.odr_g = (uint8_t) odr_gy;
891 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1);
892 }
893
894 return ret;
895 }
896
897 /**
898 * @brief Gyroscope UI data rate selection.[get]
899 *
900 * @param ctx read / write interface definitions
901 * @param val Get the values of odr_g in reg CTRL2_G
902 * @retval interface status (MANDATORY: return 0 -> no Error).
903 *
904 */
lsm6dso32x_gy_data_rate_get(stmdev_ctx_t * ctx,lsm6dso32x_odr_g_t * val)905 int32_t lsm6dso32x_gy_data_rate_get(stmdev_ctx_t *ctx, lsm6dso32x_odr_g_t *val)
906 {
907 lsm6dso32x_ctrl2_g_t reg;
908 int32_t ret;
909
910 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL2_G, (uint8_t *)®, 1);
911
912 switch (reg.odr_g)
913 {
914 case LSM6DSO32X_GY_ODR_OFF:
915 *val = LSM6DSO32X_GY_ODR_OFF;
916 break;
917
918 case LSM6DSO32X_GY_ODR_12Hz5:
919 *val = LSM6DSO32X_GY_ODR_12Hz5;
920 break;
921
922 case LSM6DSO32X_GY_ODR_26Hz:
923 *val = LSM6DSO32X_GY_ODR_26Hz;
924 break;
925
926 case LSM6DSO32X_GY_ODR_52Hz:
927 *val = LSM6DSO32X_GY_ODR_52Hz;
928 break;
929
930 case LSM6DSO32X_GY_ODR_104Hz:
931 *val = LSM6DSO32X_GY_ODR_104Hz;
932 break;
933
934 case LSM6DSO32X_GY_ODR_208Hz:
935 *val = LSM6DSO32X_GY_ODR_208Hz;
936 break;
937
938 case LSM6DSO32X_GY_ODR_417Hz:
939 *val = LSM6DSO32X_GY_ODR_417Hz;
940 break;
941
942 case LSM6DSO32X_GY_ODR_833Hz:
943 *val = LSM6DSO32X_GY_ODR_833Hz;
944 break;
945
946 case LSM6DSO32X_GY_ODR_1667Hz:
947 *val = LSM6DSO32X_GY_ODR_1667Hz;
948 break;
949
950 case LSM6DSO32X_GY_ODR_3333Hz:
951 *val = LSM6DSO32X_GY_ODR_3333Hz;
952 break;
953
954 case LSM6DSO32X_GY_ODR_6667Hz:
955 *val = LSM6DSO32X_GY_ODR_6667Hz;
956 break;
957
958 default:
959 *val = LSM6DSO32X_GY_ODR_OFF;
960 break;
961 }
962
963 return ret;
964 }
965
966 /**
967 * @brief Block data update.[set]
968 *
969 * @param ctx read / write interface definitions
970 * @param val change the values of bdu in reg CTRL3_C
971 * @retval interface status (MANDATORY: return 0 -> no Error).
972 *
973 */
lsm6dso32x_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)974 int32_t lsm6dso32x_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
975 {
976 lsm6dso32x_ctrl3_c_t reg;
977 int32_t ret;
978
979 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
980
981 if (ret == 0)
982 {
983 reg.bdu = val;
984 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
985 }
986
987 return ret;
988 }
989
990 /**
991 * @brief Block data update.[get]
992 *
993 * @param ctx read / write interface definitions
994 * @param val change the values of bdu in reg CTRL3_C
995 * @retval interface status (MANDATORY: return 0 -> no Error).
996 *
997 */
lsm6dso32x_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)998 int32_t lsm6dso32x_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
999 {
1000 lsm6dso32x_ctrl3_c_t reg;
1001 int32_t ret;
1002
1003 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
1004 *val = reg.bdu;
1005
1006 return ret;
1007 }
1008
1009 /**
1010 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
1011 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
1012 *
1013 * @param ctx read / write interface definitions
1014 * @param val change the values of usr_off_w in reg CTRL6_C
1015 * @retval interface status (MANDATORY: return 0 -> no Error).
1016 *
1017 */
lsm6dso32x_xl_offset_weight_set(stmdev_ctx_t * ctx,lsm6dso32x_usr_off_w_t val)1018 int32_t lsm6dso32x_xl_offset_weight_set(stmdev_ctx_t *ctx,
1019 lsm6dso32x_usr_off_w_t val)
1020 {
1021 lsm6dso32x_ctrl6_c_t reg;
1022 int32_t ret;
1023
1024 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
1025
1026 if (ret == 0)
1027 {
1028 reg.usr_off_w = (uint8_t)val;
1029 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
1030 }
1031
1032 return ret;
1033 }
1034
1035 /**
1036 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
1037 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
1038 *
1039 * @param ctx read / write interface definitions
1040 * @param val Get the values of usr_off_w in reg CTRL6_C
1041 * @retval interface status (MANDATORY: return 0 -> no Error).
1042 *
1043 */
lsm6dso32x_xl_offset_weight_get(stmdev_ctx_t * ctx,lsm6dso32x_usr_off_w_t * val)1044 int32_t lsm6dso32x_xl_offset_weight_get(stmdev_ctx_t *ctx,
1045 lsm6dso32x_usr_off_w_t *val)
1046 {
1047 lsm6dso32x_ctrl6_c_t reg;
1048 int32_t ret;
1049
1050 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
1051
1052 switch (reg.usr_off_w)
1053 {
1054 case LSM6DSO32X_LSb_1mg:
1055 *val = LSM6DSO32X_LSb_1mg;
1056 break;
1057
1058 case LSM6DSO32X_LSb_16mg:
1059 *val = LSM6DSO32X_LSb_16mg;
1060 break;
1061
1062 default:
1063 *val = LSM6DSO32X_LSb_1mg;
1064 break;
1065 }
1066
1067 return ret;
1068 }
1069
1070 /**
1071 * @brief Accelerometer power mode.[set]
1072 *
1073 * @param ctx read / write interface definitions
1074 * @param val change the values of xl_hm_mode in
1075 * reg CTRL6_C
1076 * @retval interface status (MANDATORY: return 0 -> no Error).
1077 *
1078 */
lsm6dso32x_xl_power_mode_set(stmdev_ctx_t * ctx,lsm6dso32x_xl_hm_mode_t val)1079 int32_t lsm6dso32x_xl_power_mode_set(stmdev_ctx_t *ctx,
1080 lsm6dso32x_xl_hm_mode_t val)
1081 {
1082 lsm6dso32x_ctrl5_c_t ctrl5_c;
1083 lsm6dso32x_ctrl6_c_t ctrl6_c;
1084 int32_t ret;
1085
1086 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C,
1087 (uint8_t *) &ctrl5_c, 1);
1088
1089 if (ret == 0)
1090 {
1091 ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x02U) >> 1;
1092 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL5_C,
1093 (uint8_t *) &ctrl5_c, 1);
1094 }
1095
1096 if (ret == 0)
1097 {
1098 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C,
1099 (uint8_t *) &ctrl6_c, 1);
1100 }
1101
1102 if (ret == 0)
1103 {
1104 ctrl6_c.xl_hm_mode = (uint8_t)val & 0x01U;
1105 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL6_C,
1106 (uint8_t *) &ctrl6_c, 1);
1107 }
1108
1109 return ret;
1110 }
1111
1112 /**
1113 * @brief Accelerometer power mode.[get]
1114 *
1115 * @param ctx read / write interface definitions
1116 * @param val Get the values of xl_hm_mode in reg CTRL6_C
1117 * @retval interface status (MANDATORY: return 0 -> no Error).
1118 *
1119 */
lsm6dso32x_xl_power_mode_get(stmdev_ctx_t * ctx,lsm6dso32x_xl_hm_mode_t * val)1120 int32_t lsm6dso32x_xl_power_mode_get(stmdev_ctx_t *ctx,
1121 lsm6dso32x_xl_hm_mode_t *val)
1122 {
1123 lsm6dso32x_ctrl5_c_t ctrl5_c;
1124 lsm6dso32x_ctrl6_c_t ctrl6_c;
1125 int32_t ret;
1126
1127 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C,
1128 (uint8_t *) &ctrl5_c, 1);
1129
1130 if (ret == 0)
1131 {
1132 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C,
1133 (uint8_t *) &ctrl6_c, 1);
1134
1135 switch ((ctrl5_c.xl_ulp_en << 1) | ctrl6_c.xl_hm_mode)
1136 {
1137 case LSM6DSO32X_HIGH_PERFORMANCE_MD:
1138 *val = LSM6DSO32X_HIGH_PERFORMANCE_MD;
1139 break;
1140
1141 case LSM6DSO32X_LOW_NORMAL_POWER_MD:
1142 *val = LSM6DSO32X_LOW_NORMAL_POWER_MD;
1143 break;
1144
1145 case LSM6DSO32X_ULTRA_LOW_POWER_MD:
1146 *val = LSM6DSO32X_ULTRA_LOW_POWER_MD;
1147 break;
1148
1149 default:
1150 *val = LSM6DSO32X_HIGH_PERFORMANCE_MD;
1151 break;
1152 }
1153 }
1154
1155 return ret;
1156 }
1157
1158 /**
1159 * @brief Operating mode for gyroscope.[set]
1160 *
1161 * @param ctx read / write interface definitions
1162 * @param val change the values of g_hm_mode in reg CTRL7_G
1163 * @retval interface status (MANDATORY: return 0 -> no Error).
1164 *
1165 */
lsm6dso32x_gy_power_mode_set(stmdev_ctx_t * ctx,lsm6dso32x_g_hm_mode_t val)1166 int32_t lsm6dso32x_gy_power_mode_set(stmdev_ctx_t *ctx,
1167 lsm6dso32x_g_hm_mode_t val)
1168 {
1169 lsm6dso32x_ctrl7_g_t reg;
1170 int32_t ret;
1171
1172 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
1173
1174 if (ret == 0)
1175 {
1176 reg.g_hm_mode = (uint8_t)val;
1177 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
1178 }
1179
1180 return ret;
1181 }
1182
1183 /**
1184 * @brief Operating mode for gyroscope.[get]
1185 *
1186 * @param ctx read / write interface definitions
1187 * @param val Get the values of g_hm_mode in reg CTRL7_G
1188 * @retval interface status (MANDATORY: return 0 -> no Error).
1189 *
1190 */
lsm6dso32x_gy_power_mode_get(stmdev_ctx_t * ctx,lsm6dso32x_g_hm_mode_t * val)1191 int32_t lsm6dso32x_gy_power_mode_get(stmdev_ctx_t *ctx,
1192 lsm6dso32x_g_hm_mode_t *val)
1193 {
1194 lsm6dso32x_ctrl7_g_t reg;
1195 int32_t ret;
1196
1197 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
1198
1199 switch (reg.g_hm_mode)
1200 {
1201 case LSM6DSO32X_GY_HIGH_PERFORMANCE:
1202 *val = LSM6DSO32X_GY_HIGH_PERFORMANCE;
1203 break;
1204
1205 case LSM6DSO32X_GY_NORMAL:
1206 *val = LSM6DSO32X_GY_NORMAL;
1207 break;
1208
1209 default:
1210 *val = LSM6DSO32X_GY_HIGH_PERFORMANCE;
1211 break;
1212 }
1213
1214 return ret;
1215 }
1216
1217 /**
1218 * @brief The STATUS_REG register is read by the primary interface.[get]
1219 *
1220 * @param ctx read / write interface definitions
1221 * @param val register STATUS_REG
1222 * @retval interface status (MANDATORY: return 0 -> no Error).
1223 *
1224 */
lsm6dso32x_status_reg_get(stmdev_ctx_t * ctx,lsm6dso32x_status_reg_t * val)1225 int32_t lsm6dso32x_status_reg_get(stmdev_ctx_t *ctx,
1226 lsm6dso32x_status_reg_t *val)
1227 {
1228 int32_t ret;
1229
1230 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_REG, (uint8_t *) val, 1);
1231
1232 return ret;
1233 }
1234
1235 /**
1236 * @brief Accelerometer new data available.[get]
1237 *
1238 * @param ctx read / write interface definitions
1239 * @param val change the values of xlda in reg STATUS_REG
1240 * @retval interface status (MANDATORY: return 0 -> no Error).
1241 *
1242 */
lsm6dso32x_xl_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1243 int32_t lsm6dso32x_xl_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
1244 {
1245 lsm6dso32x_status_reg_t reg;
1246 int32_t ret;
1247
1248 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_REG, (uint8_t *)®, 1);
1249 *val = reg.xlda;
1250
1251 return ret;
1252 }
1253
1254 /**
1255 * @brief Gyroscope new data available.[get]
1256 *
1257 * @param ctx read / write interface definitions
1258 * @param val change the values of gda in reg STATUS_REG
1259 * @retval interface status (MANDATORY: return 0 -> no Error).
1260 *
1261 */
lsm6dso32x_gy_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1262 int32_t lsm6dso32x_gy_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
1263 {
1264 lsm6dso32x_status_reg_t reg;
1265 int32_t ret;
1266
1267 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_REG, (uint8_t *)®, 1);
1268 *val = reg.gda;
1269
1270 return ret;
1271 }
1272
1273 /**
1274 * @brief Temperature new data available.[get]
1275 *
1276 * @param ctx read / write interface definitions
1277 * @param val change the values of tda in reg STATUS_REG
1278 * @retval interface status (MANDATORY: return 0 -> no Error).
1279 *
1280 */
lsm6dso32x_temp_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)1281 int32_t lsm6dso32x_temp_flag_data_ready_get(stmdev_ctx_t *ctx, uint8_t *val)
1282 {
1283 lsm6dso32x_status_reg_t reg;
1284 int32_t ret;
1285
1286 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_REG, (uint8_t *)®, 1);
1287 *val = reg.tda;
1288
1289 return ret;
1290 }
1291
1292 /**
1293 * @brief Accelerometer X-axis user offset correction expressed in
1294 * two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1295 * The value must be in the range [-127 127].[set]
1296 *
1297 * @param ctx read / write interface definitions
1298 * @param buff buffer that contains data to write
1299 * @retval interface status (MANDATORY: return 0 -> no Error).
1300 *
1301 */
lsm6dso32x_xl_usr_offset_x_set(stmdev_ctx_t * ctx,uint8_t * buff)1302 int32_t lsm6dso32x_xl_usr_offset_x_set(stmdev_ctx_t *ctx, uint8_t *buff)
1303 {
1304 int32_t ret;
1305
1306 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_X_OFS_USR, buff, 1);
1307
1308 return ret;
1309 }
1310
1311 /**
1312 * @brief Accelerometer X-axis user offset correction expressed in two’s
1313 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1314 * The value must be in the range [-127 127].[get]
1315 *
1316 * @param ctx read / write interface definitions
1317 * @param buff buffer that stores data read
1318 * @retval interface status (MANDATORY: return 0 -> no Error).
1319 *
1320 */
lsm6dso32x_xl_usr_offset_x_get(stmdev_ctx_t * ctx,uint8_t * buff)1321 int32_t lsm6dso32x_xl_usr_offset_x_get(stmdev_ctx_t *ctx, uint8_t *buff)
1322 {
1323 int32_t ret;
1324
1325 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_X_OFS_USR, buff, 1);
1326
1327 return ret;
1328 }
1329
1330 /**
1331 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1332 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1333 * The value must be in the range [-127 127].[set]
1334 *
1335 * @param ctx read / write interface definitions
1336 * @param buff buffer that contains data to write
1337 * @retval interface status (MANDATORY: return 0 -> no Error).
1338 *
1339 */
lsm6dso32x_xl_usr_offset_y_set(stmdev_ctx_t * ctx,uint8_t * buff)1340 int32_t lsm6dso32x_xl_usr_offset_y_set(stmdev_ctx_t *ctx, uint8_t *buff)
1341 {
1342 int32_t ret;
1343
1344 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_Y_OFS_USR, buff, 1);
1345
1346 return ret;
1347 }
1348
1349 /**
1350 * @brief Accelerometer Y-axis user offset correction expressed in two’s
1351 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1352 * The value must be in the range [-127 127].[get]
1353 *
1354 * @param ctx read / write interface definitions
1355 * @param buff buffer that stores data read
1356 * @retval interface status (MANDATORY: return 0 -> no Error).
1357 *
1358 */
lsm6dso32x_xl_usr_offset_y_get(stmdev_ctx_t * ctx,uint8_t * buff)1359 int32_t lsm6dso32x_xl_usr_offset_y_get(stmdev_ctx_t *ctx, uint8_t *buff)
1360 {
1361 int32_t ret;
1362
1363 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_Y_OFS_USR, buff, 1);
1364
1365 return ret;
1366 }
1367
1368 /**
1369 * @brief Accelerometer Z-axis user offset correction expressed in two’s
1370 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1371 * The value must be in the range [-127 127].[set]
1372 *
1373 * @param ctx read / write interface definitions
1374 * @param buff buffer that contains data to write
1375 * @retval interface status (MANDATORY: return 0 -> no Error).
1376 *
1377 */
lsm6dso32x_xl_usr_offset_z_set(stmdev_ctx_t * ctx,uint8_t * buff)1378 int32_t lsm6dso32x_xl_usr_offset_z_set(stmdev_ctx_t *ctx, uint8_t *buff)
1379 {
1380 int32_t ret;
1381
1382 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_Z_OFS_USR, buff, 1);
1383
1384 return ret;
1385 }
1386
1387 /**
1388 * @brief Accelerometer Z-axis user offset correction expressed in two’s
1389 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1390 * The value must be in the range [-127 127].[get]
1391 *
1392 * @param ctx read / write interface definitions
1393 * @param buff buffer that stores data read
1394 * @retval interface status (MANDATORY: return 0 -> no Error).
1395 *
1396 */
lsm6dso32x_xl_usr_offset_z_get(stmdev_ctx_t * ctx,uint8_t * buff)1397 int32_t lsm6dso32x_xl_usr_offset_z_get(stmdev_ctx_t *ctx, uint8_t *buff)
1398 {
1399 int32_t ret;
1400
1401 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_Z_OFS_USR, buff, 1);
1402
1403 return ret;
1404 }
1405
1406 /**
1407 * @brief Enables user offset on out.[set]
1408 *
1409 * @param ctx read / write interface definitions
1410 * @param val change the values of usr_off_on_out in reg CTRL7_G
1411 * @retval interface status (MANDATORY: return 0 -> no Error).
1412 *
1413 */
lsm6dso32x_xl_usr_offset_set(stmdev_ctx_t * ctx,uint8_t val)1414 int32_t lsm6dso32x_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
1415 {
1416 lsm6dso32x_ctrl7_g_t reg;
1417 int32_t ret;
1418
1419 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
1420
1421 if (ret == 0)
1422 {
1423 reg.usr_off_on_out = val;
1424 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
1425 }
1426
1427 return ret;
1428 }
1429
1430 /**
1431 * @brief User offset on out flag.[get]
1432 *
1433 * @param ctx read / write interface definitions
1434 * @param val values of usr_off_on_out in reg CTRL7_G
1435 * @retval interface status (MANDATORY: return 0 -> no Error).
1436 *
1437 */
lsm6dso32x_xl_usr_offset_get(stmdev_ctx_t * ctx,uint8_t * val)1438 int32_t lsm6dso32x_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
1439 {
1440 lsm6dso32x_ctrl7_g_t reg;
1441 int32_t ret;
1442
1443 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
1444 *val = reg.usr_off_on_out;
1445
1446 return ret;
1447 }
1448
1449 /**
1450 * @}
1451 *
1452 */
1453
1454 /**
1455 * @defgroup LSM6DSO32X_Timestamp
1456 * @brief This section groups all the functions that manage the
1457 * timestamp generation.
1458 * @{
1459 *
1460 */
1461
1462 /**
1463 * @brief Reset timestamp counter.[set]
1464 *
1465 * @param ctx Read / write interface definitions.(ptr)
1466 * @retval Interface status (MANDATORY: return 0 -> no Error).
1467 * @retval interface status (MANDATORY: return 0 -> no Error).
1468 *
1469 */
lsm6dso32x_timestamp_rst(stmdev_ctx_t * ctx)1470 int32_t lsm6dso32x_timestamp_rst(stmdev_ctx_t *ctx)
1471 {
1472 uint8_t rst_val = 0xAA;
1473 return lsm6dso32x_write_reg(ctx, LSM6DSO32X_TIMESTAMP2, &rst_val, 1);
1474 }
1475
1476 /**
1477 * @brief Enables timestamp counter.[set]
1478 *
1479 * @param ctx read / write interface definitions
1480 * @param val change the values of timestamp_en in reg CTRL10_C
1481 * @retval interface status (MANDATORY: return 0 -> no Error).
1482 *
1483 */
lsm6dso32x_timestamp_set(stmdev_ctx_t * ctx,uint8_t val)1484 int32_t lsm6dso32x_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
1485 {
1486 lsm6dso32x_ctrl10_c_t reg;
1487 int32_t ret;
1488
1489 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL10_C, (uint8_t *)®, 1);
1490
1491 if (ret == 0)
1492 {
1493 reg.timestamp_en = val;
1494 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL10_C, (uint8_t *)®, 1);
1495 }
1496
1497 return ret;
1498 }
1499
1500 /**
1501 * @brief Enables timestamp counter.[get]
1502 *
1503 * @param ctx read / write interface definitions
1504 * @param val change the values of timestamp_en in reg CTRL10_C
1505 * @retval interface status (MANDATORY: return 0 -> no Error).
1506 *
1507 */
lsm6dso32x_timestamp_get(stmdev_ctx_t * ctx,uint8_t * val)1508 int32_t lsm6dso32x_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
1509 {
1510 lsm6dso32x_ctrl10_c_t reg;
1511 int32_t ret;
1512
1513 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL10_C, (uint8_t *)®, 1);
1514 *val = reg.timestamp_en;
1515
1516 return ret;
1517 }
1518
1519 /**
1520 * @brief Timestamp first data output register (r).
1521 * The value is expressed as a 32-bit word and the bit
1522 * resolution is 25 μs.[get]
1523 *
1524 * @param ctx read / write interface definitions
1525 * @param buff buffer that stores data read
1526 * @retval interface status (MANDATORY: return 0 -> no Error).
1527 *
1528 */
lsm6dso32x_timestamp_raw_get(stmdev_ctx_t * ctx,uint32_t * val)1529 int32_t lsm6dso32x_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
1530 {
1531 uint8_t buff[4];
1532 int32_t ret;
1533
1534 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TIMESTAMP0, buff, 4);
1535 *val = buff[3];
1536 *val = (*val * 256U) + buff[2];
1537 *val = (*val * 256U) + buff[1];
1538 *val = (*val * 256U) + buff[0];
1539
1540 return ret;
1541 }
1542
1543 /**
1544 * @}
1545 *
1546 */
1547
1548 /**
1549 * @defgroup LSM6DSO32X_Data output
1550 * @brief This section groups all the data output functions.
1551 * @{
1552 *
1553 */
1554
1555 /**
1556 * @brief Circular burst-mode (rounding) read of the output
1557 * registers.[set]
1558 *
1559 * @param ctx read / write interface definitions
1560 * @param val change the values of rounding in reg CTRL5_C
1561 * @retval interface status (MANDATORY: return 0 -> no Error).
1562 *
1563 */
lsm6dso32x_rounding_mode_set(stmdev_ctx_t * ctx,lsm6dso32x_rounding_t val)1564 int32_t lsm6dso32x_rounding_mode_set(stmdev_ctx_t *ctx,
1565 lsm6dso32x_rounding_t val)
1566 {
1567 lsm6dso32x_ctrl5_c_t reg;
1568 int32_t ret;
1569
1570 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
1571
1572 if (ret == 0)
1573 {
1574 reg.rounding = (uint8_t)val;
1575 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
1576 }
1577
1578 return ret;
1579 }
1580
1581 /**
1582 * @brief Gyroscope UI chain full-scale selection.[get]
1583 *
1584 * @param ctx read / write interface definitions
1585 * @param val Get the values of rounding in reg CTRL5_C
1586 * @retval interface status (MANDATORY: return 0 -> no Error).
1587 *
1588 */
lsm6dso32x_rounding_mode_get(stmdev_ctx_t * ctx,lsm6dso32x_rounding_t * val)1589 int32_t lsm6dso32x_rounding_mode_get(stmdev_ctx_t *ctx,
1590 lsm6dso32x_rounding_t *val)
1591 {
1592 lsm6dso32x_ctrl5_c_t reg;
1593 int32_t ret;
1594
1595 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
1596
1597 switch (reg.rounding)
1598 {
1599 case LSM6DSO32X_NO_ROUND:
1600 *val = LSM6DSO32X_NO_ROUND;
1601 break;
1602
1603 case LSM6DSO32X_ROUND_XL:
1604 *val = LSM6DSO32X_ROUND_XL;
1605 break;
1606
1607 case LSM6DSO32X_ROUND_GY:
1608 *val = LSM6DSO32X_ROUND_GY;
1609 break;
1610
1611 case LSM6DSO32X_ROUND_GY_XL:
1612 *val = LSM6DSO32X_ROUND_GY_XL;
1613 break;
1614
1615 default:
1616 *val = LSM6DSO32X_NO_ROUND;
1617 break;
1618 }
1619
1620 return ret;
1621 }
1622
1623 /**
1624 * @brief Temperature data output register (r).
1625 * L and H registers together express a 16-bit word in two’s
1626 * complement.[get]
1627 *
1628 * @param ctx read / write interface definitions
1629 * @param buff buffer that stores data read
1630 * @retval interface status (MANDATORY: return 0 -> no Error).
1631 *
1632 */
lsm6dso32x_temperature_raw_get(stmdev_ctx_t * ctx,int16_t * val)1633 int32_t lsm6dso32x_temperature_raw_get(stmdev_ctx_t *ctx,
1634 int16_t *val)
1635 {
1636 uint8_t buff[2];
1637 int32_t ret;
1638
1639 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_OUT_TEMP_L, buff, 2);
1640 *val = (int16_t)buff[1];
1641 *val = (*val * 256) + (int16_t)buff[0];
1642
1643 return ret;
1644 }
1645
1646 /**
1647 * @brief Angular rate sensor. The value is expressed as a 16-bit
1648 * word in two’s complement.[get]
1649 *
1650 * @param ctx read / write interface definitions
1651 * @param buff buffer that stores data read
1652 * @retval interface status (MANDATORY: return 0 -> no Error).
1653 *
1654 */
lsm6dso32x_angular_rate_raw_get(stmdev_ctx_t * ctx,int16_t * val)1655 int32_t lsm6dso32x_angular_rate_raw_get(stmdev_ctx_t *ctx,
1656 int16_t *val)
1657 {
1658 uint8_t buff[6];
1659 int32_t ret;
1660
1661 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_OUTX_L_G, buff, 6);
1662 val[0] = (int16_t)buff[1];
1663 val[0] = (val[0] * 256) + (int16_t)buff[0];
1664 val[1] = (int16_t)buff[3];
1665 val[1] = (val[1] * 256) + (int16_t)buff[2];
1666 val[2] = (int16_t)buff[5];
1667 val[2] = (val[2] * 256) + (int16_t)buff[4];
1668
1669 return ret;
1670 }
1671
1672 /**
1673 * @brief Linear acceleration output register.
1674 * The value is expressed as a 16-bit word in two’s complement.[get]
1675 *
1676 * @param ctx read / write interface definitions
1677 * @param buff buffer that stores data read
1678 * @retval interface status (MANDATORY: return 0 -> no Error).
1679 *
1680 */
lsm6dso32x_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)1681 int32_t lsm6dso32x_acceleration_raw_get(stmdev_ctx_t *ctx,
1682 int16_t *val)
1683 {
1684 uint8_t buff[6];
1685 int32_t ret;
1686
1687 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_OUTX_L_A, buff, 6);
1688 val[0] = (int16_t)buff[1];
1689 val[0] = (val[0] * 256) + (int16_t)buff[0];
1690 val[1] = (int16_t)buff[3];
1691 val[1] = (val[1] * 256) + (int16_t)buff[2];
1692 val[2] = (int16_t)buff[5];
1693 val[2] = (val[2] * 256) + (int16_t)buff[4];
1694
1695 return ret;
1696 }
1697
1698 /**
1699 * @brief FIFO data output [get]
1700 *
1701 * @param ctx read / write interface definitions
1702 * @param buff buffer that stores data read
1703 * @retval interface status (MANDATORY: return 0 -> no Error).
1704 *
1705 */
lsm6dso32x_fifo_out_raw_get(stmdev_ctx_t * ctx,uint8_t * buff)1706 int32_t lsm6dso32x_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
1707 {
1708 int32_t ret;
1709
1710 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_DATA_OUT_X_L, buff, 6);
1711
1712 return ret;
1713 }
1714
1715 /**
1716 * @brief Step counter output register.[get]
1717 *
1718 * @param ctx read / write interface definitions
1719 * @param buff buffer that stores data read
1720 * @retval interface status (MANDATORY: return 0 -> no Error).
1721 *
1722 */
lsm6dso32x_number_of_steps_get(stmdev_ctx_t * ctx,uint16_t * val)1723 int32_t lsm6dso32x_number_of_steps_get(stmdev_ctx_t *ctx,
1724 uint16_t *val)
1725 {
1726 uint8_t buff[2];
1727 int32_t ret;
1728
1729 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
1730
1731 if (ret == 0)
1732 {
1733 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STEP_COUNTER_L, buff, 2);
1734 *val = buff[1];
1735 *val = (*val * 256U) + buff[0];
1736 }
1737
1738 if (ret == 0)
1739 {
1740 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
1741 }
1742
1743 return ret;
1744 }
1745
1746 /**
1747 * @brief Reset step counter register.[get]
1748 *
1749 * @param ctx read / write interface definitions
1750 * @retval interface status (MANDATORY: return 0 -> no Error).
1751 *
1752 */
lsm6dso32x_steps_reset(stmdev_ctx_t * ctx)1753 int32_t lsm6dso32x_steps_reset(stmdev_ctx_t *ctx)
1754 {
1755 lsm6dso32x_emb_func_src_t reg;
1756 int32_t ret;
1757
1758 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
1759
1760 if (ret == 0)
1761 {
1762 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_SRC,
1763 (uint8_t *)®, 1);
1764 }
1765
1766 if (ret == 0)
1767 {
1768 reg.pedo_rst_step = PROPERTY_ENABLE;
1769 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_SRC,
1770 (uint8_t *)®, 1);
1771 }
1772
1773 if (ret == 0)
1774 {
1775 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
1776 }
1777
1778 return ret;
1779 }
1780
1781 /**
1782 * @brief prgsens_out: [get] Output value of all MLCx decision trees.
1783 *
1784 * @param ctx_t *ctx: read / write interface definitions
1785 * @param uint8_t * : buffer that stores data read
1786 * @retval interface status (MANDATORY: return 0 -> no Error).
1787 *
1788 */
lsm6dso32x_mlc_out_get(stmdev_ctx_t * ctx,uint8_t * buff)1789 int32_t lsm6dso32x_mlc_out_get(stmdev_ctx_t *ctx, uint8_t *buff)
1790 {
1791 int32_t ret;
1792
1793 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
1794
1795 if (ret == 0)
1796 {
1797 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MLC0_SRC, buff, 8);
1798 }
1799
1800 if (ret == 0)
1801 {
1802 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
1803 }
1804
1805 return ret;
1806 }
1807
1808 /**
1809 * @}
1810 *
1811 */
1812
1813 /**
1814 * @defgroup LSM6DSO32X_common
1815 * @brief This section groups common useful functions.
1816 * @{
1817 *
1818 */
1819
1820 /**
1821 * @brief Difference in percentage of the effective ODR(and timestamp rate)
1822 * with respect to the typical.
1823 * Step: 0.15%. 8-bit format, 2's complement.[set]
1824 *
1825 * @param ctx read / write interface definitions
1826 * @param val change the values of freq_fine in reg
1827 * INTERNAL_FREQ_FINE
1828 * @retval interface status (MANDATORY: return 0 -> no Error).
1829 *
1830 */
lsm6dso32x_odr_cal_reg_set(stmdev_ctx_t * ctx,uint8_t val)1831 int32_t lsm6dso32x_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
1832 {
1833 lsm6dso32x_internal_freq_fine_t reg;
1834 int32_t ret;
1835
1836 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INTERNAL_FREQ_FINE,
1837 (uint8_t *)®, 1);
1838
1839 if (ret == 0)
1840 {
1841 reg.freq_fine = val;
1842 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INTERNAL_FREQ_FINE,
1843 (uint8_t *)®, 1);
1844 }
1845
1846 return ret;
1847 }
1848
1849 /**
1850 * @brief Difference in percentage of the effective ODR(and timestamp rate)
1851 * with respect to the typical.
1852 * Step: 0.15%. 8-bit format, 2's complement.[get]
1853 *
1854 * @param ctx read / write interface definitions
1855 * @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE
1856 * @retval interface status (MANDATORY: return 0 -> no Error).
1857 *
1858 */
lsm6dso32x_odr_cal_reg_get(stmdev_ctx_t * ctx,uint8_t * val)1859 int32_t lsm6dso32x_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
1860 {
1861 lsm6dso32x_internal_freq_fine_t reg;
1862 int32_t ret;
1863
1864 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INTERNAL_FREQ_FINE,
1865 (uint8_t *)®, 1);
1866 *val = reg.freq_fine;
1867
1868 return ret;
1869 }
1870
1871
1872 /**
1873 * @brief Enable access to the embedded functions/sensor
1874 * hub configuration registers.[set]
1875 *
1876 * @param ctx read / write interface definitions
1877 * @param val change the values of reg_access in
1878 * reg FUNC_CFG_ACCESS
1879 * @retval interface status (MANDATORY: return 0 -> no Error).
1880 *
1881 */
lsm6dso32x_mem_bank_set(stmdev_ctx_t * ctx,lsm6dso32x_reg_access_t val)1882 int32_t lsm6dso32x_mem_bank_set(stmdev_ctx_t *ctx,
1883 lsm6dso32x_reg_access_t val)
1884 {
1885 lsm6dso32x_func_cfg_access_t reg;
1886 int32_t ret;
1887
1888 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FUNC_CFG_ACCESS,
1889 (uint8_t *)®, 1);
1890
1891 if (ret == 0)
1892 {
1893 reg.reg_access = (uint8_t)val;
1894 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FUNC_CFG_ACCESS,
1895 (uint8_t *)®, 1);
1896 }
1897
1898 return ret;
1899 }
1900
1901 /**
1902 * @brief Enable access to the embedded functions/sensor
1903 * hub configuration registers.[get]
1904 *
1905 * @param ctx read / write interface definitions
1906 * @param val Get the values of reg_access in
1907 * reg FUNC_CFG_ACCESS
1908 * @retval interface status (MANDATORY: return 0 -> no Error).
1909 *
1910 */
lsm6dso32x_mem_bank_get(stmdev_ctx_t * ctx,lsm6dso32x_reg_access_t * val)1911 int32_t lsm6dso32x_mem_bank_get(stmdev_ctx_t *ctx,
1912 lsm6dso32x_reg_access_t *val)
1913 {
1914 lsm6dso32x_func_cfg_access_t reg;
1915 int32_t ret;
1916
1917 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FUNC_CFG_ACCESS,
1918 (uint8_t *)®, 1);
1919
1920 switch (reg.reg_access)
1921 {
1922 case LSM6DSO32X_USER_BANK:
1923 *val = LSM6DSO32X_USER_BANK;
1924 break;
1925
1926 case LSM6DSO32X_SENSOR_HUB_BANK:
1927 *val = LSM6DSO32X_SENSOR_HUB_BANK;
1928 break;
1929
1930 case LSM6DSO32X_EMBEDDED_FUNC_BANK:
1931 *val = LSM6DSO32X_EMBEDDED_FUNC_BANK;
1932 break;
1933
1934 default:
1935 *val = LSM6DSO32X_USER_BANK;
1936 break;
1937 }
1938
1939 return ret;
1940 }
1941
1942 /**
1943 * @brief Write a line(byte) in a page.[set]
1944 *
1945 * @param ctx read / write interface definitions
1946 * @param uint8_t address: page line address
1947 * @param val value to write
1948 * @retval interface status (MANDATORY: return 0 -> no Error).
1949 *
1950 */
lsm6dso32x_ln_pg_write_byte(stmdev_ctx_t * ctx,uint16_t address,uint8_t * val)1951 int32_t lsm6dso32x_ln_pg_write_byte(stmdev_ctx_t *ctx,
1952 uint16_t address,
1953 uint8_t *val)
1954 {
1955 lsm6dso32x_page_rw_t page_rw;
1956 lsm6dso32x_page_sel_t page_sel;
1957 lsm6dso32x_page_address_t page_address;
1958 int32_t ret;
1959
1960 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
1961
1962 if (ret == 0)
1963 {
1964 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
1965 (uint8_t *) &page_rw, 1);
1966 }
1967
1968 if (ret == 0)
1969 {
1970 page_rw.page_rw = 0x02; /* page_write enable */
1971 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
1972 (uint8_t *) &page_rw, 1);
1973 }
1974
1975 if (ret == 0)
1976 {
1977 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_SEL,
1978 (uint8_t *) &page_sel, 1);
1979 }
1980
1981 if (ret == 0)
1982 {
1983 page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
1984 page_sel.not_used_01 = 1;
1985 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL,
1986 (uint8_t *) &page_sel, 1);
1987 }
1988
1989 if (ret == 0)
1990 {
1991 page_address.page_addr = (uint8_t)address & 0xFFU;
1992 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_ADDRESS,
1993 (uint8_t *)&page_address, 1);
1994 }
1995
1996 if (ret == 0)
1997 {
1998 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_VALUE, val, 1);
1999 }
2000
2001 if (ret == 0)
2002 {
2003 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
2004 (uint8_t *) &page_rw, 1);
2005 }
2006
2007 if (ret == 0)
2008 {
2009 page_rw.page_rw = 0x00; /* page_write disable */
2010 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
2011 (uint8_t *) &page_rw, 1);
2012 }
2013
2014 if (ret == 0)
2015 {
2016 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
2017 }
2018
2019 return ret;
2020 }
2021
2022 /**
2023 * @brief Write buffer in a page.[set]
2024 *
2025 * @param ctx read / write interface definitions
2026 * @param uint8_t address: page line address
2027 * @param uint8_t *buf: buffer to write
2028 * @param uint8_t len: buffer len
2029 * @retval interface status (MANDATORY: return 0 -> no Error).
2030 *
2031 */
lsm6dso32x_ln_pg_write(stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)2032 int32_t lsm6dso32x_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
2033 uint8_t *buf, uint8_t len)
2034 {
2035 lsm6dso32x_page_rw_t page_rw;
2036 lsm6dso32x_page_sel_t page_sel;
2037 lsm6dso32x_page_address_t page_address;
2038 int32_t ret;
2039
2040 uint8_t msb, lsb;
2041 uint8_t i ;
2042 msb = ((uint8_t)(address >> 8) & 0x0FU);
2043 lsb = (uint8_t)address & 0xFFU;
2044 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
2045
2046 if (ret == 0)
2047 {
2048 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
2049 (uint8_t *) &page_rw, 1);
2050 }
2051
2052 if (ret == 0)
2053 {
2054 page_rw.page_rw = 0x02; /* page_write enable*/
2055 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
2056 (uint8_t *) &page_rw, 1);
2057 }
2058
2059 if (ret == 0)
2060 {
2061 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_SEL,
2062 (uint8_t *) &page_sel, 1);
2063 }
2064
2065 if (ret == 0)
2066 {
2067 page_sel.page_sel = msb;
2068 page_sel.not_used_01 = 1;
2069 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL,
2070 (uint8_t *) &page_sel, 1);
2071 }
2072
2073 if (ret == 0)
2074 {
2075 page_address.page_addr = lsb;
2076 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_ADDRESS,
2077 (uint8_t *)&page_address, 1);
2078 }
2079
2080 if (ret == 0)
2081 {
2082 for (i = 0; ((i < len) && (ret == 0)); i++)
2083 {
2084 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_VALUE, &buf[i], 1);
2085 lsb++;
2086
2087 /* Check if page wrap */
2088 if ((lsb == 0x00U) && (ret == 0))
2089 {
2090 msb++;
2091 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_SEL,
2092 (uint8_t *)&page_sel, 1);
2093
2094 if (ret == 0)
2095 {
2096 page_sel.page_sel = msb;
2097 page_sel.not_used_01 = 1;
2098 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL,
2099 (uint8_t *)&page_sel, 1);
2100 }
2101 }
2102 }
2103 }
2104
2105 page_sel.page_sel = 0;
2106 page_sel.not_used_01 = 1;
2107 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL,
2108 (uint8_t *) &page_sel, 1);
2109
2110 if (ret == 0)
2111 {
2112 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
2113 (uint8_t *) &page_rw, 1);
2114 }
2115
2116 if (ret == 0)
2117 {
2118 page_rw.page_rw = 0x00; /* page_write disable */
2119 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
2120 (uint8_t *) &page_rw, 1);
2121 }
2122
2123 if (ret == 0)
2124 {
2125 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
2126 }
2127
2128 return ret;
2129 }
2130
2131 /**
2132 * @brief Read a line(byte) in a page.[get]
2133 *
2134 * @param ctx read / write interface definitions
2135 * @param uint8_t address: page line address
2136 * @param val read value
2137 * @retval interface status (MANDATORY: return 0 -> no Error).
2138 *
2139 */
lsm6dso32x_ln_pg_read_byte(stmdev_ctx_t * ctx,uint16_t address,uint8_t * val)2140 int32_t lsm6dso32x_ln_pg_read_byte(stmdev_ctx_t *ctx,
2141 uint16_t address,
2142 uint8_t *val)
2143 {
2144 lsm6dso32x_page_rw_t page_rw;
2145 lsm6dso32x_page_sel_t page_sel;
2146 lsm6dso32x_page_address_t page_address;
2147 int32_t ret;
2148
2149 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
2150
2151 if (ret == 0)
2152 {
2153 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
2154 (uint8_t *) &page_rw, 1);
2155 }
2156
2157 if (ret == 0)
2158 {
2159 page_rw.page_rw = 0x01; /* page_read enable*/
2160 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
2161 (uint8_t *) &page_rw, 1);
2162 }
2163
2164 if (ret == 0)
2165 {
2166 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_SEL,
2167 (uint8_t *) &page_sel, 1);
2168 }
2169
2170 if (ret == 0)
2171 {
2172 page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
2173 page_sel.not_used_01 = 1;
2174 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_SEL,
2175 (uint8_t *) &page_sel, 1);
2176 }
2177
2178 if (ret == 0)
2179 {
2180 page_address.page_addr = (uint8_t)address & 0x00FFU;
2181 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_ADDRESS,
2182 (uint8_t *)&page_address, 1);
2183 }
2184
2185 if (ret == 0)
2186 {
2187 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_VALUE, val, 1);
2188 }
2189
2190 if (ret == 0)
2191 {
2192 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
2193 (uint8_t *) &page_rw, 1);
2194 }
2195
2196 if (ret == 0)
2197 {
2198 page_rw.page_rw = 0x00; /* page_read disable */
2199 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
2200 (uint8_t *) &page_rw, 1);
2201 }
2202
2203 if (ret == 0)
2204 {
2205 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
2206 }
2207
2208 return ret;
2209 }
2210
2211 /**
2212 * @brief Data-ready pulsed / letched mode.[set]
2213 *
2214 * @param ctx read / write interface definitions
2215 * @param val change the values of
2216 * dataready_pulsed in
2217 * reg COUNTER_BDR_REG1
2218 * @retval interface status (MANDATORY: return 0 -> no Error).
2219 *
2220 */
lsm6dso32x_data_ready_mode_set(stmdev_ctx_t * ctx,lsm6dso32x_dataready_pulsed_t val)2221 int32_t lsm6dso32x_data_ready_mode_set(stmdev_ctx_t *ctx,
2222 lsm6dso32x_dataready_pulsed_t val)
2223 {
2224 lsm6dso32x_counter_bdr_reg1_t reg;
2225 int32_t ret;
2226
2227 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
2228 (uint8_t *)®, 1);
2229
2230 if (ret == 0)
2231 {
2232 reg.dataready_pulsed = (uint8_t)val;
2233 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
2234 (uint8_t *)®, 1);
2235 }
2236
2237 return ret;
2238 }
2239
2240 /**
2241 * @brief Data-ready pulsed / letched mode.[get]
2242 *
2243 * @param ctx read / write interface definitions
2244 * @param val Get the values of
2245 * dataready_pulsed in
2246 * reg COUNTER_BDR_REG1
2247 * @retval interface status (MANDATORY: return 0 -> no Error).
2248 *
2249 */
lsm6dso32x_data_ready_mode_get(stmdev_ctx_t * ctx,lsm6dso32x_dataready_pulsed_t * val)2250 int32_t lsm6dso32x_data_ready_mode_get(stmdev_ctx_t *ctx,
2251 lsm6dso32x_dataready_pulsed_t *val)
2252 {
2253 lsm6dso32x_counter_bdr_reg1_t reg;
2254 int32_t ret;
2255
2256 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
2257 (uint8_t *)®, 1);
2258
2259 switch (reg.dataready_pulsed)
2260 {
2261 case LSM6DSO32X_DRDY_LATCHED:
2262 *val = LSM6DSO32X_DRDY_LATCHED;
2263 break;
2264
2265 case LSM6DSO32X_DRDY_PULSED:
2266 *val = LSM6DSO32X_DRDY_PULSED;
2267 break;
2268
2269 default:
2270 *val = LSM6DSO32X_DRDY_LATCHED;
2271 break;
2272 }
2273
2274 return ret;
2275 }
2276
2277 /**
2278 * @brief Device "Who am I".[get]
2279 *
2280 * @param ctx read / write interface definitions
2281 * @param buff buffer that stores data read
2282 * @retval interface status (MANDATORY: return 0 -> no Error).
2283 *
2284 */
lsm6dso32x_device_id_get(stmdev_ctx_t * ctx,uint8_t * buff)2285 int32_t lsm6dso32x_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
2286 {
2287 int32_t ret;
2288
2289 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WHO_AM_I, buff, 1);
2290
2291 return ret;
2292 }
2293
2294 /**
2295 * @brief Software reset. Restore the default values
2296 * in user registers[set]
2297 *
2298 * @param ctx read / write interface definitions
2299 * @param val change the values of sw_reset in reg CTRL3_C
2300 * @retval interface status (MANDATORY: return 0 -> no Error).
2301 *
2302 */
lsm6dso32x_reset_set(stmdev_ctx_t * ctx,uint8_t val)2303 int32_t lsm6dso32x_reset_set(stmdev_ctx_t *ctx, uint8_t val)
2304 {
2305 lsm6dso32x_ctrl3_c_t reg;
2306 int32_t ret;
2307
2308 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
2309
2310 if (ret == 0)
2311 {
2312 reg.sw_reset = val;
2313 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
2314 }
2315
2316 return ret;
2317 }
2318
2319 /**
2320 * @brief Software reset. Restore the default values in user registers.[get]
2321 *
2322 * @param ctx read / write interface definitions
2323 * @param val change the values of sw_reset in reg CTRL3_C
2324 * @retval interface status (MANDATORY: return 0 -> no Error).
2325 *
2326 */
lsm6dso32x_reset_get(stmdev_ctx_t * ctx,uint8_t * val)2327 int32_t lsm6dso32x_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
2328 {
2329 lsm6dso32x_ctrl3_c_t reg;
2330 int32_t ret;
2331
2332 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
2333 *val = reg.sw_reset;
2334
2335 return ret;
2336 }
2337
2338 /**
2339 * @brief Register address automatically incremented during a multiple byte
2340 * access with a serial interface.[set]
2341 *
2342 * @param ctx read / write interface definitions
2343 * @param val change the values of if_inc in reg CTRL3_C
2344 * @retval interface status (MANDATORY: return 0 -> no Error).
2345 *
2346 */
lsm6dso32x_auto_increment_set(stmdev_ctx_t * ctx,uint8_t val)2347 int32_t lsm6dso32x_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
2348 {
2349 lsm6dso32x_ctrl3_c_t reg;
2350 int32_t ret;
2351
2352 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
2353
2354 if (ret == 0)
2355 {
2356 reg.if_inc = val;
2357 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
2358 }
2359
2360 return ret;
2361 }
2362
2363 /**
2364 * @brief Register address automatically incremented during a multiple byte
2365 * access with a serial interface.[get]
2366 *
2367 * @param ctx read / write interface definitions
2368 * @param val change the values of if_inc in reg CTRL3_C
2369 * @retval interface status (MANDATORY: return 0 -> no Error).
2370 *
2371 */
lsm6dso32x_auto_increment_get(stmdev_ctx_t * ctx,uint8_t * val)2372 int32_t lsm6dso32x_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
2373 {
2374 lsm6dso32x_ctrl3_c_t reg;
2375 int32_t ret;
2376
2377 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
2378 *val = reg.if_inc;
2379
2380 return ret;
2381 }
2382
2383 /**
2384 * @brief Reboot memory content. Reload the calibration parameters.[set]
2385 *
2386 * @param ctx read / write interface definitions
2387 * @param val change the values of boot in reg CTRL3_C
2388 * @retval interface status (MANDATORY: return 0 -> no Error).
2389 *
2390 */
lsm6dso32x_boot_set(stmdev_ctx_t * ctx,uint8_t val)2391 int32_t lsm6dso32x_boot_set(stmdev_ctx_t *ctx, uint8_t val)
2392 {
2393 lsm6dso32x_ctrl3_c_t reg;
2394 int32_t ret;
2395
2396 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
2397
2398 if (ret == 0)
2399 {
2400 reg.boot = val;
2401 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
2402 }
2403
2404 return ret;
2405 }
2406
2407 /**
2408 * @brief Reboot memory content. Reload the calibration parameters.[get]
2409 *
2410 * @param ctx read / write interface definitions
2411 * @param val change the values of boot in reg CTRL3_C
2412 * @retval interface status (MANDATORY: return 0 -> no Error).
2413 *
2414 */
lsm6dso32x_boot_get(stmdev_ctx_t * ctx,uint8_t * val)2415 int32_t lsm6dso32x_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
2416 {
2417 lsm6dso32x_ctrl3_c_t reg;
2418 int32_t ret;
2419
2420 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
2421 *val = reg.boot;
2422
2423 return ret;
2424 }
2425
2426 /**
2427 * @brief Linear acceleration sensor self-test enable.[set]
2428 *
2429 * @param ctx read / write interface definitions
2430 * @param val change the values of st_xl in reg CTRL5_C
2431 * @retval interface status (MANDATORY: return 0 -> no Error).
2432 *
2433 */
lsm6dso32x_xl_self_test_set(stmdev_ctx_t * ctx,lsm6dso32x_st_xl_t val)2434 int32_t lsm6dso32x_xl_self_test_set(stmdev_ctx_t *ctx,
2435 lsm6dso32x_st_xl_t val)
2436 {
2437 lsm6dso32x_ctrl5_c_t reg;
2438 int32_t ret;
2439
2440 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
2441
2442 if (ret == 0)
2443 {
2444 reg.st_xl = (uint8_t)val;
2445 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
2446 }
2447
2448 return ret;
2449 }
2450
2451 /**
2452 * @brief Linear acceleration sensor self-test enable.[get]
2453 *
2454 * @param ctx read / write interface definitions
2455 * @param val Get the values of st_xl in reg CTRL5_C
2456 * @retval interface status (MANDATORY: return 0 -> no Error).
2457 *
2458 */
lsm6dso32x_xl_self_test_get(stmdev_ctx_t * ctx,lsm6dso32x_st_xl_t * val)2459 int32_t lsm6dso32x_xl_self_test_get(stmdev_ctx_t *ctx,
2460 lsm6dso32x_st_xl_t *val)
2461 {
2462 lsm6dso32x_ctrl5_c_t reg;
2463 int32_t ret;
2464
2465 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
2466
2467 switch (reg.st_xl)
2468 {
2469 case LSM6DSO32X_XL_ST_DISABLE:
2470 *val = LSM6DSO32X_XL_ST_DISABLE;
2471 break;
2472
2473 case LSM6DSO32X_XL_ST_POSITIVE:
2474 *val = LSM6DSO32X_XL_ST_POSITIVE;
2475 break;
2476
2477 case LSM6DSO32X_XL_ST_NEGATIVE:
2478 *val = LSM6DSO32X_XL_ST_NEGATIVE;
2479 break;
2480
2481 default:
2482 *val = LSM6DSO32X_XL_ST_DISABLE;
2483 break;
2484 }
2485
2486 return ret;
2487 }
2488
2489 /**
2490 * @brief Angular rate sensor self-test enable.[set]
2491 *
2492 * @param ctx read / write interface definitions
2493 * @param val change the values of st_g in reg CTRL5_C
2494 * @retval interface status (MANDATORY: return 0 -> no Error).
2495 *
2496 */
lsm6dso32x_gy_self_test_set(stmdev_ctx_t * ctx,lsm6dso32x_st_g_t val)2497 int32_t lsm6dso32x_gy_self_test_set(stmdev_ctx_t *ctx,
2498 lsm6dso32x_st_g_t val)
2499 {
2500 lsm6dso32x_ctrl5_c_t reg;
2501 int32_t ret;
2502
2503 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
2504
2505 if (ret == 0)
2506 {
2507 reg.st_g = (uint8_t)val;
2508 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
2509 }
2510
2511 return ret;
2512 }
2513
2514 /**
2515 * @brief Angular rate sensor self-test enable.[get]
2516 *
2517 * @param ctx read / write interface definitions
2518 * @param val Get the values of st_g in reg CTRL5_C
2519 * @retval interface status (MANDATORY: return 0 -> no Error).
2520 *
2521 */
lsm6dso32x_gy_self_test_get(stmdev_ctx_t * ctx,lsm6dso32x_st_g_t * val)2522 int32_t lsm6dso32x_gy_self_test_get(stmdev_ctx_t *ctx,
2523 lsm6dso32x_st_g_t *val)
2524 {
2525 lsm6dso32x_ctrl5_c_t reg;
2526 int32_t ret;
2527
2528 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C, (uint8_t *)®, 1);
2529
2530 switch (reg.st_g)
2531 {
2532 case LSM6DSO32X_GY_ST_DISABLE:
2533 *val = LSM6DSO32X_GY_ST_DISABLE;
2534 break;
2535
2536 case LSM6DSO32X_GY_ST_POSITIVE:
2537 *val = LSM6DSO32X_GY_ST_POSITIVE;
2538 break;
2539
2540 case LSM6DSO32X_GY_ST_NEGATIVE:
2541 *val = LSM6DSO32X_GY_ST_NEGATIVE;
2542 break;
2543
2544 default:
2545 *val = LSM6DSO32X_GY_ST_DISABLE;
2546 break;
2547 }
2548
2549 return ret;
2550 }
2551
2552 /**
2553 * @}
2554 *
2555 */
2556
2557 /**
2558 * @defgroup LSM6DSO32X_filters
2559 * @brief This section group all the functions concerning the
2560 * filters configuration
2561 * @{
2562 *
2563 */
2564
2565 /**
2566 * @brief Accelerometer output from LPF2 filtering stage selection.[set]
2567 *
2568 * @param ctx read / write interface definitions
2569 * @param val change the values of lpf2_xl_en in reg CTRL1_XL
2570 * @retval interface status (MANDATORY: return 0 -> no Error).
2571 *
2572 */
lsm6dso32x_xl_filter_lp2_set(stmdev_ctx_t * ctx,uint8_t val)2573 int32_t lsm6dso32x_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
2574 {
2575 lsm6dso32x_ctrl1_xl_t reg;
2576 int32_t ret;
2577
2578 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
2579
2580 if (ret == 0)
2581 {
2582 reg.lpf2_xl_en = val;
2583 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
2584 }
2585
2586 return ret;
2587 }
2588
2589 /**
2590 * @brief Accelerometer output from LPF2 filtering stage selection.[get]
2591 *
2592 * @param ctx read / write interface definitions
2593 * @param val change the values of lpf2_xl_en in reg CTRL1_XL
2594 * @retval interface status (MANDATORY: return 0 -> no Error).
2595 *
2596 */
lsm6dso32x_xl_filter_lp2_get(stmdev_ctx_t * ctx,uint8_t * val)2597 int32_t lsm6dso32x_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
2598 {
2599 lsm6dso32x_ctrl1_xl_t reg;
2600 int32_t ret;
2601
2602 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®, 1);
2603 *val = reg.lpf2_xl_en;
2604
2605 return ret;
2606 }
2607
2608 /**
2609 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2610 * the bandwidth can be selected through FTYPE [2:0]
2611 * in CTRL6_C (15h).[set]
2612 *
2613 * @param ctx read / write interface definitions
2614 * @param val change the values of lpf1_sel_g in reg CTRL4_C
2615 * @retval interface status (MANDATORY: return 0 -> no Error).
2616 *
2617 */
lsm6dso32x_gy_filter_lp1_set(stmdev_ctx_t * ctx,uint8_t val)2618 int32_t lsm6dso32x_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
2619 {
2620 lsm6dso32x_ctrl4_c_t reg;
2621 int32_t ret;
2622
2623 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
2624
2625 if (ret == 0)
2626 {
2627 reg.lpf1_sel_g = val;
2628 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
2629 }
2630
2631 return ret;
2632 }
2633
2634 /**
2635 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2636 * the bandwidth can be selected through FTYPE [2:0]
2637 * in CTRL6_C (15h).[get]
2638 *
2639 * @param ctx read / write interface definitions
2640 * @param val change the values of lpf1_sel_g in reg CTRL4_C
2641 * @retval interface status (MANDATORY: return 0 -> no Error).
2642 *
2643 */
lsm6dso32x_gy_filter_lp1_get(stmdev_ctx_t * ctx,uint8_t * val)2644 int32_t lsm6dso32x_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
2645 {
2646 lsm6dso32x_ctrl4_c_t reg;
2647 int32_t ret;
2648
2649 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
2650 *val = reg.lpf1_sel_g;
2651
2652 return ret;
2653 }
2654
2655 /**
2656 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2657 * (XL and Gyro independently masked).[set]
2658 *
2659 * @param ctx read / write interface definitions
2660 * @param val change the values of drdy_mask in reg CTRL4_C
2661 * @retval interface status (MANDATORY: return 0 -> no Error).
2662 *
2663 */
lsm6dso32x_filter_settling_mask_set(stmdev_ctx_t * ctx,uint8_t val)2664 int32_t lsm6dso32x_filter_settling_mask_set(stmdev_ctx_t *ctx,
2665 uint8_t val)
2666 {
2667 lsm6dso32x_ctrl4_c_t reg;
2668 int32_t ret;
2669
2670 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
2671
2672 if (ret == 0)
2673 {
2674 reg.drdy_mask = val;
2675 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
2676 }
2677
2678 return ret;
2679 }
2680
2681 /**
2682 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2683 * (XL and Gyro independently masked).[get]
2684 *
2685 * @param ctx read / write interface definitions
2686 * @param val change the values of drdy_mask in reg CTRL4_C
2687 * @retval interface status (MANDATORY: return 0 -> no Error).
2688 *
2689 */
lsm6dso32x_filter_settling_mask_get(stmdev_ctx_t * ctx,uint8_t * val)2690 int32_t lsm6dso32x_filter_settling_mask_get(stmdev_ctx_t *ctx,
2691 uint8_t *val)
2692 {
2693 lsm6dso32x_ctrl4_c_t reg;
2694 int32_t ret;
2695
2696 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
2697 *val = reg.drdy_mask;
2698
2699 return ret;
2700 }
2701
2702 /**
2703 * @brief Gyroscope lp1 bandwidth.[set]
2704 *
2705 * @param ctx read / write interface definitions
2706 * @param val change the values of ftype in reg CTRL6_C
2707 * @retval interface status (MANDATORY: return 0 -> no Error).
2708 *
2709 */
lsm6dso32x_gy_lp1_bandwidth_set(stmdev_ctx_t * ctx,lsm6dso32x_ftype_t val)2710 int32_t lsm6dso32x_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
2711 lsm6dso32x_ftype_t val)
2712 {
2713 lsm6dso32x_ctrl6_c_t reg;
2714 int32_t ret;
2715
2716 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
2717
2718 if (ret == 0)
2719 {
2720 reg.ftype = (uint8_t)val;
2721 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
2722 }
2723
2724 return ret;
2725 }
2726
2727 /**
2728 * @brief Gyroscope lp1 bandwidth.[get]
2729 *
2730 * @param ctx read / write interface definitions
2731 * @param val Get the values of ftype in reg CTRL6_C
2732 * @retval interface status (MANDATORY: return 0 -> no Error).
2733 *
2734 */
lsm6dso32x_gy_lp1_bandwidth_get(stmdev_ctx_t * ctx,lsm6dso32x_ftype_t * val)2735 int32_t lsm6dso32x_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
2736 lsm6dso32x_ftype_t *val)
2737 {
2738 lsm6dso32x_ctrl6_c_t reg;
2739 int32_t ret;
2740
2741 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
2742
2743 switch (reg.ftype)
2744 {
2745 case LSM6DSO32X_ULTRA_LIGHT:
2746 *val = LSM6DSO32X_ULTRA_LIGHT;
2747 break;
2748
2749 case LSM6DSO32X_VERY_LIGHT:
2750 *val = LSM6DSO32X_VERY_LIGHT;
2751 break;
2752
2753 case LSM6DSO32X_LIGHT:
2754 *val = LSM6DSO32X_LIGHT;
2755 break;
2756
2757 case LSM6DSO32X_MEDIUM:
2758 *val = LSM6DSO32X_MEDIUM;
2759 break;
2760
2761 case LSM6DSO32X_STRONG:
2762 *val = LSM6DSO32X_STRONG;
2763 break;
2764
2765 case LSM6DSO32X_VERY_STRONG:
2766 *val = LSM6DSO32X_VERY_STRONG;
2767 break;
2768
2769 case LSM6DSO32X_AGGRESSIVE:
2770 *val = LSM6DSO32X_AGGRESSIVE;
2771 break;
2772
2773 case LSM6DSO32X_XTREME:
2774 *val = LSM6DSO32X_XTREME;
2775 break;
2776
2777 default:
2778 *val = LSM6DSO32X_ULTRA_LIGHT;
2779 break;
2780 }
2781
2782 return ret;
2783 }
2784
2785 /**
2786 * @brief Low pass filter 2 on 6D function selection.[set]
2787 *
2788 * @param ctx read / write interface definitions
2789 * @param val change the values of low_pass_on_6d in reg CTRL8_XL
2790 * @retval interface status (MANDATORY: return 0 -> no Error).
2791 *
2792 */
lsm6dso32x_xl_lp2_on_6d_set(stmdev_ctx_t * ctx,uint8_t val)2793 int32_t lsm6dso32x_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
2794 {
2795 lsm6dso32x_ctrl8_xl_t reg;
2796 int32_t ret;
2797
2798 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
2799
2800 if (ret == 0)
2801 {
2802 reg.low_pass_on_6d = val;
2803 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
2804 }
2805
2806 return ret;
2807 }
2808
2809 /**
2810 * @brief Low pass filter 2 on 6D function selection.[get]
2811 *
2812 * @param ctx read / write interface definitions
2813 * @param val change the values of low_pass_on_6d in reg CTRL8_XL
2814 * @retval interface status (MANDATORY: return 0 -> no Error).
2815 *
2816 */
lsm6dso32x_xl_lp2_on_6d_get(stmdev_ctx_t * ctx,uint8_t * val)2817 int32_t lsm6dso32x_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
2818 {
2819 lsm6dso32x_ctrl8_xl_t reg;
2820 int32_t ret;
2821
2822 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
2823 *val = reg.low_pass_on_6d;
2824
2825 return ret;
2826 }
2827
2828 /**
2829 * @brief Accelerometer slope filter / high-pass filter selection
2830 * on output.[set]
2831 *
2832 * @param ctx read / write interface definitions
2833 * @param val change the values of hp_slope_xl_en
2834 * in reg CTRL8_XL
2835 * @retval interface status (MANDATORY: return 0 -> no Error).
2836 *
2837 */
lsm6dso32x_xl_hp_path_on_out_set(stmdev_ctx_t * ctx,lsm6dso32x_hp_slope_xl_en_t val)2838 int32_t lsm6dso32x_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
2839 lsm6dso32x_hp_slope_xl_en_t val)
2840 {
2841 lsm6dso32x_ctrl8_xl_t reg;
2842 int32_t ret;
2843
2844 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
2845
2846 if (ret == 0)
2847 {
2848 reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4;
2849 reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5;
2850 reg.hpcf_xl = (uint8_t)val & 0x07U;
2851 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
2852 }
2853
2854 return ret;
2855 }
2856
2857 /**
2858 * @brief Accelerometer slope filter / high-pass filter selection
2859 * on output.[get]
2860 *
2861 * @param ctx read / write interface definitions
2862 * @param val Get the values of hp_slope_xl_en
2863 * in reg CTRL8_XL
2864 * @retval interface status (MANDATORY: return 0 -> no Error).
2865 *
2866 */
lsm6dso32x_xl_hp_path_on_out_get(stmdev_ctx_t * ctx,lsm6dso32x_hp_slope_xl_en_t * val)2867 int32_t lsm6dso32x_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
2868 lsm6dso32x_hp_slope_xl_en_t *val)
2869 {
2870 lsm6dso32x_ctrl8_xl_t reg;
2871 int32_t ret;
2872
2873 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
2874
2875 switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) |
2876 reg.hpcf_xl)
2877 {
2878 case LSM6DSO32X_HP_PATH_DISABLE_ON_OUT:
2879 *val = LSM6DSO32X_HP_PATH_DISABLE_ON_OUT;
2880 break;
2881
2882 case LSM6DSO32X_SLOPE_ODR_DIV_4:
2883 *val = LSM6DSO32X_SLOPE_ODR_DIV_4;
2884 break;
2885
2886 case LSM6DSO32X_HP_ODR_DIV_10:
2887 *val = LSM6DSO32X_HP_ODR_DIV_10;
2888 break;
2889
2890 case LSM6DSO32X_HP_ODR_DIV_20:
2891 *val = LSM6DSO32X_HP_ODR_DIV_20;
2892 break;
2893
2894 case LSM6DSO32X_HP_ODR_DIV_45:
2895 *val = LSM6DSO32X_HP_ODR_DIV_45;
2896 break;
2897
2898 case LSM6DSO32X_HP_ODR_DIV_100:
2899 *val = LSM6DSO32X_HP_ODR_DIV_100;
2900 break;
2901
2902 case LSM6DSO32X_HP_ODR_DIV_200:
2903 *val = LSM6DSO32X_HP_ODR_DIV_200;
2904 break;
2905
2906 case LSM6DSO32X_HP_ODR_DIV_400:
2907 *val = LSM6DSO32X_HP_ODR_DIV_400;
2908 break;
2909
2910 case LSM6DSO32X_HP_ODR_DIV_800:
2911 *val = LSM6DSO32X_HP_ODR_DIV_800;
2912 break;
2913
2914 case LSM6DSO32X_HP_REF_MD_ODR_DIV_10:
2915 *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_10;
2916 break;
2917
2918 case LSM6DSO32X_HP_REF_MD_ODR_DIV_20:
2919 *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_20;
2920 break;
2921
2922 case LSM6DSO32X_HP_REF_MD_ODR_DIV_45:
2923 *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_45;
2924 break;
2925
2926 case LSM6DSO32X_HP_REF_MD_ODR_DIV_100:
2927 *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_100;
2928 break;
2929
2930 case LSM6DSO32X_HP_REF_MD_ODR_DIV_200:
2931 *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_200;
2932 break;
2933
2934 case LSM6DSO32X_HP_REF_MD_ODR_DIV_400:
2935 *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_400;
2936 break;
2937
2938 case LSM6DSO32X_HP_REF_MD_ODR_DIV_800:
2939 *val = LSM6DSO32X_HP_REF_MD_ODR_DIV_800;
2940 break;
2941
2942 case LSM6DSO32X_LP_ODR_DIV_10:
2943 *val = LSM6DSO32X_LP_ODR_DIV_10;
2944 break;
2945
2946 case LSM6DSO32X_LP_ODR_DIV_20:
2947 *val = LSM6DSO32X_LP_ODR_DIV_20;
2948 break;
2949
2950 case LSM6DSO32X_LP_ODR_DIV_45:
2951 *val = LSM6DSO32X_LP_ODR_DIV_45;
2952 break;
2953
2954 case LSM6DSO32X_LP_ODR_DIV_100:
2955 *val = LSM6DSO32X_LP_ODR_DIV_100;
2956 break;
2957
2958 case LSM6DSO32X_LP_ODR_DIV_200:
2959 *val = LSM6DSO32X_LP_ODR_DIV_200;
2960 break;
2961
2962 case LSM6DSO32X_LP_ODR_DIV_400:
2963 *val = LSM6DSO32X_LP_ODR_DIV_400;
2964 break;
2965
2966 case LSM6DSO32X_LP_ODR_DIV_800:
2967 *val = LSM6DSO32X_LP_ODR_DIV_800;
2968 break;
2969
2970 default:
2971 *val = LSM6DSO32X_HP_PATH_DISABLE_ON_OUT;
2972 break;
2973 }
2974
2975 return ret;
2976 }
2977
2978 /**
2979 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2980 * The filter sets the second samples after writing this bit.
2981 * Active only during device exit from power-down mode.[set]
2982 *
2983 * @param ctx read / write interface definitions
2984 * @param val change the values of fastsettl_mode_xl in
2985 * reg CTRL8_XL
2986 * @retval interface status (MANDATORY: return 0 -> no Error).
2987 *
2988 */
lsm6dso32x_xl_fast_settling_set(stmdev_ctx_t * ctx,uint8_t val)2989 int32_t lsm6dso32x_xl_fast_settling_set(stmdev_ctx_t *ctx,
2990 uint8_t val)
2991 {
2992 lsm6dso32x_ctrl8_xl_t reg;
2993 int32_t ret;
2994
2995 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
2996
2997 if (ret == 0)
2998 {
2999 reg.fastsettl_mode_xl = val;
3000 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
3001 }
3002
3003 return ret;
3004 }
3005
3006 /**
3007 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
3008 * The filter sets the second samples after writing this bit.
3009 * Active only during device exit from power-down mode.[get]
3010 *
3011 * @param ctx read / write interface definitions
3012 * @param val change the values of fastsettl_mode_xl in reg CTRL8_XL
3013 * @retval interface status (MANDATORY: return 0 -> no Error).
3014 *
3015 */
lsm6dso32x_xl_fast_settling_get(stmdev_ctx_t * ctx,uint8_t * val)3016 int32_t lsm6dso32x_xl_fast_settling_get(stmdev_ctx_t *ctx,
3017 uint8_t *val)
3018 {
3019 lsm6dso32x_ctrl8_xl_t reg;
3020 int32_t ret;
3021
3022 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL8_XL, (uint8_t *)®, 1);
3023 *val = reg.fastsettl_mode_xl;
3024
3025 return ret;
3026 }
3027
3028 /**
3029 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
3030 * functions.[set]
3031 *
3032 * @param ctx read / write interface definitions
3033 * @param val change the values of slope_fds in reg TAP_CFG0
3034 * @retval interface status (MANDATORY: return 0 -> no Error).
3035 *
3036 */
lsm6dso32x_xl_hp_path_internal_set(stmdev_ctx_t * ctx,lsm6dso32x_slope_fds_t val)3037 int32_t lsm6dso32x_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
3038 lsm6dso32x_slope_fds_t val)
3039 {
3040 lsm6dso32x_tap_cfg0_t reg;
3041 int32_t ret;
3042
3043 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
3044
3045 if (ret == 0)
3046 {
3047 reg.slope_fds = (uint8_t)val;
3048 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
3049 }
3050
3051 return ret;
3052 }
3053
3054 /**
3055 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
3056 * functions.[get]
3057 *
3058 * @param ctx read / write interface definitions
3059 * @param val Change the values of slope_fds in reg TAP_CFG0
3060 * @retval interface status (MANDATORY: return 0 -> no Error).
3061 *
3062 */
lsm6dso32x_xl_hp_path_internal_get(stmdev_ctx_t * ctx,lsm6dso32x_slope_fds_t * val)3063 int32_t lsm6dso32x_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
3064 lsm6dso32x_slope_fds_t *val)
3065 {
3066 lsm6dso32x_tap_cfg0_t reg;
3067 int32_t ret;
3068
3069 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
3070
3071 switch (reg.slope_fds)
3072 {
3073 case LSM6DSO32X_USE_SLOPE:
3074 *val = LSM6DSO32X_USE_SLOPE;
3075 break;
3076
3077 case LSM6DSO32X_USE_HPF:
3078 *val = LSM6DSO32X_USE_HPF;
3079 break;
3080
3081 default:
3082 *val = LSM6DSO32X_USE_SLOPE;
3083 break;
3084 }
3085
3086 return ret;
3087 }
3088
3089 /**
3090 * @brief Enables gyroscope digital high-pass filter. The filter is
3091 * enabled only if the gyro is in HP mode.[set]
3092 *
3093 * @param ctx read / write interface definitions
3094 * @param val Get the values of hp_en_g and hp_en_g
3095 * in reg CTRL7_G
3096 * @retval interface status (MANDATORY: return 0 -> no Error).
3097 *
3098 */
lsm6dso32x_gy_hp_path_internal_set(stmdev_ctx_t * ctx,lsm6dso32x_hpm_g_t val)3099 int32_t lsm6dso32x_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
3100 lsm6dso32x_hpm_g_t val)
3101 {
3102 lsm6dso32x_ctrl7_g_t reg;
3103 int32_t ret;
3104
3105 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
3106
3107 if (ret == 0)
3108 {
3109 reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
3110 reg.hpm_g = (uint8_t)val & 0x03U;
3111 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
3112 }
3113
3114 return ret;
3115 }
3116
3117 /**
3118 * @brief Enables gyroscope digital high-pass filter. The filter is
3119 * enabled only if the gyro is in HP mode.[get]
3120 *
3121 * @param ctx read / write interface definitions
3122 * @param val Get the values of hp_en_g and hp_en_g
3123 * in reg CTRL7_G
3124 * @retval interface status (MANDATORY: return 0 -> no Error).
3125 *
3126 */
lsm6dso32x_gy_hp_path_internal_get(stmdev_ctx_t * ctx,lsm6dso32x_hpm_g_t * val)3127 int32_t lsm6dso32x_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
3128 lsm6dso32x_hpm_g_t *val)
3129 {
3130 lsm6dso32x_ctrl7_g_t reg;
3131 int32_t ret;
3132
3133 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL7_G, (uint8_t *)®, 1);
3134
3135 switch ((reg.hp_en_g << 7) + reg.hpm_g)
3136 {
3137 case LSM6DSO32X_HP_FILTER_NONE:
3138 *val = LSM6DSO32X_HP_FILTER_NONE;
3139 break;
3140
3141 case LSM6DSO32X_HP_FILTER_16mHz:
3142 *val = LSM6DSO32X_HP_FILTER_16mHz;
3143 break;
3144
3145 case LSM6DSO32X_HP_FILTER_65mHz:
3146 *val = LSM6DSO32X_HP_FILTER_65mHz;
3147 break;
3148
3149 case LSM6DSO32X_HP_FILTER_260mHz:
3150 *val = LSM6DSO32X_HP_FILTER_260mHz;
3151 break;
3152
3153 case LSM6DSO32X_HP_FILTER_1Hz04:
3154 *val = LSM6DSO32X_HP_FILTER_1Hz04;
3155 break;
3156
3157 default:
3158 *val = LSM6DSO32X_HP_FILTER_NONE;
3159 break;
3160 }
3161
3162 return ret;
3163 }
3164
3165 /**
3166 * @}
3167 *
3168 */
3169
3170 /**
3171 * @defgroup LSM6DSO32X_ main_serial_interface
3172 * @brief This section groups all the functions concerning main
3173 * serial interface management (not auxiliary)
3174 * @{
3175 *
3176 */
3177
3178 /**
3179 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
3180 *
3181 * @param ctx read / write interface definitions
3182 * @param val change the values of sdo_pu_en in
3183 * reg PIN_CTRL
3184 * @retval interface status (MANDATORY: return 0 -> no Error).
3185 *
3186 */
lsm6dso32x_sdo_sa0_mode_set(stmdev_ctx_t * ctx,lsm6dso32x_sdo_pu_en_t val)3187 int32_t lsm6dso32x_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
3188 lsm6dso32x_sdo_pu_en_t val)
3189 {
3190 lsm6dso32x_pin_ctrl_t reg;
3191 int32_t ret;
3192
3193 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PIN_CTRL, (uint8_t *)®, 1);
3194
3195 if (ret == 0)
3196 {
3197 reg.sdo_pu_en = (uint8_t)val;
3198 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PIN_CTRL, (uint8_t *)®, 1);
3199 }
3200
3201 return ret;
3202 }
3203
3204 /**
3205 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
3206 *
3207 * @param ctx read / write interface definitions
3208 * @param val Get the values of sdo_pu_en in reg PIN_CTRL
3209 * @retval interface status (MANDATORY: return 0 -> no Error).
3210 *
3211 */
lsm6dso32x_sdo_sa0_mode_get(stmdev_ctx_t * ctx,lsm6dso32x_sdo_pu_en_t * val)3212 int32_t lsm6dso32x_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
3213 lsm6dso32x_sdo_pu_en_t *val)
3214 {
3215 lsm6dso32x_pin_ctrl_t reg;
3216 int32_t ret;
3217
3218 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PIN_CTRL, (uint8_t *)®, 1);
3219
3220 switch (reg.sdo_pu_en)
3221 {
3222 case LSM6DSO32X_PULL_UP_DISC:
3223 *val = LSM6DSO32X_PULL_UP_DISC;
3224 break;
3225
3226 case LSM6DSO32X_PULL_UP_CONNECT:
3227 *val = LSM6DSO32X_PULL_UP_CONNECT;
3228 break;
3229
3230 default:
3231 *val = LSM6DSO32X_PULL_UP_DISC;
3232 break;
3233 }
3234
3235 return ret;
3236 }
3237
3238 /**
3239 * @brief SPI Serial Interface Mode selection.[set]
3240 *
3241 * @param ctx read / write interface definitions
3242 * @param val change the values of sim in reg CTRL3_C
3243 * @retval interface status (MANDATORY: return 0 -> no Error).
3244 *
3245 */
lsm6dso32x_spi_mode_set(stmdev_ctx_t * ctx,lsm6dso32x_sim_t val)3246 int32_t lsm6dso32x_spi_mode_set(stmdev_ctx_t *ctx,
3247 lsm6dso32x_sim_t val)
3248 {
3249 lsm6dso32x_ctrl3_c_t reg;
3250 int32_t ret;
3251
3252 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
3253
3254 if (ret == 0)
3255 {
3256 reg.sim = (uint8_t)val;
3257 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
3258 }
3259
3260 return ret;
3261 }
3262
3263 /**
3264 * @brief SPI Serial Interface Mode selection.[get]
3265 *
3266 * @param ctx read / write interface definitions
3267 * @param val Get the values of sim in reg CTRL3_C
3268 * @retval interface status (MANDATORY: return 0 -> no Error).
3269 *
3270 */
lsm6dso32x_spi_mode_get(stmdev_ctx_t * ctx,lsm6dso32x_sim_t * val)3271 int32_t lsm6dso32x_spi_mode_get(stmdev_ctx_t *ctx,
3272 lsm6dso32x_sim_t *val)
3273 {
3274 lsm6dso32x_ctrl3_c_t reg;
3275 int32_t ret;
3276
3277 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
3278
3279 switch (reg.sim)
3280 {
3281 case LSM6DSO32X_SPI_4_WIRE:
3282 *val = LSM6DSO32X_SPI_4_WIRE;
3283 break;
3284
3285 case LSM6DSO32X_SPI_3_WIRE:
3286 *val = LSM6DSO32X_SPI_3_WIRE;
3287 break;
3288
3289 default:
3290 *val = LSM6DSO32X_SPI_4_WIRE;
3291 break;
3292 }
3293
3294 return ret;
3295 }
3296
3297 /**
3298 * @brief Disable / Enable I2C interface.[set]
3299 *
3300 * @param ctx read / write interface definitions
3301 * @param val change the values of i2c_disable in
3302 * reg CTRL4_C
3303 * @retval interface status (MANDATORY: return 0 -> no Error).
3304 *
3305 */
lsm6dso32x_i2c_interface_set(stmdev_ctx_t * ctx,lsm6dso32x_i2c_disable_t val)3306 int32_t lsm6dso32x_i2c_interface_set(stmdev_ctx_t *ctx,
3307 lsm6dso32x_i2c_disable_t val)
3308 {
3309 lsm6dso32x_ctrl4_c_t reg;
3310 int32_t ret;
3311
3312 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
3313
3314 if (ret == 0)
3315 {
3316 reg.i2c_disable = (uint8_t)val;
3317 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
3318 }
3319
3320 return ret;
3321 }
3322
3323 /**
3324 * @brief Disable / Enable I2C interface.[get]
3325 *
3326 * @param ctx read / write interface definitions
3327 * @param val Get the values of i2c_disable in
3328 * reg CTRL4_C
3329 * @retval interface status (MANDATORY: return 0 -> no Error).
3330 *
3331 */
lsm6dso32x_i2c_interface_get(stmdev_ctx_t * ctx,lsm6dso32x_i2c_disable_t * val)3332 int32_t lsm6dso32x_i2c_interface_get(stmdev_ctx_t *ctx,
3333 lsm6dso32x_i2c_disable_t *val)
3334 {
3335 lsm6dso32x_ctrl4_c_t reg;
3336 int32_t ret;
3337
3338 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
3339
3340 switch (reg.i2c_disable)
3341 {
3342 case LSM6DSO32X_I2C_ENABLE:
3343 *val = LSM6DSO32X_I2C_ENABLE;
3344 break;
3345
3346 case LSM6DSO32X_I2C_DISABLE:
3347 *val = LSM6DSO32X_I2C_DISABLE;
3348 break;
3349
3350 default:
3351 *val = LSM6DSO32X_I2C_ENABLE;
3352 break;
3353 }
3354
3355 return ret;
3356 }
3357
3358 /**
3359 * @brief I3C Enable/Disable communication protocol[.set]
3360 *
3361 * @param ctx read / write interface definitions
3362 * @param val change the values of i3c_disable
3363 * in reg CTRL9_XL
3364 * @retval interface status (MANDATORY: return 0 -> no Error).
3365 *
3366 */
lsm6dso32x_i3c_disable_set(stmdev_ctx_t * ctx,lsm6dso32x_i3c_disable_t val)3367 int32_t lsm6dso32x_i3c_disable_set(stmdev_ctx_t *ctx,
3368 lsm6dso32x_i3c_disable_t val)
3369 {
3370 lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
3371 lsm6dso32x_ctrl9_xl_t ctrl9_xl;
3372 int32_t ret;
3373
3374 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL,
3375 (uint8_t *)&ctrl9_xl, 1);
3376
3377 if (ret == 0)
3378 {
3379 ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
3380 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL,
3381 (uint8_t *)&ctrl9_xl, 1);
3382 }
3383
3384 if (ret == 0)
3385 {
3386 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
3387 (uint8_t *)&i3c_bus_avb, 1);
3388 }
3389
3390 if (ret == 0)
3391 {
3392 i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
3393 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
3394 (uint8_t *)&i3c_bus_avb, 1);
3395 }
3396
3397 return ret;
3398 }
3399
3400 /**
3401 * @brief I3C Enable/Disable communication protocol.[get]
3402 *
3403 * @param ctx read / write interface definitions
3404 * @param val change the values of i3c_disable in
3405 * reg CTRL9_XL
3406 * @retval interface status (MANDATORY: return 0 -> no Error).
3407 *
3408 */
lsm6dso32x_i3c_disable_get(stmdev_ctx_t * ctx,lsm6dso32x_i3c_disable_t * val)3409 int32_t lsm6dso32x_i3c_disable_get(stmdev_ctx_t *ctx,
3410 lsm6dso32x_i3c_disable_t *val)
3411 {
3412 lsm6dso32x_ctrl9_xl_t ctrl9_xl;
3413 lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
3414 int32_t ret;
3415
3416 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL,
3417 (uint8_t *)&ctrl9_xl, 1);
3418
3419 if (ret == 0)
3420 {
3421 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
3422 (uint8_t *)&i3c_bus_avb, 1);
3423
3424 switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel)
3425 {
3426 case LSM6DSO32X_I3C_DISABLE:
3427 *val = LSM6DSO32X_I3C_DISABLE;
3428 break;
3429
3430 case LSM6DSO32X_I3C_ENABLE_T_50us:
3431 *val = LSM6DSO32X_I3C_ENABLE_T_50us;
3432 break;
3433
3434 case LSM6DSO32X_I3C_ENABLE_T_2us:
3435 *val = LSM6DSO32X_I3C_ENABLE_T_2us;
3436 break;
3437
3438 case LSM6DSO32X_I3C_ENABLE_T_1ms:
3439 *val = LSM6DSO32X_I3C_ENABLE_T_1ms;
3440 break;
3441
3442 case LSM6DSO32X_I3C_ENABLE_T_25ms:
3443 *val = LSM6DSO32X_I3C_ENABLE_T_25ms;
3444 break;
3445
3446 default:
3447 *val = LSM6DSO32X_I3C_DISABLE;
3448 break;
3449 }
3450 }
3451
3452 return ret;
3453 }
3454
3455 /**
3456 * @}
3457 *
3458 */
3459
3460 /**
3461 * @defgroup LSM6DSO32X_interrupt_pins
3462 * @brief This section groups all the functions that manage interrupt pins
3463 * @{
3464 *
3465 */
3466
3467 /**
3468 * @brief Push-pull/open drain selection on interrupt pads.[set]
3469 *
3470 * @param ctx read / write interface definitions
3471 * @param val change the values of pp_od in reg CTRL3_C
3472 * @retval interface status (MANDATORY: return 0 -> no Error).
3473 *
3474 */
lsm6dso32x_pin_mode_set(stmdev_ctx_t * ctx,lsm6dso32x_pp_od_t val)3475 int32_t lsm6dso32x_pin_mode_set(stmdev_ctx_t *ctx,
3476 lsm6dso32x_pp_od_t val)
3477 {
3478 lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
3479 lsm6dso32x_ctrl3_c_t ctrl3_c;
3480 int32_t ret;
3481
3482 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
3483 (uint8_t *)&ctrl3_c, 1);
3484
3485 if (ret == 0)
3486 {
3487 ctrl3_c.pp_od = (uint8_t)val;
3488 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C,
3489 (uint8_t *)&ctrl3_c, 1);
3490 }
3491
3492 if (ret == 0)
3493 {
3494 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
3495 (uint8_t *)&i3c_bus_avb, 1);
3496 }
3497
3498 if (ret == 0)
3499 {
3500 i3c_bus_avb.pd_dis_int1 = ((uint8_t) val & 0x02U) >> 1;
3501 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
3502 (uint8_t *)&i3c_bus_avb, 1);
3503 }
3504
3505 return ret;
3506 }
3507
3508 /**
3509 * @brief Push-pull/open drain selection on interrupt pads.[get]
3510 *
3511 * @param ctx read / write interface definitions
3512 * @param val Get the values of pp_od in reg CTRL3_C
3513 * @retval interface status (MANDATORY: return 0 -> no Error).
3514 *
3515 */
lsm6dso32x_pin_mode_get(stmdev_ctx_t * ctx,lsm6dso32x_pp_od_t * val)3516 int32_t lsm6dso32x_pin_mode_get(stmdev_ctx_t *ctx,
3517 lsm6dso32x_pp_od_t *val)
3518 {
3519 lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
3520 lsm6dso32x_ctrl3_c_t ctrl3_c;
3521 int32_t ret;
3522
3523 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
3524 (uint8_t *)&ctrl3_c, 1);
3525
3526 if (ret == 0)
3527 {
3528 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
3529 (uint8_t *)&i3c_bus_avb, 1);
3530 }
3531
3532 switch ((i3c_bus_avb.pd_dis_int1 << 1) + ctrl3_c.pp_od)
3533 {
3534 case LSM6DSO32X_PUSH_PULL:
3535 *val = LSM6DSO32X_PUSH_PULL;
3536 break;
3537
3538 case LSM6DSO32X_OPEN_DRAIN:
3539 *val = LSM6DSO32X_OPEN_DRAIN;
3540 break;
3541
3542 case LSM6DSO32X_INT1_NOPULL_DOWN_INT2_PUSH_PULL:
3543 *val = LSM6DSO32X_INT1_NOPULL_DOWN_INT2_PUSH_PULL;
3544 break;
3545
3546 case LSM6DSO32X_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN:
3547 *val = LSM6DSO32X_INT1_NOPULL_DOWN_INT2_OPEN_DRAIN;
3548 break;
3549
3550 default:
3551 *val = LSM6DSO32X_PUSH_PULL;
3552 break;
3553 }
3554
3555 return ret;
3556 }
3557
3558 /**
3559 * @brief Interrupt active-high/low.[set]
3560 *
3561 * @param ctx read / write interface definitions
3562 * @param val change the values of h_lactive in reg CTRL3_C
3563 * @retval interface status (MANDATORY: return 0 -> no Error).
3564 *
3565 */
lsm6dso32x_pin_polarity_set(stmdev_ctx_t * ctx,lsm6dso32x_h_lactive_t val)3566 int32_t lsm6dso32x_pin_polarity_set(stmdev_ctx_t *ctx,
3567 lsm6dso32x_h_lactive_t val)
3568 {
3569 lsm6dso32x_ctrl3_c_t reg;
3570 int32_t ret;
3571
3572 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
3573
3574 if (ret == 0)
3575 {
3576 reg.h_lactive = (uint8_t)val;
3577 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
3578 }
3579
3580 return ret;
3581 }
3582
3583 /**
3584 * @brief Interrupt active-high/low.[get]
3585 *
3586 * @param ctx read / write interface definitions
3587 * @param val Get the values of h_lactive in reg CTRL3_C
3588 * @retval interface status (MANDATORY: return 0 -> no Error).
3589 *
3590 */
lsm6dso32x_pin_polarity_get(stmdev_ctx_t * ctx,lsm6dso32x_h_lactive_t * val)3591 int32_t lsm6dso32x_pin_polarity_get(stmdev_ctx_t *ctx,
3592 lsm6dso32x_h_lactive_t *val)
3593 {
3594 lsm6dso32x_ctrl3_c_t reg;
3595 int32_t ret;
3596
3597 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C, (uint8_t *)®, 1);
3598
3599 switch (reg.h_lactive)
3600 {
3601 case LSM6DSO32X_ACTIVE_HIGH:
3602 *val = LSM6DSO32X_ACTIVE_HIGH;
3603 break;
3604
3605 case LSM6DSO32X_ACTIVE_LOW:
3606 *val = LSM6DSO32X_ACTIVE_LOW;
3607 break;
3608
3609 default:
3610 *val = LSM6DSO32X_ACTIVE_HIGH;
3611 break;
3612 }
3613
3614 return ret;
3615 }
3616
3617 /**
3618 * @brief All interrupt signals become available on INT1 pin.[set]
3619 *
3620 * @param ctx read / write interface definitions
3621 * @param val change the values of int2_on_int1 in reg CTRL4_C
3622 * @retval interface status (MANDATORY: return 0 -> no Error).
3623 *
3624 */
lsm6dso32x_all_on_int1_set(stmdev_ctx_t * ctx,uint8_t val)3625 int32_t lsm6dso32x_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
3626 {
3627 lsm6dso32x_ctrl4_c_t reg;
3628 int32_t ret;
3629
3630 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
3631
3632 if (ret == 0)
3633 {
3634 reg.int2_on_int1 = val;
3635 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
3636 }
3637
3638 return ret;
3639 }
3640
3641 /**
3642 * @brief All interrupt signals become available on INT1 pin.[get]
3643 *
3644 * @param ctx read / write interface definitions
3645 * @param val change the values of int2_on_int1 in reg CTRL4_C
3646 * @retval interface status (MANDATORY: return 0 -> no Error).
3647 *
3648 */
lsm6dso32x_all_on_int1_get(stmdev_ctx_t * ctx,uint8_t * val)3649 int32_t lsm6dso32x_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
3650 {
3651 lsm6dso32x_ctrl4_c_t reg;
3652 int32_t ret;
3653
3654 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
3655 *val = reg.int2_on_int1;
3656
3657 return ret;
3658 }
3659
3660 /**
3661 * @brief Interrupt notification mode.[set]
3662 *
3663 * @param ctx read / write interface definitions
3664 * @param val change the values of lir in reg TAP_CFG0
3665 * @retval interface status (MANDATORY: return 0 -> no Error).
3666 *
3667 */
lsm6dso32x_int_notification_set(stmdev_ctx_t * ctx,lsm6dso32x_lir_t val)3668 int32_t lsm6dso32x_int_notification_set(stmdev_ctx_t *ctx,
3669 lsm6dso32x_lir_t val)
3670 {
3671 lsm6dso32x_tap_cfg0_t tap_cfg0;
3672 lsm6dso32x_page_rw_t page_rw;
3673 int32_t ret;
3674
3675 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0,
3676 (uint8_t *) &tap_cfg0, 1);
3677
3678 if (ret == 0)
3679 {
3680 tap_cfg0.lir = (uint8_t)val & 0x01U;
3681 tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
3682 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0,
3683 (uint8_t *) &tap_cfg0, 1);
3684 }
3685
3686 if (ret == 0)
3687 {
3688 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
3689 }
3690
3691 if (ret == 0)
3692 {
3693 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
3694 (uint8_t *) &page_rw, 1);
3695 }
3696
3697 if (ret == 0)
3698 {
3699 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
3700 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
3701 (uint8_t *) &page_rw, 1);
3702 }
3703
3704 if (ret == 0)
3705 {
3706 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
3707 }
3708
3709 return ret;
3710 }
3711
3712 /**
3713 * @brief Interrupt notification mode.[get]
3714 *
3715 * @param ctx read / write interface definitions
3716 * @param val Get the values of lir in reg TAP_CFG0
3717 * @retval interface status (MANDATORY: return 0 -> no Error).
3718 *
3719 */
lsm6dso32x_int_notification_get(stmdev_ctx_t * ctx,lsm6dso32x_lir_t * val)3720 int32_t lsm6dso32x_int_notification_get(stmdev_ctx_t *ctx,
3721 lsm6dso32x_lir_t *val)
3722 {
3723 lsm6dso32x_tap_cfg0_t tap_cfg0;
3724 lsm6dso32x_page_rw_t page_rw;
3725 int32_t ret;
3726
3727 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0,
3728 (uint8_t *) &tap_cfg0, 1);
3729
3730 if (ret == 0)
3731 {
3732 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
3733 }
3734
3735 if (ret == 0)
3736 {
3737 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
3738 (uint8_t *) &page_rw, 1);
3739 }
3740
3741 if (ret == 0)
3742 {
3743 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
3744 }
3745
3746 if (ret == 0)
3747 {
3748 switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir)
3749 {
3750 case LSM6DSO32X_ALL_INT_PULSED:
3751 *val = LSM6DSO32X_ALL_INT_PULSED;
3752 break;
3753
3754 case LSM6DSO32X_BASE_LATCHED_EMB_PULSED:
3755 *val = LSM6DSO32X_BASE_LATCHED_EMB_PULSED;
3756 break;
3757
3758 case LSM6DSO32X_BASE_PULSED_EMB_LATCHED:
3759 *val = LSM6DSO32X_BASE_PULSED_EMB_LATCHED;
3760 break;
3761
3762 case LSM6DSO32X_ALL_INT_LATCHED:
3763 *val = LSM6DSO32X_ALL_INT_LATCHED;
3764 break;
3765
3766 default:
3767 *val = LSM6DSO32X_ALL_INT_PULSED;
3768 break;
3769 }
3770
3771 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
3772 }
3773
3774 if (ret == 0)
3775 {
3776 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
3777 (uint8_t *) &page_rw, 1);
3778 }
3779
3780 if (ret == 0)
3781 {
3782 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
3783 }
3784
3785 return ret;
3786 }
3787
3788 /**
3789 * @}
3790 *
3791 */
3792
3793 /**
3794 * @defgroup LSM6DSO32X_Wake_Up_event
3795 * @brief This section groups all the functions that manage the Wake Up
3796 * event generation.
3797 * @{
3798 *
3799 */
3800
3801 /**
3802 * @brief Weight of 1 LSB of wakeup threshold.[set]
3803 * 0: 1 LSB =FS_XL / 64
3804 * 1: 1 LSB = FS_XL / 256
3805 *
3806 * @param ctx read / write interface definitions
3807 * @param val change the values of wake_ths_w in
3808 * reg WAKE_UP_DUR
3809 * @retval interface status (MANDATORY: return 0 -> no Error).
3810 *
3811 */
lsm6dso32x_wkup_ths_weight_set(stmdev_ctx_t * ctx,lsm6dso32x_wake_ths_w_t val)3812 int32_t lsm6dso32x_wkup_ths_weight_set(stmdev_ctx_t *ctx,
3813 lsm6dso32x_wake_ths_w_t val)
3814 {
3815 lsm6dso32x_wake_up_dur_t reg;
3816 int32_t ret;
3817
3818 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
3819 (uint8_t *)®, 1);
3820
3821 if (ret == 0)
3822 {
3823 reg.wake_ths_w = (uint8_t)val;
3824 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
3825 (uint8_t *)®, 1);
3826 }
3827
3828 return ret;
3829 }
3830
3831 /**
3832 * @brief Weight of 1 LSB of wakeup threshold.[get]
3833 * 0: 1 LSB =FS_XL / 64
3834 * 1: 1 LSB = FS_XL / 256
3835 *
3836 * @param ctx read / write interface definitions
3837 * @param val Get the values of wake_ths_w in
3838 * reg WAKE_UP_DUR
3839 * @retval interface status (MANDATORY: return 0 -> no Error).
3840 *
3841 */
lsm6dso32x_wkup_ths_weight_get(stmdev_ctx_t * ctx,lsm6dso32x_wake_ths_w_t * val)3842 int32_t lsm6dso32x_wkup_ths_weight_get(stmdev_ctx_t *ctx,
3843 lsm6dso32x_wake_ths_w_t *val)
3844 {
3845 lsm6dso32x_wake_up_dur_t reg;
3846 int32_t ret;
3847
3848 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
3849 (uint8_t *)®, 1);
3850
3851 switch (reg.wake_ths_w)
3852 {
3853 case LSM6DSO32X_LSb_FS_DIV_64:
3854 *val = LSM6DSO32X_LSb_FS_DIV_64;
3855 break;
3856
3857 case LSM6DSO32X_LSb_FS_DIV_256:
3858 *val = LSM6DSO32X_LSb_FS_DIV_256;
3859 break;
3860
3861 default:
3862 *val = LSM6DSO32X_LSb_FS_DIV_64;
3863 break;
3864 }
3865
3866 return ret;
3867 }
3868
3869 /**
3870 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
3871 * WAKE_UP_DUR.[set]
3872 *
3873 * @param ctx read / write interface definitions
3874 * @param val change the values of wk_ths in reg WAKE_UP_THS
3875 * @retval interface status (MANDATORY: return 0 -> no Error).
3876 *
3877 */
lsm6dso32x_wkup_threshold_set(stmdev_ctx_t * ctx,uint8_t val)3878 int32_t lsm6dso32x_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
3879 {
3880 lsm6dso32x_wake_up_ths_t reg;
3881 int32_t ret;
3882
3883 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
3884 (uint8_t *)®, 1);
3885
3886 if (ret == 0)
3887 {
3888 reg.wk_ths = val;
3889 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
3890 (uint8_t *)®, 1);
3891 }
3892
3893 return ret;
3894 }
3895
3896 /**
3897 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
3898 * WAKE_UP_DUR.[get]
3899 *
3900 * @param ctx read / write interface definitions
3901 * @param val change the values of wk_ths in reg WAKE_UP_THS
3902 * @retval interface status (MANDATORY: return 0 -> no Error).
3903 *
3904 */
lsm6dso32x_wkup_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)3905 int32_t lsm6dso32x_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
3906 {
3907 lsm6dso32x_wake_up_ths_t reg;
3908 int32_t ret;
3909
3910 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
3911 (uint8_t *)®, 1);
3912 *val = reg.wk_ths;
3913
3914 return ret;
3915 }
3916
3917 /**
3918 * @brief Wake up duration event.[set]
3919 * 1LSb = 1 / ODR
3920 *
3921 * @param ctx read / write interface definitions
3922 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
3923 * @retval interface status (MANDATORY: return 0 -> no Error).
3924 *
3925 */
lsm6dso32x_xl_usr_offset_on_wkup_set(stmdev_ctx_t * ctx,uint8_t val)3926 int32_t lsm6dso32x_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
3927 uint8_t val)
3928 {
3929 lsm6dso32x_wake_up_ths_t reg;
3930 int32_t ret;
3931
3932 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
3933 (uint8_t *)®, 1);
3934
3935 if (ret == 0)
3936 {
3937 reg.usr_off_on_wu = val;
3938 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
3939 (uint8_t *)®, 1);
3940 }
3941
3942 return ret;
3943 }
3944
3945 /**
3946 * @brief Wake up duration event.[get]
3947 * 1LSb = 1 / ODR
3948 *
3949 * @param ctx read / write interface definitions
3950 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
3951 * @retval interface status (MANDATORY: return 0 -> no Error).
3952 *
3953 */
lsm6dso32x_xl_usr_offset_on_wkup_get(stmdev_ctx_t * ctx,uint8_t * val)3954 int32_t lsm6dso32x_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
3955 uint8_t *val)
3956 {
3957 lsm6dso32x_wake_up_ths_t reg;
3958 int32_t ret;
3959
3960 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
3961 (uint8_t *)®, 1);
3962 *val = reg.usr_off_on_wu;
3963
3964 return ret;
3965 }
3966
3967 /**
3968 * @brief Wake up duration event.[set]
3969 * 1LSb = 1 / ODR
3970 *
3971 * @param ctx read / write interface definitions
3972 * @param val change the values of wake_dur in reg WAKE_UP_DUR
3973 * @retval interface status (MANDATORY: return 0 -> no Error).
3974 *
3975 */
lsm6dso32x_wkup_dur_set(stmdev_ctx_t * ctx,uint8_t val)3976 int32_t lsm6dso32x_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
3977 {
3978 lsm6dso32x_wake_up_dur_t reg;
3979 int32_t ret;
3980
3981 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
3982 (uint8_t *)®, 1);
3983
3984 if (ret == 0)
3985 {
3986 reg.wake_dur = val;
3987 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
3988 (uint8_t *)®, 1);
3989 }
3990
3991 return ret;
3992 }
3993
3994 /**
3995 * @brief Wake up duration event.[get]
3996 * 1LSb = 1 / ODR
3997 *
3998 * @param ctx read / write interface definitions
3999 * @param val change the values of wake_dur in reg WAKE_UP_DUR
4000 * @retval interface status (MANDATORY: return 0 -> no Error).
4001 *
4002 */
lsm6dso32x_wkup_dur_get(stmdev_ctx_t * ctx,uint8_t * val)4003 int32_t lsm6dso32x_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
4004 {
4005 lsm6dso32x_wake_up_dur_t reg;
4006 int32_t ret;
4007
4008 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
4009 (uint8_t *)®, 1);
4010 *val = reg.wake_dur;
4011
4012 return ret;
4013 }
4014
4015 /**
4016 * @}
4017 *
4018 */
4019
4020 /**
4021 * @defgroup LSM6DSO32X_ Activity/Inactivity_detection
4022 * @brief This section groups all the functions concerning
4023 * activity/inactivity detection.
4024 * @{
4025 *
4026 */
4027
4028 /**
4029 * @brief Enables gyroscope Sleep mode.[set]
4030 *
4031 * @param ctx read / write interface definitions
4032 * @param val change the values of sleep_g in reg CTRL4_C
4033 * @retval interface status (MANDATORY: return 0 -> no Error).
4034 *
4035 */
lsm6dso32x_gy_sleep_mode_set(stmdev_ctx_t * ctx,uint8_t val)4036 int32_t lsm6dso32x_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
4037 {
4038 lsm6dso32x_ctrl4_c_t reg;
4039 int32_t ret;
4040
4041 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
4042
4043 if (ret == 0)
4044 {
4045 reg.sleep_g = val;
4046 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
4047 }
4048
4049 return ret;
4050 }
4051
4052 /**
4053 * @brief Enables gyroscope Sleep mode.[get]
4054 *
4055 * @param ctx read / write interface definitions
4056 * @param val change the values of sleep_g in reg CTRL4_C
4057 * @retval interface status (MANDATORY: return 0 -> no Error).
4058 *
4059 */
lsm6dso32x_gy_sleep_mode_get(stmdev_ctx_t * ctx,uint8_t * val)4060 int32_t lsm6dso32x_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
4061 {
4062 lsm6dso32x_ctrl4_c_t reg;
4063 int32_t ret;
4064
4065 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C, (uint8_t *)®, 1);
4066 *val = reg.sleep_g;
4067
4068 return ret;
4069 }
4070
4071 /**
4072 * @brief Drives the sleep status instead of
4073 * sleep change on INT pins
4074 * (only if INT1_SLEEP_CHANGE or
4075 * INT2_SLEEP_CHANGE bits are enabled).[set]
4076 *
4077 * @param ctx read / write interface definitions
4078 * @param val change the values of sleep_status_on_int in reg TAP_CFG0
4079 * @retval interface status (MANDATORY: return 0 -> no Error).
4080 *
4081 */
lsm6dso32x_act_pin_notification_set(stmdev_ctx_t * ctx,lsm6dso32x_sleep_status_on_int_t val)4082 int32_t lsm6dso32x_act_pin_notification_set(stmdev_ctx_t *ctx,
4083 lsm6dso32x_sleep_status_on_int_t val)
4084 {
4085 lsm6dso32x_tap_cfg0_t reg;
4086 int32_t ret;
4087
4088 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4089
4090 if (ret == 0)
4091 {
4092 reg.sleep_status_on_int = (uint8_t)val;
4093 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4094 }
4095
4096 return ret;
4097 }
4098
4099 /**
4100 * @brief Drives the sleep status instead of
4101 * sleep change on INT pins (only if
4102 * INT1_SLEEP_CHANGE or
4103 * INT2_SLEEP_CHANGE bits are enabled).[get]
4104 *
4105 * @param ctx read / write interface definitions
4106 * @param val Get the values of sleep_status_on_int in reg TAP_CFG0
4107 * @retval interface status (MANDATORY: return 0 -> no Error).
4108 *
4109 */
lsm6dso32x_act_pin_notification_get(stmdev_ctx_t * ctx,lsm6dso32x_sleep_status_on_int_t * val)4110 int32_t lsm6dso32x_act_pin_notification_get(stmdev_ctx_t *ctx,
4111 lsm6dso32x_sleep_status_on_int_t *val)
4112 {
4113 lsm6dso32x_tap_cfg0_t reg;
4114 int32_t ret;
4115
4116 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4117
4118 switch (reg.sleep_status_on_int)
4119 {
4120 case LSM6DSO32X_DRIVE_SLEEP_CHG_EVENT:
4121 *val = LSM6DSO32X_DRIVE_SLEEP_CHG_EVENT;
4122 break;
4123
4124 case LSM6DSO32X_DRIVE_SLEEP_STATUS:
4125 *val = LSM6DSO32X_DRIVE_SLEEP_STATUS;
4126 break;
4127
4128 default:
4129 *val = LSM6DSO32X_DRIVE_SLEEP_CHG_EVENT;
4130 break;
4131 }
4132
4133 return ret;
4134 }
4135
4136 /**
4137 * @brief Enable inactivity function.[set]
4138 *
4139 * @param ctx read / write interface definitions
4140 * @param val change the values of inact_en in reg TAP_CFG2
4141 * @retval interface status (MANDATORY: return 0 -> no Error).
4142 *
4143 */
lsm6dso32x_act_mode_set(stmdev_ctx_t * ctx,lsm6dso32x_inact_en_t val)4144 int32_t lsm6dso32x_act_mode_set(stmdev_ctx_t *ctx,
4145 lsm6dso32x_inact_en_t val)
4146 {
4147 lsm6dso32x_tap_cfg2_t reg;
4148 int32_t ret;
4149
4150 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1);
4151
4152 if (ret == 0)
4153 {
4154 reg.inact_en = (uint8_t)val;
4155 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1);
4156 }
4157
4158 return ret;
4159 }
4160
4161 /**
4162 * @brief Enable inactivity function.[get]
4163 *
4164 * @param ctx read / write interface definitions
4165 * @param val Get the values of inact_en in reg TAP_CFG2
4166 * @retval interface status (MANDATORY: return 0 -> no Error).
4167 *
4168 */
lsm6dso32x_act_mode_get(stmdev_ctx_t * ctx,lsm6dso32x_inact_en_t * val)4169 int32_t lsm6dso32x_act_mode_get(stmdev_ctx_t *ctx,
4170 lsm6dso32x_inact_en_t *val)
4171 {
4172 lsm6dso32x_tap_cfg2_t reg;
4173 int32_t ret;
4174
4175 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1);
4176
4177 switch (reg.inact_en)
4178 {
4179 case LSM6DSO32X_XL_AND_GY_NOT_AFFECTED:
4180 *val = LSM6DSO32X_XL_AND_GY_NOT_AFFECTED;
4181 break;
4182
4183 case LSM6DSO32X_XL_12Hz5_GY_NOT_AFFECTED:
4184 *val = LSM6DSO32X_XL_12Hz5_GY_NOT_AFFECTED;
4185 break;
4186
4187 case LSM6DSO32X_XL_12Hz5_GY_SLEEP:
4188 *val = LSM6DSO32X_XL_12Hz5_GY_SLEEP;
4189 break;
4190
4191 case LSM6DSO32X_XL_12Hz5_GY_PD:
4192 *val = LSM6DSO32X_XL_12Hz5_GY_PD;
4193 break;
4194
4195 default:
4196 *val = LSM6DSO32X_XL_AND_GY_NOT_AFFECTED;
4197 break;
4198 }
4199
4200 return ret;
4201 }
4202
4203 /**
4204 * @brief Duration to go in sleep mode.[set]
4205 * 1 LSb = 512 / ODR
4206 *
4207 * @param ctx read / write interface definitions
4208 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
4209 * @retval interface status (MANDATORY: return 0 -> no Error).
4210 *
4211 */
lsm6dso32x_act_sleep_dur_set(stmdev_ctx_t * ctx,uint8_t val)4212 int32_t lsm6dso32x_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
4213 {
4214 lsm6dso32x_wake_up_dur_t reg;
4215 int32_t ret;
4216
4217 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
4218 (uint8_t *)®, 1);
4219
4220 if (ret == 0)
4221 {
4222 reg.sleep_dur = val;
4223 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
4224 (uint8_t *)®, 1);
4225 }
4226
4227 return ret;
4228 }
4229
4230 /**
4231 * @brief Duration to go in sleep mode.[get]
4232 * 1 LSb = 512 / ODR
4233 *
4234 * @param ctx read / write interface definitions
4235 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
4236 * @retval interface status (MANDATORY: return 0 -> no Error).
4237 *
4238 */
lsm6dso32x_act_sleep_dur_get(stmdev_ctx_t * ctx,uint8_t * val)4239 int32_t lsm6dso32x_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
4240 {
4241 lsm6dso32x_wake_up_dur_t reg;
4242 int32_t ret;
4243
4244 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
4245 (uint8_t *)®, 1);
4246 *val = reg.sleep_dur;
4247
4248 return ret;
4249 }
4250
4251 /**
4252 * @}
4253 *
4254 */
4255
4256 /**
4257 * @defgroup LSM6DSO32X_tap_generator
4258 * @brief This section groups all the functions that manage the
4259 * tap and double tap event generation.
4260 * @{
4261 *
4262 */
4263
4264 /**
4265 * @brief Enable Z direction in tap recognition.[set]
4266 *
4267 * @param ctx read / write interface definitions
4268 * @param val change the values of tap_z_en in reg TAP_CFG0
4269 * @retval interface status (MANDATORY: return 0 -> no Error).
4270 *
4271 */
lsm6dso32x_tap_detection_on_z_set(stmdev_ctx_t * ctx,uint8_t val)4272 int32_t lsm6dso32x_tap_detection_on_z_set(stmdev_ctx_t *ctx,
4273 uint8_t val)
4274 {
4275 lsm6dso32x_tap_cfg0_t reg;
4276 int32_t ret;
4277
4278 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4279
4280 if (ret == 0)
4281 {
4282 reg.tap_z_en = val;
4283 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4284 }
4285
4286 return ret;
4287 }
4288
4289 /**
4290 * @brief Enable Z direction in tap recognition.[get]
4291 *
4292 * @param ctx read / write interface definitions
4293 * @param val change the values of tap_z_en in reg TAP_CFG0
4294 * @retval interface status (MANDATORY: return 0 -> no Error).
4295 *
4296 */
lsm6dso32x_tap_detection_on_z_get(stmdev_ctx_t * ctx,uint8_t * val)4297 int32_t lsm6dso32x_tap_detection_on_z_get(stmdev_ctx_t *ctx,
4298 uint8_t *val)
4299 {
4300 lsm6dso32x_tap_cfg0_t reg;
4301 int32_t ret;
4302
4303 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4304 *val = reg.tap_z_en;
4305
4306 return ret;
4307 }
4308
4309 /**
4310 * @brief Enable Y direction in tap recognition.[set]
4311 *
4312 * @param ctx read / write interface definitions
4313 * @param val change the values of tap_y_en in reg TAP_CFG0
4314 * @retval interface status (MANDATORY: return 0 -> no Error).
4315 *
4316 */
lsm6dso32x_tap_detection_on_y_set(stmdev_ctx_t * ctx,uint8_t val)4317 int32_t lsm6dso32x_tap_detection_on_y_set(stmdev_ctx_t *ctx,
4318 uint8_t val)
4319 {
4320 lsm6dso32x_tap_cfg0_t reg;
4321 int32_t ret;
4322
4323 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4324
4325 if (ret == 0)
4326 {
4327 reg.tap_y_en = val;
4328 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4329 }
4330
4331 return ret;
4332 }
4333
4334 /**
4335 * @brief Enable Y direction in tap recognition.[get]
4336 *
4337 * @param ctx read / write interface definitions
4338 * @param val change the values of tap_y_en in reg TAP_CFG0
4339 * @retval interface status (MANDATORY: return 0 -> no Error).
4340 *
4341 */
lsm6dso32x_tap_detection_on_y_get(stmdev_ctx_t * ctx,uint8_t * val)4342 int32_t lsm6dso32x_tap_detection_on_y_get(stmdev_ctx_t *ctx,
4343 uint8_t *val)
4344 {
4345 lsm6dso32x_tap_cfg0_t reg;
4346 int32_t ret;
4347
4348 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4349 *val = reg.tap_y_en;
4350
4351 return ret;
4352 }
4353
4354 /**
4355 * @brief Enable X direction in tap recognition.[set]
4356 *
4357 * @param ctx read / write interface definitions
4358 * @param val change the values of tap_x_en in reg TAP_CFG0
4359 * @retval interface status (MANDATORY: return 0 -> no Error).
4360 *
4361 */
lsm6dso32x_tap_detection_on_x_set(stmdev_ctx_t * ctx,uint8_t val)4362 int32_t lsm6dso32x_tap_detection_on_x_set(stmdev_ctx_t *ctx,
4363 uint8_t val)
4364 {
4365 lsm6dso32x_tap_cfg0_t reg;
4366 int32_t ret;
4367
4368 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4369
4370 if (ret == 0)
4371 {
4372 reg.tap_x_en = val;
4373 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4374 }
4375
4376 return ret;
4377 }
4378
4379 /**
4380 * @brief Enable X direction in tap recognition.[get]
4381 *
4382 * @param ctx read / write interface definitions
4383 * @param val change the values of tap_x_en in reg TAP_CFG0
4384 * @retval interface status (MANDATORY: return 0 -> no Error).
4385 *
4386 */
lsm6dso32x_tap_detection_on_x_get(stmdev_ctx_t * ctx,uint8_t * val)4387 int32_t lsm6dso32x_tap_detection_on_x_get(stmdev_ctx_t *ctx,
4388 uint8_t *val)
4389 {
4390 lsm6dso32x_tap_cfg0_t reg;
4391 int32_t ret;
4392
4393 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0, (uint8_t *)®, 1);
4394 *val = reg.tap_x_en;
4395
4396 return ret;
4397 }
4398
4399 /**
4400 * @brief X-axis tap recognition threshold.[set]
4401 *
4402 * @param ctx read / write interface definitions
4403 * @param val change the values of tap_ths_x in reg TAP_CFG1
4404 * @retval interface status (MANDATORY: return 0 -> no Error).
4405 *
4406 */
lsm6dso32x_tap_threshold_x_set(stmdev_ctx_t * ctx,uint8_t val)4407 int32_t lsm6dso32x_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
4408 {
4409 lsm6dso32x_tap_cfg1_t reg;
4410 int32_t ret;
4411
4412 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1);
4413
4414 if (ret == 0)
4415 {
4416 reg.tap_ths_x = val;
4417 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1);
4418 }
4419
4420 return ret;
4421 }
4422
4423 /**
4424 * @brief X-axis tap recognition threshold.[get]
4425 *
4426 * @param ctx read / write interface definitions
4427 * @param val change the values of tap_ths_x in reg TAP_CFG1
4428 * @retval interface status (MANDATORY: return 0 -> no Error).
4429 *
4430 */
lsm6dso32x_tap_threshold_x_get(stmdev_ctx_t * ctx,uint8_t * val)4431 int32_t lsm6dso32x_tap_threshold_x_get(stmdev_ctx_t *ctx,
4432 uint8_t *val)
4433 {
4434 lsm6dso32x_tap_cfg1_t reg;
4435 int32_t ret;
4436
4437 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1);
4438 *val = reg.tap_ths_x;
4439
4440 return ret;
4441 }
4442
4443 /**
4444 * @brief Selection of axis priority for TAP detection.[set]
4445 *
4446 * @param ctx read / write interface definitions
4447 * @param val change the values of tap_priority in
4448 * reg TAP_CFG1
4449 * @retval interface status (MANDATORY: return 0 -> no Error).
4450 *
4451 */
lsm6dso32x_tap_axis_priority_set(stmdev_ctx_t * ctx,lsm6dso32x_tap_priority_t val)4452 int32_t lsm6dso32x_tap_axis_priority_set(stmdev_ctx_t *ctx,
4453 lsm6dso32x_tap_priority_t val)
4454 {
4455 lsm6dso32x_tap_cfg1_t reg;
4456 int32_t ret;
4457
4458 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1);
4459
4460 if (ret == 0)
4461 {
4462 reg.tap_priority = (uint8_t)val;
4463 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1);
4464 }
4465
4466 return ret;
4467 }
4468
4469 /**
4470 * @brief Selection of axis priority for TAP detection.[get]
4471 *
4472 * @param ctx read / write interface definitions
4473 * @param val Get the values of tap_priority in
4474 * reg TAP_CFG1
4475 * @retval interface status (MANDATORY: return 0 -> no Error).
4476 *
4477 */
lsm6dso32x_tap_axis_priority_get(stmdev_ctx_t * ctx,lsm6dso32x_tap_priority_t * val)4478 int32_t lsm6dso32x_tap_axis_priority_get(stmdev_ctx_t *ctx,
4479 lsm6dso32x_tap_priority_t *val)
4480 {
4481 lsm6dso32x_tap_cfg1_t reg;
4482 int32_t ret;
4483
4484 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG1, (uint8_t *)®, 1);
4485
4486 switch (reg.tap_priority)
4487 {
4488 case LSM6DSO32X_XYZ:
4489 *val = LSM6DSO32X_XYZ;
4490 break;
4491
4492 case LSM6DSO32X_YXZ:
4493 *val = LSM6DSO32X_YXZ;
4494 break;
4495
4496 case LSM6DSO32X_XZY:
4497 *val = LSM6DSO32X_XZY;
4498 break;
4499
4500 case LSM6DSO32X_ZYX:
4501 *val = LSM6DSO32X_ZYX;
4502 break;
4503
4504 case LSM6DSO32X_YZX:
4505 *val = LSM6DSO32X_YZX;
4506 break;
4507
4508 case LSM6DSO32X_ZXY:
4509 *val = LSM6DSO32X_ZXY;
4510 break;
4511
4512 default:
4513 *val = LSM6DSO32X_XYZ;
4514 break;
4515 }
4516
4517 return ret;
4518 }
4519
4520 /**
4521 * @brief Y-axis tap recognition threshold.[set]
4522 *
4523 * @param ctx read / write interface definitions
4524 * @param val change the values of tap_ths_y in reg TAP_CFG2
4525 * @retval interface status (MANDATORY: return 0 -> no Error).
4526 *
4527 */
lsm6dso32x_tap_threshold_y_set(stmdev_ctx_t * ctx,uint8_t val)4528 int32_t lsm6dso32x_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
4529 {
4530 lsm6dso32x_tap_cfg2_t reg;
4531 int32_t ret;
4532
4533 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1);
4534
4535 if (ret == 0)
4536 {
4537 reg.tap_ths_y = val;
4538 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1);
4539 }
4540
4541 return ret;
4542 }
4543
4544 /**
4545 * @brief Y-axis tap recognition threshold.[get]
4546 *
4547 * @param ctx read / write interface definitions
4548 * @param val change the values of tap_ths_y in reg TAP_CFG2
4549 * @retval interface status (MANDATORY: return 0 -> no Error).
4550 *
4551 */
lsm6dso32x_tap_threshold_y_get(stmdev_ctx_t * ctx,uint8_t * val)4552 int32_t lsm6dso32x_tap_threshold_y_get(stmdev_ctx_t *ctx,
4553 uint8_t *val)
4554 {
4555 lsm6dso32x_tap_cfg2_t reg;
4556 int32_t ret;
4557
4558 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2, (uint8_t *)®, 1);
4559 *val = reg.tap_ths_y;
4560
4561 return ret;
4562 }
4563
4564 /**
4565 * @brief Z-axis recognition threshold.[set]
4566 *
4567 * @param ctx read / write interface definitions
4568 * @param val change the values of tap_ths_z in reg TAP_THS_6D
4569 * @retval interface status (MANDATORY: return 0 -> no Error).
4570 *
4571 */
lsm6dso32x_tap_threshold_z_set(stmdev_ctx_t * ctx,uint8_t val)4572 int32_t lsm6dso32x_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
4573 {
4574 lsm6dso32x_tap_ths_6d_t reg;
4575 int32_t ret;
4576
4577 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1);
4578
4579 if (ret == 0)
4580 {
4581 reg.tap_ths_z = val;
4582 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_THS_6D,
4583 (uint8_t *)®, 1);
4584 }
4585
4586 return ret;
4587 }
4588
4589 /**
4590 * @brief Z-axis recognition threshold.[get]
4591 *
4592 * @param ctx read / write interface definitions
4593 * @param val change the values of tap_ths_z in reg TAP_THS_6D
4594 * @retval interface status (MANDATORY: return 0 -> no Error).
4595 *
4596 */
lsm6dso32x_tap_threshold_z_get(stmdev_ctx_t * ctx,uint8_t * val)4597 int32_t lsm6dso32x_tap_threshold_z_get(stmdev_ctx_t *ctx,
4598 uint8_t *val)
4599 {
4600 lsm6dso32x_tap_ths_6d_t reg;
4601 int32_t ret;
4602
4603 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1);
4604 *val = reg.tap_ths_z;
4605
4606 return ret;
4607 }
4608
4609 /**
4610 * @brief Maximum duration is the maximum time of an
4611 * over threshold signal detection to be recognized
4612 * as a tap event. The default value of these bits
4613 * is 00b which corresponds to 4*ODR_XL time.
4614 * If the SHOCK[1:0] bits are set to a different
4615 * value, 1LSB corresponds to 8*ODR_XL time.[set]
4616 *
4617 * @param ctx read / write interface definitions
4618 * @param val change the values of shock in reg INT_DUR2
4619 * @retval interface status (MANDATORY: return 0 -> no Error).
4620 *
4621 */
lsm6dso32x_tap_shock_set(stmdev_ctx_t * ctx,uint8_t val)4622 int32_t lsm6dso32x_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
4623 {
4624 lsm6dso32x_int_dur2_t reg;
4625 int32_t ret;
4626
4627 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
4628
4629 if (ret == 0)
4630 {
4631 reg.shock = val;
4632 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
4633 }
4634
4635 return ret;
4636 }
4637
4638 /**
4639 * @brief Maximum duration is the maximum time of an
4640 * over threshold signal detection to be recognized
4641 * as a tap event. The default value of these bits
4642 * is 00b which corresponds to 4*ODR_XL time.
4643 * If the SHOCK[1:0] bits are set to a different
4644 * value, 1LSB corresponds to 8*ODR_XL time.[get]
4645 *
4646 * @param ctx read / write interface definitions
4647 * @param val change the values of shock in reg INT_DUR2
4648 * @retval interface status (MANDATORY: return 0 -> no Error).
4649 *
4650 */
lsm6dso32x_tap_shock_get(stmdev_ctx_t * ctx,uint8_t * val)4651 int32_t lsm6dso32x_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
4652 {
4653 lsm6dso32x_int_dur2_t reg;
4654 int32_t ret;
4655
4656 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
4657 *val = reg.shock;
4658
4659 return ret;
4660 }
4661
4662 /**
4663 * @brief Quiet time is the time after the first detected
4664 * tap in which there must not be any over threshold
4665 * event.
4666 * The default value of these bits is 00b which
4667 * corresponds to 2*ODR_XL time. If the QUIET[1:0]
4668 * bits are set to a different value,
4669 * 1LSB corresponds to 4*ODR_XL time.[set]
4670 *
4671 * @param ctx read / write interface definitions
4672 * @param val change the values of quiet in reg INT_DUR2
4673 * @retval interface status (MANDATORY: return 0 -> no Error).
4674 *
4675 */
lsm6dso32x_tap_quiet_set(stmdev_ctx_t * ctx,uint8_t val)4676 int32_t lsm6dso32x_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
4677 {
4678 lsm6dso32x_int_dur2_t reg;
4679 int32_t ret;
4680
4681 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
4682
4683 if (ret == 0)
4684 {
4685 reg.quiet = val;
4686 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
4687 }
4688
4689 return ret;
4690 }
4691
4692 /**
4693 * @brief Quiet time is the time after the first detected
4694 * tap in which there must not be any over threshold
4695 * event.
4696 * The default value of these bits is 00b which
4697 * corresponds to 2*ODR_XL time.
4698 * If the QUIET[1:0] bits are set to a different
4699 * value, 1LSB corresponds to 4*ODR_XL time.[get]
4700 *
4701 * @param ctx read / write interface definitions
4702 * @param val change the values of quiet in reg INT_DUR2
4703 * @retval interface status (MANDATORY: return 0 -> no Error).
4704 *
4705 */
lsm6dso32x_tap_quiet_get(stmdev_ctx_t * ctx,uint8_t * val)4706 int32_t lsm6dso32x_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
4707 {
4708 lsm6dso32x_int_dur2_t reg;
4709 int32_t ret;
4710
4711 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
4712 *val = reg.quiet;
4713
4714 return ret;
4715 }
4716
4717 /**
4718 * @brief When double tap recognition is enabled,
4719 * this register expresses the maximum time
4720 * between two consecutive detected taps to
4721 * determine a double tap event.
4722 * The default value of these bits is 0000b which
4723 * corresponds to 16*ODR_XL time.
4724 * If the DUR[3:0] bits are set to a different value,
4725 * 1LSB corresponds to 32*ODR_XL time.[set]
4726 *
4727 * @param ctx read / write interface definitions
4728 * @param val change the values of dur in reg INT_DUR2
4729 * @retval interface status (MANDATORY: return 0 -> no Error).
4730 *
4731 */
lsm6dso32x_tap_dur_set(stmdev_ctx_t * ctx,uint8_t val)4732 int32_t lsm6dso32x_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
4733 {
4734 lsm6dso32x_int_dur2_t reg;
4735 int32_t ret;
4736
4737 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
4738
4739 if (ret == 0)
4740 {
4741 reg.dur = val;
4742 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
4743 }
4744
4745 return ret;
4746 }
4747
4748 /**
4749 * @brief When double tap recognition is enabled,
4750 * this register expresses the maximum time
4751 * between two consecutive detected taps to
4752 * determine a double tap event.
4753 * The default value of these bits is 0000b which
4754 * corresponds to 16*ODR_XL time. If the DUR[3:0]
4755 * bits are set to a different value,
4756 * 1LSB corresponds to 32*ODR_XL time.[get]
4757 *
4758 * @param ctx read / write interface definitions
4759 * @param val change the values of dur in reg INT_DUR2
4760 * @retval interface status (MANDATORY: return 0 -> no Error).
4761 *
4762 */
lsm6dso32x_tap_dur_get(stmdev_ctx_t * ctx,uint8_t * val)4763 int32_t lsm6dso32x_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
4764 {
4765 lsm6dso32x_int_dur2_t reg;
4766 int32_t ret;
4767
4768 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT_DUR2, (uint8_t *)®, 1);
4769 *val = reg.dur;
4770
4771 return ret;
4772 }
4773
4774 /**
4775 * @brief Single/double-tap event enable.[set]
4776 *
4777 * @param ctx read / write interface definitions
4778 * @param val change the values of single_double_tap in reg WAKE_UP_THS
4779 * @retval interface status (MANDATORY: return 0 -> no Error).
4780 *
4781 */
lsm6dso32x_tap_mode_set(stmdev_ctx_t * ctx,lsm6dso32x_single_double_tap_t val)4782 int32_t lsm6dso32x_tap_mode_set(stmdev_ctx_t *ctx,
4783 lsm6dso32x_single_double_tap_t val)
4784 {
4785 lsm6dso32x_wake_up_ths_t reg;
4786 int32_t ret;
4787
4788 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
4789 (uint8_t *)®, 1);
4790
4791 if (ret == 0)
4792 {
4793 reg.single_double_tap = (uint8_t)val;
4794 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
4795 (uint8_t *)®, 1);
4796 }
4797
4798 return ret;
4799 }
4800
4801 /**
4802 * @brief Single/double-tap event enable.[get]
4803 *
4804 * @param ctx read / write interface definitions
4805 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
4806 * @retval interface status (MANDATORY: return 0 -> no Error).
4807 *
4808 */
lsm6dso32x_tap_mode_get(stmdev_ctx_t * ctx,lsm6dso32x_single_double_tap_t * val)4809 int32_t lsm6dso32x_tap_mode_get(stmdev_ctx_t *ctx,
4810 lsm6dso32x_single_double_tap_t *val)
4811 {
4812 lsm6dso32x_wake_up_ths_t reg;
4813 int32_t ret;
4814
4815 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_THS,
4816 (uint8_t *)®, 1);
4817
4818 switch (reg.single_double_tap)
4819 {
4820 case LSM6DSO32X_ONLY_SINGLE:
4821 *val = LSM6DSO32X_ONLY_SINGLE;
4822 break;
4823
4824 case LSM6DSO32X_BOTH_SINGLE_DOUBLE:
4825 *val = LSM6DSO32X_BOTH_SINGLE_DOUBLE;
4826 break;
4827
4828 default:
4829 *val = LSM6DSO32X_ONLY_SINGLE;
4830 break;
4831 }
4832
4833 return ret;
4834 }
4835
4836 /**
4837 * @}
4838 *
4839 */
4840
4841 /**
4842 * @defgroup LSM6DSO32X_ Six_position_detection(6D/4D)
4843 * @brief This section groups all the functions concerning six position
4844 * detection (6D).
4845 * @{
4846 *
4847 */
4848
4849 /**
4850 * @brief Threshold for 4D/6D function.[set]
4851 *
4852 * @param ctx read / write interface definitions
4853 * @param val change the values of sixd_ths in reg TAP_THS_6D
4854 * @retval interface status (MANDATORY: return 0 -> no Error).
4855 *
4856 */
lsm6dso32x_6d_threshold_set(stmdev_ctx_t * ctx,lsm6dso32x_sixd_ths_t val)4857 int32_t lsm6dso32x_6d_threshold_set(stmdev_ctx_t *ctx,
4858 lsm6dso32x_sixd_ths_t val)
4859 {
4860 lsm6dso32x_tap_ths_6d_t reg;
4861 int32_t ret;
4862
4863 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1);
4864
4865 if (ret == 0)
4866 {
4867 reg.sixd_ths = (uint8_t)val;
4868 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_THS_6D,
4869 (uint8_t *)®, 1);
4870 }
4871
4872 return ret;
4873 }
4874
4875 /**
4876 * @brief Threshold for 4D/6D function.[get]
4877 *
4878 * @param ctx read / write interface definitions
4879 * @param val Get the values of sixd_ths in reg TAP_THS_6D
4880 * @retval interface status (MANDATORY: return 0 -> no Error).
4881 *
4882 */
lsm6dso32x_6d_threshold_get(stmdev_ctx_t * ctx,lsm6dso32x_sixd_ths_t * val)4883 int32_t lsm6dso32x_6d_threshold_get(stmdev_ctx_t *ctx,
4884 lsm6dso32x_sixd_ths_t *val)
4885 {
4886 lsm6dso32x_tap_ths_6d_t reg;
4887 int32_t ret;
4888
4889 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1);
4890
4891 switch (reg.sixd_ths)
4892 {
4893 case LSM6DSO32X_DEG_80:
4894 *val = LSM6DSO32X_DEG_80;
4895 break;
4896
4897 case LSM6DSO32X_DEG_70:
4898 *val = LSM6DSO32X_DEG_70;
4899 break;
4900
4901 case LSM6DSO32X_DEG_60:
4902 *val = LSM6DSO32X_DEG_60;
4903 break;
4904
4905 case LSM6DSO32X_DEG_50:
4906 *val = LSM6DSO32X_DEG_50;
4907 break;
4908
4909 default:
4910 *val = LSM6DSO32X_DEG_80;
4911 break;
4912 }
4913
4914 return ret;
4915 }
4916
4917 /**
4918 * @brief 4D orientation detection enable.[set]
4919 *
4920 * @param ctx read / write interface definitions
4921 * @param val change the values of d4d_en in reg TAP_THS_6D
4922 * @retval interface status (MANDATORY: return 0 -> no Error).
4923 *
4924 */
lsm6dso32x_4d_mode_set(stmdev_ctx_t * ctx,uint8_t val)4925 int32_t lsm6dso32x_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
4926 {
4927 lsm6dso32x_tap_ths_6d_t reg;
4928 int32_t ret;
4929
4930 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1);
4931
4932 if (ret == 0)
4933 {
4934 reg.d4d_en = val;
4935 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_THS_6D,
4936 (uint8_t *)®, 1);
4937 }
4938
4939 return ret;
4940 }
4941
4942 /**
4943 * @brief 4D orientation detection enable.[get]
4944 *
4945 * @param ctx read / write interface definitions
4946 * @param val change the values of d4d_en in reg TAP_THS_6D
4947 * @retval interface status (MANDATORY: return 0 -> no Error).
4948 *
4949 */
lsm6dso32x_4d_mode_get(stmdev_ctx_t * ctx,uint8_t * val)4950 int32_t lsm6dso32x_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
4951 {
4952 lsm6dso32x_tap_ths_6d_t reg;
4953 int32_t ret;
4954
4955 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_THS_6D, (uint8_t *)®, 1);
4956 *val = reg.d4d_en;
4957
4958 return ret;
4959 }
4960
4961 /**
4962 * @}
4963 *
4964 */
4965
4966 /**
4967 * @defgroup LSM6DSO32X_free_fall
4968 * @brief This section group all the functions concerning the free
4969 * fall detection.
4970 * @{
4971 *
4972 */
4973 /**
4974 * @brief Free fall threshold setting.[set]
4975 *
4976 * @param ctx read / write interface definitions
4977 * @param val change the values of ff_ths in reg FREE_FALL
4978 * @retval interface status (MANDATORY: return 0 -> no Error).
4979 *
4980 */
lsm6dso32x_ff_threshold_set(stmdev_ctx_t * ctx,lsm6dso32x_ff_ths_t val)4981 int32_t lsm6dso32x_ff_threshold_set(stmdev_ctx_t *ctx,
4982 lsm6dso32x_ff_ths_t val)
4983 {
4984 lsm6dso32x_free_fall_t reg;
4985 int32_t ret;
4986
4987 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FREE_FALL, (uint8_t *)®, 1);
4988
4989 if (ret == 0)
4990 {
4991 reg.ff_ths = (uint8_t)val;
4992 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FREE_FALL, (uint8_t *)®, 1);
4993 }
4994
4995 return ret;
4996 }
4997
4998 /**
4999 * @brief Free fall threshold setting.[get]
5000 *
5001 * @param ctx read / write interface definitions
5002 * @param val Get the values of ff_ths in reg FREE_FALL
5003 * @retval interface status (MANDATORY: return 0 -> no Error).
5004 *
5005 */
lsm6dso32x_ff_threshold_get(stmdev_ctx_t * ctx,lsm6dso32x_ff_ths_t * val)5006 int32_t lsm6dso32x_ff_threshold_get(stmdev_ctx_t *ctx,
5007 lsm6dso32x_ff_ths_t *val)
5008 {
5009 lsm6dso32x_free_fall_t reg;
5010 int32_t ret;
5011
5012 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FREE_FALL, (uint8_t *)®, 1);
5013
5014 switch (reg.ff_ths)
5015 {
5016 case LSM6DSO32X_FF_TSH_312mg:
5017 *val = LSM6DSO32X_FF_TSH_312mg;
5018 break;
5019
5020 case LSM6DSO32X_FF_TSH_438mg:
5021 *val = LSM6DSO32X_FF_TSH_438mg;
5022 break;
5023
5024 case LSM6DSO32X_FF_TSH_500mg:
5025 *val = LSM6DSO32X_FF_TSH_500mg;
5026 break;
5027
5028 default:
5029 *val = LSM6DSO32X_FF_TSH_312mg;
5030 break;
5031 }
5032
5033 return ret;
5034 }
5035
5036 /**
5037 * @brief Free-fall duration event.[set]
5038 * 1LSb = 1 / ODR
5039 *
5040 * @param ctx read / write interface definitions
5041 * @param val change the values of ff_dur in reg FREE_FALL
5042 * @retval interface status (MANDATORY: return 0 -> no Error).
5043 *
5044 */
lsm6dso32x_ff_dur_set(stmdev_ctx_t * ctx,uint8_t val)5045 int32_t lsm6dso32x_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
5046 {
5047 lsm6dso32x_wake_up_dur_t wake_up_dur;
5048 lsm6dso32x_free_fall_t free_fall;
5049 int32_t ret;
5050
5051 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
5052 (uint8_t *)&wake_up_dur, 1);
5053
5054 if (ret == 0)
5055 {
5056 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FREE_FALL,
5057 (uint8_t *)&free_fall, 1);
5058 }
5059
5060 if (ret == 0)
5061 {
5062 wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
5063 free_fall.ff_dur = (uint8_t)val & 0x1FU;
5064 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
5065 (uint8_t *)&wake_up_dur, 1);
5066 }
5067
5068 if (ret == 0)
5069 {
5070 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FREE_FALL,
5071 (uint8_t *)&free_fall, 1);
5072 }
5073
5074 return ret;
5075 }
5076
5077 /**
5078 * @brief Free-fall duration event.[get]
5079 * 1LSb = 1 / ODR
5080 *
5081 * @param ctx read / write interface definitions
5082 * @param val change the values of ff_dur in reg FREE_FALL
5083 * @retval interface status (MANDATORY: return 0 -> no Error).
5084 *
5085 */
lsm6dso32x_ff_dur_get(stmdev_ctx_t * ctx,uint8_t * val)5086 int32_t lsm6dso32x_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
5087 {
5088 lsm6dso32x_wake_up_dur_t wake_up_dur;
5089 lsm6dso32x_free_fall_t free_fall;
5090 int32_t ret;
5091
5092 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WAKE_UP_DUR,
5093 (uint8_t *)&wake_up_dur, 1);
5094
5095 if (ret == 0)
5096 {
5097 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FREE_FALL,
5098 (uint8_t *)&free_fall, 1);
5099 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
5100 }
5101
5102 return ret;
5103 }
5104
5105 /**
5106 * @}
5107 *
5108 */
5109
5110 /**
5111 * @defgroup LSM6DSO32X_fifo
5112 * @brief This section group all the functions concerning the fifo usage
5113 * @{
5114 *
5115 */
5116
5117 /**
5118 * @brief FIFO watermark level selection.[set]
5119 *
5120 * @param ctx read / write interface definitions
5121 * @param val change the values of wtm in reg FIFO_CTRL1
5122 * @retval interface status (MANDATORY: return 0 -> no Error).
5123 *
5124 */
lsm6dso32x_fifo_watermark_set(stmdev_ctx_t * ctx,uint16_t val)5125 int32_t lsm6dso32x_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
5126 {
5127 lsm6dso32x_fifo_ctrl1_t fifo_ctrl1;
5128 lsm6dso32x_fifo_ctrl2_t fifo_ctrl2;
5129 int32_t ret;
5130
5131 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
5132 (uint8_t *)&fifo_ctrl2, 1);
5133
5134 if (ret == 0)
5135 {
5136 fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val;
5137 fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8);
5138 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL1,
5139 (uint8_t *)&fifo_ctrl1, 1);
5140 }
5141
5142 if (ret == 0)
5143 {
5144 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
5145 (uint8_t *)&fifo_ctrl2, 1);
5146 }
5147
5148 return ret;
5149 }
5150
5151 /**
5152 * @brief FIFO watermark level selection.[get]
5153 *
5154 * @param ctx read / write interface definitions
5155 * @param val change the values of wtm in reg FIFO_CTRL1
5156 * @retval interface status (MANDATORY: return 0 -> no Error).
5157 *
5158 */
lsm6dso32x_fifo_watermark_get(stmdev_ctx_t * ctx,uint16_t * val)5159 int32_t lsm6dso32x_fifo_watermark_get(stmdev_ctx_t *ctx,
5160 uint16_t *val)
5161 {
5162 lsm6dso32x_fifo_ctrl1_t fifo_ctrl1;
5163 lsm6dso32x_fifo_ctrl2_t fifo_ctrl2;
5164 int32_t ret;
5165
5166 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL1,
5167 (uint8_t *)&fifo_ctrl1, 1);
5168
5169 if (ret == 0)
5170 {
5171 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
5172 (uint8_t *)&fifo_ctrl2, 1);
5173 *val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm;
5174 }
5175
5176 return ret;
5177 }
5178
5179 /**
5180 * @brief FIFO compression feature initialization request [set].
5181 *
5182 * @param ctx read / write interface definitions
5183 * @param val change the values of FIFO_COMPR_INIT in
5184 * reg EMB_FUNC_INIT_B
5185 * @retval interface status (MANDATORY: return 0 -> no Error).
5186 *
5187 */
lsm6dso32x_compression_algo_init_set(stmdev_ctx_t * ctx,uint8_t val)5188 int32_t lsm6dso32x_compression_algo_init_set(stmdev_ctx_t *ctx,
5189 uint8_t val)
5190 {
5191 lsm6dso32x_emb_func_init_b_t reg;
5192 int32_t ret;
5193
5194 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
5195
5196 if (ret == 0)
5197 {
5198 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
5199 (uint8_t *)®, 1);
5200 }
5201
5202 if (ret == 0)
5203 {
5204 reg.fifo_compr_init = val;
5205 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
5206 (uint8_t *)®, 1);
5207 }
5208
5209 if (ret == 0)
5210 {
5211 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
5212 }
5213
5214 return ret;
5215 }
5216
5217 /**
5218 * @brief FIFO compression feature initialization request [get].
5219 *
5220 * @param ctx read / write interface definitions
5221 * @param val change the values of FIFO_COMPR_INIT in
5222 * reg EMB_FUNC_INIT_B
5223 * @retval interface status (MANDATORY: return 0 -> no Error).
5224 *
5225 */
lsm6dso32x_compression_algo_init_get(stmdev_ctx_t * ctx,uint8_t * val)5226 int32_t lsm6dso32x_compression_algo_init_get(stmdev_ctx_t *ctx,
5227 uint8_t *val)
5228 {
5229 lsm6dso32x_emb_func_init_b_t reg;
5230 int32_t ret;
5231
5232 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
5233
5234 if (ret == 0)
5235 {
5236 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
5237 (uint8_t *)®, 1);
5238 }
5239
5240 if (ret == 0)
5241 {
5242 *val = reg.fifo_compr_init;
5243 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
5244 }
5245
5246 return ret;
5247 }
5248
5249 /**
5250 * @brief Enable and configure compression algo.[set]
5251 *
5252 * @param ctx read / write interface definitions
5253 * @param val change the values of uncoptr_rate in
5254 * reg FIFO_CTRL2
5255 * @retval interface status (MANDATORY: return 0 -> no Error).
5256 *
5257 */
lsm6dso32x_compression_algo_set(stmdev_ctx_t * ctx,lsm6dso32x_uncoptr_rate_t val)5258 int32_t lsm6dso32x_compression_algo_set(stmdev_ctx_t *ctx,
5259 lsm6dso32x_uncoptr_rate_t val)
5260 {
5261 lsm6dso32x_fifo_ctrl2_t fifo_ctrl2;
5262 int32_t ret;
5263
5264 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
5265 (uint8_t *)&fifo_ctrl2, 1);
5266
5267 if (ret == 0)
5268 {
5269 fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
5270 fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
5271 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
5272 (uint8_t *)&fifo_ctrl2, 1);
5273 }
5274
5275 return ret;
5276 }
5277
5278 /**
5279 * @brief Enable and configure compression algo.[get]
5280 *
5281 * @param ctx read / write interface definitions
5282 * @param val Get the values of uncoptr_rate in
5283 * reg FIFO_CTRL2
5284 * @retval interface status (MANDATORY: return 0 -> no Error).
5285 *
5286 */
lsm6dso32x_compression_algo_get(stmdev_ctx_t * ctx,lsm6dso32x_uncoptr_rate_t * val)5287 int32_t lsm6dso32x_compression_algo_get(stmdev_ctx_t *ctx,
5288 lsm6dso32x_uncoptr_rate_t *val)
5289 {
5290 lsm6dso32x_fifo_ctrl2_t reg;
5291 int32_t ret;
5292
5293 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
5294
5295 switch ((reg.fifo_compr_rt_en << 2) | reg.uncoptr_rate)
5296 {
5297 case LSM6DSO32X_CMP_DISABLE:
5298 *val = LSM6DSO32X_CMP_DISABLE;
5299 break;
5300
5301 case LSM6DSO32X_CMP_ALWAYS:
5302 *val = LSM6DSO32X_CMP_ALWAYS;
5303 break;
5304
5305 case LSM6DSO32X_CMP_8_TO_1:
5306 *val = LSM6DSO32X_CMP_8_TO_1;
5307 break;
5308
5309 case LSM6DSO32X_CMP_16_TO_1:
5310 *val = LSM6DSO32X_CMP_16_TO_1;
5311 break;
5312
5313 case LSM6DSO32X_CMP_32_TO_1:
5314 *val = LSM6DSO32X_CMP_32_TO_1;
5315 break;
5316
5317 default:
5318 *val = LSM6DSO32X_CMP_DISABLE;
5319 break;
5320 }
5321
5322 return ret;
5323 }
5324
5325 /**
5326 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
5327 *
5328 * @param ctx read / write interface definitions
5329 * @param val change the values of odrchg_en in reg FIFO_CTRL2
5330 * @retval interface status (MANDATORY: return 0 -> no Error).
5331 *
5332 */
lsm6dso32x_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t * ctx,uint8_t val)5333 int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
5334 uint8_t val)
5335 {
5336 lsm6dso32x_fifo_ctrl2_t reg;
5337 int32_t ret;
5338
5339 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
5340
5341 if (ret == 0)
5342 {
5343 reg.odrchg_en = val;
5344 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
5345 (uint8_t *)®, 1);
5346 }
5347
5348 return ret;
5349 }
5350
5351 /**
5352 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
5353 *
5354 * @param ctx read / write interface definitions
5355 * @param val change the values of odrchg_en in reg FIFO_CTRL2
5356 * @retval interface status (MANDATORY: return 0 -> no Error).
5357 *
5358 */
lsm6dso32x_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t * ctx,uint8_t * val)5359 int32_t lsm6dso32x_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
5360 uint8_t *val)
5361 {
5362 lsm6dso32x_fifo_ctrl2_t reg;
5363 int32_t ret;
5364
5365 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
5366 *val = reg.odrchg_en;
5367
5368 return ret;
5369 }
5370
5371 /**
5372 * @brief Enables/Disables compression algorithm runtime.[set]
5373 *
5374 * @param ctx read / write interface definitions
5375 * @param val change the values of fifo_compr_rt_en in
5376 * reg FIFO_CTRL2
5377 * @retval interface status (MANDATORY: return 0 -> no Error).
5378 *
5379 */
lsm6dso32x_compression_algo_real_time_set(stmdev_ctx_t * ctx,uint8_t val)5380 int32_t lsm6dso32x_compression_algo_real_time_set(stmdev_ctx_t *ctx,
5381 uint8_t val)
5382 {
5383 lsm6dso32x_fifo_ctrl2_t reg;
5384 int32_t ret;
5385
5386 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
5387
5388 if (ret == 0)
5389 {
5390 reg.fifo_compr_rt_en = val;
5391 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
5392 (uint8_t *)®, 1);
5393 }
5394
5395 return ret;
5396 }
5397
5398 /**
5399 * @brief Enables/Disables compression algorithm runtime. [get]
5400 *
5401 * @param ctx read / write interface definitions
5402 * @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2
5403 * @retval interface status (MANDATORY: return 0 -> no Error).
5404 *
5405 */
lsm6dso32x_compression_algo_real_time_get(stmdev_ctx_t * ctx,uint8_t * val)5406 int32_t lsm6dso32x_compression_algo_real_time_get(stmdev_ctx_t *ctx,
5407 uint8_t *val)
5408 {
5409 lsm6dso32x_fifo_ctrl2_t reg;
5410 int32_t ret;
5411
5412 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
5413 *val = reg.fifo_compr_rt_en;
5414
5415 return ret;
5416 }
5417
5418 /**
5419 * @brief Sensing chain FIFO stop values memorization at
5420 * threshold level.[set]
5421 *
5422 * @param ctx read / write interface definitions
5423 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2
5424 * @retval interface status (MANDATORY: return 0 -> no Error).
5425 *
5426 */
lsm6dso32x_fifo_stop_on_wtm_set(stmdev_ctx_t * ctx,uint8_t val)5427 int32_t lsm6dso32x_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx,
5428 uint8_t val)
5429 {
5430 lsm6dso32x_fifo_ctrl2_t reg;
5431 int32_t ret;
5432
5433 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
5434
5435 if (ret == 0)
5436 {
5437 reg.stop_on_wtm = val;
5438 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL2,
5439 (uint8_t *)®, 1);
5440 }
5441
5442 return ret;
5443 }
5444
5445 /**
5446 * @brief Sensing chain FIFO stop values memorization at
5447 * threshold level.[get]
5448 *
5449 * @param ctx read / write interface definitions
5450 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2
5451 * @retval interface status (MANDATORY: return 0 -> no Error).
5452 *
5453 */
lsm6dso32x_fifo_stop_on_wtm_get(stmdev_ctx_t * ctx,uint8_t * val)5454 int32_t lsm6dso32x_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
5455 uint8_t *val)
5456 {
5457 lsm6dso32x_fifo_ctrl2_t reg;
5458 int32_t ret;
5459
5460 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL2, (uint8_t *)®, 1);
5461 *val = reg.stop_on_wtm;
5462
5463 return ret;
5464 }
5465
5466 /**
5467 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5468 * for accelerometer data.[set]
5469 *
5470 * @param ctx read / write interface definitions
5471 * @param val change the values of bdr_xl in reg FIFO_CTRL3
5472 * @retval interface status (MANDATORY: return 0 -> no Error).
5473 *
5474 */
lsm6dso32x_fifo_xl_batch_set(stmdev_ctx_t * ctx,lsm6dso32x_bdr_xl_t val)5475 int32_t lsm6dso32x_fifo_xl_batch_set(stmdev_ctx_t *ctx,
5476 lsm6dso32x_bdr_xl_t val)
5477 {
5478 lsm6dso32x_fifo_ctrl3_t reg;
5479 int32_t ret;
5480
5481 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL3, (uint8_t *)®, 1);
5482
5483 if (ret == 0)
5484 {
5485 reg.bdr_xl = (uint8_t)val;
5486 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL3,
5487 (uint8_t *)®, 1);
5488 }
5489
5490 return ret;
5491 }
5492
5493 /**
5494 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5495 * for accelerometer data.[get]
5496 *
5497 * @param ctx read / write interface definitions
5498 * @param val Get the values of bdr_xl in reg FIFO_CTRL3
5499 * @retval interface status (MANDATORY: return 0 -> no Error).
5500 *
5501 */
lsm6dso32x_fifo_xl_batch_get(stmdev_ctx_t * ctx,lsm6dso32x_bdr_xl_t * val)5502 int32_t lsm6dso32x_fifo_xl_batch_get(stmdev_ctx_t *ctx,
5503 lsm6dso32x_bdr_xl_t *val)
5504 {
5505 lsm6dso32x_fifo_ctrl3_t reg;
5506 int32_t ret;
5507
5508 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL3, (uint8_t *)®, 1);
5509
5510 switch (reg.bdr_xl)
5511 {
5512 case LSM6DSO32X_XL_NOT_BATCHED:
5513 *val = LSM6DSO32X_XL_NOT_BATCHED;
5514 break;
5515
5516 case LSM6DSO32X_XL_BATCHED_AT_12Hz5:
5517 *val = LSM6DSO32X_XL_BATCHED_AT_12Hz5;
5518 break;
5519
5520 case LSM6DSO32X_XL_BATCHED_AT_26Hz:
5521 *val = LSM6DSO32X_XL_BATCHED_AT_26Hz;
5522 break;
5523
5524 case LSM6DSO32X_XL_BATCHED_AT_52Hz:
5525 *val = LSM6DSO32X_XL_BATCHED_AT_52Hz;
5526 break;
5527
5528 case LSM6DSO32X_XL_BATCHED_AT_104Hz:
5529 *val = LSM6DSO32X_XL_BATCHED_AT_104Hz;
5530 break;
5531
5532 case LSM6DSO32X_XL_BATCHED_AT_208Hz:
5533 *val = LSM6DSO32X_XL_BATCHED_AT_208Hz;
5534 break;
5535
5536 case LSM6DSO32X_XL_BATCHED_AT_417Hz:
5537 *val = LSM6DSO32X_XL_BATCHED_AT_417Hz;
5538 break;
5539
5540 case LSM6DSO32X_XL_BATCHED_AT_833Hz:
5541 *val = LSM6DSO32X_XL_BATCHED_AT_833Hz;
5542 break;
5543
5544 case LSM6DSO32X_XL_BATCHED_AT_1667Hz:
5545 *val = LSM6DSO32X_XL_BATCHED_AT_1667Hz;
5546 break;
5547
5548 case LSM6DSO32X_XL_BATCHED_AT_3333Hz:
5549 *val = LSM6DSO32X_XL_BATCHED_AT_3333Hz;
5550 break;
5551
5552 case LSM6DSO32X_XL_BATCHED_AT_6667Hz:
5553 *val = LSM6DSO32X_XL_BATCHED_AT_6667Hz;
5554 break;
5555
5556 case LSM6DSO32X_XL_BATCHED_AT_6Hz5:
5557 *val = LSM6DSO32X_XL_BATCHED_AT_6Hz5;
5558 break;
5559
5560 default:
5561 *val = LSM6DSO32X_XL_NOT_BATCHED;
5562 break;
5563 }
5564
5565 return ret;
5566 }
5567
5568 /**
5569 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5570 * for gyroscope data.[set]
5571 *
5572 * @param ctx read / write interface definitions
5573 * @param val change the values of bdr_gy in reg FIFO_CTRL3
5574 * @retval interface status (MANDATORY: return 0 -> no Error).
5575 *
5576 */
lsm6dso32x_fifo_gy_batch_set(stmdev_ctx_t * ctx,lsm6dso32x_bdr_gy_t val)5577 int32_t lsm6dso32x_fifo_gy_batch_set(stmdev_ctx_t *ctx,
5578 lsm6dso32x_bdr_gy_t val)
5579 {
5580 lsm6dso32x_fifo_ctrl3_t reg;
5581 int32_t ret;
5582
5583 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL3, (uint8_t *)®, 1);
5584
5585 if (ret == 0)
5586 {
5587 reg.bdr_gy = (uint8_t)val;
5588 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL3,
5589 (uint8_t *)®, 1);
5590 }
5591
5592 return ret;
5593 }
5594
5595 /**
5596 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5597 * for gyroscope data.[get]
5598 *
5599 * @param ctx read / write interface definitions
5600 * @param val Get the values of bdr_gy in reg FIFO_CTRL3
5601 * @retval interface status (MANDATORY: return 0 -> no Error).
5602 *
5603 */
lsm6dso32x_fifo_gy_batch_get(stmdev_ctx_t * ctx,lsm6dso32x_bdr_gy_t * val)5604 int32_t lsm6dso32x_fifo_gy_batch_get(stmdev_ctx_t *ctx,
5605 lsm6dso32x_bdr_gy_t *val)
5606 {
5607 lsm6dso32x_fifo_ctrl3_t reg;
5608 int32_t ret;
5609
5610 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL3, (uint8_t *)®, 1);
5611
5612 switch (reg.bdr_gy)
5613 {
5614 case LSM6DSO32X_GY_NOT_BATCHED:
5615 *val = LSM6DSO32X_GY_NOT_BATCHED;
5616 break;
5617
5618 case LSM6DSO32X_GY_BATCHED_AT_12Hz5:
5619 *val = LSM6DSO32X_GY_BATCHED_AT_12Hz5;
5620 break;
5621
5622 case LSM6DSO32X_GY_BATCHED_AT_26Hz:
5623 *val = LSM6DSO32X_GY_BATCHED_AT_26Hz;
5624 break;
5625
5626 case LSM6DSO32X_GY_BATCHED_AT_52Hz:
5627 *val = LSM6DSO32X_GY_BATCHED_AT_52Hz;
5628 break;
5629
5630 case LSM6DSO32X_GY_BATCHED_AT_104Hz:
5631 *val = LSM6DSO32X_GY_BATCHED_AT_104Hz;
5632 break;
5633
5634 case LSM6DSO32X_GY_BATCHED_AT_208Hz:
5635 *val = LSM6DSO32X_GY_BATCHED_AT_208Hz;
5636 break;
5637
5638 case LSM6DSO32X_GY_BATCHED_AT_417Hz:
5639 *val = LSM6DSO32X_GY_BATCHED_AT_417Hz;
5640 break;
5641
5642 case LSM6DSO32X_GY_BATCHED_AT_833Hz:
5643 *val = LSM6DSO32X_GY_BATCHED_AT_833Hz;
5644 break;
5645
5646 case LSM6DSO32X_GY_BATCHED_AT_1667Hz:
5647 *val = LSM6DSO32X_GY_BATCHED_AT_1667Hz;
5648 break;
5649
5650 case LSM6DSO32X_GY_BATCHED_AT_3333Hz:
5651 *val = LSM6DSO32X_GY_BATCHED_AT_3333Hz;
5652 break;
5653
5654 case LSM6DSO32X_GY_BATCHED_AT_6667Hz:
5655 *val = LSM6DSO32X_GY_BATCHED_AT_6667Hz;
5656 break;
5657
5658 case LSM6DSO32X_GY_BATCHED_AT_6Hz5:
5659 *val = LSM6DSO32X_GY_BATCHED_AT_6Hz5;
5660 break;
5661
5662 default:
5663 *val = LSM6DSO32X_GY_NOT_BATCHED;
5664 break;
5665 }
5666
5667 return ret;
5668 }
5669
5670 /**
5671 * @brief FIFO mode selection.[set]
5672 *
5673 * @param ctx read / write interface definitions
5674 * @param val change the values of fifo_mode in reg FIFO_CTRL4
5675 * @retval interface status (MANDATORY: return 0 -> no Error).
5676 *
5677 */
lsm6dso32x_fifo_mode_set(stmdev_ctx_t * ctx,lsm6dso32x_fifo_mode_t val)5678 int32_t lsm6dso32x_fifo_mode_set(stmdev_ctx_t *ctx,
5679 lsm6dso32x_fifo_mode_t val)
5680 {
5681 lsm6dso32x_fifo_ctrl4_t reg;
5682 int32_t ret;
5683
5684 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1);
5685
5686 if (ret == 0)
5687 {
5688 reg.fifo_mode = (uint8_t)val;
5689 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL4,
5690 (uint8_t *)®, 1);
5691 }
5692
5693 return ret;
5694 }
5695
5696 /**
5697 * @brief FIFO mode selection.[get]
5698 *
5699 * @param ctx read / write interface definitions
5700 * @param val Get the values of fifo_mode in reg FIFO_CTRL4
5701 * @retval interface status (MANDATORY: return 0 -> no Error).
5702 *
5703 */
lsm6dso32x_fifo_mode_get(stmdev_ctx_t * ctx,lsm6dso32x_fifo_mode_t * val)5704 int32_t lsm6dso32x_fifo_mode_get(stmdev_ctx_t *ctx,
5705 lsm6dso32x_fifo_mode_t *val)
5706 {
5707 lsm6dso32x_fifo_ctrl4_t reg;
5708 int32_t ret;
5709
5710 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1);
5711
5712 switch (reg.fifo_mode)
5713 {
5714 case LSM6DSO32X_BYPASS_MODE:
5715 *val = LSM6DSO32X_BYPASS_MODE;
5716 break;
5717
5718 case LSM6DSO32X_FIFO_MODE:
5719 *val = LSM6DSO32X_FIFO_MODE;
5720 break;
5721
5722 case LSM6DSO32X_STREAM_TO_FIFO_MODE:
5723 *val = LSM6DSO32X_STREAM_TO_FIFO_MODE;
5724 break;
5725
5726 case LSM6DSO32X_BYPASS_TO_STREAM_MODE:
5727 *val = LSM6DSO32X_BYPASS_TO_STREAM_MODE;
5728 break;
5729
5730 case LSM6DSO32X_STREAM_MODE:
5731 *val = LSM6DSO32X_STREAM_MODE;
5732 break;
5733
5734 case LSM6DSO32X_BYPASS_TO_FIFO_MODE:
5735 *val = LSM6DSO32X_BYPASS_TO_FIFO_MODE;
5736 break;
5737
5738 default:
5739 *val = LSM6DSO32X_BYPASS_MODE;
5740 break;
5741 }
5742
5743 return ret;
5744 }
5745
5746 /**
5747 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5748 * for temperature data.[set]
5749 *
5750 * @param ctx read / write interface definitions
5751 * @param val change the values of odr_t_batch in reg FIFO_CTRL4
5752 * @retval interface status (MANDATORY: return 0 -> no Error).
5753 *
5754 */
lsm6dso32x_fifo_temp_batch_set(stmdev_ctx_t * ctx,lsm6dso32x_odr_t_batch_t val)5755 int32_t lsm6dso32x_fifo_temp_batch_set(stmdev_ctx_t *ctx,
5756 lsm6dso32x_odr_t_batch_t val)
5757 {
5758 lsm6dso32x_fifo_ctrl4_t reg;
5759 int32_t ret;
5760
5761 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1);
5762
5763 if (ret == 0)
5764 {
5765 reg.odr_t_batch = (uint8_t)val;
5766 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL4,
5767 (uint8_t *)®, 1);
5768 }
5769
5770 return ret;
5771 }
5772
5773 /**
5774 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5775 * for temperature data.[get]
5776 *
5777 * @param ctx read / write interface definitions
5778 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4
5779 * @retval interface status (MANDATORY: return 0 -> no Error).
5780 *
5781 */
lsm6dso32x_fifo_temp_batch_get(stmdev_ctx_t * ctx,lsm6dso32x_odr_t_batch_t * val)5782 int32_t lsm6dso32x_fifo_temp_batch_get(stmdev_ctx_t *ctx,
5783 lsm6dso32x_odr_t_batch_t *val)
5784 {
5785 lsm6dso32x_fifo_ctrl4_t reg;
5786 int32_t ret;
5787
5788 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1);
5789
5790 switch (reg.odr_t_batch)
5791 {
5792 case LSM6DSO32X_TEMP_NOT_BATCHED:
5793 *val = LSM6DSO32X_TEMP_NOT_BATCHED;
5794 break;
5795
5796 case LSM6DSO32X_TEMP_BATCHED_AT_1Hz6:
5797 *val = LSM6DSO32X_TEMP_BATCHED_AT_1Hz6;
5798 break;
5799
5800 case LSM6DSO32X_TEMP_BATCHED_AT_12Hz5:
5801 *val = LSM6DSO32X_TEMP_BATCHED_AT_12Hz5;
5802 break;
5803
5804 case LSM6DSO32X_TEMP_BATCHED_AT_52Hz:
5805 *val = LSM6DSO32X_TEMP_BATCHED_AT_52Hz;
5806 break;
5807
5808 default:
5809 *val = LSM6DSO32X_TEMP_NOT_BATCHED;
5810 break;
5811 }
5812
5813 return ret;
5814 }
5815
5816 /**
5817 * @brief Selects decimation for timestamp batching in FIFO.
5818 * Writing rate will be the maximum rate between XL and
5819 * GYRO BDR divided by decimation decoder.[set]
5820 *
5821 * @param ctx read / write interface definitions
5822 * @param val change the values of odr_ts_batch in reg FIFO_CTRL4
5823 * @retval interface status (MANDATORY: return 0 -> no Error).
5824 *
5825 */
lsm6dso32x_fifo_timestamp_decimation_set(stmdev_ctx_t * ctx,lsm6dso32x_odr_ts_batch_t val)5826 int32_t lsm6dso32x_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
5827 lsm6dso32x_odr_ts_batch_t val)
5828 {
5829 lsm6dso32x_fifo_ctrl4_t reg;
5830 int32_t ret;
5831
5832 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1);
5833
5834 if (ret == 0)
5835 {
5836 reg.odr_ts_batch = (uint8_t)val;
5837 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FIFO_CTRL4,
5838 (uint8_t *)®, 1);
5839 }
5840
5841 return ret;
5842 }
5843
5844 /**
5845 * @brief Selects decimation for timestamp batching in FIFO.
5846 * Writing rate will be the maximum rate between XL and
5847 * GYRO BDR divided by decimation decoder.[get]
5848 *
5849 * @param ctx read / write interface definitions
5850 * @param val Get the values of odr_ts_batch in reg FIFO_CTRL4
5851 * @retval interface status (MANDATORY: return 0 -> no Error).
5852 *
5853 */
lsm6dso32x_fifo_timestamp_decimation_get(stmdev_ctx_t * ctx,lsm6dso32x_odr_ts_batch_t * val)5854 int32_t lsm6dso32x_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
5855 lsm6dso32x_odr_ts_batch_t *val)
5856 {
5857 lsm6dso32x_fifo_ctrl4_t reg;
5858 int32_t ret;
5859
5860 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_CTRL4, (uint8_t *)®, 1);
5861
5862 switch (reg.odr_ts_batch)
5863 {
5864 case LSM6DSO32X_NO_DECIMATION:
5865 *val = LSM6DSO32X_NO_DECIMATION;
5866 break;
5867
5868 case LSM6DSO32X_DEC_1:
5869 *val = LSM6DSO32X_DEC_1;
5870 break;
5871
5872 case LSM6DSO32X_DEC_8:
5873 *val = LSM6DSO32X_DEC_8;
5874 break;
5875
5876 case LSM6DSO32X_DEC_32:
5877 *val = LSM6DSO32X_DEC_32;
5878 break;
5879
5880 default:
5881 *val = LSM6DSO32X_NO_DECIMATION;
5882 break;
5883 }
5884
5885 return ret;
5886 }
5887
5888 /**
5889 * @brief Selects the trigger for the internal counter of batching events
5890 * between XL and gyro.[set]
5891 *
5892 * @param ctx read / write interface definitions
5893 * @param val change the values of trig_counter_bdr
5894 * in reg COUNTER_BDR_REG1
5895 * @retval interface status (MANDATORY: return 0 -> no Error).
5896 *
5897 */
lsm6dso32x_fifo_cnt_event_batch_set(stmdev_ctx_t * ctx,lsm6dso32x_trig_counter_bdr_t val)5898 int32_t lsm6dso32x_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
5899 lsm6dso32x_trig_counter_bdr_t val)
5900 {
5901 lsm6dso32x_counter_bdr_reg1_t reg;
5902 int32_t ret;
5903
5904 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
5905 (uint8_t *)®, 1);
5906
5907 if (ret == 0)
5908 {
5909 reg.trig_counter_bdr = (uint8_t)val;
5910 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
5911 (uint8_t *)®, 1);
5912 }
5913
5914 return ret;
5915 }
5916
5917 /**
5918 * @brief Selects the trigger for the internal counter of batching events
5919 * between XL and gyro.[get]
5920 *
5921 * @param ctx read / write interface definitions
5922 * @param val Get the values of trig_counter_bdr
5923 * in reg COUNTER_BDR_REG1
5924 * @retval interface status (MANDATORY: return 0 -> no Error).
5925 *
5926 */
lsm6dso32x_fifo_cnt_event_batch_get(stmdev_ctx_t * ctx,lsm6dso32x_trig_counter_bdr_t * val)5927 int32_t lsm6dso32x_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
5928 lsm6dso32x_trig_counter_bdr_t *val)
5929 {
5930 lsm6dso32x_counter_bdr_reg1_t reg;
5931 int32_t ret;
5932
5933 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
5934 (uint8_t *)®, 1);
5935
5936 switch (reg.trig_counter_bdr)
5937 {
5938 case LSM6DSO32X_XL_BATCH_EVENT:
5939 *val = LSM6DSO32X_XL_BATCH_EVENT;
5940 break;
5941
5942 case LSM6DSO32X_GYRO_BATCH_EVENT:
5943 *val = LSM6DSO32X_GYRO_BATCH_EVENT;
5944 break;
5945
5946 default:
5947 *val = LSM6DSO32X_XL_BATCH_EVENT;
5948 break;
5949 }
5950
5951 return ret;
5952 }
5953
5954 /**
5955 * @brief Resets the internal counter of batching vents for a single sensor.
5956 * This bit is automatically reset to zero if it was set to ‘1’.[set]
5957 *
5958 * @param ctx read / write interface definitions
5959 * @param val change the values of rst_counter_bdr in
5960 * reg COUNTER_BDR_REG1
5961 * @retval interface status (MANDATORY: return 0 -> no Error).
5962 *
5963 */
lsm6dso32x_rst_batch_counter_set(stmdev_ctx_t * ctx,uint8_t val)5964 int32_t lsm6dso32x_rst_batch_counter_set(stmdev_ctx_t *ctx,
5965 uint8_t val)
5966 {
5967 lsm6dso32x_counter_bdr_reg1_t reg;
5968 int32_t ret;
5969
5970 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
5971 (uint8_t *)®, 1);
5972
5973 if (ret == 0)
5974 {
5975 reg.rst_counter_bdr = val;
5976 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
5977 (uint8_t *)®, 1);
5978 }
5979
5980 return ret;
5981 }
5982
5983 /**
5984 * @brief Resets the internal counter of batching events for a single sensor.
5985 * This bit is automatically reset to zero if it was set to ‘1’.[get]
5986 *
5987 * @param ctx read / write interface definitions
5988 * @param val change the values of rst_counter_bdr in
5989 * reg COUNTER_BDR_REG1
5990 * @retval interface status (MANDATORY: return 0 -> no Error).
5991 *
5992 */
lsm6dso32x_rst_batch_counter_get(stmdev_ctx_t * ctx,uint8_t * val)5993 int32_t lsm6dso32x_rst_batch_counter_get(stmdev_ctx_t *ctx,
5994 uint8_t *val)
5995 {
5996 lsm6dso32x_counter_bdr_reg1_t reg;
5997 int32_t ret;
5998
5999 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
6000 (uint8_t *)®, 1);
6001 *val = reg.rst_counter_bdr;
6002
6003 return ret;
6004 }
6005
6006 /**
6007 * @brief Batch data rate counter.[set]
6008 *
6009 * @param ctx read / write interface definitions
6010 * @param val change the values of cnt_bdr_th in
6011 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
6012 * @retval interface status (MANDATORY: return 0 -> no Error).
6013 *
6014 */
lsm6dso32x_batch_counter_threshold_set(stmdev_ctx_t * ctx,uint16_t val)6015 int32_t lsm6dso32x_batch_counter_threshold_set(stmdev_ctx_t *ctx,
6016 uint16_t val)
6017 {
6018 lsm6dso32x_counter_bdr_reg1_t counter_bdr_reg1;
6019 lsm6dso32x_counter_bdr_reg2_t counter_bdr_reg2;
6020 int32_t ret;
6021
6022 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
6023 (uint8_t *)&counter_bdr_reg1, 1);
6024
6025 if (ret == 0)
6026 {
6027 counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val;
6028 counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8;
6029 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
6030 (uint8_t *)&counter_bdr_reg1, 1);
6031 }
6032
6033 if (ret == 0)
6034 {
6035 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG2,
6036 (uint8_t *)&counter_bdr_reg2, 1);
6037 }
6038
6039 return ret;
6040 }
6041
6042 /**
6043 * @brief Batch data rate counter.[get]
6044 *
6045 * @param ctx read / write interface definitions
6046 * @param val change the values of cnt_bdr_th in
6047 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
6048 * @retval interface status (MANDATORY: return 0 -> no Error).
6049 *
6050 */
lsm6dso32x_batch_counter_threshold_get(stmdev_ctx_t * ctx,uint16_t * val)6051 int32_t lsm6dso32x_batch_counter_threshold_get(stmdev_ctx_t *ctx,
6052 uint16_t *val)
6053 {
6054 lsm6dso32x_counter_bdr_reg1_t counter_bdr_reg1;
6055 lsm6dso32x_counter_bdr_reg2_t counter_bdr_reg2;
6056 int32_t ret;
6057
6058 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG1,
6059 (uint8_t *)&counter_bdr_reg1, 1);
6060
6061 if (ret == 0)
6062 {
6063 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_COUNTER_BDR_REG2,
6064 (uint8_t *)&counter_bdr_reg2, 1);
6065 *val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8)
6066 + (uint16_t)counter_bdr_reg2.cnt_bdr_th;
6067 }
6068
6069 return ret;
6070 }
6071
6072 /**
6073 * @brief Number of unread sensor data(TAG + 6 bytes) stored in FIFO.[get]
6074 *
6075 * @param ctx read / write interface definitions
6076 * @param val change the values of diff_fifo in reg FIFO_STATUS1
6077 * @retval interface status (MANDATORY: return 0 -> no Error).
6078 *
6079 */
lsm6dso32x_fifo_data_level_get(stmdev_ctx_t * ctx,uint16_t * val)6080 int32_t lsm6dso32x_fifo_data_level_get(stmdev_ctx_t *ctx,
6081 uint16_t *val)
6082 {
6083 lsm6dso32x_fifo_status1_t fifo_status1;
6084 lsm6dso32x_fifo_status2_t fifo_status2;
6085 int32_t ret;
6086
6087 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_STATUS1,
6088 (uint8_t *)&fifo_status1, 1);
6089
6090 if (ret == 0)
6091 {
6092 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_STATUS2,
6093 (uint8_t *)&fifo_status2, 1);
6094 *val = ((uint16_t)fifo_status2.diff_fifo << 8) +
6095 (uint16_t)fifo_status1.diff_fifo;
6096 }
6097
6098 return ret;
6099 }
6100
6101 /**
6102 * @brief FIFO status.[get]
6103 *
6104 * @param ctx read / write interface definitions
6105 * @param val registers FIFO_STATUS2
6106 * @retval interface status (MANDATORY: return 0 -> no Error).
6107 *
6108 */
lsm6dso32x_fifo_status_get(stmdev_ctx_t * ctx,lsm6dso32x_fifo_status2_t * val)6109 int32_t lsm6dso32x_fifo_status_get(stmdev_ctx_t *ctx,
6110 lsm6dso32x_fifo_status2_t *val)
6111 {
6112 int32_t ret;
6113
6114 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_STATUS2,
6115 (uint8_t *) val, 1);
6116
6117 return ret;
6118 }
6119
6120 /**
6121 * @brief Smart FIFO full status.[get]
6122 *
6123 * @param ctx read / write interface definitions
6124 * @param val change the values of fifo_full_ia in reg FIFO_STATUS2
6125 * @retval interface status (MANDATORY: return 0 -> no Error).
6126 *
6127 */
lsm6dso32x_fifo_full_flag_get(stmdev_ctx_t * ctx,uint8_t * val)6128 int32_t lsm6dso32x_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
6129 {
6130 lsm6dso32x_fifo_status2_t reg;
6131 int32_t ret;
6132
6133 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_STATUS2,
6134 (uint8_t *)®, 1);
6135 *val = reg.fifo_full_ia;
6136
6137 return ret;
6138 }
6139
6140 /**
6141 * @brief FIFO overrun status.[get]
6142 *
6143 * @param ctx read / write interface definitions
6144 * @param val change the values of fifo_over_run_latched in
6145 * reg FIFO_STATUS2
6146 * @retval interface status (MANDATORY: return 0 -> no Error).
6147 *
6148 */
lsm6dso32x_fifo_ovr_flag_get(stmdev_ctx_t * ctx,uint8_t * val)6149 int32_t lsm6dso32x_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
6150 {
6151 lsm6dso32x_fifo_status2_t reg;
6152 int32_t ret;
6153
6154 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_STATUS2,
6155 (uint8_t *)®, 1);
6156 *val = reg.fifo_ovr_ia;
6157
6158 return ret;
6159 }
6160
6161 /**
6162 * @brief FIFO watermark status.[get]
6163 *
6164 * @param ctx read / write interface definitions
6165 * @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2
6166 * @retval interface status (MANDATORY: return 0 -> no Error).
6167 *
6168 */
lsm6dso32x_fifo_wtm_flag_get(stmdev_ctx_t * ctx,uint8_t * val)6169 int32_t lsm6dso32x_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
6170 {
6171 lsm6dso32x_fifo_status2_t reg;
6172 int32_t ret;
6173
6174 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_STATUS2,
6175 (uint8_t *)®, 1);
6176 *val = reg.fifo_wtm_ia;
6177
6178 return ret;
6179 }
6180
6181 /**
6182 * @brief Identifies the sensor in FIFO_DATA_OUT.[get]
6183 *
6184 * @param ctx read / write interface definitions
6185 * @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
6186 * @retval interface status (MANDATORY: return 0 -> no Error).
6187 *
6188 */
lsm6dso32x_fifo_sensor_tag_get(stmdev_ctx_t * ctx,lsm6dso32x_fifo_tag_t * val)6189 int32_t lsm6dso32x_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
6190 lsm6dso32x_fifo_tag_t *val)
6191 {
6192 lsm6dso32x_fifo_data_out_tag_t reg;
6193 int32_t ret;
6194
6195 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FIFO_DATA_OUT_TAG,
6196 (uint8_t *)®, 1);
6197
6198 switch (reg.tag_sensor)
6199 {
6200 case LSM6DSO32X_GYRO_NC_TAG:
6201 *val = LSM6DSO32X_GYRO_NC_TAG;
6202 break;
6203
6204 case LSM6DSO32X_XL_NC_TAG:
6205 *val = LSM6DSO32X_XL_NC_TAG;
6206 break;
6207
6208 case LSM6DSO32X_TEMPERATURE_TAG:
6209 *val = LSM6DSO32X_TEMPERATURE_TAG;
6210 break;
6211
6212 case LSM6DSO32X_TIMESTAMP_TAG:
6213 *val = LSM6DSO32X_TIMESTAMP_TAG;
6214 break;
6215
6216 case LSM6DSO32X_CFG_CHANGE_TAG:
6217 *val = LSM6DSO32X_CFG_CHANGE_TAG;
6218 break;
6219
6220 case LSM6DSO32X_XL_NC_T_2_TAG:
6221 *val = LSM6DSO32X_XL_NC_T_2_TAG;
6222 break;
6223
6224 case LSM6DSO32X_XL_NC_T_1_TAG:
6225 *val = LSM6DSO32X_XL_NC_T_1_TAG;
6226 break;
6227
6228 case LSM6DSO32X_XL_2XC_TAG:
6229 *val = LSM6DSO32X_XL_2XC_TAG;
6230 break;
6231
6232 case LSM6DSO32X_XL_3XC_TAG:
6233 *val = LSM6DSO32X_XL_3XC_TAG;
6234 break;
6235
6236 case LSM6DSO32X_GYRO_NC_T_2_TAG:
6237 *val = LSM6DSO32X_GYRO_NC_T_2_TAG;
6238 break;
6239
6240 case LSM6DSO32X_GYRO_NC_T_1_TAG:
6241 *val = LSM6DSO32X_GYRO_NC_T_1_TAG;
6242 break;
6243
6244 case LSM6DSO32X_GYRO_2XC_TAG:
6245 *val = LSM6DSO32X_GYRO_2XC_TAG;
6246 break;
6247
6248 case LSM6DSO32X_GYRO_3XC_TAG:
6249 *val = LSM6DSO32X_GYRO_3XC_TAG;
6250 break;
6251
6252 case LSM6DSO32X_SENSORHUB_SLAVE0_TAG:
6253 *val = LSM6DSO32X_SENSORHUB_SLAVE0_TAG;
6254 break;
6255
6256 case LSM6DSO32X_SENSORHUB_SLAVE1_TAG:
6257 *val = LSM6DSO32X_SENSORHUB_SLAVE1_TAG;
6258 break;
6259
6260 case LSM6DSO32X_SENSORHUB_SLAVE2_TAG:
6261 *val = LSM6DSO32X_SENSORHUB_SLAVE2_TAG;
6262 break;
6263
6264 case LSM6DSO32X_SENSORHUB_SLAVE3_TAG:
6265 *val = LSM6DSO32X_SENSORHUB_SLAVE3_TAG;
6266 break;
6267
6268 case LSM6DSO32X_STEP_CPUNTER_TAG:
6269 *val = LSM6DSO32X_STEP_CPUNTER_TAG;
6270 break;
6271
6272 case LSM6DSO32X_GAME_ROTATION_TAG:
6273 *val = LSM6DSO32X_GAME_ROTATION_TAG;
6274 break;
6275
6276 case LSM6DSO32X_GEOMAG_ROTATION_TAG:
6277 *val = LSM6DSO32X_GEOMAG_ROTATION_TAG;
6278 break;
6279
6280 case LSM6DSO32X_ROTATION_TAG:
6281 *val = LSM6DSO32X_ROTATION_TAG;
6282 break;
6283
6284 case LSM6DSO32X_SENSORHUB_NACK_TAG:
6285 *val = LSM6DSO32X_SENSORHUB_NACK_TAG;
6286 break;
6287
6288 default:
6289 *val = LSM6DSO32X_GYRO_NC_TAG;
6290 break;
6291 }
6292
6293 return ret;
6294 }
6295
6296 /**
6297 * @brief : Enable FIFO batching of pedometer embedded
6298 * function values.[set]
6299 *
6300 * @param ctx read / write interface definitions
6301 * @param val change the values of gbias_fifo_en in
6302 * reg LSM6DSO32X_EMB_FUNC_FIFO_CFG
6303 * @retval interface status (MANDATORY: return 0 -> no Error).
6304 *
6305 */
lsm6dso32x_fifo_pedo_batch_set(stmdev_ctx_t * ctx,uint8_t val)6306 int32_t lsm6dso32x_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
6307 {
6308 lsm6dso32x_emb_func_fifo_cfg_t reg;
6309 int32_t ret;
6310
6311 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
6312
6313 if (ret == 0)
6314 {
6315 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_FIFO_CFG,
6316 (uint8_t *)®, 1);
6317 }
6318
6319 if (ret == 0)
6320 {
6321 reg.pedo_fifo_en = val;
6322 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_FIFO_CFG,
6323 (uint8_t *)®, 1);
6324 }
6325
6326 if (ret == 0)
6327 {
6328 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6329 }
6330
6331 return ret;
6332 }
6333
6334 /**
6335 * @brief Enable FIFO batching of pedometer embedded function values.[get]
6336 *
6337 * @param ctx read / write interface definitions
6338 * @param val change the values of pedo_fifo_en in
6339 * reg LSM6DSO32X_EMB_FUNC_FIFO_CFG
6340 * @retval interface status (MANDATORY: return 0 -> no Error).
6341 *
6342 */
lsm6dso32x_fifo_pedo_batch_get(stmdev_ctx_t * ctx,uint8_t * val)6343 int32_t lsm6dso32x_fifo_pedo_batch_get(stmdev_ctx_t *ctx,
6344 uint8_t *val)
6345 {
6346 lsm6dso32x_emb_func_fifo_cfg_t reg;
6347 int32_t ret;
6348
6349 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
6350
6351 if (ret == 0)
6352 {
6353 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_FIFO_CFG,
6354 (uint8_t *)®, 1);
6355 }
6356
6357 if (ret == 0)
6358 {
6359 *val = reg.pedo_fifo_en;
6360 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6361 }
6362
6363 return ret;
6364 }
6365
6366 /**
6367 * @brief Enable FIFO batching data of first slave.[set]
6368 *
6369 * @param ctx read / write interface definitions
6370 * @param val change the values of batch_ext_sens_0_en in
6371 * reg SLV0_CONFIG
6372 * @retval interface status (MANDATORY: return 0 -> no Error).
6373 *
6374 */
lsm6dso32x_sh_batch_slave_0_set(stmdev_ctx_t * ctx,uint8_t val)6375 int32_t lsm6dso32x_sh_batch_slave_0_set(stmdev_ctx_t *ctx,
6376 uint8_t val)
6377 {
6378 lsm6dso32x_slv0_config_t reg;
6379 int32_t ret;
6380
6381 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
6382
6383 if (ret == 0)
6384 {
6385 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
6386 (uint8_t *)®, 1);
6387 }
6388
6389 if (ret == 0)
6390 {
6391 reg.batch_ext_sens_0_en = val;
6392 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
6393 (uint8_t *)®, 1);
6394 }
6395
6396 if (ret == 0)
6397 {
6398 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6399 }
6400
6401 return ret;
6402 }
6403
6404 /**
6405 * @brief Enable FIFO batching data of first slave.[get]
6406 *
6407 * @param ctx read / write interface definitions
6408 * @param val change the values of batch_ext_sens_0_en in
6409 * reg SLV0_CONFIG
6410 * @retval interface status (MANDATORY: return 0 -> no Error).
6411 *
6412 */
lsm6dso32x_sh_batch_slave_0_get(stmdev_ctx_t * ctx,uint8_t * val)6413 int32_t lsm6dso32x_sh_batch_slave_0_get(stmdev_ctx_t *ctx,
6414 uint8_t *val)
6415 {
6416 lsm6dso32x_slv0_config_t reg;
6417 int32_t ret;
6418
6419 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
6420
6421 if (ret == 0)
6422 {
6423 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
6424 (uint8_t *)®, 1);
6425 }
6426
6427 if (ret == 0)
6428 {
6429 *val = reg.batch_ext_sens_0_en;
6430 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6431 }
6432
6433 return ret;
6434 }
6435
6436 /**
6437 * @brief Enable FIFO batching data of second slave.[set]
6438 *
6439 * @param ctx read / write interface definitions
6440 * @param val change the values of batch_ext_sens_1_en in
6441 * reg SLV1_CONFIG
6442 * @retval interface status (MANDATORY: return 0 -> no Error).
6443 *
6444 */
lsm6dso32x_sh_batch_slave_1_set(stmdev_ctx_t * ctx,uint8_t val)6445 int32_t lsm6dso32x_sh_batch_slave_1_set(stmdev_ctx_t *ctx,
6446 uint8_t val)
6447 {
6448 lsm6dso32x_slv1_config_t reg;
6449 int32_t ret;
6450
6451 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
6452
6453 if (ret == 0)
6454 {
6455 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV1_CONFIG,
6456 (uint8_t *)®, 1);
6457 }
6458
6459 if (ret == 0)
6460 {
6461 reg.batch_ext_sens_1_en = val;
6462 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV1_CONFIG,
6463 (uint8_t *)®, 1);
6464 }
6465
6466 if (ret == 0)
6467 {
6468 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6469 }
6470
6471 return ret;
6472 }
6473
6474 /**
6475 * @brief Enable FIFO batching data of second slave.[get]
6476 *
6477 * @param ctx read / write interface definitions
6478 * @param val change the values of batch_ext_sens_1_en in
6479 * reg SLV1_CONFIG
6480 * @retval interface status (MANDATORY: return 0 -> no Error).
6481 *
6482 */
lsm6dso32x_sh_batch_slave_1_get(stmdev_ctx_t * ctx,uint8_t * val)6483 int32_t lsm6dso32x_sh_batch_slave_1_get(stmdev_ctx_t *ctx,
6484 uint8_t *val)
6485 {
6486 lsm6dso32x_slv1_config_t reg;
6487 int32_t ret;
6488
6489 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
6490
6491 if (ret == 0)
6492 {
6493 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV1_CONFIG,
6494 (uint8_t *)®, 1);
6495 *val = reg.batch_ext_sens_1_en;
6496 }
6497
6498 if (ret == 0)
6499 {
6500 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6501 }
6502
6503 return ret;
6504 }
6505
6506 /**
6507 * @brief Enable FIFO batching data of third slave.[set]
6508 *
6509 * @param ctx read / write interface definitions
6510 * @param val change the values of batch_ext_sens_2_en in
6511 * reg SLV2_CONFIG
6512 * @retval interface status (MANDATORY: return 0 -> no Error).
6513 *
6514 */
lsm6dso32x_sh_batch_slave_2_set(stmdev_ctx_t * ctx,uint8_t val)6515 int32_t lsm6dso32x_sh_batch_slave_2_set(stmdev_ctx_t *ctx,
6516 uint8_t val)
6517 {
6518 lsm6dso32x_slv2_config_t reg;
6519 int32_t ret;
6520
6521 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
6522
6523 if (ret == 0)
6524 {
6525 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV2_CONFIG,
6526 (uint8_t *)®, 1);
6527 }
6528
6529 if (ret == 0)
6530 {
6531 reg.batch_ext_sens_2_en = val;
6532 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV2_CONFIG,
6533 (uint8_t *)®, 1);
6534 }
6535
6536 if (ret == 0)
6537 {
6538 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6539 }
6540
6541 return ret;
6542 }
6543
6544 /**
6545 * @brief Enable FIFO batching data of third slave.[get]
6546 *
6547 * @param ctx read / write interface definitions
6548 * @param val change the values of batch_ext_sens_2_en in
6549 * reg SLV2_CONFIG
6550 * @retval interface status (MANDATORY: return 0 -> no Error).
6551 *
6552 */
lsm6dso32x_sh_batch_slave_2_get(stmdev_ctx_t * ctx,uint8_t * val)6553 int32_t lsm6dso32x_sh_batch_slave_2_get(stmdev_ctx_t *ctx,
6554 uint8_t *val)
6555 {
6556 lsm6dso32x_slv2_config_t reg;
6557 int32_t ret;
6558
6559 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
6560
6561 if (ret == 0)
6562 {
6563 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV2_CONFIG,
6564 (uint8_t *)®, 1);
6565 }
6566
6567 if (ret == 0)
6568 {
6569 *val = reg.batch_ext_sens_2_en;
6570 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6571 }
6572
6573 return ret;
6574 }
6575
6576 /**
6577 * @brief Enable FIFO batching data of fourth slave.[set]
6578 *
6579 * @param ctx read / write interface definitions
6580 * @param val change the values of batch_ext_sens_3_en
6581 * in reg SLV3_CONFIG
6582 * @retval interface status (MANDATORY: return 0 -> no Error).
6583 *
6584 */
lsm6dso32x_sh_batch_slave_3_set(stmdev_ctx_t * ctx,uint8_t val)6585 int32_t lsm6dso32x_sh_batch_slave_3_set(stmdev_ctx_t *ctx,
6586 uint8_t val)
6587 {
6588 lsm6dso32x_slv3_config_t reg;
6589 int32_t ret;
6590
6591 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
6592
6593 if (ret == 0)
6594 {
6595 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV3_CONFIG,
6596 (uint8_t *)®, 1);
6597 }
6598
6599 if (ret == 0)
6600 {
6601 reg.batch_ext_sens_3_en = val;
6602 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV3_CONFIG,
6603 (uint8_t *)®, 1);
6604 }
6605
6606 if (ret == 0)
6607 {
6608 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6609 }
6610
6611 return ret;
6612 }
6613
6614 /**
6615 * @brief Enable FIFO batching data of fourth slave.[get]
6616 *
6617 * @param ctx read / write interface definitions
6618 * @param val change the values of batch_ext_sens_3_en in
6619 * reg SLV3_CONFIG
6620 * @retval interface status (MANDATORY: return 0 -> no Error).
6621 *
6622 */
lsm6dso32x_sh_batch_slave_3_get(stmdev_ctx_t * ctx,uint8_t * val)6623 int32_t lsm6dso32x_sh_batch_slave_3_get(stmdev_ctx_t *ctx,
6624 uint8_t *val)
6625 {
6626 lsm6dso32x_slv3_config_t reg;
6627 int32_t ret;
6628
6629 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
6630
6631 if (ret == 0)
6632 {
6633 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV3_CONFIG,
6634 (uint8_t *)®, 1);
6635 }
6636
6637 if (ret == 0)
6638 {
6639 *val = reg.batch_ext_sens_3_en;
6640 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
6641 }
6642
6643 return ret;
6644 }
6645
6646 /**
6647 * @}
6648 *
6649 */
6650
6651 /**
6652 * @defgroup LSM6DSO32X_DEN_functionality
6653 * @brief This section groups all the functions concerning
6654 * DEN functionality.
6655 * @{
6656 *
6657 */
6658
6659 /**
6660 * @brief DEN functionality marking mode.[set]
6661 *
6662 * @param ctx read / write interface definitions
6663 * @param val change the values of den_mode in reg CTRL6_C
6664 * @retval interface status (MANDATORY: return 0 -> no Error).
6665 *
6666 */
lsm6dso32x_den_mode_set(stmdev_ctx_t * ctx,lsm6dso32x_den_mode_t val)6667 int32_t lsm6dso32x_den_mode_set(stmdev_ctx_t *ctx,
6668 lsm6dso32x_den_mode_t val)
6669 {
6670 lsm6dso32x_ctrl6_c_t reg;
6671 int32_t ret;
6672
6673 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
6674
6675 if (ret == 0)
6676 {
6677 reg.den_mode = (uint8_t)val;
6678 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
6679 }
6680
6681 return ret;
6682 }
6683
6684 /**
6685 * @brief DEN functionality marking mode.[get]
6686 *
6687 * @param ctx read / write interface definitions
6688 * @param val Get the values of den_mode in reg CTRL6_C
6689 * @retval interface status (MANDATORY: return 0 -> no Error).
6690 *
6691 */
lsm6dso32x_den_mode_get(stmdev_ctx_t * ctx,lsm6dso32x_den_mode_t * val)6692 int32_t lsm6dso32x_den_mode_get(stmdev_ctx_t *ctx,
6693 lsm6dso32x_den_mode_t *val)
6694 {
6695 lsm6dso32x_ctrl6_c_t reg;
6696 int32_t ret;
6697
6698 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL6_C, (uint8_t *)®, 1);
6699
6700 switch (reg.den_mode)
6701 {
6702 case LSM6DSO32X_DEN_DISABLE:
6703 *val = LSM6DSO32X_DEN_DISABLE;
6704 break;
6705
6706 case LSM6DSO32X_LEVEL_FIFO:
6707 *val = LSM6DSO32X_LEVEL_FIFO;
6708 break;
6709
6710 case LSM6DSO32X_LEVEL_LETCHED:
6711 *val = LSM6DSO32X_LEVEL_LETCHED;
6712 break;
6713
6714 case LSM6DSO32X_LEVEL_TRIGGER:
6715 *val = LSM6DSO32X_LEVEL_TRIGGER;
6716 break;
6717
6718 case LSM6DSO32X_EDGE_TRIGGER:
6719 *val = LSM6DSO32X_EDGE_TRIGGER;
6720 break;
6721
6722 default:
6723 *val = LSM6DSO32X_DEN_DISABLE;
6724 break;
6725 }
6726
6727 return ret;
6728 }
6729
6730 /**
6731 * @brief DEN active level configuration.[set]
6732 *
6733 * @param ctx read / write interface definitions
6734 * @param val change the values of den_lh in reg CTRL9_XL
6735 * @retval interface status (MANDATORY: return 0 -> no Error).
6736 *
6737 */
lsm6dso32x_den_polarity_set(stmdev_ctx_t * ctx,lsm6dso32x_den_lh_t val)6738 int32_t lsm6dso32x_den_polarity_set(stmdev_ctx_t *ctx,
6739 lsm6dso32x_den_lh_t val)
6740 {
6741 lsm6dso32x_ctrl9_xl_t reg;
6742 int32_t ret;
6743
6744 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6745
6746 if (ret == 0)
6747 {
6748 reg.den_lh = (uint8_t)val;
6749 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6750 }
6751
6752 return ret;
6753 }
6754
6755 /**
6756 * @brief DEN active level configuration.[get]
6757 *
6758 * @param ctx read / write interface definitions
6759 * @param val Get the values of den_lh in reg CTRL9_XL
6760 * @retval interface status (MANDATORY: return 0 -> no Error).
6761 *
6762 */
lsm6dso32x_den_polarity_get(stmdev_ctx_t * ctx,lsm6dso32x_den_lh_t * val)6763 int32_t lsm6dso32x_den_polarity_get(stmdev_ctx_t *ctx,
6764 lsm6dso32x_den_lh_t *val)
6765 {
6766 lsm6dso32x_ctrl9_xl_t reg;
6767 int32_t ret;
6768
6769 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6770
6771 switch (reg.den_lh)
6772 {
6773 case LSM6DSO32X_DEN_ACT_LOW:
6774 *val = LSM6DSO32X_DEN_ACT_LOW;
6775 break;
6776
6777 case LSM6DSO32X_DEN_ACT_HIGH:
6778 *val = LSM6DSO32X_DEN_ACT_HIGH;
6779 break;
6780
6781 default:
6782 *val = LSM6DSO32X_DEN_ACT_LOW;
6783 break;
6784 }
6785
6786 return ret;
6787 }
6788
6789 /**
6790 * @brief DEN enable.[set]
6791 *
6792 * @param ctx read / write interface definitions
6793 * @param val change the values of den_xl_g in reg CTRL9_XL
6794 * @retval interface status (MANDATORY: return 0 -> no Error).
6795 *
6796 */
lsm6dso32x_den_enable_set(stmdev_ctx_t * ctx,lsm6dso32x_den_xl_g_t val)6797 int32_t lsm6dso32x_den_enable_set(stmdev_ctx_t *ctx,
6798 lsm6dso32x_den_xl_g_t val)
6799 {
6800 lsm6dso32x_ctrl9_xl_t reg;
6801 int32_t ret;
6802
6803 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6804
6805 if (ret == 0)
6806 {
6807 reg.den_xl_g = (uint8_t)val;
6808 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6809 }
6810
6811 return ret;
6812 }
6813
6814 /**
6815 * @brief DEN enable.[get]
6816 *
6817 * @param ctx read / write interface definitions
6818 * @param val Get the values of den_xl_g in reg CTRL9_XL
6819 * @retval interface status (MANDATORY: return 0 -> no Error).
6820 *
6821 */
lsm6dso32x_den_enable_get(stmdev_ctx_t * ctx,lsm6dso32x_den_xl_g_t * val)6822 int32_t lsm6dso32x_den_enable_get(stmdev_ctx_t *ctx,
6823 lsm6dso32x_den_xl_g_t *val)
6824 {
6825 lsm6dso32x_ctrl9_xl_t reg;
6826 int32_t ret;
6827
6828 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6829
6830 switch (reg.den_xl_g)
6831 {
6832 case LSM6DSO32X_STAMP_IN_GY_DATA:
6833 *val = LSM6DSO32X_STAMP_IN_GY_DATA;
6834 break;
6835
6836 case LSM6DSO32X_STAMP_IN_XL_DATA:
6837 *val = LSM6DSO32X_STAMP_IN_XL_DATA;
6838 break;
6839
6840 case LSM6DSO32X_STAMP_IN_GY_XL_DATA:
6841 *val = LSM6DSO32X_STAMP_IN_GY_XL_DATA;
6842 break;
6843
6844 default:
6845 *val = LSM6DSO32X_STAMP_IN_GY_DATA;
6846 break;
6847 }
6848
6849 return ret;
6850 }
6851
6852 /**
6853 * @brief DEN value stored in LSB of X-axis.[set]
6854 *
6855 * @param ctx read / write interface definitions
6856 * @param val change the values of den_z in reg CTRL9_XL
6857 * @retval interface status (MANDATORY: return 0 -> no Error).
6858 *
6859 */
lsm6dso32x_den_mark_axis_x_set(stmdev_ctx_t * ctx,uint8_t val)6860 int32_t lsm6dso32x_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
6861 {
6862 lsm6dso32x_ctrl9_xl_t reg;
6863 int32_t ret;
6864
6865 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6866
6867 if (ret == 0)
6868 {
6869 reg.den_z = val;
6870 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6871 }
6872
6873 return ret;
6874 }
6875
6876 /**
6877 * @brief DEN value stored in LSB of X-axis.[get]
6878 *
6879 * @param ctx read / write interface definitions
6880 * @param val change the values of den_z in reg CTRL9_XL
6881 * @retval interface status (MANDATORY: return 0 -> no Error).
6882 *
6883 */
lsm6dso32x_den_mark_axis_x_get(stmdev_ctx_t * ctx,uint8_t * val)6884 int32_t lsm6dso32x_den_mark_axis_x_get(stmdev_ctx_t *ctx,
6885 uint8_t *val)
6886 {
6887 lsm6dso32x_ctrl9_xl_t reg;
6888 int32_t ret;
6889
6890 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6891 *val = reg.den_z;
6892
6893 return ret;
6894 }
6895
6896 /**
6897 * @brief DEN value stored in LSB of Y-axis.[set]
6898 *
6899 * @param ctx read / write interface definitions
6900 * @param val change the values of den_y in reg CTRL9_XL
6901 * @retval interface status (MANDATORY: return 0 -> no Error).
6902 *
6903 */
lsm6dso32x_den_mark_axis_y_set(stmdev_ctx_t * ctx,uint8_t val)6904 int32_t lsm6dso32x_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
6905 {
6906 lsm6dso32x_ctrl9_xl_t reg;
6907 int32_t ret;
6908
6909 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6910
6911 if (ret == 0)
6912 {
6913 reg.den_y = val;
6914 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6915 }
6916
6917 return ret;
6918 }
6919
6920 /**
6921 * @brief DEN value stored in LSB of Y-axis.[get]
6922 *
6923 * @param ctx read / write interface definitions
6924 * @param val change the values of den_y in reg CTRL9_XL
6925 * @retval interface status (MANDATORY: return 0 -> no Error).
6926 *
6927 */
lsm6dso32x_den_mark_axis_y_get(stmdev_ctx_t * ctx,uint8_t * val)6928 int32_t lsm6dso32x_den_mark_axis_y_get(stmdev_ctx_t *ctx,
6929 uint8_t *val)
6930 {
6931 lsm6dso32x_ctrl9_xl_t reg;
6932 int32_t ret;
6933
6934 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6935 *val = reg.den_y;
6936
6937 return ret;
6938 }
6939
6940 /**
6941 * @brief DEN value stored in LSB of Z-axis.[set]
6942 *
6943 * @param ctx read / write interface definitions
6944 * @param val change the values of den_x in reg CTRL9_XL
6945 * @retval interface status (MANDATORY: return 0 -> no Error).
6946 *
6947 */
lsm6dso32x_den_mark_axis_z_set(stmdev_ctx_t * ctx,uint8_t val)6948 int32_t lsm6dso32x_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
6949 {
6950 lsm6dso32x_ctrl9_xl_t reg;
6951 int32_t ret;
6952
6953 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6954
6955 if (ret == 0)
6956 {
6957 reg.den_x = val;
6958 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6959 }
6960
6961 return ret;
6962 }
6963
6964 /**
6965 * @brief DEN value stored in LSB of Z-axis.[get]
6966 *
6967 * @param ctx read / write interface definitions
6968 * @param val change the values of den_x in reg CTRL9_XL
6969 * @retval interface status (MANDATORY: return 0 -> no Error).
6970 *
6971 */
lsm6dso32x_den_mark_axis_z_get(stmdev_ctx_t * ctx,uint8_t * val)6972 int32_t lsm6dso32x_den_mark_axis_z_get(stmdev_ctx_t *ctx,
6973 uint8_t *val)
6974 {
6975 lsm6dso32x_ctrl9_xl_t reg;
6976 int32_t ret;
6977
6978 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL, (uint8_t *)®, 1);
6979 *val = reg.den_x;
6980
6981 return ret;
6982 }
6983
6984 /**
6985 * @}
6986 *
6987 */
6988
6989 /**
6990 * @defgroup LSM6DSO32X_Pedometer
6991 * @brief This section groups all the functions that manage pedometer.
6992 * @{
6993 *
6994 */
6995
6996 /**
6997 * @brief Enable pedometer algorithm.[set]
6998 *
6999 * @param ctx read / write interface definitions
7000 * @param val turn on and configure pedometer
7001 * @retval interface status (MANDATORY: return 0 -> no Error).
7002 *
7003 */
lsm6dso32x_pedo_sens_set(stmdev_ctx_t * ctx,lsm6dso32x_pedo_md_t val)7004 int32_t lsm6dso32x_pedo_sens_set(stmdev_ctx_t *ctx,
7005 lsm6dso32x_pedo_md_t val)
7006 {
7007 lsm6dso32x_pedo_cmd_reg_t pedo_cmd_reg;
7008 int32_t ret;
7009
7010 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_CMD_REG,
7011 (uint8_t *)&pedo_cmd_reg);
7012
7013 if (ret == 0)
7014 {
7015 pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U) >> 4;
7016 pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U) >> 5;
7017 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_PEDO_CMD_REG,
7018 (uint8_t *)&pedo_cmd_reg);
7019 }
7020
7021 return ret;
7022 }
7023
7024 /**
7025 * @brief Enable pedometer algorithm.[get]
7026 *
7027 * @param ctx read / write interface definitions
7028 * @param val turn on and configure pedometer
7029 * @retval interface status (MANDATORY: return 0 -> no Error).
7030 *
7031 */
lsm6dso32x_pedo_sens_get(stmdev_ctx_t * ctx,lsm6dso32x_pedo_md_t * val)7032 int32_t lsm6dso32x_pedo_sens_get(stmdev_ctx_t *ctx,
7033 lsm6dso32x_pedo_md_t *val)
7034 {
7035 lsm6dso32x_pedo_cmd_reg_t pedo_cmd_reg;
7036 int32_t ret;
7037
7038 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_CMD_REG,
7039 (uint8_t *)&pedo_cmd_reg);
7040
7041 switch ((pedo_cmd_reg.ad_det_en << 5) | (pedo_cmd_reg.fp_rejection_en
7042 << 4))
7043 {
7044 case LSM6DSO32X_PEDO_BASE_MODE:
7045 *val = LSM6DSO32X_PEDO_BASE_MODE;
7046 break;
7047
7048 case LSM6DSO32X_FALSE_STEP_REJ:
7049 *val = LSM6DSO32X_FALSE_STEP_REJ;
7050 break;
7051
7052 case LSM6DSO32X_FALSE_STEP_REJ_ADV_MODE:
7053 *val = LSM6DSO32X_FALSE_STEP_REJ_ADV_MODE;
7054 break;
7055
7056 default:
7057 *val = LSM6DSO32X_PEDO_BASE_MODE;
7058 break;
7059 }
7060
7061 return ret;
7062 }
7063
7064 /**
7065 * @brief Interrupt status bit for step detection.[get]
7066 *
7067 * @param ctx read / write interface definitions
7068 * @param val change the values of is_step_det in reg EMB_FUNC_STATUS
7069 * @retval interface status (MANDATORY: return 0 -> no Error).
7070 *
7071 */
lsm6dso32x_pedo_step_detect_get(stmdev_ctx_t * ctx,uint8_t * val)7072 int32_t lsm6dso32x_pedo_step_detect_get(stmdev_ctx_t *ctx,
7073 uint8_t *val)
7074 {
7075 lsm6dso32x_emb_func_status_t reg;
7076 int32_t ret;
7077
7078 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
7079
7080 if (ret == 0)
7081 {
7082 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_STATUS,
7083 (uint8_t *)®, 1);
7084 }
7085
7086 if (ret == 0)
7087 {
7088 *val = reg.is_step_det;
7089 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
7090 }
7091
7092 return ret;
7093 }
7094
7095 /**
7096 * @brief Pedometer debounce configuration register (r/w).[set]
7097 *
7098 * @param ctx read / write interface definitions
7099 * @param buff buffer that contains data to write
7100 * @retval interface status (MANDATORY: return 0 -> no Error).
7101 *
7102 */
lsm6dso32x_pedo_debounce_steps_set(stmdev_ctx_t * ctx,uint8_t * buff)7103 int32_t lsm6dso32x_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
7104 uint8_t *buff)
7105 {
7106 int32_t ret;
7107
7108 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_PEDO_DEB_STEPS_CONF,
7109 buff);
7110
7111 return ret;
7112 }
7113
7114 /**
7115 * @brief Pedometer debounce configuration register (r/w).[get]
7116 *
7117 * @param ctx read / write interface definitions
7118 * @param buff buffer that stores data read
7119 * @retval interface status (MANDATORY: return 0 -> no Error).
7120 *
7121 */
lsm6dso32x_pedo_debounce_steps_get(stmdev_ctx_t * ctx,uint8_t * buff)7122 int32_t lsm6dso32x_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
7123 uint8_t *buff)
7124 {
7125 int32_t ret;
7126
7127 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_DEB_STEPS_CONF,
7128 buff);
7129
7130 return ret;
7131 }
7132
7133 /**
7134 * @brief Time period register for step detection on delta time (r/w).[set]
7135 *
7136 * @param ctx read / write interface definitions
7137 * @param buff buffer that contains data to write
7138 * @retval interface status (MANDATORY: return 0 -> no Error).
7139 *
7140 */
lsm6dso32x_pedo_steps_period_set(stmdev_ctx_t * ctx,uint16_t val)7141 int32_t lsm6dso32x_pedo_steps_period_set(stmdev_ctx_t *ctx,
7142 uint16_t val)
7143 {
7144 uint8_t buff[2];
7145 int32_t ret;
7146
7147 buff[1] = (uint8_t)(val / 256U);
7148 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7149 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_PEDO_SC_DELTAT_L,
7150 &buff[0]);
7151
7152 if (ret == 0)
7153 {
7154 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_PEDO_SC_DELTAT_H,
7155 &buff[1]);
7156 }
7157
7158 return ret;
7159 }
7160
7161 /**
7162 * @brief Time period register for step detection on delta time (r/w).[get]
7163 *
7164 * @param ctx read / write interface definitions
7165 * @param buff buffer that stores data read
7166 * @retval interface status (MANDATORY: return 0 -> no Error).
7167 *
7168 */
lsm6dso32x_pedo_steps_period_get(stmdev_ctx_t * ctx,uint16_t * val)7169 int32_t lsm6dso32x_pedo_steps_period_get(stmdev_ctx_t *ctx,
7170 uint16_t *val)
7171 {
7172 uint8_t buff[2];
7173 int32_t ret;
7174
7175 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_SC_DELTAT_L,
7176 &buff[0]);
7177
7178 if (ret == 0)
7179 {
7180 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_SC_DELTAT_H,
7181 &buff[1]);
7182 *val = buff[1];
7183 *val = (*val * 256U) + buff[0];
7184 }
7185
7186 return ret;
7187 }
7188
7189 /**
7190 * @brief Set when user wants to generate interrupt on count overflow
7191 * event/every step.[set]
7192 *
7193 * @param ctx read / write interface definitions
7194 * @param val change the values of carry_count_en in reg PEDO_CMD_REG
7195 * @retval interface status (MANDATORY: return 0 -> no Error).
7196 *
7197 */
lsm6dso32x_pedo_int_mode_set(stmdev_ctx_t * ctx,lsm6dso32x_carry_count_en_t val)7198 int32_t lsm6dso32x_pedo_int_mode_set(stmdev_ctx_t *ctx,
7199 lsm6dso32x_carry_count_en_t val)
7200 {
7201 lsm6dso32x_pedo_cmd_reg_t reg;
7202 int32_t ret;
7203
7204 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_CMD_REG,
7205 (uint8_t *)®);
7206
7207 if (ret == 0)
7208 {
7209 reg.carry_count_en = (uint8_t)val;
7210 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_PEDO_CMD_REG,
7211 (uint8_t *)®);
7212 }
7213
7214 return ret;
7215 }
7216
7217 /**
7218 * @brief Set when user wants to generate interrupt on count overflow
7219 * event/every step.[get]
7220 *
7221 * @param ctx read / write interface definitions
7222 * @param val Get the values of carry_count_en in reg PEDO_CMD_REG
7223 * @retval interface status (MANDATORY: return 0 -> no Error).
7224 *
7225 */
lsm6dso32x_pedo_int_mode_get(stmdev_ctx_t * ctx,lsm6dso32x_carry_count_en_t * val)7226 int32_t lsm6dso32x_pedo_int_mode_get(stmdev_ctx_t *ctx,
7227 lsm6dso32x_carry_count_en_t *val)
7228 {
7229 lsm6dso32x_pedo_cmd_reg_t reg;
7230 int32_t ret;
7231
7232 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_PEDO_CMD_REG,
7233 (uint8_t *)®);
7234
7235 switch (reg.carry_count_en)
7236 {
7237 case LSM6DSO32X_EVERY_STEP:
7238 *val = LSM6DSO32X_EVERY_STEP;
7239 break;
7240
7241 case LSM6DSO32X_COUNT_OVERFLOW:
7242 *val = LSM6DSO32X_COUNT_OVERFLOW;
7243 break;
7244
7245 default:
7246 *val = LSM6DSO32X_EVERY_STEP;
7247 break;
7248 }
7249
7250 return ret;
7251 }
7252
7253 /**
7254 * @}
7255 *
7256 */
7257
7258 /**
7259 * @defgroup LSM6DSO32X_significant_motion
7260 * @brief This section groups all the functions that manage the
7261 * significant motion detection.
7262 * @{
7263 *
7264 */
7265
7266 /**
7267 * @brief Interrupt status bit for significant motion detection.[get]
7268 *
7269 * @param ctx read / write interface definitions
7270 * @param val change the values of is_sigmot in reg EMB_FUNC_STATUS
7271 * @retval interface status (MANDATORY: return 0 -> no Error).
7272 *
7273 */
lsm6dso32x_motion_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)7274 int32_t lsm6dso32x_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
7275 uint8_t *val)
7276 {
7277 lsm6dso32x_emb_func_status_t reg;
7278 int32_t ret;
7279
7280 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
7281
7282 if (ret == 0)
7283 {
7284 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_STATUS,
7285 (uint8_t *)®, 1);
7286 }
7287
7288 if (ret == 0)
7289 {
7290 *val = reg.is_sigmot;
7291 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
7292 }
7293
7294 return ret;
7295 }
7296
7297 /**
7298 * @}
7299 *
7300 */
7301
7302 /**
7303 * @defgroup LSM6DSO32X_tilt_detection
7304 * @brief This section groups all the functions that manage the tilt
7305 * event detection.
7306 * @{
7307 *
7308 */
7309
7310 /**
7311 * @brief Interrupt status bit for tilt detection.[get]
7312 *
7313 * @param ctx read / write interface definitions
7314 * @param val change the values of is_tilt in reg EMB_FUNC_STATUS
7315 * @retval interface status (MANDATORY: return 0 -> no Error).
7316 *
7317 */
lsm6dso32x_tilt_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)7318 int32_t lsm6dso32x_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
7319 uint8_t *val)
7320 {
7321 lsm6dso32x_emb_func_status_t reg;
7322 int32_t ret;
7323
7324 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
7325
7326 if (ret == 0)
7327 {
7328 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_STATUS,
7329 (uint8_t *)®, 1);
7330 }
7331
7332 if (ret == 0)
7333 {
7334 *val = reg.is_tilt;
7335 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
7336 }
7337
7338 return ret;
7339 }
7340
7341 /**
7342 * @}
7343 *
7344 */
7345
7346 /**
7347 * @defgroup LSM6DSO32X_ magnetometer_sensor
7348 * @brief This section groups all the functions that manage additional
7349 * magnetometer sensor.
7350 * @{
7351 *
7352 */
7353
7354 /**
7355 * @brief External magnetometer sensitivity value register for
7356 * Sensor hub.[set]
7357 *
7358 * @param ctx read / write interface definitions
7359 * @param buff buffer that contains data to write
7360 * @retval interface status (MANDATORY: return 0 -> no Error).
7361 *
7362 */
lsm6dso32x_sh_mag_sensitivity_set(stmdev_ctx_t * ctx,uint16_t val)7363 int32_t lsm6dso32x_sh_mag_sensitivity_set(stmdev_ctx_t *ctx,
7364 uint16_t val)
7365 {
7366 uint8_t buff[2];
7367 int32_t ret;
7368
7369 buff[1] = (uint8_t)(val / 256U);
7370 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7371 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SENSITIVITY_L,
7372 &buff[0]);
7373
7374 if (ret == 0)
7375 {
7376 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SENSITIVITY_H,
7377 &buff[1]);
7378 }
7379
7380 return ret;
7381 }
7382
7383 /**
7384 * @brief External magnetometer sensitivity value register for
7385 * Sensor hub.[get]
7386 *
7387 * @param ctx read / write interface definitions
7388 * @param buff buffer that stores data read
7389 * @retval interface status (MANDATORY: return 0 -> no Error).
7390 *
7391 */
lsm6dso32x_sh_mag_sensitivity_get(stmdev_ctx_t * ctx,uint16_t * val)7392 int32_t lsm6dso32x_sh_mag_sensitivity_get(stmdev_ctx_t *ctx,
7393 uint16_t *val)
7394 {
7395 uint8_t buff[2];
7396 int32_t ret;
7397
7398 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SENSITIVITY_L,
7399 &buff[0]);
7400
7401 if (ret == 0)
7402 {
7403 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SENSITIVITY_H,
7404 &buff[1]);
7405 *val = buff[1];
7406 *val = (*val * 256U) + buff[0];
7407 }
7408
7409 return ret;
7410 }
7411
7412 /**
7413 * @brief External magnetometer sensitivity value register for
7414 * Machine Learning Core.[set]
7415 *
7416 * @param ctx read / write interface definitions
7417 * @param buff buffer that contains data to write
7418 * @retval interface status (MANDATORY: return 0 -> no Error).
7419 *
7420 */
lsm6dso32x_mlc_mag_sensitivity_set(stmdev_ctx_t * ctx,uint16_t val)7421 int32_t lsm6dso32x_mlc_mag_sensitivity_set(stmdev_ctx_t *ctx,
7422 uint16_t val)
7423 {
7424 uint8_t buff[2];
7425 int32_t ret;
7426
7427 buff[1] = (uint8_t)(val / 256U);
7428 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7429 ret = lsm6dso32x_ln_pg_write_byte(ctx,
7430 LSM6DSO32X_MLC_MAG_SENSITIVITY_L,
7431 &buff[0]);
7432
7433 if (ret == 0)
7434 {
7435 ret = lsm6dso32x_ln_pg_write_byte(ctx,
7436 LSM6DSO32X_MLC_MAG_SENSITIVITY_H,
7437 &buff[1]);
7438 }
7439
7440 return ret;
7441 }
7442
7443 /**
7444 * @brief External magnetometer sensitivity value register for
7445 * Machine Learning Core.[get]
7446 *
7447 * @param ctx read / write interface definitions
7448 * @param buff buffer that stores data read
7449 * @retval interface status (MANDATORY: return 0 -> no Error).
7450 *
7451 */
lsm6dso32x_mlc_mag_sensitivity_get(stmdev_ctx_t * ctx,uint16_t * val)7452 int32_t lsm6dso32x_mlc_mag_sensitivity_get(stmdev_ctx_t *ctx,
7453 uint16_t *val)
7454 {
7455 uint8_t buff[2];
7456 int32_t ret;
7457
7458 ret = lsm6dso32x_ln_pg_read_byte(ctx,
7459 LSM6DSO32X_MLC_MAG_SENSITIVITY_L,
7460 &buff[0]);
7461
7462 if (ret == 0)
7463 {
7464 ret = lsm6dso32x_ln_pg_read_byte(ctx,
7465 LSM6DSO32X_MLC_MAG_SENSITIVITY_H,
7466 &buff[1]);
7467 *val = buff[1];
7468 *val = (*val * 256U) + buff[0];
7469 }
7470
7471 return ret;
7472 }
7473
7474
7475 /**
7476 * @brief Offset for hard-iron compensation register (r/w).[set]
7477 *
7478 * @param ctx read / write interface definitions
7479 * @param buff buffer that contains data to write
7480 * @retval interface status (MANDATORY: return 0 -> no Error).
7481 *
7482 */
lsm6dso32x_mag_offset_set(stmdev_ctx_t * ctx,int16_t * val)7483 int32_t lsm6dso32x_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
7484 {
7485 uint8_t buff[6];
7486 int32_t ret;
7487
7488 uint8_t i;
7489 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
7490 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
7491 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
7492 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
7493 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
7494 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
7495 i = 0x00U;
7496 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_OFFX_L,
7497 &buff[i]);
7498
7499 if (ret == 0)
7500 {
7501 i++;
7502 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_OFFX_H,
7503 &buff[i]);
7504 }
7505
7506 if (ret == 0)
7507 {
7508 i++;
7509 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_OFFY_L,
7510 &buff[i]);
7511 }
7512
7513 if (ret == 0)
7514 {
7515 i++;
7516 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_OFFY_H,
7517 &buff[i]);
7518 }
7519
7520 if (ret == 0)
7521 {
7522 i++;
7523 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_OFFZ_L,
7524 &buff[i]);
7525 }
7526
7527 if (ret == 0)
7528 {
7529 i++;
7530 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_OFFZ_H,
7531 &buff[i]);
7532 }
7533
7534 return ret;
7535 }
7536
7537 /**
7538 * @brief Offset for hard-iron compensation register (r/w).[get]
7539 *
7540 * @param ctx read / write interface definitions
7541 * @param buff buffer that stores data read
7542 * @retval interface status (MANDATORY: return 0 -> no Error).
7543 *
7544 */
lsm6dso32x_mag_offset_get(stmdev_ctx_t * ctx,int16_t * val)7545 int32_t lsm6dso32x_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
7546 {
7547 uint8_t buff[6];
7548 int32_t ret;
7549
7550 uint8_t i;
7551 i = 0x00U;
7552 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_OFFX_L,
7553 &buff[i]);
7554
7555 if (ret == 0)
7556 {
7557 i++;
7558 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_OFFX_H,
7559 &buff[i]);
7560 }
7561
7562 if (ret == 0)
7563 {
7564 i++;
7565 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_OFFY_L,
7566 &buff[i]);
7567 }
7568
7569 if (ret == 0)
7570 {
7571 i++;
7572 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_OFFY_H,
7573 &buff[i]);
7574 }
7575
7576 if (ret == 0)
7577 {
7578 i++;
7579 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_OFFZ_L,
7580 &buff[i]);
7581 }
7582
7583 if (ret == 0)
7584 {
7585 i++;
7586 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_OFFZ_H,
7587 &buff[i]);
7588 }
7589
7590 val[0] = (int16_t)buff[1];
7591 val[0] = (val[0] * 256) + (int16_t)buff[0];
7592 val[1] = (int16_t)buff[3];
7593 val[1] = (val[1] * 256) + (int16_t)buff[2];
7594 val[2] = (int16_t)buff[5];
7595 val[2] = (val[2] * 256) + (int16_t)buff[4];
7596
7597 return ret;
7598 }
7599
7600 /**
7601 * @brief Soft-iron (3x3 symmetric) matrix correction
7602 * register (r/w). The value is expressed as
7603 * half-precision floating-point format:
7604 * SEEEEEFFFFFFFFFF
7605 * S: 1 sign bit;
7606 * E: 5 exponent bits;
7607 * F: 10 fraction bits).[set]
7608 *
7609 * @param ctx read / write interface definitions
7610 * @param buff buffer that contains data to write
7611 * @retval interface status (MANDATORY: return 0 -> no Error).
7612 *
7613 */
lsm6dso32x_mag_soft_iron_set(stmdev_ctx_t * ctx,uint16_t * val)7614 int32_t lsm6dso32x_mag_soft_iron_set(stmdev_ctx_t *ctx, uint16_t *val)
7615 {
7616 uint8_t buff[12];
7617 uint8_t index;
7618 int32_t ret;
7619
7620 buff[1] = (uint8_t)(val[0] / 256U);
7621 buff[0] = (uint8_t)(val[0] - (buff[1] * 256U));
7622 buff[3] = (uint8_t)(val[1] / 256U);
7623 buff[2] = (uint8_t)(val[1] - (buff[3] * 256U));
7624 buff[5] = (uint8_t)(val[2] / 256U);
7625 buff[4] = (uint8_t)(val[2] - (buff[5] * 256U));
7626 buff[7] = (uint8_t)(val[3] / 256U);
7627 buff[6] = (uint8_t)(val[3] - (buff[1] * 256U));
7628 buff[9] = (uint8_t)(val[4] / 256U);
7629 buff[8] = (uint8_t)(val[4] - (buff[3] * 256U));
7630 buff[11] = (uint8_t)(val[5] / 256U);
7631 buff[10] = (uint8_t)(val[5] - (buff[5] * 256U));
7632 index = 0x00U;
7633 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_XX_L,
7634 &buff[index]);
7635
7636 if (ret == 0)
7637 {
7638 index++;
7639 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_XX_H,
7640 &buff[index]);
7641 }
7642
7643 if (ret == 0)
7644 {
7645 index++;
7646 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_XY_L,
7647 &buff[index]);
7648 }
7649
7650 if (ret == 0)
7651 {
7652 index++;
7653 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_XY_H,
7654 &buff[index]);
7655 }
7656
7657 if (ret == 0)
7658 {
7659 index++;
7660 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_XZ_L,
7661 &buff[index]);
7662 }
7663
7664 if (ret == 0)
7665 {
7666 index++;
7667 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_XZ_H,
7668 &buff[index]);
7669 }
7670
7671 if (ret == 0)
7672 {
7673 index++;
7674 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_YY_L,
7675 &buff[index]);
7676 }
7677
7678 if (ret == 0)
7679 {
7680 index++;
7681 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_YY_H,
7682 &buff[index]);
7683 }
7684
7685 if (ret == 0)
7686 {
7687 index++;
7688 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_YZ_L,
7689 &buff[index]);
7690 }
7691
7692 if (ret == 0)
7693 {
7694 index++;
7695 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_YZ_H,
7696 &buff[index]);
7697 }
7698
7699 if (ret == 0)
7700 {
7701 index++;
7702 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_ZZ_L,
7703 &buff[index]);
7704 }
7705
7706 if (ret == 0)
7707 {
7708 index++;
7709 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_SI_ZZ_H,
7710 &buff[index]);
7711 }
7712
7713 return ret;
7714 }
7715
7716 /**
7717 * @brief Soft-iron (3x3 symmetric) matrix
7718 * correction register (r/w).
7719 * The value is expressed as half-precision
7720 * floating-point format:
7721 * SEEEEEFFFFFFFFFF
7722 * S: 1 sign bit;
7723 * E: 5 exponent bits;
7724 * F: 10 fraction bits.[get]
7725 *
7726 * @param ctx read / write interface definitions
7727 * @param buff buffer that stores data read
7728 * @retval interface status (MANDATORY: return 0 -> no Error).
7729 *
7730 */
lsm6dso32x_mag_soft_iron_get(stmdev_ctx_t * ctx,uint16_t * val)7731 int32_t lsm6dso32x_mag_soft_iron_get(stmdev_ctx_t *ctx, uint16_t *val)
7732 {
7733 uint8_t buff[12];
7734 uint8_t index;
7735 int32_t ret;
7736
7737 index = 0x00U;
7738 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_XX_L,
7739 &buff[index]);
7740
7741 if (ret == 0)
7742 {
7743 index++;
7744 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_XX_H,
7745 &buff[index]);
7746 }
7747
7748 if (ret == 0)
7749 {
7750 index++;
7751 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_XY_L,
7752 &buff[index]);
7753 }
7754
7755 if (ret == 0)
7756 {
7757 index++;
7758 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_XY_H,
7759 &buff[index]);
7760 }
7761
7762 if (ret == 0)
7763 {
7764 index++;
7765 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_XZ_L,
7766 &buff[index]);
7767 }
7768
7769 if (ret == 0)
7770 {
7771 index++;
7772 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_XZ_H,
7773 &buff[index]);
7774 }
7775
7776 if (ret == 0)
7777 {
7778 index++;
7779 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_YY_L,
7780 &buff[index]);
7781 }
7782
7783 if (ret == 0)
7784 {
7785 index++;
7786 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_YY_H,
7787 &buff[index]);
7788 }
7789
7790 if (ret == 0)
7791 {
7792 index++;
7793 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_YZ_L,
7794 &buff[index]);
7795 }
7796
7797 if (ret == 0)
7798 {
7799 index++;
7800 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_YZ_H,
7801 &buff[index]);
7802 }
7803
7804 if (ret == 0)
7805 {
7806 index++;
7807 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_ZZ_L,
7808 &buff[index]);
7809 }
7810
7811 if (ret == 0)
7812 {
7813 index++;
7814 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_SI_ZZ_H,
7815 &buff[index]);
7816 }
7817
7818 val[0] = buff[1];
7819 val[0] = (val[0] * 256U) + buff[0];
7820 val[1] = buff[3];
7821 val[1] = (val[1] * 256U) + buff[2];
7822 val[2] = buff[5];
7823 val[2] = (val[2] * 256U) + buff[4];
7824 val[3] = buff[7];
7825 val[3] = (val[3] * 256U) + buff[6];
7826 val[4] = buff[9];
7827 val[4] = (val[4] * 256U) + buff[8];
7828 val[5] = buff[11];
7829 val[6] = (val[5] * 256U) + buff[10];
7830
7831 return ret;
7832 }
7833
7834 /**
7835 * @brief Magnetometer Z-axis coordinates
7836 * rotation (to be aligned to
7837 * accelerometer/gyroscope axes
7838 * orientation).[set]
7839 *
7840 * @param ctx read / write interface definitions
7841 * @param val change the values of mag_z_axis in reg MAG_CFG_A
7842 * @retval interface status (MANDATORY: return 0 -> no Error).
7843 *
7844 */
lsm6dso32x_mag_z_orient_set(stmdev_ctx_t * ctx,lsm6dso32x_mag_z_axis_t val)7845 int32_t lsm6dso32x_mag_z_orient_set(stmdev_ctx_t *ctx,
7846 lsm6dso32x_mag_z_axis_t val)
7847 {
7848 lsm6dso32x_mag_cfg_a_t reg;
7849 int32_t ret;
7850
7851 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_A,
7852 (uint8_t *)®);
7853
7854 if (ret == 0)
7855 {
7856 reg.mag_z_axis = (uint8_t) val;
7857 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_CFG_A,
7858 (uint8_t *)®);
7859 }
7860
7861 return ret;
7862 }
7863
7864 /**
7865 * @brief Magnetometer Z-axis coordinates
7866 * rotation (to be aligned to
7867 * accelerometer/gyroscope axes
7868 * orientation).[get]
7869 *
7870 * @param ctx read / write interface definitions
7871 * @param val Get the values of mag_z_axis in reg MAG_CFG_A
7872 * @retval interface status (MANDATORY: return 0 -> no Error).
7873 *
7874 */
lsm6dso32x_mag_z_orient_get(stmdev_ctx_t * ctx,lsm6dso32x_mag_z_axis_t * val)7875 int32_t lsm6dso32x_mag_z_orient_get(stmdev_ctx_t *ctx,
7876 lsm6dso32x_mag_z_axis_t *val)
7877 {
7878 lsm6dso32x_mag_cfg_a_t reg;
7879 int32_t ret;
7880
7881 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_A,
7882 (uint8_t *)®);
7883
7884 switch (reg.mag_z_axis)
7885 {
7886 case LSM6DSO32X_Z_EQ_Y:
7887 *val = LSM6DSO32X_Z_EQ_Y;
7888 break;
7889
7890 case LSM6DSO32X_Z_EQ_MIN_Y:
7891 *val = LSM6DSO32X_Z_EQ_MIN_Y;
7892 break;
7893
7894 case LSM6DSO32X_Z_EQ_X:
7895 *val = LSM6DSO32X_Z_EQ_X;
7896 break;
7897
7898 case LSM6DSO32X_Z_EQ_MIN_X:
7899 *val = LSM6DSO32X_Z_EQ_MIN_X;
7900 break;
7901
7902 case LSM6DSO32X_Z_EQ_MIN_Z:
7903 *val = LSM6DSO32X_Z_EQ_MIN_Z;
7904 break;
7905
7906 case LSM6DSO32X_Z_EQ_Z:
7907 *val = LSM6DSO32X_Z_EQ_Z;
7908 break;
7909
7910 default:
7911 *val = LSM6DSO32X_Z_EQ_Y;
7912 break;
7913 }
7914
7915 return ret;
7916 }
7917
7918 /**
7919 * @brief Magnetometer Y-axis coordinates
7920 * rotation (to be aligned to
7921 * accelerometer/gyroscope axes
7922 * orientation).[set]
7923 *
7924 * @param ctx read / write interface definitions
7925 * @param val change the values of mag_y_axis in reg MAG_CFG_A
7926 * @retval interface status (MANDATORY: return 0 -> no Error).
7927 *
7928 */
lsm6dso32x_mag_y_orient_set(stmdev_ctx_t * ctx,lsm6dso32x_mag_y_axis_t val)7929 int32_t lsm6dso32x_mag_y_orient_set(stmdev_ctx_t *ctx,
7930 lsm6dso32x_mag_y_axis_t val)
7931 {
7932 lsm6dso32x_mag_cfg_a_t reg;
7933 int32_t ret;
7934
7935 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_A,
7936 (uint8_t *)®);
7937
7938 if (ret == 0)
7939 {
7940 reg.mag_y_axis = (uint8_t)val;
7941 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_CFG_A,
7942 (uint8_t *) ®);
7943 }
7944
7945 return ret;
7946 }
7947
7948 /**
7949 * @brief Magnetometer Y-axis coordinates
7950 * rotation (to be aligned to
7951 * accelerometer/gyroscope axes
7952 * orientation).[get]
7953 *
7954 * @param ctx read / write interface definitions
7955 * @param val Get the values of mag_y_axis in reg MAG_CFG_A
7956 * @retval interface status (MANDATORY: return 0 -> no Error).
7957 *
7958 */
lsm6dso32x_mag_y_orient_get(stmdev_ctx_t * ctx,lsm6dso32x_mag_y_axis_t * val)7959 int32_t lsm6dso32x_mag_y_orient_get(stmdev_ctx_t *ctx,
7960 lsm6dso32x_mag_y_axis_t *val)
7961 {
7962 lsm6dso32x_mag_cfg_a_t reg;
7963 int32_t ret;
7964
7965 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_A,
7966 (uint8_t *)®);
7967
7968 switch (reg.mag_y_axis)
7969 {
7970 case LSM6DSO32X_Y_EQ_Y:
7971 *val = LSM6DSO32X_Y_EQ_Y;
7972 break;
7973
7974 case LSM6DSO32X_Y_EQ_MIN_Y:
7975 *val = LSM6DSO32X_Y_EQ_MIN_Y;
7976 break;
7977
7978 case LSM6DSO32X_Y_EQ_X:
7979 *val = LSM6DSO32X_Y_EQ_X;
7980 break;
7981
7982 case LSM6DSO32X_Y_EQ_MIN_X:
7983 *val = LSM6DSO32X_Y_EQ_MIN_X;
7984 break;
7985
7986 case LSM6DSO32X_Y_EQ_MIN_Z:
7987 *val = LSM6DSO32X_Y_EQ_MIN_Z;
7988 break;
7989
7990 case LSM6DSO32X_Y_EQ_Z:
7991 *val = LSM6DSO32X_Y_EQ_Z;
7992 break;
7993
7994 default:
7995 *val = LSM6DSO32X_Y_EQ_Y;
7996 break;
7997 }
7998
7999 return ret;
8000 }
8001
8002 /**
8003 * @brief Magnetometer X-axis coordinates
8004 * rotation (to be aligned to
8005 * accelerometer/gyroscope axes
8006 * orientation).[set]
8007 *
8008 * @param ctx read / write interface definitions
8009 * @param val change the values of mag_x_axis in reg MAG_CFG_B
8010 * @retval interface status (MANDATORY: return 0 -> no Error).
8011 *
8012 */
lsm6dso32x_mag_x_orient_set(stmdev_ctx_t * ctx,lsm6dso32x_mag_x_axis_t val)8013 int32_t lsm6dso32x_mag_x_orient_set(stmdev_ctx_t *ctx,
8014 lsm6dso32x_mag_x_axis_t val)
8015 {
8016 lsm6dso32x_mag_cfg_b_t reg;
8017 int32_t ret;
8018
8019 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_B,
8020 (uint8_t *)®);
8021
8022 if (ret == 0)
8023 {
8024 reg.mag_x_axis = (uint8_t)val;
8025 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_MAG_CFG_B,
8026 (uint8_t *)®);
8027 }
8028
8029 return ret;
8030 }
8031
8032 /**
8033 * @brief Magnetometer X-axis coordinates
8034 * rotation (to be aligned to
8035 * accelerometer/gyroscope axes
8036 * orientation).[get]
8037 *
8038 * @param ctx read / write interface definitions
8039 * @param val Get the values of mag_x_axis in reg MAG_CFG_B
8040 * @retval interface status (MANDATORY: return 0 -> no Error).
8041 *
8042 */
lsm6dso32x_mag_x_orient_get(stmdev_ctx_t * ctx,lsm6dso32x_mag_x_axis_t * val)8043 int32_t lsm6dso32x_mag_x_orient_get(stmdev_ctx_t *ctx,
8044 lsm6dso32x_mag_x_axis_t *val)
8045 {
8046 lsm6dso32x_mag_cfg_b_t reg;
8047 int32_t ret;
8048
8049 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_MAG_CFG_B,
8050 (uint8_t *)®);
8051
8052 switch (reg.mag_x_axis)
8053 {
8054 case LSM6DSO32X_X_EQ_Y:
8055 *val = LSM6DSO32X_X_EQ_Y;
8056 break;
8057
8058 case LSM6DSO32X_X_EQ_MIN_Y:
8059 *val = LSM6DSO32X_X_EQ_MIN_Y;
8060 break;
8061
8062 case LSM6DSO32X_X_EQ_X:
8063 *val = LSM6DSO32X_X_EQ_X;
8064 break;
8065
8066 case LSM6DSO32X_X_EQ_MIN_X:
8067 *val = LSM6DSO32X_X_EQ_MIN_X;
8068 break;
8069
8070 case LSM6DSO32X_X_EQ_MIN_Z:
8071 *val = LSM6DSO32X_X_EQ_MIN_Z;
8072 break;
8073
8074 case LSM6DSO32X_X_EQ_Z:
8075 *val = LSM6DSO32X_X_EQ_Z;
8076 break;
8077
8078 default:
8079 *val = LSM6DSO32X_X_EQ_Y;
8080 break;
8081 }
8082
8083 return ret;
8084 }
8085
8086 /**
8087 * @}
8088 *
8089 */
8090
8091 /**
8092 * @defgroup LSM6DSO32X_finite_state_machine
8093 * @brief This section groups all the functions that manage the
8094 * state_machine.
8095 * @{
8096 *
8097 */
8098
8099 /**
8100 * @brief Interrupt status bit for FSM long counter
8101 * timeout interrupt event.[get]
8102 *
8103 * @param ctx read / write interface definitions
8104 * @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS
8105 * @retval interface status (MANDATORY: return 0 -> no Error).
8106 *
8107 */
lsm6dso32x_long_cnt_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)8108 int32_t lsm6dso32x_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
8109 uint8_t *val)
8110 {
8111 lsm6dso32x_emb_func_status_t reg;
8112 int32_t ret;
8113
8114 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8115
8116 if (ret == 0)
8117 {
8118 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_STATUS,
8119 (uint8_t *)®, 1);
8120 }
8121
8122 if (ret == 0)
8123 {
8124 *val = reg.is_fsm_lc;
8125 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8126 }
8127
8128 return ret;
8129 }
8130
8131 /**
8132 * @brief Finite State Machine enable.[set]
8133 *
8134 * @param ctx read / write interface definitions
8135 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
8136 * @retval interface status (MANDATORY: return 0 -> no Error).
8137 *
8138 */
lsm6dso32x_fsm_enable_set(stmdev_ctx_t * ctx,lsm6dso32x_emb_fsm_enable_t * val)8139 int32_t lsm6dso32x_fsm_enable_set(stmdev_ctx_t *ctx,
8140 lsm6dso32x_emb_fsm_enable_t *val)
8141 {
8142 int32_t ret;
8143
8144 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8145
8146 if (ret == 0)
8147 {
8148 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_ENABLE_A,
8149 (uint8_t *)&val->fsm_enable_a, 1);
8150 }
8151
8152 if (ret == 0)
8153 {
8154 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_ENABLE_B,
8155 (uint8_t *)&val->fsm_enable_b, 1);
8156 }
8157
8158 if (ret == 0)
8159 {
8160 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8161 }
8162
8163 return ret;
8164 }
8165
8166 /**
8167 * @brief Finite State Machine enable.[get]
8168 *
8169 * @param ctx read / write interface definitions
8170 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
8171 * @retval interface status (MANDATORY: return 0 -> no Error).
8172 *
8173 */
lsm6dso32x_fsm_enable_get(stmdev_ctx_t * ctx,lsm6dso32x_emb_fsm_enable_t * val)8174 int32_t lsm6dso32x_fsm_enable_get(stmdev_ctx_t *ctx,
8175 lsm6dso32x_emb_fsm_enable_t *val)
8176 {
8177 int32_t ret;
8178
8179 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8180
8181 if (ret == 0)
8182 {
8183 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_ENABLE_A,
8184 (uint8_t *) val,
8185 2);
8186 }
8187
8188 if (ret == 0)
8189 {
8190 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8191 }
8192
8193 return ret;
8194 }
8195
8196 /**
8197 * @brief FSM long counter status register. Long counter value is an
8198 * unsigned integer value (16-bit format).[set]
8199 *
8200 * @param ctx read / write interface definitions
8201 * @param buff buffer that contains data to write
8202 * @retval interface status (MANDATORY: return 0 -> no Error).
8203 *
8204 */
lsm6dso32x_long_cnt_set(stmdev_ctx_t * ctx,uint16_t val)8205 int32_t lsm6dso32x_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
8206 {
8207 uint8_t buff[2];
8208 int32_t ret;
8209
8210 buff[1] = (uint8_t)(val / 256U);
8211 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8212 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8213
8214 if (ret == 0)
8215 {
8216 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_LONG_COUNTER_L, buff,
8217 2);
8218 }
8219
8220 if (ret == 0)
8221 {
8222 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8223 }
8224
8225 return ret;
8226 }
8227
8228 /**
8229 * @brief FSM long counter status register. Long counter value is an
8230 * unsigned integer value (16-bit format).[get]
8231 *
8232 * @param ctx read / write interface definitions
8233 * @param buff buffer that stores data read
8234 * @retval interface status (MANDATORY: return 0 -> no Error).
8235 *
8236 */
lsm6dso32x_long_cnt_get(stmdev_ctx_t * ctx,uint16_t * val)8237 int32_t lsm6dso32x_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
8238 {
8239 uint8_t buff[2];
8240 int32_t ret;
8241
8242 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8243
8244 if (ret == 0)
8245 {
8246 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_LONG_COUNTER_L, buff,
8247 2);
8248 *val = buff[1];
8249 *val = (*val * 256U) + buff[0];
8250 }
8251
8252 if (ret == 0)
8253 {
8254 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8255 }
8256
8257 return ret;
8258 }
8259
8260 /**
8261 * @brief Clear FSM long counter value.[set]
8262 *
8263 * @param ctx read / write interface definitions
8264 * @param val change the values of fsm_lc_clr in
8265 * reg FSM_LONG_COUNTER_CLEAR
8266 * @retval interface status (MANDATORY: return 0 -> no Error).
8267 *
8268 */
lsm6dso32x_long_clr_set(stmdev_ctx_t * ctx,lsm6dso32x_fsm_lc_clr_t val)8269 int32_t lsm6dso32x_long_clr_set(stmdev_ctx_t *ctx,
8270 lsm6dso32x_fsm_lc_clr_t val)
8271 {
8272 lsm6dso32x_fsm_long_counter_clear_t reg;
8273 int32_t ret;
8274
8275 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8276
8277 if (ret == 0)
8278 {
8279 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_LONG_COUNTER_CLEAR,
8280 (uint8_t *)®, 1);
8281 }
8282
8283 if (ret == 0)
8284 {
8285 reg. fsm_lc_clr = (uint8_t)val;
8286 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_LONG_COUNTER_CLEAR,
8287 (uint8_t *)®, 1);
8288 }
8289
8290 if (ret == 0)
8291 {
8292 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8293 }
8294
8295 return ret;
8296 }
8297
8298 /**
8299 * @brief Clear FSM long counter value.[get]
8300 *
8301 * @param ctx read / write interface definitions
8302 * @param val Get the values of fsm_lc_clr in
8303 * reg FSM_LONG_COUNTER_CLEAR
8304 * @retval interface status (MANDATORY: return 0 -> no Error).
8305 *
8306 */
lsm6dso32x_long_clr_get(stmdev_ctx_t * ctx,lsm6dso32x_fsm_lc_clr_t * val)8307 int32_t lsm6dso32x_long_clr_get(stmdev_ctx_t *ctx,
8308 lsm6dso32x_fsm_lc_clr_t *val)
8309 {
8310 lsm6dso32x_fsm_long_counter_clear_t reg;
8311 int32_t ret;
8312
8313 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8314
8315 if (ret == 0)
8316 {
8317 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_LONG_COUNTER_CLEAR,
8318 (uint8_t *)®, 1);
8319 }
8320
8321 if (ret == 0)
8322 {
8323 switch (reg.fsm_lc_clr)
8324 {
8325 case LSM6DSO32X_LC_NORMAL:
8326 *val = LSM6DSO32X_LC_NORMAL;
8327 break;
8328
8329 case LSM6DSO32X_LC_CLEAR:
8330 *val = LSM6DSO32X_LC_CLEAR;
8331 break;
8332
8333 case LSM6DSO32X_LC_CLEAR_DONE:
8334 *val = LSM6DSO32X_LC_CLEAR_DONE;
8335 break;
8336
8337 default:
8338 *val = LSM6DSO32X_LC_NORMAL;
8339 break;
8340 }
8341 }
8342
8343 if (ret == 0)
8344 {
8345 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8346 }
8347
8348 return ret;
8349 }
8350
8351 /**
8352 * @brief FSM output registers[get]
8353 *
8354 * @param ctx read / write interface definitions
8355 * @param val struct of registers from FSM_OUTS1 to FSM_OUTS16
8356 * @retval interface status (MANDATORY: return 0 -> no Error).
8357 *
8358 */
lsm6dso32x_fsm_out_get(stmdev_ctx_t * ctx,lsm6dso32x_fsm_out_t * val)8359 int32_t lsm6dso32x_fsm_out_get(stmdev_ctx_t *ctx,
8360 lsm6dso32x_fsm_out_t *val)
8361 {
8362 int32_t ret;
8363
8364 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8365
8366 if (ret == 0)
8367 {
8368 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_OUTS1, (uint8_t *)val,
8369 16);
8370 }
8371
8372 if (ret == 0)
8373 {
8374 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8375 }
8376
8377 return ret;
8378 }
8379
8380 /**
8381 * @brief Finite State Machine ODR configuration.[set]
8382 *
8383 * @param ctx read / write interface definitions
8384 * @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
8385 * @retval interface status (MANDATORY: return 0 -> no Error).
8386 *
8387 */
lsm6dso32x_fsm_data_rate_set(stmdev_ctx_t * ctx,lsm6dso32x_fsm_odr_t val)8388 int32_t lsm6dso32x_fsm_data_rate_set(stmdev_ctx_t *ctx,
8389 lsm6dso32x_fsm_odr_t val)
8390 {
8391 lsm6dso32x_emb_func_odr_cfg_b_t reg;
8392 int32_t ret;
8393
8394 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8395
8396 if (ret == 0)
8397 {
8398 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_B,
8399 (uint8_t *)®, 1);
8400 }
8401
8402 if (ret == 0)
8403 {
8404 reg.not_used_01 = 3; /* set default values */
8405 reg.not_used_02 = 2; /* set default values */
8406 reg.fsm_odr = (uint8_t)val;
8407 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_B,
8408 (uint8_t *)®, 1);
8409 }
8410
8411 if (ret == 0)
8412 {
8413 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8414 }
8415
8416 return ret;
8417 }
8418
8419 /**
8420 * @brief Finite State Machine ODR configuration.[get]
8421 *
8422 * @param ctx read / write interface definitions
8423 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
8424 * @retval interface status (MANDATORY: return 0 -> no Error).
8425 *
8426 */
lsm6dso32x_fsm_data_rate_get(stmdev_ctx_t * ctx,lsm6dso32x_fsm_odr_t * val)8427 int32_t lsm6dso32x_fsm_data_rate_get(stmdev_ctx_t *ctx,
8428 lsm6dso32x_fsm_odr_t *val)
8429 {
8430 lsm6dso32x_emb_func_odr_cfg_b_t reg;
8431 int32_t ret;
8432
8433 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8434
8435 if (ret == 0)
8436 {
8437 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_B,
8438 (uint8_t *)®, 1);
8439 }
8440
8441 if (ret == 0)
8442 {
8443 switch (reg.fsm_odr)
8444 {
8445 case LSM6DSO32X_ODR_FSM_12Hz5:
8446 *val = LSM6DSO32X_ODR_FSM_12Hz5;
8447 break;
8448
8449 case LSM6DSO32X_ODR_FSM_26Hz:
8450 *val = LSM6DSO32X_ODR_FSM_26Hz;
8451 break;
8452
8453 case LSM6DSO32X_ODR_FSM_52Hz:
8454 *val = LSM6DSO32X_ODR_FSM_52Hz;
8455 break;
8456
8457 case LSM6DSO32X_ODR_FSM_104Hz:
8458 *val = LSM6DSO32X_ODR_FSM_104Hz;
8459 break;
8460
8461 default:
8462 *val = LSM6DSO32X_ODR_FSM_12Hz5;
8463 break;
8464 }
8465
8466 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8467 }
8468
8469 return ret;
8470 }
8471
8472 /**
8473 * @brief FSM initialization request.[set]
8474 *
8475 * @param ctx read / write interface definitions
8476 * @param val change the values of fsm_init in reg FSM_INIT
8477 * @retval interface status (MANDATORY: return 0 -> no Error).
8478 *
8479 */
lsm6dso32x_fsm_init_set(stmdev_ctx_t * ctx,uint8_t val)8480 int32_t lsm6dso32x_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
8481 {
8482 lsm6dso32x_emb_func_init_b_t reg;
8483 int32_t ret;
8484
8485 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8486
8487 if (ret == 0)
8488 {
8489 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
8490 (uint8_t *)®, 1);
8491 }
8492
8493 if (ret == 0)
8494 {
8495 reg.fsm_init = val;
8496 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
8497 (uint8_t *)®, 1);
8498 }
8499
8500 if (ret == 0)
8501 {
8502 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8503 }
8504
8505 return ret;
8506 }
8507
8508 /**
8509 * @brief FSM initialization request.[get]
8510 *
8511 * @param ctx read / write interface definitions
8512 * @param val change the values of fsm_init in reg FSM_INIT
8513 * @retval interface status (MANDATORY: return 0 -> no Error).
8514 *
8515 */
lsm6dso32x_fsm_init_get(stmdev_ctx_t * ctx,uint8_t * val)8516 int32_t lsm6dso32x_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
8517 {
8518 lsm6dso32x_emb_func_init_b_t reg;
8519 int32_t ret;
8520
8521 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8522
8523 if (ret == 0)
8524 {
8525 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
8526 (uint8_t *)®, 1);
8527 }
8528
8529 if (ret == 0)
8530 {
8531 *val = reg.fsm_init;
8532 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8533 }
8534
8535 return ret;
8536 }
8537
8538 /**
8539 * @brief FSM long counter timeout register (r/w). The long counter
8540 * timeout value is an unsigned integer value (16-bit format).
8541 * When the long counter value reached this value,
8542 * the FSM generates an interrupt.[set]
8543 *
8544 * @param ctx read / write interface definitions
8545 * @param val the value of long counter
8546 * @retval interface status (MANDATORY: return 0 -> no Error).
8547 *
8548 */
lsm6dso32x_long_cnt_int_value_set(stmdev_ctx_t * ctx,uint16_t val)8549 int32_t lsm6dso32x_long_cnt_int_value_set(stmdev_ctx_t *ctx,
8550 uint16_t val)
8551 {
8552 int32_t ret;
8553
8554 uint8_t add_l;
8555 uint8_t add_h;
8556 add_h = (uint8_t)((val & 0xFF00U) >> 8);
8557 add_l = (uint8_t)(val & 0x00FFU);
8558 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_FSM_LC_TIMEOUT_L,
8559 &add_l);
8560
8561 if (ret == 0)
8562 {
8563 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_FSM_LC_TIMEOUT_H,
8564 &add_h);
8565 }
8566
8567 return ret;
8568 }
8569
8570 /**
8571 * @brief FSM long counter timeout register (r/w). The long counter
8572 * timeout value is an unsigned integer value (16-bit format).
8573 * When the long counter value reached this value,
8574 * the FSM generates an interrupt.[get]
8575 *
8576 * @param ctx read / write interface definitions
8577 * @param val buffer that stores the value of long counter
8578 * @retval interface status (MANDATORY: return 0 -> no Error).
8579 *
8580 */
lsm6dso32x_long_cnt_int_value_get(stmdev_ctx_t * ctx,uint16_t * val)8581 int32_t lsm6dso32x_long_cnt_int_value_get(stmdev_ctx_t *ctx,
8582 uint16_t *val)
8583 {
8584 int32_t ret;
8585
8586 uint8_t add_l;
8587 uint8_t add_h;
8588 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_FSM_LC_TIMEOUT_L,
8589 &add_l);
8590
8591 if (ret == 0)
8592 {
8593 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_FSM_LC_TIMEOUT_H,
8594 &add_h);
8595 *val = add_h;
8596 *val = *val << 8;
8597 *val += add_l;
8598 }
8599
8600 return ret;
8601 }
8602
8603 /**
8604 * @brief FSM number of programs register.[set]
8605 *
8606 * @param ctx read / write interface definitions
8607 * @param val value to write
8608 * @retval interface status (MANDATORY: return 0 -> no Error).
8609 *
8610 */
lsm6dso32x_fsm_number_of_programs_set(stmdev_ctx_t * ctx,uint8_t val)8611 int32_t lsm6dso32x_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
8612 uint8_t val)
8613 {
8614 int32_t ret;
8615
8616 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_FSM_PROGRAMS, &val);
8617
8618 return ret;
8619 }
8620
8621 /**
8622 * @brief FSM number of programs register.[get]
8623 *
8624 * @param ctx read / write interface definitions
8625 * @param val buffer that stores data read.
8626 * @retval interface status (MANDATORY: return 0 -> no Error).
8627 *
8628 */
lsm6dso32x_fsm_number_of_programs_get(stmdev_ctx_t * ctx,uint8_t * val)8629 int32_t lsm6dso32x_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
8630 uint8_t *val)
8631 {
8632 int32_t ret;
8633
8634 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_FSM_PROGRAMS, val);
8635
8636 return ret;
8637 }
8638
8639 /**
8640 * @brief FSM start address register (r/w).
8641 * First available address is 0x033C.[set]
8642 *
8643 * @param ctx read / write interface definitions
8644 * @param val the value of start address
8645 * @retval interface status (MANDATORY: return 0 -> no Error).
8646 *
8647 */
lsm6dso32x_fsm_start_address_set(stmdev_ctx_t * ctx,uint16_t val)8648 int32_t lsm6dso32x_fsm_start_address_set(stmdev_ctx_t *ctx,
8649 uint16_t val)
8650 {
8651 int32_t ret;
8652
8653 uint8_t add_l;
8654 uint8_t add_h;
8655 add_h = (uint8_t)((val & 0xFF00U) >> 8);
8656 add_l = (uint8_t)(val & 0x00FFU);
8657 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_FSM_START_ADD_L,
8658 &add_l);
8659
8660 if (ret == 0)
8661 {
8662 ret = lsm6dso32x_ln_pg_write_byte(ctx, LSM6DSO32X_FSM_START_ADD_H,
8663 &add_h);
8664 }
8665
8666 return ret;
8667 }
8668
8669 /**
8670 * @brief FSM start address register (r/w).
8671 * First available address is 0x033C.[get]
8672 *
8673 * @param ctx read / write interface definitions
8674 * @param val buffer the value of start address.
8675 * @retval interface status (MANDATORY: return 0 -> no Error).
8676 *
8677 */
lsm6dso32x_fsm_start_address_get(stmdev_ctx_t * ctx,uint16_t * val)8678 int32_t lsm6dso32x_fsm_start_address_get(stmdev_ctx_t *ctx,
8679 uint16_t *val)
8680 {
8681 int32_t ret;
8682
8683 uint8_t add_l;
8684 uint8_t add_h;
8685 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_FSM_START_ADD_L,
8686 &add_l);
8687
8688 if (ret == 0)
8689 {
8690 ret = lsm6dso32x_ln_pg_read_byte(ctx, LSM6DSO32X_FSM_START_ADD_H,
8691 &add_h);
8692 *val = add_h;
8693 *val = *val << 8;
8694 *val += add_l;
8695 }
8696
8697 return ret;
8698 }
8699
8700 /**
8701 * @}
8702 *
8703 */
8704
8705 /**
8706 * @addtogroup Machine Learning Core
8707 * @brief This section group all the functions concerning the
8708 * usage of Machine Learning Core
8709 * @{
8710 *
8711 */
8712
8713 /**
8714 * @brief Machine Learning Core status register[get]
8715 *
8716 * @param ctx read / write interface definitions
8717 * @param val register MLC_STATUS_MAINPAGE
8718 * @retval interface status (MANDATORY: return 0 -> no Error).
8719 *
8720 */
lsm6dso32x_mlc_status_get(stmdev_ctx_t * ctx,lsm6dso32x_mlc_status_mainpage_t * val)8721 int32_t lsm6dso32x_mlc_status_get(stmdev_ctx_t *ctx,
8722 lsm6dso32x_mlc_status_mainpage_t *val)
8723 {
8724 return lsm6dso32x_read_reg(ctx, LSM6DSO32X_MLC_STATUS_MAINPAGE,
8725 (uint8_t *) val, 1);
8726 }
8727
8728 /**
8729 * @brief Machine Learning Core data rate selection.[set]
8730 *
8731 * @param ctx read / write interface definitions
8732 * @param val get the values of mlc_odr in
8733 * reg EMB_FUNC_ODR_CFG_C
8734 * @retval interface status (MANDATORY: return 0 -> no Error).
8735 *
8736 */
lsm6dso32x_mlc_data_rate_set(stmdev_ctx_t * ctx,lsm6dso32x_mlc_odr_t val)8737 int32_t lsm6dso32x_mlc_data_rate_set(stmdev_ctx_t *ctx,
8738 lsm6dso32x_mlc_odr_t val)
8739 {
8740 lsm6dso32x_emb_func_odr_cfg_c_t reg;
8741 int32_t ret;
8742
8743 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8744
8745 if (ret == 0)
8746 {
8747 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_C,
8748 (uint8_t *)®, 1);
8749 }
8750
8751 if (ret == 0)
8752 {
8753 reg.mlc_odr = (uint8_t)val;
8754 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_C,
8755 (uint8_t *)®, 1);
8756 }
8757
8758 if (ret == 0)
8759 {
8760 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8761 }
8762
8763 return ret;
8764 }
8765
8766 /**
8767 * @brief Machine Learning Core data rate selection.[get]
8768 *
8769 * @param ctx read / write interface definitions
8770 * @param val change the values of mlc_odr in
8771 * reg EMB_FUNC_ODR_CFG_C
8772 * @retval interface status (MANDATORY: return 0 -> no Error).
8773 *
8774 */
lsm6dso32x_mlc_data_rate_get(stmdev_ctx_t * ctx,lsm6dso32x_mlc_odr_t * val)8775 int32_t lsm6dso32x_mlc_data_rate_get(stmdev_ctx_t *ctx,
8776 lsm6dso32x_mlc_odr_t *val)
8777 {
8778 lsm6dso32x_emb_func_odr_cfg_c_t reg;
8779 int32_t ret;
8780
8781 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
8782
8783 if (ret == 0)
8784 {
8785 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_C,
8786 (uint8_t *)®, 1);
8787 }
8788
8789 if (ret == 0)
8790 {
8791 switch (reg.mlc_odr)
8792 {
8793 case LSM6DSO32X_ODR_PRGS_12Hz5:
8794 *val = LSM6DSO32X_ODR_PRGS_12Hz5;
8795 break;
8796
8797 case LSM6DSO32X_ODR_PRGS_26Hz:
8798 *val = LSM6DSO32X_ODR_PRGS_26Hz;
8799 break;
8800
8801 case LSM6DSO32X_ODR_PRGS_52Hz:
8802 *val = LSM6DSO32X_ODR_PRGS_52Hz;
8803 break;
8804
8805 case LSM6DSO32X_ODR_PRGS_104Hz:
8806 *val = LSM6DSO32X_ODR_PRGS_104Hz;
8807 break;
8808
8809 default:
8810 *val = LSM6DSO32X_ODR_PRGS_12Hz5;
8811 break;
8812 }
8813
8814 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8815 }
8816
8817 return ret;
8818 }
8819
8820 /**
8821 * @}
8822 *
8823 */
8824
8825 /**
8826 * @defgroup LSM6DSO32X_Sensor_hub
8827 * @brief This section groups all the functions that manage the
8828 * sensor hub.
8829 * @{
8830 *
8831 */
8832
8833 /**
8834 * @brief Sensor hub output registers.[get]
8835 *
8836 * @param ctx read / write interface definitions
8837 * @param val union of registers from SENSOR_HUB_1 to SENSOR_HUB_18
8838 *
8839 */
lsm6dso32x_sh_read_data_raw_get(stmdev_ctx_t * ctx,lsm6dso32x_emb_sh_read_t * val,uint8_t len)8840 int32_t lsm6dso32x_sh_read_data_raw_get(stmdev_ctx_t *ctx,
8841 lsm6dso32x_emb_sh_read_t *val,
8842 uint8_t len)
8843 {
8844 int32_t ret;
8845
8846 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
8847
8848 if (ret == 0)
8849 {
8850 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SENSOR_HUB_1,
8851 (uint8_t *) val,
8852 len);
8853 }
8854
8855 if (ret == 0)
8856 {
8857 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8858 }
8859
8860 return ret;
8861 }
8862
8863 /**
8864 * @brief Number of external sensors to be read by the sensor hub.[set]
8865 *
8866 * @param ctx read / write interface definitions
8867 * @param val change the values of aux_sens_on in reg MASTER_CONFIG
8868 * @retval interface status (MANDATORY: return 0 -> no Error).
8869 *
8870 */
lsm6dso32x_sh_slave_connected_set(stmdev_ctx_t * ctx,lsm6dso32x_aux_sens_on_t val)8871 int32_t lsm6dso32x_sh_slave_connected_set(stmdev_ctx_t *ctx,
8872 lsm6dso32x_aux_sens_on_t val)
8873 {
8874 lsm6dso32x_master_config_t reg;
8875 int32_t ret;
8876
8877 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
8878
8879 if (ret == 0)
8880 {
8881 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
8882 (uint8_t *)®, 1);
8883 }
8884
8885 if (ret == 0)
8886 {
8887 reg.aux_sens_on = (uint8_t)val;
8888 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
8889 (uint8_t *)®, 1);
8890 }
8891
8892 if (ret == 0)
8893 {
8894 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8895 }
8896
8897 return ret;
8898 }
8899
8900 /**
8901 * @brief Number of external sensors to be read by the sensor hub.[get]
8902 *
8903 * @param ctx read / write interface definitions
8904 * @param val Get the values of aux_sens_on in reg MASTER_CONFIG
8905 * @retval interface status (MANDATORY: return 0 -> no Error).
8906 *
8907 */
lsm6dso32x_sh_slave_connected_get(stmdev_ctx_t * ctx,lsm6dso32x_aux_sens_on_t * val)8908 int32_t lsm6dso32x_sh_slave_connected_get(stmdev_ctx_t *ctx,
8909 lsm6dso32x_aux_sens_on_t *val)
8910 {
8911 lsm6dso32x_master_config_t reg;
8912 int32_t ret;
8913
8914 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
8915
8916 if (ret == 0)
8917 {
8918 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
8919 (uint8_t *)®, 1);
8920 }
8921
8922 if (ret == 0)
8923 {
8924 switch (reg.aux_sens_on)
8925 {
8926 case LSM6DSO32X_SLV_0:
8927 *val = LSM6DSO32X_SLV_0;
8928 break;
8929
8930 case LSM6DSO32X_SLV_0_1:
8931 *val = LSM6DSO32X_SLV_0_1;
8932 break;
8933
8934 case LSM6DSO32X_SLV_0_1_2:
8935 *val = LSM6DSO32X_SLV_0_1_2;
8936 break;
8937
8938 case LSM6DSO32X_SLV_0_1_2_3:
8939 *val = LSM6DSO32X_SLV_0_1_2_3;
8940 break;
8941
8942 default:
8943 *val = LSM6DSO32X_SLV_0;
8944 break;
8945 }
8946
8947 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8948 }
8949
8950 return ret;
8951 }
8952
8953 /**
8954 * @brief Sensor hub I2C master enable.[set]
8955 *
8956 * @param ctx read / write interface definitions
8957 * @param val change the values of master_on in reg MASTER_CONFIG
8958 * @retval interface status (MANDATORY: return 0 -> no Error).
8959 *
8960 */
lsm6dso32x_sh_master_set(stmdev_ctx_t * ctx,uint8_t val)8961 int32_t lsm6dso32x_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
8962 {
8963 lsm6dso32x_master_config_t reg;
8964 int32_t ret;
8965
8966 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
8967
8968 if (ret == 0)
8969 {
8970 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
8971 (uint8_t *)®, 1);
8972 }
8973
8974 if (ret == 0)
8975 {
8976 reg.master_on = val;
8977 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
8978 (uint8_t *)®, 1);
8979 }
8980
8981 if (ret == 0)
8982 {
8983 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
8984 }
8985
8986 return ret;
8987 }
8988
8989 /**
8990 * @brief Sensor hub I2C master enable.[get]
8991 *
8992 * @param ctx read / write interface definitions
8993 * @param val change the values of master_on in reg MASTER_CONFIG
8994 * @retval interface status (MANDATORY: return 0 -> no Error).
8995 *
8996 */
lsm6dso32x_sh_master_get(stmdev_ctx_t * ctx,uint8_t * val)8997 int32_t lsm6dso32x_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
8998 {
8999 lsm6dso32x_master_config_t reg;
9000 int32_t ret;
9001
9002 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9003
9004 if (ret == 0)
9005 {
9006 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9007 (uint8_t *)®, 1);
9008 }
9009
9010 if (ret == 0)
9011 {
9012 *val = reg.master_on;
9013 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9014 }
9015
9016 return ret;
9017 }
9018
9019 /**
9020 * @brief Master I2C pull-up enable.[set]
9021 *
9022 * @param ctx read / write interface definitions
9023 * @param val change the values of shub_pu_en in reg MASTER_CONFIG
9024 * @retval interface status (MANDATORY: return 0 -> no Error).
9025 *
9026 */
lsm6dso32x_sh_pin_mode_set(stmdev_ctx_t * ctx,lsm6dso32x_shub_pu_en_t val)9027 int32_t lsm6dso32x_sh_pin_mode_set(stmdev_ctx_t *ctx,
9028 lsm6dso32x_shub_pu_en_t val)
9029 {
9030 lsm6dso32x_master_config_t reg;
9031 int32_t ret;
9032
9033 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9034
9035 if (ret == 0)
9036 {
9037 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9038 (uint8_t *)®, 1);
9039 }
9040
9041 if (ret == 0)
9042 {
9043 reg.shub_pu_en = (uint8_t)val;
9044 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9045 (uint8_t *)®, 1);
9046 }
9047
9048 if (ret == 0)
9049 {
9050 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9051 }
9052
9053 return ret;
9054 }
9055
9056 /**
9057 * @brief Master I2C pull-up enable.[get]
9058 *
9059 * @param ctx read / write interface definitions
9060 * @param val Get the values of shub_pu_en in reg MASTER_CONFIG
9061 * @retval interface status (MANDATORY: return 0 -> no Error).
9062 *
9063 */
lsm6dso32x_sh_pin_mode_get(stmdev_ctx_t * ctx,lsm6dso32x_shub_pu_en_t * val)9064 int32_t lsm6dso32x_sh_pin_mode_get(stmdev_ctx_t *ctx,
9065 lsm6dso32x_shub_pu_en_t *val)
9066 {
9067 lsm6dso32x_master_config_t reg;
9068 int32_t ret;
9069
9070 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9071
9072 if (ret == 0)
9073 {
9074 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9075 (uint8_t *)®, 1);
9076 }
9077
9078 if (ret == 0)
9079 {
9080 switch (reg.shub_pu_en)
9081 {
9082 case LSM6DSO32X_EXT_PULL_UP:
9083 *val = LSM6DSO32X_EXT_PULL_UP;
9084 break;
9085
9086 case LSM6DSO32X_INTERNAL_PULL_UP:
9087 *val = LSM6DSO32X_INTERNAL_PULL_UP;
9088 break;
9089
9090 default:
9091 *val = LSM6DSO32X_EXT_PULL_UP;
9092 break;
9093 }
9094
9095 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9096 }
9097
9098 return ret;
9099 }
9100
9101 /**
9102 * @brief I2C interface pass-through.[set]
9103 *
9104 * @param ctx read / write interface definitions
9105 * @param val change the values of pass_through_mode in
9106 * reg MASTER_CONFIG
9107 * @retval interface status (MANDATORY: return 0 -> no Error).
9108 *
9109 */
lsm6dso32x_sh_pass_through_set(stmdev_ctx_t * ctx,uint8_t val)9110 int32_t lsm6dso32x_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
9111 {
9112 lsm6dso32x_master_config_t reg;
9113 int32_t ret;
9114
9115 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9116
9117 if (ret == 0)
9118 {
9119 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9120 (uint8_t *)®, 1);
9121 }
9122
9123 if (ret == 0)
9124 {
9125 reg.pass_through_mode = val;
9126 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9127 (uint8_t *)®, 1);
9128 }
9129
9130 if (ret == 0)
9131 {
9132 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9133 }
9134
9135 return ret;
9136 }
9137
9138 /**
9139 * @brief I2C interface pass-through.[get]
9140 *
9141 * @param ctx read / write interface definitions
9142 * @param val change the values of pass_through_mode in
9143 * reg MASTER_CONFIG
9144 * @retval interface status (MANDATORY: return 0 -> no Error).
9145 *
9146 */
lsm6dso32x_sh_pass_through_get(stmdev_ctx_t * ctx,uint8_t * val)9147 int32_t lsm6dso32x_sh_pass_through_get(stmdev_ctx_t *ctx,
9148 uint8_t *val)
9149 {
9150 lsm6dso32x_master_config_t reg;
9151 int32_t ret;
9152
9153 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9154
9155 if (ret == 0)
9156 {
9157 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9158 (uint8_t *)®, 1);
9159 }
9160
9161 if (ret == 0)
9162 {
9163 *val = reg.pass_through_mode;
9164 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9165 }
9166
9167 return ret;
9168 }
9169
9170 /**
9171 * @brief Sensor hub trigger signal selection.[set]
9172 *
9173 * @param ctx read / write interface definitions
9174 * @param val change the values of start_config in reg MASTER_CONFIG
9175 * @retval interface status (MANDATORY: return 0 -> no Error).
9176 *
9177 */
lsm6dso32x_sh_syncro_mode_set(stmdev_ctx_t * ctx,lsm6dso32x_start_config_t val)9178 int32_t lsm6dso32x_sh_syncro_mode_set(stmdev_ctx_t *ctx,
9179 lsm6dso32x_start_config_t val)
9180 {
9181 lsm6dso32x_master_config_t reg;
9182 int32_t ret;
9183
9184 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9185
9186 if (ret == 0)
9187 {
9188 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9189 (uint8_t *)®, 1);
9190 }
9191
9192 if (ret == 0)
9193 {
9194 reg.start_config = (uint8_t)val;
9195 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9196 (uint8_t *)®, 1);
9197 }
9198
9199 if (ret == 0)
9200 {
9201 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9202 }
9203
9204 return ret;
9205 }
9206
9207 /**
9208 * @brief Sensor hub trigger signal selection.[get]
9209 *
9210 * @param ctx read / write interface definitions
9211 * @param val Get the values of start_config in reg MASTER_CONFIG
9212 * @retval interface status (MANDATORY: return 0 -> no Error).
9213 *
9214 */
lsm6dso32x_sh_syncro_mode_get(stmdev_ctx_t * ctx,lsm6dso32x_start_config_t * val)9215 int32_t lsm6dso32x_sh_syncro_mode_get(stmdev_ctx_t *ctx,
9216 lsm6dso32x_start_config_t *val)
9217 {
9218 lsm6dso32x_master_config_t reg;
9219 int32_t ret;
9220
9221 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9222
9223 if (ret == 0)
9224 {
9225 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9226 (uint8_t *)®, 1);
9227 }
9228
9229 if (ret == 0)
9230 {
9231 switch (reg.start_config)
9232 {
9233 case LSM6DSO32X_EXT_ON_INT2_PIN:
9234 *val = LSM6DSO32X_EXT_ON_INT2_PIN;
9235 break;
9236
9237 case LSM6DSO32X_XL_GY_DRDY:
9238 *val = LSM6DSO32X_XL_GY_DRDY;
9239 break;
9240
9241 default:
9242 *val = LSM6DSO32X_EXT_ON_INT2_PIN;
9243 break;
9244 }
9245
9246 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9247 }
9248
9249 return ret;
9250 }
9251
9252 /**
9253 * @brief Slave 0 write operation is performed only at the first
9254 * sensor hub cycle.[set]
9255 *
9256 * @param ctx read / write interface definitions
9257 * @param val change the values of write_once in reg MASTER_CONFIG
9258 * @retval interface status (MANDATORY: return 0 -> no Error).
9259 *
9260 */
lsm6dso32x_sh_write_mode_set(stmdev_ctx_t * ctx,lsm6dso32x_write_once_t val)9261 int32_t lsm6dso32x_sh_write_mode_set(stmdev_ctx_t *ctx,
9262 lsm6dso32x_write_once_t val)
9263 {
9264 lsm6dso32x_master_config_t reg;
9265 int32_t ret;
9266
9267 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9268
9269 if (ret == 0)
9270 {
9271 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9272 (uint8_t *)®, 1);
9273 }
9274
9275 if (ret == 0)
9276 {
9277 reg.write_once = (uint8_t)val;
9278 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9279 (uint8_t *)®, 1);
9280 }
9281
9282 if (ret == 0)
9283 {
9284 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9285 }
9286
9287 return ret;
9288 }
9289
9290 /**
9291 * @brief Slave 0 write operation is performed only at the first sensor
9292 * hub cycle.[get]
9293 *
9294 * @param ctx read / write interface definitions
9295 * @param val Get the values of write_once in reg MASTER_CONFIG
9296 * @retval interface status (MANDATORY: return 0 -> no Error).
9297 *
9298 */
lsm6dso32x_sh_write_mode_get(stmdev_ctx_t * ctx,lsm6dso32x_write_once_t * val)9299 int32_t lsm6dso32x_sh_write_mode_get(stmdev_ctx_t *ctx,
9300 lsm6dso32x_write_once_t *val)
9301 {
9302 lsm6dso32x_master_config_t reg;
9303 int32_t ret;
9304
9305 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9306
9307 if (ret == 0)
9308 {
9309 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9310 (uint8_t *)®, 1);
9311 }
9312
9313 if (ret == 0)
9314 {
9315 switch (reg.write_once)
9316 {
9317 case LSM6DSO32X_EACH_SH_CYCLE:
9318 *val = LSM6DSO32X_EACH_SH_CYCLE;
9319 break;
9320
9321 case LSM6DSO32X_ONLY_FIRST_CYCLE:
9322 *val = LSM6DSO32X_ONLY_FIRST_CYCLE;
9323 break;
9324
9325 default:
9326 *val = LSM6DSO32X_EACH_SH_CYCLE;
9327 break;
9328 }
9329
9330 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9331 }
9332
9333 return ret;
9334 }
9335
9336 /**
9337 * @brief Reset Master logic and output registers.[set]
9338 *
9339 * @param ctx read / write interface definitions
9340 * @retval interface status (MANDATORY: return 0 -> no Error).
9341 *
9342 */
lsm6dso32x_sh_reset_set(stmdev_ctx_t * ctx)9343 int32_t lsm6dso32x_sh_reset_set(stmdev_ctx_t *ctx)
9344 {
9345 lsm6dso32x_master_config_t reg;
9346 int32_t ret;
9347
9348 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9349
9350 if (ret == 0)
9351 {
9352 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9353 (uint8_t *)®, 1);
9354 }
9355
9356 if (ret == 0)
9357 {
9358 reg.rst_master_regs = PROPERTY_ENABLE;
9359 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9360 (uint8_t *)®, 1);
9361 }
9362
9363 if (ret == 0)
9364 {
9365 reg.rst_master_regs = PROPERTY_DISABLE;
9366 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9367 (uint8_t *)®, 1);
9368 }
9369
9370 if (ret == 0)
9371 {
9372 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9373 }
9374
9375 return ret;
9376 }
9377
9378 /**
9379 * @brief Reset Master logic and output registers.[get]
9380 *
9381 * @param ctx read / write interface definitions
9382 * @param val change the values of rst_master_regs in reg MASTER_CONFIG
9383 * @retval interface status (MANDATORY: return 0 -> no Error).
9384 *
9385 */
lsm6dso32x_sh_reset_get(stmdev_ctx_t * ctx,uint8_t * val)9386 int32_t lsm6dso32x_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
9387 {
9388 lsm6dso32x_master_config_t reg;
9389 int32_t ret;
9390
9391 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9392
9393 if (ret == 0)
9394 {
9395 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MASTER_CONFIG,
9396 (uint8_t *)®, 1);
9397 }
9398
9399 if (ret == 0)
9400 {
9401 *val = reg.rst_master_regs;
9402 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9403 }
9404
9405 return ret;
9406 }
9407
9408 /**
9409 * @brief Rate at which the master communicates.[set]
9410 *
9411 * @param ctx read / write interface definitions
9412 * @param val change the values of shub_odr in reg slv1_CONFIG
9413 * @retval interface status (MANDATORY: return 0 -> no Error).
9414 *
9415 */
lsm6dso32x_sh_data_rate_set(stmdev_ctx_t * ctx,lsm6dso32x_shub_odr_t val)9416 int32_t lsm6dso32x_sh_data_rate_set(stmdev_ctx_t *ctx,
9417 lsm6dso32x_shub_odr_t val)
9418 {
9419 lsm6dso32x_slv0_config_t reg;
9420 int32_t ret;
9421
9422 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9423
9424 if (ret == 0)
9425 {
9426 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
9427 (uint8_t *)®, 1);
9428 }
9429
9430 if (ret == 0)
9431 {
9432 reg.shub_odr = (uint8_t)val;
9433 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
9434 (uint8_t *)®, 1);
9435 }
9436
9437 if (ret == 0)
9438 {
9439 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9440 }
9441
9442 return ret;
9443 }
9444
9445 /**
9446 * @brief Rate at which the master communicates.[get]
9447 *
9448 * @param ctx read / write interface definitions
9449 * @param val Get the values of shub_odr in reg slv1_CONFIG
9450 * @retval interface status (MANDATORY: return 0 -> no Error).
9451 *
9452 */
lsm6dso32x_sh_data_rate_get(stmdev_ctx_t * ctx,lsm6dso32x_shub_odr_t * val)9453 int32_t lsm6dso32x_sh_data_rate_get(stmdev_ctx_t *ctx,
9454 lsm6dso32x_shub_odr_t *val)
9455 {
9456 lsm6dso32x_slv0_config_t reg;
9457 int32_t ret;
9458
9459 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9460
9461 if (ret == 0)
9462 {
9463 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
9464 (uint8_t *)®, 1);
9465 }
9466
9467 if (ret == 0)
9468 {
9469 switch (reg.shub_odr)
9470 {
9471 case LSM6DSO32X_SH_ODR_104Hz:
9472 *val = LSM6DSO32X_SH_ODR_104Hz;
9473 break;
9474
9475 case LSM6DSO32X_SH_ODR_52Hz:
9476 *val = LSM6DSO32X_SH_ODR_52Hz;
9477 break;
9478
9479 case LSM6DSO32X_SH_ODR_26Hz:
9480 *val = LSM6DSO32X_SH_ODR_26Hz;
9481 break;
9482
9483 case LSM6DSO32X_SH_ODR_13Hz:
9484 *val = LSM6DSO32X_SH_ODR_13Hz;
9485 break;
9486
9487 default:
9488 *val = LSM6DSO32X_SH_ODR_104Hz;
9489 break;
9490 }
9491
9492 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9493 }
9494
9495 return ret;
9496 }
9497
9498 /**
9499 * @brief Configure slave 0 for perform a write.[set]
9500 *
9501 * @param ctx read / write interface definitions
9502 * @param val a structure that contain
9503 * - uint8_t slv1_add; 8 bit i2c device address
9504 * - uint8_t slv1_subadd; 8 bit register device address
9505 * - uint8_t slv1_data; 8 bit data to write
9506 * @retval interface status (MANDATORY: return 0 -> no Error).
9507 *
9508 */
lsm6dso32x_sh_cfg_write(stmdev_ctx_t * ctx,lsm6dso32x_sh_cfg_write_t * val)9509 int32_t lsm6dso32x_sh_cfg_write(stmdev_ctx_t *ctx,
9510 lsm6dso32x_sh_cfg_write_t *val)
9511 {
9512 lsm6dso32x_slv0_add_t reg;
9513 int32_t ret;
9514
9515 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9516
9517 if (ret == 0)
9518 {
9519 reg.slave0 = val->slv0_add;
9520 reg.rw_0 = 0;
9521 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_ADD, (uint8_t *)®, 1);
9522 }
9523
9524 if (ret == 0)
9525 {
9526 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_SUBADD,
9527 &(val->slv0_subadd), 1);
9528 }
9529
9530 if (ret == 0)
9531 {
9532 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_DATAWRITE_SLV0,
9533 &(val->slv0_data), 1);
9534 }
9535
9536 if (ret == 0)
9537 {
9538 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9539 }
9540
9541 return ret;
9542 }
9543
9544 /**
9545 * @brief Configure slave 0 for perform a read.[set]
9546 *
9547 * @param ctx read / write interface definitions
9548 * @param val Structure that contain
9549 * - uint8_t slv1_add; 8 bit i2c device address
9550 * - uint8_t slv1_subadd; 8 bit register device address
9551 * - uint8_t slv1_len; num of bit to read
9552 * @retval interface status (MANDATORY: return 0 -> no Error).
9553 *
9554 */
lsm6dso32x_sh_slv0_cfg_read(stmdev_ctx_t * ctx,lsm6dso32x_sh_cfg_read_t * val)9555 int32_t lsm6dso32x_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
9556 lsm6dso32x_sh_cfg_read_t *val)
9557 {
9558 lsm6dso32x_slv0_add_t slv0_add;
9559 lsm6dso32x_slv0_config_t slv0_config;
9560 int32_t ret;
9561
9562 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9563
9564 if (ret == 0)
9565 {
9566 slv0_add.slave0 = val->slv_add;
9567 slv0_add.rw_0 = 1;
9568 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_ADD,
9569 (uint8_t *)&slv0_add, 1);
9570 }
9571
9572 if (ret == 0)
9573 {
9574 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_SUBADD,
9575 &(val->slv_subadd), 1);
9576 }
9577
9578 if (ret == 0)
9579 {
9580 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
9581 (uint8_t *)&slv0_config, 1);
9582 }
9583
9584 if (ret == 0)
9585 {
9586 slv0_config.slave0_numop = val->slv_len;
9587 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV0_CONFIG,
9588 (uint8_t *)&slv0_config, 1);
9589 }
9590
9591 if (ret == 0)
9592 {
9593 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9594 }
9595
9596 return ret;
9597 }
9598
9599 /**
9600 * @brief Configure slave 0 for perform a write/read.[set]
9601 *
9602 * @param ctx read / write interface definitions
9603 * @param val Structure that contain
9604 * - uint8_t slv1_add; 8 bit i2c device address
9605 * - uint8_t slv1_subadd; 8 bit register device address
9606 * - uint8_t slv1_len; num of bit to read
9607 * @retval interface status (MANDATORY: return 0 -> no Error).
9608 *
9609 */
lsm6dso32x_sh_slv1_cfg_read(stmdev_ctx_t * ctx,lsm6dso32x_sh_cfg_read_t * val)9610 int32_t lsm6dso32x_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
9611 lsm6dso32x_sh_cfg_read_t *val)
9612 {
9613 lsm6dso32x_slv1_add_t slv1_add;
9614 lsm6dso32x_slv1_config_t slv1_config;
9615 int32_t ret;
9616
9617 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9618
9619 if (ret == 0)
9620 {
9621 slv1_add.slave1_add = val->slv_add;
9622 slv1_add.r_1 = 1;
9623 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV1_ADD,
9624 (uint8_t *)&slv1_add, 1);
9625 }
9626
9627 if (ret == 0)
9628 {
9629 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV1_SUBADD,
9630 &(val->slv_subadd), 1);
9631 }
9632
9633 if (ret == 0)
9634 {
9635 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV1_CONFIG,
9636 (uint8_t *)&slv1_config, 1);
9637 }
9638
9639 if (ret == 0)
9640 {
9641 slv1_config.slave1_numop = val->slv_len;
9642 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV1_CONFIG,
9643 (uint8_t *)&slv1_config, 1);
9644 }
9645
9646 if (ret == 0)
9647 {
9648 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9649 }
9650
9651 return ret;
9652 }
9653
9654 /**
9655 * @brief Configure slave 0 for perform a write/read.[set]
9656 *
9657 * @param ctx read / write interface definitions
9658 * @param val Structure that contain
9659 * - uint8_t slv2_add; 8 bit i2c device address
9660 * - uint8_t slv2_subadd; 8 bit register device address
9661 * - uint8_t slv2_len; num of bit to read
9662 * @retval interface status (MANDATORY: return 0 -> no Error).
9663 *
9664 */
lsm6dso32x_sh_slv2_cfg_read(stmdev_ctx_t * ctx,lsm6dso32x_sh_cfg_read_t * val)9665 int32_t lsm6dso32x_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
9666 lsm6dso32x_sh_cfg_read_t *val)
9667 {
9668 lsm6dso32x_slv2_add_t slv2_add;
9669 lsm6dso32x_slv2_config_t slv2_config;
9670 int32_t ret;
9671
9672 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9673
9674 if (ret == 0)
9675 {
9676 slv2_add.slave2_add = val->slv_add;
9677 slv2_add.r_2 = 1;
9678 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV2_ADD,
9679 (uint8_t *)&slv2_add, 1);
9680 }
9681
9682 if (ret == 0)
9683 {
9684 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV2_SUBADD,
9685 &(val->slv_subadd), 1);
9686 }
9687
9688 if (ret == 0)
9689 {
9690 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV2_CONFIG,
9691 (uint8_t *)&slv2_config, 1);
9692 }
9693
9694 if (ret == 0)
9695 {
9696 slv2_config.slave2_numop = val->slv_len;
9697 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV2_CONFIG,
9698 (uint8_t *)&slv2_config, 1);
9699 }
9700
9701 if (ret == 0)
9702 {
9703 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9704 }
9705
9706 return ret;
9707 }
9708
9709 /**
9710 * @brief Configure slave 0 for perform a write/read.[set]
9711 *
9712 * @param ctx read / write interface definitions
9713 * @param val Structure that contain
9714 * - uint8_t slv3_add; 8 bit i2c device address
9715 * - uint8_t slv3_subadd; 8 bit register device address
9716 * - uint8_t slv3_len; num of bit to read
9717 * @retval interface status (MANDATORY: return 0 -> no Error).
9718 *
9719 */
lsm6dso32x_sh_slv3_cfg_read(stmdev_ctx_t * ctx,lsm6dso32x_sh_cfg_read_t * val)9720 int32_t lsm6dso32x_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
9721 lsm6dso32x_sh_cfg_read_t *val)
9722 {
9723 lsm6dso32x_slv3_add_t slv3_add;
9724 lsm6dso32x_slv3_config_t slv3_config;
9725 int32_t ret;
9726
9727 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9728
9729 if (ret == 0)
9730 {
9731 slv3_add.slave3_add = val->slv_add;
9732 slv3_add.r_3 = 1;
9733 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV3_ADD,
9734 (uint8_t *)&slv3_add, 1);
9735 }
9736
9737 if (ret == 0)
9738 {
9739 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV3_SUBADD,
9740 &(val->slv_subadd), 1);
9741 }
9742
9743 if (ret == 0)
9744 {
9745 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_SLV3_CONFIG,
9746 (uint8_t *)&slv3_config, 1);
9747 }
9748
9749 if (ret == 0)
9750 {
9751 slv3_config.slave3_numop = val->slv_len;
9752 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_SLV3_CONFIG,
9753 (uint8_t *)&slv3_config, 1);
9754 }
9755
9756 if (ret == 0)
9757 {
9758 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9759 }
9760
9761 return ret;
9762 }
9763
9764 /**
9765 * @brief Sensor hub source register.[get]
9766 *
9767 * @param ctx read / write interface definitions
9768 * @param val union of registers from STATUS_MASTER to
9769 * @retval interface status (MANDATORY: return 0 -> no Error).
9770 *
9771 */
lsm6dso32x_sh_status_get(stmdev_ctx_t * ctx,lsm6dso32x_status_master_t * val)9772 int32_t lsm6dso32x_sh_status_get(stmdev_ctx_t *ctx,
9773 lsm6dso32x_status_master_t *val)
9774 {
9775 int32_t ret;
9776
9777 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_SENSOR_HUB_BANK);
9778
9779 if (ret == 0)
9780 {
9781 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_MASTER,
9782 (uint8_t *) val, 1);
9783 }
9784
9785 if (ret == 0)
9786 {
9787 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9788 }
9789
9790 return ret;
9791 }
9792
9793 /**
9794 * @}
9795 *
9796 */
9797
9798 /**
9799 * @defgroup Basic configuration
9800 * @brief This section groups all the functions concerning
9801 * device basic configuration.
9802 * @{
9803 *
9804 */
9805
9806 /**
9807 * @brief Device "Who am I".[get]
9808 *
9809 * @param ctx communication interface handler. Use NULL to ignore
9810 * this interface.(ptr)
9811 * @param val ID values read from the two interfaces. ID values
9812 * will be the same.(ptr)
9813 * @retval interface status (MANDATORY: return 0 -> no Error).
9814 *
9815 */
lsm6dso32x_id_get(stmdev_ctx_t * ctx,lsm6dso32x_id_t * val)9816 int32_t lsm6dso32x_id_get(stmdev_ctx_t *ctx, lsm6dso32x_id_t *val)
9817 {
9818 int32_t ret = 0;
9819
9820 if (ctx != NULL)
9821 {
9822 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_WHO_AM_I,
9823 (uint8_t *) & (val->ui), 1);
9824 }
9825
9826 return ret;
9827 }
9828
9829 /**
9830 * @brief Re-initialize the device.[set]
9831 *
9832 * @param ctx communication interface handler.(ptr)
9833 * @param val re-initialization mode. Refer to datasheet
9834 * and application note for more information
9835 * about differencies between boot and sw_reset
9836 * procedure.
9837 * @retval interface status (MANDATORY: return 0 -> no Error).
9838 *
9839 */
lsm6dso32x_init_set(stmdev_ctx_t * ctx,lsm6dso32x_init_t val)9840 int32_t lsm6dso32x_init_set(stmdev_ctx_t *ctx, lsm6dso32x_init_t val)
9841 {
9842 lsm6dso32x_emb_func_init_a_t emb_func_init_a;
9843 lsm6dso32x_emb_func_init_b_t emb_func_init_b;
9844 lsm6dso32x_ctrl3_c_t ctrl3_c;
9845 int32_t ret;
9846
9847 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
9848
9849 if (ret == 0)
9850 {
9851 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
9852 (uint8_t *)&emb_func_init_b, 1);
9853 }
9854
9855 if (ret == 0)
9856 {
9857 emb_func_init_b.fifo_compr_init = (uint8_t)val
9858 & ((uint8_t)LSM6DSO32X_FIFO_COMP >> 2);
9859 emb_func_init_b.fsm_init = (uint8_t)val
9860 & ((uint8_t)LSM6DSO32X_FSM >> 3);
9861 emb_func_init_b.mlc_init = (uint8_t)val
9862 & ((uint8_t)LSM6DSO32X_MLC >> 4);
9863 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_B,
9864 (uint8_t *)&emb_func_init_b, 1);
9865 }
9866
9867 if (ret == 0)
9868 {
9869 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_A,
9870 (uint8_t *)&emb_func_init_a, 1);
9871 }
9872
9873 if (ret == 0)
9874 {
9875 emb_func_init_a.step_det_init = ((uint8_t)val
9876 & (uint8_t)LSM6DSO32X_PEDO) >> 5;
9877 emb_func_init_a.tilt_init = ((uint8_t)val
9878 & (uint8_t)LSM6DSO32X_TILT) >> 6;
9879 emb_func_init_a.sig_mot_init = ((uint8_t)val
9880 & (uint8_t)LSM6DSO32X_SMOTION) >> 7;
9881 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INIT_A,
9882 (uint8_t *)&emb_func_init_a, 1);
9883 }
9884
9885 if (ret == 0)
9886 {
9887 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
9888 }
9889
9890 if (ret == 0)
9891 {
9892 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
9893 (uint8_t *)&ctrl3_c, 1);
9894 }
9895
9896 if (((val == LSM6DSO32X_BOOT) || (val == LSM6DSO32X_RESET)) &&
9897 (ret == 0))
9898 {
9899 ctrl3_c.boot = (uint8_t)val & (uint8_t)LSM6DSO32X_BOOT;
9900 ctrl3_c.sw_reset = ((uint8_t)val & (uint8_t)LSM6DSO32X_RESET) >> 1;
9901 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C,
9902 (uint8_t *)&ctrl3_c, 1);
9903 }
9904
9905 if ((val == LSM6DSO32X_DRV_RDY)
9906 && ((ctrl3_c.bdu == PROPERTY_DISABLE)
9907 || (ctrl3_c.if_inc == PROPERTY_DISABLE)) && (ret == 0))
9908 {
9909 ctrl3_c.bdu = PROPERTY_ENABLE;
9910 ctrl3_c.if_inc = PROPERTY_ENABLE;
9911 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C,
9912 (uint8_t *)&ctrl3_c, 1);
9913 }
9914
9915 return ret;
9916 }
9917
9918 /**
9919 * @brief Configures the bus operating mode.[set]
9920 *
9921 * @param ctx communication interface handler. Use NULL to ignore
9922 * this interface.(ptr)
9923 * @param val configures the bus operating mode for both the
9924 * main and the auxiliary interface.
9925 * @retval interface status (MANDATORY: return 0 -> no Error).
9926 *
9927 */
lsm6dso32x_bus_mode_set(stmdev_ctx_t * ctx,lsm6dso32x_bus_mode_t val)9928 int32_t lsm6dso32x_bus_mode_set(stmdev_ctx_t *ctx,
9929 lsm6dso32x_bus_mode_t val)
9930 {
9931 lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
9932 lsm6dso32x_ctrl9_xl_t ctrl9_xl;
9933 lsm6dso32x_ctrl3_c_t ctrl3_c;
9934 lsm6dso32x_ctrl4_c_t ctrl4_c;
9935 uint8_t bit_val;
9936 int32_t ret;
9937
9938 ret = 0;
9939
9940 if (ctx != NULL)
9941 {
9942 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL,
9943 (uint8_t *)&ctrl9_xl, 1);
9944
9945 bit_val = ((uint8_t)val.ui_bus_md & 0x04U) >> 2;
9946
9947 if ((ret == 0) && (ctrl9_xl.i3c_disable != bit_val))
9948 {
9949 ctrl9_xl.i3c_disable = bit_val;
9950 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL9_XL,
9951 (uint8_t *)&ctrl9_xl, 1);
9952 }
9953
9954 if (ret == 0)
9955 {
9956 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
9957 (uint8_t *)&i3c_bus_avb, 1);
9958 }
9959
9960 bit_val = ((uint8_t)val.ui_bus_md & 0x30U) >> 4;
9961
9962 if ((ret == 0) && (i3c_bus_avb.i3c_bus_avb_sel != bit_val))
9963 {
9964 i3c_bus_avb.i3c_bus_avb_sel = bit_val;
9965 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
9966 (uint8_t *)&i3c_bus_avb, 1);
9967 }
9968
9969 if (ret == 0)
9970 {
9971 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C,
9972 (uint8_t *)&ctrl4_c, 1);
9973 }
9974
9975 bit_val = ((uint8_t)val.ui_bus_md & 0x02U) >> 1;
9976
9977 if ((ret == 0) && (ctrl4_c.i2c_disable != bit_val))
9978 {
9979 ctrl4_c.i2c_disable = bit_val;
9980 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C,
9981 (uint8_t *)&ctrl4_c, 1);
9982 }
9983
9984 if (ret == 0)
9985 {
9986 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
9987 (uint8_t *)&ctrl3_c, 1);
9988 }
9989
9990 bit_val = (uint8_t)val.ui_bus_md & 0x01U;
9991
9992 if ((ret == 0) && (ctrl3_c.sim != bit_val))
9993 {
9994 ctrl3_c.sim = bit_val;
9995 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C,
9996 (uint8_t *)&ctrl3_c, 1);
9997 }
9998 }
9999
10000 return ret;
10001 }
10002
10003 /**
10004 * @brief Get the bus operating mode.[get]
10005 *
10006 * @param ctx communication interface handler. Use NULL to ignore
10007 * this interface.(ptr)
10008 * @param val retrieves the bus operating mode for both the main
10009 * and the auxiliary interface.(ptr)
10010 * @retval interface status (MANDATORY: return 0 -> no Error).
10011 *
10012 */
lsm6dso32x_bus_mode_get(stmdev_ctx_t * ctx,lsm6dso32x_bus_mode_t * val)10013 int32_t lsm6dso32x_bus_mode_get(stmdev_ctx_t *ctx,
10014 lsm6dso32x_bus_mode_t *val)
10015 {
10016 lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
10017 lsm6dso32x_ctrl9_xl_t ctrl9_xl;
10018 lsm6dso32x_ctrl3_c_t ctrl3_c;
10019 lsm6dso32x_ctrl4_c_t ctrl4_c;
10020 int32_t ret = 0;
10021
10022 if (ctx != NULL)
10023 {
10024 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL9_XL,
10025 (uint8_t *)&ctrl9_xl, 1);
10026
10027 if (ret == 0)
10028 {
10029 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
10030 (uint8_t *)&i3c_bus_avb, 1);
10031 }
10032
10033 if (ret == 0)
10034 {
10035 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C,
10036 (uint8_t *)&ctrl4_c, 1);
10037 }
10038
10039 if (ret == 0)
10040 {
10041 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
10042 (uint8_t *)&ctrl3_c, 1);
10043
10044 switch ((i3c_bus_avb.i3c_bus_avb_sel << 4) &
10045 (ctrl9_xl.i3c_disable << 2) &
10046 (ctrl4_c.i2c_disable << 1) & ctrl3_c.sim)
10047 {
10048 case LSM6DSO32X_SEL_BY_HW:
10049 val->ui_bus_md = LSM6DSO32X_SEL_BY_HW;
10050 break;
10051
10052 case LSM6DSO32X_SPI_4W:
10053 val->ui_bus_md = LSM6DSO32X_SPI_4W;
10054 break;
10055
10056 case LSM6DSO32X_SPI_3W:
10057 val->ui_bus_md = LSM6DSO32X_SPI_3W;
10058 break;
10059
10060 case LSM6DSO32X_I2C:
10061 val->ui_bus_md = LSM6DSO32X_I2C;
10062 break;
10063
10064 case LSM6DSO32X_I3C_T_50us:
10065 val->ui_bus_md = LSM6DSO32X_I3C_T_50us;
10066 break;
10067
10068 case LSM6DSO32X_I3C_T_2us:
10069 val->ui_bus_md = LSM6DSO32X_I3C_T_2us;
10070 break;
10071
10072 case LSM6DSO32X_I3C_T_1ms:
10073 val->ui_bus_md = LSM6DSO32X_I3C_T_1ms;
10074 break;
10075
10076 case LSM6DSO32X_I3C_T_25ms:
10077 val->ui_bus_md = LSM6DSO32X_I3C_T_25ms;
10078 break;
10079
10080 default:
10081 val->ui_bus_md = LSM6DSO32X_SEL_BY_HW;
10082 break;
10083 }
10084 }
10085 }
10086
10087 return ret;
10088 }
10089
10090 /**
10091 * @brief Get the status of the device.[get]
10092 *
10093 * @param ctx communication interface handler. Use NULL to ignore
10094 * this interface.(ptr)
10095 * @param val the status of the device.(ptr)
10096 * @retval interface status (MANDATORY: return 0 -> no Error).
10097 *
10098 */
lsm6dso32x_status_get(stmdev_ctx_t * ctx,lsm6dso32x_status_t * val)10099 int32_t lsm6dso32x_status_get(stmdev_ctx_t *ctx,
10100 lsm6dso32x_status_t *val)
10101 {
10102 lsm6dso32x_status_reg_t status_reg;
10103 lsm6dso32x_ctrl3_c_t ctrl3_c;
10104 int32_t ret;
10105 ret = 0;
10106
10107 if (ctx != NULL)
10108 {
10109 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
10110 (uint8_t *)&ctrl3_c, 1);
10111 val->sw_reset = ctrl3_c.sw_reset;
10112 val->boot = ctrl3_c.boot;
10113
10114 if ((ret == 0) && (ctrl3_c.sw_reset == PROPERTY_DISABLE) &&
10115 (ctrl3_c.boot == PROPERTY_DISABLE))
10116 {
10117 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_STATUS_REG,
10118 (uint8_t *)&status_reg, 1);
10119 val->drdy_xl = status_reg.xlda;
10120 val->drdy_g = status_reg.gda;
10121 val->drdy_temp = status_reg.tda;
10122 }
10123 }
10124
10125 return ret;
10126 }
10127
10128 /**
10129 * @brief Electrical pin configuration.[set]
10130 *
10131 * @param ctx communication interface handler.(ptr)
10132 * @param val the electrical settings for the configurable
10133 * pins.
10134 * @retval interface status (MANDATORY: return 0 -> no Error).
10135 *
10136 */
lsm6dso32x_pin_conf_set(stmdev_ctx_t * ctx,lsm6dso32x_pin_conf_t val)10137 int32_t lsm6dso32x_pin_conf_set(stmdev_ctx_t *ctx,
10138 lsm6dso32x_pin_conf_t val)
10139 {
10140 lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
10141 lsm6dso32x_pin_ctrl_t pin_ctrl;
10142 lsm6dso32x_ctrl3_c_t ctrl3_c;
10143 int32_t ret;
10144
10145 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PIN_CTRL,
10146 (uint8_t *)&pin_ctrl, 1);
10147
10148 if (ret == 0)
10149 {
10150 pin_ctrl.sdo_pu_en = val.sdo_sa0_pull_up;
10151 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PIN_CTRL,
10152 (uint8_t *)&pin_ctrl, 1);
10153 }
10154
10155 if (ret == 0)
10156 {
10157 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
10158 (uint8_t *)&ctrl3_c, 1);
10159 }
10160
10161 if (ret == 0)
10162 {
10163 ctrl3_c.pp_od = ~val.int1_int2_push_pull;
10164 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C,
10165 (uint8_t *)&ctrl3_c, 1);
10166 }
10167
10168 if (ret == 0)
10169 {
10170 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
10171 (uint8_t *)&i3c_bus_avb, 1);
10172 }
10173
10174 if (ret == 0)
10175 {
10176 i3c_bus_avb.pd_dis_int1 = ~val.int1_pull_down;
10177 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
10178 (uint8_t *)&i3c_bus_avb, 1);
10179 }
10180
10181 return ret;
10182 }
10183
10184 /**
10185 * @brief Electrical pin configuration.[get]
10186 *
10187 * @param ctx communication interface handler.(ptr)
10188 * @param val the electrical settings for the configurable
10189 * pins.(ptr)
10190 * @retval interface status (MANDATORY: return 0 -> no Error).
10191 *
10192 */
lsm6dso32x_pin_conf_get(stmdev_ctx_t * ctx,lsm6dso32x_pin_conf_t * val)10193 int32_t lsm6dso32x_pin_conf_get(stmdev_ctx_t *ctx,
10194 lsm6dso32x_pin_conf_t *val)
10195 {
10196 lsm6dso32x_i3c_bus_avb_t i3c_bus_avb;
10197 lsm6dso32x_pin_ctrl_t pin_ctrl;
10198 lsm6dso32x_ctrl3_c_t ctrl3_c;
10199 int32_t ret;
10200
10201 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PIN_CTRL,
10202 (uint8_t *)&pin_ctrl, 1);
10203
10204 if (ret == 0)
10205 {
10206 val->aux_sdo_ocs_pull_up = pin_ctrl.sdo_pu_en;
10207 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
10208 (uint8_t *)&ctrl3_c, 1);
10209 }
10210
10211 if (ret == 0)
10212 {
10213 val->int1_int2_push_pull = ~ctrl3_c.pp_od;
10214 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_I3C_BUS_AVB,
10215 (uint8_t *)&i3c_bus_avb, 1);
10216 }
10217
10218 if (ret == 0)
10219 {
10220 val->int1_pull_down = ~i3c_bus_avb.pd_dis_int1;
10221 }
10222
10223 return ret;
10224 }
10225
10226 /**
10227 * @brief Interrupt pins hardware signal configuration.[set]
10228 *
10229 * @param ctx communication interface handler.(ptr)
10230 * @param val the pins hardware signal settings.
10231 * @retval interface status (MANDATORY: return 0 -> no Error).
10232 *
10233 */
lsm6dso32x_interrupt_mode_set(stmdev_ctx_t * ctx,lsm6dso32x_int_mode_t val)10234 int32_t lsm6dso32x_interrupt_mode_set(stmdev_ctx_t *ctx,
10235 lsm6dso32x_int_mode_t val)
10236 {
10237 lsm6dso32x_tap_cfg0_t tap_cfg0;
10238 lsm6dso32x_page_rw_t page_rw;
10239 lsm6dso32x_ctrl3_c_t ctrl3_c;
10240 int32_t ret;
10241
10242 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
10243 (uint8_t *)&ctrl3_c, 1);
10244
10245 if (ret == 0)
10246 {
10247 ctrl3_c.h_lactive = val.active_low;
10248 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL3_C,
10249 (uint8_t *)&ctrl3_c, 1);
10250 }
10251
10252 if (ret == 0)
10253 {
10254 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0,
10255 (uint8_t *) &tap_cfg0, 1);
10256 }
10257
10258 if (ret == 0)
10259 {
10260 tap_cfg0.lir = val.base_latched;
10261 tap_cfg0.int_clr_on_read = val.base_latched | val.emb_latched;
10262 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG0,
10263 (uint8_t *) &tap_cfg0, 1);
10264 }
10265
10266 if (ret == 0)
10267 {
10268 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
10269 }
10270
10271 if (ret == 0)
10272 {
10273 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
10274 (uint8_t *) &page_rw, 1);
10275 }
10276
10277 if (ret == 0)
10278 {
10279 page_rw.emb_func_lir = val.emb_latched;
10280 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
10281 (uint8_t *) &page_rw, 1);
10282 }
10283
10284 if (ret == 0)
10285 {
10286 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
10287 }
10288
10289 return ret;
10290 }
10291
10292 /**
10293 * @brief Interrupt pins hardware signal configuration.[get]
10294 *
10295 * @param ctx communication interface handler.(ptr)
10296 * @param val the pins hardware signal settings.(ptr)
10297 * @retval interface status (MANDATORY: return 0 -> no Error).
10298 *
10299 */
lsm6dso32x_interrupt_mode_get(stmdev_ctx_t * ctx,lsm6dso32x_int_mode_t * val)10300 int32_t lsm6dso32x_interrupt_mode_get(stmdev_ctx_t *ctx,
10301 lsm6dso32x_int_mode_t *val)
10302 {
10303 lsm6dso32x_tap_cfg0_t tap_cfg0;
10304 lsm6dso32x_page_rw_t page_rw;
10305 lsm6dso32x_ctrl3_c_t ctrl3_c;
10306 int32_t ret;
10307
10308 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL3_C,
10309 (uint8_t *)&ctrl3_c, 1);
10310
10311 if (ret == 0)
10312 {
10313 ctrl3_c.h_lactive = val->active_low;
10314 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG0,
10315 (uint8_t *) &tap_cfg0, 1);
10316 }
10317
10318 if (ret == 0)
10319 {
10320 tap_cfg0.lir = val->base_latched;
10321 tap_cfg0.int_clr_on_read = val->base_latched | val->emb_latched;
10322 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
10323 }
10324
10325 if (ret == 0)
10326 {
10327 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_PAGE_RW,
10328 (uint8_t *) &page_rw, 1);
10329 }
10330
10331 if (ret == 0)
10332 {
10333 page_rw.emb_func_lir = val->emb_latched;
10334 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_PAGE_RW,
10335 (uint8_t *) &page_rw, 1);
10336 }
10337
10338 if (ret == 0)
10339 {
10340 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
10341 }
10342
10343 return ret;
10344 }
10345
10346 /**
10347 * @brief Route interrupt signals on int1 pin.[set]
10348 *
10349 * @param ctx communication interface handler.(ptr)
10350 * @param val the signals to route on int1 pin.
10351 * @retval interface status (MANDATORY: return 0 -> no Error).
10352 *
10353 */
lsm6dso32x_pin_int1_route_set(stmdev_ctx_t * ctx,lsm6dso32x_pin_int1_route_t val)10354 int32_t lsm6dso32x_pin_int1_route_set(stmdev_ctx_t *ctx,
10355 lsm6dso32x_pin_int1_route_t val)
10356 {
10357 lsm6dso32x_pin_int2_route_t pin_int2_route;
10358 lsm6dso32x_emb_func_int1_t emb_func_int1 = {0};
10359 lsm6dso32x_fsm_int1_a_t fsm_int1_a = {0};
10360 lsm6dso32x_fsm_int1_b_t fsm_int1_b = {0};
10361 lsm6dso32x_int1_ctrl_t int1_ctrl = {0};
10362 lsm6dso32x_int2_ctrl_t int2_ctrl;
10363 lsm6dso32x_mlc_int1_t mlc_int1 = {0};
10364 lsm6dso32x_tap_cfg2_t tap_cfg2;
10365 lsm6dso32x_md2_cfg_t md2_cfg;
10366 lsm6dso32x_md1_cfg_t md1_cfg = {0};
10367 lsm6dso32x_ctrl4_c_t ctrl4_c;
10368 int32_t ret;
10369
10370 int1_ctrl.int1_drdy_xl = val.drdy_xl;
10371 int1_ctrl.int1_drdy_g = val.drdy_g;
10372 int1_ctrl.int1_boot = val.boot;
10373 int1_ctrl.int1_fifo_th = val.fifo_th;
10374 int1_ctrl.int1_fifo_ovr = val.fifo_ovr;
10375 int1_ctrl.int1_fifo_full = val.fifo_full;
10376 int1_ctrl.int1_cnt_bdr = val.fifo_bdr;
10377 int1_ctrl.den_drdy_flag = val.den_flag;
10378 md1_cfg.int1_shub = val.sh_endop;
10379 md1_cfg.int1_6d = val.six_d;
10380 md1_cfg.int1_double_tap = val.double_tap;
10381 md1_cfg.int1_ff = val.free_fall;
10382 md1_cfg.int1_wu = val.wake_up;
10383 md1_cfg.int1_single_tap = val.single_tap;
10384 md1_cfg.int1_sleep_change = val.sleep_change;
10385 emb_func_int1.int1_step_detector = val.step_detector;
10386 emb_func_int1.int1_tilt = val.tilt;
10387 emb_func_int1.int1_sig_mot = val.sig_mot;
10388 emb_func_int1.int1_fsm_lc = val.fsm_lc;
10389 fsm_int1_a.int1_fsm1 = val.fsm1;
10390 fsm_int1_a.int1_fsm2 = val.fsm2;
10391 fsm_int1_a.int1_fsm3 = val.fsm3;
10392 fsm_int1_a.int1_fsm4 = val.fsm4;
10393 fsm_int1_a.int1_fsm5 = val.fsm5;
10394 fsm_int1_a.int1_fsm6 = val.fsm6;
10395 fsm_int1_a.int1_fsm7 = val.fsm7;
10396 fsm_int1_a.int1_fsm8 = val.fsm8;
10397 fsm_int1_b.int1_fsm9 = val.fsm9 ;
10398 fsm_int1_b.int1_fsm10 = val.fsm10;
10399 fsm_int1_b.int1_fsm11 = val.fsm11;
10400 fsm_int1_b.int1_fsm12 = val.fsm12;
10401 fsm_int1_b.int1_fsm13 = val.fsm13;
10402 fsm_int1_b.int1_fsm14 = val.fsm14;
10403 fsm_int1_b.int1_fsm15 = val.fsm15;
10404 fsm_int1_b.int1_fsm16 = val.fsm16;
10405 mlc_int1.int1_mlc1 = val.mlc1;
10406 mlc_int1.int1_mlc2 = val.mlc2;
10407 mlc_int1.int1_mlc3 = val.mlc3;
10408 mlc_int1.int1_mlc4 = val.mlc4;
10409 mlc_int1.int1_mlc5 = val.mlc5;
10410 mlc_int1.int1_mlc6 = val.mlc6;
10411 mlc_int1.int1_mlc7 = val.mlc7;
10412 mlc_int1.int1_mlc8 = val.mlc8;
10413 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C,
10414 (uint8_t *)&ctrl4_c, 1);
10415
10416 if (ret == 0)
10417 {
10418 if ((val.drdy_temp | val.timestamp) != PROPERTY_DISABLE)
10419 {
10420 ctrl4_c.int2_on_int1 = PROPERTY_ENABLE;
10421 }
10422
10423 else
10424 {
10425 ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
10426 }
10427
10428 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C,
10429 (uint8_t *)&ctrl4_c, 1);
10430 }
10431
10432 if (ret == 0)
10433 {
10434 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
10435 }
10436
10437 if (ret == 0)
10438 {
10439 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MLC_INT1,
10440 (uint8_t *)&mlc_int1, 1);
10441 }
10442
10443 if (ret == 0)
10444 {
10445 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INT1,
10446 (uint8_t *)&emb_func_int1, 1);
10447 }
10448
10449 if (ret == 0)
10450 {
10451 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT1_A,
10452 (uint8_t *)&fsm_int1_a, 1);
10453 }
10454
10455 if (ret == 0)
10456 {
10457 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT1_B,
10458 (uint8_t *)&fsm_int1_b, 1);
10459 }
10460
10461 if (ret == 0)
10462 {
10463 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
10464 }
10465
10466 if (ret == 0)
10467 {
10468 if ((emb_func_int1.int1_fsm_lc
10469 | emb_func_int1.int1_sig_mot
10470 | emb_func_int1.int1_step_detector
10471 | emb_func_int1.int1_tilt
10472 | fsm_int1_a.int1_fsm1
10473 | fsm_int1_a.int1_fsm2
10474 | fsm_int1_a.int1_fsm3
10475 | fsm_int1_a.int1_fsm4
10476 | fsm_int1_a.int1_fsm5
10477 | fsm_int1_a.int1_fsm6
10478 | fsm_int1_a.int1_fsm7
10479 | fsm_int1_a.int1_fsm8
10480 | fsm_int1_b.int1_fsm9
10481 | fsm_int1_b.int1_fsm10
10482 | fsm_int1_b.int1_fsm11
10483 | fsm_int1_b.int1_fsm12
10484 | fsm_int1_b.int1_fsm13
10485 | fsm_int1_b.int1_fsm14
10486 | fsm_int1_b.int1_fsm15
10487 | fsm_int1_b.int1_fsm16
10488 | mlc_int1.int1_mlc1
10489 | mlc_int1.int1_mlc2
10490 | mlc_int1.int1_mlc3
10491 | mlc_int1.int1_mlc4
10492 | mlc_int1.int1_mlc5
10493 | mlc_int1.int1_mlc6
10494 | mlc_int1.int1_mlc7
10495 | mlc_int1.int1_mlc8) != PROPERTY_DISABLE)
10496 {
10497 md1_cfg.int1_emb_func = PROPERTY_ENABLE;
10498 }
10499
10500 else
10501 {
10502 md1_cfg.int1_emb_func = PROPERTY_DISABLE;
10503 }
10504
10505 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INT1_CTRL,
10506 (uint8_t *)&int1_ctrl, 1);
10507 }
10508
10509 if (ret == 0)
10510 {
10511 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MD1_CFG,
10512 (uint8_t *)&md1_cfg, 1);
10513 }
10514
10515 if (ret == 0)
10516 {
10517 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT2_CTRL,
10518 (uint8_t *)&int2_ctrl, 1);
10519 }
10520
10521 if (ret == 0)
10522 {
10523 int2_ctrl.int2_drdy_temp = val.drdy_temp;
10524 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INT2_CTRL,
10525 (uint8_t *)&int2_ctrl, 1);
10526 }
10527
10528 if (ret == 0)
10529 {
10530 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MD2_CFG,
10531 (uint8_t *)&md2_cfg, 1);
10532 }
10533
10534 if (ret == 0)
10535 {
10536 md2_cfg.int2_timestamp = val.timestamp;
10537 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MD2_CFG,
10538 (uint8_t *)&md2_cfg, 1);
10539 }
10540
10541 if (ret == 0)
10542 {
10543 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2,
10544 (uint8_t *) &tap_cfg2, 1);
10545 }
10546
10547 if (ret == 0)
10548 {
10549 ret = lsm6dso32x_pin_int2_route_get(ctx, &pin_int2_route);
10550 }
10551
10552 if (ret == 0)
10553 {
10554 if ((pin_int2_route.fifo_bdr
10555 | pin_int2_route.drdy_g
10556 | pin_int2_route.drdy_temp
10557 | pin_int2_route.drdy_xl
10558 | pin_int2_route.fifo_full
10559 | pin_int2_route.fifo_ovr
10560 | pin_int2_route.fifo_th
10561 | pin_int2_route.six_d
10562 | pin_int2_route.double_tap
10563 | pin_int2_route.free_fall
10564 | pin_int2_route.wake_up
10565 | pin_int2_route.single_tap
10566 | pin_int2_route.sleep_change
10567 | int1_ctrl.den_drdy_flag
10568 | int1_ctrl.int1_boot
10569 | int1_ctrl.int1_cnt_bdr
10570 | int1_ctrl.int1_drdy_g
10571 | int1_ctrl.int1_drdy_xl
10572 | int1_ctrl.int1_fifo_full
10573 | int1_ctrl.int1_fifo_ovr
10574 | int1_ctrl.int1_fifo_th
10575 | md1_cfg.int1_shub
10576 | md1_cfg.int1_6d
10577 | md1_cfg.int1_double_tap
10578 | md1_cfg.int1_ff
10579 | md1_cfg.int1_wu
10580 | md1_cfg.int1_single_tap
10581 | md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
10582 {
10583 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
10584 }
10585
10586 else
10587 {
10588 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
10589 }
10590
10591 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG2,
10592 (uint8_t *) &tap_cfg2, 1);
10593 }
10594
10595 return ret;
10596 }
10597
10598 /**
10599 * @brief Route interrupt signals on int1 pin.[get]
10600 *
10601 * @param ctx communication interface handler.(ptr)
10602 * @param val the signals that are routed on int1 pin.(ptr)
10603 * @retval interface status (MANDATORY: return 0 -> no Error).
10604 *
10605 */
lsm6dso32x_pin_int1_route_get(stmdev_ctx_t * ctx,lsm6dso32x_pin_int1_route_t * val)10606 int32_t lsm6dso32x_pin_int1_route_get(stmdev_ctx_t *ctx,
10607 lsm6dso32x_pin_int1_route_t *val)
10608 {
10609 lsm6dso32x_emb_func_int1_t emb_func_int1;
10610 lsm6dso32x_fsm_int1_a_t fsm_int1_a;
10611 lsm6dso32x_fsm_int1_b_t fsm_int1_b;
10612 lsm6dso32x_int1_ctrl_t int1_ctrl;
10613 lsm6dso32x_int2_ctrl_t int2_ctrl;
10614 lsm6dso32x_mlc_int1_t mlc_int1;
10615 lsm6dso32x_md2_cfg_t md2_cfg;
10616 lsm6dso32x_md1_cfg_t md1_cfg;
10617 lsm6dso32x_ctrl4_c_t ctrl4_c;
10618 int32_t ret;
10619 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
10620
10621 if (ret == 0)
10622 {
10623 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MLC_INT1,
10624 (uint8_t *)&mlc_int1, 1);
10625 }
10626
10627 if (ret == 0)
10628 {
10629 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INT1,
10630 (uint8_t *)&emb_func_int1, 1);
10631 }
10632
10633 if (ret == 0)
10634 {
10635 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_INT1_A,
10636 (uint8_t *)&fsm_int1_a, 1);
10637 }
10638
10639 if (ret == 0)
10640 {
10641 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_INT1_B,
10642 (uint8_t *)&fsm_int1_b, 1);
10643 }
10644
10645 if (ret == 0)
10646 {
10647 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
10648 }
10649
10650 if (ret == 0)
10651 {
10652 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT1_CTRL,
10653 (uint8_t *)&int1_ctrl, 1);
10654 }
10655
10656 if (ret == 0)
10657 {
10658 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MD1_CFG,
10659 (uint8_t *)&md1_cfg, 1);
10660 }
10661
10662 if (ret == 0)
10663 {
10664 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C,
10665 (uint8_t *)&ctrl4_c, 1);
10666 }
10667
10668 if (ctrl4_c.int2_on_int1 == PROPERTY_ENABLE)
10669 {
10670 if (ret == 0)
10671 {
10672 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT2_CTRL,
10673 (uint8_t *)&int2_ctrl, 1);
10674 val->drdy_temp = int2_ctrl.int2_drdy_temp;
10675 }
10676
10677 if (ret == 0)
10678 {
10679 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MD2_CFG,
10680 (uint8_t *)&md2_cfg, 1);
10681 val->timestamp = md2_cfg.int2_timestamp;
10682 }
10683 }
10684
10685 else
10686 {
10687 val->drdy_temp = PROPERTY_DISABLE;
10688 val->timestamp = PROPERTY_DISABLE;
10689 }
10690
10691 val->drdy_xl = int1_ctrl.int1_drdy_xl;
10692 val->drdy_g = int1_ctrl.int1_drdy_g;
10693 val->boot = int1_ctrl.int1_boot;
10694 val->fifo_th = int1_ctrl.int1_fifo_th;
10695 val->fifo_ovr = int1_ctrl.int1_fifo_ovr;
10696 val->fifo_full = int1_ctrl.int1_fifo_full;
10697 val->fifo_bdr = int1_ctrl.int1_cnt_bdr;
10698 val->den_flag = int1_ctrl.den_drdy_flag;
10699 val->sh_endop = md1_cfg.int1_shub;
10700 val->six_d = md1_cfg.int1_6d;
10701 val->double_tap = md1_cfg.int1_double_tap;
10702 val->free_fall = md1_cfg.int1_ff;
10703 val->wake_up = md1_cfg.int1_wu;
10704 val->single_tap = md1_cfg.int1_single_tap;
10705 val->sleep_change = md1_cfg.int1_sleep_change;
10706 val->step_detector = emb_func_int1.int1_step_detector;
10707 val->tilt = emb_func_int1.int1_tilt;
10708 val->sig_mot = emb_func_int1.int1_sig_mot;
10709 val->fsm_lc = emb_func_int1.int1_fsm_lc;
10710 val->fsm1 = fsm_int1_a.int1_fsm1;
10711 val->fsm2 = fsm_int1_a.int1_fsm2;
10712 val->fsm3 = fsm_int1_a.int1_fsm3;
10713 val->fsm4 = fsm_int1_a.int1_fsm4;
10714 val->fsm5 = fsm_int1_a.int1_fsm5;
10715 val->fsm6 = fsm_int1_a.int1_fsm6;
10716 val->fsm7 = fsm_int1_a.int1_fsm7;
10717 val->fsm8 = fsm_int1_a.int1_fsm8;
10718 val->fsm9 = fsm_int1_b.int1_fsm9;
10719 val->fsm10 = fsm_int1_b.int1_fsm10;
10720 val->fsm11 = fsm_int1_b.int1_fsm11;
10721 val->fsm12 = fsm_int1_b.int1_fsm12;
10722 val->fsm13 = fsm_int1_b.int1_fsm13;
10723 val->fsm14 = fsm_int1_b.int1_fsm14;
10724 val->fsm15 = fsm_int1_b.int1_fsm15;
10725 val->fsm16 = fsm_int1_b.int1_fsm16;
10726 val->mlc1 = mlc_int1.int1_mlc1;
10727 val->mlc2 = mlc_int1.int1_mlc2;
10728 val->mlc3 = mlc_int1.int1_mlc3;
10729 val->mlc4 = mlc_int1.int1_mlc4;
10730 val->mlc5 = mlc_int1.int1_mlc5;
10731 val->mlc6 = mlc_int1.int1_mlc6;
10732 val->mlc7 = mlc_int1.int1_mlc7;
10733 val->mlc8 = mlc_int1.int1_mlc8;
10734
10735 return ret;
10736 }
10737
10738 /**
10739 * @brief Route interrupt signals on int2 pin.[set]
10740 *
10741 * @param ctx communication interface handler. Use NULL to ignore
10742 * this interface.(ptr)
10743 * @param val the signals to route on int2 pin.
10744 * @retval interface status (MANDATORY: return 0 -> no Error).
10745 *
10746 */
lsm6dso32x_pin_int2_route_set(stmdev_ctx_t * ctx,lsm6dso32x_pin_int2_route_t val)10747 int32_t lsm6dso32x_pin_int2_route_set(stmdev_ctx_t *ctx,
10748 lsm6dso32x_pin_int2_route_t val)
10749 {
10750 lsm6dso32x_pin_int1_route_t pin_int1_route;
10751 lsm6dso32x_emb_func_int2_t emb_func_int2 = {0};
10752 lsm6dso32x_fsm_int2_a_t fsm_int2_a = {0};
10753 lsm6dso32x_fsm_int2_b_t fsm_int2_b = {0};
10754 lsm6dso32x_int2_ctrl_t int2_ctrl = {0};
10755 lsm6dso32x_mlc_int2_t mlc_int2 = {0};
10756 lsm6dso32x_tap_cfg2_t tap_cfg2;
10757 lsm6dso32x_md2_cfg_t md2_cfg = {0};
10758 lsm6dso32x_ctrl4_c_t ctrl4_c;
10759 int32_t ret;
10760 ret = 0;
10761
10762 if (ctx != NULL)
10763 {
10764 int2_ctrl.int2_drdy_xl = val.drdy_xl;
10765 int2_ctrl.int2_drdy_g = val.drdy_g;
10766 int2_ctrl.int2_drdy_temp = val.drdy_temp;
10767 int2_ctrl.int2_fifo_th = val.fifo_th;
10768 int2_ctrl.int2_fifo_ovr = val.fifo_ovr;
10769 int2_ctrl.int2_fifo_full = val.fifo_full;
10770 int2_ctrl.int2_cnt_bdr = val.fifo_bdr;
10771 md2_cfg.int2_timestamp = val.timestamp;
10772 md2_cfg.int2_6d = val.six_d;
10773 md2_cfg.int2_double_tap = val.double_tap;
10774 md2_cfg.int2_ff = val.free_fall;
10775 md2_cfg.int2_wu = val.wake_up;
10776 md2_cfg.int2_single_tap = val.single_tap;
10777 md2_cfg.int2_sleep_change = val.sleep_change;
10778 emb_func_int2. int2_step_detector = val.step_detector;
10779 emb_func_int2.int2_tilt = val.tilt;
10780 emb_func_int2.int2_fsm_lc = val.fsm_lc;
10781 fsm_int2_a.int2_fsm1 = val.fsm1;
10782 fsm_int2_a.int2_fsm2 = val.fsm2;
10783 fsm_int2_a.int2_fsm3 = val.fsm3;
10784 fsm_int2_a.int2_fsm4 = val.fsm4;
10785 fsm_int2_a.int2_fsm5 = val.fsm5;
10786 fsm_int2_a.int2_fsm6 = val.fsm6;
10787 fsm_int2_a.int2_fsm7 = val.fsm7;
10788 fsm_int2_a.int2_fsm8 = val.fsm8;
10789 fsm_int2_b.int2_fsm9 = val.fsm9 ;
10790 fsm_int2_b.int2_fsm10 = val.fsm10;
10791 fsm_int2_b.int2_fsm11 = val.fsm11;
10792 fsm_int2_b.int2_fsm12 = val.fsm12;
10793 fsm_int2_b.int2_fsm13 = val.fsm13;
10794 fsm_int2_b.int2_fsm14 = val.fsm14;
10795 fsm_int2_b.int2_fsm15 = val.fsm15;
10796 fsm_int2_b.int2_fsm16 = val.fsm16;
10797 mlc_int2.int2_mlc1 = val.mlc1;
10798 mlc_int2.int2_mlc2 = val.mlc2;
10799 mlc_int2.int2_mlc3 = val.mlc3;
10800 mlc_int2.int2_mlc4 = val.mlc4;
10801 mlc_int2.int2_mlc5 = val.mlc5;
10802 mlc_int2.int2_mlc6 = val.mlc6;
10803 mlc_int2.int2_mlc7 = val.mlc7;
10804 mlc_int2.int2_mlc8 = val.mlc8;
10805
10806 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C,
10807 (uint8_t *)&ctrl4_c, 1);
10808
10809 if (ret == 0)
10810 {
10811 if ((val.drdy_temp | val.timestamp) != PROPERTY_DISABLE)
10812 {
10813 ctrl4_c.int2_on_int1 = PROPERTY_DISABLE;
10814 }
10815 else
10816 {
10817 ctrl4_c.int2_on_int1 = PROPERTY_ENABLE;
10818 }
10819
10820 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL4_C,
10821 (uint8_t *)&ctrl4_c, 1);
10822 }
10823
10824 if (ret == 0)
10825 {
10826 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
10827 }
10828
10829 if (ret == 0)
10830 {
10831 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MLC_INT2,
10832 (uint8_t *)&mlc_int2, 1);
10833 }
10834
10835 if (ret == 0)
10836 {
10837 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_INT2,
10838 (uint8_t *)&emb_func_int2, 1);
10839 }
10840
10841 if (ret == 0)
10842 {
10843 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT2_A,
10844 (uint8_t *)&fsm_int2_a, 1);
10845 }
10846
10847 if (ret == 0)
10848 {
10849 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FSM_INT2_B,
10850 (uint8_t *)&fsm_int2_b, 1);
10851 }
10852
10853 if (ret == 0)
10854 {
10855 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
10856 }
10857
10858 if (ret == 0)
10859 {
10860 if ((emb_func_int2.int2_fsm_lc
10861 | emb_func_int2.int2_sig_mot
10862 | emb_func_int2.int2_step_detector
10863 | emb_func_int2.int2_tilt
10864 | fsm_int2_a.int2_fsm1
10865 | fsm_int2_a.int2_fsm2
10866 | fsm_int2_a.int2_fsm3
10867 | fsm_int2_a.int2_fsm4
10868 | fsm_int2_a.int2_fsm5
10869 | fsm_int2_a.int2_fsm6
10870 | fsm_int2_a.int2_fsm7
10871 | fsm_int2_a.int2_fsm8
10872 | fsm_int2_b.int2_fsm9
10873 | fsm_int2_b.int2_fsm10
10874 | fsm_int2_b.int2_fsm11
10875 | fsm_int2_b.int2_fsm12
10876 | fsm_int2_b.int2_fsm13
10877 | fsm_int2_b.int2_fsm14
10878 | fsm_int2_b.int2_fsm15
10879 | fsm_int2_b.int2_fsm16
10880 | mlc_int2.int2_mlc1
10881 | mlc_int2.int2_mlc2
10882 | mlc_int2.int2_mlc3
10883 | mlc_int2.int2_mlc4
10884 | mlc_int2.int2_mlc5
10885 | mlc_int2.int2_mlc6
10886 | mlc_int2.int2_mlc7
10887 | mlc_int2.int2_mlc8) != PROPERTY_DISABLE)
10888 {
10889 md2_cfg.int2_emb_func = PROPERTY_ENABLE;
10890 }
10891
10892 else
10893 {
10894 md2_cfg.int2_emb_func = PROPERTY_DISABLE;
10895 }
10896
10897 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_INT2_CTRL,
10898 (uint8_t *)&int2_ctrl, 1);
10899 }
10900
10901 if (ret == 0)
10902 {
10903 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_MD2_CFG,
10904 (uint8_t *)&md2_cfg, 1);
10905 }
10906
10907 if (ret == 0)
10908 {
10909 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_TAP_CFG2,
10910 (uint8_t *) &tap_cfg2, 1);
10911 }
10912
10913 if (ret == 0)
10914 {
10915 ret = lsm6dso32x_pin_int1_route_get(ctx, &pin_int1_route);
10916 }
10917
10918 if (ret == 0)
10919 {
10920 if ((val.fifo_bdr
10921 | val.drdy_g
10922 | val.drdy_temp
10923 | val.drdy_xl
10924 | val.fifo_full
10925 | val.fifo_ovr
10926 | val.fifo_th
10927 | val.six_d
10928 | val.double_tap
10929 | val.free_fall
10930 | val.wake_up
10931 | val.single_tap
10932 | val.sleep_change
10933 | pin_int1_route.den_flag
10934 | pin_int1_route.boot
10935 | pin_int1_route.fifo_bdr
10936 | pin_int1_route.drdy_g
10937 | pin_int1_route.drdy_xl
10938 | pin_int1_route.fifo_full
10939 | pin_int1_route.fifo_ovr
10940 | pin_int1_route.fifo_th
10941 | pin_int1_route.six_d
10942 | pin_int1_route.double_tap
10943 | pin_int1_route.free_fall
10944 | pin_int1_route.wake_up
10945 | pin_int1_route.single_tap
10946 | pin_int1_route.sleep_change) != PROPERTY_DISABLE)
10947 {
10948 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
10949 }
10950
10951 else
10952 {
10953 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
10954 }
10955
10956 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_TAP_CFG2,
10957 (uint8_t *) &tap_cfg2, 1);
10958 }
10959 }
10960
10961 return ret;
10962 }
10963
10964 /**
10965 * @brief Route interrupt signals on int2 pin.[get]
10966 *
10967 * @param ctx communication interface handler. Use NULL to ignore
10968 * this interface.(ptr)
10969 * @param val the signals that are routed on int2 pin.(ptr)
10970 * @retval interface status (MANDATORY: return 0 -> no Error).
10971 *
10972 */
lsm6dso32x_pin_int2_route_get(stmdev_ctx_t * ctx,lsm6dso32x_pin_int2_route_t * val)10973 int32_t lsm6dso32x_pin_int2_route_get(stmdev_ctx_t *ctx,
10974 lsm6dso32x_pin_int2_route_t *val)
10975 {
10976 lsm6dso32x_emb_func_int2_t emb_func_int2;
10977 lsm6dso32x_fsm_int2_a_t fsm_int2_a;
10978 lsm6dso32x_fsm_int2_b_t fsm_int2_b;
10979 lsm6dso32x_int2_ctrl_t int2_ctrl;
10980 lsm6dso32x_mlc_int2_t mlc_int2;
10981 lsm6dso32x_md2_cfg_t md2_cfg;
10982 lsm6dso32x_ctrl4_c_t ctrl4_c;
10983 int32_t ret;
10984 ret = 0;
10985
10986 if (ctx != NULL)
10987 {
10988 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
10989
10990 if (ret == 0)
10991 {
10992 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MLC_INT2,
10993 (uint8_t *)&mlc_int2, 1);
10994 }
10995
10996 if (ret == 0)
10997 {
10998 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_INT2,
10999 (uint8_t *)&emb_func_int2, 1);
11000 }
11001
11002 if (ret == 0)
11003 {
11004 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_INT2_A,
11005 (uint8_t *)&fsm_int2_a, 1);
11006 }
11007
11008 if (ret == 0)
11009 {
11010 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_INT2_B,
11011 (uint8_t *)&fsm_int2_b, 1);
11012 }
11013
11014 if (ret == 0)
11015 {
11016 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
11017 }
11018
11019 if (ret == 0)
11020 {
11021 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT2_CTRL,
11022 (uint8_t *)&int2_ctrl, 1);
11023 }
11024
11025 if (ret == 0)
11026 {
11027 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MD2_CFG,
11028 (uint8_t *)&md2_cfg, 1);
11029 }
11030
11031 if (ret == 0)
11032 {
11033 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL4_C,
11034 (uint8_t *)&ctrl4_c, 1);
11035 }
11036
11037 if (ctrl4_c.int2_on_int1 == PROPERTY_DISABLE)
11038 {
11039 if (ret == 0)
11040 {
11041 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_INT2_CTRL,
11042 (uint8_t *)&int2_ctrl, 1);
11043 val->drdy_temp = int2_ctrl.int2_drdy_temp;
11044 }
11045
11046 if (ret == 0)
11047 {
11048 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_MD2_CFG,
11049 (uint8_t *)&md2_cfg, 1);
11050 val->timestamp = md2_cfg.int2_timestamp;
11051 }
11052 }
11053
11054 else
11055 {
11056 val->drdy_temp = PROPERTY_DISABLE;
11057 val->timestamp = PROPERTY_DISABLE;
11058 }
11059
11060 val->drdy_xl = int2_ctrl.int2_drdy_xl;
11061 val->drdy_g = int2_ctrl.int2_drdy_g;
11062 val->drdy_temp = int2_ctrl.int2_drdy_temp;
11063 val->fifo_th = int2_ctrl.int2_fifo_th;
11064 val->fifo_ovr = int2_ctrl.int2_fifo_ovr;
11065 val->fifo_full = int2_ctrl.int2_fifo_full;
11066 val->fifo_bdr = int2_ctrl.int2_cnt_bdr;
11067 val->timestamp = md2_cfg.int2_timestamp;
11068 val->six_d = md2_cfg.int2_6d;
11069 val->double_tap = md2_cfg.int2_double_tap;
11070 val->free_fall = md2_cfg.int2_ff;
11071 val->wake_up = md2_cfg.int2_wu;
11072 val->single_tap = md2_cfg.int2_single_tap;
11073 val->sleep_change = md2_cfg.int2_sleep_change;
11074 val->step_detector = emb_func_int2. int2_step_detector;
11075 val->tilt = emb_func_int2.int2_tilt;
11076 val->fsm_lc = emb_func_int2.int2_fsm_lc;
11077 val->fsm1 = fsm_int2_a.int2_fsm1;
11078 val->fsm2 = fsm_int2_a.int2_fsm2;
11079 val->fsm3 = fsm_int2_a.int2_fsm3;
11080 val->fsm4 = fsm_int2_a.int2_fsm4;
11081 val->fsm5 = fsm_int2_a.int2_fsm5;
11082 val->fsm6 = fsm_int2_a.int2_fsm6;
11083 val->fsm7 = fsm_int2_a.int2_fsm7;
11084 val->fsm8 = fsm_int2_a.int2_fsm8;
11085 val->fsm9 = fsm_int2_b.int2_fsm9;
11086 val->fsm10 = fsm_int2_b.int2_fsm10;
11087 val->fsm11 = fsm_int2_b.int2_fsm11;
11088 val->fsm12 = fsm_int2_b.int2_fsm12;
11089 val->fsm13 = fsm_int2_b.int2_fsm13;
11090 val->fsm14 = fsm_int2_b.int2_fsm14;
11091 val->fsm15 = fsm_int2_b.int2_fsm15;
11092 val->fsm16 = fsm_int2_b.int2_fsm16;
11093 val->mlc1 = mlc_int2.int2_mlc1;
11094 val->mlc2 = mlc_int2.int2_mlc2;
11095 val->mlc3 = mlc_int2.int2_mlc3;
11096 val->mlc4 = mlc_int2.int2_mlc4;
11097 val->mlc5 = mlc_int2.int2_mlc5;
11098 val->mlc6 = mlc_int2.int2_mlc6;
11099 val->mlc7 = mlc_int2.int2_mlc7;
11100 val->mlc8 = mlc_int2.int2_mlc8;
11101 }
11102
11103 return ret;
11104 }
11105
11106 /**
11107 * @brief Get the status of all the interrupt sources.[get]
11108 *
11109 * @param ctx communication interface handler.(ptr)
11110 * @param val the status of all the interrupt sources.(ptr)
11111 * @retval interface status (MANDATORY: return 0 -> no Error).
11112 *
11113 */
lsm6dso32x_all_sources_get(stmdev_ctx_t * ctx,lsm6dso32x_all_sources_t * val)11114 int32_t lsm6dso32x_all_sources_get(stmdev_ctx_t *ctx,
11115 lsm6dso32x_all_sources_t *val)
11116 {
11117 lsm6dso32x_emb_func_status_mainpage_t emb_func_status_mainpage;
11118 lsm6dso32x_status_master_mainpage_t status_master_mainpage;
11119 lsm6dso32x_fsm_status_a_mainpage_t fsm_status_a_mainpage;
11120 lsm6dso32x_fsm_status_b_mainpage_t fsm_status_b_mainpage;
11121 lsm6dso32x_mlc_status_mainpage_t mlc_status_mainpage;
11122 lsm6dso32x_fifo_status1_t fifo_status1;
11123 lsm6dso32x_fifo_status2_t fifo_status2;
11124 lsm6dso32x_all_int_src_t all_int_src;
11125 lsm6dso32x_wake_up_src_t wake_up_src;
11126 lsm6dso32x_status_reg_t status_reg;
11127 lsm6dso32x_tap_src_t tap_src;
11128 lsm6dso32x_d6d_src_t d6d_src;
11129 lsm6dso32x_ctrl5_c_t ctrl5_c;
11130 uint8_t reg[12];
11131 int32_t ret;
11132 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL5_C,
11133 (uint8_t *)&ctrl5_c, 1);
11134
11135 if (ret == 0)
11136 {
11137 ctrl5_c.not_used_01 = PROPERTY_ENABLE;
11138 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL5_C,
11139 (uint8_t *)&ctrl5_c, 1);
11140 }
11141
11142 if (ret == 0)
11143 {
11144 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_ALL_INT_SRC, reg, 12);
11145 }
11146
11147 if (ret == 0)
11148 {
11149 bytecpy((uint8_t *)&all_int_src, ®[0]);
11150 bytecpy((uint8_t *)&wake_up_src, ®[1]);
11151 bytecpy((uint8_t *)&tap_src, ®[2]);
11152 bytecpy((uint8_t *)&d6d_src, ®[3]);
11153 bytecpy((uint8_t *)&status_reg, ®[4]);
11154 bytecpy((uint8_t *)&emb_func_status_mainpage, ®[5]);
11155 bytecpy((uint8_t *)&fsm_status_a_mainpage, ®[6]);
11156 bytecpy((uint8_t *)&fsm_status_b_mainpage, ®[7]);
11157 bytecpy((uint8_t *)&mlc_status_mainpage, ®[8]);
11158 bytecpy((uint8_t *)&status_master_mainpage, ®[9]);
11159 bytecpy((uint8_t *)&fifo_status1, ®[10]);
11160 bytecpy((uint8_t *)&fifo_status2, ®[11]);
11161 val->timestamp = all_int_src.timestamp_endcount;
11162 val->wake_up_z = wake_up_src.z_wu;
11163 val->wake_up_y = wake_up_src.y_wu;
11164 val->wake_up_x = wake_up_src.x_wu;
11165 val->wake_up = wake_up_src.wu_ia;
11166 val->sleep_state = wake_up_src.sleep_state;
11167 val->free_fall = wake_up_src.ff_ia;
11168 val->sleep_change = wake_up_src.sleep_change_ia;
11169 val->tap_x = tap_src.x_tap;
11170 val->tap_y = tap_src.y_tap;
11171 val->tap_z = tap_src.z_tap;
11172 val->tap_sign = tap_src.tap_sign;
11173 val->double_tap = tap_src.double_tap;
11174 val->single_tap = tap_src.single_tap;
11175 val->six_d_xl = d6d_src.xl;
11176 val->six_d_xh = d6d_src.xh;
11177 val->six_d_yl = d6d_src.yl;
11178 val->six_d_yh = d6d_src.yh;
11179 val->six_d_zl = d6d_src.zl;
11180 val->six_d_zh = d6d_src.zh;
11181 val->six_d = d6d_src.d6d_ia;
11182 val->den_flag = d6d_src.den_drdy;
11183 val->drdy_xl = status_reg.xlda;
11184 val->drdy_g = status_reg.gda;
11185 val->drdy_temp = status_reg.tda;
11186 val->step_detector = emb_func_status_mainpage.is_step_det;
11187 val->tilt = emb_func_status_mainpage.is_tilt;
11188 val->sig_mot = emb_func_status_mainpage.is_sigmot;
11189 val->fsm_lc = emb_func_status_mainpage.is_fsm_lc;
11190 val->fsm1 = fsm_status_a_mainpage.is_fsm1;
11191 val->fsm2 = fsm_status_a_mainpage.is_fsm2;
11192 val->fsm3 = fsm_status_a_mainpage.is_fsm3;
11193 val->fsm4 = fsm_status_a_mainpage.is_fsm4;
11194 val->fsm5 = fsm_status_a_mainpage.is_fsm5;
11195 val->fsm6 = fsm_status_a_mainpage.is_fsm6;
11196 val->fsm7 = fsm_status_a_mainpage.is_fsm7;
11197 val->fsm8 = fsm_status_a_mainpage.is_fsm8;
11198 val->fsm9 = fsm_status_b_mainpage.is_fsm9;
11199 val->fsm10 = fsm_status_b_mainpage.is_fsm10;
11200 val->fsm11 = fsm_status_b_mainpage.is_fsm11;
11201 val->fsm12 = fsm_status_b_mainpage.is_fsm12;
11202 val->fsm13 = fsm_status_b_mainpage.is_fsm13;
11203 val->fsm14 = fsm_status_b_mainpage.is_fsm14;
11204 val->fsm15 = fsm_status_b_mainpage.is_fsm15;
11205 val->fsm16 = fsm_status_b_mainpage.is_fsm16;
11206 val->mlc1 = mlc_status_mainpage.is_mlc1;
11207 val->mlc2 = mlc_status_mainpage.is_mlc2;
11208 val->mlc3 = mlc_status_mainpage.is_mlc3;
11209 val->mlc4 = mlc_status_mainpage.is_mlc4;
11210 val->mlc5 = mlc_status_mainpage.is_mlc5;
11211 val->mlc6 = mlc_status_mainpage.is_mlc6;
11212 val->mlc7 = mlc_status_mainpage.is_mlc7;
11213 val->mlc8 = mlc_status_mainpage.is_mlc8;
11214 val->sh_endop = status_master_mainpage.sens_hub_endop;
11215 val->sh_slave0_nack = status_master_mainpage.slave0_nack;
11216 val->sh_slave1_nack = status_master_mainpage.slave1_nack;
11217 val->sh_slave2_nack = status_master_mainpage.slave2_nack;
11218 val->sh_slave3_nack = status_master_mainpage.slave3_nack;
11219 val->sh_wr_once = status_master_mainpage.wr_once_done;
11220 val->fifo_diff = (256U * fifo_status2.diff_fifo) +
11221 fifo_status1.diff_fifo;
11222 val->fifo_ovr_latched = fifo_status2.over_run_latched;
11223 val->fifo_bdr = fifo_status2.counter_bdr_ia;
11224 val->fifo_full = fifo_status2.fifo_full_ia;
11225 val->fifo_ovr = fifo_status2.fifo_ovr_ia;
11226 val->fifo_th = fifo_status2.fifo_wtm_ia;
11227 ctrl5_c.not_used_01 = PROPERTY_DISABLE;
11228 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL5_C,
11229 (uint8_t *)&ctrl5_c, 1);
11230 }
11231
11232 return ret;
11233 }
11234
11235 /**
11236 * @brief Sensor conversion parameters selection.[set]
11237 *
11238 * @param ctx communication interface handler. Use NULL to ignore
11239 * this interface.(ptr)
11240 * @param val set the sensor conversion parameters by checking
11241 * the constraints of the device.(ptr)
11242 * @retval interface status (MANDATORY: return 0 -> no Error).
11243 *
11244 */
lsm6dso32x_mode_set(stmdev_ctx_t * ctx,lsm6dso32x_md_t * val)11245 int32_t lsm6dso32x_mode_set(stmdev_ctx_t *ctx,
11246 lsm6dso32x_md_t *val)
11247 {
11248 lsm6dso32x_func_cfg_access_t func_cfg_access;
11249 lsm6dso32x_ctrl1_xl_t ctrl1_xl;
11250 lsm6dso32x_ctrl8_xl_t ctrl8_xl;
11251 lsm6dso32x_ctrl2_g_t ctrl2_g;
11252 lsm6dso32x_ctrl3_c_t ctrl3_c = {0};
11253 lsm6dso32x_ctrl4_c_t ctrl4_c = {0};
11254 lsm6dso32x_ctrl5_c_t ctrl5_c;
11255 lsm6dso32x_ctrl6_c_t ctrl6_c;
11256 lsm6dso32x_ctrl7_g_t ctrl7_g;
11257 uint8_t xl_hm_mode;
11258 uint8_t g_hm_mode;
11259 uint8_t xl_ulp_en;
11260 uint8_t odr_gy;
11261 uint8_t odr_xl;
11262 uint8_t reg[8];
11263 int32_t ret;
11264
11265 ret = 0;
11266 /* FIXME: Remove warnings with STM32CubeIDE */
11267 ctrl3_c.not_used_01 = 0;
11268 ctrl4_c.not_used_01 = 0;
11269 /* reading input configuration */
11270 xl_hm_mode = ((uint8_t)val->ui.xl.odr & 0x10U) >> 4;
11271 xl_ulp_en = ((uint8_t)val->ui.xl.odr & 0x20U) >> 5;
11272 odr_xl = (uint8_t)val->ui.xl.odr & 0x0FU;
11273 g_hm_mode = ((uint8_t)val->ui.gy.odr & 0x10U) >> 4;
11274 odr_gy = (uint8_t)val->ui.gy.odr & 0x0FU;
11275
11276 /* reading registers to be configured */
11277 if (ctx != NULL)
11278 {
11279 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, reg, 8);
11280 bytecpy((uint8_t *)&ctrl1_xl, ®[0]);
11281 bytecpy((uint8_t *)&ctrl2_g, ®[1]);
11282 bytecpy((uint8_t *)&ctrl3_c, ®[2]);
11283 bytecpy((uint8_t *)&ctrl4_c, ®[3]);
11284 bytecpy((uint8_t *)&ctrl5_c, ®[4]);
11285 bytecpy((uint8_t *)&ctrl6_c, ®[5]);
11286 bytecpy((uint8_t *)&ctrl7_g, ®[6]);
11287 bytecpy((uint8_t *)&ctrl8_xl, ®[7]);
11288
11289 if (ret == 0)
11290 {
11291 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FUNC_CFG_ACCESS,
11292 (uint8_t *)&func_cfg_access, 1);
11293 }
11294
11295 /* if toggle xl ultra low power mode, turn off xl before reconfigure */
11296 if (ctrl5_c.xl_ulp_en != xl_ulp_en)
11297 {
11298 ctrl1_xl.odr_xl = (uint8_t) 0x00U;
11299 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL1_XL,
11300 (uint8_t *)&ctrl1_xl, 1);
11301 }
11302 }
11303
11304 /* Check the Finite State Machine data rate constraints */
11305 if (val->fsm.sens != LSM6DSO32X_FSM_DISABLE)
11306 {
11307 switch (val->fsm.odr)
11308 {
11309 case LSM6DSO32X_FSM_12Hz5:
11310 if ((val->fsm.sens != LSM6DSO32X_FSM_GY) && (odr_xl == 0x00U))
11311 {
11312 odr_xl = 0x01U;
11313 }
11314
11315 if ((val->fsm.sens != LSM6DSO32X_FSM_XL) && (odr_gy == 0x00U))
11316 {
11317 xl_ulp_en = PROPERTY_DISABLE;
11318 odr_gy = 0x01U;
11319 }
11320
11321 break;
11322
11323 case LSM6DSO32X_FSM_26Hz:
11324 if ((val->fsm.sens != LSM6DSO32X_FSM_GY) && (odr_xl < 0x02U))
11325 {
11326 odr_xl = 0x02U;
11327 }
11328
11329 if ((val->fsm.sens != LSM6DSO32X_FSM_XL) && (odr_gy < 0x02U))
11330 {
11331 xl_ulp_en = PROPERTY_DISABLE;
11332 odr_gy = 0x02U;
11333 }
11334
11335 break;
11336
11337 case LSM6DSO32X_FSM_52Hz:
11338 if ((val->fsm.sens != LSM6DSO32X_FSM_GY) && (odr_xl < 0x03U))
11339 {
11340 odr_xl = 0x03U;
11341 }
11342
11343 if ((val->fsm.sens != LSM6DSO32X_FSM_XL) && (odr_gy < 0x03U))
11344 {
11345 xl_ulp_en = PROPERTY_DISABLE;
11346 odr_gy = 0x03U;
11347 }
11348
11349 break;
11350
11351 case LSM6DSO32X_FSM_104Hz:
11352 if ((val->fsm.sens != LSM6DSO32X_FSM_GY) && (odr_xl < 0x04U))
11353 {
11354 odr_xl = 0x04U;
11355 }
11356
11357 if ((val->fsm.sens != LSM6DSO32X_FSM_XL) && (odr_gy < 0x04U))
11358 {
11359 xl_ulp_en = PROPERTY_DISABLE;
11360 odr_gy = 0x04U;
11361 }
11362
11363 break;
11364
11365 default:
11366 odr_xl = 0x00U;
11367 odr_gy = 0x00U;
11368 break;
11369 }
11370 }
11371
11372 /* Check the Machine Learning Core data rate constraints */
11373 if (val->mlc.sens != LSM6DSO32X_MLC_DISABLE)
11374 {
11375 switch (val->mlc.odr)
11376 {
11377 case LSM6DSO32X_MLC_12Hz5:
11378 if (odr_xl == 0x00U)
11379 {
11380 odr_xl = 0x01U;
11381 }
11382
11383 if ((val->mlc.sens != LSM6DSO32X_MLC_XL) && (odr_gy == 0x00U))
11384 {
11385 xl_ulp_en = PROPERTY_DISABLE;
11386 odr_gy = 0x01U;
11387 }
11388
11389 break;
11390
11391 case LSM6DSO32X_MLC_26Hz:
11392 if (odr_xl < 0x02U)
11393 {
11394 odr_xl = 0x02U;
11395 }
11396
11397 if ((val->mlc.sens != LSM6DSO32X_MLC_XL) && (odr_gy < 0x02U))
11398 {
11399 xl_ulp_en = PROPERTY_DISABLE;
11400 odr_gy = 0x02U;
11401 }
11402
11403 break;
11404
11405 case LSM6DSO32X_MLC_52Hz:
11406 if (odr_xl < 0x03U)
11407 {
11408 odr_xl = 0x03U;
11409 }
11410
11411 if ((val->mlc.sens != LSM6DSO32X_MLC_XL) && (odr_gy < 0x03U))
11412 {
11413 xl_ulp_en = PROPERTY_DISABLE;
11414 odr_gy = 0x03U;
11415 }
11416
11417 break;
11418
11419 case LSM6DSO32X_MLC_104Hz:
11420 if (odr_xl < 0x04U)
11421 {
11422 odr_xl = 0x04U;
11423 }
11424
11425 if ((val->mlc.sens != LSM6DSO32X_MLC_XL) && (odr_gy < 0x04U))
11426 {
11427 xl_ulp_en = PROPERTY_DISABLE;
11428 odr_gy = 0x04U;
11429 }
11430
11431 break;
11432
11433 default:
11434 odr_xl = 0x00U;
11435 odr_gy = 0x00U;
11436 break;
11437 }
11438 }
11439
11440 /* Updating the accelerometer data rate configuration */
11441 switch ((ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
11442 ctrl1_xl.odr_xl)
11443 {
11444 case LSM6DSO32X_XL_UI_OFF:
11445 val->ui.xl.odr = LSM6DSO32X_XL_UI_OFF;
11446 break;
11447
11448 case LSM6DSO32X_XL_UI_12Hz5_HP:
11449 val->ui.xl.odr = LSM6DSO32X_XL_UI_12Hz5_HP;
11450 break;
11451
11452 case LSM6DSO32X_XL_UI_26Hz_HP:
11453 val->ui.xl.odr = LSM6DSO32X_XL_UI_26Hz_HP;
11454 break;
11455
11456 case LSM6DSO32X_XL_UI_52Hz_HP:
11457 val->ui.xl.odr = LSM6DSO32X_XL_UI_52Hz_HP;
11458 break;
11459
11460 case LSM6DSO32X_XL_UI_104Hz_HP:
11461 val->ui.xl.odr = LSM6DSO32X_XL_UI_104Hz_HP;
11462 break;
11463
11464 case LSM6DSO32X_XL_UI_208Hz_HP:
11465 val->ui.xl.odr = LSM6DSO32X_XL_UI_208Hz_HP;
11466 break;
11467
11468 case LSM6DSO32X_XL_UI_416Hz_HP:
11469 val->ui.xl.odr = LSM6DSO32X_XL_UI_416Hz_HP;
11470 break;
11471
11472 case LSM6DSO32X_XL_UI_833Hz_HP:
11473 val->ui.xl.odr = LSM6DSO32X_XL_UI_833Hz_HP;
11474 break;
11475
11476 case LSM6DSO32X_XL_UI_1667Hz_HP:
11477 val->ui.xl.odr = LSM6DSO32X_XL_UI_1667Hz_HP;
11478 break;
11479
11480 case LSM6DSO32X_XL_UI_3333Hz_HP:
11481 val->ui.xl.odr = LSM6DSO32X_XL_UI_3333Hz_HP;
11482 break;
11483
11484 case LSM6DSO32X_XL_UI_6667Hz_HP:
11485 val->ui.xl.odr = LSM6DSO32X_XL_UI_6667Hz_HP;
11486 break;
11487
11488 case LSM6DSO32X_XL_UI_1Hz6_LP:
11489 val->ui.xl.odr = LSM6DSO32X_XL_UI_1Hz6_LP;
11490 break;
11491
11492 case LSM6DSO32X_XL_UI_12Hz5_LP:
11493 val->ui.xl.odr = LSM6DSO32X_XL_UI_12Hz5_LP;
11494 break;
11495
11496 case LSM6DSO32X_XL_UI_26Hz_LP:
11497 val->ui.xl.odr = LSM6DSO32X_XL_UI_26Hz_LP;
11498 break;
11499
11500 case LSM6DSO32X_XL_UI_52Hz_LP:
11501 val->ui.xl.odr = LSM6DSO32X_XL_UI_52Hz_LP;
11502 break;
11503
11504 case LSM6DSO32X_XL_UI_104Hz_NM:
11505 val->ui.xl.odr = LSM6DSO32X_XL_UI_104Hz_NM;
11506 break;
11507
11508 case LSM6DSO32X_XL_UI_208Hz_NM:
11509 val->ui.xl.odr = LSM6DSO32X_XL_UI_208Hz_NM;
11510 break;
11511
11512 case LSM6DSO32X_XL_UI_1Hz6_ULP:
11513 val->ui.xl.odr = LSM6DSO32X_XL_UI_1Hz6_ULP;
11514 break;
11515
11516 case LSM6DSO32X_XL_UI_12Hz5_ULP:
11517 val->ui.xl.odr = LSM6DSO32X_XL_UI_12Hz5_ULP;
11518 break;
11519
11520 case LSM6DSO32X_XL_UI_26Hz_ULP:
11521 val->ui.xl.odr = LSM6DSO32X_XL_UI_26Hz_ULP;
11522 break;
11523
11524 case LSM6DSO32X_XL_UI_52Hz_ULP:
11525 val->ui.xl.odr = LSM6DSO32X_XL_UI_52Hz_ULP;
11526 break;
11527
11528 case LSM6DSO32X_XL_UI_104Hz_ULP:
11529 val->ui.xl.odr = LSM6DSO32X_XL_UI_104Hz_ULP;
11530 break;
11531
11532 case LSM6DSO32X_XL_UI_208Hz_ULP:
11533 val->ui.xl.odr = LSM6DSO32X_XL_UI_208Hz_ULP;
11534 break;
11535
11536 default:
11537 val->ui.xl.odr = LSM6DSO32X_XL_UI_OFF;
11538 break;
11539 }
11540
11541 /* Updating the accelerometer data rate configuration */
11542 switch ((ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g)
11543 {
11544 case LSM6DSO32X_GY_UI_OFF:
11545 val->ui.gy.odr = LSM6DSO32X_GY_UI_OFF;
11546 break;
11547
11548 case LSM6DSO32X_GY_UI_12Hz5_LP:
11549 val->ui.gy.odr = LSM6DSO32X_GY_UI_12Hz5_LP;
11550 break;
11551
11552 case LSM6DSO32X_GY_UI_12Hz5_HP:
11553 val->ui.gy.odr = LSM6DSO32X_GY_UI_12Hz5_HP;
11554 break;
11555
11556 case LSM6DSO32X_GY_UI_26Hz_LP:
11557 val->ui.gy.odr = LSM6DSO32X_GY_UI_26Hz_LP;
11558 break;
11559
11560 case LSM6DSO32X_GY_UI_26Hz_HP:
11561 val->ui.gy.odr = LSM6DSO32X_GY_UI_26Hz_HP;
11562 break;
11563
11564 case LSM6DSO32X_GY_UI_52Hz_LP:
11565 val->ui.gy.odr = LSM6DSO32X_GY_UI_52Hz_LP;
11566 break;
11567
11568 case LSM6DSO32X_GY_UI_52Hz_HP:
11569 val->ui.gy.odr = LSM6DSO32X_GY_UI_52Hz_HP;
11570 break;
11571
11572 case LSM6DSO32X_GY_UI_104Hz_NM:
11573 val->ui.gy.odr = LSM6DSO32X_GY_UI_104Hz_NM;
11574 break;
11575
11576 case LSM6DSO32X_GY_UI_104Hz_HP:
11577 val->ui.gy.odr = LSM6DSO32X_GY_UI_104Hz_HP;
11578 break;
11579
11580 case LSM6DSO32X_GY_UI_208Hz_NM:
11581 val->ui.gy.odr = LSM6DSO32X_GY_UI_208Hz_NM;
11582 break;
11583
11584 case LSM6DSO32X_GY_UI_208Hz_HP:
11585 val->ui.gy.odr = LSM6DSO32X_GY_UI_208Hz_HP;
11586 break;
11587
11588 case LSM6DSO32X_GY_UI_416Hz_HP:
11589 val->ui.gy.odr = LSM6DSO32X_GY_UI_416Hz_HP;
11590 break;
11591
11592 case LSM6DSO32X_GY_UI_833Hz_HP:
11593 val->ui.gy.odr = LSM6DSO32X_GY_UI_833Hz_HP;
11594 break;
11595
11596 case LSM6DSO32X_GY_UI_1667Hz_HP:
11597 val->ui.gy.odr = LSM6DSO32X_GY_UI_1667Hz_HP;
11598 break;
11599
11600 case LSM6DSO32X_GY_UI_3333Hz_HP:
11601 val->ui.gy.odr = LSM6DSO32X_GY_UI_3333Hz_HP;
11602 break;
11603
11604 case LSM6DSO32X_GY_UI_6667Hz_HP:
11605 val->ui.gy.odr = LSM6DSO32X_GY_UI_6667Hz_HP;
11606 break;
11607
11608 default:
11609 val->ui.gy.odr = LSM6DSO32X_GY_UI_OFF;
11610 break;
11611 }
11612
11613 /* prapare new configuration */
11614 /* UI new configuration */
11615 ctrl1_xl.odr_xl = odr_xl;
11616 ctrl1_xl.fs_xl = (uint8_t)val->ui.xl.fs;
11617 ctrl5_c.xl_ulp_en = xl_ulp_en;
11618 ctrl6_c.xl_hm_mode = xl_hm_mode;
11619 ctrl7_g.g_hm_mode = g_hm_mode;
11620 ctrl2_g.odr_g = odr_gy;
11621 ctrl2_g.fs_g = (uint8_t) val->ui.gy.fs;
11622
11623 /* writing checked configuration */
11624 if (ctx != NULL)
11625 {
11626 bytecpy(®[0], (uint8_t *)&ctrl1_xl);
11627 bytecpy(®[1], (uint8_t *)&ctrl2_g);
11628 bytecpy(®[2], (uint8_t *)&ctrl3_c);
11629 bytecpy(®[3], (uint8_t *)&ctrl4_c);
11630 bytecpy(®[4], (uint8_t *)&ctrl5_c);
11631 bytecpy(®[5], (uint8_t *)&ctrl6_c);
11632 bytecpy(®[6], (uint8_t *)&ctrl7_g);
11633 bytecpy(®[7], (uint8_t *)&ctrl8_xl);
11634
11635 if (ret == 0)
11636 {
11637 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_CTRL1_XL, (uint8_t *)®,
11638 8);
11639 }
11640
11641 if (ret == 0)
11642 {
11643 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_FUNC_CFG_ACCESS,
11644 (uint8_t *)&func_cfg_access, 1);
11645 }
11646 }
11647
11648 return ret;
11649 }
11650
11651 /**
11652 * @brief Sensor conversion parameters selection.[get]
11653 *
11654 * @param ctx communication interface handler. Use NULL to ignore
11655 * this interface.(ptr)
11656 * @param val get the sensor conversion parameters.(ptr)
11657 * @retval interface status (MANDATORY: return 0 -> no Error).
11658 *
11659 */
lsm6dso32x_mode_get(stmdev_ctx_t * ctx,lsm6dso32x_md_t * val)11660 int32_t lsm6dso32x_mode_get(stmdev_ctx_t *ctx,
11661 lsm6dso32x_md_t *val)
11662 {
11663 lsm6dso32x_emb_func_odr_cfg_b_t emb_func_odr_cfg_b;
11664 lsm6dso32x_emb_func_odr_cfg_c_t emb_func_odr_cfg_c;
11665 lsm6dso32x_func_cfg_access_t func_cfg_access;
11666 lsm6dso32x_emb_func_en_b_t emb_func_en_b;
11667 lsm6dso32x_fsm_enable_a_t fsm_enable_a;
11668 lsm6dso32x_fsm_enable_b_t fsm_enable_b;
11669 lsm6dso32x_ctrl1_xl_t ctrl1_xl;
11670 lsm6dso32x_ctrl2_g_t ctrl2_g;
11671 lsm6dso32x_ctrl3_c_t ctrl3_c;
11672 lsm6dso32x_ctrl4_c_t ctrl4_c;
11673 lsm6dso32x_ctrl5_c_t ctrl5_c;
11674 lsm6dso32x_ctrl6_c_t ctrl6_c;
11675 lsm6dso32x_ctrl7_g_t ctrl7_g;
11676 uint8_t reg[8];
11677 int32_t ret;
11678
11679 ret = 0;
11680
11681 /* reading the registers of the device */
11682 if (ctx != NULL)
11683 {
11684 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_CTRL1_XL, reg, 7);
11685 bytecpy((uint8_t *)&ctrl1_xl, ®[0]);
11686 bytecpy((uint8_t *)&ctrl2_g, ®[1]);
11687 bytecpy((uint8_t *)&ctrl3_c, ®[2]);
11688 bytecpy((uint8_t *)&ctrl4_c, ®[3]);
11689 bytecpy((uint8_t *)&ctrl5_c, ®[4]);
11690 bytecpy((uint8_t *)&ctrl6_c, ®[5]);
11691 bytecpy((uint8_t *)&ctrl7_g, ®[6]);
11692
11693 if (ret == 0)
11694 {
11695 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FUNC_CFG_ACCESS,
11696 (uint8_t *)&func_cfg_access, 1);
11697 }
11698
11699 if (ret == 0)
11700 {
11701 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
11702 }
11703
11704 if (ret == 0)
11705 {
11706 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_ODR_CFG_B, reg, 2);
11707 bytecpy((uint8_t *)&emb_func_odr_cfg_b, ®[0]);
11708 bytecpy((uint8_t *)&emb_func_odr_cfg_c, ®[1]);
11709 }
11710
11711 if (ret == 0)
11712 {
11713 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B,
11714 (uint8_t *)&emb_func_en_b, 1);
11715 }
11716
11717 if (ret == 0)
11718 {
11719 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_FSM_ENABLE_A, reg, 2);
11720 bytecpy((uint8_t *)&fsm_enable_a, ®[0]);
11721 bytecpy((uint8_t *)&fsm_enable_b, ®[1]);
11722 }
11723
11724 if (ret == 0)
11725 {
11726 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
11727 }
11728 }
11729
11730 /* fill the input structure */
11731
11732 /* get accelerometer configuration */
11733 switch ((ctrl5_c.xl_ulp_en << 5) | (ctrl6_c.xl_hm_mode << 4) |
11734 ctrl1_xl.odr_xl)
11735 {
11736 case LSM6DSO32X_XL_UI_OFF:
11737 val->ui.xl.odr = LSM6DSO32X_XL_UI_OFF;
11738 break;
11739
11740 case LSM6DSO32X_XL_UI_12Hz5_HP:
11741 val->ui.xl.odr = LSM6DSO32X_XL_UI_12Hz5_HP;
11742 break;
11743
11744 case LSM6DSO32X_XL_UI_26Hz_HP:
11745 val->ui.xl.odr = LSM6DSO32X_XL_UI_26Hz_HP;
11746 break;
11747
11748 case LSM6DSO32X_XL_UI_52Hz_HP:
11749 val->ui.xl.odr = LSM6DSO32X_XL_UI_52Hz_HP;
11750 break;
11751
11752 case LSM6DSO32X_XL_UI_104Hz_HP:
11753 val->ui.xl.odr = LSM6DSO32X_XL_UI_104Hz_HP;
11754 break;
11755
11756 case LSM6DSO32X_XL_UI_208Hz_HP:
11757 val->ui.xl.odr = LSM6DSO32X_XL_UI_208Hz_HP;
11758 break;
11759
11760 case LSM6DSO32X_XL_UI_416Hz_HP:
11761 val->ui.xl.odr = LSM6DSO32X_XL_UI_416Hz_HP;
11762 break;
11763
11764 case LSM6DSO32X_XL_UI_833Hz_HP:
11765 val->ui.xl.odr = LSM6DSO32X_XL_UI_833Hz_HP;
11766 break;
11767
11768 case LSM6DSO32X_XL_UI_1667Hz_HP:
11769 val->ui.xl.odr = LSM6DSO32X_XL_UI_1667Hz_HP;
11770 break;
11771
11772 case LSM6DSO32X_XL_UI_3333Hz_HP:
11773 val->ui.xl.odr = LSM6DSO32X_XL_UI_3333Hz_HP;
11774 break;
11775
11776 case LSM6DSO32X_XL_UI_6667Hz_HP:
11777 val->ui.xl.odr = LSM6DSO32X_XL_UI_6667Hz_HP;
11778 break;
11779
11780 case LSM6DSO32X_XL_UI_1Hz6_LP:
11781 val->ui.xl.odr = LSM6DSO32X_XL_UI_1Hz6_LP;
11782 break;
11783
11784 case LSM6DSO32X_XL_UI_12Hz5_LP:
11785 val->ui.xl.odr = LSM6DSO32X_XL_UI_12Hz5_LP;
11786 break;
11787
11788 case LSM6DSO32X_XL_UI_26Hz_LP:
11789 val->ui.xl.odr = LSM6DSO32X_XL_UI_26Hz_LP;
11790 break;
11791
11792 case LSM6DSO32X_XL_UI_52Hz_LP:
11793 val->ui.xl.odr = LSM6DSO32X_XL_UI_52Hz_LP;
11794 break;
11795
11796 case LSM6DSO32X_XL_UI_104Hz_NM:
11797 val->ui.xl.odr = LSM6DSO32X_XL_UI_104Hz_NM;
11798 break;
11799
11800 case LSM6DSO32X_XL_UI_208Hz_NM:
11801 val->ui.xl.odr = LSM6DSO32X_XL_UI_208Hz_NM;
11802 break;
11803
11804 case LSM6DSO32X_XL_UI_1Hz6_ULP:
11805 val->ui.xl.odr = LSM6DSO32X_XL_UI_1Hz6_ULP;
11806 break;
11807
11808 case LSM6DSO32X_XL_UI_12Hz5_ULP:
11809 val->ui.xl.odr = LSM6DSO32X_XL_UI_12Hz5_ULP;
11810 break;
11811
11812 case LSM6DSO32X_XL_UI_26Hz_ULP:
11813 val->ui.xl.odr = LSM6DSO32X_XL_UI_26Hz_ULP;
11814 break;
11815
11816 case LSM6DSO32X_XL_UI_52Hz_ULP:
11817 val->ui.xl.odr = LSM6DSO32X_XL_UI_52Hz_ULP;
11818 break;
11819
11820 case LSM6DSO32X_XL_UI_104Hz_ULP:
11821 val->ui.xl.odr = LSM6DSO32X_XL_UI_104Hz_ULP;
11822 break;
11823
11824 case LSM6DSO32X_XL_UI_208Hz_ULP:
11825 val->ui.xl.odr = LSM6DSO32X_XL_UI_208Hz_ULP;
11826 break;
11827
11828 default:
11829 val->ui.xl.odr = LSM6DSO32X_XL_UI_OFF;
11830 break;
11831 }
11832
11833 switch (ctrl1_xl.fs_xl)
11834 {
11835 case LSM6DSO32X_XL_UI_32g:
11836 val->ui.xl.fs = LSM6DSO32X_XL_UI_32g;
11837 break;
11838
11839 case LSM6DSO32X_XL_UI_4g:
11840 val->ui.xl.fs = LSM6DSO32X_XL_UI_4g;
11841 break;
11842
11843 case LSM6DSO32X_XL_UI_8g:
11844 val->ui.xl.fs = LSM6DSO32X_XL_UI_8g;
11845 break;
11846
11847 case LSM6DSO32X_XL_UI_16g:
11848 val->ui.xl.fs = LSM6DSO32X_XL_UI_16g;
11849 break;
11850
11851 default:
11852 val->ui.xl.fs = LSM6DSO32X_XL_UI_4g;
11853 break;
11854 }
11855
11856 /* get gyroscope configuration */
11857 switch ((ctrl7_g.g_hm_mode << 4) | ctrl2_g.odr_g)
11858 {
11859 case LSM6DSO32X_GY_UI_OFF:
11860 val->ui.gy.odr = LSM6DSO32X_GY_UI_OFF;
11861 break;
11862
11863 case LSM6DSO32X_GY_UI_12Hz5_LP:
11864 val->ui.gy.odr = LSM6DSO32X_GY_UI_12Hz5_LP;
11865 break;
11866
11867 case LSM6DSO32X_GY_UI_12Hz5_HP:
11868 val->ui.gy.odr = LSM6DSO32X_GY_UI_12Hz5_HP;
11869 break;
11870
11871 case LSM6DSO32X_GY_UI_26Hz_LP:
11872 val->ui.gy.odr = LSM6DSO32X_GY_UI_26Hz_LP;
11873 break;
11874
11875 case LSM6DSO32X_GY_UI_26Hz_HP:
11876 val->ui.gy.odr = LSM6DSO32X_GY_UI_26Hz_HP;
11877 break;
11878
11879 case LSM6DSO32X_GY_UI_52Hz_LP:
11880 val->ui.gy.odr = LSM6DSO32X_GY_UI_52Hz_LP;
11881 break;
11882
11883 case LSM6DSO32X_GY_UI_52Hz_HP:
11884 val->ui.gy.odr = LSM6DSO32X_GY_UI_52Hz_HP;
11885 break;
11886
11887 case LSM6DSO32X_GY_UI_104Hz_NM:
11888 val->ui.gy.odr = LSM6DSO32X_GY_UI_104Hz_NM;
11889 break;
11890
11891 case LSM6DSO32X_GY_UI_104Hz_HP:
11892 val->ui.gy.odr = LSM6DSO32X_GY_UI_104Hz_HP;
11893 break;
11894
11895 case LSM6DSO32X_GY_UI_208Hz_NM:
11896 val->ui.gy.odr = LSM6DSO32X_GY_UI_208Hz_NM;
11897 break;
11898
11899 case LSM6DSO32X_GY_UI_208Hz_HP:
11900 val->ui.gy.odr = LSM6DSO32X_GY_UI_208Hz_HP;
11901 break;
11902
11903 case LSM6DSO32X_GY_UI_416Hz_HP:
11904 val->ui.gy.odr = LSM6DSO32X_GY_UI_416Hz_HP;
11905 break;
11906
11907 case LSM6DSO32X_GY_UI_833Hz_HP:
11908 val->ui.gy.odr = LSM6DSO32X_GY_UI_833Hz_HP;
11909 break;
11910
11911 case LSM6DSO32X_GY_UI_1667Hz_HP:
11912 val->ui.gy.odr = LSM6DSO32X_GY_UI_1667Hz_HP;
11913 break;
11914
11915 case LSM6DSO32X_GY_UI_3333Hz_HP:
11916 val->ui.gy.odr = LSM6DSO32X_GY_UI_3333Hz_HP;
11917 break;
11918
11919 case LSM6DSO32X_GY_UI_6667Hz_HP:
11920 val->ui.gy.odr = LSM6DSO32X_GY_UI_6667Hz_HP;
11921 break;
11922
11923 default:
11924 val->ui.gy.odr = LSM6DSO32X_GY_UI_OFF;
11925 break;
11926 }
11927
11928 switch (ctrl2_g.fs_g)
11929 {
11930 case LSM6DSO32X_GY_UI_125dps:
11931 val->ui.gy.fs = LSM6DSO32X_GY_UI_125dps;
11932 break;
11933
11934 case LSM6DSO32X_GY_UI_250dps:
11935 val->ui.gy.fs = LSM6DSO32X_GY_UI_250dps;
11936 break;
11937
11938 case LSM6DSO32X_GY_UI_500dps:
11939 val->ui.gy.fs = LSM6DSO32X_GY_UI_500dps;
11940 break;
11941
11942 case LSM6DSO32X_GY_UI_1000dps:
11943 val->ui.gy.fs = LSM6DSO32X_GY_UI_1000dps;
11944 break;
11945
11946 case LSM6DSO32X_GY_UI_2000dps:
11947 val->ui.gy.fs = LSM6DSO32X_GY_UI_2000dps;
11948 break;
11949
11950 default:
11951 val->ui.gy.fs = LSM6DSO32X_GY_UI_125dps;
11952 break;
11953 }
11954
11955 /* get finite state machine configuration */
11956 if ((fsm_enable_a.fsm1_en | fsm_enable_a.fsm2_en |
11957 fsm_enable_a.fsm3_en |
11958 fsm_enable_a.fsm4_en | fsm_enable_a.fsm5_en | fsm_enable_a.fsm6_en |
11959 fsm_enable_a.fsm7_en | fsm_enable_a.fsm8_en | fsm_enable_b.fsm9_en |
11960 fsm_enable_b.fsm10_en | fsm_enable_b.fsm11_en |
11961 fsm_enable_b.fsm12_en | fsm_enable_b.fsm13_en |
11962 fsm_enable_b.fsm14_en | fsm_enable_b.fsm15_en |
11963 fsm_enable_b.fsm16_en) == PROPERTY_ENABLE)
11964 {
11965 switch (emb_func_odr_cfg_b.fsm_odr)
11966 {
11967 case LSM6DSO32X_FSM_12Hz5:
11968 val->fsm.odr = LSM6DSO32X_FSM_12Hz5;
11969 break;
11970
11971 case LSM6DSO32X_FSM_26Hz:
11972 val->fsm.odr = LSM6DSO32X_FSM_26Hz;
11973 break;
11974
11975 case LSM6DSO32X_FSM_52Hz:
11976 val->fsm.odr = LSM6DSO32X_FSM_52Hz;
11977 break;
11978
11979 case LSM6DSO32X_FSM_104Hz:
11980 val->fsm.odr = LSM6DSO32X_FSM_104Hz;
11981 break;
11982
11983 default:
11984 val->fsm.odr = LSM6DSO32X_FSM_12Hz5;
11985 break;
11986 }
11987
11988 val->fsm.sens = LSM6DSO32X_FSM_XL_GY;
11989
11990 if (val->ui.gy.odr == LSM6DSO32X_GY_UI_OFF)
11991 {
11992 val->fsm.sens = LSM6DSO32X_FSM_XL;
11993 }
11994
11995 if (val->ui.xl.odr == LSM6DSO32X_XL_UI_OFF)
11996 {
11997 val->fsm.sens = LSM6DSO32X_FSM_GY;
11998 }
11999 }
12000
12001 else
12002 {
12003 val->fsm.sens = LSM6DSO32X_FSM_DISABLE;
12004 }
12005
12006 /* get machine learning core configuration */
12007 if (emb_func_en_b.mlc_en == PROPERTY_ENABLE)
12008 {
12009 switch (emb_func_odr_cfg_c.mlc_odr)
12010 {
12011 case LSM6DSO32X_MLC_12Hz5:
12012 val->mlc.odr = LSM6DSO32X_MLC_12Hz5;
12013 break;
12014
12015 case LSM6DSO32X_MLC_26Hz:
12016 val->mlc.odr = LSM6DSO32X_MLC_26Hz;
12017 break;
12018
12019 case LSM6DSO32X_MLC_52Hz:
12020 val->mlc.odr = LSM6DSO32X_MLC_52Hz;
12021 break;
12022
12023 case LSM6DSO32X_MLC_104Hz:
12024 val->mlc.odr = LSM6DSO32X_MLC_104Hz;
12025 break;
12026
12027 default:
12028 val->mlc.odr = LSM6DSO32X_MLC_12Hz5;
12029 break;
12030 }
12031
12032 val->mlc.sens = LSM6DSO32X_MLC_XL_GY;
12033
12034 if (val->ui.gy.odr == LSM6DSO32X_GY_UI_OFF)
12035 {
12036 val->mlc.sens = LSM6DSO32X_MLC_XL;
12037 }
12038
12039 if (val->ui.xl.odr == LSM6DSO32X_XL_UI_OFF)
12040 {
12041 val->mlc.sens = LSM6DSO32X_MLC_DISABLE;
12042 }
12043 }
12044
12045 else
12046 {
12047 val->mlc.sens = LSM6DSO32X_MLC_DISABLE;
12048 }
12049
12050 return ret;
12051 }
12052
12053 /**
12054 * @brief Read data in engineering unit.[get]
12055 *
12056 * @param ctx communication interface handler.(ptr)
12057 * @param md the sensor conversion parameters.(ptr)
12058 * @retval interface status (MANDATORY: return 0 -> no Error).
12059 *
12060 */
lsm6dso32x_data_get(stmdev_ctx_t * ctx,lsm6dso32x_md_t * md,lsm6dso32x_data_t * data)12061 int32_t lsm6dso32x_data_get(stmdev_ctx_t *ctx,
12062 lsm6dso32x_md_t *md,
12063 lsm6dso32x_data_t *data)
12064 {
12065 uint8_t buff[14];
12066 int32_t ret;
12067
12068 uint8_t i;
12069 uint8_t j;
12070 ret = 0;
12071
12072 /* read data */
12073 if (ctx != NULL)
12074 {
12075 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_OUT_TEMP_L, buff, 14);
12076 }
12077
12078 j = 0;
12079 /* temperature conversion */
12080 data->ui.heat.raw = (int16_t)buff[j + 1U];
12081 data->ui.heat.raw = (((int16_t)data->ui.heat.raw * (int16_t)256) +
12082 (int16_t)buff[j]);
12083 j += 2U;
12084 data->ui.heat.deg_c = lsm6dso32x_from_lsb_to_celsius((
12085 int16_t)data->ui.heat.raw);
12086
12087 /* angular rate conversion */
12088 for (i = 0U; i < 3U; i++)
12089 {
12090 data->ui.gy.raw[i] = (int16_t)buff[j + 1U];
12091 data->ui.gy.raw[i] = (data->ui.gy.raw[i] * 256) + (int16_t) buff[j];
12092 j += 2U;
12093
12094 switch (md->ui.gy.fs)
12095 {
12096 case LSM6DSO32X_GY_UI_250dps:
12097 data->ui.gy.mdps[i] = lsm6dso32x_from_fs250_to_mdps(
12098 data->ui.gy.raw[i]);
12099 break;
12100
12101 case LSM6DSO32X_GY_UI_125dps:
12102 data->ui.gy.mdps[i] = lsm6dso32x_from_fs125_to_mdps(
12103 data->ui.gy.raw[i]);
12104 break;
12105
12106 case LSM6DSO32X_GY_UI_500dps:
12107 data->ui.gy.mdps[i] = lsm6dso32x_from_fs500_to_mdps(
12108 data->ui.gy.raw[i]);
12109 break;
12110
12111 case LSM6DSO32X_GY_UI_1000dps:
12112 data->ui.gy.mdps[i] = lsm6dso32x_from_fs1000_to_mdps(
12113 data->ui.gy.raw[i]);
12114 break;
12115
12116 case LSM6DSO32X_GY_UI_2000dps:
12117 data->ui.gy.mdps[i] = lsm6dso32x_from_fs2000_to_mdps(
12118 data->ui.gy.raw[i]);
12119 break;
12120
12121 default:
12122 data->ui.gy.mdps[i] = 0.0f;
12123 break;
12124 }
12125 }
12126
12127 /* acceleration conversion */
12128 for (i = 0U; i < 3U; i++)
12129 {
12130 data->ui.xl.raw[i] = (int16_t)buff[j + 1U];
12131 data->ui.xl.raw[i] = (data->ui.xl.raw[i] * 256) + (int16_t) buff[j];
12132 j += 2U;
12133
12134 switch (md->ui.xl.fs)
12135 {
12136 case LSM6DSO32X_XL_UI_4g:
12137 data->ui.xl.mg[i] = lsm6dso32x_from_fs4_to_mg(data->ui.xl.raw[i]);
12138 break;
12139
12140 case LSM6DSO32X_XL_UI_32g:
12141 data->ui.xl.mg[i] = lsm6dso32x_from_fs32_to_mg(data->ui.xl.raw[i]);
12142 break;
12143
12144 case LSM6DSO32X_XL_UI_8g:
12145 data->ui.xl.mg[i] = lsm6dso32x_from_fs8_to_mg(data->ui.xl.raw[i]);
12146 break;
12147
12148 case LSM6DSO32X_XL_UI_16g:
12149 data->ui.xl.mg[i] = lsm6dso32x_from_fs16_to_mg(data->ui.xl.raw[i]);
12150 break;
12151
12152 default:
12153 data->ui.xl.mg[i] = 0.0f;
12154 break;
12155 }
12156 }
12157
12158 return ret;
12159 }
12160
12161 /**
12162 * @brief Embedded functions.[set]
12163 *
12164 * @param ctx read / write interface definitions
12165 * @param val change the values of registers
12166 * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
12167 * @retval interface status (MANDATORY: return 0 -> no Error).
12168 *
12169 */
lsm6dso32x_embedded_sens_set(stmdev_ctx_t * ctx,lsm6dso32x_emb_sens_t * val)12170 int32_t lsm6dso32x_embedded_sens_set(stmdev_ctx_t *ctx,
12171 lsm6dso32x_emb_sens_t *val)
12172 {
12173 lsm6dso32x_emb_func_en_a_t emb_func_en_a;
12174 lsm6dso32x_emb_func_en_b_t emb_func_en_b;
12175 int32_t ret;
12176
12177 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
12178
12179 if (ret == 0)
12180 {
12181 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_A,
12182 (uint8_t *)&emb_func_en_a, 1);
12183 }
12184
12185 if (ret == 0)
12186 {
12187 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B,
12188 (uint8_t *)&emb_func_en_b, 1);
12189 emb_func_en_b.mlc_en = val->mlc;
12190 emb_func_en_b.fsm_en = val->fsm;
12191 emb_func_en_a.tilt_en = val->tilt;
12192 emb_func_en_a.pedo_en = val->step;
12193 emb_func_en_a.sign_motion_en = val->sig_mot;
12194 emb_func_en_b.fifo_compr_en = val->fifo_compr;
12195 }
12196
12197 if (ret == 0)
12198 {
12199 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_A,
12200 (uint8_t *)&emb_func_en_a, 1);
12201 }
12202
12203 if (ret == 0)
12204 {
12205 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B,
12206 (uint8_t *)&emb_func_en_b, 1);
12207 }
12208
12209 if (ret == 0)
12210 {
12211 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
12212 }
12213
12214 return ret;
12215 }
12216
12217 /**
12218 * @brief Embedded functions.[get]
12219 *
12220 * @param ctx read / write interface definitions
12221 * @param val get the values of registers
12222 * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
12223 * @retval interface status (MANDATORY: return 0 -> no Error).
12224 *
12225 */
lsm6dso32x_embedded_sens_get(stmdev_ctx_t * ctx,lsm6dso32x_emb_sens_t * emb_sens)12226 int32_t lsm6dso32x_embedded_sens_get(stmdev_ctx_t *ctx,
12227 lsm6dso32x_emb_sens_t *emb_sens)
12228 {
12229 lsm6dso32x_emb_func_en_a_t emb_func_en_a;
12230 lsm6dso32x_emb_func_en_b_t emb_func_en_b;
12231 int32_t ret;
12232
12233 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
12234
12235 if (ret == 0)
12236 {
12237 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_A,
12238 (uint8_t *)&emb_func_en_a, 1);
12239 }
12240
12241 if (ret == 0)
12242 {
12243 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B,
12244 (uint8_t *)&emb_func_en_b, 1);
12245 emb_sens->mlc = emb_func_en_b.mlc_en;
12246 emb_sens->fsm = emb_func_en_b.fsm_en;
12247 emb_sens->tilt = emb_func_en_a.tilt_en;
12248 emb_sens->step = emb_func_en_a.pedo_en;
12249 emb_sens->sig_mot = emb_func_en_a.sign_motion_en;
12250 emb_sens->fifo_compr = emb_func_en_b.fifo_compr_en;
12251 }
12252
12253 if (ret == 0)
12254 {
12255 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
12256 }
12257
12258 return ret;
12259 }
12260
12261 /**
12262 * @brief turn off all embedded functions.[get]
12263 *
12264 * @param ctx read / write interface definitions
12265 * @param val get the values of registers
12266 * EMB_FUNC_EN_A e EMB_FUNC_EN_B.
12267 * @retval interface status (MANDATORY: return 0 -> no Error).
12268 *
12269 */
lsm6dso32x_embedded_sens_off(stmdev_ctx_t * ctx)12270 int32_t lsm6dso32x_embedded_sens_off(stmdev_ctx_t *ctx)
12271 {
12272 lsm6dso32x_emb_func_en_a_t emb_func_en_a;
12273 lsm6dso32x_emb_func_en_b_t emb_func_en_b;
12274 int32_t ret;
12275
12276 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_EMBEDDED_FUNC_BANK);
12277
12278 if (ret == 0)
12279 {
12280 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_A,
12281 (uint8_t *)&emb_func_en_a, 1);
12282 }
12283
12284 if (ret == 0)
12285 {
12286 ret = lsm6dso32x_read_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B,
12287 (uint8_t *)&emb_func_en_b, 1);
12288 emb_func_en_b.mlc_en = PROPERTY_DISABLE;
12289 emb_func_en_b.fsm_en = PROPERTY_DISABLE;
12290 emb_func_en_a.tilt_en = PROPERTY_DISABLE;
12291 emb_func_en_a.pedo_en = PROPERTY_DISABLE;
12292 emb_func_en_a.sign_motion_en = PROPERTY_DISABLE;
12293 emb_func_en_b.fifo_compr_en = PROPERTY_DISABLE;
12294 }
12295
12296 if (ret == 0)
12297 {
12298 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_A,
12299 (uint8_t *)&emb_func_en_a, 1);
12300 }
12301
12302 if (ret == 0)
12303 {
12304 ret = lsm6dso32x_write_reg(ctx, LSM6DSO32X_EMB_FUNC_EN_B,
12305 (uint8_t *)&emb_func_en_b, 1);
12306 }
12307
12308 if (ret == 0)
12309 {
12310 ret = lsm6dso32x_mem_bank_set(ctx, LSM6DSO32X_USER_BANK);
12311 }
12312
12313 return ret;
12314 }
12315
12316 /**
12317 * @}
12318 *
12319 */
12320
12321 /**
12322 * @}
12323 *
12324 */
12325
12326 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
12327
