1 /**
2 ******************************************************************************
3 * @file lsm6dso32_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSO32 driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dso32_reg.h"
21
22 /**
23 * @defgroup LSM6DSO32
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dso32 enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LSM6DSO32_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6dso32_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dso32_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 ret = ctx->read_reg(ctx->handle, reg, data, len);
56
57 return ret;
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx read / write interface definitions(ptr)
64 * @param reg register to write
65 * @param data pointer to data to write in register reg(ptr)
66 * @param len number of consecutive register to write
67 * @retval interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
lsm6dso32_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak lsm6dso32_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
71 uint8_t *data,
72 uint16_t len)
73 {
74 int32_t ret;
75
76 ret = ctx->write_reg(ctx->handle, reg, data, len);
77
78 return ret;
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup LSM6DSO32_Sensitivity
88 * @brief These functions convert raw-data into engineering units.
89 * @{
90 *
91 */
lsm6dso32_from_fs4_to_mg(int16_t lsb)92 float_t lsm6dso32_from_fs4_to_mg(int16_t lsb)
93 {
94 return ((float_t)lsb) * 0.122f;
95 }
96
lsm6dso32_from_fs8_to_mg(int16_t lsb)97 float_t lsm6dso32_from_fs8_to_mg(int16_t lsb)
98 {
99 return ((float_t)lsb) * 0.244f;
100 }
101
lsm6dso32_from_fs16_to_mg(int16_t lsb)102 float_t lsm6dso32_from_fs16_to_mg(int16_t lsb)
103 {
104 return ((float_t)lsb) * 0.488f;
105 }
106
lsm6dso32_from_fs32_to_mg(int16_t lsb)107 float_t lsm6dso32_from_fs32_to_mg(int16_t lsb)
108 {
109 return ((float_t)lsb) * 0.976f;
110 }
111
lsm6dso32_from_fs125_to_mdps(int16_t lsb)112 float_t lsm6dso32_from_fs125_to_mdps(int16_t lsb)
113 {
114 return ((float_t)lsb) * 4.375f;
115 }
116
lsm6dso32_from_fs250_to_mdps(int16_t lsb)117 float_t lsm6dso32_from_fs250_to_mdps(int16_t lsb)
118 {
119 return ((float_t)lsb) * 8.75f;
120 }
121
lsm6dso32_from_fs500_to_mdps(int16_t lsb)122 float_t lsm6dso32_from_fs500_to_mdps(int16_t lsb)
123 {
124 return ((float_t)lsb) * 17.50f;
125 }
126
lsm6dso32_from_fs1000_to_mdps(int16_t lsb)127 float_t lsm6dso32_from_fs1000_to_mdps(int16_t lsb)
128 {
129 return ((float_t)lsb) * 35.0f;
130 }
131
lsm6dso32_from_fs2000_to_mdps(int16_t lsb)132 float_t lsm6dso32_from_fs2000_to_mdps(int16_t lsb)
133 {
134 return ((float_t)lsb) * 70.0f;
135 }
136
lsm6dso32_from_lsb_to_celsius(int16_t lsb)137 float_t lsm6dso32_from_lsb_to_celsius(int16_t lsb)
138 {
139 return (((float_t)lsb / 256.0f) + 25.0f);
140 }
141
lsm6dso32_from_lsb_to_nsec(int16_t lsb)142 float_t lsm6dso32_from_lsb_to_nsec(int16_t lsb)
143 {
144 return ((float_t)lsb * 25000.0f);
145 }
146
147 /**
148 * @}
149 *
150 */
151
152 /**
153 * @defgroup LSM6DSO32_Data_Generation
154 * @brief This section groups all the functions concerning
155 * data generation.
156 *
157 */
158
159 /**
160 * @brief Accelerometer full-scale selection.[set]
161 *
162 * @param ctx read / write interface definitions
163 * @param val change the values of fs_xl in reg CTRL1_XL
164 * @retval interface status (MANDATORY: return 0 -> no Error)
165 *
166 */
lsm6dso32_xl_full_scale_set(stmdev_ctx_t * ctx,lsm6dso32_fs_xl_t val)167 int32_t lsm6dso32_xl_full_scale_set(stmdev_ctx_t *ctx,
168 lsm6dso32_fs_xl_t val)
169 {
170 lsm6dso32_ctrl1_xl_t ctrl1_xl;
171 int32_t ret;
172
173 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL,
174 (uint8_t *)&ctrl1_xl, 1);
175
176 if (ret == 0)
177 {
178 ctrl1_xl.fs_xl = (uint8_t) val & 0x03U;
179 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL1_XL,
180 (uint8_t *)&ctrl1_xl, 1);
181 }
182
183 return ret;
184 }
185
186 /**
187 * @brief Accelerometer full-scale selection.[get]
188 *
189 * @param ctx read / write interface definitions
190 * @param val Get the values of fs_xl in reg CTRL1_XL
191 * @retval interface status (MANDATORY: return 0 -> no Error)
192 *
193 */
lsm6dso32_xl_full_scale_get(stmdev_ctx_t * ctx,lsm6dso32_fs_xl_t * val)194 int32_t lsm6dso32_xl_full_scale_get(stmdev_ctx_t *ctx,
195 lsm6dso32_fs_xl_t *val)
196 {
197 lsm6dso32_ctrl1_xl_t reg;
198 int32_t ret;
199
200 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t *)®, 1);
201
202 switch (reg.fs_xl)
203 {
204 case LSM6DSO32_4g:
205 *val = LSM6DSO32_4g;
206 break;
207
208 case LSM6DSO32_8g:
209 *val = LSM6DSO32_8g;
210 break;
211
212 case LSM6DSO32_16g:
213 *val = LSM6DSO32_16g;
214 break;
215
216 case LSM6DSO32_32g:
217 *val = LSM6DSO32_32g;
218 break;
219
220 default:
221 *val = LSM6DSO32_4g;
222 break;
223 }
224
225 return ret;
226 }
227
228 /**
229 * @brief Accelerometer UI data rate and power mode selection.[set]
230 *
231 * @param ctx read / write interface definitions
232 * @param val Change the data rate and the power mode of
233 * the accelerometer
234 * @retval interface status (MANDATORY: return 0 -> no Error)
235 *
236 */
lsm6dso32_xl_data_rate_set(stmdev_ctx_t * ctx,lsm6dso32_odr_xl_t val)237 int32_t lsm6dso32_xl_data_rate_set(stmdev_ctx_t *ctx,
238 lsm6dso32_odr_xl_t val)
239 {
240 lsm6dso32_ctrl1_xl_t ctrl1_xl;
241 lsm6dso32_ctrl5_c_t ctrl5_c;
242 lsm6dso32_ctrl6_c_t ctrl6_c;
243 lsm6dso32_func_cfg_access_t func_cfg_access;
244 int32_t ret;
245
246 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL,
247 (uint8_t *)&ctrl1_xl, 1);
248
249 if (ret == 0)
250 {
251 ctrl1_xl.odr_xl = (uint8_t) LSM6DSO32_XL_ODR_OFF & 0x0FU;
252 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL1_XL,
253 (uint8_t *)&ctrl1_xl, 1);
254 }
255
256 if (ret == 0)
257 {
258 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS,
259 (uint8_t *)&func_cfg_access, 1);
260 }
261
262 if (ret == 0)
263 {
264 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
265 }
266
267 if (ret == 0)
268 {
269 ctrl5_c.xl_ulp_en = ((uint8_t)val & 0x20U) >> 5;
270 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL5_C,
271 (uint8_t *) &ctrl5_c, 1);
272 }
273
274 if (ret == 0)
275 {
276 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
277 }
278
279 if (ret == 0)
280 {
281 ctrl6_c.xl_hm_mode = ((uint8_t)val & 0x10U) >> 4;
282 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL6_C,
283 (uint8_t *) &ctrl6_c, 1);
284 }
285
286 if (ret == 0)
287 {
288 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL,
289 (uint8_t *)&ctrl1_xl, 1);
290 }
291
292 if (ret == 0)
293 {
294 ctrl1_xl.odr_xl = (uint8_t) val & 0x0FU;
295 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL1_XL,
296 (uint8_t *)&ctrl1_xl, 1);
297 }
298
299 return ret;
300 }
301
302 /**
303 * @brief Accelerometer UI data rate selection.[get]
304 *
305 * @param ctx read / write interface definitions
306 * @param val Get the data rate and the power mode of
307 * the accelerometer
308 * @retval interface status (MANDATORY: return 0 -> no Error)
309 *
310 */
lsm6dso32_xl_data_rate_get(stmdev_ctx_t * ctx,lsm6dso32_odr_xl_t * val)311 int32_t lsm6dso32_xl_data_rate_get(stmdev_ctx_t *ctx,
312 lsm6dso32_odr_xl_t *val)
313 {
314 lsm6dso32_ctrl1_xl_t ctrl1_xl;
315 lsm6dso32_ctrl5_c_t ctrl5_c;
316 lsm6dso32_ctrl6_c_t ctrl6_c;
317 lsm6dso32_func_cfg_access_t func_cfg_access;
318 int32_t ret;
319
320 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL,
321 (uint8_t *)&ctrl1_xl, 1);
322
323 if (ret == 0)
324 {
325 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS,
326 (uint8_t *)&func_cfg_access, 1);
327 }
328
329 if (ret == 0)
330 {
331 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *) &ctrl5_c, 1);
332 }
333
334 if (ret == 0)
335 {
336 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *) &ctrl6_c, 1);
337 }
338
339 switch ((ctrl5_c.xl_ulp_en << 5) + (ctrl6_c.xl_hm_mode << 4) +
340 ctrl1_xl.odr_xl)
341 {
342 case LSM6DSO32_XL_ODR_OFF:
343 *val = LSM6DSO32_XL_ODR_OFF;
344 break;
345
346 case LSM6DSO32_XL_ODR_6Hz5_LOW_PW:
347 *val = LSM6DSO32_XL_ODR_6Hz5_LOW_PW;
348 break;
349
350 case LSM6DSO32_XL_ODR_12Hz5_LOW_PW:
351 *val = LSM6DSO32_XL_ODR_12Hz5_LOW_PW;
352 break;
353
354 case LSM6DSO32_XL_ODR_26Hz_LOW_PW:
355 *val = LSM6DSO32_XL_ODR_26Hz_LOW_PW;
356 break;
357
358 case LSM6DSO32_XL_ODR_52Hz_LOW_PW:
359 *val = LSM6DSO32_XL_ODR_52Hz_LOW_PW;
360 break;
361
362 case LSM6DSO32_XL_ODR_104Hz_NORMAL_MD:
363 *val = LSM6DSO32_XL_ODR_104Hz_NORMAL_MD;
364 break;
365
366 case LSM6DSO32_XL_ODR_208Hz_NORMAL_MD:
367 *val = LSM6DSO32_XL_ODR_208Hz_NORMAL_MD;
368 break;
369
370 case LSM6DSO32_XL_ODR_12Hz5_HIGH_PERF:
371 *val = LSM6DSO32_XL_ODR_12Hz5_HIGH_PERF;
372 break;
373
374 case LSM6DSO32_XL_ODR_26Hz_HIGH_PERF:
375 *val = LSM6DSO32_XL_ODR_26Hz_HIGH_PERF;
376 break;
377
378 case LSM6DSO32_XL_ODR_52Hz_HIGH_PERF:
379 *val = LSM6DSO32_XL_ODR_52Hz_HIGH_PERF;
380 break;
381
382 case LSM6DSO32_XL_ODR_104Hz_HIGH_PERF:
383 *val = LSM6DSO32_XL_ODR_104Hz_HIGH_PERF;
384 break;
385
386 case LSM6DSO32_XL_ODR_208Hz_HIGH_PERF:
387 *val = LSM6DSO32_XL_ODR_208Hz_HIGH_PERF;
388 break;
389
390 case LSM6DSO32_XL_ODR_417Hz_HIGH_PERF:
391 *val = LSM6DSO32_XL_ODR_417Hz_HIGH_PERF;
392 break;
393
394 case LSM6DSO32_XL_ODR_833Hz_HIGH_PERF:
395 *val = LSM6DSO32_XL_ODR_833Hz_HIGH_PERF;
396 break;
397
398 case LSM6DSO32_XL_ODR_1667Hz_HIGH_PERF:
399 *val = LSM6DSO32_XL_ODR_1667Hz_HIGH_PERF;
400 break;
401
402 case LSM6DSO32_XL_ODR_3333Hz_HIGH_PERF:
403 *val = LSM6DSO32_XL_ODR_3333Hz_HIGH_PERF;
404 break;
405
406 case LSM6DSO32_XL_ODR_6667Hz_HIGH_PERF:
407 *val = LSM6DSO32_XL_ODR_6667Hz_HIGH_PERF;
408 break;
409
410 case LSM6DSO32_XL_ODR_6Hz5_ULTRA_LOW_PW:
411 *val = LSM6DSO32_XL_ODR_6Hz5_ULTRA_LOW_PW;
412 break;
413
414 case LSM6DSO32_XL_ODR_12Hz5_ULTRA_LOW_PW:
415 *val = LSM6DSO32_XL_ODR_12Hz5_ULTRA_LOW_PW;
416 break;
417
418 case LSM6DSO32_XL_ODR_26Hz_ULTRA_LOW_PW:
419 *val = LSM6DSO32_XL_ODR_26Hz_ULTRA_LOW_PW;
420 break;
421
422 case LSM6DSO32_XL_ODR_52Hz_ULTRA_LOW_PW:
423 *val = LSM6DSO32_XL_ODR_52Hz_ULTRA_LOW_PW;
424 break;
425
426 case LSM6DSO32_XL_ODR_104Hz_ULTRA_LOW_PW:
427 *val = LSM6DSO32_XL_ODR_104Hz_ULTRA_LOW_PW;
428 break;
429
430 case LSM6DSO32_XL_ODR_208Hz_ULTRA_LOW_PW:
431 *val = LSM6DSO32_XL_ODR_208Hz_ULTRA_LOW_PW;
432 break;
433
434 default:
435 *val = LSM6DSO32_XL_ODR_OFF;
436 break;
437 }
438
439 return ret;
440 }
441
442 /**
443 * @brief Gyroscope UI chain full-scale selection.[set]
444 *
445 * @param ctx read / write interface definitions
446 * @param val change the values of fs_g in reg CTRL2_G
447 * @retval interface status (MANDATORY: return 0 -> no Error)
448 *
449 */
lsm6dso32_gy_full_scale_set(stmdev_ctx_t * ctx,lsm6dso32_fs_g_t val)450 int32_t lsm6dso32_gy_full_scale_set(stmdev_ctx_t *ctx,
451 lsm6dso32_fs_g_t val)
452 {
453 lsm6dso32_ctrl2_g_t reg;
454 int32_t ret;
455
456 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)®, 1);
457
458 if (ret == 0)
459 {
460 reg.fs_g = (uint8_t) val;
461 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)®, 1);
462 }
463
464 return ret;
465 }
466
467 /**
468 * @brief Gyroscope UI chain full-scale selection.[get]
469 *
470 * @param ctx read / write interface definitions
471 * @param val Get the values of fs_g in reg CTRL2_G
472 * @retval interface status (MANDATORY: return 0 -> no Error)
473 *
474 */
lsm6dso32_gy_full_scale_get(stmdev_ctx_t * ctx,lsm6dso32_fs_g_t * val)475 int32_t lsm6dso32_gy_full_scale_get(stmdev_ctx_t *ctx,
476 lsm6dso32_fs_g_t *val)
477 {
478 lsm6dso32_ctrl2_g_t reg;
479 int32_t ret;
480
481 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)®, 1);
482
483 switch (reg.fs_g)
484 {
485 case LSM6DSO32_250dps:
486 *val = LSM6DSO32_250dps;
487 break;
488
489 case LSM6DSO32_125dps:
490 *val = LSM6DSO32_125dps;
491 break;
492
493 case LSM6DSO32_500dps:
494 *val = LSM6DSO32_500dps;
495 break;
496
497 case LSM6DSO32_1000dps:
498 *val = LSM6DSO32_1000dps;
499 break;
500
501 case LSM6DSO32_2000dps:
502 *val = LSM6DSO32_2000dps;
503 break;
504
505 default:
506 *val = LSM6DSO32_250dps;
507 break;
508 }
509
510 return ret;
511 }
512
513 /**
514 * @brief Gyroscope UI data rate selection.[set]
515 *
516 * @param ctx read / write interface definitions
517 * @param val change the values of odr_g in reg CTRL2_G
518 * @retval interface status (MANDATORY: return 0 -> no Error)
519 *
520 */
lsm6dso32_gy_data_rate_set(stmdev_ctx_t * ctx,lsm6dso32_odr_g_t val)521 int32_t lsm6dso32_gy_data_rate_set(stmdev_ctx_t *ctx,
522 lsm6dso32_odr_g_t val)
523 {
524 lsm6dso32_ctrl2_g_t ctrl2_g;
525 lsm6dso32_ctrl7_g_t ctrl7_g;
526 int32_t ret;
527
528 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
529
530 if (ret == 0)
531 {
532 ctrl2_g.odr_g = (uint8_t) LSM6DSO32_GY_ODR_OFF & 0x0FU;
533 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
534 }
535
536 if (ret == 0)
537 {
538 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
539 }
540
541 if (ret == 0)
542 {
543 ctrl7_g.g_hm_mode = ((uint8_t)val & 0x10U) >> 4;
544 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
545 }
546
547 if (ret == 0)
548 {
549 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
550 }
551
552 if (ret == 0)
553 {
554 ctrl2_g.odr_g = (uint8_t)val & 0x0FU;
555 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
556 }
557
558 return ret;
559 }
560
561 /**
562 * @brief Gyroscope UI data rate selection.[get]
563 *
564 * @param ctx read / write interface definitions
565 * @param val Get the values of odr_g in reg CTRL2_G
566 * @retval interface status (MANDATORY: return 0 -> no Error)
567 *
568 */
lsm6dso32_gy_data_rate_get(stmdev_ctx_t * ctx,lsm6dso32_odr_g_t * val)569 int32_t lsm6dso32_gy_data_rate_get(stmdev_ctx_t *ctx,
570 lsm6dso32_odr_g_t *val)
571 {
572 lsm6dso32_ctrl2_g_t ctrl2_g;
573 lsm6dso32_ctrl7_g_t ctrl7_g;
574 int32_t ret;
575
576 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
577
578 if (ret == 0)
579 {
580 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
581 }
582
583 switch ((ctrl7_g.g_hm_mode << 4) + ctrl2_g.odr_g)
584 {
585 case LSM6DSO32_GY_ODR_OFF:
586 *val = LSM6DSO32_GY_ODR_OFF;
587 break;
588
589 case LSM6DSO32_GY_ODR_12Hz5_HIGH_PERF:
590 *val = LSM6DSO32_GY_ODR_12Hz5_HIGH_PERF;
591 break;
592
593 case LSM6DSO32_GY_ODR_26Hz_HIGH_PERF:
594 *val = LSM6DSO32_GY_ODR_26Hz_HIGH_PERF;
595 break;
596
597 case LSM6DSO32_GY_ODR_52Hz_HIGH_PERF:
598 *val = LSM6DSO32_GY_ODR_52Hz_HIGH_PERF;
599 break;
600
601 case LSM6DSO32_GY_ODR_104Hz_HIGH_PERF:
602 *val = LSM6DSO32_GY_ODR_104Hz_HIGH_PERF;
603 break;
604
605 case LSM6DSO32_GY_ODR_208Hz_HIGH_PERF:
606 *val = LSM6DSO32_GY_ODR_208Hz_HIGH_PERF;
607 break;
608
609 case LSM6DSO32_GY_ODR_417Hz_HIGH_PERF:
610 *val = LSM6DSO32_GY_ODR_417Hz_HIGH_PERF;
611 break;
612
613 case LSM6DSO32_GY_ODR_833Hz_HIGH_PERF:
614 *val = LSM6DSO32_GY_ODR_833Hz_HIGH_PERF;
615 break;
616
617 case LSM6DSO32_GY_ODR_1667Hz_HIGH_PERF:
618 *val = LSM6DSO32_GY_ODR_1667Hz_HIGH_PERF;
619 break;
620
621 case LSM6DSO32_GY_ODR_3333Hz_HIGH_PERF:
622 *val = LSM6DSO32_GY_ODR_3333Hz_HIGH_PERF;
623 break;
624
625 case LSM6DSO32_GY_ODR_6667Hz_HIGH_PERF:
626 *val = LSM6DSO32_GY_ODR_6667Hz_HIGH_PERF;
627 break;
628
629 case LSM6DSO32_GY_ODR_104Hz_NORMAL_MD:
630 *val = LSM6DSO32_GY_ODR_104Hz_NORMAL_MD;
631 break;
632
633 case LSM6DSO32_GY_ODR_208Hz_NORMAL_MD:
634 *val = LSM6DSO32_GY_ODR_208Hz_NORMAL_MD;
635 break;
636
637 case LSM6DSO32_GY_ODR_12Hz5_LOW_PW:
638 *val = LSM6DSO32_GY_ODR_12Hz5_LOW_PW;
639 break;
640
641 case LSM6DSO32_GY_ODR_26Hz_LOW_PW:
642 *val = LSM6DSO32_GY_ODR_26Hz_LOW_PW;
643 break;
644
645 case LSM6DSO32_GY_ODR_52Hz_LOW_PW:
646 *val = LSM6DSO32_GY_ODR_52Hz_LOW_PW;
647 break;
648
649 default:
650 *val = LSM6DSO32_GY_ODR_OFF;
651 break;
652 }
653
654 return ret;
655 }
656
657 /**
658 * @brief Block data update.[set]
659 *
660 * @param ctx read / write interface definitions
661 * @param val change the values of bdu in reg CTRL3_C
662 * @retval interface status (MANDATORY: return 0 -> no Error)
663 *
664 */
lsm6dso32_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)665 int32_t lsm6dso32_block_data_update_set(stmdev_ctx_t *ctx,
666 uint8_t val)
667 {
668 lsm6dso32_ctrl3_c_t reg;
669 int32_t ret;
670
671 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
672
673 if (ret == 0)
674 {
675 reg.bdu = val;
676 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
677 }
678
679 return ret;
680 }
681
682 /**
683 * @brief Block data update.[get]
684 *
685 * @param ctx read / write interface definitions
686 * @param val change the values of bdu in reg CTRL3_C
687 * @retval interface status (MANDATORY: return 0 -> no Error)
688 *
689 */
lsm6dso32_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)690 int32_t lsm6dso32_block_data_update_get(stmdev_ctx_t *ctx,
691 uint8_t *val)
692 {
693 lsm6dso32_ctrl3_c_t reg;
694 int32_t ret;
695
696 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
697 *val = reg.bdu;
698
699 return ret;
700 }
701
702 /**
703 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
704 * Y_OFS_USR (74h), Z_OFS_USR (75h).[set]
705 *
706 * @param ctx read / write interface definitions
707 * @param val change the values of usr_off_w in reg CTRL6_C
708 * @retval interface status (MANDATORY: return 0 -> no Error)
709 *
710 */
lsm6dso32_xl_offset_weight_set(stmdev_ctx_t * ctx,lsm6dso32_usr_off_w_t val)711 int32_t lsm6dso32_xl_offset_weight_set(stmdev_ctx_t *ctx,
712 lsm6dso32_usr_off_w_t val)
713 {
714 lsm6dso32_ctrl6_c_t reg;
715 int32_t ret;
716
717 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
718
719 if (ret == 0)
720 {
721 reg.usr_off_w = (uint8_t)val;
722 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
723 }
724
725 return ret;
726 }
727
728 /**
729 * @brief Weight of XL user offset bits of registers X_OFS_USR (73h),
730 * Y_OFS_USR (74h), Z_OFS_USR (75h).[get]
731 *
732 * @param ctx read / write interface definitions
733 * @param val Get the values of usr_off_w in reg CTRL6_C
734 * @retval interface status (MANDATORY: return 0 -> no Error)
735 *
736 */
lsm6dso32_xl_offset_weight_get(stmdev_ctx_t * ctx,lsm6dso32_usr_off_w_t * val)737 int32_t lsm6dso32_xl_offset_weight_get(stmdev_ctx_t *ctx,
738 lsm6dso32_usr_off_w_t *val)
739 {
740 lsm6dso32_ctrl6_c_t reg;
741 int32_t ret;
742
743 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
744
745 switch (reg.usr_off_w)
746 {
747 case LSM6DSO32_LSb_1mg:
748 *val = LSM6DSO32_LSb_1mg;
749 break;
750
751 case LSM6DSO32_LSb_16mg:
752 *val = LSM6DSO32_LSb_16mg;
753 break;
754
755 default:
756 *val = LSM6DSO32_LSb_1mg;
757 break;
758 }
759
760 return ret;
761 }
762
763 /**
764 * @brief Read all the interrupt flag of the device.[get]
765 *
766 * @param ctx read / write interface definitions
767 * @param val registers ALL_INT_SRC; WAKE_UP_SRC;
768 * TAP_SRC; D6D_SRC; STATUS_REG;
769 * EMB_FUNC_STATUS; FSM_STATUS_A/B
770 * @retval interface status (MANDATORY: return 0 -> no Error)
771 *
772 */
lsm6dso32_all_sources_get(stmdev_ctx_t * ctx,lsm6dso32_all_sources_t * val)773 int32_t lsm6dso32_all_sources_get(stmdev_ctx_t *ctx,
774 lsm6dso32_all_sources_t *val)
775 {
776 int32_t ret;
777
778 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_ALL_INT_SRC,
779 (uint8_t *)&val->all_int_src, 1);
780
781 if (ret == 0)
782 {
783 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_SRC,
784 (uint8_t *)&val->wake_up_src, 1);
785 }
786
787 if (ret == 0)
788 {
789 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_SRC,
790 (uint8_t *)&val->tap_src, 1);
791 }
792
793 if (ret == 0)
794 {
795 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_D6D_SRC,
796 (uint8_t *)&val->d6d_src, 1);
797 }
798
799 if (ret == 0)
800 {
801 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG,
802 (uint8_t *)&val->status_reg, 1);
803 }
804
805 if (ret == 0)
806 {
807 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
808 }
809
810 if (ret == 0)
811 {
812 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_STATUS,
813 (uint8_t *)&val->emb_func_status, 1);
814 }
815
816 if (ret == 0)
817 {
818 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_STATUS_A,
819 (uint8_t *)&val->fsm_status_a, 1);
820 }
821
822 if (ret == 0)
823 {
824 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_STATUS_B,
825 (uint8_t *)&val->fsm_status_b, 1);
826 }
827
828 if (ret == 0)
829 {
830 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
831 }
832
833 return ret;
834 }
835
836 /**
837 * @brief The STATUS_REG register is read by the primary interface.[get]
838 *
839 * @param ctx read / write interface definitions
840 * @param val register STATUS_REG
841 * @retval interface status (MANDATORY: return 0 -> no Error)
842 *
843 */
lsm6dso32_status_reg_get(stmdev_ctx_t * ctx,lsm6dso32_status_reg_t * val)844 int32_t lsm6dso32_status_reg_get(stmdev_ctx_t *ctx,
845 lsm6dso32_status_reg_t *val)
846 {
847 int32_t ret;
848
849 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG, (uint8_t *) val, 1);
850
851 return ret;
852 }
853
854 /**
855 * @brief Accelerometer new data available.[get]
856 *
857 * @param ctx read / write interface definitions
858 * @param val change the values of xlda in reg STATUS_REG
859 * @retval interface status (MANDATORY: return 0 -> no Error)
860 *
861 */
lsm6dso32_xl_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)862 int32_t lsm6dso32_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
863 uint8_t *val)
864 {
865 lsm6dso32_status_reg_t reg;
866 int32_t ret;
867
868 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG, (uint8_t *)®, 1);
869 *val = reg.xlda;
870
871 return ret;
872 }
873
874 /**
875 * @brief Gyroscope new data available.[get]
876 *
877 * @param ctx read / write interface definitions
878 * @param val change the values of gda in reg STATUS_REG
879 * @retval interface status (MANDATORY: return 0 -> no Error)
880 *
881 */
lsm6dso32_gy_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)882 int32_t lsm6dso32_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
883 uint8_t *val)
884 {
885 lsm6dso32_status_reg_t reg;
886 int32_t ret;
887
888 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG, (uint8_t *)®, 1);
889 *val = reg.gda;
890
891 return ret;
892 }
893
894 /**
895 * @brief Temperature new data available.[get]
896 *
897 * @param ctx read / write interface definitions
898 * @param val change the values of tda in reg STATUS_REG
899 * @retval interface status (MANDATORY: return 0 -> no Error)
900 *
901 */
lsm6dso32_temp_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)902 int32_t lsm6dso32_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
903 uint8_t *val)
904 {
905 lsm6dso32_status_reg_t reg;
906 int32_t ret;
907
908 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_REG, (uint8_t *)®, 1);
909 *val = reg.tda;
910
911 return ret;
912 }
913
914 /**
915 * @brief Accelerometer X-axis user offset correction expressed in
916 * two’s complement, weight depends on USR_OFF_W in CTRL6_C (15h).
917 * The value must be in the range [-127 127].[set]
918 *
919 * @param ctx read / write interface definitions
920 * @param buff buffer that contains data to write
921 * @retval interface status (MANDATORY: return 0 -> no Error)
922 *
923 */
lsm6dso32_xl_usr_offset_x_set(stmdev_ctx_t * ctx,uint8_t * buff)924 int32_t lsm6dso32_xl_usr_offset_x_set(stmdev_ctx_t *ctx,
925 uint8_t *buff)
926 {
927 int32_t ret;
928
929 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_X_OFS_USR, buff, 1);
930
931 return ret;
932 }
933
934 /**
935 * @brief Accelerometer X-axis user offset correction expressed in two’s
936 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
937 * The value must be in the range [-127 127].[get]
938 *
939 * @param ctx read / write interface definitions
940 * @param buff buffer that stores data read
941 * @retval interface status (MANDATORY: return 0 -> no Error)
942 *
943 */
lsm6dso32_xl_usr_offset_x_get(stmdev_ctx_t * ctx,uint8_t * buff)944 int32_t lsm6dso32_xl_usr_offset_x_get(stmdev_ctx_t *ctx,
945 uint8_t *buff)
946 {
947 int32_t ret;
948
949 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_X_OFS_USR, buff, 1);
950
951 return ret;
952 }
953
954 /**
955 * @brief Accelerometer Y-axis user offset correction expressed in two’s
956 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
957 * The value must be in the range [-127 127].[set]
958 *
959 * @param ctx read / write interface definitions
960 * @param buff buffer that contains data to write
961 * @retval interface status (MANDATORY: return 0 -> no Error)
962 *
963 */
lsm6dso32_xl_usr_offset_y_set(stmdev_ctx_t * ctx,uint8_t * buff)964 int32_t lsm6dso32_xl_usr_offset_y_set(stmdev_ctx_t *ctx,
965 uint8_t *buff)
966 {
967 int32_t ret;
968
969 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_Y_OFS_USR, buff, 1);
970
971 return ret;
972 }
973
974 /**
975 * @brief Accelerometer Y-axis user offset correction expressed in two’s
976 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
977 * The value must be in the range [-127 127].[get]
978 *
979 * @param ctx read / write interface definitions
980 * @param buff buffer that stores data read
981 * @retval interface status (MANDATORY: return 0 -> no Error)
982 *
983 */
lsm6dso32_xl_usr_offset_y_get(stmdev_ctx_t * ctx,uint8_t * buff)984 int32_t lsm6dso32_xl_usr_offset_y_get(stmdev_ctx_t *ctx,
985 uint8_t *buff)
986 {
987 int32_t ret;
988
989 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_Y_OFS_USR, buff, 1);
990
991 return ret;
992 }
993
994 /**
995 * @brief Accelerometer Z-axis user offset correction expressed in two’s
996 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
997 * The value must be in the range [-127 127].[set]
998 *
999 * @param ctx read / write interface definitions
1000 * @param buff buffer that contains data to write
1001 * @retval interface status (MANDATORY: return 0 -> no Error)
1002 *
1003 */
lsm6dso32_xl_usr_offset_z_set(stmdev_ctx_t * ctx,uint8_t * buff)1004 int32_t lsm6dso32_xl_usr_offset_z_set(stmdev_ctx_t *ctx,
1005 uint8_t *buff)
1006 {
1007 int32_t ret;
1008
1009 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_Z_OFS_USR, buff, 1);
1010
1011 return ret;
1012 }
1013
1014 /**
1015 * @brief Accelerometer Z-axis user offset correction expressed in two’s
1016 * complement, weight depends on USR_OFF_W in CTRL6_C (15h).
1017 * The value must be in the range [-127 127].[get]
1018 *
1019 * @param ctx read / write interface definitions
1020 * @param buff buffer that stores data read
1021 * @retval interface status (MANDATORY: return 0 -> no Error)
1022 *
1023 */
lsm6dso32_xl_usr_offset_z_get(stmdev_ctx_t * ctx,uint8_t * buff)1024 int32_t lsm6dso32_xl_usr_offset_z_get(stmdev_ctx_t *ctx,
1025 uint8_t *buff)
1026 {
1027 int32_t ret;
1028
1029 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_Z_OFS_USR, buff, 1);
1030
1031 return ret;
1032 }
1033
1034 /**
1035 * @brief Enables user offset on out.[set]
1036 *
1037 * @param ctx read / write interface definitions
1038 * @param val change the values of usr_off_on_out in reg CTRL7_G
1039 * @retval interface status (MANDATORY: return 0 -> no Error)
1040 *
1041 */
lsm6dso32_xl_usr_offset_set(stmdev_ctx_t * ctx,uint8_t val)1042 int32_t lsm6dso32_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t val)
1043 {
1044 lsm6dso32_ctrl7_g_t reg;
1045 int32_t ret;
1046
1047 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1);
1048
1049 if (ret == 0)
1050 {
1051 reg.usr_off_on_out = val;
1052 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1);
1053 }
1054
1055 return ret;
1056 }
1057
1058 /**
1059 * @brief User offset on out flag.[get]
1060 *
1061 * @param ctx read / write interface definitions
1062 * @param val values of usr_off_on_out in reg CTRL7_G
1063 * @retval interface status (MANDATORY: return 0 -> no Error)
1064 *
1065 */
lsm6dso32_xl_usr_offset_get(stmdev_ctx_t * ctx,uint8_t * val)1066 int32_t lsm6dso32_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *val)
1067 {
1068 lsm6dso32_ctrl7_g_t reg;
1069 int32_t ret;
1070
1071 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1);
1072 *val = reg.usr_off_on_out;
1073
1074 return ret;
1075 }
1076
1077 /**
1078 * @}
1079 *
1080 */
1081
1082 /**
1083 * @defgroup LSM6DSO32_Timestamp
1084 * @brief This section groups all the functions that manage the
1085 * timestamp generation.
1086 * @{
1087 *
1088 */
1089
1090 /**
1091 * @brief Enables timestamp counter.[set]
1092 *
1093 * @param ctx read / write interface definitions
1094 * @param val change the values of timestamp_en in reg CTRL10_C
1095 * @retval interface status (MANDATORY: return 0 -> no Error)
1096 *
1097 */
lsm6dso32_timestamp_set(stmdev_ctx_t * ctx,uint8_t val)1098 int32_t lsm6dso32_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
1099 {
1100 lsm6dso32_ctrl10_c_t reg;
1101 int32_t ret;
1102
1103 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL10_C, (uint8_t *)®, 1);
1104
1105 if (ret == 0)
1106 {
1107 reg.timestamp_en = val;
1108 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL10_C, (uint8_t *)®, 1);
1109 }
1110
1111 return ret;
1112 }
1113
1114 /**
1115 * @brief Enables timestamp counter.[get]
1116 *
1117 * @param ctx read / write interface definitions
1118 * @param val change the values of timestamp_en in reg CTRL10_C
1119 * @retval interface status (MANDATORY: return 0 -> no Error)
1120 *
1121 */
lsm6dso32_timestamp_get(stmdev_ctx_t * ctx,uint8_t * val)1122 int32_t lsm6dso32_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
1123 {
1124 lsm6dso32_ctrl10_c_t reg;
1125 int32_t ret;
1126
1127 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL10_C, (uint8_t *)®, 1);
1128 *val = reg.timestamp_en;
1129
1130 return ret;
1131 }
1132
1133 /**
1134 * @brief Timestamp first data output register (r).
1135 * The value is expressed as a 32-bit word and the bit
1136 * resolution is 25 μs.[get]
1137 *
1138 * @param ctx read / write interface definitions
1139 * @param buff buffer that stores data read
1140 * @retval interface status (MANDATORY: return 0 -> no Error)
1141 *
1142 */
lsm6dso32_timestamp_raw_get(stmdev_ctx_t * ctx,uint32_t * val)1143 int32_t lsm6dso32_timestamp_raw_get(stmdev_ctx_t *ctx, uint32_t *val)
1144 {
1145 uint8_t buff[4];
1146 int32_t ret;
1147
1148 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TIMESTAMP0, buff, 4);
1149 *val = buff[3];
1150 *val = (*val * 256U) + buff[2];
1151 *val = (*val * 256U) + buff[1];
1152 *val = (*val * 256U) + buff[0];
1153
1154 return ret;
1155 }
1156
1157 /**
1158 * @}
1159 *
1160 */
1161
1162 /**
1163 * @defgroup LSM6DSO32_Data output
1164 * @brief This section groups all the data output functions.
1165 * @{
1166 *
1167 */
1168
1169 /**
1170 * @brief Circular burst-mode (rounding) read of the output
1171 * registers.[set]
1172 *
1173 * @param ctx read / write interface definitions
1174 * @param val change the values of rounding in reg CTRL5_C
1175 * @retval interface status (MANDATORY: return 0 -> no Error)
1176 *
1177 */
lsm6dso32_rounding_mode_set(stmdev_ctx_t * ctx,lsm6dso32_rounding_t val)1178 int32_t lsm6dso32_rounding_mode_set(stmdev_ctx_t *ctx,
1179 lsm6dso32_rounding_t val)
1180 {
1181 lsm6dso32_ctrl5_c_t reg;
1182 int32_t ret;
1183
1184 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
1185
1186 if (ret == 0)
1187 {
1188 reg.rounding = (uint8_t)val;
1189 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
1190 }
1191
1192 return ret;
1193 }
1194
1195 /**
1196 * @brief Gyroscope UI chain full-scale selection.[get]
1197 *
1198 * @param ctx read / write interface definitions
1199 * @param val Get the values of rounding in reg CTRL5_C
1200 * @retval interface status (MANDATORY: return 0 -> no Error)
1201 *
1202 */
lsm6dso32_rounding_mode_get(stmdev_ctx_t * ctx,lsm6dso32_rounding_t * val)1203 int32_t lsm6dso32_rounding_mode_get(stmdev_ctx_t *ctx,
1204 lsm6dso32_rounding_t *val)
1205 {
1206 lsm6dso32_ctrl5_c_t reg;
1207 int32_t ret;
1208
1209 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
1210
1211 switch (reg.rounding)
1212 {
1213 case LSM6DSO32_NO_ROUND:
1214 *val = LSM6DSO32_NO_ROUND;
1215 break;
1216
1217 case LSM6DSO32_ROUND_XL:
1218 *val = LSM6DSO32_ROUND_XL;
1219 break;
1220
1221 case LSM6DSO32_ROUND_GY:
1222 *val = LSM6DSO32_ROUND_GY;
1223 break;
1224
1225 case LSM6DSO32_ROUND_GY_XL:
1226 *val = LSM6DSO32_ROUND_GY_XL;
1227 break;
1228
1229 default:
1230 *val = LSM6DSO32_NO_ROUND;
1231 break;
1232 }
1233
1234 return ret;
1235 }
1236
1237 /**
1238 * @brief Temperature data output register (r).
1239 * L and H registers together express a 16-bit word in two’s
1240 * complement.[get]
1241 *
1242 * @param ctx read / write interface definitions
1243 * @param buff buffer that stores data read
1244 * @retval interface status (MANDATORY: return 0 -> no Error)
1245 *
1246 */
lsm6dso32_temperature_raw_get(stmdev_ctx_t * ctx,int16_t * val)1247 int32_t lsm6dso32_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1248 {
1249 uint8_t buff[2];
1250 int32_t ret;
1251
1252 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_OUT_TEMP_L, buff, 2);
1253 val[0] = (int16_t)buff[1];
1254 val[0] = (val[0] * 256) + (int16_t)buff[0];
1255
1256 return ret;
1257 }
1258
1259 /**
1260 * @brief Angular rate sensor. The value is expressed as a 16-bit
1261 * word in two’s complement.[get]
1262 *
1263 * @param ctx read / write interface definitions
1264 * @param buff buffer that stores data read
1265 * @retval interface status (MANDATORY: return 0 -> no Error)
1266 *
1267 */
lsm6dso32_angular_rate_raw_get(stmdev_ctx_t * ctx,int16_t * val)1268 int32_t lsm6dso32_angular_rate_raw_get(stmdev_ctx_t *ctx,
1269 int16_t *val)
1270 {
1271 uint8_t buff[6];
1272 int32_t ret;
1273
1274 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_OUTX_L_G, buff, 6);
1275 val[0] = (int16_t)buff[1];
1276 val[0] = (val[0] * 256) + (int16_t)buff[0];
1277 val[1] = (int16_t)buff[3];
1278 val[1] = (val[1] * 256) + (int16_t)buff[2];
1279 val[2] = (int16_t)buff[5];
1280 val[2] = (val[2] * 256) + (int16_t)buff[4];
1281
1282 return ret;
1283 }
1284
1285 /**
1286 * @brief Linear acceleration output register.
1287 * The value is expressed as a 16-bit word in two’s complement.[get]
1288 *
1289 * @param ctx read / write interface definitions
1290 * @param buff buffer that stores data read
1291 * @retval interface status (MANDATORY: return 0 -> no Error)
1292 *
1293 */
lsm6dso32_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)1294 int32_t lsm6dso32_acceleration_raw_get(stmdev_ctx_t *ctx,
1295 int16_t *val)
1296 {
1297 uint8_t buff[6];
1298 int32_t ret;
1299
1300 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_OUTX_L_A, buff, 6);
1301 val[0] = (int16_t)buff[1];
1302 val[0] = (val[0] * 256) + (int16_t)buff[0];
1303 val[1] = (int16_t)buff[3];
1304 val[1] = (val[1] * 256) + (int16_t)buff[2];
1305 val[2] = (int16_t)buff[5];
1306 val[2] = (val[2] * 256) + (int16_t)buff[4];
1307
1308 return ret;
1309 }
1310
1311 /**
1312 * @brief FIFO data output [get]
1313 *
1314 * @param ctx read / write interface definitions
1315 * @param buff buffer that stores data read
1316 * @retval interface status (MANDATORY: return 0 -> no Error)
1317 *
1318 */
lsm6dso32_fifo_out_raw_get(stmdev_ctx_t * ctx,uint8_t * buff)1319 int32_t lsm6dso32_fifo_out_raw_get(stmdev_ctx_t *ctx, uint8_t *buff)
1320 {
1321 int32_t ret;
1322
1323 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_DATA_OUT_X_L, buff, 6);
1324
1325 return ret;
1326 }
1327
1328 /**
1329 * @brief Step counter output register.[get]
1330 *
1331 * @param ctx read / write interface definitions
1332 * @param buff buffer that stores data read
1333 * @retval interface status (MANDATORY: return 0 -> no Error)
1334 *
1335 */
lsm6dso32_number_of_steps_get(stmdev_ctx_t * ctx,uint16_t * val)1336 int32_t lsm6dso32_number_of_steps_get(stmdev_ctx_t *ctx,
1337 uint16_t *val)
1338 {
1339 uint8_t buff[2];
1340 int32_t ret;
1341
1342 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
1343
1344 if (ret == 0)
1345 {
1346 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STEP_COUNTER_L, buff, 2);
1347 }
1348
1349 if (ret == 0)
1350 {
1351 *val = buff[1];
1352 *val = (*val * 256U) + buff[0];
1353 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
1354 }
1355
1356 return ret;
1357 }
1358
1359 /**
1360 * @brief Reset step counter register.[get]
1361 *
1362 * @param ctx read / write interface definitions
1363 * @retval interface status (MANDATORY: return 0 -> no Error)
1364 *
1365 */
lsm6dso32_steps_reset(stmdev_ctx_t * ctx)1366 int32_t lsm6dso32_steps_reset(stmdev_ctx_t *ctx)
1367 {
1368 lsm6dso32_emb_func_src_t reg;
1369 int32_t ret;
1370
1371 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
1372
1373 if (ret == 0)
1374 {
1375 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_SRC, (uint8_t *)®, 1);
1376 }
1377
1378 if (ret == 0)
1379 {
1380 reg.pedo_rst_step = PROPERTY_ENABLE;
1381 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_SRC,
1382 (uint8_t *)®, 1);
1383 }
1384
1385 if (ret == 0)
1386 {
1387 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
1388 }
1389
1390 return ret;
1391 }
1392
1393 /**
1394 * @}
1395 *
1396 */
1397
1398 /**
1399 * @defgroup LSM6DSO32_common
1400 * @brief This section groups common useful functions.
1401 * @{
1402 *
1403 */
1404
1405 /**
1406 * @brief Difference in percentage of the effective ODR(and timestamp rate)
1407 * with respect to the typical.
1408 * Step: 0.15%. 8-bit format, 2's complement.[set]
1409 *
1410 * @param ctx read / write interface definitions
1411 * @param val change the values of freq_fine in reg
1412 * INTERNAL_FREQ_FINE
1413 * @retval interface status (MANDATORY: return 0 -> no Error)
1414 *
1415 */
lsm6dso32_odr_cal_reg_set(stmdev_ctx_t * ctx,uint8_t val)1416 int32_t lsm6dso32_odr_cal_reg_set(stmdev_ctx_t *ctx, uint8_t val)
1417 {
1418 lsm6dso32_internal_freq_fine_t reg;
1419 int32_t ret;
1420
1421 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INTERNAL_FREQ_FINE,
1422 (uint8_t *)®, 1);
1423
1424 if (ret == 0)
1425 {
1426 reg.freq_fine = val;
1427 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INTERNAL_FREQ_FINE,
1428 (uint8_t *)®, 1);
1429 }
1430
1431 return ret;
1432 }
1433
1434 /**
1435 * @brief Difference in percentage of the effective ODR(and timestamp rate)
1436 * with respect to the typical.
1437 * Step: 0.15%. 8-bit format, 2's complement.[get]
1438 *
1439 * @param ctx read / write interface definitions
1440 * @param val change the values of freq_fine in reg INTERNAL_FREQ_FINE
1441 * @retval interface status (MANDATORY: return 0 -> no Error)
1442 *
1443 */
lsm6dso32_odr_cal_reg_get(stmdev_ctx_t * ctx,uint8_t * val)1444 int32_t lsm6dso32_odr_cal_reg_get(stmdev_ctx_t *ctx, uint8_t *val)
1445 {
1446 lsm6dso32_internal_freq_fine_t reg;
1447 int32_t ret;
1448
1449 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INTERNAL_FREQ_FINE,
1450 (uint8_t *)®, 1);
1451 *val = reg.freq_fine;
1452
1453 return ret;
1454 }
1455
1456
1457 /**
1458 * @brief Enable access to the embedded functions/sensor
1459 * hub configuration registers.[set]
1460 *
1461 * @param ctx read / write interface definitions
1462 * @param val change the values of reg_access in reg FUNC_CFG_ACCESS
1463 * @retval interface status (MANDATORY: return 0 -> no Error)
1464 *
1465 */
lsm6dso32_mem_bank_set(stmdev_ctx_t * ctx,lsm6dso32_reg_access_t val)1466 int32_t lsm6dso32_mem_bank_set(stmdev_ctx_t *ctx,
1467 lsm6dso32_reg_access_t val)
1468 {
1469 lsm6dso32_func_cfg_access_t reg;
1470 int32_t ret;
1471
1472 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS,
1473 (uint8_t *)®, 1);
1474
1475 if (ret == 0)
1476 {
1477 reg.reg_access = (uint8_t)val;
1478 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS,
1479 (uint8_t *)®, 1);
1480 }
1481
1482 return ret;
1483 }
1484
1485 /**
1486 * @brief Enable access to the embedded functions/sensor
1487 * hub configuration registers.[get]
1488 *
1489 * @param ctx read / write interface definitions
1490 * @param val Get the values of reg_access in reg FUNC_CFG_ACCESS
1491 * @retval interface status (MANDATORY: return 0 -> no Error)
1492 *
1493 */
lsm6dso32_mem_bank_get(stmdev_ctx_t * ctx,lsm6dso32_reg_access_t * val)1494 int32_t lsm6dso32_mem_bank_get(stmdev_ctx_t *ctx,
1495 lsm6dso32_reg_access_t *val)
1496 {
1497 lsm6dso32_func_cfg_access_t reg;
1498 int32_t ret;
1499
1500 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FUNC_CFG_ACCESS,
1501 (uint8_t *)®, 1);
1502
1503 switch (reg.reg_access)
1504 {
1505 case LSM6DSO32_USER_BANK:
1506 *val = LSM6DSO32_USER_BANK;
1507 break;
1508
1509 case LSM6DSO32_SENSOR_HUB_BANK:
1510 *val = LSM6DSO32_SENSOR_HUB_BANK;
1511 break;
1512
1513 case LSM6DSO32_EMBEDDED_FUNC_BANK:
1514 *val = LSM6DSO32_EMBEDDED_FUNC_BANK;
1515 break;
1516
1517 default:
1518 *val = LSM6DSO32_USER_BANK;
1519 break;
1520 }
1521
1522 return ret;
1523 }
1524
1525 /**
1526 * @brief Write a line(byte) in a page.[set]
1527 *
1528 * @param ctx read / write interface definitions
1529 * @param uint8_t address: page line address
1530 * @param val value to write
1531 * @retval interface status (MANDATORY: return 0 -> no Error)
1532 *
1533 */
lsm6dso32_ln_pg_write_byte(stmdev_ctx_t * ctx,uint16_t address,uint8_t * val)1534 int32_t lsm6dso32_ln_pg_write_byte(stmdev_ctx_t *ctx,
1535 uint16_t address,
1536 uint8_t *val)
1537 {
1538 lsm6dso32_page_rw_t page_rw;
1539 lsm6dso32_page_sel_t page_sel;
1540 lsm6dso32_page_address_t page_address;
1541 int32_t ret;
1542
1543 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
1544
1545 if (ret == 0)
1546 {
1547 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
1548 }
1549
1550 if (ret == 0)
1551 {
1552 page_rw.page_rw = 0x02; /* page_write enable */
1553 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW,
1554 (uint8_t *) &page_rw, 1);
1555 }
1556
1557 if (ret == 0)
1558 {
1559 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL,
1560 (uint8_t *) &page_sel, 1);
1561 }
1562
1563 if (ret == 0)
1564 {
1565 page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
1566 page_sel.not_used_01 = 1;
1567 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL,
1568 (uint8_t *) &page_sel, 1);
1569 }
1570
1571 if (ret == 0)
1572 {
1573 page_address.page_addr = (uint8_t)address & 0xFFU;
1574 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_ADDRESS,
1575 (uint8_t *)&page_address, 1);
1576 }
1577
1578 if (ret == 0)
1579 {
1580 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_VALUE, val, 1);
1581 }
1582
1583 if (ret == 0)
1584 {
1585 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
1586 }
1587
1588 if (ret == 0)
1589 {
1590 page_rw.page_rw = 0x00; /* page_write disable */
1591 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW,
1592 (uint8_t *) &page_rw, 1);
1593 }
1594
1595 if (ret == 0)
1596 {
1597 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
1598 }
1599
1600 return ret;
1601 }
1602
1603 /**
1604 * @brief Write buffer in a page.[set]
1605 *
1606 * @param ctx read / write interface definitions
1607 * @param uint8_t address: page line address
1608 * @param uint8_t *buf: buffer to write
1609 * @param uint8_t len: buffer len
1610 * @retval interface status (MANDATORY: return 0 -> no Error)
1611 *
1612 */
lsm6dso32_ln_pg_write(stmdev_ctx_t * ctx,uint16_t address,uint8_t * buf,uint8_t len)1613 int32_t lsm6dso32_ln_pg_write(stmdev_ctx_t *ctx, uint16_t address,
1614 uint8_t *buf, uint8_t len)
1615 {
1616 lsm6dso32_page_rw_t page_rw;
1617 lsm6dso32_page_sel_t page_sel;
1618 lsm6dso32_page_address_t page_address;
1619 int32_t ret;
1620
1621 uint8_t msb, lsb;
1622 uint8_t i ;
1623 msb = ((uint8_t)(address >> 8) & 0x0FU);
1624 lsb = (uint8_t)address & 0xFFU;
1625 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
1626
1627 if (ret == 0)
1628 {
1629 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
1630 }
1631
1632 if (ret == 0)
1633 {
1634 page_rw.page_rw = 0x02; /* page_write enable*/
1635 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW,
1636 (uint8_t *) &page_rw, 1);
1637 }
1638
1639 if (ret == 0)
1640 {
1641 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL,
1642 (uint8_t *) &page_sel, 1);
1643 }
1644
1645 if (ret == 0)
1646 {
1647 page_sel.page_sel = msb;
1648 page_sel.not_used_01 = 1;
1649 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL,
1650 (uint8_t *) &page_sel, 1);
1651 }
1652
1653 if (ret == 0)
1654 {
1655 page_address.page_addr = lsb;
1656 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_ADDRESS,
1657 (uint8_t *)&page_address, 1);
1658 }
1659
1660 if (ret == 0)
1661 {
1662 for (i = 0; ((i < len) && (ret == 0)); i++)
1663 {
1664 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_VALUE, &buf[i], 1);
1665
1666 /* Check if page wrap */
1667 if ((lsb == 0x00U) && (ret == 0))
1668 {
1669 lsb++;
1670 msb++;
1671 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL,
1672 (uint8_t *)&page_sel, 1);
1673
1674 if (ret == 0)
1675 {
1676 page_sel.page_sel = msb;
1677 page_sel.not_used_01 = 1;
1678 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL,
1679 (uint8_t *)&page_sel, 1);
1680 }
1681 }
1682 }
1683
1684 page_sel.page_sel = 0;
1685 page_sel.not_used_01 = 1;
1686 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL,
1687 (uint8_t *) &page_sel, 1);
1688 }
1689
1690 if (ret == 0)
1691 {
1692 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
1693 }
1694
1695 if (ret == 0)
1696 {
1697 page_rw.page_rw = 0x00; /* page_write disable */
1698 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW,
1699 (uint8_t *) &page_rw, 1);
1700 }
1701
1702 if (ret == 0)
1703 {
1704 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
1705 }
1706
1707 return ret;
1708 }
1709
1710 /**
1711 * @brief Read a line(byte) in a page.[get]
1712 *
1713 * @param ctx read / write interface definitions
1714 * @param uint8_t address: page line address
1715 * @param val read value
1716 * @retval interface status (MANDATORY: return 0 -> no Error)
1717 *
1718 */
lsm6dso32_ln_pg_read_byte(stmdev_ctx_t * ctx,uint16_t address,uint8_t * val)1719 int32_t lsm6dso32_ln_pg_read_byte(stmdev_ctx_t *ctx, uint16_t address,
1720 uint8_t *val)
1721 {
1722 lsm6dso32_page_rw_t page_rw;
1723 lsm6dso32_page_sel_t page_sel;
1724 lsm6dso32_page_address_t page_address;
1725 int32_t ret;
1726
1727 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
1728
1729 if (ret == 0)
1730 {
1731 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
1732 }
1733
1734 if (ret == 0)
1735 {
1736 page_rw.page_rw = 0x01; /* page_read enable*/
1737 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW,
1738 (uint8_t *) &page_rw, 1);
1739 }
1740
1741 if (ret == 0)
1742 {
1743 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_SEL,
1744 (uint8_t *) &page_sel, 1);
1745 }
1746
1747 if (ret == 0)
1748 {
1749 page_sel.page_sel = ((uint8_t)(address >> 8) & 0x0FU);
1750 page_sel.not_used_01 = 1;
1751 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_SEL,
1752 (uint8_t *) &page_sel, 1);
1753 }
1754
1755 if (ret == 0)
1756 {
1757 page_address.page_addr = (uint8_t)address & 0x00FFU;
1758 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_ADDRESS,
1759 (uint8_t *)&page_address, 1);
1760 }
1761
1762 if (ret == 0)
1763 {
1764 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_VALUE, val, 2);
1765 }
1766
1767 if (ret == 0)
1768 {
1769 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
1770 }
1771
1772 if (ret == 0)
1773 {
1774 page_rw.page_rw = 0x00; /* page_read disable */
1775 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW,
1776 (uint8_t *) &page_rw, 1);
1777 }
1778
1779 if (ret == 0)
1780 {
1781 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
1782 }
1783
1784 return ret;
1785 }
1786
1787 /**
1788 * @brief Data-ready pulsed / letched mode.[set]
1789 *
1790 * @param ctx read / write interface definitions
1791 * @param val change the values of dataready_pulsed in
1792 * reg COUNTER_BDR_REG1
1793 * @retval interface status (MANDATORY: return 0 -> no Error)
1794 *
1795 */
lsm6dso32_data_ready_mode_set(stmdev_ctx_t * ctx,lsm6dso32_dataready_pulsed_t val)1796 int32_t lsm6dso32_data_ready_mode_set(stmdev_ctx_t *ctx,
1797 lsm6dso32_dataready_pulsed_t val)
1798 {
1799 lsm6dso32_counter_bdr_reg1_t reg;
1800 int32_t ret;
1801
1802 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
1803 (uint8_t *)®, 1);
1804
1805 if (ret == 0)
1806 {
1807 reg.dataready_pulsed = (uint8_t)val;
1808 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
1809 (uint8_t *)®, 1);
1810 }
1811
1812 return ret;
1813 }
1814
1815 /**
1816 * @brief Data-ready pulsed / letched mode.[get]
1817 *
1818 * @param ctx read / write interface definitions
1819 * @param val Get the values of
1820 * dataready_pulsed in
1821 * reg COUNTER_BDR_REG1
1822 * @retval interface status (MANDATORY: return 0 -> no Error)
1823 *
1824 */
lsm6dso32_data_ready_mode_get(stmdev_ctx_t * ctx,lsm6dso32_dataready_pulsed_t * val)1825 int32_t lsm6dso32_data_ready_mode_get(stmdev_ctx_t *ctx,
1826 lsm6dso32_dataready_pulsed_t *val)
1827 {
1828 lsm6dso32_counter_bdr_reg1_t reg;
1829 int32_t ret;
1830
1831 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
1832 (uint8_t *)®, 1);
1833
1834 switch (reg.dataready_pulsed)
1835 {
1836 case LSM6DSO32_DRDY_LATCHED:
1837 *val = LSM6DSO32_DRDY_LATCHED;
1838 break;
1839
1840 case LSM6DSO32_DRDY_PULSED:
1841 *val = LSM6DSO32_DRDY_PULSED;
1842 break;
1843
1844 default:
1845 *val = LSM6DSO32_DRDY_LATCHED;
1846 break;
1847 }
1848
1849 return ret;
1850 }
1851
1852 /**
1853 * @brief Device "Who am I".[get]
1854 *
1855 * @param ctx read / write interface definitions
1856 * @param buff buffer that stores data read
1857 * @retval interface status (MANDATORY: return 0 -> no Error)
1858 *
1859 */
lsm6dso32_device_id_get(stmdev_ctx_t * ctx,uint8_t * buff)1860 int32_t lsm6dso32_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
1861 {
1862 int32_t ret;
1863
1864 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WHO_AM_I, buff, 1);
1865
1866 return ret;
1867 }
1868
1869 /**
1870 * @brief Software reset. Restore the default values
1871 * in user registers[set]
1872 *
1873 * @param ctx read / write interface definitions
1874 * @param val change the values of sw_reset in reg CTRL3_C
1875 * @retval interface status (MANDATORY: return 0 -> no Error)
1876 *
1877 */
lsm6dso32_reset_set(stmdev_ctx_t * ctx,uint8_t val)1878 int32_t lsm6dso32_reset_set(stmdev_ctx_t *ctx, uint8_t val)
1879 {
1880 lsm6dso32_ctrl3_c_t reg;
1881 int32_t ret;
1882
1883 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
1884
1885 if (ret == 0)
1886 {
1887 reg.sw_reset = val;
1888 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
1889 }
1890
1891 return ret;
1892 }
1893
1894 /**
1895 * @brief Software reset. Restore the default values in user registers.[get]
1896 *
1897 * @param ctx read / write interface definitions
1898 * @param val change the values of sw_reset in reg CTRL3_C
1899 * @retval interface status (MANDATORY: return 0 -> no Error)
1900 *
1901 */
lsm6dso32_reset_get(stmdev_ctx_t * ctx,uint8_t * val)1902 int32_t lsm6dso32_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
1903 {
1904 lsm6dso32_ctrl3_c_t reg;
1905 int32_t ret;
1906
1907 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
1908 *val = reg.sw_reset;
1909
1910 return ret;
1911 }
1912
1913 /**
1914 * @brief Register address automatically incremented during a multiple byte
1915 * access with a serial interface.[set]
1916 *
1917 * @param ctx read / write interface definitions
1918 * @param val change the values of if_inc in reg CTRL3_C
1919 * @retval interface status (MANDATORY: return 0 -> no Error)
1920 *
1921 */
lsm6dso32_auto_increment_set(stmdev_ctx_t * ctx,uint8_t val)1922 int32_t lsm6dso32_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
1923 {
1924 lsm6dso32_ctrl3_c_t reg;
1925 int32_t ret;
1926
1927 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
1928
1929 if (ret == 0)
1930 {
1931 reg.if_inc = val;
1932 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
1933 }
1934
1935 return ret;
1936 }
1937
1938 /**
1939 * @brief Register address automatically incremented during a multiple byte
1940 * access with a serial interface.[get]
1941 *
1942 * @param ctx read / write interface definitions
1943 * @param val change the values of if_inc in reg CTRL3_C
1944 * @retval interface status (MANDATORY: return 0 -> no Error)
1945 *
1946 */
lsm6dso32_auto_increment_get(stmdev_ctx_t * ctx,uint8_t * val)1947 int32_t lsm6dso32_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
1948 {
1949 lsm6dso32_ctrl3_c_t reg;
1950 int32_t ret;
1951
1952 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
1953 *val = reg.if_inc;
1954
1955 return ret;
1956 }
1957
1958 /**
1959 * @brief Reboot memory content. Reload the calibration parameters.[set]
1960 *
1961 * @param ctx read / write interface definitions
1962 * @param val change the values of boot in reg CTRL3_C
1963 * @retval interface status (MANDATORY: return 0 -> no Error)
1964 *
1965 */
lsm6dso32_boot_set(stmdev_ctx_t * ctx,uint8_t val)1966 int32_t lsm6dso32_boot_set(stmdev_ctx_t *ctx, uint8_t val)
1967 {
1968 lsm6dso32_ctrl3_c_t reg;
1969 int32_t ret;
1970
1971 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
1972
1973 if (ret == 0)
1974 {
1975 reg.boot = val;
1976 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
1977 }
1978
1979 return ret;
1980 }
1981
1982 /**
1983 * @brief Reboot memory content. Reload the calibration parameters.[get]
1984 *
1985 * @param ctx read / write interface definitions
1986 * @param val change the values of boot in reg CTRL3_C
1987 * @retval interface status (MANDATORY: return 0 -> no Error)
1988 *
1989 */
lsm6dso32_boot_get(stmdev_ctx_t * ctx,uint8_t * val)1990 int32_t lsm6dso32_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
1991 {
1992 lsm6dso32_ctrl3_c_t reg;
1993 int32_t ret;
1994
1995 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
1996 *val = reg.boot;
1997
1998 return ret;
1999 }
2000
2001 /**
2002 * @brief Linear acceleration sensor self-test enable.[set]
2003 *
2004 * @param ctx read / write interface definitions
2005 * @param val change the values of st_xl in reg CTRL5_C
2006 * @retval interface status (MANDATORY: return 0 -> no Error)
2007 *
2008 */
lsm6dso32_xl_self_test_set(stmdev_ctx_t * ctx,lsm6dso32_st_xl_t val)2009 int32_t lsm6dso32_xl_self_test_set(stmdev_ctx_t *ctx,
2010 lsm6dso32_st_xl_t val)
2011 {
2012 lsm6dso32_ctrl5_c_t reg;
2013 int32_t ret;
2014
2015 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
2016
2017 if (ret == 0)
2018 {
2019 reg.st_xl = (uint8_t)val;
2020 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
2021 }
2022
2023 return ret;
2024 }
2025
2026 /**
2027 * @brief Linear acceleration sensor self-test enable.[get]
2028 *
2029 * @param ctx read / write interface definitions
2030 * @param val Get the values of st_xl in reg CTRL5_C
2031 * @retval interface status (MANDATORY: return 0 -> no Error)
2032 *
2033 */
lsm6dso32_xl_self_test_get(stmdev_ctx_t * ctx,lsm6dso32_st_xl_t * val)2034 int32_t lsm6dso32_xl_self_test_get(stmdev_ctx_t *ctx,
2035 lsm6dso32_st_xl_t *val)
2036 {
2037 lsm6dso32_ctrl5_c_t reg;
2038 int32_t ret;
2039
2040 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
2041
2042 switch (reg.st_xl)
2043 {
2044 case LSM6DSO32_XL_ST_DISABLE:
2045 *val = LSM6DSO32_XL_ST_DISABLE;
2046 break;
2047
2048 case LSM6DSO32_XL_ST_POSITIVE:
2049 *val = LSM6DSO32_XL_ST_POSITIVE;
2050 break;
2051
2052 case LSM6DSO32_XL_ST_NEGATIVE:
2053 *val = LSM6DSO32_XL_ST_NEGATIVE;
2054 break;
2055
2056 default:
2057 *val = LSM6DSO32_XL_ST_DISABLE;
2058 break;
2059 }
2060
2061 return ret;
2062 }
2063
2064 /**
2065 * @brief Angular rate sensor self-test enable.[set]
2066 *
2067 * @param ctx read / write interface definitions
2068 * @param val change the values of st_g in reg CTRL5_C
2069 * @retval interface status (MANDATORY: return 0 -> no Error)
2070 *
2071 */
lsm6dso32_gy_self_test_set(stmdev_ctx_t * ctx,lsm6dso32_st_g_t val)2072 int32_t lsm6dso32_gy_self_test_set(stmdev_ctx_t *ctx,
2073 lsm6dso32_st_g_t val)
2074 {
2075 lsm6dso32_ctrl5_c_t reg;
2076 int32_t ret;
2077
2078 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
2079
2080 if (ret == 0)
2081 {
2082 reg.st_g = (uint8_t)val;
2083 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
2084 }
2085
2086 return ret;
2087 }
2088
2089 /**
2090 * @brief Angular rate sensor self-test enable.[get]
2091 *
2092 * @param ctx read / write interface definitions
2093 * @param val Get the values of st_g in reg CTRL5_C
2094 * @retval interface status (MANDATORY: return 0 -> no Error)
2095 *
2096 */
lsm6dso32_gy_self_test_get(stmdev_ctx_t * ctx,lsm6dso32_st_g_t * val)2097 int32_t lsm6dso32_gy_self_test_get(stmdev_ctx_t *ctx,
2098 lsm6dso32_st_g_t *val)
2099 {
2100 lsm6dso32_ctrl5_c_t reg;
2101 int32_t ret;
2102
2103 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL5_C, (uint8_t *)®, 1);
2104
2105 switch (reg.st_g)
2106 {
2107 case LSM6DSO32_GY_ST_DISABLE:
2108 *val = LSM6DSO32_GY_ST_DISABLE;
2109 break;
2110
2111 case LSM6DSO32_GY_ST_POSITIVE:
2112 *val = LSM6DSO32_GY_ST_POSITIVE;
2113 break;
2114
2115 case LSM6DSO32_GY_ST_NEGATIVE:
2116 *val = LSM6DSO32_GY_ST_NEGATIVE;
2117 break;
2118
2119 default:
2120 *val = LSM6DSO32_GY_ST_DISABLE;
2121 break;
2122 }
2123
2124 return ret;
2125 }
2126
2127 /**
2128 * @}
2129 *
2130 */
2131
2132 /**
2133 * @defgroup LSM6DSO32_filters
2134 * @brief This section group all the functions concerning the
2135 * filters configuration
2136 * @{
2137 *
2138 */
2139
2140 /**
2141 * @brief Accelerometer output from LPF2 filtering stage selection.[set]
2142 *
2143 * @param ctx read / write interface definitions
2144 * @param val change the values of lpf2_xl_en in reg CTRL1_XL
2145 * @retval interface status (MANDATORY: return 0 -> no Error)
2146 *
2147 */
lsm6dso32_xl_filter_lp2_set(stmdev_ctx_t * ctx,uint8_t val)2148 int32_t lsm6dso32_xl_filter_lp2_set(stmdev_ctx_t *ctx, uint8_t val)
2149 {
2150 lsm6dso32_ctrl1_xl_t reg;
2151 int32_t ret;
2152
2153 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t *)®, 1);
2154
2155 if (ret == 0)
2156 {
2157 reg.lpf2_xl_en = val;
2158 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t *)®, 1);
2159 }
2160
2161 return ret;
2162 }
2163
2164 /**
2165 * @brief Accelerometer output from LPF2 filtering stage selection.[get]
2166 *
2167 * @param ctx read / write interface definitions
2168 * @param val change the values of lpf2_xl_en in reg CTRL1_XL
2169 * @retval interface status (MANDATORY: return 0 -> no Error)
2170 *
2171 */
lsm6dso32_xl_filter_lp2_get(stmdev_ctx_t * ctx,uint8_t * val)2172 int32_t lsm6dso32_xl_filter_lp2_get(stmdev_ctx_t *ctx, uint8_t *val)
2173 {
2174 lsm6dso32_ctrl1_xl_t reg;
2175 int32_t ret;
2176
2177 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL1_XL, (uint8_t *)®, 1);
2178 *val = reg.lpf2_xl_en;
2179
2180 return ret;
2181 }
2182
2183 /**
2184 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2185 * the bandwidth can be selected through FTYPE [2:0]
2186 * in CTRL6_C (15h).[set]
2187 *
2188 * @param ctx read / write interface definitions
2189 * @param val change the values of lpf1_sel_g in reg CTRL4_C
2190 * @retval interface status (MANDATORY: return 0 -> no Error)
2191 *
2192 */
lsm6dso32_gy_filter_lp1_set(stmdev_ctx_t * ctx,uint8_t val)2193 int32_t lsm6dso32_gy_filter_lp1_set(stmdev_ctx_t *ctx, uint8_t val)
2194 {
2195 lsm6dso32_ctrl4_c_t reg;
2196 int32_t ret;
2197
2198 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
2199
2200 if (ret == 0)
2201 {
2202 reg.lpf1_sel_g = val;
2203 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
2204 }
2205
2206 return ret;
2207 }
2208
2209 /**
2210 * @brief Enables gyroscope digital LPF1 if auxiliary SPI is disabled;
2211 * the bandwidth can be selected through FTYPE [2:0]
2212 * in CTRL6_C (15h).[get]
2213 *
2214 * @param ctx read / write interface definitions
2215 * @param val change the values of lpf1_sel_g in reg CTRL4_C
2216 * @retval interface status (MANDATORY: return 0 -> no Error)
2217 *
2218 */
lsm6dso32_gy_filter_lp1_get(stmdev_ctx_t * ctx,uint8_t * val)2219 int32_t lsm6dso32_gy_filter_lp1_get(stmdev_ctx_t *ctx, uint8_t *val)
2220 {
2221 lsm6dso32_ctrl4_c_t reg;
2222 int32_t ret;
2223
2224 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
2225 *val = reg.lpf1_sel_g;
2226
2227 return ret;
2228 }
2229
2230 /**
2231 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2232 * (XL and Gyro independently masked).[set]
2233 *
2234 * @param ctx read / write interface definitions
2235 * @param val change the values of drdy_mask in reg CTRL4_C
2236 * @retval interface status (MANDATORY: return 0 -> no Error)
2237 *
2238 */
lsm6dso32_filter_settling_mask_set(stmdev_ctx_t * ctx,uint8_t val)2239 int32_t lsm6dso32_filter_settling_mask_set(stmdev_ctx_t *ctx,
2240 uint8_t val)
2241 {
2242 lsm6dso32_ctrl4_c_t reg;
2243 int32_t ret;
2244
2245 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
2246
2247 if (ret == 0)
2248 {
2249 reg.drdy_mask = val;
2250 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
2251 }
2252
2253 return ret;
2254 }
2255
2256 /**
2257 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
2258 * (XL and Gyro independently masked).[get]
2259 *
2260 * @param ctx read / write interface definitions
2261 * @param val change the values of drdy_mask in reg CTRL4_C
2262 * @retval interface status (MANDATORY: return 0 -> no Error)
2263 *
2264 */
lsm6dso32_filter_settling_mask_get(stmdev_ctx_t * ctx,uint8_t * val)2265 int32_t lsm6dso32_filter_settling_mask_get(stmdev_ctx_t *ctx,
2266 uint8_t *val)
2267 {
2268 lsm6dso32_ctrl4_c_t reg;
2269 int32_t ret;
2270
2271 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
2272 *val = reg.drdy_mask;
2273
2274 return ret;
2275 }
2276
2277 /**
2278 * @brief Gyroscope lp1 bandwidth.[set]
2279 *
2280 * @param ctx read / write interface definitions
2281 * @param val change the values of ftype in reg CTRL6_C
2282 * @retval interface status (MANDATORY: return 0 -> no Error)
2283 *
2284 */
lsm6dso32_gy_lp1_bandwidth_set(stmdev_ctx_t * ctx,lsm6dso32_ftype_t val)2285 int32_t lsm6dso32_gy_lp1_bandwidth_set(stmdev_ctx_t *ctx,
2286 lsm6dso32_ftype_t val)
2287 {
2288 lsm6dso32_ctrl6_c_t reg;
2289 int32_t ret;
2290
2291 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
2292
2293 if (ret == 0)
2294 {
2295 reg.ftype = (uint8_t)val;
2296 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
2297 }
2298
2299 return ret;
2300 }
2301
2302 /**
2303 * @brief Gyroscope lp1 bandwidth.[get]
2304 *
2305 * @param ctx read / write interface definitions
2306 * @param val Get the values of ftype in reg CTRL6_C
2307 * @retval interface status (MANDATORY: return 0 -> no Error)
2308 *
2309 */
lsm6dso32_gy_lp1_bandwidth_get(stmdev_ctx_t * ctx,lsm6dso32_ftype_t * val)2310 int32_t lsm6dso32_gy_lp1_bandwidth_get(stmdev_ctx_t *ctx,
2311 lsm6dso32_ftype_t *val)
2312 {
2313 lsm6dso32_ctrl6_c_t reg;
2314 int32_t ret;
2315
2316 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
2317
2318 switch (reg.ftype)
2319 {
2320 case LSM6DSO32_ULTRA_LIGHT:
2321 *val = LSM6DSO32_ULTRA_LIGHT;
2322 break;
2323
2324 case LSM6DSO32_VERY_LIGHT:
2325 *val = LSM6DSO32_VERY_LIGHT;
2326 break;
2327
2328 case LSM6DSO32_LIGHT:
2329 *val = LSM6DSO32_LIGHT;
2330 break;
2331
2332 case LSM6DSO32_MEDIUM:
2333 *val = LSM6DSO32_MEDIUM;
2334 break;
2335
2336 case LSM6DSO32_STRONG:
2337 *val = LSM6DSO32_STRONG;
2338 break;
2339
2340 case LSM6DSO32_VERY_STRONG:
2341 *val = LSM6DSO32_VERY_STRONG;
2342 break;
2343
2344 case LSM6DSO32_AGGRESSIVE:
2345 *val = LSM6DSO32_AGGRESSIVE;
2346 break;
2347
2348 case LSM6DSO32_XTREME:
2349 *val = LSM6DSO32_XTREME;
2350 break;
2351
2352 default:
2353 *val = LSM6DSO32_ULTRA_LIGHT;
2354 break;
2355 }
2356
2357 return ret;
2358 }
2359
2360 /**
2361 * @brief Low pass filter 2 on 6D function selection.[set]
2362 *
2363 * @param ctx read / write interface definitions
2364 * @param val change the values of low_pass_on_6d in reg CTRL8_XL
2365 * @retval interface status (MANDATORY: return 0 -> no Error)
2366 *
2367 */
lsm6dso32_xl_lp2_on_6d_set(stmdev_ctx_t * ctx,uint8_t val)2368 int32_t lsm6dso32_xl_lp2_on_6d_set(stmdev_ctx_t *ctx, uint8_t val)
2369 {
2370 lsm6dso32_ctrl8_xl_t reg;
2371 int32_t ret;
2372
2373 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
2374
2375 if (ret == 0)
2376 {
2377 reg.low_pass_on_6d = val;
2378 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
2379 }
2380
2381 return ret;
2382 }
2383
2384 /**
2385 * @brief Low pass filter 2 on 6D function selection.[get]
2386 *
2387 * @param ctx read / write interface definitions
2388 * @param val change the values of low_pass_on_6d in reg CTRL8_XL
2389 * @retval interface status (MANDATORY: return 0 -> no Error)
2390 *
2391 */
lsm6dso32_xl_lp2_on_6d_get(stmdev_ctx_t * ctx,uint8_t * val)2392 int32_t lsm6dso32_xl_lp2_on_6d_get(stmdev_ctx_t *ctx, uint8_t *val)
2393 {
2394 lsm6dso32_ctrl8_xl_t reg;
2395 int32_t ret;
2396
2397 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
2398 *val = reg.low_pass_on_6d;
2399
2400 return ret;
2401 }
2402
2403 /**
2404 * @brief Accelerometer slope filter / high-pass filter selection
2405 * on output.[set]
2406 *
2407 * @param ctx read / write interface definitions
2408 * @param val change the values of hp_slope_xl_en
2409 * in reg CTRL8_XL
2410 * @retval interface status (MANDATORY: return 0 -> no Error)
2411 *
2412 */
lsm6dso32_xl_hp_path_on_out_set(stmdev_ctx_t * ctx,lsm6dso32_hp_slope_xl_en_t val)2413 int32_t lsm6dso32_xl_hp_path_on_out_set(stmdev_ctx_t *ctx,
2414 lsm6dso32_hp_slope_xl_en_t val)
2415 {
2416 lsm6dso32_ctrl8_xl_t reg;
2417 int32_t ret;
2418
2419 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
2420
2421 if (ret == 0)
2422 {
2423 reg.hp_slope_xl_en = ((uint8_t)val & 0x10U) >> 4;
2424 reg.hp_ref_mode_xl = ((uint8_t)val & 0x20U) >> 5;
2425 reg.hpcf_xl = (uint8_t)val & 0x07U;
2426 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
2427 }
2428
2429 return ret;
2430 }
2431
2432 /**
2433 * @brief Accelerometer slope filter / high-pass filter selection
2434 * on output.[get]
2435 *
2436 * @param ctx read / write interface definitions
2437 * @param val Get the values of hp_slope_xl_en in reg CTRL8_XL
2438 * @retval interface status (MANDATORY: return 0 -> no Error)
2439 *
2440 */
lsm6dso32_xl_hp_path_on_out_get(stmdev_ctx_t * ctx,lsm6dso32_hp_slope_xl_en_t * val)2441 int32_t lsm6dso32_xl_hp_path_on_out_get(stmdev_ctx_t *ctx,
2442 lsm6dso32_hp_slope_xl_en_t *val)
2443 {
2444 lsm6dso32_ctrl8_xl_t reg;
2445 int32_t ret;
2446
2447 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
2448
2449 switch ((reg.hp_ref_mode_xl << 5) | (reg.hp_slope_xl_en << 4) |
2450 reg.hpcf_xl)
2451 {
2452 case LSM6DSO32_HP_PATH_DISABLE_ON_OUT:
2453 *val = LSM6DSO32_HP_PATH_DISABLE_ON_OUT;
2454 break;
2455
2456 case LSM6DSO32_SLOPE_ODR_DIV_4:
2457 *val = LSM6DSO32_SLOPE_ODR_DIV_4;
2458 break;
2459
2460 case LSM6DSO32_HP_ODR_DIV_10:
2461 *val = LSM6DSO32_HP_ODR_DIV_10;
2462 break;
2463
2464 case LSM6DSO32_HP_ODR_DIV_20:
2465 *val = LSM6DSO32_HP_ODR_DIV_20;
2466 break;
2467
2468 case LSM6DSO32_HP_ODR_DIV_45:
2469 *val = LSM6DSO32_HP_ODR_DIV_45;
2470 break;
2471
2472 case LSM6DSO32_HP_ODR_DIV_100:
2473 *val = LSM6DSO32_HP_ODR_DIV_100;
2474 break;
2475
2476 case LSM6DSO32_HP_ODR_DIV_200:
2477 *val = LSM6DSO32_HP_ODR_DIV_200;
2478 break;
2479
2480 case LSM6DSO32_HP_ODR_DIV_400:
2481 *val = LSM6DSO32_HP_ODR_DIV_400;
2482 break;
2483
2484 case LSM6DSO32_HP_ODR_DIV_800:
2485 *val = LSM6DSO32_HP_ODR_DIV_800;
2486 break;
2487
2488 case LSM6DSO32_HP_REF_MD_ODR_DIV_10:
2489 *val = LSM6DSO32_HP_REF_MD_ODR_DIV_10;
2490 break;
2491
2492 case LSM6DSO32_HP_REF_MD_ODR_DIV_20:
2493 *val = LSM6DSO32_HP_REF_MD_ODR_DIV_20;
2494 break;
2495
2496 case LSM6DSO32_HP_REF_MD_ODR_DIV_45:
2497 *val = LSM6DSO32_HP_REF_MD_ODR_DIV_45;
2498 break;
2499
2500 case LSM6DSO32_HP_REF_MD_ODR_DIV_100:
2501 *val = LSM6DSO32_HP_REF_MD_ODR_DIV_100;
2502 break;
2503
2504 case LSM6DSO32_HP_REF_MD_ODR_DIV_200:
2505 *val = LSM6DSO32_HP_REF_MD_ODR_DIV_200;
2506 break;
2507
2508 case LSM6DSO32_HP_REF_MD_ODR_DIV_400:
2509 *val = LSM6DSO32_HP_REF_MD_ODR_DIV_400;
2510 break;
2511
2512 case LSM6DSO32_HP_REF_MD_ODR_DIV_800:
2513 *val = LSM6DSO32_HP_REF_MD_ODR_DIV_800;
2514 break;
2515
2516 case LSM6DSO32_LP_ODR_DIV_10:
2517 *val = LSM6DSO32_LP_ODR_DIV_10;
2518 break;
2519
2520 case LSM6DSO32_LP_ODR_DIV_20:
2521 *val = LSM6DSO32_LP_ODR_DIV_20;
2522 break;
2523
2524 case LSM6DSO32_LP_ODR_DIV_45:
2525 *val = LSM6DSO32_LP_ODR_DIV_45;
2526 break;
2527
2528 case LSM6DSO32_LP_ODR_DIV_100:
2529 *val = LSM6DSO32_LP_ODR_DIV_100;
2530 break;
2531
2532 case LSM6DSO32_LP_ODR_DIV_200:
2533 *val = LSM6DSO32_LP_ODR_DIV_200;
2534 break;
2535
2536 case LSM6DSO32_LP_ODR_DIV_400:
2537 *val = LSM6DSO32_LP_ODR_DIV_400;
2538 break;
2539
2540 case LSM6DSO32_LP_ODR_DIV_800:
2541 *val = LSM6DSO32_LP_ODR_DIV_800;
2542 break;
2543
2544 default:
2545 *val = LSM6DSO32_HP_PATH_DISABLE_ON_OUT;
2546 break;
2547 }
2548
2549 return ret;
2550 }
2551
2552 /**
2553 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2554 * The filter sets the second samples after writing this bit.
2555 * Active only during device exit from power-down mode.[set]
2556 *
2557 * @param ctx read / write interface definitions
2558 * @param val change the values of fastsettl_mode_xl in
2559 * reg CTRL8_XL
2560 * @retval interface status (MANDATORY: return 0 -> no Error)
2561 *
2562 */
lsm6dso32_xl_fast_settling_set(stmdev_ctx_t * ctx,uint8_t val)2563 int32_t lsm6dso32_xl_fast_settling_set(stmdev_ctx_t *ctx, uint8_t val)
2564 {
2565 lsm6dso32_ctrl8_xl_t reg;
2566 int32_t ret;
2567
2568 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
2569
2570 if (ret == 0)
2571 {
2572 reg.fastsettl_mode_xl = val;
2573 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
2574 }
2575
2576 return ret;
2577 }
2578
2579 /**
2580 * @brief Enables accelerometer LPF2 and HPF fast-settling mode.
2581 * The filter sets the second samples after writing this bit.
2582 * Active only during device exit from power-down mode.[get]
2583 *
2584 * @param ctx read / write interface definitions
2585 * @param val change the values of fastsettl_mode_xl in reg CTRL8_XL
2586 * @retval interface status (MANDATORY: return 0 -> no Error)
2587 *
2588 */
lsm6dso32_xl_fast_settling_get(stmdev_ctx_t * ctx,uint8_t * val)2589 int32_t lsm6dso32_xl_fast_settling_get(stmdev_ctx_t *ctx,
2590 uint8_t *val)
2591 {
2592 lsm6dso32_ctrl8_xl_t reg;
2593 int32_t ret;
2594
2595 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL8_XL, (uint8_t *)®, 1);
2596 *val = reg.fastsettl_mode_xl;
2597
2598 return ret;
2599 }
2600
2601 /**
2602 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2603 * functions.[set]
2604 *
2605 * @param ctx read / write interface definitions
2606 * @param val change the values of slope_fds in reg TAP_CFG0
2607 * @retval interface status (MANDATORY: return 0 -> no Error)
2608 *
2609 */
lsm6dso32_xl_hp_path_internal_set(stmdev_ctx_t * ctx,lsm6dso32_slope_fds_t val)2610 int32_t lsm6dso32_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
2611 lsm6dso32_slope_fds_t val)
2612 {
2613 lsm6dso32_tap_cfg0_t reg;
2614 int32_t ret;
2615
2616 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
2617
2618 if (ret == 0)
2619 {
2620 reg.slope_fds = (uint8_t)val;
2621 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
2622 }
2623
2624 return ret;
2625 }
2626
2627 /**
2628 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
2629 * functions.[get]
2630 *
2631 * @param ctx read / write interface definitions
2632 * @param val Get the values of slope_fds in reg TAP_CFG0
2633 * @retval interface status (MANDATORY: return 0 -> no Error)
2634 *
2635 */
lsm6dso32_xl_hp_path_internal_get(stmdev_ctx_t * ctx,lsm6dso32_slope_fds_t * val)2636 int32_t lsm6dso32_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
2637 lsm6dso32_slope_fds_t *val)
2638 {
2639 lsm6dso32_tap_cfg0_t reg;
2640 int32_t ret;
2641
2642 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
2643
2644 switch (reg.slope_fds)
2645 {
2646 case LSM6DSO32_USE_SLOPE:
2647 *val = LSM6DSO32_USE_SLOPE;
2648 break;
2649
2650 case LSM6DSO32_USE_HPF:
2651 *val = LSM6DSO32_USE_HPF;
2652 break;
2653
2654 default:
2655 *val = LSM6DSO32_USE_SLOPE;
2656 break;
2657 }
2658
2659 return ret;
2660 }
2661
2662 /**
2663 * @brief Enables gyroscope digital high-pass filter. The filter is
2664 * enabled only if the gyro is in HP mode.[set]
2665 *
2666 * @param ctx read / write interface definitions
2667 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
2668 * @retval interface status (MANDATORY: return 0 -> no Error)
2669 *
2670 */
lsm6dso32_gy_hp_path_internal_set(stmdev_ctx_t * ctx,lsm6dso32_hpm_g_t val)2671 int32_t lsm6dso32_gy_hp_path_internal_set(stmdev_ctx_t *ctx,
2672 lsm6dso32_hpm_g_t val)
2673 {
2674 lsm6dso32_ctrl7_g_t reg;
2675 int32_t ret;
2676
2677 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1);
2678
2679 if (ret == 0)
2680 {
2681 reg.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
2682 reg.hpm_g = (uint8_t)val & 0x03U;
2683 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1);
2684 }
2685
2686 return ret;
2687 }
2688
2689 /**
2690 * @brief Enables gyroscope digital high-pass filter. The filter is
2691 * enabled only if the gyro is in HP mode.[get]
2692 *
2693 * @param ctx read / write interface definitions
2694 * @param val Get the values of hp_en_g and hp_en_g in reg CTRL7_G
2695 * @retval interface status (MANDATORY: return 0 -> no Error)
2696 *
2697 */
lsm6dso32_gy_hp_path_internal_get(stmdev_ctx_t * ctx,lsm6dso32_hpm_g_t * val)2698 int32_t lsm6dso32_gy_hp_path_internal_get(stmdev_ctx_t *ctx,
2699 lsm6dso32_hpm_g_t *val)
2700 {
2701 lsm6dso32_ctrl7_g_t reg;
2702 int32_t ret;
2703
2704 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL7_G, (uint8_t *)®, 1);
2705
2706 switch ((reg.hp_en_g << 7) + reg.hpm_g)
2707 {
2708 case LSM6DSO32_HP_FILTER_NONE:
2709 *val = LSM6DSO32_HP_FILTER_NONE;
2710 break;
2711
2712 case LSM6DSO32_HP_FILTER_16mHz:
2713 *val = LSM6DSO32_HP_FILTER_16mHz;
2714 break;
2715
2716 case LSM6DSO32_HP_FILTER_65mHz:
2717 *val = LSM6DSO32_HP_FILTER_65mHz;
2718 break;
2719
2720 case LSM6DSO32_HP_FILTER_260mHz:
2721 *val = LSM6DSO32_HP_FILTER_260mHz;
2722 break;
2723
2724 case LSM6DSO32_HP_FILTER_1Hz04:
2725 *val = LSM6DSO32_HP_FILTER_1Hz04;
2726 break;
2727
2728 default:
2729 *val = LSM6DSO32_HP_FILTER_NONE;
2730 break;
2731 }
2732
2733 return ret;
2734 }
2735
2736 /**
2737 * @}
2738 *
2739 */
2740
2741 /**
2742 * @defgroup LSM6DSO32 main_serial_interface
2743 * @brief This section groups all the functions concerning main
2744 * serial interface management (not auxiliary)
2745 * @{
2746 *
2747 */
2748
2749 /**
2750 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[set]
2751 *
2752 * @param ctx read / write interface definitions
2753 * @param val change the values of sdo_pu_en in
2754 * reg PIN_CTRL
2755 * @retval interface status (MANDATORY: return 0 -> no Error)
2756 *
2757 */
lsm6dso32_sdo_sa0_mode_set(stmdev_ctx_t * ctx,lsm6dso32_sdo_pu_en_t val)2758 int32_t lsm6dso32_sdo_sa0_mode_set(stmdev_ctx_t *ctx,
2759 lsm6dso32_sdo_pu_en_t val)
2760 {
2761 lsm6dso32_pin_ctrl_t reg;
2762 int32_t ret;
2763
2764 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PIN_CTRL, (uint8_t *)®, 1);
2765
2766 if (ret == 0)
2767 {
2768 reg.sdo_pu_en = (uint8_t)val;
2769 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PIN_CTRL, (uint8_t *)®, 1);
2770 }
2771
2772 return ret;
2773 }
2774
2775 /**
2776 * @brief Connect/Disconnect SDO/SA0 internal pull-up.[get]
2777 *
2778 * @param ctx read / write interface definitions
2779 * @param val Get the values of sdo_pu_en in reg PIN_CTRL
2780 * @retval interface status (MANDATORY: return 0 -> no Error)
2781 *
2782 */
lsm6dso32_sdo_sa0_mode_get(stmdev_ctx_t * ctx,lsm6dso32_sdo_pu_en_t * val)2783 int32_t lsm6dso32_sdo_sa0_mode_get(stmdev_ctx_t *ctx,
2784 lsm6dso32_sdo_pu_en_t *val)
2785 {
2786 lsm6dso32_pin_ctrl_t reg;
2787 int32_t ret;
2788
2789 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PIN_CTRL, (uint8_t *)®, 1);
2790
2791 switch (reg.sdo_pu_en)
2792 {
2793 case LSM6DSO32_PULL_UP_DISC:
2794 *val = LSM6DSO32_PULL_UP_DISC;
2795 break;
2796
2797 case LSM6DSO32_PULL_UP_CONNECT:
2798 *val = LSM6DSO32_PULL_UP_CONNECT;
2799 break;
2800
2801 default:
2802 *val = LSM6DSO32_PULL_UP_DISC;
2803 break;
2804 }
2805
2806 return ret;
2807 }
2808
2809 /**
2810 * @brief SPI Serial Interface Mode selection.[set]
2811 *
2812 * @param ctx read / write interface definitions
2813 * @param val change the values of sim in reg CTRL3_C
2814 * @retval interface status (MANDATORY: return 0 -> no Error)
2815 *
2816 */
lsm6dso32_spi_mode_set(stmdev_ctx_t * ctx,lsm6dso32_sim_t val)2817 int32_t lsm6dso32_spi_mode_set(stmdev_ctx_t *ctx, lsm6dso32_sim_t val)
2818 {
2819 lsm6dso32_ctrl3_c_t reg;
2820 int32_t ret;
2821
2822 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
2823
2824 if (ret == 0)
2825 {
2826 reg.sim = (uint8_t)val;
2827 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
2828 }
2829
2830 return ret;
2831 }
2832
2833 /**
2834 * @brief SPI Serial Interface Mode selection.[get]
2835 *
2836 * @param ctx read / write interface definitions
2837 * @param val Get the values of sim in reg CTRL3_C
2838 * @retval interface status (MANDATORY: return 0 -> no Error)
2839 *
2840 */
lsm6dso32_spi_mode_get(stmdev_ctx_t * ctx,lsm6dso32_sim_t * val)2841 int32_t lsm6dso32_spi_mode_get(stmdev_ctx_t *ctx,
2842 lsm6dso32_sim_t *val)
2843 {
2844 lsm6dso32_ctrl3_c_t reg;
2845 int32_t ret;
2846
2847 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
2848
2849 switch (reg.sim)
2850 {
2851 case LSM6DSO32_SPI_4_WIRE:
2852 *val = LSM6DSO32_SPI_4_WIRE;
2853 break;
2854
2855 case LSM6DSO32_SPI_3_WIRE:
2856 *val = LSM6DSO32_SPI_3_WIRE;
2857 break;
2858
2859 default:
2860 *val = LSM6DSO32_SPI_4_WIRE;
2861 break;
2862 }
2863
2864 return ret;
2865 }
2866
2867 /**
2868 * @brief Disable / Enable I2C interface.[set]
2869 *
2870 * @param ctx read / write interface definitions
2871 * @param val change the values of i2c_disable in
2872 * reg CTRL4_C
2873 * @retval interface status (MANDATORY: return 0 -> no Error)
2874 *
2875 */
lsm6dso32_i2c_interface_set(stmdev_ctx_t * ctx,lsm6dso32_i2c_disable_t val)2876 int32_t lsm6dso32_i2c_interface_set(stmdev_ctx_t *ctx,
2877 lsm6dso32_i2c_disable_t val)
2878 {
2879 lsm6dso32_ctrl4_c_t reg;
2880 int32_t ret;
2881
2882 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
2883
2884 if (ret == 0)
2885 {
2886 reg.i2c_disable = (uint8_t)val;
2887 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
2888 }
2889
2890 return ret;
2891 }
2892
2893 /**
2894 * @brief Disable / Enable I2C interface.[get]
2895 *
2896 * @param ctx read / write interface definitions
2897 * @param val Get the values of i2c_disable in
2898 * reg CTRL4_C
2899 * @retval interface status (MANDATORY: return 0 -> no Error)
2900 *
2901 */
lsm6dso32_i2c_interface_get(stmdev_ctx_t * ctx,lsm6dso32_i2c_disable_t * val)2902 int32_t lsm6dso32_i2c_interface_get(stmdev_ctx_t *ctx,
2903 lsm6dso32_i2c_disable_t *val)
2904 {
2905 lsm6dso32_ctrl4_c_t reg;
2906 int32_t ret;
2907
2908 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
2909
2910 switch (reg.i2c_disable)
2911 {
2912 case LSM6DSO32_I2C_ENABLE:
2913 *val = LSM6DSO32_I2C_ENABLE;
2914 break;
2915
2916 case LSM6DSO32_I2C_DISABLE:
2917 *val = LSM6DSO32_I2C_DISABLE;
2918 break;
2919
2920 default:
2921 *val = LSM6DSO32_I2C_ENABLE;
2922 break;
2923 }
2924
2925 return ret;
2926 }
2927
2928 /**
2929 * @brief I3C Enable/Disable communication protocol[.set]
2930 *
2931 * @param ctx read / write interface definitions
2932 * @param val change the values of i3c_disable in reg CTRL9_XL
2933 * @retval interface status (MANDATORY: return 0 -> no Error)
2934 *
2935 */
lsm6dso32_i3c_disable_set(stmdev_ctx_t * ctx,lsm6dso32_i3c_disable_t val)2936 int32_t lsm6dso32_i3c_disable_set(stmdev_ctx_t *ctx,
2937 lsm6dso32_i3c_disable_t val)
2938 {
2939 lsm6dso32_i3c_bus_avb_t i3c_bus_avb;
2940 lsm6dso32_ctrl9_xl_t ctrl9_xl;
2941 int32_t ret;
2942
2943 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL,
2944 (uint8_t *)&ctrl9_xl, 1);
2945
2946 if (ret == 0)
2947 {
2948 ctrl9_xl.i3c_disable = ((uint8_t)val & 0x80U) >> 7;
2949 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL,
2950 (uint8_t *)&ctrl9_xl, 1);
2951 }
2952
2953 if (ret == 0)
2954 {
2955 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_I3C_BUS_AVB,
2956 (uint8_t *)&i3c_bus_avb, 1);
2957 }
2958
2959 if (ret == 0)
2960 {
2961 i3c_bus_avb.i3c_bus_avb_sel = (uint8_t)val & 0x03U;
2962 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_I3C_BUS_AVB,
2963 (uint8_t *)&i3c_bus_avb, 1);
2964 }
2965
2966 return ret;
2967 }
2968
2969 /**
2970 * @brief I3C Enable/Disable communication protocol.[get]
2971 *
2972 * @param ctx read / write interface definitions
2973 * @param val change the values of i3c_disable in reg CTRL9_XL
2974 * @retval interface status (MANDATORY: return 0 -> no Error)
2975 *
2976 */
lsm6dso32_i3c_disable_get(stmdev_ctx_t * ctx,lsm6dso32_i3c_disable_t * val)2977 int32_t lsm6dso32_i3c_disable_get(stmdev_ctx_t *ctx,
2978 lsm6dso32_i3c_disable_t *val)
2979 {
2980 lsm6dso32_ctrl9_xl_t ctrl9_xl;
2981 lsm6dso32_i3c_bus_avb_t i3c_bus_avb;
2982 int32_t ret;
2983
2984 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL,
2985 (uint8_t *)&ctrl9_xl, 1);
2986
2987 if (ret == 0)
2988 {
2989 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_I3C_BUS_AVB,
2990 (uint8_t *)&i3c_bus_avb, 1);
2991
2992 switch ((ctrl9_xl.i3c_disable << 7) | i3c_bus_avb.i3c_bus_avb_sel)
2993 {
2994 case LSM6DSO32_I3C_DISABLE:
2995 *val = LSM6DSO32_I3C_DISABLE;
2996 break;
2997
2998 case LSM6DSO32_I3C_ENABLE_T_50us:
2999 *val = LSM6DSO32_I3C_ENABLE_T_50us;
3000 break;
3001
3002 case LSM6DSO32_I3C_ENABLE_T_2us:
3003 *val = LSM6DSO32_I3C_ENABLE_T_2us;
3004 break;
3005
3006 case LSM6DSO32_I3C_ENABLE_T_1ms:
3007 *val = LSM6DSO32_I3C_ENABLE_T_1ms;
3008 break;
3009
3010 case LSM6DSO32_I3C_ENABLE_T_25ms:
3011 *val = LSM6DSO32_I3C_ENABLE_T_25ms;
3012 break;
3013
3014 default:
3015 *val = LSM6DSO32_I3C_DISABLE;
3016 break;
3017 }
3018 }
3019
3020 return ret;
3021 }
3022
3023 /**
3024 * @}
3025 *
3026 */
3027
3028 /**
3029 * @defgroup LSM6DSO32_interrupt_pins
3030 * @brief This section groups all the functions that manage interrupt pins
3031 * @{
3032 *
3033 */
3034
3035 /**
3036 * @brief Connect/Disconnect INT1 internal pull-down.[set]
3037 *
3038 * @param ctx read / write interface definitions
3039 * @param val change the values of pd_dis_int1 in reg I3C_BUS_AVB
3040 * @retval interface status (MANDATORY: return 0 -> no Error)
3041 *
3042 */
lsm6dso32_int1_mode_set(stmdev_ctx_t * ctx,lsm6dso32_int1_pd_en_t val)3043 int32_t lsm6dso32_int1_mode_set(stmdev_ctx_t *ctx,
3044 lsm6dso32_int1_pd_en_t val)
3045 {
3046 lsm6dso32_i3c_bus_avb_t reg;
3047 int32_t ret;
3048
3049 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_I3C_BUS_AVB, (uint8_t *)®, 1);
3050
3051 if (ret == 0)
3052 {
3053 reg.pd_dis_int1 = (uint8_t)val;
3054 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_I3C_BUS_AVB, (uint8_t *)®, 1);
3055 }
3056
3057 return ret;
3058 }
3059
3060 /**
3061 * @brief Connect/Disconnect INT1 internal pull-down.[get]
3062 *
3063 * @param ctx read / write interface definitions
3064 * @param val Get the values of pd_dis_int1 in reg I3C_BUS_AVB
3065 * @retval interface status (MANDATORY: return 0 -> no Error)
3066 *
3067 */
lsm6dso32_int1_mode_get(stmdev_ctx_t * ctx,lsm6dso32_int1_pd_en_t * val)3068 int32_t lsm6dso32_int1_mode_get(stmdev_ctx_t *ctx,
3069 lsm6dso32_int1_pd_en_t *val)
3070 {
3071 lsm6dso32_i3c_bus_avb_t reg;
3072 int32_t ret;
3073
3074 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_I3C_BUS_AVB, (uint8_t *)®, 1);
3075
3076 switch (reg.pd_dis_int1)
3077 {
3078 case LSM6DSO32_PULL_DOWN_DISC:
3079 *val = LSM6DSO32_PULL_DOWN_DISC;
3080 break;
3081
3082 case LSM6DSO32_PULL_DOWN_CONNECT:
3083 *val = LSM6DSO32_PULL_DOWN_CONNECT;
3084 break;
3085
3086 default:
3087 *val = LSM6DSO32_PULL_DOWN_DISC;
3088 break;
3089 }
3090
3091 return ret;
3092 }
3093
3094 /**
3095 * @brief Select the signal that need to route on int1 pad.[set]
3096 *
3097 * @param ctx read / write interface definitions
3098 * @param val struct of registers: INT1_CTRL,
3099 * MD1_CFG, EMB_FUNC_INT1, FSM_INT1_A,
3100 * FSM_INT1_B
3101 * @retval interface status (MANDATORY: return 0 -> no Error)
3102 *
3103 */
lsm6dso32_pin_int1_route_set(stmdev_ctx_t * ctx,lsm6dso32_pin_int1_route_t * val)3104 int32_t lsm6dso32_pin_int1_route_set(stmdev_ctx_t *ctx,
3105 lsm6dso32_pin_int1_route_t *val)
3106 {
3107 lsm6dso32_pin_int2_route_t pin_int2_route;
3108 lsm6dso32_tap_cfg2_t tap_cfg2;
3109 int32_t ret;
3110
3111 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
3112
3113 if (ret == 0)
3114 {
3115 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_INT1,
3116 (uint8_t *)&val->emb_func_int1, 1);
3117 }
3118
3119 if (ret == 0)
3120 {
3121 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_INT1_A,
3122 (uint8_t *)&val->fsm_int1_a, 1);
3123 }
3124
3125 if (ret == 0)
3126 {
3127 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_INT1_B,
3128 (uint8_t *)&val->fsm_int1_b, 1);
3129 }
3130
3131 if (ret == 0)
3132 {
3133 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
3134 }
3135
3136 if (ret == 0)
3137 {
3138 if ((val->emb_func_int1.int1_fsm_lc
3139 | val->emb_func_int1.int1_sig_mot
3140 | val->emb_func_int1.int1_step_detector
3141 | val->emb_func_int1.int1_tilt
3142 | val->fsm_int1_a.int1_fsm1
3143 | val->fsm_int1_a.int1_fsm2
3144 | val->fsm_int1_a.int1_fsm3
3145 | val->fsm_int1_a.int1_fsm4
3146 | val->fsm_int1_a.int1_fsm5
3147 | val->fsm_int1_a.int1_fsm6
3148 | val->fsm_int1_a.int1_fsm7
3149 | val->fsm_int1_a.int1_fsm8
3150 | val->fsm_int1_b.int1_fsm9
3151 | val->fsm_int1_b.int1_fsm10
3152 | val->fsm_int1_b.int1_fsm11
3153 | val->fsm_int1_b.int1_fsm12
3154 | val->fsm_int1_b.int1_fsm13
3155 | val->fsm_int1_b.int1_fsm14
3156 | val->fsm_int1_b.int1_fsm15
3157 | val->fsm_int1_b.int1_fsm16) != PROPERTY_DISABLE)
3158 {
3159 val->md1_cfg.int1_emb_func = PROPERTY_ENABLE;
3160 }
3161
3162 else
3163 {
3164 val->md1_cfg.int1_emb_func = PROPERTY_DISABLE;
3165 }
3166
3167 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT1_CTRL,
3168 (uint8_t *)&val->int1_ctrl, 1);
3169 }
3170
3171 if (ret == 0)
3172 {
3173 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MD1_CFG,
3174 (uint8_t *)&val->md1_cfg, 1);
3175 }
3176
3177 if (ret == 0)
3178 {
3179 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2,
3180 (uint8_t *) &tap_cfg2, 1);
3181 }
3182
3183 if (ret == 0)
3184 {
3185 ret = lsm6dso32_pin_int2_route_get(ctx, &pin_int2_route);
3186 }
3187
3188 if (ret == 0)
3189 {
3190 if ((pin_int2_route.int2_ctrl.int2_cnt_bdr
3191 | pin_int2_route.int2_ctrl.int2_drdy_g
3192 | pin_int2_route.int2_ctrl.int2_drdy_temp
3193 | pin_int2_route.int2_ctrl.int2_drdy_xl
3194 | pin_int2_route.int2_ctrl.int2_fifo_full
3195 | pin_int2_route.int2_ctrl.int2_fifo_ovr
3196 | pin_int2_route.int2_ctrl.int2_fifo_th
3197 | pin_int2_route.md2_cfg.int2_6d
3198 | pin_int2_route.md2_cfg.int2_double_tap
3199 | pin_int2_route.md2_cfg.int2_ff
3200 | pin_int2_route.md2_cfg.int2_wu
3201 | pin_int2_route.md2_cfg.int2_single_tap
3202 | pin_int2_route.md2_cfg.int2_sleep_change
3203 | val->int1_ctrl.den_drdy_flag
3204 | val->int1_ctrl.int1_boot
3205 | val->int1_ctrl.int1_cnt_bdr
3206 | val->int1_ctrl.int1_drdy_g
3207 | val->int1_ctrl.int1_drdy_xl
3208 | val->int1_ctrl.int1_fifo_full
3209 | val->int1_ctrl.int1_fifo_ovr
3210 | val->int1_ctrl.int1_fifo_th
3211 | val->md1_cfg.int1_6d
3212 | val->md1_cfg.int1_double_tap
3213 | val->md1_cfg.int1_ff
3214 | val->md1_cfg.int1_wu
3215 | val->md1_cfg.int1_single_tap
3216 | val->md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
3217 {
3218 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
3219 }
3220
3221 else
3222 {
3223 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
3224 }
3225
3226 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG2,
3227 (uint8_t *) &tap_cfg2, 1);
3228 }
3229
3230 return ret;
3231 }
3232
3233 /**
3234 * @brief Select the signal that need to route on int1 pad.[get]
3235 *
3236 * @param ctx read / write interface definitions
3237 * @param val struct of registers: INT1_CTRL, MD1_CFG,
3238 * EMB_FUNC_INT1, FSM_INT1_A, FSM_INT1_B
3239 * @retval interface status (MANDATORY: return 0 -> no Error)
3240 *
3241 */
lsm6dso32_pin_int1_route_get(stmdev_ctx_t * ctx,lsm6dso32_pin_int1_route_t * val)3242 int32_t lsm6dso32_pin_int1_route_get(stmdev_ctx_t *ctx,
3243 lsm6dso32_pin_int1_route_t *val)
3244 {
3245 int32_t ret;
3246
3247 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
3248
3249 if (ret == 0)
3250 {
3251 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INT1,
3252 (uint8_t *)&val->emb_func_int1, 1);
3253 }
3254
3255 if (ret == 0)
3256 {
3257 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_INT1_A,
3258 (uint8_t *)&val->fsm_int1_a, 1);
3259 }
3260
3261 if (ret == 0)
3262 {
3263 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_INT1_B,
3264 (uint8_t *)&val->fsm_int1_b, 1);
3265 }
3266
3267 if (ret == 0)
3268 {
3269 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
3270 }
3271
3272 if (ret == 0)
3273 {
3274 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT1_CTRL,
3275 (uint8_t *)&val->int1_ctrl, 1);
3276 }
3277
3278 if (ret == 0)
3279 {
3280 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MD1_CFG,
3281 (uint8_t *)&val->md1_cfg, 1);
3282 }
3283
3284 return ret;
3285 }
3286
3287 /**
3288 * @brief Select the signal that need to route on int2 pad.[set]
3289 *
3290 * @param ctx read / write interface definitions
3291 * @param val union of registers INT2_CTRL, MD2_CFG,
3292 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
3293 * @retval interface status (MANDATORY: return 0 -> no Error)
3294 *
3295 */
lsm6dso32_pin_int2_route_set(stmdev_ctx_t * ctx,lsm6dso32_pin_int2_route_t * val)3296 int32_t lsm6dso32_pin_int2_route_set(stmdev_ctx_t *ctx,
3297 lsm6dso32_pin_int2_route_t *val)
3298 {
3299 lsm6dso32_pin_int1_route_t pin_int1_route;
3300 lsm6dso32_tap_cfg2_t tap_cfg2;
3301 int32_t ret;
3302
3303 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
3304
3305 if (ret == 0)
3306 {
3307 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_INT2,
3308 (uint8_t *)&val->emb_func_int2, 1);
3309 }
3310
3311 if (ret == 0)
3312 {
3313 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_INT2_A,
3314 (uint8_t *)&val->fsm_int2_a, 1);
3315 }
3316
3317 if (ret == 0)
3318 {
3319 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_INT2_B,
3320 (uint8_t *)&val->fsm_int2_b, 1);
3321 }
3322
3323 if (ret == 0)
3324 {
3325 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
3326 }
3327
3328 if (ret == 0)
3329 {
3330 if ((val->emb_func_int2.int2_fsm_lc
3331 | val->emb_func_int2.int2_sig_mot
3332 | val->emb_func_int2.int2_step_detector
3333 | val->emb_func_int2.int2_tilt
3334 | val->fsm_int2_a.int2_fsm1
3335 | val->fsm_int2_a.int2_fsm2
3336 | val->fsm_int2_a.int2_fsm3
3337 | val->fsm_int2_a.int2_fsm4
3338 | val->fsm_int2_a.int2_fsm5
3339 | val->fsm_int2_a.int2_fsm6
3340 | val->fsm_int2_a.int2_fsm7
3341 | val->fsm_int2_a.int2_fsm8
3342 | val->fsm_int2_b.int2_fsm9
3343 | val->fsm_int2_b.int2_fsm10
3344 | val->fsm_int2_b.int2_fsm11
3345 | val->fsm_int2_b.int2_fsm12
3346 | val->fsm_int2_b.int2_fsm13
3347 | val->fsm_int2_b.int2_fsm14
3348 | val->fsm_int2_b.int2_fsm15
3349 | val->fsm_int2_b.int2_fsm16) != PROPERTY_DISABLE)
3350 {
3351 val->md2_cfg.int2_emb_func = PROPERTY_ENABLE;
3352 }
3353
3354 else
3355 {
3356 val->md2_cfg.int2_emb_func = PROPERTY_DISABLE;
3357 }
3358
3359 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT2_CTRL,
3360 (uint8_t *)&val->int2_ctrl, 1);
3361 }
3362
3363 if (ret == 0)
3364 {
3365 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MD2_CFG,
3366 (uint8_t *)&val->md2_cfg, 1);
3367 }
3368
3369 if (ret == 0)
3370 {
3371 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2,
3372 (uint8_t *) &tap_cfg2, 1);
3373 }
3374
3375 if (ret == 0)
3376 {
3377 ret = lsm6dso32_pin_int1_route_get(ctx, &pin_int1_route);
3378 }
3379
3380 if (ret == 0)
3381 {
3382 if ((val->int2_ctrl.int2_cnt_bdr
3383 | val->int2_ctrl.int2_drdy_g
3384 | val->int2_ctrl.int2_drdy_temp
3385 | val->int2_ctrl.int2_drdy_xl
3386 | val->int2_ctrl.int2_fifo_full
3387 | val->int2_ctrl.int2_fifo_ovr
3388 | val->int2_ctrl.int2_fifo_th
3389 | val->md2_cfg.int2_6d
3390 | val->md2_cfg.int2_double_tap
3391 | val->md2_cfg.int2_ff
3392 | val->md2_cfg.int2_wu
3393 | val->md2_cfg.int2_single_tap
3394 | val->md2_cfg.int2_sleep_change
3395 | pin_int1_route.int1_ctrl.den_drdy_flag
3396 | pin_int1_route.int1_ctrl.int1_boot
3397 | pin_int1_route.int1_ctrl.int1_cnt_bdr
3398 | pin_int1_route.int1_ctrl.int1_drdy_g
3399 | pin_int1_route.int1_ctrl.int1_drdy_xl
3400 | pin_int1_route.int1_ctrl.int1_fifo_full
3401 | pin_int1_route.int1_ctrl.int1_fifo_ovr
3402 | pin_int1_route.int1_ctrl.int1_fifo_th
3403 | pin_int1_route.md1_cfg.int1_6d
3404 | pin_int1_route.md1_cfg.int1_double_tap
3405 | pin_int1_route.md1_cfg.int1_ff
3406 | pin_int1_route.md1_cfg.int1_wu
3407 | pin_int1_route.md1_cfg.int1_single_tap
3408 | pin_int1_route.md1_cfg.int1_sleep_change) != PROPERTY_DISABLE)
3409 {
3410 tap_cfg2.interrupts_enable = PROPERTY_ENABLE;
3411 }
3412
3413 else
3414 {
3415 tap_cfg2.interrupts_enable = PROPERTY_DISABLE;
3416 }
3417
3418 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG2,
3419 (uint8_t *) &tap_cfg2, 1);
3420 }
3421
3422 return ret;
3423 }
3424
3425 /**
3426 * @brief Select the signal that need to route on int2 pad.[get]
3427 *
3428 * @param ctx read / write interface definitions
3429 * @param val union of registers INT2_CTRL, MD2_CFG,
3430 * EMB_FUNC_INT2, FSM_INT2_A, FSM_INT2_B
3431 * @retval interface status (MANDATORY: return 0 -> no Error)
3432 *
3433 */
lsm6dso32_pin_int2_route_get(stmdev_ctx_t * ctx,lsm6dso32_pin_int2_route_t * val)3434 int32_t lsm6dso32_pin_int2_route_get(stmdev_ctx_t *ctx,
3435 lsm6dso32_pin_int2_route_t *val)
3436 {
3437 int32_t ret;
3438
3439 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
3440
3441 if (ret == 0)
3442 {
3443 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INT2,
3444 (uint8_t *)&val->emb_func_int2, 1);
3445 }
3446
3447 if (ret == 0)
3448 {
3449 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_INT2_A,
3450 (uint8_t *)&val->fsm_int2_a, 1);
3451 }
3452
3453 if (ret == 0)
3454 {
3455 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_INT2_B,
3456 (uint8_t *)&val->fsm_int2_b, 1);
3457 }
3458
3459 if (ret == 0)
3460 {
3461 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
3462 }
3463
3464 if (ret == 0)
3465 {
3466 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT2_CTRL,
3467 (uint8_t *)&val->int2_ctrl, 1);
3468 }
3469
3470 if (ret == 0)
3471 {
3472 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MD2_CFG,
3473 (uint8_t *)&val->md2_cfg, 1);
3474 }
3475
3476 return ret;
3477 }
3478
3479 /**
3480 * @brief Push-pull/open drain selection on interrupt pads.[set]
3481 *
3482 * @param ctx read / write interface definitions
3483 * @param val change the values of pp_od in reg CTRL3_C
3484 * @retval interface status (MANDATORY: return 0 -> no Error)
3485 *
3486 */
lsm6dso32_pin_mode_set(stmdev_ctx_t * ctx,lsm6dso32_pp_od_t val)3487 int32_t lsm6dso32_pin_mode_set(stmdev_ctx_t *ctx,
3488 lsm6dso32_pp_od_t val)
3489 {
3490 lsm6dso32_ctrl3_c_t reg;
3491 int32_t ret;
3492
3493 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
3494
3495 if (ret == 0)
3496 {
3497 reg.pp_od = (uint8_t)val;
3498 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
3499 }
3500
3501 return ret;
3502 }
3503
3504 /**
3505 * @brief Push-pull/open drain selection on interrupt pads.[get]
3506 *
3507 * @param ctx read / write interface definitions
3508 * @param val Get the values of pp_od in reg CTRL3_C
3509 * @retval interface status (MANDATORY: return 0 -> no Error)
3510 *
3511 */
lsm6dso32_pin_mode_get(stmdev_ctx_t * ctx,lsm6dso32_pp_od_t * val)3512 int32_t lsm6dso32_pin_mode_get(stmdev_ctx_t *ctx,
3513 lsm6dso32_pp_od_t *val)
3514 {
3515 lsm6dso32_ctrl3_c_t reg;
3516 int32_t ret;
3517
3518 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
3519
3520 switch (reg.pp_od)
3521 {
3522 case LSM6DSO32_PUSH_PULL:
3523 *val = LSM6DSO32_PUSH_PULL;
3524 break;
3525
3526 case LSM6DSO32_OPEN_DRAIN:
3527 *val = LSM6DSO32_OPEN_DRAIN;
3528 break;
3529
3530 default:
3531 *val = LSM6DSO32_PUSH_PULL;
3532 break;
3533 }
3534
3535 return ret;
3536 }
3537
3538 /**
3539 * @brief Interrupt active-high/low.[set]
3540 *
3541 * @param ctx read / write interface definitions
3542 * @param val change the values of h_lactive in reg CTRL3_C
3543 * @retval interface status (MANDATORY: return 0 -> no Error)
3544 *
3545 */
lsm6dso32_pin_polarity_set(stmdev_ctx_t * ctx,lsm6dso32_h_lactive_t val)3546 int32_t lsm6dso32_pin_polarity_set(stmdev_ctx_t *ctx,
3547 lsm6dso32_h_lactive_t val)
3548 {
3549 lsm6dso32_ctrl3_c_t reg;
3550 int32_t ret;
3551
3552 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
3553
3554 if (ret == 0)
3555 {
3556 reg.h_lactive = (uint8_t)val;
3557 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
3558 }
3559
3560 return ret;
3561 }
3562
3563 /**
3564 * @brief Interrupt active-high/low.[get]
3565 *
3566 * @param ctx read / write interface definitions
3567 * @param val Get the values of h_lactive in reg CTRL3_C
3568 * @retval interface status (MANDATORY: return 0 -> no Error)
3569 *
3570 */
lsm6dso32_pin_polarity_get(stmdev_ctx_t * ctx,lsm6dso32_h_lactive_t * val)3571 int32_t lsm6dso32_pin_polarity_get(stmdev_ctx_t *ctx,
3572 lsm6dso32_h_lactive_t *val)
3573 {
3574 lsm6dso32_ctrl3_c_t reg;
3575 int32_t ret;
3576
3577 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL3_C, (uint8_t *)®, 1);
3578
3579 switch (reg.h_lactive)
3580 {
3581 case LSM6DSO32_ACTIVE_HIGH:
3582 *val = LSM6DSO32_ACTIVE_HIGH;
3583 break;
3584
3585 case LSM6DSO32_ACTIVE_LOW:
3586 *val = LSM6DSO32_ACTIVE_LOW;
3587 break;
3588
3589 default:
3590 *val = LSM6DSO32_ACTIVE_HIGH;
3591 break;
3592 }
3593
3594 return ret;
3595 }
3596
3597 /**
3598 * @brief All interrupt signals become available on INT1 pin.[set]
3599 *
3600 * @param ctx read / write interface definitions
3601 * @param val change the values of int2_on_int1 in reg CTRL4_C
3602 * @retval interface status (MANDATORY: return 0 -> no Error)
3603 *
3604 */
lsm6dso32_all_on_int1_set(stmdev_ctx_t * ctx,uint8_t val)3605 int32_t lsm6dso32_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
3606 {
3607 lsm6dso32_ctrl4_c_t reg;
3608 int32_t ret;
3609
3610 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
3611
3612 if (ret == 0)
3613 {
3614 reg.int2_on_int1 = val;
3615 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
3616 }
3617
3618 return ret;
3619 }
3620
3621 /**
3622 * @brief All interrupt signals become available on INT1 pin.[get]
3623 *
3624 * @param ctx read / write interface definitions
3625 * @param val change the values of int2_on_int1 in reg CTRL4_C
3626 * @retval interface status (MANDATORY: return 0 -> no Error)
3627 *
3628 */
lsm6dso32_all_on_int1_get(stmdev_ctx_t * ctx,uint8_t * val)3629 int32_t lsm6dso32_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
3630 {
3631 lsm6dso32_ctrl4_c_t reg;
3632 int32_t ret;
3633
3634 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
3635 *val = reg.int2_on_int1;
3636
3637 return ret;
3638 }
3639
3640 /**
3641 * @brief Interrupt notification mode.[set]
3642 *
3643 * @param ctx read / write interface definitions
3644 * @param val change the values of lir in reg TAP_CFG0
3645 * @retval interface status (MANDATORY: return 0 -> no Error)
3646 *
3647 */
lsm6dso32_int_notification_set(stmdev_ctx_t * ctx,lsm6dso32_lir_t val)3648 int32_t lsm6dso32_int_notification_set(stmdev_ctx_t *ctx,
3649 lsm6dso32_lir_t val)
3650 {
3651 lsm6dso32_tap_cfg0_t tap_cfg0;
3652 lsm6dso32_page_rw_t page_rw;
3653 int32_t ret;
3654
3655 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0,
3656 (uint8_t *) &tap_cfg0, 1);
3657
3658 if (ret == 0)
3659 {
3660 tap_cfg0.lir = (uint8_t)val & 0x01U;
3661 tap_cfg0.int_clr_on_read = (uint8_t)val & 0x01U;
3662 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0,
3663 (uint8_t *) &tap_cfg0, 1);
3664 }
3665
3666 if (ret == 0)
3667 {
3668 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
3669 }
3670
3671 if (ret == 0)
3672 {
3673 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
3674 }
3675
3676 if (ret == 0)
3677 {
3678 page_rw.emb_func_lir = ((uint8_t)val & 0x02U) >> 1;
3679 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_PAGE_RW,
3680 (uint8_t *) &page_rw, 1);
3681 }
3682
3683 if (ret == 0)
3684 {
3685 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
3686 }
3687
3688 return ret;
3689 }
3690
3691 /**
3692 * @brief Interrupt notification mode.[get]
3693 *
3694 * @param ctx read / write interface definitions
3695 * @param val Get the values of lir in reg TAP_CFG0
3696 * @retval interface status (MANDATORY: return 0 -> no Error)
3697 *
3698 */
lsm6dso32_int_notification_get(stmdev_ctx_t * ctx,lsm6dso32_lir_t * val)3699 int32_t lsm6dso32_int_notification_get(stmdev_ctx_t *ctx,
3700 lsm6dso32_lir_t *val)
3701 {
3702 lsm6dso32_tap_cfg0_t tap_cfg0;
3703 lsm6dso32_page_rw_t page_rw;
3704 int32_t ret;
3705
3706 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0,
3707 (uint8_t *) &tap_cfg0, 1);
3708
3709 if (ret == 0)
3710 {
3711 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
3712 }
3713
3714 if (ret == 0)
3715 {
3716 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
3717 }
3718
3719 if (ret == 0)
3720 {
3721 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
3722 }
3723
3724 if (ret == 0)
3725 {
3726 switch ((page_rw.emb_func_lir << 1) | tap_cfg0.lir)
3727 {
3728 case LSM6DSO32_ALL_INT_PULSED:
3729 *val = LSM6DSO32_ALL_INT_PULSED;
3730 break;
3731
3732 case LSM6DSO32_BASE_LATCHED_EMB_PULSED:
3733 *val = LSM6DSO32_BASE_LATCHED_EMB_PULSED;
3734 break;
3735
3736 case LSM6DSO32_BASE_PULSED_EMB_LATCHED:
3737 *val = LSM6DSO32_BASE_PULSED_EMB_LATCHED;
3738 break;
3739
3740 case LSM6DSO32_ALL_INT_LATCHED:
3741 *val = LSM6DSO32_ALL_INT_LATCHED;
3742 break;
3743
3744 default:
3745 *val = LSM6DSO32_ALL_INT_PULSED;
3746 break;
3747 }
3748
3749 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
3750 }
3751
3752 if (ret == 0)
3753 {
3754 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_PAGE_RW, (uint8_t *) &page_rw, 1);
3755 }
3756
3757 if (ret == 0)
3758 {
3759 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
3760 }
3761
3762 return ret;
3763 }
3764
3765 /**
3766 * @}
3767 *
3768 */
3769
3770 /**
3771 * @defgroup LSM6DSO32_Wake_Up_event
3772 * @brief This section groups all the functions that manage the Wake Up
3773 * event generation.
3774 * @{
3775 *
3776 */
3777
3778 /**
3779 * @brief Weight of 1 LSB of wakeup threshold.[set]
3780 * 0: 1 LSB =FS_XL / 64
3781 * 1: 1 LSB = FS_XL / 256
3782 *
3783 * @param ctx read / write interface definitions
3784 * @param val change the values of wake_ths_w in
3785 * reg WAKE_UP_DUR
3786 * @retval interface status (MANDATORY: return 0 -> no Error)
3787 *
3788 */
lsm6dso32_wkup_ths_weight_set(stmdev_ctx_t * ctx,lsm6dso32_wake_ths_w_t val)3789 int32_t lsm6dso32_wkup_ths_weight_set(stmdev_ctx_t *ctx,
3790 lsm6dso32_wake_ths_w_t val)
3791 {
3792 lsm6dso32_wake_up_dur_t reg;
3793 int32_t ret;
3794
3795 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
3796
3797 if (ret == 0)
3798 {
3799 reg.wake_ths_w = (uint8_t)val;
3800 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
3801 }
3802
3803 return ret;
3804 }
3805
3806 /**
3807 * @brief Weight of 1 LSB of wakeup threshold.[get]
3808 * 0: 1 LSB =FS_XL / 64
3809 * 1: 1 LSB = FS_XL / 256
3810 *
3811 * @param ctx read / write interface definitions
3812 * @param val Get the values of wake_ths_w in
3813 * reg WAKE_UP_DUR
3814 * @retval interface status (MANDATORY: return 0 -> no Error)
3815 *
3816 */
lsm6dso32_wkup_ths_weight_get(stmdev_ctx_t * ctx,lsm6dso32_wake_ths_w_t * val)3817 int32_t lsm6dso32_wkup_ths_weight_get(stmdev_ctx_t *ctx,
3818 lsm6dso32_wake_ths_w_t *val)
3819 {
3820 lsm6dso32_wake_up_dur_t reg;
3821 int32_t ret;
3822
3823 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
3824
3825 switch (reg.wake_ths_w)
3826 {
3827 case LSM6DSO32_LSb_FS_DIV_64:
3828 *val = LSM6DSO32_LSb_FS_DIV_64;
3829 break;
3830
3831 case LSM6DSO32_LSb_FS_DIV_256:
3832 *val = LSM6DSO32_LSb_FS_DIV_256;
3833 break;
3834
3835 default:
3836 *val = LSM6DSO32_LSb_FS_DIV_64;
3837 break;
3838 }
3839
3840 return ret;
3841 }
3842
3843 /**
3844 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
3845 * WAKE_UP_DUR.[set]
3846 *
3847 * @param ctx read / write interface definitions
3848 * @param val change the values of wk_ths in reg WAKE_UP_THS
3849 * @retval interface status (MANDATORY: return 0 -> no Error)
3850 *
3851 */
lsm6dso32_wkup_threshold_set(stmdev_ctx_t * ctx,uint8_t val)3852 int32_t lsm6dso32_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
3853 {
3854 lsm6dso32_wake_up_ths_t reg;
3855 int32_t ret;
3856
3857 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
3858
3859 if (ret == 0)
3860 {
3861 reg.wk_ths = val;
3862 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
3863 }
3864
3865 return ret;
3866 }
3867
3868 /**
3869 * @brief Threshold for wakeup: 1 LSB weight depends on WAKE_THS_W in
3870 * WAKE_UP_DUR.[get]
3871 *
3872 * @param ctx read / write interface definitions
3873 * @param val change the values of wk_ths in reg WAKE_UP_THS
3874 * @retval interface status (MANDATORY: return 0 -> no Error)
3875 *
3876 */
lsm6dso32_wkup_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)3877 int32_t lsm6dso32_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
3878 {
3879 lsm6dso32_wake_up_ths_t reg;
3880 int32_t ret;
3881
3882 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
3883 *val = reg.wk_ths;
3884
3885 return ret;
3886 }
3887
3888 /**
3889 * @brief Wake up duration event.[set]
3890 * 1LSb = 1 / ODR
3891 *
3892 * @param ctx read / write interface definitions
3893 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
3894 * @retval interface status (MANDATORY: return 0 -> no Error)
3895 *
3896 */
lsm6dso32_xl_usr_offset_on_wkup_set(stmdev_ctx_t * ctx,uint8_t val)3897 int32_t lsm6dso32_xl_usr_offset_on_wkup_set(stmdev_ctx_t *ctx,
3898 uint8_t val)
3899 {
3900 lsm6dso32_wake_up_ths_t reg;
3901 int32_t ret;
3902
3903 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
3904
3905 if (ret == 0)
3906 {
3907 reg.usr_off_on_wu = val;
3908 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
3909 }
3910
3911 return ret;
3912 }
3913
3914 /**
3915 * @brief Wake up duration event.[get]
3916 * 1LSb = 1 / ODR
3917 *
3918 * @param ctx read / write interface definitions
3919 * @param val change the values of usr_off_on_wu in reg WAKE_UP_THS
3920 * @retval interface status (MANDATORY: return 0 -> no Error)
3921 *
3922 */
lsm6dso32_xl_usr_offset_on_wkup_get(stmdev_ctx_t * ctx,uint8_t * val)3923 int32_t lsm6dso32_xl_usr_offset_on_wkup_get(stmdev_ctx_t *ctx,
3924 uint8_t *val)
3925 {
3926 lsm6dso32_wake_up_ths_t reg;
3927 int32_t ret;
3928
3929 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
3930 *val = reg.usr_off_on_wu;
3931
3932 return ret;
3933 }
3934
3935 /**
3936 * @brief Wake up duration event.[set]
3937 * 1LSb = 1 / ODR
3938 *
3939 * @param ctx read / write interface definitions
3940 * @param val change the values of wake_dur in reg WAKE_UP_DUR
3941 * @retval interface status (MANDATORY: return 0 -> no Error)
3942 *
3943 */
lsm6dso32_wkup_dur_set(stmdev_ctx_t * ctx,uint8_t val)3944 int32_t lsm6dso32_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
3945 {
3946 lsm6dso32_wake_up_dur_t reg;
3947 int32_t ret;
3948
3949 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
3950
3951 if (ret == 0)
3952 {
3953 reg.wake_dur = val;
3954 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
3955 }
3956
3957 return ret;
3958 }
3959
3960 /**
3961 * @brief Wake up duration event.[get]
3962 * 1LSb = 1 / ODR
3963 *
3964 * @param ctx read / write interface definitions
3965 * @param val change the values of wake_dur in reg WAKE_UP_DUR
3966 * @retval interface status (MANDATORY: return 0 -> no Error)
3967 *
3968 */
lsm6dso32_wkup_dur_get(stmdev_ctx_t * ctx,uint8_t * val)3969 int32_t lsm6dso32_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
3970 {
3971 lsm6dso32_wake_up_dur_t reg;
3972 int32_t ret;
3973
3974 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
3975 *val = reg.wake_dur;
3976
3977 return ret;
3978 }
3979
3980 /**
3981 * @}
3982 *
3983 */
3984
3985 /**
3986 * @defgroup LSM6DSO32_ Activity/Inactivity_detection
3987 * @brief This section groups all the functions concerning
3988 * activity/inactivity detection.
3989 * @{
3990 *
3991 */
3992
3993 /**
3994 * @brief Enables gyroscope Sleep mode.[set]
3995 *
3996 * @param ctx read / write interface definitions
3997 * @param val change the values of sleep_g in reg CTRL4_C
3998 * @retval interface status (MANDATORY: return 0 -> no Error)
3999 *
4000 */
lsm6dso32_gy_sleep_mode_set(stmdev_ctx_t * ctx,uint8_t val)4001 int32_t lsm6dso32_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
4002 {
4003 lsm6dso32_ctrl4_c_t reg;
4004 int32_t ret;
4005
4006 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
4007
4008 if (ret == 0)
4009 {
4010 reg.sleep_g = val;
4011 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
4012 }
4013
4014 return ret;
4015 }
4016
4017 /**
4018 * @brief Enables gyroscope Sleep mode.[get]
4019 *
4020 * @param ctx read / write interface definitions
4021 * @param val change the values of sleep_g in reg CTRL4_C
4022 * @retval interface status (MANDATORY: return 0 -> no Error)
4023 *
4024 */
lsm6dso32_gy_sleep_mode_get(stmdev_ctx_t * ctx,uint8_t * val)4025 int32_t lsm6dso32_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
4026 {
4027 lsm6dso32_ctrl4_c_t reg;
4028 int32_t ret;
4029
4030 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL4_C, (uint8_t *)®, 1);
4031 *val = reg.sleep_g;
4032
4033 return ret;
4034 }
4035
4036 /**
4037 * @brief Drives the sleep status instead of
4038 * sleep change on INT pins
4039 * (only if INT1_SLEEP_CHANGE or
4040 * INT2_SLEEP_CHANGE bits are enabled).[set]
4041 *
4042 * @param ctx read / write interface definitions
4043 * @param val change the values of sleep_status_on_int in reg TAP_CFG0
4044 * @retval interface status (MANDATORY: return 0 -> no Error)
4045 *
4046 */
lsm6dso32_act_pin_notification_set(stmdev_ctx_t * ctx,lsm6dso32_sleep_status_on_int_t val)4047 int32_t lsm6dso32_act_pin_notification_set(stmdev_ctx_t *ctx,
4048 lsm6dso32_sleep_status_on_int_t val)
4049 {
4050 lsm6dso32_tap_cfg0_t reg;
4051 int32_t ret;
4052
4053 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4054
4055 if (ret == 0)
4056 {
4057 reg.sleep_status_on_int = (uint8_t)val;
4058 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4059 }
4060
4061 return ret;
4062 }
4063
4064 /**
4065 * @brief Drives the sleep status instead of
4066 * sleep change on INT pins (only if
4067 * INT1_SLEEP_CHANGE or
4068 * INT2_SLEEP_CHANGE bits are enabled).[get]
4069 *
4070 * @param ctx read / write interface definitions
4071 * @param val Get the values of sleep_status_on_int in reg TAP_CFG0
4072 * @retval interface status (MANDATORY: return 0 -> no Error)
4073 *
4074 */
lsm6dso32_act_pin_notification_get(stmdev_ctx_t * ctx,lsm6dso32_sleep_status_on_int_t * val)4075 int32_t lsm6dso32_act_pin_notification_get(stmdev_ctx_t *ctx,
4076 lsm6dso32_sleep_status_on_int_t *val)
4077 {
4078 lsm6dso32_tap_cfg0_t reg;
4079 int32_t ret;
4080
4081 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4082
4083 switch (reg.sleep_status_on_int)
4084 {
4085 case LSM6DSO32_DRIVE_SLEEP_CHG_EVENT:
4086 *val = LSM6DSO32_DRIVE_SLEEP_CHG_EVENT;
4087 break;
4088
4089 case LSM6DSO32_DRIVE_SLEEP_STATUS:
4090 *val = LSM6DSO32_DRIVE_SLEEP_STATUS;
4091 break;
4092
4093 default:
4094 *val = LSM6DSO32_DRIVE_SLEEP_CHG_EVENT;
4095 break;
4096 }
4097
4098 return ret;
4099 }
4100
4101 /**
4102 * @brief Enable inactivity function.[set]
4103 *
4104 * @param ctx read / write interface definitions
4105 * @param val change the values of inact_en in reg TAP_CFG2
4106 * @retval interface status (MANDATORY: return 0 -> no Error)
4107 *
4108 */
lsm6dso32_act_mode_set(stmdev_ctx_t * ctx,lsm6dso32_inact_en_t val)4109 int32_t lsm6dso32_act_mode_set(stmdev_ctx_t *ctx,
4110 lsm6dso32_inact_en_t val)
4111 {
4112 lsm6dso32_tap_cfg2_t reg;
4113 int32_t ret;
4114
4115 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1);
4116
4117 if (ret == 0)
4118 {
4119 reg.inact_en = (uint8_t)val;
4120 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1);
4121 }
4122
4123 return ret;
4124 }
4125
4126 /**
4127 * @brief Enable inactivity function.[get]
4128 *
4129 * @param ctx read / write interface definitions
4130 * @param val Get the values of inact_en in reg TAP_CFG2
4131 * @retval interface status (MANDATORY: return 0 -> no Error)
4132 *
4133 */
lsm6dso32_act_mode_get(stmdev_ctx_t * ctx,lsm6dso32_inact_en_t * val)4134 int32_t lsm6dso32_act_mode_get(stmdev_ctx_t *ctx,
4135 lsm6dso32_inact_en_t *val)
4136 {
4137 lsm6dso32_tap_cfg2_t reg;
4138 int32_t ret;
4139
4140 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1);
4141
4142 switch (reg.inact_en)
4143 {
4144 case LSM6DSO32_XL_AND_GY_NOT_AFFECTED:
4145 *val = LSM6DSO32_XL_AND_GY_NOT_AFFECTED;
4146 break;
4147
4148 case LSM6DSO32_XL_12Hz5_GY_NOT_AFFECTED:
4149 *val = LSM6DSO32_XL_12Hz5_GY_NOT_AFFECTED;
4150 break;
4151
4152 case LSM6DSO32_XL_12Hz5_GY_SLEEP:
4153 *val = LSM6DSO32_XL_12Hz5_GY_SLEEP;
4154 break;
4155
4156 case LSM6DSO32_XL_12Hz5_GY_PD:
4157 *val = LSM6DSO32_XL_12Hz5_GY_PD;
4158 break;
4159
4160 default:
4161 *val = LSM6DSO32_XL_AND_GY_NOT_AFFECTED;
4162 break;
4163 }
4164
4165 return ret;
4166 }
4167
4168 /**
4169 * @brief Duration to go in sleep mode.[set]
4170 * 1 LSb = 512 / ODR
4171 *
4172 * @param ctx read / write interface definitions
4173 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
4174 * @retval interface status (MANDATORY: return 0 -> no Error)
4175 *
4176 */
lsm6dso32_act_sleep_dur_set(stmdev_ctx_t * ctx,uint8_t val)4177 int32_t lsm6dso32_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
4178 {
4179 lsm6dso32_wake_up_dur_t reg;
4180 int32_t ret;
4181
4182 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
4183
4184 if (ret == 0)
4185 {
4186 reg.sleep_dur = val;
4187 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
4188 }
4189
4190 return ret;
4191 }
4192
4193 /**
4194 * @brief Duration to go in sleep mode.[get]
4195 * 1 LSb = 512 / ODR
4196 *
4197 * @param ctx read / write interface definitions
4198 * @param val change the values of sleep_dur in reg WAKE_UP_DUR
4199 * @retval interface status (MANDATORY: return 0 -> no Error)
4200 *
4201 */
lsm6dso32_act_sleep_dur_get(stmdev_ctx_t * ctx,uint8_t * val)4202 int32_t lsm6dso32_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
4203 {
4204 lsm6dso32_wake_up_dur_t reg;
4205 int32_t ret;
4206
4207 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR, (uint8_t *)®, 1);
4208 *val = reg.sleep_dur;
4209
4210 return ret;
4211 }
4212
4213 /**
4214 * @}
4215 *
4216 */
4217
4218 /**
4219 * @defgroup LSM6DSO32_tap_generator
4220 * @brief This section groups all the functions that manage the
4221 * tap and double tap event generation.
4222 * @{
4223 *
4224 */
4225
4226 /**
4227 * @brief Enable Z direction in tap recognition.[set]
4228 *
4229 * @param ctx read / write interface definitions
4230 * @param val change the values of tap_z_en in reg TAP_CFG0
4231 * @retval interface status (MANDATORY: return 0 -> no Error)
4232 *
4233 */
lsm6dso32_tap_detection_on_z_set(stmdev_ctx_t * ctx,uint8_t val)4234 int32_t lsm6dso32_tap_detection_on_z_set(stmdev_ctx_t *ctx,
4235 uint8_t val)
4236 {
4237 lsm6dso32_tap_cfg0_t reg;
4238 int32_t ret;
4239
4240 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4241
4242 if (ret == 0)
4243 {
4244 reg.tap_z_en = val;
4245 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4246 }
4247
4248 return ret;
4249 }
4250
4251 /**
4252 * @brief Enable Z direction in tap recognition.[get]
4253 *
4254 * @param ctx read / write interface definitions
4255 * @param val change the values of tap_z_en in reg TAP_CFG0
4256 * @retval interface status (MANDATORY: return 0 -> no Error)
4257 *
4258 */
lsm6dso32_tap_detection_on_z_get(stmdev_ctx_t * ctx,uint8_t * val)4259 int32_t lsm6dso32_tap_detection_on_z_get(stmdev_ctx_t *ctx,
4260 uint8_t *val)
4261 {
4262 lsm6dso32_tap_cfg0_t reg;
4263 int32_t ret;
4264
4265 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4266 *val = reg.tap_z_en;
4267
4268 return ret;
4269 }
4270
4271 /**
4272 * @brief Enable Y direction in tap recognition.[set]
4273 *
4274 * @param ctx read / write interface definitions
4275 * @param val change the values of tap_y_en in reg TAP_CFG0
4276 * @retval interface status (MANDATORY: return 0 -> no Error)
4277 *
4278 */
lsm6dso32_tap_detection_on_y_set(stmdev_ctx_t * ctx,uint8_t val)4279 int32_t lsm6dso32_tap_detection_on_y_set(stmdev_ctx_t *ctx,
4280 uint8_t val)
4281 {
4282 lsm6dso32_tap_cfg0_t reg;
4283 int32_t ret;
4284
4285 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4286
4287 if (ret == 0)
4288 {
4289 reg.tap_y_en = val;
4290 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4291 }
4292
4293 return ret;
4294 }
4295
4296 /**
4297 * @brief Enable Y direction in tap recognition.[get]
4298 *
4299 * @param ctx read / write interface definitions
4300 * @param val change the values of tap_y_en in reg TAP_CFG0
4301 * @retval interface status (MANDATORY: return 0 -> no Error)
4302 *
4303 */
lsm6dso32_tap_detection_on_y_get(stmdev_ctx_t * ctx,uint8_t * val)4304 int32_t lsm6dso32_tap_detection_on_y_get(stmdev_ctx_t *ctx,
4305 uint8_t *val)
4306 {
4307 lsm6dso32_tap_cfg0_t reg;
4308 int32_t ret;
4309
4310 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4311 *val = reg.tap_y_en;
4312
4313 return ret;
4314 }
4315
4316 /**
4317 * @brief Enable X direction in tap recognition.[set]
4318 *
4319 * @param ctx read / write interface definitions
4320 * @param val change the values of tap_x_en in reg TAP_CFG0
4321 * @retval interface status (MANDATORY: return 0 -> no Error)
4322 *
4323 */
lsm6dso32_tap_detection_on_x_set(stmdev_ctx_t * ctx,uint8_t val)4324 int32_t lsm6dso32_tap_detection_on_x_set(stmdev_ctx_t *ctx,
4325 uint8_t val)
4326 {
4327 lsm6dso32_tap_cfg0_t reg;
4328 int32_t ret;
4329
4330 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4331
4332 if (ret == 0)
4333 {
4334 reg.tap_x_en = val;
4335 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4336 }
4337
4338 return ret;
4339 }
4340
4341 /**
4342 * @brief Enable X direction in tap recognition.[get]
4343 *
4344 * @param ctx read / write interface definitions
4345 * @param val change the values of tap_x_en in reg TAP_CFG0
4346 * @retval interface status (MANDATORY: return 0 -> no Error)
4347 *
4348 */
lsm6dso32_tap_detection_on_x_get(stmdev_ctx_t * ctx,uint8_t * val)4349 int32_t lsm6dso32_tap_detection_on_x_get(stmdev_ctx_t *ctx,
4350 uint8_t *val)
4351 {
4352 lsm6dso32_tap_cfg0_t reg;
4353 int32_t ret;
4354
4355 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG0, (uint8_t *)®, 1);
4356 *val = reg.tap_x_en;
4357
4358 return ret;
4359 }
4360
4361 /**
4362 * @brief X-axis tap recognition threshold.[set]
4363 *
4364 * @param ctx read / write interface definitions
4365 * @param val change the values of tap_ths_x in reg TAP_CFG1
4366 * @retval interface status (MANDATORY: return 0 -> no Error)
4367 *
4368 */
lsm6dso32_tap_threshold_x_set(stmdev_ctx_t * ctx,uint8_t val)4369 int32_t lsm6dso32_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
4370 {
4371 lsm6dso32_tap_cfg1_t reg;
4372 int32_t ret;
4373
4374 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1);
4375
4376 if (ret == 0)
4377 {
4378 reg.tap_ths_x = val;
4379 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1);
4380 }
4381
4382 return ret;
4383 }
4384
4385 /**
4386 * @brief X-axis tap recognition threshold.[get]
4387 *
4388 * @param ctx read / write interface definitions
4389 * @param val change the values of tap_ths_x in reg TAP_CFG1
4390 * @retval interface status (MANDATORY: return 0 -> no Error)
4391 *
4392 */
lsm6dso32_tap_threshold_x_get(stmdev_ctx_t * ctx,uint8_t * val)4393 int32_t lsm6dso32_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
4394 {
4395 lsm6dso32_tap_cfg1_t reg;
4396 int32_t ret;
4397
4398 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1);
4399 *val = reg.tap_ths_x;
4400
4401 return ret;
4402 }
4403
4404 /**
4405 * @brief Selection of axis priority for TAP detection.[set]
4406 *
4407 * @param ctx read / write interface definitions
4408 * @param val change the values of tap_priority in reg TAP_CFG1
4409 * @retval interface status (MANDATORY: return 0 -> no Error)
4410 *
4411 */
lsm6dso32_tap_axis_priority_set(stmdev_ctx_t * ctx,lsm6dso32_tap_priority_t val)4412 int32_t lsm6dso32_tap_axis_priority_set(stmdev_ctx_t *ctx,
4413 lsm6dso32_tap_priority_t val)
4414 {
4415 lsm6dso32_tap_cfg1_t reg;
4416 int32_t ret;
4417
4418 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1);
4419
4420 if (ret == 0)
4421 {
4422 reg.tap_priority = (uint8_t)val;
4423 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1);
4424 }
4425
4426 return ret;
4427 }
4428
4429 /**
4430 * @brief Selection of axis priority for TAP detection.[get]
4431 *
4432 * @param ctx read / write interface definitions
4433 * @param val Get the values of tap_priority in reg TAP_CFG1
4434 * @retval interface status (MANDATORY: return 0 -> no Error)
4435 *
4436 */
lsm6dso32_tap_axis_priority_get(stmdev_ctx_t * ctx,lsm6dso32_tap_priority_t * val)4437 int32_t lsm6dso32_tap_axis_priority_get(stmdev_ctx_t *ctx,
4438 lsm6dso32_tap_priority_t *val)
4439 {
4440 lsm6dso32_tap_cfg1_t reg;
4441 int32_t ret;
4442
4443 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG1, (uint8_t *)®, 1);
4444
4445 switch (reg.tap_priority)
4446 {
4447 case LSM6DSO32_XYZ:
4448 *val = LSM6DSO32_XYZ;
4449 break;
4450
4451 case LSM6DSO32_YXZ:
4452 *val = LSM6DSO32_YXZ;
4453 break;
4454
4455 case LSM6DSO32_XZY:
4456 *val = LSM6DSO32_XZY;
4457 break;
4458
4459 case LSM6DSO32_ZYX:
4460 *val = LSM6DSO32_ZYX;
4461 break;
4462
4463 case LSM6DSO32_YZX:
4464 *val = LSM6DSO32_YZX;
4465 break;
4466
4467 case LSM6DSO32_ZXY:
4468 *val = LSM6DSO32_ZXY;
4469 break;
4470
4471 default:
4472 *val = LSM6DSO32_XYZ;
4473 break;
4474 }
4475
4476 return ret;
4477 }
4478
4479 /**
4480 * @brief Y-axis tap recognition threshold.[set]
4481 *
4482 * @param ctx read / write interface definitions
4483 * @param val change the values of tap_ths_y in reg TAP_CFG2
4484 * @retval interface status (MANDATORY: return 0 -> no Error)
4485 *
4486 */
lsm6dso32_tap_threshold_y_set(stmdev_ctx_t * ctx,uint8_t val)4487 int32_t lsm6dso32_tap_threshold_y_set(stmdev_ctx_t *ctx, uint8_t val)
4488 {
4489 lsm6dso32_tap_cfg2_t reg;
4490 int32_t ret;
4491
4492 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1);
4493
4494 if (ret == 0)
4495 {
4496 reg.tap_ths_y = val;
4497 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1);
4498 }
4499
4500 return ret;
4501 }
4502
4503 /**
4504 * @brief Y-axis tap recognition threshold.[get]
4505 *
4506 * @param ctx read / write interface definitions
4507 * @param val change the values of tap_ths_y in reg TAP_CFG2
4508 * @retval interface status (MANDATORY: return 0 -> no Error)
4509 *
4510 */
lsm6dso32_tap_threshold_y_get(stmdev_ctx_t * ctx,uint8_t * val)4511 int32_t lsm6dso32_tap_threshold_y_get(stmdev_ctx_t *ctx, uint8_t *val)
4512 {
4513 lsm6dso32_tap_cfg2_t reg;
4514 int32_t ret;
4515
4516 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_CFG2, (uint8_t *)®, 1);
4517 *val = reg.tap_ths_y;
4518
4519 return ret;
4520 }
4521
4522 /**
4523 * @brief Z-axis recognition threshold.[set]
4524 *
4525 * @param ctx read / write interface definitions
4526 * @param val change the values of tap_ths_z in reg TAP_THS_6D
4527 * @retval interface status (MANDATORY: return 0 -> no Error)
4528 *
4529 */
lsm6dso32_tap_threshold_z_set(stmdev_ctx_t * ctx,uint8_t val)4530 int32_t lsm6dso32_tap_threshold_z_set(stmdev_ctx_t *ctx, uint8_t val)
4531 {
4532 lsm6dso32_tap_ths_6d_t reg;
4533 int32_t ret;
4534
4535 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
4536
4537 if (ret == 0)
4538 {
4539 reg.tap_ths_z = val;
4540 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
4541 }
4542
4543 return ret;
4544 }
4545
4546 /**
4547 * @brief Z-axis recognition threshold.[get]
4548 *
4549 * @param ctx read / write interface definitions
4550 * @param val change the values of tap_ths_z in reg TAP_THS_6D
4551 * @retval interface status (MANDATORY: return 0 -> no Error)
4552 *
4553 */
lsm6dso32_tap_threshold_z_get(stmdev_ctx_t * ctx,uint8_t * val)4554 int32_t lsm6dso32_tap_threshold_z_get(stmdev_ctx_t *ctx, uint8_t *val)
4555 {
4556 lsm6dso32_tap_ths_6d_t reg;
4557 int32_t ret;
4558
4559 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
4560 *val = reg.tap_ths_z;
4561
4562 return ret;
4563 }
4564
4565 /**
4566 * @brief Maximum duration is the maximum time of an
4567 * over threshold signal detection to be recognized
4568 * as a tap event. The default value of these bits
4569 * is 00b which corresponds to 4*ODR_XL time.
4570 * If the SHOCK[1:0] bits are set to a different
4571 * value, 1LSB corresponds to 8*ODR_XL time.[set]
4572 *
4573 * @param ctx read / write interface definitions
4574 * @param val change the values of shock in reg INT_DUR2
4575 * @retval interface status (MANDATORY: return 0 -> no Error)
4576 *
4577 */
lsm6dso32_tap_shock_set(stmdev_ctx_t * ctx,uint8_t val)4578 int32_t lsm6dso32_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
4579 {
4580 lsm6dso32_int_dur2_t reg;
4581 int32_t ret;
4582
4583 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
4584
4585 if (ret == 0)
4586 {
4587 reg.shock = val;
4588 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
4589 }
4590
4591 return ret;
4592 }
4593
4594 /**
4595 * @brief Maximum duration is the maximum time of an
4596 * over threshold signal detection to be recognized
4597 * as a tap event. The default value of these bits
4598 * is 00b which corresponds to 4*ODR_XL time.
4599 * If the SHOCK[1:0] bits are set to a different
4600 * value, 1LSB corresponds to 8*ODR_XL time.[get]
4601 *
4602 * @param ctx read / write interface definitions
4603 * @param val change the values of shock in reg INT_DUR2
4604 * @retval interface status (MANDATORY: return 0 -> no Error)
4605 *
4606 */
lsm6dso32_tap_shock_get(stmdev_ctx_t * ctx,uint8_t * val)4607 int32_t lsm6dso32_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
4608 {
4609 lsm6dso32_int_dur2_t reg;
4610 int32_t ret;
4611
4612 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
4613 *val = reg.shock;
4614
4615 return ret;
4616 }
4617
4618 /**
4619 * @brief Quiet time is the time after the first detected
4620 * tap in which there must not be any over threshold
4621 * event.
4622 * The default value of these bits is 00b which
4623 * corresponds to 2*ODR_XL time. If the QUIET[1:0]
4624 * bits are set to a different value,
4625 * 1LSB corresponds to 4*ODR_XL time.[set]
4626 *
4627 * @param ctx read / write interface definitions
4628 * @param val change the values of quiet in reg INT_DUR2
4629 * @retval interface status (MANDATORY: return 0 -> no Error)
4630 *
4631 */
lsm6dso32_tap_quiet_set(stmdev_ctx_t * ctx,uint8_t val)4632 int32_t lsm6dso32_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
4633 {
4634 lsm6dso32_int_dur2_t reg;
4635 int32_t ret;
4636
4637 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
4638
4639 if (ret == 0)
4640 {
4641 reg.quiet = val;
4642 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
4643 }
4644
4645 return ret;
4646 }
4647
4648 /**
4649 * @brief Quiet time is the time after the first detected
4650 * tap in which there must not be any over threshold
4651 * event.
4652 * The default value of these bits is 00b which
4653 * corresponds to 2*ODR_XL time.
4654 * If the QUIET[1:0] bits are set to a different
4655 * value, 1LSB corresponds to 4*ODR_XL time.[get]
4656 *
4657 * @param ctx read / write interface definitions
4658 * @param val change the values of quiet in reg INT_DUR2
4659 * @retval interface status (MANDATORY: return 0 -> no Error)
4660 *
4661 */
lsm6dso32_tap_quiet_get(stmdev_ctx_t * ctx,uint8_t * val)4662 int32_t lsm6dso32_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
4663 {
4664 lsm6dso32_int_dur2_t reg;
4665 int32_t ret;
4666
4667 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
4668 *val = reg.quiet;
4669
4670 return ret;
4671 }
4672
4673 /**
4674 * @brief When double tap recognition is enabled,
4675 * this register expresses the maximum time
4676 * between two consecutive detected taps to
4677 * determine a double tap event.
4678 * The default value of these bits is 0000b which
4679 * corresponds to 16*ODR_XL time.
4680 * If the DUR[3:0] bits are set to a different value,
4681 * 1LSB corresponds to 32*ODR_XL time.[set]
4682 *
4683 * @param ctx read / write interface definitions
4684 * @param val change the values of dur in reg INT_DUR2
4685 * @retval interface status (MANDATORY: return 0 -> no Error)
4686 *
4687 */
lsm6dso32_tap_dur_set(stmdev_ctx_t * ctx,uint8_t val)4688 int32_t lsm6dso32_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
4689 {
4690 lsm6dso32_int_dur2_t reg;
4691 int32_t ret;
4692
4693 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
4694
4695 if (ret == 0)
4696 {
4697 reg.dur = val;
4698 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
4699 }
4700
4701 return ret;
4702 }
4703
4704 /**
4705 * @brief When double tap recognition is enabled,
4706 * this register expresses the maximum time
4707 * between two consecutive detected taps to
4708 * determine a double tap event.
4709 * The default value of these bits is 0000b which
4710 * corresponds to 16*ODR_XL time. If the DUR[3:0]
4711 * bits are set to a different value,
4712 * 1LSB corresponds to 32*ODR_XL time.[get]
4713 *
4714 * @param ctx read / write interface definitions
4715 * @param val change the values of dur in reg INT_DUR2
4716 * @retval interface status (MANDATORY: return 0 -> no Error)
4717 *
4718 */
lsm6dso32_tap_dur_get(stmdev_ctx_t * ctx,uint8_t * val)4719 int32_t lsm6dso32_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
4720 {
4721 lsm6dso32_int_dur2_t reg;
4722 int32_t ret;
4723
4724 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_INT_DUR2, (uint8_t *)®, 1);
4725 *val = reg.dur;
4726
4727 return ret;
4728 }
4729
4730 /**
4731 * @brief Single/double-tap event enable.[set]
4732 *
4733 * @param ctx read / write interface definitions
4734 * @param val change the values of single_double_tap in reg WAKE_UP_THS
4735 * @retval interface status (MANDATORY: return 0 -> no Error)
4736 *
4737 */
lsm6dso32_tap_mode_set(stmdev_ctx_t * ctx,lsm6dso32_single_double_tap_t val)4738 int32_t lsm6dso32_tap_mode_set(stmdev_ctx_t *ctx,
4739 lsm6dso32_single_double_tap_t val)
4740 {
4741 lsm6dso32_wake_up_ths_t reg;
4742 int32_t ret;
4743
4744 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
4745
4746 if (ret == 0)
4747 {
4748 reg.single_double_tap = (uint8_t)val;
4749 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
4750 }
4751
4752 return ret;
4753 }
4754
4755 /**
4756 * @brief Single/double-tap event enable.[get]
4757 *
4758 * @param ctx read / write interface definitions
4759 * @param val Get the values of single_double_tap in reg WAKE_UP_THS
4760 * @retval interface status (MANDATORY: return 0 -> no Error)
4761 *
4762 */
lsm6dso32_tap_mode_get(stmdev_ctx_t * ctx,lsm6dso32_single_double_tap_t * val)4763 int32_t lsm6dso32_tap_mode_get(stmdev_ctx_t *ctx,
4764 lsm6dso32_single_double_tap_t *val)
4765 {
4766 lsm6dso32_wake_up_ths_t reg;
4767 int32_t ret;
4768
4769 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_THS, (uint8_t *)®, 1);
4770
4771 switch (reg.single_double_tap)
4772 {
4773 case LSM6DSO32_ONLY_SINGLE:
4774 *val = LSM6DSO32_ONLY_SINGLE;
4775 break;
4776
4777 case LSM6DSO32_BOTH_SINGLE_DOUBLE:
4778 *val = LSM6DSO32_BOTH_SINGLE_DOUBLE;
4779 break;
4780
4781 default:
4782 *val = LSM6DSO32_ONLY_SINGLE;
4783 break;
4784 }
4785
4786 return ret;
4787 }
4788
4789 /**
4790 * @}
4791 *
4792 */
4793
4794 /**
4795 * @defgroup LSM6DSO32_ Six_position_detection(6D/4D)
4796 * @brief This section groups all the functions concerning six position
4797 * detection (6D).
4798 * @{
4799 *
4800 */
4801
4802 /**
4803 * @brief Threshold for 4D/6D function.[set]
4804 *
4805 * @param ctx read / write interface definitions
4806 * @param val change the values of sixd_ths in reg TAP_THS_6D
4807 * @retval interface status (MANDATORY: return 0 -> no Error)
4808 *
4809 */
lsm6dso32_6d_threshold_set(stmdev_ctx_t * ctx,lsm6dso32_sixd_ths_t val)4810 int32_t lsm6dso32_6d_threshold_set(stmdev_ctx_t *ctx,
4811 lsm6dso32_sixd_ths_t val)
4812 {
4813 lsm6dso32_tap_ths_6d_t reg;
4814 int32_t ret;
4815
4816 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
4817
4818 if (ret == 0)
4819 {
4820 reg.sixd_ths = (uint8_t)val;
4821 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
4822 }
4823
4824 return ret;
4825 }
4826
4827 /**
4828 * @brief Threshold for 4D/6D function.[get]
4829 *
4830 * @param ctx read / write interface definitions
4831 * @param val Get the values of sixd_ths in reg TAP_THS_6D
4832 * @retval interface status (MANDATORY: return 0 -> no Error)
4833 *
4834 */
lsm6dso32_6d_threshold_get(stmdev_ctx_t * ctx,lsm6dso32_sixd_ths_t * val)4835 int32_t lsm6dso32_6d_threshold_get(stmdev_ctx_t *ctx,
4836 lsm6dso32_sixd_ths_t *val)
4837 {
4838 lsm6dso32_tap_ths_6d_t reg;
4839 int32_t ret;
4840
4841 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
4842
4843 switch (reg.sixd_ths)
4844 {
4845 case LSM6DSO32_DEG_68:
4846 *val = LSM6DSO32_DEG_68;
4847 break;
4848
4849 case LSM6DSO32_DEG_47:
4850 *val = LSM6DSO32_DEG_47;
4851 break;
4852
4853 default:
4854 *val = LSM6DSO32_DEG_68;
4855 break;
4856 }
4857
4858 return ret;
4859 }
4860
4861 /**
4862 * @brief 4D orientation detection enable.[set]
4863 *
4864 * @param ctx read / write interface definitions
4865 * @param val change the values of d4d_en in reg TAP_THS_6D
4866 * @retval interface status (MANDATORY: return 0 -> no Error)
4867 *
4868 */
lsm6dso32_4d_mode_set(stmdev_ctx_t * ctx,uint8_t val)4869 int32_t lsm6dso32_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
4870 {
4871 lsm6dso32_tap_ths_6d_t reg;
4872 int32_t ret;
4873
4874 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
4875
4876 if (ret == 0)
4877 {
4878 reg.d4d_en = val;
4879 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
4880 }
4881
4882 return ret;
4883 }
4884
4885 /**
4886 * @brief 4D orientation detection enable.[get]
4887 *
4888 * @param ctx read / write interface definitions
4889 * @param val change the values of d4d_en in reg TAP_THS_6D
4890 * @retval interface status (MANDATORY: return 0 -> no Error)
4891 *
4892 */
lsm6dso32_4d_mode_get(stmdev_ctx_t * ctx,uint8_t * val)4893 int32_t lsm6dso32_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
4894 {
4895 lsm6dso32_tap_ths_6d_t reg;
4896 int32_t ret;
4897
4898 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_TAP_THS_6D, (uint8_t *)®, 1);
4899 *val = reg.d4d_en;
4900
4901 return ret;
4902 }
4903
4904 /**
4905 * @}
4906 *
4907 */
4908
4909 /**
4910 * @defgroup LSM6DSO32_free_fall
4911 * @brief This section group all the functions concerning the free
4912 * fall detection.
4913 * @{
4914 *
4915 */
4916
4917 /**
4918 * @brief Free fall threshold setting.[set]
4919 *
4920 * @param ctx read / write interface definitions
4921 * @param val change the values of ff_ths in reg FREE_FALL
4922 * @retval interface status (MANDATORY: return 0 -> no Error)
4923 *
4924 */
lsm6dso32_ff_threshold_set(stmdev_ctx_t * ctx,lsm6dso32_ff_ths_t val)4925 int32_t lsm6dso32_ff_threshold_set(stmdev_ctx_t *ctx,
4926 lsm6dso32_ff_ths_t val)
4927 {
4928 lsm6dso32_free_fall_t reg;
4929 int32_t ret;
4930
4931 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FREE_FALL, (uint8_t *)®, 1);
4932
4933 if (ret == 0)
4934 {
4935 reg.ff_ths = (uint8_t)val;
4936 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FREE_FALL, (uint8_t *)®, 1);
4937 }
4938
4939 return ret;
4940 }
4941
4942 /**
4943 * @brief Free fall threshold setting.[get]
4944 *
4945 * @param ctx read / write interface definitions
4946 * @param val Get the values of ff_ths in reg FREE_FALL
4947 * @retval interface status (MANDATORY: return 0 -> no Error)
4948 *
4949 */
lsm6dso32_ff_threshold_get(stmdev_ctx_t * ctx,lsm6dso32_ff_ths_t * val)4950 int32_t lsm6dso32_ff_threshold_get(stmdev_ctx_t *ctx,
4951 lsm6dso32_ff_ths_t *val)
4952 {
4953 lsm6dso32_free_fall_t reg;
4954 int32_t ret;
4955
4956 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FREE_FALL, (uint8_t *)®, 1);
4957
4958 switch (reg.ff_ths)
4959 {
4960 case LSM6DSO32_FF_TSH_312mg:
4961 *val = LSM6DSO32_FF_TSH_312mg;
4962 break;
4963
4964 case LSM6DSO32_FF_TSH_438mg:
4965 *val = LSM6DSO32_FF_TSH_438mg;
4966 break;
4967
4968 case LSM6DSO32_FF_TSH_500mg:
4969 *val = LSM6DSO32_FF_TSH_500mg;
4970 break;
4971
4972 default:
4973 *val = LSM6DSO32_FF_TSH_312mg;
4974 break;
4975 }
4976
4977 return ret;
4978 }
4979
4980 /**
4981 * @brief Free-fall duration event.[set]
4982 * 1LSb = 1 / ODR
4983 *
4984 * @param ctx read / write interface definitions
4985 * @param val change the values of ff_dur in reg FREE_FALL
4986 * @retval interface status (MANDATORY: return 0 -> no Error)
4987 *
4988 */
lsm6dso32_ff_dur_set(stmdev_ctx_t * ctx,uint8_t val)4989 int32_t lsm6dso32_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
4990 {
4991 lsm6dso32_wake_up_dur_t wake_up_dur;
4992 lsm6dso32_free_fall_t free_fall;
4993 int32_t ret;
4994
4995 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR,
4996 (uint8_t *)&wake_up_dur, 1);
4997
4998 if (ret == 0)
4999 {
5000 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FREE_FALL,
5001 (uint8_t *)&free_fall, 1);
5002 }
5003
5004 if (ret == 0)
5005 {
5006 wake_up_dur.ff_dur = ((uint8_t)val & 0x20U) >> 5;
5007 free_fall.ff_dur = (uint8_t)val & 0x1FU;
5008 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_WAKE_UP_DUR,
5009 (uint8_t *)&wake_up_dur, 1);
5010 }
5011
5012 if (ret == 0)
5013 {
5014 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FREE_FALL,
5015 (uint8_t *)&free_fall, 1);
5016 }
5017
5018 return ret;
5019 }
5020
5021 /**
5022 * @brief Free-fall duration event.[get]
5023 * 1LSb = 1 / ODR
5024 *
5025 * @param ctx read / write interface definitions
5026 * @param val change the values of ff_dur in reg FREE_FALL
5027 * @retval interface status (MANDATORY: return 0 -> no Error)
5028 *
5029 */
lsm6dso32_ff_dur_get(stmdev_ctx_t * ctx,uint8_t * val)5030 int32_t lsm6dso32_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
5031 {
5032 lsm6dso32_wake_up_dur_t wake_up_dur;
5033 lsm6dso32_free_fall_t free_fall;
5034 int32_t ret;
5035
5036 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_WAKE_UP_DUR,
5037 (uint8_t *)&wake_up_dur, 1);
5038
5039 if (ret == 0)
5040 {
5041 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FREE_FALL,
5042 (uint8_t *)&free_fall, 1);
5043 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
5044 }
5045
5046 return ret;
5047 }
5048
5049 /**
5050 * @}
5051 *
5052 */
5053
5054 /**
5055 * @defgroup LSM6DSO32_fifo
5056 * @brief This section group all the functions concerning the fifo usage
5057 * @{
5058 *
5059 */
5060
5061 /**
5062 * @brief FIFO watermark level selection.[set]
5063 *
5064 * @param ctx read / write interface definitions
5065 * @param val change the values of wtm in reg FIFO_CTRL1
5066 * @retval interface status (MANDATORY: return 0 -> no Error)
5067 *
5068 */
lsm6dso32_fifo_watermark_set(stmdev_ctx_t * ctx,uint16_t val)5069 int32_t lsm6dso32_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
5070 {
5071 lsm6dso32_fifo_ctrl1_t fifo_ctrl1;
5072 lsm6dso32_fifo_ctrl2_t fifo_ctrl2;
5073 int32_t ret;
5074
5075 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2,
5076 (uint8_t *)&fifo_ctrl2, 1);
5077
5078 if (ret == 0)
5079 {
5080 fifo_ctrl1.wtm = 0x00FFU & (uint8_t)val;
5081 fifo_ctrl2.wtm = (uint8_t)((0x0100U & val) >> 8);
5082 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL1,
5083 (uint8_t *)&fifo_ctrl1, 1);
5084 }
5085
5086 if (ret == 0)
5087 {
5088 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL2,
5089 (uint8_t *)&fifo_ctrl2, 1);
5090 }
5091
5092 return ret;
5093 }
5094
5095 /**
5096 * @brief FIFO watermark level selection.[get]
5097 *
5098 * @param ctx read / write interface definitions
5099 * @param val change the values of wtm in reg FIFO_CTRL1
5100 * @retval interface status (MANDATORY: return 0 -> no Error)
5101 *
5102 */
lsm6dso32_fifo_watermark_get(stmdev_ctx_t * ctx,uint16_t * val)5103 int32_t lsm6dso32_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
5104 {
5105 lsm6dso32_fifo_ctrl1_t fifo_ctrl1;
5106 lsm6dso32_fifo_ctrl2_t fifo_ctrl2;
5107 int32_t ret;
5108
5109 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL1,
5110 (uint8_t *)&fifo_ctrl1, 1);
5111
5112 if (ret == 0)
5113 {
5114 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2,
5115 (uint8_t *)&fifo_ctrl2, 1);
5116 *val = ((uint16_t)fifo_ctrl2.wtm << 8) + (uint16_t)fifo_ctrl1.wtm;
5117 }
5118
5119 return ret;
5120 }
5121
5122 /**
5123 * @brief FIFO compression feature initialization request [set].
5124 *
5125 * @param ctx read / write interface definitions
5126 * @param val change the values of FIFO_COMPR_INIT in
5127 * reg EMB_FUNC_INIT_B
5128 * @retval interface status (MANDATORY: return 0 -> no Error)
5129 *
5130 */
lsm6dso32_compression_algo_init_set(stmdev_ctx_t * ctx,uint8_t val)5131 int32_t lsm6dso32_compression_algo_init_set(stmdev_ctx_t *ctx,
5132 uint8_t val)
5133 {
5134 lsm6dso32_emb_func_init_b_t reg;
5135 int32_t ret;
5136
5137 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
5138
5139 if (ret == 0)
5140 {
5141 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INIT_B,
5142 (uint8_t *)®, 1);
5143 }
5144
5145 if (ret == 0)
5146 {
5147 reg.fifo_compr_init = val;
5148 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_INIT_B,
5149 (uint8_t *)®, 1);
5150 }
5151
5152 if (ret == 0)
5153 {
5154 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
5155 }
5156
5157 return ret;
5158 }
5159
5160 /**
5161 * @brief FIFO compression feature initialization request [get].
5162 *
5163 * @param ctx read / write interface definitions
5164 * @param val change the values of FIFO_COMPR_INIT in
5165 * reg EMB_FUNC_INIT_B
5166 * @retval interface status (MANDATORY: return 0 -> no Error)
5167 *
5168 */
lsm6dso32_compression_algo_init_get(stmdev_ctx_t * ctx,uint8_t * val)5169 int32_t lsm6dso32_compression_algo_init_get(stmdev_ctx_t *ctx,
5170 uint8_t *val)
5171 {
5172 lsm6dso32_emb_func_init_b_t reg;
5173 int32_t ret;
5174
5175 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
5176
5177 if (ret == 0)
5178 {
5179 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INIT_B,
5180 (uint8_t *)®, 1);
5181 }
5182
5183 if (ret == 0)
5184 {
5185 *val = reg.fifo_compr_init;
5186 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
5187 }
5188
5189 return ret;
5190 }
5191
5192 /**
5193 * @brief Enable and configure compression algo.[set]
5194 *
5195 * @param ctx read / write interface definitions
5196 * @param val change the values of uncoptr_rate in
5197 * reg FIFO_CTRL2
5198 * @retval interface status (MANDATORY: return 0 -> no Error)
5199 *
5200 */
lsm6dso32_compression_algo_set(stmdev_ctx_t * ctx,lsm6dso32_uncoptr_rate_t val)5201 int32_t lsm6dso32_compression_algo_set(stmdev_ctx_t *ctx,
5202 lsm6dso32_uncoptr_rate_t val)
5203 {
5204 lsm6dso32_emb_func_en_b_t emb_func_en_b;
5205 lsm6dso32_fifo_ctrl2_t fifo_ctrl2;
5206 int32_t ret;
5207
5208 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
5209
5210 if (ret == 0)
5211 {
5212 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
5213 (uint8_t *)&emb_func_en_b, 1);
5214 }
5215
5216 if (ret == 0)
5217 {
5218 emb_func_en_b.fifo_compr_en = ((uint8_t)val & 0x04U) >> 2;
5219 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
5220 (uint8_t *)&emb_func_en_b, 1);
5221 }
5222
5223 if (ret == 0)
5224 {
5225 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
5226 }
5227
5228 if (ret == 0)
5229 {
5230 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2,
5231 (uint8_t *)&fifo_ctrl2, 1);
5232 }
5233
5234 if (ret == 0)
5235 {
5236 fifo_ctrl2.fifo_compr_rt_en = ((uint8_t)val & 0x04U) >> 2;
5237 fifo_ctrl2.uncoptr_rate = (uint8_t)val & 0x03U;
5238 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL2,
5239 (uint8_t *)&fifo_ctrl2, 1);
5240 }
5241
5242 return ret;
5243 }
5244
5245 /**
5246 * @brief Enable and configure compression algo.[get]
5247 *
5248 * @param ctx read / write interface definitions
5249 * @param val Get the values of uncoptr_rate in
5250 * reg FIFO_CTRL2
5251 * @retval interface status (MANDATORY: return 0 -> no Error)
5252 *
5253 */
lsm6dso32_compression_algo_get(stmdev_ctx_t * ctx,lsm6dso32_uncoptr_rate_t * val)5254 int32_t lsm6dso32_compression_algo_get(stmdev_ctx_t *ctx,
5255 lsm6dso32_uncoptr_rate_t *val)
5256 {
5257 lsm6dso32_fifo_ctrl2_t reg;
5258 int32_t ret;
5259
5260 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5261
5262 switch ((reg.fifo_compr_rt_en << 2) | reg.uncoptr_rate)
5263 {
5264 case LSM6DSO32_CMP_DISABLE:
5265 *val = LSM6DSO32_CMP_DISABLE;
5266 break;
5267
5268 case LSM6DSO32_CMP_ALWAYS:
5269 *val = LSM6DSO32_CMP_ALWAYS;
5270 break;
5271
5272 case LSM6DSO32_CMP_8_TO_1:
5273 *val = LSM6DSO32_CMP_8_TO_1;
5274 break;
5275
5276 case LSM6DSO32_CMP_16_TO_1:
5277 *val = LSM6DSO32_CMP_16_TO_1;
5278 break;
5279
5280 case LSM6DSO32_CMP_32_TO_1:
5281 *val = LSM6DSO32_CMP_32_TO_1;
5282 break;
5283
5284 default:
5285 *val = LSM6DSO32_CMP_DISABLE;
5286 break;
5287 }
5288
5289 return ret;
5290 }
5291
5292 /**
5293 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[set]
5294 *
5295 * @param ctx read / write interface definitions
5296 * @param val change the values of odrchg_en in reg FIFO_CTRL2
5297 * @retval interface status (MANDATORY: return 0 -> no Error)
5298 *
5299 */
lsm6dso32_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t * ctx,uint8_t val)5300 int32_t lsm6dso32_fifo_virtual_sens_odr_chg_set(stmdev_ctx_t *ctx,
5301 uint8_t val)
5302 {
5303 lsm6dso32_fifo_ctrl2_t reg;
5304 int32_t ret;
5305
5306 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5307
5308 if (ret == 0)
5309 {
5310 reg.odrchg_en = val;
5311 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5312 }
5313
5314 return ret;
5315 }
5316
5317 /**
5318 * @brief Enables ODR CHANGE virtual sensor to be batched in FIFO.[get]
5319 *
5320 * @param ctx read / write interface definitions
5321 * @param val change the values of odrchg_en in reg FIFO_CTRL2
5322 * @retval interface status (MANDATORY: return 0 -> no Error)
5323 *
5324 */
lsm6dso32_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t * ctx,uint8_t * val)5325 int32_t lsm6dso32_fifo_virtual_sens_odr_chg_get(stmdev_ctx_t *ctx,
5326 uint8_t *val)
5327 {
5328 lsm6dso32_fifo_ctrl2_t reg;
5329 int32_t ret;
5330
5331 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5332 *val = reg.odrchg_en;
5333
5334 return ret;
5335 }
5336
5337 /**
5338 * @brief Enables/Disables compression algorithm runtime.[set]
5339 *
5340 * @param ctx read / write interface definitions
5341 * @param val change the values of fifo_compr_rt_en in
5342 * reg FIFO_CTRL2
5343 * @retval interface status (MANDATORY: return 0 -> no Error)
5344 *
5345 */
lsm6dso32_compression_algo_real_time_set(stmdev_ctx_t * ctx,uint8_t val)5346 int32_t lsm6dso32_compression_algo_real_time_set(stmdev_ctx_t *ctx,
5347 uint8_t val)
5348 {
5349 lsm6dso32_fifo_ctrl2_t reg;
5350 int32_t ret;
5351
5352 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5353
5354 if (ret == 0)
5355 {
5356 reg.fifo_compr_rt_en = val;
5357 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5358 }
5359
5360 return ret;
5361 }
5362
5363 /**
5364 * @brief Enables/Disables compression algorithm runtime.[get]
5365 *
5366 * @param ctx read / write interface definitions
5367 * @param val change the values of fifo_compr_rt_en in reg FIFO_CTRL2
5368 * @retval interface status (MANDATORY: return 0 -> no Error)
5369 *
5370 */
lsm6dso32_compression_algo_real_time_get(stmdev_ctx_t * ctx,uint8_t * val)5371 int32_t lsm6dso32_compression_algo_real_time_get(stmdev_ctx_t *ctx,
5372 uint8_t *val)
5373 {
5374 lsm6dso32_fifo_ctrl2_t reg;
5375 int32_t ret;
5376
5377 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5378 *val = reg.fifo_compr_rt_en;
5379
5380 return ret;
5381 }
5382
5383 /**
5384 * @brief Sensing chain FIFO stop values memorization at
5385 * threshold level.[set]
5386 *
5387 * @param ctx read / write interface definitions
5388 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2
5389 * @retval interface status (MANDATORY: return 0 -> no Error)
5390 *
5391 */
lsm6dso32_fifo_stop_on_wtm_set(stmdev_ctx_t * ctx,uint8_t val)5392 int32_t lsm6dso32_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
5393 {
5394 lsm6dso32_fifo_ctrl2_t reg;
5395 int32_t ret;
5396
5397 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5398
5399 if (ret == 0)
5400 {
5401 reg.stop_on_wtm = val;
5402 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5403 }
5404
5405 return ret;
5406 }
5407
5408 /**
5409 * @brief Sensing chain FIFO stop values memorization at
5410 * threshold level.[get]
5411 *
5412 * @param ctx read / write interface definitions
5413 * @param val change the values of stop_on_wtm in reg FIFO_CTRL2
5414 * @retval interface status (MANDATORY: return 0 -> no Error)
5415 *
5416 */
lsm6dso32_fifo_stop_on_wtm_get(stmdev_ctx_t * ctx,uint8_t * val)5417 int32_t lsm6dso32_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx,
5418 uint8_t *val)
5419 {
5420 lsm6dso32_fifo_ctrl2_t reg;
5421 int32_t ret;
5422
5423 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL2, (uint8_t *)®, 1);
5424 *val = reg.stop_on_wtm;
5425
5426 return ret;
5427 }
5428
5429 /**
5430 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5431 * for accelerometer data.[set]
5432 *
5433 * @param ctx read / write interface definitions
5434 * @param val change the values of bdr_xl in reg FIFO_CTRL3
5435 * @retval interface status (MANDATORY: return 0 -> no Error)
5436 *
5437 */
lsm6dso32_fifo_xl_batch_set(stmdev_ctx_t * ctx,lsm6dso32_bdr_xl_t val)5438 int32_t lsm6dso32_fifo_xl_batch_set(stmdev_ctx_t *ctx,
5439 lsm6dso32_bdr_xl_t val)
5440 {
5441 lsm6dso32_fifo_ctrl3_t reg;
5442 int32_t ret;
5443
5444 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1);
5445
5446 if (ret == 0)
5447 {
5448 reg.bdr_xl = (uint8_t)val;
5449 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1);
5450 }
5451
5452 return ret;
5453 }
5454
5455 /**
5456 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5457 * for accelerometer data.[get]
5458 *
5459 * @param ctx read / write interface definitions
5460 * @param val Get the values of bdr_xl in reg FIFO_CTRL3
5461 * @retval interface status (MANDATORY: return 0 -> no Error)
5462 *
5463 */
lsm6dso32_fifo_xl_batch_get(stmdev_ctx_t * ctx,lsm6dso32_bdr_xl_t * val)5464 int32_t lsm6dso32_fifo_xl_batch_get(stmdev_ctx_t *ctx,
5465 lsm6dso32_bdr_xl_t *val)
5466 {
5467 lsm6dso32_fifo_ctrl3_t reg;
5468 int32_t ret;
5469
5470 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1);
5471
5472 switch (reg.bdr_xl)
5473 {
5474 case LSM6DSO32_XL_NOT_BATCHED:
5475 *val = LSM6DSO32_XL_NOT_BATCHED;
5476 break;
5477
5478 case LSM6DSO32_XL_BATCHED_AT_12Hz5:
5479 *val = LSM6DSO32_XL_BATCHED_AT_12Hz5;
5480 break;
5481
5482 case LSM6DSO32_XL_BATCHED_AT_26Hz:
5483 *val = LSM6DSO32_XL_BATCHED_AT_26Hz;
5484 break;
5485
5486 case LSM6DSO32_XL_BATCHED_AT_52Hz:
5487 *val = LSM6DSO32_XL_BATCHED_AT_52Hz;
5488 break;
5489
5490 case LSM6DSO32_XL_BATCHED_AT_104Hz:
5491 *val = LSM6DSO32_XL_BATCHED_AT_104Hz;
5492 break;
5493
5494 case LSM6DSO32_XL_BATCHED_AT_208Hz:
5495 *val = LSM6DSO32_XL_BATCHED_AT_208Hz;
5496 break;
5497
5498 case LSM6DSO32_XL_BATCHED_AT_417Hz:
5499 *val = LSM6DSO32_XL_BATCHED_AT_417Hz;
5500 break;
5501
5502 case LSM6DSO32_XL_BATCHED_AT_833Hz:
5503 *val = LSM6DSO32_XL_BATCHED_AT_833Hz;
5504 break;
5505
5506 case LSM6DSO32_XL_BATCHED_AT_1667Hz:
5507 *val = LSM6DSO32_XL_BATCHED_AT_1667Hz;
5508 break;
5509
5510 case LSM6DSO32_XL_BATCHED_AT_3333Hz:
5511 *val = LSM6DSO32_XL_BATCHED_AT_3333Hz;
5512 break;
5513
5514 case LSM6DSO32_XL_BATCHED_AT_6667Hz:
5515 *val = LSM6DSO32_XL_BATCHED_AT_6667Hz;
5516 break;
5517
5518 case LSM6DSO32_XL_BATCHED_AT_6Hz5:
5519 *val = LSM6DSO32_XL_BATCHED_AT_6Hz5;
5520 break;
5521
5522 default:
5523 *val = LSM6DSO32_XL_NOT_BATCHED;
5524 break;
5525 }
5526
5527 return ret;
5528 }
5529
5530 /**
5531 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5532 * for gyroscope data.[set]
5533 *
5534 * @param ctx read / write interface definitions
5535 * @param val change the values of bdr_gy in reg FIFO_CTRL3
5536 * @retval interface status (MANDATORY: return 0 -> no Error)
5537 *
5538 */
lsm6dso32_fifo_gy_batch_set(stmdev_ctx_t * ctx,lsm6dso32_bdr_gy_t val)5539 int32_t lsm6dso32_fifo_gy_batch_set(stmdev_ctx_t *ctx,
5540 lsm6dso32_bdr_gy_t val)
5541 {
5542 lsm6dso32_fifo_ctrl3_t reg;
5543 int32_t ret;
5544
5545 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1);
5546
5547 if (ret == 0)
5548 {
5549 reg.bdr_gy = (uint8_t)val;
5550 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1);
5551 }
5552
5553 return ret;
5554 }
5555
5556 /**
5557 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5558 * for gyroscope data.[get]
5559 *
5560 * @param ctx read / write interface definitions
5561 * @param val Get the values of bdr_gy in reg FIFO_CTRL3
5562 * @retval interface status (MANDATORY: return 0 -> no Error)
5563 *
5564 */
lsm6dso32_fifo_gy_batch_get(stmdev_ctx_t * ctx,lsm6dso32_bdr_gy_t * val)5565 int32_t lsm6dso32_fifo_gy_batch_get(stmdev_ctx_t *ctx,
5566 lsm6dso32_bdr_gy_t *val)
5567 {
5568 lsm6dso32_fifo_ctrl3_t reg;
5569 int32_t ret;
5570
5571 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL3, (uint8_t *)®, 1);
5572
5573 switch (reg.bdr_gy)
5574 {
5575 case LSM6DSO32_GY_NOT_BATCHED:
5576 *val = LSM6DSO32_GY_NOT_BATCHED;
5577 break;
5578
5579 case LSM6DSO32_GY_BATCHED_AT_12Hz5:
5580 *val = LSM6DSO32_GY_BATCHED_AT_12Hz5;
5581 break;
5582
5583 case LSM6DSO32_GY_BATCHED_AT_26Hz:
5584 *val = LSM6DSO32_GY_BATCHED_AT_26Hz;
5585 break;
5586
5587 case LSM6DSO32_GY_BATCHED_AT_52Hz:
5588 *val = LSM6DSO32_GY_BATCHED_AT_52Hz;
5589 break;
5590
5591 case LSM6DSO32_GY_BATCHED_AT_104Hz:
5592 *val = LSM6DSO32_GY_BATCHED_AT_104Hz;
5593 break;
5594
5595 case LSM6DSO32_GY_BATCHED_AT_208Hz:
5596 *val = LSM6DSO32_GY_BATCHED_AT_208Hz;
5597 break;
5598
5599 case LSM6DSO32_GY_BATCHED_AT_417Hz:
5600 *val = LSM6DSO32_GY_BATCHED_AT_417Hz;
5601 break;
5602
5603 case LSM6DSO32_GY_BATCHED_AT_833Hz:
5604 *val = LSM6DSO32_GY_BATCHED_AT_833Hz;
5605 break;
5606
5607 case LSM6DSO32_GY_BATCHED_AT_1667Hz:
5608 *val = LSM6DSO32_GY_BATCHED_AT_1667Hz;
5609 break;
5610
5611 case LSM6DSO32_GY_BATCHED_AT_3333Hz:
5612 *val = LSM6DSO32_GY_BATCHED_AT_3333Hz;
5613 break;
5614
5615 case LSM6DSO32_GY_BATCHED_AT_6667Hz:
5616 *val = LSM6DSO32_GY_BATCHED_AT_6667Hz;
5617 break;
5618
5619 case LSM6DSO32_GY_BATCHED_AT_6Hz5:
5620 *val = LSM6DSO32_GY_BATCHED_AT_6Hz5;
5621 break;
5622
5623 default:
5624 *val = LSM6DSO32_GY_NOT_BATCHED;
5625 break;
5626 }
5627
5628 return ret;
5629 }
5630
5631 /**
5632 * @brief FIFO mode selection.[set]
5633 *
5634 * @param ctx read / write interface definitions
5635 * @param val change the values of fifo_mode in reg FIFO_CTRL4
5636 * @retval interface status (MANDATORY: return 0 -> no Error)
5637 *
5638 */
lsm6dso32_fifo_mode_set(stmdev_ctx_t * ctx,lsm6dso32_fifo_mode_t val)5639 int32_t lsm6dso32_fifo_mode_set(stmdev_ctx_t *ctx,
5640 lsm6dso32_fifo_mode_t val)
5641 {
5642 lsm6dso32_fifo_ctrl4_t reg;
5643 int32_t ret;
5644
5645 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
5646
5647 if (ret == 0)
5648 {
5649 reg.fifo_mode = (uint8_t)val;
5650 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
5651 }
5652
5653 return ret;
5654 }
5655
5656 /**
5657 * @brief FIFO mode selection.[get]
5658 *
5659 * @param ctx read / write interface definitions
5660 * @param val Get the values of fifo_mode in reg FIFO_CTRL4
5661 * @retval interface status (MANDATORY: return 0 -> no Error)
5662 *
5663 */
lsm6dso32_fifo_mode_get(stmdev_ctx_t * ctx,lsm6dso32_fifo_mode_t * val)5664 int32_t lsm6dso32_fifo_mode_get(stmdev_ctx_t *ctx,
5665 lsm6dso32_fifo_mode_t *val)
5666 {
5667 lsm6dso32_fifo_ctrl4_t reg;
5668 int32_t ret;
5669
5670 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
5671
5672 switch (reg.fifo_mode)
5673 {
5674 case LSM6DSO32_BYPASS_MODE:
5675 *val = LSM6DSO32_BYPASS_MODE;
5676 break;
5677
5678 case LSM6DSO32_FIFO_MODE:
5679 *val = LSM6DSO32_FIFO_MODE;
5680 break;
5681
5682 case LSM6DSO32_STREAM_TO_FIFO_MODE:
5683 *val = LSM6DSO32_STREAM_TO_FIFO_MODE;
5684 break;
5685
5686 case LSM6DSO32_BYPASS_TO_STREAM_MODE:
5687 *val = LSM6DSO32_BYPASS_TO_STREAM_MODE;
5688 break;
5689
5690 case LSM6DSO32_STREAM_MODE:
5691 *val = LSM6DSO32_STREAM_MODE;
5692 break;
5693
5694 case LSM6DSO32_BYPASS_TO_FIFO_MODE:
5695 *val = LSM6DSO32_BYPASS_TO_FIFO_MODE;
5696 break;
5697
5698 default:
5699 *val = LSM6DSO32_BYPASS_MODE;
5700 break;
5701 }
5702
5703 return ret;
5704 }
5705
5706 /**
5707 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5708 * for temperature data.[set]
5709 *
5710 * @param ctx read / write interface definitions
5711 * @param val change the values of odr_t_batch in reg FIFO_CTRL4
5712 * @retval interface status (MANDATORY: return 0 -> no Error)
5713 *
5714 */
lsm6dso32_fifo_temp_batch_set(stmdev_ctx_t * ctx,lsm6dso32_odr_t_batch_t val)5715 int32_t lsm6dso32_fifo_temp_batch_set(stmdev_ctx_t *ctx,
5716 lsm6dso32_odr_t_batch_t val)
5717 {
5718 lsm6dso32_fifo_ctrl4_t reg;
5719 int32_t ret;
5720
5721 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
5722
5723 if (ret == 0)
5724 {
5725 reg.odr_t_batch = (uint8_t)val;
5726 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
5727 }
5728
5729 return ret;
5730 }
5731
5732 /**
5733 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5734 * for temperature data.[get]
5735 *
5736 * @param ctx read / write interface definitions
5737 * @param val Get the values of odr_t_batch in reg FIFO_CTRL4
5738 * @retval interface status (MANDATORY: return 0 -> no Error)
5739 *
5740 */
lsm6dso32_fifo_temp_batch_get(stmdev_ctx_t * ctx,lsm6dso32_odr_t_batch_t * val)5741 int32_t lsm6dso32_fifo_temp_batch_get(stmdev_ctx_t *ctx,
5742 lsm6dso32_odr_t_batch_t *val)
5743 {
5744 lsm6dso32_fifo_ctrl4_t reg;
5745 int32_t ret;
5746
5747 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
5748
5749 switch (reg.odr_t_batch)
5750 {
5751 case LSM6DSO32_TEMP_NOT_BATCHED:
5752 *val = LSM6DSO32_TEMP_NOT_BATCHED;
5753 break;
5754
5755 case LSM6DSO32_TEMP_BATCHED_AT_1Hz6:
5756 *val = LSM6DSO32_TEMP_BATCHED_AT_1Hz6;
5757 break;
5758
5759 case LSM6DSO32_TEMP_BATCHED_AT_12Hz5:
5760 *val = LSM6DSO32_TEMP_BATCHED_AT_12Hz5;
5761 break;
5762
5763 case LSM6DSO32_TEMP_BATCHED_AT_52Hz:
5764 *val = LSM6DSO32_TEMP_BATCHED_AT_52Hz;
5765 break;
5766
5767 default:
5768 *val = LSM6DSO32_TEMP_NOT_BATCHED;
5769 break;
5770 }
5771
5772 return ret;
5773 }
5774
5775 /**
5776 * @brief Selects decimation for timestamp batching in FIFO.
5777 * Writing rate will be the maximum rate between XL and
5778 * GYRO BDR divided by decimation decoder.[set]
5779 *
5780 * @param ctx read / write interface definitions
5781 * @param val change the values of odr_ts_batch in reg FIFO_CTRL4
5782 * @retval interface status (MANDATORY: return 0 -> no Error)
5783 *
5784 */
lsm6dso32_fifo_timestamp_decimation_set(stmdev_ctx_t * ctx,lsm6dso32_odr_ts_batch_t val)5785 int32_t lsm6dso32_fifo_timestamp_decimation_set(stmdev_ctx_t *ctx,
5786 lsm6dso32_odr_ts_batch_t val)
5787 {
5788 lsm6dso32_fifo_ctrl4_t reg;
5789 int32_t ret;
5790
5791 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
5792
5793 if (ret == 0)
5794 {
5795 reg.odr_ts_batch = (uint8_t)val;
5796 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
5797 }
5798
5799 return ret;
5800 }
5801
5802 /**
5803 * @brief Selects decimation for timestamp batching in FIFO.
5804 * Writing rate will be the maximum rate between XL and
5805 * GYRO BDR divided by decimation decoder.[get]
5806 *
5807 * @param ctx read / write interface definitions
5808 * @param val Get the values of odr_ts_batch in reg FIFO_CTRL4
5809 * @retval interface status (MANDATORY: return 0 -> no Error)
5810 *
5811 */
lsm6dso32_fifo_timestamp_decimation_get(stmdev_ctx_t * ctx,lsm6dso32_odr_ts_batch_t * val)5812 int32_t lsm6dso32_fifo_timestamp_decimation_get(stmdev_ctx_t *ctx,
5813 lsm6dso32_odr_ts_batch_t *val)
5814 {
5815 lsm6dso32_fifo_ctrl4_t reg;
5816 int32_t ret;
5817
5818 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_CTRL4, (uint8_t *)®, 1);
5819
5820 switch (reg.odr_ts_batch)
5821 {
5822 case LSM6DSO32_NO_DECIMATION:
5823 *val = LSM6DSO32_NO_DECIMATION;
5824 break;
5825
5826 case LSM6DSO32_DEC_1:
5827 *val = LSM6DSO32_DEC_1;
5828 break;
5829
5830 case LSM6DSO32_DEC_8:
5831 *val = LSM6DSO32_DEC_8;
5832 break;
5833
5834 case LSM6DSO32_DEC_32:
5835 *val = LSM6DSO32_DEC_32;
5836 break;
5837
5838 default:
5839 *val = LSM6DSO32_NO_DECIMATION;
5840 break;
5841 }
5842
5843 return ret;
5844 }
5845
5846 /**
5847 * @brief Selects the trigger for the internal counter of batching events
5848 * between XL and gyro.[set]
5849 *
5850 * @param ctx read / write interface definitions
5851 * @param val change the values of trig_counter_bdr
5852 * in reg COUNTER_BDR_REG1
5853 * @retval interface status (MANDATORY: return 0 -> no Error)
5854 *
5855 */
lsm6dso32_fifo_cnt_event_batch_set(stmdev_ctx_t * ctx,lsm6dso32_trig_counter_bdr_t val)5856 int32_t lsm6dso32_fifo_cnt_event_batch_set(stmdev_ctx_t *ctx,
5857 lsm6dso32_trig_counter_bdr_t val)
5858 {
5859 lsm6dso32_counter_bdr_reg1_t reg;
5860 int32_t ret;
5861
5862 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
5863 (uint8_t *)®, 1);
5864
5865 if (ret == 0)
5866 {
5867 reg.trig_counter_bdr = (uint8_t)val;
5868 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
5869 (uint8_t *)®, 1);
5870 }
5871
5872 return ret;
5873 }
5874
5875 /**
5876 * @brief Selects the trigger for the internal counter of batching events
5877 * between XL and gyro.[get]
5878 *
5879 * @param ctx read / write interface definitions
5880 * @param val Get the values of trig_counter_bdr
5881 * in reg COUNTER_BDR_REG1
5882 * @retval interface status (MANDATORY: return 0 -> no Error)
5883 *
5884 */
lsm6dso32_fifo_cnt_event_batch_get(stmdev_ctx_t * ctx,lsm6dso32_trig_counter_bdr_t * val)5885 int32_t lsm6dso32_fifo_cnt_event_batch_get(stmdev_ctx_t *ctx,
5886 lsm6dso32_trig_counter_bdr_t *val)
5887 {
5888 lsm6dso32_counter_bdr_reg1_t reg;
5889 int32_t ret;
5890
5891 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
5892 (uint8_t *)®, 1);
5893
5894 switch (reg.trig_counter_bdr)
5895 {
5896 case LSM6DSO32_XL_BATCH_EVENT:
5897 *val = LSM6DSO32_XL_BATCH_EVENT;
5898 break;
5899
5900 case LSM6DSO32_GYRO_BATCH_EVENT:
5901 *val = LSM6DSO32_GYRO_BATCH_EVENT;
5902 break;
5903
5904 default:
5905 *val = LSM6DSO32_XL_BATCH_EVENT;
5906 break;
5907 }
5908
5909 return ret;
5910 }
5911
5912 /**
5913 * @brief Resets the internal counter of batching vents for a single sensor.
5914 * This bit is automatically reset to zero if it was set to ‘1’.[set]
5915 *
5916 * @param ctx read / write interface definitions
5917 * @param val change the values of rst_counter_bdr in
5918 * reg COUNTER_BDR_REG1
5919 * @retval interface status (MANDATORY: return 0 -> no Error)
5920 *
5921 */
lsm6dso32_rst_batch_counter_set(stmdev_ctx_t * ctx,uint8_t val)5922 int32_t lsm6dso32_rst_batch_counter_set(stmdev_ctx_t *ctx,
5923 uint8_t val)
5924 {
5925 lsm6dso32_counter_bdr_reg1_t reg;
5926 int32_t ret;
5927
5928 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
5929 (uint8_t *)®, 1);
5930
5931 if (ret == 0)
5932 {
5933 reg.rst_counter_bdr = val;
5934 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
5935 (uint8_t *)®, 1);
5936 }
5937
5938 return ret;
5939 }
5940
5941 /**
5942 * @brief Resets the internal counter of batching events for a single sensor.
5943 * This bit is automatically reset to zero if it was set to ‘1’.[get]
5944 *
5945 * @param ctx read / write interface definitions
5946 * @param val change the values of rst_counter_bdr in
5947 * reg COUNTER_BDR_REG1
5948 * @retval interface status (MANDATORY: return 0 -> no Error)
5949 *
5950 */
lsm6dso32_rst_batch_counter_get(stmdev_ctx_t * ctx,uint8_t * val)5951 int32_t lsm6dso32_rst_batch_counter_get(stmdev_ctx_t *ctx,
5952 uint8_t *val)
5953 {
5954 lsm6dso32_counter_bdr_reg1_t reg;
5955 int32_t ret;
5956
5957 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
5958 (uint8_t *)®, 1);
5959 *val = reg.rst_counter_bdr;
5960
5961 return ret;
5962 }
5963
5964 /**
5965 * @brief Batch data rate counter.[set]
5966 *
5967 * @param ctx read / write interface definitions
5968 * @param val change the values of cnt_bdr_th in
5969 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
5970 * @retval interface status (MANDATORY: return 0 -> no Error)
5971 *
5972 */
lsm6dso32_batch_counter_threshold_set(stmdev_ctx_t * ctx,uint16_t val)5973 int32_t lsm6dso32_batch_counter_threshold_set(stmdev_ctx_t *ctx,
5974 uint16_t val)
5975 {
5976 lsm6dso32_counter_bdr_reg1_t counter_bdr_reg1;
5977 lsm6dso32_counter_bdr_reg2_t counter_bdr_reg2;
5978 int32_t ret;
5979
5980 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
5981 (uint8_t *)&counter_bdr_reg1, 1);
5982
5983 if (ret == 0)
5984 {
5985 counter_bdr_reg2.cnt_bdr_th = 0x00FFU & (uint8_t)val;
5986 counter_bdr_reg1.cnt_bdr_th = (uint8_t)(0x0700U & val) >> 8;
5987 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
5988 (uint8_t *)&counter_bdr_reg1, 1);
5989 }
5990
5991 if (ret == 0)
5992 {
5993 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_COUNTER_BDR_REG2,
5994 (uint8_t *)&counter_bdr_reg2, 1);
5995 }
5996
5997 return ret;
5998 }
5999
6000 /**
6001 * @brief Batch data rate counter.[get]
6002 *
6003 * @param ctx read / write interface definitions
6004 * @param val change the values of cnt_bdr_th in
6005 * reg COUNTER_BDR_REG2 and COUNTER_BDR_REG1.
6006 * @retval interface status (MANDATORY: return 0 -> no Error)
6007 *
6008 */
lsm6dso32_batch_counter_threshold_get(stmdev_ctx_t * ctx,uint16_t * val)6009 int32_t lsm6dso32_batch_counter_threshold_get(stmdev_ctx_t *ctx,
6010 uint16_t *val)
6011 {
6012 lsm6dso32_counter_bdr_reg1_t counter_bdr_reg1;
6013 lsm6dso32_counter_bdr_reg2_t counter_bdr_reg2;
6014 int32_t ret;
6015
6016 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG1,
6017 (uint8_t *)&counter_bdr_reg1, 1);
6018
6019 if (ret == 0)
6020 {
6021 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_COUNTER_BDR_REG2,
6022 (uint8_t *)&counter_bdr_reg2, 1);
6023 *val = ((uint16_t)counter_bdr_reg1.cnt_bdr_th << 8)
6024 + (uint16_t)counter_bdr_reg2.cnt_bdr_th;
6025 }
6026
6027 return ret;
6028 }
6029
6030 /**
6031 * @brief Number of unread sensor data(TAG + 6 bytes) stored in FIFO.[get]
6032 *
6033 * @param ctx read / write interface definitions
6034 * @param val change the values of diff_fifo in reg FIFO_STATUS1
6035 * @retval interface status (MANDATORY: return 0 -> no Error)
6036 *
6037 */
lsm6dso32_fifo_data_level_get(stmdev_ctx_t * ctx,uint16_t * val)6038 int32_t lsm6dso32_fifo_data_level_get(stmdev_ctx_t *ctx,
6039 uint16_t *val)
6040 {
6041 lsm6dso32_fifo_status1_t fifo_status1;
6042 lsm6dso32_fifo_status2_t fifo_status2;
6043 int32_t ret;
6044
6045 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS1,
6046 (uint8_t *)&fifo_status1, 1);
6047
6048 if (ret == 0)
6049 {
6050 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS2,
6051 (uint8_t *)&fifo_status2, 1);
6052 *val = ((uint16_t)fifo_status2.diff_fifo << 8) +
6053 (uint16_t)fifo_status1.diff_fifo;
6054 }
6055
6056 return ret;
6057 }
6058
6059 /**
6060 * @brief FIFO status.[get]
6061 *
6062 * @param ctx read / write interface definitions
6063 * @param val registers FIFO_STATUS2
6064 * @retval interface status (MANDATORY: return 0 -> no Error)
6065 *
6066 */
lsm6dso32_fifo_status_get(stmdev_ctx_t * ctx,lsm6dso32_fifo_status2_t * val)6067 int32_t lsm6dso32_fifo_status_get(stmdev_ctx_t *ctx,
6068 lsm6dso32_fifo_status2_t *val)
6069 {
6070 int32_t ret;
6071
6072 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS2, (uint8_t *) val, 1);
6073
6074 return ret;
6075 }
6076
6077 /**
6078 * @brief Smart FIFO full status.[get]
6079 *
6080 * @param ctx read / write interface definitions
6081 * @param val change the values of fifo_full_ia in reg FIFO_STATUS2
6082 * @retval interface status (MANDATORY: return 0 -> no Error)
6083 *
6084 */
lsm6dso32_fifo_full_flag_get(stmdev_ctx_t * ctx,uint8_t * val)6085 int32_t lsm6dso32_fifo_full_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
6086 {
6087 lsm6dso32_fifo_status2_t reg;
6088 int32_t ret;
6089
6090 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS2, (uint8_t *)®, 1);
6091 *val = reg.fifo_full_ia;
6092
6093 return ret;
6094 }
6095
6096 /**
6097 * @brief FIFO overrun status.[get]
6098 *
6099 * @param ctx read / write interface definitions
6100 * @param val change the values of fifo_over_run_latched in
6101 * reg FIFO_STATUS2
6102 * @retval interface status (MANDATORY: return 0 -> no Error)
6103 *
6104 */
lsm6dso32_fifo_ovr_flag_get(stmdev_ctx_t * ctx,uint8_t * val)6105 int32_t lsm6dso32_fifo_ovr_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
6106 {
6107 lsm6dso32_fifo_status2_t reg;
6108 int32_t ret;
6109
6110 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS2, (uint8_t *)®, 1);
6111 *val = reg.fifo_ovr_ia;
6112
6113 return ret;
6114 }
6115
6116 /**
6117 * @brief FIFO watermark status.[get]
6118 *
6119 * @param ctx read / write interface definitions
6120 * @param val change the values of fifo_wtm_ia in reg FIFO_STATUS2
6121 * @retval interface status (MANDATORY: return 0 -> no Error)
6122 *
6123 */
lsm6dso32_fifo_wtm_flag_get(stmdev_ctx_t * ctx,uint8_t * val)6124 int32_t lsm6dso32_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
6125 {
6126 lsm6dso32_fifo_status2_t reg;
6127 int32_t ret;
6128
6129 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_STATUS2, (uint8_t *)®, 1);
6130 *val = reg.fifo_wtm_ia;
6131
6132 return ret;
6133 }
6134
6135 /**
6136 * @brief Identifies the sensor in FIFO_DATA_OUT.[get]
6137 *
6138 * @param ctx read / write interface definitions
6139 * @param val change the values of tag_sensor in reg FIFO_DATA_OUT_TAG
6140 * @retval interface status (MANDATORY: return 0 -> no Error)
6141 *
6142 */
lsm6dso32_fifo_sensor_tag_get(stmdev_ctx_t * ctx,lsm6dso32_fifo_tag_t * val)6143 int32_t lsm6dso32_fifo_sensor_tag_get(stmdev_ctx_t *ctx,
6144 lsm6dso32_fifo_tag_t *val)
6145 {
6146 lsm6dso32_fifo_data_out_tag_t reg;
6147 int32_t ret;
6148
6149 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FIFO_DATA_OUT_TAG,
6150 (uint8_t *)®, 1);
6151
6152 switch (reg.tag_sensor)
6153 {
6154 case LSM6DSO32_GYRO_NC_TAG:
6155 *val = LSM6DSO32_GYRO_NC_TAG;
6156 break;
6157
6158 case LSM6DSO32_XL_NC_TAG:
6159 *val = LSM6DSO32_XL_NC_TAG;
6160 break;
6161
6162 case LSM6DSO32_TEMPERATURE_TAG:
6163 *val = LSM6DSO32_TEMPERATURE_TAG;
6164 break;
6165
6166 case LSM6DSO32_TIMESTAMP_TAG:
6167 *val = LSM6DSO32_TIMESTAMP_TAG;
6168 break;
6169
6170 case LSM6DSO32_CFG_CHANGE_TAG:
6171 *val = LSM6DSO32_CFG_CHANGE_TAG;
6172 break;
6173
6174 case LSM6DSO32_XL_NC_T_2_TAG:
6175 *val = LSM6DSO32_XL_NC_T_2_TAG;
6176 break;
6177
6178 case LSM6DSO32_XL_NC_T_1_TAG:
6179 *val = LSM6DSO32_XL_NC_T_1_TAG;
6180 break;
6181
6182 case LSM6DSO32_XL_2XC_TAG:
6183 *val = LSM6DSO32_XL_2XC_TAG;
6184 break;
6185
6186 case LSM6DSO32_XL_3XC_TAG:
6187 *val = LSM6DSO32_XL_3XC_TAG;
6188 break;
6189
6190 case LSM6DSO32_GYRO_NC_T_2_TAG:
6191 *val = LSM6DSO32_GYRO_NC_T_2_TAG;
6192 break;
6193
6194 case LSM6DSO32_GYRO_NC_T_1_TAG:
6195 *val = LSM6DSO32_GYRO_NC_T_1_TAG;
6196 break;
6197
6198 case LSM6DSO32_GYRO_2XC_TAG:
6199 *val = LSM6DSO32_GYRO_2XC_TAG;
6200 break;
6201
6202 case LSM6DSO32_GYRO_3XC_TAG:
6203 *val = LSM6DSO32_GYRO_3XC_TAG;
6204 break;
6205
6206 case LSM6DSO32_SENSORHUB_SLAVE0_TAG:
6207 *val = LSM6DSO32_SENSORHUB_SLAVE0_TAG;
6208 break;
6209
6210 case LSM6DSO32_SENSORHUB_SLAVE1_TAG:
6211 *val = LSM6DSO32_SENSORHUB_SLAVE1_TAG;
6212 break;
6213
6214 case LSM6DSO32_SENSORHUB_SLAVE2_TAG:
6215 *val = LSM6DSO32_SENSORHUB_SLAVE2_TAG;
6216 break;
6217
6218 case LSM6DSO32_SENSORHUB_SLAVE3_TAG:
6219 *val = LSM6DSO32_SENSORHUB_SLAVE3_TAG;
6220 break;
6221
6222 case LSM6DSO32_STEP_COUNTER_TAG:
6223 *val = LSM6DSO32_STEP_COUNTER_TAG;
6224 break;
6225
6226 case LSM6DSO32_SENSORHUB_NACK_TAG:
6227 *val = LSM6DSO32_SENSORHUB_NACK_TAG;
6228 break;
6229
6230 default:
6231 *val = LSM6DSO32_GYRO_NC_TAG;
6232 break;
6233 }
6234
6235 return ret;
6236 }
6237
6238 /**
6239 * @brief : Enable FIFO batching of pedometer embedded
6240 * function values.[set]
6241 *
6242 * @param ctx read / write interface definitions
6243 * @param val change the values of gbias_fifo_en in
6244 * reg LSM6DSO32_EMB_FUNC_FIFO_CFG
6245 * @retval interface status (MANDATORY: return 0 -> no Error)
6246 *
6247 */
lsm6dso32_fifo_pedo_batch_set(stmdev_ctx_t * ctx,uint8_t val)6248 int32_t lsm6dso32_fifo_pedo_batch_set(stmdev_ctx_t *ctx, uint8_t val)
6249 {
6250 lsm6dso32_emb_func_fifo_cfg_t reg;
6251 int32_t ret;
6252
6253 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
6254
6255 if (ret == 0)
6256 {
6257 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_FIFO_CFG,
6258 (uint8_t *)®, 1);
6259 }
6260
6261 if (ret == 0)
6262 {
6263 reg.pedo_fifo_en = val;
6264 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_FIFO_CFG,
6265 (uint8_t *)®, 1);
6266 }
6267
6268 if (ret == 0)
6269 {
6270 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6271 }
6272
6273 return ret;
6274 }
6275
6276 /**
6277 * @brief Enable FIFO batching of pedometer embedded function values.[get]
6278 *
6279 * @param ctx read / write interface definitions
6280 * @param val change the values of pedo_fifo_en in
6281 * reg LSM6DSO32_EMB_FUNC_FIFO_CFG
6282 * @retval interface status (MANDATORY: return 0 -> no Error)
6283 *
6284 */
lsm6dso32_fifo_pedo_batch_get(stmdev_ctx_t * ctx,uint8_t * val)6285 int32_t lsm6dso32_fifo_pedo_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
6286 {
6287 lsm6dso32_emb_func_fifo_cfg_t reg;
6288 int32_t ret;
6289
6290 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
6291
6292 if (ret == 0)
6293 {
6294 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_FIFO_CFG,
6295 (uint8_t *)®, 1);
6296 }
6297
6298 if (ret == 0)
6299 {
6300 *val = reg.pedo_fifo_en;
6301 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6302 }
6303
6304 return ret;
6305 }
6306
6307 /**
6308 * @brief Enable FIFO batching data of first slave.[set]
6309 *
6310 * @param ctx read / write interface definitions
6311 * @param val change the values of batch_ext_sens_0_en in
6312 * reg SLV0_CONFIG
6313 * @retval interface status (MANDATORY: return 0 -> no Error)
6314 *
6315 */
lsm6dso32_sh_batch_slave_0_set(stmdev_ctx_t * ctx,uint8_t val)6316 int32_t lsm6dso32_sh_batch_slave_0_set(stmdev_ctx_t *ctx, uint8_t val)
6317 {
6318 lsm6dso32_slv0_config_t reg;
6319 int32_t ret;
6320
6321 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
6322
6323 if (ret == 0)
6324 {
6325 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1);
6326 }
6327
6328 if (ret == 0)
6329 {
6330 reg.batch_ext_sens_0_en = val;
6331 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1);
6332 }
6333
6334 if (ret == 0)
6335 {
6336 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6337 }
6338
6339 return ret;
6340 }
6341
6342 /**
6343 * @brief Enable FIFO batching data of first slave.[get]
6344 *
6345 * @param ctx read / write interface definitions
6346 * @param val change the values of batch_ext_sens_0_en in
6347 * reg SLV0_CONFIG
6348 * @retval interface status (MANDATORY: return 0 -> no Error)
6349 *
6350 */
lsm6dso32_sh_batch_slave_0_get(stmdev_ctx_t * ctx,uint8_t * val)6351 int32_t lsm6dso32_sh_batch_slave_0_get(stmdev_ctx_t *ctx,
6352 uint8_t *val)
6353 {
6354 lsm6dso32_slv0_config_t reg;
6355 int32_t ret;
6356
6357 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
6358
6359 if (ret == 0)
6360 {
6361 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1);
6362 }
6363
6364 if (ret == 0)
6365 {
6366 *val = reg.batch_ext_sens_0_en;
6367 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6368 }
6369
6370 return ret;
6371 }
6372
6373 /**
6374 * @brief Enable FIFO batching data of second slave.[set]
6375 *
6376 * @param ctx read / write interface definitions
6377 * @param val change the values of batch_ext_sens_1_en in
6378 * reg SLV1_CONFIG
6379 * @retval interface status (MANDATORY: return 0 -> no Error)
6380 *
6381 */
lsm6dso32_sh_batch_slave_1_set(stmdev_ctx_t * ctx,uint8_t val)6382 int32_t lsm6dso32_sh_batch_slave_1_set(stmdev_ctx_t *ctx, uint8_t val)
6383 {
6384 lsm6dso32_slv1_config_t reg;
6385 int32_t ret;
6386
6387 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
6388
6389 if (ret == 0)
6390 {
6391 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV1_CONFIG, (uint8_t *)®, 1);
6392 }
6393
6394 if (ret == 0)
6395 {
6396 reg.batch_ext_sens_1_en = val;
6397 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV1_CONFIG, (uint8_t *)®, 1);
6398 }
6399
6400 if (ret == 0)
6401 {
6402 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6403 }
6404
6405 return ret;
6406 }
6407
6408 /**
6409 * @brief Enable FIFO batching data of second slave.[get]
6410 *
6411 * @param ctx read / write interface definitions
6412 * @param val change the values of batch_ext_sens_1_en in
6413 * reg SLV1_CONFIG
6414 * @retval interface status (MANDATORY: return 0 -> no Error)
6415 *
6416 */
lsm6dso32_sh_batch_slave_1_get(stmdev_ctx_t * ctx,uint8_t * val)6417 int32_t lsm6dso32_sh_batch_slave_1_get(stmdev_ctx_t *ctx,
6418 uint8_t *val)
6419 {
6420 lsm6dso32_slv1_config_t reg;
6421 int32_t ret;
6422
6423 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
6424
6425 if (ret == 0)
6426 {
6427 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV1_CONFIG, (uint8_t *)®, 1);
6428 *val = reg.batch_ext_sens_1_en;
6429 }
6430
6431 if (ret == 0)
6432 {
6433 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6434 }
6435
6436 return ret;
6437 }
6438
6439 /**
6440 * @brief Enable FIFO batching data of third slave.[set]
6441 *
6442 * @param ctx read / write interface definitions
6443 * @param val change the values of batch_ext_sens_2_en in
6444 * reg SLV2_CONFIG
6445 * @retval interface status (MANDATORY: return 0 -> no Error)
6446 *
6447 */
lsm6dso32_sh_batch_slave_2_set(stmdev_ctx_t * ctx,uint8_t val)6448 int32_t lsm6dso32_sh_batch_slave_2_set(stmdev_ctx_t *ctx, uint8_t val)
6449 {
6450 lsm6dso32_slv2_config_t reg;
6451 int32_t ret;
6452
6453 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
6454
6455 if (ret == 0)
6456 {
6457 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV2_CONFIG, (uint8_t *)®, 1);
6458 }
6459
6460 if (ret == 0)
6461 {
6462 reg.batch_ext_sens_2_en = val;
6463 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV2_CONFIG, (uint8_t *)®, 1);
6464 }
6465
6466 if (ret == 0)
6467 {
6468 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6469 }
6470
6471 return ret;
6472 }
6473
6474 /**
6475 * @brief Enable FIFO batching data of third slave.[get]
6476 *
6477 * @param ctx read / write interface definitions
6478 * @param val change the values of batch_ext_sens_2_en in
6479 * reg SLV2_CONFIG
6480 * @retval interface status (MANDATORY: return 0 -> no Error)
6481 *
6482 */
lsm6dso32_sh_batch_slave_2_get(stmdev_ctx_t * ctx,uint8_t * val)6483 int32_t lsm6dso32_sh_batch_slave_2_get(stmdev_ctx_t *ctx,
6484 uint8_t *val)
6485 {
6486 lsm6dso32_slv2_config_t reg;
6487 int32_t ret;
6488
6489 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
6490
6491 if (ret == 0)
6492 {
6493 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV2_CONFIG, (uint8_t *)®, 1);
6494 }
6495
6496 if (ret == 0)
6497 {
6498 *val = reg.batch_ext_sens_2_en;
6499 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6500 }
6501
6502 return ret;
6503 }
6504
6505 /**
6506 * @brief Enable FIFO batching data of fourth slave.[set]
6507 *
6508 * @param ctx read / write interface definitions
6509 * @param val change the values of batch_ext_sens_3_en
6510 * in reg SLV3_CONFIG
6511 * @retval interface status (MANDATORY: return 0 -> no Error)
6512 *
6513 */
lsm6dso32_sh_batch_slave_3_set(stmdev_ctx_t * ctx,uint8_t val)6514 int32_t lsm6dso32_sh_batch_slave_3_set(stmdev_ctx_t *ctx, uint8_t val)
6515 {
6516 lsm6dso32_slv3_config_t reg;
6517 int32_t ret;
6518
6519 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
6520
6521 if (ret == 0)
6522 {
6523 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV3_CONFIG, (uint8_t *)®, 1);
6524 }
6525
6526 if (ret == 0)
6527 {
6528 reg.batch_ext_sens_3_en = val;
6529 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV3_CONFIG, (uint8_t *)®, 1);
6530 }
6531
6532 if (ret == 0)
6533 {
6534 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6535 }
6536
6537 return ret;
6538 }
6539
6540 /**
6541 * @brief Enable FIFO batching data of fourth slave.[get]
6542 *
6543 * @param ctx read / write interface definitions
6544 * @param val change the values of batch_ext_sens_3_en in
6545 * reg SLV3_CONFIG
6546 * @retval interface status (MANDATORY: return 0 -> no Error)
6547 *
6548 */
lsm6dso32_sh_batch_slave_3_get(stmdev_ctx_t * ctx,uint8_t * val)6549 int32_t lsm6dso32_sh_batch_slave_3_get(stmdev_ctx_t *ctx,
6550 uint8_t *val)
6551 {
6552 lsm6dso32_slv3_config_t reg;
6553 int32_t ret;
6554
6555 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
6556
6557 if (ret == 0)
6558 {
6559 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV3_CONFIG, (uint8_t *)®, 1);
6560 }
6561
6562 if (ret == 0)
6563 {
6564 *val = reg.batch_ext_sens_3_en;
6565 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6566 }
6567
6568 return ret;
6569 }
6570
6571 /**
6572 * @}
6573 *
6574 */
6575
6576 /**
6577 * @defgroup LSM6DSO32_DEN_functionality
6578 * @brief This section groups all the functions concerning
6579 * DEN functionality.
6580 * @{
6581 *
6582 */
6583
6584 /**
6585 * @brief DEN functionality marking mode.[set]
6586 *
6587 * @param ctx read / write interface definitions
6588 * @param val change the values of den_mode in reg CTRL6_C
6589 * @retval interface status (MANDATORY: return 0 -> no Error)
6590 *
6591 */
lsm6dso32_den_mode_set(stmdev_ctx_t * ctx,lsm6dso32_den_mode_t val)6592 int32_t lsm6dso32_den_mode_set(stmdev_ctx_t *ctx,
6593 lsm6dso32_den_mode_t val)
6594 {
6595 lsm6dso32_ctrl6_c_t reg;
6596 int32_t ret;
6597
6598 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
6599
6600 if (ret == 0)
6601 {
6602 reg.den_mode = (uint8_t)val;
6603 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
6604 }
6605
6606 return ret;
6607 }
6608
6609 /**
6610 * @brief DEN functionality marking mode.[get]
6611 *
6612 * @param ctx read / write interface definitions
6613 * @param val Get the values of den_mode in reg CTRL6_C
6614 * @retval interface status (MANDATORY: return 0 -> no Error)
6615 *
6616 */
lsm6dso32_den_mode_get(stmdev_ctx_t * ctx,lsm6dso32_den_mode_t * val)6617 int32_t lsm6dso32_den_mode_get(stmdev_ctx_t *ctx,
6618 lsm6dso32_den_mode_t *val)
6619 {
6620 lsm6dso32_ctrl6_c_t reg;
6621 int32_t ret;
6622
6623 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL6_C, (uint8_t *)®, 1);
6624
6625 switch (reg.den_mode)
6626 {
6627 case LSM6DSO32_DEN_DISABLE:
6628 *val = LSM6DSO32_DEN_DISABLE;
6629 break;
6630
6631 case LSM6DSO32_LEVEL_FIFO:
6632 *val = LSM6DSO32_LEVEL_FIFO;
6633 break;
6634
6635 case LSM6DSO32_LEVEL_LETCHED:
6636 *val = LSM6DSO32_LEVEL_LETCHED;
6637 break;
6638
6639 case LSM6DSO32_LEVEL_TRIGGER:
6640 *val = LSM6DSO32_LEVEL_TRIGGER;
6641 break;
6642
6643 case LSM6DSO32_EDGE_TRIGGER:
6644 *val = LSM6DSO32_EDGE_TRIGGER;
6645 break;
6646
6647 default:
6648 *val = LSM6DSO32_DEN_DISABLE;
6649 break;
6650 }
6651
6652 return ret;
6653 }
6654
6655 /**
6656 * @brief DEN active level configuration.[set]
6657 *
6658 * @param ctx read / write interface definitions
6659 * @param val change the values of den_lh in reg CTRL9_XL
6660 * @retval interface status (MANDATORY: return 0 -> no Error)
6661 *
6662 */
lsm6dso32_den_polarity_set(stmdev_ctx_t * ctx,lsm6dso32_den_lh_t val)6663 int32_t lsm6dso32_den_polarity_set(stmdev_ctx_t *ctx,
6664 lsm6dso32_den_lh_t val)
6665 {
6666 lsm6dso32_ctrl9_xl_t reg;
6667 int32_t ret;
6668
6669 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6670
6671 if (ret == 0)
6672 {
6673 reg.den_lh = (uint8_t)val;
6674 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6675 }
6676
6677 return ret;
6678 }
6679
6680 /**
6681 * @brief DEN active level configuration.[get]
6682 *
6683 * @param ctx read / write interface definitions
6684 * @param val Get the values of den_lh in reg CTRL9_XL
6685 * @retval interface status (MANDATORY: return 0 -> no Error)
6686 *
6687 */
lsm6dso32_den_polarity_get(stmdev_ctx_t * ctx,lsm6dso32_den_lh_t * val)6688 int32_t lsm6dso32_den_polarity_get(stmdev_ctx_t *ctx,
6689 lsm6dso32_den_lh_t *val)
6690 {
6691 lsm6dso32_ctrl9_xl_t reg;
6692 int32_t ret;
6693
6694 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6695
6696 switch (reg.den_lh)
6697 {
6698 case LSM6DSO32_DEN_ACT_LOW:
6699 *val = LSM6DSO32_DEN_ACT_LOW;
6700 break;
6701
6702 case LSM6DSO32_DEN_ACT_HIGH:
6703 *val = LSM6DSO32_DEN_ACT_HIGH;
6704 break;
6705
6706 default:
6707 *val = LSM6DSO32_DEN_ACT_LOW;
6708 break;
6709 }
6710
6711 return ret;
6712 }
6713
6714 /**
6715 * @brief DEN enable.[set]
6716 *
6717 * @param ctx read / write interface definitions
6718 * @param val change the values of den_xl_g in reg CTRL9_XL
6719 * @retval interface status (MANDATORY: return 0 -> no Error)
6720 *
6721 */
lsm6dso32_den_enable_set(stmdev_ctx_t * ctx,lsm6dso32_den_xl_g_t val)6722 int32_t lsm6dso32_den_enable_set(stmdev_ctx_t *ctx,
6723 lsm6dso32_den_xl_g_t val)
6724 {
6725 lsm6dso32_ctrl9_xl_t reg;
6726 int32_t ret;
6727
6728 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6729
6730 if (ret == 0)
6731 {
6732 reg.den_xl_g = (uint8_t)val;
6733 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6734 }
6735
6736 return ret;
6737 }
6738
6739 /**
6740 * @brief DEN enable.[get]
6741 *
6742 * @param ctx read / write interface definitions
6743 * @param val Get the values of den_xl_g in reg CTRL9_XL
6744 * @retval interface status (MANDATORY: return 0 -> no Error)
6745 *
6746 */
lsm6dso32_den_enable_get(stmdev_ctx_t * ctx,lsm6dso32_den_xl_g_t * val)6747 int32_t lsm6dso32_den_enable_get(stmdev_ctx_t *ctx,
6748 lsm6dso32_den_xl_g_t *val)
6749 {
6750 lsm6dso32_ctrl9_xl_t reg;
6751 int32_t ret;
6752
6753 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6754
6755 switch (reg.den_xl_g)
6756 {
6757 case LSM6DSO32_STAMP_IN_GY_DATA:
6758 *val = LSM6DSO32_STAMP_IN_GY_DATA;
6759 break;
6760
6761 case LSM6DSO32_STAMP_IN_XL_DATA:
6762 *val = LSM6DSO32_STAMP_IN_XL_DATA;
6763 break;
6764
6765 case LSM6DSO32_STAMP_IN_GY_XL_DATA:
6766 *val = LSM6DSO32_STAMP_IN_GY_XL_DATA;
6767 break;
6768
6769 default:
6770 *val = LSM6DSO32_STAMP_IN_GY_DATA;
6771 break;
6772 }
6773
6774 return ret;
6775 }
6776
6777 /**
6778 * @brief DEN value stored in LSB of X-axis.[set]
6779 *
6780 * @param ctx read / write interface definitions
6781 * @param val change the values of den_z in reg CTRL9_XL
6782 * @retval interface status (MANDATORY: return 0 -> no Error)
6783 *
6784 */
lsm6dso32_den_mark_axis_x_set(stmdev_ctx_t * ctx,uint8_t val)6785 int32_t lsm6dso32_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
6786 {
6787 lsm6dso32_ctrl9_xl_t reg;
6788 int32_t ret;
6789
6790 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6791
6792 if (ret == 0)
6793 {
6794 reg.den_z = val;
6795 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6796 }
6797
6798 return ret;
6799 }
6800
6801 /**
6802 * @brief DEN value stored in LSB of X-axis.[get]
6803 *
6804 * @param ctx read / write interface definitions
6805 * @param val change the values of den_z in reg CTRL9_XL
6806 * @retval interface status (MANDATORY: return 0 -> no Error)
6807 *
6808 */
lsm6dso32_den_mark_axis_x_get(stmdev_ctx_t * ctx,uint8_t * val)6809 int32_t lsm6dso32_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
6810 {
6811 lsm6dso32_ctrl9_xl_t reg;
6812 int32_t ret;
6813
6814 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6815 *val = reg.den_z;
6816
6817 return ret;
6818 }
6819
6820 /**
6821 * @brief DEN value stored in LSB of Y-axis.[set]
6822 *
6823 * @param ctx read / write interface definitions
6824 * @param val change the values of den_y in reg CTRL9_XL
6825 * @retval interface status (MANDATORY: return 0 -> no Error)
6826 *
6827 */
lsm6dso32_den_mark_axis_y_set(stmdev_ctx_t * ctx,uint8_t val)6828 int32_t lsm6dso32_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
6829 {
6830 lsm6dso32_ctrl9_xl_t reg;
6831 int32_t ret;
6832
6833 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6834
6835 if (ret == 0)
6836 {
6837 reg.den_y = val;
6838 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6839 }
6840
6841 return ret;
6842 }
6843
6844 /**
6845 * @brief DEN value stored in LSB of Y-axis.[get]
6846 *
6847 * @param ctx read / write interface definitions
6848 * @param val change the values of den_y in reg CTRL9_XL
6849 * @retval interface status (MANDATORY: return 0 -> no Error)
6850 *
6851 */
lsm6dso32_den_mark_axis_y_get(stmdev_ctx_t * ctx,uint8_t * val)6852 int32_t lsm6dso32_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
6853 {
6854 lsm6dso32_ctrl9_xl_t reg;
6855 int32_t ret;
6856
6857 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6858 *val = reg.den_y;
6859
6860 return ret;
6861 }
6862
6863 /**
6864 * @brief DEN value stored in LSB of Z-axis.[set]
6865 *
6866 * @param ctx read / write interface definitions
6867 * @param val change the values of den_x in reg CTRL9_XL
6868 * @retval interface status (MANDATORY: return 0 -> no Error)
6869 *
6870 */
lsm6dso32_den_mark_axis_z_set(stmdev_ctx_t * ctx,uint8_t val)6871 int32_t lsm6dso32_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
6872 {
6873 lsm6dso32_ctrl9_xl_t reg;
6874 int32_t ret;
6875
6876 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6877
6878 if (ret == 0)
6879 {
6880 reg.den_x = val;
6881 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6882 }
6883
6884 return ret;
6885 }
6886
6887 /**
6888 * @brief DEN value stored in LSB of Z-axis.[get]
6889 *
6890 * @param ctx read / write interface definitions
6891 * @param val change the values of den_x in reg CTRL9_XL
6892 * @retval interface status (MANDATORY: return 0 -> no Error)
6893 *
6894 */
lsm6dso32_den_mark_axis_z_get(stmdev_ctx_t * ctx,uint8_t * val)6895 int32_t lsm6dso32_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
6896 {
6897 lsm6dso32_ctrl9_xl_t reg;
6898 int32_t ret;
6899
6900 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_CTRL9_XL, (uint8_t *)®, 1);
6901 *val = reg.den_x;
6902
6903 return ret;
6904 }
6905
6906 /**
6907 * @}
6908 *
6909 */
6910
6911 /**
6912 * @defgroup LSM6DSO32_Pedometer
6913 * @brief This section groups all the functions that manage pedometer.
6914 * @{
6915 *
6916 */
6917
6918 /**
6919 * @brief Enable pedometer algorithm.[set]
6920 *
6921 * @param ctx read / write interface definitions
6922 * @param val turn on and configure pedometer
6923 * @retval interface status (MANDATORY: return 0 -> no Error)
6924 *
6925 */
lsm6dso32_pedo_sens_set(stmdev_ctx_t * ctx,lsm6dso32_pedo_md_t val)6926 int32_t lsm6dso32_pedo_sens_set(stmdev_ctx_t *ctx,
6927 lsm6dso32_pedo_md_t val)
6928 {
6929 lsm6dso32_emb_func_en_a_t emb_func_en_a;
6930 lsm6dso32_emb_func_en_b_t emb_func_en_b;
6931 lsm6dso32_pedo_cmd_reg_t pedo_cmd_reg;
6932 int32_t ret;
6933
6934 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_CMD_REG,
6935 (uint8_t *)&pedo_cmd_reg);
6936
6937 if (ret == 0)
6938 {
6939 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
6940 }
6941
6942 if (ret == 0)
6943 {
6944 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
6945 (uint8_t *)&emb_func_en_a, 1);
6946 }
6947
6948 if (ret == 0)
6949 {
6950 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
6951 (uint8_t *)&emb_func_en_b, 1);
6952 emb_func_en_a.pedo_en = (uint8_t)val & 0x01U;
6953 emb_func_en_b.pedo_adv_en = ((uint8_t)val & 0x02U) >> 1;
6954 pedo_cmd_reg.fp_rejection_en = ((uint8_t)val & 0x10U) >> 4;
6955 pedo_cmd_reg.ad_det_en = ((uint8_t)val & 0x20U) >> 5;
6956 }
6957
6958 if (ret == 0)
6959 {
6960 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
6961 (uint8_t *)&emb_func_en_a, 1);
6962 }
6963
6964 if (ret == 0)
6965 {
6966 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
6967 (uint8_t *)&emb_func_en_b, 1);
6968 }
6969
6970 if (ret == 0)
6971 {
6972 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
6973 }
6974
6975 if (ret == 0)
6976 {
6977 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_PEDO_CMD_REG,
6978 (uint8_t *)&pedo_cmd_reg);
6979 }
6980
6981 return ret;
6982 }
6983
6984 /**
6985 * @brief Enable pedometer algorithm.[get]
6986 *
6987 * @param ctx read / write interface definitions
6988 * @param val turn on and configure pedometer
6989 * @retval interface status (MANDATORY: return 0 -> no Error)
6990 *
6991 */
lsm6dso32_pedo_sens_get(stmdev_ctx_t * ctx,lsm6dso32_pedo_md_t * val)6992 int32_t lsm6dso32_pedo_sens_get(stmdev_ctx_t *ctx,
6993 lsm6dso32_pedo_md_t *val)
6994 {
6995 lsm6dso32_emb_func_en_a_t emb_func_en_a;
6996 lsm6dso32_emb_func_en_b_t emb_func_en_b;
6997 lsm6dso32_pedo_cmd_reg_t pedo_cmd_reg;
6998 int32_t ret;
6999
7000 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_CMD_REG,
7001 (uint8_t *)&pedo_cmd_reg);
7002
7003 if (ret == 0)
7004 {
7005 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
7006 }
7007
7008 if (ret == 0)
7009 {
7010 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
7011 (uint8_t *)&emb_func_en_a, 1);
7012 }
7013
7014 if (ret == 0)
7015 {
7016 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
7017 (uint8_t *)&emb_func_en_b, 1);
7018 }
7019
7020 if (ret == 0)
7021 {
7022 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
7023 }
7024
7025 switch ((pedo_cmd_reg.ad_det_en << 5) | (pedo_cmd_reg.fp_rejection_en
7026 << 4) |
7027 (emb_func_en_b.pedo_adv_en << 1) | emb_func_en_a.pedo_en)
7028 {
7029 case LSM6DSO32_PEDO_DISABLE:
7030 *val = LSM6DSO32_PEDO_DISABLE;
7031 break;
7032
7033 case LSM6DSO32_PEDO_BASE_MODE:
7034 *val = LSM6DSO32_PEDO_BASE_MODE;
7035 break;
7036
7037 case LSM6DSO32_PEDO_ADV_MODE:
7038 *val = LSM6DSO32_PEDO_ADV_MODE;
7039 break;
7040
7041 case LSM6DSO32_FALSE_STEP_REJ:
7042 *val = LSM6DSO32_FALSE_STEP_REJ;
7043 break;
7044
7045 case LSM6DSO32_FALSE_STEP_REJ_ADV_MODE:
7046 *val = LSM6DSO32_FALSE_STEP_REJ_ADV_MODE;
7047 break;
7048
7049 default:
7050 *val = LSM6DSO32_PEDO_DISABLE;
7051 break;
7052 }
7053
7054 return ret;
7055 }
7056
7057 /**
7058 * @brief Interrupt status bit for step detection.[get]
7059 *
7060 * @param ctx read / write interface definitions
7061 * @param val change the values of is_step_det in reg EMB_FUNC_STATUS
7062 * @retval interface status (MANDATORY: return 0 -> no Error)
7063 *
7064 */
lsm6dso32_pedo_step_detect_get(stmdev_ctx_t * ctx,uint8_t * val)7065 int32_t lsm6dso32_pedo_step_detect_get(stmdev_ctx_t *ctx,
7066 uint8_t *val)
7067 {
7068 lsm6dso32_emb_func_status_t reg;
7069 int32_t ret;
7070
7071 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
7072
7073 if (ret == 0)
7074 {
7075 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_STATUS,
7076 (uint8_t *)®, 1);
7077 }
7078
7079 if (ret == 0)
7080 {
7081 *val = reg.is_step_det;
7082 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
7083 }
7084
7085 return ret;
7086 }
7087
7088 /**
7089 * @brief Pedometer debounce configuration register (r/w).[set]
7090 *
7091 * @param ctx read / write interface definitions
7092 * @param buff buffer that contains data to write
7093 * @retval interface status (MANDATORY: return 0 -> no Error)
7094 *
7095 */
lsm6dso32_pedo_debounce_steps_set(stmdev_ctx_t * ctx,uint8_t * buff)7096 int32_t lsm6dso32_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
7097 uint8_t *buff)
7098 {
7099 int32_t ret;
7100
7101 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_PEDO_DEB_STEPS_CONF,
7102 buff);
7103
7104 return ret;
7105 }
7106
7107 /**
7108 * @brief Pedometer debounce configuration register (r/w).[get]
7109 *
7110 * @param ctx read / write interface definitions
7111 * @param buff buffer that stores data read
7112 * @retval interface status (MANDATORY: return 0 -> no Error)
7113 *
7114 */
lsm6dso32_pedo_debounce_steps_get(stmdev_ctx_t * ctx,uint8_t * buff)7115 int32_t lsm6dso32_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
7116 uint8_t *buff)
7117 {
7118 int32_t ret;
7119
7120 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_DEB_STEPS_CONF,
7121 buff);
7122
7123 return ret;
7124 }
7125
7126 /**
7127 * @brief Time period register for step detection on delta time (r/w).[set]
7128 *
7129 * @param ctx read / write interface definitions
7130 * @param buff buffer that contains data to write
7131 * @retval interface status (MANDATORY: return 0 -> no Error)
7132 *
7133 */
lsm6dso32_pedo_steps_period_set(stmdev_ctx_t * ctx,uint16_t val)7134 int32_t lsm6dso32_pedo_steps_period_set(stmdev_ctx_t *ctx,
7135 uint16_t val)
7136 {
7137 uint8_t buff[2];
7138 int32_t ret;
7139
7140 buff[1] = (uint8_t)(val / 256U);
7141 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7142 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_PEDO_SC_DELTAT_L,
7143 &buff[0]);
7144
7145 if (ret == 0)
7146 {
7147 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_PEDO_SC_DELTAT_H,
7148 &buff[1]);
7149 }
7150
7151 return ret;
7152 }
7153
7154 /**
7155 * @brief Time period register for step detection on delta time (r/w).[get]
7156 *
7157 * @param ctx read / write interface definitions
7158 * @param buff buffer that stores data read
7159 * @retval interface status (MANDATORY: return 0 -> no Error)
7160 *
7161 */
lsm6dso32_pedo_steps_period_get(stmdev_ctx_t * ctx,uint16_t * val)7162 int32_t lsm6dso32_pedo_steps_period_get(stmdev_ctx_t *ctx,
7163 uint16_t *val)
7164 {
7165 uint8_t buff[2];
7166 int32_t ret;
7167
7168 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_SC_DELTAT_L,
7169 &buff[0]);
7170
7171 if (ret == 0)
7172 {
7173 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_SC_DELTAT_H,
7174 &buff[1]);
7175 *val = buff[1];
7176 *val = (*val * 256U) + buff[0];
7177 }
7178
7179 return ret;
7180 }
7181
7182 /**
7183 * @brief Set when user wants to generate interrupt on count overflow
7184 * event/every step.[set]
7185 *
7186 * @param ctx read / write interface definitions
7187 * @param val change the values of carry_count_en in reg PEDO_CMD_REG
7188 * @retval interface status (MANDATORY: return 0 -> no Error)
7189 *
7190 */
lsm6dso32_pedo_int_mode_set(stmdev_ctx_t * ctx,lsm6dso32_carry_count_en_t val)7191 int32_t lsm6dso32_pedo_int_mode_set(stmdev_ctx_t *ctx,
7192 lsm6dso32_carry_count_en_t val)
7193 {
7194 lsm6dso32_pedo_cmd_reg_t reg;
7195 int32_t ret;
7196
7197 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_CMD_REG,
7198 (uint8_t *)®);
7199
7200 if (ret == 0)
7201 {
7202 reg.carry_count_en = (uint8_t)val;
7203 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_PEDO_CMD_REG,
7204 (uint8_t *)®);
7205 }
7206
7207 return ret;
7208 }
7209
7210 /**
7211 * @brief Set when user wants to generate interrupt on count overflow
7212 * event/every step.[get]
7213 *
7214 * @param ctx read / write interface definitions
7215 * @param val Get the values of carry_count_en in reg PEDO_CMD_REG
7216 * @retval interface status (MANDATORY: return 0 -> no Error)
7217 *
7218 */
lsm6dso32_pedo_int_mode_get(stmdev_ctx_t * ctx,lsm6dso32_carry_count_en_t * val)7219 int32_t lsm6dso32_pedo_int_mode_get(stmdev_ctx_t *ctx,
7220 lsm6dso32_carry_count_en_t *val)
7221 {
7222 lsm6dso32_pedo_cmd_reg_t reg;
7223 int32_t ret;
7224
7225 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_PEDO_CMD_REG,
7226 (uint8_t *)®);
7227
7228 switch (reg.carry_count_en)
7229 {
7230 case LSM6DSO32_EVERY_STEP:
7231 *val = LSM6DSO32_EVERY_STEP;
7232 break;
7233
7234 case LSM6DSO32_COUNT_OVERFLOW:
7235 *val = LSM6DSO32_COUNT_OVERFLOW;
7236 break;
7237
7238 default:
7239 *val = LSM6DSO32_EVERY_STEP;
7240 break;
7241 }
7242
7243 return ret;
7244 }
7245
7246 /**
7247 * @}
7248 *
7249 */
7250
7251 /**
7252 * @defgroup LSM6DSO32_significant_motion
7253 * @brief This section groups all the functions that manage the
7254 * significant motion detection.
7255 * @{
7256 *
7257 */
7258
7259 /**
7260 * @brief Enable significant motion detection function.[set]
7261 *
7262 * @param ctx read / write interface definitions
7263 * @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A
7264 * @retval interface status (MANDATORY: return 0 -> no Error)
7265 *
7266 */
lsm6dso32_motion_sens_set(stmdev_ctx_t * ctx,uint8_t val)7267 int32_t lsm6dso32_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
7268 {
7269 lsm6dso32_emb_func_en_a_t reg;
7270 int32_t ret;
7271
7272 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
7273
7274 if (ret == 0)
7275 {
7276 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
7277 (uint8_t *)®, 1);
7278 }
7279
7280 if (ret == 0)
7281 {
7282 reg.sign_motion_en = val;
7283 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
7284 (uint8_t *)®, 1);
7285 }
7286
7287 if (ret == 0)
7288 {
7289 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
7290 }
7291
7292 return ret;
7293 }
7294
7295 /**
7296 * @brief Enable significant motion detection function.[get]
7297 *
7298 * @param ctx read / write interface definitions
7299 * @param val change the values of sign_motion_en in reg EMB_FUNC_EN_A
7300 * @retval interface status (MANDATORY: return 0 -> no Error)
7301 *
7302 */
lsm6dso32_motion_sens_get(stmdev_ctx_t * ctx,uint8_t * val)7303 int32_t lsm6dso32_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
7304 {
7305 lsm6dso32_emb_func_en_a_t reg;
7306 int32_t ret;
7307
7308 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
7309
7310 if (ret == 0)
7311 {
7312 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
7313 (uint8_t *)®, 1);
7314 }
7315
7316 if (ret == 0)
7317 {
7318 *val = reg.sign_motion_en;
7319 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
7320 }
7321
7322 return ret;
7323 }
7324
7325 /**
7326 * @brief Interrupt status bit for significant motion detection.[get]
7327 *
7328 * @param ctx read / write interface definitions
7329 * @param val change the values of is_sigmot in reg EMB_FUNC_STATUS
7330 * @retval interface status (MANDATORY: return 0 -> no Error)
7331 *
7332 */
lsm6dso32_motion_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)7333 int32_t lsm6dso32_motion_flag_data_ready_get(stmdev_ctx_t *ctx,
7334 uint8_t *val)
7335 {
7336 lsm6dso32_emb_func_status_t reg;
7337 int32_t ret;
7338
7339 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
7340
7341 if (ret == 0)
7342 {
7343 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_STATUS,
7344 (uint8_t *)®, 1);
7345 }
7346
7347 if (ret == 0)
7348 {
7349 *val = reg.is_sigmot;
7350 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
7351 }
7352
7353 return ret;
7354 }
7355
7356 /**
7357 * @}
7358 *
7359 */
7360
7361 /**
7362 * @defgroup LSM6DSO32_tilt_detection
7363 * @brief This section groups all the functions that manage the tilt
7364 * event detection.
7365 * @{
7366 *
7367 */
7368
7369 /**
7370 * @brief Enable tilt calculation.[set]
7371 *
7372 * @param ctx read / write interface definitions
7373 * @param val change the values of tilt_en in reg EMB_FUNC_EN_A
7374 * @retval interface status (MANDATORY: return 0 -> no Error)
7375 *
7376 */
lsm6dso32_tilt_sens_set(stmdev_ctx_t * ctx,uint8_t val)7377 int32_t lsm6dso32_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
7378 {
7379 lsm6dso32_emb_func_en_a_t reg;
7380 int32_t ret;
7381
7382 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
7383
7384 if (ret == 0)
7385 {
7386 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
7387 (uint8_t *)®, 1);
7388 }
7389
7390 if (ret == 0)
7391 {
7392 reg.tilt_en = val;
7393 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
7394 (uint8_t *)®, 1);
7395 }
7396
7397 if (ret == 0)
7398 {
7399 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
7400 }
7401
7402 return ret;
7403 }
7404
7405 /**
7406 * @brief Enable tilt calculation.[get]
7407 *
7408 * @param ctx read / write interface definitions
7409 * @param val change the values of tilt_en in reg EMB_FUNC_EN_A
7410 * @retval interface status (MANDATORY: return 0 -> no Error)
7411 *
7412 */
lsm6dso32_tilt_sens_get(stmdev_ctx_t * ctx,uint8_t * val)7413 int32_t lsm6dso32_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
7414 {
7415 lsm6dso32_emb_func_en_a_t reg;
7416 int32_t ret;
7417
7418 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
7419
7420 if (ret == 0)
7421 {
7422 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_A,
7423 (uint8_t *)®, 1);
7424 }
7425
7426 if (ret == 0)
7427 {
7428 *val = reg.tilt_en;
7429 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
7430 }
7431
7432 return ret;
7433 }
7434
7435 /**
7436 * @brief Interrupt status bit for tilt detection.[get]
7437 *
7438 * @param ctx read / write interface definitions
7439 * @param val change the values of is_tilt in reg EMB_FUNC_STATUS
7440 * @retval interface status (MANDATORY: return 0 -> no Error)
7441 *
7442 */
lsm6dso32_tilt_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)7443 int32_t lsm6dso32_tilt_flag_data_ready_get(stmdev_ctx_t *ctx,
7444 uint8_t *val)
7445 {
7446 lsm6dso32_emb_func_status_t reg;
7447 int32_t ret;
7448
7449 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
7450
7451 if (ret == 0)
7452 {
7453 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_STATUS,
7454 (uint8_t *)®, 1);
7455 }
7456
7457 if (ret == 0)
7458 {
7459 *val = reg.is_tilt;
7460 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
7461 }
7462
7463 return ret;
7464 }
7465
7466 /**
7467 * @}
7468 *
7469 */
7470
7471 /**
7472 * @defgroup LSM6DSO32_ magnetometer_sensor
7473 * @brief This section groups all the functions that manage additional
7474 * magnetometer sensor.
7475 * @{
7476 *
7477 */
7478
7479 /**
7480 * @brief External magnetometer sensitivity value register.[set]
7481 *
7482 * @param ctx read / write interface definitions
7483 * @param buff buffer that contains data to write
7484 * @retval interface status (MANDATORY: return 0 -> no Error)
7485 *
7486 */
lsm6dso32_mag_sensitivity_set(stmdev_ctx_t * ctx,uint16_t val)7487 int32_t lsm6dso32_mag_sensitivity_set(stmdev_ctx_t *ctx, uint16_t val)
7488 {
7489 uint8_t buff[2];
7490 int32_t ret;
7491
7492 buff[1] = (uint8_t)(val / 256U);
7493 buff[0] = (uint8_t)(val - (buff[1] * 256U));
7494 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SENSITIVITY_L,
7495 &buff[0]);
7496
7497 if (ret == 0)
7498 {
7499 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SENSITIVITY_H,
7500 &buff[1]);
7501 }
7502
7503 return ret;
7504 }
7505
7506 /**
7507 * @brief External magnetometer sensitivity value register.[get]
7508 *
7509 * @param ctx read / write interface definitions
7510 * @param buff buffer that stores data read
7511 * @retval interface status (MANDATORY: return 0 -> no Error)
7512 *
7513 */
lsm6dso32_mag_sensitivity_get(stmdev_ctx_t * ctx,uint16_t * val)7514 int32_t lsm6dso32_mag_sensitivity_get(stmdev_ctx_t *ctx,
7515 uint16_t *val)
7516 {
7517 uint8_t buff[2];
7518 int32_t ret;
7519
7520 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SENSITIVITY_L,
7521 &buff[0]);
7522
7523 if (ret == 0)
7524 {
7525 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SENSITIVITY_H,
7526 &buff[1]);
7527 *val = buff[1];
7528 *val = (*val * 256U) + buff[0];
7529 }
7530
7531 return ret;
7532 }
7533
7534 /**
7535 * @brief Offset for hard-iron compensation register (r/w).[set]
7536 *
7537 * @param ctx read / write interface definitions
7538 * @param buff buffer that contains data to write
7539 * @retval interface status (MANDATORY: return 0 -> no Error)
7540 *
7541 */
lsm6dso32_mag_offset_set(stmdev_ctx_t * ctx,int16_t * val)7542 int32_t lsm6dso32_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
7543 {
7544 uint8_t buff[6];
7545 int32_t ret;
7546
7547 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
7548 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
7549 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
7550 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
7551 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
7552 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
7553 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFX_L,
7554 &buff[0]);
7555
7556 if (ret == 0)
7557 {
7558 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFX_H,
7559 &buff[1]);
7560 }
7561
7562 if (ret == 0)
7563 {
7564 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFY_L,
7565 &buff[2]);
7566 }
7567
7568 if (ret == 0)
7569 {
7570 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFY_H,
7571 &buff[3]);
7572 }
7573
7574 if (ret == 0)
7575 {
7576 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFZ_L,
7577 &buff[4]);
7578 }
7579
7580 if (ret == 0)
7581 {
7582 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_OFFZ_H,
7583 &buff[5]);
7584 }
7585
7586 return ret;
7587 }
7588
7589 /**
7590 * @brief Offset for hard-iron compensation register (r/w).[get]
7591 *
7592 * @param ctx read / write interface definitions
7593 * @param buff buffer that stores data read
7594 * @retval interface status (MANDATORY: return 0 -> no Error)
7595 *
7596 */
lsm6dso32_mag_offset_get(stmdev_ctx_t * ctx,int16_t * val)7597 int32_t lsm6dso32_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
7598 {
7599 uint8_t buff[6];
7600 int32_t ret;
7601
7602 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFX_L,
7603 &buff[0]);
7604
7605 if (ret == 0)
7606 {
7607 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFX_H,
7608 &buff[1]);
7609 }
7610
7611 if (ret == 0)
7612 {
7613 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFY_L,
7614 &buff[2]);
7615 }
7616
7617 if (ret == 0)
7618 {
7619 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFY_H,
7620 &buff[3]);
7621 }
7622
7623 if (ret == 0)
7624 {
7625 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFZ_L,
7626 &buff[4]);
7627 }
7628
7629 if (ret == 0)
7630 {
7631 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_OFFZ_H,
7632 &buff[5]);
7633 val[0] = (int16_t)buff[1];
7634 val[0] = (val[0] * 256) + (int16_t)buff[0];
7635 val[1] = (int16_t)buff[3];
7636 val[1] = (val[1] * 256) + (int16_t)buff[2];
7637 val[2] = (int16_t)buff[5];
7638 val[2] = (val[2] * 256) + (int16_t)buff[4];
7639 }
7640
7641 return ret;
7642 }
7643
7644 /**
7645 * @brief Soft-iron (3x3 symmetric) matrix correction
7646 * register (r/w). The value is expressed as
7647 * half-precision floating-point format:
7648 * SEEEEEFFFFFFFFFF
7649 * S: 1 sign bit;
7650 * E: 5 exponent bits;
7651 * F: 10 fraction bits).[set]
7652 *
7653 * @param ctx read / write interface definitions
7654 * @param buff buffer that contains data to write
7655 * @retval interface status (MANDATORY: return 0 -> no Error)
7656 *
7657 */
lsm6dso32_mag_soft_iron_set(stmdev_ctx_t * ctx,int16_t * val)7658 int32_t lsm6dso32_mag_soft_iron_set(stmdev_ctx_t *ctx, int16_t *val)
7659 {
7660 uint8_t buff[12];
7661 int32_t ret;
7662
7663 uint8_t index;
7664 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
7665 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
7666 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
7667 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
7668 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
7669 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
7670 buff[7] = (uint8_t)((uint16_t)val[3] / 256U);
7671 buff[6] = (uint8_t)((uint16_t)val[3] - (buff[7] * 256U));
7672 buff[9] = (uint8_t)((uint16_t)val[4] / 256U);
7673 buff[8] = (uint8_t)((uint16_t)val[4] - (buff[9] * 256U));
7674 buff[11] = (uint8_t)((uint16_t)val[5] / 256U);
7675 buff[10] = (uint8_t)((uint16_t)val[5] - (buff[11] * 256U));
7676 index = 0x00U;
7677 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XX_L,
7678 &buff[index]);
7679
7680 if (ret == 0)
7681 {
7682 index++;
7683 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XX_H,
7684 &buff[index]);
7685 }
7686
7687 if (ret == 0)
7688 {
7689 index++;
7690 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XY_L,
7691 &buff[index]);
7692 }
7693
7694 if (ret == 0)
7695 {
7696 index++;
7697 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XY_H,
7698 &buff[index]);
7699 }
7700
7701 if (ret == 0)
7702 {
7703 index++;
7704 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XZ_L,
7705 &buff[index]);
7706 }
7707
7708 if (ret == 0)
7709 {
7710 index++;
7711 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_XZ_H,
7712 &buff[index]);
7713 }
7714
7715 if (ret == 0)
7716 {
7717 index++;
7718 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_YY_L,
7719 &buff[index]);
7720 }
7721
7722 if (ret == 0)
7723 {
7724 index++;
7725 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_YY_H,
7726 &buff[index]);
7727 }
7728
7729 if (ret == 0)
7730 {
7731 index++;
7732 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_YZ_L,
7733 &buff[index]);
7734 }
7735
7736 if (ret == 0)
7737 {
7738 index++;
7739 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_YZ_H,
7740 &buff[index]);
7741 }
7742
7743 if (ret == 0)
7744 {
7745 index++;
7746 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_ZZ_L,
7747 &buff[index]);
7748 }
7749
7750 if (ret == 0)
7751 {
7752 index++;
7753 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_SI_ZZ_H,
7754 &buff[index]);
7755 }
7756
7757 return ret;
7758 }
7759
7760 /**
7761 * @brief Soft-iron (3x3 symmetric) matrix
7762 * correction register (r/w).
7763 * The value is expressed as half-precision
7764 * floating-point format:
7765 * SEEEEEFFFFFFFFFF
7766 * S: 1 sign bit;
7767 * E: 5 exponent bits;
7768 * F: 10 fraction bits.[get]
7769 *
7770 * @param ctx read / write interface definitions
7771 * @param buff buffer that stores data read
7772 * @retval interface status (MANDATORY: return 0 -> no Error)
7773 *
7774 */
lsm6dso32_mag_soft_iron_get(stmdev_ctx_t * ctx,int16_t * val)7775 int32_t lsm6dso32_mag_soft_iron_get(stmdev_ctx_t *ctx, int16_t *val)
7776 {
7777 uint8_t buff[12];
7778 int32_t ret;
7779
7780 uint8_t index;
7781 index = 0x00U;
7782 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XX_L,
7783 &buff[index]);
7784
7785 if (ret == 0)
7786 {
7787 index++;
7788 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XX_H,
7789 &buff[index]);
7790 }
7791
7792 if (ret == 0)
7793 {
7794 index++;
7795 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XY_L,
7796 &buff[index]);
7797 }
7798
7799 if (ret == 0)
7800 {
7801 index++;
7802 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XY_H,
7803 &buff[index]);
7804 }
7805
7806 if (ret == 0)
7807 {
7808 index++;
7809 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XZ_L,
7810 &buff[index]);
7811 }
7812
7813 if (ret == 0)
7814 {
7815 index++;
7816 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_XZ_H,
7817 &buff[index]);
7818 }
7819
7820 if (ret == 0)
7821 {
7822 index++;
7823 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_YY_L,
7824 &buff[index]);
7825 }
7826
7827 if (ret == 0)
7828 {
7829 index++;
7830 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_YY_H,
7831 &buff[index]);
7832 }
7833
7834 if (ret == 0)
7835 {
7836 index++;
7837 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_YZ_L,
7838 &buff[index]);
7839 }
7840
7841 if (ret == 0)
7842 {
7843 index++;
7844 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_YZ_H,
7845 &buff[index]);
7846 }
7847
7848 if (ret == 0)
7849 {
7850 index++;
7851 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_ZZ_L,
7852 &buff[index]);
7853 }
7854
7855 if (ret == 0)
7856 {
7857 index++;
7858 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_SI_ZZ_H,
7859 &buff[index]);
7860 }
7861
7862 val[0] = (int16_t)buff[1];
7863 val[0] = (val[0] * 256) + (int16_t)buff[0];
7864 val[1] = (int16_t)buff[3];
7865 val[1] = (val[1] * 256) + (int16_t)buff[2];
7866 val[2] = (int16_t)buff[5];
7867 val[2] = (val[2] * 256) + (int16_t)buff[4];
7868 val[3] = (int16_t)buff[7];
7869 val[3] = (val[3] * 256) + (int16_t)buff[6];
7870 val[4] = (int16_t)buff[9];
7871 val[4] = (val[4] * 256) + (int16_t)buff[8];
7872 val[5] = (int16_t)buff[11];
7873 val[5] = (val[5] * 256) + (int16_t)buff[10];
7874
7875 return ret;
7876 }
7877
7878 /**
7879 * @brief Magnetometer Z-axis coordinates
7880 * rotation (to be aligned to
7881 * accelerometer/gyroscope axes
7882 * orientation).[set]
7883 *
7884 * @param ctx read / write interface definitions
7885 * @param val change the values of mag_z_axis in reg MAG_CFG_A
7886 * @retval interface status (MANDATORY: return 0 -> no Error)
7887 *
7888 */
lsm6dso32_mag_z_orient_set(stmdev_ctx_t * ctx,lsm6dso32_mag_z_axis_t val)7889 int32_t lsm6dso32_mag_z_orient_set(stmdev_ctx_t *ctx,
7890 lsm6dso32_mag_z_axis_t val)
7891 {
7892 lsm6dso32_mag_cfg_a_t reg;
7893 int32_t ret;
7894
7895 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_A,
7896 (uint8_t *)®);
7897
7898 if (ret == 0)
7899 {
7900 reg.mag_z_axis = (uint8_t) val;
7901 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_CFG_A,
7902 (uint8_t *)®);
7903 }
7904
7905 return ret;
7906 }
7907
7908 /**
7909 * @brief Magnetometer Z-axis coordinates
7910 * rotation (to be aligned to
7911 * accelerometer/gyroscope axes
7912 * orientation).[get]
7913 *
7914 * @param ctx read / write interface definitions
7915 * @param val Get the values of mag_z_axis in reg MAG_CFG_A
7916 * @retval interface status (MANDATORY: return 0 -> no Error)
7917 *
7918 */
lsm6dso32_mag_z_orient_get(stmdev_ctx_t * ctx,lsm6dso32_mag_z_axis_t * val)7919 int32_t lsm6dso32_mag_z_orient_get(stmdev_ctx_t *ctx,
7920 lsm6dso32_mag_z_axis_t *val)
7921 {
7922 lsm6dso32_mag_cfg_a_t reg;
7923 int32_t ret;
7924
7925 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_A,
7926 (uint8_t *)®);
7927
7928 switch (reg.mag_z_axis)
7929 {
7930 case LSM6DSO32_Z_EQ_Y:
7931 *val = LSM6DSO32_Z_EQ_Y;
7932 break;
7933
7934 case LSM6DSO32_Z_EQ_MIN_Y:
7935 *val = LSM6DSO32_Z_EQ_MIN_Y;
7936 break;
7937
7938 case LSM6DSO32_Z_EQ_X:
7939 *val = LSM6DSO32_Z_EQ_X;
7940 break;
7941
7942 case LSM6DSO32_Z_EQ_MIN_X:
7943 *val = LSM6DSO32_Z_EQ_MIN_X;
7944 break;
7945
7946 case LSM6DSO32_Z_EQ_MIN_Z:
7947 *val = LSM6DSO32_Z_EQ_MIN_Z;
7948 break;
7949
7950 case LSM6DSO32_Z_EQ_Z:
7951 *val = LSM6DSO32_Z_EQ_Z;
7952 break;
7953
7954 default:
7955 *val = LSM6DSO32_Z_EQ_Y;
7956 break;
7957 }
7958
7959 return ret;
7960 }
7961
7962 /**
7963 * @brief Magnetometer Y-axis coordinates
7964 * rotation (to be aligned to
7965 * accelerometer/gyroscope axes
7966 * orientation).[set]
7967 *
7968 * @param ctx read / write interface definitions
7969 * @param val change the values of mag_y_axis in reg MAG_CFG_A
7970 * @retval interface status (MANDATORY: return 0 -> no Error)
7971 *
7972 */
lsm6dso32_mag_y_orient_set(stmdev_ctx_t * ctx,lsm6dso32_mag_y_axis_t val)7973 int32_t lsm6dso32_mag_y_orient_set(stmdev_ctx_t *ctx,
7974 lsm6dso32_mag_y_axis_t val)
7975 {
7976 lsm6dso32_mag_cfg_a_t reg;
7977 int32_t ret;
7978
7979 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_A,
7980 (uint8_t *)®);
7981
7982 if (ret == 0)
7983 {
7984 reg.mag_y_axis = (uint8_t)val;
7985 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_CFG_A,
7986 (uint8_t *) ®);
7987 }
7988
7989 return ret;
7990 }
7991
7992 /**
7993 * @brief Magnetometer Y-axis coordinates
7994 * rotation (to be aligned to
7995 * accelerometer/gyroscope axes
7996 * orientation).[get]
7997 *
7998 * @param ctx read / write interface definitions
7999 * @param val Get the values of mag_y_axis in reg MAG_CFG_A
8000 * @retval interface status (MANDATORY: return 0 -> no Error)
8001 *
8002 */
lsm6dso32_mag_y_orient_get(stmdev_ctx_t * ctx,lsm6dso32_mag_y_axis_t * val)8003 int32_t lsm6dso32_mag_y_orient_get(stmdev_ctx_t *ctx,
8004 lsm6dso32_mag_y_axis_t *val)
8005 {
8006 lsm6dso32_mag_cfg_a_t reg;
8007 int32_t ret;
8008
8009 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_A,
8010 (uint8_t *)®);
8011
8012 switch (reg.mag_y_axis)
8013 {
8014 case LSM6DSO32_Y_EQ_Y:
8015 *val = LSM6DSO32_Y_EQ_Y;
8016 break;
8017
8018 case LSM6DSO32_Y_EQ_MIN_Y:
8019 *val = LSM6DSO32_Y_EQ_MIN_Y;
8020 break;
8021
8022 case LSM6DSO32_Y_EQ_X:
8023 *val = LSM6DSO32_Y_EQ_X;
8024 break;
8025
8026 case LSM6DSO32_Y_EQ_MIN_X:
8027 *val = LSM6DSO32_Y_EQ_MIN_X;
8028 break;
8029
8030 case LSM6DSO32_Y_EQ_MIN_Z:
8031 *val = LSM6DSO32_Y_EQ_MIN_Z;
8032 break;
8033
8034 case LSM6DSO32_Y_EQ_Z:
8035 *val = LSM6DSO32_Y_EQ_Z;
8036 break;
8037
8038 default:
8039 *val = LSM6DSO32_Y_EQ_Y;
8040 break;
8041 }
8042
8043 return ret;
8044 }
8045
8046 /**
8047 * @brief Magnetometer X-axis coordinates
8048 * rotation (to be aligned to
8049 * accelerometer/gyroscope axes
8050 * orientation).[set]
8051 *
8052 * @param ctx read / write interface definitions
8053 * @param val change the values of mag_x_axis in reg MAG_CFG_B
8054 * @retval interface status (MANDATORY: return 0 -> no Error)
8055 *
8056 */
lsm6dso32_mag_x_orient_set(stmdev_ctx_t * ctx,lsm6dso32_mag_x_axis_t val)8057 int32_t lsm6dso32_mag_x_orient_set(stmdev_ctx_t *ctx,
8058 lsm6dso32_mag_x_axis_t val)
8059 {
8060 lsm6dso32_mag_cfg_b_t reg;
8061 int32_t ret;
8062
8063 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_B,
8064 (uint8_t *)®);
8065
8066 if (ret == 0)
8067 {
8068 reg.mag_x_axis = (uint8_t)val;
8069 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_MAG_CFG_B,
8070 (uint8_t *)®);
8071 }
8072
8073 return ret;
8074 }
8075
8076 /**
8077 * @brief Magnetometer X-axis coordinates
8078 * rotation (to be aligned to
8079 * accelerometer/gyroscope axes
8080 * orientation).[get]
8081 *
8082 * @param ctx read / write interface definitions
8083 * @param val Get the values of mag_x_axis in reg MAG_CFG_B
8084 * @retval interface status (MANDATORY: return 0 -> no Error)
8085 *
8086 */
lsm6dso32_mag_x_orient_get(stmdev_ctx_t * ctx,lsm6dso32_mag_x_axis_t * val)8087 int32_t lsm6dso32_mag_x_orient_get(stmdev_ctx_t *ctx,
8088 lsm6dso32_mag_x_axis_t *val)
8089 {
8090 lsm6dso32_mag_cfg_b_t reg;
8091 int32_t ret;
8092
8093 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_MAG_CFG_B,
8094 (uint8_t *)®);
8095
8096 switch (reg.mag_x_axis)
8097 {
8098 case LSM6DSO32_X_EQ_Y:
8099 *val = LSM6DSO32_X_EQ_Y;
8100 break;
8101
8102 case LSM6DSO32_X_EQ_MIN_Y:
8103 *val = LSM6DSO32_X_EQ_MIN_Y;
8104 break;
8105
8106 case LSM6DSO32_X_EQ_X:
8107 *val = LSM6DSO32_X_EQ_X;
8108 break;
8109
8110 case LSM6DSO32_X_EQ_MIN_X:
8111 *val = LSM6DSO32_X_EQ_MIN_X;
8112 break;
8113
8114 case LSM6DSO32_X_EQ_MIN_Z:
8115 *val = LSM6DSO32_X_EQ_MIN_Z;
8116 break;
8117
8118 case LSM6DSO32_X_EQ_Z:
8119 *val = LSM6DSO32_X_EQ_Z;
8120 break;
8121
8122 default:
8123 *val = LSM6DSO32_X_EQ_Y;
8124 break;
8125 }
8126
8127 return ret;
8128 }
8129
8130 /**
8131 * @}
8132 *
8133 */
8134
8135 /**
8136 * @defgroup LSM6DSO32_finite_state_machine
8137 * @brief This section groups all the functions that manage the
8138 * state_machine.
8139 * @{
8140 *
8141 */
8142
8143 /**
8144 * @brief Interrupt status bit for FSM long counter
8145 * timeout interrupt event.[get]
8146 *
8147 * @param ctx read / write interface definitions
8148 * @param val change the values of is_fsm_lc in reg EMB_FUNC_STATUS
8149 * @retval interface status (MANDATORY: return 0 -> no Error)
8150 *
8151 */
lsm6dso32_long_cnt_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)8152 int32_t lsm6dso32_long_cnt_flag_data_ready_get(stmdev_ctx_t *ctx,
8153 uint8_t *val)
8154 {
8155 lsm6dso32_emb_func_status_t reg;
8156 int32_t ret;
8157
8158 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8159
8160 if (ret == 0)
8161 {
8162 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_STATUS,
8163 (uint8_t *)®, 1);
8164 }
8165
8166 if (ret == 0)
8167 {
8168 *val = reg.is_fsm_lc;
8169 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8170 }
8171
8172 return ret;
8173 }
8174
8175 /**
8176 * @brief Final State Machine global enable.[set]
8177 *
8178 * @param ctx read / write interface definitions
8179 * @param val change the values of fsm_en in reg EMB_FUNC_EN_B
8180 * @retval interface status (MANDATORY: return 0 -> no Error)
8181 *
8182 */
lsm6dso32_emb_fsm_en_set(stmdev_ctx_t * ctx,uint8_t val)8183 int32_t lsm6dso32_emb_fsm_en_set(stmdev_ctx_t *ctx, uint8_t val)
8184 {
8185 int32_t ret;
8186
8187 lsm6dso32_emb_func_en_b_t reg;
8188 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8189
8190 if (ret == 0)
8191 {
8192 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
8193 (uint8_t *)®, 1);
8194 }
8195
8196 if (ret == 0)
8197 {
8198 reg.fsm_en = val;
8199 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
8200 (uint8_t *)®, 1);
8201 }
8202
8203 if (ret == 0)
8204 {
8205 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8206 }
8207
8208 return ret;
8209 }
8210
8211 /**
8212 * @brief Final State Machine global enable.[get]
8213 *
8214 * @param ctx read / write interface definitions
8215 * @param uint8_t *: return the values of fsm_en in reg EMB_FUNC_EN_B
8216 * @retval interface status (MANDATORY: return 0 -> no Error)
8217 *
8218 */
lsm6dso32_emb_fsm_en_get(stmdev_ctx_t * ctx,uint8_t * val)8219 int32_t lsm6dso32_emb_fsm_en_get(stmdev_ctx_t *ctx, uint8_t *val)
8220 {
8221 int32_t ret;
8222
8223 lsm6dso32_emb_func_en_b_t reg;
8224 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8225
8226 if (ret == 0)
8227 {
8228 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
8229 (uint8_t *)®, 1);
8230 }
8231
8232 if (ret == 0)
8233 {
8234 *val = reg.fsm_en;
8235 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
8236 (uint8_t *)®, 1);
8237 }
8238
8239 if (ret == 0)
8240 {
8241 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8242 }
8243
8244 return ret;
8245 }
8246
8247 /**
8248 * @brief Final State Machine enable.[set]
8249 *
8250 * @param ctx read / write interface definitions
8251 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
8252 * @retval interface status (MANDATORY: return 0 -> no Error)
8253 *
8254 */
lsm6dso32_fsm_enable_set(stmdev_ctx_t * ctx,lsm6dso32_emb_fsm_enable_t * val)8255 int32_t lsm6dso32_fsm_enable_set(stmdev_ctx_t *ctx,
8256 lsm6dso32_emb_fsm_enable_t *val)
8257 {
8258 int32_t ret;
8259
8260 lsm6dso32_emb_func_en_b_t reg;
8261 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8262
8263 if (ret == 0)
8264 {
8265 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_ENABLE_A,
8266 (uint8_t *)&val->fsm_enable_a, 1);
8267 }
8268
8269 if (ret == 0)
8270 {
8271 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_ENABLE_B,
8272 (uint8_t *)&val->fsm_enable_b, 1);
8273 }
8274
8275 if (ret == 0)
8276 {
8277 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
8278 (uint8_t *)®, 1);
8279 }
8280
8281 if (ret == 0)
8282 {
8283 if ((val->fsm_enable_a.fsm1_en |
8284 val->fsm_enable_a.fsm2_en |
8285 val->fsm_enable_a.fsm3_en |
8286 val->fsm_enable_a.fsm4_en |
8287 val->fsm_enable_a.fsm5_en |
8288 val->fsm_enable_a.fsm6_en |
8289 val->fsm_enable_a.fsm7_en |
8290 val->fsm_enable_a.fsm8_en |
8291 val->fsm_enable_b.fsm9_en |
8292 val->fsm_enable_b.fsm10_en |
8293 val->fsm_enable_b.fsm11_en |
8294 val->fsm_enable_b.fsm12_en |
8295 val->fsm_enable_b.fsm13_en |
8296 val->fsm_enable_b.fsm14_en |
8297 val->fsm_enable_b.fsm15_en |
8298 val->fsm_enable_b.fsm16_en)
8299 != PROPERTY_DISABLE)
8300 {
8301 reg.fsm_en = PROPERTY_ENABLE;
8302 }
8303
8304 else
8305 {
8306 reg.fsm_en = PROPERTY_DISABLE;
8307 }
8308
8309 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_EN_B,
8310 (uint8_t *)®, 1);
8311 }
8312
8313 if (ret == 0)
8314 {
8315 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8316 }
8317
8318 return ret;
8319 }
8320
8321 /**
8322 * @brief Final State Machine enable.[get]
8323 *
8324 * @param ctx read / write interface definitions
8325 * @param val union of registers from FSM_ENABLE_A to FSM_ENABLE_B
8326 * @retval interface status (MANDATORY: return 0 -> no Error)
8327 *
8328 */
lsm6dso32_fsm_enable_get(stmdev_ctx_t * ctx,lsm6dso32_emb_fsm_enable_t * val)8329 int32_t lsm6dso32_fsm_enable_get(stmdev_ctx_t *ctx,
8330 lsm6dso32_emb_fsm_enable_t *val)
8331 {
8332 int32_t ret;
8333
8334 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8335
8336 if (ret == 0)
8337 {
8338 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_ENABLE_A, (uint8_t *) val,
8339 2);
8340 }
8341
8342 if (ret == 0)
8343 {
8344 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8345 }
8346
8347 return ret;
8348 }
8349
8350 /**
8351 * @brief FSM long counter status register. Long counter value is an
8352 * unsigned integer value (16-bit format).[set]
8353 *
8354 * @param ctx read / write interface definitions
8355 * @param buff buffer that contains data to write
8356 * @retval interface status (MANDATORY: return 0 -> no Error)
8357 *
8358 */
lsm6dso32_long_cnt_set(stmdev_ctx_t * ctx,uint16_t val)8359 int32_t lsm6dso32_long_cnt_set(stmdev_ctx_t *ctx, uint16_t val)
8360 {
8361 uint8_t buff[2];
8362 int32_t ret;
8363
8364 buff[1] = (uint8_t)(val / 256U);
8365 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8366 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8367
8368 if (ret == 0)
8369 {
8370 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_LONG_COUNTER_L, buff, 2);
8371 }
8372
8373 if (ret == 0)
8374 {
8375 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8376 }
8377
8378 return ret;
8379 }
8380
8381 /**
8382 * @brief FSM long counter status register. Long counter value is an
8383 * unsigned integer value (16-bit format).[get]
8384 *
8385 * @param ctx read / write interface definitions
8386 * @param buff buffer that stores data read
8387 * @retval interface status (MANDATORY: return 0 -> no Error)
8388 *
8389 */
lsm6dso32_long_cnt_get(stmdev_ctx_t * ctx,uint16_t * val)8390 int32_t lsm6dso32_long_cnt_get(stmdev_ctx_t *ctx, uint16_t *val)
8391 {
8392 uint8_t buff[2];
8393 int32_t ret;
8394
8395 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8396
8397 if (ret == 0)
8398 {
8399 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_LONG_COUNTER_L, buff, 2);
8400 }
8401
8402 if (ret == 0)
8403 {
8404 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8405 *val = buff[1];
8406 *val = (*val * 256U) + buff[0];
8407 }
8408
8409 return ret;
8410 }
8411
8412 /**
8413 * @brief Clear FSM long counter value.[set]
8414 *
8415 * @param ctx read / write interface definitions
8416 * @param val change the values of fsm_lc_clr in
8417 * reg FSM_LONG_COUNTER_CLEAR
8418 * @retval interface status (MANDATORY: return 0 -> no Error)
8419 *
8420 */
lsm6dso32_long_clr_set(stmdev_ctx_t * ctx,lsm6dso32_fsm_lc_clr_t val)8421 int32_t lsm6dso32_long_clr_set(stmdev_ctx_t *ctx,
8422 lsm6dso32_fsm_lc_clr_t val)
8423 {
8424 lsm6dso32_fsm_long_counter_clear_t reg;
8425 int32_t ret;
8426
8427 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8428
8429 if (ret == 0)
8430 {
8431 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_LONG_COUNTER_CLEAR,
8432 (uint8_t *)®, 1);
8433 }
8434
8435 if (ret == 0)
8436 {
8437 reg. fsm_lc_clr = (uint8_t)val;
8438 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_FSM_LONG_COUNTER_CLEAR,
8439 (uint8_t *)®, 1);
8440 }
8441
8442 if (ret == 0)
8443 {
8444 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8445 }
8446
8447 return ret;
8448 }
8449
8450 /**
8451 * @brief Clear FSM long counter value.[get]
8452 *
8453 * @param ctx read / write interface definitions
8454 * @param val Get the values of fsm_lc_clr in
8455 * reg FSM_LONG_COUNTER_CLEAR
8456 * @retval interface status (MANDATORY: return 0 -> no Error)
8457 *
8458 */
lsm6dso32_long_clr_get(stmdev_ctx_t * ctx,lsm6dso32_fsm_lc_clr_t * val)8459 int32_t lsm6dso32_long_clr_get(stmdev_ctx_t *ctx,
8460 lsm6dso32_fsm_lc_clr_t *val)
8461 {
8462 lsm6dso32_fsm_long_counter_clear_t reg;
8463 int32_t ret;
8464
8465 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8466
8467 if (ret == 0)
8468 {
8469 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_LONG_COUNTER_CLEAR,
8470 (uint8_t *)®, 1);
8471 }
8472
8473 if (ret == 0)
8474 {
8475 switch (reg.fsm_lc_clr)
8476 {
8477 case LSM6DSO32_LC_NORMAL:
8478 *val = LSM6DSO32_LC_NORMAL;
8479 break;
8480
8481 case LSM6DSO32_LC_CLEAR:
8482 *val = LSM6DSO32_LC_CLEAR;
8483 break;
8484
8485 case LSM6DSO32_LC_CLEAR_DONE:
8486 *val = LSM6DSO32_LC_CLEAR_DONE;
8487 break;
8488
8489 default:
8490 *val = LSM6DSO32_LC_NORMAL;
8491 break;
8492 }
8493 }
8494
8495 if (ret == 0)
8496 {
8497 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8498 }
8499
8500 return ret;
8501 }
8502
8503 /**
8504 * @brief FSM output registers[get]
8505 *
8506 * @param ctx read / write interface definitions
8507 * @param val struct of registers from FSM_OUTS1 to FSM_OUTS16
8508 * @retval interface status (MANDATORY: return 0 -> no Error)
8509 *
8510 */
lsm6dso32_fsm_out_get(stmdev_ctx_t * ctx,lsm6dso32_fsm_out_t * val)8511 int32_t lsm6dso32_fsm_out_get(stmdev_ctx_t *ctx,
8512 lsm6dso32_fsm_out_t *val)
8513 {
8514 int32_t ret;
8515
8516 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8517
8518 if (ret == 0)
8519 {
8520 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_FSM_OUTS1, (uint8_t *) &val,
8521 16);
8522 }
8523
8524 if (ret == 0)
8525 {
8526 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8527 }
8528
8529 return ret;
8530 }
8531
8532 /**
8533 * @brief Finite State Machine ODR configuration.[set]
8534 *
8535 * @param ctx read / write interface definitions
8536 * @param val change the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
8537 * @retval interface status (MANDATORY: return 0 -> no Error)
8538 *
8539 */
lsm6dso32_fsm_data_rate_set(stmdev_ctx_t * ctx,lsm6dso32_fsm_odr_t val)8540 int32_t lsm6dso32_fsm_data_rate_set(stmdev_ctx_t *ctx,
8541 lsm6dso32_fsm_odr_t val)
8542 {
8543 lsm6dso32_emb_func_odr_cfg_b_t reg;
8544 int32_t ret;
8545
8546 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8547
8548 if (ret == 0)
8549 {
8550 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_ODR_CFG_B,
8551 (uint8_t *)®, 1);
8552 }
8553
8554 if (ret == 0)
8555 {
8556 reg.not_used_01 = 3; /* set default values */
8557 reg.not_used_02 = 1; /* set default values */
8558 reg.fsm_odr = (uint8_t)val;
8559 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_ODR_CFG_B,
8560 (uint8_t *)®, 1);
8561 }
8562
8563 if (ret == 0)
8564 {
8565 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8566 }
8567
8568 return ret;
8569 }
8570
8571 /**
8572 * @brief Finite State Machine ODR configuration.[get]
8573 *
8574 * @param ctx read / write interface definitions
8575 * @param val Get the values of fsm_odr in reg EMB_FUNC_ODR_CFG_B
8576 * @retval interface status (MANDATORY: return 0 -> no Error)
8577 *
8578 */
lsm6dso32_fsm_data_rate_get(stmdev_ctx_t * ctx,lsm6dso32_fsm_odr_t * val)8579 int32_t lsm6dso32_fsm_data_rate_get(stmdev_ctx_t *ctx,
8580 lsm6dso32_fsm_odr_t *val)
8581 {
8582 lsm6dso32_emb_func_odr_cfg_b_t reg;
8583 int32_t ret;
8584
8585 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8586
8587 if (ret == 0)
8588 {
8589 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_ODR_CFG_B,
8590 (uint8_t *)®, 1);
8591 }
8592
8593 if (ret == 0)
8594 {
8595 switch (reg.fsm_odr)
8596 {
8597 case LSM6DSO32_ODR_FSM_12Hz5:
8598 *val = LSM6DSO32_ODR_FSM_12Hz5;
8599 break;
8600
8601 case LSM6DSO32_ODR_FSM_26Hz:
8602 *val = LSM6DSO32_ODR_FSM_26Hz;
8603 break;
8604
8605 case LSM6DSO32_ODR_FSM_52Hz:
8606 *val = LSM6DSO32_ODR_FSM_52Hz;
8607 break;
8608
8609 case LSM6DSO32_ODR_FSM_104Hz:
8610 *val = LSM6DSO32_ODR_FSM_104Hz;
8611 break;
8612
8613 default:
8614 *val = LSM6DSO32_ODR_FSM_12Hz5;
8615 break;
8616 }
8617
8618 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8619 }
8620
8621 return ret;
8622 }
8623
8624 /**
8625 * @brief FSM initialization request.[set]
8626 *
8627 * @param ctx read / write interface definitions
8628 * @param val change the values of fsm_init in reg FSM_INIT
8629 * @retval interface status (MANDATORY: return 0 -> no Error)
8630 *
8631 */
lsm6dso32_fsm_init_set(stmdev_ctx_t * ctx,uint8_t val)8632 int32_t lsm6dso32_fsm_init_set(stmdev_ctx_t *ctx, uint8_t val)
8633 {
8634 lsm6dso32_emb_func_init_b_t reg;
8635 int32_t ret;
8636
8637 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8638
8639 if (ret == 0)
8640 {
8641 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INIT_B,
8642 (uint8_t *)®, 1);
8643 }
8644
8645 if (ret == 0)
8646 {
8647 reg.fsm_init = val;
8648 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_EMB_FUNC_INIT_B,
8649 (uint8_t *)®, 1);
8650 }
8651
8652 if (ret == 0)
8653 {
8654 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8655 }
8656
8657 return ret;
8658 }
8659
8660 /**
8661 * @brief FSM initialization request.[get]
8662 *
8663 * @param ctx read / write interface definitions
8664 * @param val change the values of fsm_init in reg FSM_INIT
8665 * @retval interface status (MANDATORY: return 0 -> no Error)
8666 *
8667 */
lsm6dso32_fsm_init_get(stmdev_ctx_t * ctx,uint8_t * val)8668 int32_t lsm6dso32_fsm_init_get(stmdev_ctx_t *ctx, uint8_t *val)
8669 {
8670 lsm6dso32_emb_func_init_b_t reg;
8671 int32_t ret;
8672
8673 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_EMBEDDED_FUNC_BANK);
8674
8675 if (ret == 0)
8676 {
8677 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_EMB_FUNC_INIT_B,
8678 (uint8_t *)®, 1);
8679 }
8680
8681 if (ret == 0)
8682 {
8683 *val = reg.fsm_init;
8684 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8685 }
8686
8687 return ret;
8688 }
8689
8690 /**
8691 * @brief FSM long counter timeout register (r/w). The long counter
8692 * timeout value is an unsigned integer value (16-bit format).
8693 * When the long counter value reached this value,
8694 * the FSM generates an interrupt.[set]
8695 *
8696 * @param ctx read / write interface definitions
8697 * @param buff buffer that contains data to write
8698 * @retval interface status (MANDATORY: return 0 -> no Error)
8699 *
8700 */
lsm6dso32_long_cnt_int_value_set(stmdev_ctx_t * ctx,uint16_t val)8701 int32_t lsm6dso32_long_cnt_int_value_set(stmdev_ctx_t *ctx,
8702 uint16_t val)
8703 {
8704 uint8_t buff[2];
8705 int32_t ret;
8706
8707 buff[1] = (uint8_t)(val / 256U);
8708 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8709 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_FSM_LC_TIMEOUT_L,
8710 &buff[0]);
8711
8712 if (ret == 0)
8713 {
8714 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_FSM_LC_TIMEOUT_H,
8715 &buff[1]);
8716 }
8717
8718 return ret;
8719 }
8720
8721 /**
8722 * @brief FSM long counter timeout register (r/w). The long counter
8723 * timeout value is an unsigned integer value (16-bit format).
8724 * When the long counter value reached this value,
8725 * the FSM generates an interrupt.[get]
8726 *
8727 * @param ctx read / write interface definitions
8728 * @param buff buffer that stores data read
8729 * @retval interface status (MANDATORY: return 0 -> no Error)
8730 *
8731 */
lsm6dso32_long_cnt_int_value_get(stmdev_ctx_t * ctx,uint16_t * val)8732 int32_t lsm6dso32_long_cnt_int_value_get(stmdev_ctx_t *ctx,
8733 uint16_t *val)
8734 {
8735 uint8_t buff[2];
8736 int32_t ret;
8737
8738 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_LC_TIMEOUT_L,
8739 &buff[0]);
8740
8741 if (ret == 0)
8742 {
8743 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_LC_TIMEOUT_H,
8744 &buff[1]);
8745 *val = buff[1];
8746 *val = (*val * 256U) + buff[0];
8747 }
8748
8749 return ret;
8750 }
8751
8752 /**
8753 * @brief FSM number of programs register.[set]
8754 *
8755 * @param ctx read / write interface definitions
8756 * @param buff buffer that contains data to write
8757 * @retval interface status (MANDATORY: return 0 -> no Error)
8758 *
8759 */
lsm6dso32_fsm_number_of_programs_set(stmdev_ctx_t * ctx,uint8_t * buff)8760 int32_t lsm6dso32_fsm_number_of_programs_set(stmdev_ctx_t *ctx,
8761 uint8_t *buff)
8762 {
8763 int32_t ret;
8764
8765 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_FSM_PROGRAMS, buff);
8766
8767 return ret;
8768 }
8769
8770 /**
8771 * @brief FSM number of programs register.[get]
8772 *
8773 * @param ctx read / write interface definitions
8774 * @param buff buffer that stores data read
8775 * @retval interface status (MANDATORY: return 0 -> no Error)
8776 *
8777 */
lsm6dso32_fsm_number_of_programs_get(stmdev_ctx_t * ctx,uint8_t * buff)8778 int32_t lsm6dso32_fsm_number_of_programs_get(stmdev_ctx_t *ctx,
8779 uint8_t *buff)
8780 {
8781 int32_t ret;
8782
8783 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_PROGRAMS, buff);
8784
8785 return ret;
8786 }
8787
8788 /**
8789 * @brief FSM start address register (r/w).
8790 * First available address is 0x033C.[set]
8791 *
8792 * @param ctx read / write interface definitions
8793 * @param buff buffer that contains data to write
8794 * @retval interface status (MANDATORY: return 0 -> no Error)
8795 *
8796 */
lsm6dso32_fsm_start_address_set(stmdev_ctx_t * ctx,uint16_t val)8797 int32_t lsm6dso32_fsm_start_address_set(stmdev_ctx_t *ctx,
8798 uint16_t val)
8799 {
8800 uint8_t buff[2];
8801 int32_t ret;
8802
8803 buff[1] = (uint8_t)(val / 256U);
8804 buff[0] = (uint8_t)(val - (buff[1] * 256U));
8805 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_FSM_START_ADD_L,
8806 &buff[0]);
8807
8808 if (ret == 0)
8809 {
8810 ;
8811 ret = lsm6dso32_ln_pg_write_byte(ctx, LSM6DSO32_FSM_START_ADD_H,
8812 &buff[1]);
8813 }
8814
8815 return ret;
8816 }
8817
8818 /**
8819 * @brief FSM start address register (r/w).
8820 * First available address is 0x033C.[get]
8821 *
8822 * @param ctx read / write interface definitions
8823 * @param buff buffer that stores data read
8824 * @retval interface status (MANDATORY: return 0 -> no Error)
8825 *
8826 */
lsm6dso32_fsm_start_address_get(stmdev_ctx_t * ctx,uint16_t * val)8827 int32_t lsm6dso32_fsm_start_address_get(stmdev_ctx_t *ctx,
8828 uint16_t *val)
8829 {
8830 uint8_t buff[2];
8831 int32_t ret;
8832
8833 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_START_ADD_L,
8834 &buff[0]);
8835
8836 if (ret == 0)
8837 {
8838 ret = lsm6dso32_ln_pg_read_byte(ctx, LSM6DSO32_FSM_START_ADD_H,
8839 &buff[1]);
8840 *val = buff[1];
8841 *val = (*val * 256U) + buff[0];
8842 }
8843
8844 return ret;
8845 }
8846
8847 /**
8848 * @}
8849 *
8850 */
8851
8852 /**
8853 * @defgroup LSM6DSO32_Sensor_hub
8854 * @brief This section groups all the functions that manage the
8855 * sensor hub.
8856 * @{
8857 *
8858 */
8859
8860 /**
8861 * @brief Sensor hub output registers.[get]
8862 *
8863 * @param ctx read / write interface definitions
8864 * @param val union of registers from SENSOR_HUB_1 to SENSOR_HUB_18
8865 * @retval interface status (MANDATORY: return 0 -> no Error)
8866 *
8867 */
lsm6dso32_sh_read_data_raw_get(stmdev_ctx_t * ctx,lsm6dso32_emb_sh_read_t * val)8868 int32_t lsm6dso32_sh_read_data_raw_get(stmdev_ctx_t *ctx,
8869 lsm6dso32_emb_sh_read_t *val)
8870 {
8871 int32_t ret;
8872
8873 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
8874
8875 if (ret == 0)
8876 {
8877 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SENSOR_HUB_1,
8878 (uint8_t *) val, 18U);
8879 }
8880
8881 if (ret == 0)
8882 {
8883 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8884 }
8885
8886 return ret;
8887 }
8888
8889 /**
8890 * @brief Number of external sensors to be read by the sensor hub.[set]
8891 *
8892 * @param ctx read / write interface definitions
8893 * @param val change the values of aux_sens_on in reg MASTER_CONFIG
8894 * @retval interface status (MANDATORY: return 0 -> no Error)
8895 *
8896 */
lsm6dso32_sh_slave_connected_set(stmdev_ctx_t * ctx,lsm6dso32_aux_sens_on_t val)8897 int32_t lsm6dso32_sh_slave_connected_set(stmdev_ctx_t *ctx,
8898 lsm6dso32_aux_sens_on_t val)
8899 {
8900 lsm6dso32_master_config_t reg;
8901 int32_t ret;
8902
8903 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
8904
8905 if (ret == 0)
8906 {
8907 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
8908 (uint8_t *)®, 1);
8909 }
8910
8911 if (ret == 0)
8912 {
8913 reg.aux_sens_on = (uint8_t)val;
8914 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
8915 (uint8_t *)®, 1);
8916 }
8917
8918 if (ret == 0)
8919 {
8920 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8921 }
8922
8923 return ret;
8924 }
8925
8926 /**
8927 * @brief Number of external sensors to be read by the sensor hub.[get]
8928 *
8929 * @param ctx read / write interface definitions
8930 * @param val Get the values of aux_sens_on in reg MASTER_CONFIG
8931 * @retval interface status (MANDATORY: return 0 -> no Error)
8932 *
8933 */
lsm6dso32_sh_slave_connected_get(stmdev_ctx_t * ctx,lsm6dso32_aux_sens_on_t * val)8934 int32_t lsm6dso32_sh_slave_connected_get(stmdev_ctx_t *ctx,
8935 lsm6dso32_aux_sens_on_t *val)
8936 {
8937 lsm6dso32_master_config_t reg;
8938 int32_t ret;
8939
8940 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
8941
8942 if (ret == 0)
8943 {
8944 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
8945 (uint8_t *)®, 1);
8946 }
8947
8948 if (ret == 0)
8949 {
8950 switch (reg.aux_sens_on)
8951 {
8952 case LSM6DSO32_SLV_0:
8953 *val = LSM6DSO32_SLV_0;
8954 break;
8955
8956 case LSM6DSO32_SLV_0_1:
8957 *val = LSM6DSO32_SLV_0_1;
8958 break;
8959
8960 case LSM6DSO32_SLV_0_1_2:
8961 *val = LSM6DSO32_SLV_0_1_2;
8962 break;
8963
8964 case LSM6DSO32_SLV_0_1_2_3:
8965 *val = LSM6DSO32_SLV_0_1_2_3;
8966 break;
8967
8968 default:
8969 *val = LSM6DSO32_SLV_0;
8970 break;
8971 }
8972
8973 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
8974 }
8975
8976 return ret;
8977 }
8978
8979 /**
8980 * @brief Sensor hub I2C master enable.[set]
8981 *
8982 * @param ctx read / write interface definitions
8983 * @param val change the values of master_on in reg MASTER_CONFIG
8984 * @retval interface status (MANDATORY: return 0 -> no Error)
8985 *
8986 */
lsm6dso32_sh_master_set(stmdev_ctx_t * ctx,uint8_t val)8987 int32_t lsm6dso32_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
8988 {
8989 lsm6dso32_master_config_t reg;
8990 int32_t ret;
8991
8992 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
8993
8994 if (ret == 0)
8995 {
8996 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
8997 (uint8_t *)®, 1);
8998 }
8999
9000 if (ret == 0)
9001 {
9002 reg.master_on = val;
9003 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9004 (uint8_t *)®, 1);
9005 }
9006
9007 if (ret == 0)
9008 {
9009 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9010 }
9011
9012 return ret;
9013 }
9014
9015 /**
9016 * @brief Sensor hub I2C master enable.[get]
9017 *
9018 * @param ctx read / write interface definitions
9019 * @param val change the values of master_on in reg MASTER_CONFIG
9020 * @retval interface status (MANDATORY: return 0 -> no Error)
9021 *
9022 */
lsm6dso32_sh_master_get(stmdev_ctx_t * ctx,uint8_t * val)9023 int32_t lsm6dso32_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
9024 {
9025 lsm6dso32_master_config_t reg;
9026 int32_t ret;
9027
9028 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9029
9030 if (ret == 0)
9031 {
9032 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9033 (uint8_t *)®, 1);
9034 }
9035
9036 if (ret == 0)
9037 {
9038 *val = reg.master_on;
9039 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9040 }
9041
9042 return ret;
9043 }
9044
9045 /**
9046 * @brief Master I2C pull-up enable.[set]
9047 *
9048 * @param ctx read / write interface definitions
9049 * @param val change the values of shub_pu_en in reg MASTER_CONFIG
9050 * @retval interface status (MANDATORY: return 0 -> no Error)
9051 *
9052 */
lsm6dso32_sh_pin_mode_set(stmdev_ctx_t * ctx,lsm6dso32_shub_pu_en_t val)9053 int32_t lsm6dso32_sh_pin_mode_set(stmdev_ctx_t *ctx,
9054 lsm6dso32_shub_pu_en_t val)
9055 {
9056 lsm6dso32_master_config_t reg;
9057 int32_t ret;
9058
9059 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9060
9061 if (ret == 0)
9062 {
9063 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9064 (uint8_t *)®, 1);
9065 }
9066
9067 if (ret == 0)
9068 {
9069 reg.shub_pu_en = (uint8_t)val;
9070 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9071 (uint8_t *)®, 1);
9072 }
9073
9074 if (ret == 0)
9075 {
9076 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9077 }
9078
9079 return ret;
9080 }
9081
9082 /**
9083 * @brief Master I2C pull-up enable.[get]
9084 *
9085 * @param ctx read / write interface definitions
9086 * @param val Get the values of shub_pu_en in reg MASTER_CONFIG
9087 * @retval interface status (MANDATORY: return 0 -> no Error)
9088 *
9089 */
lsm6dso32_sh_pin_mode_get(stmdev_ctx_t * ctx,lsm6dso32_shub_pu_en_t * val)9090 int32_t lsm6dso32_sh_pin_mode_get(stmdev_ctx_t *ctx,
9091 lsm6dso32_shub_pu_en_t *val)
9092 {
9093 lsm6dso32_master_config_t reg;
9094 int32_t ret;
9095
9096 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9097
9098 if (ret == 0)
9099 {
9100 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9101 (uint8_t *)®, 1);
9102 }
9103
9104 if (ret == 0)
9105 {
9106 switch (reg.shub_pu_en)
9107 {
9108 case LSM6DSO32_EXT_PULL_UP:
9109 *val = LSM6DSO32_EXT_PULL_UP;
9110 break;
9111
9112 case LSM6DSO32_INTERNAL_PULL_UP:
9113 *val = LSM6DSO32_INTERNAL_PULL_UP;
9114 break;
9115
9116 default:
9117 *val = LSM6DSO32_EXT_PULL_UP;
9118 break;
9119 }
9120
9121 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9122 }
9123
9124 return ret;
9125 }
9126
9127 /**
9128 * @brief I2C interface pass-through.[set]
9129 *
9130 * @param ctx read / write interface definitions
9131 * @param val change the values of pass_through_mode in
9132 * reg MASTER_CONFIG
9133 * @retval interface status (MANDATORY: return 0 -> no Error)
9134 *
9135 */
lsm6dso32_sh_pass_through_set(stmdev_ctx_t * ctx,uint8_t val)9136 int32_t lsm6dso32_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
9137 {
9138 lsm6dso32_master_config_t reg;
9139 int32_t ret;
9140
9141 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9142
9143 if (ret == 0)
9144 {
9145 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9146 (uint8_t *)®, 1);
9147 }
9148
9149 if (ret == 0)
9150 {
9151 reg.pass_through_mode = val;
9152 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9153 (uint8_t *)®, 1);
9154 }
9155
9156 if (ret == 0)
9157 {
9158 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9159 }
9160
9161 return ret;
9162 }
9163
9164 /**
9165 * @brief I2C interface pass-through.[get]
9166 *
9167 * @param ctx read / write interface definitions
9168 * @param val change the values of pass_through_mode in
9169 * reg MASTER_CONFIG
9170 * @retval interface status (MANDATORY: return 0 -> no Error)
9171 *
9172 */
lsm6dso32_sh_pass_through_get(stmdev_ctx_t * ctx,uint8_t * val)9173 int32_t lsm6dso32_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
9174 {
9175 lsm6dso32_master_config_t reg;
9176 int32_t ret;
9177
9178 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9179
9180 if (ret == 0)
9181 {
9182 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9183 (uint8_t *)®, 1);
9184 }
9185
9186 if (ret == 0)
9187 {
9188 *val = reg.pass_through_mode;
9189 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9190 }
9191
9192 return ret;
9193 }
9194
9195 /**
9196 * @brief Sensor hub trigger signal selection.[set]
9197 *
9198 * @param ctx read / write interface definitions
9199 * @param val change the values of start_config in reg MASTER_CONFIG
9200 * @retval interface status (MANDATORY: return 0 -> no Error)
9201 *
9202 */
lsm6dso32_sh_syncro_mode_set(stmdev_ctx_t * ctx,lsm6dso32_start_config_t val)9203 int32_t lsm6dso32_sh_syncro_mode_set(stmdev_ctx_t *ctx,
9204 lsm6dso32_start_config_t val)
9205 {
9206 lsm6dso32_master_config_t reg;
9207 int32_t ret;
9208
9209 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9210
9211 if (ret == 0)
9212 {
9213 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9214 (uint8_t *)®, 1);
9215 }
9216
9217 if (ret == 0)
9218 {
9219 reg.start_config = (uint8_t)val;
9220 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9221 (uint8_t *)®, 1);
9222 }
9223
9224 if (ret == 0)
9225 {
9226 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9227 }
9228
9229 return ret;
9230 }
9231
9232 /**
9233 * @brief Sensor hub trigger signal selection.[get]
9234 *
9235 * @param ctx read / write interface definitions
9236 * @param val Get the values of start_config in reg MASTER_CONFIG
9237 * @retval interface status (MANDATORY: return 0 -> no Error)
9238 *
9239 */
lsm6dso32_sh_syncro_mode_get(stmdev_ctx_t * ctx,lsm6dso32_start_config_t * val)9240 int32_t lsm6dso32_sh_syncro_mode_get(stmdev_ctx_t *ctx,
9241 lsm6dso32_start_config_t *val)
9242 {
9243 lsm6dso32_master_config_t reg;
9244 int32_t ret;
9245
9246 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9247
9248 if (ret == 0)
9249 {
9250 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9251 (uint8_t *)®, 1);
9252 }
9253
9254 if (ret == 0)
9255 {
9256 switch (reg.start_config)
9257 {
9258 case LSM6DSO32_EXT_ON_INT2_PIN:
9259 *val = LSM6DSO32_EXT_ON_INT2_PIN;
9260 break;
9261
9262 case LSM6DSO32_XL_GY_DRDY:
9263 *val = LSM6DSO32_XL_GY_DRDY;
9264 break;
9265
9266 default:
9267 *val = LSM6DSO32_EXT_ON_INT2_PIN;
9268 break;
9269 }
9270
9271 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9272 }
9273
9274 return ret;
9275 }
9276
9277 /**
9278 * @brief Slave 0 write operation is performed only at the first
9279 * sensor hub cycle.[set]
9280 *
9281 * @param ctx read / write interface definitions
9282 * @param val change the values of write_once in reg MASTER_CONFIG
9283 * @retval interface status (MANDATORY: return 0 -> no Error)
9284 *
9285 */
lsm6dso32_sh_write_mode_set(stmdev_ctx_t * ctx,lsm6dso32_write_once_t val)9286 int32_t lsm6dso32_sh_write_mode_set(stmdev_ctx_t *ctx,
9287 lsm6dso32_write_once_t val)
9288 {
9289 lsm6dso32_master_config_t reg;
9290 int32_t ret;
9291
9292 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9293
9294 if (ret == 0)
9295 {
9296 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9297 (uint8_t *)®, 1);
9298 }
9299
9300 if (ret == 0)
9301 {
9302 reg.write_once = (uint8_t)val;
9303 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9304 (uint8_t *)®, 1);
9305 }
9306
9307 if (ret == 0)
9308 {
9309 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9310 }
9311
9312 return ret;
9313 }
9314
9315 /**
9316 * @brief Slave 0 write operation is performed only at the first sensor
9317 * hub cycle.[get]
9318 *
9319 * @param ctx read / write interface definitions
9320 * @param val Get the values of write_once in reg MASTER_CONFIG
9321 * @retval interface status (MANDATORY: return 0 -> no Error)
9322 *
9323 */
lsm6dso32_sh_write_mode_get(stmdev_ctx_t * ctx,lsm6dso32_write_once_t * val)9324 int32_t lsm6dso32_sh_write_mode_get(stmdev_ctx_t *ctx,
9325 lsm6dso32_write_once_t *val)
9326 {
9327 lsm6dso32_master_config_t reg;
9328 int32_t ret;
9329
9330 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9331
9332 if (ret == 0)
9333 {
9334 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9335 (uint8_t *)®, 1);
9336 }
9337
9338 if (ret == 0)
9339 {
9340 switch (reg.write_once)
9341 {
9342 case LSM6DSO32_EACH_SH_CYCLE:
9343 *val = LSM6DSO32_EACH_SH_CYCLE;
9344 break;
9345
9346 case LSM6DSO32_ONLY_FIRST_CYCLE:
9347 *val = LSM6DSO32_ONLY_FIRST_CYCLE;
9348 break;
9349
9350 default:
9351 *val = LSM6DSO32_EACH_SH_CYCLE;
9352 break;
9353 }
9354
9355 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9356 }
9357
9358 return ret;
9359 }
9360
9361 /**
9362 * @brief Reset Master logic and output registers.[set]
9363 *
9364 * @param ctx read / write interface definitions
9365 * @retval interface status (MANDATORY: return 0 -> no Error)
9366 *
9367 */
lsm6dso32_sh_reset_set(stmdev_ctx_t * ctx)9368 int32_t lsm6dso32_sh_reset_set(stmdev_ctx_t *ctx)
9369 {
9370 lsm6dso32_master_config_t reg;
9371 int32_t ret;
9372
9373 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9374
9375 if (ret == 0)
9376 {
9377 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9378 (uint8_t *)®, 1);
9379 }
9380
9381 if (ret == 0)
9382 {
9383 reg.rst_master_regs = PROPERTY_ENABLE;
9384 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9385 (uint8_t *)®, 1);
9386 }
9387
9388 if (ret == 0)
9389 {
9390 reg.rst_master_regs = PROPERTY_DISABLE;
9391 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9392 (uint8_t *)®, 1);
9393 }
9394
9395 if (ret == 0)
9396 {
9397 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9398 }
9399
9400 return ret;
9401 }
9402
9403 /**
9404 * @brief Reset Master logic and output registers.[get]
9405 *
9406 * @param ctx read / write interface definitions
9407 * @param val change the values of rst_master_regs in reg MASTER_CONFIG
9408 * @retval interface status (MANDATORY: return 0 -> no Error)
9409 *
9410 */
lsm6dso32_sh_reset_get(stmdev_ctx_t * ctx,uint8_t * val)9411 int32_t lsm6dso32_sh_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
9412 {
9413 lsm6dso32_master_config_t reg;
9414 int32_t ret;
9415
9416 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9417
9418 if (ret == 0)
9419 {
9420 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_MASTER_CONFIG,
9421 (uint8_t *)®, 1);
9422 }
9423
9424 if (ret == 0)
9425 {
9426 *val = reg.rst_master_regs;
9427 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9428 }
9429
9430 return ret;
9431 }
9432
9433 /**
9434 * @brief Rate at which the master communicates.[set]
9435 *
9436 * @param ctx read / write interface definitions
9437 * @param val change the values of shub_odr in reg slv1_CONFIG
9438 * @retval interface status (MANDATORY: return 0 -> no Error)
9439 *
9440 */
lsm6dso32_sh_data_rate_set(stmdev_ctx_t * ctx,lsm6dso32_shub_odr_t val)9441 int32_t lsm6dso32_sh_data_rate_set(stmdev_ctx_t *ctx,
9442 lsm6dso32_shub_odr_t val)
9443 {
9444 lsm6dso32_slv0_config_t reg;
9445 int32_t ret;
9446
9447 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9448
9449 if (ret == 0)
9450 {
9451 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1);
9452 }
9453
9454 if (ret == 0)
9455 {
9456 reg.shub_odr = (uint8_t)val;
9457 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1);
9458 }
9459
9460 if (ret == 0)
9461 {
9462 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9463 }
9464
9465 return ret;
9466 }
9467
9468 /**
9469 * @brief Rate at which the master communicates.[get]
9470 *
9471 * @param ctx read / write interface definitions
9472 * @param val Get the values of shub_odr in reg slv1_CONFIG
9473 * @retval interface status (MANDATORY: return 0 -> no Error)
9474 *
9475 */
lsm6dso32_sh_data_rate_get(stmdev_ctx_t * ctx,lsm6dso32_shub_odr_t * val)9476 int32_t lsm6dso32_sh_data_rate_get(stmdev_ctx_t *ctx,
9477 lsm6dso32_shub_odr_t *val)
9478 {
9479 lsm6dso32_slv0_config_t reg;
9480 int32_t ret;
9481
9482 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9483
9484 if (ret == 0)
9485 {
9486 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG, (uint8_t *)®, 1);
9487 }
9488
9489 if (ret == 0)
9490 {
9491 switch (reg.shub_odr)
9492 {
9493 case LSM6DSO32_SH_ODR_104Hz:
9494 *val = LSM6DSO32_SH_ODR_104Hz;
9495 break;
9496
9497 case LSM6DSO32_SH_ODR_52Hz:
9498 *val = LSM6DSO32_SH_ODR_52Hz;
9499 break;
9500
9501 case LSM6DSO32_SH_ODR_26Hz:
9502 *val = LSM6DSO32_SH_ODR_26Hz;
9503 break;
9504
9505 case LSM6DSO32_SH_ODR_13Hz:
9506 *val = LSM6DSO32_SH_ODR_13Hz;
9507 break;
9508
9509 default:
9510 *val = LSM6DSO32_SH_ODR_104Hz;
9511 break;
9512 }
9513
9514 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9515 }
9516
9517 return ret;
9518 }
9519
9520 /**
9521 * @brief Configure slave 0 for perform a write.[set]
9522 *
9523 * @param ctx read / write interface definitions
9524 * @param val a structure that contain
9525 * - uint8_t slv1_add; 8 bit i2c device address
9526 * - uint8_t slv1_subadd; 8 bit register device address
9527 * - uint8_t slv1_data; 8 bit data to write
9528 * @retval interface status (MANDATORY: return 0 -> no Error)
9529 *
9530 */
lsm6dso32_sh_cfg_write(stmdev_ctx_t * ctx,lsm6dso32_sh_cfg_write_t * val)9531 int32_t lsm6dso32_sh_cfg_write(stmdev_ctx_t *ctx,
9532 lsm6dso32_sh_cfg_write_t *val)
9533 {
9534 lsm6dso32_slv0_add_t reg;
9535 int32_t ret;
9536
9537 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9538
9539 if (ret == 0)
9540 {
9541 reg.slave0 = val->slv0_add;
9542 reg.rw_0 = 0;
9543 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_ADD, (uint8_t *)®, 1);
9544 }
9545
9546 if (ret == 0)
9547 {
9548 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_SUBADD,
9549 &(val->slv0_subadd), 1);
9550 }
9551
9552 if (ret == 0)
9553 {
9554 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_DATAWRITE_SLV0,
9555 &(val->slv0_data), 1);
9556 }
9557
9558 if (ret == 0)
9559 {
9560 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9561 }
9562
9563 return ret;
9564 }
9565
9566 /**
9567 * @brief Configure slave 0 for perform a read.[set]
9568 *
9569 * @param ctx read / write interface definitions
9570 * @param val Structure that contain
9571 * - uint8_t slv1_add; 8 bit i2c device address
9572 * - uint8_t slv1_subadd; 8 bit register device address
9573 * - uint8_t slv1_len; num of bit to read
9574 * @retval interface status (MANDATORY: return 0 -> no Error)
9575 *
9576 */
lsm6dso32_sh_slv0_cfg_read(stmdev_ctx_t * ctx,lsm6dso32_sh_cfg_read_t * val)9577 int32_t lsm6dso32_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
9578 lsm6dso32_sh_cfg_read_t *val)
9579 {
9580 lsm6dso32_slv0_add_t slv0_add;
9581 lsm6dso32_slv0_config_t slv0_config;
9582 int32_t ret;
9583
9584 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9585
9586 if (ret == 0)
9587 {
9588 slv0_add.slave0 = val->slv_add;
9589 slv0_add.rw_0 = 1;
9590 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_ADD,
9591 (uint8_t *)&slv0_add, 1);
9592 }
9593
9594 if (ret == 0)
9595 {
9596 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_SUBADD,
9597 &(val->slv_subadd), 1);
9598 }
9599
9600 if (ret == 0)
9601 {
9602 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV0_CONFIG,
9603 (uint8_t *)&slv0_config, 1);
9604 }
9605
9606 if (ret == 0)
9607 {
9608 slv0_config.slave0_numop = val->slv_len;
9609 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV0_CONFIG,
9610 (uint8_t *)&slv0_config, 1);
9611 }
9612
9613 if (ret == 0)
9614 {
9615 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9616 }
9617
9618 return ret;
9619 }
9620
9621 /**
9622 * @brief Configure slave 0 for perform a write/read.[set]
9623 *
9624 * @param ctx read / write interface definitions
9625 * @param val Structure that contain
9626 * - uint8_t slv1_add; 8 bit i2c device address
9627 * - uint8_t slv1_subadd; 8 bit register device address
9628 * - uint8_t slv1_len; num of bit to read
9629 * @retval interface status (MANDATORY: return 0 -> no Error)
9630 *
9631 */
lsm6dso32_sh_slv1_cfg_read(stmdev_ctx_t * ctx,lsm6dso32_sh_cfg_read_t * val)9632 int32_t lsm6dso32_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
9633 lsm6dso32_sh_cfg_read_t *val)
9634 {
9635 lsm6dso32_slv1_add_t slv1_add;
9636 lsm6dso32_slv1_config_t slv1_config;
9637 int32_t ret;
9638
9639 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9640
9641 if (ret == 0)
9642 {
9643 slv1_add.slave1_add = val->slv_add;
9644 slv1_add.r_1 = 1;
9645 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV1_ADD,
9646 (uint8_t *)&slv1_add, 1);
9647 }
9648
9649 if (ret == 0)
9650 {
9651 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV1_SUBADD,
9652 &(val->slv_subadd), 1);
9653 }
9654
9655 if (ret == 0)
9656 {
9657 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV1_CONFIG,
9658 (uint8_t *)&slv1_config, 1);
9659 }
9660
9661 if (ret == 0)
9662 {
9663 slv1_config.slave1_numop = val->slv_len;
9664 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV1_CONFIG,
9665 (uint8_t *)&slv1_config, 1);
9666 }
9667
9668 if (ret == 0)
9669 {
9670 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9671 }
9672
9673 return ret;
9674 }
9675
9676 /**
9677 * @brief Configure slave 0 for perform a write/read.[set]
9678 *
9679 * @param ctx read / write interface definitions
9680 * @param val Structure that contain
9681 * - uint8_t slv2_add; 8 bit i2c device address
9682 * - uint8_t slv2_subadd; 8 bit register device address
9683 * - uint8_t slv2_len; num of bit to read
9684 * @retval interface status (MANDATORY: return 0 -> no Error)
9685 *
9686 */
lsm6dso32_sh_slv2_cfg_read(stmdev_ctx_t * ctx,lsm6dso32_sh_cfg_read_t * val)9687 int32_t lsm6dso32_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
9688 lsm6dso32_sh_cfg_read_t *val)
9689 {
9690 lsm6dso32_slv2_add_t slv2_add;
9691 lsm6dso32_slv2_config_t slv2_config;
9692 int32_t ret;
9693
9694 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9695
9696 if (ret == 0)
9697 {
9698 slv2_add.slave2_add = val->slv_add;
9699 slv2_add.r_2 = 1;
9700 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV2_ADD,
9701 (uint8_t *)&slv2_add, 1);
9702 }
9703
9704 if (ret == 0)
9705 {
9706 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV2_SUBADD,
9707 &(val->slv_subadd), 1);
9708 }
9709
9710 if (ret == 0)
9711 {
9712 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV2_CONFIG,
9713 (uint8_t *)&slv2_config, 1);
9714 }
9715
9716 if (ret == 0)
9717 {
9718 slv2_config.slave2_numop = val->slv_len;
9719 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV2_CONFIG,
9720 (uint8_t *)&slv2_config, 1);
9721 }
9722
9723 if (ret == 0)
9724 {
9725 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9726 }
9727
9728 return ret;
9729 }
9730
9731 /**
9732 * @brief Configure slave 0 for perform a write/read.[set]
9733 *
9734 * @param ctx read / write interface definitions
9735 * @param val Structure that contain
9736 * - uint8_t slv3_add; 8 bit i2c device address
9737 * - uint8_t slv3_subadd; 8 bit register device address
9738 * - uint8_t slv3_len; num of bit to read
9739 * @retval interface status (MANDATORY: return 0 -> no Error)
9740 *
9741 */
lsm6dso32_sh_slv3_cfg_read(stmdev_ctx_t * ctx,lsm6dso32_sh_cfg_read_t * val)9742 int32_t lsm6dso32_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
9743 lsm6dso32_sh_cfg_read_t *val)
9744 {
9745 lsm6dso32_slv3_add_t slv3_add;
9746 lsm6dso32_slv3_config_t slv3_config;
9747 int32_t ret;
9748
9749 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9750
9751 if (ret == 0)
9752 {
9753 slv3_add.slave3_add = val->slv_add;
9754 slv3_add.r_3 = 1;
9755 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV3_ADD,
9756 (uint8_t *)&slv3_add, 1);
9757 }
9758
9759 if (ret == 0)
9760 {
9761 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV3_SUBADD,
9762 &(val->slv_subadd), 1);
9763 }
9764
9765 if (ret == 0)
9766 {
9767 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_SLV3_CONFIG,
9768 (uint8_t *)&slv3_config, 1);
9769 }
9770
9771 if (ret == 0)
9772 {
9773 slv3_config.slave3_numop = val->slv_len;
9774 ret = lsm6dso32_write_reg(ctx, LSM6DSO32_SLV3_CONFIG,
9775 (uint8_t *)&slv3_config, 1);
9776 }
9777
9778 if (ret == 0)
9779 {
9780 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9781 }
9782
9783 return ret;
9784 }
9785
9786 /**
9787 * @brief Sensor hub source register.[get]
9788 *
9789 * @param ctx read / write interface definitions
9790 * @param val union of registers from STATUS_MASTER to
9791 * @retval interface status (MANDATORY: return 0 -> no Error)
9792 *
9793 */
lsm6dso32_sh_status_get(stmdev_ctx_t * ctx,lsm6dso32_status_master_t * val)9794 int32_t lsm6dso32_sh_status_get(stmdev_ctx_t *ctx,
9795 lsm6dso32_status_master_t *val)
9796 {
9797 int32_t ret;
9798
9799 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_SENSOR_HUB_BANK);
9800
9801 if (ret == 0)
9802 {
9803 ret = lsm6dso32_read_reg(ctx, LSM6DSO32_STATUS_MASTER,
9804 (uint8_t *) val, 1);
9805 }
9806
9807 if (ret == 0)
9808 {
9809 ret = lsm6dso32_mem_bank_set(ctx, LSM6DSO32_USER_BANK);
9810 }
9811
9812 return ret;
9813 }
9814
9815 /**
9816 * @}
9817 *
9818 */
9819
9820 /**
9821 * @}
9822 *
9823 */
9824
9825 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
9826
