1 /**
2 ******************************************************************************
3 * @file lsm6dsm_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSM driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dsm_reg.h"
21
22 /**
23 * @defgroup LSM6DSM
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dsm enanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LSM6DSM_interfaces_functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6dsm_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dsm_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 ret = ctx->read_reg(ctx->handle, reg, data, len);
56
57 return ret;
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx read / write interface definitions(ptr)
64 * @param reg register to write
65 * @param data pointer to data to write in register reg(ptr)
66 * @param len number of consecutive register to write
67 * @retval interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
lsm6dsm_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak lsm6dsm_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
71 uint8_t *data,
72 uint16_t len)
73 {
74 int32_t ret;
75
76 ret = ctx->write_reg(ctx->handle, reg, data, len);
77
78 return ret;
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup LSM6DSM_Sensitivity
88 * @brief These functions convert raw-data into engineering units.
89 * @{
90 *
91 */
92
lsm6dsm_from_fs2g_to_mg(int16_t lsb)93 float_t lsm6dsm_from_fs2g_to_mg(int16_t lsb)
94 {
95 return ((float_t)lsb * 0.061f);
96 }
97
lsm6dsm_from_fs4g_to_mg(int16_t lsb)98 float_t lsm6dsm_from_fs4g_to_mg(int16_t lsb)
99 {
100 return ((float_t)lsb * 0.122f);
101 }
102
lsm6dsm_from_fs8g_to_mg(int16_t lsb)103 float_t lsm6dsm_from_fs8g_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb * 0.244f);
106 }
107
lsm6dsm_from_fs16g_to_mg(int16_t lsb)108 float_t lsm6dsm_from_fs16g_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb * 0.488f);
111 }
112
lsm6dsm_from_fs125dps_to_mdps(int16_t lsb)113 float_t lsm6dsm_from_fs125dps_to_mdps(int16_t lsb)
114 {
115 return ((float_t)lsb * 4.375f);
116 }
117
lsm6dsm_from_fs250dps_to_mdps(int16_t lsb)118 float_t lsm6dsm_from_fs250dps_to_mdps(int16_t lsb)
119 {
120 return ((float_t)lsb * 8.750f);
121 }
122
lsm6dsm_from_fs500dps_to_mdps(int16_t lsb)123 float_t lsm6dsm_from_fs500dps_to_mdps(int16_t lsb)
124 {
125 return ((float_t)lsb * 17.50f);
126 }
127
lsm6dsm_from_fs1000dps_to_mdps(int16_t lsb)128 float_t lsm6dsm_from_fs1000dps_to_mdps(int16_t lsb)
129 {
130 return ((float_t)lsb * 35.0f);
131 }
132
lsm6dsm_from_fs2000dps_to_mdps(int16_t lsb)133 float_t lsm6dsm_from_fs2000dps_to_mdps(int16_t lsb)
134 {
135 return ((float_t)lsb * 70.0f);
136 }
137
lsm6dsm_from_lsb_to_celsius(int16_t lsb)138 float_t lsm6dsm_from_lsb_to_celsius(int16_t lsb)
139 {
140 return (((float_t)lsb / 256.0f) + 25.0f);
141 }
142
143 /**
144 * @}
145 *
146 */
147
148
149 /**
150 * @defgroup LSM6DSM_data_generation
151 * @brief This section groups all the functions concerning data
152 * generation
153 * @{
154 *
155 */
156
157 /**
158 * @brief Accelerometer full-scale selection.[set]
159 *
160 * @param ctx Read / write interface definitions
161 * @param val Change the values of fs_xl in reg CTRL1_XL
162 * @retval Interface status (MANDATORY: return 0 -> no Error).
163 *
164 */
lsm6dsm_xl_full_scale_set(stmdev_ctx_t * ctx,lsm6dsm_fs_xl_t val)165 int32_t lsm6dsm_xl_full_scale_set(stmdev_ctx_t *ctx,
166 lsm6dsm_fs_xl_t val)
167 {
168 lsm6dsm_ctrl1_xl_t ctrl1_xl;
169 int32_t ret;
170
171 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
172
173 if (ret == 0)
174 {
175 ctrl1_xl.fs_xl = (uint8_t) val;
176 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
177 }
178
179 return ret;
180 }
181
182 /**
183 * @brief Accelerometer full-scale selection.[get]
184 *
185 * @param ctx Read / write interface definitions
186 * @param val Get the values of fs_xl in reg CTRL1_XL
187 * @retval Interface status (MANDATORY: return 0 -> no Error).
188 *
189 */
lsm6dsm_xl_full_scale_get(stmdev_ctx_t * ctx,lsm6dsm_fs_xl_t * val)190 int32_t lsm6dsm_xl_full_scale_get(stmdev_ctx_t *ctx,
191 lsm6dsm_fs_xl_t *val)
192 {
193 lsm6dsm_ctrl1_xl_t ctrl1_xl;
194 int32_t ret;
195
196 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
197
198 switch (ctrl1_xl.fs_xl)
199 {
200 case LSM6DSM_2g:
201 *val = LSM6DSM_2g;
202 break;
203
204 case LSM6DSM_16g:
205 *val = LSM6DSM_16g;
206 break;
207
208 case LSM6DSM_4g:
209 *val = LSM6DSM_4g;
210 break;
211
212 case LSM6DSM_8g:
213 *val = LSM6DSM_8g;
214 break;
215
216 default:
217 *val = LSM6DSM_2g;
218 break;
219 }
220
221 return ret;
222 }
223
224 /**
225 * @brief Accelerometer data rate selection.[set]
226 *
227 * @param ctx Read / write interface definitions
228 * @param val Change the values of odr_xl in reg CTRL1_XL
229 * @retval Interface status (MANDATORY: return 0 -> no Error).
230 *
231 */
lsm6dsm_xl_data_rate_set(stmdev_ctx_t * ctx,lsm6dsm_odr_xl_t val)232 int32_t lsm6dsm_xl_data_rate_set(stmdev_ctx_t *ctx,
233 lsm6dsm_odr_xl_t val)
234 {
235 lsm6dsm_ctrl1_xl_t ctrl1_xl;
236 int32_t ret;
237
238 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
239
240 if (ret == 0)
241 {
242 ctrl1_xl.odr_xl = (uint8_t) val;
243 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
244 }
245
246 return ret;
247 }
248
249 /**
250 * @brief Accelerometer data rate selection.[get]
251 *
252 * @param ctx Read / write interface definitions
253 * @param val Get the values of odr_xl in reg CTRL1_XL
254 * @retval Interface status (MANDATORY: return 0 -> no Error).
255 *
256 */
lsm6dsm_xl_data_rate_get(stmdev_ctx_t * ctx,lsm6dsm_odr_xl_t * val)257 int32_t lsm6dsm_xl_data_rate_get(stmdev_ctx_t *ctx,
258 lsm6dsm_odr_xl_t *val)
259 {
260 lsm6dsm_ctrl1_xl_t ctrl1_xl;
261 int32_t ret;
262
263 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
264
265 switch (ctrl1_xl.odr_xl)
266 {
267 case LSM6DSM_XL_ODR_OFF:
268 *val = LSM6DSM_XL_ODR_OFF;
269 break;
270
271 case LSM6DSM_XL_ODR_12Hz5:
272 *val = LSM6DSM_XL_ODR_12Hz5;
273 break;
274
275 case LSM6DSM_XL_ODR_26Hz:
276 *val = LSM6DSM_XL_ODR_26Hz;
277 break;
278
279 case LSM6DSM_XL_ODR_52Hz:
280 *val = LSM6DSM_XL_ODR_52Hz;
281 break;
282
283 case LSM6DSM_XL_ODR_104Hz:
284 *val = LSM6DSM_XL_ODR_104Hz;
285 break;
286
287 case LSM6DSM_XL_ODR_208Hz:
288 *val = LSM6DSM_XL_ODR_208Hz;
289 break;
290
291 case LSM6DSM_XL_ODR_416Hz:
292 *val = LSM6DSM_XL_ODR_416Hz;
293 break;
294
295 case LSM6DSM_XL_ODR_833Hz:
296 *val = LSM6DSM_XL_ODR_833Hz;
297 break;
298
299 case LSM6DSM_XL_ODR_1k66Hz:
300 *val = LSM6DSM_XL_ODR_1k66Hz;
301 break;
302
303 case LSM6DSM_XL_ODR_3k33Hz:
304 *val = LSM6DSM_XL_ODR_3k33Hz;
305 break;
306
307 case LSM6DSM_XL_ODR_6k66Hz:
308 *val = LSM6DSM_XL_ODR_6k66Hz;
309 break;
310
311 case LSM6DSM_XL_ODR_1Hz6:
312 *val = LSM6DSM_XL_ODR_1Hz6;
313 break;
314
315 default:
316 *val = LSM6DSM_XL_ODR_OFF;
317 break;
318 }
319
320 return ret;
321 }
322
323 /**
324 * @brief Gyroscope chain full-scale selection.[set]
325 *
326 * @param ctx Read / write interface definitions
327 * @param val Change the values of fs_g in reg CTRL2_G
328 * @retval Interface status (MANDATORY: return 0 -> no Error).
329 *
330 */
lsm6dsm_gy_full_scale_set(stmdev_ctx_t * ctx,lsm6dsm_fs_g_t val)331 int32_t lsm6dsm_gy_full_scale_set(stmdev_ctx_t *ctx,
332 lsm6dsm_fs_g_t val)
333 {
334 lsm6dsm_ctrl2_g_t ctrl2_g;
335 int32_t ret;
336
337 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
338
339 if (ret == 0)
340 {
341 ctrl2_g.fs_g = (uint8_t) val;
342 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
343 }
344
345 return ret;
346 }
347
348 /**
349 * @brief Gyroscope chain full-scale selection.[get]
350 *
351 * @param ctx Read / write interface definitions
352 * @param val Get the values of fs_g in reg CTRL2_G
353 * @retval Interface status (MANDATORY: return 0 -> no Error).
354 *
355 */
lsm6dsm_gy_full_scale_get(stmdev_ctx_t * ctx,lsm6dsm_fs_g_t * val)356 int32_t lsm6dsm_gy_full_scale_get(stmdev_ctx_t *ctx,
357 lsm6dsm_fs_g_t *val)
358 {
359 lsm6dsm_ctrl2_g_t ctrl2_g;
360 int32_t ret;
361
362 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
363
364 switch (ctrl2_g.fs_g)
365 {
366 case LSM6DSM_250dps:
367 *val = LSM6DSM_250dps;
368 break;
369
370 case LSM6DSM_125dps:
371 *val = LSM6DSM_125dps;
372 break;
373
374 case LSM6DSM_500dps:
375 *val = LSM6DSM_500dps;
376 break;
377
378 case LSM6DSM_1000dps:
379 *val = LSM6DSM_1000dps;
380 break;
381
382 case LSM6DSM_2000dps:
383 *val = LSM6DSM_2000dps;
384 break;
385
386 default:
387 *val = LSM6DSM_250dps;
388 break;
389 }
390
391 return ret;
392 }
393
394 /**
395 * @brief Gyroscope data rate selection.[set]
396 *
397 * @param ctx Read / write interface definitions
398 * @param val Change the values of odr_g in reg CTRL2_G
399 * @retval Interface status (MANDATORY: return 0 -> no Error).
400 *
401 */
lsm6dsm_gy_data_rate_set(stmdev_ctx_t * ctx,lsm6dsm_odr_g_t val)402 int32_t lsm6dsm_gy_data_rate_set(stmdev_ctx_t *ctx,
403 lsm6dsm_odr_g_t val)
404 {
405 lsm6dsm_ctrl2_g_t ctrl2_g;
406 int32_t ret;
407
408 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
409
410 if (ret == 0)
411 {
412 ctrl2_g.odr_g = (uint8_t) val;
413 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
414 }
415
416 return ret;
417 }
418
419 /**
420 * @brief Gyroscope data rate selection.[get]
421 *
422 * @param ctx Read / write interface definitions
423 * @param val Get the values of odr_g in reg CTRL2_G
424 * @retval Interface status (MANDATORY: return 0 -> no Error).
425 *
426 */
lsm6dsm_gy_data_rate_get(stmdev_ctx_t * ctx,lsm6dsm_odr_g_t * val)427 int32_t lsm6dsm_gy_data_rate_get(stmdev_ctx_t *ctx,
428 lsm6dsm_odr_g_t *val)
429 {
430 lsm6dsm_ctrl2_g_t ctrl2_g;
431 int32_t ret;
432
433 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
434
435 switch (ctrl2_g.odr_g)
436 {
437 case LSM6DSM_GY_ODR_OFF:
438 *val = LSM6DSM_GY_ODR_OFF;
439 break;
440
441 case LSM6DSM_GY_ODR_12Hz5:
442 *val = LSM6DSM_GY_ODR_12Hz5;
443 break;
444
445 case LSM6DSM_GY_ODR_26Hz:
446 *val = LSM6DSM_GY_ODR_26Hz;
447 break;
448
449 case LSM6DSM_GY_ODR_52Hz:
450 *val = LSM6DSM_GY_ODR_52Hz;
451 break;
452
453 case LSM6DSM_GY_ODR_104Hz:
454 *val = LSM6DSM_GY_ODR_104Hz;
455 break;
456
457 case LSM6DSM_GY_ODR_208Hz:
458 *val = LSM6DSM_GY_ODR_208Hz;
459 break;
460
461 case LSM6DSM_GY_ODR_416Hz:
462 *val = LSM6DSM_GY_ODR_416Hz;
463 break;
464
465 case LSM6DSM_GY_ODR_833Hz:
466 *val = LSM6DSM_GY_ODR_833Hz;
467 break;
468
469 case LSM6DSM_GY_ODR_1k66Hz:
470 *val = LSM6DSM_GY_ODR_1k66Hz;
471 break;
472
473 case LSM6DSM_GY_ODR_3k33Hz:
474 *val = LSM6DSM_GY_ODR_3k33Hz;
475 break;
476
477 case LSM6DSM_GY_ODR_6k66Hz:
478 *val = LSM6DSM_GY_ODR_6k66Hz;
479 break;
480
481 default:
482 *val = LSM6DSM_GY_ODR_OFF;
483 break;
484 }
485
486 return ret;
487 }
488
489 /**
490 * @brief Block data update.[set]
491 *
492 * @param ctx Read / write interface definitions
493 * @param val Change the values of bdu in reg CTRL3_C
494 * @retval Interface status (MANDATORY: return 0 -> no Error).
495 *
496 */
lsm6dsm_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)497 int32_t lsm6dsm_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
498 {
499 lsm6dsm_ctrl3_c_t ctrl3_c;
500 int32_t ret;
501
502 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
503
504 if (ret == 0)
505 {
506 ctrl3_c.bdu = val;
507 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
508 }
509
510 return ret;
511 }
512
513 /**
514 * @brief Block data update.[get]
515 *
516 * @param ctx Read / write interface definitions
517 * @param val Change the values of bdu in reg CTRL3_C
518 * @retval Interface status (MANDATORY: return 0 -> no Error).
519 *
520 */
lsm6dsm_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)521 int32_t lsm6dsm_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
522 {
523 lsm6dsm_ctrl3_c_t ctrl3_c;
524 int32_t ret;
525
526 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
527 *val = ctrl3_c.bdu;
528
529 return ret;
530 }
531
532 /**
533 * @brief Weight of XL user offset bits of registers
534 * X_OFS_USR(73h), Y_OFS_USR(74h), Z_OFS_USR(75h).[set]
535 *
536 * @param ctx Read / write interface definitions
537 * @param val Change the values of usr_off_w in reg CTRL6_C
538 * @retval Interface status (MANDATORY: return 0 -> no Error).
539 *
540 */
lsm6dsm_xl_offset_weight_set(stmdev_ctx_t * ctx,lsm6dsm_usr_off_w_t val)541 int32_t lsm6dsm_xl_offset_weight_set(stmdev_ctx_t *ctx,
542 lsm6dsm_usr_off_w_t val)
543 {
544 lsm6dsm_ctrl6_c_t ctrl6_c;
545 int32_t ret;
546
547 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
548
549 if (ret == 0)
550 {
551 ctrl6_c.usr_off_w = (uint8_t) val;
552 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
553 }
554
555 return ret;
556 }
557
558 /**
559 * @brief Weight of XL user offset bits of registers
560 * X_OFS_USR(73h), Y_OFS_USR(74h), Z_OFS_USR(75h).[get]
561 *
562 * @param ctx Read / write interface definitions
563 * @param val Get the values of usr_off_w in reg CTRL6_C
564 * @retval Interface status (MANDATORY: return 0 -> no Error).
565 *
566 */
lsm6dsm_xl_offset_weight_get(stmdev_ctx_t * ctx,lsm6dsm_usr_off_w_t * val)567 int32_t lsm6dsm_xl_offset_weight_get(stmdev_ctx_t *ctx,
568 lsm6dsm_usr_off_w_t *val)
569 {
570 lsm6dsm_ctrl6_c_t ctrl6_c;
571 int32_t ret;
572
573 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
574
575 switch (ctrl6_c.usr_off_w)
576 {
577 case LSM6DSM_LSb_1mg:
578 *val = LSM6DSM_LSb_1mg;
579 break;
580
581 case LSM6DSM_LSb_16mg:
582 *val = LSM6DSM_LSb_16mg;
583 break;
584
585 default:
586 *val = LSM6DSM_LSb_1mg;
587 break;
588 }
589
590 return ret;
591 }
592
593 /**
594 * @brief High-performance operating mode for accelerometer[set]
595 *
596 * @param ctx Read / write interface definitions
597 * @param val Change the values of xl_hm_mode in reg CTRL6_C
598 * @retval Interface status (MANDATORY: return 0 -> no Error).
599 *
600 */
lsm6dsm_xl_power_mode_set(stmdev_ctx_t * ctx,lsm6dsm_xl_hm_mode_t val)601 int32_t lsm6dsm_xl_power_mode_set(stmdev_ctx_t *ctx,
602 lsm6dsm_xl_hm_mode_t val)
603 {
604 lsm6dsm_ctrl6_c_t ctrl6_c;
605 int32_t ret;
606
607 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
608
609 if (ret == 0)
610 {
611 ctrl6_c.xl_hm_mode = (uint8_t) val;
612 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
613 }
614
615 return ret;
616 }
617
618 /**
619 * @brief High-performance operating mode for accelerometer.[get]
620 *
621 * @param ctx Read / write interface definitions
622 * @param val Get the values of xl_hm_mode in reg CTRL6_C
623 * @retval Interface status (MANDATORY: return 0 -> no Error).
624 *
625 */
lsm6dsm_xl_power_mode_get(stmdev_ctx_t * ctx,lsm6dsm_xl_hm_mode_t * val)626 int32_t lsm6dsm_xl_power_mode_get(stmdev_ctx_t *ctx,
627 lsm6dsm_xl_hm_mode_t *val)
628 {
629 lsm6dsm_ctrl6_c_t ctrl6_c;
630 int32_t ret;
631
632 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
633
634 switch (ctrl6_c.xl_hm_mode)
635 {
636 case LSM6DSM_XL_HIGH_PERFORMANCE:
637 *val = LSM6DSM_XL_HIGH_PERFORMANCE;
638 break;
639
640 case LSM6DSM_XL_NORMAL:
641 *val = LSM6DSM_XL_NORMAL;
642 break;
643
644 default:
645 *val = LSM6DSM_XL_HIGH_PERFORMANCE;
646 break;
647 }
648
649 return ret;
650 }
651
652 /**
653 * @brief Source register rounding function on WAKE_UP_SRC (1Bh),
654 * TAP_SRC (1Ch), D6D_SRC (1Dh), STATUS_REG (1Eh) and
655 * FUNC_SRC1 (53h) registers in the primary interface.[set]
656 *
657 * @param ctx Read / write interface definitions
658 * @param val Change the values of rounding_status in reg CTRL7_G
659 * @retval Interface status (MANDATORY: return 0 -> no Error).
660 *
661 */
lsm6dsm_rounding_on_status_set(stmdev_ctx_t * ctx,lsm6dsm_rounding_status_t val)662 int32_t lsm6dsm_rounding_on_status_set(stmdev_ctx_t *ctx,
663 lsm6dsm_rounding_status_t val)
664 {
665 lsm6dsm_ctrl7_g_t ctrl7_g;
666 int32_t ret;
667
668 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
669
670 if (ret == 0)
671 {
672 ctrl7_g.rounding_status = (uint8_t) val;
673 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
674 }
675
676 return ret;
677 }
678
679 /**
680 * @brief Source register rounding function on WAKE_UP_SRC (1Bh),
681 * TAP_SRC (1Ch), D6D_SRC (1Dh), STATUS_REG (1Eh) and
682 * FUNC_SRC1 (53h) registers in the primary interface.[get]
683 *
684 * @param ctx Read / write interface definitions
685 * @param val Get the values of rounding_status in reg CTRL7_G
686 * @retval Interface status (MANDATORY: return 0 -> no Error).
687 *
688 */
lsm6dsm_rounding_on_status_get(stmdev_ctx_t * ctx,lsm6dsm_rounding_status_t * val)689 int32_t lsm6dsm_rounding_on_status_get(stmdev_ctx_t *ctx,
690 lsm6dsm_rounding_status_t *val)
691 {
692 lsm6dsm_ctrl7_g_t ctrl7_g;
693 int32_t ret;
694
695 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
696
697 switch (ctrl7_g.rounding_status)
698 {
699 case LSM6DSM_STAT_RND_DISABLE:
700 *val = LSM6DSM_STAT_RND_DISABLE;
701 break;
702
703 case LSM6DSM_STAT_RND_ENABLE:
704 *val = LSM6DSM_STAT_RND_ENABLE;
705 break;
706
707 default:
708 *val = LSM6DSM_STAT_RND_DISABLE;
709 break;
710 }
711
712 return ret;
713 }
714
715 /**
716 * @brief High-performance operating mode disable for gyroscope.[set]
717 *
718 * @param ctx Read / write interface definitions
719 * @param val Change the values of g_hm_mode in reg CTRL7_G
720 * @retval Interface status (MANDATORY: return 0 -> no Error).
721 *
722 */
lsm6dsm_gy_power_mode_set(stmdev_ctx_t * ctx,lsm6dsm_g_hm_mode_t val)723 int32_t lsm6dsm_gy_power_mode_set(stmdev_ctx_t *ctx,
724 lsm6dsm_g_hm_mode_t val)
725 {
726 lsm6dsm_ctrl7_g_t ctrl7_g;
727 int32_t ret;
728
729 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
730
731 if (ret == 0)
732 {
733 ctrl7_g.g_hm_mode = (uint8_t) val;
734 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
735 }
736
737 return ret;
738 }
739
740 /**
741 * @brief High-performance operating mode disable for gyroscope.[get]
742 *
743 * @param ctx Read / write interface definitions
744 * @param val Get the values of g_hm_mode in reg CTRL7_G
745 * @retval Interface status (MANDATORY: return 0 -> no Error).
746 *
747 */
lsm6dsm_gy_power_mode_get(stmdev_ctx_t * ctx,lsm6dsm_g_hm_mode_t * val)748 int32_t lsm6dsm_gy_power_mode_get(stmdev_ctx_t *ctx,
749 lsm6dsm_g_hm_mode_t *val)
750 {
751 lsm6dsm_ctrl7_g_t ctrl7_g;
752 int32_t ret;
753
754 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
755
756 switch (ctrl7_g.g_hm_mode)
757 {
758 case LSM6DSM_GY_HIGH_PERFORMANCE:
759 *val = LSM6DSM_GY_HIGH_PERFORMANCE;
760 break;
761
762 case LSM6DSM_GY_NORMAL:
763 *val = LSM6DSM_GY_NORMAL;
764 break;
765
766 default:
767 *val = LSM6DSM_GY_HIGH_PERFORMANCE;
768 break;
769 }
770
771 return ret;
772 }
773
774 /**
775 * @brief Read all the interrupt/status flag of the device.[get]
776 *
777 * @param ctx Read / write interface definitions
778 * @param val WAKE_UP_SRC, TAP_SRC, D6D_SRC, STATUS_REG,
779 * FUNC_SRC1, FUNC_SRC2, WRIST_TILT_IA, A_WRIST_TILT_Mask
780 * @retval Interface status (MANDATORY: return 0 -> no Error).
781 *
782 */
lsm6dsm_all_sources_get(stmdev_ctx_t * ctx,lsm6dsm_all_sources_t * val)783 int32_t lsm6dsm_all_sources_get(stmdev_ctx_t *ctx,
784 lsm6dsm_all_sources_t *val)
785 {
786 int32_t ret;
787
788 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_SRC,
789 (uint8_t *) & (val->wake_up_src), 1);
790
791 if (ret == 0)
792 {
793 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_SRC,
794 (uint8_t *) & (val->tap_src), 1);
795 }
796
797 if (ret == 0)
798 {
799 ret = lsm6dsm_read_reg(ctx, LSM6DSM_D6D_SRC,
800 (uint8_t *) & (val->d6d_src), 1);
801 }
802
803 if (ret == 0)
804 {
805 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG,
806 (uint8_t *) & (val->status_reg), 1);
807 }
808
809 if (ret == 0)
810 {
811 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FUNC_SRC1,
812 (uint8_t *) & (val->func_src1), 1);
813 }
814
815 if (ret == 0)
816 {
817 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FUNC_SRC2,
818 (uint8_t *) & (val->func_src2), 1);
819 }
820
821 if (ret == 0)
822 {
823 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WRIST_TILT_IA,
824 (uint8_t *) & (val->wrist_tilt_ia), 1);
825 }
826
827 if (ret == 0)
828 {
829 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
830 }
831
832 if (ret == 0)
833 {
834 ret = lsm6dsm_read_reg(ctx, LSM6DSM_A_WRIST_TILT_MASK,
835 (uint8_t *) & (val->a_wrist_tilt_mask), 1);
836 }
837
838 if (ret == 0)
839 {
840 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
841 }
842
843 return ret;
844 }
845 /**
846 * @brief The STATUS_REG register is read by the primary interface[get]
847 *
848 * @param ctx Read / write interface definitions
849 * @param val Registers STATUS_REG
850 * @retval Interface status (MANDATORY: return 0 -> no Error).
851 *
852 */
lsm6dsm_status_reg_get(stmdev_ctx_t * ctx,lsm6dsm_status_reg_t * val)853 int32_t lsm6dsm_status_reg_get(stmdev_ctx_t *ctx,
854 lsm6dsm_status_reg_t *val)
855 {
856 int32_t ret;
857
858 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG, (uint8_t *) val, 1);
859
860 return ret;
861 }
862
863 /**
864 * @brief Accelerometer new data available.[get]
865 *
866 * @param ctx Read / write interface definitions
867 * @param val Change the values of xlda in reg STATUS_REG
868 * @retval Interface status (MANDATORY: return 0 -> no Error).
869 *
870 */
lsm6dsm_xl_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)871 int32_t lsm6dsm_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
872 uint8_t *val)
873 {
874 lsm6dsm_status_reg_t status_reg;
875 int32_t ret;
876
877 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG,
878 (uint8_t *)&status_reg, 1);
879 *val = status_reg.xlda;
880
881 return ret;
882 }
883
884 /**
885 * @brief Gyroscope new data available.[get]
886 *
887 * @param ctx Read / write interface definitions
888 * @param val Change the values of gda in reg STATUS_REG
889 * @retval Interface status (MANDATORY: return 0 -> no Error).
890 *
891 */
lsm6dsm_gy_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)892 int32_t lsm6dsm_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
893 uint8_t *val)
894 {
895 lsm6dsm_status_reg_t status_reg;
896 int32_t ret;
897
898 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG,
899 (uint8_t *)&status_reg, 1);
900 *val = status_reg.gda;
901
902 return ret;
903 }
904
905 /**
906 * @brief Temperature new data available.[get]
907 *
908 * @param ctx Read / write interface definitions
909 * @param val Change the values of tda in reg STATUS_REG
910 * @retval Interface status (MANDATORY: return 0 -> no Error).
911 *
912 */
lsm6dsm_temp_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)913 int32_t lsm6dsm_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
914 uint8_t *val)
915 {
916 lsm6dsm_status_reg_t status_reg;
917 int32_t ret;
918
919 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG,
920 (uint8_t *)&status_reg, 1);
921 *val = status_reg.tda;
922
923 return ret;
924 }
925
926 /**
927 * @brief Accelerometer axis user offset correction expressed in two’s
928 * complement, weight depends on USR_OFF_W in CTRL6_C.
929 * The value must be in the range [-127 127].[set]
930 *
931 * @param ctx Read / write interface definitions
932 * @param buff Buffer that contains data to write
933 * @retval Interface status (MANDATORY: return 0 -> no Error).
934 *
935 */
lsm6dsm_xl_usr_offset_set(stmdev_ctx_t * ctx,uint8_t * buff)936 int32_t lsm6dsm_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
937 {
938 int32_t ret;
939
940 ret = lsm6dsm_write_reg(ctx, LSM6DSM_X_OFS_USR, buff, 3);
941
942 return ret;
943 }
944
945 /**
946 * @brief Accelerometer axis user offset correction xpressed in two’s
947 * complement, weight depends on USR_OFF_W in CTRL6_C.
948 * The value must be in the range [-127 127].[get]
949 *
950 * @param ctx Read / write interface definitions
951 * @param buff Buffer that stores data read
952 * @retval Interface status (MANDATORY: return 0 -> no Error).
953 *
954 */
lsm6dsm_xl_usr_offset_get(stmdev_ctx_t * ctx,uint8_t * buff)955 int32_t lsm6dsm_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
956 {
957 int32_t ret;
958
959 ret = lsm6dsm_read_reg(ctx, LSM6DSM_X_OFS_USR, buff, 3);
960
961 return ret;
962 }
963
964 /**
965 * @}
966 *
967 */
968
969 /**
970 * @defgroup LSM6DSM_Timestamp
971 * @brief This section groups all the functions that manage the
972 * timestamp generation.
973 * @{
974 *
975 */
976
977 /**
978 * @brief Enable timestamp count. The count is saved in TIMESTAMP0_REG (40h),
979 * TIMESTAMP1_REG (41h) and TIMESTAMP2_REG (42h).[set]
980 *
981 * @param ctx Read / write interface definitions
982 * @param val Change the values of timer_en in reg CTRL10_C
983 * @retval Interface status (MANDATORY: return 0 -> no Error).
984 *
985 */
lsm6dsm_timestamp_set(stmdev_ctx_t * ctx,uint8_t val)986 int32_t lsm6dsm_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
987 {
988 lsm6dsm_ctrl10_c_t ctrl10_c;
989 int32_t ret;
990
991 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
992
993 if (ret == 0)
994 {
995 ctrl10_c.timer_en = val;
996
997 if (val != 0x00U)
998 {
999 ctrl10_c.func_en = val;
1000 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1001 }
1002 }
1003
1004 return ret;
1005 }
1006
1007 /**
1008 * @brief Enable timestamp count. The count is saved in TIMESTAMP0_REG (40h),
1009 * TIMESTAMP1_REG (41h) and TIMESTAMP2_REG (42h).[get]
1010 *
1011 * @param ctx Read / write interface definitions
1012 * @param val Change the values of timer_en in reg CTRL10_C
1013 * @retval Interface status (MANDATORY: return 0 -> no Error).
1014 *
1015 */
lsm6dsm_timestamp_get(stmdev_ctx_t * ctx,uint8_t * val)1016 int32_t lsm6dsm_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
1017 {
1018 lsm6dsm_ctrl10_c_t ctrl10_c;
1019 int32_t ret;
1020
1021 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1022 *val = ctrl10_c.timer_en;
1023
1024 return ret;
1025 }
1026
1027 /**
1028 * @brief Timestamp register resolution setting.
1029 * Configuration of this bit affects
1030 * TIMESTAMP0_REG(40h), TIMESTAMP1_REG(41h),
1031 * TIMESTAMP2_REG(42h), STEP_TIMESTAMP_L(49h),
1032 * STEP_TIMESTAMP_H(4Ah) and
1033 * STEP_COUNT_DELTA(15h) registers.[set]
1034 *
1035 * @param ctx Read / write interface definitions
1036 * @param val Change the values of timer_hr in reg WAKE_UP_DUR
1037 * @retval Interface status (MANDATORY: return 0 -> no Error).
1038 *
1039 */
lsm6dsm_timestamp_res_set(stmdev_ctx_t * ctx,lsm6dsm_timer_hr_t val)1040 int32_t lsm6dsm_timestamp_res_set(stmdev_ctx_t *ctx,
1041 lsm6dsm_timer_hr_t val)
1042 {
1043 lsm6dsm_wake_up_dur_t wake_up_dur;
1044 int32_t ret;
1045
1046 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
1047 (uint8_t *)&wake_up_dur, 1);
1048
1049 if (ret == 0)
1050 {
1051 wake_up_dur.timer_hr = (uint8_t) val;
1052 ret = lsm6dsm_write_reg(ctx, LSM6DSM_WAKE_UP_DUR,
1053 (uint8_t *)&wake_up_dur, 1);
1054 }
1055
1056 return ret;
1057 }
1058
1059 /**
1060 * @brief Timestamp register resolution setting.
1061 * Configuration of this bit affects
1062 * TIMESTAMP0_REG(40h), TIMESTAMP1_REG(41h),
1063 * TIMESTAMP2_REG(42h), STEP_TIMESTAMP_L(49h),
1064 * STEP_TIMESTAMP_H(4Ah) and
1065 * STEP_COUNT_DELTA(15h) registers.[get]
1066 *
1067 * @param ctx Read / write interface definitions
1068 * @param val Get the values of timer_hr in reg WAKE_UP_DUR
1069 * @retval Interface status (MANDATORY: return 0 -> no Error).
1070 *
1071 */
lsm6dsm_timestamp_res_get(stmdev_ctx_t * ctx,lsm6dsm_timer_hr_t * val)1072 int32_t lsm6dsm_timestamp_res_get(stmdev_ctx_t *ctx,
1073 lsm6dsm_timer_hr_t *val)
1074 {
1075 lsm6dsm_wake_up_dur_t wake_up_dur;
1076 int32_t ret;
1077
1078 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
1079 (uint8_t *)&wake_up_dur, 1);
1080
1081 switch (wake_up_dur.timer_hr)
1082 {
1083 case LSM6DSM_LSB_6ms4:
1084 *val = LSM6DSM_LSB_6ms4;
1085 break;
1086
1087 case LSM6DSM_LSB_25us:
1088 *val = LSM6DSM_LSB_25us;
1089 break;
1090
1091 default:
1092 *val = LSM6DSM_LSB_6ms4;
1093 break;
1094 }
1095
1096 return ret;
1097 }
1098
1099 /**
1100 * @}
1101 *
1102 */
1103
1104 /**
1105 * @defgroup LSM6DSM_Dataoutput
1106 * @brief This section groups all the data output functions.
1107 * @{
1108 *
1109 */
1110
1111 /**
1112 * @brief Circular burst-mode (rounding) read from output registers
1113 * through the primary interface.[set]
1114 *
1115 * @param ctx Read / write interface definitions
1116 * @param val Change the values of rounding in reg CTRL5_C
1117 * @retval Interface status (MANDATORY: return 0 -> no Error).
1118 *
1119 */
lsm6dsm_rounding_mode_set(stmdev_ctx_t * ctx,lsm6dsm_rounding_t val)1120 int32_t lsm6dsm_rounding_mode_set(stmdev_ctx_t *ctx,
1121 lsm6dsm_rounding_t val)
1122 {
1123 lsm6dsm_ctrl5_c_t ctrl5_c;
1124 int32_t ret;
1125
1126 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1127
1128 if (ret == 0)
1129 {
1130 ctrl5_c.rounding = (uint8_t) val;
1131 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1132 }
1133
1134 return ret;
1135 }
1136
1137 /**
1138 * @brief Circular burst-mode (rounding) read from output registers
1139 * through the primary interface.[get]
1140 *
1141 * @param ctx Read / write interface definitions
1142 * @param val Get the values of rounding in reg CTRL5_C
1143 * @retval Interface status (MANDATORY: return 0 -> no Error).
1144 *
1145 */
lsm6dsm_rounding_mode_get(stmdev_ctx_t * ctx,lsm6dsm_rounding_t * val)1146 int32_t lsm6dsm_rounding_mode_get(stmdev_ctx_t *ctx,
1147 lsm6dsm_rounding_t *val)
1148 {
1149 lsm6dsm_ctrl5_c_t ctrl5_c;
1150 int32_t ret;
1151
1152 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1153
1154 switch (ctrl5_c.rounding)
1155 {
1156 case LSM6DSM_ROUND_DISABLE:
1157 *val = LSM6DSM_ROUND_DISABLE;
1158 break;
1159
1160 case LSM6DSM_ROUND_XL:
1161 *val = LSM6DSM_ROUND_XL;
1162 break;
1163
1164 case LSM6DSM_ROUND_GY:
1165 *val = LSM6DSM_ROUND_GY;
1166 break;
1167
1168 case LSM6DSM_ROUND_GY_XL:
1169 *val = LSM6DSM_ROUND_GY_XL;
1170 break;
1171
1172 case LSM6DSM_ROUND_SH1_TO_SH6:
1173 *val = LSM6DSM_ROUND_SH1_TO_SH6;
1174 break;
1175
1176 case LSM6DSM_ROUND_XL_SH1_TO_SH6:
1177 *val = LSM6DSM_ROUND_XL_SH1_TO_SH6;
1178 break;
1179
1180 case LSM6DSM_ROUND_GY_XL_SH1_TO_SH12:
1181 *val = LSM6DSM_ROUND_GY_XL_SH1_TO_SH12;
1182 break;
1183
1184 case LSM6DSM_ROUND_GY_XL_SH1_TO_SH6:
1185 *val = LSM6DSM_ROUND_GY_XL_SH1_TO_SH6;
1186 break;
1187
1188 default:
1189 *val = LSM6DSM_ROUND_DISABLE;
1190 break;
1191 }
1192
1193 return ret;
1194 }
1195
1196 /**
1197 * @brief Temperature data output register (r). L and H registers together
1198 * express a 16-bit word in two’s complement.[get]
1199 *
1200 * @param ctx Read / write interface definitions
1201 * @param buff Buffer that stores data read
1202 * @retval Interface status (MANDATORY: return 0 -> no Error).
1203 *
1204 */
lsm6dsm_temperature_raw_get(stmdev_ctx_t * ctx,int16_t * val)1205 int32_t lsm6dsm_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1206 {
1207 uint8_t buff[2];
1208 int32_t ret;
1209
1210 ret = lsm6dsm_read_reg(ctx, LSM6DSM_OUT_TEMP_L, buff, 2);
1211 val[0] = (int16_t)buff[1];
1212 val[0] = (val[0] * 256) + (int16_t)buff[0];
1213
1214 return ret;
1215 }
1216
1217 /**
1218 * @brief Angular rate sensor. The value is expressed as a 16-bit word in
1219 * two’s complement.[get]
1220 *
1221 * @param ctx Read / write interface definitions
1222 * @param buff Buffer that stores data read
1223 * @retval Interface status (MANDATORY: return 0 -> no Error).
1224 *
1225 */
lsm6dsm_angular_rate_raw_get(stmdev_ctx_t * ctx,int16_t * val)1226 int32_t lsm6dsm_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1227 {
1228 uint8_t buff[6];
1229 int32_t ret;
1230
1231 ret = lsm6dsm_read_reg(ctx, LSM6DSM_OUTX_L_G, buff, 6);
1232 val[0] = (int16_t)buff[1];
1233 val[0] = (val[0] * 256) + (int16_t)buff[0];
1234 val[1] = (int16_t)buff[3];
1235 val[1] = (val[1] * 256) + (int16_t)buff[2];
1236 val[2] = (int16_t)buff[5];
1237 val[2] = (val[2] * 256) + (int16_t)buff[4];
1238
1239 return ret;
1240 }
1241
1242 /**
1243 * @brief Linear acceleration output register. The value is expressed
1244 * as a 16-bit word in two’s complement.[get]
1245 *
1246 * @param ctx Read / write interface definitions
1247 * @param buff Buffer that stores data read
1248 * @retval Interface status (MANDATORY: return 0 -> no Error).
1249 *
1250 */
lsm6dsm_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)1251 int32_t lsm6dsm_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1252 {
1253 uint8_t buff[6];
1254 int32_t ret;
1255
1256 ret = lsm6dsm_read_reg(ctx, LSM6DSM_OUTX_L_XL, buff, 6);
1257 val[0] = (int16_t)buff[1];
1258 val[0] = (val[0] * 256) + (int16_t)buff[0];
1259 val[1] = (int16_t)buff[3];
1260 val[1] = (val[1] * 256) + (int16_t)buff[2];
1261 val[2] = (int16_t)buff[5];
1262 val[2] = (val[2] * 256) + (int16_t)buff[4];
1263
1264 return ret;
1265 }
1266
1267 /**
1268 * @brief External magnetometer raw data.[get]
1269 *
1270 * @param ctx Read / write interface definitions
1271 * @param buff Buffer that stores data read
1272 * @retval Interface status (MANDATORY: return 0 -> no Error).
1273 *
1274 */
lsm6dsm_mag_calibrated_raw_get(stmdev_ctx_t * ctx,int16_t * val)1275 int32_t lsm6dsm_mag_calibrated_raw_get(stmdev_ctx_t *ctx,
1276 int16_t *val)
1277 {
1278 uint8_t buff[6];
1279 int32_t ret;
1280
1281 ret = lsm6dsm_read_reg(ctx, LSM6DSM_OUT_MAG_RAW_X_L, buff, 6);
1282 val[0] = (int16_t)buff[1];
1283 val[0] = (val[0] * 256) + (int16_t)buff[0];
1284 val[1] = (int16_t)buff[3];
1285 val[1] = (val[1] * 256) + (int16_t)buff[2];
1286 val[2] = (int16_t)buff[5];
1287 val[2] = (val[2] * 256) + (int16_t)buff[4];
1288
1289 return ret;
1290 }
1291
1292 /**
1293 * @brief Read data in FIFO.[get]
1294 *
1295 * @param ctx Read / write interface definitions
1296 * @param buffer Data buffer to store FIFO data.
1297 * @param len Number of data to read from FIFO.
1298 * @retval Interface status (MANDATORY: return 0 -> no Error).
1299 *
1300 */
lsm6dsm_fifo_raw_data_get(stmdev_ctx_t * ctx,uint8_t * buffer,uint8_t len)1301 int32_t lsm6dsm_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer,
1302 uint8_t len)
1303 {
1304 int32_t ret;
1305
1306 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_DATA_OUT_L, buffer, len);
1307
1308 return ret;
1309 }
1310
1311 /**
1312 * @}
1313 *
1314 */
1315
1316 /**
1317 * @defgroup LSM6DSM_common
1318 * @brief This section groups common useful functions.
1319 * @{
1320 *
1321 */
1322
1323 /**
1324 * @brief Enable access to the embedded functions/sensor hub
1325 * configuration registers[set]
1326 *
1327 * @param ctx Read / write interface definitions
1328 * @param val Change the values of func_cfg_en in reg FUNC_CFG_ACCESS
1329 * @retval Interface status (MANDATORY: return 0 -> no Error).
1330 *
1331 */
lsm6dsm_mem_bank_set(stmdev_ctx_t * ctx,lsm6dsm_func_cfg_en_t val)1332 int32_t lsm6dsm_mem_bank_set(stmdev_ctx_t *ctx,
1333 lsm6dsm_func_cfg_en_t val)
1334 {
1335 lsm6dsm_func_cfg_access_t func_cfg_access;
1336 int32_t ret;
1337
1338 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FUNC_CFG_ACCESS,
1339 (uint8_t *)&func_cfg_access, 1);
1340
1341 if (ret == 0)
1342 {
1343 func_cfg_access.func_cfg_en = (uint8_t) val;
1344 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FUNC_CFG_ACCESS,
1345 (uint8_t *)&func_cfg_access, 1);
1346 }
1347
1348 return ret;
1349 }
1350
1351 /**
1352 * @brief Enable access to the embedded functions/sensor hub configuration
1353 * registers[get]
1354 *
1355 * @param ctx Read / write interface definitions
1356 * @param val Get the values of func_cfg_en in reg FUNC_CFG_ACCESS
1357 * @retval Interface status (MANDATORY: return 0 -> no Error).
1358 *
1359 */
lsm6dsm_mem_bank_get(stmdev_ctx_t * ctx,lsm6dsm_func_cfg_en_t * val)1360 int32_t lsm6dsm_mem_bank_get(stmdev_ctx_t *ctx,
1361 lsm6dsm_func_cfg_en_t *val)
1362 {
1363 lsm6dsm_func_cfg_access_t func_cfg_access;
1364 int32_t ret;
1365
1366 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FUNC_CFG_ACCESS,
1367 (uint8_t *)&func_cfg_access, 1);
1368
1369 switch (func_cfg_access.func_cfg_en)
1370 {
1371 case LSM6DSM_USER_BANK:
1372 *val = LSM6DSM_USER_BANK;
1373 break;
1374
1375 case LSM6DSM_BANK_B:
1376 *val = LSM6DSM_BANK_B;
1377 break;
1378
1379 default:
1380 *val = LSM6DSM_USER_BANK;
1381 break;
1382 }
1383
1384 return ret;
1385 }
1386
1387 /**
1388 * @brief Data-ready pulsed / letched mode[set]
1389 *
1390 * @param ctx Read / write interface definitions
1391 * @param val Change the values of drdy_pulsed in reg DRDY_PULSE_CFG
1392 * @retval Interface status (MANDATORY: return 0 -> no Error).
1393 *
1394 */
lsm6dsm_data_ready_mode_set(stmdev_ctx_t * ctx,lsm6dsm_drdy_pulsed_g_t val)1395 int32_t lsm6dsm_data_ready_mode_set(stmdev_ctx_t *ctx,
1396 lsm6dsm_drdy_pulsed_g_t val)
1397 {
1398 lsm6dsm_drdy_pulse_cfg_t drdy_pulse_cfg;
1399 int32_t ret;
1400
1401 ret = lsm6dsm_read_reg(ctx, LSM6DSM_DRDY_PULSE_CFG,
1402 (uint8_t *)&drdy_pulse_cfg, 1);
1403
1404 if (ret == 0)
1405 {
1406 drdy_pulse_cfg.drdy_pulsed = (uint8_t) val;
1407 ret = lsm6dsm_write_reg(ctx, LSM6DSM_DRDY_PULSE_CFG,
1408 (uint8_t *)&drdy_pulse_cfg, 1);
1409 }
1410
1411 return ret;
1412 }
1413
1414 /**
1415 * @brief Data-ready pulsed / letched mode[get]
1416 *
1417 * @param ctx Read / write interface definitions
1418 * @param val Get the values of drdy_pulsed in reg DRDY_PULSE_CFG
1419 * @retval Interface status (MANDATORY: return 0 -> no Error).
1420 *
1421 */
lsm6dsm_data_ready_mode_get(stmdev_ctx_t * ctx,lsm6dsm_drdy_pulsed_g_t * val)1422 int32_t lsm6dsm_data_ready_mode_get(stmdev_ctx_t *ctx,
1423 lsm6dsm_drdy_pulsed_g_t *val)
1424 {
1425 lsm6dsm_drdy_pulse_cfg_t drdy_pulse_cfg;
1426 int32_t ret;
1427
1428 ret = lsm6dsm_read_reg(ctx, LSM6DSM_DRDY_PULSE_CFG,
1429 (uint8_t *)&drdy_pulse_cfg, 1);
1430
1431 switch (drdy_pulse_cfg.drdy_pulsed)
1432 {
1433 case LSM6DSM_DRDY_LATCHED:
1434 *val = LSM6DSM_DRDY_LATCHED;
1435 break;
1436
1437 case LSM6DSM_DRDY_PULSED:
1438 *val = LSM6DSM_DRDY_PULSED;
1439 break;
1440
1441 default:
1442 *val = LSM6DSM_DRDY_LATCHED;
1443 break;
1444 }
1445
1446 return ret;
1447 }
1448
1449 /**
1450 * @brief DeviceWhoamI.[get]
1451 *
1452 * @param ctx Read / write interface definitions
1453 * @param buff Buffer that stores data read
1454 * @retval Interface status (MANDATORY: return 0 -> no Error).
1455 *
1456 */
lsm6dsm_device_id_get(stmdev_ctx_t * ctx,uint8_t * buff)1457 int32_t lsm6dsm_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
1458 {
1459 int32_t ret;
1460
1461 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WHO_AM_I, buff, 1);
1462
1463 return ret;
1464 }
1465
1466 /**
1467 * @brief Software reset. Restore the default values in user registers[set]
1468 *
1469 * @param ctx Read / write interface definitions
1470 * @param val Change the values of sw_reset in reg CTRL3_C
1471 * @retval Interface status (MANDATORY: return 0 -> no Error).
1472 *
1473 */
lsm6dsm_reset_set(stmdev_ctx_t * ctx,uint8_t val)1474 int32_t lsm6dsm_reset_set(stmdev_ctx_t *ctx, uint8_t val)
1475 {
1476 lsm6dsm_ctrl3_c_t ctrl3_c;
1477 int32_t ret;
1478
1479 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1480
1481 if (ret == 0)
1482 {
1483 ctrl3_c.sw_reset = val;
1484 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1485 }
1486
1487 return ret;
1488 }
1489
1490 /**
1491 * @brief Software reset. Restore the default values in user registers[get]
1492 *
1493 * @param ctx Read / write interface definitions
1494 * @param val Change the values of sw_reset in reg CTRL3_C
1495 * @retval Interface status (MANDATORY: return 0 -> no Error).
1496 *
1497 */
lsm6dsm_reset_get(stmdev_ctx_t * ctx,uint8_t * val)1498 int32_t lsm6dsm_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
1499 {
1500 lsm6dsm_ctrl3_c_t ctrl3_c;
1501 int32_t ret;
1502
1503 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1504 *val = ctrl3_c.sw_reset;
1505
1506 return ret;
1507 }
1508
1509 /**
1510 * @brief Big/Little Endian Data selection.[set]
1511 *
1512 * @param ctx Read / write interface definitions
1513 * @param val Change the values of ble in reg CTRL3_C
1514 * @retval Interface status (MANDATORY: return 0 -> no Error).
1515 *
1516 */
lsm6dsm_data_format_set(stmdev_ctx_t * ctx,lsm6dsm_ble_t val)1517 int32_t lsm6dsm_data_format_set(stmdev_ctx_t *ctx, lsm6dsm_ble_t val)
1518 {
1519 lsm6dsm_ctrl3_c_t ctrl3_c;
1520 int32_t ret;
1521
1522 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1523
1524 if (ret == 0)
1525 {
1526 ctrl3_c.ble = (uint8_t) val;
1527 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1528 }
1529
1530 return ret;
1531 }
1532
1533 /**
1534 * @brief Big/Little Endian Data selection.[get]
1535 *
1536 * @param ctx Read / write interface definitions
1537 * @param val Get the values of ble in reg CTRL3_C
1538 * @retval Interface status (MANDATORY: return 0 -> no Error).
1539 *
1540 */
lsm6dsm_data_format_get(stmdev_ctx_t * ctx,lsm6dsm_ble_t * val)1541 int32_t lsm6dsm_data_format_get(stmdev_ctx_t *ctx, lsm6dsm_ble_t *val)
1542 {
1543 lsm6dsm_ctrl3_c_t ctrl3_c;
1544 int32_t ret;
1545
1546 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1547
1548 switch (ctrl3_c.ble)
1549 {
1550 case LSM6DSM_LSB_AT_LOW_ADD:
1551 *val = LSM6DSM_LSB_AT_LOW_ADD;
1552 break;
1553
1554 case LSM6DSM_MSB_AT_LOW_ADD:
1555 *val = LSM6DSM_MSB_AT_LOW_ADD;
1556 break;
1557
1558 default:
1559 *val = LSM6DSM_LSB_AT_LOW_ADD;
1560 break;
1561 }
1562
1563 return ret;
1564 }
1565
1566 /**
1567 * @brief Register address automatically incremented during a multiple byte
1568 * access with a serial interface.[set]
1569 *
1570 * @param ctx Read / write interface definitions
1571 * @param val Change the values of if_inc in reg CTRL3_C
1572 * @retval Interface status (MANDATORY: return 0 -> no Error).
1573 *
1574 */
lsm6dsm_auto_increment_set(stmdev_ctx_t * ctx,uint8_t val)1575 int32_t lsm6dsm_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
1576 {
1577 lsm6dsm_ctrl3_c_t ctrl3_c;
1578 int32_t ret;
1579
1580 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1581
1582 if (ret == 0)
1583 {
1584 ctrl3_c.if_inc = val;
1585 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1586 }
1587
1588 return ret;
1589 }
1590
1591 /**
1592 * @brief Register address automatically incremented during a multiple byte
1593 * access with a serial interface.[get]
1594 *
1595 * @param ctx Read / write interface definitions
1596 * @param val Change the values of if_inc in reg CTRL3_C
1597 * @retval Interface status (MANDATORY: return 0 -> no Error).
1598 *
1599 */
lsm6dsm_auto_increment_get(stmdev_ctx_t * ctx,uint8_t * val)1600 int32_t lsm6dsm_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
1601 {
1602 lsm6dsm_ctrl3_c_t ctrl3_c;
1603 int32_t ret;
1604
1605 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1606 *val = ctrl3_c.if_inc;
1607
1608 return ret;
1609 }
1610
1611 /**
1612 * @brief Reboot memory content. Reload the calibration parameters.[set]
1613 *
1614 * @param ctx Read / write interface definitions
1615 * @param val Change the values of boot in reg CTRL3_C
1616 * @retval Interface status (MANDATORY: return 0 -> no Error).
1617 *
1618 */
lsm6dsm_boot_set(stmdev_ctx_t * ctx,uint8_t val)1619 int32_t lsm6dsm_boot_set(stmdev_ctx_t *ctx, uint8_t val)
1620 {
1621 lsm6dsm_ctrl3_c_t ctrl3_c;
1622 int32_t ret;
1623
1624 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1625
1626 if (ret == 0)
1627 {
1628 ctrl3_c.boot = val;
1629 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1630 }
1631
1632 return ret;
1633 }
1634
1635 /**
1636 * @brief Reboot memory content. Reload the calibration parameters.[get]
1637 *
1638 * @param ctx Read / write interface definitions
1639 * @param val Change the values of boot in reg CTRL3_C
1640 * @retval Interface status (MANDATORY: return 0 -> no Error).
1641 *
1642 */
lsm6dsm_boot_get(stmdev_ctx_t * ctx,uint8_t * val)1643 int32_t lsm6dsm_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
1644 {
1645 lsm6dsm_ctrl3_c_t ctrl3_c;
1646 int32_t ret;
1647
1648 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1649 *val = ctrl3_c.boot;
1650
1651 return ret;
1652 }
1653
1654 /**
1655 * @brief Linear acceleration sensor self-test enable.[set]
1656 *
1657 * @param ctx Read / write interface definitions
1658 * @param val Change the values of st_xl in reg CTRL5_C
1659 * @retval Interface status (MANDATORY: return 0 -> no Error).
1660 *
1661 */
lsm6dsm_xl_self_test_set(stmdev_ctx_t * ctx,lsm6dsm_st_xl_t val)1662 int32_t lsm6dsm_xl_self_test_set(stmdev_ctx_t *ctx,
1663 lsm6dsm_st_xl_t val)
1664 {
1665 lsm6dsm_ctrl5_c_t ctrl5_c;
1666 int32_t ret;
1667
1668 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1669
1670 if (ret == 0)
1671 {
1672 ctrl5_c.st_xl = (uint8_t) val;
1673 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1674 }
1675
1676 return ret;
1677 }
1678
1679 /**
1680 * @brief Linear acceleration sensor self-test enable.[get]
1681 *
1682 * @param ctx Read / write interface definitions
1683 * @param val Get the values of st_xl in reg CTRL5_C
1684 * @retval Interface status (MANDATORY: return 0 -> no Error).
1685 *
1686 */
lsm6dsm_xl_self_test_get(stmdev_ctx_t * ctx,lsm6dsm_st_xl_t * val)1687 int32_t lsm6dsm_xl_self_test_get(stmdev_ctx_t *ctx,
1688 lsm6dsm_st_xl_t *val)
1689 {
1690 lsm6dsm_ctrl5_c_t ctrl5_c;
1691 int32_t ret;
1692
1693 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1694
1695 switch (ctrl5_c.st_xl)
1696 {
1697 case LSM6DSM_XL_ST_DISABLE:
1698 *val = LSM6DSM_XL_ST_DISABLE;
1699 break;
1700
1701 case LSM6DSM_XL_ST_POSITIVE:
1702 *val = LSM6DSM_XL_ST_POSITIVE;
1703 break;
1704
1705 case LSM6DSM_XL_ST_NEGATIVE:
1706 *val = LSM6DSM_XL_ST_NEGATIVE;
1707 break;
1708
1709 default:
1710 *val = LSM6DSM_XL_ST_DISABLE;
1711 break;
1712 }
1713
1714 return ret;
1715 }
1716
1717 /**
1718 * @brief Angular rate sensor self-test enable.[set]
1719 *
1720 * @param ctx Read / write interface definitions
1721 * @param val Change the values of st_g in reg CTRL5_C
1722 * @retval Interface status (MANDATORY: return 0 -> no Error).
1723 *
1724 */
lsm6dsm_gy_self_test_set(stmdev_ctx_t * ctx,lsm6dsm_st_g_t val)1725 int32_t lsm6dsm_gy_self_test_set(stmdev_ctx_t *ctx,
1726 lsm6dsm_st_g_t val)
1727 {
1728 lsm6dsm_ctrl5_c_t ctrl5_c;
1729 int32_t ret;
1730
1731 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1732
1733 if (ret == 0)
1734 {
1735 ctrl5_c.st_g = (uint8_t) val;
1736 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1737 }
1738
1739 return ret;
1740 }
1741
1742 /**
1743 * @brief Angular rate sensor self-test enable.[get]
1744 *
1745 * @param ctx Read / write interface definitions
1746 * @param val Get the values of st_g in reg CTRL5_C
1747 * @retval Interface status (MANDATORY: return 0 -> no Error).
1748 *
1749 */
lsm6dsm_gy_self_test_get(stmdev_ctx_t * ctx,lsm6dsm_st_g_t * val)1750 int32_t lsm6dsm_gy_self_test_get(stmdev_ctx_t *ctx,
1751 lsm6dsm_st_g_t *val)
1752 {
1753 lsm6dsm_ctrl5_c_t ctrl5_c;
1754 int32_t ret;
1755
1756 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1757
1758 switch (ctrl5_c.st_g)
1759 {
1760 case LSM6DSM_GY_ST_DISABLE:
1761 *val = LSM6DSM_GY_ST_DISABLE;
1762 break;
1763
1764 case LSM6DSM_GY_ST_POSITIVE:
1765 *val = LSM6DSM_GY_ST_POSITIVE;
1766 break;
1767
1768 case LSM6DSM_GY_ST_NEGATIVE:
1769 *val = LSM6DSM_GY_ST_NEGATIVE;
1770 break;
1771
1772 default:
1773 *val = LSM6DSM_GY_ST_DISABLE;
1774 break;
1775 }
1776
1777 return ret;
1778 }
1779
1780 /**
1781 * @}
1782 *
1783 */
1784
1785 /**
1786 * @defgroup LSM6DSM_filters
1787 * @brief This section group all the functions concerning the filters
1788 * configuration that impact both accelerometer and gyro.
1789 * @{
1790 *
1791 */
1792
1793 /**
1794 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
1795 * (XL and Gyro independently masked).[set]
1796 *
1797 * @param ctx Read / write interface definitions
1798 * @param val Change the values of drdy_mask in reg CTRL4_C
1799 * @retval Interface status (MANDATORY: return 0 -> no Error).
1800 *
1801 */
lsm6dsm_filter_settling_mask_set(stmdev_ctx_t * ctx,uint8_t val)1802 int32_t lsm6dsm_filter_settling_mask_set(stmdev_ctx_t *ctx,
1803 uint8_t val)
1804 {
1805 lsm6dsm_ctrl4_c_t ctrl4_c;
1806 int32_t ret;
1807
1808 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1809
1810 if (ret == 0)
1811 {
1812 ctrl4_c.drdy_mask = val;
1813 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1814 }
1815
1816 return ret;
1817 }
1818
1819 /**
1820 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
1821 * (XL and Gyro independently masked).[get]
1822 *
1823 * @param ctx Read / write interface definitions
1824 * @param val Change the values of drdy_mask in reg CTRL4_C
1825 * @retval Interface status (MANDATORY: return 0 -> no Error).
1826 *
1827 */
lsm6dsm_filter_settling_mask_get(stmdev_ctx_t * ctx,uint8_t * val)1828 int32_t lsm6dsm_filter_settling_mask_get(stmdev_ctx_t *ctx,
1829 uint8_t *val)
1830 {
1831 lsm6dsm_ctrl4_c_t ctrl4_c;
1832 int32_t ret;
1833
1834 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1835 *val = ctrl4_c.drdy_mask;
1836
1837 return ret;
1838 }
1839
1840 /**
1841 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
1842 * functions.[set]
1843 *
1844 * @param ctx Read / write interface definitions
1845 * @param val Change the values of slope_fds in reg TAP_CFG
1846 * @retval Interface status (MANDATORY: return 0 -> no Error).
1847 *
1848 */
lsm6dsm_xl_hp_path_internal_set(stmdev_ctx_t * ctx,lsm6dsm_slope_fds_t val)1849 int32_t lsm6dsm_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
1850 lsm6dsm_slope_fds_t val)
1851 {
1852 lsm6dsm_tap_cfg_t tap_cfg;
1853 int32_t ret;
1854
1855 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
1856
1857 if (ret == 0)
1858 {
1859 tap_cfg.slope_fds = (uint8_t) val;
1860 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
1861 }
1862
1863 return ret;
1864 }
1865
1866 /**
1867 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
1868 * functions.[get]
1869 *
1870 * @param ctx Read / write interface definitions
1871 * @param val Get the values of slope_fds in reg TAP_CFG
1872 * @retval Interface status (MANDATORY: return 0 -> no Error).
1873 *
1874 */
lsm6dsm_xl_hp_path_internal_get(stmdev_ctx_t * ctx,lsm6dsm_slope_fds_t * val)1875 int32_t lsm6dsm_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
1876 lsm6dsm_slope_fds_t *val)
1877 {
1878 lsm6dsm_tap_cfg_t tap_cfg;
1879 int32_t ret;
1880
1881 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
1882
1883 switch (tap_cfg.slope_fds)
1884 {
1885 case LSM6DSM_USE_SLOPE:
1886 *val = LSM6DSM_USE_SLOPE;
1887 break;
1888
1889 case LSM6DSM_USE_HPF:
1890 *val = LSM6DSM_USE_HPF;
1891 break;
1892
1893 default:
1894 *val = LSM6DSM_USE_SLOPE;
1895 break;
1896 }
1897
1898 return ret;
1899 }
1900
1901 /**
1902 * @}
1903 *
1904 */
1905
1906 /**
1907 * @defgroup LSM6DSM_accelerometer_filters
1908 * @brief This section group all the functions concerning the filters
1909 * configuration that impact accelerometer in every mode.
1910 * @{
1911 *
1912 */
1913
1914 /**
1915 * @brief Accelerometer analog chain bandwidth selection (only for
1916 * accelerometer ODR ≥ 1.67 kHz).[set]
1917 *
1918 * @param ctx Read / write interface definitions
1919 * @param val Change the values of bw0_xl in reg CTRL1_XL
1920 * @retval Interface status (MANDATORY: return 0 -> no Error).
1921 *
1922 */
lsm6dsm_xl_filter_analog_set(stmdev_ctx_t * ctx,lsm6dsm_bw0_xl_t val)1923 int32_t lsm6dsm_xl_filter_analog_set(stmdev_ctx_t *ctx,
1924 lsm6dsm_bw0_xl_t val)
1925 {
1926 lsm6dsm_ctrl1_xl_t ctrl1_xl;
1927 int32_t ret;
1928
1929 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
1930
1931 if (ret == 0)
1932 {
1933 ctrl1_xl.bw0_xl = (uint8_t) val;
1934 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
1935 }
1936
1937 return ret;
1938 }
1939
1940 /**
1941 * @brief Accelerometer analog chain bandwidth selection (only for
1942 * accelerometer ODR ≥ 1.67 kHz).[get]
1943 *
1944 * @param ctx Read / write interface definitions
1945 * @param val Get the values of bw0_xl in reg CTRL1_XL
1946 * @retval Interface status (MANDATORY: return 0 -> no Error).
1947 *
1948 */
lsm6dsm_xl_filter_analog_get(stmdev_ctx_t * ctx,lsm6dsm_bw0_xl_t * val)1949 int32_t lsm6dsm_xl_filter_analog_get(stmdev_ctx_t *ctx,
1950 lsm6dsm_bw0_xl_t *val)
1951 {
1952 lsm6dsm_ctrl1_xl_t ctrl1_xl;
1953 int32_t ret;
1954
1955 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
1956
1957 switch (ctrl1_xl.bw0_xl)
1958 {
1959 case LSM6DSM_XL_ANA_BW_1k5Hz:
1960 *val = LSM6DSM_XL_ANA_BW_1k5Hz;
1961 break;
1962
1963 case LSM6DSM_XL_ANA_BW_400Hz:
1964 *val = LSM6DSM_XL_ANA_BW_400Hz;
1965 break;
1966
1967 default:
1968 *val = LSM6DSM_XL_ANA_BW_1k5Hz;
1969 break;
1970 }
1971
1972 return ret;
1973 }
1974
1975 /**
1976 * @}
1977 *
1978 */
1979
1980 /**
1981 * @defgroup LSM6DSM_accelerometer_filters_mode:1,2,3
1982 * @brief This section group all the functions concerning the filters
1983 * configuration that impact accelerometer mode 1, 2, 3
1984 * (accelerometer on aux interface disable).
1985 * @{
1986 *
1987 */
1988
1989 /**
1990 * @brief Accelerometer digital LPF (LPF1) bandwidth selection LPF2 is
1991 * not used.[set]
1992 *
1993 * @param ctx Read / write interface definitions
1994 * @param val Change the values of lpf1_bw_sel in reg CTRL1_XL
1995 * @retval Interface status (MANDATORY: return 0 -> no Error).
1996 *
1997 */
lsm6dsm_xl_lp1_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsm_lpf1_bw_sel_t val)1998 int32_t lsm6dsm_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx,
1999 lsm6dsm_lpf1_bw_sel_t val)
2000 {
2001 lsm6dsm_ctrl1_xl_t ctrl1_xl;
2002 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2003 int32_t ret;
2004
2005 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2006
2007 if (ret == 0)
2008 {
2009 ctrl1_xl.lpf1_bw_sel = (uint8_t) val;
2010 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2011
2012 if (ret == 0)
2013 {
2014 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2015
2016 if (ret == 0)
2017 {
2018 ctrl8_xl.lpf2_xl_en = 0;
2019 ctrl8_xl.hp_slope_xl_en = 0;
2020 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2021 }
2022 }
2023 }
2024
2025 return ret;
2026 }
2027
2028 /**
2029 * @brief Accelerometer digital LPF (LPF1) bandwidth selection LPF2
2030 * is not used.[get]
2031 *
2032 * @param ctx Read / write interface definitions
2033 * @param val Get the values of lpf1_bw_sel in reg CTRL1_XL
2034 * @retval Interface status (MANDATORY: return 0 -> no Error).
2035 *
2036 */
lsm6dsm_xl_lp1_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsm_lpf1_bw_sel_t * val)2037 int32_t lsm6dsm_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx,
2038 lsm6dsm_lpf1_bw_sel_t *val)
2039 {
2040 lsm6dsm_ctrl1_xl_t ctrl1_xl;
2041 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2042 int32_t ret;
2043
2044 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2045
2046 if (ret == 0)
2047 {
2048 if ((ctrl8_xl.lpf2_xl_en != 0x00U) ||
2049 (ctrl8_xl.hp_slope_xl_en != 0x00U))
2050 {
2051 *val = LSM6DSM_XL_LP1_NA;
2052 }
2053
2054 else
2055 {
2056 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2057
2058 switch (ctrl1_xl.lpf1_bw_sel)
2059 {
2060 case LSM6DSM_XL_LP1_ODR_DIV_2:
2061 *val = LSM6DSM_XL_LP1_ODR_DIV_2;
2062 break;
2063
2064 case LSM6DSM_XL_LP1_ODR_DIV_4:
2065 *val = LSM6DSM_XL_LP1_ODR_DIV_4;
2066 break;
2067
2068 default:
2069 *val = LSM6DSM_XL_LP1_ODR_DIV_2;
2070 break;
2071 }
2072 }
2073 }
2074
2075 return ret;
2076 }
2077
2078 /**
2079 * @brief LPF2 on outputs[set]
2080 *
2081 * @param ctx Read / write interface definitions
2082 * @param val Change the values of input_composite in reg CTRL8_XL
2083 * @retval Interface status (MANDATORY: return 0 -> no Error).
2084 *
2085 */
lsm6dsm_xl_lp2_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsm_input_composite_t val)2086 int32_t lsm6dsm_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx,
2087 lsm6dsm_input_composite_t val)
2088 {
2089 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2090 int32_t ret;
2091
2092 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2093
2094 if (ret == 0)
2095 {
2096 ctrl8_xl.input_composite = ((uint8_t) val & 0x10U) >> 4;
2097 ctrl8_xl.hpcf_xl = (uint8_t) val & 0x03U;
2098 ctrl8_xl.lpf2_xl_en = 1;
2099 ctrl8_xl.hp_slope_xl_en = 0;
2100 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2101 }
2102
2103 return ret;
2104 }
2105
2106 /**
2107 * @brief LPF2 on outputs[get]
2108 *
2109 * @param ctx Read / write interface definitions
2110 * @param val Get the values of input_composite in reg CTRL8_XL
2111 * @retval Interface status (MANDATORY: return 0 -> no Error).
2112 *
2113 */
lsm6dsm_xl_lp2_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsm_input_composite_t * val)2114 int32_t lsm6dsm_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx,
2115 lsm6dsm_input_composite_t *val)
2116 {
2117 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2118 int32_t ret;
2119
2120 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2121
2122 if (ret == 0)
2123 {
2124 if ((ctrl8_xl.lpf2_xl_en == 0x00U) ||
2125 (ctrl8_xl.hp_slope_xl_en != 0x00U))
2126 {
2127 *val = LSM6DSM_XL_LP_NA;
2128 }
2129
2130 else
2131 {
2132 switch ((ctrl8_xl.input_composite << 4) + ctrl8_xl.hpcf_xl)
2133 {
2134 case LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_50:
2135 *val = LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_50;
2136 break;
2137
2138 case LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_100:
2139 *val = LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_100;
2140 break;
2141
2142 case LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_9:
2143 *val = LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_9;
2144 break;
2145
2146 case LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_400:
2147 *val = LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_400;
2148 break;
2149
2150 case LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_50:
2151 *val = LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_50;
2152 break;
2153
2154 case LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_100:
2155 *val = LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_100;
2156 break;
2157
2158 case LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_9:
2159 *val = LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_9;
2160 break;
2161
2162 case LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_400:
2163 *val = LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_400;
2164 break;
2165
2166 default:
2167 *val = LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_50;
2168 break;
2169 }
2170 }
2171 }
2172
2173 return ret;
2174 }
2175
2176 /**
2177 * @brief Enable HP filter reference mode.[set]
2178 *
2179 * @param ctx Read / write interface definitions
2180 * @param val Change the values of hp_ref_mode in reg CTRL8_XL
2181 * @retval Interface status (MANDATORY: return 0 -> no Error).
2182 *
2183 */
lsm6dsm_xl_reference_mode_set(stmdev_ctx_t * ctx,uint8_t val)2184 int32_t lsm6dsm_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val)
2185 {
2186 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2187 int32_t ret;
2188
2189 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2190
2191 if (ret == 0)
2192 {
2193 ctrl8_xl.hp_ref_mode = val;
2194 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2195 }
2196
2197 return ret;
2198 }
2199
2200 /**
2201 * @brief Enable HP filter reference mode.[get]
2202 *
2203 * @param ctx Read / write interface definitions
2204 * @param val Change the values of hp_ref_mode in reg CTRL8_XL
2205 * @retval Interface status (MANDATORY: return 0 -> no Error).
2206 *
2207 */
lsm6dsm_xl_reference_mode_get(stmdev_ctx_t * ctx,uint8_t * val)2208 int32_t lsm6dsm_xl_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
2209 {
2210 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2211 int32_t ret;
2212
2213 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2214 *val = ctrl8_xl.hp_ref_mode;
2215
2216 return ret;
2217 }
2218
2219 /**
2220 * @brief High pass/Slope on outputs.[set]
2221 *
2222 * @param ctx Read / write interface definitions
2223 * @param val Change the values of hpcf_xl in reg CTRL8_XL
2224 * @retval Interface status (MANDATORY: return 0 -> no Error).
2225 *
2226 */
lsm6dsm_xl_hp_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsm_hpcf_xl_t val)2227 int32_t lsm6dsm_xl_hp_bandwidth_set(stmdev_ctx_t *ctx,
2228 lsm6dsm_hpcf_xl_t val)
2229 {
2230 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2231 int32_t ret;
2232
2233 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2234
2235 if (ret == 0)
2236 {
2237 ctrl8_xl.input_composite = 0;
2238 ctrl8_xl.hpcf_xl = (uint8_t)val & 0x03U;
2239 ctrl8_xl.hp_slope_xl_en = 1;
2240 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2241 }
2242
2243 return ret;
2244 }
2245
2246 /**
2247 * @brief High pass/Slope on outputs.[get]
2248 *
2249 * @param ctx Read / write interface definitions
2250 * @param val Get the values of hpcf_xl in reg CTRL8_XL
2251 * @retval Interface status (MANDATORY: return 0 -> no Error).
2252 *
2253 */
lsm6dsm_xl_hp_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsm_hpcf_xl_t * val)2254 int32_t lsm6dsm_xl_hp_bandwidth_get(stmdev_ctx_t *ctx,
2255 lsm6dsm_hpcf_xl_t *val)
2256 {
2257 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2258 int32_t ret;
2259
2260 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2261
2262 if (ctrl8_xl.hp_slope_xl_en == 0x00U)
2263 {
2264 *val = LSM6DSM_XL_HP_NA;
2265 }
2266
2267 switch (ctrl8_xl.hpcf_xl)
2268 {
2269 case LSM6DSM_XL_HP_ODR_DIV_4:
2270 *val = LSM6DSM_XL_HP_ODR_DIV_4;
2271 break;
2272
2273 case LSM6DSM_XL_HP_ODR_DIV_100:
2274 *val = LSM6DSM_XL_HP_ODR_DIV_100;
2275 break;
2276
2277 case LSM6DSM_XL_HP_ODR_DIV_9:
2278 *val = LSM6DSM_XL_HP_ODR_DIV_9;
2279 break;
2280
2281 case LSM6DSM_XL_HP_ODR_DIV_400:
2282 *val = LSM6DSM_XL_HP_ODR_DIV_400;
2283 break;
2284
2285 default:
2286 *val = LSM6DSM_XL_HP_ODR_DIV_4;
2287 break;
2288 }
2289
2290 return ret;
2291 }
2292
2293 /**
2294 * @}
2295 *
2296 */
2297
2298 /**
2299 * @defgroup LSM6DSM_accelerometer_filters_mode:4
2300 * @brief This section group all the functions concerning the filters
2301 * configuration that impact accelerometer when mode 4
2302 * (accelerometer on aux interface enable).
2303 * @{
2304 *
2305 */
2306
2307 /**
2308 * @brief Accelerometer digital LPF (LPF1) bandwidth selection.
2309 * Only for mode 4.[set]
2310 *
2311 * @param ctx Read / write interface definitions
2312 * @param val change the values of lpf1_bw_sel in reg CTRL1_XL
2313 * @retval Interface status (MANDATORY: return 0 -> no Error).
2314 *
2315 */
lsm6dsm_xl_ui_lp1_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsm_ui_lpf1_bw_sel_t val)2316 int32_t lsm6dsm_xl_ui_lp1_bandwidth_set(stmdev_ctx_t *ctx,
2317 lsm6dsm_ui_lpf1_bw_sel_t val)
2318 {
2319 lsm6dsm_ctrl1_xl_t ctrl1_xl;
2320 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2321 int32_t ret;
2322
2323 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2324
2325 if (ret == 0)
2326 {
2327 ctrl1_xl.lpf1_bw_sel = (uint8_t)val;
2328 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2329 }
2330
2331 if (ret == 0)
2332 {
2333 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2334 }
2335
2336 if (ret == 0)
2337 {
2338 ctrl8_xl.hp_slope_xl_en = 0x00U;
2339 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2340 }
2341
2342 return ret;
2343 }
2344
2345 /**
2346 * @brief Accelerometer digital LPF (LPF1) bandwidth selection.
2347 * Only for mode 4.[get]
2348 *
2349 * @param ctx Read / write interface definitions
2350 * @param val Get the values of lpf1_bw_sel in reg CTRL1_XL
2351 * @retval Interface status (MANDATORY: return 0 -> no Error).
2352 *
2353 */
lsm6dsm_xl_ui_lp1_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsm_ui_lpf1_bw_sel_t * val)2354 int32_t lsm6dsm_xl_ui_lp1_bandwidth_get(stmdev_ctx_t *ctx,
2355 lsm6dsm_ui_lpf1_bw_sel_t *val)
2356 {
2357 lsm6dsm_ctrl1_xl_t ctrl1_xl;
2358 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2359 int32_t ret;
2360
2361 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2362
2363 if (ret == 0)
2364 {
2365 if (ctrl8_xl.hp_slope_xl_en != PROPERTY_DISABLE)
2366 {
2367 *val = LSM6DSM_XL_UI_LP1_NA;
2368 }
2369
2370 else
2371 {
2372 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2373
2374 switch (ctrl1_xl.lpf1_bw_sel)
2375 {
2376 case LSM6DSM_XL_UI_LP1_ODR_DIV_2:
2377 *val = LSM6DSM_XL_UI_LP1_ODR_DIV_2;
2378 break;
2379
2380 case LSM6DSM_XL_UI_LP1_ODR_DIV_4:
2381 *val = LSM6DSM_XL_UI_LP1_ODR_DIV_4;
2382 break;
2383
2384 default:
2385 *val = LSM6DSM_XL_UI_LP1_ODR_DIV_2;
2386 break;
2387 }
2388 }
2389 }
2390
2391 return ret;
2392 }
2393
2394 /**
2395 * @brief Slope filter on outputs.[set]
2396 *
2397 * @param ctx Read / write interface definitions
2398 * @param val change the values of hp_slope_xl_en in reg CTRL8_XL
2399 * @retval Interface status (MANDATORY: return 0 -> no Error).
2400 *
2401 */
lsm6dsm_xl_ui_slope_set(stmdev_ctx_t * ctx,uint8_t val)2402 int32_t lsm6dsm_xl_ui_slope_set(stmdev_ctx_t *ctx, uint8_t val)
2403 {
2404 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2405 int32_t ret;
2406
2407 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2408
2409 if (ret == 0)
2410 {
2411 ctrl8_xl.hp_slope_xl_en = (uint8_t) val;
2412 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2413 }
2414
2415 return ret;
2416 }
2417
2418 /**
2419 * @brief Slope filter on outputs.[get]
2420 *
2421 * @param ctx Read / write interface definitions
2422 * @param val Get the values of hp_slope_xl_en in reg CTRL8_XL
2423 * @retval Interface status (MANDATORY: return 0 -> no Error).
2424 *
2425 */
lsm6dsm_xl_ui_slope_get(stmdev_ctx_t * ctx,uint8_t * val)2426 int32_t lsm6dsm_xl_ui_slope_get(stmdev_ctx_t *ctx, uint8_t *val)
2427 {
2428 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2429 int32_t ret;
2430
2431 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2432 *val = ctrl8_xl.hp_slope_xl_en;
2433
2434 return ret;
2435 }
2436
2437 /**
2438 * @brief accelerometer auxiliary low pass bandwidth.[set]
2439 *
2440 * @param ctx Read / write interface definitions
2441 * @param val change the values of filter_xl_conf_ois in reg CTRL3_OIS
2442 *
2443 * Cut off feq [ODR_UI = 0 / ODR UI ≥ 1600 Hz]
2444 * LIGHT 636 Hz 2.96°
2445 * NORMAL 295 Hz 5.12°
2446 * STRONG 140 Hz 9.39°
2447 * AGGRESSIVE 68.2 Hz 17.6°
2448 *
2449 * Cut off feq [ODR UI ≤ 800 Hz ]
2450 * LIGHT 329 Hz 5.08°
2451 * NORMAL 222 Hz 7.23°
2452 * STRONG 128 Hz 11.5°
2453 * AGGRESSIVE 66.5 Hz 19.7°
2454 *
2455 * @retval Interface status (MANDATORY: return 0 -> no Error).
2456 *
2457 */
lsm6dsm_xl_aux_lp_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsm_filter_xl_conf_ois_t val)2458 int32_t lsm6dsm_xl_aux_lp_bandwidth_set(stmdev_ctx_t *ctx,
2459 lsm6dsm_filter_xl_conf_ois_t val)
2460 {
2461 lsm6dsm_ctrl3_ois_t ctrl3_ois;
2462 int32_t ret;
2463
2464 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
2465
2466 if (ret == 0)
2467 {
2468 ctrl3_ois.filter_xl_conf_ois = (uint8_t) val;
2469 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
2470 }
2471
2472 return ret;
2473 }
2474
2475 /**
2476 * @brief accelerometer auxiliary low pass bandwidth.[get]
2477 *
2478 * @param ctx Read / write interface definitions
2479 * @param val Get the values of filter_xl_conf_ois in reg CTRL3_OIS
2480 *
2481 * Cut off feq [ODR_UI = 0 / ODR UI ≥ 1600 Hz]
2482 * LIGHT 636 Hz 2.96°
2483 * NORMAL 295 Hz 5.12°
2484 * STRONG 140 Hz 9.39°
2485 * AGGRESSIVE 68.2 Hz 17.6°
2486 *
2487 * Cut off feq [ODR UI ≤ 800 Hz ]
2488 * LIGHT 329 Hz 5.08°
2489 * NORMAL 222 Hz 7.23°
2490 * STRONG 128 Hz 11.5°
2491 * AGGRESSIVE 66.5 Hz 19.7°
2492 *
2493 * @retval Interface status (MANDATORY: return 0 -> no Error).
2494 *
2495 */
lsm6dsm_xl_aux_lp_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsm_filter_xl_conf_ois_t * val)2496 int32_t lsm6dsm_xl_aux_lp_bandwidth_get(stmdev_ctx_t *ctx,
2497 lsm6dsm_filter_xl_conf_ois_t *val)
2498 {
2499 lsm6dsm_ctrl3_ois_t ctrl3_ois;
2500 int32_t ret;
2501
2502 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
2503
2504 switch (ctrl3_ois.filter_xl_conf_ois)
2505 {
2506 case LSM6DSM_AUX_LP_LIGHT:
2507 *val = LSM6DSM_AUX_LP_LIGHT;
2508 break;
2509
2510 case LSM6DSM_AUX_LP_NORMAL:
2511 *val = LSM6DSM_AUX_LP_NORMAL;
2512 break;
2513
2514 case LSM6DSM_AUX_LP_STRONG:
2515 *val = LSM6DSM_AUX_LP_STRONG;
2516 break;
2517
2518 case LSM6DSM_AUX_LP_AGGRESSIVE:
2519 *val = LSM6DSM_AUX_LP_AGGRESSIVE;
2520 break;
2521
2522 default:
2523 *val = LSM6DSM_AUX_LP_LIGHT;
2524 break;
2525 }
2526
2527 return ret;
2528 }
2529
2530 /**
2531 * @}
2532 *
2533 */
2534
2535 /**
2536 * @defgroup LSM6DSM_gyroscope_filters_mode:1,2
2537 * @brief This section group all the functions concerning the filters
2538 * configuration that impact gyroscope mode 1, 2
2539 * (gyroscope on aux interface disable).
2540 * @{
2541 *
2542 */
2543
2544 /**
2545 * @brief Gyroscope low pass path bandwidth.[set]
2546 *
2547 * @param ctx Read / write interface definitions
2548 * @param val gyroscope filtering chain configuration.
2549 * @retval Interface status (MANDATORY: return 0 -> no Error).
2550 *
2551 */
lsm6dsm_gy_band_pass_set(stmdev_ctx_t * ctx,lsm6dsm_lpf1_sel_g_t val)2552 int32_t lsm6dsm_gy_band_pass_set(stmdev_ctx_t *ctx,
2553 lsm6dsm_lpf1_sel_g_t val)
2554 {
2555 lsm6dsm_ctrl4_c_t ctrl4_c;
2556 lsm6dsm_ctrl6_c_t ctrl6_c;
2557 lsm6dsm_ctrl7_g_t ctrl7_g;
2558 int32_t ret;
2559
2560 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2561
2562 if (ret == 0)
2563 {
2564 ctrl7_g.hpm_g = ((uint8_t)val & 0x30U) >> 4;
2565 ctrl7_g.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
2566 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2567
2568 if (ret == 0)
2569 {
2570 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2571
2572 if (ret == 0)
2573 {
2574 ctrl6_c.ftype = (uint8_t)val & 0x03U;
2575 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2576
2577 if (ret == 0)
2578 {
2579 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C,
2580 (uint8_t *)&ctrl4_c, 1);
2581
2582 if (ret == 0)
2583 {
2584 ctrl4_c.lpf1_sel_g = ((uint8_t)val & 0x08U) >> 3;
2585 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C,
2586 (uint8_t *)&ctrl4_c, 1);
2587 }
2588 }
2589 }
2590 }
2591 }
2592
2593 return ret;
2594 }
2595
2596 /**
2597 * @brief Gyroscope low pass path bandwidth.[get]
2598 *
2599 * @param ctx Read / write interface definitions
2600 * @param val gyroscope filtering chain
2601 * @retval Interface status (MANDATORY: return 0 -> no Error).
2602 *
2603 */
lsm6dsm_gy_band_pass_get(stmdev_ctx_t * ctx,lsm6dsm_lpf1_sel_g_t * val)2604 int32_t lsm6dsm_gy_band_pass_get(stmdev_ctx_t *ctx,
2605 lsm6dsm_lpf1_sel_g_t *val)
2606 {
2607 lsm6dsm_ctrl4_c_t ctrl4_c;
2608 lsm6dsm_ctrl6_c_t ctrl6_c;
2609 lsm6dsm_ctrl7_g_t ctrl7_g;
2610 int32_t ret;
2611
2612 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2613
2614 if (ret == 0)
2615 {
2616 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2617
2618 if (ret == 0)
2619 {
2620 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2621
2622 switch ((ctrl7_g.hp_en_g << 7) + (ctrl7_g.hpm_g << 4) +
2623 (ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype)
2624 {
2625 case LSM6DSM_HP_16mHz_LP2:
2626 *val = LSM6DSM_HP_16mHz_LP2;
2627 break;
2628
2629 case LSM6DSM_HP_65mHz_LP2:
2630 *val = LSM6DSM_HP_65mHz_LP2;
2631 break;
2632
2633 case LSM6DSM_HP_260mHz_LP2:
2634 *val = LSM6DSM_HP_260mHz_LP2;
2635 break;
2636
2637 case LSM6DSM_HP_1Hz04_LP2:
2638 *val = LSM6DSM_HP_1Hz04_LP2;
2639 break;
2640
2641 case LSM6DSM_HP_DISABLE_LP1_LIGHT:
2642 *val = LSM6DSM_HP_DISABLE_LP1_LIGHT;
2643 break;
2644
2645 case LSM6DSM_HP_DISABLE_LP1_NORMAL:
2646 *val = LSM6DSM_HP_DISABLE_LP1_NORMAL;
2647 break;
2648
2649 case LSM6DSM_HP_DISABLE_LP_STRONG:
2650 *val = LSM6DSM_HP_DISABLE_LP_STRONG;
2651 break;
2652
2653 case LSM6DSM_HP_DISABLE_LP1_AGGRESSIVE:
2654 *val = LSM6DSM_HP_DISABLE_LP1_AGGRESSIVE;
2655 break;
2656
2657 case LSM6DSM_HP_16mHz_LP1_LIGHT:
2658 *val = LSM6DSM_HP_16mHz_LP1_LIGHT;
2659 break;
2660
2661 case LSM6DSM_HP_65mHz_LP1_NORMAL:
2662 *val = LSM6DSM_HP_65mHz_LP1_NORMAL;
2663 break;
2664
2665 case LSM6DSM_HP_260mHz_LP1_STRONG:
2666 *val = LSM6DSM_HP_260mHz_LP1_STRONG;
2667 break;
2668
2669 case LSM6DSM_HP_1Hz04_LP1_AGGRESSIVE:
2670 *val = LSM6DSM_HP_1Hz04_LP1_AGGRESSIVE;
2671 break;
2672
2673 default:
2674 *val = LSM6DSM_HP_65mHz_LP2;
2675 break;
2676 }
2677 }
2678 }
2679
2680 return ret;
2681 }
2682
2683 /**
2684 * @}
2685 *
2686 */
2687
2688 /**
2689 * @defgroup LSM6DSM_gyroscope_filters_mode:3,4
2690 * @brief This section group all the functions concerning the filters
2691 * configuration that impact gyroscope when mode 3, 4
2692 * (gyroscope on aux interface enable).
2693 * @{
2694 *
2695 */
2696
2697 /**
2698 * @brief HPF is available on gyroscope's OIS chain only if HP_EN_G
2699 * in CTRL7_G (16h) is set to '0'.[set]
2700 *
2701 * @param ctx Read / write interface definitions
2702 * @param val gyroscope ui filtering chain configuration in Mode: 3, 4.
2703 * @retval Interface status (MANDATORY: return 0 -> no Error).
2704 *
2705 */
lsm6dsm_gy_ui_high_pass_set(stmdev_ctx_t * ctx,uint8_t val)2706 int32_t lsm6dsm_gy_ui_high_pass_set(stmdev_ctx_t *ctx, uint8_t val)
2707 {
2708 lsm6dsm_ctrl7_g_t ctrl7_g;
2709 int32_t ret;
2710
2711 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2712
2713 if (ret == 0)
2714 {
2715 ctrl7_g.hp_en_g = val;
2716 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2717 }
2718
2719 return ret;
2720 }
2721
2722 /**
2723 * @brief HPF is available on gyroscope's OIS chain only if HP_EN_G
2724 * in CTRL7_G (16h) is set to '0'.[get]
2725 *
2726 * @param ctx Read / write interface definitions
2727 * @param val gyroscope ui filtering chain configuration in Mode: 3, 4.
2728 * @retval Interface status (MANDATORY: return 0 -> no Error).
2729 *
2730 */
lsm6dsm_gy_ui_high_pass_get(stmdev_ctx_t * ctx,uint8_t * val)2731 int32_t lsm6dsm_gy_ui_high_pass_get(stmdev_ctx_t *ctx, uint8_t *val)
2732 {
2733 lsm6dsm_ctrl7_g_t ctrl7_g;
2734 int32_t ret;
2735
2736 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2737 *val = ctrl7_g.hp_en_g;
2738
2739 return ret;
2740 }
2741
2742
2743 /**
2744 * @brief HPF is available on gyroscope's OIS chain only if HP_EN_G
2745 * in CTRL7_G (16h) is set to '0'.[set]
2746 *
2747 * @param ctx Read / write interface definitions
2748 * @param val gyroscope aux (ois) filtering chain configuration in
2749 * Mode: 3, 4.
2750 * @retval Interface status (MANDATORY: return 0 -> no Error).
2751 *
2752 */
lsm6dsm_gy_aux_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsm_hp_en_ois_t val)2753 int32_t lsm6dsm_gy_aux_bandwidth_set(stmdev_ctx_t *ctx,
2754 lsm6dsm_hp_en_ois_t val)
2755 {
2756 lsm6dsm_ctrl7_g_t ctrl7_g;
2757 lsm6dsm_ctrl2_ois_t ctrl2_ois;
2758 int32_t ret;
2759
2760 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2761
2762 if (ret == 0)
2763 {
2764 ctrl7_g.hp_en_g = 0x00U;
2765 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2766 }
2767
2768 if (ret == 0)
2769 {
2770 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1);
2771 }
2772
2773 if (ret == 0)
2774 {
2775 ctrl2_ois.ftype_ois = (uint8_t)val & 0x03U;
2776 ctrl2_ois.hp_en_ois = ((uint8_t)val & 0x80U) >> 7;
2777 ctrl2_ois.hpm_ois = ((uint8_t)val & 0x30U) >> 4;
2778 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1);
2779 }
2780
2781 return ret;
2782 }
2783
2784 /**
2785 * @brief HPF is available on gyroscope's OIS chain only if HP_EN_G
2786 * in CTRL7_G (16h) is set to '0'.[get]
2787 *
2788 * @param ctx Read / write interface definitions
2789 * @param val gyroscope aux (ois) filtering chain configuration in
2790 * Mode: 3, 4.
2791 * @retval Interface status (MANDATORY: return 0 -> no Error).
2792 *
2793 */
lsm6dsm_gy_aux_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsm_hp_en_ois_t * val)2794 int32_t lsm6dsm_gy_aux_bandwidth_get(stmdev_ctx_t *ctx,
2795 lsm6dsm_hp_en_ois_t *val)
2796 {
2797 lsm6dsm_ctrl2_ois_t ctrl2_ois;
2798 int32_t ret;
2799
2800 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1);
2801
2802 switch (((ctrl2_ois.hp_en_ois << 7) + (ctrl2_ois.hpm_ois << 4)
2803 + ctrl2_ois.ftype_ois))
2804 {
2805 case LSM6DSM_HP_DISABLE_LP_173Hz:
2806 *val = LSM6DSM_HP_DISABLE_LP_173Hz;
2807 break;
2808
2809 case LSM6DSM_HP_DISABLE_LP_237Hz:
2810 *val = LSM6DSM_HP_DISABLE_LP_237Hz;
2811 break;
2812
2813 case LSM6DSM_HP_DISABLE_LP_351Hz:
2814 *val = LSM6DSM_HP_DISABLE_LP_351Hz;
2815 break;
2816
2817 case LSM6DSM_HP_DISABLE_LP_937Hz:
2818 *val = LSM6DSM_HP_DISABLE_LP_937Hz;
2819 break;
2820
2821 case LSM6DSM_HP_16mHz_LP_173Hz:
2822 *val = LSM6DSM_HP_16mHz_LP_173Hz;
2823 break;
2824
2825 case LSM6DSM_HP_65mHz_LP_237Hz:
2826 *val = LSM6DSM_HP_65mHz_LP_237Hz;
2827 break;
2828
2829 case LSM6DSM_HP_260mHz_LP_351Hz:
2830 *val = LSM6DSM_HP_260mHz_LP_351Hz;
2831 break;
2832
2833 case LSM6DSM_HP_1Hz04_LP_937Hz:
2834 *val = LSM6DSM_HP_1Hz04_LP_937Hz;
2835 break;
2836
2837 default:
2838 *val = LSM6DSM_HP_DISABLE_LP_173Hz;
2839 break;
2840 }
2841
2842 return ret;
2843 }
2844
2845 /**
2846 * @}
2847 *
2848 */
2849
2850 /**
2851 * @defgroup LSM6DSM_Auxiliary_interface
2852 * @brief This section groups all the functions concerning
2853 * auxiliary interface.
2854 * @{
2855 *
2856 */
2857
2858 /**
2859 * @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get]
2860 *
2861 * @param ctx Read / write interface definitions
2862 * @param val registers STATUS_SPIAUX.
2863 * @retval Interface status (MANDATORY: return 0 -> no Error).
2864 *
2865 */
lsm6dsm_aux_status_reg_get(stmdev_ctx_t * ctx,lsm6dsm_status_spiaux_t * val)2866 int32_t lsm6dsm_aux_status_reg_get(stmdev_ctx_t *ctx,
2867 lsm6dsm_status_spiaux_t *val)
2868 {
2869 int32_t ret;
2870
2871 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_SPIAUX, (uint8_t *) val, 1);
2872
2873 return ret;
2874 }
2875
2876 /**
2877 * @brief AUX accelerometer data available.[get]
2878 *
2879 * @param ctx Read / write interface definitions
2880 * @param val change the values of xlda in reg STATUS_SPIAUX
2881 * @retval Interface status (MANDATORY: return 0 -> no Error).
2882 *
2883 */
lsm6dsm_aux_xl_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)2884 int32_t lsm6dsm_aux_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
2885 uint8_t *val)
2886 {
2887 lsm6dsm_status_spiaux_t status_spiaux;
2888 int32_t ret;
2889
2890 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_SPIAUX,
2891 (uint8_t *)&status_spiaux, 1);
2892 *val = status_spiaux.xlda;
2893
2894 return ret;
2895 }
2896
2897 /**
2898 * @brief AUX gyroscope data available.[get]
2899 *
2900 * @param ctx Read / write interface definitions
2901 * @param val change the values of gda in reg STATUS_SPIAUX
2902 * @retval Interface status (MANDATORY: return 0 -> no Error).
2903 *
2904 */
lsm6dsm_aux_gy_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)2905 int32_t lsm6dsm_aux_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
2906 uint8_t *val)
2907 {
2908 lsm6dsm_status_spiaux_t status_spiaux;
2909 int32_t ret;
2910
2911 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_SPIAUX,
2912 (uint8_t *)&status_spiaux, 1);
2913 *val = status_spiaux.gda;
2914
2915 return ret;
2916 }
2917
2918 /**
2919 * @brief High when the gyroscope output is in the settling phase.[get]
2920 *
2921 * @param ctx Read / write interface definitions
2922 * @param val change the values of gyro_settling in reg STATUS_SPIAUX
2923 * @retval Interface status (MANDATORY: return 0 -> no Error).
2924 *
2925 */
lsm6dsm_aux_gy_flag_settling_get(stmdev_ctx_t * ctx,uint8_t * val)2926 int32_t lsm6dsm_aux_gy_flag_settling_get(stmdev_ctx_t *ctx,
2927 uint8_t *val)
2928 {
2929 lsm6dsm_status_spiaux_t status_spiaux;
2930 int32_t ret;
2931
2932 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_SPIAUX,
2933 (uint8_t *)&status_spiaux, 1);
2934 *val = status_spiaux.gyro_settling;
2935
2936 return ret;
2937 }
2938
2939 /**
2940 * @brief Configure DEN mode on the OIS chain.[set]
2941 *
2942 * @param ctx Read / write interface definitions
2943 * @param val change the values of lvl2_ois in reg INT_OIS
2944 * @retval Interface status (MANDATORY: return 0 -> no Error).
2945 *
2946 */
lsm6dsm_aux_den_mode_set(stmdev_ctx_t * ctx,lsm6dsm_lvl_ois_t val)2947 int32_t lsm6dsm_aux_den_mode_set(stmdev_ctx_t *ctx,
2948 lsm6dsm_lvl_ois_t val)
2949 {
2950 lsm6dsm_int_ois_t int_ois;
2951 lsm6dsm_ctrl1_ois_t ctrl1_ois;
2952 int32_t ret;
2953
2954 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1);
2955
2956 if (ret == 0)
2957 {
2958 int_ois.lvl2_ois = (uint8_t)val & 0x01U;
2959 ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1);
2960 }
2961
2962 if (ret == 0)
2963 {
2964 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
2965 ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
2966 }
2967
2968 if (ret == 0)
2969 {
2970 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
2971 }
2972
2973 return ret;
2974 }
2975
2976 /**
2977 * @brief Configure DEN mode on the OIS chain.[get]
2978 *
2979 * @param ctx Read / write interface definitions
2980 * @param val Get the values of lvl2_ois in reg INT_OIS
2981 * @retval Interface status (MANDATORY: return 0 -> no Error).
2982 *
2983 */
lsm6dsm_aux_den_mode_get(stmdev_ctx_t * ctx,lsm6dsm_lvl_ois_t * val)2984 int32_t lsm6dsm_aux_den_mode_get(stmdev_ctx_t *ctx,
2985 lsm6dsm_lvl_ois_t *val)
2986 {
2987 lsm6dsm_int_ois_t int_ois;
2988 lsm6dsm_ctrl1_ois_t ctrl1_ois;
2989 int32_t ret;
2990
2991 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1);
2992
2993 if (ret == 0)
2994 {
2995 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
2996
2997 switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois)
2998 {
2999 case LSM6DSM_AUX_DEN_DISABLE:
3000 *val = LSM6DSM_AUX_DEN_DISABLE;
3001 break;
3002
3003 case LSM6DSM_AUX_DEN_LEVEL_LATCH:
3004 *val = LSM6DSM_AUX_DEN_LEVEL_LATCH;
3005 break;
3006
3007 case LSM6DSM_AUX_DEN_LEVEL_TRIG:
3008 *val = LSM6DSM_AUX_DEN_LEVEL_TRIG;
3009 break;
3010
3011 default:
3012 *val = LSM6DSM_AUX_DEN_DISABLE;
3013 break;
3014 }
3015 }
3016
3017 return ret;
3018 }
3019
3020 /**
3021 * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting
3022 * has priority over all other INT2 settings.[set]
3023 *
3024 * @param ctx Read / write interface definitions
3025 * @param val change the values of int2_drdy_ois in reg INT_OIS
3026 * @retval Interface status (MANDATORY: return 0 -> no Error).
3027 *
3028 */
lsm6dsm_aux_drdy_on_int2_set(stmdev_ctx_t * ctx,uint8_t val)3029 int32_t lsm6dsm_aux_drdy_on_int2_set(stmdev_ctx_t *ctx, uint8_t val)
3030 {
3031 lsm6dsm_int_ois_t int_ois;
3032 int32_t ret;
3033
3034 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1);
3035
3036 if (ret == 0)
3037 {
3038 int_ois.int2_drdy_ois = val;
3039 ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1);
3040 }
3041
3042 return ret;
3043 }
3044
3045 /**
3046 * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting
3047 * has priority over all other INT2 settings.[get]
3048 *
3049 * @param ctx Read / write interface definitions
3050 * @param val change the values of int2_drdy_ois in reg INT_OIS
3051 * @retval Interface status (MANDATORY: return 0 -> no Error).
3052 *
3053 */
lsm6dsm_aux_drdy_on_int2_get(stmdev_ctx_t * ctx,uint8_t * val)3054 int32_t lsm6dsm_aux_drdy_on_int2_get(stmdev_ctx_t *ctx, uint8_t *val)
3055 {
3056 lsm6dsm_int_ois_t int_ois;
3057 int32_t ret;
3058
3059 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1);
3060 *val = int_ois.int2_drdy_ois;
3061
3062 return ret;
3063 }
3064
3065 /**
3066 * @brief Enables OIS chain data processing for gyro
3067 * in Mode 3 and Mode 4 (mode4_en = 1) and
3068 * accelerometer data in and Mode 4 (mode4_en = 1).
3069 * When the OIS chain is enabled, the OIS outputs are
3070 * available through the SPI2 in registers
3071 * OUTX_L_G(22h) through OUTZ_H_G(27h) and
3072 * STATUS_REG(1Eh) / STATUS_SPIAux, and LPF1 is
3073 * dedicated to this chain.[set]
3074 *
3075 * @param ctx Read / write interface definitions
3076 * @param val change the values of ois_en_spi2 in reg CTRL1_OIS
3077 * @retval Interface status (MANDATORY: return 0 -> no Error).
3078 *
3079 */
lsm6dsm_aux_mode_set(stmdev_ctx_t * ctx,lsm6dsm_ois_en_spi2_t val)3080 int32_t lsm6dsm_aux_mode_set(stmdev_ctx_t *ctx,
3081 lsm6dsm_ois_en_spi2_t val)
3082 {
3083 lsm6dsm_ctrl1_ois_t ctrl1_ois;
3084 int32_t ret;
3085
3086 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3087
3088 if (ret == 0)
3089 {
3090 ctrl1_ois.ois_en_spi2 = (uint8_t)val & 0x01U;
3091 ctrl1_ois.mode4_en = ((uint8_t)val & 0x02U) >> 1;
3092 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3093 }
3094
3095 return ret;
3096 }
3097
3098 /**
3099 * @brief Enables OIS chain data processing for gyro
3100 * in Mode 3 and Mode 4 (mode4_en = 1) and
3101 * accelerometer data in and Mode 4 (mode4_en = 1).
3102 * When the OIS chain is enabled, the OIS outputs
3103 * are available through the SPI2 in registers
3104 * OUTX_L_G(22h) through OUTZ_H_G(27h) and
3105 * STATUS_REG(1Eh) / STATUS_SPIAux, and LPF1 is
3106 * dedicated to this chain.[get]
3107 *
3108 * @param ctx Read / write interface definitions
3109 * @param val Get the values of ois_en_spi2 in reg CTRL1_OIS
3110 * @retval Interface status (MANDATORY: return 0 -> no Error).
3111 *
3112 */
lsm6dsm_aux_mode_get(stmdev_ctx_t * ctx,lsm6dsm_ois_en_spi2_t * val)3113 int32_t lsm6dsm_aux_mode_get(stmdev_ctx_t *ctx,
3114 lsm6dsm_ois_en_spi2_t *val)
3115 {
3116 lsm6dsm_ctrl1_ois_t ctrl1_ois;
3117 int32_t ret;
3118
3119 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3120
3121 switch ((ctrl1_ois.mode4_en << 1) + ctrl1_ois.ois_en_spi2)
3122 {
3123 case LSM6DSM_AUX_DISABLE:
3124 *val = LSM6DSM_AUX_DISABLE;
3125 break;
3126
3127 case LSM6DSM_MODE_3_GY:
3128 *val = LSM6DSM_MODE_3_GY;
3129 break;
3130
3131 case LSM6DSM_MODE_4_GY_XL:
3132 *val = LSM6DSM_MODE_4_GY_XL;
3133 break;
3134
3135 default:
3136 *val = LSM6DSM_AUX_DISABLE;
3137 break;
3138 }
3139
3140 return ret;
3141 }
3142
3143 /**
3144 * @brief Selects gyroscope OIS chain full-scale.[set]
3145 *
3146 * @param ctx Read / write interface definitions
3147 * @param val change the values of fs_g_ois in reg CTRL1_OIS
3148 * @retval Interface status (MANDATORY: return 0 -> no Error).
3149 *
3150 */
lsm6dsm_aux_gy_full_scale_set(stmdev_ctx_t * ctx,lsm6dsm_fs_g_ois_t val)3151 int32_t lsm6dsm_aux_gy_full_scale_set(stmdev_ctx_t *ctx,
3152 lsm6dsm_fs_g_ois_t val)
3153 {
3154 lsm6dsm_ctrl1_ois_t ctrl1_ois;
3155 int32_t ret;
3156
3157 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3158
3159 if (ret == 0)
3160 {
3161 ctrl1_ois.fs_g_ois = (uint8_t)val;
3162 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3163 }
3164
3165 return ret;
3166 }
3167
3168 /**
3169 * @brief Selects gyroscope OIS chain full-scale.[get]
3170 *
3171 * @param ctx Read / write interface definitions
3172 * @param val Get the values of fs_g_ois in reg CTRL1_OIS
3173 * @retval Interface status (MANDATORY: return 0 -> no Error).
3174 *
3175 */
lsm6dsm_aux_gy_full_scale_get(stmdev_ctx_t * ctx,lsm6dsm_fs_g_ois_t * val)3176 int32_t lsm6dsm_aux_gy_full_scale_get(stmdev_ctx_t *ctx,
3177 lsm6dsm_fs_g_ois_t *val)
3178 {
3179 lsm6dsm_ctrl1_ois_t ctrl1_ois;
3180 int32_t ret;
3181
3182 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3183
3184 switch (ctrl1_ois.fs_g_ois)
3185 {
3186 case LSM6DSM_250dps_AUX:
3187 *val = LSM6DSM_250dps_AUX;
3188 break;
3189
3190 case LSM6DSM_125dps_AUX:
3191 *val = LSM6DSM_125dps_AUX;
3192 break;
3193
3194 case LSM6DSM_500dps_AUX:
3195 *val = LSM6DSM_500dps_AUX;
3196 break;
3197
3198 case LSM6DSM_1000dps_AUX:
3199 *val = LSM6DSM_1000dps_AUX;
3200 break;
3201
3202 case LSM6DSM_2000dps_AUX:
3203 *val = LSM6DSM_2000dps_AUX;
3204 break;
3205
3206 default:
3207 *val = LSM6DSM_250dps_AUX;
3208 break;
3209 }
3210
3211 return ret;
3212 }
3213
3214 /**
3215 * @brief SPI2 3- or 4-wire interface.[set]
3216 *
3217 * @param ctx Read / write interface definitions
3218 * @param val change the values of sim_ois in reg CTRL1_OIS
3219 * @retval Interface status (MANDATORY: return 0 -> no Error).
3220 *
3221 */
lsm6dsm_aux_spi_mode_set(stmdev_ctx_t * ctx,lsm6dsm_sim_ois_t val)3222 int32_t lsm6dsm_aux_spi_mode_set(stmdev_ctx_t *ctx,
3223 lsm6dsm_sim_ois_t val)
3224 {
3225 lsm6dsm_ctrl1_ois_t ctrl1_ois;
3226 int32_t ret;
3227
3228 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3229
3230 if (ret == 0)
3231 {
3232 ctrl1_ois.sim_ois = (uint8_t)val;
3233 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3234 }
3235
3236 return ret;
3237 }
3238
3239 /**
3240 * @brief SPI2 3- or 4-wire interface.[get]
3241 *
3242 * @param ctx Read / write interface definitions
3243 * @param val Get the values of sim_ois in reg CTRL1_OIS
3244 * @retval Interface status (MANDATORY: return 0 -> no Error).
3245 *
3246 */
lsm6dsm_aux_spi_mode_get(stmdev_ctx_t * ctx,lsm6dsm_sim_ois_t * val)3247 int32_t lsm6dsm_aux_spi_mode_get(stmdev_ctx_t *ctx,
3248 lsm6dsm_sim_ois_t *val)
3249 {
3250 lsm6dsm_ctrl1_ois_t ctrl1_ois;
3251 int32_t ret;
3252
3253 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3254
3255 switch (ctrl1_ois.sim_ois)
3256 {
3257 case LSM6DSM_AUX_SPI_4_WIRE:
3258 *val = LSM6DSM_AUX_SPI_4_WIRE;
3259 break;
3260
3261 case LSM6DSM_AUX_SPI_3_WIRE:
3262 *val = LSM6DSM_AUX_SPI_3_WIRE;
3263 break;
3264
3265 default:
3266 *val = LSM6DSM_AUX_SPI_4_WIRE;
3267 break;
3268 }
3269
3270 return ret;
3271 }
3272
3273 /**
3274 * @brief Big/Little Endian Data selection on aux interface.[set]
3275 *
3276 * @param ctx Read / write interface definitions
3277 * @param val change the values of ble_ois in reg CTRL1_OIS
3278 * @retval Interface status (MANDATORY: return 0 -> no Error).
3279 *
3280 */
lsm6dsm_aux_data_format_set(stmdev_ctx_t * ctx,lsm6dsm_ble_ois_t val)3281 int32_t lsm6dsm_aux_data_format_set(stmdev_ctx_t *ctx,
3282 lsm6dsm_ble_ois_t val)
3283 {
3284 lsm6dsm_ctrl1_ois_t ctrl1_ois;
3285 int32_t ret;
3286
3287 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3288
3289 if (ret == 0)
3290 {
3291 ctrl1_ois.ble_ois = (uint8_t)val;
3292 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3293 }
3294
3295 return ret;
3296 }
3297
3298 /**
3299 * @brief Big/Little Endian Data selection on aux interface.[get]
3300 *
3301 * @param ctx Read / write interface definitions
3302 * @param val Get the values of ble_ois in reg CTRL1_OIS
3303 * @retval Interface status (MANDATORY: return 0 -> no Error).
3304 *
3305 */
lsm6dsm_aux_data_format_get(stmdev_ctx_t * ctx,lsm6dsm_ble_ois_t * val)3306 int32_t lsm6dsm_aux_data_format_get(stmdev_ctx_t *ctx,
3307 lsm6dsm_ble_ois_t *val)
3308 {
3309 lsm6dsm_ctrl1_ois_t ctrl1_ois;
3310 int32_t ret;
3311
3312 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3313
3314 switch (ctrl1_ois.ble_ois)
3315 {
3316 case LSM6DSM_AUX_LSB_AT_LOW_ADD:
3317 *val = LSM6DSM_AUX_LSB_AT_LOW_ADD;
3318 break;
3319
3320 case LSM6DSM_AUX_MSB_AT_LOW_ADD:
3321 *val = LSM6DSM_AUX_MSB_AT_LOW_ADD;
3322 break;
3323
3324 default:
3325 *val = LSM6DSM_AUX_LSB_AT_LOW_ADD;
3326 break;
3327 }
3328
3329 return ret;
3330 }
3331
3332 /**
3333 * @brief Enable / Disables OIS chain clamp.
3334 * Enable: All OIS chain outputs = 8000h
3335 * during self-test; Disable: OIS chain
3336 * self-test outputs dependent from the aux
3337 * gyro full scale selected.[set]
3338 *
3339 * @param ctx Read / write interface definitions
3340 * @param val change the values of st_ois_clampdis in reg CTRL3_OIS
3341 * @retval Interface status (MANDATORY: return 0 -> no Error).
3342 *
3343 */
lsm6dsm_aux_gy_clamp_set(stmdev_ctx_t * ctx,lsm6dsm_st_ois_clampdis_t val)3344 int32_t lsm6dsm_aux_gy_clamp_set(stmdev_ctx_t *ctx,
3345 lsm6dsm_st_ois_clampdis_t val)
3346 {
3347 lsm6dsm_ctrl3_ois_t ctrl3_ois;
3348 int32_t ret;
3349
3350 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3351
3352 if (ret == 0)
3353 {
3354 ctrl3_ois.st_ois_clampdis = (uint8_t)val;
3355 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3356 }
3357
3358 return ret;
3359 }
3360
3361 /**
3362 * @brief Enable / Disables OIS chain clamp.
3363 * Enable: All OIS chain outputs = 8000h
3364 * during self-test; Disable: OIS chain self-test
3365 * outputs dependent from the aux gyro full
3366 * scale selected.[get]
3367 *
3368 * @param ctx Read / write interface definitions
3369 * @param val Get the values of st_ois_clampdis in reg CTRL3_OIS
3370 * @retval Interface status (MANDATORY: return 0 -> no Error).
3371 *
3372 */
lsm6dsm_aux_gy_clamp_get(stmdev_ctx_t * ctx,lsm6dsm_st_ois_clampdis_t * val)3373 int32_t lsm6dsm_aux_gy_clamp_get(stmdev_ctx_t *ctx,
3374 lsm6dsm_st_ois_clampdis_t *val)
3375 {
3376 lsm6dsm_ctrl3_ois_t ctrl3_ois;
3377 int32_t ret;
3378
3379 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3380
3381 switch (ctrl3_ois.st_ois_clampdis)
3382 {
3383 case LSM6DSM_ENABLE_CLAMP:
3384 *val = LSM6DSM_ENABLE_CLAMP;
3385 break;
3386
3387 case LSM6DSM_DISABLE_CLAMP:
3388 *val = LSM6DSM_DISABLE_CLAMP;
3389 break;
3390
3391 default:
3392 *val = LSM6DSM_ENABLE_CLAMP;
3393 break;
3394 }
3395
3396 return ret;
3397 }
3398
3399 /**
3400 * @brief Selects gyroscope OIS chain self-test.[set]
3401 *
3402 * @param ctx Read / write interface definitions
3403 * @param val change the values of st_ois in reg CTRL3_OIS
3404 * @retval Interface status (MANDATORY: return 0 -> no Error).
3405 *
3406 */
lsm6dsm_aux_gy_self_test_set(stmdev_ctx_t * ctx,lsm6dsm_st_ois_t val)3407 int32_t lsm6dsm_aux_gy_self_test_set(stmdev_ctx_t *ctx,
3408 lsm6dsm_st_ois_t val)
3409 {
3410 lsm6dsm_ctrl3_ois_t ctrl3_ois;
3411 int32_t ret;
3412
3413 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3414
3415 if (ret == 0)
3416 {
3417 ctrl3_ois.st_ois = (uint8_t)val;
3418 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3419 }
3420
3421 return ret;
3422 }
3423
3424 /**
3425 * @brief Selects gyroscope OIS chain self-test.[get]
3426 *
3427 * @param ctx Read / write interface definitions
3428 * @param val Get the values of st_ois in reg CTRL3_OIS
3429 * @retval Interface status (MANDATORY: return 0 -> no Error).
3430 *
3431 */
lsm6dsm_aux_gy_self_test_get(stmdev_ctx_t * ctx,lsm6dsm_st_ois_t * val)3432 int32_t lsm6dsm_aux_gy_self_test_get(stmdev_ctx_t *ctx,
3433 lsm6dsm_st_ois_t *val)
3434 {
3435 lsm6dsm_ctrl3_ois_t ctrl3_ois;
3436 int32_t ret;
3437
3438 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3439
3440 switch (ctrl3_ois.st_ois)
3441 {
3442 case LSM6DSM_AUX_GY_DISABLE:
3443 *val = LSM6DSM_AUX_GY_DISABLE;
3444 break;
3445
3446 case LSM6DSM_AUX_GY_POS:
3447 *val = LSM6DSM_AUX_GY_POS;
3448 break;
3449
3450 case LSM6DSM_AUX_GY_NEG:
3451 *val = LSM6DSM_AUX_GY_NEG;
3452 break;
3453
3454 default:
3455 *val = LSM6DSM_AUX_GY_DISABLE;
3456 break;
3457 }
3458
3459 return ret;
3460 }
3461
3462 /**
3463 * @brief Selects accelerometer OIS channel full-scale.[set]
3464 *
3465 * @param ctx Read / write interface definitions
3466 * @param val change the values of fs_xl_ois in reg CTRL3_OIS
3467 * @retval Interface status (MANDATORY: return 0 -> no Error).
3468 *
3469 */
lsm6dsm_aux_xl_full_scale_set(stmdev_ctx_t * ctx,lsm6dsm_fs_xl_ois_t val)3470 int32_t lsm6dsm_aux_xl_full_scale_set(stmdev_ctx_t *ctx,
3471 lsm6dsm_fs_xl_ois_t val)
3472 {
3473 lsm6dsm_ctrl3_ois_t ctrl3_ois;
3474 int32_t ret;
3475
3476 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3477
3478 if (ret == 0)
3479 {
3480 ctrl3_ois.fs_xl_ois = (uint8_t)val;
3481 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3482 }
3483
3484 return ret;
3485 }
3486
3487 /**
3488 * @brief Selects accelerometer OIS channel full-scale.[get]
3489 *
3490 * @param ctx Read / write interface definitions
3491 * @param val Get the values of fs_xl_ois in reg CTRL3_OIS
3492 * @retval Interface status (MANDATORY: return 0 -> no Error).
3493 *
3494 */
lsm6dsm_aux_xl_full_scale_get(stmdev_ctx_t * ctx,lsm6dsm_fs_xl_ois_t * val)3495 int32_t lsm6dsm_aux_xl_full_scale_get(stmdev_ctx_t *ctx,
3496 lsm6dsm_fs_xl_ois_t *val)
3497 {
3498 lsm6dsm_ctrl3_ois_t ctrl3_ois;
3499 int32_t ret;
3500
3501 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3502
3503 switch (ctrl3_ois.fs_xl_ois)
3504 {
3505 case LSM6DSM_AUX_2g:
3506 *val = LSM6DSM_AUX_2g;
3507 break;
3508
3509 case LSM6DSM_AUX_16g:
3510 *val = LSM6DSM_AUX_16g;
3511 break;
3512
3513 case LSM6DSM_AUX_4g:
3514 *val = LSM6DSM_AUX_4g;
3515 break;
3516
3517 case LSM6DSM_AUX_8g:
3518 *val = LSM6DSM_AUX_8g;
3519 break;
3520
3521 default:
3522 *val = LSM6DSM_AUX_2g;
3523 break;
3524 }
3525
3526 return ret;
3527 }
3528
3529 /**
3530 * @brief Indicates polarity of DEN signal on OIS chain.[set]
3531 *
3532 * @param ctx Read / write interface definitions
3533 * @param val change the values of den_lh_ois in reg CTRL3_OIS
3534 * @retval Interface status (MANDATORY: return 0 -> no Error).
3535 *
3536 */
lsm6dsm_aux_den_polarity_set(stmdev_ctx_t * ctx,lsm6dsm_den_lh_ois_t val)3537 int32_t lsm6dsm_aux_den_polarity_set(stmdev_ctx_t *ctx,
3538 lsm6dsm_den_lh_ois_t val)
3539 {
3540 lsm6dsm_ctrl3_ois_t ctrl3_ois;
3541 int32_t ret;
3542
3543 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3544
3545 if (ret == 0)
3546 {
3547 ctrl3_ois.den_lh_ois = (uint8_t)val;
3548 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3549 }
3550
3551 return ret;
3552 }
3553
3554 /**
3555 * @brief Indicates polarity of DEN signal on OIS chain.[get]
3556 *
3557 * @param ctx Read / write interface definitions
3558 * @param val Get the values of den_lh_ois in reg CTRL3_OIS
3559 * @retval Interface status (MANDATORY: return 0 -> no Error).
3560 *
3561 */
lsm6dsm_aux_den_polarity_get(stmdev_ctx_t * ctx,lsm6dsm_den_lh_ois_t * val)3562 int32_t lsm6dsm_aux_den_polarity_get(stmdev_ctx_t *ctx,
3563 lsm6dsm_den_lh_ois_t *val)
3564 {
3565 lsm6dsm_ctrl3_ois_t ctrl3_ois;
3566 int32_t ret;
3567
3568 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3569
3570 switch (ctrl3_ois.den_lh_ois)
3571 {
3572 case LSM6DSM_AUX_DEN_ACTIVE_LOW:
3573 *val = LSM6DSM_AUX_DEN_ACTIVE_LOW;
3574 break;
3575
3576 case LSM6DSM_AUX_DEN_ACTIVE_HIGH:
3577 *val = LSM6DSM_AUX_DEN_ACTIVE_HIGH;
3578 break;
3579
3580 default:
3581 *val = LSM6DSM_AUX_DEN_ACTIVE_LOW;
3582 break;
3583 }
3584
3585 return ret;
3586 }
3587
3588 /**
3589 * @}
3590 *
3591 */
3592
3593 /**
3594 * @defgroup LSM6DSM main serial_interface
3595 * @brief This section groups all the functions concerning serial
3596 * interface management
3597 * @{
3598 *
3599 */
3600
3601 /**
3602 * @brief SPI Serial Interface Mode selection.[set]
3603 *
3604 * @param ctx Read / write interface definitions
3605 * @param val Change the values of sim in reg CTRL3_C
3606 * @retval Interface status (MANDATORY: return 0 -> no Error).
3607 *
3608 */
lsm6dsm_spi_mode_set(stmdev_ctx_t * ctx,lsm6dsm_sim_t val)3609 int32_t lsm6dsm_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsm_sim_t val)
3610 {
3611 lsm6dsm_ctrl3_c_t ctrl3_c;
3612 int32_t ret;
3613
3614 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3615
3616 if (ret == 0)
3617 {
3618 ctrl3_c.sim = (uint8_t)val;
3619 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3620 }
3621
3622 return ret;
3623 }
3624
3625 /**
3626 * @brief SPI Serial Interface Mode selection.[get]
3627 *
3628 * @param ctx Read / write interface definitions
3629 * @param val Get the values of sim in reg CTRL3_C
3630 * @retval Interface status (MANDATORY: return 0 -> no Error).
3631 *
3632 */
lsm6dsm_spi_mode_get(stmdev_ctx_t * ctx,lsm6dsm_sim_t * val)3633 int32_t lsm6dsm_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsm_sim_t *val)
3634 {
3635 lsm6dsm_ctrl3_c_t ctrl3_c;
3636 int32_t ret;
3637
3638 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3639
3640 switch (ctrl3_c.sim)
3641 {
3642 case LSM6DSM_SPI_4_WIRE:
3643 *val = LSM6DSM_SPI_4_WIRE;
3644 break;
3645
3646 case LSM6DSM_SPI_3_WIRE:
3647 *val = LSM6DSM_SPI_3_WIRE;
3648 break;
3649
3650 default:
3651 *val = LSM6DSM_SPI_4_WIRE;
3652 break;
3653 }
3654
3655 return ret;
3656 }
3657
3658 /**
3659 * @brief Disable / Enable I2C interface.[set]
3660 *
3661 * @param ctx Read / write interface definitions
3662 * @param val Change the values of i2c_disable in reg CTRL4_C
3663 * @retval Interface status (MANDATORY: return 0 -> no Error).
3664 *
3665 */
lsm6dsm_i2c_interface_set(stmdev_ctx_t * ctx,lsm6dsm_i2c_disable_t val)3666 int32_t lsm6dsm_i2c_interface_set(stmdev_ctx_t *ctx,
3667 lsm6dsm_i2c_disable_t val)
3668 {
3669 lsm6dsm_ctrl4_c_t ctrl4_c;
3670 int32_t ret;
3671
3672 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3673
3674 if (ret == 0)
3675 {
3676 ctrl4_c.i2c_disable = (uint8_t)val;
3677 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3678 }
3679
3680 return ret;
3681 }
3682
3683 /**
3684 * @brief Disable / Enable I2C interface.[get]
3685 *
3686 * @param ctx Read / write interface definitions
3687 * @param val Get the values of i2c_disable in reg CTRL4_C
3688 * @retval Interface status (MANDATORY: return 0 -> no Error).
3689 *
3690 */
lsm6dsm_i2c_interface_get(stmdev_ctx_t * ctx,lsm6dsm_i2c_disable_t * val)3691 int32_t lsm6dsm_i2c_interface_get(stmdev_ctx_t *ctx,
3692 lsm6dsm_i2c_disable_t *val)
3693 {
3694 lsm6dsm_ctrl4_c_t ctrl4_c;
3695 int32_t ret;
3696
3697 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3698
3699 switch (ctrl4_c.i2c_disable)
3700 {
3701 case LSM6DSM_I2C_ENABLE:
3702 *val = LSM6DSM_I2C_ENABLE;
3703 break;
3704
3705 case LSM6DSM_I2C_DISABLE:
3706 *val = LSM6DSM_I2C_DISABLE;
3707 break;
3708
3709 default:
3710 *val = LSM6DSM_I2C_ENABLE;
3711 break;
3712 }
3713
3714 return ret;
3715 }
3716
3717 /**
3718 * @}
3719 *
3720 */
3721
3722 /**
3723 * @defgroup LSM6DSM_interrupt_pins
3724 * @brief This section groups all the functions that manage
3725 * interrupt pins
3726 * @{
3727 *
3728 */
3729
3730 /**
3731 * @brief Select the signal that need to route on int1 pad[set]
3732 *
3733 * @param ctx Read / write interface definitions
3734 * @param val configure INT1_CTRL, MD1_CFG, CTRL4_C(den_drdy_int1),
3735 * MASTER_CONFIG(drdy_on_int1)
3736 * @retval Interface status (MANDATORY: return 0 -> no Error).
3737 *
3738 */
lsm6dsm_pin_int1_route_set(stmdev_ctx_t * ctx,lsm6dsm_int1_route_t val)3739 int32_t lsm6dsm_pin_int1_route_set(stmdev_ctx_t *ctx,
3740 lsm6dsm_int1_route_t val)
3741 {
3742 lsm6dsm_master_config_t master_config;
3743 lsm6dsm_int1_ctrl_t int1_ctrl;
3744 lsm6dsm_md1_cfg_t md1_cfg;
3745 lsm6dsm_md2_cfg_t md2_cfg;
3746 lsm6dsm_ctrl4_c_t ctrl4_c;
3747 lsm6dsm_tap_cfg_t tap_cfg;
3748 int32_t ret;
3749
3750 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
3751
3752 if (ret == 0)
3753 {
3754 int1_ctrl.int1_drdy_xl = val.int1_drdy_xl;
3755 int1_ctrl.int1_drdy_g = val.int1_drdy_g;
3756 int1_ctrl.int1_boot = val.int1_boot;
3757 int1_ctrl.int1_fth = val.int1_fth;
3758 int1_ctrl.int1_fifo_ovr = val.int1_fifo_ovr;
3759 int1_ctrl.int1_full_flag = val.int1_full_flag;
3760 int1_ctrl.int1_sign_mot = val.int1_sign_mot;
3761 int1_ctrl.int1_step_detector = val.int1_step_detector;
3762 ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
3763 }
3764
3765 if (ret == 0)
3766 {
3767 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3768 }
3769
3770 if (ret == 0)
3771 {
3772 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3773 }
3774
3775 if (ret == 0)
3776 {
3777 md1_cfg.int1_timer = val.int1_timer;
3778 md1_cfg.int1_tilt = val.int1_tilt;
3779 md1_cfg.int1_6d = val.int1_6d;
3780 md1_cfg.int1_double_tap = val.int1_double_tap;
3781 md1_cfg.int1_ff = val.int1_ff;
3782 md1_cfg.int1_wu = val.int1_wu;
3783 md1_cfg.int1_single_tap = val.int1_single_tap;
3784 md1_cfg.int1_inact_state = val.int1_inact_state;
3785 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3786 }
3787
3788 if (ret == 0)
3789 {
3790 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3791 }
3792
3793 if (ret == 0)
3794 {
3795 ctrl4_c.den_drdy_int1 = val.den_drdy_int1;
3796 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3797 }
3798
3799 if (ret == 0)
3800 {
3801 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
3802 (uint8_t *)&master_config, 1);
3803 }
3804
3805 if (ret == 0)
3806 {
3807 master_config.drdy_on_int1 = val.den_drdy_int1;
3808 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
3809 (uint8_t *)&master_config, 1);
3810 }
3811
3812 if (ret == 0)
3813 {
3814 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3815
3816 if ((val.int1_6d != 0x00U) ||
3817 (val.int1_ff != 0x00U) ||
3818 (val.int1_wu != 0x00U) ||
3819 (val.int1_single_tap != 0x00U) ||
3820 (val.int1_double_tap != 0x00U) ||
3821 (val.int1_inact_state != 0x00U) ||
3822 (md2_cfg.int2_6d != 0x00U) ||
3823 (md2_cfg.int2_ff != 0x00U) ||
3824 (md2_cfg.int2_wu != 0x00U) ||
3825 (md2_cfg.int2_single_tap != 0x00U) ||
3826 (md2_cfg.int2_double_tap != 0x00U) ||
3827 (md2_cfg.int2_inact_state != 0x00U))
3828 {
3829 tap_cfg.interrupts_enable = PROPERTY_ENABLE;
3830 }
3831
3832 else
3833 {
3834 tap_cfg.interrupts_enable = PROPERTY_DISABLE;
3835 }
3836 }
3837
3838 if (ret == 0)
3839 {
3840 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3841 }
3842
3843 return ret;
3844 }
3845
3846 /**
3847 * @brief Select the signal that need to route on int1 pad[get]
3848 *
3849 * @param ctx Read / write interface definitions
3850 * @param val read INT1_CTRL, MD1_CFG, CTRL4_C(den_drdy_int1),
3851 * MASTER_CONFIG(drdy_on_int1)
3852 * @retval Interface status (MANDATORY: return 0 -> no Error).
3853 *
3854 */
lsm6dsm_pin_int1_route_get(stmdev_ctx_t * ctx,lsm6dsm_int1_route_t * val)3855 int32_t lsm6dsm_pin_int1_route_get(stmdev_ctx_t *ctx,
3856 lsm6dsm_int1_route_t *val)
3857 {
3858 lsm6dsm_master_config_t master_config;
3859 lsm6dsm_int1_ctrl_t int1_ctrl;
3860 lsm6dsm_md1_cfg_t md1_cfg;
3861 lsm6dsm_ctrl4_c_t ctrl4_c;
3862 int32_t ret;
3863
3864 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
3865
3866 if (ret == 0)
3867 {
3868 val->int1_drdy_xl = int1_ctrl.int1_drdy_xl;
3869 val->int1_drdy_g = int1_ctrl.int1_drdy_g;
3870 val->int1_boot = int1_ctrl.int1_boot;
3871 val->int1_fth = int1_ctrl.int1_fth;
3872 val->int1_fifo_ovr = int1_ctrl.int1_fifo_ovr;
3873 val->int1_full_flag = int1_ctrl.int1_full_flag;
3874 val->int1_sign_mot = int1_ctrl.int1_sign_mot;
3875 val->int1_step_detector = int1_ctrl.int1_step_detector ;
3876 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3877
3878 if (ret == 0)
3879 {
3880 val->int1_timer = md1_cfg.int1_timer;
3881 val->int1_tilt = md1_cfg.int1_tilt;
3882 val->int1_6d = md1_cfg.int1_6d;
3883 val->int1_double_tap = md1_cfg.int1_double_tap;
3884 val->int1_ff = md1_cfg.int1_ff;
3885 val->int1_wu = md1_cfg.int1_wu;
3886 val->int1_single_tap = md1_cfg.int1_single_tap;
3887 val->int1_inact_state = md1_cfg.int1_inact_state;
3888 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3889
3890 if (ret == 0)
3891 {
3892 val->den_drdy_int1 = ctrl4_c.den_drdy_int1;
3893 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
3894 (uint8_t *)&master_config, 1);
3895 val->den_drdy_int1 = master_config.drdy_on_int1;
3896 }
3897 }
3898 }
3899
3900 return ret;
3901 }
3902
3903 /**
3904 * @brief Select the signal that need to route on int2 pad[set]
3905 *
3906 * @param ctx Read / write interface definitions
3907 * @param val INT2_CTRL, DRDY_PULSE_CFG(int2_wrist_tilt), MD2_CFG
3908 * @retval Interface status (MANDATORY: return 0 -> no Error).
3909 *
3910 */
lsm6dsm_pin_int2_route_set(stmdev_ctx_t * ctx,lsm6dsm_int2_route_t val)3911 int32_t lsm6dsm_pin_int2_route_set(stmdev_ctx_t *ctx,
3912 lsm6dsm_int2_route_t val)
3913 {
3914 lsm6dsm_int2_ctrl_t int2_ctrl;
3915 lsm6dsm_md1_cfg_t md1_cfg;
3916 lsm6dsm_md2_cfg_t md2_cfg;
3917 lsm6dsm_drdy_pulse_cfg_t drdy_pulse_cfg;
3918 lsm6dsm_tap_cfg_t tap_cfg;
3919 int32_t ret;
3920
3921 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3922
3923 if (ret == 0)
3924 {
3925 int2_ctrl.int2_drdy_xl = val.int2_drdy_xl;
3926 int2_ctrl.int2_drdy_g = val.int2_drdy_g;
3927 int2_ctrl.int2_drdy_temp = val.int2_drdy_temp;
3928 int2_ctrl.int2_fth = val.int2_fth;
3929 int2_ctrl.int2_fifo_ovr = val.int2_fifo_ovr;
3930 int2_ctrl.int2_full_flag = val.int2_full_flag;
3931 int2_ctrl.int2_step_count_ov = val.int2_step_count_ov;
3932 int2_ctrl.int2_step_delta = val.int2_step_delta;
3933 ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3934 }
3935
3936 if (ret == 0)
3937 {
3938 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3939 }
3940
3941 if (ret == 0)
3942 {
3943 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3944 }
3945
3946 if (ret == 0)
3947 {
3948 md2_cfg.int2_iron = val.int2_iron;
3949 md2_cfg.int2_tilt = val.int2_tilt;
3950 md2_cfg.int2_6d = val.int2_6d;
3951 md2_cfg.int2_double_tap = val.int2_double_tap;
3952 md2_cfg.int2_ff = val.int2_ff;
3953 md2_cfg.int2_wu = val.int2_wu;
3954 md2_cfg.int2_single_tap = val.int2_single_tap;
3955 md2_cfg.int2_inact_state = val.int2_inact_state;
3956 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3957 }
3958
3959 if (ret == 0)
3960 {
3961 ret = lsm6dsm_read_reg(ctx, LSM6DSM_DRDY_PULSE_CFG,
3962 (uint8_t *)&drdy_pulse_cfg, 1);
3963 }
3964
3965 if (ret == 0)
3966 {
3967 drdy_pulse_cfg.int2_wrist_tilt = val.int2_wrist_tilt;
3968 ret = lsm6dsm_write_reg(ctx, LSM6DSM_DRDY_PULSE_CFG,
3969 (uint8_t *)&drdy_pulse_cfg, 1);
3970 }
3971
3972 if (ret == 0)
3973 {
3974 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3975
3976 if ((md1_cfg.int1_6d != 0x00U) ||
3977 (md1_cfg.int1_ff != 0x00U) ||
3978 (md1_cfg.int1_wu != 0x00U) ||
3979 (md1_cfg.int1_single_tap != 0x00U) ||
3980 (md1_cfg.int1_double_tap != 0x00U) ||
3981 (md1_cfg.int1_inact_state != 0x00U) ||
3982 (val.int2_6d != 0x00U) ||
3983 (val.int2_ff != 0x00U) ||
3984 (val.int2_wu != 0x00U) ||
3985 (val.int2_single_tap != 0x00U) ||
3986 (val.int2_double_tap != 0x00U) ||
3987 (val.int2_inact_state != 0x00U))
3988 {
3989 tap_cfg.interrupts_enable = PROPERTY_ENABLE;
3990 }
3991
3992 else
3993 {
3994 tap_cfg.interrupts_enable = PROPERTY_DISABLE;
3995 }
3996 }
3997
3998 if (ret == 0)
3999 {
4000 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4001 }
4002
4003 return ret;
4004 }
4005
4006 /**
4007 * @brief Select the signal that need to route on int2 pad[get]
4008 *
4009 * @param ctx Read / write interface definitions
4010 * @param val INT2_CTRL, DRDY_PULSE_CFG(int2_wrist_tilt), MD2_CFG
4011 * @retval Interface status (MANDATORY: return 0 -> no Error).
4012 *
4013 */
lsm6dsm_pin_int2_route_get(stmdev_ctx_t * ctx,lsm6dsm_int2_route_t * val)4014 int32_t lsm6dsm_pin_int2_route_get(stmdev_ctx_t *ctx,
4015 lsm6dsm_int2_route_t *val)
4016 {
4017 lsm6dsm_int2_ctrl_t int2_ctrl;
4018 lsm6dsm_md2_cfg_t md2_cfg;
4019 lsm6dsm_drdy_pulse_cfg_t drdy_pulse_cfg;
4020 int32_t ret;
4021
4022 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
4023
4024 if (ret == 0)
4025 {
4026 val->int2_drdy_xl = int2_ctrl.int2_drdy_xl;
4027 val->int2_drdy_g = int2_ctrl.int2_drdy_g;
4028 val->int2_drdy_temp = int2_ctrl.int2_drdy_temp;
4029 val->int2_fth = int2_ctrl.int2_fth;
4030 val->int2_fifo_ovr = int2_ctrl.int2_fifo_ovr;
4031 val->int2_full_flag = int2_ctrl.int2_full_flag;
4032 val->int2_step_count_ov = int2_ctrl.int2_step_count_ov;
4033 val->int2_step_delta = int2_ctrl.int2_step_delta;
4034 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD2_CFG, (uint8_t *)&md2_cfg, 1);
4035
4036 if (ret == 0)
4037 {
4038 val->int2_iron = md2_cfg.int2_iron;
4039 val->int2_tilt = md2_cfg.int2_tilt;
4040 val->int2_6d = md2_cfg.int2_6d;
4041 val->int2_double_tap = md2_cfg.int2_double_tap;
4042 val->int2_ff = md2_cfg.int2_ff;
4043 val->int2_wu = md2_cfg.int2_wu;
4044 val->int2_single_tap = md2_cfg.int2_single_tap;
4045 val->int2_inact_state = md2_cfg.int2_inact_state;
4046 ret = lsm6dsm_read_reg(ctx, LSM6DSM_DRDY_PULSE_CFG,
4047 (uint8_t *)&drdy_pulse_cfg, 1);
4048 val->int2_wrist_tilt = drdy_pulse_cfg.int2_wrist_tilt;
4049 }
4050 }
4051
4052 return ret;
4053 }
4054
4055 /**
4056 * @brief Push-pull/open drain selection on interrupt pads.[set]
4057 *
4058 * @param ctx Read / write interface definitions
4059 * @param val Change the values of pp_od in reg CTRL3_C
4060 * @retval Interface status (MANDATORY: return 0 -> no Error).
4061 *
4062 */
lsm6dsm_pin_mode_set(stmdev_ctx_t * ctx,lsm6dsm_pp_od_t val)4063 int32_t lsm6dsm_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsm_pp_od_t val)
4064 {
4065 lsm6dsm_ctrl3_c_t ctrl3_c;
4066 int32_t ret;
4067
4068 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4069
4070 if (ret == 0)
4071 {
4072 ctrl3_c.pp_od = (uint8_t) val;
4073 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4074 }
4075
4076 return ret;
4077 }
4078
4079 /**
4080 * @brief Push-pull/open drain selection on interrupt pads.[get]
4081 *
4082 * @param ctx Read / write interface definitions
4083 * @param val Get the values of pp_od in reg CTRL3_C
4084 * @retval Interface status (MANDATORY: return 0 -> no Error).
4085 *
4086 */
lsm6dsm_pin_mode_get(stmdev_ctx_t * ctx,lsm6dsm_pp_od_t * val)4087 int32_t lsm6dsm_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsm_pp_od_t *val)
4088 {
4089 lsm6dsm_ctrl3_c_t ctrl3_c;
4090 int32_t ret;
4091
4092 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4093
4094 switch (ctrl3_c.pp_od)
4095 {
4096 case LSM6DSM_PUSH_PULL:
4097 *val = LSM6DSM_PUSH_PULL;
4098 break;
4099
4100 case LSM6DSM_OPEN_DRAIN:
4101 *val = LSM6DSM_OPEN_DRAIN;
4102 break;
4103
4104 default:
4105 *val = LSM6DSM_PUSH_PULL;
4106 break;
4107 }
4108
4109 return ret;
4110 }
4111
4112 /**
4113 * @brief Interrupt active-high/low.[set]
4114 *
4115 * @param ctx Read / write interface definitions
4116 * @param val Change the values of h_lactive in reg CTRL3_C
4117 * @retval Interface status (MANDATORY: return 0 -> no Error).
4118 *
4119 */
lsm6dsm_pin_polarity_set(stmdev_ctx_t * ctx,lsm6dsm_h_lactive_t val)4120 int32_t lsm6dsm_pin_polarity_set(stmdev_ctx_t *ctx,
4121 lsm6dsm_h_lactive_t val)
4122 {
4123 lsm6dsm_ctrl3_c_t ctrl3_c;
4124 int32_t ret;
4125
4126 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4127
4128 if (ret == 0)
4129 {
4130 ctrl3_c.h_lactive = (uint8_t) val;
4131 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4132 }
4133
4134 return ret;
4135 }
4136
4137 /**
4138 * @brief Interrupt active-high/low.[get]
4139 *
4140 * @param ctx Read / write interface definitions
4141 * @param val Get the values of h_lactive in reg CTRL3_C
4142 * @retval Interface status (MANDATORY: return 0 -> no Error).
4143 *
4144 */
lsm6dsm_pin_polarity_get(stmdev_ctx_t * ctx,lsm6dsm_h_lactive_t * val)4145 int32_t lsm6dsm_pin_polarity_get(stmdev_ctx_t *ctx,
4146 lsm6dsm_h_lactive_t *val)
4147 {
4148 lsm6dsm_ctrl3_c_t ctrl3_c;
4149 int32_t ret;
4150
4151 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4152
4153 switch (ctrl3_c.h_lactive)
4154 {
4155 case LSM6DSM_ACTIVE_HIGH:
4156 *val = LSM6DSM_ACTIVE_HIGH;
4157 break;
4158
4159 case LSM6DSM_ACTIVE_LOW:
4160 *val = LSM6DSM_ACTIVE_LOW;
4161 break;
4162
4163 default:
4164 *val = LSM6DSM_ACTIVE_HIGH;
4165 break;
4166 }
4167
4168 return ret;
4169 }
4170
4171 /**
4172 * @brief All interrupt signals become available on INT1 pin.[set]
4173 *
4174 * @param ctx Read / write interface definitions
4175 * @param val Change the values of int2_on_int1 in reg CTRL4_C
4176 * @retval Interface status (MANDATORY: return 0 -> no Error).
4177 *
4178 */
lsm6dsm_all_on_int1_set(stmdev_ctx_t * ctx,uint8_t val)4179 int32_t lsm6dsm_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
4180 {
4181 lsm6dsm_ctrl4_c_t ctrl4_c;
4182 int32_t ret;
4183
4184 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4185
4186 if (ret == 0)
4187 {
4188 ctrl4_c.int2_on_int1 = val;
4189 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4190 }
4191
4192 return ret;
4193 }
4194
4195 /**
4196 * @brief All interrupt signals become available on INT1 pin.[get]
4197 *
4198 * @param ctx Read / write interface definitions
4199 * @param val Change the values of int2_on_int1 in reg CTRL4_C
4200 * @retval Interface status (MANDATORY: return 0 -> no Error).
4201 *
4202 */
lsm6dsm_all_on_int1_get(stmdev_ctx_t * ctx,uint8_t * val)4203 int32_t lsm6dsm_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
4204 {
4205 lsm6dsm_ctrl4_c_t ctrl4_c;
4206 int32_t ret;
4207
4208 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4209 *val = ctrl4_c.int2_on_int1;
4210
4211 return ret;
4212 }
4213
4214 /**
4215 * @brief Latched/pulsed interrupt.[set]
4216 *
4217 * @param ctx Read / write interface definitions
4218 * @param val Change the values of lir in reg TAP_CFG
4219 * @retval Interface status (MANDATORY: return 0 -> no Error).
4220 *
4221 */
lsm6dsm_int_notification_set(stmdev_ctx_t * ctx,lsm6dsm_lir_t val)4222 int32_t lsm6dsm_int_notification_set(stmdev_ctx_t *ctx,
4223 lsm6dsm_lir_t val)
4224 {
4225 lsm6dsm_tap_cfg_t tap_cfg;
4226 int32_t ret;
4227
4228 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4229
4230 if (ret == 0)
4231 {
4232 tap_cfg.lir = (uint8_t) val;
4233 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4234 }
4235
4236 return ret;
4237 }
4238
4239 /**
4240 * @brief Latched/pulsed interrupt.[get]
4241 *
4242 * @param ctx Read / write interface definitions
4243 * @param val Get the values of lir in reg TAP_CFG
4244 * @retval Interface status (MANDATORY: return 0 -> no Error).
4245 *
4246 */
lsm6dsm_int_notification_get(stmdev_ctx_t * ctx,lsm6dsm_lir_t * val)4247 int32_t lsm6dsm_int_notification_get(stmdev_ctx_t *ctx,
4248 lsm6dsm_lir_t *val)
4249 {
4250 lsm6dsm_tap_cfg_t tap_cfg;
4251 int32_t ret;
4252
4253 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4254
4255 switch (tap_cfg.lir)
4256 {
4257 case LSM6DSM_INT_PULSED:
4258 *val = LSM6DSM_INT_PULSED;
4259 break;
4260
4261 case LSM6DSM_INT_LATCHED:
4262 *val = LSM6DSM_INT_LATCHED;
4263 break;
4264
4265 default:
4266 *val = LSM6DSM_INT_PULSED;
4267 break;
4268 }
4269
4270 return ret;
4271 }
4272
4273 /**
4274 * @}
4275 *
4276 */
4277
4278 /**
4279 * @defgroup LSM6DSM_Wake_Up_event
4280 * @brief This section groups all the functions that manage the
4281 * Wake Up event generation.
4282 * @{
4283 *
4284 */
4285
4286 /**
4287 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set]
4288 *
4289 * @param ctx Read / write interface definitions
4290 * @param val Change the values of wk_ths in reg WAKE_UP_THS
4291 * @retval Interface status (MANDATORY: return 0 -> no Error).
4292 *
4293 */
lsm6dsm_wkup_threshold_set(stmdev_ctx_t * ctx,uint8_t val)4294 int32_t lsm6dsm_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
4295 {
4296 lsm6dsm_wake_up_ths_t wake_up_ths;
4297 int32_t ret;
4298
4299 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_THS,
4300 (uint8_t *)&wake_up_ths, 1);
4301
4302 if (ret == 0)
4303 {
4304 wake_up_ths.wk_ths = val;
4305 ret = lsm6dsm_write_reg(ctx, LSM6DSM_WAKE_UP_THS,
4306 (uint8_t *)&wake_up_ths, 1);
4307 }
4308
4309 return ret;
4310 }
4311
4312 /**
4313 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get]
4314 *
4315 * @param ctx Read / write interface definitions
4316 * @param val Change the values of wk_ths in reg WAKE_UP_THS
4317 * @retval Interface status (MANDATORY: return 0 -> no Error).
4318 *
4319 */
lsm6dsm_wkup_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)4320 int32_t lsm6dsm_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
4321 {
4322 lsm6dsm_wake_up_ths_t wake_up_ths;
4323 int32_t ret;
4324
4325 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_THS,
4326 (uint8_t *)&wake_up_ths, 1);
4327 *val = wake_up_ths.wk_ths;
4328
4329 return ret;
4330 }
4331
4332 /**
4333 * @brief Wake up duration event.1LSb = 1 / ODR[set]
4334 *
4335 * @param ctx Read / write interface definitions
4336 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
4337 * @retval Interface status (MANDATORY: return 0 -> no Error).
4338 *
4339 */
lsm6dsm_wkup_dur_set(stmdev_ctx_t * ctx,uint8_t val)4340 int32_t lsm6dsm_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
4341 {
4342 lsm6dsm_wake_up_dur_t wake_up_dur;
4343 int32_t ret;
4344
4345 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
4346 (uint8_t *)&wake_up_dur, 1);
4347
4348 if (ret == 0)
4349 {
4350 wake_up_dur.wake_dur = val;
4351 ret = lsm6dsm_write_reg(ctx, LSM6DSM_WAKE_UP_DUR,
4352 (uint8_t *)&wake_up_dur, 1);
4353 }
4354
4355 return ret;
4356 }
4357
4358 /**
4359 * @brief Wake up duration event.1LSb = 1 / ODR[get]
4360 *
4361 * @param ctx Read / write interface definitions
4362 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
4363 * @retval Interface status (MANDATORY: return 0 -> no Error).
4364 *
4365 */
lsm6dsm_wkup_dur_get(stmdev_ctx_t * ctx,uint8_t * val)4366 int32_t lsm6dsm_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
4367 {
4368 lsm6dsm_wake_up_dur_t wake_up_dur;
4369 int32_t ret;
4370
4371 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
4372 (uint8_t *)&wake_up_dur, 1);
4373 *val = wake_up_dur.wake_dur;
4374
4375 return ret;
4376 }
4377
4378 /**
4379 * @}
4380 *
4381 */
4382
4383 /**
4384 * @defgroup LSM6DSM_Activity/Inactivity_detection
4385 * @brief This section groups all the functions concerning
4386 * activity/inactivity detection.
4387 * @{
4388 *
4389 */
4390
4391 /**
4392 * @brief Enables gyroscope Sleep mode.[set]
4393 *
4394 * @param ctx Read / write interface definitions
4395 * @param val Change the values of sleep in reg CTRL4_C
4396 * @retval Interface status (MANDATORY: return 0 -> no Error).
4397 *
4398 */
lsm6dsm_gy_sleep_mode_set(stmdev_ctx_t * ctx,uint8_t val)4399 int32_t lsm6dsm_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
4400 {
4401 lsm6dsm_ctrl4_c_t ctrl4_c;
4402 int32_t ret;
4403
4404 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4405
4406 if (ret == 0)
4407 {
4408 ctrl4_c.sleep = val;
4409 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4410 }
4411
4412 return ret;
4413 }
4414
4415 /**
4416 * @brief Enables gyroscope Sleep mode.[get]
4417 *
4418 * @param ctx Read / write interface definitions
4419 * @param val Change the values of sleep in reg CTRL4_C
4420 * @retval Interface status (MANDATORY: return 0 -> no Error).
4421 *
4422 */
lsm6dsm_gy_sleep_mode_get(stmdev_ctx_t * ctx,uint8_t * val)4423 int32_t lsm6dsm_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
4424 {
4425 lsm6dsm_ctrl4_c_t ctrl4_c;
4426 int32_t ret;
4427
4428 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4429 *val = ctrl4_c.sleep;
4430
4431 return ret;
4432 }
4433
4434 /**
4435 * @brief Enable inactivity function.[set]
4436 *
4437 * @param ctx Read / write interface definitions
4438 * @param val Change the values of inact_en in reg TAP_CFG
4439 * @retval Interface status (MANDATORY: return 0 -> no Error).
4440 *
4441 */
lsm6dsm_act_mode_set(stmdev_ctx_t * ctx,lsm6dsm_inact_en_t val)4442 int32_t lsm6dsm_act_mode_set(stmdev_ctx_t *ctx,
4443 lsm6dsm_inact_en_t val)
4444 {
4445 lsm6dsm_tap_cfg_t tap_cfg;
4446 int32_t ret;
4447
4448 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4449
4450 if (ret == 0)
4451 {
4452 tap_cfg.inact_en = (uint8_t) val;
4453 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4454 }
4455
4456 return ret;
4457 }
4458
4459 /**
4460 * @brief Enable inactivity function.[get]
4461 *
4462 * @param ctx Read / write interface definitions
4463 * @param val Get the values of inact_en in reg TAP_CFG
4464 * @retval Interface status (MANDATORY: return 0 -> no Error).
4465 *
4466 */
lsm6dsm_act_mode_get(stmdev_ctx_t * ctx,lsm6dsm_inact_en_t * val)4467 int32_t lsm6dsm_act_mode_get(stmdev_ctx_t *ctx,
4468 lsm6dsm_inact_en_t *val)
4469 {
4470 lsm6dsm_tap_cfg_t tap_cfg;
4471 int32_t ret;
4472
4473 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4474
4475 switch (tap_cfg.inact_en)
4476 {
4477 case LSM6DSM_PROPERTY_DISABLE:
4478 *val = LSM6DSM_PROPERTY_DISABLE;
4479 break;
4480
4481 case LSM6DSM_XL_12Hz5_GY_NOT_AFFECTED:
4482 *val = LSM6DSM_XL_12Hz5_GY_NOT_AFFECTED;
4483 break;
4484
4485 case LSM6DSM_XL_12Hz5_GY_SLEEP:
4486 *val = LSM6DSM_XL_12Hz5_GY_SLEEP;
4487 break;
4488
4489 case LSM6DSM_XL_12Hz5_GY_PD:
4490 *val = LSM6DSM_XL_12Hz5_GY_PD;
4491 break;
4492
4493 default:
4494 *val = LSM6DSM_PROPERTY_DISABLE;
4495 break;
4496 }
4497
4498 return ret;
4499 }
4500
4501 /**
4502 * @brief Duration to go in sleep mode.1 LSb = 512 / ODR[set]
4503 *
4504 * @param ctx Read / write interface definitions
4505 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
4506 * @retval Interface status (MANDATORY: return 0 -> no Error).
4507 *
4508 */
lsm6dsm_act_sleep_dur_set(stmdev_ctx_t * ctx,uint8_t val)4509 int32_t lsm6dsm_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
4510 {
4511 lsm6dsm_wake_up_dur_t wake_up_dur;
4512 int32_t ret;
4513
4514 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
4515 (uint8_t *)&wake_up_dur, 1);
4516
4517 if (ret == 0)
4518 {
4519 wake_up_dur.sleep_dur = val;
4520 ret = lsm6dsm_write_reg(ctx, LSM6DSM_WAKE_UP_DUR,
4521 (uint8_t *)&wake_up_dur, 1);
4522 }
4523
4524 return ret;
4525 }
4526
4527 /**
4528 * @brief Duration to go in sleep mode. 1 LSb = 512 / ODR[get]
4529 *
4530 * @param ctx Read / write interface definitions
4531 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
4532 * @retval Interface status (MANDATORY: return 0 -> no Error).
4533 *
4534 */
lsm6dsm_act_sleep_dur_get(stmdev_ctx_t * ctx,uint8_t * val)4535 int32_t lsm6dsm_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
4536 {
4537 lsm6dsm_wake_up_dur_t wake_up_dur;
4538 int32_t ret;
4539
4540 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
4541 (uint8_t *)&wake_up_dur, 1);
4542 *val = wake_up_dur.sleep_dur;
4543
4544 return ret;
4545 }
4546
4547 /**
4548 * @}
4549 *
4550 */
4551
4552 /**
4553 * @defgroup LSM6DSM_tap_generator
4554 * @brief This section groups all the functions that manage the
4555 * tap and double tap event generation.
4556 * @{
4557 *
4558 */
4559
4560 /**
4561 * @brief Read the tap / double tap source register.[get]
4562 *
4563 * @param ctx Read / write interface definitions
4564 * @param val Structure of registers from TAP_SRC
4565 * @retval Interface status (MANDATORY: return 0 -> no Error).
4566 *
4567 */
lsm6dsm_tap_src_get(stmdev_ctx_t * ctx,lsm6dsm_tap_src_t * val)4568 int32_t lsm6dsm_tap_src_get(stmdev_ctx_t *ctx, lsm6dsm_tap_src_t *val)
4569 {
4570 int32_t ret;
4571
4572 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_SRC, (uint8_t *) val, 1);
4573
4574 return ret;
4575 }
4576
4577 /**
4578 * @brief Enable Z direction in tap recognition.[set]
4579 *
4580 * @param ctx Read / write interface definitions
4581 * @param val Change the values of tap_z_en in reg TAP_CFG
4582 *
4583 */
lsm6dsm_tap_detection_on_z_set(stmdev_ctx_t * ctx,uint8_t val)4584 int32_t lsm6dsm_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
4585 {
4586 lsm6dsm_tap_cfg_t tap_cfg;
4587 int32_t ret;
4588
4589 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4590
4591 if (ret == 0)
4592 {
4593 tap_cfg.tap_z_en = val;
4594 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4595 }
4596
4597 return ret;
4598 }
4599
4600 /**
4601 * @brief Enable Z direction in tap recognition.[get]
4602 *
4603 * @param ctx Read / write interface definitions
4604 * @param val Change the values of tap_z_en in reg TAP_CFG
4605 * @retval Interface status (MANDATORY: return 0 -> no Error).
4606 *
4607 */
lsm6dsm_tap_detection_on_z_get(stmdev_ctx_t * ctx,uint8_t * val)4608 int32_t lsm6dsm_tap_detection_on_z_get(stmdev_ctx_t *ctx,
4609 uint8_t *val)
4610 {
4611 lsm6dsm_tap_cfg_t tap_cfg;
4612 int32_t ret;
4613
4614 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4615 *val = tap_cfg.tap_z_en;
4616
4617 return ret;
4618 }
4619
4620 /**
4621 * @brief Enable Y direction in tap recognition.[set]
4622 *
4623 * @param ctx Read / write interface definitions
4624 * @param val Change the values of tap_y_en in reg TAP_CFG
4625 * @retval Interface status (MANDATORY: return 0 -> no Error).
4626 *
4627 */
lsm6dsm_tap_detection_on_y_set(stmdev_ctx_t * ctx,uint8_t val)4628 int32_t lsm6dsm_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
4629 {
4630 lsm6dsm_tap_cfg_t tap_cfg;
4631 int32_t ret;
4632
4633 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4634
4635 if (ret == 0)
4636 {
4637 tap_cfg.tap_y_en = val;
4638 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4639 }
4640
4641 return ret;
4642 }
4643
4644 /**
4645 * @brief Enable Y direction in tap recognition.[get]
4646 *
4647 * @param ctx Read / write interface definitions
4648 * @param val Change the values of tap_y_en in reg TAP_CFG
4649 * @retval Interface status (MANDATORY: return 0 -> no Error).
4650 *
4651 */
lsm6dsm_tap_detection_on_y_get(stmdev_ctx_t * ctx,uint8_t * val)4652 int32_t lsm6dsm_tap_detection_on_y_get(stmdev_ctx_t *ctx,
4653 uint8_t *val)
4654 {
4655 lsm6dsm_tap_cfg_t tap_cfg;
4656 int32_t ret;
4657
4658 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4659 *val = tap_cfg.tap_y_en;
4660
4661 return ret;
4662 }
4663
4664 /**
4665 * @brief Enable X direction in tap recognition.[set]
4666 *
4667 * @param ctx Read / write interface definitions
4668 * @param val Change the values of tap_x_en in reg TAP_CFG
4669 * @retval Interface status (MANDATORY: return 0 -> no Error).
4670 *
4671 */
lsm6dsm_tap_detection_on_x_set(stmdev_ctx_t * ctx,uint8_t val)4672 int32_t lsm6dsm_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
4673 {
4674 lsm6dsm_tap_cfg_t tap_cfg;
4675 int32_t ret;
4676
4677 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4678
4679 if (ret == 0)
4680 {
4681 tap_cfg.tap_x_en = val;
4682 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4683 }
4684
4685 return ret;
4686 }
4687
4688 /**
4689 * @brief Enable X direction in tap recognition.[get]
4690 *
4691 * @param ctx Read / write interface definitions
4692 * @param val Change the values of tap_x_en in reg TAP_CFG
4693 * @retval Interface status (MANDATORY: return 0 -> no Error).
4694 *
4695 */
lsm6dsm_tap_detection_on_x_get(stmdev_ctx_t * ctx,uint8_t * val)4696 int32_t lsm6dsm_tap_detection_on_x_get(stmdev_ctx_t *ctx,
4697 uint8_t *val)
4698 {
4699 lsm6dsm_tap_cfg_t tap_cfg;
4700 int32_t ret;
4701
4702 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4703 *val = tap_cfg.tap_x_en;
4704
4705 return ret;
4706 }
4707
4708 /**
4709 * @brief Threshold for tap recognition.[set]
4710 *
4711 * @param ctx Read / write interface definitions
4712 * @param val Change the values of tap_ths in reg TAP_THS_6D
4713 * @retval Interface status (MANDATORY: return 0 -> no Error).
4714 *
4715 */
lsm6dsm_tap_threshold_x_set(stmdev_ctx_t * ctx,uint8_t val)4716 int32_t lsm6dsm_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
4717 {
4718 lsm6dsm_tap_ths_6d_t tap_ths_6d;
4719 int32_t ret;
4720
4721 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D,
4722 (uint8_t *)&tap_ths_6d, 1);
4723
4724 if (ret == 0)
4725 {
4726 tap_ths_6d.tap_ths = val;
4727 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_THS_6D,
4728 (uint8_t *)&tap_ths_6d, 1);
4729 }
4730
4731 return ret;
4732 }
4733
4734 /**
4735 * @brief Threshold for tap recognition.[get]
4736 *
4737 * @param ctx Read / write interface definitions
4738 * @param val Change the values of tap_ths in reg TAP_THS_6D
4739 * @retval Interface status (MANDATORY: return 0 -> no Error).
4740 *
4741 */
lsm6dsm_tap_threshold_x_get(stmdev_ctx_t * ctx,uint8_t * val)4742 int32_t lsm6dsm_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
4743 {
4744 lsm6dsm_tap_ths_6d_t tap_ths_6d;
4745 int32_t ret;
4746
4747 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D,
4748 (uint8_t *)&tap_ths_6d, 1);
4749 *val = tap_ths_6d.tap_ths;
4750
4751 return ret;
4752 }
4753
4754 /**
4755 * @brief Maximum duration is the maximum time of an overthreshold signal
4756 * detection to be recognized as a tap event.
4757 * The default value of these bits is 00b which corresponds to
4758 * 4*ODR_XL time.
4759 * If the SHOCK[1:0] bits are set to a different
4760 * value, 1LSB corresponds to 8*ODR_XL time.[set]
4761 *
4762 * @param ctx Read / write interface definitions
4763 * @param val Change the values of shock in reg INT_DUR2
4764 * @retval Interface status (MANDATORY: return 0 -> no Error).
4765 *
4766 */
lsm6dsm_tap_shock_set(stmdev_ctx_t * ctx,uint8_t val)4767 int32_t lsm6dsm_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
4768 {
4769 lsm6dsm_int_dur2_t int_dur2;
4770 int32_t ret;
4771
4772 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
4773
4774 if (ret == 0)
4775 {
4776 int_dur2.shock = val;
4777 ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
4778 }
4779
4780 return ret;
4781 }
4782
4783 /**
4784 * @brief Maximum duration is the maximum time of an overthreshold signal
4785 * detection to be recognized as a tap event.
4786 * The default value of these bits is 00b which corresponds to
4787 * 4*ODR_XL time.
4788 * If the SHOCK[1:0] bits are set to a different value, 1LSB
4789 * corresponds to 8*ODR_XL time.[get]
4790 *
4791 * @param ctx Read / write interface definitions
4792 * @param val Change the values of shock in reg INT_DUR2
4793 * @retval Interface status (MANDATORY: return 0 -> no Error).
4794 *
4795 */
lsm6dsm_tap_shock_get(stmdev_ctx_t * ctx,uint8_t * val)4796 int32_t lsm6dsm_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
4797 {
4798 lsm6dsm_int_dur2_t int_dur2;
4799 int32_t ret;
4800
4801 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
4802 *val = int_dur2.shock;
4803
4804 return ret;
4805 }
4806
4807 /**
4808 * @brief Quiet time is the time after the first detected tap in which there
4809 * must not be any overthreshold event.
4810 * The default value of these bits is 00b which corresponds to
4811 * 2*ODR_XL time.
4812 * If the QUIET[1:0] bits are set to a different value, 1LSB
4813 * corresponds to 4*ODR_XL time.[set]
4814 *
4815 * @param ctx Read / write interface definitions
4816 * @param val Change the values of quiet in reg INT_DUR2
4817 * @retval Interface status (MANDATORY: return 0 -> no Error).
4818 *
4819 */
lsm6dsm_tap_quiet_set(stmdev_ctx_t * ctx,uint8_t val)4820 int32_t lsm6dsm_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
4821 {
4822 lsm6dsm_int_dur2_t int_dur2;
4823 int32_t ret;
4824
4825 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
4826
4827 if (ret == 0)
4828 {
4829 int_dur2.quiet = val;
4830 ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
4831 }
4832
4833 return ret;
4834 }
4835
4836 /**
4837 * @brief Quiet time is the time after the first detected tap in which there
4838 * must not be any overthreshold event.
4839 * The default value of these bits is 00b which corresponds to
4840 * 2*ODR_XL time.
4841 * If the QUIET[1:0] bits are set to a different value, 1LSB
4842 * corresponds to 4*ODR_XL time.[get]
4843 *
4844 * @param ctx Read / write interface definitions
4845 * @param val Change the values of quiet in reg INT_DUR2
4846 * @retval Interface status (MANDATORY: return 0 -> no Error).
4847 *
4848 */
lsm6dsm_tap_quiet_get(stmdev_ctx_t * ctx,uint8_t * val)4849 int32_t lsm6dsm_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
4850 {
4851 lsm6dsm_int_dur2_t int_dur2;
4852 int32_t ret;
4853
4854 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
4855 *val = int_dur2.quiet;
4856
4857 return ret;
4858 }
4859
4860 /**
4861 * @brief When double tap recognition is enabled, this register expresses the
4862 * maximum time between two consecutive detected taps to determine a
4863 * double tap event.
4864 * The default value of these bits is 0000b which corresponds to
4865 * 16*ODR_XL time.
4866 * If the DUR[3:0] bits are set to a different value,1LSB corresponds
4867 * to 32*ODR_XL time.[set]
4868 *
4869 * @param ctx Read / write interface definitions
4870 * @param val Change the values of dur in reg INT_DUR2
4871 * @retval Interface status (MANDATORY: return 0 -> no Error).
4872 *
4873 */
lsm6dsm_tap_dur_set(stmdev_ctx_t * ctx,uint8_t val)4874 int32_t lsm6dsm_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
4875 {
4876 lsm6dsm_int_dur2_t int_dur2;
4877 int32_t ret;
4878
4879 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
4880
4881 if (ret == 0)
4882 {
4883 int_dur2.dur = val;
4884 ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
4885 }
4886
4887 return ret;
4888 }
4889
4890 /**
4891 * @brief When double tap recognition is enabled, this register expresses the
4892 * maximum time between two consecutive detected taps to determine a
4893 * double tap event.
4894 * The default value of these bits is 0000b which corresponds to
4895 * 16*ODR_XL time.
4896 * If the DUR[3:0] bits are set to a different value,1LSB corresponds
4897 * to 32*ODR_XL time.[get]
4898 *
4899 * @param ctx Read / write interface definitions
4900 * @param val Change the values of dur in reg INT_DUR2
4901 * @retval Interface status (MANDATORY: return 0 -> no Error).
4902 *
4903 */
lsm6dsm_tap_dur_get(stmdev_ctx_t * ctx,uint8_t * val)4904 int32_t lsm6dsm_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
4905 {
4906 lsm6dsm_int_dur2_t int_dur2;
4907 int32_t ret;
4908
4909 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
4910 *val = int_dur2.dur;
4911
4912 return ret;
4913 }
4914
4915 /**
4916 * @brief Single/double-tap event enable/disable.[set]
4917 *
4918 * @param ctx Read / write interface definitions
4919 * @param val Change the values of
4920 * single_double_tap in reg WAKE_UP_THS
4921 * @retval Interface status (MANDATORY: return 0 -> no Error).
4922 *
4923 */
lsm6dsm_tap_mode_set(stmdev_ctx_t * ctx,lsm6dsm_single_double_tap_t val)4924 int32_t lsm6dsm_tap_mode_set(stmdev_ctx_t *ctx,
4925 lsm6dsm_single_double_tap_t val)
4926 {
4927 lsm6dsm_wake_up_ths_t wake_up_ths;
4928 int32_t ret;
4929
4930 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_THS,
4931 (uint8_t *)&wake_up_ths, 1);
4932
4933 if (ret == 0)
4934 {
4935 wake_up_ths.single_double_tap = (uint8_t) val;
4936 ret = lsm6dsm_write_reg(ctx, LSM6DSM_WAKE_UP_THS,
4937 (uint8_t *)&wake_up_ths, 1);
4938 }
4939
4940 return ret;
4941 }
4942
4943 /**
4944 * @brief Single/double-tap event enable/disable.[get]
4945 *
4946 * @param ctx Read / write interface definitions
4947 * @param val Get the values of single_double_tap
4948 * in reg WAKE_UP_THS
4949 * @retval Interface status (MANDATORY: return 0 -> no Error).
4950 *
4951 */
lsm6dsm_tap_mode_get(stmdev_ctx_t * ctx,lsm6dsm_single_double_tap_t * val)4952 int32_t lsm6dsm_tap_mode_get(stmdev_ctx_t *ctx,
4953 lsm6dsm_single_double_tap_t *val)
4954 {
4955 lsm6dsm_wake_up_ths_t wake_up_ths;
4956 int32_t ret;
4957
4958 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_THS,
4959 (uint8_t *)&wake_up_ths, 1);
4960
4961 switch (wake_up_ths.single_double_tap)
4962 {
4963 case LSM6DSM_ONLY_SINGLE:
4964 *val = LSM6DSM_ONLY_SINGLE;
4965 break;
4966
4967 case LSM6DSM_BOTH_SINGLE_DOUBLE:
4968 *val = LSM6DSM_BOTH_SINGLE_DOUBLE;
4969 break;
4970
4971 default:
4972 *val = LSM6DSM_ONLY_SINGLE;
4973 break;
4974 }
4975
4976 return ret;
4977 }
4978
4979 /**
4980 * @}
4981 *
4982 */
4983
4984 /**
4985 * @defgroup LSM6DSM_ Six_position_detection(6D/4D)
4986 * @brief This section groups all the functions concerning six
4987 * position detection (6D).
4988 * @{
4989 *
4990 */
4991
4992 /**
4993 * @brief LPF2 feed 6D function selection.[set]
4994 *
4995 * @param ctx Read / write interface definitions
4996 * @param val Change the values of low_pass_on_6d in
4997 * reg CTRL8_XL
4998 * @retval Interface status (MANDATORY: return 0 -> no Error).
4999 *
5000 */
lsm6dsm_6d_feed_data_set(stmdev_ctx_t * ctx,lsm6dsm_low_pass_on_6d_t val)5001 int32_t lsm6dsm_6d_feed_data_set(stmdev_ctx_t *ctx,
5002 lsm6dsm_low_pass_on_6d_t val)
5003 {
5004 lsm6dsm_ctrl8_xl_t ctrl8_xl;
5005 int32_t ret;
5006
5007 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
5008
5009 if (ret == 0)
5010 {
5011 ctrl8_xl.low_pass_on_6d = (uint8_t) val;
5012 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
5013 }
5014
5015 return ret;
5016 }
5017
5018 /**
5019 * @brief LPF2 feed 6D function selection.[get]
5020 *
5021 * @param ctx Read / write interface definitions
5022 * @param val Get the values of low_pass_on_6d in reg CTRL8_XL
5023 * @retval Interface status (MANDATORY: return 0 -> no Error).
5024 *
5025 */
lsm6dsm_6d_feed_data_get(stmdev_ctx_t * ctx,lsm6dsm_low_pass_on_6d_t * val)5026 int32_t lsm6dsm_6d_feed_data_get(stmdev_ctx_t *ctx,
5027 lsm6dsm_low_pass_on_6d_t *val)
5028 {
5029 lsm6dsm_ctrl8_xl_t ctrl8_xl;
5030 int32_t ret;
5031
5032 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
5033
5034 switch (ctrl8_xl.low_pass_on_6d)
5035 {
5036 case LSM6DSM_ODR_DIV_2_FEED:
5037 *val = LSM6DSM_ODR_DIV_2_FEED;
5038 break;
5039
5040 case LSM6DSM_LPF2_FEED:
5041 *val = LSM6DSM_LPF2_FEED;
5042 break;
5043
5044 default:
5045 *val = LSM6DSM_ODR_DIV_2_FEED;
5046 break;
5047 }
5048
5049 return ret;
5050 }
5051
5052 /**
5053 * @brief Threshold for 4D/6D function.[set]
5054 *
5055 * @param ctx Read / write interface definitions
5056 * @param val Change the values of sixd_ths in reg TAP_THS_6D
5057 * @retval Interface status (MANDATORY: return 0 -> no Error).
5058 *
5059 */
lsm6dsm_6d_threshold_set(stmdev_ctx_t * ctx,lsm6dsm_sixd_ths_t val)5060 int32_t lsm6dsm_6d_threshold_set(stmdev_ctx_t *ctx,
5061 lsm6dsm_sixd_ths_t val)
5062 {
5063 lsm6dsm_tap_ths_6d_t tap_ths_6d;
5064 int32_t ret;
5065
5066 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D,
5067 (uint8_t *)&tap_ths_6d, 1);
5068
5069 if (ret == 0)
5070 {
5071 tap_ths_6d.sixd_ths = (uint8_t) val;
5072 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_THS_6D,
5073 (uint8_t *)&tap_ths_6d, 1);
5074 }
5075
5076 return ret;
5077 }
5078
5079 /**
5080 * @brief Threshold for 4D/6D function.[get]
5081 *
5082 * @param ctx Read / write interface definitions
5083 * @param val Get the values of sixd_ths in reg TAP_THS_6D
5084 * @retval Interface status (MANDATORY: return 0 -> no Error).
5085 *
5086 */
lsm6dsm_6d_threshold_get(stmdev_ctx_t * ctx,lsm6dsm_sixd_ths_t * val)5087 int32_t lsm6dsm_6d_threshold_get(stmdev_ctx_t *ctx,
5088 lsm6dsm_sixd_ths_t *val)
5089 {
5090 lsm6dsm_tap_ths_6d_t tap_ths_6d;
5091 int32_t ret;
5092
5093 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D,
5094 (uint8_t *)&tap_ths_6d, 1);
5095
5096 switch (tap_ths_6d.sixd_ths)
5097 {
5098 case LSM6DSM_DEG_80:
5099 *val = LSM6DSM_DEG_80;
5100 break;
5101
5102 case LSM6DSM_DEG_70:
5103 *val = LSM6DSM_DEG_70;
5104 break;
5105
5106 case LSM6DSM_DEG_60:
5107 *val = LSM6DSM_DEG_60;
5108 break;
5109
5110 case LSM6DSM_DEG_50:
5111 *val = LSM6DSM_DEG_50;
5112 break;
5113
5114 default:
5115 *val = LSM6DSM_DEG_80;
5116 break;
5117 }
5118
5119 return ret;
5120 }
5121
5122 /**
5123 * @brief 4D orientation detection enable.[set]
5124 *
5125 * @param ctx Read / write interface definitions
5126 * @param val Change the values of d4d_en in reg TAP_THS_6D
5127 * @retval Interface status (MANDATORY: return 0 -> no Error).
5128 *
5129 */
lsm6dsm_4d_mode_set(stmdev_ctx_t * ctx,uint8_t val)5130 int32_t lsm6dsm_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
5131 {
5132 lsm6dsm_tap_ths_6d_t tap_ths_6d;
5133 int32_t ret;
5134
5135 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D,
5136 (uint8_t *)&tap_ths_6d, 1);
5137
5138 if (ret == 0)
5139 {
5140 tap_ths_6d.d4d_en = val;
5141 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_THS_6D,
5142 (uint8_t *)&tap_ths_6d, 1);
5143 }
5144
5145 return ret;
5146 }
5147
5148 /**
5149 * @brief 4D orientation detection enable.[get]
5150 *
5151 * @param ctx Read / write interface definitions
5152 * @param val Change the values of d4d_en in reg TAP_THS_6D
5153 * @retval Interface status (MANDATORY: return 0 -> no Error).
5154 *
5155 */
lsm6dsm_4d_mode_get(stmdev_ctx_t * ctx,uint8_t * val)5156 int32_t lsm6dsm_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
5157 {
5158 lsm6dsm_tap_ths_6d_t tap_ths_6d;
5159 int32_t ret;
5160
5161 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D,
5162 (uint8_t *)&tap_ths_6d, 1);
5163 *val = tap_ths_6d.d4d_en;
5164
5165 return ret;
5166 }
5167
5168 /**
5169 * @}
5170 *
5171 */
5172
5173 /**
5174 * @defgroup LSM6DSM_free_fall
5175 * @brief This section group all the functions concerning the free
5176 * fall detection.
5177 * @{
5178 *
5179 */
5180
5181 /**
5182 * @brief Free-fall duration event. 1LSb = 1 / ODR[set]
5183 *
5184 * @param ctx Read / write interface definitions
5185 * @param val Change the values of ff_dur in reg WAKE_UP_DUR
5186 * @retval Interface status (MANDATORY: return 0 -> no Error).
5187 *
5188 */
lsm6dsm_ff_dur_set(stmdev_ctx_t * ctx,uint8_t val)5189 int32_t lsm6dsm_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
5190 {
5191 lsm6dsm_wake_up_dur_t wake_up_dur;
5192 lsm6dsm_free_fall_t free_fall;
5193 int32_t ret;
5194
5195 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1);
5196
5197 if (ret == 0)
5198 {
5199 free_fall.ff_dur = (val & 0x1FU);
5200 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1);
5201
5202 if (ret == 0)
5203 {
5204 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
5205 (uint8_t *)&wake_up_dur, 1);
5206
5207 if (ret == 0)
5208 {
5209 wake_up_dur.ff_dur = (val & 0x20U) >> 5;
5210 ret = lsm6dsm_write_reg(ctx, LSM6DSM_WAKE_UP_DUR,
5211 (uint8_t *)&wake_up_dur, 1);
5212 }
5213 }
5214 }
5215
5216 return ret;
5217 }
5218
5219 /**
5220 * @brief Free-fall duration event. 1LSb = 1 / ODR[get]
5221 *
5222 * @param ctx Read / write interface definitions
5223 * @param val Change the values of ff_dur in reg WAKE_UP_DUR
5224 * @retval Interface status (MANDATORY: return 0 -> no Error).
5225 *
5226 */
lsm6dsm_ff_dur_get(stmdev_ctx_t * ctx,uint8_t * val)5227 int32_t lsm6dsm_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
5228 {
5229 lsm6dsm_wake_up_dur_t wake_up_dur;
5230 lsm6dsm_free_fall_t free_fall;
5231 int32_t ret;
5232
5233 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
5234 (uint8_t *)&wake_up_dur, 1);
5235
5236 if (ret == 0)
5237 {
5238 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1);
5239 }
5240
5241 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
5242
5243 return ret;
5244 }
5245
5246 /**
5247 * @brief Free fall threshold setting.[set]
5248 *
5249 * @param ctx Read / write interface definitions
5250 * @param val Change the values of ff_ths in reg FREE_FALL
5251 * @retval Interface status (MANDATORY: return 0 -> no Error).
5252 *
5253 */
lsm6dsm_ff_threshold_set(stmdev_ctx_t * ctx,lsm6dsm_ff_ths_t val)5254 int32_t lsm6dsm_ff_threshold_set(stmdev_ctx_t *ctx,
5255 lsm6dsm_ff_ths_t val)
5256 {
5257 lsm6dsm_free_fall_t free_fall;
5258 int32_t ret;
5259
5260 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1);
5261
5262 if (ret == 0)
5263 {
5264 free_fall.ff_ths = (uint8_t) val;
5265 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1);
5266 }
5267
5268 return ret;
5269 }
5270
5271 /**
5272 * @brief Free fall threshold setting.[get]
5273 *
5274 * @param ctx Read / write interface definitions
5275 * @param val Get the values of ff_ths in reg FREE_FALL
5276 * @retval Interface status (MANDATORY: return 0 -> no Error).
5277 *
5278 */
lsm6dsm_ff_threshold_get(stmdev_ctx_t * ctx,lsm6dsm_ff_ths_t * val)5279 int32_t lsm6dsm_ff_threshold_get(stmdev_ctx_t *ctx,
5280 lsm6dsm_ff_ths_t *val)
5281 {
5282 lsm6dsm_free_fall_t free_fall;
5283 int32_t ret;
5284
5285 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1);
5286
5287 switch (free_fall.ff_ths)
5288 {
5289 case LSM6DSM_FF_TSH_156mg:
5290 *val = LSM6DSM_FF_TSH_156mg;
5291 break;
5292
5293 case LSM6DSM_FF_TSH_219mg:
5294 *val = LSM6DSM_FF_TSH_219mg;
5295 break;
5296
5297 case LSM6DSM_FF_TSH_250mg:
5298 *val = LSM6DSM_FF_TSH_250mg;
5299 break;
5300
5301 case LSM6DSM_FF_TSH_312mg:
5302 *val = LSM6DSM_FF_TSH_312mg;
5303 break;
5304
5305 case LSM6DSM_FF_TSH_344mg:
5306 *val = LSM6DSM_FF_TSH_344mg;
5307 break;
5308
5309 case LSM6DSM_FF_TSH_406mg:
5310 *val = LSM6DSM_FF_TSH_406mg;
5311 break;
5312
5313 case LSM6DSM_FF_TSH_469mg:
5314 *val = LSM6DSM_FF_TSH_469mg;
5315 break;
5316
5317 case LSM6DSM_FF_TSH_500mg:
5318 *val = LSM6DSM_FF_TSH_500mg;
5319 break;
5320
5321 default:
5322 *val = LSM6DSM_FF_TSH_156mg;
5323 break;
5324 }
5325
5326 return ret;
5327 }
5328
5329 /**
5330 * @}
5331 *
5332 */
5333
5334 /**
5335 * @defgroup LSM6DSM_fifo
5336 * @brief This section group all the functions concerning the
5337 * fifo usage
5338 * @{
5339 *
5340 */
5341
5342 /**
5343 * @brief FIFO watermark level selection.[set]
5344 *
5345 * @param ctx Read / write interface definitions
5346 * @param val Change the values of fth in reg FIFO_CTRL1
5347 * @retval Interface status (MANDATORY: return 0 -> no Error).
5348 *
5349 */
lsm6dsm_fifo_watermark_set(stmdev_ctx_t * ctx,uint16_t val)5350 int32_t lsm6dsm_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
5351 {
5352 lsm6dsm_fifo_ctrl1_t fifo_ctrl1;
5353 lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
5354 int32_t ret;
5355
5356 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
5357 (uint8_t *)&fifo_ctrl2, 1);
5358
5359 if (ret == 0)
5360 {
5361 fifo_ctrl1.fth = (uint8_t)(0x00FFU & val);
5362 fifo_ctrl2.fth = (uint8_t)((0x0700U & val) >> 8);
5363 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL1,
5364 (uint8_t *)&fifo_ctrl1, 1);
5365
5366 if (ret == 0)
5367 {
5368 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL2,
5369 (uint8_t *)&fifo_ctrl2, 1);
5370 }
5371 }
5372
5373 return ret;
5374 }
5375
5376 /**
5377 * @brief FIFO watermark level selection.[get]
5378 *
5379 * @param ctx Read / write interface definitions
5380 * @param val Change the values of fth in reg FIFO_CTRL1
5381 * @retval Interface status (MANDATORY: return 0 -> no Error).
5382 *
5383 */
lsm6dsm_fifo_watermark_get(stmdev_ctx_t * ctx,uint16_t * val)5384 int32_t lsm6dsm_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
5385 {
5386 lsm6dsm_fifo_ctrl1_t fifo_ctrl1;
5387 lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
5388 int32_t ret;
5389
5390 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL1,
5391 (uint8_t *)&fifo_ctrl1, 1);
5392
5393 if (ret == 0)
5394 {
5395 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
5396 (uint8_t *)&fifo_ctrl2, 1);
5397 }
5398
5399 *val = ((uint16_t)fifo_ctrl2.fth << 8) + (uint16_t)fifo_ctrl1.fth;
5400
5401 return ret;
5402 }
5403
5404 /**
5405 * @brief FIFO data level.[get]
5406 *
5407 * @param ctx Read / write interface definitions
5408 * @param val get the values of diff_fifo in reg FIFO_STATUS1 and
5409 * FIFO_STATUS2(diff_fifo), it is recommended to set the
5410 * BDU bit.
5411 * @retval Interface status (MANDATORY: return 0 -> no Error).
5412 *
5413 */
lsm6dsm_fifo_data_level_get(stmdev_ctx_t * ctx,uint16_t * val)5414 int32_t lsm6dsm_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
5415 {
5416 lsm6dsm_fifo_status1_t fifo_status1;
5417 lsm6dsm_fifo_status2_t fifo_status2;
5418 int32_t ret;
5419
5420 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS1,
5421 (uint8_t *)&fifo_status1, 1);
5422
5423 if (ret == 0)
5424 {
5425 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS2,
5426 (uint8_t *)&fifo_status2, 1);
5427 *val = ((uint16_t) fifo_status2.diff_fifo << 8) +
5428 (uint16_t) fifo_status1.diff_fifo;
5429 }
5430
5431 return ret;
5432 }
5433
5434 /**
5435 * @brief FIFO watermark.[get]
5436 *
5437 * @param ctx Read / write interface definitions
5438 * @param val get the values of watermark in reg FIFO_STATUS2 and
5439 * @retval Interface status (MANDATORY: return 0 -> no Error).
5440 *
5441 */
lsm6dsm_fifo_wtm_flag_get(stmdev_ctx_t * ctx,uint8_t * val)5442 int32_t lsm6dsm_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
5443 {
5444 lsm6dsm_fifo_status2_t fifo_status2;
5445 int32_t ret;
5446
5447 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS2,
5448 (uint8_t *)&fifo_status2, 1);
5449 *val = fifo_status2.waterm;
5450
5451 return ret;
5452 }
5453
5454 /**
5455 * @brief FIFO over run.[get]
5456 *
5457 * @param ctx Read / write interface definitions
5458 * @param val get the value of over run in reg FIFO_STATUS2
5459 * @retval Interface status (MANDATORY: return 0 -> no Error).
5460 *
5461 */
lsm6dsm_fifo_over_run_get(stmdev_ctx_t * ctx,uint8_t * val)5462 int32_t lsm6dsm_fifo_over_run_get(stmdev_ctx_t *ctx, uint8_t *val)
5463 {
5464 lsm6dsm_fifo_status2_t fifo_status2;
5465 int32_t ret;
5466
5467 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS2,
5468 (uint8_t *)&fifo_status2, 1);
5469 *val = fifo_status2.over_run;
5470
5471 return ret;
5472 }
5473
5474 /**
5475 * @brief FIFO pattern.[get]
5476 *
5477 * @param ctx Read / write interface definitions
5478 * @param val get the values of fifo_pattern in reg FIFO_STATUS3 and
5479 * FIFO_STATUS4, it is recommended to set the BDU bit
5480 * @retval Interface status (MANDATORY: return 0 -> no Error).
5481 *
5482 */
lsm6dsm_fifo_pattern_get(stmdev_ctx_t * ctx,uint16_t * val)5483 int32_t lsm6dsm_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val)
5484 {
5485 lsm6dsm_fifo_status3_t fifo_status3;
5486 lsm6dsm_fifo_status4_t fifo_status4;
5487 int32_t ret;
5488
5489 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS3,
5490 (uint8_t *)&fifo_status3, 1);
5491
5492 if (ret == 0)
5493 {
5494 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS4,
5495 (uint8_t *)&fifo_status4, 1);
5496 *val = ((uint16_t)fifo_status4.fifo_pattern << 8) +
5497 fifo_status3.fifo_pattern;
5498 }
5499
5500 return ret;
5501 }
5502
5503 /**
5504 * @brief Batching of temperature data[set]
5505 *
5506 * @param ctx Read / write interface definitions
5507 * @param val Change the values of fifo_temp_en in reg FIFO_CTRL2
5508 * @retval Interface status (MANDATORY: return 0 -> no Error).
5509 *
5510 */
lsm6dsm_fifo_temp_batch_set(stmdev_ctx_t * ctx,uint8_t val)5511 int32_t lsm6dsm_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val)
5512 {
5513 lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
5514 int32_t ret;
5515
5516 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
5517 (uint8_t *)&fifo_ctrl2, 1);
5518
5519 if (ret == 0)
5520 {
5521 fifo_ctrl2.fifo_temp_en = val;
5522 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL2,
5523 (uint8_t *)&fifo_ctrl2, 1);
5524 }
5525
5526 return ret;
5527 }
5528
5529 /**
5530 * @brief Batching of temperature data[get]
5531 *
5532 * @param ctx Read / write interface definitions
5533 * @param val Change the values of fifo_temp_en in reg FIFO_CTRL2
5534 * @retval Interface status (MANDATORY: return 0 -> no Error).
5535 *
5536 */
lsm6dsm_fifo_temp_batch_get(stmdev_ctx_t * ctx,uint8_t * val)5537 int32_t lsm6dsm_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
5538 {
5539 lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
5540 int32_t ret;
5541
5542 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
5543 (uint8_t *)&fifo_ctrl2, 1);
5544 *val = fifo_ctrl2.fifo_temp_en;
5545
5546 return ret;
5547 }
5548
5549 /**
5550 * @brief Trigger signal for FIFO write operation.[set]
5551 *
5552 * @param ctx Read / write interface definitions
5553 * @param val act on FIFO_CTRL2(timer_pedo_fifo_drdy)
5554 * and MASTER_CONFIG(data_valid_sel_fifo)
5555 * @retval Interface status (MANDATORY: return 0 -> no Error).
5556 *
5557 */
lsm6dsm_fifo_write_trigger_set(stmdev_ctx_t * ctx,lsm6dsm_trigger_fifo_t val)5558 int32_t lsm6dsm_fifo_write_trigger_set(stmdev_ctx_t *ctx,
5559 lsm6dsm_trigger_fifo_t val)
5560 {
5561 lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
5562 lsm6dsm_master_config_t master_config;
5563 int32_t ret;
5564
5565 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
5566 (uint8_t *)&fifo_ctrl2, 1);
5567
5568 if (ret == 0)
5569 {
5570 fifo_ctrl2.timer_pedo_fifo_drdy = (uint8_t)val & 0x01U;
5571 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL2,
5572 (uint8_t *)&fifo_ctrl2, 1);
5573
5574 if (ret == 0)
5575 {
5576 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
5577 (uint8_t *)&master_config, 1);
5578
5579 if (ret == 0)
5580 {
5581 master_config.data_valid_sel_fifo = (((uint8_t)val & 0x02U) >> 1);
5582 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
5583 (uint8_t *)&master_config, 1);
5584 }
5585 }
5586 }
5587
5588 return ret;
5589 }
5590
5591 /**
5592 * @brief Trigger signal for FIFO write operation.[get]
5593 *
5594 * @param ctx Read / write interface definitions
5595 * @param val act on FIFO_CTRL2(timer_pedo_fifo_drdy)
5596 * and MASTER_CONFIG(data_valid_sel_fifo)
5597 * @retval Interface status (MANDATORY: return 0 -> no Error).
5598 *
5599 */
lsm6dsm_fifo_write_trigger_get(stmdev_ctx_t * ctx,lsm6dsm_trigger_fifo_t * val)5600 int32_t lsm6dsm_fifo_write_trigger_get(stmdev_ctx_t *ctx,
5601 lsm6dsm_trigger_fifo_t *val)
5602 {
5603 lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
5604 lsm6dsm_master_config_t master_config;
5605 int32_t ret;
5606
5607 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
5608 (uint8_t *)&fifo_ctrl2, 1);
5609
5610 if (ret == 0)
5611 {
5612 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
5613 (uint8_t *)&master_config, 1);
5614
5615 switch ((fifo_ctrl2.timer_pedo_fifo_drdy << 1) +
5616 fifo_ctrl2. timer_pedo_fifo_drdy)
5617 {
5618 case LSM6DSM_TRG_XL_GY_DRDY:
5619 *val = LSM6DSM_TRG_XL_GY_DRDY;
5620 break;
5621
5622 case LSM6DSM_TRG_STEP_DETECT:
5623 *val = LSM6DSM_TRG_STEP_DETECT;
5624 break;
5625
5626 case LSM6DSM_TRG_SH_DRDY:
5627 *val = LSM6DSM_TRG_SH_DRDY;
5628 break;
5629
5630 default:
5631 *val = LSM6DSM_TRG_XL_GY_DRDY;
5632 break;
5633 }
5634 }
5635
5636 return ret;
5637 }
5638
5639 /**
5640 * @brief Enable pedometer step counter and timestamp as 4th
5641 * FIFO data set.[set]
5642 *
5643 * @param ctx Read / write interface definitions
5644 * @param val Change the values of timer_pedo_fifo_en in reg FIFO_CTRL2
5645 * @retval Interface status (MANDATORY: return 0 -> no Error).
5646 *
5647 */
lsm6dsm_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t * ctx,uint8_t val)5648 int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t *ctx,
5649 uint8_t val)
5650 {
5651 lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
5652 int32_t ret;
5653
5654 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
5655 (uint8_t *)&fifo_ctrl2, 1);
5656
5657 if (ret == 0)
5658 {
5659 fifo_ctrl2.timer_pedo_fifo_en = val;
5660 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL2,
5661 (uint8_t *)&fifo_ctrl2, 1);
5662 }
5663
5664 return ret;
5665 }
5666
5667 /**
5668 * @brief Enable pedometer step counter and timestamp as 4th
5669 * FIFO data set.[get]
5670 *
5671 * @param ctx Read / write interface definitions
5672 * @param val Change the values of timer_pedo_fifo_en in reg FIFO_CTRL2
5673 * @retval Interface status (MANDATORY: return 0 -> no Error).
5674 *
5675 */
lsm6dsm_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t * ctx,uint8_t * val)5676 int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t *ctx,
5677 uint8_t *val)
5678 {
5679 lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
5680 int32_t ret;
5681
5682 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
5683 (uint8_t *)&fifo_ctrl2, 1);
5684 *val = fifo_ctrl2.timer_pedo_fifo_en;
5685
5686 return ret;
5687 }
5688
5689 /**
5690 * @brief Selects Batching Data Rate (writing frequency in FIFO) for
5691 * accelerometer data.[set]
5692 *
5693 * @param ctx Read / write interface definitions
5694 * @param val Change the values of dec_fifo_xl in reg FIFO_CTRL3
5695 * @retval Interface status (MANDATORY: return 0 -> no Error).
5696 *
5697 */
lsm6dsm_fifo_xl_batch_set(stmdev_ctx_t * ctx,lsm6dsm_dec_fifo_xl_t val)5698 int32_t lsm6dsm_fifo_xl_batch_set(stmdev_ctx_t *ctx,
5699 lsm6dsm_dec_fifo_xl_t val)
5700 {
5701 lsm6dsm_fifo_ctrl3_t fifo_ctrl3;
5702 int32_t ret;
5703
5704 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL3,
5705 (uint8_t *)&fifo_ctrl3, 1);
5706
5707 if (ret == 0)
5708 {
5709 fifo_ctrl3.dec_fifo_xl = (uint8_t)val;
5710 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL3,
5711 (uint8_t *)&fifo_ctrl3, 1);
5712 }
5713
5714 return ret;
5715 }
5716
5717 /**
5718 * @brief Selects Batching Data Rate (writing frequency in FIFO) for
5719 * accelerometer data.[get]
5720 *
5721 * @param ctx Read / write interface definitions
5722 * @param val Get the values of dec_fifo_xl in reg FIFO_CTRL3
5723 * @retval Interface status (MANDATORY: return 0 -> no Error).
5724 *
5725 */
lsm6dsm_fifo_xl_batch_get(stmdev_ctx_t * ctx,lsm6dsm_dec_fifo_xl_t * val)5726 int32_t lsm6dsm_fifo_xl_batch_get(stmdev_ctx_t *ctx,
5727 lsm6dsm_dec_fifo_xl_t *val)
5728 {
5729 lsm6dsm_fifo_ctrl3_t fifo_ctrl3;
5730 int32_t ret;
5731
5732 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL3,
5733 (uint8_t *)&fifo_ctrl3, 1);
5734
5735 switch (fifo_ctrl3.dec_fifo_xl)
5736 {
5737 case LSM6DSM_FIFO_XL_DISABLE:
5738 *val = LSM6DSM_FIFO_XL_DISABLE;
5739 break;
5740
5741 case LSM6DSM_FIFO_XL_NO_DEC:
5742 *val = LSM6DSM_FIFO_XL_NO_DEC;
5743 break;
5744
5745 case LSM6DSM_FIFO_XL_DEC_2:
5746 *val = LSM6DSM_FIFO_XL_DEC_2;
5747 break;
5748
5749 case LSM6DSM_FIFO_XL_DEC_3:
5750 *val = LSM6DSM_FIFO_XL_DEC_3;
5751 break;
5752
5753 case LSM6DSM_FIFO_XL_DEC_4:
5754 *val = LSM6DSM_FIFO_XL_DEC_4;
5755 break;
5756
5757 case LSM6DSM_FIFO_XL_DEC_8:
5758 *val = LSM6DSM_FIFO_XL_DEC_8;
5759 break;
5760
5761 case LSM6DSM_FIFO_XL_DEC_16:
5762 *val = LSM6DSM_FIFO_XL_DEC_16;
5763 break;
5764
5765 case LSM6DSM_FIFO_XL_DEC_32:
5766 *val = LSM6DSM_FIFO_XL_DEC_32;
5767 break;
5768
5769 default:
5770 *val = LSM6DSM_FIFO_XL_DISABLE;
5771 break;
5772 }
5773
5774 return ret;
5775 }
5776
5777 /**
5778 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5779 * for gyroscope data.[set]
5780 *
5781 * @param ctx Read / write interface definitions
5782 * @param val Change the values of dec_fifo_gyro in reg FIFO_CTRL3
5783 * @retval Interface status (MANDATORY: return 0 -> no Error).
5784 *
5785 */
lsm6dsm_fifo_gy_batch_set(stmdev_ctx_t * ctx,lsm6dsm_dec_fifo_gyro_t val)5786 int32_t lsm6dsm_fifo_gy_batch_set(stmdev_ctx_t *ctx,
5787 lsm6dsm_dec_fifo_gyro_t val)
5788 {
5789 lsm6dsm_fifo_ctrl3_t fifo_ctrl3;
5790 int32_t ret;
5791
5792 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL3,
5793 (uint8_t *)&fifo_ctrl3, 1);
5794
5795 if (ret == 0)
5796 {
5797 fifo_ctrl3.dec_fifo_gyro = (uint8_t)val;
5798 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL3,
5799 (uint8_t *)&fifo_ctrl3, 1);
5800 }
5801
5802 return ret;
5803 }
5804
5805 /**
5806 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5807 * for gyroscope data.[get]
5808 *
5809 * @param ctx Read / write interface definitions
5810 * @param val Get the values of dec_fifo_gyro in reg FIFO_CTRL3
5811 * @retval Interface status (MANDATORY: return 0 -> no Error).
5812 *
5813 */
lsm6dsm_fifo_gy_batch_get(stmdev_ctx_t * ctx,lsm6dsm_dec_fifo_gyro_t * val)5814 int32_t lsm6dsm_fifo_gy_batch_get(stmdev_ctx_t *ctx,
5815 lsm6dsm_dec_fifo_gyro_t *val)
5816 {
5817 lsm6dsm_fifo_ctrl3_t fifo_ctrl3;
5818 int32_t ret;
5819
5820 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL3,
5821 (uint8_t *)&fifo_ctrl3, 1);
5822
5823 switch (fifo_ctrl3.dec_fifo_gyro)
5824 {
5825 case LSM6DSM_FIFO_GY_DISABLE:
5826 *val = LSM6DSM_FIFO_GY_DISABLE;
5827 break;
5828
5829 case LSM6DSM_FIFO_GY_NO_DEC:
5830 *val = LSM6DSM_FIFO_GY_NO_DEC;
5831 break;
5832
5833 case LSM6DSM_FIFO_GY_DEC_2:
5834 *val = LSM6DSM_FIFO_GY_DEC_2;
5835 break;
5836
5837 case LSM6DSM_FIFO_GY_DEC_3:
5838 *val = LSM6DSM_FIFO_GY_DEC_3;
5839 break;
5840
5841 case LSM6DSM_FIFO_GY_DEC_4:
5842 *val = LSM6DSM_FIFO_GY_DEC_4;
5843 break;
5844
5845 case LSM6DSM_FIFO_GY_DEC_8:
5846 *val = LSM6DSM_FIFO_GY_DEC_8;
5847 break;
5848
5849 case LSM6DSM_FIFO_GY_DEC_16:
5850 *val = LSM6DSM_FIFO_GY_DEC_16;
5851 break;
5852
5853 case LSM6DSM_FIFO_GY_DEC_32:
5854 *val = LSM6DSM_FIFO_GY_DEC_32;
5855 break;
5856
5857 default:
5858 *val = LSM6DSM_FIFO_GY_DISABLE;
5859 break;
5860 }
5861
5862 return ret;
5863 }
5864
5865 /**
5866 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5867 * for third data set.[set]
5868 *
5869 * @param ctx Read / write interface definitions
5870 * @param val Change the values of dec_ds3_fifo in reg FIFO_CTRL4
5871 * @retval Interface status (MANDATORY: return 0 -> no Error).
5872 *
5873 */
lsm6dsm_fifo_dataset_3_batch_set(stmdev_ctx_t * ctx,lsm6dsm_dec_ds3_fifo_t val)5874 int32_t lsm6dsm_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx,
5875 lsm6dsm_dec_ds3_fifo_t val)
5876 {
5877 lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
5878 int32_t ret;
5879
5880 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
5881 (uint8_t *)&fifo_ctrl4, 1);
5882
5883 if (ret == 0)
5884 {
5885 fifo_ctrl4.dec_ds3_fifo = (uint8_t)val;
5886 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL4,
5887 (uint8_t *)&fifo_ctrl4, 1);
5888 }
5889
5890 return ret;
5891 }
5892
5893 /**
5894 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5895 * for third data set.[get]
5896 *
5897 * @param ctx Read / write interface definitions
5898 * @param val Get the values of dec_ds3_fifo in reg FIFO_CTRL4
5899 * @retval Interface status (MANDATORY: return 0 -> no Error).
5900 *
5901 */
lsm6dsm_fifo_dataset_3_batch_get(stmdev_ctx_t * ctx,lsm6dsm_dec_ds3_fifo_t * val)5902 int32_t lsm6dsm_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx,
5903 lsm6dsm_dec_ds3_fifo_t *val)
5904 {
5905 lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
5906 int32_t ret;
5907
5908 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
5909 (uint8_t *)&fifo_ctrl4, 1);
5910
5911 switch (fifo_ctrl4.dec_ds3_fifo)
5912 {
5913 case LSM6DSM_FIFO_DS3_DISABLE:
5914 *val = LSM6DSM_FIFO_DS3_DISABLE;
5915 break;
5916
5917 case LSM6DSM_FIFO_DS3_NO_DEC:
5918 *val = LSM6DSM_FIFO_DS3_NO_DEC;
5919 break;
5920
5921 case LSM6DSM_FIFO_DS3_DEC_2:
5922 *val = LSM6DSM_FIFO_DS3_DEC_2;
5923 break;
5924
5925 case LSM6DSM_FIFO_DS3_DEC_3:
5926 *val = LSM6DSM_FIFO_DS3_DEC_3;
5927 break;
5928
5929 case LSM6DSM_FIFO_DS3_DEC_4:
5930 *val = LSM6DSM_FIFO_DS3_DEC_4;
5931 break;
5932
5933 case LSM6DSM_FIFO_DS3_DEC_8:
5934 *val = LSM6DSM_FIFO_DS3_DEC_8;
5935 break;
5936
5937 case LSM6DSM_FIFO_DS3_DEC_16:
5938 *val = LSM6DSM_FIFO_DS3_DEC_16;
5939 break;
5940
5941 case LSM6DSM_FIFO_DS3_DEC_32:
5942 *val = LSM6DSM_FIFO_DS3_DEC_32;
5943 break;
5944
5945 default:
5946 *val = LSM6DSM_FIFO_DS3_DISABLE;
5947 break;
5948 }
5949
5950 return ret;
5951 }
5952
5953 /**
5954 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5955 * for fourth data set.[set]
5956 *
5957 * @param ctx Read / write interface definitions
5958 * @param val Change the values of dec_ds4_fifo in reg FIFO_CTRL4
5959 * @retval Interface status (MANDATORY: return 0 -> no Error).
5960 *
5961 */
lsm6dsm_fifo_dataset_4_batch_set(stmdev_ctx_t * ctx,lsm6dsm_dec_ds4_fifo_t val)5962 int32_t lsm6dsm_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx,
5963 lsm6dsm_dec_ds4_fifo_t val)
5964 {
5965 lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
5966 int32_t ret;
5967
5968 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
5969 (uint8_t *)&fifo_ctrl4, 1);
5970
5971 if (ret == 0)
5972 {
5973 fifo_ctrl4.dec_ds4_fifo = (uint8_t)val;
5974 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL4,
5975 (uint8_t *)&fifo_ctrl4, 1);
5976 }
5977
5978 return ret;
5979 }
5980
5981 /**
5982 * @brief Selects Batching Data Rate (writing frequency in FIFO) for
5983 * fourth data set.[get]
5984 *
5985 * @param ctx Read / write interface definitions
5986 * @param val Get the values of dec_ds4_fifo in reg FIFO_CTRL4
5987 * @retval Interface status (MANDATORY: return 0 -> no Error).
5988 *
5989 */
lsm6dsm_fifo_dataset_4_batch_get(stmdev_ctx_t * ctx,lsm6dsm_dec_ds4_fifo_t * val)5990 int32_t lsm6dsm_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx,
5991 lsm6dsm_dec_ds4_fifo_t *val)
5992 {
5993 lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
5994 int32_t ret;
5995
5996 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
5997 (uint8_t *)&fifo_ctrl4, 1);
5998
5999 switch (fifo_ctrl4.dec_ds4_fifo)
6000 {
6001 case LSM6DSM_FIFO_DS4_DISABLE:
6002 *val = LSM6DSM_FIFO_DS4_DISABLE;
6003 break;
6004
6005 case LSM6DSM_FIFO_DS4_NO_DEC:
6006 *val = LSM6DSM_FIFO_DS4_NO_DEC;
6007 break;
6008
6009 case LSM6DSM_FIFO_DS4_DEC_2:
6010 *val = LSM6DSM_FIFO_DS4_DEC_2;
6011 break;
6012
6013 case LSM6DSM_FIFO_DS4_DEC_3:
6014 *val = LSM6DSM_FIFO_DS4_DEC_3;
6015 break;
6016
6017 case LSM6DSM_FIFO_DS4_DEC_4:
6018 *val = LSM6DSM_FIFO_DS4_DEC_4;
6019 break;
6020
6021 case LSM6DSM_FIFO_DS4_DEC_8:
6022 *val = LSM6DSM_FIFO_DS4_DEC_8;
6023 break;
6024
6025 case LSM6DSM_FIFO_DS4_DEC_16:
6026 *val = LSM6DSM_FIFO_DS4_DEC_16;
6027 break;
6028
6029 case LSM6DSM_FIFO_DS4_DEC_32:
6030 *val = LSM6DSM_FIFO_DS4_DEC_32;
6031 break;
6032
6033 default:
6034 *val = LSM6DSM_FIFO_DS4_DISABLE;
6035 break;
6036 }
6037
6038 return ret;
6039 }
6040
6041 /**
6042 * @brief 8-bit data storage in FIFO.[set]
6043 *
6044 * @param ctx Read / write interface definitions
6045 * @param val Change the values of only_high_data in reg FIFO_CTRL4
6046 * @retval Interface status (MANDATORY: return 0 -> no Error).
6047 *
6048 */
lsm6dsm_fifo_xl_gy_8bit_format_set(stmdev_ctx_t * ctx,uint8_t val)6049 int32_t lsm6dsm_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx,
6050 uint8_t val)
6051 {
6052 lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
6053 int32_t ret;
6054
6055 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
6056 (uint8_t *)&fifo_ctrl4, 1);
6057
6058 if (ret == 0)
6059 {
6060 fifo_ctrl4.only_high_data = val;
6061 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL4,
6062 (uint8_t *)&fifo_ctrl4, 1);
6063 }
6064
6065 return ret;
6066 }
6067
6068 /**
6069 * @brief 8-bit data storage in FIFO.[get]
6070 *
6071 * @param ctx Read / write interface definitions
6072 * @param val Change the values of only_high_data in reg FIFO_CTRL4
6073 * @retval Interface status (MANDATORY: return 0 -> no Error).
6074 *
6075 */
lsm6dsm_fifo_xl_gy_8bit_format_get(stmdev_ctx_t * ctx,uint8_t * val)6076 int32_t lsm6dsm_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx,
6077 uint8_t *val)
6078 {
6079 lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
6080 int32_t ret;
6081
6082 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
6083 (uint8_t *)&fifo_ctrl4, 1);
6084 *val = fifo_ctrl4.only_high_data;
6085
6086 return ret;
6087 }
6088
6089 /**
6090 * @brief Sensing chain FIFO stop values memorization at threshold
6091 * level.[set]
6092 *
6093 * @param ctx Read / write interface definitions
6094 * @param val Change the values of stop_on_fth in reg FIFO_CTRL4
6095 * @retval Interface status (MANDATORY: return 0 -> no Error).
6096 *
6097 */
lsm6dsm_fifo_stop_on_wtm_set(stmdev_ctx_t * ctx,uint8_t val)6098 int32_t lsm6dsm_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
6099 {
6100 lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
6101 int32_t ret;
6102
6103 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
6104 (uint8_t *)&fifo_ctrl4, 1);
6105
6106 if (ret == 0)
6107 {
6108 fifo_ctrl4.stop_on_fth = val;
6109 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL4,
6110 (uint8_t *)&fifo_ctrl4, 1);
6111 }
6112
6113 return ret;
6114 }
6115
6116 /**
6117 * @brief Sensing chain FIFO stop values memorization at threshold
6118 * level.[get]
6119 *
6120 * @param ctx Read / write interface definitions
6121 * @param val Change the values of stop_on_fth in reg FIFO_CTRL4
6122 * @retval Interface status (MANDATORY: return 0 -> no Error).
6123 *
6124 */
lsm6dsm_fifo_stop_on_wtm_get(stmdev_ctx_t * ctx,uint8_t * val)6125 int32_t lsm6dsm_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
6126 {
6127 lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
6128 int32_t ret;
6129
6130 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
6131 (uint8_t *)&fifo_ctrl4, 1);
6132 *val = fifo_ctrl4.stop_on_fth;
6133
6134 return ret;
6135 }
6136
6137 /**
6138 * @brief FIFO mode selection.[set]
6139 *
6140 * @param ctx Read / write interface definitions
6141 * @param val Change the values of fifo_mode in reg FIFO_CTRL5
6142 * @retval Interface status (MANDATORY: return 0 -> no Error).
6143 *
6144 */
lsm6dsm_fifo_mode_set(stmdev_ctx_t * ctx,lsm6dsm_fifo_mode_t val)6145 int32_t lsm6dsm_fifo_mode_set(stmdev_ctx_t *ctx,
6146 lsm6dsm_fifo_mode_t val)
6147 {
6148 lsm6dsm_fifo_ctrl5_t fifo_ctrl5;
6149 int32_t ret;
6150
6151 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL5,
6152 (uint8_t *)&fifo_ctrl5, 1);
6153
6154 if (ret == 0)
6155 {
6156 fifo_ctrl5.fifo_mode = (uint8_t)val;
6157 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL5,
6158 (uint8_t *)&fifo_ctrl5, 1);
6159 }
6160
6161 return ret;
6162 }
6163
6164 /**
6165 * @brief FIFO mode selection.[get]
6166 *
6167 * @param ctx Read / write interface definitions
6168 * @param val Get the values of fifo_mode in reg FIFO_CTRL5
6169 * @retval Interface status (MANDATORY: return 0 -> no Error).
6170 *
6171 */
lsm6dsm_fifo_mode_get(stmdev_ctx_t * ctx,lsm6dsm_fifo_mode_t * val)6172 int32_t lsm6dsm_fifo_mode_get(stmdev_ctx_t *ctx,
6173 lsm6dsm_fifo_mode_t *val)
6174 {
6175 lsm6dsm_fifo_ctrl5_t fifo_ctrl5;
6176 int32_t ret;
6177
6178 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL5,
6179 (uint8_t *)&fifo_ctrl5, 1);
6180
6181 switch (fifo_ctrl5.fifo_mode)
6182 {
6183 case LSM6DSM_BYPASS_MODE:
6184 *val = LSM6DSM_BYPASS_MODE;
6185 break;
6186
6187 case LSM6DSM_FIFO_MODE:
6188 *val = LSM6DSM_FIFO_MODE;
6189 break;
6190
6191 case LSM6DSM_STREAM_TO_FIFO_MODE:
6192 *val = LSM6DSM_STREAM_TO_FIFO_MODE;
6193 break;
6194
6195 case LSM6DSM_BYPASS_TO_STREAM_MODE:
6196 *val = LSM6DSM_BYPASS_TO_STREAM_MODE;
6197 break;
6198
6199 case LSM6DSM_STREAM_MODE:
6200 *val = LSM6DSM_STREAM_MODE;
6201 break;
6202
6203 default:
6204 *val = LSM6DSM_BYPASS_MODE;
6205 break;
6206 }
6207
6208 return ret;
6209 }
6210
6211 /**
6212 * @brief FIFO ODR selection, setting FIFO_MODE also.[set]
6213 *
6214 * @param ctx Read / write interface definitions
6215 * @param val Change the values of odr_fifo in reg FIFO_CTRL5
6216 * @retval Interface status (MANDATORY: return 0 -> no Error).
6217 *
6218 */
lsm6dsm_fifo_data_rate_set(stmdev_ctx_t * ctx,lsm6dsm_odr_fifo_t val)6219 int32_t lsm6dsm_fifo_data_rate_set(stmdev_ctx_t *ctx,
6220 lsm6dsm_odr_fifo_t val)
6221 {
6222 lsm6dsm_fifo_ctrl5_t fifo_ctrl5;
6223 int32_t ret;
6224
6225 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL5,
6226 (uint8_t *)&fifo_ctrl5, 1);
6227
6228 if (ret == 0)
6229 {
6230 fifo_ctrl5.odr_fifo = (uint8_t)val;
6231 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL5,
6232 (uint8_t *)&fifo_ctrl5, 1);
6233 }
6234
6235 return ret;
6236 }
6237
6238 /**
6239 * @brief FIFO ODR selection, setting FIFO_MODE also.[get]
6240 *
6241 * @param ctx Read / write interface definitions
6242 * @param val Get the values of odr_fifo in reg FIFO_CTRL5
6243 * @retval Interface status (MANDATORY: return 0 -> no Error).
6244 *
6245 */
lsm6dsm_fifo_data_rate_get(stmdev_ctx_t * ctx,lsm6dsm_odr_fifo_t * val)6246 int32_t lsm6dsm_fifo_data_rate_get(stmdev_ctx_t *ctx,
6247 lsm6dsm_odr_fifo_t *val)
6248 {
6249 lsm6dsm_fifo_ctrl5_t fifo_ctrl5;
6250 int32_t ret;
6251
6252 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL5,
6253 (uint8_t *)&fifo_ctrl5, 1);
6254
6255 switch (fifo_ctrl5.odr_fifo)
6256 {
6257 case LSM6DSM_FIFO_DISABLE:
6258 *val = LSM6DSM_FIFO_DISABLE;
6259 break;
6260
6261 case LSM6DSM_FIFO_12Hz5:
6262 *val = LSM6DSM_FIFO_12Hz5;
6263 break;
6264
6265 case LSM6DSM_FIFO_26Hz:
6266 *val = LSM6DSM_FIFO_26Hz;
6267 break;
6268
6269 case LSM6DSM_FIFO_52Hz:
6270 *val = LSM6DSM_FIFO_52Hz;
6271 break;
6272
6273 case LSM6DSM_FIFO_104Hz:
6274 *val = LSM6DSM_FIFO_104Hz;
6275 break;
6276
6277 case LSM6DSM_FIFO_208Hz:
6278 *val = LSM6DSM_FIFO_208Hz;
6279 break;
6280
6281 case LSM6DSM_FIFO_416Hz:
6282 *val = LSM6DSM_FIFO_416Hz;
6283 break;
6284
6285 case LSM6DSM_FIFO_833Hz:
6286 *val = LSM6DSM_FIFO_833Hz;
6287 break;
6288
6289 case LSM6DSM_FIFO_1k66Hz:
6290 *val = LSM6DSM_FIFO_1k66Hz;
6291 break;
6292
6293 case LSM6DSM_FIFO_3k33Hz:
6294 *val = LSM6DSM_FIFO_3k33Hz;
6295 break;
6296
6297 case LSM6DSM_FIFO_6k66Hz:
6298 *val = LSM6DSM_FIFO_6k66Hz;
6299 break;
6300
6301 default:
6302 *val = LSM6DSM_FIFO_DISABLE;
6303 break;
6304 }
6305
6306 return ret;
6307 }
6308
6309 /**
6310 * @}
6311 *
6312 */
6313
6314 /**
6315 * @defgroup LSM6DSM_DEN_functionality
6316 * @brief This section groups all the functions concerning DEN
6317 * functionality.
6318 * @{
6319 *
6320 */
6321
6322 /**
6323 * @brief DEN active level configuration.[set]
6324 *
6325 * @param ctx Read / write interface definitions
6326 * @param val Change the values of den_lh in reg CTRL5_C
6327 * @retval Interface status (MANDATORY: return 0 -> no Error).
6328 *
6329 */
lsm6dsm_den_polarity_set(stmdev_ctx_t * ctx,lsm6dsm_den_lh_t val)6330 int32_t lsm6dsm_den_polarity_set(stmdev_ctx_t *ctx,
6331 lsm6dsm_den_lh_t val)
6332 {
6333 lsm6dsm_ctrl5_c_t ctrl5_c;
6334 int32_t ret;
6335
6336 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
6337
6338 if (ret == 0)
6339 {
6340 ctrl5_c.den_lh = (uint8_t)val;
6341 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
6342 }
6343
6344 return ret;
6345 }
6346
6347 /**
6348 * @brief DEN active level configuration.[get]
6349 *
6350 * @param ctx Read / write interface definitions
6351 * @param val Get the values of den_lh in reg CTRL5_C
6352 * @retval Interface status (MANDATORY: return 0 -> no Error).
6353 *
6354 */
lsm6dsm_den_polarity_get(stmdev_ctx_t * ctx,lsm6dsm_den_lh_t * val)6355 int32_t lsm6dsm_den_polarity_get(stmdev_ctx_t *ctx,
6356 lsm6dsm_den_lh_t *val)
6357 {
6358 lsm6dsm_ctrl5_c_t ctrl5_c;
6359 int32_t ret;
6360
6361 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
6362
6363 switch (ctrl5_c.den_lh)
6364 {
6365 case LSM6DSM_DEN_ACT_LOW:
6366 *val = LSM6DSM_DEN_ACT_LOW;
6367 break;
6368
6369 case LSM6DSM_DEN_ACT_HIGH:
6370 *val = LSM6DSM_DEN_ACT_HIGH;
6371 break;
6372
6373 default:
6374 *val = LSM6DSM_DEN_ACT_LOW;
6375 break;
6376 }
6377
6378 return ret;
6379 }
6380
6381 /**
6382 * @brief DEN functionality marking mode[set]
6383 *
6384 * @param ctx Read / write interface definitions
6385 * @param val Change the values of den_mode in reg CTRL6_C
6386 * @retval Interface status (MANDATORY: return 0 -> no Error).
6387 *
6388 */
lsm6dsm_den_mode_set(stmdev_ctx_t * ctx,lsm6dsm_den_mode_t val)6389 int32_t lsm6dsm_den_mode_set(stmdev_ctx_t *ctx,
6390 lsm6dsm_den_mode_t val)
6391 {
6392 lsm6dsm_ctrl6_c_t ctrl6_c;
6393 int32_t ret;
6394
6395 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
6396
6397 if (ret == 0)
6398 {
6399 ctrl6_c.den_mode = (uint8_t)val;
6400 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
6401 }
6402
6403 return ret;
6404 }
6405
6406 /**
6407 * @brief DEN functionality marking mode[get]
6408 *
6409 * @param ctx Read / write interface definitions
6410 * @param val Change the values of den_mode in reg CTRL6_C
6411 * @retval Interface status (MANDATORY: return 0 -> no Error).
6412 *
6413 */
lsm6dsm_den_mode_get(stmdev_ctx_t * ctx,lsm6dsm_den_mode_t * val)6414 int32_t lsm6dsm_den_mode_get(stmdev_ctx_t *ctx,
6415 lsm6dsm_den_mode_t *val)
6416 {
6417 lsm6dsm_ctrl6_c_t ctrl6_c;
6418 int32_t ret;
6419
6420 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
6421
6422 switch (ctrl6_c.den_mode)
6423 {
6424 case LSM6DSM_DEN_DISABLE:
6425 *val = LSM6DSM_DEN_DISABLE;
6426 break;
6427
6428 case LSM6DSM_LEVEL_LETCHED:
6429 *val = LSM6DSM_LEVEL_LETCHED;
6430 break;
6431
6432 case LSM6DSM_LEVEL_TRIGGER:
6433 *val = LSM6DSM_LEVEL_TRIGGER;
6434 break;
6435
6436 case LSM6DSM_EDGE_TRIGGER:
6437 *val = LSM6DSM_EDGE_TRIGGER;
6438 break;
6439
6440 default:
6441 *val = LSM6DSM_DEN_DISABLE;
6442 break;
6443 }
6444
6445 return ret;
6446 }
6447
6448 /**
6449 * @brief Extend DEN functionality to accelerometer sensor.[set]
6450 *
6451 * @param ctx Read / write interface definitions
6452 * @param val Change the values of den_xl_g in reg CTRL9_XL
6453 * and den_xl_en in CTRL4_C.
6454 * @retval Interface status (MANDATORY: return 0 -> no Error).
6455 *
6456 */
lsm6dsm_den_enable_set(stmdev_ctx_t * ctx,lsm6dsm_den_xl_en_t val)6457 int32_t lsm6dsm_den_enable_set(stmdev_ctx_t *ctx,
6458 lsm6dsm_den_xl_en_t val)
6459 {
6460 lsm6dsm_ctrl4_c_t ctrl4_c;
6461 lsm6dsm_ctrl9_xl_t ctrl9_xl;
6462 int32_t ret;
6463
6464 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6465
6466 if (ret == 0)
6467 {
6468 ctrl9_xl.den_xl_g = (uint8_t)val & 0x01U;
6469 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6470
6471 if (ret == 0)
6472 {
6473 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
6474
6475 if (ret == 0)
6476 {
6477 ctrl4_c.den_xl_en = (uint8_t)val & 0x02U;
6478 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
6479 }
6480 }
6481 }
6482
6483 return ret;
6484 }
6485
6486 /**
6487 * @brief Extend DEN functionality to accelerometer sensor. [get]
6488 *
6489 * @param ctx Read / write interface definitions
6490 * @param val Get the values of den_xl_g in reg CTRL9_XL
6491 * and den_xl_en in CTRL4_C.
6492 * @retval Interface status (MANDATORY: return 0 -> no Error).
6493 *
6494 */
lsm6dsm_den_enable_get(stmdev_ctx_t * ctx,lsm6dsm_den_xl_en_t * val)6495 int32_t lsm6dsm_den_enable_get(stmdev_ctx_t *ctx,
6496 lsm6dsm_den_xl_en_t *val)
6497 {
6498 lsm6dsm_ctrl4_c_t ctrl4_c;
6499 lsm6dsm_ctrl9_xl_t ctrl9_xl;
6500 int32_t ret;
6501
6502 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
6503
6504 if (ret == 0)
6505 {
6506 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6507
6508 switch ((ctrl4_c.den_xl_en << 1) + ctrl9_xl.den_xl_g)
6509 {
6510 case LSM6DSM_STAMP_IN_GY_DATA:
6511 *val = LSM6DSM_STAMP_IN_GY_DATA;
6512 break;
6513
6514 case LSM6DSM_STAMP_IN_XL_DATA:
6515 *val = LSM6DSM_STAMP_IN_XL_DATA;
6516 break;
6517
6518 case LSM6DSM_STAMP_IN_GY_XL_DATA:
6519 *val = LSM6DSM_STAMP_IN_GY_XL_DATA;
6520 break;
6521
6522 default:
6523 *val = LSM6DSM_STAMP_IN_GY_DATA;
6524 break;
6525 }
6526 }
6527
6528 return ret;
6529 }
6530
6531 /**
6532 * @brief DEN value stored in LSB of Z-axis.[set]
6533 *
6534 * @param ctx Read / write interface definitions
6535 * @param val Change the values of den_z in reg CTRL9_XL
6536 * @retval Interface status (MANDATORY: return 0 -> no Error).
6537 *
6538 */
lsm6dsm_den_mark_axis_z_set(stmdev_ctx_t * ctx,uint8_t val)6539 int32_t lsm6dsm_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
6540 {
6541 lsm6dsm_ctrl9_xl_t ctrl9_xl;
6542 int32_t ret;
6543
6544 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6545
6546 if (ret == 0)
6547 {
6548 ctrl9_xl.den_z = val;
6549 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6550 }
6551
6552 return ret;
6553 }
6554
6555 /**
6556 * @brief DEN value stored in LSB of Z-axis.[get]
6557 *
6558 * @param ctx Read / write interface definitions
6559 * @param val Change the values of den_z in reg CTRL9_XL
6560 * @retval Interface status (MANDATORY: return 0 -> no Error).
6561 *
6562 */
lsm6dsm_den_mark_axis_z_get(stmdev_ctx_t * ctx,uint8_t * val)6563 int32_t lsm6dsm_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
6564 {
6565 lsm6dsm_ctrl9_xl_t ctrl9_xl;
6566 int32_t ret;
6567
6568 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6569 *val = ctrl9_xl.den_z;
6570
6571 return ret;
6572 }
6573
6574 /**
6575 * @brief DEN value stored in LSB of Y-axis.[set]
6576 *
6577 * @param ctx Read / write interface definitions
6578 * @param val Change the values of den_y in reg CTRL9_XL
6579 * @retval Interface status (MANDATORY: return 0 -> no Error).
6580 *
6581 */
lsm6dsm_den_mark_axis_y_set(stmdev_ctx_t * ctx,uint8_t val)6582 int32_t lsm6dsm_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
6583 {
6584 lsm6dsm_ctrl9_xl_t ctrl9_xl;
6585 int32_t ret;
6586
6587 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6588
6589 if (ret == 0)
6590 {
6591 ctrl9_xl.den_y = val;
6592 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6593 }
6594
6595 return ret;
6596 }
6597
6598 /**
6599 * @brief DEN value stored in LSB of Y-axis.[get]
6600 *
6601 * @param ctx Read / write interface definitions
6602 * @param val Change the values of den_y in reg CTRL9_XL
6603 * @retval Interface status (MANDATORY: return 0 -> no Error).
6604 *
6605 */
lsm6dsm_den_mark_axis_y_get(stmdev_ctx_t * ctx,uint8_t * val)6606 int32_t lsm6dsm_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
6607 {
6608 lsm6dsm_ctrl9_xl_t ctrl9_xl;
6609 int32_t ret;
6610
6611 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6612 *val = ctrl9_xl.den_y;
6613
6614 return ret;
6615 }
6616
6617 /**
6618 * @brief DEN value stored in LSB of X-axis.[set]
6619 *
6620 * @param ctx Read / write interface definitions
6621 * @param val Change the values of den_x in reg CTRL9_XL
6622 * @retval Interface status (MANDATORY: return 0 -> no Error).
6623 *
6624 */
lsm6dsm_den_mark_axis_x_set(stmdev_ctx_t * ctx,uint8_t val)6625 int32_t lsm6dsm_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
6626 {
6627 lsm6dsm_ctrl9_xl_t ctrl9_xl;
6628 int32_t ret;
6629
6630 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6631
6632 if (ret == 0)
6633 {
6634 ctrl9_xl.den_x = val;
6635 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6636 }
6637
6638 return ret;
6639 }
6640
6641 /**
6642 * @brief DEN value stored in LSB of X-axis.[get]
6643 *
6644 * @param ctx Read / write interface definitions
6645 * @param val Change the values of den_x in reg CTRL9_XL
6646 * @retval Interface status (MANDATORY: return 0 -> no Error).
6647 *
6648 */
lsm6dsm_den_mark_axis_x_get(stmdev_ctx_t * ctx,uint8_t * val)6649 int32_t lsm6dsm_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
6650 {
6651 lsm6dsm_ctrl9_xl_t ctrl9_xl;
6652 int32_t ret;
6653
6654 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6655 *val = ctrl9_xl.den_x;
6656
6657 return ret;
6658 }
6659
6660 /**
6661 * @}
6662 *
6663 */
6664
6665 /**
6666 * @defgroup LSM6DSM_Pedometer
6667 * @brief This section groups all the functions that manage pedometer.
6668 * @{
6669 *
6670 */
6671
6672 /**
6673 * @brief Reset pedometer step counter.[set]
6674 *
6675 * @param ctx Read / write interface definitions
6676 * @param val Change the values of pedo_rst_step in reg CTRL10_C
6677 * @retval Interface status (MANDATORY: return 0 -> no Error).
6678 *
6679 */
lsm6dsm_pedo_step_reset_set(stmdev_ctx_t * ctx,uint8_t val)6680 int32_t lsm6dsm_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val)
6681 {
6682 lsm6dsm_ctrl10_c_t ctrl10_c;
6683 int32_t ret;
6684
6685 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6686
6687 if (ret == 0)
6688 {
6689 ctrl10_c.pedo_rst_step = val;
6690 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6691 }
6692
6693 return ret;
6694 }
6695
6696 /**
6697 * @brief Reset pedometer step counter.[get]
6698 *
6699 * @param ctx Read / write interface definitions
6700 * @param val Change the values of pedo_rst_step in reg CTRL10_C
6701 * @retval Interface status (MANDATORY: return 0 -> no Error).
6702 *
6703 */
lsm6dsm_pedo_step_reset_get(stmdev_ctx_t * ctx,uint8_t * val)6704 int32_t lsm6dsm_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
6705 {
6706 lsm6dsm_ctrl10_c_t ctrl10_c;
6707 int32_t ret;
6708
6709 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6710 *val = ctrl10_c.pedo_rst_step;
6711
6712 return ret;
6713 }
6714
6715 /**
6716 * @brief Enable pedometer algorithm.[set]
6717 *
6718 * @param ctx Read / write interface definitions
6719 * @param val Change the values of pedo_en in reg CTRL10_C
6720 * @retval Interface status (MANDATORY: return 0 -> no Error).
6721 *
6722 */
lsm6dsm_pedo_sens_set(stmdev_ctx_t * ctx,uint8_t val)6723 int32_t lsm6dsm_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val)
6724 {
6725 lsm6dsm_ctrl10_c_t ctrl10_c;
6726 int32_t ret;
6727
6728 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6729
6730 if (ret == 0)
6731 {
6732 ctrl10_c.pedo_en = val;
6733
6734 if (val != 0x00U)
6735 {
6736 ctrl10_c.func_en = val;
6737 }
6738
6739 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6740 }
6741
6742 return ret;
6743 }
6744
6745 /**
6746 * @brief pedo_sens: Enable pedometer algorithm.[get]
6747 *
6748 * @param ctx Read / write interface definitions
6749 * @param val Change the values of pedo_en in reg CTRL10_C
6750 * @retval Interface status (MANDATORY: return 0 -> no Error).
6751 *
6752 */
lsm6dsm_pedo_sens_get(stmdev_ctx_t * ctx,uint8_t * val)6753 int32_t lsm6dsm_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
6754 {
6755 lsm6dsm_ctrl10_c_t ctrl10_c;
6756 int32_t ret;
6757
6758 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6759 *val = ctrl10_c.pedo_en;
6760
6761 return ret;
6762 }
6763
6764 /**
6765 * @brief Minimum threshold to detect a peak. Default is 10h.[set]
6766 *
6767 * @param ctx Read / write interface definitions
6768 * @param val Change the values of ths_min in reg
6769 * CONFIG_PEDO_THS_MIN
6770 * @retval Interface status (MANDATORY: return 0 -> no Error).
6771 *
6772 */
lsm6dsm_pedo_threshold_set(stmdev_ctx_t * ctx,uint8_t val)6773 int32_t lsm6dsm_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
6774 {
6775 lsm6dsm_config_pedo_ths_min_t config_pedo_ths_min;
6776 int32_t ret;
6777
6778 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
6779
6780 if (ret == 0)
6781 {
6782 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN,
6783 (uint8_t *)&config_pedo_ths_min, 1);
6784
6785 if (ret == 0)
6786 {
6787 config_pedo_ths_min.ths_min = val;
6788 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN,
6789 (uint8_t *)&config_pedo_ths_min, 1);
6790
6791 if (ret == 0)
6792 {
6793 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
6794 }
6795 }
6796 }
6797
6798 return ret;
6799 }
6800
6801 /**
6802 * @brief Minimum threshold to detect a peak. Default is 10h.[get]
6803 *
6804 * @param ctx Read / write interface definitions
6805 * @param val Change the values of ths_min in reg CONFIG_PEDO_THS_MIN
6806 * @retval Interface status (MANDATORY: return 0 -> no Error).
6807 *
6808 */
lsm6dsm_pedo_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)6809 int32_t lsm6dsm_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
6810 {
6811 lsm6dsm_config_pedo_ths_min_t config_pedo_ths_min;
6812 int32_t ret;
6813
6814 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
6815
6816 if (ret == 0)
6817 {
6818 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN,
6819 (uint8_t *)&config_pedo_ths_min, 1);
6820
6821 if (ret == 0)
6822 {
6823 *val = config_pedo_ths_min.ths_min;
6824 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
6825 }
6826 }
6827
6828 return ret;
6829 }
6830
6831 /**
6832 * @brief pedo_full_scale: Pedometer data range.[set]
6833 *
6834 * @param ctx Read / write interface definitions
6835 * @param val Change the values of pedo_fs in
6836 * reg CONFIG_PEDO_THS_MIN
6837 * @retval Interface status (MANDATORY: return 0 -> no Error).
6838 *
6839 */
lsm6dsm_pedo_full_scale_set(stmdev_ctx_t * ctx,lsm6dsm_pedo_fs_t val)6840 int32_t lsm6dsm_pedo_full_scale_set(stmdev_ctx_t *ctx,
6841 lsm6dsm_pedo_fs_t val)
6842 {
6843 lsm6dsm_config_pedo_ths_min_t config_pedo_ths_min;
6844 int32_t ret;
6845
6846 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
6847
6848 if (ret == 0)
6849 {
6850 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN,
6851 (uint8_t *)&config_pedo_ths_min, 1);
6852
6853 if (ret == 0)
6854 {
6855 config_pedo_ths_min.pedo_fs = (uint8_t) val;
6856 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN,
6857 (uint8_t *)&config_pedo_ths_min, 1);
6858
6859 if (ret == 0)
6860 {
6861 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
6862 }
6863 }
6864 }
6865
6866 return ret;
6867 }
6868
6869 /**
6870 * @brief Pedometer data range.[get]
6871 *
6872 * @param ctx Read / write interface definitions
6873 * @param val Get the values of pedo_fs in
6874 * reg CONFIG_PEDO_THS_MIN
6875 * @retval Interface status (MANDATORY: return 0 -> no Error).
6876 *
6877 */
lsm6dsm_pedo_full_scale_get(stmdev_ctx_t * ctx,lsm6dsm_pedo_fs_t * val)6878 int32_t lsm6dsm_pedo_full_scale_get(stmdev_ctx_t *ctx,
6879 lsm6dsm_pedo_fs_t *val)
6880 {
6881 lsm6dsm_config_pedo_ths_min_t config_pedo_ths_min;
6882 int32_t ret;
6883
6884 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
6885
6886 if (ret == 0)
6887 {
6888 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN,
6889 (uint8_t *)&config_pedo_ths_min, 1);
6890
6891 if (ret == 0)
6892 {
6893 switch (config_pedo_ths_min.pedo_fs)
6894 {
6895 case LSM6DSM_PEDO_AT_2g:
6896 *val = LSM6DSM_PEDO_AT_2g;
6897 break;
6898
6899 case LSM6DSM_PEDO_AT_4g:
6900 *val = LSM6DSM_PEDO_AT_4g;
6901 break;
6902
6903 default:
6904 *val = LSM6DSM_PEDO_AT_2g;
6905 break;
6906 }
6907
6908 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
6909 }
6910 }
6911
6912 return ret;
6913 }
6914
6915 /**
6916 * @brief Pedometer debounce configuration register (r/w).[set]
6917 *
6918 * @param ctx Read / write interface definitions
6919 * @param val Change the values of deb_step in reg PEDO_DEB_REG
6920 * @retval Interface status (MANDATORY: return 0 -> no Error).
6921 *
6922 */
lsm6dsm_pedo_debounce_steps_set(stmdev_ctx_t * ctx,uint8_t val)6923 int32_t lsm6dsm_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
6924 uint8_t val)
6925 {
6926 lsm6dsm_pedo_deb_reg_t pedo_deb_reg;
6927 int32_t ret;
6928
6929 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
6930
6931 if (ret == 0)
6932 {
6933 ret = lsm6dsm_read_reg(ctx, LSM6DSM_PEDO_DEB_REG,
6934 (uint8_t *)&pedo_deb_reg, 1);
6935
6936 if (ret == 0)
6937 {
6938 pedo_deb_reg.deb_step = val;
6939 ret = lsm6dsm_write_reg(ctx, LSM6DSM_PEDO_DEB_REG,
6940 (uint8_t *)&pedo_deb_reg, 1);
6941
6942 if (ret == 0)
6943 {
6944 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
6945 }
6946 }
6947 }
6948
6949 return ret;
6950 }
6951
6952 /**
6953 * @brief Pedometer debounce configuration register (r/w).[get]
6954 *
6955 * @param ctx Read / write interface definitions
6956 * @param val Change the values of deb_step in reg PEDO_DEB_REG
6957 * @retval Interface status (MANDATORY: return 0 -> no Error).
6958 *
6959 */
lsm6dsm_pedo_debounce_steps_get(stmdev_ctx_t * ctx,uint8_t * val)6960 int32_t lsm6dsm_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
6961 uint8_t *val)
6962 {
6963 lsm6dsm_pedo_deb_reg_t pedo_deb_reg;
6964 int32_t ret;
6965
6966 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
6967
6968 if (ret == 0)
6969 {
6970 ret = lsm6dsm_read_reg(ctx, LSM6DSM_PEDO_DEB_REG,
6971 (uint8_t *)&pedo_deb_reg, 1);
6972
6973 if (ret == 0)
6974 {
6975 *val = pedo_deb_reg.deb_step;
6976 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
6977 }
6978 }
6979
6980 return ret;
6981 }
6982
6983 /**
6984 * @brief Debounce time. If the time between two consecutive steps is
6985 * greater than DEB_TIME*80ms, the debouncer is reactivated.
6986 * Default value: 01101[set]
6987 *
6988 * @param ctx Read / write interface definitions
6989 * @param val Change the values of deb_time in reg PEDO_DEB_REG
6990 * @retval Interface status (MANDATORY: return 0 -> no Error).
6991 *
6992 */
lsm6dsm_pedo_timeout_set(stmdev_ctx_t * ctx,uint8_t val)6993 int32_t lsm6dsm_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
6994 {
6995 lsm6dsm_pedo_deb_reg_t pedo_deb_reg;
6996 int32_t ret;
6997
6998 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
6999
7000 if (ret == 0)
7001 {
7002 ret = lsm6dsm_read_reg(ctx, LSM6DSM_PEDO_DEB_REG,
7003 (uint8_t *)&pedo_deb_reg, 1);
7004
7005 if (ret == 0)
7006 {
7007 pedo_deb_reg.deb_time = val;
7008 ret = lsm6dsm_write_reg(ctx, LSM6DSM_PEDO_DEB_REG,
7009 (uint8_t *)&pedo_deb_reg, 1);
7010
7011 if (ret == 0)
7012 {
7013 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7014 }
7015 }
7016 }
7017
7018 return ret;
7019 }
7020
7021 /**
7022 * @brief Debounce time. If the time between two consecutive steps is
7023 * greater than DEB_TIME*80ms, the debouncer is reactivated.
7024 * Default value: 01101[get]
7025 *
7026 * @param ctx Read / write interface definitions
7027 * @param val Change the values of deb_time in reg PEDO_DEB_REG
7028 * @retval Interface status (MANDATORY: return 0 -> no Error).
7029 *
7030 */
lsm6dsm_pedo_timeout_get(stmdev_ctx_t * ctx,uint8_t * val)7031 int32_t lsm6dsm_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
7032 {
7033 lsm6dsm_pedo_deb_reg_t pedo_deb_reg;
7034 int32_t ret;
7035
7036 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
7037
7038 if (ret == 0)
7039 {
7040 ret = lsm6dsm_read_reg(ctx, LSM6DSM_PEDO_DEB_REG,
7041 (uint8_t *)&pedo_deb_reg, 1);
7042
7043 if (ret == 0)
7044 {
7045 *val = pedo_deb_reg.deb_time;
7046 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7047 }
7048 }
7049
7050 return ret;
7051 }
7052
7053 /**
7054 * @brief Time period register for step detection on delta time (r/w).[set]
7055 *
7056 * @param ctx Read / write interface definitions
7057 * @param buff Buffer that contains data to write
7058 * @retval Interface status (MANDATORY: return 0 -> no Error).
7059 *
7060 */
lsm6dsm_pedo_steps_period_set(stmdev_ctx_t * ctx,uint8_t * buff)7061 int32_t lsm6dsm_pedo_steps_period_set(stmdev_ctx_t *ctx,
7062 uint8_t *buff)
7063 {
7064 int32_t ret;
7065
7066 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
7067
7068 if (ret == 0)
7069 {
7070 ret = lsm6dsm_write_reg(ctx, LSM6DSM_STEP_COUNT_DELTA, buff, 1);
7071
7072 if (ret == 0)
7073 {
7074 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7075 }
7076 }
7077
7078 return ret;
7079 }
7080
7081 /**
7082 * @brief Time period register for step detection on delta time (r/w).[get]
7083 *
7084 * @param ctx Read / write interface definitions
7085 * @param buff Buffer that stores data read
7086 * @retval Interface status (MANDATORY: return 0 -> no Error).
7087 *
7088 */
lsm6dsm_pedo_steps_period_get(stmdev_ctx_t * ctx,uint8_t * buff)7089 int32_t lsm6dsm_pedo_steps_period_get(stmdev_ctx_t *ctx,
7090 uint8_t *buff)
7091 {
7092 int32_t ret;
7093
7094 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
7095
7096 if (ret == 0)
7097 {
7098 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STEP_COUNT_DELTA, buff, 1);
7099
7100 if (ret == 0)
7101 {
7102 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7103 }
7104 }
7105
7106 return ret;
7107 }
7108
7109 /**
7110 * @}
7111 *
7112 */
7113
7114 /**
7115 * @defgroup LSM6DSM_significant_motion
7116 * @brief This section groups all the functions that manage the
7117 * significant motion detection.
7118 * @{
7119 *
7120 */
7121
7122 /**
7123 * @brief Enable significant motion detection function.[set]
7124 *
7125 * @param ctx Read / write interface definitions
7126 * @param val Change the values of sign_motion_en in reg CTRL10_C
7127 * @retval Interface status (MANDATORY: return 0 -> no Error).
7128 *
7129 */
lsm6dsm_motion_sens_set(stmdev_ctx_t * ctx,uint8_t val)7130 int32_t lsm6dsm_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
7131 {
7132 lsm6dsm_ctrl10_c_t ctrl10_c;
7133 int32_t ret;
7134
7135 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7136
7137 if (ret == 0)
7138 {
7139 ctrl10_c.sign_motion_en = val;
7140
7141 if (val != 0x00U)
7142 {
7143 ctrl10_c.func_en = val;
7144 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7145 }
7146 }
7147
7148 return ret;
7149 }
7150
7151 /**
7152 * @brief Enable significant motion detection function.[get]
7153 *
7154 * @param ctx Read / write interface definitions
7155 * @param val Change the values of sign_motion_en in reg CTRL10_C
7156 * @retval Interface status (MANDATORY: return 0 -> no Error).
7157 *
7158 */
lsm6dsm_motion_sens_get(stmdev_ctx_t * ctx,uint8_t * val)7159 int32_t lsm6dsm_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
7160 {
7161 lsm6dsm_ctrl10_c_t ctrl10_c;
7162 int32_t ret;
7163
7164 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7165 *val = ctrl10_c.sign_motion_en;
7166
7167 return ret;
7168 }
7169
7170 /**
7171 * @brief Significant motion threshold.[set]
7172 *
7173 * @param ctx Read / write interface definitions
7174 * @param buff Buffer that store significant motion threshold.
7175 * @retval Interface status (MANDATORY: return 0 -> no Error).
7176 *
7177 */
lsm6dsm_motion_threshold_set(stmdev_ctx_t * ctx,uint8_t * buff)7178 int32_t lsm6dsm_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
7179 {
7180 int32_t ret;
7181
7182 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
7183
7184 if (ret == 0)
7185 {
7186 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SM_THS, buff, 1);
7187
7188 if (ret == 0)
7189 {
7190 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7191 }
7192 }
7193
7194 return ret;
7195 }
7196
7197 /**
7198 * @brief Significant motion threshold.[get]
7199 *
7200 * @param ctx Read / write interface definitions
7201 * @param buff Buffer that store significant motion threshold.
7202 * @retval Interface status (MANDATORY: return 0 -> no Error).
7203 *
7204 */
lsm6dsm_motion_threshold_get(stmdev_ctx_t * ctx,uint8_t * buff)7205 int32_t lsm6dsm_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
7206 {
7207 int32_t ret;
7208
7209 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
7210
7211 if (ret == 0)
7212 {
7213 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SM_THS, buff, 1);
7214
7215 if (ret == 0)
7216 {
7217 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7218 }
7219 }
7220
7221 return ret;
7222 }
7223
7224 /**
7225 * @}
7226 *
7227 */
7228
7229 /**
7230 * @defgroup LSM6DSM_tilt_detection
7231 * @brief This section groups all the functions that manage the tilt
7232 * event detection.
7233 * @{
7234 *
7235 */
7236
7237 /**
7238 * @brief Enable tilt calculation.[set]
7239 *
7240 * @param ctx Read / write interface definitions
7241 * @param val Change the values of tilt_en in reg CTRL10_C
7242 * @retval Interface status (MANDATORY: return 0 -> no Error).
7243 *
7244 */
lsm6dsm_tilt_sens_set(stmdev_ctx_t * ctx,uint8_t val)7245 int32_t lsm6dsm_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
7246 {
7247 lsm6dsm_ctrl10_c_t ctrl10_c;
7248 int32_t ret;
7249
7250 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7251
7252 if (ret == 0)
7253 {
7254 ctrl10_c.tilt_en = val;
7255
7256 if (val != 0x00U)
7257 {
7258 ctrl10_c.func_en = val;
7259 }
7260
7261 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7262 }
7263
7264 return ret;
7265 }
7266
7267 /**
7268 * @brief Enable tilt calculation.[get]
7269 *
7270 * @param ctx Read / write interface definitions
7271 * @param val Change the values of tilt_en in reg CTRL10_C
7272 * @retval Interface status (MANDATORY: return 0 -> no Error).
7273 *
7274 */
lsm6dsm_tilt_sens_get(stmdev_ctx_t * ctx,uint8_t * val)7275 int32_t lsm6dsm_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
7276 {
7277 lsm6dsm_ctrl10_c_t ctrl10_c;
7278 int32_t ret;
7279
7280 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7281 *val = ctrl10_c.tilt_en;
7282
7283 return ret;
7284 }
7285
7286 /**
7287 * @brief Enable tilt calculation.[set]
7288 *
7289 * @param ctx Read / write interface definitions
7290 * @param val Change the values of tilt_en in reg CTRL10_C
7291 * @retval Interface status (MANDATORY: return 0 -> no Error).
7292 *
7293 */
lsm6dsm_wrist_tilt_sens_set(stmdev_ctx_t * ctx,uint8_t val)7294 int32_t lsm6dsm_wrist_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
7295 {
7296 lsm6dsm_ctrl10_c_t ctrl10_c;
7297 int32_t ret;
7298
7299 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7300
7301 if (ret == 0)
7302 {
7303 ctrl10_c.wrist_tilt_en = val;
7304
7305 if (val != 0x00U)
7306 {
7307 ctrl10_c.func_en = val;
7308 }
7309
7310 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7311 }
7312
7313 return ret;
7314 }
7315
7316 /**
7317 * @brief Enable tilt calculation.[get]
7318 *
7319 * @param ctx Read / write interface definitions
7320 * @param val Change the values of tilt_en in reg CTRL10_C
7321 * @retval Interface status (MANDATORY: return 0 -> no Error).
7322 *
7323 */
lsm6dsm_wrist_tilt_sens_get(stmdev_ctx_t * ctx,uint8_t * val)7324 int32_t lsm6dsm_wrist_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
7325 {
7326 lsm6dsm_ctrl10_c_t ctrl10_c;
7327 int32_t ret;
7328
7329 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7330 *val = ctrl10_c.wrist_tilt_en;
7331
7332 return ret;
7333 }
7334
7335 /**
7336 * @brief Absolute Wrist Tilt latency register (r/w).
7337 * Absolute wrist tilt latency parameters.
7338 * 1 LSB = 40 ms. Default value: 0Fh (600 ms).[set]
7339 *
7340 * @param ctx Read / write interface definitions
7341 * @param buff Buffer that contains data to write
7342 * @retval Interface status (MANDATORY: return 0 -> no Error).
7343 *
7344 */
lsm6dsm_tilt_latency_set(stmdev_ctx_t * ctx,uint8_t * buff)7345 int32_t lsm6dsm_tilt_latency_set(stmdev_ctx_t *ctx, uint8_t *buff)
7346 {
7347 int32_t ret;
7348
7349 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
7350
7351 if (ret == 0)
7352 {
7353 ret = lsm6dsm_write_reg(ctx, LSM6DSM_A_WRIST_TILT_LAT, buff, 1);
7354
7355 if (ret == 0)
7356 {
7357 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7358 }
7359 }
7360
7361 return ret;
7362 }
7363
7364 /**
7365 * @brief Absolute Wrist Tilt latency register (r/w).
7366 * Absolute wrist tilt latency parameters.
7367 * 1 LSB = 40 ms. Default value: 0Fh (600 ms).[get]
7368 *
7369 * @param ctx Read / write interface definitions
7370 * @param buff Buffer that stores data read
7371 * @retval Interface status (MANDATORY: return 0 -> no Error).
7372 *
7373 */
lsm6dsm_tilt_latency_get(stmdev_ctx_t * ctx,uint8_t * buff)7374 int32_t lsm6dsm_tilt_latency_get(stmdev_ctx_t *ctx, uint8_t *buff)
7375 {
7376 int32_t ret;
7377
7378 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
7379
7380 if (ret == 0)
7381 {
7382 ret = lsm6dsm_read_reg(ctx, LSM6DSM_A_WRIST_TILT_LAT, buff, 1);
7383
7384 if (ret == 0)
7385 {
7386 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7387 }
7388 }
7389
7390 return ret;
7391 }
7392
7393 /**
7394 * @brief Absolute Wrist Tilt threshold register(r/w).
7395 * Absolute wrist tilt threshold parameters.
7396 * 1 LSB = 15.625 mg.Default value: 20h (500 mg).[set]
7397 *
7398 * @param ctx Read / write interface definitions
7399 * @param buff Buffer that contains data to write
7400 * @retval Interface status (MANDATORY: return 0 -> no Error).
7401 *
7402 */
lsm6dsm_tilt_threshold_set(stmdev_ctx_t * ctx,uint8_t * buff)7403 int32_t lsm6dsm_tilt_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
7404 {
7405 int32_t ret;
7406
7407 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
7408
7409 if (ret == 0)
7410 {
7411 ret = lsm6dsm_write_reg(ctx, LSM6DSM_A_WRIST_TILT_THS, buff, 1);
7412
7413 if (ret == 0)
7414 {
7415 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7416 }
7417 }
7418
7419 return ret;
7420 }
7421
7422 /**
7423 * @brief Absolute Wrist Tilt threshold register(r/w).
7424 * Absolute wrist tilt threshold parameters.
7425 * 1 LSB = 15.625 mg.Default value: 20h (500 mg).[get]
7426 *
7427 * @param ctx Read / write interface definitions
7428 * @param buff Buffer that stores data read
7429 * @retval Interface status (MANDATORY: return 0 -> no Error).
7430 *
7431 */
lsm6dsm_tilt_threshold_get(stmdev_ctx_t * ctx,uint8_t * buff)7432 int32_t lsm6dsm_tilt_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
7433 {
7434 int32_t ret;
7435
7436 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
7437
7438 if (ret == 0)
7439 {
7440 ret = lsm6dsm_read_reg(ctx, LSM6DSM_A_WRIST_TILT_THS, buff, 1);
7441
7442 if (ret == 0)
7443 {
7444 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7445 }
7446 }
7447
7448 return ret;
7449 }
7450
7451 /**
7452 * @brief Absolute Wrist Tilt mask register (r/w).[set]
7453 *
7454 * @param ctx Read / write interface definitions
7455 * @param val Registers A_WRIST_TILT_MASK
7456 * @retval Interface status (MANDATORY: return 0 -> no Error).
7457 *
7458 */
lsm6dsm_tilt_src_set(stmdev_ctx_t * ctx,lsm6dsm_a_wrist_tilt_mask_t * val)7459 int32_t lsm6dsm_tilt_src_set(stmdev_ctx_t *ctx,
7460 lsm6dsm_a_wrist_tilt_mask_t *val)
7461 {
7462 int32_t ret;
7463
7464 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
7465
7466 if (ret == 0)
7467 {
7468 ret = lsm6dsm_write_reg(ctx, LSM6DSM_A_WRIST_TILT_MASK,
7469 (uint8_t *) val, 1);
7470
7471 if (ret == 0)
7472 {
7473 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7474 }
7475 }
7476
7477 return ret;
7478 }
7479
7480 /**
7481 * @brief Absolute Wrist Tilt mask register (r/w).[get]
7482 *
7483 * @param ctx Read / write interface definitions
7484 * @param val Registers A_WRIST_TILT_MASK
7485 * @retval Interface status (MANDATORY: return 0 -> no Error).
7486 *
7487 */
lsm6dsm_tilt_src_get(stmdev_ctx_t * ctx,lsm6dsm_a_wrist_tilt_mask_t * val)7488 int32_t lsm6dsm_tilt_src_get(stmdev_ctx_t *ctx,
7489 lsm6dsm_a_wrist_tilt_mask_t *val)
7490 {
7491 int32_t ret;
7492
7493 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
7494
7495 if (ret == 0)
7496 {
7497 ret = lsm6dsm_read_reg(ctx, LSM6DSM_A_WRIST_TILT_MASK,
7498 (uint8_t *) val, 1);
7499
7500 if (ret == 0)
7501 {
7502 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7503 }
7504 }
7505
7506 return ret;
7507 }
7508
7509 /**
7510 * @}
7511 *
7512 */
7513
7514 /**
7515 * @defgroup LSM6DSM_ magnetometer_sensor
7516 * @brief This section groups all the functions that manage additional
7517 * magnetometer sensor.
7518 * @{
7519 *
7520 */
7521
7522 /**
7523 * @brief Enable soft-iron correction algorithm for magnetometer.[set]
7524 *
7525 * @param ctx Read / write interface definitions
7526 * @param val Change the values of soft_en in reg CTRL9_XL
7527 * @retval Interface status (MANDATORY: return 0 -> no Error).
7528 *
7529 */
lsm6dsm_mag_soft_iron_set(stmdev_ctx_t * ctx,uint8_t val)7530 int32_t lsm6dsm_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val)
7531 {
7532 lsm6dsm_ctrl9_xl_t ctrl9_xl;
7533 int32_t ret;
7534
7535 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
7536
7537 if (ret == 0)
7538 {
7539 ctrl9_xl.soft_en = val;
7540 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
7541 }
7542
7543 return ret;
7544 }
7545
7546 /**
7547 * @brief Enable soft-iron correction algorithm for magnetometer.[get]
7548 *
7549 * @param ctx Read / write interface definitions
7550 * @param val Change the values of soft_en in reg CTRL9_XL
7551 * @retval Interface status (MANDATORY: return 0 -> no Error).
7552 *
7553 */
lsm6dsm_mag_soft_iron_get(stmdev_ctx_t * ctx,uint8_t * val)7554 int32_t lsm6dsm_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val)
7555 {
7556 lsm6dsm_ctrl9_xl_t ctrl9_xl;
7557 int32_t ret;
7558
7559 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
7560 *val = ctrl9_xl.soft_en;
7561
7562 return ret;
7563 }
7564
7565 /**
7566 * @brief Enable hard-iron correction algorithm for magnetometer.[set]
7567 *
7568 * @param ctx Read / write interface definitions
7569 * @param val Change the values of iron_en in reg MASTER_CONFIG
7570 * @retval Interface status (MANDATORY: return 0 -> no Error).
7571 *
7572 */
lsm6dsm_mag_hard_iron_set(stmdev_ctx_t * ctx,uint8_t val)7573 int32_t lsm6dsm_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val)
7574 {
7575 lsm6dsm_master_config_t master_config;
7576 lsm6dsm_ctrl10_c_t ctrl10_c;
7577 int32_t ret;
7578
7579 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
7580 (uint8_t *)&master_config, 1);
7581
7582 if (ret == 0)
7583 {
7584 master_config.iron_en = val;
7585 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
7586 (uint8_t *)&master_config, 1);
7587
7588 if (ret == 0)
7589 {
7590 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7591
7592 if (ret == 0)
7593 {
7594 if (val != 0x00U)
7595 {
7596 ctrl10_c.func_en = val;
7597 }
7598
7599 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C,
7600 (uint8_t *)&ctrl10_c, 1);
7601 }
7602 }
7603 }
7604
7605 return ret;
7606 }
7607
7608 /**
7609 * @brief Enable hard-iron correction algorithm for magnetometer.[get]
7610 *
7611 * @param ctx Read / write interface definitions
7612 * @param val Change the values of iron_en in reg MASTER_CONFIG
7613 * @retval Interface status (MANDATORY: return 0 -> no Error).
7614 *
7615 */
lsm6dsm_mag_hard_iron_get(stmdev_ctx_t * ctx,uint8_t * val)7616 int32_t lsm6dsm_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val)
7617 {
7618 lsm6dsm_master_config_t master_config;
7619 int32_t ret;
7620
7621 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
7622 (uint8_t *)&master_config, 1);
7623 *val = master_config.iron_en;
7624
7625 return ret;
7626 }
7627
7628 /**
7629 * @brief Soft iron 3x3 matrix. Value are expressed in sign-module format.
7630 * (Es. SVVVVVVVb where S is the sign 0/+1/- and V is the value).[set]
7631 *
7632 * @param ctx Read / write interface definitions
7633 * @param buff Buffer that contains data to write
7634 * @retval Interface status (MANDATORY: return 0 -> no Error).
7635 *
7636 */
lsm6dsm_mag_soft_iron_mat_set(stmdev_ctx_t * ctx,uint8_t * buff)7637 int32_t lsm6dsm_mag_soft_iron_mat_set(stmdev_ctx_t *ctx,
7638 uint8_t *buff)
7639 {
7640 int32_t ret;
7641
7642 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
7643
7644 if (ret == 0)
7645 {
7646 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MAG_SI_XX, buff, 9);
7647
7648 if (ret == 0)
7649 {
7650 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7651 }
7652 }
7653
7654 return ret;
7655 }
7656
7657 /**
7658 * @brief Soft iron 3x3 matrix. Value are expressed in sign-module format.
7659 * (Es. SVVVVVVVb where S is the sign 0/+1/- and V is the value).[get]
7660 *
7661 * @param ctx Read / write interface definitions
7662 * @param buff Buffer that stores data read
7663 * @retval Interface status (MANDATORY: return 0 -> no Error).
7664 *
7665 */
lsm6dsm_mag_soft_iron_mat_get(stmdev_ctx_t * ctx,uint8_t * buff)7666 int32_t lsm6dsm_mag_soft_iron_mat_get(stmdev_ctx_t *ctx,
7667 uint8_t *buff)
7668 {
7669 int32_t ret;
7670
7671 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
7672
7673 if (ret == 0)
7674 {
7675 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MAG_SI_XX, buff, 9);
7676
7677 if (ret == 0)
7678 {
7679 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7680 }
7681 }
7682
7683 return ret;
7684 }
7685
7686 /**
7687 * @brief Offset for hard-iron compensation register (r/w). The value is
7688 * expressed as a 16-bit word in two’s complement.[set]
7689 *
7690 * @param ctx Read / write interface definitions
7691 * @param buff Buffer that contains data to write
7692 * @retval Interface status (MANDATORY: return 0 -> no Error).
7693 *
7694 */
lsm6dsm_mag_offset_set(stmdev_ctx_t * ctx,int16_t * val)7695 int32_t lsm6dsm_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
7696 {
7697 uint8_t buff[6];
7698 int32_t ret;
7699
7700 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
7701
7702 if (ret == 0)
7703 {
7704 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
7705 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
7706 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
7707 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
7708 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
7709 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
7710 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MAG_OFFX_L, buff, 6);
7711
7712 if (ret == 0)
7713 {
7714 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7715 }
7716 }
7717
7718 return ret;
7719 }
7720
7721 /**
7722 * @brief Offset for hard-iron compensation register(r/w).
7723 * The value is expressed as a 16-bit word in two’s complement.[get]
7724 *
7725 * @param ctx Read / write interface definitions
7726 * @param buff Buffer that stores data read
7727 * @retval Interface status (MANDATORY: return 0 -> no Error).
7728 *
7729 */
lsm6dsm_mag_offset_get(stmdev_ctx_t * ctx,int16_t * val)7730 int32_t lsm6dsm_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
7731 {
7732 uint8_t buff[6];
7733 int32_t ret;
7734
7735 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
7736
7737 if (ret == 0)
7738 {
7739 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MAG_OFFX_L, buff, 6);
7740
7741 if (ret == 0)
7742 {
7743 val[0] = (int16_t)buff[1];
7744 val[0] = (val[0] * 256) + (int16_t)buff[0];
7745 val[1] = (int16_t)buff[3];
7746 val[1] = (val[1] * 256) + (int16_t)buff[2];
7747 val[2] = (int16_t)buff[5];
7748 val[2] = (val[2] * 256) + (int16_t)buff[4];
7749 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7750 }
7751 }
7752
7753 return ret;
7754 }
7755
7756 /**
7757 * @}
7758 *
7759 */
7760
7761 /**
7762 * @defgroup LSM6DSM_Sensor_hub
7763 * @brief This section groups all the functions that manage the sensor
7764 * hub functionality.
7765 * @{
7766 *
7767 */
7768
7769 /**
7770 * @brief Enable function.[set]
7771 *
7772 * @param ctx Read / write interface definitions
7773 * @param val Change the values func_en
7774 * @retval Interface status (MANDATORY: return 0 -> no Error).
7775 *
7776 */
lsm6dsm_func_en_set(stmdev_ctx_t * ctx,uint8_t val)7777 int32_t lsm6dsm_func_en_set(stmdev_ctx_t *ctx, uint8_t val)
7778 {
7779 lsm6dsm_ctrl10_c_t ctrl10_c;
7780 int32_t ret;
7781
7782 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7783
7784 if (ret == 0)
7785 {
7786 ctrl10_c.func_en = val;
7787 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7788 }
7789
7790 return ret;
7791 }
7792
7793 /**
7794 * @brief Sensor synchronization time frame with the step of 500 ms and
7795 * full range of 5s. Unsigned 8-bit.[set]
7796 *
7797 * @param ctx Read / write interface definitions
7798 * @param val Change the values of tph in reg SENSOR_SYNC_TIME_FRAME
7799 * @retval Interface status (MANDATORY: return 0 -> no Error).
7800 *
7801 */
lsm6dsm_sh_sync_sens_frame_set(stmdev_ctx_t * ctx,uint8_t val)7802 int32_t lsm6dsm_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val)
7803 {
7804 lsm6dsm_sensor_sync_time_frame_t sensor_sync_time_frame;
7805 int32_t ret;
7806
7807 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSOR_SYNC_TIME_FRAME,
7808 (uint8_t *)&sensor_sync_time_frame, 1);
7809
7810 if (ret == 0)
7811 {
7812 sensor_sync_time_frame.tph = val;
7813 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SENSOR_SYNC_TIME_FRAME,
7814 (uint8_t *)&sensor_sync_time_frame, 1);
7815 }
7816
7817 return ret;
7818 }
7819
7820 /**
7821 * @brief Sensor synchronization time frame with the step of 500 ms and
7822 * full range of 5s. Unsigned 8-bit.[get]
7823 *
7824 * @param ctx Read / write interface definitions
7825 * @param val Change the values of tph in reg SENSOR_SYNC_TIME_FRAME
7826 * @retval Interface status (MANDATORY: return 0 -> no Error).
7827 *
7828 */
lsm6dsm_sh_sync_sens_frame_get(stmdev_ctx_t * ctx,uint8_t * val)7829 int32_t lsm6dsm_sh_sync_sens_frame_get(stmdev_ctx_t *ctx,
7830 uint8_t *val)
7831 {
7832 lsm6dsm_sensor_sync_time_frame_t sensor_sync_time_frame;
7833 int32_t ret;
7834
7835 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSOR_SYNC_TIME_FRAME,
7836 (uint8_t *)&sensor_sync_time_frame, 1);
7837 *val = sensor_sync_time_frame.tph;
7838
7839 return ret;
7840 }
7841
7842 /**
7843 * @brief Resolution ratio of error code for sensor synchronization.[set]
7844 *
7845 * @param ctx Read / write interface definitions
7846 * @param val Change the values of rr in reg SENSOR_SYNC_RES_RATIO
7847 * @retval Interface status (MANDATORY: return 0 -> no Error).
7848 *
7849 */
lsm6dsm_sh_sync_sens_ratio_set(stmdev_ctx_t * ctx,lsm6dsm_rr_t val)7850 int32_t lsm6dsm_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx,
7851 lsm6dsm_rr_t val)
7852 {
7853 lsm6dsm_sensor_sync_res_ratio_t sensor_sync_res_ratio;
7854 int32_t ret;
7855
7856 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSOR_SYNC_RES_RATIO,
7857 (uint8_t *)&sensor_sync_res_ratio, 1);
7858
7859 if (ret == 0)
7860 {
7861 sensor_sync_res_ratio.rr = (uint8_t) val;
7862 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SENSOR_SYNC_RES_RATIO,
7863 (uint8_t *)&sensor_sync_res_ratio, 1);
7864 }
7865
7866 return ret;
7867 }
7868
7869 /**
7870 * @brief Resolution ratio of error code for sensor synchronization.[get]
7871 *
7872 * @param ctx Read / write interface definitions
7873 * @param val Get the values of rr in reg SENSOR_SYNC_RES_RATIO
7874 * @retval Interface status (MANDATORY: return 0 -> no Error).
7875 *
7876 */
lsm6dsm_sh_sync_sens_ratio_get(stmdev_ctx_t * ctx,lsm6dsm_rr_t * val)7877 int32_t lsm6dsm_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx,
7878 lsm6dsm_rr_t *val)
7879 {
7880 lsm6dsm_sensor_sync_res_ratio_t sensor_sync_res_ratio;
7881 int32_t ret;
7882
7883 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSOR_SYNC_RES_RATIO,
7884 (uint8_t *)&sensor_sync_res_ratio, 1);
7885
7886 switch (sensor_sync_res_ratio.rr)
7887 {
7888 case LSM6DSM_RES_RATIO_2_11:
7889 *val = LSM6DSM_RES_RATIO_2_11;
7890 break;
7891
7892 case LSM6DSM_RES_RATIO_2_12:
7893 *val = LSM6DSM_RES_RATIO_2_12;
7894 break;
7895
7896 case LSM6DSM_RES_RATIO_2_13:
7897 *val = LSM6DSM_RES_RATIO_2_13;
7898 break;
7899
7900 case LSM6DSM_RES_RATIO_2_14:
7901 *val = LSM6DSM_RES_RATIO_2_14;
7902 break;
7903
7904 default:
7905 *val = LSM6DSM_RES_RATIO_2_11;
7906 break;
7907 }
7908
7909 return ret;
7910 }
7911
7912 /**
7913 * @brief Sensor hub I2C master enable.[set]
7914 *
7915 * @param ctx Read / write interface definitions
7916 * @param val Change the values of master_on in reg MASTER_CONFIG
7917 * @retval Interface status (MANDATORY: return 0 -> no Error).
7918 *
7919 */
lsm6dsm_sh_master_set(stmdev_ctx_t * ctx,uint8_t val)7920 int32_t lsm6dsm_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
7921 {
7922 lsm6dsm_master_config_t master_config;
7923 int32_t ret;
7924
7925 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
7926 (uint8_t *)&master_config, 1);
7927
7928 if (ret == 0)
7929 {
7930 master_config.master_on = val;
7931 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
7932 (uint8_t *)&master_config, 1);
7933 }
7934
7935 return ret;
7936 }
7937
7938 /**
7939 * @brief Sensor hub I2C master enable.[get]
7940 *
7941 * @param ctx Read / write interface definitions
7942 * @param val Change the values of master_on in reg MASTER_CONFIG
7943 * @retval Interface status (MANDATORY: return 0 -> no Error).
7944 *
7945 */
lsm6dsm_sh_master_get(stmdev_ctx_t * ctx,uint8_t * val)7946 int32_t lsm6dsm_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
7947 {
7948 lsm6dsm_master_config_t master_config;
7949 int32_t ret;
7950
7951 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
7952 (uint8_t *)&master_config, 1);
7953 *val = master_config.master_on;
7954
7955 return ret;
7956 }
7957
7958 /**
7959 * @brief I2C interface pass-through.[set]
7960 *
7961 * @param ctx Read / write interface definitions
7962 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
7963 * @retval Interface status (MANDATORY: return 0 -> no Error).
7964 *
7965 */
lsm6dsm_sh_pass_through_set(stmdev_ctx_t * ctx,uint8_t val)7966 int32_t lsm6dsm_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
7967 {
7968 lsm6dsm_master_config_t master_config;
7969 int32_t ret;
7970
7971 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
7972 (uint8_t *)&master_config, 1);
7973
7974 if (ret == 0)
7975 {
7976 master_config.pass_through_mode = val;
7977 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
7978 (uint8_t *)&master_config, 1);
7979 }
7980
7981 return ret;
7982 }
7983
7984 /**
7985 * @brief I2C interface pass-through.[get]
7986 *
7987 * @param ctx Read / write interface definitions
7988 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
7989 * @retval Interface status (MANDATORY: return 0 -> no Error).
7990 *
7991 */
lsm6dsm_sh_pass_through_get(stmdev_ctx_t * ctx,uint8_t * val)7992 int32_t lsm6dsm_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
7993 {
7994 lsm6dsm_master_config_t master_config;
7995 int32_t ret;
7996
7997 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
7998 (uint8_t *)&master_config, 1);
7999 *val = master_config.pass_through_mode;
8000
8001 return ret;
8002 }
8003
8004 /**
8005 * @brief Master I2C pull-up enable/disable.[set]
8006 *
8007 * @param ctx Read / write interface definitions
8008 * @param val Change the values of pull_up_en in reg MASTER_CONFIG
8009 * @retval Interface status (MANDATORY: return 0 -> no Error).
8010 *
8011 */
lsm6dsm_sh_pin_mode_set(stmdev_ctx_t * ctx,lsm6dsm_pull_up_en_t val)8012 int32_t lsm6dsm_sh_pin_mode_set(stmdev_ctx_t *ctx,
8013 lsm6dsm_pull_up_en_t val)
8014 {
8015 lsm6dsm_master_config_t master_config;
8016 int32_t ret;
8017
8018 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
8019 (uint8_t *)&master_config, 1);
8020
8021 if (ret == 0)
8022 {
8023 master_config.pull_up_en = (uint8_t) val;
8024 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
8025 (uint8_t *)&master_config, 1);
8026 }
8027
8028 return ret;
8029 }
8030
8031 /**
8032 * @brief Master I2C pull-up enable/disable.[get]
8033 *
8034 * @param ctx Read / write interface definitions
8035 * @param val Get the values of pull_up_en in reg MASTER_CONFIG
8036 * @retval Interface status (MANDATORY: return 0 -> no Error).
8037 *
8038 */
lsm6dsm_sh_pin_mode_get(stmdev_ctx_t * ctx,lsm6dsm_pull_up_en_t * val)8039 int32_t lsm6dsm_sh_pin_mode_get(stmdev_ctx_t *ctx,
8040 lsm6dsm_pull_up_en_t *val)
8041 {
8042 lsm6dsm_master_config_t master_config;
8043 int32_t ret;
8044
8045 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
8046 (uint8_t *)&master_config, 1);
8047
8048 switch (master_config.pull_up_en)
8049 {
8050 case LSM6DSM_EXT_PULL_UP:
8051 *val = LSM6DSM_EXT_PULL_UP;
8052 break;
8053
8054 case LSM6DSM_INTERNAL_PULL_UP:
8055 *val = LSM6DSM_INTERNAL_PULL_UP;
8056 break;
8057
8058 default:
8059 *val = LSM6DSM_SH_PIN_MODE;
8060 break;
8061 }
8062
8063 return ret;
8064 }
8065
8066 /**
8067 * @brief Sensor hub trigger signal selection.[set]
8068 *
8069 * @param ctx Read / write interface definitions
8070 * @param val Change the values of start_config in reg MASTER_CONFIG
8071 * @retval Interface status (MANDATORY: return 0 -> no Error).
8072 *
8073 */
lsm6dsm_sh_syncro_mode_set(stmdev_ctx_t * ctx,lsm6dsm_start_config_t val)8074 int32_t lsm6dsm_sh_syncro_mode_set(stmdev_ctx_t *ctx,
8075 lsm6dsm_start_config_t val)
8076 {
8077 lsm6dsm_master_config_t master_config;
8078 int32_t ret;
8079
8080 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
8081 (uint8_t *)&master_config, 1);
8082
8083 if (ret == 0)
8084 {
8085 master_config.start_config = (uint8_t)val;
8086 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
8087 (uint8_t *)&master_config, 1);
8088 }
8089
8090 return ret;
8091 }
8092
8093 /**
8094 * @brief Sensor hub trigger signal selection.[get]
8095 *
8096 * @param ctx Read / write interface definitions
8097 * @param val Get the values of start_config in reg MASTER_CONFIG
8098 * @retval Interface status (MANDATORY: return 0 -> no Error).
8099 *
8100 */
lsm6dsm_sh_syncro_mode_get(stmdev_ctx_t * ctx,lsm6dsm_start_config_t * val)8101 int32_t lsm6dsm_sh_syncro_mode_get(stmdev_ctx_t *ctx,
8102 lsm6dsm_start_config_t *val)
8103 {
8104 lsm6dsm_master_config_t master_config;
8105 int32_t ret;
8106
8107 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
8108 (uint8_t *)&master_config, 1);
8109
8110 switch (master_config.start_config)
8111 {
8112 case LSM6DSM_XL_GY_DRDY:
8113 *val = LSM6DSM_XL_GY_DRDY;
8114 break;
8115
8116 case LSM6DSM_EXT_ON_INT2_PIN:
8117 *val = LSM6DSM_EXT_ON_INT2_PIN;
8118 break;
8119
8120 default:
8121 *val = LSM6DSM_XL_GY_DRDY;
8122 break;
8123 }
8124
8125 return ret;
8126 }
8127
8128 /**
8129 * @brief Manage the Master DRDY signal on INT1 pad.[set]
8130 *
8131 * @param ctx Read / write interface definitions
8132 * @param val Change the values of drdy_on_int1 in reg MASTER_CONFIG
8133 * @retval Interface status (MANDATORY: return 0 -> no Error).
8134 *
8135 */
lsm6dsm_sh_drdy_on_int1_set(stmdev_ctx_t * ctx,uint8_t val)8136 int32_t lsm6dsm_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
8137 {
8138 lsm6dsm_master_config_t master_config;
8139 int32_t ret;
8140
8141 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
8142 (uint8_t *)&master_config, 1);
8143
8144 if (ret == 0)
8145 {
8146 master_config.drdy_on_int1 = val;
8147 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
8148 (uint8_t *)&master_config, 1);
8149 }
8150
8151 return ret;
8152 }
8153
8154 /**
8155 * @brief Manage the Master DRDY signal on INT1 pad.[get]
8156 *
8157 * @param ctx Read / write interface definitions
8158 * @param val Change the values of drdy_on_int1 in reg MASTER_CONFIG
8159 * @retval Interface status (MANDATORY: return 0 -> no Error).
8160 *
8161 */
lsm6dsm_sh_drdy_on_int1_get(stmdev_ctx_t * ctx,uint8_t * val)8162 int32_t lsm6dsm_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
8163 {
8164 lsm6dsm_master_config_t master_config;
8165 int32_t ret;
8166
8167 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
8168 (uint8_t *)&master_config, 1);
8169 *val = master_config.drdy_on_int1;
8170
8171 return ret;
8172 }
8173
8174 /**
8175 * @brief Sensor hub output registers.[get]
8176 *
8177 * @param ctx Read / write interface definitions
8178 * @param val Structure of registers from SENSORHUB1_REG
8179 * @retval Interface status (MANDATORY: return 0 -> no Error).
8180 *
8181 */
lsm6dsm_sh_read_data_raw_get(stmdev_ctx_t * ctx,lsm6dsm_emb_sh_read_t * val)8182 int32_t lsm6dsm_sh_read_data_raw_get(stmdev_ctx_t *ctx,
8183 lsm6dsm_emb_sh_read_t *val)
8184 {
8185 int32_t ret;
8186
8187 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSORHUB1_REG,
8188 (uint8_t *) & (val->sh_byte_1), 12);
8189
8190 if (ret == 0)
8191 {
8192 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSORHUB13_REG,
8193 (uint8_t *) & (val->sh_byte_13), 6);
8194 }
8195
8196 return ret;
8197 }
8198
8199 /**
8200 * @brief Master command code used for stamping for sensor sync.[set]
8201 *
8202 * @param ctx Read / write interface definitions
8203 * @param val Change the values of master_cmd_code in
8204 * reg MASTER_CMD_CODE
8205 * @retval Interface status (MANDATORY: return 0 -> no Error).
8206 *
8207 */
lsm6dsm_sh_cmd_sens_sync_set(stmdev_ctx_t * ctx,uint8_t val)8208 int32_t lsm6dsm_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val)
8209 {
8210 lsm6dsm_master_cmd_code_t master_cmd_code;
8211 int32_t ret;
8212
8213 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CMD_CODE,
8214 (uint8_t *)&master_cmd_code, 1);
8215
8216 if (ret == 0)
8217 {
8218 master_cmd_code.master_cmd_code = val;
8219 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CMD_CODE,
8220 (uint8_t *)&master_cmd_code, 1);
8221 }
8222
8223 return ret;
8224 }
8225
8226 /**
8227 * @brief Master command code used for stamping for sensor sync.[get]
8228 *
8229 * @param ctx Read / write interface definitions
8230 * @param val Change the values of master_cmd_code in
8231 * reg MASTER_CMD_CODE
8232 * @retval Interface status (MANDATORY: return 0 -> no Error).
8233 *
8234 */
lsm6dsm_sh_cmd_sens_sync_get(stmdev_ctx_t * ctx,uint8_t * val)8235 int32_t lsm6dsm_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val)
8236 {
8237 lsm6dsm_master_cmd_code_t master_cmd_code;
8238 int32_t ret;
8239
8240 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CMD_CODE,
8241 (uint8_t *)&master_cmd_code, 1);
8242 *val = master_cmd_code.master_cmd_code;
8243
8244 return ret;
8245 }
8246
8247 /**
8248 * @brief Error code used for sensor synchronization.[set]
8249 *
8250 * @param ctx Read / write interface definitions
8251 * @param val Change the values of error_code in
8252 * reg SENS_SYNC_SPI_ERROR_CODE.
8253 * @retval Interface status (MANDATORY: return 0 -> no Error).
8254 *
8255 */
lsm6dsm_sh_spi_sync_error_set(stmdev_ctx_t * ctx,uint8_t val)8256 int32_t lsm6dsm_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val)
8257 {
8258 lsm6dsm_sens_sync_spi_error_code_t sens_sync_spi_error_code;
8259 int32_t ret;
8260
8261 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENS_SYNC_SPI_ERROR_CODE,
8262 (uint8_t *)&sens_sync_spi_error_code, 1);
8263
8264 if (ret == 0)
8265 {
8266 sens_sync_spi_error_code.error_code = val;
8267 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SENS_SYNC_SPI_ERROR_CODE,
8268 (uint8_t *)&sens_sync_spi_error_code, 1);
8269 }
8270
8271 return ret;
8272 }
8273
8274 /**
8275 * @brief Error code used for sensor synchronization.[get]
8276 *
8277 * @param ctx Read / write interface definitions
8278 * @param val Change the values of error_code in
8279 * reg SENS_SYNC_SPI_ERROR_CODE.
8280 * @retval Interface status (MANDATORY: return 0 -> no Error).
8281 *
8282 */
lsm6dsm_sh_spi_sync_error_get(stmdev_ctx_t * ctx,uint8_t * val)8283 int32_t lsm6dsm_sh_spi_sync_error_get(stmdev_ctx_t *ctx, uint8_t *val)
8284 {
8285 lsm6dsm_sens_sync_spi_error_code_t sens_sync_spi_error_code;
8286 int32_t ret;
8287
8288 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENS_SYNC_SPI_ERROR_CODE,
8289 (uint8_t *)&sens_sync_spi_error_code, 1);
8290 *val = sens_sync_spi_error_code.error_code;
8291
8292 return ret;
8293 }
8294
8295 /**
8296 * @brief Number of external sensors to be read by the sensor hub.[set]
8297 *
8298 * @param ctx Read / write interface definitions
8299 * @param val Change the values of aux_sens_on in reg SLAVE0_CONFIG.
8300 * @retval Interface status (MANDATORY: return 0 -> no Error).
8301 *
8302 */
lsm6dsm_sh_num_of_dev_connected_set(stmdev_ctx_t * ctx,lsm6dsm_aux_sens_on_t val)8303 int32_t lsm6dsm_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx,
8304 lsm6dsm_aux_sens_on_t val)
8305 {
8306 lsm6dsm_slave0_config_t slave0_config;
8307 int32_t ret;
8308
8309 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8310
8311 if (ret == 0)
8312 {
8313 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
8314 (uint8_t *)&slave0_config, 1);
8315
8316 if (ret == 0)
8317 {
8318 slave0_config.aux_sens_on = (uint8_t) val;
8319 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
8320 (uint8_t *)&slave0_config, 1);
8321
8322 if (ret == 0)
8323 {
8324 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8325 }
8326 }
8327 }
8328
8329 return ret;
8330 }
8331
8332 /**
8333 * @brief Number of external sensors to be read by the sensor hub.[get]
8334 *
8335 * @param ctx Read / write interface definitions
8336 * @param val Get the values of aux_sens_on in reg SLAVE0_CONFIG.
8337 * @retval Interface status (MANDATORY: return 0 -> no Error).
8338 *
8339 */
lsm6dsm_sh_num_of_dev_connected_get(stmdev_ctx_t * ctx,lsm6dsm_aux_sens_on_t * val)8340 int32_t lsm6dsm_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx,
8341 lsm6dsm_aux_sens_on_t *val)
8342 {
8343 lsm6dsm_slave0_config_t slave0_config;
8344 int32_t ret;
8345
8346 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8347
8348 if (ret == 0)
8349 {
8350 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
8351 (uint8_t *)&slave0_config, 1);
8352
8353 if (ret == 0)
8354 {
8355 switch (slave0_config.aux_sens_on)
8356 {
8357 case LSM6DSM_SLV_0:
8358 *val = LSM6DSM_SLV_0;
8359 break;
8360
8361 case LSM6DSM_SLV_0_1:
8362 *val = LSM6DSM_SLV_0_1;
8363 break;
8364
8365 case LSM6DSM_SLV_0_1_2:
8366 *val = LSM6DSM_SLV_0_1_2;
8367 break;
8368
8369 case LSM6DSM_SLV_0_1_2_3:
8370 *val = LSM6DSM_SLV_0_1_2_3;
8371 break;
8372
8373 default:
8374 *val = LSM6DSM_SLV_0;
8375 break;
8376 }
8377
8378 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8379 }
8380 }
8381
8382 return ret;
8383 }
8384
8385 /**
8386 * @brief Configure slave 0 for perform a write.[set]
8387 *
8388 * @param ctx Read / write interface definitions
8389 * @param val Structure that contain:
8390 * - uint8_t slv_add; 8 bit i2c device address
8391 * - uint8_t slv_subadd; 8 bit register device address
8392 * - uint8_t slv_data; 8 bit data to write
8393 * @retval Interface status (MANDATORY: return 0 -> no Error).
8394 *
8395 */
lsm6dsm_sh_cfg_write(stmdev_ctx_t * ctx,lsm6dsm_sh_cfg_write_t * val)8396 int32_t lsm6dsm_sh_cfg_write(stmdev_ctx_t *ctx,
8397 lsm6dsm_sh_cfg_write_t *val)
8398 {
8399 lsm6dsm_slv0_add_t slv0_add;
8400 int32_t ret;
8401
8402 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8403
8404 if (ret == 0)
8405 {
8406 slv0_add.slave0_add = val->slv0_add;
8407 slv0_add.rw_0 = 0;
8408 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV0_ADD, (uint8_t *)&slv0_add, 1);
8409
8410 if (ret == 0)
8411 {
8412 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV0_SUBADD,
8413 &(val->slv0_subadd), 1);
8414
8415 if (ret == 0)
8416 {
8417 ret = lsm6dsm_write_reg(ctx, LSM6DSM_DATAWRITE_SRC_MODE_SUB_SLV0,
8418 &(val->slv0_data), 1);
8419
8420 if (ret == 0)
8421 {
8422 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8423 }
8424 }
8425 }
8426 }
8427
8428 return ret;
8429 }
8430
8431 /**
8432 * @brief Configure slave 0 for perform a read.[get]
8433 *
8434 * @param ctx Read / write interface definitions
8435 * @param val Structure that contain:
8436 * - uint8_t slv_add; 8 bit i2c device address
8437 * - uint8_t slv_subadd; 8 bit register device address
8438 * - uint8_t slv_len; num of bit to read
8439 * @retval Interface status (MANDATORY: return 0 -> no Error).
8440 *
8441 */
lsm6dsm_sh_slv0_cfg_read(stmdev_ctx_t * ctx,lsm6dsm_sh_cfg_read_t * val)8442 int32_t lsm6dsm_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
8443 lsm6dsm_sh_cfg_read_t *val)
8444 {
8445 lsm6dsm_slave0_config_t slave0_config;
8446 lsm6dsm_slv0_add_t slv0_add;
8447 int32_t ret;
8448
8449 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8450
8451 if (ret == 0)
8452 {
8453 slv0_add.slave0_add = val->slv_add;
8454 slv0_add.rw_0 = 1;
8455 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV0_ADD, (uint8_t *)&slv0_add, 1);
8456
8457 if (ret == 0)
8458 {
8459 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV0_SUBADD,
8460 &(val->slv_subadd), 1);
8461
8462 if (ret == 0)
8463 {
8464 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
8465 (uint8_t *)&slave0_config, 1);
8466 slave0_config.slave0_numop = val->slv_len;
8467
8468 if (ret == 0)
8469 {
8470 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
8471 (uint8_t *)&slave0_config, 1);
8472
8473 if (ret == 0)
8474 {
8475 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8476 }
8477 }
8478 }
8479 }
8480 }
8481
8482 return ret;
8483 }
8484
8485 /**
8486 * @brief Configure slave 1 for perform a read.[get]
8487 *
8488 * @param ctx Read / write interface definitions
8489 * @param val Structure that contain:
8490 * - uint8_t slv_add; 8 bit i2c device address
8491 * - uint8_t slv_subadd; 8 bit register device address
8492 * - uint8_t slv_len; num of bit to read
8493 * @retval Interface status (MANDATORY: return 0 -> no Error).
8494 *
8495 */
lsm6dsm_sh_slv1_cfg_read(stmdev_ctx_t * ctx,lsm6dsm_sh_cfg_read_t * val)8496 int32_t lsm6dsm_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
8497 lsm6dsm_sh_cfg_read_t *val)
8498 {
8499 lsm6dsm_slave1_config_t slave1_config;
8500 lsm6dsm_slv1_add_t slv1_add;
8501 int32_t ret;
8502
8503 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8504
8505 if (ret == 0)
8506 {
8507 slv1_add.slave1_add = val->slv_add;
8508 slv1_add.r_1 = 1;
8509 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV1_ADD, (uint8_t *)&slv1_add, 1);
8510
8511 if (ret == 0)
8512 {
8513 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV1_SUBADD,
8514 &(val->slv_subadd), 1);
8515
8516 if (ret == 0)
8517 {
8518 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
8519 (uint8_t *)&slave1_config, 1);
8520 slave1_config.slave1_numop = val->slv_len;
8521
8522 if (ret == 0)
8523 {
8524 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
8525 (uint8_t *)&slave1_config, 1);
8526
8527 if (ret == 0)
8528 {
8529 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8530 }
8531 }
8532 }
8533 }
8534 }
8535
8536 return ret;
8537 }
8538
8539 /**
8540 * @brief Configure slave 2 for perform a read.[get]
8541 *
8542 * @param ctx Read / write interface definitions
8543 * @param val Structure that contain:
8544 * - uint8_t slv_add; 8 bit i2c device address
8545 * - uint8_t slv_subadd; 8 bit register device address
8546 * - uint8_t slv_len; num of bit to read
8547 * @retval Interface status (MANDATORY: return 0 -> no Error).
8548 *
8549 */
lsm6dsm_sh_slv2_cfg_read(stmdev_ctx_t * ctx,lsm6dsm_sh_cfg_read_t * val)8550 int32_t lsm6dsm_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
8551 lsm6dsm_sh_cfg_read_t *val)
8552 {
8553 lsm6dsm_slv2_add_t slv2_add;
8554 lsm6dsm_slave2_config_t slave2_config;
8555 int32_t ret;
8556
8557 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8558
8559 if (ret == 0)
8560 {
8561 slv2_add.slave2_add = val->slv_add;
8562 slv2_add.r_2 = 1;
8563 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV2_ADD, (uint8_t *)&slv2_add, 1);
8564
8565 if (ret == 0)
8566 {
8567 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV2_SUBADD,
8568 &(val->slv_subadd), 1);
8569
8570 if (ret == 0)
8571 {
8572 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE2_CONFIG,
8573 (uint8_t *)&slave2_config, 1);
8574
8575 if (ret == 0)
8576 {
8577 slave2_config.slave2_numop = val->slv_len;
8578 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE2_CONFIG,
8579 (uint8_t *)&slave2_config, 1);
8580
8581 if (ret == 0)
8582 {
8583 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8584 }
8585 }
8586 }
8587 }
8588 }
8589
8590 return ret;
8591 }
8592
8593 /**
8594 * @brief Configure slave 3 for perform a read.[get]
8595 *
8596 * @param ctx Read / write interface definitions
8597 * @param val Structure that contain:
8598 * - uint8_t slv_add; 8 bit i2c device address
8599 * - uint8_t slv_subadd; 8 bit register device address
8600 * - uint8_t slv_len; num of bit to read
8601 * @retval Interface status (MANDATORY: return 0 -> no Error).
8602 *
8603 */
lsm6dsm_sh_slv3_cfg_read(stmdev_ctx_t * ctx,lsm6dsm_sh_cfg_read_t * val)8604 int32_t lsm6dsm_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
8605 lsm6dsm_sh_cfg_read_t *val)
8606 {
8607 lsm6dsm_slave3_config_t slave3_config;
8608 lsm6dsm_slv3_add_t slv3_add;
8609 int32_t ret;
8610
8611 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8612
8613 if (ret == 0)
8614 {
8615 slv3_add.slave3_add = val->slv_add;
8616 slv3_add.r_3 = 1;
8617 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV3_ADD, (uint8_t *)&slv3_add, 1);
8618
8619 if (ret == 0)
8620 {
8621 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV3_SUBADD,
8622 (uint8_t *) & (val->slv_subadd), 1);
8623
8624 if (ret == 0)
8625 {
8626 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE3_CONFIG,
8627 (uint8_t *)&slave3_config, 1);
8628
8629 if (ret == 0)
8630 {
8631 slave3_config.slave3_numop = val->slv_len;
8632 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE3_CONFIG,
8633 (uint8_t *)&slave3_config, 1);
8634
8635 if (ret == 0)
8636 {
8637 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8638 }
8639 }
8640 }
8641 }
8642 }
8643
8644 return ret;
8645 }
8646
8647 /**
8648 * @brief Decimation of read operation on Slave 0 starting from the
8649 * sensor hub trigger.[set]
8650 *
8651 * @param ctx Read / write interface definitions
8652 * @param val Change the values of slave0_rate in reg SLAVE0_CONFIG
8653 * @retval Interface status (MANDATORY: return 0 -> no Error).
8654 *
8655 */
lsm6dsm_sh_slave_0_dec_set(stmdev_ctx_t * ctx,lsm6dsm_slave0_rate_t val)8656 int32_t lsm6dsm_sh_slave_0_dec_set(stmdev_ctx_t *ctx,
8657 lsm6dsm_slave0_rate_t val)
8658 {
8659 lsm6dsm_slave0_config_t slave0_config;
8660 int32_t ret;
8661
8662 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8663
8664 if (ret == 0)
8665 {
8666 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
8667 (uint8_t *)&slave0_config, 1);
8668
8669 if (ret == 0)
8670 {
8671 slave0_config.slave0_rate = (uint8_t) val;
8672 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
8673 (uint8_t *)&slave0_config, 1);
8674
8675 if (ret == 0)
8676 {
8677 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8678 }
8679 }
8680 }
8681
8682 return ret;
8683 }
8684
8685 /**
8686 * @brief Decimation of read operation on Slave 0 starting from the
8687 * sensor hub trigger.[get]
8688 *
8689 * @param ctx Read / write interface definitions
8690 * @param val Get the values of slave0_rate in reg SLAVE0_CONFIG
8691 * @retval Interface status (MANDATORY: return 0 -> no Error).
8692 *
8693 */
lsm6dsm_sh_slave_0_dec_get(stmdev_ctx_t * ctx,lsm6dsm_slave0_rate_t * val)8694 int32_t lsm6dsm_sh_slave_0_dec_get(stmdev_ctx_t *ctx,
8695 lsm6dsm_slave0_rate_t *val)
8696 {
8697 lsm6dsm_slave0_config_t slave0_config;
8698 int32_t ret;
8699
8700 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8701
8702 if (ret == 0)
8703 {
8704 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
8705 (uint8_t *)&slave0_config, 1);
8706
8707 if (ret == 0)
8708 {
8709 switch (slave0_config.slave0_rate)
8710 {
8711 case LSM6DSM_SL0_NO_DEC:
8712 *val = LSM6DSM_SL0_NO_DEC;
8713 break;
8714
8715 case LSM6DSM_SL0_DEC_2:
8716 *val = LSM6DSM_SL0_DEC_2;
8717 break;
8718
8719 case LSM6DSM_SL0_DEC_4:
8720 *val = LSM6DSM_SL0_DEC_4;
8721 break;
8722
8723 case LSM6DSM_SL0_DEC_8:
8724 *val = LSM6DSM_SL0_DEC_8;
8725 break;
8726
8727 default:
8728 *val = LSM6DSM_SL0_NO_DEC;
8729 break;
8730 }
8731
8732 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8733 }
8734 }
8735
8736 return ret;
8737 }
8738
8739 /**
8740 * @brief Slave 0 write operation is performed only at the first sensor
8741 * hub cycle.
8742 * This is effective if the Aux_sens_on[1:0] field in
8743 * SLAVE0_CONFIG(04h) is set to a value other than 00.[set]
8744 *
8745 * @param ctx Read / write interface definitions
8746 * @param val Change the values of write_once in reg SLAVE1_CONFIG
8747 * @retval Interface status (MANDATORY: return 0 -> no Error).
8748 *
8749 */
lsm6dsm_sh_write_mode_set(stmdev_ctx_t * ctx,lsm6dsm_write_once_t val)8750 int32_t lsm6dsm_sh_write_mode_set(stmdev_ctx_t *ctx,
8751 lsm6dsm_write_once_t val)
8752 {
8753 lsm6dsm_slave1_config_t slave1_config;
8754 int32_t ret;
8755
8756 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8757
8758 if (ret == 0)
8759 {
8760 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
8761 (uint8_t *)&slave1_config, 1);
8762 slave1_config.write_once = (uint8_t) val;
8763
8764 if (ret == 0)
8765 {
8766 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
8767 (uint8_t *)&slave1_config, 1);
8768
8769 if (ret == 0)
8770 {
8771 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8772 }
8773 }
8774 }
8775
8776 return ret;
8777 }
8778
8779 /**
8780 * @brief Slave 0 write operation is performed only at the first sensor
8781 * hub cycle.
8782 * This is effective if the Aux_sens_on[1:0] field in
8783 * SLAVE0_CONFIG(04h) is set to a value other than 00.[get]
8784 *
8785 * @param ctx Read / write interface definitions
8786 * @param val Get the values of write_once in reg SLAVE1_CONFIG
8787 * @retval Interface status (MANDATORY: return 0 -> no Error).
8788 *
8789 */
lsm6dsm_sh_write_mode_get(stmdev_ctx_t * ctx,lsm6dsm_write_once_t * val)8790 int32_t lsm6dsm_sh_write_mode_get(stmdev_ctx_t *ctx,
8791 lsm6dsm_write_once_t *val)
8792 {
8793 lsm6dsm_slave1_config_t slave1_config;
8794 int32_t ret;
8795
8796 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8797
8798 if (ret == 0)
8799 {
8800 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
8801 (uint8_t *)&slave1_config, 1);
8802
8803 if (ret == 0)
8804 {
8805 switch (slave1_config.write_once)
8806 {
8807 case LSM6DSM_EACH_SH_CYCLE:
8808 *val = LSM6DSM_EACH_SH_CYCLE;
8809 break;
8810
8811 case LSM6DSM_ONLY_FIRST_CYCLE:
8812 *val = LSM6DSM_ONLY_FIRST_CYCLE;
8813 break;
8814
8815 default:
8816 *val = LSM6DSM_EACH_SH_CYCLE;
8817 break;
8818 }
8819
8820 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8821 }
8822 }
8823
8824 return ret;
8825 }
8826
8827 /**
8828 * @brief Decimation of read operation on Slave 1 starting from the
8829 * sensor hub trigger.[set]
8830 *
8831 * @param ctx Read / write interface definitions
8832 * @param val Change the values of slave1_rate in reg SLAVE1_CONFIG
8833 * @retval Interface status (MANDATORY: return 0 -> no Error).
8834 *
8835 */
lsm6dsm_sh_slave_1_dec_set(stmdev_ctx_t * ctx,lsm6dsm_slave1_rate_t val)8836 int32_t lsm6dsm_sh_slave_1_dec_set(stmdev_ctx_t *ctx,
8837 lsm6dsm_slave1_rate_t val)
8838 {
8839 lsm6dsm_slave1_config_t slave1_config;
8840 int32_t ret;
8841
8842 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8843
8844 if (ret == 0)
8845 {
8846 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
8847 (uint8_t *)&slave1_config, 1);
8848
8849 if (ret == 0)
8850 {
8851 slave1_config.slave1_rate = (uint8_t) val;
8852 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
8853 (uint8_t *)&slave1_config, 1);
8854
8855 if (ret == 0)
8856 {
8857 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8858 }
8859 }
8860 }
8861
8862 return ret;
8863 }
8864
8865 /**
8866 * @brief Decimation of read operation on Slave 1 starting from the
8867 * sensor hub trigger.[get]
8868 *
8869 * @param ctx Read / write interface definitions reg SLAVE1_CONFIG
8870 * @retval Interface status (MANDATORY: return 0 -> no Error).
8871 *
8872 */
lsm6dsm_sh_slave_1_dec_get(stmdev_ctx_t * ctx,lsm6dsm_slave1_rate_t * val)8873 int32_t lsm6dsm_sh_slave_1_dec_get(stmdev_ctx_t *ctx,
8874 lsm6dsm_slave1_rate_t *val)
8875 {
8876 lsm6dsm_slave1_config_t slave1_config;
8877 int32_t ret;
8878
8879 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8880
8881 if (ret == 0)
8882 {
8883 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
8884 (uint8_t *)&slave1_config, 1);
8885
8886 if (ret == 0)
8887 {
8888 switch (slave1_config.slave1_rate)
8889 {
8890 case LSM6DSM_SL1_NO_DEC:
8891 *val = LSM6DSM_SL1_NO_DEC;
8892 break;
8893
8894 case LSM6DSM_SL1_DEC_2:
8895 *val = LSM6DSM_SL1_DEC_2;
8896 break;
8897
8898 case LSM6DSM_SL1_DEC_4:
8899 *val = LSM6DSM_SL1_DEC_4;
8900 break;
8901
8902 case LSM6DSM_SL1_DEC_8:
8903 *val = LSM6DSM_SL1_DEC_8;
8904 break;
8905
8906 default:
8907 *val = LSM6DSM_SL1_NO_DEC;
8908 break;
8909 }
8910
8911 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8912 }
8913 }
8914
8915 return ret;
8916 }
8917
8918 /**
8919 * @brief Decimation of read operation on Slave 2 starting from the
8920 * sensor hub trigger.[set]
8921 *
8922 * @param ctx Read / write interface definitions
8923 * @param val Change the values of slave2_rate in reg SLAVE2_CONFIG
8924 * @retval Interface status (MANDATORY: return 0 -> no Error).
8925 *
8926 */
lsm6dsm_sh_slave_2_dec_set(stmdev_ctx_t * ctx,lsm6dsm_slave2_rate_t val)8927 int32_t lsm6dsm_sh_slave_2_dec_set(stmdev_ctx_t *ctx,
8928 lsm6dsm_slave2_rate_t val)
8929 {
8930 lsm6dsm_slave2_config_t slave2_config;
8931 int32_t ret;
8932
8933 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8934
8935 if (ret == 0)
8936 {
8937 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE2_CONFIG,
8938 (uint8_t *)&slave2_config, 1);
8939
8940 if (ret == 0)
8941 {
8942 slave2_config.slave2_rate = (uint8_t) val;
8943 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE2_CONFIG,
8944 (uint8_t *)&slave2_config, 1);
8945
8946 if (ret == 0)
8947 {
8948 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8949 }
8950 }
8951 }
8952
8953 return ret;
8954 }
8955
8956 /**
8957 * @brief Decimation of read operation on Slave 2 starting from the
8958 * sensor hub trigger.[get]
8959 *
8960 * @param ctx Read / write interface definitions
8961 * @param val Get the values of slave2_rate in reg SLAVE2_CONFIG
8962 * @retval Interface status (MANDATORY: return 0 -> no Error).
8963 *
8964 */
lsm6dsm_sh_slave_2_dec_get(stmdev_ctx_t * ctx,lsm6dsm_slave2_rate_t * val)8965 int32_t lsm6dsm_sh_slave_2_dec_get(stmdev_ctx_t *ctx,
8966 lsm6dsm_slave2_rate_t *val)
8967 {
8968 lsm6dsm_slave2_config_t slave2_config;
8969 int32_t ret;
8970
8971 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8972
8973 if (ret == 0)
8974 {
8975 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE2_CONFIG,
8976 (uint8_t *)&slave2_config, 1);
8977
8978 if (ret == 0)
8979 {
8980 switch (slave2_config.slave2_rate)
8981 {
8982 case LSM6DSM_SL2_NO_DEC:
8983 *val = LSM6DSM_SL2_NO_DEC;
8984 break;
8985
8986 case LSM6DSM_SL2_DEC_2:
8987 *val = LSM6DSM_SL2_DEC_2;
8988 break;
8989
8990 case LSM6DSM_SL2_DEC_4:
8991 *val = LSM6DSM_SL2_DEC_4;
8992 break;
8993
8994 case LSM6DSM_SL2_DEC_8:
8995 *val = LSM6DSM_SL2_DEC_8;
8996 break;
8997
8998 default:
8999 *val = LSM6DSM_SL2_NO_DEC;
9000 break;
9001 }
9002
9003 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
9004 }
9005 }
9006
9007 return ret;
9008 }
9009
9010 /**
9011 * @brief Decimation of read operation on Slave 3 starting from the
9012 * sensor hub trigger.[set]
9013 *
9014 * @param ctx Read / write interface definitions
9015 * @param val Change the values of slave3_rate in reg SLAVE3_CONFIG
9016 * @retval Interface status (MANDATORY: return 0 -> no Error).
9017 *
9018 */
lsm6dsm_sh_slave_3_dec_set(stmdev_ctx_t * ctx,lsm6dsm_slave3_rate_t val)9019 int32_t lsm6dsm_sh_slave_3_dec_set(stmdev_ctx_t *ctx,
9020 lsm6dsm_slave3_rate_t val)
9021 {
9022 lsm6dsm_slave3_config_t slave3_config;
9023 int32_t ret;
9024
9025 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
9026
9027 if (ret == 0)
9028 {
9029 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE3_CONFIG,
9030 (uint8_t *)&slave3_config, 1);
9031 slave3_config.slave3_rate = (uint8_t)val;
9032
9033 if (ret == 0)
9034 {
9035 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE3_CONFIG,
9036 (uint8_t *)&slave3_config, 1);
9037
9038 if (ret == 0)
9039 {
9040 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
9041 }
9042 }
9043 }
9044
9045 return ret;
9046 }
9047
9048 /**
9049 * @brief Decimation of read operation on Slave 3 starting from the
9050 * sensor hub trigger.[get]
9051 *
9052 * @param ctx Read / write interface definitions
9053 * @param val Get the values of slave3_rate in reg SLAVE3_CONFIG.
9054 * @retval Interface status (MANDATORY: return 0 -> no Error).
9055 *
9056 */
lsm6dsm_sh_slave_3_dec_get(stmdev_ctx_t * ctx,lsm6dsm_slave3_rate_t * val)9057 int32_t lsm6dsm_sh_slave_3_dec_get(stmdev_ctx_t *ctx,
9058 lsm6dsm_slave3_rate_t *val)
9059 {
9060 lsm6dsm_slave3_config_t slave3_config;
9061 int32_t ret;
9062
9063 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
9064
9065 if (ret == 0)
9066 {
9067 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE3_CONFIG,
9068 (uint8_t *)&slave3_config, 1);
9069
9070 if (ret == 0)
9071 {
9072 switch (slave3_config.slave3_rate)
9073 {
9074 case LSM6DSM_SL3_NO_DEC:
9075 *val = LSM6DSM_SL3_NO_DEC;
9076 break;
9077
9078 case LSM6DSM_SL3_DEC_2:
9079 *val = LSM6DSM_SL3_DEC_2;
9080 break;
9081
9082 case LSM6DSM_SL3_DEC_4:
9083 *val = LSM6DSM_SL3_DEC_4;
9084 break;
9085
9086 case LSM6DSM_SL3_DEC_8:
9087 *val = LSM6DSM_SL3_DEC_8;
9088 break;
9089
9090 default:
9091 *val = LSM6DSM_SL3_NO_DEC;
9092 break;
9093 }
9094
9095 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
9096 }
9097 }
9098
9099 return ret;
9100 }
9101
9102 /**
9103 * @}
9104 *
9105 */
9106
9107 /**
9108 * @}
9109 *
9110 */
9111
9112 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
9113
