1 /**
2 ******************************************************************************
3 * @file lsm6dsm_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSM driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dsm_reg.h"
21
22 /**
23 * @defgroup LSM6DSM
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dsm enanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LSM6DSM_interfaces_functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6dsm_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dsm_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx read / write interface definitions(ptr)
69 * @param reg register to write
70 * @param data pointer to data to write in register reg(ptr)
71 * @param len number of consecutive register to write
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lsm6dsm_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lsm6dsm_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup LSM6DSM_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
102
lsm6dsm_from_fs2g_to_mg(int16_t lsb)103 float_t lsm6dsm_from_fs2g_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb * 0.061f);
106 }
107
lsm6dsm_from_fs4g_to_mg(int16_t lsb)108 float_t lsm6dsm_from_fs4g_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb * 0.122f);
111 }
112
lsm6dsm_from_fs8g_to_mg(int16_t lsb)113 float_t lsm6dsm_from_fs8g_to_mg(int16_t lsb)
114 {
115 return ((float_t)lsb * 0.244f);
116 }
117
lsm6dsm_from_fs16g_to_mg(int16_t lsb)118 float_t lsm6dsm_from_fs16g_to_mg(int16_t lsb)
119 {
120 return ((float_t)lsb * 0.488f);
121 }
122
lsm6dsm_from_fs125dps_to_mdps(int16_t lsb)123 float_t lsm6dsm_from_fs125dps_to_mdps(int16_t lsb)
124 {
125 return ((float_t)lsb * 4.375f);
126 }
127
lsm6dsm_from_fs250dps_to_mdps(int16_t lsb)128 float_t lsm6dsm_from_fs250dps_to_mdps(int16_t lsb)
129 {
130 return ((float_t)lsb * 8.750f);
131 }
132
lsm6dsm_from_fs500dps_to_mdps(int16_t lsb)133 float_t lsm6dsm_from_fs500dps_to_mdps(int16_t lsb)
134 {
135 return ((float_t)lsb * 17.50f);
136 }
137
lsm6dsm_from_fs1000dps_to_mdps(int16_t lsb)138 float_t lsm6dsm_from_fs1000dps_to_mdps(int16_t lsb)
139 {
140 return ((float_t)lsb * 35.0f);
141 }
142
lsm6dsm_from_fs2000dps_to_mdps(int16_t lsb)143 float_t lsm6dsm_from_fs2000dps_to_mdps(int16_t lsb)
144 {
145 return ((float_t)lsb * 70.0f);
146 }
147
lsm6dsm_from_lsb_to_celsius(int16_t lsb)148 float_t lsm6dsm_from_lsb_to_celsius(int16_t lsb)
149 {
150 return (((float_t)lsb / 256.0f) + 25.0f);
151 }
152
153 /**
154 * @}
155 *
156 */
157
158
159 /**
160 * @defgroup LSM6DSM_data_generation
161 * @brief This section groups all the functions concerning data
162 * generation
163 * @{
164 *
165 */
166
167 /**
168 * @brief Accelerometer full-scale selection.[set]
169 *
170 * @param ctx Read / write interface definitions
171 * @param val Change the values of fs_xl in reg CTRL1_XL
172 * @retval Interface status (MANDATORY: return 0 -> no Error).
173 *
174 */
lsm6dsm_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsm_fs_xl_t val)175 int32_t lsm6dsm_xl_full_scale_set(const stmdev_ctx_t *ctx,
176 lsm6dsm_fs_xl_t val)
177 {
178 lsm6dsm_ctrl1_xl_t ctrl1_xl;
179 int32_t ret;
180
181 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
182
183 if (ret == 0)
184 {
185 ctrl1_xl.fs_xl = (uint8_t) val;
186 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
187 }
188
189 return ret;
190 }
191
192 /**
193 * @brief Accelerometer full-scale selection.[get]
194 *
195 * @param ctx Read / write interface definitions
196 * @param val Get the values of fs_xl in reg CTRL1_XL
197 * @retval Interface status (MANDATORY: return 0 -> no Error).
198 *
199 */
lsm6dsm_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsm_fs_xl_t * val)200 int32_t lsm6dsm_xl_full_scale_get(const stmdev_ctx_t *ctx,
201 lsm6dsm_fs_xl_t *val)
202 {
203 lsm6dsm_ctrl1_xl_t ctrl1_xl;
204 int32_t ret;
205
206 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
207
208 switch (ctrl1_xl.fs_xl)
209 {
210 case LSM6DSM_2g:
211 *val = LSM6DSM_2g;
212 break;
213
214 case LSM6DSM_16g:
215 *val = LSM6DSM_16g;
216 break;
217
218 case LSM6DSM_4g:
219 *val = LSM6DSM_4g;
220 break;
221
222 case LSM6DSM_8g:
223 *val = LSM6DSM_8g;
224 break;
225
226 default:
227 *val = LSM6DSM_2g;
228 break;
229 }
230
231 return ret;
232 }
233
234 /**
235 * @brief Accelerometer data rate selection.[set]
236 *
237 * @param ctx Read / write interface definitions
238 * @param val Change the values of odr_xl in reg CTRL1_XL
239 * @retval Interface status (MANDATORY: return 0 -> no Error).
240 *
241 */
lsm6dsm_xl_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsm_odr_xl_t val)242 int32_t lsm6dsm_xl_data_rate_set(const stmdev_ctx_t *ctx,
243 lsm6dsm_odr_xl_t val)
244 {
245 lsm6dsm_ctrl1_xl_t ctrl1_xl;
246 int32_t ret;
247
248 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
249
250 if (ret == 0)
251 {
252 ctrl1_xl.odr_xl = (uint8_t) val;
253 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
254 }
255
256 return ret;
257 }
258
259 /**
260 * @brief Accelerometer data rate selection.[get]
261 *
262 * @param ctx Read / write interface definitions
263 * @param val Get the values of odr_xl in reg CTRL1_XL
264 * @retval Interface status (MANDATORY: return 0 -> no Error).
265 *
266 */
lsm6dsm_xl_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsm_odr_xl_t * val)267 int32_t lsm6dsm_xl_data_rate_get(const stmdev_ctx_t *ctx,
268 lsm6dsm_odr_xl_t *val)
269 {
270 lsm6dsm_ctrl1_xl_t ctrl1_xl;
271 int32_t ret;
272
273 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
274
275 switch (ctrl1_xl.odr_xl)
276 {
277 case LSM6DSM_XL_ODR_OFF:
278 *val = LSM6DSM_XL_ODR_OFF;
279 break;
280
281 case LSM6DSM_XL_ODR_12Hz5:
282 *val = LSM6DSM_XL_ODR_12Hz5;
283 break;
284
285 case LSM6DSM_XL_ODR_26Hz:
286 *val = LSM6DSM_XL_ODR_26Hz;
287 break;
288
289 case LSM6DSM_XL_ODR_52Hz:
290 *val = LSM6DSM_XL_ODR_52Hz;
291 break;
292
293 case LSM6DSM_XL_ODR_104Hz:
294 *val = LSM6DSM_XL_ODR_104Hz;
295 break;
296
297 case LSM6DSM_XL_ODR_208Hz:
298 *val = LSM6DSM_XL_ODR_208Hz;
299 break;
300
301 case LSM6DSM_XL_ODR_416Hz:
302 *val = LSM6DSM_XL_ODR_416Hz;
303 break;
304
305 case LSM6DSM_XL_ODR_833Hz:
306 *val = LSM6DSM_XL_ODR_833Hz;
307 break;
308
309 case LSM6DSM_XL_ODR_1k66Hz:
310 *val = LSM6DSM_XL_ODR_1k66Hz;
311 break;
312
313 case LSM6DSM_XL_ODR_3k33Hz:
314 *val = LSM6DSM_XL_ODR_3k33Hz;
315 break;
316
317 case LSM6DSM_XL_ODR_6k66Hz:
318 *val = LSM6DSM_XL_ODR_6k66Hz;
319 break;
320
321 case LSM6DSM_XL_ODR_1Hz6:
322 *val = LSM6DSM_XL_ODR_1Hz6;
323 break;
324
325 default:
326 *val = LSM6DSM_XL_ODR_OFF;
327 break;
328 }
329
330 return ret;
331 }
332
333 /**
334 * @brief Gyroscope chain full-scale selection.[set]
335 *
336 * @param ctx Read / write interface definitions
337 * @param val Change the values of fs_g in reg CTRL2_G
338 * @retval Interface status (MANDATORY: return 0 -> no Error).
339 *
340 */
lsm6dsm_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsm_fs_g_t val)341 int32_t lsm6dsm_gy_full_scale_set(const stmdev_ctx_t *ctx,
342 lsm6dsm_fs_g_t val)
343 {
344 lsm6dsm_ctrl2_g_t ctrl2_g;
345 int32_t ret;
346
347 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
348
349 if (ret == 0)
350 {
351 ctrl2_g.fs_g = (uint8_t) val;
352 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
353 }
354
355 return ret;
356 }
357
358 /**
359 * @brief Gyroscope chain full-scale selection.[get]
360 *
361 * @param ctx Read / write interface definitions
362 * @param val Get the values of fs_g in reg CTRL2_G
363 * @retval Interface status (MANDATORY: return 0 -> no Error).
364 *
365 */
lsm6dsm_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsm_fs_g_t * val)366 int32_t lsm6dsm_gy_full_scale_get(const stmdev_ctx_t *ctx,
367 lsm6dsm_fs_g_t *val)
368 {
369 lsm6dsm_ctrl2_g_t ctrl2_g;
370 int32_t ret;
371
372 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
373
374 switch (ctrl2_g.fs_g)
375 {
376 case LSM6DSM_250dps:
377 *val = LSM6DSM_250dps;
378 break;
379
380 case LSM6DSM_125dps:
381 *val = LSM6DSM_125dps;
382 break;
383
384 case LSM6DSM_500dps:
385 *val = LSM6DSM_500dps;
386 break;
387
388 case LSM6DSM_1000dps:
389 *val = LSM6DSM_1000dps;
390 break;
391
392 case LSM6DSM_2000dps:
393 *val = LSM6DSM_2000dps;
394 break;
395
396 default:
397 *val = LSM6DSM_250dps;
398 break;
399 }
400
401 return ret;
402 }
403
404 /**
405 * @brief Gyroscope data rate selection.[set]
406 *
407 * @param ctx Read / write interface definitions
408 * @param val Change the values of odr_g in reg CTRL2_G
409 * @retval Interface status (MANDATORY: return 0 -> no Error).
410 *
411 */
lsm6dsm_gy_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsm_odr_g_t val)412 int32_t lsm6dsm_gy_data_rate_set(const stmdev_ctx_t *ctx,
413 lsm6dsm_odr_g_t val)
414 {
415 lsm6dsm_ctrl2_g_t ctrl2_g;
416 int32_t ret;
417
418 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
419
420 if (ret == 0)
421 {
422 ctrl2_g.odr_g = (uint8_t) val;
423 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
424 }
425
426 return ret;
427 }
428
429 /**
430 * @brief Gyroscope data rate selection.[get]
431 *
432 * @param ctx Read / write interface definitions
433 * @param val Get the values of odr_g in reg CTRL2_G
434 * @retval Interface status (MANDATORY: return 0 -> no Error).
435 *
436 */
lsm6dsm_gy_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsm_odr_g_t * val)437 int32_t lsm6dsm_gy_data_rate_get(const stmdev_ctx_t *ctx,
438 lsm6dsm_odr_g_t *val)
439 {
440 lsm6dsm_ctrl2_g_t ctrl2_g;
441 int32_t ret;
442
443 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
444
445 switch (ctrl2_g.odr_g)
446 {
447 case LSM6DSM_GY_ODR_OFF:
448 *val = LSM6DSM_GY_ODR_OFF;
449 break;
450
451 case LSM6DSM_GY_ODR_12Hz5:
452 *val = LSM6DSM_GY_ODR_12Hz5;
453 break;
454
455 case LSM6DSM_GY_ODR_26Hz:
456 *val = LSM6DSM_GY_ODR_26Hz;
457 break;
458
459 case LSM6DSM_GY_ODR_52Hz:
460 *val = LSM6DSM_GY_ODR_52Hz;
461 break;
462
463 case LSM6DSM_GY_ODR_104Hz:
464 *val = LSM6DSM_GY_ODR_104Hz;
465 break;
466
467 case LSM6DSM_GY_ODR_208Hz:
468 *val = LSM6DSM_GY_ODR_208Hz;
469 break;
470
471 case LSM6DSM_GY_ODR_416Hz:
472 *val = LSM6DSM_GY_ODR_416Hz;
473 break;
474
475 case LSM6DSM_GY_ODR_833Hz:
476 *val = LSM6DSM_GY_ODR_833Hz;
477 break;
478
479 case LSM6DSM_GY_ODR_1k66Hz:
480 *val = LSM6DSM_GY_ODR_1k66Hz;
481 break;
482
483 case LSM6DSM_GY_ODR_3k33Hz:
484 *val = LSM6DSM_GY_ODR_3k33Hz;
485 break;
486
487 case LSM6DSM_GY_ODR_6k66Hz:
488 *val = LSM6DSM_GY_ODR_6k66Hz;
489 break;
490
491 default:
492 *val = LSM6DSM_GY_ODR_OFF;
493 break;
494 }
495
496 return ret;
497 }
498
499 /**
500 * @brief Block data update.[set]
501 *
502 * @param ctx Read / write interface definitions
503 * @param val Change the values of bdu in reg CTRL3_C
504 * @retval Interface status (MANDATORY: return 0 -> no Error).
505 *
506 */
lsm6dsm_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)507 int32_t lsm6dsm_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val)
508 {
509 lsm6dsm_ctrl3_c_t ctrl3_c;
510 int32_t ret;
511
512 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
513
514 if (ret == 0)
515 {
516 ctrl3_c.bdu = val;
517 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
518 }
519
520 return ret;
521 }
522
523 /**
524 * @brief Block data update.[get]
525 *
526 * @param ctx Read / write interface definitions
527 * @param val Change the values of bdu in reg CTRL3_C
528 * @retval Interface status (MANDATORY: return 0 -> no Error).
529 *
530 */
lsm6dsm_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)531 int32_t lsm6dsm_block_data_update_get(const stmdev_ctx_t *ctx, uint8_t *val)
532 {
533 lsm6dsm_ctrl3_c_t ctrl3_c;
534 int32_t ret;
535
536 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
537 *val = ctrl3_c.bdu;
538
539 return ret;
540 }
541
542 /**
543 * @brief Weight of XL user offset bits of registers
544 * X_OFS_USR(73h), Y_OFS_USR(74h), Z_OFS_USR(75h).[set]
545 *
546 * @param ctx Read / write interface definitions
547 * @param val Change the values of usr_off_w in reg CTRL6_C
548 * @retval Interface status (MANDATORY: return 0 -> no Error).
549 *
550 */
lsm6dsm_xl_offset_weight_set(const stmdev_ctx_t * ctx,lsm6dsm_usr_off_w_t val)551 int32_t lsm6dsm_xl_offset_weight_set(const stmdev_ctx_t *ctx,
552 lsm6dsm_usr_off_w_t val)
553 {
554 lsm6dsm_ctrl6_c_t ctrl6_c;
555 int32_t ret;
556
557 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
558
559 if (ret == 0)
560 {
561 ctrl6_c.usr_off_w = (uint8_t) val;
562 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
563 }
564
565 return ret;
566 }
567
568 /**
569 * @brief Weight of XL user offset bits of registers
570 * X_OFS_USR(73h), Y_OFS_USR(74h), Z_OFS_USR(75h).[get]
571 *
572 * @param ctx Read / write interface definitions
573 * @param val Get the values of usr_off_w in reg CTRL6_C
574 * @retval Interface status (MANDATORY: return 0 -> no Error).
575 *
576 */
lsm6dsm_xl_offset_weight_get(const stmdev_ctx_t * ctx,lsm6dsm_usr_off_w_t * val)577 int32_t lsm6dsm_xl_offset_weight_get(const stmdev_ctx_t *ctx,
578 lsm6dsm_usr_off_w_t *val)
579 {
580 lsm6dsm_ctrl6_c_t ctrl6_c;
581 int32_t ret;
582
583 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
584
585 switch (ctrl6_c.usr_off_w)
586 {
587 case LSM6DSM_LSb_1mg:
588 *val = LSM6DSM_LSb_1mg;
589 break;
590
591 case LSM6DSM_LSb_16mg:
592 *val = LSM6DSM_LSb_16mg;
593 break;
594
595 default:
596 *val = LSM6DSM_LSb_1mg;
597 break;
598 }
599
600 return ret;
601 }
602
603 /**
604 * @brief High-performance operating mode for accelerometer[set]
605 *
606 * @param ctx Read / write interface definitions
607 * @param val Change the values of xl_hm_mode in reg CTRL6_C
608 * @retval Interface status (MANDATORY: return 0 -> no Error).
609 *
610 */
lsm6dsm_xl_power_mode_set(const stmdev_ctx_t * ctx,lsm6dsm_xl_hm_mode_t val)611 int32_t lsm6dsm_xl_power_mode_set(const stmdev_ctx_t *ctx,
612 lsm6dsm_xl_hm_mode_t val)
613 {
614 lsm6dsm_ctrl6_c_t ctrl6_c;
615 int32_t ret;
616
617 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
618
619 if (ret == 0)
620 {
621 ctrl6_c.xl_hm_mode = (uint8_t) val;
622 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
623 }
624
625 return ret;
626 }
627
628 /**
629 * @brief High-performance operating mode for accelerometer.[get]
630 *
631 * @param ctx Read / write interface definitions
632 * @param val Get the values of xl_hm_mode in reg CTRL6_C
633 * @retval Interface status (MANDATORY: return 0 -> no Error).
634 *
635 */
lsm6dsm_xl_power_mode_get(const stmdev_ctx_t * ctx,lsm6dsm_xl_hm_mode_t * val)636 int32_t lsm6dsm_xl_power_mode_get(const stmdev_ctx_t *ctx,
637 lsm6dsm_xl_hm_mode_t *val)
638 {
639 lsm6dsm_ctrl6_c_t ctrl6_c;
640 int32_t ret;
641
642 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
643
644 switch (ctrl6_c.xl_hm_mode)
645 {
646 case LSM6DSM_XL_HIGH_PERFORMANCE:
647 *val = LSM6DSM_XL_HIGH_PERFORMANCE;
648 break;
649
650 case LSM6DSM_XL_NORMAL:
651 *val = LSM6DSM_XL_NORMAL;
652 break;
653
654 default:
655 *val = LSM6DSM_XL_HIGH_PERFORMANCE;
656 break;
657 }
658
659 return ret;
660 }
661
662 /**
663 * @brief Source register rounding function on WAKE_UP_SRC (1Bh),
664 * TAP_SRC (1Ch), D6D_SRC (1Dh), STATUS_REG (1Eh) and
665 * FUNC_SRC1 (53h) registers in the primary interface.[set]
666 *
667 * @param ctx Read / write interface definitions
668 * @param val Change the values of rounding_status in reg CTRL7_G
669 * @retval Interface status (MANDATORY: return 0 -> no Error).
670 *
671 */
lsm6dsm_rounding_on_status_set(const stmdev_ctx_t * ctx,lsm6dsm_rounding_status_t val)672 int32_t lsm6dsm_rounding_on_status_set(const stmdev_ctx_t *ctx,
673 lsm6dsm_rounding_status_t val)
674 {
675 lsm6dsm_ctrl7_g_t ctrl7_g;
676 int32_t ret;
677
678 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
679
680 if (ret == 0)
681 {
682 ctrl7_g.rounding_status = (uint8_t) val;
683 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
684 }
685
686 return ret;
687 }
688
689 /**
690 * @brief Source register rounding function on WAKE_UP_SRC (1Bh),
691 * TAP_SRC (1Ch), D6D_SRC (1Dh), STATUS_REG (1Eh) and
692 * FUNC_SRC1 (53h) registers in the primary interface.[get]
693 *
694 * @param ctx Read / write interface definitions
695 * @param val Get the values of rounding_status in reg CTRL7_G
696 * @retval Interface status (MANDATORY: return 0 -> no Error).
697 *
698 */
lsm6dsm_rounding_on_status_get(const stmdev_ctx_t * ctx,lsm6dsm_rounding_status_t * val)699 int32_t lsm6dsm_rounding_on_status_get(const stmdev_ctx_t *ctx,
700 lsm6dsm_rounding_status_t *val)
701 {
702 lsm6dsm_ctrl7_g_t ctrl7_g;
703 int32_t ret;
704
705 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
706
707 switch (ctrl7_g.rounding_status)
708 {
709 case LSM6DSM_STAT_RND_DISABLE:
710 *val = LSM6DSM_STAT_RND_DISABLE;
711 break;
712
713 case LSM6DSM_STAT_RND_ENABLE:
714 *val = LSM6DSM_STAT_RND_ENABLE;
715 break;
716
717 default:
718 *val = LSM6DSM_STAT_RND_DISABLE;
719 break;
720 }
721
722 return ret;
723 }
724
725 /**
726 * @brief High-performance operating mode disable for gyroscope.[set]
727 *
728 * @param ctx Read / write interface definitions
729 * @param val Change the values of g_hm_mode in reg CTRL7_G
730 * @retval Interface status (MANDATORY: return 0 -> no Error).
731 *
732 */
lsm6dsm_gy_power_mode_set(const stmdev_ctx_t * ctx,lsm6dsm_g_hm_mode_t val)733 int32_t lsm6dsm_gy_power_mode_set(const stmdev_ctx_t *ctx,
734 lsm6dsm_g_hm_mode_t val)
735 {
736 lsm6dsm_ctrl7_g_t ctrl7_g;
737 int32_t ret;
738
739 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
740
741 if (ret == 0)
742 {
743 ctrl7_g.g_hm_mode = (uint8_t) val;
744 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
745 }
746
747 return ret;
748 }
749
750 /**
751 * @brief High-performance operating mode disable for gyroscope.[get]
752 *
753 * @param ctx Read / write interface definitions
754 * @param val Get the values of g_hm_mode in reg CTRL7_G
755 * @retval Interface status (MANDATORY: return 0 -> no Error).
756 *
757 */
lsm6dsm_gy_power_mode_get(const stmdev_ctx_t * ctx,lsm6dsm_g_hm_mode_t * val)758 int32_t lsm6dsm_gy_power_mode_get(const stmdev_ctx_t *ctx,
759 lsm6dsm_g_hm_mode_t *val)
760 {
761 lsm6dsm_ctrl7_g_t ctrl7_g;
762 int32_t ret;
763
764 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
765
766 switch (ctrl7_g.g_hm_mode)
767 {
768 case LSM6DSM_GY_HIGH_PERFORMANCE:
769 *val = LSM6DSM_GY_HIGH_PERFORMANCE;
770 break;
771
772 case LSM6DSM_GY_NORMAL:
773 *val = LSM6DSM_GY_NORMAL;
774 break;
775
776 default:
777 *val = LSM6DSM_GY_HIGH_PERFORMANCE;
778 break;
779 }
780
781 return ret;
782 }
783
784 /**
785 * @brief Read all the interrupt/status flag of the device.[get]
786 *
787 * @param ctx Read / write interface definitions
788 * @param val WAKE_UP_SRC, TAP_SRC, D6D_SRC, STATUS_REG,
789 * FUNC_SRC1, FUNC_SRC2, WRIST_TILT_IA, A_WRIST_TILT_Mask
790 * @retval Interface status (MANDATORY: return 0 -> no Error).
791 *
792 */
lsm6dsm_all_sources_get(const stmdev_ctx_t * ctx,lsm6dsm_all_sources_t * val)793 int32_t lsm6dsm_all_sources_get(const stmdev_ctx_t *ctx,
794 lsm6dsm_all_sources_t *val)
795 {
796 int32_t ret;
797
798 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_SRC,
799 (uint8_t *) & (val->wake_up_src), 1);
800
801 if (ret == 0)
802 {
803 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_SRC,
804 (uint8_t *) & (val->tap_src), 1);
805 }
806
807 if (ret == 0)
808 {
809 ret = lsm6dsm_read_reg(ctx, LSM6DSM_D6D_SRC,
810 (uint8_t *) & (val->d6d_src), 1);
811 }
812
813 if (ret == 0)
814 {
815 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG,
816 (uint8_t *) & (val->status_reg), 1);
817 }
818
819 if (ret == 0)
820 {
821 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FUNC_SRC1,
822 (uint8_t *) & (val->func_src1), 1);
823 }
824
825 if (ret == 0)
826 {
827 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FUNC_SRC2,
828 (uint8_t *) & (val->func_src2), 1);
829 }
830
831 if (ret == 0)
832 {
833 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WRIST_TILT_IA,
834 (uint8_t *) & (val->wrist_tilt_ia), 1);
835 }
836
837 if (ret == 0)
838 {
839 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
840 }
841
842 if (ret == 0)
843 {
844 ret = lsm6dsm_read_reg(ctx, LSM6DSM_A_WRIST_TILT_MASK,
845 (uint8_t *) & (val->a_wrist_tilt_mask), 1);
846 }
847
848 if (ret == 0)
849 {
850 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
851 }
852
853 return ret;
854 }
855 /**
856 * @brief The STATUS_REG register is read by the primary interface[get]
857 *
858 * @param ctx Read / write interface definitions
859 * @param val Registers STATUS_REG
860 * @retval Interface status (MANDATORY: return 0 -> no Error).
861 *
862 */
lsm6dsm_status_reg_get(const stmdev_ctx_t * ctx,lsm6dsm_status_reg_t * val)863 int32_t lsm6dsm_status_reg_get(const stmdev_ctx_t *ctx,
864 lsm6dsm_status_reg_t *val)
865 {
866 int32_t ret;
867
868 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG, (uint8_t *) val, 1);
869
870 return ret;
871 }
872
873 /**
874 * @brief Accelerometer new data available.[get]
875 *
876 * @param ctx Read / write interface definitions
877 * @param val Change the values of xlda in reg STATUS_REG
878 * @retval Interface status (MANDATORY: return 0 -> no Error).
879 *
880 */
lsm6dsm_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)881 int32_t lsm6dsm_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
882 uint8_t *val)
883 {
884 lsm6dsm_status_reg_t status_reg;
885 int32_t ret;
886
887 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG,
888 (uint8_t *)&status_reg, 1);
889 *val = status_reg.xlda;
890
891 return ret;
892 }
893
894 /**
895 * @brief Gyroscope new data available.[get]
896 *
897 * @param ctx Read / write interface definitions
898 * @param val Change the values of gda in reg STATUS_REG
899 * @retval Interface status (MANDATORY: return 0 -> no Error).
900 *
901 */
lsm6dsm_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)902 int32_t lsm6dsm_gy_flag_data_ready_get(const stmdev_ctx_t *ctx,
903 uint8_t *val)
904 {
905 lsm6dsm_status_reg_t status_reg;
906 int32_t ret;
907
908 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG,
909 (uint8_t *)&status_reg, 1);
910 *val = status_reg.gda;
911
912 return ret;
913 }
914
915 /**
916 * @brief Temperature new data available.[get]
917 *
918 * @param ctx Read / write interface definitions
919 * @param val Change the values of tda in reg STATUS_REG
920 * @retval Interface status (MANDATORY: return 0 -> no Error).
921 *
922 */
lsm6dsm_temp_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)923 int32_t lsm6dsm_temp_flag_data_ready_get(const stmdev_ctx_t *ctx,
924 uint8_t *val)
925 {
926 lsm6dsm_status_reg_t status_reg;
927 int32_t ret;
928
929 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_REG,
930 (uint8_t *)&status_reg, 1);
931 *val = status_reg.tda;
932
933 return ret;
934 }
935
936 /**
937 * @brief Accelerometer axis user offset correction expressed in two’s
938 * complement, weight depends on USR_OFF_W in CTRL6_C.
939 * The value must be in the range [-127 127].[set]
940 *
941 * @param ctx Read / write interface definitions
942 * @param buff Buffer that contains data to write
943 * @retval Interface status (MANDATORY: return 0 -> no Error).
944 *
945 */
lsm6dsm_xl_usr_offset_set(const stmdev_ctx_t * ctx,uint8_t * buff)946 int32_t lsm6dsm_xl_usr_offset_set(const stmdev_ctx_t *ctx, uint8_t *buff)
947 {
948 int32_t ret;
949
950 ret = lsm6dsm_write_reg(ctx, LSM6DSM_X_OFS_USR, buff, 3);
951
952 return ret;
953 }
954
955 /**
956 * @brief Accelerometer axis user offset correction xpressed in two’s
957 * complement, weight depends on USR_OFF_W in CTRL6_C.
958 * The value must be in the range [-127 127].[get]
959 *
960 * @param ctx Read / write interface definitions
961 * @param buff Buffer that stores data read
962 * @retval Interface status (MANDATORY: return 0 -> no Error).
963 *
964 */
lsm6dsm_xl_usr_offset_get(const stmdev_ctx_t * ctx,uint8_t * buff)965 int32_t lsm6dsm_xl_usr_offset_get(const stmdev_ctx_t *ctx, uint8_t *buff)
966 {
967 int32_t ret;
968
969 ret = lsm6dsm_read_reg(ctx, LSM6DSM_X_OFS_USR, buff, 3);
970
971 return ret;
972 }
973
974 /**
975 * @}
976 *
977 */
978
979 /**
980 * @defgroup LSM6DSM_Timestamp
981 * @brief This section groups all the functions that manage the
982 * timestamp generation.
983 * @{
984 *
985 */
986
987 /**
988 * @brief Enable timestamp count. The count is saved in TIMESTAMP0_REG (40h),
989 * TIMESTAMP1_REG (41h) and TIMESTAMP2_REG (42h).[set]
990 *
991 * @param ctx Read / write interface definitions
992 * @param val Change the values of timer_en in reg CTRL10_C
993 * @retval Interface status (MANDATORY: return 0 -> no Error).
994 *
995 */
lsm6dsm_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)996 int32_t lsm6dsm_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
997 {
998 lsm6dsm_ctrl10_c_t ctrl10_c;
999 int32_t ret;
1000
1001 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1002
1003 if (ret == 0)
1004 {
1005 ctrl10_c.timer_en = val;
1006
1007 if (val != 0x00U)
1008 {
1009 ctrl10_c.func_en = val;
1010 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1011 }
1012 }
1013
1014 return ret;
1015 }
1016
1017 /**
1018 * @brief Enable timestamp count. The count is saved in TIMESTAMP0_REG (40h),
1019 * TIMESTAMP1_REG (41h) and TIMESTAMP2_REG (42h).[get]
1020 *
1021 * @param ctx Read / write interface definitions
1022 * @param val Change the values of timer_en in reg CTRL10_C
1023 * @retval Interface status (MANDATORY: return 0 -> no Error).
1024 *
1025 */
lsm6dsm_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)1026 int32_t lsm6dsm_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
1027 {
1028 lsm6dsm_ctrl10_c_t ctrl10_c;
1029 int32_t ret;
1030
1031 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1032 *val = ctrl10_c.timer_en;
1033
1034 return ret;
1035 }
1036
1037 /**
1038 * @brief Timestamp register resolution setting.
1039 * Configuration of this bit affects
1040 * TIMESTAMP0_REG(40h), TIMESTAMP1_REG(41h),
1041 * TIMESTAMP2_REG(42h), STEP_TIMESTAMP_L(49h),
1042 * STEP_TIMESTAMP_H(4Ah) and
1043 * STEP_COUNT_DELTA(15h) registers.[set]
1044 *
1045 * @param ctx Read / write interface definitions
1046 * @param val Change the values of timer_hr in reg WAKE_UP_DUR
1047 * @retval Interface status (MANDATORY: return 0 -> no Error).
1048 *
1049 */
lsm6dsm_timestamp_res_set(const stmdev_ctx_t * ctx,lsm6dsm_timer_hr_t val)1050 int32_t lsm6dsm_timestamp_res_set(const stmdev_ctx_t *ctx,
1051 lsm6dsm_timer_hr_t val)
1052 {
1053 lsm6dsm_wake_up_dur_t wake_up_dur;
1054 int32_t ret;
1055
1056 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
1057 (uint8_t *)&wake_up_dur, 1);
1058
1059 if (ret == 0)
1060 {
1061 wake_up_dur.timer_hr = (uint8_t) val;
1062 ret = lsm6dsm_write_reg(ctx, LSM6DSM_WAKE_UP_DUR,
1063 (uint8_t *)&wake_up_dur, 1);
1064 }
1065
1066 return ret;
1067 }
1068
1069 /**
1070 * @brief Timestamp register resolution setting.
1071 * Configuration of this bit affects
1072 * TIMESTAMP0_REG(40h), TIMESTAMP1_REG(41h),
1073 * TIMESTAMP2_REG(42h), STEP_TIMESTAMP_L(49h),
1074 * STEP_TIMESTAMP_H(4Ah) and
1075 * STEP_COUNT_DELTA(15h) registers.[get]
1076 *
1077 * @param ctx Read / write interface definitions
1078 * @param val Get the values of timer_hr in reg WAKE_UP_DUR
1079 * @retval Interface status (MANDATORY: return 0 -> no Error).
1080 *
1081 */
lsm6dsm_timestamp_res_get(const stmdev_ctx_t * ctx,lsm6dsm_timer_hr_t * val)1082 int32_t lsm6dsm_timestamp_res_get(const stmdev_ctx_t *ctx,
1083 lsm6dsm_timer_hr_t *val)
1084 {
1085 lsm6dsm_wake_up_dur_t wake_up_dur;
1086 int32_t ret;
1087
1088 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
1089 (uint8_t *)&wake_up_dur, 1);
1090
1091 switch (wake_up_dur.timer_hr)
1092 {
1093 case LSM6DSM_LSB_6ms4:
1094 *val = LSM6DSM_LSB_6ms4;
1095 break;
1096
1097 case LSM6DSM_LSB_25us:
1098 *val = LSM6DSM_LSB_25us;
1099 break;
1100
1101 default:
1102 *val = LSM6DSM_LSB_6ms4;
1103 break;
1104 }
1105
1106 return ret;
1107 }
1108
1109 /**
1110 * @}
1111 *
1112 */
1113
1114 /**
1115 * @defgroup LSM6DSM_Dataoutput
1116 * @brief This section groups all the data output functions.
1117 * @{
1118 *
1119 */
1120
1121 /**
1122 * @brief Circular burst-mode (rounding) read from output registers
1123 * through the primary interface.[set]
1124 *
1125 * @param ctx Read / write interface definitions
1126 * @param val Change the values of rounding in reg CTRL5_C
1127 * @retval Interface status (MANDATORY: return 0 -> no Error).
1128 *
1129 */
lsm6dsm_rounding_mode_set(const stmdev_ctx_t * ctx,lsm6dsm_rounding_t val)1130 int32_t lsm6dsm_rounding_mode_set(const stmdev_ctx_t *ctx,
1131 lsm6dsm_rounding_t val)
1132 {
1133 lsm6dsm_ctrl5_c_t ctrl5_c;
1134 int32_t ret;
1135
1136 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1137
1138 if (ret == 0)
1139 {
1140 ctrl5_c.rounding = (uint8_t) val;
1141 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1142 }
1143
1144 return ret;
1145 }
1146
1147 /**
1148 * @brief Circular burst-mode (rounding) read from output registers
1149 * through the primary interface.[get]
1150 *
1151 * @param ctx Read / write interface definitions
1152 * @param val Get the values of rounding in reg CTRL5_C
1153 * @retval Interface status (MANDATORY: return 0 -> no Error).
1154 *
1155 */
lsm6dsm_rounding_mode_get(const stmdev_ctx_t * ctx,lsm6dsm_rounding_t * val)1156 int32_t lsm6dsm_rounding_mode_get(const stmdev_ctx_t *ctx,
1157 lsm6dsm_rounding_t *val)
1158 {
1159 lsm6dsm_ctrl5_c_t ctrl5_c;
1160 int32_t ret;
1161
1162 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1163
1164 switch (ctrl5_c.rounding)
1165 {
1166 case LSM6DSM_ROUND_DISABLE:
1167 *val = LSM6DSM_ROUND_DISABLE;
1168 break;
1169
1170 case LSM6DSM_ROUND_XL:
1171 *val = LSM6DSM_ROUND_XL;
1172 break;
1173
1174 case LSM6DSM_ROUND_GY:
1175 *val = LSM6DSM_ROUND_GY;
1176 break;
1177
1178 case LSM6DSM_ROUND_GY_XL:
1179 *val = LSM6DSM_ROUND_GY_XL;
1180 break;
1181
1182 case LSM6DSM_ROUND_SH1_TO_SH6:
1183 *val = LSM6DSM_ROUND_SH1_TO_SH6;
1184 break;
1185
1186 case LSM6DSM_ROUND_XL_SH1_TO_SH6:
1187 *val = LSM6DSM_ROUND_XL_SH1_TO_SH6;
1188 break;
1189
1190 case LSM6DSM_ROUND_GY_XL_SH1_TO_SH12:
1191 *val = LSM6DSM_ROUND_GY_XL_SH1_TO_SH12;
1192 break;
1193
1194 case LSM6DSM_ROUND_GY_XL_SH1_TO_SH6:
1195 *val = LSM6DSM_ROUND_GY_XL_SH1_TO_SH6;
1196 break;
1197
1198 default:
1199 *val = LSM6DSM_ROUND_DISABLE;
1200 break;
1201 }
1202
1203 return ret;
1204 }
1205
1206 /**
1207 * @brief Temperature data output register (r). L and H registers together
1208 * express a 16-bit word in two’s complement.[get]
1209 *
1210 * @param ctx Read / write interface definitions
1211 * @param buff Buffer that stores data read
1212 * @retval Interface status (MANDATORY: return 0 -> no Error).
1213 *
1214 */
lsm6dsm_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1215 int32_t lsm6dsm_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1216 {
1217 uint8_t buff[2];
1218 int32_t ret;
1219
1220 ret = lsm6dsm_read_reg(ctx, LSM6DSM_OUT_TEMP_L, buff, 2);
1221 val[0] = (int16_t)buff[1];
1222 val[0] = (val[0] * 256) + (int16_t)buff[0];
1223
1224 return ret;
1225 }
1226
1227 /**
1228 * @brief Angular rate sensor. The value is expressed as a 16-bit word in
1229 * two’s complement.[get]
1230 *
1231 * @param ctx Read / write interface definitions
1232 * @param buff Buffer that stores data read
1233 * @retval Interface status (MANDATORY: return 0 -> no Error).
1234 *
1235 */
lsm6dsm_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1236 int32_t lsm6dsm_angular_rate_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1237 {
1238 uint8_t buff[6];
1239 int32_t ret;
1240
1241 ret = lsm6dsm_read_reg(ctx, LSM6DSM_OUTX_L_G, buff, 6);
1242 val[0] = (int16_t)buff[1];
1243 val[0] = (val[0] * 256) + (int16_t)buff[0];
1244 val[1] = (int16_t)buff[3];
1245 val[1] = (val[1] * 256) + (int16_t)buff[2];
1246 val[2] = (int16_t)buff[5];
1247 val[2] = (val[2] * 256) + (int16_t)buff[4];
1248
1249 return ret;
1250 }
1251
1252 /**
1253 * @brief Linear acceleration output register. The value is expressed
1254 * as a 16-bit word in two’s complement.[get]
1255 *
1256 * @param ctx Read / write interface definitions
1257 * @param buff Buffer that stores data read
1258 * @retval Interface status (MANDATORY: return 0 -> no Error).
1259 *
1260 */
lsm6dsm_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1261 int32_t lsm6dsm_acceleration_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1262 {
1263 uint8_t buff[6];
1264 int32_t ret;
1265
1266 ret = lsm6dsm_read_reg(ctx, LSM6DSM_OUTX_L_XL, buff, 6);
1267 val[0] = (int16_t)buff[1];
1268 val[0] = (val[0] * 256) + (int16_t)buff[0];
1269 val[1] = (int16_t)buff[3];
1270 val[1] = (val[1] * 256) + (int16_t)buff[2];
1271 val[2] = (int16_t)buff[5];
1272 val[2] = (val[2] * 256) + (int16_t)buff[4];
1273
1274 return ret;
1275 }
1276
1277 /**
1278 * @brief External magnetometer raw data.[get]
1279 *
1280 * @param ctx Read / write interface definitions
1281 * @param buff Buffer that stores data read
1282 * @retval Interface status (MANDATORY: return 0 -> no Error).
1283 *
1284 */
lsm6dsm_mag_calibrated_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1285 int32_t lsm6dsm_mag_calibrated_raw_get(const stmdev_ctx_t *ctx,
1286 int16_t *val)
1287 {
1288 uint8_t buff[6];
1289 int32_t ret;
1290
1291 ret = lsm6dsm_read_reg(ctx, LSM6DSM_OUT_MAG_RAW_X_L, buff, 6);
1292 val[0] = (int16_t)buff[1];
1293 val[0] = (val[0] * 256) + (int16_t)buff[0];
1294 val[1] = (int16_t)buff[3];
1295 val[1] = (val[1] * 256) + (int16_t)buff[2];
1296 val[2] = (int16_t)buff[5];
1297 val[2] = (val[2] * 256) + (int16_t)buff[4];
1298
1299 return ret;
1300 }
1301
1302 /**
1303 * @brief Read data in FIFO.[get]
1304 *
1305 * @param ctx Read / write interface definitions
1306 * @param buffer Data buffer to store FIFO data.
1307 * @param len Number of data to read from FIFO.
1308 * @retval Interface status (MANDATORY: return 0 -> no Error).
1309 *
1310 */
lsm6dsm_fifo_raw_data_get(const stmdev_ctx_t * ctx,uint8_t * buffer,uint8_t len)1311 int32_t lsm6dsm_fifo_raw_data_get(const stmdev_ctx_t *ctx, uint8_t *buffer,
1312 uint8_t len)
1313 {
1314 int32_t ret;
1315
1316 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_DATA_OUT_L, buffer, len);
1317
1318 return ret;
1319 }
1320
1321 /**
1322 * @}
1323 *
1324 */
1325
1326 /**
1327 * @defgroup LSM6DSM_common
1328 * @brief This section groups common useful functions.
1329 * @{
1330 *
1331 */
1332
1333 /**
1334 * @brief Enable access to the embedded functions/sensor hub
1335 * configuration registers[set]
1336 *
1337 * @param ctx Read / write interface definitions
1338 * @param val Change the values of func_cfg_en in reg FUNC_CFG_ACCESS
1339 * @retval Interface status (MANDATORY: return 0 -> no Error).
1340 *
1341 */
lsm6dsm_mem_bank_set(const stmdev_ctx_t * ctx,lsm6dsm_func_cfg_en_t val)1342 int32_t lsm6dsm_mem_bank_set(const stmdev_ctx_t *ctx,
1343 lsm6dsm_func_cfg_en_t val)
1344 {
1345 lsm6dsm_func_cfg_access_t func_cfg_access;
1346 int32_t ret;
1347
1348 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FUNC_CFG_ACCESS,
1349 (uint8_t *)&func_cfg_access, 1);
1350
1351 if (ret == 0)
1352 {
1353 func_cfg_access.func_cfg_en = (uint8_t) val;
1354 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FUNC_CFG_ACCESS,
1355 (uint8_t *)&func_cfg_access, 1);
1356 }
1357
1358 return ret;
1359 }
1360
1361 /**
1362 * @brief Enable access to the embedded functions/sensor hub configuration
1363 * registers[get]
1364 *
1365 * @param ctx Read / write interface definitions
1366 * @param val Get the values of func_cfg_en in reg FUNC_CFG_ACCESS
1367 * @retval Interface status (MANDATORY: return 0 -> no Error).
1368 *
1369 */
lsm6dsm_mem_bank_get(const stmdev_ctx_t * ctx,lsm6dsm_func_cfg_en_t * val)1370 int32_t lsm6dsm_mem_bank_get(const stmdev_ctx_t *ctx,
1371 lsm6dsm_func_cfg_en_t *val)
1372 {
1373 lsm6dsm_func_cfg_access_t func_cfg_access;
1374 int32_t ret;
1375
1376 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FUNC_CFG_ACCESS,
1377 (uint8_t *)&func_cfg_access, 1);
1378
1379 switch (func_cfg_access.func_cfg_en)
1380 {
1381 case LSM6DSM_USER_BANK:
1382 *val = LSM6DSM_USER_BANK;
1383 break;
1384
1385 case LSM6DSM_BANK_B:
1386 *val = LSM6DSM_BANK_B;
1387 break;
1388
1389 default:
1390 *val = LSM6DSM_USER_BANK;
1391 break;
1392 }
1393
1394 return ret;
1395 }
1396
1397 /**
1398 * @brief Data-ready pulsed / letched mode[set]
1399 *
1400 * @param ctx Read / write interface definitions
1401 * @param val Change the values of drdy_pulsed in reg DRDY_PULSE_CFG
1402 * @retval Interface status (MANDATORY: return 0 -> no Error).
1403 *
1404 */
lsm6dsm_data_ready_mode_set(const stmdev_ctx_t * ctx,lsm6dsm_drdy_pulsed_g_t val)1405 int32_t lsm6dsm_data_ready_mode_set(const stmdev_ctx_t *ctx,
1406 lsm6dsm_drdy_pulsed_g_t val)
1407 {
1408 lsm6dsm_drdy_pulse_cfg_t drdy_pulse_cfg;
1409 int32_t ret;
1410
1411 ret = lsm6dsm_read_reg(ctx, LSM6DSM_DRDY_PULSE_CFG,
1412 (uint8_t *)&drdy_pulse_cfg, 1);
1413
1414 if (ret == 0)
1415 {
1416 drdy_pulse_cfg.drdy_pulsed = (uint8_t) val;
1417 ret = lsm6dsm_write_reg(ctx, LSM6DSM_DRDY_PULSE_CFG,
1418 (uint8_t *)&drdy_pulse_cfg, 1);
1419 }
1420
1421 return ret;
1422 }
1423
1424 /**
1425 * @brief Data-ready pulsed / letched mode[get]
1426 *
1427 * @param ctx Read / write interface definitions
1428 * @param val Get the values of drdy_pulsed in reg DRDY_PULSE_CFG
1429 * @retval Interface status (MANDATORY: return 0 -> no Error).
1430 *
1431 */
lsm6dsm_data_ready_mode_get(const stmdev_ctx_t * ctx,lsm6dsm_drdy_pulsed_g_t * val)1432 int32_t lsm6dsm_data_ready_mode_get(const stmdev_ctx_t *ctx,
1433 lsm6dsm_drdy_pulsed_g_t *val)
1434 {
1435 lsm6dsm_drdy_pulse_cfg_t drdy_pulse_cfg;
1436 int32_t ret;
1437
1438 ret = lsm6dsm_read_reg(ctx, LSM6DSM_DRDY_PULSE_CFG,
1439 (uint8_t *)&drdy_pulse_cfg, 1);
1440
1441 switch (drdy_pulse_cfg.drdy_pulsed)
1442 {
1443 case LSM6DSM_DRDY_LATCHED:
1444 *val = LSM6DSM_DRDY_LATCHED;
1445 break;
1446
1447 case LSM6DSM_DRDY_PULSED:
1448 *val = LSM6DSM_DRDY_PULSED;
1449 break;
1450
1451 default:
1452 *val = LSM6DSM_DRDY_LATCHED;
1453 break;
1454 }
1455
1456 return ret;
1457 }
1458
1459 /**
1460 * @brief DeviceWhoamI.[get]
1461 *
1462 * @param ctx Read / write interface definitions
1463 * @param buff Buffer that stores data read
1464 * @retval Interface status (MANDATORY: return 0 -> no Error).
1465 *
1466 */
lsm6dsm_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)1467 int32_t lsm6dsm_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1468 {
1469 int32_t ret;
1470
1471 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WHO_AM_I, buff, 1);
1472
1473 return ret;
1474 }
1475
1476 /**
1477 * @brief Software reset. Restore the default values in user registers[set]
1478 *
1479 * @param ctx Read / write interface definitions
1480 * @param val Change the values of sw_reset in reg CTRL3_C
1481 * @retval Interface status (MANDATORY: return 0 -> no Error).
1482 *
1483 */
lsm6dsm_reset_set(const stmdev_ctx_t * ctx,uint8_t val)1484 int32_t lsm6dsm_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
1485 {
1486 lsm6dsm_ctrl3_c_t ctrl3_c;
1487 int32_t ret;
1488
1489 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1490
1491 if (ret == 0)
1492 {
1493 ctrl3_c.sw_reset = val;
1494 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1495 }
1496
1497 return ret;
1498 }
1499
1500 /**
1501 * @brief Software reset. Restore the default values in user registers[get]
1502 *
1503 * @param ctx Read / write interface definitions
1504 * @param val Change the values of sw_reset in reg CTRL3_C
1505 * @retval Interface status (MANDATORY: return 0 -> no Error).
1506 *
1507 */
lsm6dsm_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)1508 int32_t lsm6dsm_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
1509 {
1510 lsm6dsm_ctrl3_c_t ctrl3_c;
1511 int32_t ret;
1512
1513 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1514 *val = ctrl3_c.sw_reset;
1515
1516 return ret;
1517 }
1518
1519 /**
1520 * @brief Big/Little Endian Data selection.[set]
1521 *
1522 * @param ctx Read / write interface definitions
1523 * @param val Change the values of ble in reg CTRL3_C
1524 * @retval Interface status (MANDATORY: return 0 -> no Error).
1525 *
1526 */
lsm6dsm_data_format_set(const stmdev_ctx_t * ctx,lsm6dsm_ble_t val)1527 int32_t lsm6dsm_data_format_set(const stmdev_ctx_t *ctx, lsm6dsm_ble_t val)
1528 {
1529 lsm6dsm_ctrl3_c_t ctrl3_c;
1530 int32_t ret;
1531
1532 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1533
1534 if (ret == 0)
1535 {
1536 ctrl3_c.ble = (uint8_t) val;
1537 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1538 }
1539
1540 return ret;
1541 }
1542
1543 /**
1544 * @brief Big/Little Endian Data selection.[get]
1545 *
1546 * @param ctx Read / write interface definitions
1547 * @param val Get the values of ble in reg CTRL3_C
1548 * @retval Interface status (MANDATORY: return 0 -> no Error).
1549 *
1550 */
lsm6dsm_data_format_get(const stmdev_ctx_t * ctx,lsm6dsm_ble_t * val)1551 int32_t lsm6dsm_data_format_get(const stmdev_ctx_t *ctx, lsm6dsm_ble_t *val)
1552 {
1553 lsm6dsm_ctrl3_c_t ctrl3_c;
1554 int32_t ret;
1555
1556 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1557
1558 switch (ctrl3_c.ble)
1559 {
1560 case LSM6DSM_LSB_AT_LOW_ADD:
1561 *val = LSM6DSM_LSB_AT_LOW_ADD;
1562 break;
1563
1564 case LSM6DSM_MSB_AT_LOW_ADD:
1565 *val = LSM6DSM_MSB_AT_LOW_ADD;
1566 break;
1567
1568 default:
1569 *val = LSM6DSM_LSB_AT_LOW_ADD;
1570 break;
1571 }
1572
1573 return ret;
1574 }
1575
1576 /**
1577 * @brief Register address automatically incremented during a multiple byte
1578 * access with a serial interface.[set]
1579 *
1580 * @param ctx Read / write interface definitions
1581 * @param val Change the values of if_inc in reg CTRL3_C
1582 * @retval Interface status (MANDATORY: return 0 -> no Error).
1583 *
1584 */
lsm6dsm_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)1585 int32_t lsm6dsm_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
1586 {
1587 lsm6dsm_ctrl3_c_t ctrl3_c;
1588 int32_t ret;
1589
1590 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1591
1592 if (ret == 0)
1593 {
1594 ctrl3_c.if_inc = val;
1595 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1596 }
1597
1598 return ret;
1599 }
1600
1601 /**
1602 * @brief Register address automatically incremented during a multiple byte
1603 * access with a serial interface.[get]
1604 *
1605 * @param ctx Read / write interface definitions
1606 * @param val Change the values of if_inc in reg CTRL3_C
1607 * @retval Interface status (MANDATORY: return 0 -> no Error).
1608 *
1609 */
lsm6dsm_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)1610 int32_t lsm6dsm_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val)
1611 {
1612 lsm6dsm_ctrl3_c_t ctrl3_c;
1613 int32_t ret;
1614
1615 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1616 *val = ctrl3_c.if_inc;
1617
1618 return ret;
1619 }
1620
1621 /**
1622 * @brief Reboot memory content. Reload the calibration parameters.[set]
1623 *
1624 * @param ctx Read / write interface definitions
1625 * @param val Change the values of boot in reg CTRL3_C
1626 * @retval Interface status (MANDATORY: return 0 -> no Error).
1627 *
1628 */
lsm6dsm_boot_set(const stmdev_ctx_t * ctx,uint8_t val)1629 int32_t lsm6dsm_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
1630 {
1631 lsm6dsm_ctrl3_c_t ctrl3_c;
1632 int32_t ret;
1633
1634 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1635
1636 if (ret == 0)
1637 {
1638 ctrl3_c.boot = val;
1639 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1640 }
1641
1642 return ret;
1643 }
1644
1645 /**
1646 * @brief Reboot memory content. Reload the calibration parameters.[get]
1647 *
1648 * @param ctx Read / write interface definitions
1649 * @param val Change the values of boot in reg CTRL3_C
1650 * @retval Interface status (MANDATORY: return 0 -> no Error).
1651 *
1652 */
lsm6dsm_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)1653 int32_t lsm6dsm_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
1654 {
1655 lsm6dsm_ctrl3_c_t ctrl3_c;
1656 int32_t ret;
1657
1658 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1659 *val = ctrl3_c.boot;
1660
1661 return ret;
1662 }
1663
1664 /**
1665 * @brief Linear acceleration sensor self-test enable.[set]
1666 *
1667 * @param ctx Read / write interface definitions
1668 * @param val Change the values of st_xl in reg CTRL5_C
1669 * @retval Interface status (MANDATORY: return 0 -> no Error).
1670 *
1671 */
lsm6dsm_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6dsm_st_xl_t val)1672 int32_t lsm6dsm_xl_self_test_set(const stmdev_ctx_t *ctx,
1673 lsm6dsm_st_xl_t val)
1674 {
1675 lsm6dsm_ctrl5_c_t ctrl5_c;
1676 int32_t ret;
1677
1678 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1679
1680 if (ret == 0)
1681 {
1682 ctrl5_c.st_xl = (uint8_t) val;
1683 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1684 }
1685
1686 return ret;
1687 }
1688
1689 /**
1690 * @brief Linear acceleration sensor self-test enable.[get]
1691 *
1692 * @param ctx Read / write interface definitions
1693 * @param val Get the values of st_xl in reg CTRL5_C
1694 * @retval Interface status (MANDATORY: return 0 -> no Error).
1695 *
1696 */
lsm6dsm_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6dsm_st_xl_t * val)1697 int32_t lsm6dsm_xl_self_test_get(const stmdev_ctx_t *ctx,
1698 lsm6dsm_st_xl_t *val)
1699 {
1700 lsm6dsm_ctrl5_c_t ctrl5_c;
1701 int32_t ret;
1702
1703 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1704
1705 switch (ctrl5_c.st_xl)
1706 {
1707 case LSM6DSM_XL_ST_DISABLE:
1708 *val = LSM6DSM_XL_ST_DISABLE;
1709 break;
1710
1711 case LSM6DSM_XL_ST_POSITIVE:
1712 *val = LSM6DSM_XL_ST_POSITIVE;
1713 break;
1714
1715 case LSM6DSM_XL_ST_NEGATIVE:
1716 *val = LSM6DSM_XL_ST_NEGATIVE;
1717 break;
1718
1719 default:
1720 *val = LSM6DSM_XL_ST_DISABLE;
1721 break;
1722 }
1723
1724 return ret;
1725 }
1726
1727 /**
1728 * @brief Angular rate sensor self-test enable.[set]
1729 *
1730 * @param ctx Read / write interface definitions
1731 * @param val Change the values of st_g in reg CTRL5_C
1732 * @retval Interface status (MANDATORY: return 0 -> no Error).
1733 *
1734 */
lsm6dsm_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dsm_st_g_t val)1735 int32_t lsm6dsm_gy_self_test_set(const stmdev_ctx_t *ctx,
1736 lsm6dsm_st_g_t val)
1737 {
1738 lsm6dsm_ctrl5_c_t ctrl5_c;
1739 int32_t ret;
1740
1741 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1742
1743 if (ret == 0)
1744 {
1745 ctrl5_c.st_g = (uint8_t) val;
1746 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1747 }
1748
1749 return ret;
1750 }
1751
1752 /**
1753 * @brief Angular rate sensor self-test enable.[get]
1754 *
1755 * @param ctx Read / write interface definitions
1756 * @param val Get the values of st_g in reg CTRL5_C
1757 * @retval Interface status (MANDATORY: return 0 -> no Error).
1758 *
1759 */
lsm6dsm_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dsm_st_g_t * val)1760 int32_t lsm6dsm_gy_self_test_get(const stmdev_ctx_t *ctx,
1761 lsm6dsm_st_g_t *val)
1762 {
1763 lsm6dsm_ctrl5_c_t ctrl5_c;
1764 int32_t ret;
1765
1766 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1767
1768 switch (ctrl5_c.st_g)
1769 {
1770 case LSM6DSM_GY_ST_DISABLE:
1771 *val = LSM6DSM_GY_ST_DISABLE;
1772 break;
1773
1774 case LSM6DSM_GY_ST_POSITIVE:
1775 *val = LSM6DSM_GY_ST_POSITIVE;
1776 break;
1777
1778 case LSM6DSM_GY_ST_NEGATIVE:
1779 *val = LSM6DSM_GY_ST_NEGATIVE;
1780 break;
1781
1782 default:
1783 *val = LSM6DSM_GY_ST_DISABLE;
1784 break;
1785 }
1786
1787 return ret;
1788 }
1789
1790 /**
1791 * @}
1792 *
1793 */
1794
1795 /**
1796 * @defgroup LSM6DSM_filters
1797 * @brief This section group all the functions concerning the filters
1798 * configuration that impact both accelerometer and gyro.
1799 * @{
1800 *
1801 */
1802
1803 /**
1804 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
1805 * (XL and Gyro independently masked).[set]
1806 *
1807 * @param ctx Read / write interface definitions
1808 * @param val Change the values of drdy_mask in reg CTRL4_C
1809 * @retval Interface status (MANDATORY: return 0 -> no Error).
1810 *
1811 */
lsm6dsm_filter_settling_mask_set(const stmdev_ctx_t * ctx,uint8_t val)1812 int32_t lsm6dsm_filter_settling_mask_set(const stmdev_ctx_t *ctx,
1813 uint8_t val)
1814 {
1815 lsm6dsm_ctrl4_c_t ctrl4_c;
1816 int32_t ret;
1817
1818 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1819
1820 if (ret == 0)
1821 {
1822 ctrl4_c.drdy_mask = val;
1823 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1824 }
1825
1826 return ret;
1827 }
1828
1829 /**
1830 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
1831 * (XL and Gyro independently masked).[get]
1832 *
1833 * @param ctx Read / write interface definitions
1834 * @param val Change the values of drdy_mask in reg CTRL4_C
1835 * @retval Interface status (MANDATORY: return 0 -> no Error).
1836 *
1837 */
lsm6dsm_filter_settling_mask_get(const stmdev_ctx_t * ctx,uint8_t * val)1838 int32_t lsm6dsm_filter_settling_mask_get(const stmdev_ctx_t *ctx,
1839 uint8_t *val)
1840 {
1841 lsm6dsm_ctrl4_c_t ctrl4_c;
1842 int32_t ret;
1843
1844 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1845 *val = ctrl4_c.drdy_mask;
1846
1847 return ret;
1848 }
1849
1850 /**
1851 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
1852 * functions.[set]
1853 *
1854 * @param ctx Read / write interface definitions
1855 * @param val Change the values of slope_fds in reg TAP_CFG
1856 * @retval Interface status (MANDATORY: return 0 -> no Error).
1857 *
1858 */
lsm6dsm_xl_hp_path_internal_set(const stmdev_ctx_t * ctx,lsm6dsm_slope_fds_t val)1859 int32_t lsm6dsm_xl_hp_path_internal_set(const stmdev_ctx_t *ctx,
1860 lsm6dsm_slope_fds_t val)
1861 {
1862 lsm6dsm_tap_cfg_t tap_cfg;
1863 int32_t ret;
1864
1865 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
1866
1867 if (ret == 0)
1868 {
1869 tap_cfg.slope_fds = (uint8_t) val;
1870 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
1871 }
1872
1873 return ret;
1874 }
1875
1876 /**
1877 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
1878 * functions.[get]
1879 *
1880 * @param ctx Read / write interface definitions
1881 * @param val Get the values of slope_fds in reg TAP_CFG
1882 * @retval Interface status (MANDATORY: return 0 -> no Error).
1883 *
1884 */
lsm6dsm_xl_hp_path_internal_get(const stmdev_ctx_t * ctx,lsm6dsm_slope_fds_t * val)1885 int32_t lsm6dsm_xl_hp_path_internal_get(const stmdev_ctx_t *ctx,
1886 lsm6dsm_slope_fds_t *val)
1887 {
1888 lsm6dsm_tap_cfg_t tap_cfg;
1889 int32_t ret;
1890
1891 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
1892
1893 switch (tap_cfg.slope_fds)
1894 {
1895 case LSM6DSM_USE_SLOPE:
1896 *val = LSM6DSM_USE_SLOPE;
1897 break;
1898
1899 case LSM6DSM_USE_HPF:
1900 *val = LSM6DSM_USE_HPF;
1901 break;
1902
1903 default:
1904 *val = LSM6DSM_USE_SLOPE;
1905 break;
1906 }
1907
1908 return ret;
1909 }
1910
1911 /**
1912 * @}
1913 *
1914 */
1915
1916 /**
1917 * @defgroup LSM6DSM_accelerometer_filters
1918 * @brief This section group all the functions concerning the filters
1919 * configuration that impact accelerometer in every mode.
1920 * @{
1921 *
1922 */
1923
1924 /**
1925 * @brief Accelerometer analog chain bandwidth selection (only for
1926 * accelerometer ODR ≥ 1.67 kHz).[set]
1927 *
1928 * @param ctx Read / write interface definitions
1929 * @param val Change the values of bw0_xl in reg CTRL1_XL
1930 * @retval Interface status (MANDATORY: return 0 -> no Error).
1931 *
1932 */
lsm6dsm_xl_filter_analog_set(const stmdev_ctx_t * ctx,lsm6dsm_bw0_xl_t val)1933 int32_t lsm6dsm_xl_filter_analog_set(const stmdev_ctx_t *ctx,
1934 lsm6dsm_bw0_xl_t val)
1935 {
1936 lsm6dsm_ctrl1_xl_t ctrl1_xl;
1937 int32_t ret;
1938
1939 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
1940
1941 if (ret == 0)
1942 {
1943 ctrl1_xl.bw0_xl = (uint8_t) val;
1944 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
1945 }
1946
1947 return ret;
1948 }
1949
1950 /**
1951 * @brief Accelerometer analog chain bandwidth selection (only for
1952 * accelerometer ODR ≥ 1.67 kHz).[get]
1953 *
1954 * @param ctx Read / write interface definitions
1955 * @param val Get the values of bw0_xl in reg CTRL1_XL
1956 * @retval Interface status (MANDATORY: return 0 -> no Error).
1957 *
1958 */
lsm6dsm_xl_filter_analog_get(const stmdev_ctx_t * ctx,lsm6dsm_bw0_xl_t * val)1959 int32_t lsm6dsm_xl_filter_analog_get(const stmdev_ctx_t *ctx,
1960 lsm6dsm_bw0_xl_t *val)
1961 {
1962 lsm6dsm_ctrl1_xl_t ctrl1_xl;
1963 int32_t ret;
1964
1965 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
1966
1967 switch (ctrl1_xl.bw0_xl)
1968 {
1969 case LSM6DSM_XL_ANA_BW_1k5Hz:
1970 *val = LSM6DSM_XL_ANA_BW_1k5Hz;
1971 break;
1972
1973 case LSM6DSM_XL_ANA_BW_400Hz:
1974 *val = LSM6DSM_XL_ANA_BW_400Hz;
1975 break;
1976
1977 default:
1978 *val = LSM6DSM_XL_ANA_BW_1k5Hz;
1979 break;
1980 }
1981
1982 return ret;
1983 }
1984
1985 /**
1986 * @}
1987 *
1988 */
1989
1990 /**
1991 * @defgroup LSM6DSM_accelerometer_filters_mode:1,2,3
1992 * @brief This section group all the functions concerning the filters
1993 * configuration that impact accelerometer mode 1, 2, 3
1994 * (accelerometer on aux interface disable).
1995 * @{
1996 *
1997 */
1998
1999 /**
2000 * @brief Accelerometer digital LPF (LPF1) bandwidth selection LPF2 is
2001 * not used.[set]
2002 *
2003 * @param ctx Read / write interface definitions
2004 * @param val Change the values of lpf1_bw_sel in reg CTRL1_XL
2005 * @retval Interface status (MANDATORY: return 0 -> no Error).
2006 *
2007 */
lsm6dsm_xl_lp1_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsm_lpf1_bw_sel_t val)2008 int32_t lsm6dsm_xl_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
2009 lsm6dsm_lpf1_bw_sel_t val)
2010 {
2011 lsm6dsm_ctrl1_xl_t ctrl1_xl;
2012 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2013 int32_t ret;
2014
2015 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2016
2017 if (ret == 0)
2018 {
2019 ctrl1_xl.lpf1_bw_sel = (uint8_t) val;
2020 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2021
2022 if (ret == 0)
2023 {
2024 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2025
2026 if (ret == 0)
2027 {
2028 ctrl8_xl.lpf2_xl_en = 0;
2029 ctrl8_xl.hp_slope_xl_en = 0;
2030 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2031 }
2032 }
2033 }
2034
2035 return ret;
2036 }
2037
2038 /**
2039 * @brief Accelerometer digital LPF (LPF1) bandwidth selection LPF2
2040 * is not used.[get]
2041 *
2042 * @param ctx Read / write interface definitions
2043 * @param val Get the values of lpf1_bw_sel in reg CTRL1_XL
2044 * @retval Interface status (MANDATORY: return 0 -> no Error).
2045 *
2046 */
lsm6dsm_xl_lp1_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsm_lpf1_bw_sel_t * val)2047 int32_t lsm6dsm_xl_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
2048 lsm6dsm_lpf1_bw_sel_t *val)
2049 {
2050 lsm6dsm_ctrl1_xl_t ctrl1_xl;
2051 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2052 int32_t ret;
2053
2054 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2055
2056 if (ret == 0)
2057 {
2058 if ((ctrl8_xl.lpf2_xl_en != 0x00U) ||
2059 (ctrl8_xl.hp_slope_xl_en != 0x00U))
2060 {
2061 *val = LSM6DSM_XL_LP1_NA;
2062 }
2063
2064 else
2065 {
2066 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2067
2068 switch (ctrl1_xl.lpf1_bw_sel)
2069 {
2070 case LSM6DSM_XL_LP1_ODR_DIV_2:
2071 *val = LSM6DSM_XL_LP1_ODR_DIV_2;
2072 break;
2073
2074 case LSM6DSM_XL_LP1_ODR_DIV_4:
2075 *val = LSM6DSM_XL_LP1_ODR_DIV_4;
2076 break;
2077
2078 default:
2079 *val = LSM6DSM_XL_LP1_ODR_DIV_2;
2080 break;
2081 }
2082 }
2083 }
2084
2085 return ret;
2086 }
2087
2088 /**
2089 * @brief LPF2 on outputs[set]
2090 *
2091 * @param ctx Read / write interface definitions
2092 * @param val Change the values of input_composite in reg CTRL8_XL
2093 * @retval Interface status (MANDATORY: return 0 -> no Error).
2094 *
2095 */
lsm6dsm_xl_lp2_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsm_input_composite_t val)2096 int32_t lsm6dsm_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx,
2097 lsm6dsm_input_composite_t val)
2098 {
2099 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2100 int32_t ret;
2101
2102 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2103
2104 if (ret == 0)
2105 {
2106 ctrl8_xl.input_composite = ((uint8_t) val & 0x10U) >> 4;
2107 ctrl8_xl.hpcf_xl = (uint8_t) val & 0x03U;
2108 ctrl8_xl.lpf2_xl_en = 1;
2109 ctrl8_xl.hp_slope_xl_en = 0;
2110 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2111 }
2112
2113 return ret;
2114 }
2115
2116 /**
2117 * @brief LPF2 on outputs[get]
2118 *
2119 * @param ctx Read / write interface definitions
2120 * @param val Get the values of input_composite in reg CTRL8_XL
2121 * @retval Interface status (MANDATORY: return 0 -> no Error).
2122 *
2123 */
lsm6dsm_xl_lp2_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsm_input_composite_t * val)2124 int32_t lsm6dsm_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx,
2125 lsm6dsm_input_composite_t *val)
2126 {
2127 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2128 int32_t ret;
2129
2130 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2131
2132 if (ret == 0)
2133 {
2134 if ((ctrl8_xl.lpf2_xl_en == 0x00U) ||
2135 (ctrl8_xl.hp_slope_xl_en != 0x00U))
2136 {
2137 *val = LSM6DSM_XL_LP_NA;
2138 }
2139
2140 else
2141 {
2142 switch ((ctrl8_xl.input_composite << 4) + ctrl8_xl.hpcf_xl)
2143 {
2144 case LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_50:
2145 *val = LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_50;
2146 break;
2147
2148 case LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_100:
2149 *val = LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_100;
2150 break;
2151
2152 case LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_9:
2153 *val = LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_9;
2154 break;
2155
2156 case LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_400:
2157 *val = LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_400;
2158 break;
2159
2160 case LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_50:
2161 *val = LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_50;
2162 break;
2163
2164 case LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_100:
2165 *val = LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_100;
2166 break;
2167
2168 case LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_9:
2169 *val = LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_9;
2170 break;
2171
2172 case LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_400:
2173 *val = LSM6DSM_XL_LOW_NOISE_LP_ODR_DIV_400;
2174 break;
2175
2176 default:
2177 *val = LSM6DSM_XL_LOW_LAT_LP_ODR_DIV_50;
2178 break;
2179 }
2180 }
2181 }
2182
2183 return ret;
2184 }
2185
2186 /**
2187 * @brief Enable HP filter reference mode.[set]
2188 *
2189 * @param ctx Read / write interface definitions
2190 * @param val Change the values of hp_ref_mode in reg CTRL8_XL
2191 * @retval Interface status (MANDATORY: return 0 -> no Error).
2192 *
2193 */
lsm6dsm_xl_reference_mode_set(const stmdev_ctx_t * ctx,uint8_t val)2194 int32_t lsm6dsm_xl_reference_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
2195 {
2196 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2197 int32_t ret;
2198
2199 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2200
2201 if (ret == 0)
2202 {
2203 ctrl8_xl.hp_ref_mode = val;
2204 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2205 }
2206
2207 return ret;
2208 }
2209
2210 /**
2211 * @brief Enable HP filter reference mode.[get]
2212 *
2213 * @param ctx Read / write interface definitions
2214 * @param val Change the values of hp_ref_mode in reg CTRL8_XL
2215 * @retval Interface status (MANDATORY: return 0 -> no Error).
2216 *
2217 */
lsm6dsm_xl_reference_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)2218 int32_t lsm6dsm_xl_reference_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
2219 {
2220 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2221 int32_t ret;
2222
2223 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2224 *val = ctrl8_xl.hp_ref_mode;
2225
2226 return ret;
2227 }
2228
2229 /**
2230 * @brief High pass/Slope on outputs.[set]
2231 *
2232 * @param ctx Read / write interface definitions
2233 * @param val Change the values of hpcf_xl in reg CTRL8_XL
2234 * @retval Interface status (MANDATORY: return 0 -> no Error).
2235 *
2236 */
lsm6dsm_xl_hp_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsm_hpcf_xl_t val)2237 int32_t lsm6dsm_xl_hp_bandwidth_set(const stmdev_ctx_t *ctx,
2238 lsm6dsm_hpcf_xl_t val)
2239 {
2240 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2241 int32_t ret;
2242
2243 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2244
2245 if (ret == 0)
2246 {
2247 ctrl8_xl.input_composite = 0;
2248 ctrl8_xl.hpcf_xl = (uint8_t)val & 0x03U;
2249 ctrl8_xl.hp_slope_xl_en = 1;
2250 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2251 }
2252
2253 return ret;
2254 }
2255
2256 /**
2257 * @brief High pass/Slope on outputs.[get]
2258 *
2259 * @param ctx Read / write interface definitions
2260 * @param val Get the values of hpcf_xl in reg CTRL8_XL
2261 * @retval Interface status (MANDATORY: return 0 -> no Error).
2262 *
2263 */
lsm6dsm_xl_hp_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsm_hpcf_xl_t * val)2264 int32_t lsm6dsm_xl_hp_bandwidth_get(const stmdev_ctx_t *ctx,
2265 lsm6dsm_hpcf_xl_t *val)
2266 {
2267 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2268 int32_t ret;
2269
2270 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2271
2272 if (ctrl8_xl.hp_slope_xl_en == 0x00U)
2273 {
2274 *val = LSM6DSM_XL_HP_NA;
2275 }
2276
2277 switch (ctrl8_xl.hpcf_xl)
2278 {
2279 case LSM6DSM_XL_HP_ODR_DIV_4:
2280 *val = LSM6DSM_XL_HP_ODR_DIV_4;
2281 break;
2282
2283 case LSM6DSM_XL_HP_ODR_DIV_100:
2284 *val = LSM6DSM_XL_HP_ODR_DIV_100;
2285 break;
2286
2287 case LSM6DSM_XL_HP_ODR_DIV_9:
2288 *val = LSM6DSM_XL_HP_ODR_DIV_9;
2289 break;
2290
2291 case LSM6DSM_XL_HP_ODR_DIV_400:
2292 *val = LSM6DSM_XL_HP_ODR_DIV_400;
2293 break;
2294
2295 default:
2296 *val = LSM6DSM_XL_HP_ODR_DIV_4;
2297 break;
2298 }
2299
2300 return ret;
2301 }
2302
2303 /**
2304 * @}
2305 *
2306 */
2307
2308 /**
2309 * @defgroup LSM6DSM_accelerometer_filters_mode:4
2310 * @brief This section group all the functions concerning the filters
2311 * configuration that impact accelerometer when mode 4
2312 * (accelerometer on aux interface enable).
2313 * @{
2314 *
2315 */
2316
2317 /**
2318 * @brief Accelerometer digital LPF (LPF1) bandwidth selection.
2319 * Only for mode 4.[set]
2320 *
2321 * @param ctx Read / write interface definitions
2322 * @param val change the values of lpf1_bw_sel in reg CTRL1_XL
2323 * @retval Interface status (MANDATORY: return 0 -> no Error).
2324 *
2325 */
lsm6dsm_xl_ui_lp1_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsm_ui_lpf1_bw_sel_t val)2326 int32_t lsm6dsm_xl_ui_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
2327 lsm6dsm_ui_lpf1_bw_sel_t val)
2328 {
2329 lsm6dsm_ctrl1_xl_t ctrl1_xl;
2330 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2331 int32_t ret;
2332
2333 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2334
2335 if (ret == 0)
2336 {
2337 ctrl1_xl.lpf1_bw_sel = (uint8_t)val;
2338 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2339 }
2340
2341 if (ret == 0)
2342 {
2343 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2344 }
2345
2346 if (ret == 0)
2347 {
2348 ctrl8_xl.hp_slope_xl_en = 0x00U;
2349 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2350 }
2351
2352 return ret;
2353 }
2354
2355 /**
2356 * @brief Accelerometer digital LPF (LPF1) bandwidth selection.
2357 * Only for mode 4.[get]
2358 *
2359 * @param ctx Read / write interface definitions
2360 * @param val Get the values of lpf1_bw_sel in reg CTRL1_XL
2361 * @retval Interface status (MANDATORY: return 0 -> no Error).
2362 *
2363 */
lsm6dsm_xl_ui_lp1_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsm_ui_lpf1_bw_sel_t * val)2364 int32_t lsm6dsm_xl_ui_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
2365 lsm6dsm_ui_lpf1_bw_sel_t *val)
2366 {
2367 lsm6dsm_ctrl1_xl_t ctrl1_xl;
2368 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2369 int32_t ret;
2370
2371 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2372
2373 if (ret == 0)
2374 {
2375 if (ctrl8_xl.hp_slope_xl_en != PROPERTY_DISABLE)
2376 {
2377 *val = LSM6DSM_XL_UI_LP1_NA;
2378 }
2379
2380 else
2381 {
2382 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2383
2384 switch (ctrl1_xl.lpf1_bw_sel)
2385 {
2386 case LSM6DSM_XL_UI_LP1_ODR_DIV_2:
2387 *val = LSM6DSM_XL_UI_LP1_ODR_DIV_2;
2388 break;
2389
2390 case LSM6DSM_XL_UI_LP1_ODR_DIV_4:
2391 *val = LSM6DSM_XL_UI_LP1_ODR_DIV_4;
2392 break;
2393
2394 default:
2395 *val = LSM6DSM_XL_UI_LP1_ODR_DIV_2;
2396 break;
2397 }
2398 }
2399 }
2400
2401 return ret;
2402 }
2403
2404 /**
2405 * @brief Slope filter on outputs.[set]
2406 *
2407 * @param ctx Read / write interface definitions
2408 * @param val change the values of hp_slope_xl_en in reg CTRL8_XL
2409 * @retval Interface status (MANDATORY: return 0 -> no Error).
2410 *
2411 */
lsm6dsm_xl_ui_slope_set(const stmdev_ctx_t * ctx,uint8_t val)2412 int32_t lsm6dsm_xl_ui_slope_set(const stmdev_ctx_t *ctx, uint8_t val)
2413 {
2414 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2415 int32_t ret;
2416
2417 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2418
2419 if (ret == 0)
2420 {
2421 ctrl8_xl.hp_slope_xl_en = (uint8_t) val;
2422 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2423 }
2424
2425 return ret;
2426 }
2427
2428 /**
2429 * @brief Slope filter on outputs.[get]
2430 *
2431 * @param ctx Read / write interface definitions
2432 * @param val Get the values of hp_slope_xl_en in reg CTRL8_XL
2433 * @retval Interface status (MANDATORY: return 0 -> no Error).
2434 *
2435 */
lsm6dsm_xl_ui_slope_get(const stmdev_ctx_t * ctx,uint8_t * val)2436 int32_t lsm6dsm_xl_ui_slope_get(const stmdev_ctx_t *ctx, uint8_t *val)
2437 {
2438 lsm6dsm_ctrl8_xl_t ctrl8_xl;
2439 int32_t ret;
2440
2441 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2442 *val = ctrl8_xl.hp_slope_xl_en;
2443
2444 return ret;
2445 }
2446
2447 /**
2448 * @brief accelerometer auxiliary low pass bandwidth.[set]
2449 *
2450 * @param ctx Read / write interface definitions
2451 * @param val change the values of filter_xl_conf_ois in reg CTRL3_OIS
2452 *
2453 * Cut off feq [ODR_UI = 0 / ODR UI ≥ 1600 Hz]
2454 * LIGHT 636 Hz 2.96°
2455 * NORMAL 295 Hz 5.12°
2456 * STRONG 140 Hz 9.39°
2457 * AGGRESSIVE 68.2 Hz 17.6°
2458 *
2459 * Cut off feq [ODR UI ≤ 800 Hz ]
2460 * LIGHT 329 Hz 5.08°
2461 * NORMAL 222 Hz 7.23°
2462 * STRONG 128 Hz 11.5°
2463 * AGGRESSIVE 66.5 Hz 19.7°
2464 *
2465 * @retval Interface status (MANDATORY: return 0 -> no Error).
2466 *
2467 */
lsm6dsm_xl_aux_lp_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsm_filter_xl_conf_ois_t val)2468 int32_t lsm6dsm_xl_aux_lp_bandwidth_set(const stmdev_ctx_t *ctx,
2469 lsm6dsm_filter_xl_conf_ois_t val)
2470 {
2471 lsm6dsm_ctrl3_ois_t ctrl3_ois;
2472 int32_t ret;
2473
2474 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
2475
2476 if (ret == 0)
2477 {
2478 ctrl3_ois.filter_xl_conf_ois = (uint8_t) val;
2479 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
2480 }
2481
2482 return ret;
2483 }
2484
2485 /**
2486 * @brief accelerometer auxiliary low pass bandwidth.[get]
2487 *
2488 * @param ctx Read / write interface definitions
2489 * @param val Get the values of filter_xl_conf_ois in reg CTRL3_OIS
2490 *
2491 * Cut off feq [ODR_UI = 0 / ODR UI ≥ 1600 Hz]
2492 * LIGHT 636 Hz 2.96°
2493 * NORMAL 295 Hz 5.12°
2494 * STRONG 140 Hz 9.39°
2495 * AGGRESSIVE 68.2 Hz 17.6°
2496 *
2497 * Cut off feq [ODR UI ≤ 800 Hz ]
2498 * LIGHT 329 Hz 5.08°
2499 * NORMAL 222 Hz 7.23°
2500 * STRONG 128 Hz 11.5°
2501 * AGGRESSIVE 66.5 Hz 19.7°
2502 *
2503 * @retval Interface status (MANDATORY: return 0 -> no Error).
2504 *
2505 */
lsm6dsm_xl_aux_lp_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsm_filter_xl_conf_ois_t * val)2506 int32_t lsm6dsm_xl_aux_lp_bandwidth_get(const stmdev_ctx_t *ctx,
2507 lsm6dsm_filter_xl_conf_ois_t *val)
2508 {
2509 lsm6dsm_ctrl3_ois_t ctrl3_ois;
2510 int32_t ret;
2511
2512 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
2513
2514 switch (ctrl3_ois.filter_xl_conf_ois)
2515 {
2516 case LSM6DSM_AUX_LP_LIGHT:
2517 *val = LSM6DSM_AUX_LP_LIGHT;
2518 break;
2519
2520 case LSM6DSM_AUX_LP_NORMAL:
2521 *val = LSM6DSM_AUX_LP_NORMAL;
2522 break;
2523
2524 case LSM6DSM_AUX_LP_STRONG:
2525 *val = LSM6DSM_AUX_LP_STRONG;
2526 break;
2527
2528 case LSM6DSM_AUX_LP_AGGRESSIVE:
2529 *val = LSM6DSM_AUX_LP_AGGRESSIVE;
2530 break;
2531
2532 default:
2533 *val = LSM6DSM_AUX_LP_LIGHT;
2534 break;
2535 }
2536
2537 return ret;
2538 }
2539
2540 /**
2541 * @}
2542 *
2543 */
2544
2545 /**
2546 * @defgroup LSM6DSM_gyroscope_filters_mode:1,2
2547 * @brief This section group all the functions concerning the filters
2548 * configuration that impact gyroscope mode 1, 2
2549 * (gyroscope on aux interface disable).
2550 * @{
2551 *
2552 */
2553
2554 /**
2555 * @brief Gyroscope low pass path bandwidth.[set]
2556 *
2557 * @param ctx Read / write interface definitions
2558 * @param val gyroscope filtering chain configuration.
2559 * @retval Interface status (MANDATORY: return 0 -> no Error).
2560 *
2561 */
lsm6dsm_gy_band_pass_set(const stmdev_ctx_t * ctx,lsm6dsm_lpf1_sel_g_t val)2562 int32_t lsm6dsm_gy_band_pass_set(const stmdev_ctx_t *ctx,
2563 lsm6dsm_lpf1_sel_g_t val)
2564 {
2565 lsm6dsm_ctrl4_c_t ctrl4_c;
2566 lsm6dsm_ctrl6_c_t ctrl6_c;
2567 lsm6dsm_ctrl7_g_t ctrl7_g;
2568 int32_t ret;
2569
2570 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2571
2572 if (ret == 0)
2573 {
2574 ctrl7_g.hpm_g = ((uint8_t)val & 0x30U) >> 4;
2575 ctrl7_g.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
2576 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2577
2578 if (ret == 0)
2579 {
2580 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2581
2582 if (ret == 0)
2583 {
2584 ctrl6_c.ftype = (uint8_t)val & 0x03U;
2585 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2586
2587 if (ret == 0)
2588 {
2589 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C,
2590 (uint8_t *)&ctrl4_c, 1);
2591
2592 if (ret == 0)
2593 {
2594 ctrl4_c.lpf1_sel_g = ((uint8_t)val & 0x08U) >> 3;
2595 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C,
2596 (uint8_t *)&ctrl4_c, 1);
2597 }
2598 }
2599 }
2600 }
2601 }
2602
2603 return ret;
2604 }
2605
2606 /**
2607 * @brief Gyroscope low pass path bandwidth.[get]
2608 *
2609 * @param ctx Read / write interface definitions
2610 * @param val gyroscope filtering chain
2611 * @retval Interface status (MANDATORY: return 0 -> no Error).
2612 *
2613 */
lsm6dsm_gy_band_pass_get(const stmdev_ctx_t * ctx,lsm6dsm_lpf1_sel_g_t * val)2614 int32_t lsm6dsm_gy_band_pass_get(const stmdev_ctx_t *ctx,
2615 lsm6dsm_lpf1_sel_g_t *val)
2616 {
2617 lsm6dsm_ctrl4_c_t ctrl4_c;
2618 lsm6dsm_ctrl6_c_t ctrl6_c;
2619 lsm6dsm_ctrl7_g_t ctrl7_g;
2620 int32_t ret;
2621
2622 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2623
2624 if (ret == 0)
2625 {
2626 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2627
2628 if (ret == 0)
2629 {
2630 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2631
2632 switch ((ctrl7_g.hp_en_g << 7) + (ctrl7_g.hpm_g << 4) +
2633 (ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype)
2634 {
2635 case LSM6DSM_HP_16mHz_LP2:
2636 *val = LSM6DSM_HP_16mHz_LP2;
2637 break;
2638
2639 case LSM6DSM_HP_65mHz_LP2:
2640 *val = LSM6DSM_HP_65mHz_LP2;
2641 break;
2642
2643 case LSM6DSM_HP_260mHz_LP2:
2644 *val = LSM6DSM_HP_260mHz_LP2;
2645 break;
2646
2647 case LSM6DSM_HP_1Hz04_LP2:
2648 *val = LSM6DSM_HP_1Hz04_LP2;
2649 break;
2650
2651 case LSM6DSM_HP_DISABLE_LP1_LIGHT:
2652 *val = LSM6DSM_HP_DISABLE_LP1_LIGHT;
2653 break;
2654
2655 case LSM6DSM_HP_DISABLE_LP1_NORMAL:
2656 *val = LSM6DSM_HP_DISABLE_LP1_NORMAL;
2657 break;
2658
2659 case LSM6DSM_HP_DISABLE_LP_STRONG:
2660 *val = LSM6DSM_HP_DISABLE_LP_STRONG;
2661 break;
2662
2663 case LSM6DSM_HP_DISABLE_LP1_AGGRESSIVE:
2664 *val = LSM6DSM_HP_DISABLE_LP1_AGGRESSIVE;
2665 break;
2666
2667 case LSM6DSM_HP_16mHz_LP1_LIGHT:
2668 *val = LSM6DSM_HP_16mHz_LP1_LIGHT;
2669 break;
2670
2671 case LSM6DSM_HP_65mHz_LP1_NORMAL:
2672 *val = LSM6DSM_HP_65mHz_LP1_NORMAL;
2673 break;
2674
2675 case LSM6DSM_HP_260mHz_LP1_STRONG:
2676 *val = LSM6DSM_HP_260mHz_LP1_STRONG;
2677 break;
2678
2679 case LSM6DSM_HP_1Hz04_LP1_AGGRESSIVE:
2680 *val = LSM6DSM_HP_1Hz04_LP1_AGGRESSIVE;
2681 break;
2682
2683 default:
2684 *val = LSM6DSM_HP_65mHz_LP2;
2685 break;
2686 }
2687 }
2688 }
2689
2690 return ret;
2691 }
2692
2693 /**
2694 * @}
2695 *
2696 */
2697
2698 /**
2699 * @defgroup LSM6DSM_gyroscope_filters_mode:3,4
2700 * @brief This section group all the functions concerning the filters
2701 * configuration that impact gyroscope when mode 3, 4
2702 * (gyroscope on aux interface enable).
2703 * @{
2704 *
2705 */
2706
2707 /**
2708 * @brief HPF is available on gyroscope's OIS chain only if HP_EN_G
2709 * in CTRL7_G (16h) is set to '0'.[set]
2710 *
2711 * @param ctx Read / write interface definitions
2712 * @param val gyroscope ui filtering chain configuration in Mode: 3, 4.
2713 * @retval Interface status (MANDATORY: return 0 -> no Error).
2714 *
2715 */
lsm6dsm_gy_ui_high_pass_set(const stmdev_ctx_t * ctx,uint8_t val)2716 int32_t lsm6dsm_gy_ui_high_pass_set(const stmdev_ctx_t *ctx, uint8_t val)
2717 {
2718 lsm6dsm_ctrl7_g_t ctrl7_g;
2719 int32_t ret;
2720
2721 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2722
2723 if (ret == 0)
2724 {
2725 ctrl7_g.hp_en_g = val;
2726 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2727 }
2728
2729 return ret;
2730 }
2731
2732 /**
2733 * @brief HPF is available on gyroscope's OIS chain only if HP_EN_G
2734 * in CTRL7_G (16h) is set to '0'.[get]
2735 *
2736 * @param ctx Read / write interface definitions
2737 * @param val gyroscope ui filtering chain configuration in Mode: 3, 4.
2738 * @retval Interface status (MANDATORY: return 0 -> no Error).
2739 *
2740 */
lsm6dsm_gy_ui_high_pass_get(const stmdev_ctx_t * ctx,uint8_t * val)2741 int32_t lsm6dsm_gy_ui_high_pass_get(const stmdev_ctx_t *ctx, uint8_t *val)
2742 {
2743 lsm6dsm_ctrl7_g_t ctrl7_g;
2744 int32_t ret;
2745
2746 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2747 *val = ctrl7_g.hp_en_g;
2748
2749 return ret;
2750 }
2751
2752
2753 /**
2754 * @brief HPF is available on gyroscope's OIS chain only if HP_EN_G
2755 * in CTRL7_G (16h) is set to '0'.[set]
2756 *
2757 * @param ctx Read / write interface definitions
2758 * @param val gyroscope aux (ois) filtering chain configuration in
2759 * Mode: 3, 4.
2760 * @retval Interface status (MANDATORY: return 0 -> no Error).
2761 *
2762 */
lsm6dsm_gy_aux_bandwidth_set(const stmdev_ctx_t * ctx,lsm6dsm_hp_en_ois_t val)2763 int32_t lsm6dsm_gy_aux_bandwidth_set(const stmdev_ctx_t *ctx,
2764 lsm6dsm_hp_en_ois_t val)
2765 {
2766 lsm6dsm_ctrl7_g_t ctrl7_g;
2767 lsm6dsm_ctrl2_ois_t ctrl2_ois;
2768 int32_t ret;
2769
2770 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2771
2772 if (ret == 0)
2773 {
2774 ctrl7_g.hp_en_g = 0x00U;
2775 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2776 }
2777
2778 if (ret == 0)
2779 {
2780 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1);
2781 }
2782
2783 if (ret == 0)
2784 {
2785 ctrl2_ois.ftype_ois = (uint8_t)val & 0x03U;
2786 ctrl2_ois.hp_en_ois = ((uint8_t)val & 0x80U) >> 7;
2787 ctrl2_ois.hpm_ois = ((uint8_t)val & 0x30U) >> 4;
2788 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1);
2789 }
2790
2791 return ret;
2792 }
2793
2794 /**
2795 * @brief HPF is available on gyroscope's OIS chain only if HP_EN_G
2796 * in CTRL7_G (16h) is set to '0'.[get]
2797 *
2798 * @param ctx Read / write interface definitions
2799 * @param val gyroscope aux (ois) filtering chain configuration in
2800 * Mode: 3, 4.
2801 * @retval Interface status (MANDATORY: return 0 -> no Error).
2802 *
2803 */
lsm6dsm_gy_aux_bandwidth_get(const stmdev_ctx_t * ctx,lsm6dsm_hp_en_ois_t * val)2804 int32_t lsm6dsm_gy_aux_bandwidth_get(const stmdev_ctx_t *ctx,
2805 lsm6dsm_hp_en_ois_t *val)
2806 {
2807 lsm6dsm_ctrl2_ois_t ctrl2_ois;
2808 int32_t ret;
2809
2810 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL2_OIS, (uint8_t *)&ctrl2_ois, 1);
2811
2812 switch (((ctrl2_ois.hp_en_ois << 7) + (ctrl2_ois.hpm_ois << 4)
2813 + ctrl2_ois.ftype_ois))
2814 {
2815 case LSM6DSM_HP_DISABLE_LP_173Hz:
2816 *val = LSM6DSM_HP_DISABLE_LP_173Hz;
2817 break;
2818
2819 case LSM6DSM_HP_DISABLE_LP_237Hz:
2820 *val = LSM6DSM_HP_DISABLE_LP_237Hz;
2821 break;
2822
2823 case LSM6DSM_HP_DISABLE_LP_351Hz:
2824 *val = LSM6DSM_HP_DISABLE_LP_351Hz;
2825 break;
2826
2827 case LSM6DSM_HP_DISABLE_LP_937Hz:
2828 *val = LSM6DSM_HP_DISABLE_LP_937Hz;
2829 break;
2830
2831 case LSM6DSM_HP_16mHz_LP_173Hz:
2832 *val = LSM6DSM_HP_16mHz_LP_173Hz;
2833 break;
2834
2835 case LSM6DSM_HP_65mHz_LP_237Hz:
2836 *val = LSM6DSM_HP_65mHz_LP_237Hz;
2837 break;
2838
2839 case LSM6DSM_HP_260mHz_LP_351Hz:
2840 *val = LSM6DSM_HP_260mHz_LP_351Hz;
2841 break;
2842
2843 case LSM6DSM_HP_1Hz04_LP_937Hz:
2844 *val = LSM6DSM_HP_1Hz04_LP_937Hz;
2845 break;
2846
2847 default:
2848 *val = LSM6DSM_HP_DISABLE_LP_173Hz;
2849 break;
2850 }
2851
2852 return ret;
2853 }
2854
2855 /**
2856 * @}
2857 *
2858 */
2859
2860 /**
2861 * @defgroup LSM6DSM_Auxiliary_interface
2862 * @brief This section groups all the functions concerning
2863 * auxiliary interface.
2864 * @{
2865 *
2866 */
2867
2868 /**
2869 * @brief The STATUS_SPIAux register is read by the auxiliary SPI.[get]
2870 *
2871 * @param ctx Read / write interface definitions
2872 * @param val registers STATUS_SPIAUX.
2873 * @retval Interface status (MANDATORY: return 0 -> no Error).
2874 *
2875 */
lsm6dsm_aux_status_reg_get(const stmdev_ctx_t * ctx,lsm6dsm_status_spiaux_t * val)2876 int32_t lsm6dsm_aux_status_reg_get(const stmdev_ctx_t *ctx,
2877 lsm6dsm_status_spiaux_t *val)
2878 {
2879 int32_t ret;
2880
2881 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_SPIAUX, (uint8_t *) val, 1);
2882
2883 return ret;
2884 }
2885
2886 /**
2887 * @brief AUX accelerometer data available.[get]
2888 *
2889 * @param ctx Read / write interface definitions
2890 * @param val change the values of xlda in reg STATUS_SPIAUX
2891 * @retval Interface status (MANDATORY: return 0 -> no Error).
2892 *
2893 */
lsm6dsm_aux_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)2894 int32_t lsm6dsm_aux_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
2895 uint8_t *val)
2896 {
2897 lsm6dsm_status_spiaux_t status_spiaux;
2898 int32_t ret;
2899
2900 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_SPIAUX,
2901 (uint8_t *)&status_spiaux, 1);
2902 *val = status_spiaux.xlda;
2903
2904 return ret;
2905 }
2906
2907 /**
2908 * @brief AUX gyroscope data available.[get]
2909 *
2910 * @param ctx Read / write interface definitions
2911 * @param val change the values of gda in reg STATUS_SPIAUX
2912 * @retval Interface status (MANDATORY: return 0 -> no Error).
2913 *
2914 */
lsm6dsm_aux_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)2915 int32_t lsm6dsm_aux_gy_flag_data_ready_get(const stmdev_ctx_t *ctx,
2916 uint8_t *val)
2917 {
2918 lsm6dsm_status_spiaux_t status_spiaux;
2919 int32_t ret;
2920
2921 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_SPIAUX,
2922 (uint8_t *)&status_spiaux, 1);
2923 *val = status_spiaux.gda;
2924
2925 return ret;
2926 }
2927
2928 /**
2929 * @brief High when the gyroscope output is in the settling phase.[get]
2930 *
2931 * @param ctx Read / write interface definitions
2932 * @param val change the values of gyro_settling in reg STATUS_SPIAUX
2933 * @retval Interface status (MANDATORY: return 0 -> no Error).
2934 *
2935 */
lsm6dsm_aux_gy_flag_settling_get(const stmdev_ctx_t * ctx,uint8_t * val)2936 int32_t lsm6dsm_aux_gy_flag_settling_get(const stmdev_ctx_t *ctx,
2937 uint8_t *val)
2938 {
2939 lsm6dsm_status_spiaux_t status_spiaux;
2940 int32_t ret;
2941
2942 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STATUS_SPIAUX,
2943 (uint8_t *)&status_spiaux, 1);
2944 *val = status_spiaux.gyro_settling;
2945
2946 return ret;
2947 }
2948
2949 /**
2950 * @brief Configure DEN mode on the OIS chain.[set]
2951 *
2952 * @param ctx Read / write interface definitions
2953 * @param val change the values of lvl2_ois in reg INT_OIS
2954 * @retval Interface status (MANDATORY: return 0 -> no Error).
2955 *
2956 */
lsm6dsm_aux_den_mode_set(const stmdev_ctx_t * ctx,lsm6dsm_lvl_ois_t val)2957 int32_t lsm6dsm_aux_den_mode_set(const stmdev_ctx_t *ctx,
2958 lsm6dsm_lvl_ois_t val)
2959 {
2960 lsm6dsm_int_ois_t int_ois;
2961 lsm6dsm_ctrl1_ois_t ctrl1_ois;
2962 int32_t ret;
2963
2964 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1);
2965
2966 if (ret == 0)
2967 {
2968 int_ois.lvl2_ois = (uint8_t)val & 0x01U;
2969 ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1);
2970 }
2971
2972 if (ret == 0)
2973 {
2974 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
2975 ctrl1_ois.lvl1_ois = ((uint8_t)val & 0x02U) >> 1;
2976 }
2977
2978 if (ret == 0)
2979 {
2980 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
2981 }
2982
2983 return ret;
2984 }
2985
2986 /**
2987 * @brief Configure DEN mode on the OIS chain.[get]
2988 *
2989 * @param ctx Read / write interface definitions
2990 * @param val Get the values of lvl2_ois in reg INT_OIS
2991 * @retval Interface status (MANDATORY: return 0 -> no Error).
2992 *
2993 */
lsm6dsm_aux_den_mode_get(const stmdev_ctx_t * ctx,lsm6dsm_lvl_ois_t * val)2994 int32_t lsm6dsm_aux_den_mode_get(const stmdev_ctx_t *ctx,
2995 lsm6dsm_lvl_ois_t *val)
2996 {
2997 lsm6dsm_int_ois_t int_ois;
2998 lsm6dsm_ctrl1_ois_t ctrl1_ois;
2999 int32_t ret;
3000
3001 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1);
3002
3003 if (ret == 0)
3004 {
3005 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3006
3007 switch ((ctrl1_ois.lvl1_ois << 1) + int_ois.lvl2_ois)
3008 {
3009 case LSM6DSM_AUX_DEN_DISABLE:
3010 *val = LSM6DSM_AUX_DEN_DISABLE;
3011 break;
3012
3013 case LSM6DSM_AUX_DEN_LEVEL_LATCH:
3014 *val = LSM6DSM_AUX_DEN_LEVEL_LATCH;
3015 break;
3016
3017 case LSM6DSM_AUX_DEN_LEVEL_TRIG:
3018 *val = LSM6DSM_AUX_DEN_LEVEL_TRIG;
3019 break;
3020
3021 default:
3022 *val = LSM6DSM_AUX_DEN_DISABLE;
3023 break;
3024 }
3025 }
3026
3027 return ret;
3028 }
3029
3030 /**
3031 * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting
3032 * has priority over all other INT2 settings.[set]
3033 *
3034 * @param ctx Read / write interface definitions
3035 * @param val change the values of int2_drdy_ois in reg INT_OIS
3036 * @retval Interface status (MANDATORY: return 0 -> no Error).
3037 *
3038 */
lsm6dsm_aux_drdy_on_int2_set(const stmdev_ctx_t * ctx,uint8_t val)3039 int32_t lsm6dsm_aux_drdy_on_int2_set(const stmdev_ctx_t *ctx, uint8_t val)
3040 {
3041 lsm6dsm_int_ois_t int_ois;
3042 int32_t ret;
3043
3044 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1);
3045
3046 if (ret == 0)
3047 {
3048 int_ois.int2_drdy_ois = val;
3049 ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1);
3050 }
3051
3052 return ret;
3053 }
3054
3055 /**
3056 * @brief Enables/Disable OIS chain DRDY on INT2 pin. This setting
3057 * has priority over all other INT2 settings.[get]
3058 *
3059 * @param ctx Read / write interface definitions
3060 * @param val change the values of int2_drdy_ois in reg INT_OIS
3061 * @retval Interface status (MANDATORY: return 0 -> no Error).
3062 *
3063 */
lsm6dsm_aux_drdy_on_int2_get(const stmdev_ctx_t * ctx,uint8_t * val)3064 int32_t lsm6dsm_aux_drdy_on_int2_get(const stmdev_ctx_t *ctx, uint8_t *val)
3065 {
3066 lsm6dsm_int_ois_t int_ois;
3067 int32_t ret;
3068
3069 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_OIS, (uint8_t *)&int_ois, 1);
3070 *val = int_ois.int2_drdy_ois;
3071
3072 return ret;
3073 }
3074
3075 /**
3076 * @brief Enables OIS chain data processing for gyro
3077 * in Mode 3 and Mode 4 (mode4_en = 1) and
3078 * accelerometer data in and Mode 4 (mode4_en = 1).
3079 * When the OIS chain is enabled, the OIS outputs are
3080 * available through the SPI2 in registers
3081 * OUTX_L_G(22h) through OUTZ_H_G(27h) and
3082 * STATUS_REG(1Eh) / STATUS_SPIAux, and LPF1 is
3083 * dedicated to this chain.[set]
3084 *
3085 * @param ctx Read / write interface definitions
3086 * @param val change the values of ois_en_spi2 in reg CTRL1_OIS
3087 * @retval Interface status (MANDATORY: return 0 -> no Error).
3088 *
3089 */
lsm6dsm_aux_mode_set(const stmdev_ctx_t * ctx,lsm6dsm_ois_en_spi2_t val)3090 int32_t lsm6dsm_aux_mode_set(const stmdev_ctx_t *ctx,
3091 lsm6dsm_ois_en_spi2_t val)
3092 {
3093 lsm6dsm_ctrl1_ois_t ctrl1_ois;
3094 int32_t ret;
3095
3096 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3097
3098 if (ret == 0)
3099 {
3100 ctrl1_ois.ois_en_spi2 = (uint8_t)val & 0x01U;
3101 ctrl1_ois.mode4_en = ((uint8_t)val & 0x02U) >> 1;
3102 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3103 }
3104
3105 return ret;
3106 }
3107
3108 /**
3109 * @brief Enables OIS chain data processing for gyro
3110 * in Mode 3 and Mode 4 (mode4_en = 1) and
3111 * accelerometer data in and Mode 4 (mode4_en = 1).
3112 * When the OIS chain is enabled, the OIS outputs
3113 * are available through the SPI2 in registers
3114 * OUTX_L_G(22h) through OUTZ_H_G(27h) and
3115 * STATUS_REG(1Eh) / STATUS_SPIAux, and LPF1 is
3116 * dedicated to this chain.[get]
3117 *
3118 * @param ctx Read / write interface definitions
3119 * @param val Get the values of ois_en_spi2 in reg CTRL1_OIS
3120 * @retval Interface status (MANDATORY: return 0 -> no Error).
3121 *
3122 */
lsm6dsm_aux_mode_get(const stmdev_ctx_t * ctx,lsm6dsm_ois_en_spi2_t * val)3123 int32_t lsm6dsm_aux_mode_get(const stmdev_ctx_t *ctx,
3124 lsm6dsm_ois_en_spi2_t *val)
3125 {
3126 lsm6dsm_ctrl1_ois_t ctrl1_ois;
3127 int32_t ret;
3128
3129 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3130
3131 switch ((ctrl1_ois.mode4_en << 1) + ctrl1_ois.ois_en_spi2)
3132 {
3133 case LSM6DSM_AUX_DISABLE:
3134 *val = LSM6DSM_AUX_DISABLE;
3135 break;
3136
3137 case LSM6DSM_MODE_3_GY:
3138 *val = LSM6DSM_MODE_3_GY;
3139 break;
3140
3141 case LSM6DSM_MODE_4_GY_XL:
3142 *val = LSM6DSM_MODE_4_GY_XL;
3143 break;
3144
3145 default:
3146 *val = LSM6DSM_AUX_DISABLE;
3147 break;
3148 }
3149
3150 return ret;
3151 }
3152
3153 /**
3154 * @brief Selects gyroscope OIS chain full-scale.[set]
3155 *
3156 * @param ctx Read / write interface definitions
3157 * @param val change the values of fs_g_ois in reg CTRL1_OIS
3158 * @retval Interface status (MANDATORY: return 0 -> no Error).
3159 *
3160 */
lsm6dsm_aux_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsm_fs_g_ois_t val)3161 int32_t lsm6dsm_aux_gy_full_scale_set(const stmdev_ctx_t *ctx,
3162 lsm6dsm_fs_g_ois_t val)
3163 {
3164 lsm6dsm_ctrl1_ois_t ctrl1_ois;
3165 int32_t ret;
3166
3167 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3168
3169 if (ret == 0)
3170 {
3171 ctrl1_ois.fs_g_ois = (uint8_t)val;
3172 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3173 }
3174
3175 return ret;
3176 }
3177
3178 /**
3179 * @brief Selects gyroscope OIS chain full-scale.[get]
3180 *
3181 * @param ctx Read / write interface definitions
3182 * @param val Get the values of fs_g_ois in reg CTRL1_OIS
3183 * @retval Interface status (MANDATORY: return 0 -> no Error).
3184 *
3185 */
lsm6dsm_aux_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsm_fs_g_ois_t * val)3186 int32_t lsm6dsm_aux_gy_full_scale_get(const stmdev_ctx_t *ctx,
3187 lsm6dsm_fs_g_ois_t *val)
3188 {
3189 lsm6dsm_ctrl1_ois_t ctrl1_ois;
3190 int32_t ret;
3191
3192 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3193
3194 switch (ctrl1_ois.fs_g_ois)
3195 {
3196 case LSM6DSM_250dps_AUX:
3197 *val = LSM6DSM_250dps_AUX;
3198 break;
3199
3200 case LSM6DSM_125dps_AUX:
3201 *val = LSM6DSM_125dps_AUX;
3202 break;
3203
3204 case LSM6DSM_500dps_AUX:
3205 *val = LSM6DSM_500dps_AUX;
3206 break;
3207
3208 case LSM6DSM_1000dps_AUX:
3209 *val = LSM6DSM_1000dps_AUX;
3210 break;
3211
3212 case LSM6DSM_2000dps_AUX:
3213 *val = LSM6DSM_2000dps_AUX;
3214 break;
3215
3216 default:
3217 *val = LSM6DSM_250dps_AUX;
3218 break;
3219 }
3220
3221 return ret;
3222 }
3223
3224 /**
3225 * @brief SPI2 3- or 4-wire interface.[set]
3226 *
3227 * @param ctx Read / write interface definitions
3228 * @param val change the values of sim_ois in reg CTRL1_OIS
3229 * @retval Interface status (MANDATORY: return 0 -> no Error).
3230 *
3231 */
lsm6dsm_aux_spi_mode_set(const stmdev_ctx_t * ctx,lsm6dsm_sim_ois_t val)3232 int32_t lsm6dsm_aux_spi_mode_set(const stmdev_ctx_t *ctx,
3233 lsm6dsm_sim_ois_t val)
3234 {
3235 lsm6dsm_ctrl1_ois_t ctrl1_ois;
3236 int32_t ret;
3237
3238 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3239
3240 if (ret == 0)
3241 {
3242 ctrl1_ois.sim_ois = (uint8_t)val;
3243 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3244 }
3245
3246 return ret;
3247 }
3248
3249 /**
3250 * @brief SPI2 3- or 4-wire interface.[get]
3251 *
3252 * @param ctx Read / write interface definitions
3253 * @param val Get the values of sim_ois in reg CTRL1_OIS
3254 * @retval Interface status (MANDATORY: return 0 -> no Error).
3255 *
3256 */
lsm6dsm_aux_spi_mode_get(const stmdev_ctx_t * ctx,lsm6dsm_sim_ois_t * val)3257 int32_t lsm6dsm_aux_spi_mode_get(const stmdev_ctx_t *ctx,
3258 lsm6dsm_sim_ois_t *val)
3259 {
3260 lsm6dsm_ctrl1_ois_t ctrl1_ois;
3261 int32_t ret;
3262
3263 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3264
3265 switch (ctrl1_ois.sim_ois)
3266 {
3267 case LSM6DSM_AUX_SPI_4_WIRE:
3268 *val = LSM6DSM_AUX_SPI_4_WIRE;
3269 break;
3270
3271 case LSM6DSM_AUX_SPI_3_WIRE:
3272 *val = LSM6DSM_AUX_SPI_3_WIRE;
3273 break;
3274
3275 default:
3276 *val = LSM6DSM_AUX_SPI_4_WIRE;
3277 break;
3278 }
3279
3280 return ret;
3281 }
3282
3283 /**
3284 * @brief Big/Little Endian Data selection on aux interface.[set]
3285 *
3286 * @param ctx Read / write interface definitions
3287 * @param val change the values of ble_ois in reg CTRL1_OIS
3288 * @retval Interface status (MANDATORY: return 0 -> no Error).
3289 *
3290 */
lsm6dsm_aux_data_format_set(const stmdev_ctx_t * ctx,lsm6dsm_ble_ois_t val)3291 int32_t lsm6dsm_aux_data_format_set(const stmdev_ctx_t *ctx,
3292 lsm6dsm_ble_ois_t val)
3293 {
3294 lsm6dsm_ctrl1_ois_t ctrl1_ois;
3295 int32_t ret;
3296
3297 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3298
3299 if (ret == 0)
3300 {
3301 ctrl1_ois.ble_ois = (uint8_t)val;
3302 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3303 }
3304
3305 return ret;
3306 }
3307
3308 /**
3309 * @brief Big/Little Endian Data selection on aux interface.[get]
3310 *
3311 * @param ctx Read / write interface definitions
3312 * @param val Get the values of ble_ois in reg CTRL1_OIS
3313 * @retval Interface status (MANDATORY: return 0 -> no Error).
3314 *
3315 */
lsm6dsm_aux_data_format_get(const stmdev_ctx_t * ctx,lsm6dsm_ble_ois_t * val)3316 int32_t lsm6dsm_aux_data_format_get(const stmdev_ctx_t *ctx,
3317 lsm6dsm_ble_ois_t *val)
3318 {
3319 lsm6dsm_ctrl1_ois_t ctrl1_ois;
3320 int32_t ret;
3321
3322 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL1_OIS, (uint8_t *)&ctrl1_ois, 1);
3323
3324 switch (ctrl1_ois.ble_ois)
3325 {
3326 case LSM6DSM_AUX_LSB_AT_LOW_ADD:
3327 *val = LSM6DSM_AUX_LSB_AT_LOW_ADD;
3328 break;
3329
3330 case LSM6DSM_AUX_MSB_AT_LOW_ADD:
3331 *val = LSM6DSM_AUX_MSB_AT_LOW_ADD;
3332 break;
3333
3334 default:
3335 *val = LSM6DSM_AUX_LSB_AT_LOW_ADD;
3336 break;
3337 }
3338
3339 return ret;
3340 }
3341
3342 /**
3343 * @brief Enable / Disables OIS chain clamp.
3344 * Enable: All OIS chain outputs = 8000h
3345 * during self-test; Disable: OIS chain
3346 * self-test outputs dependent from the aux
3347 * gyro full scale selected.[set]
3348 *
3349 * @param ctx Read / write interface definitions
3350 * @param val change the values of st_ois_clampdis in reg CTRL3_OIS
3351 * @retval Interface status (MANDATORY: return 0 -> no Error).
3352 *
3353 */
lsm6dsm_aux_gy_clamp_set(const stmdev_ctx_t * ctx,lsm6dsm_st_ois_clampdis_t val)3354 int32_t lsm6dsm_aux_gy_clamp_set(const stmdev_ctx_t *ctx,
3355 lsm6dsm_st_ois_clampdis_t val)
3356 {
3357 lsm6dsm_ctrl3_ois_t ctrl3_ois;
3358 int32_t ret;
3359
3360 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3361
3362 if (ret == 0)
3363 {
3364 ctrl3_ois.st_ois_clampdis = (uint8_t)val;
3365 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3366 }
3367
3368 return ret;
3369 }
3370
3371 /**
3372 * @brief Enable / Disables OIS chain clamp.
3373 * Enable: All OIS chain outputs = 8000h
3374 * during self-test; Disable: OIS chain self-test
3375 * outputs dependent from the aux gyro full
3376 * scale selected.[get]
3377 *
3378 * @param ctx Read / write interface definitions
3379 * @param val Get the values of st_ois_clampdis in reg CTRL3_OIS
3380 * @retval Interface status (MANDATORY: return 0 -> no Error).
3381 *
3382 */
lsm6dsm_aux_gy_clamp_get(const stmdev_ctx_t * ctx,lsm6dsm_st_ois_clampdis_t * val)3383 int32_t lsm6dsm_aux_gy_clamp_get(const stmdev_ctx_t *ctx,
3384 lsm6dsm_st_ois_clampdis_t *val)
3385 {
3386 lsm6dsm_ctrl3_ois_t ctrl3_ois;
3387 int32_t ret;
3388
3389 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3390
3391 switch (ctrl3_ois.st_ois_clampdis)
3392 {
3393 case LSM6DSM_ENABLE_CLAMP:
3394 *val = LSM6DSM_ENABLE_CLAMP;
3395 break;
3396
3397 case LSM6DSM_DISABLE_CLAMP:
3398 *val = LSM6DSM_DISABLE_CLAMP;
3399 break;
3400
3401 default:
3402 *val = LSM6DSM_ENABLE_CLAMP;
3403 break;
3404 }
3405
3406 return ret;
3407 }
3408
3409 /**
3410 * @brief Selects gyroscope OIS chain self-test.[set]
3411 *
3412 * @param ctx Read / write interface definitions
3413 * @param val change the values of st_ois in reg CTRL3_OIS
3414 * @retval Interface status (MANDATORY: return 0 -> no Error).
3415 *
3416 */
lsm6dsm_aux_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6dsm_st_ois_t val)3417 int32_t lsm6dsm_aux_gy_self_test_set(const stmdev_ctx_t *ctx,
3418 lsm6dsm_st_ois_t val)
3419 {
3420 lsm6dsm_ctrl3_ois_t ctrl3_ois;
3421 int32_t ret;
3422
3423 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3424
3425 if (ret == 0)
3426 {
3427 ctrl3_ois.st_ois = (uint8_t)val;
3428 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3429 }
3430
3431 return ret;
3432 }
3433
3434 /**
3435 * @brief Selects gyroscope OIS chain self-test.[get]
3436 *
3437 * @param ctx Read / write interface definitions
3438 * @param val Get the values of st_ois in reg CTRL3_OIS
3439 * @retval Interface status (MANDATORY: return 0 -> no Error).
3440 *
3441 */
lsm6dsm_aux_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6dsm_st_ois_t * val)3442 int32_t lsm6dsm_aux_gy_self_test_get(const stmdev_ctx_t *ctx,
3443 lsm6dsm_st_ois_t *val)
3444 {
3445 lsm6dsm_ctrl3_ois_t ctrl3_ois;
3446 int32_t ret;
3447
3448 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3449
3450 switch (ctrl3_ois.st_ois)
3451 {
3452 case LSM6DSM_AUX_GY_DISABLE:
3453 *val = LSM6DSM_AUX_GY_DISABLE;
3454 break;
3455
3456 case LSM6DSM_AUX_GY_POS:
3457 *val = LSM6DSM_AUX_GY_POS;
3458 break;
3459
3460 case LSM6DSM_AUX_GY_NEG:
3461 *val = LSM6DSM_AUX_GY_NEG;
3462 break;
3463
3464 default:
3465 *val = LSM6DSM_AUX_GY_DISABLE;
3466 break;
3467 }
3468
3469 return ret;
3470 }
3471
3472 /**
3473 * @brief Selects accelerometer OIS channel full-scale.[set]
3474 *
3475 * @param ctx Read / write interface definitions
3476 * @param val change the values of fs_xl_ois in reg CTRL3_OIS
3477 * @retval Interface status (MANDATORY: return 0 -> no Error).
3478 *
3479 */
lsm6dsm_aux_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsm_fs_xl_ois_t val)3480 int32_t lsm6dsm_aux_xl_full_scale_set(const stmdev_ctx_t *ctx,
3481 lsm6dsm_fs_xl_ois_t val)
3482 {
3483 lsm6dsm_ctrl3_ois_t ctrl3_ois;
3484 int32_t ret;
3485
3486 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3487
3488 if (ret == 0)
3489 {
3490 ctrl3_ois.fs_xl_ois = (uint8_t)val;
3491 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3492 }
3493
3494 return ret;
3495 }
3496
3497 /**
3498 * @brief Selects accelerometer OIS channel full-scale.[get]
3499 *
3500 * @param ctx Read / write interface definitions
3501 * @param val Get the values of fs_xl_ois in reg CTRL3_OIS
3502 * @retval Interface status (MANDATORY: return 0 -> no Error).
3503 *
3504 */
lsm6dsm_aux_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsm_fs_xl_ois_t * val)3505 int32_t lsm6dsm_aux_xl_full_scale_get(const stmdev_ctx_t *ctx,
3506 lsm6dsm_fs_xl_ois_t *val)
3507 {
3508 lsm6dsm_ctrl3_ois_t ctrl3_ois;
3509 int32_t ret;
3510
3511 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3512
3513 switch (ctrl3_ois.fs_xl_ois)
3514 {
3515 case LSM6DSM_AUX_2g:
3516 *val = LSM6DSM_AUX_2g;
3517 break;
3518
3519 case LSM6DSM_AUX_16g:
3520 *val = LSM6DSM_AUX_16g;
3521 break;
3522
3523 case LSM6DSM_AUX_4g:
3524 *val = LSM6DSM_AUX_4g;
3525 break;
3526
3527 case LSM6DSM_AUX_8g:
3528 *val = LSM6DSM_AUX_8g;
3529 break;
3530
3531 default:
3532 *val = LSM6DSM_AUX_2g;
3533 break;
3534 }
3535
3536 return ret;
3537 }
3538
3539 /**
3540 * @brief Indicates polarity of DEN signal on OIS chain.[set]
3541 *
3542 * @param ctx Read / write interface definitions
3543 * @param val change the values of den_lh_ois in reg CTRL3_OIS
3544 * @retval Interface status (MANDATORY: return 0 -> no Error).
3545 *
3546 */
lsm6dsm_aux_den_polarity_set(const stmdev_ctx_t * ctx,lsm6dsm_den_lh_ois_t val)3547 int32_t lsm6dsm_aux_den_polarity_set(const stmdev_ctx_t *ctx,
3548 lsm6dsm_den_lh_ois_t val)
3549 {
3550 lsm6dsm_ctrl3_ois_t ctrl3_ois;
3551 int32_t ret;
3552
3553 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3554
3555 if (ret == 0)
3556 {
3557 ctrl3_ois.den_lh_ois = (uint8_t)val;
3558 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3559 }
3560
3561 return ret;
3562 }
3563
3564 /**
3565 * @brief Indicates polarity of DEN signal on OIS chain.[get]
3566 *
3567 * @param ctx Read / write interface definitions
3568 * @param val Get the values of den_lh_ois in reg CTRL3_OIS
3569 * @retval Interface status (MANDATORY: return 0 -> no Error).
3570 *
3571 */
lsm6dsm_aux_den_polarity_get(const stmdev_ctx_t * ctx,lsm6dsm_den_lh_ois_t * val)3572 int32_t lsm6dsm_aux_den_polarity_get(const stmdev_ctx_t *ctx,
3573 lsm6dsm_den_lh_ois_t *val)
3574 {
3575 lsm6dsm_ctrl3_ois_t ctrl3_ois;
3576 int32_t ret;
3577
3578 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_OIS, (uint8_t *)&ctrl3_ois, 1);
3579
3580 switch (ctrl3_ois.den_lh_ois)
3581 {
3582 case LSM6DSM_AUX_DEN_ACTIVE_LOW:
3583 *val = LSM6DSM_AUX_DEN_ACTIVE_LOW;
3584 break;
3585
3586 case LSM6DSM_AUX_DEN_ACTIVE_HIGH:
3587 *val = LSM6DSM_AUX_DEN_ACTIVE_HIGH;
3588 break;
3589
3590 default:
3591 *val = LSM6DSM_AUX_DEN_ACTIVE_LOW;
3592 break;
3593 }
3594
3595 return ret;
3596 }
3597
3598 /**
3599 * @}
3600 *
3601 */
3602
3603 /**
3604 * @defgroup LSM6DSM main serial_interface
3605 * @brief This section groups all the functions concerning serial
3606 * interface management
3607 * @{
3608 *
3609 */
3610
3611 /**
3612 * @brief SPI Serial Interface Mode selection.[set]
3613 *
3614 * @param ctx Read / write interface definitions
3615 * @param val Change the values of sim in reg CTRL3_C
3616 * @retval Interface status (MANDATORY: return 0 -> no Error).
3617 *
3618 */
lsm6dsm_spi_mode_set(const stmdev_ctx_t * ctx,lsm6dsm_sim_t val)3619 int32_t lsm6dsm_spi_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_sim_t val)
3620 {
3621 lsm6dsm_ctrl3_c_t ctrl3_c;
3622 int32_t ret;
3623
3624 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3625
3626 if (ret == 0)
3627 {
3628 ctrl3_c.sim = (uint8_t)val;
3629 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3630 }
3631
3632 return ret;
3633 }
3634
3635 /**
3636 * @brief SPI Serial Interface Mode selection.[get]
3637 *
3638 * @param ctx Read / write interface definitions
3639 * @param val Get the values of sim in reg CTRL3_C
3640 * @retval Interface status (MANDATORY: return 0 -> no Error).
3641 *
3642 */
lsm6dsm_spi_mode_get(const stmdev_ctx_t * ctx,lsm6dsm_sim_t * val)3643 int32_t lsm6dsm_spi_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_sim_t *val)
3644 {
3645 lsm6dsm_ctrl3_c_t ctrl3_c;
3646 int32_t ret;
3647
3648 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3649
3650 switch (ctrl3_c.sim)
3651 {
3652 case LSM6DSM_SPI_4_WIRE:
3653 *val = LSM6DSM_SPI_4_WIRE;
3654 break;
3655
3656 case LSM6DSM_SPI_3_WIRE:
3657 *val = LSM6DSM_SPI_3_WIRE;
3658 break;
3659
3660 default:
3661 *val = LSM6DSM_SPI_4_WIRE;
3662 break;
3663 }
3664
3665 return ret;
3666 }
3667
3668 /**
3669 * @brief Disable / Enable I2C interface.[set]
3670 *
3671 * @param ctx Read / write interface definitions
3672 * @param val Change the values of i2c_disable in reg CTRL4_C
3673 * @retval Interface status (MANDATORY: return 0 -> no Error).
3674 *
3675 */
lsm6dsm_i2c_interface_set(const stmdev_ctx_t * ctx,lsm6dsm_i2c_disable_t val)3676 int32_t lsm6dsm_i2c_interface_set(const stmdev_ctx_t *ctx,
3677 lsm6dsm_i2c_disable_t val)
3678 {
3679 lsm6dsm_ctrl4_c_t ctrl4_c;
3680 int32_t ret;
3681
3682 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3683
3684 if (ret == 0)
3685 {
3686 ctrl4_c.i2c_disable = (uint8_t)val;
3687 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3688 }
3689
3690 return ret;
3691 }
3692
3693 /**
3694 * @brief Disable / Enable I2C interface.[get]
3695 *
3696 * @param ctx Read / write interface definitions
3697 * @param val Get the values of i2c_disable in reg CTRL4_C
3698 * @retval Interface status (MANDATORY: return 0 -> no Error).
3699 *
3700 */
lsm6dsm_i2c_interface_get(const stmdev_ctx_t * ctx,lsm6dsm_i2c_disable_t * val)3701 int32_t lsm6dsm_i2c_interface_get(const stmdev_ctx_t *ctx,
3702 lsm6dsm_i2c_disable_t *val)
3703 {
3704 lsm6dsm_ctrl4_c_t ctrl4_c;
3705 int32_t ret;
3706
3707 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3708
3709 switch (ctrl4_c.i2c_disable)
3710 {
3711 case LSM6DSM_I2C_ENABLE:
3712 *val = LSM6DSM_I2C_ENABLE;
3713 break;
3714
3715 case LSM6DSM_I2C_DISABLE:
3716 *val = LSM6DSM_I2C_DISABLE;
3717 break;
3718
3719 default:
3720 *val = LSM6DSM_I2C_ENABLE;
3721 break;
3722 }
3723
3724 return ret;
3725 }
3726
3727 /**
3728 * @}
3729 *
3730 */
3731
3732 /**
3733 * @defgroup LSM6DSM_interrupt_pins
3734 * @brief This section groups all the functions that manage
3735 * interrupt pins
3736 * @{
3737 *
3738 */
3739
3740 /**
3741 * @brief Select the signal that need to route on int1 pad[set]
3742 *
3743 * @param ctx Read / write interface definitions
3744 * @param val configure INT1_CTRL, MD1_CFG, CTRL4_C(den_drdy_int1),
3745 * MASTER_CONFIG(drdy_on_int1)
3746 * @retval Interface status (MANDATORY: return 0 -> no Error).
3747 *
3748 */
lsm6dsm_pin_int1_route_set(const stmdev_ctx_t * ctx,lsm6dsm_int1_route_t val)3749 int32_t lsm6dsm_pin_int1_route_set(const stmdev_ctx_t *ctx,
3750 lsm6dsm_int1_route_t val)
3751 {
3752 lsm6dsm_master_config_t master_config;
3753 lsm6dsm_int1_ctrl_t int1_ctrl;
3754 lsm6dsm_md1_cfg_t md1_cfg;
3755 lsm6dsm_md2_cfg_t md2_cfg;
3756 lsm6dsm_ctrl4_c_t ctrl4_c;
3757 lsm6dsm_tap_cfg_t tap_cfg;
3758 int32_t ret;
3759
3760 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
3761
3762 if (ret == 0)
3763 {
3764 int1_ctrl.int1_drdy_xl = val.int1_drdy_xl;
3765 int1_ctrl.int1_drdy_g = val.int1_drdy_g;
3766 int1_ctrl.int1_boot = val.int1_boot;
3767 int1_ctrl.int1_fth = val.int1_fth;
3768 int1_ctrl.int1_fifo_ovr = val.int1_fifo_ovr;
3769 int1_ctrl.int1_full_flag = val.int1_full_flag;
3770 int1_ctrl.int1_sign_mot = val.int1_sign_mot;
3771 int1_ctrl.int1_step_detector = val.int1_step_detector;
3772 ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
3773 }
3774
3775 if (ret == 0)
3776 {
3777 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3778 }
3779
3780 if (ret == 0)
3781 {
3782 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3783 }
3784
3785 if (ret == 0)
3786 {
3787 md1_cfg.int1_timer = val.int1_timer;
3788 md1_cfg.int1_tilt = val.int1_tilt;
3789 md1_cfg.int1_6d = val.int1_6d;
3790 md1_cfg.int1_double_tap = val.int1_double_tap;
3791 md1_cfg.int1_ff = val.int1_ff;
3792 md1_cfg.int1_wu = val.int1_wu;
3793 md1_cfg.int1_single_tap = val.int1_single_tap;
3794 md1_cfg.int1_inact_state = val.int1_inact_state;
3795 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3796 }
3797
3798 if (ret == 0)
3799 {
3800 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3801 }
3802
3803 if (ret == 0)
3804 {
3805 ctrl4_c.den_drdy_int1 = val.den_drdy_int1;
3806 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3807 }
3808
3809 if (ret == 0)
3810 {
3811 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
3812 (uint8_t *)&master_config, 1);
3813 }
3814
3815 if (ret == 0)
3816 {
3817 master_config.drdy_on_int1 = val.den_drdy_int1;
3818 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
3819 (uint8_t *)&master_config, 1);
3820 }
3821
3822 if (ret == 0)
3823 {
3824 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3825
3826 if ((val.int1_6d != 0x00U) ||
3827 (val.int1_ff != 0x00U) ||
3828 (val.int1_wu != 0x00U) ||
3829 (val.int1_single_tap != 0x00U) ||
3830 (val.int1_double_tap != 0x00U) ||
3831 (val.int1_inact_state != 0x00U) ||
3832 (md2_cfg.int2_6d != 0x00U) ||
3833 (md2_cfg.int2_ff != 0x00U) ||
3834 (md2_cfg.int2_wu != 0x00U) ||
3835 (md2_cfg.int2_single_tap != 0x00U) ||
3836 (md2_cfg.int2_double_tap != 0x00U) ||
3837 (md2_cfg.int2_inact_state != 0x00U))
3838 {
3839 tap_cfg.interrupts_enable = PROPERTY_ENABLE;
3840 }
3841
3842 else
3843 {
3844 tap_cfg.interrupts_enable = PROPERTY_DISABLE;
3845 }
3846 }
3847
3848 if (ret == 0)
3849 {
3850 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3851 }
3852
3853 return ret;
3854 }
3855
3856 /**
3857 * @brief Select the signal that need to route on int1 pad[get]
3858 *
3859 * @param ctx Read / write interface definitions
3860 * @param val read INT1_CTRL, MD1_CFG, CTRL4_C(den_drdy_int1),
3861 * MASTER_CONFIG(drdy_on_int1)
3862 * @retval Interface status (MANDATORY: return 0 -> no Error).
3863 *
3864 */
lsm6dsm_pin_int1_route_get(const stmdev_ctx_t * ctx,lsm6dsm_int1_route_t * val)3865 int32_t lsm6dsm_pin_int1_route_get(const stmdev_ctx_t *ctx,
3866 lsm6dsm_int1_route_t *val)
3867 {
3868 lsm6dsm_master_config_t master_config;
3869 lsm6dsm_int1_ctrl_t int1_ctrl;
3870 lsm6dsm_md1_cfg_t md1_cfg;
3871 lsm6dsm_ctrl4_c_t ctrl4_c;
3872 int32_t ret;
3873
3874 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
3875
3876 if (ret == 0)
3877 {
3878 val->int1_drdy_xl = int1_ctrl.int1_drdy_xl;
3879 val->int1_drdy_g = int1_ctrl.int1_drdy_g;
3880 val->int1_boot = int1_ctrl.int1_boot;
3881 val->int1_fth = int1_ctrl.int1_fth;
3882 val->int1_fifo_ovr = int1_ctrl.int1_fifo_ovr;
3883 val->int1_full_flag = int1_ctrl.int1_full_flag;
3884 val->int1_sign_mot = int1_ctrl.int1_sign_mot;
3885 val->int1_step_detector = int1_ctrl.int1_step_detector ;
3886 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3887
3888 if (ret == 0)
3889 {
3890 val->int1_timer = md1_cfg.int1_timer;
3891 val->int1_tilt = md1_cfg.int1_tilt;
3892 val->int1_6d = md1_cfg.int1_6d;
3893 val->int1_double_tap = md1_cfg.int1_double_tap;
3894 val->int1_ff = md1_cfg.int1_ff;
3895 val->int1_wu = md1_cfg.int1_wu;
3896 val->int1_single_tap = md1_cfg.int1_single_tap;
3897 val->int1_inact_state = md1_cfg.int1_inact_state;
3898 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3899
3900 if (ret == 0)
3901 {
3902 val->den_drdy_int1 = ctrl4_c.den_drdy_int1;
3903 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
3904 (uint8_t *)&master_config, 1);
3905 val->den_drdy_int1 = master_config.drdy_on_int1;
3906 }
3907 }
3908 }
3909
3910 return ret;
3911 }
3912
3913 /**
3914 * @brief Select the signal that need to route on int2 pad[set]
3915 *
3916 * @param ctx Read / write interface definitions
3917 * @param val INT2_CTRL, DRDY_PULSE_CFG(int2_wrist_tilt), MD2_CFG
3918 * @retval Interface status (MANDATORY: return 0 -> no Error).
3919 *
3920 */
lsm6dsm_pin_int2_route_set(const stmdev_ctx_t * ctx,lsm6dsm_int2_route_t val)3921 int32_t lsm6dsm_pin_int2_route_set(const stmdev_ctx_t *ctx,
3922 lsm6dsm_int2_route_t val)
3923 {
3924 lsm6dsm_int2_ctrl_t int2_ctrl;
3925 lsm6dsm_md1_cfg_t md1_cfg;
3926 lsm6dsm_md2_cfg_t md2_cfg;
3927 lsm6dsm_drdy_pulse_cfg_t drdy_pulse_cfg;
3928 lsm6dsm_tap_cfg_t tap_cfg;
3929 int32_t ret;
3930
3931 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3932
3933 if (ret == 0)
3934 {
3935 int2_ctrl.int2_drdy_xl = val.int2_drdy_xl;
3936 int2_ctrl.int2_drdy_g = val.int2_drdy_g;
3937 int2_ctrl.int2_drdy_temp = val.int2_drdy_temp;
3938 int2_ctrl.int2_fth = val.int2_fth;
3939 int2_ctrl.int2_fifo_ovr = val.int2_fifo_ovr;
3940 int2_ctrl.int2_full_flag = val.int2_full_flag;
3941 int2_ctrl.int2_step_count_ov = val.int2_step_count_ov;
3942 int2_ctrl.int2_step_delta = val.int2_step_delta;
3943 ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
3944 }
3945
3946 if (ret == 0)
3947 {
3948 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD1_CFG, (uint8_t *)&md1_cfg, 1);
3949 }
3950
3951 if (ret == 0)
3952 {
3953 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3954 }
3955
3956 if (ret == 0)
3957 {
3958 md2_cfg.int2_iron = val.int2_iron;
3959 md2_cfg.int2_tilt = val.int2_tilt;
3960 md2_cfg.int2_6d = val.int2_6d;
3961 md2_cfg.int2_double_tap = val.int2_double_tap;
3962 md2_cfg.int2_ff = val.int2_ff;
3963 md2_cfg.int2_wu = val.int2_wu;
3964 md2_cfg.int2_single_tap = val.int2_single_tap;
3965 md2_cfg.int2_inact_state = val.int2_inact_state;
3966 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MD2_CFG, (uint8_t *)&md2_cfg, 1);
3967 }
3968
3969 if (ret == 0)
3970 {
3971 ret = lsm6dsm_read_reg(ctx, LSM6DSM_DRDY_PULSE_CFG,
3972 (uint8_t *)&drdy_pulse_cfg, 1);
3973 }
3974
3975 if (ret == 0)
3976 {
3977 drdy_pulse_cfg.int2_wrist_tilt = val.int2_wrist_tilt;
3978 ret = lsm6dsm_write_reg(ctx, LSM6DSM_DRDY_PULSE_CFG,
3979 (uint8_t *)&drdy_pulse_cfg, 1);
3980 }
3981
3982 if (ret == 0)
3983 {
3984 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3985
3986 if ((md1_cfg.int1_6d != 0x00U) ||
3987 (md1_cfg.int1_ff != 0x00U) ||
3988 (md1_cfg.int1_wu != 0x00U) ||
3989 (md1_cfg.int1_single_tap != 0x00U) ||
3990 (md1_cfg.int1_double_tap != 0x00U) ||
3991 (md1_cfg.int1_inact_state != 0x00U) ||
3992 (val.int2_6d != 0x00U) ||
3993 (val.int2_ff != 0x00U) ||
3994 (val.int2_wu != 0x00U) ||
3995 (val.int2_single_tap != 0x00U) ||
3996 (val.int2_double_tap != 0x00U) ||
3997 (val.int2_inact_state != 0x00U))
3998 {
3999 tap_cfg.interrupts_enable = PROPERTY_ENABLE;
4000 }
4001
4002 else
4003 {
4004 tap_cfg.interrupts_enable = PROPERTY_DISABLE;
4005 }
4006 }
4007
4008 if (ret == 0)
4009 {
4010 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4011 }
4012
4013 return ret;
4014 }
4015
4016 /**
4017 * @brief Select the signal that need to route on int2 pad[get]
4018 *
4019 * @param ctx Read / write interface definitions
4020 * @param val INT2_CTRL, DRDY_PULSE_CFG(int2_wrist_tilt), MD2_CFG
4021 * @retval Interface status (MANDATORY: return 0 -> no Error).
4022 *
4023 */
lsm6dsm_pin_int2_route_get(const stmdev_ctx_t * ctx,lsm6dsm_int2_route_t * val)4024 int32_t lsm6dsm_pin_int2_route_get(const stmdev_ctx_t *ctx,
4025 lsm6dsm_int2_route_t *val)
4026 {
4027 lsm6dsm_int2_ctrl_t int2_ctrl;
4028 lsm6dsm_md2_cfg_t md2_cfg;
4029 lsm6dsm_drdy_pulse_cfg_t drdy_pulse_cfg;
4030 int32_t ret;
4031
4032 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
4033
4034 if (ret == 0)
4035 {
4036 val->int2_drdy_xl = int2_ctrl.int2_drdy_xl;
4037 val->int2_drdy_g = int2_ctrl.int2_drdy_g;
4038 val->int2_drdy_temp = int2_ctrl.int2_drdy_temp;
4039 val->int2_fth = int2_ctrl.int2_fth;
4040 val->int2_fifo_ovr = int2_ctrl.int2_fifo_ovr;
4041 val->int2_full_flag = int2_ctrl.int2_full_flag;
4042 val->int2_step_count_ov = int2_ctrl.int2_step_count_ov;
4043 val->int2_step_delta = int2_ctrl.int2_step_delta;
4044 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MD2_CFG, (uint8_t *)&md2_cfg, 1);
4045
4046 if (ret == 0)
4047 {
4048 val->int2_iron = md2_cfg.int2_iron;
4049 val->int2_tilt = md2_cfg.int2_tilt;
4050 val->int2_6d = md2_cfg.int2_6d;
4051 val->int2_double_tap = md2_cfg.int2_double_tap;
4052 val->int2_ff = md2_cfg.int2_ff;
4053 val->int2_wu = md2_cfg.int2_wu;
4054 val->int2_single_tap = md2_cfg.int2_single_tap;
4055 val->int2_inact_state = md2_cfg.int2_inact_state;
4056 ret = lsm6dsm_read_reg(ctx, LSM6DSM_DRDY_PULSE_CFG,
4057 (uint8_t *)&drdy_pulse_cfg, 1);
4058 val->int2_wrist_tilt = drdy_pulse_cfg.int2_wrist_tilt;
4059 }
4060 }
4061
4062 return ret;
4063 }
4064
4065 /**
4066 * @brief Push-pull/open drain selection on interrupt pads.[set]
4067 *
4068 * @param ctx Read / write interface definitions
4069 * @param val Change the values of pp_od in reg CTRL3_C
4070 * @retval Interface status (MANDATORY: return 0 -> no Error).
4071 *
4072 */
lsm6dsm_pin_mode_set(const stmdev_ctx_t * ctx,lsm6dsm_pp_od_t val)4073 int32_t lsm6dsm_pin_mode_set(const stmdev_ctx_t *ctx, lsm6dsm_pp_od_t val)
4074 {
4075 lsm6dsm_ctrl3_c_t ctrl3_c;
4076 int32_t ret;
4077
4078 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4079
4080 if (ret == 0)
4081 {
4082 ctrl3_c.pp_od = (uint8_t) val;
4083 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4084 }
4085
4086 return ret;
4087 }
4088
4089 /**
4090 * @brief Push-pull/open drain selection on interrupt pads.[get]
4091 *
4092 * @param ctx Read / write interface definitions
4093 * @param val Get the values of pp_od in reg CTRL3_C
4094 * @retval Interface status (MANDATORY: return 0 -> no Error).
4095 *
4096 */
lsm6dsm_pin_mode_get(const stmdev_ctx_t * ctx,lsm6dsm_pp_od_t * val)4097 int32_t lsm6dsm_pin_mode_get(const stmdev_ctx_t *ctx, lsm6dsm_pp_od_t *val)
4098 {
4099 lsm6dsm_ctrl3_c_t ctrl3_c;
4100 int32_t ret;
4101
4102 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4103
4104 switch (ctrl3_c.pp_od)
4105 {
4106 case LSM6DSM_PUSH_PULL:
4107 *val = LSM6DSM_PUSH_PULL;
4108 break;
4109
4110 case LSM6DSM_OPEN_DRAIN:
4111 *val = LSM6DSM_OPEN_DRAIN;
4112 break;
4113
4114 default:
4115 *val = LSM6DSM_PUSH_PULL;
4116 break;
4117 }
4118
4119 return ret;
4120 }
4121
4122 /**
4123 * @brief Interrupt active-high/low.[set]
4124 *
4125 * @param ctx Read / write interface definitions
4126 * @param val Change the values of h_lactive in reg CTRL3_C
4127 * @retval Interface status (MANDATORY: return 0 -> no Error).
4128 *
4129 */
lsm6dsm_pin_polarity_set(const stmdev_ctx_t * ctx,lsm6dsm_h_lactive_t val)4130 int32_t lsm6dsm_pin_polarity_set(const stmdev_ctx_t *ctx,
4131 lsm6dsm_h_lactive_t val)
4132 {
4133 lsm6dsm_ctrl3_c_t ctrl3_c;
4134 int32_t ret;
4135
4136 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4137
4138 if (ret == 0)
4139 {
4140 ctrl3_c.h_lactive = (uint8_t) val;
4141 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4142 }
4143
4144 return ret;
4145 }
4146
4147 /**
4148 * @brief Interrupt active-high/low.[get]
4149 *
4150 * @param ctx Read / write interface definitions
4151 * @param val Get the values of h_lactive in reg CTRL3_C
4152 * @retval Interface status (MANDATORY: return 0 -> no Error).
4153 *
4154 */
lsm6dsm_pin_polarity_get(const stmdev_ctx_t * ctx,lsm6dsm_h_lactive_t * val)4155 int32_t lsm6dsm_pin_polarity_get(const stmdev_ctx_t *ctx,
4156 lsm6dsm_h_lactive_t *val)
4157 {
4158 lsm6dsm_ctrl3_c_t ctrl3_c;
4159 int32_t ret;
4160
4161 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
4162
4163 switch (ctrl3_c.h_lactive)
4164 {
4165 case LSM6DSM_ACTIVE_HIGH:
4166 *val = LSM6DSM_ACTIVE_HIGH;
4167 break;
4168
4169 case LSM6DSM_ACTIVE_LOW:
4170 *val = LSM6DSM_ACTIVE_LOW;
4171 break;
4172
4173 default:
4174 *val = LSM6DSM_ACTIVE_HIGH;
4175 break;
4176 }
4177
4178 return ret;
4179 }
4180
4181 /**
4182 * @brief All interrupt signals become available on INT1 pin.[set]
4183 *
4184 * @param ctx Read / write interface definitions
4185 * @param val Change the values of int2_on_int1 in reg CTRL4_C
4186 * @retval Interface status (MANDATORY: return 0 -> no Error).
4187 *
4188 */
lsm6dsm_all_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)4189 int32_t lsm6dsm_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
4190 {
4191 lsm6dsm_ctrl4_c_t ctrl4_c;
4192 int32_t ret;
4193
4194 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4195
4196 if (ret == 0)
4197 {
4198 ctrl4_c.int2_on_int1 = val;
4199 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4200 }
4201
4202 return ret;
4203 }
4204
4205 /**
4206 * @brief All interrupt signals become available on INT1 pin.[get]
4207 *
4208 * @param ctx Read / write interface definitions
4209 * @param val Change the values of int2_on_int1 in reg CTRL4_C
4210 * @retval Interface status (MANDATORY: return 0 -> no Error).
4211 *
4212 */
lsm6dsm_all_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)4213 int32_t lsm6dsm_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
4214 {
4215 lsm6dsm_ctrl4_c_t ctrl4_c;
4216 int32_t ret;
4217
4218 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4219 *val = ctrl4_c.int2_on_int1;
4220
4221 return ret;
4222 }
4223
4224 /**
4225 * @brief Latched/pulsed interrupt.[set]
4226 *
4227 * @param ctx Read / write interface definitions
4228 * @param val Change the values of lir in reg TAP_CFG
4229 * @retval Interface status (MANDATORY: return 0 -> no Error).
4230 *
4231 */
lsm6dsm_int_notification_set(const stmdev_ctx_t * ctx,lsm6dsm_lir_t val)4232 int32_t lsm6dsm_int_notification_set(const stmdev_ctx_t *ctx,
4233 lsm6dsm_lir_t val)
4234 {
4235 lsm6dsm_tap_cfg_t tap_cfg;
4236 int32_t ret;
4237
4238 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4239
4240 if (ret == 0)
4241 {
4242 tap_cfg.lir = (uint8_t) val;
4243 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4244 }
4245
4246 return ret;
4247 }
4248
4249 /**
4250 * @brief Latched/pulsed interrupt.[get]
4251 *
4252 * @param ctx Read / write interface definitions
4253 * @param val Get the values of lir in reg TAP_CFG
4254 * @retval Interface status (MANDATORY: return 0 -> no Error).
4255 *
4256 */
lsm6dsm_int_notification_get(const stmdev_ctx_t * ctx,lsm6dsm_lir_t * val)4257 int32_t lsm6dsm_int_notification_get(const stmdev_ctx_t *ctx,
4258 lsm6dsm_lir_t *val)
4259 {
4260 lsm6dsm_tap_cfg_t tap_cfg;
4261 int32_t ret;
4262
4263 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4264
4265 switch (tap_cfg.lir)
4266 {
4267 case LSM6DSM_INT_PULSED:
4268 *val = LSM6DSM_INT_PULSED;
4269 break;
4270
4271 case LSM6DSM_INT_LATCHED:
4272 *val = LSM6DSM_INT_LATCHED;
4273 break;
4274
4275 default:
4276 *val = LSM6DSM_INT_PULSED;
4277 break;
4278 }
4279
4280 return ret;
4281 }
4282
4283 /**
4284 * @}
4285 *
4286 */
4287
4288 /**
4289 * @defgroup LSM6DSM_Wake_Up_event
4290 * @brief This section groups all the functions that manage the
4291 * Wake Up event generation.
4292 * @{
4293 *
4294 */
4295
4296 /**
4297 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set]
4298 *
4299 * @param ctx Read / write interface definitions
4300 * @param val Change the values of wk_ths in reg WAKE_UP_THS
4301 * @retval Interface status (MANDATORY: return 0 -> no Error).
4302 *
4303 */
lsm6dsm_wkup_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)4304 int32_t lsm6dsm_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
4305 {
4306 lsm6dsm_wake_up_ths_t wake_up_ths;
4307 int32_t ret;
4308
4309 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_THS,
4310 (uint8_t *)&wake_up_ths, 1);
4311
4312 if (ret == 0)
4313 {
4314 wake_up_ths.wk_ths = val;
4315 ret = lsm6dsm_write_reg(ctx, LSM6DSM_WAKE_UP_THS,
4316 (uint8_t *)&wake_up_ths, 1);
4317 }
4318
4319 return ret;
4320 }
4321
4322 /**
4323 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get]
4324 *
4325 * @param ctx Read / write interface definitions
4326 * @param val Change the values of wk_ths in reg WAKE_UP_THS
4327 * @retval Interface status (MANDATORY: return 0 -> no Error).
4328 *
4329 */
lsm6dsm_wkup_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)4330 int32_t lsm6dsm_wkup_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
4331 {
4332 lsm6dsm_wake_up_ths_t wake_up_ths;
4333 int32_t ret;
4334
4335 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_THS,
4336 (uint8_t *)&wake_up_ths, 1);
4337 *val = wake_up_ths.wk_ths;
4338
4339 return ret;
4340 }
4341
4342 /**
4343 * @brief Wake up duration event.1LSb = 1 / ODR[set]
4344 *
4345 * @param ctx Read / write interface definitions
4346 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
4347 * @retval Interface status (MANDATORY: return 0 -> no Error).
4348 *
4349 */
lsm6dsm_wkup_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4350 int32_t lsm6dsm_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4351 {
4352 lsm6dsm_wake_up_dur_t wake_up_dur;
4353 int32_t ret;
4354
4355 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
4356 (uint8_t *)&wake_up_dur, 1);
4357
4358 if (ret == 0)
4359 {
4360 wake_up_dur.wake_dur = val;
4361 ret = lsm6dsm_write_reg(ctx, LSM6DSM_WAKE_UP_DUR,
4362 (uint8_t *)&wake_up_dur, 1);
4363 }
4364
4365 return ret;
4366 }
4367
4368 /**
4369 * @brief Wake up duration event.1LSb = 1 / ODR[get]
4370 *
4371 * @param ctx Read / write interface definitions
4372 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
4373 * @retval Interface status (MANDATORY: return 0 -> no Error).
4374 *
4375 */
lsm6dsm_wkup_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4376 int32_t lsm6dsm_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4377 {
4378 lsm6dsm_wake_up_dur_t wake_up_dur;
4379 int32_t ret;
4380
4381 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
4382 (uint8_t *)&wake_up_dur, 1);
4383 *val = wake_up_dur.wake_dur;
4384
4385 return ret;
4386 }
4387
4388 /**
4389 * @}
4390 *
4391 */
4392
4393 /**
4394 * @defgroup LSM6DSM_Activity/Inactivity_detection
4395 * @brief This section groups all the functions concerning
4396 * activity/inactivity detection.
4397 * @{
4398 *
4399 */
4400
4401 /**
4402 * @brief Enables gyroscope Sleep mode.[set]
4403 *
4404 * @param ctx Read / write interface definitions
4405 * @param val Change the values of sleep in reg CTRL4_C
4406 * @retval Interface status (MANDATORY: return 0 -> no Error).
4407 *
4408 */
lsm6dsm_gy_sleep_mode_set(const stmdev_ctx_t * ctx,uint8_t val)4409 int32_t lsm6dsm_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
4410 {
4411 lsm6dsm_ctrl4_c_t ctrl4_c;
4412 int32_t ret;
4413
4414 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4415
4416 if (ret == 0)
4417 {
4418 ctrl4_c.sleep = val;
4419 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4420 }
4421
4422 return ret;
4423 }
4424
4425 /**
4426 * @brief Enables gyroscope Sleep mode.[get]
4427 *
4428 * @param ctx Read / write interface definitions
4429 * @param val Change the values of sleep in reg CTRL4_C
4430 * @retval Interface status (MANDATORY: return 0 -> no Error).
4431 *
4432 */
lsm6dsm_gy_sleep_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)4433 int32_t lsm6dsm_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
4434 {
4435 lsm6dsm_ctrl4_c_t ctrl4_c;
4436 int32_t ret;
4437
4438 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
4439 *val = ctrl4_c.sleep;
4440
4441 return ret;
4442 }
4443
4444 /**
4445 * @brief Enable inactivity function.[set]
4446 *
4447 * @param ctx Read / write interface definitions
4448 * @param val Change the values of inact_en in reg TAP_CFG
4449 * @retval Interface status (MANDATORY: return 0 -> no Error).
4450 *
4451 */
lsm6dsm_act_mode_set(const stmdev_ctx_t * ctx,lsm6dsm_inact_en_t val)4452 int32_t lsm6dsm_act_mode_set(const stmdev_ctx_t *ctx,
4453 lsm6dsm_inact_en_t val)
4454 {
4455 lsm6dsm_tap_cfg_t tap_cfg;
4456 int32_t ret;
4457
4458 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4459
4460 if (ret == 0)
4461 {
4462 tap_cfg.inact_en = (uint8_t) val;
4463 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4464 }
4465
4466 return ret;
4467 }
4468
4469 /**
4470 * @brief Enable inactivity function.[get]
4471 *
4472 * @param ctx Read / write interface definitions
4473 * @param val Get the values of inact_en in reg TAP_CFG
4474 * @retval Interface status (MANDATORY: return 0 -> no Error).
4475 *
4476 */
lsm6dsm_act_mode_get(const stmdev_ctx_t * ctx,lsm6dsm_inact_en_t * val)4477 int32_t lsm6dsm_act_mode_get(const stmdev_ctx_t *ctx,
4478 lsm6dsm_inact_en_t *val)
4479 {
4480 lsm6dsm_tap_cfg_t tap_cfg;
4481 int32_t ret;
4482
4483 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4484
4485 switch (tap_cfg.inact_en)
4486 {
4487 case LSM6DSM_PROPERTY_DISABLE:
4488 *val = LSM6DSM_PROPERTY_DISABLE;
4489 break;
4490
4491 case LSM6DSM_XL_12Hz5_GY_NOT_AFFECTED:
4492 *val = LSM6DSM_XL_12Hz5_GY_NOT_AFFECTED;
4493 break;
4494
4495 case LSM6DSM_XL_12Hz5_GY_SLEEP:
4496 *val = LSM6DSM_XL_12Hz5_GY_SLEEP;
4497 break;
4498
4499 case LSM6DSM_XL_12Hz5_GY_PD:
4500 *val = LSM6DSM_XL_12Hz5_GY_PD;
4501 break;
4502
4503 default:
4504 *val = LSM6DSM_PROPERTY_DISABLE;
4505 break;
4506 }
4507
4508 return ret;
4509 }
4510
4511 /**
4512 * @brief Duration to go in sleep mode.1 LSb = 512 / ODR[set]
4513 *
4514 * @param ctx Read / write interface definitions
4515 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
4516 * @retval Interface status (MANDATORY: return 0 -> no Error).
4517 *
4518 */
lsm6dsm_act_sleep_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4519 int32_t lsm6dsm_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4520 {
4521 lsm6dsm_wake_up_dur_t wake_up_dur;
4522 int32_t ret;
4523
4524 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
4525 (uint8_t *)&wake_up_dur, 1);
4526
4527 if (ret == 0)
4528 {
4529 wake_up_dur.sleep_dur = val;
4530 ret = lsm6dsm_write_reg(ctx, LSM6DSM_WAKE_UP_DUR,
4531 (uint8_t *)&wake_up_dur, 1);
4532 }
4533
4534 return ret;
4535 }
4536
4537 /**
4538 * @brief Duration to go in sleep mode. 1 LSb = 512 / ODR[get]
4539 *
4540 * @param ctx Read / write interface definitions
4541 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
4542 * @retval Interface status (MANDATORY: return 0 -> no Error).
4543 *
4544 */
lsm6dsm_act_sleep_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4545 int32_t lsm6dsm_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4546 {
4547 lsm6dsm_wake_up_dur_t wake_up_dur;
4548 int32_t ret;
4549
4550 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
4551 (uint8_t *)&wake_up_dur, 1);
4552 *val = wake_up_dur.sleep_dur;
4553
4554 return ret;
4555 }
4556
4557 /**
4558 * @}
4559 *
4560 */
4561
4562 /**
4563 * @defgroup LSM6DSM_tap_generator
4564 * @brief This section groups all the functions that manage the
4565 * tap and double tap event generation.
4566 * @{
4567 *
4568 */
4569
4570 /**
4571 * @brief Read the tap / double tap source register.[get]
4572 *
4573 * @param ctx Read / write interface definitions
4574 * @param val Structure of registers from TAP_SRC
4575 * @retval Interface status (MANDATORY: return 0 -> no Error).
4576 *
4577 */
lsm6dsm_tap_src_get(const stmdev_ctx_t * ctx,lsm6dsm_tap_src_t * val)4578 int32_t lsm6dsm_tap_src_get(const stmdev_ctx_t *ctx, lsm6dsm_tap_src_t *val)
4579 {
4580 int32_t ret;
4581
4582 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_SRC, (uint8_t *) val, 1);
4583
4584 return ret;
4585 }
4586
4587 /**
4588 * @brief Enable Z direction in tap recognition.[set]
4589 *
4590 * @param ctx Read / write interface definitions
4591 * @param val Change the values of tap_z_en in reg TAP_CFG
4592 *
4593 */
lsm6dsm_tap_detection_on_z_set(const stmdev_ctx_t * ctx,uint8_t val)4594 int32_t lsm6dsm_tap_detection_on_z_set(const stmdev_ctx_t *ctx, uint8_t val)
4595 {
4596 lsm6dsm_tap_cfg_t tap_cfg;
4597 int32_t ret;
4598
4599 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4600
4601 if (ret == 0)
4602 {
4603 tap_cfg.tap_z_en = val;
4604 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4605 }
4606
4607 return ret;
4608 }
4609
4610 /**
4611 * @brief Enable Z direction in tap recognition.[get]
4612 *
4613 * @param ctx Read / write interface definitions
4614 * @param val Change the values of tap_z_en in reg TAP_CFG
4615 * @retval Interface status (MANDATORY: return 0 -> no Error).
4616 *
4617 */
lsm6dsm_tap_detection_on_z_get(const stmdev_ctx_t * ctx,uint8_t * val)4618 int32_t lsm6dsm_tap_detection_on_z_get(const stmdev_ctx_t *ctx,
4619 uint8_t *val)
4620 {
4621 lsm6dsm_tap_cfg_t tap_cfg;
4622 int32_t ret;
4623
4624 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4625 *val = tap_cfg.tap_z_en;
4626
4627 return ret;
4628 }
4629
4630 /**
4631 * @brief Enable Y direction in tap recognition.[set]
4632 *
4633 * @param ctx Read / write interface definitions
4634 * @param val Change the values of tap_y_en in reg TAP_CFG
4635 * @retval Interface status (MANDATORY: return 0 -> no Error).
4636 *
4637 */
lsm6dsm_tap_detection_on_y_set(const stmdev_ctx_t * ctx,uint8_t val)4638 int32_t lsm6dsm_tap_detection_on_y_set(const stmdev_ctx_t *ctx, uint8_t val)
4639 {
4640 lsm6dsm_tap_cfg_t tap_cfg;
4641 int32_t ret;
4642
4643 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4644
4645 if (ret == 0)
4646 {
4647 tap_cfg.tap_y_en = val;
4648 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4649 }
4650
4651 return ret;
4652 }
4653
4654 /**
4655 * @brief Enable Y direction in tap recognition.[get]
4656 *
4657 * @param ctx Read / write interface definitions
4658 * @param val Change the values of tap_y_en in reg TAP_CFG
4659 * @retval Interface status (MANDATORY: return 0 -> no Error).
4660 *
4661 */
lsm6dsm_tap_detection_on_y_get(const stmdev_ctx_t * ctx,uint8_t * val)4662 int32_t lsm6dsm_tap_detection_on_y_get(const stmdev_ctx_t *ctx,
4663 uint8_t *val)
4664 {
4665 lsm6dsm_tap_cfg_t tap_cfg;
4666 int32_t ret;
4667
4668 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4669 *val = tap_cfg.tap_y_en;
4670
4671 return ret;
4672 }
4673
4674 /**
4675 * @brief Enable X direction in tap recognition.[set]
4676 *
4677 * @param ctx Read / write interface definitions
4678 * @param val Change the values of tap_x_en in reg TAP_CFG
4679 * @retval Interface status (MANDATORY: return 0 -> no Error).
4680 *
4681 */
lsm6dsm_tap_detection_on_x_set(const stmdev_ctx_t * ctx,uint8_t val)4682 int32_t lsm6dsm_tap_detection_on_x_set(const stmdev_ctx_t *ctx, uint8_t val)
4683 {
4684 lsm6dsm_tap_cfg_t tap_cfg;
4685 int32_t ret;
4686
4687 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4688
4689 if (ret == 0)
4690 {
4691 tap_cfg.tap_x_en = val;
4692 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4693 }
4694
4695 return ret;
4696 }
4697
4698 /**
4699 * @brief Enable X direction in tap recognition.[get]
4700 *
4701 * @param ctx Read / write interface definitions
4702 * @param val Change the values of tap_x_en in reg TAP_CFG
4703 * @retval Interface status (MANDATORY: return 0 -> no Error).
4704 *
4705 */
lsm6dsm_tap_detection_on_x_get(const stmdev_ctx_t * ctx,uint8_t * val)4706 int32_t lsm6dsm_tap_detection_on_x_get(const stmdev_ctx_t *ctx,
4707 uint8_t *val)
4708 {
4709 lsm6dsm_tap_cfg_t tap_cfg;
4710 int32_t ret;
4711
4712 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_CFG, (uint8_t *)&tap_cfg, 1);
4713 *val = tap_cfg.tap_x_en;
4714
4715 return ret;
4716 }
4717
4718 /**
4719 * @brief Threshold for tap recognition.[set]
4720 *
4721 * @param ctx Read / write interface definitions
4722 * @param val Change the values of tap_ths in reg TAP_THS_6D
4723 * @retval Interface status (MANDATORY: return 0 -> no Error).
4724 *
4725 */
lsm6dsm_tap_threshold_x_set(const stmdev_ctx_t * ctx,uint8_t val)4726 int32_t lsm6dsm_tap_threshold_x_set(const stmdev_ctx_t *ctx, uint8_t val)
4727 {
4728 lsm6dsm_tap_ths_6d_t tap_ths_6d;
4729 int32_t ret;
4730
4731 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D,
4732 (uint8_t *)&tap_ths_6d, 1);
4733
4734 if (ret == 0)
4735 {
4736 tap_ths_6d.tap_ths = val;
4737 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_THS_6D,
4738 (uint8_t *)&tap_ths_6d, 1);
4739 }
4740
4741 return ret;
4742 }
4743
4744 /**
4745 * @brief Threshold for tap recognition.[get]
4746 *
4747 * @param ctx Read / write interface definitions
4748 * @param val Change the values of tap_ths in reg TAP_THS_6D
4749 * @retval Interface status (MANDATORY: return 0 -> no Error).
4750 *
4751 */
lsm6dsm_tap_threshold_x_get(const stmdev_ctx_t * ctx,uint8_t * val)4752 int32_t lsm6dsm_tap_threshold_x_get(const stmdev_ctx_t *ctx, uint8_t *val)
4753 {
4754 lsm6dsm_tap_ths_6d_t tap_ths_6d;
4755 int32_t ret;
4756
4757 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D,
4758 (uint8_t *)&tap_ths_6d, 1);
4759 *val = tap_ths_6d.tap_ths;
4760
4761 return ret;
4762 }
4763
4764 /**
4765 * @brief Maximum duration is the maximum time of an overthreshold signal
4766 * detection to be recognized as a tap event.
4767 * The default value of these bits is 00b which corresponds to
4768 * 4*ODR_XL time.
4769 * If the SHOCK[1:0] bits are set to a different
4770 * value, 1LSB corresponds to 8*ODR_XL time.[set]
4771 *
4772 * @param ctx Read / write interface definitions
4773 * @param val Change the values of shock in reg INT_DUR2
4774 * @retval Interface status (MANDATORY: return 0 -> no Error).
4775 *
4776 */
lsm6dsm_tap_shock_set(const stmdev_ctx_t * ctx,uint8_t val)4777 int32_t lsm6dsm_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val)
4778 {
4779 lsm6dsm_int_dur2_t int_dur2;
4780 int32_t ret;
4781
4782 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
4783
4784 if (ret == 0)
4785 {
4786 int_dur2.shock = val;
4787 ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
4788 }
4789
4790 return ret;
4791 }
4792
4793 /**
4794 * @brief Maximum duration is the maximum time of an overthreshold signal
4795 * detection to be recognized as a tap event.
4796 * The default value of these bits is 00b which corresponds to
4797 * 4*ODR_XL time.
4798 * If the SHOCK[1:0] bits are set to a different value, 1LSB
4799 * corresponds to 8*ODR_XL time.[get]
4800 *
4801 * @param ctx Read / write interface definitions
4802 * @param val Change the values of shock in reg INT_DUR2
4803 * @retval Interface status (MANDATORY: return 0 -> no Error).
4804 *
4805 */
lsm6dsm_tap_shock_get(const stmdev_ctx_t * ctx,uint8_t * val)4806 int32_t lsm6dsm_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val)
4807 {
4808 lsm6dsm_int_dur2_t int_dur2;
4809 int32_t ret;
4810
4811 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
4812 *val = int_dur2.shock;
4813
4814 return ret;
4815 }
4816
4817 /**
4818 * @brief Quiet time is the time after the first detected tap in which there
4819 * must not be any overthreshold event.
4820 * The default value of these bits is 00b which corresponds to
4821 * 2*ODR_XL time.
4822 * If the QUIET[1:0] bits are set to a different value, 1LSB
4823 * corresponds to 4*ODR_XL time.[set]
4824 *
4825 * @param ctx Read / write interface definitions
4826 * @param val Change the values of quiet in reg INT_DUR2
4827 * @retval Interface status (MANDATORY: return 0 -> no Error).
4828 *
4829 */
lsm6dsm_tap_quiet_set(const stmdev_ctx_t * ctx,uint8_t val)4830 int32_t lsm6dsm_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val)
4831 {
4832 lsm6dsm_int_dur2_t int_dur2;
4833 int32_t ret;
4834
4835 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
4836
4837 if (ret == 0)
4838 {
4839 int_dur2.quiet = val;
4840 ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
4841 }
4842
4843 return ret;
4844 }
4845
4846 /**
4847 * @brief Quiet time is the time after the first detected tap in which there
4848 * must not be any overthreshold event.
4849 * The default value of these bits is 00b which corresponds to
4850 * 2*ODR_XL time.
4851 * If the QUIET[1:0] bits are set to a different value, 1LSB
4852 * corresponds to 4*ODR_XL time.[get]
4853 *
4854 * @param ctx Read / write interface definitions
4855 * @param val Change the values of quiet in reg INT_DUR2
4856 * @retval Interface status (MANDATORY: return 0 -> no Error).
4857 *
4858 */
lsm6dsm_tap_quiet_get(const stmdev_ctx_t * ctx,uint8_t * val)4859 int32_t lsm6dsm_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val)
4860 {
4861 lsm6dsm_int_dur2_t int_dur2;
4862 int32_t ret;
4863
4864 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
4865 *val = int_dur2.quiet;
4866
4867 return ret;
4868 }
4869
4870 /**
4871 * @brief When double tap recognition is enabled, this register expresses the
4872 * maximum time between two consecutive detected taps to determine a
4873 * double tap event.
4874 * The default value of these bits is 0000b which corresponds to
4875 * 16*ODR_XL time.
4876 * If the DUR[3:0] bits are set to a different value,1LSB corresponds
4877 * to 32*ODR_XL time.[set]
4878 *
4879 * @param ctx Read / write interface definitions
4880 * @param val Change the values of dur in reg INT_DUR2
4881 * @retval Interface status (MANDATORY: return 0 -> no Error).
4882 *
4883 */
lsm6dsm_tap_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4884 int32_t lsm6dsm_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4885 {
4886 lsm6dsm_int_dur2_t int_dur2;
4887 int32_t ret;
4888
4889 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
4890
4891 if (ret == 0)
4892 {
4893 int_dur2.dur = val;
4894 ret = lsm6dsm_write_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
4895 }
4896
4897 return ret;
4898 }
4899
4900 /**
4901 * @brief When double tap recognition is enabled, this register expresses the
4902 * maximum time between two consecutive detected taps to determine a
4903 * double tap event.
4904 * The default value of these bits is 0000b which corresponds to
4905 * 16*ODR_XL time.
4906 * If the DUR[3:0] bits are set to a different value,1LSB corresponds
4907 * to 32*ODR_XL time.[get]
4908 *
4909 * @param ctx Read / write interface definitions
4910 * @param val Change the values of dur in reg INT_DUR2
4911 * @retval Interface status (MANDATORY: return 0 -> no Error).
4912 *
4913 */
lsm6dsm_tap_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4914 int32_t lsm6dsm_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4915 {
4916 lsm6dsm_int_dur2_t int_dur2;
4917 int32_t ret;
4918
4919 ret = lsm6dsm_read_reg(ctx, LSM6DSM_INT_DUR2, (uint8_t *)&int_dur2, 1);
4920 *val = int_dur2.dur;
4921
4922 return ret;
4923 }
4924
4925 /**
4926 * @brief Single/double-tap event enable/disable.[set]
4927 *
4928 * @param ctx Read / write interface definitions
4929 * @param val Change the values of
4930 * single_double_tap in reg WAKE_UP_THS
4931 * @retval Interface status (MANDATORY: return 0 -> no Error).
4932 *
4933 */
lsm6dsm_tap_mode_set(const stmdev_ctx_t * ctx,lsm6dsm_single_double_tap_t val)4934 int32_t lsm6dsm_tap_mode_set(const stmdev_ctx_t *ctx,
4935 lsm6dsm_single_double_tap_t val)
4936 {
4937 lsm6dsm_wake_up_ths_t wake_up_ths;
4938 int32_t ret;
4939
4940 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_THS,
4941 (uint8_t *)&wake_up_ths, 1);
4942
4943 if (ret == 0)
4944 {
4945 wake_up_ths.single_double_tap = (uint8_t) val;
4946 ret = lsm6dsm_write_reg(ctx, LSM6DSM_WAKE_UP_THS,
4947 (uint8_t *)&wake_up_ths, 1);
4948 }
4949
4950 return ret;
4951 }
4952
4953 /**
4954 * @brief Single/double-tap event enable/disable.[get]
4955 *
4956 * @param ctx Read / write interface definitions
4957 * @param val Get the values of single_double_tap
4958 * in reg WAKE_UP_THS
4959 * @retval Interface status (MANDATORY: return 0 -> no Error).
4960 *
4961 */
lsm6dsm_tap_mode_get(const stmdev_ctx_t * ctx,lsm6dsm_single_double_tap_t * val)4962 int32_t lsm6dsm_tap_mode_get(const stmdev_ctx_t *ctx,
4963 lsm6dsm_single_double_tap_t *val)
4964 {
4965 lsm6dsm_wake_up_ths_t wake_up_ths;
4966 int32_t ret;
4967
4968 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_THS,
4969 (uint8_t *)&wake_up_ths, 1);
4970
4971 switch (wake_up_ths.single_double_tap)
4972 {
4973 case LSM6DSM_ONLY_SINGLE:
4974 *val = LSM6DSM_ONLY_SINGLE;
4975 break;
4976
4977 case LSM6DSM_BOTH_SINGLE_DOUBLE:
4978 *val = LSM6DSM_BOTH_SINGLE_DOUBLE;
4979 break;
4980
4981 default:
4982 *val = LSM6DSM_ONLY_SINGLE;
4983 break;
4984 }
4985
4986 return ret;
4987 }
4988
4989 /**
4990 * @}
4991 *
4992 */
4993
4994 /**
4995 * @defgroup LSM6DSM_ Six_position_detection(6D/4D)
4996 * @brief This section groups all the functions concerning six
4997 * position detection (6D).
4998 * @{
4999 *
5000 */
5001
5002 /**
5003 * @brief LPF2 feed 6D function selection.[set]
5004 *
5005 * @param ctx Read / write interface definitions
5006 * @param val Change the values of low_pass_on_6d in
5007 * reg CTRL8_XL
5008 * @retval Interface status (MANDATORY: return 0 -> no Error).
5009 *
5010 */
lsm6dsm_6d_feed_data_set(const stmdev_ctx_t * ctx,lsm6dsm_low_pass_on_6d_t val)5011 int32_t lsm6dsm_6d_feed_data_set(const stmdev_ctx_t *ctx,
5012 lsm6dsm_low_pass_on_6d_t val)
5013 {
5014 lsm6dsm_ctrl8_xl_t ctrl8_xl;
5015 int32_t ret;
5016
5017 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
5018
5019 if (ret == 0)
5020 {
5021 ctrl8_xl.low_pass_on_6d = (uint8_t) val;
5022 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
5023 }
5024
5025 return ret;
5026 }
5027
5028 /**
5029 * @brief LPF2 feed 6D function selection.[get]
5030 *
5031 * @param ctx Read / write interface definitions
5032 * @param val Get the values of low_pass_on_6d in reg CTRL8_XL
5033 * @retval Interface status (MANDATORY: return 0 -> no Error).
5034 *
5035 */
lsm6dsm_6d_feed_data_get(const stmdev_ctx_t * ctx,lsm6dsm_low_pass_on_6d_t * val)5036 int32_t lsm6dsm_6d_feed_data_get(const stmdev_ctx_t *ctx,
5037 lsm6dsm_low_pass_on_6d_t *val)
5038 {
5039 lsm6dsm_ctrl8_xl_t ctrl8_xl;
5040 int32_t ret;
5041
5042 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
5043
5044 switch (ctrl8_xl.low_pass_on_6d)
5045 {
5046 case LSM6DSM_ODR_DIV_2_FEED:
5047 *val = LSM6DSM_ODR_DIV_2_FEED;
5048 break;
5049
5050 case LSM6DSM_LPF2_FEED:
5051 *val = LSM6DSM_LPF2_FEED;
5052 break;
5053
5054 default:
5055 *val = LSM6DSM_ODR_DIV_2_FEED;
5056 break;
5057 }
5058
5059 return ret;
5060 }
5061
5062 /**
5063 * @brief Threshold for 4D/6D function.[set]
5064 *
5065 * @param ctx Read / write interface definitions
5066 * @param val Change the values of sixd_ths in reg TAP_THS_6D
5067 * @retval Interface status (MANDATORY: return 0 -> no Error).
5068 *
5069 */
lsm6dsm_6d_threshold_set(const stmdev_ctx_t * ctx,lsm6dsm_sixd_ths_t val)5070 int32_t lsm6dsm_6d_threshold_set(const stmdev_ctx_t *ctx,
5071 lsm6dsm_sixd_ths_t val)
5072 {
5073 lsm6dsm_tap_ths_6d_t tap_ths_6d;
5074 int32_t ret;
5075
5076 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D,
5077 (uint8_t *)&tap_ths_6d, 1);
5078
5079 if (ret == 0)
5080 {
5081 tap_ths_6d.sixd_ths = (uint8_t) val;
5082 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_THS_6D,
5083 (uint8_t *)&tap_ths_6d, 1);
5084 }
5085
5086 return ret;
5087 }
5088
5089 /**
5090 * @brief Threshold for 4D/6D function.[get]
5091 *
5092 * @param ctx Read / write interface definitions
5093 * @param val Get the values of sixd_ths in reg TAP_THS_6D
5094 * @retval Interface status (MANDATORY: return 0 -> no Error).
5095 *
5096 */
lsm6dsm_6d_threshold_get(const stmdev_ctx_t * ctx,lsm6dsm_sixd_ths_t * val)5097 int32_t lsm6dsm_6d_threshold_get(const stmdev_ctx_t *ctx,
5098 lsm6dsm_sixd_ths_t *val)
5099 {
5100 lsm6dsm_tap_ths_6d_t tap_ths_6d;
5101 int32_t ret;
5102
5103 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D,
5104 (uint8_t *)&tap_ths_6d, 1);
5105
5106 switch (tap_ths_6d.sixd_ths)
5107 {
5108 case LSM6DSM_DEG_80:
5109 *val = LSM6DSM_DEG_80;
5110 break;
5111
5112 case LSM6DSM_DEG_70:
5113 *val = LSM6DSM_DEG_70;
5114 break;
5115
5116 case LSM6DSM_DEG_60:
5117 *val = LSM6DSM_DEG_60;
5118 break;
5119
5120 case LSM6DSM_DEG_50:
5121 *val = LSM6DSM_DEG_50;
5122 break;
5123
5124 default:
5125 *val = LSM6DSM_DEG_80;
5126 break;
5127 }
5128
5129 return ret;
5130 }
5131
5132 /**
5133 * @brief 4D orientation detection enable.[set]
5134 *
5135 * @param ctx Read / write interface definitions
5136 * @param val Change the values of d4d_en in reg TAP_THS_6D
5137 * @retval Interface status (MANDATORY: return 0 -> no Error).
5138 *
5139 */
lsm6dsm_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)5140 int32_t lsm6dsm_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
5141 {
5142 lsm6dsm_tap_ths_6d_t tap_ths_6d;
5143 int32_t ret;
5144
5145 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D,
5146 (uint8_t *)&tap_ths_6d, 1);
5147
5148 if (ret == 0)
5149 {
5150 tap_ths_6d.d4d_en = val;
5151 ret = lsm6dsm_write_reg(ctx, LSM6DSM_TAP_THS_6D,
5152 (uint8_t *)&tap_ths_6d, 1);
5153 }
5154
5155 return ret;
5156 }
5157
5158 /**
5159 * @brief 4D orientation detection enable.[get]
5160 *
5161 * @param ctx Read / write interface definitions
5162 * @param val Change the values of d4d_en in reg TAP_THS_6D
5163 * @retval Interface status (MANDATORY: return 0 -> no Error).
5164 *
5165 */
lsm6dsm_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)5166 int32_t lsm6dsm_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
5167 {
5168 lsm6dsm_tap_ths_6d_t tap_ths_6d;
5169 int32_t ret;
5170
5171 ret = lsm6dsm_read_reg(ctx, LSM6DSM_TAP_THS_6D,
5172 (uint8_t *)&tap_ths_6d, 1);
5173 *val = tap_ths_6d.d4d_en;
5174
5175 return ret;
5176 }
5177
5178 /**
5179 * @}
5180 *
5181 */
5182
5183 /**
5184 * @defgroup LSM6DSM_free_fall
5185 * @brief This section group all the functions concerning the free
5186 * fall detection.
5187 * @{
5188 *
5189 */
5190
5191 /**
5192 * @brief Free-fall duration event. 1LSb = 1 / ODR[set]
5193 *
5194 * @param ctx Read / write interface definitions
5195 * @param val Change the values of ff_dur in reg WAKE_UP_DUR
5196 * @retval Interface status (MANDATORY: return 0 -> no Error).
5197 *
5198 */
lsm6dsm_ff_dur_set(const stmdev_ctx_t * ctx,uint8_t val)5199 int32_t lsm6dsm_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
5200 {
5201 lsm6dsm_wake_up_dur_t wake_up_dur;
5202 lsm6dsm_free_fall_t free_fall;
5203 int32_t ret;
5204
5205 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1);
5206
5207 if (ret == 0)
5208 {
5209 free_fall.ff_dur = (val & 0x1FU);
5210 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1);
5211
5212 if (ret == 0)
5213 {
5214 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
5215 (uint8_t *)&wake_up_dur, 1);
5216
5217 if (ret == 0)
5218 {
5219 wake_up_dur.ff_dur = (val & 0x20U) >> 5;
5220 ret = lsm6dsm_write_reg(ctx, LSM6DSM_WAKE_UP_DUR,
5221 (uint8_t *)&wake_up_dur, 1);
5222 }
5223 }
5224 }
5225
5226 return ret;
5227 }
5228
5229 /**
5230 * @brief Free-fall duration event. 1LSb = 1 / ODR[get]
5231 *
5232 * @param ctx Read / write interface definitions
5233 * @param val Change the values of ff_dur in reg WAKE_UP_DUR
5234 * @retval Interface status (MANDATORY: return 0 -> no Error).
5235 *
5236 */
lsm6dsm_ff_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)5237 int32_t lsm6dsm_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
5238 {
5239 lsm6dsm_wake_up_dur_t wake_up_dur;
5240 lsm6dsm_free_fall_t free_fall;
5241 int32_t ret;
5242
5243 ret = lsm6dsm_read_reg(ctx, LSM6DSM_WAKE_UP_DUR,
5244 (uint8_t *)&wake_up_dur, 1);
5245
5246 if (ret == 0)
5247 {
5248 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1);
5249 }
5250
5251 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
5252
5253 return ret;
5254 }
5255
5256 /**
5257 * @brief Free fall threshold setting.[set]
5258 *
5259 * @param ctx Read / write interface definitions
5260 * @param val Change the values of ff_ths in reg FREE_FALL
5261 * @retval Interface status (MANDATORY: return 0 -> no Error).
5262 *
5263 */
lsm6dsm_ff_threshold_set(const stmdev_ctx_t * ctx,lsm6dsm_ff_ths_t val)5264 int32_t lsm6dsm_ff_threshold_set(const stmdev_ctx_t *ctx,
5265 lsm6dsm_ff_ths_t val)
5266 {
5267 lsm6dsm_free_fall_t free_fall;
5268 int32_t ret;
5269
5270 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1);
5271
5272 if (ret == 0)
5273 {
5274 free_fall.ff_ths = (uint8_t) val;
5275 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1);
5276 }
5277
5278 return ret;
5279 }
5280
5281 /**
5282 * @brief Free fall threshold setting.[get]
5283 *
5284 * @param ctx Read / write interface definitions
5285 * @param val Get the values of ff_ths in reg FREE_FALL
5286 * @retval Interface status (MANDATORY: return 0 -> no Error).
5287 *
5288 */
lsm6dsm_ff_threshold_get(const stmdev_ctx_t * ctx,lsm6dsm_ff_ths_t * val)5289 int32_t lsm6dsm_ff_threshold_get(const stmdev_ctx_t *ctx,
5290 lsm6dsm_ff_ths_t *val)
5291 {
5292 lsm6dsm_free_fall_t free_fall;
5293 int32_t ret;
5294
5295 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FREE_FALL, (uint8_t *)&free_fall, 1);
5296
5297 switch (free_fall.ff_ths)
5298 {
5299 case LSM6DSM_FF_TSH_156mg:
5300 *val = LSM6DSM_FF_TSH_156mg;
5301 break;
5302
5303 case LSM6DSM_FF_TSH_219mg:
5304 *val = LSM6DSM_FF_TSH_219mg;
5305 break;
5306
5307 case LSM6DSM_FF_TSH_250mg:
5308 *val = LSM6DSM_FF_TSH_250mg;
5309 break;
5310
5311 case LSM6DSM_FF_TSH_312mg:
5312 *val = LSM6DSM_FF_TSH_312mg;
5313 break;
5314
5315 case LSM6DSM_FF_TSH_344mg:
5316 *val = LSM6DSM_FF_TSH_344mg;
5317 break;
5318
5319 case LSM6DSM_FF_TSH_406mg:
5320 *val = LSM6DSM_FF_TSH_406mg;
5321 break;
5322
5323 case LSM6DSM_FF_TSH_469mg:
5324 *val = LSM6DSM_FF_TSH_469mg;
5325 break;
5326
5327 case LSM6DSM_FF_TSH_500mg:
5328 *val = LSM6DSM_FF_TSH_500mg;
5329 break;
5330
5331 default:
5332 *val = LSM6DSM_FF_TSH_156mg;
5333 break;
5334 }
5335
5336 return ret;
5337 }
5338
5339 /**
5340 * @}
5341 *
5342 */
5343
5344 /**
5345 * @defgroup LSM6DSM_fifo
5346 * @brief This section group all the functions concerning the
5347 * fifo usage
5348 * @{
5349 *
5350 */
5351
5352 /**
5353 * @brief FIFO watermark level selection.[set]
5354 *
5355 * @param ctx Read / write interface definitions
5356 * @param val Change the values of fth in reg FIFO_CTRL1
5357 * @retval Interface status (MANDATORY: return 0 -> no Error).
5358 *
5359 */
lsm6dsm_fifo_watermark_set(const stmdev_ctx_t * ctx,uint16_t val)5360 int32_t lsm6dsm_fifo_watermark_set(const stmdev_ctx_t *ctx, uint16_t val)
5361 {
5362 lsm6dsm_fifo_ctrl1_t fifo_ctrl1;
5363 lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
5364 int32_t ret;
5365
5366 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
5367 (uint8_t *)&fifo_ctrl2, 1);
5368
5369 if (ret == 0)
5370 {
5371 fifo_ctrl1.fth = (uint8_t)(0x00FFU & val);
5372 fifo_ctrl2.fth = (uint8_t)((0x0700U & val) >> 8);
5373 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL1,
5374 (uint8_t *)&fifo_ctrl1, 1);
5375
5376 if (ret == 0)
5377 {
5378 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL2,
5379 (uint8_t *)&fifo_ctrl2, 1);
5380 }
5381 }
5382
5383 return ret;
5384 }
5385
5386 /**
5387 * @brief FIFO watermark level selection.[get]
5388 *
5389 * @param ctx Read / write interface definitions
5390 * @param val Change the values of fth in reg FIFO_CTRL1
5391 * @retval Interface status (MANDATORY: return 0 -> no Error).
5392 *
5393 */
lsm6dsm_fifo_watermark_get(const stmdev_ctx_t * ctx,uint16_t * val)5394 int32_t lsm6dsm_fifo_watermark_get(const stmdev_ctx_t *ctx, uint16_t *val)
5395 {
5396 lsm6dsm_fifo_ctrl1_t fifo_ctrl1;
5397 lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
5398 int32_t ret;
5399
5400 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL1,
5401 (uint8_t *)&fifo_ctrl1, 1);
5402
5403 if (ret == 0)
5404 {
5405 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
5406 (uint8_t *)&fifo_ctrl2, 1);
5407 }
5408
5409 *val = ((uint16_t)fifo_ctrl2.fth << 8) + (uint16_t)fifo_ctrl1.fth;
5410
5411 return ret;
5412 }
5413
5414 /**
5415 * @brief FIFO data level.[get]
5416 *
5417 * @param ctx Read / write interface definitions
5418 * @param val get the values of diff_fifo in reg FIFO_STATUS1 and
5419 * FIFO_STATUS2(diff_fifo), it is recommended to set the
5420 * BDU bit.
5421 * @retval Interface status (MANDATORY: return 0 -> no Error).
5422 *
5423 */
lsm6dsm_fifo_data_level_get(const stmdev_ctx_t * ctx,uint16_t * val)5424 int32_t lsm6dsm_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val)
5425 {
5426 lsm6dsm_fifo_status1_t fifo_status1;
5427 lsm6dsm_fifo_status2_t fifo_status2;
5428 int32_t ret;
5429
5430 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS1,
5431 (uint8_t *)&fifo_status1, 1);
5432
5433 if (ret == 0)
5434 {
5435 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS2,
5436 (uint8_t *)&fifo_status2, 1);
5437 *val = ((uint16_t) fifo_status2.diff_fifo << 8) +
5438 (uint16_t) fifo_status1.diff_fifo;
5439 }
5440
5441 return ret;
5442 }
5443
5444 /**
5445 * @brief FIFO watermark.[get]
5446 *
5447 * @param ctx Read / write interface definitions
5448 * @param val get the values of watermark in reg FIFO_STATUS2 and
5449 * @retval Interface status (MANDATORY: return 0 -> no Error).
5450 *
5451 */
lsm6dsm_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)5452 int32_t lsm6dsm_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
5453 {
5454 lsm6dsm_fifo_status2_t fifo_status2;
5455 int32_t ret;
5456
5457 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS2,
5458 (uint8_t *)&fifo_status2, 1);
5459 *val = fifo_status2.waterm;
5460
5461 return ret;
5462 }
5463
5464 /**
5465 * @brief FIFO over run.[get]
5466 *
5467 * @param ctx Read / write interface definitions
5468 * @param val get the value of over run in reg FIFO_STATUS2
5469 * @retval Interface status (MANDATORY: return 0 -> no Error).
5470 *
5471 */
lsm6dsm_fifo_over_run_get(const stmdev_ctx_t * ctx,uint8_t * val)5472 int32_t lsm6dsm_fifo_over_run_get(const stmdev_ctx_t *ctx, uint8_t *val)
5473 {
5474 lsm6dsm_fifo_status2_t fifo_status2;
5475 int32_t ret;
5476
5477 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS2,
5478 (uint8_t *)&fifo_status2, 1);
5479 *val = fifo_status2.over_run;
5480
5481 return ret;
5482 }
5483
5484 /**
5485 * @brief FIFO pattern.[get]
5486 *
5487 * @param ctx Read / write interface definitions
5488 * @param val get the values of fifo_pattern in reg FIFO_STATUS3 and
5489 * FIFO_STATUS4, it is recommended to set the BDU bit
5490 * @retval Interface status (MANDATORY: return 0 -> no Error).
5491 *
5492 */
lsm6dsm_fifo_pattern_get(const stmdev_ctx_t * ctx,uint16_t * val)5493 int32_t lsm6dsm_fifo_pattern_get(const stmdev_ctx_t *ctx, uint16_t *val)
5494 {
5495 lsm6dsm_fifo_status3_t fifo_status3;
5496 lsm6dsm_fifo_status4_t fifo_status4;
5497 int32_t ret;
5498
5499 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS3,
5500 (uint8_t *)&fifo_status3, 1);
5501
5502 if (ret == 0)
5503 {
5504 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_STATUS4,
5505 (uint8_t *)&fifo_status4, 1);
5506 *val = ((uint16_t)fifo_status4.fifo_pattern << 8) +
5507 fifo_status3.fifo_pattern;
5508 }
5509
5510 return ret;
5511 }
5512
5513 /**
5514 * @brief Batching of temperature data[set]
5515 *
5516 * @param ctx Read / write interface definitions
5517 * @param val Change the values of fifo_temp_en in reg FIFO_CTRL2
5518 * @retval Interface status (MANDATORY: return 0 -> no Error).
5519 *
5520 */
lsm6dsm_fifo_temp_batch_set(const stmdev_ctx_t * ctx,uint8_t val)5521 int32_t lsm6dsm_fifo_temp_batch_set(const stmdev_ctx_t *ctx, uint8_t val)
5522 {
5523 lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
5524 int32_t ret;
5525
5526 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
5527 (uint8_t *)&fifo_ctrl2, 1);
5528
5529 if (ret == 0)
5530 {
5531 fifo_ctrl2.fifo_temp_en = val;
5532 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL2,
5533 (uint8_t *)&fifo_ctrl2, 1);
5534 }
5535
5536 return ret;
5537 }
5538
5539 /**
5540 * @brief Batching of temperature data[get]
5541 *
5542 * @param ctx Read / write interface definitions
5543 * @param val Change the values of fifo_temp_en in reg FIFO_CTRL2
5544 * @retval Interface status (MANDATORY: return 0 -> no Error).
5545 *
5546 */
lsm6dsm_fifo_temp_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)5547 int32_t lsm6dsm_fifo_temp_batch_get(const stmdev_ctx_t *ctx, uint8_t *val)
5548 {
5549 lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
5550 int32_t ret;
5551
5552 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
5553 (uint8_t *)&fifo_ctrl2, 1);
5554 *val = fifo_ctrl2.fifo_temp_en;
5555
5556 return ret;
5557 }
5558
5559 /**
5560 * @brief Trigger signal for FIFO write operation.[set]
5561 *
5562 * @param ctx Read / write interface definitions
5563 * @param val act on FIFO_CTRL2(timer_pedo_fifo_drdy)
5564 * and MASTER_CONFIG(data_valid_sel_fifo)
5565 * @retval Interface status (MANDATORY: return 0 -> no Error).
5566 *
5567 */
lsm6dsm_fifo_write_trigger_set(const stmdev_ctx_t * ctx,lsm6dsm_trigger_fifo_t val)5568 int32_t lsm6dsm_fifo_write_trigger_set(const stmdev_ctx_t *ctx,
5569 lsm6dsm_trigger_fifo_t val)
5570 {
5571 lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
5572 lsm6dsm_master_config_t master_config;
5573 int32_t ret;
5574
5575 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
5576 (uint8_t *)&fifo_ctrl2, 1);
5577
5578 if (ret == 0)
5579 {
5580 fifo_ctrl2.timer_pedo_fifo_drdy = (uint8_t)val & 0x01U;
5581 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL2,
5582 (uint8_t *)&fifo_ctrl2, 1);
5583
5584 if (ret == 0)
5585 {
5586 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
5587 (uint8_t *)&master_config, 1);
5588
5589 if (ret == 0)
5590 {
5591 master_config.data_valid_sel_fifo = (((uint8_t)val & 0x02U) >> 1);
5592 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
5593 (uint8_t *)&master_config, 1);
5594 }
5595 }
5596 }
5597
5598 return ret;
5599 }
5600
5601 /**
5602 * @brief Trigger signal for FIFO write operation.[get]
5603 *
5604 * @param ctx Read / write interface definitions
5605 * @param val act on FIFO_CTRL2(timer_pedo_fifo_drdy)
5606 * and MASTER_CONFIG(data_valid_sel_fifo)
5607 * @retval Interface status (MANDATORY: return 0 -> no Error).
5608 *
5609 */
lsm6dsm_fifo_write_trigger_get(const stmdev_ctx_t * ctx,lsm6dsm_trigger_fifo_t * val)5610 int32_t lsm6dsm_fifo_write_trigger_get(const stmdev_ctx_t *ctx,
5611 lsm6dsm_trigger_fifo_t *val)
5612 {
5613 lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
5614 lsm6dsm_master_config_t master_config;
5615 int32_t ret;
5616
5617 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
5618 (uint8_t *)&fifo_ctrl2, 1);
5619
5620 if (ret == 0)
5621 {
5622 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
5623 (uint8_t *)&master_config, 1);
5624
5625 switch ((master_config.data_valid_sel_fifo << 1) +
5626 fifo_ctrl2.timer_pedo_fifo_drdy)
5627 {
5628 case LSM6DSM_TRG_XL_GY_DRDY:
5629 *val = LSM6DSM_TRG_XL_GY_DRDY;
5630 break;
5631
5632 case LSM6DSM_TRG_STEP_DETECT:
5633 *val = LSM6DSM_TRG_STEP_DETECT;
5634 break;
5635
5636 case LSM6DSM_TRG_SH_DRDY:
5637 *val = LSM6DSM_TRG_SH_DRDY;
5638 break;
5639
5640 default:
5641 *val = LSM6DSM_TRG_XL_GY_DRDY;
5642 break;
5643 }
5644 }
5645
5646 return ret;
5647 }
5648
5649 /**
5650 * @brief Enable pedometer step counter and timestamp as 4th
5651 * FIFO data set.[set]
5652 *
5653 * @param ctx Read / write interface definitions
5654 * @param val Change the values of timer_pedo_fifo_en in reg FIFO_CTRL2
5655 * @retval Interface status (MANDATORY: return 0 -> no Error).
5656 *
5657 */
lsm6dsm_fifo_pedo_and_timestamp_batch_set(const stmdev_ctx_t * ctx,uint8_t val)5658 int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_set(const stmdev_ctx_t *ctx,
5659 uint8_t val)
5660 {
5661 lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
5662 int32_t ret;
5663
5664 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
5665 (uint8_t *)&fifo_ctrl2, 1);
5666
5667 if (ret == 0)
5668 {
5669 fifo_ctrl2.timer_pedo_fifo_en = val;
5670 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL2,
5671 (uint8_t *)&fifo_ctrl2, 1);
5672 }
5673
5674 return ret;
5675 }
5676
5677 /**
5678 * @brief Enable pedometer step counter and timestamp as 4th
5679 * FIFO data set.[get]
5680 *
5681 * @param ctx Read / write interface definitions
5682 * @param val Change the values of timer_pedo_fifo_en in reg FIFO_CTRL2
5683 * @retval Interface status (MANDATORY: return 0 -> no Error).
5684 *
5685 */
lsm6dsm_fifo_pedo_and_timestamp_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)5686 int32_t lsm6dsm_fifo_pedo_and_timestamp_batch_get(const stmdev_ctx_t *ctx,
5687 uint8_t *val)
5688 {
5689 lsm6dsm_fifo_ctrl2_t fifo_ctrl2;
5690 int32_t ret;
5691
5692 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL2,
5693 (uint8_t *)&fifo_ctrl2, 1);
5694 *val = fifo_ctrl2.timer_pedo_fifo_en;
5695
5696 return ret;
5697 }
5698
5699 /**
5700 * @brief Selects Batching Data Rate (writing frequency in FIFO) for
5701 * accelerometer data.[set]
5702 *
5703 * @param ctx Read / write interface definitions
5704 * @param val Change the values of dec_fifo_xl in reg FIFO_CTRL3
5705 * @retval Interface status (MANDATORY: return 0 -> no Error).
5706 *
5707 */
lsm6dsm_fifo_xl_batch_set(const stmdev_ctx_t * ctx,lsm6dsm_dec_fifo_xl_t val)5708 int32_t lsm6dsm_fifo_xl_batch_set(const stmdev_ctx_t *ctx,
5709 lsm6dsm_dec_fifo_xl_t val)
5710 {
5711 lsm6dsm_fifo_ctrl3_t fifo_ctrl3;
5712 int32_t ret;
5713
5714 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL3,
5715 (uint8_t *)&fifo_ctrl3, 1);
5716
5717 if (ret == 0)
5718 {
5719 fifo_ctrl3.dec_fifo_xl = (uint8_t)val;
5720 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL3,
5721 (uint8_t *)&fifo_ctrl3, 1);
5722 }
5723
5724 return ret;
5725 }
5726
5727 /**
5728 * @brief Selects Batching Data Rate (writing frequency in FIFO) for
5729 * accelerometer data.[get]
5730 *
5731 * @param ctx Read / write interface definitions
5732 * @param val Get the values of dec_fifo_xl in reg FIFO_CTRL3
5733 * @retval Interface status (MANDATORY: return 0 -> no Error).
5734 *
5735 */
lsm6dsm_fifo_xl_batch_get(const stmdev_ctx_t * ctx,lsm6dsm_dec_fifo_xl_t * val)5736 int32_t lsm6dsm_fifo_xl_batch_get(const stmdev_ctx_t *ctx,
5737 lsm6dsm_dec_fifo_xl_t *val)
5738 {
5739 lsm6dsm_fifo_ctrl3_t fifo_ctrl3;
5740 int32_t ret;
5741
5742 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL3,
5743 (uint8_t *)&fifo_ctrl3, 1);
5744
5745 switch (fifo_ctrl3.dec_fifo_xl)
5746 {
5747 case LSM6DSM_FIFO_XL_DISABLE:
5748 *val = LSM6DSM_FIFO_XL_DISABLE;
5749 break;
5750
5751 case LSM6DSM_FIFO_XL_NO_DEC:
5752 *val = LSM6DSM_FIFO_XL_NO_DEC;
5753 break;
5754
5755 case LSM6DSM_FIFO_XL_DEC_2:
5756 *val = LSM6DSM_FIFO_XL_DEC_2;
5757 break;
5758
5759 case LSM6DSM_FIFO_XL_DEC_3:
5760 *val = LSM6DSM_FIFO_XL_DEC_3;
5761 break;
5762
5763 case LSM6DSM_FIFO_XL_DEC_4:
5764 *val = LSM6DSM_FIFO_XL_DEC_4;
5765 break;
5766
5767 case LSM6DSM_FIFO_XL_DEC_8:
5768 *val = LSM6DSM_FIFO_XL_DEC_8;
5769 break;
5770
5771 case LSM6DSM_FIFO_XL_DEC_16:
5772 *val = LSM6DSM_FIFO_XL_DEC_16;
5773 break;
5774
5775 case LSM6DSM_FIFO_XL_DEC_32:
5776 *val = LSM6DSM_FIFO_XL_DEC_32;
5777 break;
5778
5779 default:
5780 *val = LSM6DSM_FIFO_XL_DISABLE;
5781 break;
5782 }
5783
5784 return ret;
5785 }
5786
5787 /**
5788 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5789 * for gyroscope data.[set]
5790 *
5791 * @param ctx Read / write interface definitions
5792 * @param val Change the values of dec_fifo_gyro in reg FIFO_CTRL3
5793 * @retval Interface status (MANDATORY: return 0 -> no Error).
5794 *
5795 */
lsm6dsm_fifo_gy_batch_set(const stmdev_ctx_t * ctx,lsm6dsm_dec_fifo_gyro_t val)5796 int32_t lsm6dsm_fifo_gy_batch_set(const stmdev_ctx_t *ctx,
5797 lsm6dsm_dec_fifo_gyro_t val)
5798 {
5799 lsm6dsm_fifo_ctrl3_t fifo_ctrl3;
5800 int32_t ret;
5801
5802 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL3,
5803 (uint8_t *)&fifo_ctrl3, 1);
5804
5805 if (ret == 0)
5806 {
5807 fifo_ctrl3.dec_fifo_gyro = (uint8_t)val;
5808 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL3,
5809 (uint8_t *)&fifo_ctrl3, 1);
5810 }
5811
5812 return ret;
5813 }
5814
5815 /**
5816 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5817 * for gyroscope data.[get]
5818 *
5819 * @param ctx Read / write interface definitions
5820 * @param val Get the values of dec_fifo_gyro in reg FIFO_CTRL3
5821 * @retval Interface status (MANDATORY: return 0 -> no Error).
5822 *
5823 */
lsm6dsm_fifo_gy_batch_get(const stmdev_ctx_t * ctx,lsm6dsm_dec_fifo_gyro_t * val)5824 int32_t lsm6dsm_fifo_gy_batch_get(const stmdev_ctx_t *ctx,
5825 lsm6dsm_dec_fifo_gyro_t *val)
5826 {
5827 lsm6dsm_fifo_ctrl3_t fifo_ctrl3;
5828 int32_t ret;
5829
5830 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL3,
5831 (uint8_t *)&fifo_ctrl3, 1);
5832
5833 switch (fifo_ctrl3.dec_fifo_gyro)
5834 {
5835 case LSM6DSM_FIFO_GY_DISABLE:
5836 *val = LSM6DSM_FIFO_GY_DISABLE;
5837 break;
5838
5839 case LSM6DSM_FIFO_GY_NO_DEC:
5840 *val = LSM6DSM_FIFO_GY_NO_DEC;
5841 break;
5842
5843 case LSM6DSM_FIFO_GY_DEC_2:
5844 *val = LSM6DSM_FIFO_GY_DEC_2;
5845 break;
5846
5847 case LSM6DSM_FIFO_GY_DEC_3:
5848 *val = LSM6DSM_FIFO_GY_DEC_3;
5849 break;
5850
5851 case LSM6DSM_FIFO_GY_DEC_4:
5852 *val = LSM6DSM_FIFO_GY_DEC_4;
5853 break;
5854
5855 case LSM6DSM_FIFO_GY_DEC_8:
5856 *val = LSM6DSM_FIFO_GY_DEC_8;
5857 break;
5858
5859 case LSM6DSM_FIFO_GY_DEC_16:
5860 *val = LSM6DSM_FIFO_GY_DEC_16;
5861 break;
5862
5863 case LSM6DSM_FIFO_GY_DEC_32:
5864 *val = LSM6DSM_FIFO_GY_DEC_32;
5865 break;
5866
5867 default:
5868 *val = LSM6DSM_FIFO_GY_DISABLE;
5869 break;
5870 }
5871
5872 return ret;
5873 }
5874
5875 /**
5876 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5877 * for third data set.[set]
5878 *
5879 * @param ctx Read / write interface definitions
5880 * @param val Change the values of dec_ds3_fifo in reg FIFO_CTRL4
5881 * @retval Interface status (MANDATORY: return 0 -> no Error).
5882 *
5883 */
lsm6dsm_fifo_dataset_3_batch_set(const stmdev_ctx_t * ctx,lsm6dsm_dec_ds3_fifo_t val)5884 int32_t lsm6dsm_fifo_dataset_3_batch_set(const stmdev_ctx_t *ctx,
5885 lsm6dsm_dec_ds3_fifo_t val)
5886 {
5887 lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
5888 int32_t ret;
5889
5890 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
5891 (uint8_t *)&fifo_ctrl4, 1);
5892
5893 if (ret == 0)
5894 {
5895 fifo_ctrl4.dec_ds3_fifo = (uint8_t)val;
5896 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL4,
5897 (uint8_t *)&fifo_ctrl4, 1);
5898 }
5899
5900 return ret;
5901 }
5902
5903 /**
5904 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5905 * for third data set.[get]
5906 *
5907 * @param ctx Read / write interface definitions
5908 * @param val Get the values of dec_ds3_fifo in reg FIFO_CTRL4
5909 * @retval Interface status (MANDATORY: return 0 -> no Error).
5910 *
5911 */
lsm6dsm_fifo_dataset_3_batch_get(const stmdev_ctx_t * ctx,lsm6dsm_dec_ds3_fifo_t * val)5912 int32_t lsm6dsm_fifo_dataset_3_batch_get(const stmdev_ctx_t *ctx,
5913 lsm6dsm_dec_ds3_fifo_t *val)
5914 {
5915 lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
5916 int32_t ret;
5917
5918 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
5919 (uint8_t *)&fifo_ctrl4, 1);
5920
5921 switch (fifo_ctrl4.dec_ds3_fifo)
5922 {
5923 case LSM6DSM_FIFO_DS3_DISABLE:
5924 *val = LSM6DSM_FIFO_DS3_DISABLE;
5925 break;
5926
5927 case LSM6DSM_FIFO_DS3_NO_DEC:
5928 *val = LSM6DSM_FIFO_DS3_NO_DEC;
5929 break;
5930
5931 case LSM6DSM_FIFO_DS3_DEC_2:
5932 *val = LSM6DSM_FIFO_DS3_DEC_2;
5933 break;
5934
5935 case LSM6DSM_FIFO_DS3_DEC_3:
5936 *val = LSM6DSM_FIFO_DS3_DEC_3;
5937 break;
5938
5939 case LSM6DSM_FIFO_DS3_DEC_4:
5940 *val = LSM6DSM_FIFO_DS3_DEC_4;
5941 break;
5942
5943 case LSM6DSM_FIFO_DS3_DEC_8:
5944 *val = LSM6DSM_FIFO_DS3_DEC_8;
5945 break;
5946
5947 case LSM6DSM_FIFO_DS3_DEC_16:
5948 *val = LSM6DSM_FIFO_DS3_DEC_16;
5949 break;
5950
5951 case LSM6DSM_FIFO_DS3_DEC_32:
5952 *val = LSM6DSM_FIFO_DS3_DEC_32;
5953 break;
5954
5955 default:
5956 *val = LSM6DSM_FIFO_DS3_DISABLE;
5957 break;
5958 }
5959
5960 return ret;
5961 }
5962
5963 /**
5964 * @brief Selects Batching Data Rate (writing frequency in FIFO)
5965 * for fourth data set.[set]
5966 *
5967 * @param ctx Read / write interface definitions
5968 * @param val Change the values of dec_ds4_fifo in reg FIFO_CTRL4
5969 * @retval Interface status (MANDATORY: return 0 -> no Error).
5970 *
5971 */
lsm6dsm_fifo_dataset_4_batch_set(const stmdev_ctx_t * ctx,lsm6dsm_dec_ds4_fifo_t val)5972 int32_t lsm6dsm_fifo_dataset_4_batch_set(const stmdev_ctx_t *ctx,
5973 lsm6dsm_dec_ds4_fifo_t val)
5974 {
5975 lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
5976 int32_t ret;
5977
5978 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
5979 (uint8_t *)&fifo_ctrl4, 1);
5980
5981 if (ret == 0)
5982 {
5983 fifo_ctrl4.dec_ds4_fifo = (uint8_t)val;
5984 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL4,
5985 (uint8_t *)&fifo_ctrl4, 1);
5986 }
5987
5988 return ret;
5989 }
5990
5991 /**
5992 * @brief Selects Batching Data Rate (writing frequency in FIFO) for
5993 * fourth data set.[get]
5994 *
5995 * @param ctx Read / write interface definitions
5996 * @param val Get the values of dec_ds4_fifo in reg FIFO_CTRL4
5997 * @retval Interface status (MANDATORY: return 0 -> no Error).
5998 *
5999 */
lsm6dsm_fifo_dataset_4_batch_get(const stmdev_ctx_t * ctx,lsm6dsm_dec_ds4_fifo_t * val)6000 int32_t lsm6dsm_fifo_dataset_4_batch_get(const stmdev_ctx_t *ctx,
6001 lsm6dsm_dec_ds4_fifo_t *val)
6002 {
6003 lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
6004 int32_t ret;
6005
6006 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
6007 (uint8_t *)&fifo_ctrl4, 1);
6008
6009 switch (fifo_ctrl4.dec_ds4_fifo)
6010 {
6011 case LSM6DSM_FIFO_DS4_DISABLE:
6012 *val = LSM6DSM_FIFO_DS4_DISABLE;
6013 break;
6014
6015 case LSM6DSM_FIFO_DS4_NO_DEC:
6016 *val = LSM6DSM_FIFO_DS4_NO_DEC;
6017 break;
6018
6019 case LSM6DSM_FIFO_DS4_DEC_2:
6020 *val = LSM6DSM_FIFO_DS4_DEC_2;
6021 break;
6022
6023 case LSM6DSM_FIFO_DS4_DEC_3:
6024 *val = LSM6DSM_FIFO_DS4_DEC_3;
6025 break;
6026
6027 case LSM6DSM_FIFO_DS4_DEC_4:
6028 *val = LSM6DSM_FIFO_DS4_DEC_4;
6029 break;
6030
6031 case LSM6DSM_FIFO_DS4_DEC_8:
6032 *val = LSM6DSM_FIFO_DS4_DEC_8;
6033 break;
6034
6035 case LSM6DSM_FIFO_DS4_DEC_16:
6036 *val = LSM6DSM_FIFO_DS4_DEC_16;
6037 break;
6038
6039 case LSM6DSM_FIFO_DS4_DEC_32:
6040 *val = LSM6DSM_FIFO_DS4_DEC_32;
6041 break;
6042
6043 default:
6044 *val = LSM6DSM_FIFO_DS4_DISABLE;
6045 break;
6046 }
6047
6048 return ret;
6049 }
6050
6051 /**
6052 * @brief 8-bit data storage in FIFO.[set]
6053 *
6054 * @param ctx Read / write interface definitions
6055 * @param val Change the values of only_high_data in reg FIFO_CTRL4
6056 * @retval Interface status (MANDATORY: return 0 -> no Error).
6057 *
6058 */
lsm6dsm_fifo_xl_gy_8bit_format_set(const stmdev_ctx_t * ctx,uint8_t val)6059 int32_t lsm6dsm_fifo_xl_gy_8bit_format_set(const stmdev_ctx_t *ctx,
6060 uint8_t val)
6061 {
6062 lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
6063 int32_t ret;
6064
6065 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
6066 (uint8_t *)&fifo_ctrl4, 1);
6067
6068 if (ret == 0)
6069 {
6070 fifo_ctrl4.only_high_data = val;
6071 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL4,
6072 (uint8_t *)&fifo_ctrl4, 1);
6073 }
6074
6075 return ret;
6076 }
6077
6078 /**
6079 * @brief 8-bit data storage in FIFO.[get]
6080 *
6081 * @param ctx Read / write interface definitions
6082 * @param val Change the values of only_high_data in reg FIFO_CTRL4
6083 * @retval Interface status (MANDATORY: return 0 -> no Error).
6084 *
6085 */
lsm6dsm_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t * ctx,uint8_t * val)6086 int32_t lsm6dsm_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t *ctx,
6087 uint8_t *val)
6088 {
6089 lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
6090 int32_t ret;
6091
6092 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
6093 (uint8_t *)&fifo_ctrl4, 1);
6094 *val = fifo_ctrl4.only_high_data;
6095
6096 return ret;
6097 }
6098
6099 /**
6100 * @brief Sensing chain FIFO stop values memorization at threshold
6101 * level.[set]
6102 *
6103 * @param ctx Read / write interface definitions
6104 * @param val Change the values of stop_on_fth in reg FIFO_CTRL4
6105 * @retval Interface status (MANDATORY: return 0 -> no Error).
6106 *
6107 */
lsm6dsm_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)6108 int32_t lsm6dsm_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx, uint8_t val)
6109 {
6110 lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
6111 int32_t ret;
6112
6113 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
6114 (uint8_t *)&fifo_ctrl4, 1);
6115
6116 if (ret == 0)
6117 {
6118 fifo_ctrl4.stop_on_fth = val;
6119 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL4,
6120 (uint8_t *)&fifo_ctrl4, 1);
6121 }
6122
6123 return ret;
6124 }
6125
6126 /**
6127 * @brief Sensing chain FIFO stop values memorization at threshold
6128 * level.[get]
6129 *
6130 * @param ctx Read / write interface definitions
6131 * @param val Change the values of stop_on_fth in reg FIFO_CTRL4
6132 * @retval Interface status (MANDATORY: return 0 -> no Error).
6133 *
6134 */
lsm6dsm_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)6135 int32_t lsm6dsm_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx, uint8_t *val)
6136 {
6137 lsm6dsm_fifo_ctrl4_t fifo_ctrl4;
6138 int32_t ret;
6139
6140 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL4,
6141 (uint8_t *)&fifo_ctrl4, 1);
6142 *val = fifo_ctrl4.stop_on_fth;
6143
6144 return ret;
6145 }
6146
6147 /**
6148 * @brief FIFO mode selection.[set]
6149 *
6150 * @param ctx Read / write interface definitions
6151 * @param val Change the values of fifo_mode in reg FIFO_CTRL5
6152 * @retval Interface status (MANDATORY: return 0 -> no Error).
6153 *
6154 */
lsm6dsm_fifo_mode_set(const stmdev_ctx_t * ctx,lsm6dsm_fifo_mode_t val)6155 int32_t lsm6dsm_fifo_mode_set(const stmdev_ctx_t *ctx,
6156 lsm6dsm_fifo_mode_t val)
6157 {
6158 lsm6dsm_fifo_ctrl5_t fifo_ctrl5;
6159 int32_t ret;
6160
6161 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL5,
6162 (uint8_t *)&fifo_ctrl5, 1);
6163
6164 if (ret == 0)
6165 {
6166 fifo_ctrl5.fifo_mode = (uint8_t)val;
6167 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL5,
6168 (uint8_t *)&fifo_ctrl5, 1);
6169 }
6170
6171 return ret;
6172 }
6173
6174 /**
6175 * @brief FIFO mode selection.[get]
6176 *
6177 * @param ctx Read / write interface definitions
6178 * @param val Get the values of fifo_mode in reg FIFO_CTRL5
6179 * @retval Interface status (MANDATORY: return 0 -> no Error).
6180 *
6181 */
lsm6dsm_fifo_mode_get(const stmdev_ctx_t * ctx,lsm6dsm_fifo_mode_t * val)6182 int32_t lsm6dsm_fifo_mode_get(const stmdev_ctx_t *ctx,
6183 lsm6dsm_fifo_mode_t *val)
6184 {
6185 lsm6dsm_fifo_ctrl5_t fifo_ctrl5;
6186 int32_t ret;
6187
6188 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL5,
6189 (uint8_t *)&fifo_ctrl5, 1);
6190
6191 switch (fifo_ctrl5.fifo_mode)
6192 {
6193 case LSM6DSM_BYPASS_MODE:
6194 *val = LSM6DSM_BYPASS_MODE;
6195 break;
6196
6197 case LSM6DSM_FIFO_MODE:
6198 *val = LSM6DSM_FIFO_MODE;
6199 break;
6200
6201 case LSM6DSM_STREAM_TO_FIFO_MODE:
6202 *val = LSM6DSM_STREAM_TO_FIFO_MODE;
6203 break;
6204
6205 case LSM6DSM_BYPASS_TO_STREAM_MODE:
6206 *val = LSM6DSM_BYPASS_TO_STREAM_MODE;
6207 break;
6208
6209 case LSM6DSM_STREAM_MODE:
6210 *val = LSM6DSM_STREAM_MODE;
6211 break;
6212
6213 default:
6214 *val = LSM6DSM_BYPASS_MODE;
6215 break;
6216 }
6217
6218 return ret;
6219 }
6220
6221 /**
6222 * @brief FIFO ODR selection, setting FIFO_MODE also.[set]
6223 *
6224 * @param ctx Read / write interface definitions
6225 * @param val Change the values of odr_fifo in reg FIFO_CTRL5
6226 * @retval Interface status (MANDATORY: return 0 -> no Error).
6227 *
6228 */
lsm6dsm_fifo_data_rate_set(const stmdev_ctx_t * ctx,lsm6dsm_odr_fifo_t val)6229 int32_t lsm6dsm_fifo_data_rate_set(const stmdev_ctx_t *ctx,
6230 lsm6dsm_odr_fifo_t val)
6231 {
6232 lsm6dsm_fifo_ctrl5_t fifo_ctrl5;
6233 int32_t ret;
6234
6235 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL5,
6236 (uint8_t *)&fifo_ctrl5, 1);
6237
6238 if (ret == 0)
6239 {
6240 fifo_ctrl5.odr_fifo = (uint8_t)val;
6241 ret = lsm6dsm_write_reg(ctx, LSM6DSM_FIFO_CTRL5,
6242 (uint8_t *)&fifo_ctrl5, 1);
6243 }
6244
6245 return ret;
6246 }
6247
6248 /**
6249 * @brief FIFO ODR selection, setting FIFO_MODE also.[get]
6250 *
6251 * @param ctx Read / write interface definitions
6252 * @param val Get the values of odr_fifo in reg FIFO_CTRL5
6253 * @retval Interface status (MANDATORY: return 0 -> no Error).
6254 *
6255 */
lsm6dsm_fifo_data_rate_get(const stmdev_ctx_t * ctx,lsm6dsm_odr_fifo_t * val)6256 int32_t lsm6dsm_fifo_data_rate_get(const stmdev_ctx_t *ctx,
6257 lsm6dsm_odr_fifo_t *val)
6258 {
6259 lsm6dsm_fifo_ctrl5_t fifo_ctrl5;
6260 int32_t ret;
6261
6262 ret = lsm6dsm_read_reg(ctx, LSM6DSM_FIFO_CTRL5,
6263 (uint8_t *)&fifo_ctrl5, 1);
6264
6265 switch (fifo_ctrl5.odr_fifo)
6266 {
6267 case LSM6DSM_FIFO_DISABLE:
6268 *val = LSM6DSM_FIFO_DISABLE;
6269 break;
6270
6271 case LSM6DSM_FIFO_12Hz5:
6272 *val = LSM6DSM_FIFO_12Hz5;
6273 break;
6274
6275 case LSM6DSM_FIFO_26Hz:
6276 *val = LSM6DSM_FIFO_26Hz;
6277 break;
6278
6279 case LSM6DSM_FIFO_52Hz:
6280 *val = LSM6DSM_FIFO_52Hz;
6281 break;
6282
6283 case LSM6DSM_FIFO_104Hz:
6284 *val = LSM6DSM_FIFO_104Hz;
6285 break;
6286
6287 case LSM6DSM_FIFO_208Hz:
6288 *val = LSM6DSM_FIFO_208Hz;
6289 break;
6290
6291 case LSM6DSM_FIFO_416Hz:
6292 *val = LSM6DSM_FIFO_416Hz;
6293 break;
6294
6295 case LSM6DSM_FIFO_833Hz:
6296 *val = LSM6DSM_FIFO_833Hz;
6297 break;
6298
6299 case LSM6DSM_FIFO_1k66Hz:
6300 *val = LSM6DSM_FIFO_1k66Hz;
6301 break;
6302
6303 case LSM6DSM_FIFO_3k33Hz:
6304 *val = LSM6DSM_FIFO_3k33Hz;
6305 break;
6306
6307 case LSM6DSM_FIFO_6k66Hz:
6308 *val = LSM6DSM_FIFO_6k66Hz;
6309 break;
6310
6311 default:
6312 *val = LSM6DSM_FIFO_DISABLE;
6313 break;
6314 }
6315
6316 return ret;
6317 }
6318
6319 /**
6320 * @}
6321 *
6322 */
6323
6324 /**
6325 * @defgroup LSM6DSM_DEN_functionality
6326 * @brief This section groups all the functions concerning DEN
6327 * functionality.
6328 * @{
6329 *
6330 */
6331
6332 /**
6333 * @brief DEN active level configuration.[set]
6334 *
6335 * @param ctx Read / write interface definitions
6336 * @param val Change the values of den_lh in reg CTRL5_C
6337 * @retval Interface status (MANDATORY: return 0 -> no Error).
6338 *
6339 */
lsm6dsm_den_polarity_set(const stmdev_ctx_t * ctx,lsm6dsm_den_lh_t val)6340 int32_t lsm6dsm_den_polarity_set(const stmdev_ctx_t *ctx,
6341 lsm6dsm_den_lh_t val)
6342 {
6343 lsm6dsm_ctrl5_c_t ctrl5_c;
6344 int32_t ret;
6345
6346 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
6347
6348 if (ret == 0)
6349 {
6350 ctrl5_c.den_lh = (uint8_t)val;
6351 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
6352 }
6353
6354 return ret;
6355 }
6356
6357 /**
6358 * @brief DEN active level configuration.[get]
6359 *
6360 * @param ctx Read / write interface definitions
6361 * @param val Get the values of den_lh in reg CTRL5_C
6362 * @retval Interface status (MANDATORY: return 0 -> no Error).
6363 *
6364 */
lsm6dsm_den_polarity_get(const stmdev_ctx_t * ctx,lsm6dsm_den_lh_t * val)6365 int32_t lsm6dsm_den_polarity_get(const stmdev_ctx_t *ctx,
6366 lsm6dsm_den_lh_t *val)
6367 {
6368 lsm6dsm_ctrl5_c_t ctrl5_c;
6369 int32_t ret;
6370
6371 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
6372
6373 switch (ctrl5_c.den_lh)
6374 {
6375 case LSM6DSM_DEN_ACT_LOW:
6376 *val = LSM6DSM_DEN_ACT_LOW;
6377 break;
6378
6379 case LSM6DSM_DEN_ACT_HIGH:
6380 *val = LSM6DSM_DEN_ACT_HIGH;
6381 break;
6382
6383 default:
6384 *val = LSM6DSM_DEN_ACT_LOW;
6385 break;
6386 }
6387
6388 return ret;
6389 }
6390
6391 /**
6392 * @brief DEN functionality marking mode[set]
6393 *
6394 * @param ctx Read / write interface definitions
6395 * @param val Change the values of den_mode in reg CTRL6_C
6396 * @retval Interface status (MANDATORY: return 0 -> no Error).
6397 *
6398 */
lsm6dsm_den_mode_set(const stmdev_ctx_t * ctx,lsm6dsm_den_mode_t val)6399 int32_t lsm6dsm_den_mode_set(const stmdev_ctx_t *ctx,
6400 lsm6dsm_den_mode_t val)
6401 {
6402 lsm6dsm_ctrl6_c_t ctrl6_c;
6403 int32_t ret;
6404
6405 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
6406
6407 if (ret == 0)
6408 {
6409 ctrl6_c.den_mode = (uint8_t)val;
6410 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
6411 }
6412
6413 return ret;
6414 }
6415
6416 /**
6417 * @brief DEN functionality marking mode[get]
6418 *
6419 * @param ctx Read / write interface definitions
6420 * @param val Change the values of den_mode in reg CTRL6_C
6421 * @retval Interface status (MANDATORY: return 0 -> no Error).
6422 *
6423 */
lsm6dsm_den_mode_get(const stmdev_ctx_t * ctx,lsm6dsm_den_mode_t * val)6424 int32_t lsm6dsm_den_mode_get(const stmdev_ctx_t *ctx,
6425 lsm6dsm_den_mode_t *val)
6426 {
6427 lsm6dsm_ctrl6_c_t ctrl6_c;
6428 int32_t ret;
6429
6430 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
6431
6432 switch (ctrl6_c.den_mode)
6433 {
6434 case LSM6DSM_DEN_DISABLE:
6435 *val = LSM6DSM_DEN_DISABLE;
6436 break;
6437
6438 case LSM6DSM_LEVEL_LETCHED:
6439 *val = LSM6DSM_LEVEL_LETCHED;
6440 break;
6441
6442 case LSM6DSM_LEVEL_TRIGGER:
6443 *val = LSM6DSM_LEVEL_TRIGGER;
6444 break;
6445
6446 case LSM6DSM_EDGE_TRIGGER:
6447 *val = LSM6DSM_EDGE_TRIGGER;
6448 break;
6449
6450 default:
6451 *val = LSM6DSM_DEN_DISABLE;
6452 break;
6453 }
6454
6455 return ret;
6456 }
6457
6458 /**
6459 * @brief Extend DEN functionality to accelerometer sensor.[set]
6460 *
6461 * @param ctx Read / write interface definitions
6462 * @param val Change the values of den_xl_g in reg CTRL9_XL
6463 * and den_xl_en in CTRL4_C.
6464 * @retval Interface status (MANDATORY: return 0 -> no Error).
6465 *
6466 */
lsm6dsm_den_enable_set(const stmdev_ctx_t * ctx,lsm6dsm_den_xl_en_t val)6467 int32_t lsm6dsm_den_enable_set(const stmdev_ctx_t *ctx,
6468 lsm6dsm_den_xl_en_t val)
6469 {
6470 lsm6dsm_ctrl4_c_t ctrl4_c;
6471 lsm6dsm_ctrl9_xl_t ctrl9_xl;
6472 int32_t ret;
6473
6474 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6475
6476 if (ret == 0)
6477 {
6478 ctrl9_xl.den_xl_g = (uint8_t)val & 0x01U;
6479 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6480
6481 if (ret == 0)
6482 {
6483 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
6484
6485 if (ret == 0)
6486 {
6487 ctrl4_c.den_xl_en = (uint8_t)val & 0x02U;
6488 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
6489 }
6490 }
6491 }
6492
6493 return ret;
6494 }
6495
6496 /**
6497 * @brief Extend DEN functionality to accelerometer sensor. [get]
6498 *
6499 * @param ctx Read / write interface definitions
6500 * @param val Get the values of den_xl_g in reg CTRL9_XL
6501 * and den_xl_en in CTRL4_C.
6502 * @retval Interface status (MANDATORY: return 0 -> no Error).
6503 *
6504 */
lsm6dsm_den_enable_get(const stmdev_ctx_t * ctx,lsm6dsm_den_xl_en_t * val)6505 int32_t lsm6dsm_den_enable_get(const stmdev_ctx_t *ctx,
6506 lsm6dsm_den_xl_en_t *val)
6507 {
6508 lsm6dsm_ctrl4_c_t ctrl4_c;
6509 lsm6dsm_ctrl9_xl_t ctrl9_xl;
6510 int32_t ret;
6511
6512 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
6513
6514 if (ret == 0)
6515 {
6516 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6517
6518 switch ((ctrl4_c.den_xl_en << 1) + ctrl9_xl.den_xl_g)
6519 {
6520 case LSM6DSM_STAMP_IN_GY_DATA:
6521 *val = LSM6DSM_STAMP_IN_GY_DATA;
6522 break;
6523
6524 case LSM6DSM_STAMP_IN_XL_DATA:
6525 *val = LSM6DSM_STAMP_IN_XL_DATA;
6526 break;
6527
6528 case LSM6DSM_STAMP_IN_GY_XL_DATA:
6529 *val = LSM6DSM_STAMP_IN_GY_XL_DATA;
6530 break;
6531
6532 default:
6533 *val = LSM6DSM_STAMP_IN_GY_DATA;
6534 break;
6535 }
6536 }
6537
6538 return ret;
6539 }
6540
6541 /**
6542 * @brief DEN value stored in LSB of Z-axis.[set]
6543 *
6544 * @param ctx Read / write interface definitions
6545 * @param val Change the values of den_z in reg CTRL9_XL
6546 * @retval Interface status (MANDATORY: return 0 -> no Error).
6547 *
6548 */
lsm6dsm_den_mark_axis_z_set(const stmdev_ctx_t * ctx,uint8_t val)6549 int32_t lsm6dsm_den_mark_axis_z_set(const stmdev_ctx_t *ctx, uint8_t val)
6550 {
6551 lsm6dsm_ctrl9_xl_t ctrl9_xl;
6552 int32_t ret;
6553
6554 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6555
6556 if (ret == 0)
6557 {
6558 ctrl9_xl.den_z = val;
6559 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6560 }
6561
6562 return ret;
6563 }
6564
6565 /**
6566 * @brief DEN value stored in LSB of Z-axis.[get]
6567 *
6568 * @param ctx Read / write interface definitions
6569 * @param val Change the values of den_z in reg CTRL9_XL
6570 * @retval Interface status (MANDATORY: return 0 -> no Error).
6571 *
6572 */
lsm6dsm_den_mark_axis_z_get(const stmdev_ctx_t * ctx,uint8_t * val)6573 int32_t lsm6dsm_den_mark_axis_z_get(const stmdev_ctx_t *ctx, uint8_t *val)
6574 {
6575 lsm6dsm_ctrl9_xl_t ctrl9_xl;
6576 int32_t ret;
6577
6578 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6579 *val = ctrl9_xl.den_z;
6580
6581 return ret;
6582 }
6583
6584 /**
6585 * @brief DEN value stored in LSB of Y-axis.[set]
6586 *
6587 * @param ctx Read / write interface definitions
6588 * @param val Change the values of den_y in reg CTRL9_XL
6589 * @retval Interface status (MANDATORY: return 0 -> no Error).
6590 *
6591 */
lsm6dsm_den_mark_axis_y_set(const stmdev_ctx_t * ctx,uint8_t val)6592 int32_t lsm6dsm_den_mark_axis_y_set(const stmdev_ctx_t *ctx, uint8_t val)
6593 {
6594 lsm6dsm_ctrl9_xl_t ctrl9_xl;
6595 int32_t ret;
6596
6597 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6598
6599 if (ret == 0)
6600 {
6601 ctrl9_xl.den_y = val;
6602 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6603 }
6604
6605 return ret;
6606 }
6607
6608 /**
6609 * @brief DEN value stored in LSB of Y-axis.[get]
6610 *
6611 * @param ctx Read / write interface definitions
6612 * @param val Change the values of den_y in reg CTRL9_XL
6613 * @retval Interface status (MANDATORY: return 0 -> no Error).
6614 *
6615 */
lsm6dsm_den_mark_axis_y_get(const stmdev_ctx_t * ctx,uint8_t * val)6616 int32_t lsm6dsm_den_mark_axis_y_get(const stmdev_ctx_t *ctx, uint8_t *val)
6617 {
6618 lsm6dsm_ctrl9_xl_t ctrl9_xl;
6619 int32_t ret;
6620
6621 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6622 *val = ctrl9_xl.den_y;
6623
6624 return ret;
6625 }
6626
6627 /**
6628 * @brief DEN value stored in LSB of X-axis.[set]
6629 *
6630 * @param ctx Read / write interface definitions
6631 * @param val Change the values of den_x in reg CTRL9_XL
6632 * @retval Interface status (MANDATORY: return 0 -> no Error).
6633 *
6634 */
lsm6dsm_den_mark_axis_x_set(const stmdev_ctx_t * ctx,uint8_t val)6635 int32_t lsm6dsm_den_mark_axis_x_set(const stmdev_ctx_t *ctx, uint8_t val)
6636 {
6637 lsm6dsm_ctrl9_xl_t ctrl9_xl;
6638 int32_t ret;
6639
6640 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6641
6642 if (ret == 0)
6643 {
6644 ctrl9_xl.den_x = val;
6645 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6646 }
6647
6648 return ret;
6649 }
6650
6651 /**
6652 * @brief DEN value stored in LSB of X-axis.[get]
6653 *
6654 * @param ctx Read / write interface definitions
6655 * @param val Change the values of den_x in reg CTRL9_XL
6656 * @retval Interface status (MANDATORY: return 0 -> no Error).
6657 *
6658 */
lsm6dsm_den_mark_axis_x_get(const stmdev_ctx_t * ctx,uint8_t * val)6659 int32_t lsm6dsm_den_mark_axis_x_get(const stmdev_ctx_t *ctx, uint8_t *val)
6660 {
6661 lsm6dsm_ctrl9_xl_t ctrl9_xl;
6662 int32_t ret;
6663
6664 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6665 *val = ctrl9_xl.den_x;
6666
6667 return ret;
6668 }
6669
6670 /**
6671 * @}
6672 *
6673 */
6674
6675 /**
6676 * @defgroup LSM6DSM_Pedometer
6677 * @brief This section groups all the functions that manage pedometer.
6678 * @{
6679 *
6680 */
6681
6682 /**
6683 * @brief Reset pedometer step counter.[set]
6684 *
6685 * @param ctx Read / write interface definitions
6686 * @param val Change the values of pedo_rst_step in reg CTRL10_C
6687 * @retval Interface status (MANDATORY: return 0 -> no Error).
6688 *
6689 */
lsm6dsm_pedo_step_reset_set(const stmdev_ctx_t * ctx,uint8_t val)6690 int32_t lsm6dsm_pedo_step_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
6691 {
6692 lsm6dsm_ctrl10_c_t ctrl10_c;
6693 int32_t ret;
6694
6695 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6696
6697 if (ret == 0)
6698 {
6699 ctrl10_c.pedo_rst_step = val;
6700 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6701 }
6702
6703 return ret;
6704 }
6705
6706 /**
6707 * @brief Reset pedometer step counter.[get]
6708 *
6709 * @param ctx Read / write interface definitions
6710 * @param val Change the values of pedo_rst_step in reg CTRL10_C
6711 * @retval Interface status (MANDATORY: return 0 -> no Error).
6712 *
6713 */
lsm6dsm_pedo_step_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)6714 int32_t lsm6dsm_pedo_step_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
6715 {
6716 lsm6dsm_ctrl10_c_t ctrl10_c;
6717 int32_t ret;
6718
6719 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6720 *val = ctrl10_c.pedo_rst_step;
6721
6722 return ret;
6723 }
6724
6725 /**
6726 * @brief Enable pedometer algorithm.[set]
6727 *
6728 * @param ctx Read / write interface definitions
6729 * @param val Change the values of pedo_en in reg CTRL10_C
6730 * @retval Interface status (MANDATORY: return 0 -> no Error).
6731 *
6732 */
lsm6dsm_pedo_sens_set(const stmdev_ctx_t * ctx,uint8_t val)6733 int32_t lsm6dsm_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val)
6734 {
6735 lsm6dsm_ctrl10_c_t ctrl10_c;
6736 int32_t ret;
6737
6738 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6739
6740 if (ret == 0)
6741 {
6742 ctrl10_c.pedo_en = val;
6743
6744 if (val != 0x00U)
6745 {
6746 ctrl10_c.func_en = val;
6747 }
6748
6749 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6750 }
6751
6752 return ret;
6753 }
6754
6755 /**
6756 * @brief pedo_sens: Enable pedometer algorithm.[get]
6757 *
6758 * @param ctx Read / write interface definitions
6759 * @param val Change the values of pedo_en in reg CTRL10_C
6760 * @retval Interface status (MANDATORY: return 0 -> no Error).
6761 *
6762 */
lsm6dsm_pedo_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)6763 int32_t lsm6dsm_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val)
6764 {
6765 lsm6dsm_ctrl10_c_t ctrl10_c;
6766 int32_t ret;
6767
6768 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6769 *val = ctrl10_c.pedo_en;
6770
6771 return ret;
6772 }
6773
6774 /**
6775 * @brief Minimum threshold to detect a peak. Default is 10h.[set]
6776 *
6777 * @param ctx Read / write interface definitions
6778 * @param val Change the values of ths_min in reg
6779 * CONFIG_PEDO_THS_MIN
6780 * @retval Interface status (MANDATORY: return 0 -> no Error).
6781 *
6782 */
lsm6dsm_pedo_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)6783 int32_t lsm6dsm_pedo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
6784 {
6785 lsm6dsm_config_pedo_ths_min_t config_pedo_ths_min;
6786 int32_t ret;
6787
6788 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
6789
6790 if (ret == 0)
6791 {
6792 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN,
6793 (uint8_t *)&config_pedo_ths_min, 1);
6794
6795 if (ret == 0)
6796 {
6797 config_pedo_ths_min.ths_min = val;
6798 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN,
6799 (uint8_t *)&config_pedo_ths_min, 1);
6800
6801 if (ret == 0)
6802 {
6803 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
6804 }
6805 }
6806 }
6807
6808 return ret;
6809 }
6810
6811 /**
6812 * @brief Minimum threshold to detect a peak. Default is 10h.[get]
6813 *
6814 * @param ctx Read / write interface definitions
6815 * @param val Change the values of ths_min in reg CONFIG_PEDO_THS_MIN
6816 * @retval Interface status (MANDATORY: return 0 -> no Error).
6817 *
6818 */
lsm6dsm_pedo_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)6819 int32_t lsm6dsm_pedo_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
6820 {
6821 lsm6dsm_config_pedo_ths_min_t config_pedo_ths_min;
6822 int32_t ret;
6823
6824 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
6825
6826 if (ret == 0)
6827 {
6828 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN,
6829 (uint8_t *)&config_pedo_ths_min, 1);
6830
6831 if (ret == 0)
6832 {
6833 *val = config_pedo_ths_min.ths_min;
6834 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
6835 }
6836 }
6837
6838 return ret;
6839 }
6840
6841 /**
6842 * @brief pedo_full_scale: Pedometer data range.[set]
6843 *
6844 * @param ctx Read / write interface definitions
6845 * @param val Change the values of pedo_fs in
6846 * reg CONFIG_PEDO_THS_MIN
6847 * @retval Interface status (MANDATORY: return 0 -> no Error).
6848 *
6849 */
lsm6dsm_pedo_full_scale_set(const stmdev_ctx_t * ctx,lsm6dsm_pedo_fs_t val)6850 int32_t lsm6dsm_pedo_full_scale_set(const stmdev_ctx_t *ctx,
6851 lsm6dsm_pedo_fs_t val)
6852 {
6853 lsm6dsm_config_pedo_ths_min_t config_pedo_ths_min;
6854 int32_t ret;
6855
6856 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
6857
6858 if (ret == 0)
6859 {
6860 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN,
6861 (uint8_t *)&config_pedo_ths_min, 1);
6862
6863 if (ret == 0)
6864 {
6865 config_pedo_ths_min.pedo_fs = (uint8_t) val;
6866 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN,
6867 (uint8_t *)&config_pedo_ths_min, 1);
6868
6869 if (ret == 0)
6870 {
6871 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
6872 }
6873 }
6874 }
6875
6876 return ret;
6877 }
6878
6879 /**
6880 * @brief Pedometer data range.[get]
6881 *
6882 * @param ctx Read / write interface definitions
6883 * @param val Get the values of pedo_fs in
6884 * reg CONFIG_PEDO_THS_MIN
6885 * @retval Interface status (MANDATORY: return 0 -> no Error).
6886 *
6887 */
lsm6dsm_pedo_full_scale_get(const stmdev_ctx_t * ctx,lsm6dsm_pedo_fs_t * val)6888 int32_t lsm6dsm_pedo_full_scale_get(const stmdev_ctx_t *ctx,
6889 lsm6dsm_pedo_fs_t *val)
6890 {
6891 lsm6dsm_config_pedo_ths_min_t config_pedo_ths_min;
6892 int32_t ret;
6893
6894 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
6895
6896 if (ret == 0)
6897 {
6898 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CONFIG_PEDO_THS_MIN,
6899 (uint8_t *)&config_pedo_ths_min, 1);
6900
6901 if (ret == 0)
6902 {
6903 switch (config_pedo_ths_min.pedo_fs)
6904 {
6905 case LSM6DSM_PEDO_AT_2g:
6906 *val = LSM6DSM_PEDO_AT_2g;
6907 break;
6908
6909 case LSM6DSM_PEDO_AT_4g:
6910 *val = LSM6DSM_PEDO_AT_4g;
6911 break;
6912
6913 default:
6914 *val = LSM6DSM_PEDO_AT_2g;
6915 break;
6916 }
6917
6918 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
6919 }
6920 }
6921
6922 return ret;
6923 }
6924
6925 /**
6926 * @brief Pedometer debounce configuration register (r/w).[set]
6927 *
6928 * @param ctx Read / write interface definitions
6929 * @param val Change the values of deb_step in reg PEDO_DEB_REG
6930 * @retval Interface status (MANDATORY: return 0 -> no Error).
6931 *
6932 */
lsm6dsm_pedo_debounce_steps_set(const stmdev_ctx_t * ctx,uint8_t val)6933 int32_t lsm6dsm_pedo_debounce_steps_set(const stmdev_ctx_t *ctx,
6934 uint8_t val)
6935 {
6936 lsm6dsm_pedo_deb_reg_t pedo_deb_reg;
6937 int32_t ret;
6938
6939 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
6940
6941 if (ret == 0)
6942 {
6943 ret = lsm6dsm_read_reg(ctx, LSM6DSM_PEDO_DEB_REG,
6944 (uint8_t *)&pedo_deb_reg, 1);
6945
6946 if (ret == 0)
6947 {
6948 pedo_deb_reg.deb_step = val;
6949 ret = lsm6dsm_write_reg(ctx, LSM6DSM_PEDO_DEB_REG,
6950 (uint8_t *)&pedo_deb_reg, 1);
6951
6952 if (ret == 0)
6953 {
6954 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
6955 }
6956 }
6957 }
6958
6959 return ret;
6960 }
6961
6962 /**
6963 * @brief Pedometer debounce configuration register (r/w).[get]
6964 *
6965 * @param ctx Read / write interface definitions
6966 * @param val Change the values of deb_step in reg PEDO_DEB_REG
6967 * @retval Interface status (MANDATORY: return 0 -> no Error).
6968 *
6969 */
lsm6dsm_pedo_debounce_steps_get(const stmdev_ctx_t * ctx,uint8_t * val)6970 int32_t lsm6dsm_pedo_debounce_steps_get(const stmdev_ctx_t *ctx,
6971 uint8_t *val)
6972 {
6973 lsm6dsm_pedo_deb_reg_t pedo_deb_reg;
6974 int32_t ret;
6975
6976 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
6977
6978 if (ret == 0)
6979 {
6980 ret = lsm6dsm_read_reg(ctx, LSM6DSM_PEDO_DEB_REG,
6981 (uint8_t *)&pedo_deb_reg, 1);
6982
6983 if (ret == 0)
6984 {
6985 *val = pedo_deb_reg.deb_step;
6986 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
6987 }
6988 }
6989
6990 return ret;
6991 }
6992
6993 /**
6994 * @brief Debounce time. If the time between two consecutive steps is
6995 * greater than DEB_TIME*80ms, the debouncer is reactivated.
6996 * Default value: 01101[set]
6997 *
6998 * @param ctx Read / write interface definitions
6999 * @param val Change the values of deb_time in reg PEDO_DEB_REG
7000 * @retval Interface status (MANDATORY: return 0 -> no Error).
7001 *
7002 */
lsm6dsm_pedo_timeout_set(const stmdev_ctx_t * ctx,uint8_t val)7003 int32_t lsm6dsm_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val)
7004 {
7005 lsm6dsm_pedo_deb_reg_t pedo_deb_reg;
7006 int32_t ret;
7007
7008 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
7009
7010 if (ret == 0)
7011 {
7012 ret = lsm6dsm_read_reg(ctx, LSM6DSM_PEDO_DEB_REG,
7013 (uint8_t *)&pedo_deb_reg, 1);
7014
7015 if (ret == 0)
7016 {
7017 pedo_deb_reg.deb_time = val;
7018 ret = lsm6dsm_write_reg(ctx, LSM6DSM_PEDO_DEB_REG,
7019 (uint8_t *)&pedo_deb_reg, 1);
7020
7021 if (ret == 0)
7022 {
7023 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7024 }
7025 }
7026 }
7027
7028 return ret;
7029 }
7030
7031 /**
7032 * @brief Debounce time. If the time between two consecutive steps is
7033 * greater than DEB_TIME*80ms, the debouncer is reactivated.
7034 * Default value: 01101[get]
7035 *
7036 * @param ctx Read / write interface definitions
7037 * @param val Change the values of deb_time in reg PEDO_DEB_REG
7038 * @retval Interface status (MANDATORY: return 0 -> no Error).
7039 *
7040 */
lsm6dsm_pedo_timeout_get(const stmdev_ctx_t * ctx,uint8_t * val)7041 int32_t lsm6dsm_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val)
7042 {
7043 lsm6dsm_pedo_deb_reg_t pedo_deb_reg;
7044 int32_t ret;
7045
7046 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
7047
7048 if (ret == 0)
7049 {
7050 ret = lsm6dsm_read_reg(ctx, LSM6DSM_PEDO_DEB_REG,
7051 (uint8_t *)&pedo_deb_reg, 1);
7052
7053 if (ret == 0)
7054 {
7055 *val = pedo_deb_reg.deb_time;
7056 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7057 }
7058 }
7059
7060 return ret;
7061 }
7062
7063 /**
7064 * @brief Time period register for step detection on delta time (r/w).[set]
7065 *
7066 * @param ctx Read / write interface definitions
7067 * @param buff Buffer that contains data to write
7068 * @retval Interface status (MANDATORY: return 0 -> no Error).
7069 *
7070 */
lsm6dsm_pedo_steps_period_set(const stmdev_ctx_t * ctx,uint8_t * buff)7071 int32_t lsm6dsm_pedo_steps_period_set(const stmdev_ctx_t *ctx,
7072 uint8_t *buff)
7073 {
7074 int32_t ret;
7075
7076 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
7077
7078 if (ret == 0)
7079 {
7080 ret = lsm6dsm_write_reg(ctx, LSM6DSM_STEP_COUNT_DELTA, buff, 1);
7081
7082 if (ret == 0)
7083 {
7084 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7085 }
7086 }
7087
7088 return ret;
7089 }
7090
7091 /**
7092 * @brief Time period register for step detection on delta time (r/w).[get]
7093 *
7094 * @param ctx Read / write interface definitions
7095 * @param buff Buffer that stores data read
7096 * @retval Interface status (MANDATORY: return 0 -> no Error).
7097 *
7098 */
lsm6dsm_pedo_steps_period_get(const stmdev_ctx_t * ctx,uint8_t * buff)7099 int32_t lsm6dsm_pedo_steps_period_get(const stmdev_ctx_t *ctx,
7100 uint8_t *buff)
7101 {
7102 int32_t ret;
7103
7104 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
7105
7106 if (ret == 0)
7107 {
7108 ret = lsm6dsm_read_reg(ctx, LSM6DSM_STEP_COUNT_DELTA, buff, 1);
7109
7110 if (ret == 0)
7111 {
7112 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7113 }
7114 }
7115
7116 return ret;
7117 }
7118
7119 /**
7120 * @}
7121 *
7122 */
7123
7124 /**
7125 * @defgroup LSM6DSM_significant_motion
7126 * @brief This section groups all the functions that manage the
7127 * significant motion detection.
7128 * @{
7129 *
7130 */
7131
7132 /**
7133 * @brief Enable significant motion detection function.[set]
7134 *
7135 * @param ctx Read / write interface definitions
7136 * @param val Change the values of sign_motion_en in reg CTRL10_C
7137 * @retval Interface status (MANDATORY: return 0 -> no Error).
7138 *
7139 */
lsm6dsm_motion_sens_set(const stmdev_ctx_t * ctx,uint8_t val)7140 int32_t lsm6dsm_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val)
7141 {
7142 lsm6dsm_ctrl10_c_t ctrl10_c;
7143 int32_t ret;
7144
7145 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7146
7147 if (ret == 0)
7148 {
7149 ctrl10_c.sign_motion_en = val;
7150
7151 if (val != 0x00U)
7152 {
7153 ctrl10_c.func_en = val;
7154 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7155 }
7156 }
7157
7158 return ret;
7159 }
7160
7161 /**
7162 * @brief Enable significant motion detection function.[get]
7163 *
7164 * @param ctx Read / write interface definitions
7165 * @param val Change the values of sign_motion_en in reg CTRL10_C
7166 * @retval Interface status (MANDATORY: return 0 -> no Error).
7167 *
7168 */
lsm6dsm_motion_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)7169 int32_t lsm6dsm_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val)
7170 {
7171 lsm6dsm_ctrl10_c_t ctrl10_c;
7172 int32_t ret;
7173
7174 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7175 *val = ctrl10_c.sign_motion_en;
7176
7177 return ret;
7178 }
7179
7180 /**
7181 * @brief Significant motion threshold.[set]
7182 *
7183 * @param ctx Read / write interface definitions
7184 * @param buff Buffer that store significant motion threshold.
7185 * @retval Interface status (MANDATORY: return 0 -> no Error).
7186 *
7187 */
lsm6dsm_motion_threshold_set(const stmdev_ctx_t * ctx,uint8_t * buff)7188 int32_t lsm6dsm_motion_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff)
7189 {
7190 int32_t ret;
7191
7192 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
7193
7194 if (ret == 0)
7195 {
7196 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SM_THS, buff, 1);
7197
7198 if (ret == 0)
7199 {
7200 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7201 }
7202 }
7203
7204 return ret;
7205 }
7206
7207 /**
7208 * @brief Significant motion threshold.[get]
7209 *
7210 * @param ctx Read / write interface definitions
7211 * @param buff Buffer that store significant motion threshold.
7212 * @retval Interface status (MANDATORY: return 0 -> no Error).
7213 *
7214 */
lsm6dsm_motion_threshold_get(const stmdev_ctx_t * ctx,uint8_t * buff)7215 int32_t lsm6dsm_motion_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff)
7216 {
7217 int32_t ret;
7218
7219 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
7220
7221 if (ret == 0)
7222 {
7223 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SM_THS, buff, 1);
7224
7225 if (ret == 0)
7226 {
7227 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7228 }
7229 }
7230
7231 return ret;
7232 }
7233
7234 /**
7235 * @}
7236 *
7237 */
7238
7239 /**
7240 * @defgroup LSM6DSM_tilt_detection
7241 * @brief This section groups all the functions that manage the tilt
7242 * event detection.
7243 * @{
7244 *
7245 */
7246
7247 /**
7248 * @brief Enable tilt calculation.[set]
7249 *
7250 * @param ctx Read / write interface definitions
7251 * @param val Change the values of tilt_en in reg CTRL10_C
7252 * @retval Interface status (MANDATORY: return 0 -> no Error).
7253 *
7254 */
lsm6dsm_tilt_sens_set(const stmdev_ctx_t * ctx,uint8_t val)7255 int32_t lsm6dsm_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val)
7256 {
7257 lsm6dsm_ctrl10_c_t ctrl10_c;
7258 int32_t ret;
7259
7260 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7261
7262 if (ret == 0)
7263 {
7264 ctrl10_c.tilt_en = val;
7265
7266 if (val != 0x00U)
7267 {
7268 ctrl10_c.func_en = val;
7269 }
7270
7271 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7272 }
7273
7274 return ret;
7275 }
7276
7277 /**
7278 * @brief Enable tilt calculation.[get]
7279 *
7280 * @param ctx Read / write interface definitions
7281 * @param val Change the values of tilt_en in reg CTRL10_C
7282 * @retval Interface status (MANDATORY: return 0 -> no Error).
7283 *
7284 */
lsm6dsm_tilt_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)7285 int32_t lsm6dsm_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val)
7286 {
7287 lsm6dsm_ctrl10_c_t ctrl10_c;
7288 int32_t ret;
7289
7290 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7291 *val = ctrl10_c.tilt_en;
7292
7293 return ret;
7294 }
7295
7296 /**
7297 * @brief Enable tilt calculation.[set]
7298 *
7299 * @param ctx Read / write interface definitions
7300 * @param val Change the values of tilt_en in reg CTRL10_C
7301 * @retval Interface status (MANDATORY: return 0 -> no Error).
7302 *
7303 */
lsm6dsm_wrist_tilt_sens_set(const stmdev_ctx_t * ctx,uint8_t val)7304 int32_t lsm6dsm_wrist_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val)
7305 {
7306 lsm6dsm_ctrl10_c_t ctrl10_c;
7307 int32_t ret;
7308
7309 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7310
7311 if (ret == 0)
7312 {
7313 ctrl10_c.wrist_tilt_en = val;
7314
7315 if (val != 0x00U)
7316 {
7317 ctrl10_c.func_en = val;
7318 }
7319
7320 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7321 }
7322
7323 return ret;
7324 }
7325
7326 /**
7327 * @brief Enable tilt calculation.[get]
7328 *
7329 * @param ctx Read / write interface definitions
7330 * @param val Change the values of tilt_en in reg CTRL10_C
7331 * @retval Interface status (MANDATORY: return 0 -> no Error).
7332 *
7333 */
lsm6dsm_wrist_tilt_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)7334 int32_t lsm6dsm_wrist_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val)
7335 {
7336 lsm6dsm_ctrl10_c_t ctrl10_c;
7337 int32_t ret;
7338
7339 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7340 *val = ctrl10_c.wrist_tilt_en;
7341
7342 return ret;
7343 }
7344
7345 /**
7346 * @brief Absolute Wrist Tilt latency register (r/w).
7347 * Absolute wrist tilt latency parameters.
7348 * 1 LSB = 40 ms. Default value: 0Fh (600 ms).[set]
7349 *
7350 * @param ctx Read / write interface definitions
7351 * @param buff Buffer that contains data to write
7352 * @retval Interface status (MANDATORY: return 0 -> no Error).
7353 *
7354 */
lsm6dsm_tilt_latency_set(const stmdev_ctx_t * ctx,uint8_t * buff)7355 int32_t lsm6dsm_tilt_latency_set(const stmdev_ctx_t *ctx, uint8_t *buff)
7356 {
7357 int32_t ret;
7358
7359 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
7360
7361 if (ret == 0)
7362 {
7363 ret = lsm6dsm_write_reg(ctx, LSM6DSM_A_WRIST_TILT_LAT, buff, 1);
7364
7365 if (ret == 0)
7366 {
7367 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7368 }
7369 }
7370
7371 return ret;
7372 }
7373
7374 /**
7375 * @brief Absolute Wrist Tilt latency register (r/w).
7376 * Absolute wrist tilt latency parameters.
7377 * 1 LSB = 40 ms. Default value: 0Fh (600 ms).[get]
7378 *
7379 * @param ctx Read / write interface definitions
7380 * @param buff Buffer that stores data read
7381 * @retval Interface status (MANDATORY: return 0 -> no Error).
7382 *
7383 */
lsm6dsm_tilt_latency_get(const stmdev_ctx_t * ctx,uint8_t * buff)7384 int32_t lsm6dsm_tilt_latency_get(const stmdev_ctx_t *ctx, uint8_t *buff)
7385 {
7386 int32_t ret;
7387
7388 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
7389
7390 if (ret == 0)
7391 {
7392 ret = lsm6dsm_read_reg(ctx, LSM6DSM_A_WRIST_TILT_LAT, buff, 1);
7393
7394 if (ret == 0)
7395 {
7396 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7397 }
7398 }
7399
7400 return ret;
7401 }
7402
7403 /**
7404 * @brief Absolute Wrist Tilt threshold register(r/w).
7405 * Absolute wrist tilt threshold parameters.
7406 * 1 LSB = 15.625 mg.Default value: 20h (500 mg).[set]
7407 *
7408 * @param ctx Read / write interface definitions
7409 * @param buff Buffer that contains data to write
7410 * @retval Interface status (MANDATORY: return 0 -> no Error).
7411 *
7412 */
lsm6dsm_tilt_threshold_set(const stmdev_ctx_t * ctx,uint8_t * buff)7413 int32_t lsm6dsm_tilt_threshold_set(const stmdev_ctx_t *ctx, uint8_t *buff)
7414 {
7415 int32_t ret;
7416
7417 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
7418
7419 if (ret == 0)
7420 {
7421 ret = lsm6dsm_write_reg(ctx, LSM6DSM_A_WRIST_TILT_THS, buff, 1);
7422
7423 if (ret == 0)
7424 {
7425 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7426 }
7427 }
7428
7429 return ret;
7430 }
7431
7432 /**
7433 * @brief Absolute Wrist Tilt threshold register(r/w).
7434 * Absolute wrist tilt threshold parameters.
7435 * 1 LSB = 15.625 mg.Default value: 20h (500 mg).[get]
7436 *
7437 * @param ctx Read / write interface definitions
7438 * @param buff Buffer that stores data read
7439 * @retval Interface status (MANDATORY: return 0 -> no Error).
7440 *
7441 */
lsm6dsm_tilt_threshold_get(const stmdev_ctx_t * ctx,uint8_t * buff)7442 int32_t lsm6dsm_tilt_threshold_get(const stmdev_ctx_t *ctx, uint8_t *buff)
7443 {
7444 int32_t ret;
7445
7446 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
7447
7448 if (ret == 0)
7449 {
7450 ret = lsm6dsm_read_reg(ctx, LSM6DSM_A_WRIST_TILT_THS, buff, 1);
7451
7452 if (ret == 0)
7453 {
7454 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7455 }
7456 }
7457
7458 return ret;
7459 }
7460
7461 /**
7462 * @brief Absolute Wrist Tilt mask register (r/w).[set]
7463 *
7464 * @param ctx Read / write interface definitions
7465 * @param val Registers A_WRIST_TILT_MASK
7466 * @retval Interface status (MANDATORY: return 0 -> no Error).
7467 *
7468 */
lsm6dsm_tilt_src_set(const stmdev_ctx_t * ctx,lsm6dsm_a_wrist_tilt_mask_t * val)7469 int32_t lsm6dsm_tilt_src_set(const stmdev_ctx_t *ctx,
7470 lsm6dsm_a_wrist_tilt_mask_t *val)
7471 {
7472 int32_t ret;
7473
7474 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
7475
7476 if (ret == 0)
7477 {
7478 ret = lsm6dsm_write_reg(ctx, LSM6DSM_A_WRIST_TILT_MASK,
7479 (uint8_t *) val, 1);
7480
7481 if (ret == 0)
7482 {
7483 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7484 }
7485 }
7486
7487 return ret;
7488 }
7489
7490 /**
7491 * @brief Absolute Wrist Tilt mask register (r/w).[get]
7492 *
7493 * @param ctx Read / write interface definitions
7494 * @param val Registers A_WRIST_TILT_MASK
7495 * @retval Interface status (MANDATORY: return 0 -> no Error).
7496 *
7497 */
lsm6dsm_tilt_src_get(const stmdev_ctx_t * ctx,lsm6dsm_a_wrist_tilt_mask_t * val)7498 int32_t lsm6dsm_tilt_src_get(const stmdev_ctx_t *ctx,
7499 lsm6dsm_a_wrist_tilt_mask_t *val)
7500 {
7501 int32_t ret;
7502
7503 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_B);
7504
7505 if (ret == 0)
7506 {
7507 ret = lsm6dsm_read_reg(ctx, LSM6DSM_A_WRIST_TILT_MASK,
7508 (uint8_t *) val, 1);
7509
7510 if (ret == 0)
7511 {
7512 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7513 }
7514 }
7515
7516 return ret;
7517 }
7518
7519 /**
7520 * @}
7521 *
7522 */
7523
7524 /**
7525 * @defgroup LSM6DSM_ magnetometer_sensor
7526 * @brief This section groups all the functions that manage additional
7527 * magnetometer sensor.
7528 * @{
7529 *
7530 */
7531
7532 /**
7533 * @brief Enable soft-iron correction algorithm for magnetometer.[set]
7534 *
7535 * @param ctx Read / write interface definitions
7536 * @param val Change the values of soft_en in reg CTRL9_XL
7537 * @retval Interface status (MANDATORY: return 0 -> no Error).
7538 *
7539 */
lsm6dsm_mag_soft_iron_set(const stmdev_ctx_t * ctx,uint8_t val)7540 int32_t lsm6dsm_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint8_t val)
7541 {
7542 lsm6dsm_ctrl9_xl_t ctrl9_xl;
7543 int32_t ret;
7544
7545 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
7546
7547 if (ret == 0)
7548 {
7549 ctrl9_xl.soft_en = val;
7550 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
7551 }
7552
7553 return ret;
7554 }
7555
7556 /**
7557 * @brief Enable soft-iron correction algorithm for magnetometer.[get]
7558 *
7559 * @param ctx Read / write interface definitions
7560 * @param val Change the values of soft_en in reg CTRL9_XL
7561 * @retval Interface status (MANDATORY: return 0 -> no Error).
7562 *
7563 */
lsm6dsm_mag_soft_iron_get(const stmdev_ctx_t * ctx,uint8_t * val)7564 int32_t lsm6dsm_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint8_t *val)
7565 {
7566 lsm6dsm_ctrl9_xl_t ctrl9_xl;
7567 int32_t ret;
7568
7569 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
7570 *val = ctrl9_xl.soft_en;
7571
7572 return ret;
7573 }
7574
7575 /**
7576 * @brief Enable hard-iron correction algorithm for magnetometer.[set]
7577 *
7578 * @param ctx Read / write interface definitions
7579 * @param val Change the values of iron_en in reg MASTER_CONFIG
7580 * @retval Interface status (MANDATORY: return 0 -> no Error).
7581 *
7582 */
lsm6dsm_mag_hard_iron_set(const stmdev_ctx_t * ctx,uint8_t val)7583 int32_t lsm6dsm_mag_hard_iron_set(const stmdev_ctx_t *ctx, uint8_t val)
7584 {
7585 lsm6dsm_master_config_t master_config;
7586 lsm6dsm_ctrl10_c_t ctrl10_c;
7587 int32_t ret;
7588
7589 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
7590 (uint8_t *)&master_config, 1);
7591
7592 if (ret == 0)
7593 {
7594 master_config.iron_en = val;
7595 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
7596 (uint8_t *)&master_config, 1);
7597
7598 if (ret == 0)
7599 {
7600 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7601
7602 if (ret == 0)
7603 {
7604 if (val != 0x00U)
7605 {
7606 ctrl10_c.func_en = val;
7607 }
7608
7609 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C,
7610 (uint8_t *)&ctrl10_c, 1);
7611 }
7612 }
7613 }
7614
7615 return ret;
7616 }
7617
7618 /**
7619 * @brief Enable hard-iron correction algorithm for magnetometer.[get]
7620 *
7621 * @param ctx Read / write interface definitions
7622 * @param val Change the values of iron_en in reg MASTER_CONFIG
7623 * @retval Interface status (MANDATORY: return 0 -> no Error).
7624 *
7625 */
lsm6dsm_mag_hard_iron_get(const stmdev_ctx_t * ctx,uint8_t * val)7626 int32_t lsm6dsm_mag_hard_iron_get(const stmdev_ctx_t *ctx, uint8_t *val)
7627 {
7628 lsm6dsm_master_config_t master_config;
7629 int32_t ret;
7630
7631 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
7632 (uint8_t *)&master_config, 1);
7633 *val = master_config.iron_en;
7634
7635 return ret;
7636 }
7637
7638 /**
7639 * @brief Soft iron 3x3 matrix. Value are expressed in sign-module format.
7640 * (Es. SVVVVVVVb where S is the sign 0/+1/- and V is the value).[set]
7641 *
7642 * @param ctx Read / write interface definitions
7643 * @param buff Buffer that contains data to write
7644 * @retval Interface status (MANDATORY: return 0 -> no Error).
7645 *
7646 */
lsm6dsm_mag_soft_iron_mat_set(const stmdev_ctx_t * ctx,uint8_t * buff)7647 int32_t lsm6dsm_mag_soft_iron_mat_set(const stmdev_ctx_t *ctx,
7648 uint8_t *buff)
7649 {
7650 int32_t ret;
7651
7652 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
7653
7654 if (ret == 0)
7655 {
7656 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MAG_SI_XX, buff, 9);
7657
7658 if (ret == 0)
7659 {
7660 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7661 }
7662 }
7663
7664 return ret;
7665 }
7666
7667 /**
7668 * @brief Soft iron 3x3 matrix. Value are expressed in sign-module format.
7669 * (Es. SVVVVVVVb where S is the sign 0/+1/- and V is the value).[get]
7670 *
7671 * @param ctx Read / write interface definitions
7672 * @param buff Buffer that stores data read
7673 * @retval Interface status (MANDATORY: return 0 -> no Error).
7674 *
7675 */
lsm6dsm_mag_soft_iron_mat_get(const stmdev_ctx_t * ctx,uint8_t * buff)7676 int32_t lsm6dsm_mag_soft_iron_mat_get(const stmdev_ctx_t *ctx,
7677 uint8_t *buff)
7678 {
7679 int32_t ret;
7680
7681 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
7682
7683 if (ret == 0)
7684 {
7685 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MAG_SI_XX, buff, 9);
7686
7687 if (ret == 0)
7688 {
7689 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7690 }
7691 }
7692
7693 return ret;
7694 }
7695
7696 /**
7697 * @brief Offset for hard-iron compensation register (r/w). The value is
7698 * expressed as a 16-bit word in two’s complement.[set]
7699 *
7700 * @param ctx Read / write interface definitions
7701 * @param buff Buffer that contains data to write
7702 * @retval Interface status (MANDATORY: return 0 -> no Error).
7703 *
7704 */
lsm6dsm_mag_offset_set(const stmdev_ctx_t * ctx,int16_t * val)7705 int32_t lsm6dsm_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val)
7706 {
7707 uint8_t buff[6];
7708 int32_t ret;
7709
7710 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
7711
7712 if (ret == 0)
7713 {
7714 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
7715 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
7716 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
7717 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
7718 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
7719 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
7720 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MAG_OFFX_L, buff, 6);
7721
7722 if (ret == 0)
7723 {
7724 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7725 }
7726 }
7727
7728 return ret;
7729 }
7730
7731 /**
7732 * @brief Offset for hard-iron compensation register(r/w).
7733 * The value is expressed as a 16-bit word in two’s complement.[get]
7734 *
7735 * @param ctx Read / write interface definitions
7736 * @param buff Buffer that stores data read
7737 * @retval Interface status (MANDATORY: return 0 -> no Error).
7738 *
7739 */
lsm6dsm_mag_offset_get(const stmdev_ctx_t * ctx,int16_t * val)7740 int32_t lsm6dsm_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
7741 {
7742 uint8_t buff[6];
7743 int32_t ret;
7744
7745 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
7746
7747 if (ret == 0)
7748 {
7749 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MAG_OFFX_L, buff, 6);
7750
7751 if (ret == 0)
7752 {
7753 val[0] = (int16_t)buff[1];
7754 val[0] = (val[0] * 256) + (int16_t)buff[0];
7755 val[1] = (int16_t)buff[3];
7756 val[1] = (val[1] * 256) + (int16_t)buff[2];
7757 val[2] = (int16_t)buff[5];
7758 val[2] = (val[2] * 256) + (int16_t)buff[4];
7759 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
7760 }
7761 }
7762
7763 return ret;
7764 }
7765
7766 /**
7767 * @}
7768 *
7769 */
7770
7771 /**
7772 * @defgroup LSM6DSM_Sensor_hub
7773 * @brief This section groups all the functions that manage the sensor
7774 * hub functionality.
7775 * @{
7776 *
7777 */
7778
7779 /**
7780 * @brief Enable function.[set]
7781 *
7782 * @param ctx Read / write interface definitions
7783 * @param val Change the values func_en
7784 * @retval Interface status (MANDATORY: return 0 -> no Error).
7785 *
7786 */
lsm6dsm_func_en_set(const stmdev_ctx_t * ctx,uint8_t val)7787 int32_t lsm6dsm_func_en_set(const stmdev_ctx_t *ctx, uint8_t val)
7788 {
7789 lsm6dsm_ctrl10_c_t ctrl10_c;
7790 int32_t ret;
7791
7792 ret = lsm6dsm_read_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7793
7794 if (ret == 0)
7795 {
7796 ctrl10_c.func_en = val;
7797 ret = lsm6dsm_write_reg(ctx, LSM6DSM_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
7798 }
7799
7800 return ret;
7801 }
7802
7803 /**
7804 * @brief Sensor synchronization time frame with the step of 500 ms and
7805 * full range of 5s. Unsigned 8-bit.[set]
7806 *
7807 * @param ctx Read / write interface definitions
7808 * @param val Change the values of tph in reg SENSOR_SYNC_TIME_FRAME
7809 * @retval Interface status (MANDATORY: return 0 -> no Error).
7810 *
7811 */
lsm6dsm_sh_sync_sens_frame_set(const stmdev_ctx_t * ctx,uint8_t val)7812 int32_t lsm6dsm_sh_sync_sens_frame_set(const stmdev_ctx_t *ctx, uint8_t val)
7813 {
7814 lsm6dsm_sensor_sync_time_frame_t sensor_sync_time_frame;
7815 int32_t ret;
7816
7817 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSOR_SYNC_TIME_FRAME,
7818 (uint8_t *)&sensor_sync_time_frame, 1);
7819
7820 if (ret == 0)
7821 {
7822 sensor_sync_time_frame.tph = val;
7823 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SENSOR_SYNC_TIME_FRAME,
7824 (uint8_t *)&sensor_sync_time_frame, 1);
7825 }
7826
7827 return ret;
7828 }
7829
7830 /**
7831 * @brief Sensor synchronization time frame with the step of 500 ms and
7832 * full range of 5s. Unsigned 8-bit.[get]
7833 *
7834 * @param ctx Read / write interface definitions
7835 * @param val Change the values of tph in reg SENSOR_SYNC_TIME_FRAME
7836 * @retval Interface status (MANDATORY: return 0 -> no Error).
7837 *
7838 */
lsm6dsm_sh_sync_sens_frame_get(const stmdev_ctx_t * ctx,uint8_t * val)7839 int32_t lsm6dsm_sh_sync_sens_frame_get(const stmdev_ctx_t *ctx,
7840 uint8_t *val)
7841 {
7842 lsm6dsm_sensor_sync_time_frame_t sensor_sync_time_frame;
7843 int32_t ret;
7844
7845 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSOR_SYNC_TIME_FRAME,
7846 (uint8_t *)&sensor_sync_time_frame, 1);
7847 *val = sensor_sync_time_frame.tph;
7848
7849 return ret;
7850 }
7851
7852 /**
7853 * @brief Resolution ratio of error code for sensor synchronization.[set]
7854 *
7855 * @param ctx Read / write interface definitions
7856 * @param val Change the values of rr in reg SENSOR_SYNC_RES_RATIO
7857 * @retval Interface status (MANDATORY: return 0 -> no Error).
7858 *
7859 */
lsm6dsm_sh_sync_sens_ratio_set(const stmdev_ctx_t * ctx,lsm6dsm_rr_t val)7860 int32_t lsm6dsm_sh_sync_sens_ratio_set(const stmdev_ctx_t *ctx,
7861 lsm6dsm_rr_t val)
7862 {
7863 lsm6dsm_sensor_sync_res_ratio_t sensor_sync_res_ratio;
7864 int32_t ret;
7865
7866 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSOR_SYNC_RES_RATIO,
7867 (uint8_t *)&sensor_sync_res_ratio, 1);
7868
7869 if (ret == 0)
7870 {
7871 sensor_sync_res_ratio.rr = (uint8_t) val;
7872 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SENSOR_SYNC_RES_RATIO,
7873 (uint8_t *)&sensor_sync_res_ratio, 1);
7874 }
7875
7876 return ret;
7877 }
7878
7879 /**
7880 * @brief Resolution ratio of error code for sensor synchronization.[get]
7881 *
7882 * @param ctx Read / write interface definitions
7883 * @param val Get the values of rr in reg SENSOR_SYNC_RES_RATIO
7884 * @retval Interface status (MANDATORY: return 0 -> no Error).
7885 *
7886 */
lsm6dsm_sh_sync_sens_ratio_get(const stmdev_ctx_t * ctx,lsm6dsm_rr_t * val)7887 int32_t lsm6dsm_sh_sync_sens_ratio_get(const stmdev_ctx_t *ctx,
7888 lsm6dsm_rr_t *val)
7889 {
7890 lsm6dsm_sensor_sync_res_ratio_t sensor_sync_res_ratio;
7891 int32_t ret;
7892
7893 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSOR_SYNC_RES_RATIO,
7894 (uint8_t *)&sensor_sync_res_ratio, 1);
7895
7896 switch (sensor_sync_res_ratio.rr)
7897 {
7898 case LSM6DSM_RES_RATIO_2_11:
7899 *val = LSM6DSM_RES_RATIO_2_11;
7900 break;
7901
7902 case LSM6DSM_RES_RATIO_2_12:
7903 *val = LSM6DSM_RES_RATIO_2_12;
7904 break;
7905
7906 case LSM6DSM_RES_RATIO_2_13:
7907 *val = LSM6DSM_RES_RATIO_2_13;
7908 break;
7909
7910 case LSM6DSM_RES_RATIO_2_14:
7911 *val = LSM6DSM_RES_RATIO_2_14;
7912 break;
7913
7914 default:
7915 *val = LSM6DSM_RES_RATIO_2_11;
7916 break;
7917 }
7918
7919 return ret;
7920 }
7921
7922 /**
7923 * @brief Sensor hub I2C master enable.[set]
7924 *
7925 * @param ctx Read / write interface definitions
7926 * @param val Change the values of master_on in reg MASTER_CONFIG
7927 * @retval Interface status (MANDATORY: return 0 -> no Error).
7928 *
7929 */
lsm6dsm_sh_master_set(const stmdev_ctx_t * ctx,uint8_t val)7930 int32_t lsm6dsm_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val)
7931 {
7932 lsm6dsm_master_config_t master_config;
7933 int32_t ret;
7934
7935 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
7936 (uint8_t *)&master_config, 1);
7937
7938 if (ret == 0)
7939 {
7940 master_config.master_on = val;
7941 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
7942 (uint8_t *)&master_config, 1);
7943 }
7944
7945 return ret;
7946 }
7947
7948 /**
7949 * @brief Sensor hub I2C master enable.[get]
7950 *
7951 * @param ctx Read / write interface definitions
7952 * @param val Change the values of master_on in reg MASTER_CONFIG
7953 * @retval Interface status (MANDATORY: return 0 -> no Error).
7954 *
7955 */
lsm6dsm_sh_master_get(const stmdev_ctx_t * ctx,uint8_t * val)7956 int32_t lsm6dsm_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val)
7957 {
7958 lsm6dsm_master_config_t master_config;
7959 int32_t ret;
7960
7961 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
7962 (uint8_t *)&master_config, 1);
7963 *val = master_config.master_on;
7964
7965 return ret;
7966 }
7967
7968 /**
7969 * @brief I2C interface pass-through.[set]
7970 *
7971 * @param ctx Read / write interface definitions
7972 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
7973 * @retval Interface status (MANDATORY: return 0 -> no Error).
7974 *
7975 */
lsm6dsm_sh_pass_through_set(const stmdev_ctx_t * ctx,uint8_t val)7976 int32_t lsm6dsm_sh_pass_through_set(const stmdev_ctx_t *ctx, uint8_t val)
7977 {
7978 lsm6dsm_master_config_t master_config;
7979 int32_t ret;
7980
7981 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
7982 (uint8_t *)&master_config, 1);
7983
7984 if (ret == 0)
7985 {
7986 master_config.pass_through_mode = val;
7987 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
7988 (uint8_t *)&master_config, 1);
7989 }
7990
7991 return ret;
7992 }
7993
7994 /**
7995 * @brief I2C interface pass-through.[get]
7996 *
7997 * @param ctx Read / write interface definitions
7998 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
7999 * @retval Interface status (MANDATORY: return 0 -> no Error).
8000 *
8001 */
lsm6dsm_sh_pass_through_get(const stmdev_ctx_t * ctx,uint8_t * val)8002 int32_t lsm6dsm_sh_pass_through_get(const stmdev_ctx_t *ctx, uint8_t *val)
8003 {
8004 lsm6dsm_master_config_t master_config;
8005 int32_t ret;
8006
8007 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
8008 (uint8_t *)&master_config, 1);
8009 *val = master_config.pass_through_mode;
8010
8011 return ret;
8012 }
8013
8014 /**
8015 * @brief Master I2C pull-up enable/disable.[set]
8016 *
8017 * @param ctx Read / write interface definitions
8018 * @param val Change the values of pull_up_en in reg MASTER_CONFIG
8019 * @retval Interface status (MANDATORY: return 0 -> no Error).
8020 *
8021 */
lsm6dsm_sh_pin_mode_set(const stmdev_ctx_t * ctx,lsm6dsm_pull_up_en_t val)8022 int32_t lsm6dsm_sh_pin_mode_set(const stmdev_ctx_t *ctx,
8023 lsm6dsm_pull_up_en_t val)
8024 {
8025 lsm6dsm_master_config_t master_config;
8026 int32_t ret;
8027
8028 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
8029 (uint8_t *)&master_config, 1);
8030
8031 if (ret == 0)
8032 {
8033 master_config.pull_up_en = (uint8_t) val;
8034 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
8035 (uint8_t *)&master_config, 1);
8036 }
8037
8038 return ret;
8039 }
8040
8041 /**
8042 * @brief Master I2C pull-up enable/disable.[get]
8043 *
8044 * @param ctx Read / write interface definitions
8045 * @param val Get the values of pull_up_en in reg MASTER_CONFIG
8046 * @retval Interface status (MANDATORY: return 0 -> no Error).
8047 *
8048 */
lsm6dsm_sh_pin_mode_get(const stmdev_ctx_t * ctx,lsm6dsm_pull_up_en_t * val)8049 int32_t lsm6dsm_sh_pin_mode_get(const stmdev_ctx_t *ctx,
8050 lsm6dsm_pull_up_en_t *val)
8051 {
8052 lsm6dsm_master_config_t master_config;
8053 int32_t ret;
8054
8055 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
8056 (uint8_t *)&master_config, 1);
8057
8058 switch (master_config.pull_up_en)
8059 {
8060 case LSM6DSM_EXT_PULL_UP:
8061 *val = LSM6DSM_EXT_PULL_UP;
8062 break;
8063
8064 case LSM6DSM_INTERNAL_PULL_UP:
8065 *val = LSM6DSM_INTERNAL_PULL_UP;
8066 break;
8067
8068 default:
8069 *val = LSM6DSM_SH_PIN_MODE;
8070 break;
8071 }
8072
8073 return ret;
8074 }
8075
8076 /**
8077 * @brief Sensor hub trigger signal selection.[set]
8078 *
8079 * @param ctx Read / write interface definitions
8080 * @param val Change the values of start_config in reg MASTER_CONFIG
8081 * @retval Interface status (MANDATORY: return 0 -> no Error).
8082 *
8083 */
lsm6dsm_sh_syncro_mode_set(const stmdev_ctx_t * ctx,lsm6dsm_start_config_t val)8084 int32_t lsm6dsm_sh_syncro_mode_set(const stmdev_ctx_t *ctx,
8085 lsm6dsm_start_config_t val)
8086 {
8087 lsm6dsm_master_config_t master_config;
8088 int32_t ret;
8089
8090 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
8091 (uint8_t *)&master_config, 1);
8092
8093 if (ret == 0)
8094 {
8095 master_config.start_config = (uint8_t)val;
8096 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
8097 (uint8_t *)&master_config, 1);
8098 }
8099
8100 return ret;
8101 }
8102
8103 /**
8104 * @brief Sensor hub trigger signal selection.[get]
8105 *
8106 * @param ctx Read / write interface definitions
8107 * @param val Get the values of start_config in reg MASTER_CONFIG
8108 * @retval Interface status (MANDATORY: return 0 -> no Error).
8109 *
8110 */
lsm6dsm_sh_syncro_mode_get(const stmdev_ctx_t * ctx,lsm6dsm_start_config_t * val)8111 int32_t lsm6dsm_sh_syncro_mode_get(const stmdev_ctx_t *ctx,
8112 lsm6dsm_start_config_t *val)
8113 {
8114 lsm6dsm_master_config_t master_config;
8115 int32_t ret;
8116
8117 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
8118 (uint8_t *)&master_config, 1);
8119
8120 switch (master_config.start_config)
8121 {
8122 case LSM6DSM_XL_GY_DRDY:
8123 *val = LSM6DSM_XL_GY_DRDY;
8124 break;
8125
8126 case LSM6DSM_EXT_ON_INT2_PIN:
8127 *val = LSM6DSM_EXT_ON_INT2_PIN;
8128 break;
8129
8130 default:
8131 *val = LSM6DSM_XL_GY_DRDY;
8132 break;
8133 }
8134
8135 return ret;
8136 }
8137
8138 /**
8139 * @brief Manage the Master DRDY signal on INT1 pad.[set]
8140 *
8141 * @param ctx Read / write interface definitions
8142 * @param val Change the values of drdy_on_int1 in reg MASTER_CONFIG
8143 * @retval Interface status (MANDATORY: return 0 -> no Error).
8144 *
8145 */
lsm6dsm_sh_drdy_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)8146 int32_t lsm6dsm_sh_drdy_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
8147 {
8148 lsm6dsm_master_config_t master_config;
8149 int32_t ret;
8150
8151 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
8152 (uint8_t *)&master_config, 1);
8153
8154 if (ret == 0)
8155 {
8156 master_config.drdy_on_int1 = val;
8157 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CONFIG,
8158 (uint8_t *)&master_config, 1);
8159 }
8160
8161 return ret;
8162 }
8163
8164 /**
8165 * @brief Manage the Master DRDY signal on INT1 pad.[get]
8166 *
8167 * @param ctx Read / write interface definitions
8168 * @param val Change the values of drdy_on_int1 in reg MASTER_CONFIG
8169 * @retval Interface status (MANDATORY: return 0 -> no Error).
8170 *
8171 */
lsm6dsm_sh_drdy_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)8172 int32_t lsm6dsm_sh_drdy_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
8173 {
8174 lsm6dsm_master_config_t master_config;
8175 int32_t ret;
8176
8177 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CONFIG,
8178 (uint8_t *)&master_config, 1);
8179 *val = master_config.drdy_on_int1;
8180
8181 return ret;
8182 }
8183
8184 /**
8185 * @brief Sensor hub output registers.[get]
8186 *
8187 * @param ctx Read / write interface definitions
8188 * @param val Structure of registers from SENSORHUB1_REG
8189 * @retval Interface status (MANDATORY: return 0 -> no Error).
8190 *
8191 */
lsm6dsm_sh_read_data_raw_get(const stmdev_ctx_t * ctx,lsm6dsm_emb_sh_read_t * val)8192 int32_t lsm6dsm_sh_read_data_raw_get(const stmdev_ctx_t *ctx,
8193 lsm6dsm_emb_sh_read_t *val)
8194 {
8195 int32_t ret;
8196
8197 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSORHUB1_REG,
8198 (uint8_t *) & (val->sh_byte_1), 12);
8199
8200 if (ret == 0)
8201 {
8202 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENSORHUB13_REG,
8203 (uint8_t *) & (val->sh_byte_13), 6);
8204 }
8205
8206 return ret;
8207 }
8208
8209 /**
8210 * @brief Master command code used for stamping for sensor sync.[set]
8211 *
8212 * @param ctx Read / write interface definitions
8213 * @param val Change the values of master_cmd_code in
8214 * reg MASTER_CMD_CODE
8215 * @retval Interface status (MANDATORY: return 0 -> no Error).
8216 *
8217 */
lsm6dsm_sh_cmd_sens_sync_set(const stmdev_ctx_t * ctx,uint8_t val)8218 int32_t lsm6dsm_sh_cmd_sens_sync_set(const stmdev_ctx_t *ctx, uint8_t val)
8219 {
8220 lsm6dsm_master_cmd_code_t master_cmd_code;
8221 int32_t ret;
8222
8223 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CMD_CODE,
8224 (uint8_t *)&master_cmd_code, 1);
8225
8226 if (ret == 0)
8227 {
8228 master_cmd_code.master_cmd_code = val;
8229 ret = lsm6dsm_write_reg(ctx, LSM6DSM_MASTER_CMD_CODE,
8230 (uint8_t *)&master_cmd_code, 1);
8231 }
8232
8233 return ret;
8234 }
8235
8236 /**
8237 * @brief Master command code used for stamping for sensor sync.[get]
8238 *
8239 * @param ctx Read / write interface definitions
8240 * @param val Change the values of master_cmd_code in
8241 * reg MASTER_CMD_CODE
8242 * @retval Interface status (MANDATORY: return 0 -> no Error).
8243 *
8244 */
lsm6dsm_sh_cmd_sens_sync_get(const stmdev_ctx_t * ctx,uint8_t * val)8245 int32_t lsm6dsm_sh_cmd_sens_sync_get(const stmdev_ctx_t *ctx, uint8_t *val)
8246 {
8247 lsm6dsm_master_cmd_code_t master_cmd_code;
8248 int32_t ret;
8249
8250 ret = lsm6dsm_read_reg(ctx, LSM6DSM_MASTER_CMD_CODE,
8251 (uint8_t *)&master_cmd_code, 1);
8252 *val = master_cmd_code.master_cmd_code;
8253
8254 return ret;
8255 }
8256
8257 /**
8258 * @brief Error code used for sensor synchronization.[set]
8259 *
8260 * @param ctx Read / write interface definitions
8261 * @param val Change the values of error_code in
8262 * reg SENS_SYNC_SPI_ERROR_CODE.
8263 * @retval Interface status (MANDATORY: return 0 -> no Error).
8264 *
8265 */
lsm6dsm_sh_spi_sync_error_set(const stmdev_ctx_t * ctx,uint8_t val)8266 int32_t lsm6dsm_sh_spi_sync_error_set(const stmdev_ctx_t *ctx, uint8_t val)
8267 {
8268 lsm6dsm_sens_sync_spi_error_code_t sens_sync_spi_error_code;
8269 int32_t ret;
8270
8271 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENS_SYNC_SPI_ERROR_CODE,
8272 (uint8_t *)&sens_sync_spi_error_code, 1);
8273
8274 if (ret == 0)
8275 {
8276 sens_sync_spi_error_code.error_code = val;
8277 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SENS_SYNC_SPI_ERROR_CODE,
8278 (uint8_t *)&sens_sync_spi_error_code, 1);
8279 }
8280
8281 return ret;
8282 }
8283
8284 /**
8285 * @brief Error code used for sensor synchronization.[get]
8286 *
8287 * @param ctx Read / write interface definitions
8288 * @param val Change the values of error_code in
8289 * reg SENS_SYNC_SPI_ERROR_CODE.
8290 * @retval Interface status (MANDATORY: return 0 -> no Error).
8291 *
8292 */
lsm6dsm_sh_spi_sync_error_get(const stmdev_ctx_t * ctx,uint8_t * val)8293 int32_t lsm6dsm_sh_spi_sync_error_get(const stmdev_ctx_t *ctx, uint8_t *val)
8294 {
8295 lsm6dsm_sens_sync_spi_error_code_t sens_sync_spi_error_code;
8296 int32_t ret;
8297
8298 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SENS_SYNC_SPI_ERROR_CODE,
8299 (uint8_t *)&sens_sync_spi_error_code, 1);
8300 *val = sens_sync_spi_error_code.error_code;
8301
8302 return ret;
8303 }
8304
8305 /**
8306 * @brief Number of external sensors to be read by the sensor hub.[set]
8307 *
8308 * @param ctx Read / write interface definitions
8309 * @param val Change the values of aux_sens_on in reg SLAVE0_CONFIG.
8310 * @retval Interface status (MANDATORY: return 0 -> no Error).
8311 *
8312 */
lsm6dsm_sh_num_of_dev_connected_set(const stmdev_ctx_t * ctx,lsm6dsm_aux_sens_on_t val)8313 int32_t lsm6dsm_sh_num_of_dev_connected_set(const stmdev_ctx_t *ctx,
8314 lsm6dsm_aux_sens_on_t val)
8315 {
8316 lsm6dsm_slave0_config_t slave0_config;
8317 int32_t ret;
8318
8319 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8320
8321 if (ret == 0)
8322 {
8323 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
8324 (uint8_t *)&slave0_config, 1);
8325
8326 if (ret == 0)
8327 {
8328 slave0_config.aux_sens_on = (uint8_t) val;
8329 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
8330 (uint8_t *)&slave0_config, 1);
8331
8332 if (ret == 0)
8333 {
8334 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8335 }
8336 }
8337 }
8338
8339 return ret;
8340 }
8341
8342 /**
8343 * @brief Number of external sensors to be read by the sensor hub.[get]
8344 *
8345 * @param ctx Read / write interface definitions
8346 * @param val Get the values of aux_sens_on in reg SLAVE0_CONFIG.
8347 * @retval Interface status (MANDATORY: return 0 -> no Error).
8348 *
8349 */
lsm6dsm_sh_num_of_dev_connected_get(const stmdev_ctx_t * ctx,lsm6dsm_aux_sens_on_t * val)8350 int32_t lsm6dsm_sh_num_of_dev_connected_get(const stmdev_ctx_t *ctx,
8351 lsm6dsm_aux_sens_on_t *val)
8352 {
8353 lsm6dsm_slave0_config_t slave0_config;
8354 int32_t ret;
8355
8356 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8357
8358 if (ret == 0)
8359 {
8360 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
8361 (uint8_t *)&slave0_config, 1);
8362
8363 if (ret == 0)
8364 {
8365 switch (slave0_config.aux_sens_on)
8366 {
8367 case LSM6DSM_SLV_0:
8368 *val = LSM6DSM_SLV_0;
8369 break;
8370
8371 case LSM6DSM_SLV_0_1:
8372 *val = LSM6DSM_SLV_0_1;
8373 break;
8374
8375 case LSM6DSM_SLV_0_1_2:
8376 *val = LSM6DSM_SLV_0_1_2;
8377 break;
8378
8379 case LSM6DSM_SLV_0_1_2_3:
8380 *val = LSM6DSM_SLV_0_1_2_3;
8381 break;
8382
8383 default:
8384 *val = LSM6DSM_SLV_0;
8385 break;
8386 }
8387
8388 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8389 }
8390 }
8391
8392 return ret;
8393 }
8394
8395 /**
8396 * @brief Configure slave 0 for perform a write.[set]
8397 *
8398 * @param ctx Read / write interface definitions
8399 * @param val Structure that contain:
8400 * - uint8_t slv_add; 8 bit i2c device address
8401 * - uint8_t slv_subadd; 8 bit register device address
8402 * - uint8_t slv_data; 8 bit data to write
8403 * @retval Interface status (MANDATORY: return 0 -> no Error).
8404 *
8405 */
lsm6dsm_sh_cfg_write(const stmdev_ctx_t * ctx,lsm6dsm_sh_cfg_write_t * val)8406 int32_t lsm6dsm_sh_cfg_write(const stmdev_ctx_t *ctx,
8407 lsm6dsm_sh_cfg_write_t *val)
8408 {
8409 lsm6dsm_slv0_add_t slv0_add;
8410 int32_t ret;
8411
8412 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8413
8414 if (ret == 0)
8415 {
8416 slv0_add.slave0_add = val->slv0_add;
8417 slv0_add.rw_0 = 0;
8418 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV0_ADD, (uint8_t *)&slv0_add, 1);
8419
8420 if (ret == 0)
8421 {
8422 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV0_SUBADD,
8423 &(val->slv0_subadd), 1);
8424
8425 if (ret == 0)
8426 {
8427 ret = lsm6dsm_write_reg(ctx, LSM6DSM_DATAWRITE_SRC_MODE_SUB_SLV0,
8428 &(val->slv0_data), 1);
8429
8430 if (ret == 0)
8431 {
8432 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8433 }
8434 }
8435 }
8436 }
8437
8438 return ret;
8439 }
8440
8441 /**
8442 * @brief Configure slave 0 for perform a read.[get]
8443 *
8444 * @param ctx Read / write interface definitions
8445 * @param val Structure that contain:
8446 * - uint8_t slv_add; 8 bit i2c device address
8447 * - uint8_t slv_subadd; 8 bit register device address
8448 * - uint8_t slv_len; num of bit to read
8449 * @retval Interface status (MANDATORY: return 0 -> no Error).
8450 *
8451 */
lsm6dsm_sh_slv0_cfg_read(const stmdev_ctx_t * ctx,lsm6dsm_sh_cfg_read_t * val)8452 int32_t lsm6dsm_sh_slv0_cfg_read(const stmdev_ctx_t *ctx,
8453 lsm6dsm_sh_cfg_read_t *val)
8454 {
8455 lsm6dsm_slave0_config_t slave0_config;
8456 lsm6dsm_slv0_add_t slv0_add;
8457 int32_t ret;
8458
8459 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8460
8461 if (ret == 0)
8462 {
8463 slv0_add.slave0_add = val->slv_add;
8464 slv0_add.rw_0 = 1;
8465 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV0_ADD, (uint8_t *)&slv0_add, 1);
8466
8467 if (ret == 0)
8468 {
8469 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV0_SUBADD,
8470 &(val->slv_subadd), 1);
8471
8472 if (ret == 0)
8473 {
8474 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
8475 (uint8_t *)&slave0_config, 1);
8476 slave0_config.slave0_numop = val->slv_len;
8477
8478 if (ret == 0)
8479 {
8480 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
8481 (uint8_t *)&slave0_config, 1);
8482
8483 if (ret == 0)
8484 {
8485 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8486 }
8487 }
8488 }
8489 }
8490 }
8491
8492 return ret;
8493 }
8494
8495 /**
8496 * @brief Configure slave 1 for perform a read.[get]
8497 *
8498 * @param ctx Read / write interface definitions
8499 * @param val Structure that contain:
8500 * - uint8_t slv_add; 8 bit i2c device address
8501 * - uint8_t slv_subadd; 8 bit register device address
8502 * - uint8_t slv_len; num of bit to read
8503 * @retval Interface status (MANDATORY: return 0 -> no Error).
8504 *
8505 */
lsm6dsm_sh_slv1_cfg_read(const stmdev_ctx_t * ctx,lsm6dsm_sh_cfg_read_t * val)8506 int32_t lsm6dsm_sh_slv1_cfg_read(const stmdev_ctx_t *ctx,
8507 lsm6dsm_sh_cfg_read_t *val)
8508 {
8509 lsm6dsm_slave1_config_t slave1_config;
8510 lsm6dsm_slv1_add_t slv1_add;
8511 int32_t ret;
8512
8513 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8514
8515 if (ret == 0)
8516 {
8517 slv1_add.slave1_add = val->slv_add;
8518 slv1_add.r_1 = 1;
8519 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV1_ADD, (uint8_t *)&slv1_add, 1);
8520
8521 if (ret == 0)
8522 {
8523 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV1_SUBADD,
8524 &(val->slv_subadd), 1);
8525
8526 if (ret == 0)
8527 {
8528 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
8529 (uint8_t *)&slave1_config, 1);
8530 slave1_config.slave1_numop = val->slv_len;
8531
8532 if (ret == 0)
8533 {
8534 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
8535 (uint8_t *)&slave1_config, 1);
8536
8537 if (ret == 0)
8538 {
8539 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8540 }
8541 }
8542 }
8543 }
8544 }
8545
8546 return ret;
8547 }
8548
8549 /**
8550 * @brief Configure slave 2 for perform a read.[get]
8551 *
8552 * @param ctx Read / write interface definitions
8553 * @param val Structure that contain:
8554 * - uint8_t slv_add; 8 bit i2c device address
8555 * - uint8_t slv_subadd; 8 bit register device address
8556 * - uint8_t slv_len; num of bit to read
8557 * @retval Interface status (MANDATORY: return 0 -> no Error).
8558 *
8559 */
lsm6dsm_sh_slv2_cfg_read(const stmdev_ctx_t * ctx,lsm6dsm_sh_cfg_read_t * val)8560 int32_t lsm6dsm_sh_slv2_cfg_read(const stmdev_ctx_t *ctx,
8561 lsm6dsm_sh_cfg_read_t *val)
8562 {
8563 lsm6dsm_slv2_add_t slv2_add;
8564 lsm6dsm_slave2_config_t slave2_config;
8565 int32_t ret;
8566
8567 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8568
8569 if (ret == 0)
8570 {
8571 slv2_add.slave2_add = val->slv_add;
8572 slv2_add.r_2 = 1;
8573 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV2_ADD, (uint8_t *)&slv2_add, 1);
8574
8575 if (ret == 0)
8576 {
8577 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV2_SUBADD,
8578 &(val->slv_subadd), 1);
8579
8580 if (ret == 0)
8581 {
8582 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE2_CONFIG,
8583 (uint8_t *)&slave2_config, 1);
8584
8585 if (ret == 0)
8586 {
8587 slave2_config.slave2_numop = val->slv_len;
8588 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE2_CONFIG,
8589 (uint8_t *)&slave2_config, 1);
8590
8591 if (ret == 0)
8592 {
8593 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8594 }
8595 }
8596 }
8597 }
8598 }
8599
8600 return ret;
8601 }
8602
8603 /**
8604 * @brief Configure slave 3 for perform a read.[get]
8605 *
8606 * @param ctx Read / write interface definitions
8607 * @param val Structure that contain:
8608 * - uint8_t slv_add; 8 bit i2c device address
8609 * - uint8_t slv_subadd; 8 bit register device address
8610 * - uint8_t slv_len; num of bit to read
8611 * @retval Interface status (MANDATORY: return 0 -> no Error).
8612 *
8613 */
lsm6dsm_sh_slv3_cfg_read(const stmdev_ctx_t * ctx,lsm6dsm_sh_cfg_read_t * val)8614 int32_t lsm6dsm_sh_slv3_cfg_read(const stmdev_ctx_t *ctx,
8615 lsm6dsm_sh_cfg_read_t *val)
8616 {
8617 lsm6dsm_slave3_config_t slave3_config;
8618 lsm6dsm_slv3_add_t slv3_add;
8619 int32_t ret;
8620
8621 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8622
8623 if (ret == 0)
8624 {
8625 slv3_add.slave3_add = val->slv_add;
8626 slv3_add.r_3 = 1;
8627 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV3_ADD, (uint8_t *)&slv3_add, 1);
8628
8629 if (ret == 0)
8630 {
8631 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLV3_SUBADD,
8632 (uint8_t *) & (val->slv_subadd), 1);
8633
8634 if (ret == 0)
8635 {
8636 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE3_CONFIG,
8637 (uint8_t *)&slave3_config, 1);
8638
8639 if (ret == 0)
8640 {
8641 slave3_config.slave3_numop = val->slv_len;
8642 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE3_CONFIG,
8643 (uint8_t *)&slave3_config, 1);
8644
8645 if (ret == 0)
8646 {
8647 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8648 }
8649 }
8650 }
8651 }
8652 }
8653
8654 return ret;
8655 }
8656
8657 /**
8658 * @brief Decimation of read operation on Slave 0 starting from the
8659 * sensor hub trigger.[set]
8660 *
8661 * @param ctx Read / write interface definitions
8662 * @param val Change the values of slave0_rate in reg SLAVE0_CONFIG
8663 * @retval Interface status (MANDATORY: return 0 -> no Error).
8664 *
8665 */
lsm6dsm_sh_slave_0_dec_set(const stmdev_ctx_t * ctx,lsm6dsm_slave0_rate_t val)8666 int32_t lsm6dsm_sh_slave_0_dec_set(const stmdev_ctx_t *ctx,
8667 lsm6dsm_slave0_rate_t val)
8668 {
8669 lsm6dsm_slave0_config_t slave0_config;
8670 int32_t ret;
8671
8672 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8673
8674 if (ret == 0)
8675 {
8676 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
8677 (uint8_t *)&slave0_config, 1);
8678
8679 if (ret == 0)
8680 {
8681 slave0_config.slave0_rate = (uint8_t) val;
8682 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
8683 (uint8_t *)&slave0_config, 1);
8684
8685 if (ret == 0)
8686 {
8687 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8688 }
8689 }
8690 }
8691
8692 return ret;
8693 }
8694
8695 /**
8696 * @brief Decimation of read operation on Slave 0 starting from the
8697 * sensor hub trigger.[get]
8698 *
8699 * @param ctx Read / write interface definitions
8700 * @param val Get the values of slave0_rate in reg SLAVE0_CONFIG
8701 * @retval Interface status (MANDATORY: return 0 -> no Error).
8702 *
8703 */
lsm6dsm_sh_slave_0_dec_get(const stmdev_ctx_t * ctx,lsm6dsm_slave0_rate_t * val)8704 int32_t lsm6dsm_sh_slave_0_dec_get(const stmdev_ctx_t *ctx,
8705 lsm6dsm_slave0_rate_t *val)
8706 {
8707 lsm6dsm_slave0_config_t slave0_config;
8708 int32_t ret;
8709
8710 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8711
8712 if (ret == 0)
8713 {
8714 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE0_CONFIG,
8715 (uint8_t *)&slave0_config, 1);
8716
8717 if (ret == 0)
8718 {
8719 switch (slave0_config.slave0_rate)
8720 {
8721 case LSM6DSM_SL0_NO_DEC:
8722 *val = LSM6DSM_SL0_NO_DEC;
8723 break;
8724
8725 case LSM6DSM_SL0_DEC_2:
8726 *val = LSM6DSM_SL0_DEC_2;
8727 break;
8728
8729 case LSM6DSM_SL0_DEC_4:
8730 *val = LSM6DSM_SL0_DEC_4;
8731 break;
8732
8733 case LSM6DSM_SL0_DEC_8:
8734 *val = LSM6DSM_SL0_DEC_8;
8735 break;
8736
8737 default:
8738 *val = LSM6DSM_SL0_NO_DEC;
8739 break;
8740 }
8741
8742 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8743 }
8744 }
8745
8746 return ret;
8747 }
8748
8749 /**
8750 * @brief Slave 0 write operation is performed only at the first sensor
8751 * hub cycle.
8752 * This is effective if the Aux_sens_on[1:0] field in
8753 * SLAVE0_CONFIG(04h) is set to a value other than 00.[set]
8754 *
8755 * @param ctx Read / write interface definitions
8756 * @param val Change the values of write_once in reg SLAVE1_CONFIG
8757 * @retval Interface status (MANDATORY: return 0 -> no Error).
8758 *
8759 */
lsm6dsm_sh_write_mode_set(const stmdev_ctx_t * ctx,lsm6dsm_write_once_t val)8760 int32_t lsm6dsm_sh_write_mode_set(const stmdev_ctx_t *ctx,
8761 lsm6dsm_write_once_t val)
8762 {
8763 lsm6dsm_slave1_config_t slave1_config;
8764 int32_t ret;
8765
8766 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8767
8768 if (ret == 0)
8769 {
8770 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
8771 (uint8_t *)&slave1_config, 1);
8772 slave1_config.write_once = (uint8_t) val;
8773
8774 if (ret == 0)
8775 {
8776 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
8777 (uint8_t *)&slave1_config, 1);
8778
8779 if (ret == 0)
8780 {
8781 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8782 }
8783 }
8784 }
8785
8786 return ret;
8787 }
8788
8789 /**
8790 * @brief Slave 0 write operation is performed only at the first sensor
8791 * hub cycle.
8792 * This is effective if the Aux_sens_on[1:0] field in
8793 * SLAVE0_CONFIG(04h) is set to a value other than 00.[get]
8794 *
8795 * @param ctx Read / write interface definitions
8796 * @param val Get the values of write_once in reg SLAVE1_CONFIG
8797 * @retval Interface status (MANDATORY: return 0 -> no Error).
8798 *
8799 */
lsm6dsm_sh_write_mode_get(const stmdev_ctx_t * ctx,lsm6dsm_write_once_t * val)8800 int32_t lsm6dsm_sh_write_mode_get(const stmdev_ctx_t *ctx,
8801 lsm6dsm_write_once_t *val)
8802 {
8803 lsm6dsm_slave1_config_t slave1_config;
8804 int32_t ret;
8805
8806 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8807
8808 if (ret == 0)
8809 {
8810 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
8811 (uint8_t *)&slave1_config, 1);
8812
8813 if (ret == 0)
8814 {
8815 switch (slave1_config.write_once)
8816 {
8817 case LSM6DSM_EACH_SH_CYCLE:
8818 *val = LSM6DSM_EACH_SH_CYCLE;
8819 break;
8820
8821 case LSM6DSM_ONLY_FIRST_CYCLE:
8822 *val = LSM6DSM_ONLY_FIRST_CYCLE;
8823 break;
8824
8825 default:
8826 *val = LSM6DSM_EACH_SH_CYCLE;
8827 break;
8828 }
8829
8830 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8831 }
8832 }
8833
8834 return ret;
8835 }
8836
8837 /**
8838 * @brief Decimation of read operation on Slave 1 starting from the
8839 * sensor hub trigger.[set]
8840 *
8841 * @param ctx Read / write interface definitions
8842 * @param val Change the values of slave1_rate in reg SLAVE1_CONFIG
8843 * @retval Interface status (MANDATORY: return 0 -> no Error).
8844 *
8845 */
lsm6dsm_sh_slave_1_dec_set(const stmdev_ctx_t * ctx,lsm6dsm_slave1_rate_t val)8846 int32_t lsm6dsm_sh_slave_1_dec_set(const stmdev_ctx_t *ctx,
8847 lsm6dsm_slave1_rate_t val)
8848 {
8849 lsm6dsm_slave1_config_t slave1_config;
8850 int32_t ret;
8851
8852 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8853
8854 if (ret == 0)
8855 {
8856 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
8857 (uint8_t *)&slave1_config, 1);
8858
8859 if (ret == 0)
8860 {
8861 slave1_config.slave1_rate = (uint8_t) val;
8862 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
8863 (uint8_t *)&slave1_config, 1);
8864
8865 if (ret == 0)
8866 {
8867 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8868 }
8869 }
8870 }
8871
8872 return ret;
8873 }
8874
8875 /**
8876 * @brief Decimation of read operation on Slave 1 starting from the
8877 * sensor hub trigger.[get]
8878 *
8879 * @param ctx Read / write interface definitions reg SLAVE1_CONFIG
8880 * @retval Interface status (MANDATORY: return 0 -> no Error).
8881 *
8882 */
lsm6dsm_sh_slave_1_dec_get(const stmdev_ctx_t * ctx,lsm6dsm_slave1_rate_t * val)8883 int32_t lsm6dsm_sh_slave_1_dec_get(const stmdev_ctx_t *ctx,
8884 lsm6dsm_slave1_rate_t *val)
8885 {
8886 lsm6dsm_slave1_config_t slave1_config;
8887 int32_t ret;
8888
8889 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8890
8891 if (ret == 0)
8892 {
8893 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE1_CONFIG,
8894 (uint8_t *)&slave1_config, 1);
8895
8896 if (ret == 0)
8897 {
8898 switch (slave1_config.slave1_rate)
8899 {
8900 case LSM6DSM_SL1_NO_DEC:
8901 *val = LSM6DSM_SL1_NO_DEC;
8902 break;
8903
8904 case LSM6DSM_SL1_DEC_2:
8905 *val = LSM6DSM_SL1_DEC_2;
8906 break;
8907
8908 case LSM6DSM_SL1_DEC_4:
8909 *val = LSM6DSM_SL1_DEC_4;
8910 break;
8911
8912 case LSM6DSM_SL1_DEC_8:
8913 *val = LSM6DSM_SL1_DEC_8;
8914 break;
8915
8916 default:
8917 *val = LSM6DSM_SL1_NO_DEC;
8918 break;
8919 }
8920
8921 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8922 }
8923 }
8924
8925 return ret;
8926 }
8927
8928 /**
8929 * @brief Decimation of read operation on Slave 2 starting from the
8930 * sensor hub trigger.[set]
8931 *
8932 * @param ctx Read / write interface definitions
8933 * @param val Change the values of slave2_rate in reg SLAVE2_CONFIG
8934 * @retval Interface status (MANDATORY: return 0 -> no Error).
8935 *
8936 */
lsm6dsm_sh_slave_2_dec_set(const stmdev_ctx_t * ctx,lsm6dsm_slave2_rate_t val)8937 int32_t lsm6dsm_sh_slave_2_dec_set(const stmdev_ctx_t *ctx,
8938 lsm6dsm_slave2_rate_t val)
8939 {
8940 lsm6dsm_slave2_config_t slave2_config;
8941 int32_t ret;
8942
8943 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8944
8945 if (ret == 0)
8946 {
8947 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE2_CONFIG,
8948 (uint8_t *)&slave2_config, 1);
8949
8950 if (ret == 0)
8951 {
8952 slave2_config.slave2_rate = (uint8_t) val;
8953 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE2_CONFIG,
8954 (uint8_t *)&slave2_config, 1);
8955
8956 if (ret == 0)
8957 {
8958 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
8959 }
8960 }
8961 }
8962
8963 return ret;
8964 }
8965
8966 /**
8967 * @brief Decimation of read operation on Slave 2 starting from the
8968 * sensor hub trigger.[get]
8969 *
8970 * @param ctx Read / write interface definitions
8971 * @param val Get the values of slave2_rate in reg SLAVE2_CONFIG
8972 * @retval Interface status (MANDATORY: return 0 -> no Error).
8973 *
8974 */
lsm6dsm_sh_slave_2_dec_get(const stmdev_ctx_t * ctx,lsm6dsm_slave2_rate_t * val)8975 int32_t lsm6dsm_sh_slave_2_dec_get(const stmdev_ctx_t *ctx,
8976 lsm6dsm_slave2_rate_t *val)
8977 {
8978 lsm6dsm_slave2_config_t slave2_config;
8979 int32_t ret;
8980
8981 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
8982
8983 if (ret == 0)
8984 {
8985 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE2_CONFIG,
8986 (uint8_t *)&slave2_config, 1);
8987
8988 if (ret == 0)
8989 {
8990 switch (slave2_config.slave2_rate)
8991 {
8992 case LSM6DSM_SL2_NO_DEC:
8993 *val = LSM6DSM_SL2_NO_DEC;
8994 break;
8995
8996 case LSM6DSM_SL2_DEC_2:
8997 *val = LSM6DSM_SL2_DEC_2;
8998 break;
8999
9000 case LSM6DSM_SL2_DEC_4:
9001 *val = LSM6DSM_SL2_DEC_4;
9002 break;
9003
9004 case LSM6DSM_SL2_DEC_8:
9005 *val = LSM6DSM_SL2_DEC_8;
9006 break;
9007
9008 default:
9009 *val = LSM6DSM_SL2_NO_DEC;
9010 break;
9011 }
9012
9013 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
9014 }
9015 }
9016
9017 return ret;
9018 }
9019
9020 /**
9021 * @brief Decimation of read operation on Slave 3 starting from the
9022 * sensor hub trigger.[set]
9023 *
9024 * @param ctx Read / write interface definitions
9025 * @param val Change the values of slave3_rate in reg SLAVE3_CONFIG
9026 * @retval Interface status (MANDATORY: return 0 -> no Error).
9027 *
9028 */
lsm6dsm_sh_slave_3_dec_set(const stmdev_ctx_t * ctx,lsm6dsm_slave3_rate_t val)9029 int32_t lsm6dsm_sh_slave_3_dec_set(const stmdev_ctx_t *ctx,
9030 lsm6dsm_slave3_rate_t val)
9031 {
9032 lsm6dsm_slave3_config_t slave3_config;
9033 int32_t ret;
9034
9035 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
9036
9037 if (ret == 0)
9038 {
9039 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE3_CONFIG,
9040 (uint8_t *)&slave3_config, 1);
9041 slave3_config.slave3_rate = (uint8_t)val;
9042
9043 if (ret == 0)
9044 {
9045 ret = lsm6dsm_write_reg(ctx, LSM6DSM_SLAVE3_CONFIG,
9046 (uint8_t *)&slave3_config, 1);
9047
9048 if (ret == 0)
9049 {
9050 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
9051 }
9052 }
9053 }
9054
9055 return ret;
9056 }
9057
9058 /**
9059 * @brief Decimation of read operation on Slave 3 starting from the
9060 * sensor hub trigger.[get]
9061 *
9062 * @param ctx Read / write interface definitions
9063 * @param val Get the values of slave3_rate in reg SLAVE3_CONFIG.
9064 * @retval Interface status (MANDATORY: return 0 -> no Error).
9065 *
9066 */
lsm6dsm_sh_slave_3_dec_get(const stmdev_ctx_t * ctx,lsm6dsm_slave3_rate_t * val)9067 int32_t lsm6dsm_sh_slave_3_dec_get(const stmdev_ctx_t *ctx,
9068 lsm6dsm_slave3_rate_t *val)
9069 {
9070 lsm6dsm_slave3_config_t slave3_config;
9071 int32_t ret;
9072
9073 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_BANK_A);
9074
9075 if (ret == 0)
9076 {
9077 ret = lsm6dsm_read_reg(ctx, LSM6DSM_SLAVE3_CONFIG,
9078 (uint8_t *)&slave3_config, 1);
9079
9080 if (ret == 0)
9081 {
9082 switch (slave3_config.slave3_rate)
9083 {
9084 case LSM6DSM_SL3_NO_DEC:
9085 *val = LSM6DSM_SL3_NO_DEC;
9086 break;
9087
9088 case LSM6DSM_SL3_DEC_2:
9089 *val = LSM6DSM_SL3_DEC_2;
9090 break;
9091
9092 case LSM6DSM_SL3_DEC_4:
9093 *val = LSM6DSM_SL3_DEC_4;
9094 break;
9095
9096 case LSM6DSM_SL3_DEC_8:
9097 *val = LSM6DSM_SL3_DEC_8;
9098 break;
9099
9100 default:
9101 *val = LSM6DSM_SL3_NO_DEC;
9102 break;
9103 }
9104
9105 ret = lsm6dsm_mem_bank_set(ctx, LSM6DSM_USER_BANK);
9106 }
9107 }
9108
9109 return ret;
9110 }
9111
9112 /**
9113 * @}
9114 *
9115 */
9116
9117 /**
9118 * @}
9119 *
9120 */
9121
9122 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
9123
