1 /**
2 ******************************************************************************
3 * @file lsm6dsl_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DSL driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6dsl_reg.h"
21
22 /**
23 * @defgroup LSM6DSL
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6dsl enanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LSM6DSL_interfaces_functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6dsl_read_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6dsl_read_reg(stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 ret = ctx->read_reg(ctx->handle, reg, data, len);
56
57 return ret;
58 }
59
60 /**
61 * @brief Write generic device register
62 *
63 * @param ctx read / write interface definitions(ptr)
64 * @param reg register to write
65 * @param data pointer to data to write in register reg(ptr)
66 * @param len number of consecutive register to write
67 * @retval interface status (MANDATORY: return 0 -> no Error)
68 *
69 */
lsm6dsl_write_reg(stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)70 int32_t __weak lsm6dsl_write_reg(stmdev_ctx_t *ctx, uint8_t reg,
71 uint8_t *data,
72 uint16_t len)
73 {
74 int32_t ret;
75
76 ret = ctx->write_reg(ctx->handle, reg, data, len);
77
78 return ret;
79 }
80
81 /**
82 * @}
83 *
84 */
85
86 /**
87 * @defgroup LSM6DSL_Sensitivity
88 * @brief These functions convert raw-data into engineering units.
89 * @{
90 *
91 */
92
lsm6dsl_from_fs2g_to_mg(int16_t lsb)93 float_t lsm6dsl_from_fs2g_to_mg(int16_t lsb)
94 {
95 return ((float_t)lsb * 0.061f);
96 }
97
lsm6dsl_from_fs4g_to_mg(int16_t lsb)98 float_t lsm6dsl_from_fs4g_to_mg(int16_t lsb)
99 {
100 return ((float_t)lsb * 0.122f);
101 }
102
lsm6dsl_from_fs8g_to_mg(int16_t lsb)103 float_t lsm6dsl_from_fs8g_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb * 0.244f);
106 }
107
lsm6dsl_from_fs16g_to_mg(int16_t lsb)108 float_t lsm6dsl_from_fs16g_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb * 0.488f);
111 }
112
lsm6dsl_from_fs125dps_to_mdps(int16_t lsb)113 float_t lsm6dsl_from_fs125dps_to_mdps(int16_t lsb)
114 {
115 return ((float_t)lsb * 4.375f);
116 }
117
lsm6dsl_from_fs250dps_to_mdps(int16_t lsb)118 float_t lsm6dsl_from_fs250dps_to_mdps(int16_t lsb)
119 {
120 return ((float_t)lsb * 8.750f);
121 }
122
lsm6dsl_from_fs500dps_to_mdps(int16_t lsb)123 float_t lsm6dsl_from_fs500dps_to_mdps(int16_t lsb)
124 {
125 return ((float_t)lsb * 17.50f);
126 }
127
lsm6dsl_from_fs1000dps_to_mdps(int16_t lsb)128 float_t lsm6dsl_from_fs1000dps_to_mdps(int16_t lsb)
129 {
130 return ((float_t)lsb * 35.0f);
131 }
132
lsm6dsl_from_fs2000dps_to_mdps(int16_t lsb)133 float_t lsm6dsl_from_fs2000dps_to_mdps(int16_t lsb)
134 {
135 return ((float_t)lsb * 70.0f);
136 }
137
lsm6dsl_from_lsb_to_celsius(int16_t lsb)138 float_t lsm6dsl_from_lsb_to_celsius(int16_t lsb)
139 {
140 return (((float_t)lsb / 256.0f) + 25.0f);
141 }
142
143 /**
144 * @}
145 *
146 */
147
148
149 /**
150 * @defgroup LSM6DSL_data_generation
151 * @brief This section groups all the functions concerning data
152 * generation
153 * @{
154 *
155 */
156
157 /**
158 * @brief Accelerometer full-scale selection.[set]
159 *
160 * @param ctx Read / write interface definitions
161 * @param val Change the values of fs_xl in reg CTRL1_XL
162 * @retval Interface status (MANDATORY: return 0 -> no Error).
163 *
164 */
lsm6dsl_xl_full_scale_set(stmdev_ctx_t * ctx,lsm6dsl_fs_xl_t val)165 int32_t lsm6dsl_xl_full_scale_set(stmdev_ctx_t *ctx,
166 lsm6dsl_fs_xl_t val)
167 {
168 lsm6dsl_ctrl1_xl_t ctrl1_xl;
169 int32_t ret;
170
171 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
172
173 if (ret == 0)
174 {
175 ctrl1_xl.fs_xl = (uint8_t) val;
176 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
177 }
178
179 return ret;
180 }
181
182 /**
183 * @brief Accelerometer full-scale selection.[get]
184 *
185 * @param ctx Read / write interface definitions
186 * @param val Get the values of fs_xl in reg CTRL1_XL
187 * @retval Interface status (MANDATORY: return 0 -> no Error).
188 *
189 */
lsm6dsl_xl_full_scale_get(stmdev_ctx_t * ctx,lsm6dsl_fs_xl_t * val)190 int32_t lsm6dsl_xl_full_scale_get(stmdev_ctx_t *ctx,
191 lsm6dsl_fs_xl_t *val)
192 {
193 lsm6dsl_ctrl1_xl_t ctrl1_xl;
194 int32_t ret;
195
196 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
197
198 switch (ctrl1_xl.fs_xl)
199 {
200 case LSM6DSL_2g:
201 *val = LSM6DSL_2g;
202 break;
203
204 case LSM6DSL_16g:
205 *val = LSM6DSL_16g;
206 break;
207
208 case LSM6DSL_4g:
209 *val = LSM6DSL_4g;
210 break;
211
212 case LSM6DSL_8g:
213 *val = LSM6DSL_8g;
214 break;
215
216 default:
217 *val = LSM6DSL_XL_FS_ND;
218 break;
219 }
220
221 return ret;
222 }
223
224 /**
225 * @brief Accelerometer data rate selection.[set]
226 *
227 * @param ctx Read / write interface definitions
228 * @param val Change the values of odr_xl in reg CTRL1_XL
229 * @retval Interface status (MANDATORY: return 0 -> no Error).
230 *
231 */
lsm6dsl_xl_data_rate_set(stmdev_ctx_t * ctx,lsm6dsl_odr_xl_t val)232 int32_t lsm6dsl_xl_data_rate_set(stmdev_ctx_t *ctx,
233 lsm6dsl_odr_xl_t val)
234 {
235 lsm6dsl_ctrl1_xl_t ctrl1_xl;
236 int32_t ret;
237
238 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
239
240 if (ret == 0)
241 {
242 ctrl1_xl.odr_xl = (uint8_t) val;
243 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
244 }
245
246 return ret;
247 }
248
249 /**
250 * @brief Accelerometer data rate selection.[get]
251 *
252 * @param ctx Read / write interface definitions
253 * @param val Get the values of odr_xl in reg CTRL1_XL
254 * @retval Interface status (MANDATORY: return 0 -> no Error).
255 *
256 */
lsm6dsl_xl_data_rate_get(stmdev_ctx_t * ctx,lsm6dsl_odr_xl_t * val)257 int32_t lsm6dsl_xl_data_rate_get(stmdev_ctx_t *ctx,
258 lsm6dsl_odr_xl_t *val)
259 {
260 lsm6dsl_ctrl1_xl_t ctrl1_xl;
261 int32_t ret;
262
263 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
264
265 switch (ctrl1_xl.odr_xl)
266 {
267 case LSM6DSL_XL_ODR_OFF:
268 *val = LSM6DSL_XL_ODR_OFF;
269 break;
270
271 case LSM6DSL_XL_ODR_12Hz5:
272 *val = LSM6DSL_XL_ODR_12Hz5;
273 break;
274
275 case LSM6DSL_XL_ODR_26Hz:
276 *val = LSM6DSL_XL_ODR_26Hz;
277 break;
278
279 case LSM6DSL_XL_ODR_52Hz:
280 *val = LSM6DSL_XL_ODR_52Hz;
281 break;
282
283 case LSM6DSL_XL_ODR_104Hz:
284 *val = LSM6DSL_XL_ODR_104Hz;
285 break;
286
287 case LSM6DSL_XL_ODR_208Hz:
288 *val = LSM6DSL_XL_ODR_208Hz;
289 break;
290
291 case LSM6DSL_XL_ODR_416Hz:
292 *val = LSM6DSL_XL_ODR_416Hz;
293 break;
294
295 case LSM6DSL_XL_ODR_833Hz:
296 *val = LSM6DSL_XL_ODR_833Hz;
297 break;
298
299 case LSM6DSL_XL_ODR_1k66Hz:
300 *val = LSM6DSL_XL_ODR_1k66Hz;
301 break;
302
303 case LSM6DSL_XL_ODR_3k33Hz:
304 *val = LSM6DSL_XL_ODR_3k33Hz;
305 break;
306
307 case LSM6DSL_XL_ODR_6k66Hz:
308 *val = LSM6DSL_XL_ODR_6k66Hz;
309 break;
310
311 case LSM6DSL_XL_ODR_1Hz6:
312 *val = LSM6DSL_XL_ODR_1Hz6;
313 break;
314
315 default:
316 *val = LSM6DSL_XL_ODR_ND;
317 break;
318 }
319
320 return ret;
321 }
322
323 /**
324 * @brief Gyroscope chain full-scale selection.[set]
325 *
326 * @param ctx Read / write interface definitions
327 * @param val Change the values of fs_g in reg CTRL2_G
328 * @retval Interface status (MANDATORY: return 0 -> no Error).
329 *
330 */
lsm6dsl_gy_full_scale_set(stmdev_ctx_t * ctx,lsm6dsl_fs_g_t val)331 int32_t lsm6dsl_gy_full_scale_set(stmdev_ctx_t *ctx,
332 lsm6dsl_fs_g_t val)
333 {
334 lsm6dsl_ctrl2_g_t ctrl2_g;
335 int32_t ret;
336
337 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
338
339 if (ret == 0)
340 {
341 ctrl2_g.fs_g = (uint8_t) val;
342 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
343 }
344
345 return ret;
346 }
347
348 /**
349 * @brief Gyroscope chain full-scale selection.[get]
350 *
351 * @param ctx Read / write interface definitions
352 * @param val Get the values of fs_g in reg CTRL2_G
353 * @retval Interface status (MANDATORY: return 0 -> no Error).
354 *
355 */
lsm6dsl_gy_full_scale_get(stmdev_ctx_t * ctx,lsm6dsl_fs_g_t * val)356 int32_t lsm6dsl_gy_full_scale_get(stmdev_ctx_t *ctx,
357 lsm6dsl_fs_g_t *val)
358 {
359 lsm6dsl_ctrl2_g_t ctrl2_g;
360 int32_t ret;
361
362 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
363
364 switch (ctrl2_g.fs_g)
365 {
366 case LSM6DSL_250dps:
367 *val = LSM6DSL_250dps;
368 break;
369
370 case LSM6DSL_125dps:
371 *val = LSM6DSL_125dps;
372 break;
373
374 case LSM6DSL_500dps:
375 *val = LSM6DSL_500dps;
376 break;
377
378 case LSM6DSL_1000dps:
379 *val = LSM6DSL_1000dps;
380 break;
381
382 case LSM6DSL_2000dps:
383 *val = LSM6DSL_2000dps;
384 break;
385
386 default:
387 *val = LSM6DSL_GY_FS_ND;
388 break;
389 }
390
391 return ret;
392 }
393
394 /**
395 * @brief Gyroscope data rate selection.[set]
396 *
397 * @param ctx Read / write interface definitions
398 * @param val Change the values of odr_g in reg CTRL2_G
399 * @retval Interface status (MANDATORY: return 0 -> no Error).
400 *
401 */
lsm6dsl_gy_data_rate_set(stmdev_ctx_t * ctx,lsm6dsl_odr_g_t val)402 int32_t lsm6dsl_gy_data_rate_set(stmdev_ctx_t *ctx,
403 lsm6dsl_odr_g_t val)
404 {
405 lsm6dsl_ctrl2_g_t ctrl2_g;
406 int32_t ret;
407
408 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
409
410 if (ret == 0)
411 {
412 ctrl2_g.odr_g = (uint8_t) val;
413 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
414 }
415
416 return ret;
417 }
418
419 /**
420 * @brief Gyroscope data rate selection.[get]
421 *
422 * @param ctx Read / write interface definitions
423 * @param val Get the values of odr_g in reg CTRL2_G
424 * @retval Interface status (MANDATORY: return 0 -> no Error).
425 *
426 */
lsm6dsl_gy_data_rate_get(stmdev_ctx_t * ctx,lsm6dsl_odr_g_t * val)427 int32_t lsm6dsl_gy_data_rate_get(stmdev_ctx_t *ctx,
428 lsm6dsl_odr_g_t *val)
429 {
430 lsm6dsl_ctrl2_g_t ctrl2_g;
431 int32_t ret;
432
433 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL2_G, (uint8_t *)&ctrl2_g, 1);
434
435 switch (ctrl2_g.odr_g)
436 {
437 case LSM6DSL_GY_ODR_OFF:
438 *val = LSM6DSL_GY_ODR_OFF;
439 break;
440
441 case LSM6DSL_GY_ODR_12Hz5:
442 *val = LSM6DSL_GY_ODR_12Hz5;
443 break;
444
445 case LSM6DSL_GY_ODR_26Hz:
446 *val = LSM6DSL_GY_ODR_26Hz;
447 break;
448
449 case LSM6DSL_GY_ODR_52Hz:
450 *val = LSM6DSL_GY_ODR_52Hz;
451 break;
452
453 case LSM6DSL_GY_ODR_104Hz:
454 *val = LSM6DSL_GY_ODR_104Hz;
455 break;
456
457 case LSM6DSL_GY_ODR_208Hz:
458 *val = LSM6DSL_GY_ODR_208Hz;
459 break;
460
461 case LSM6DSL_GY_ODR_416Hz:
462 *val = LSM6DSL_GY_ODR_416Hz;
463 break;
464
465 case LSM6DSL_GY_ODR_833Hz:
466 *val = LSM6DSL_GY_ODR_833Hz;
467 break;
468
469 case LSM6DSL_GY_ODR_1k66Hz:
470 *val = LSM6DSL_GY_ODR_1k66Hz;
471 break;
472
473 case LSM6DSL_GY_ODR_3k33Hz:
474 *val = LSM6DSL_GY_ODR_3k33Hz;
475 break;
476
477 case LSM6DSL_GY_ODR_6k66Hz:
478 *val = LSM6DSL_GY_ODR_6k66Hz;
479 break;
480
481 default:
482 *val = LSM6DSL_GY_ODR_ND;
483 break;
484 }
485
486 return ret;
487 }
488
489 /**
490 * @brief Block data update.[set]
491 *
492 * @param ctx Read / write interface definitions
493 * @param val Change the values of bdu in reg CTRL3_C
494 * @retval Interface status (MANDATORY: return 0 -> no Error).
495 *
496 */
lsm6dsl_block_data_update_set(stmdev_ctx_t * ctx,uint8_t val)497 int32_t lsm6dsl_block_data_update_set(stmdev_ctx_t *ctx, uint8_t val)
498 {
499 lsm6dsl_ctrl3_c_t ctrl3_c;
500 int32_t ret;
501
502 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
503
504 if (ret == 0)
505 {
506 ctrl3_c.bdu = val;
507 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
508 }
509
510 return ret;
511 }
512
513 /**
514 * @brief Block data update.[get]
515 *
516 * @param ctx Read / write interface definitions
517 * @param val Change the values of bdu in reg CTRL3_C
518 * @retval Interface status (MANDATORY: return 0 -> no Error).
519 *
520 */
lsm6dsl_block_data_update_get(stmdev_ctx_t * ctx,uint8_t * val)521 int32_t lsm6dsl_block_data_update_get(stmdev_ctx_t *ctx, uint8_t *val)
522 {
523 lsm6dsl_ctrl3_c_t ctrl3_c;
524 int32_t ret;
525
526 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
527 *val = ctrl3_c.bdu;
528
529 return ret;
530 }
531
532 /**
533 * @brief Weight of XL user offset bits of registers
534 * X_OFS_USR(73h), Y_OFS_USR(74h), Z_OFS_USR(75h).[set]
535 *
536 * @param ctx Read / write interface definitions
537 * @param val Change the values of usr_off_w in reg CTRL6_C
538 * @retval Interface status (MANDATORY: return 0 -> no Error).
539 *
540 */
lsm6dsl_xl_offset_weight_set(stmdev_ctx_t * ctx,lsm6dsl_usr_off_w_t val)541 int32_t lsm6dsl_xl_offset_weight_set(stmdev_ctx_t *ctx,
542 lsm6dsl_usr_off_w_t val)
543 {
544 lsm6dsl_ctrl6_c_t ctrl6_c;
545 int32_t ret;
546
547 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
548
549 if (ret == 0)
550 {
551 ctrl6_c.usr_off_w = (uint8_t) val;
552 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
553 }
554
555 return ret;
556 }
557
558 /**
559 * @brief Weight of XL user offset bits of registers
560 * X_OFS_USR(73h), Y_OFS_USR(74h), Z_OFS_USR(75h).[get]
561 *
562 * @param ctx Read / write interface definitions
563 * @param val Get the values of usr_off_w in reg CTRL6_C
564 * @retval Interface status (MANDATORY: return 0 -> no Error).
565 *
566 */
lsm6dsl_xl_offset_weight_get(stmdev_ctx_t * ctx,lsm6dsl_usr_off_w_t * val)567 int32_t lsm6dsl_xl_offset_weight_get(stmdev_ctx_t *ctx,
568 lsm6dsl_usr_off_w_t *val)
569 {
570 lsm6dsl_ctrl6_c_t ctrl6_c;
571 int32_t ret;
572
573 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
574
575 switch (ctrl6_c.usr_off_w)
576 {
577 case LSM6DSL_LSb_1mg:
578 *val = LSM6DSL_LSb_1mg;
579 break;
580
581 case LSM6DSL_LSb_16mg:
582 *val = LSM6DSL_LSb_16mg;
583 break;
584
585 default:
586 *val = LSM6DSL_WEIGHT_ND;
587 break;
588 }
589
590 return ret;
591 }
592
593 /**
594 * @brief High-performance operating mode for accelerometer[set]
595 *
596 * @param ctx Read / write interface definitions
597 * @param val Change the values of xl_hm_mode in reg CTRL6_C
598 * @retval Interface status (MANDATORY: return 0 -> no Error).
599 *
600 */
lsm6dsl_xl_power_mode_set(stmdev_ctx_t * ctx,lsm6dsl_xl_hm_mode_t val)601 int32_t lsm6dsl_xl_power_mode_set(stmdev_ctx_t *ctx,
602 lsm6dsl_xl_hm_mode_t val)
603 {
604 lsm6dsl_ctrl6_c_t ctrl6_c;
605 int32_t ret;
606
607 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
608
609 if (ret == 0)
610 {
611 ctrl6_c.xl_hm_mode = (uint8_t) val;
612 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
613 }
614
615 return ret;
616 }
617
618 /**
619 * @brief High-performance operating mode for accelerometer.[get]
620 *
621 * @param ctx Read / write interface definitions
622 * @param val Get the values of xl_hm_mode in reg CTRL6_C
623 * @retval Interface status (MANDATORY: return 0 -> no Error).
624 *
625 */
lsm6dsl_xl_power_mode_get(stmdev_ctx_t * ctx,lsm6dsl_xl_hm_mode_t * val)626 int32_t lsm6dsl_xl_power_mode_get(stmdev_ctx_t *ctx,
627 lsm6dsl_xl_hm_mode_t *val)
628 {
629 lsm6dsl_ctrl6_c_t ctrl6_c;
630 int32_t ret;
631
632 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
633
634 switch (ctrl6_c.xl_hm_mode)
635 {
636 case LSM6DSL_XL_HIGH_PERFORMANCE:
637 *val = LSM6DSL_XL_HIGH_PERFORMANCE;
638 break;
639
640 case LSM6DSL_XL_NORMAL:
641 *val = LSM6DSL_XL_NORMAL;
642 break;
643
644 default:
645 *val = LSM6DSL_XL_PW_MODE_ND;
646 break;
647 }
648
649 return ret;
650 }
651
652 /**
653 * @brief Source register rounding function on WAKE_UP_SRC (1Bh),
654 * TAP_SRC (1Ch), D6D_SRC (1Dh), STATUS_REG (1Eh) and
655 * FUNC_SRC1 (53h) registers in the primary interface.[set]
656 *
657 * @param ctx Read / write interface definitions
658 * @param val Change the values of rounding_status in reg CTRL7_G
659 * @retval Interface status (MANDATORY: return 0 -> no Error).
660 *
661 */
lsm6dsl_rounding_on_status_set(stmdev_ctx_t * ctx,lsm6dsl_rounding_status_t val)662 int32_t lsm6dsl_rounding_on_status_set(stmdev_ctx_t *ctx,
663 lsm6dsl_rounding_status_t val)
664 {
665 lsm6dsl_ctrl7_g_t ctrl7_g;
666 int32_t ret;
667
668 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
669
670 if (ret == 0)
671 {
672 ctrl7_g.rounding_status = (uint8_t) val;
673 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
674 }
675
676 return ret;
677 }
678
679 /**
680 * @brief Source register rounding function on WAKE_UP_SRC (1Bh),
681 * TAP_SRC (1Ch), D6D_SRC (1Dh), STATUS_REG (1Eh) and
682 * FUNC_SRC1 (53h) registers in the primary interface.[get]
683 *
684 * @param ctx Read / write interface definitions
685 * @param val Get the values of rounding_status in reg CTRL7_G
686 * @retval Interface status (MANDATORY: return 0 -> no Error).
687 *
688 */
lsm6dsl_rounding_on_status_get(stmdev_ctx_t * ctx,lsm6dsl_rounding_status_t * val)689 int32_t lsm6dsl_rounding_on_status_get(stmdev_ctx_t *ctx,
690 lsm6dsl_rounding_status_t *val)
691 {
692 lsm6dsl_ctrl7_g_t ctrl7_g;
693 int32_t ret;
694
695 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
696
697 switch (ctrl7_g.rounding_status)
698 {
699 case LSM6DSL_STAT_RND_DISABLE:
700 *val = LSM6DSL_STAT_RND_DISABLE;
701 break;
702
703 case LSM6DSL_STAT_RND_ENABLE:
704 *val = LSM6DSL_STAT_RND_ENABLE;
705 break;
706
707 default:
708 *val = LSM6DSL_STAT_RND_ND;
709 break;
710 }
711
712 return ret;
713 }
714
715 /**
716 * @brief High-performance operating mode disable for gyroscope.[set]
717 *
718 * @param ctx Read / write interface definitions
719 * @param val Change the values of g_hm_mode in reg CTRL7_G
720 * @retval Interface status (MANDATORY: return 0 -> no Error).
721 *
722 */
lsm6dsl_gy_power_mode_set(stmdev_ctx_t * ctx,lsm6dsl_g_hm_mode_t val)723 int32_t lsm6dsl_gy_power_mode_set(stmdev_ctx_t *ctx,
724 lsm6dsl_g_hm_mode_t val)
725 {
726 lsm6dsl_ctrl7_g_t ctrl7_g;
727 int32_t ret;
728
729 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
730
731 if (ret == 0)
732 {
733 ctrl7_g.g_hm_mode = (uint8_t) val;
734 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
735 }
736
737 return ret;
738 }
739
740 /**
741 * @brief High-performance operating mode disable for gyroscope.[get]
742 *
743 * @param ctx Read / write interface definitions
744 * @param val Get the values of g_hm_mode in reg CTRL7_G
745 * @retval Interface status (MANDATORY: return 0 -> no Error).
746 *
747 */
lsm6dsl_gy_power_mode_get(stmdev_ctx_t * ctx,lsm6dsl_g_hm_mode_t * val)748 int32_t lsm6dsl_gy_power_mode_get(stmdev_ctx_t *ctx,
749 lsm6dsl_g_hm_mode_t *val)
750 {
751 lsm6dsl_ctrl7_g_t ctrl7_g;
752 int32_t ret;
753
754 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
755
756 switch (ctrl7_g.g_hm_mode)
757 {
758 case LSM6DSL_GY_HIGH_PERFORMANCE:
759 *val = LSM6DSL_GY_HIGH_PERFORMANCE;
760 break;
761
762 case LSM6DSL_GY_NORMAL:
763 *val = LSM6DSL_GY_NORMAL;
764 break;
765
766 default:
767 *val = LSM6DSL_GY_PW_MODE_ND;
768 break;
769 }
770
771 return ret;
772 }
773
774 /**
775 * @brief Read all the interrupt/status flag of the device.[get]
776 *
777 * @param ctx Read / write interface definitions
778 * @param val WAKE_UP_SRC, TAP_SRC, D6D_SRC, STATUS_REG,
779 * FUNC_SRC1, FUNC_SRC2, WRIST_TILT_IA, A_WRIST_TILT_Mask
780 * @retval Interface status (MANDATORY: return 0 -> no Error).
781 *
782 */
lsm6dsl_all_sources_get(stmdev_ctx_t * ctx,lsm6dsl_all_sources_t * val)783 int32_t lsm6dsl_all_sources_get(stmdev_ctx_t *ctx,
784 lsm6dsl_all_sources_t *val)
785 {
786 int32_t ret;
787
788 ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_SRC,
789 (uint8_t *) & (val->wake_up_src), 1);
790
791 if (ret == 0)
792 {
793 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_SRC,
794 (uint8_t *) & (val->tap_src), 1);
795 }
796
797 if (ret == 0)
798 {
799 ret = lsm6dsl_read_reg(ctx, LSM6DSL_D6D_SRC,
800 (uint8_t *) & (val->d6d_src), 1);
801 }
802
803 if (ret == 0)
804 {
805 ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG,
806 (uint8_t *) & (val->status_reg), 1);
807 }
808
809 if (ret == 0)
810 {
811 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FUNC_SRC1,
812 (uint8_t *) & (val->func_src1), 1);
813 }
814
815 if (ret == 0)
816 {
817 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FUNC_SRC2,
818 (uint8_t *) & (val->func_src2), 1);
819 }
820
821 if (ret == 0)
822 {
823 ret = lsm6dsl_read_reg(ctx, LSM6DSL_WRIST_TILT_IA,
824 (uint8_t *) & (val->wrist_tilt_ia), 1);
825 }
826
827 if (ret == 0)
828 {
829 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B);
830 }
831
832 if (ret == 0)
833 {
834 ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_MASK,
835 (uint8_t *) & (val->a_wrist_tilt_mask), 1);
836 }
837
838 if (ret == 0)
839 {
840 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
841 }
842
843 return ret;
844 }
845 /**
846 * @brief The STATUS_REG register is read by the primary interface[get]
847 *
848 * @param ctx Read / write interface definitions
849 * @param val Registers STATUS_REG
850 * @retval Interface status (MANDATORY: return 0 -> no Error).
851 *
852 */
lsm6dsl_status_reg_get(stmdev_ctx_t * ctx,lsm6dsl_status_reg_t * val)853 int32_t lsm6dsl_status_reg_get(stmdev_ctx_t *ctx,
854 lsm6dsl_status_reg_t *val)
855 {
856 int32_t ret;
857
858 ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG, (uint8_t *) val, 1);
859
860 return ret;
861 }
862
863 /**
864 * @brief Accelerometer new data available.[get]
865 *
866 * @param ctx Read / write interface definitions
867 * @param val Change the values of xlda in reg STATUS_REG
868 * @retval Interface status (MANDATORY: return 0 -> no Error).
869 *
870 */
lsm6dsl_xl_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)871 int32_t lsm6dsl_xl_flag_data_ready_get(stmdev_ctx_t *ctx,
872 uint8_t *val)
873 {
874 lsm6dsl_status_reg_t status_reg;
875 int32_t ret;
876
877 ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG,
878 (uint8_t *)&status_reg, 1);
879 *val = status_reg.xlda;
880
881 return ret;
882 }
883
884 /**
885 * @brief Gyroscope new data available.[get]
886 *
887 * @param ctx Read / write interface definitions
888 * @param val Change the values of gda in reg STATUS_REG
889 * @retval Interface status (MANDATORY: return 0 -> no Error).
890 *
891 */
lsm6dsl_gy_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)892 int32_t lsm6dsl_gy_flag_data_ready_get(stmdev_ctx_t *ctx,
893 uint8_t *val)
894 {
895 lsm6dsl_status_reg_t status_reg;
896 int32_t ret;
897
898 ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG,
899 (uint8_t *)&status_reg, 1);
900 *val = status_reg.gda;
901
902 return ret;
903 }
904
905 /**
906 * @brief Temperature new data available.[get]
907 *
908 * @param ctx Read / write interface definitions
909 * @param val Change the values of tda in reg STATUS_REG
910 * @retval Interface status (MANDATORY: return 0 -> no Error).
911 *
912 */
lsm6dsl_temp_flag_data_ready_get(stmdev_ctx_t * ctx,uint8_t * val)913 int32_t lsm6dsl_temp_flag_data_ready_get(stmdev_ctx_t *ctx,
914 uint8_t *val)
915 {
916 lsm6dsl_status_reg_t status_reg;
917 int32_t ret;
918
919 ret = lsm6dsl_read_reg(ctx, LSM6DSL_STATUS_REG,
920 (uint8_t *)&status_reg, 1);
921 *val = status_reg.tda;
922
923 return ret;
924 }
925
926 /**
927 * @brief Accelerometer axis user offset correction expressed in two’s
928 * complement, weight depends on USR_OFF_W in CTRL6_C.
929 * The value must be in the range [-127 127].[set]
930 *
931 * @param ctx Read / write interface definitions
932 * @param buff Buffer that contains data to write
933 * @retval Interface status (MANDATORY: return 0 -> no Error).
934 *
935 */
lsm6dsl_xl_usr_offset_set(stmdev_ctx_t * ctx,uint8_t * buff)936 int32_t lsm6dsl_xl_usr_offset_set(stmdev_ctx_t *ctx, uint8_t *buff)
937 {
938 int32_t ret;
939
940 ret = lsm6dsl_write_reg(ctx, LSM6DSL_X_OFS_USR, buff, 3);
941
942 return ret;
943 }
944
945 /**
946 * @brief Accelerometer axis user offset correction xpressed in two’s
947 * complement, weight depends on USR_OFF_W in CTRL6_C.
948 * The value must be in the range [-127 127].[get]
949 *
950 * @param ctx Read / write interface definitions
951 * @param buff Buffer that stores data read
952 * @retval Interface status (MANDATORY: return 0 -> no Error).
953 *
954 */
lsm6dsl_xl_usr_offset_get(stmdev_ctx_t * ctx,uint8_t * buff)955 int32_t lsm6dsl_xl_usr_offset_get(stmdev_ctx_t *ctx, uint8_t *buff)
956 {
957 int32_t ret;
958
959 ret = lsm6dsl_read_reg(ctx, LSM6DSL_X_OFS_USR, buff, 3);
960
961 return ret;
962 }
963
964 /**
965 * @}
966 *
967 */
968
969 /**
970 * @defgroup LSM6DSL_Timestamp
971 * @brief This section groups all the functions that manage the
972 * timestamp generation.
973 * @{
974 *
975 */
976
977 /**
978 * @brief Enable timestamp count. The count is saved in TIMESTAMP0_REG (40h),
979 * TIMESTAMP1_REG (41h) and TIMESTAMP2_REG (42h).[set]
980 *
981 * @param ctx Read / write interface definitions
982 * @param val Change the values of timer_en in reg CTRL10_C
983 * @retval Interface status (MANDATORY: return 0 -> no Error).
984 *
985 */
lsm6dsl_timestamp_set(stmdev_ctx_t * ctx,uint8_t val)986 int32_t lsm6dsl_timestamp_set(stmdev_ctx_t *ctx, uint8_t val)
987 {
988 lsm6dsl_ctrl10_c_t ctrl10_c;
989 int32_t ret;
990
991 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
992
993 if (ret == 0)
994 {
995 ctrl10_c.timer_en = val;
996
997 if (val != 0x00U)
998 {
999 ctrl10_c.func_en = val;
1000 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1001 }
1002 }
1003
1004 return ret;
1005 }
1006
1007 /**
1008 * @brief Enable timestamp count. The count is saved in TIMESTAMP0_REG (40h),
1009 * TIMESTAMP1_REG (41h) and TIMESTAMP2_REG (42h).[get]
1010 *
1011 * @param ctx Read / write interface definitions
1012 * @param val Change the values of timer_en in reg CTRL10_C
1013 * @retval Interface status (MANDATORY: return 0 -> no Error).
1014 *
1015 */
lsm6dsl_timestamp_get(stmdev_ctx_t * ctx,uint8_t * val)1016 int32_t lsm6dsl_timestamp_get(stmdev_ctx_t *ctx, uint8_t *val)
1017 {
1018 lsm6dsl_ctrl10_c_t ctrl10_c;
1019 int32_t ret;
1020
1021 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
1022 *val = ctrl10_c.timer_en;
1023
1024 return ret;
1025 }
1026
1027 /**
1028 * @brief Timestamp register resolution setting.
1029 * Configuration of this bit affects
1030 * TIMESTAMP0_REG(40h), TIMESTAMP1_REG(41h),
1031 * TIMESTAMP2_REG(42h), STEP_TIMESTAMP_L(49h),
1032 * STEP_TIMESTAMP_H(4Ah) and
1033 * STEP_COUNT_DELTA(15h) registers.[set]
1034 *
1035 * @param ctx Read / write interface definitions
1036 * @param val Change the values of timer_hr in reg WAKE_UP_DUR
1037 * @retval Interface status (MANDATORY: return 0 -> no Error).
1038 *
1039 */
lsm6dsl_timestamp_res_set(stmdev_ctx_t * ctx,lsm6dsl_timer_hr_t val)1040 int32_t lsm6dsl_timestamp_res_set(stmdev_ctx_t *ctx,
1041 lsm6dsl_timer_hr_t val)
1042 {
1043 lsm6dsl_wake_up_dur_t wake_up_dur;
1044 int32_t ret;
1045
1046 ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR,
1047 (uint8_t *)&wake_up_dur, 1);
1048
1049 if (ret == 0)
1050 {
1051 wake_up_dur.timer_hr = (uint8_t) val;
1052 ret = lsm6dsl_write_reg(ctx, LSM6DSL_WAKE_UP_DUR,
1053 (uint8_t *)&wake_up_dur, 1);
1054 }
1055
1056 return ret;
1057 }
1058
1059 /**
1060 * @brief Timestamp register resolution setting.
1061 * Configuration of this bit affects
1062 * TIMESTAMP0_REG(40h), TIMESTAMP1_REG(41h),
1063 * TIMESTAMP2_REG(42h), STEP_TIMESTAMP_L(49h),
1064 * STEP_TIMESTAMP_H(4Ah) and
1065 * STEP_COUNT_DELTA(15h) registers.[get]
1066 *
1067 * @param ctx Read / write interface definitions
1068 * @param val Get the values of timer_hr in reg WAKE_UP_DUR
1069 * @retval Interface status (MANDATORY: return 0 -> no Error).
1070 *
1071 */
lsm6dsl_timestamp_res_get(stmdev_ctx_t * ctx,lsm6dsl_timer_hr_t * val)1072 int32_t lsm6dsl_timestamp_res_get(stmdev_ctx_t *ctx,
1073 lsm6dsl_timer_hr_t *val)
1074 {
1075 lsm6dsl_wake_up_dur_t wake_up_dur;
1076 int32_t ret;
1077
1078 ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR,
1079 (uint8_t *)&wake_up_dur, 1);
1080
1081 switch (wake_up_dur.timer_hr)
1082 {
1083 case LSM6DSL_LSB_6ms4:
1084 *val = LSM6DSL_LSB_6ms4;
1085 break;
1086
1087 case LSM6DSL_LSB_25us:
1088 *val = LSM6DSL_LSB_25us;
1089 break;
1090
1091 default:
1092 *val = LSM6DSL_TS_RES_ND;
1093 break;
1094 }
1095
1096 return ret;
1097 }
1098
1099 /**
1100 * @}
1101 *
1102 */
1103
1104 /**
1105 * @defgroup LSM6DSL_Dataoutput
1106 * @brief This section groups all the data output functions.
1107 * @{
1108 *
1109 */
1110
1111 /**
1112 * @brief Circular burst-mode (rounding) read from output registers
1113 * through the primary interface.[set]
1114 *
1115 * @param ctx Read / write interface definitions
1116 * @param val Change the values of rounding in reg CTRL5_C
1117 * @retval Interface status (MANDATORY: return 0 -> no Error).
1118 *
1119 */
lsm6dsl_rounding_mode_set(stmdev_ctx_t * ctx,lsm6dsl_rounding_t val)1120 int32_t lsm6dsl_rounding_mode_set(stmdev_ctx_t *ctx,
1121 lsm6dsl_rounding_t val)
1122 {
1123 lsm6dsl_ctrl5_c_t ctrl5_c;
1124 int32_t ret;
1125
1126 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1127
1128 if (ret == 0)
1129 {
1130 ctrl5_c.rounding = (uint8_t) val;
1131 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1132 }
1133
1134 return ret;
1135 }
1136
1137 /**
1138 * @brief Circular burst-mode (rounding) read from output registers
1139 * through the primary interface.[get]
1140 *
1141 * @param ctx Read / write interface definitions
1142 * @param val Get the values of rounding in reg CTRL5_C
1143 * @retval Interface status (MANDATORY: return 0 -> no Error).
1144 *
1145 */
lsm6dsl_rounding_mode_get(stmdev_ctx_t * ctx,lsm6dsl_rounding_t * val)1146 int32_t lsm6dsl_rounding_mode_get(stmdev_ctx_t *ctx,
1147 lsm6dsl_rounding_t *val)
1148 {
1149 lsm6dsl_ctrl5_c_t ctrl5_c;
1150 int32_t ret;
1151
1152 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1153
1154 switch (ctrl5_c.rounding)
1155 {
1156 case LSM6DSL_ROUND_DISABLE:
1157 *val = LSM6DSL_ROUND_DISABLE;
1158 break;
1159
1160 case LSM6DSL_ROUND_XL:
1161 *val = LSM6DSL_ROUND_XL;
1162 break;
1163
1164 case LSM6DSL_ROUND_GY:
1165 *val = LSM6DSL_ROUND_GY;
1166 break;
1167
1168 case LSM6DSL_ROUND_GY_XL:
1169 *val = LSM6DSL_ROUND_GY_XL;
1170 break;
1171
1172 case LSM6DSL_ROUND_SH1_TO_SH6:
1173 *val = LSM6DSL_ROUND_SH1_TO_SH6;
1174 break;
1175
1176 case LSM6DSL_ROUND_XL_SH1_TO_SH6:
1177 *val = LSM6DSL_ROUND_XL_SH1_TO_SH6;
1178 break;
1179
1180 case LSM6DSL_ROUND_GY_XL_SH1_TO_SH12:
1181 *val = LSM6DSL_ROUND_GY_XL_SH1_TO_SH12;
1182 break;
1183
1184 case LSM6DSL_ROUND_GY_XL_SH1_TO_SH6:
1185 *val = LSM6DSL_ROUND_GY_XL_SH1_TO_SH6;
1186 break;
1187
1188 default:
1189 *val = LSM6DSL_ROUND_OUT_ND;
1190 break;
1191 }
1192
1193 return ret;
1194 }
1195
1196 /**
1197 * @brief Temperature data output register (r). L and H registers together
1198 * express a 16-bit word in two’s complement.[get]
1199 *
1200 * @param ctx Read / write interface definitions
1201 * @param buff Buffer that stores data read
1202 * @retval Interface status (MANDATORY: return 0 -> no Error).
1203 *
1204 */
lsm6dsl_temperature_raw_get(stmdev_ctx_t * ctx,int16_t * val)1205 int32_t lsm6dsl_temperature_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1206 {
1207 uint8_t buff[2];
1208 int32_t ret;
1209
1210 ret = lsm6dsl_read_reg(ctx, LSM6DSL_OUT_TEMP_L, buff, 2);
1211 val[0] = (int16_t)buff[1];
1212 val[0] = (val[0] * 256) + (int16_t)buff[0];
1213
1214 return ret;
1215 }
1216
1217 /**
1218 * @brief Angular rate sensor. The value is expressed as a 16-bit word in
1219 * two’s complement.[get]
1220 *
1221 * @param ctx Read / write interface definitions
1222 * @param buff Buffer that stores data read
1223 * @retval Interface status (MANDATORY: return 0 -> no Error).
1224 *
1225 */
lsm6dsl_angular_rate_raw_get(stmdev_ctx_t * ctx,int16_t * val)1226 int32_t lsm6dsl_angular_rate_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1227 {
1228 uint8_t buff[6];
1229 int32_t ret;
1230
1231 ret = lsm6dsl_read_reg(ctx, LSM6DSL_OUTX_L_G, buff, 6);
1232 val[0] = (int16_t)buff[1];
1233 val[0] = (val[0] * 256) + (int16_t)buff[0];
1234 val[1] = (int16_t)buff[3];
1235 val[1] = (val[1] * 256) + (int16_t)buff[2];
1236 val[2] = (int16_t)buff[5];
1237 val[2] = (val[2] * 256) + (int16_t)buff[4];
1238
1239 return ret;
1240 }
1241
1242 /**
1243 * @brief Linear acceleration output register. The value is expressed
1244 * as a 16-bit word in two’s complement.[get]
1245 *
1246 * @param ctx Read / write interface definitions
1247 * @param buff Buffer that stores data read
1248 * @retval Interface status (MANDATORY: return 0 -> no Error).
1249 *
1250 */
lsm6dsl_acceleration_raw_get(stmdev_ctx_t * ctx,int16_t * val)1251 int32_t lsm6dsl_acceleration_raw_get(stmdev_ctx_t *ctx, int16_t *val)
1252 {
1253 uint8_t buff[6];
1254 int32_t ret;
1255
1256 ret = lsm6dsl_read_reg(ctx, LSM6DSL_OUTX_L_XL, buff, 6);
1257 val[0] = (int16_t)buff[1];
1258 val[0] = (val[0] * 256) + (int16_t)buff[0];
1259 val[1] = (int16_t)buff[3];
1260 val[1] = (val[1] * 256) + (int16_t)buff[2];
1261 val[2] = (int16_t)buff[5];
1262 val[2] = (val[2] * 256) + (int16_t)buff[4];
1263
1264 return ret;
1265 }
1266
1267 /**
1268 * @brief External magnetometer raw data.[get]
1269 *
1270 * @param ctx Read / write interface definitions
1271 * @param buff Buffer that stores data read
1272 * @retval Interface status (MANDATORY: return 0 -> no Error).
1273 *
1274 */
lsm6dsl_mag_calibrated_raw_get(stmdev_ctx_t * ctx,int16_t * val)1275 int32_t lsm6dsl_mag_calibrated_raw_get(stmdev_ctx_t *ctx,
1276 int16_t *val)
1277 {
1278 uint8_t buff[6];
1279 int32_t ret;
1280
1281 ret = lsm6dsl_read_reg(ctx, LSM6DSL_OUT_MAG_RAW_X_L, buff, 6);
1282 val[0] = (int16_t)buff[1];
1283 val[0] = (val[0] * 256) + (int16_t)buff[0];
1284 val[1] = (int16_t)buff[3];
1285 val[1] = (val[1] * 256) + (int16_t)buff[2];
1286 val[2] = (int16_t)buff[5];
1287 val[2] = (val[2] * 256) + (int16_t)buff[4];
1288
1289 return ret;
1290 }
1291
1292 /**
1293 * @brief Read data in FIFO.[get]
1294 *
1295 * @param ctx Read / write interface definitions
1296 * @param buffer Data buffer to store FIFO data.
1297 * @param len Number of data to read from FIFO.
1298 * @retval Interface status (MANDATORY: return 0 -> no Error).
1299 *
1300 */
lsm6dsl_fifo_raw_data_get(stmdev_ctx_t * ctx,uint8_t * buffer,uint8_t len)1301 int32_t lsm6dsl_fifo_raw_data_get(stmdev_ctx_t *ctx, uint8_t *buffer,
1302 uint8_t len)
1303 {
1304 int32_t ret;
1305
1306 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_DATA_OUT_L, buffer, len);
1307
1308 return ret;
1309 }
1310
1311 /**
1312 * @}
1313 *
1314 */
1315
1316 /**
1317 * @defgroup LSM6DSL_common
1318 * @brief This section groups common useful functions.
1319 * @{
1320 *
1321 */
1322
1323 /**
1324 * @brief Enable access to the embedded functions/sensor hub
1325 * configuration registers[set]
1326 *
1327 * @param ctx Read / write interface definitions
1328 * @param val Change the values of func_cfg_en in reg FUNC_CFG_ACCESS
1329 * @retval Interface status (MANDATORY: return 0 -> no Error).
1330 *
1331 */
lsm6dsl_mem_bank_set(stmdev_ctx_t * ctx,lsm6dsl_func_cfg_en_t val)1332 int32_t lsm6dsl_mem_bank_set(stmdev_ctx_t *ctx,
1333 lsm6dsl_func_cfg_en_t val)
1334 {
1335 lsm6dsl_func_cfg_access_t func_cfg_access;
1336 int32_t ret;
1337
1338 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FUNC_CFG_ACCESS,
1339 (uint8_t *)&func_cfg_access, 1);
1340
1341 if (ret == 0)
1342 {
1343 func_cfg_access.func_cfg_en = (uint8_t) val;
1344 ret = lsm6dsl_write_reg(ctx, LSM6DSL_FUNC_CFG_ACCESS,
1345 (uint8_t *)&func_cfg_access, 1);
1346 }
1347
1348 return ret;
1349 }
1350
1351 /**
1352 * @brief Enable access to the embedded functions/sensor hub configuration
1353 * registers[get]
1354 *
1355 * @param ctx Read / write interface definitions
1356 * @param val Get the values of func_cfg_en in reg FUNC_CFG_ACCESS
1357 * @retval Interface status (MANDATORY: return 0 -> no Error).
1358 *
1359 */
lsm6dsl_mem_bank_get(stmdev_ctx_t * ctx,lsm6dsl_func_cfg_en_t * val)1360 int32_t lsm6dsl_mem_bank_get(stmdev_ctx_t *ctx,
1361 lsm6dsl_func_cfg_en_t *val)
1362 {
1363 lsm6dsl_func_cfg_access_t func_cfg_access;
1364 int32_t ret;
1365
1366 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FUNC_CFG_ACCESS,
1367 (uint8_t *)&func_cfg_access, 1);
1368
1369 switch (func_cfg_access.func_cfg_en)
1370 {
1371 case LSM6DSL_USER_BANK:
1372 *val = LSM6DSL_USER_BANK;
1373 break;
1374
1375 case LSM6DSL_BANK_B:
1376 *val = LSM6DSL_BANK_B;
1377 break;
1378
1379 default:
1380 *val = LSM6DSL_BANK_ND;
1381 break;
1382 }
1383
1384 return ret;
1385 }
1386
1387 /**
1388 * @brief Data-ready pulsed / letched mode[set]
1389 *
1390 * @param ctx Read / write interface definitions
1391 * @param val Change the values of drdy_pulsed in reg DRDY_PULSE_CFG
1392 * @retval Interface status (MANDATORY: return 0 -> no Error).
1393 *
1394 */
lsm6dsl_data_ready_mode_set(stmdev_ctx_t * ctx,lsm6dsl_drdy_pulsed_g_t val)1395 int32_t lsm6dsl_data_ready_mode_set(stmdev_ctx_t *ctx,
1396 lsm6dsl_drdy_pulsed_g_t val)
1397 {
1398 lsm6dsl_drdy_pulse_cfg_g_t drdy_pulse_cfg_g;
1399 int32_t ret;
1400
1401 ret = lsm6dsl_read_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G,
1402 (uint8_t *)&drdy_pulse_cfg_g, 1);
1403
1404 if (ret == 0)
1405 {
1406 drdy_pulse_cfg_g.drdy_pulsed = (uint8_t) val;
1407 ret = lsm6dsl_write_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G,
1408 (uint8_t *)&drdy_pulse_cfg_g, 1);
1409 }
1410
1411 return ret;
1412 }
1413
1414 /**
1415 * @brief Data-ready pulsed / letched mode[get]
1416 *
1417 * @param ctx Read / write interface definitions
1418 * @param val Get the values of drdy_pulsed in reg DRDY_PULSE_CFG
1419 * @retval Interface status (MANDATORY: return 0 -> no Error).
1420 *
1421 */
lsm6dsl_data_ready_mode_get(stmdev_ctx_t * ctx,lsm6dsl_drdy_pulsed_g_t * val)1422 int32_t lsm6dsl_data_ready_mode_get(stmdev_ctx_t *ctx,
1423 lsm6dsl_drdy_pulsed_g_t *val)
1424 {
1425 lsm6dsl_drdy_pulse_cfg_g_t drdy_pulse_cfg_g;
1426 int32_t ret;
1427
1428 ret = lsm6dsl_read_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G,
1429 (uint8_t *)&drdy_pulse_cfg_g, 1);
1430
1431 switch (drdy_pulse_cfg_g.drdy_pulsed)
1432 {
1433 case LSM6DSL_DRDY_LATCHED:
1434 *val = LSM6DSL_DRDY_LATCHED;
1435 break;
1436
1437 case LSM6DSL_DRDY_PULSED:
1438 *val = LSM6DSL_DRDY_PULSED;
1439 break;
1440
1441 default:
1442 *val = LSM6DSL_DRDY_ND;
1443 break;
1444 }
1445
1446 return ret;
1447 }
1448
1449 /**
1450 * @brief DeviceWhoamI.[get]
1451 *
1452 * @param ctx Read / write interface definitions
1453 * @param buff Buffer that stores data read
1454 * @retval Interface status (MANDATORY: return 0 -> no Error).
1455 *
1456 */
lsm6dsl_device_id_get(stmdev_ctx_t * ctx,uint8_t * buff)1457 int32_t lsm6dsl_device_id_get(stmdev_ctx_t *ctx, uint8_t *buff)
1458 {
1459 int32_t ret;
1460
1461 ret = lsm6dsl_read_reg(ctx, LSM6DSL_WHO_AM_I, buff, 1);
1462
1463 return ret;
1464 }
1465
1466 /**
1467 * @brief Software reset. Restore the default values in user registers[set]
1468 *
1469 * @param ctx Read / write interface definitions
1470 * @param val Change the values of sw_reset in reg CTRL3_C
1471 * @retval Interface status (MANDATORY: return 0 -> no Error).
1472 *
1473 */
lsm6dsl_reset_set(stmdev_ctx_t * ctx,uint8_t val)1474 int32_t lsm6dsl_reset_set(stmdev_ctx_t *ctx, uint8_t val)
1475 {
1476 lsm6dsl_ctrl3_c_t ctrl3_c;
1477 int32_t ret;
1478
1479 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1480
1481 if (ret == 0)
1482 {
1483 ctrl3_c.sw_reset = val;
1484 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1485 }
1486
1487 return ret;
1488 }
1489
1490 /**
1491 * @brief Software reset. Restore the default values in user registers[get]
1492 *
1493 * @param ctx Read / write interface definitions
1494 * @param val Change the values of sw_reset in reg CTRL3_C
1495 * @retval Interface status (MANDATORY: return 0 -> no Error).
1496 *
1497 */
lsm6dsl_reset_get(stmdev_ctx_t * ctx,uint8_t * val)1498 int32_t lsm6dsl_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
1499 {
1500 lsm6dsl_ctrl3_c_t ctrl3_c;
1501 int32_t ret;
1502
1503 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1504 *val = ctrl3_c.sw_reset;
1505
1506 return ret;
1507 }
1508
1509 /**
1510 * @brief Big/Little Endian Data selection.[set]
1511 *
1512 * @param ctx Read / write interface definitions
1513 * @param val Change the values of ble in reg CTRL3_C
1514 * @retval Interface status (MANDATORY: return 0 -> no Error).
1515 *
1516 */
lsm6dsl_data_format_set(stmdev_ctx_t * ctx,lsm6dsl_ble_t val)1517 int32_t lsm6dsl_data_format_set(stmdev_ctx_t *ctx, lsm6dsl_ble_t val)
1518 {
1519 lsm6dsl_ctrl3_c_t ctrl3_c;
1520 int32_t ret;
1521
1522 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1523
1524 if (ret == 0)
1525 {
1526 ctrl3_c.ble = (uint8_t) val;
1527 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1528 }
1529
1530 return ret;
1531 }
1532
1533 /**
1534 * @brief Big/Little Endian Data selection.[get]
1535 *
1536 * @param ctx Read / write interface definitions
1537 * @param val Get the values of ble in reg CTRL3_C
1538 * @retval Interface status (MANDATORY: return 0 -> no Error).
1539 *
1540 */
lsm6dsl_data_format_get(stmdev_ctx_t * ctx,lsm6dsl_ble_t * val)1541 int32_t lsm6dsl_data_format_get(stmdev_ctx_t *ctx, lsm6dsl_ble_t *val)
1542 {
1543 lsm6dsl_ctrl3_c_t ctrl3_c;
1544 int32_t ret;
1545
1546 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1547
1548 switch (ctrl3_c.ble)
1549 {
1550 case LSM6DSL_LSB_AT_LOW_ADD:
1551 *val = LSM6DSL_LSB_AT_LOW_ADD;
1552 break;
1553
1554 case LSM6DSL_MSB_AT_LOW_ADD:
1555 *val = LSM6DSL_MSB_AT_LOW_ADD;
1556 break;
1557
1558 default:
1559 *val = LSM6DSL_DATA_FMT_ND;
1560 break;
1561 }
1562
1563 return ret;
1564 }
1565
1566 /**
1567 * @brief Register address automatically incremented during a multiple byte
1568 * access with a serial interface.[set]
1569 *
1570 * @param ctx Read / write interface definitions
1571 * @param val Change the values of if_inc in reg CTRL3_C
1572 * @retval Interface status (MANDATORY: return 0 -> no Error).
1573 *
1574 */
lsm6dsl_auto_increment_set(stmdev_ctx_t * ctx,uint8_t val)1575 int32_t lsm6dsl_auto_increment_set(stmdev_ctx_t *ctx, uint8_t val)
1576 {
1577 lsm6dsl_ctrl3_c_t ctrl3_c;
1578 int32_t ret;
1579
1580 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1581
1582 if (ret == 0)
1583 {
1584 ctrl3_c.if_inc = val;
1585 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1586 }
1587
1588 return ret;
1589 }
1590
1591 /**
1592 * @brief Register address automatically incremented during a multiple byte
1593 * access with a serial interface.[get]
1594 *
1595 * @param ctx Read / write interface definitions
1596 * @param val Change the values of if_inc in reg CTRL3_C
1597 * @retval Interface status (MANDATORY: return 0 -> no Error).
1598 *
1599 */
lsm6dsl_auto_increment_get(stmdev_ctx_t * ctx,uint8_t * val)1600 int32_t lsm6dsl_auto_increment_get(stmdev_ctx_t *ctx, uint8_t *val)
1601 {
1602 lsm6dsl_ctrl3_c_t ctrl3_c;
1603 int32_t ret;
1604
1605 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1606 *val = ctrl3_c.if_inc;
1607
1608 return ret;
1609 }
1610
1611 /**
1612 * @brief Reboot memory content. Reload the calibration parameters.[set]
1613 *
1614 * @param ctx Read / write interface definitions
1615 * @param val Change the values of boot in reg CTRL3_C
1616 * @retval Interface status (MANDATORY: return 0 -> no Error).
1617 *
1618 */
lsm6dsl_boot_set(stmdev_ctx_t * ctx,uint8_t val)1619 int32_t lsm6dsl_boot_set(stmdev_ctx_t *ctx, uint8_t val)
1620 {
1621 lsm6dsl_ctrl3_c_t ctrl3_c;
1622 int32_t ret;
1623
1624 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1625
1626 if (ret == 0)
1627 {
1628 ctrl3_c.boot = val;
1629 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1630 }
1631
1632 return ret;
1633 }
1634
1635 /**
1636 * @brief Reboot memory content. Reload the calibration parameters.[get]
1637 *
1638 * @param ctx Read / write interface definitions
1639 * @param val Change the values of boot in reg CTRL3_C
1640 * @retval Interface status (MANDATORY: return 0 -> no Error).
1641 *
1642 */
lsm6dsl_boot_get(stmdev_ctx_t * ctx,uint8_t * val)1643 int32_t lsm6dsl_boot_get(stmdev_ctx_t *ctx, uint8_t *val)
1644 {
1645 lsm6dsl_ctrl3_c_t ctrl3_c;
1646 int32_t ret;
1647
1648 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
1649 *val = ctrl3_c.boot;
1650
1651 return ret;
1652 }
1653
1654 /**
1655 * @brief Linear acceleration sensor self-test enable.[set]
1656 *
1657 * @param ctx Read / write interface definitions
1658 * @param val Change the values of st_xl in reg CTRL5_C
1659 * @retval Interface status (MANDATORY: return 0 -> no Error).
1660 *
1661 */
lsm6dsl_xl_self_test_set(stmdev_ctx_t * ctx,lsm6dsl_st_xl_t val)1662 int32_t lsm6dsl_xl_self_test_set(stmdev_ctx_t *ctx,
1663 lsm6dsl_st_xl_t val)
1664 {
1665 lsm6dsl_ctrl5_c_t ctrl5_c;
1666 int32_t ret;
1667
1668 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1669
1670 if (ret == 0)
1671 {
1672 ctrl5_c.st_xl = (uint8_t) val;
1673 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1674 }
1675
1676 return ret;
1677 }
1678
1679 /**
1680 * @brief Linear acceleration sensor self-test enable.[get]
1681 *
1682 * @param ctx Read / write interface definitions
1683 * @param val Get the values of st_xl in reg CTRL5_C
1684 * @retval Interface status (MANDATORY: return 0 -> no Error).
1685 *
1686 */
lsm6dsl_xl_self_test_get(stmdev_ctx_t * ctx,lsm6dsl_st_xl_t * val)1687 int32_t lsm6dsl_xl_self_test_get(stmdev_ctx_t *ctx,
1688 lsm6dsl_st_xl_t *val)
1689 {
1690 lsm6dsl_ctrl5_c_t ctrl5_c;
1691 int32_t ret;
1692
1693 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1694
1695 switch (ctrl5_c.st_xl)
1696 {
1697 case LSM6DSL_XL_ST_DISABLE:
1698 *val = LSM6DSL_XL_ST_DISABLE;
1699 break;
1700
1701 case LSM6DSL_XL_ST_POSITIVE:
1702 *val = LSM6DSL_XL_ST_POSITIVE;
1703 break;
1704
1705 case LSM6DSL_XL_ST_NEGATIVE:
1706 *val = LSM6DSL_XL_ST_NEGATIVE;
1707 break;
1708
1709 default:
1710 *val = LSM6DSL_XL_ST_ND;
1711 break;
1712 }
1713
1714 return ret;
1715 }
1716
1717 /**
1718 * @brief Angular rate sensor self-test enable.[set]
1719 *
1720 * @param ctx Read / write interface definitions
1721 * @param val Change the values of st_g in reg CTRL5_C
1722 * @retval Interface status (MANDATORY: return 0 -> no Error).
1723 *
1724 */
lsm6dsl_gy_self_test_set(stmdev_ctx_t * ctx,lsm6dsl_st_g_t val)1725 int32_t lsm6dsl_gy_self_test_set(stmdev_ctx_t *ctx,
1726 lsm6dsl_st_g_t val)
1727 {
1728 lsm6dsl_ctrl5_c_t ctrl5_c;
1729 int32_t ret;
1730
1731 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1732
1733 if (ret == 0)
1734 {
1735 ctrl5_c.st_g = (uint8_t) val;
1736 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1737 }
1738
1739 return ret;
1740 }
1741
1742 /**
1743 * @brief Angular rate sensor self-test enable.[get]
1744 *
1745 * @param ctx Read / write interface definitions
1746 * @param val Get the values of st_g in reg CTRL5_C
1747 * @retval Interface status (MANDATORY: return 0 -> no Error).
1748 *
1749 */
lsm6dsl_gy_self_test_get(stmdev_ctx_t * ctx,lsm6dsl_st_g_t * val)1750 int32_t lsm6dsl_gy_self_test_get(stmdev_ctx_t *ctx,
1751 lsm6dsl_st_g_t *val)
1752 {
1753 lsm6dsl_ctrl5_c_t ctrl5_c;
1754 int32_t ret;
1755
1756 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
1757
1758 switch (ctrl5_c.st_g)
1759 {
1760 case LSM6DSL_GY_ST_DISABLE:
1761 *val = LSM6DSL_GY_ST_DISABLE;
1762 break;
1763
1764 case LSM6DSL_GY_ST_POSITIVE:
1765 *val = LSM6DSL_GY_ST_POSITIVE;
1766 break;
1767
1768 case LSM6DSL_GY_ST_NEGATIVE:
1769 *val = LSM6DSL_GY_ST_NEGATIVE;
1770 break;
1771
1772 default:
1773 *val = LSM6DSL_GY_ST_ND;
1774 break;
1775 }
1776
1777 return ret;
1778 }
1779
1780 /**
1781 * @}
1782 *
1783 */
1784
1785 /**
1786 * @defgroup LSM6DSL_filters
1787 * @brief This section group all the functions concerning the filters
1788 * configuration that impact both accelerometer and gyro.
1789 * @{
1790 *
1791 */
1792
1793 /**
1794 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
1795 * (XL and Gyro independently masked).[set]
1796 *
1797 * @param ctx Read / write interface definitions
1798 * @param val Change the values of drdy_mask in reg CTRL4_C
1799 * @retval Interface status (MANDATORY: return 0 -> no Error).
1800 *
1801 */
lsm6dsl_filter_settling_mask_set(stmdev_ctx_t * ctx,uint8_t val)1802 int32_t lsm6dsl_filter_settling_mask_set(stmdev_ctx_t *ctx,
1803 uint8_t val)
1804 {
1805 lsm6dsl_ctrl4_c_t ctrl4_c;
1806 int32_t ret;
1807
1808 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1809
1810 if (ret == 0)
1811 {
1812 ctrl4_c.drdy_mask = val;
1813 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1814 }
1815
1816 return ret;
1817 }
1818
1819 /**
1820 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
1821 * (XL and Gyro independently masked).[get]
1822 *
1823 * @param ctx Read / write interface definitions
1824 * @param val Change the values of drdy_mask in reg CTRL4_C
1825 * @retval Interface status (MANDATORY: return 0 -> no Error).
1826 *
1827 */
lsm6dsl_filter_settling_mask_get(stmdev_ctx_t * ctx,uint8_t * val)1828 int32_t lsm6dsl_filter_settling_mask_get(stmdev_ctx_t *ctx,
1829 uint8_t *val)
1830 {
1831 lsm6dsl_ctrl4_c_t ctrl4_c;
1832 int32_t ret;
1833
1834 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
1835 *val = ctrl4_c.drdy_mask;
1836
1837 return ret;
1838 }
1839
1840 /**
1841 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
1842 * functions.[set]
1843 *
1844 * @param ctx Read / write interface definitions
1845 * @param val Change the values of slope_fds in reg TAP_CFG
1846 * @retval Interface status (MANDATORY: return 0 -> no Error).
1847 *
1848 */
lsm6dsl_xl_hp_path_internal_set(stmdev_ctx_t * ctx,lsm6dsl_slope_fds_t val)1849 int32_t lsm6dsl_xl_hp_path_internal_set(stmdev_ctx_t *ctx,
1850 lsm6dsl_slope_fds_t val)
1851 {
1852 lsm6dsl_tap_cfg_t tap_cfg;
1853 int32_t ret;
1854
1855 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
1856
1857 if (ret == 0)
1858 {
1859 tap_cfg.slope_fds = (uint8_t) val;
1860 ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
1861 }
1862
1863 return ret;
1864 }
1865
1866 /**
1867 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
1868 * functions.[get]
1869 *
1870 * @param ctx Read / write interface definitions
1871 * @param val Get the values of slope_fds in reg TAP_CFG
1872 * @retval Interface status (MANDATORY: return 0 -> no Error).
1873 *
1874 */
lsm6dsl_xl_hp_path_internal_get(stmdev_ctx_t * ctx,lsm6dsl_slope_fds_t * val)1875 int32_t lsm6dsl_xl_hp_path_internal_get(stmdev_ctx_t *ctx,
1876 lsm6dsl_slope_fds_t *val)
1877 {
1878 lsm6dsl_tap_cfg_t tap_cfg;
1879 int32_t ret;
1880
1881 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
1882
1883 switch (tap_cfg.slope_fds)
1884 {
1885 case LSM6DSL_USE_SLOPE:
1886 *val = LSM6DSL_USE_SLOPE;
1887 break;
1888
1889 case LSM6DSL_USE_HPF:
1890 *val = LSM6DSL_USE_HPF;
1891 break;
1892
1893 default:
1894 *val = LSM6DSL_HP_PATH_ND;
1895 break;
1896 }
1897
1898 return ret;
1899 }
1900
1901 /**
1902 * @}
1903 *
1904 */
1905
1906 /**
1907 * @defgroup LSM6DSL_accelerometer_filters
1908 * @brief This section group all the functions concerning the filters
1909 * configuration that impact accelerometer in every mode.
1910 * @{
1911 *
1912 */
1913
1914 /**
1915 * @brief Accelerometer analog chain bandwidth selection (only for
1916 * accelerometer ODR ≥ 1.67 kHz).[set]
1917 *
1918 * @param ctx Read / write interface definitions
1919 * @param val Change the values of bw0_xl in reg CTRL1_XL
1920 * @retval Interface status (MANDATORY: return 0 -> no Error).
1921 *
1922 */
lsm6dsl_xl_filter_analog_set(stmdev_ctx_t * ctx,lsm6dsl_bw0_xl_t val)1923 int32_t lsm6dsl_xl_filter_analog_set(stmdev_ctx_t *ctx,
1924 lsm6dsl_bw0_xl_t val)
1925 {
1926 lsm6dsl_ctrl1_xl_t ctrl1_xl;
1927 int32_t ret;
1928
1929 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
1930
1931 if (ret == 0)
1932 {
1933 ctrl1_xl.bw0_xl = (uint8_t) val;
1934 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
1935 }
1936
1937 return ret;
1938 }
1939
1940 /**
1941 * @brief Accelerometer analog chain bandwidth selection (only for
1942 * accelerometer ODR ≥ 1.67 kHz).[get]
1943 *
1944 * @param ctx Read / write interface definitions
1945 * @param val Get the values of bw0_xl in reg CTRL1_XL
1946 * @retval Interface status (MANDATORY: return 0 -> no Error).
1947 *
1948 */
lsm6dsl_xl_filter_analog_get(stmdev_ctx_t * ctx,lsm6dsl_bw0_xl_t * val)1949 int32_t lsm6dsl_xl_filter_analog_get(stmdev_ctx_t *ctx,
1950 lsm6dsl_bw0_xl_t *val)
1951 {
1952 lsm6dsl_ctrl1_xl_t ctrl1_xl;
1953 int32_t ret;
1954
1955 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
1956
1957 switch (ctrl1_xl.bw0_xl)
1958 {
1959 case LSM6DSL_XL_ANA_BW_1k5Hz:
1960 *val = LSM6DSL_XL_ANA_BW_1k5Hz;
1961 break;
1962
1963 case LSM6DSL_XL_ANA_BW_400Hz:
1964 *val = LSM6DSL_XL_ANA_BW_400Hz;
1965 break;
1966
1967 default:
1968 *val = LSM6DSL_XL_ANA_BW_ND;
1969 break;
1970 }
1971
1972 return ret;
1973 }
1974
1975 /**
1976 * @}
1977 *
1978 */
1979
1980 /**
1981 * @defgroup LSM6DSL_accelerometer_filters
1982 * @brief This section group all the functions concerning the filters
1983 * configuration that impact accelerometer.
1984 * @{
1985 *
1986 */
1987
1988 /**
1989 * @brief Accelerometer digital LPF (LPF1) bandwidth selection LPF2 is
1990 * not used.[set]
1991 *
1992 * @param ctx Read / write interface definitions
1993 * @param val Change the values of lpf1_bw_sel in reg CTRL1_XL
1994 * @retval Interface status (MANDATORY: return 0 -> no Error).
1995 *
1996 */
lsm6dsl_xl_lp1_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsl_lpf1_bw_sel_t val)1997 int32_t lsm6dsl_xl_lp1_bandwidth_set(stmdev_ctx_t *ctx,
1998 lsm6dsl_lpf1_bw_sel_t val)
1999 {
2000 lsm6dsl_ctrl1_xl_t ctrl1_xl;
2001 lsm6dsl_ctrl8_xl_t ctrl8_xl;
2002 int32_t ret;
2003
2004 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2005
2006 if (ret == 0)
2007 {
2008 ctrl1_xl.lpf1_bw_sel = (uint8_t) val;
2009 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2010
2011 if (ret == 0)
2012 {
2013 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2014
2015 if (ret == 0)
2016 {
2017 ctrl8_xl.lpf2_xl_en = 0;
2018 ctrl8_xl.hp_slope_xl_en = 0;
2019 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2020 }
2021 }
2022 }
2023
2024 return ret;
2025 }
2026
2027 /**
2028 * @brief Accelerometer digital LPF (LPF1) bandwidth selection LPF2
2029 * is not used.[get]
2030 *
2031 * @param ctx Read / write interface definitions
2032 * @param val Get the values of lpf1_bw_sel in reg CTRL1_XL
2033 * @retval Interface status (MANDATORY: return 0 -> no Error).
2034 *
2035 */
lsm6dsl_xl_lp1_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsl_lpf1_bw_sel_t * val)2036 int32_t lsm6dsl_xl_lp1_bandwidth_get(stmdev_ctx_t *ctx,
2037 lsm6dsl_lpf1_bw_sel_t *val)
2038 {
2039 lsm6dsl_ctrl1_xl_t ctrl1_xl;
2040 lsm6dsl_ctrl8_xl_t ctrl8_xl;
2041 int32_t ret;
2042
2043 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2044
2045 if (ret == 0)
2046 {
2047 if ((ctrl8_xl.lpf2_xl_en != 0x00U) ||
2048 (ctrl8_xl.hp_slope_xl_en != 0x00U))
2049 {
2050 *val = LSM6DSL_XL_LP1_NA;
2051 }
2052
2053 else
2054 {
2055 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL1_XL, (uint8_t *)&ctrl1_xl, 1);
2056
2057 switch (ctrl1_xl.lpf1_bw_sel)
2058 {
2059 case LSM6DSL_XL_LP1_ODR_DIV_2:
2060 *val = LSM6DSL_XL_LP1_ODR_DIV_2;
2061 break;
2062
2063 case LSM6DSL_XL_LP1_ODR_DIV_4:
2064 *val = LSM6DSL_XL_LP1_ODR_DIV_4;
2065 break;
2066
2067 default:
2068 *val = LSM6DSL_XL_LP1_NA;
2069 break;
2070 }
2071 }
2072 }
2073
2074 return ret;
2075 }
2076
2077 /**
2078 * @brief LPF2 on outputs[set]
2079 *
2080 * @param ctx Read / write interface definitions
2081 * @param val Change the values of input_composite in reg CTRL8_XL
2082 * @retval Interface status (MANDATORY: return 0 -> no Error).
2083 *
2084 */
lsm6dsl_xl_lp2_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsl_input_composite_t val)2085 int32_t lsm6dsl_xl_lp2_bandwidth_set(stmdev_ctx_t *ctx,
2086 lsm6dsl_input_composite_t val)
2087 {
2088 lsm6dsl_ctrl8_xl_t ctrl8_xl;
2089 int32_t ret;
2090
2091 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2092
2093 if (ret == 0)
2094 {
2095 ctrl8_xl.input_composite = ((uint8_t) val & 0x10U) >> 4;
2096 ctrl8_xl.hpcf_xl = (uint8_t) val & 0x03U;
2097 ctrl8_xl.lpf2_xl_en = 1;
2098 ctrl8_xl.hp_slope_xl_en = 0;
2099 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2100 }
2101
2102 return ret;
2103 }
2104
2105 /**
2106 * @brief LPF2 on outputs[get]
2107 *
2108 * @param ctx Read / write interface definitions
2109 * @param val Get the values of input_composite in reg CTRL8_XL
2110 * @retval Interface status (MANDATORY: return 0 -> no Error).
2111 *
2112 */
lsm6dsl_xl_lp2_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsl_input_composite_t * val)2113 int32_t lsm6dsl_xl_lp2_bandwidth_get(stmdev_ctx_t *ctx,
2114 lsm6dsl_input_composite_t *val)
2115 {
2116 lsm6dsl_ctrl8_xl_t ctrl8_xl;
2117 int32_t ret;
2118
2119 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2120
2121 if (ret == 0)
2122 {
2123 if ((ctrl8_xl.lpf2_xl_en == 0x00U) ||
2124 (ctrl8_xl.hp_slope_xl_en != 0x00U))
2125 {
2126 *val = LSM6DSL_XL_LP_NA;
2127 }
2128
2129 else
2130 {
2131 switch ((ctrl8_xl.input_composite << 4) + ctrl8_xl.hpcf_xl)
2132 {
2133 case LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_50:
2134 *val = LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_50;
2135 break;
2136
2137 case LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_100:
2138 *val = LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_100;
2139 break;
2140
2141 case LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_9:
2142 *val = LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_9;
2143 break;
2144
2145 case LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_400:
2146 *val = LSM6DSL_XL_LOW_LAT_LP_ODR_DIV_400;
2147 break;
2148
2149 case LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_50:
2150 *val = LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_50;
2151 break;
2152
2153 case LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_100:
2154 *val = LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_100;
2155 break;
2156
2157 case LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_9:
2158 *val = LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_9;
2159 break;
2160
2161 case LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_400:
2162 *val = LSM6DSL_XL_LOW_NOISE_LP_ODR_DIV_400;
2163 break;
2164
2165 default:
2166 *val = LSM6DSL_XL_LP_NA;
2167 break;
2168 }
2169 }
2170 }
2171
2172 return ret;
2173 }
2174
2175 /**
2176 * @brief Enable HP filter reference mode.[set]
2177 *
2178 * @param ctx Read / write interface definitions
2179 * @param val Change the values of hp_ref_mode in reg CTRL8_XL
2180 * @retval Interface status (MANDATORY: return 0 -> no Error).
2181 *
2182 */
lsm6dsl_xl_reference_mode_set(stmdev_ctx_t * ctx,uint8_t val)2183 int32_t lsm6dsl_xl_reference_mode_set(stmdev_ctx_t *ctx, uint8_t val)
2184 {
2185 lsm6dsl_ctrl8_xl_t ctrl8_xl;
2186 int32_t ret;
2187
2188 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2189
2190 if (ret == 0)
2191 {
2192 ctrl8_xl.hp_ref_mode = val;
2193 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2194 }
2195
2196 return ret;
2197 }
2198
2199 /**
2200 * @brief Enable HP filter reference mode.[get]
2201 *
2202 * @param ctx Read / write interface definitions
2203 * @param val Change the values of hp_ref_mode in reg CTRL8_XL
2204 * @retval Interface status (MANDATORY: return 0 -> no Error).
2205 *
2206 */
lsm6dsl_xl_reference_mode_get(stmdev_ctx_t * ctx,uint8_t * val)2207 int32_t lsm6dsl_xl_reference_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
2208 {
2209 lsm6dsl_ctrl8_xl_t ctrl8_xl;
2210 int32_t ret;
2211
2212 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2213 *val = ctrl8_xl.hp_ref_mode;
2214
2215 return ret;
2216 }
2217
2218 /**
2219 * @brief High pass/Slope on outputs.[set]
2220 *
2221 * @param ctx Read / write interface definitions
2222 * @param val Change the values of hpcf_xl in reg CTRL8_XL
2223 * @retval Interface status (MANDATORY: return 0 -> no Error).
2224 *
2225 */
lsm6dsl_xl_hp_bandwidth_set(stmdev_ctx_t * ctx,lsm6dsl_hpcf_xl_t val)2226 int32_t lsm6dsl_xl_hp_bandwidth_set(stmdev_ctx_t *ctx,
2227 lsm6dsl_hpcf_xl_t val)
2228 {
2229 lsm6dsl_ctrl8_xl_t ctrl8_xl;
2230 int32_t ret;
2231
2232 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2233
2234 if (ret == 0)
2235 {
2236 ctrl8_xl.input_composite = 0;
2237 ctrl8_xl.hpcf_xl = (uint8_t)val & 0x03U;
2238 ctrl8_xl.hp_slope_xl_en = 1;
2239 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2240 }
2241
2242 return ret;
2243 }
2244
2245 /**
2246 * @brief High pass/Slope on outputs.[get]
2247 *
2248 * @param ctx Read / write interface definitions
2249 * @param val Get the values of hpcf_xl in reg CTRL8_XL
2250 * @retval Interface status (MANDATORY: return 0 -> no Error).
2251 *
2252 */
lsm6dsl_xl_hp_bandwidth_get(stmdev_ctx_t * ctx,lsm6dsl_hpcf_xl_t * val)2253 int32_t lsm6dsl_xl_hp_bandwidth_get(stmdev_ctx_t *ctx,
2254 lsm6dsl_hpcf_xl_t *val)
2255 {
2256 lsm6dsl_ctrl8_xl_t ctrl8_xl;
2257 int32_t ret;
2258
2259 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
2260
2261 if (ctrl8_xl.hp_slope_xl_en == 0x00U)
2262 {
2263 *val = LSM6DSL_XL_HP_NA;
2264 }
2265
2266 switch (ctrl8_xl.hpcf_xl)
2267 {
2268 case LSM6DSL_XL_HP_ODR_DIV_4:
2269 *val = LSM6DSL_XL_HP_ODR_DIV_4;
2270 break;
2271
2272 case LSM6DSL_XL_HP_ODR_DIV_100:
2273 *val = LSM6DSL_XL_HP_ODR_DIV_100;
2274 break;
2275
2276 case LSM6DSL_XL_HP_ODR_DIV_9:
2277 *val = LSM6DSL_XL_HP_ODR_DIV_9;
2278 break;
2279
2280 case LSM6DSL_XL_HP_ODR_DIV_400:
2281 *val = LSM6DSL_XL_HP_ODR_DIV_400;
2282 break;
2283
2284 default:
2285 *val = LSM6DSL_XL_HP_NA;
2286 break;
2287 }
2288
2289 return ret;
2290 }
2291
2292 /**
2293 * @}
2294 *
2295 */
2296
2297 /**
2298 * @defgroup LSM6DSL_gyroscope_filters
2299 * @brief This section group all the functions concerning the filters
2300 * configuration that impact gyroscope.
2301 * @{
2302 *
2303 */
2304
2305 /**
2306 * @brief Gyroscope low pass path bandwidth.[set]
2307 *
2308 * @param ctx Read / write interface definitions
2309 * @param val gyroscope filtering chain configuration.
2310 * @retval Interface status (MANDATORY: return 0 -> no Error).
2311 *
2312 */
lsm6dsl_gy_band_pass_set(stmdev_ctx_t * ctx,lsm6dsl_lpf1_sel_g_t val)2313 int32_t lsm6dsl_gy_band_pass_set(stmdev_ctx_t *ctx,
2314 lsm6dsl_lpf1_sel_g_t val)
2315 {
2316 lsm6dsl_ctrl4_c_t ctrl4_c;
2317 lsm6dsl_ctrl6_c_t ctrl6_c;
2318 lsm6dsl_ctrl7_g_t ctrl7_g;
2319 int32_t ret;
2320
2321 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2322
2323 if (ret == 0)
2324 {
2325 ctrl7_g.hpm_g = ((uint8_t)val & 0x30U) >> 4;
2326 ctrl7_g.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
2327 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2328
2329 if (ret == 0)
2330 {
2331 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2332
2333 if (ret == 0)
2334 {
2335 ctrl6_c.ftype = (uint8_t)val & 0x03U;
2336 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2337
2338 if (ret == 0)
2339 {
2340 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C,
2341 (uint8_t *)&ctrl4_c, 1);
2342
2343 if (ret == 0)
2344 {
2345 ctrl4_c.lpf1_sel_g = ((uint8_t)val & 0x08U) >> 3;
2346 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C,
2347 (uint8_t *)&ctrl4_c, 1);
2348 }
2349 }
2350 }
2351 }
2352 }
2353
2354 return ret;
2355 }
2356
2357 /**
2358 * @brief Gyroscope low pass path bandwidth.[get]
2359 *
2360 * @param ctx Read / write interface definitions
2361 * @param val gyroscope filtering chain
2362 * @retval Interface status (MANDATORY: return 0 -> no Error).
2363 *
2364 */
lsm6dsl_gy_band_pass_get(stmdev_ctx_t * ctx,lsm6dsl_lpf1_sel_g_t * val)2365 int32_t lsm6dsl_gy_band_pass_get(stmdev_ctx_t *ctx,
2366 lsm6dsl_lpf1_sel_g_t *val)
2367 {
2368 lsm6dsl_ctrl4_c_t ctrl4_c;
2369 lsm6dsl_ctrl6_c_t ctrl6_c;
2370 lsm6dsl_ctrl7_g_t ctrl7_g;
2371 int32_t ret;
2372
2373 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
2374
2375 if (ret == 0)
2376 {
2377 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2378
2379 if (ret == 0)
2380 {
2381 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL7_G, (uint8_t *)&ctrl7_g, 1);
2382
2383 switch ((ctrl7_g.hp_en_g << 7) + (ctrl7_g.hpm_g << 4) +
2384 (ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype)
2385 {
2386 case LSM6DSL_HP_16mHz_LP2:
2387 *val = LSM6DSL_HP_16mHz_LP2;
2388 break;
2389
2390 case LSM6DSL_HP_65mHz_LP2:
2391 *val = LSM6DSL_HP_65mHz_LP2;
2392 break;
2393
2394 case LSM6DSL_HP_260mHz_LP2:
2395 *val = LSM6DSL_HP_260mHz_LP2;
2396 break;
2397
2398 case LSM6DSL_HP_1Hz04_LP2:
2399 *val = LSM6DSL_HP_1Hz04_LP2;
2400 break;
2401
2402 case LSM6DSL_HP_DISABLE_LP1_LIGHT:
2403 *val = LSM6DSL_HP_DISABLE_LP1_LIGHT;
2404 break;
2405
2406 case LSM6DSL_HP_DISABLE_LP1_NORMAL:
2407 *val = LSM6DSL_HP_DISABLE_LP1_NORMAL;
2408 break;
2409
2410 case LSM6DSL_HP_DISABLE_LP_STRONG:
2411 *val = LSM6DSL_HP_DISABLE_LP_STRONG;
2412 break;
2413
2414 case LSM6DSL_HP_DISABLE_LP1_AGGRESSIVE:
2415 *val = LSM6DSL_HP_DISABLE_LP1_AGGRESSIVE;
2416 break;
2417
2418 case LSM6DSL_HP_16mHz_LP1_LIGHT:
2419 *val = LSM6DSL_HP_16mHz_LP1_LIGHT;
2420 break;
2421
2422 case LSM6DSL_HP_65mHz_LP1_NORMAL:
2423 *val = LSM6DSL_HP_65mHz_LP1_NORMAL;
2424 break;
2425
2426 case LSM6DSL_HP_260mHz_LP1_STRONG:
2427 *val = LSM6DSL_HP_260mHz_LP1_STRONG;
2428 break;
2429
2430 case LSM6DSL_HP_1Hz04_LP1_AGGRESSIVE:
2431 *val = LSM6DSL_HP_1Hz04_LP1_AGGRESSIVE;
2432 break;
2433
2434 default:
2435 *val = LSM6DSL_HP_GY_BAND_NA;
2436 break;
2437 }
2438 }
2439 }
2440
2441 return ret;
2442 }
2443
2444 /**
2445 * @}
2446 *
2447 */
2448
2449 /**
2450 * @defgroup LSM6DSL_serial_interface
2451 * @brief This section groups all the functions concerning serial
2452 * interface management
2453 * @{
2454 *
2455 */
2456
2457 /**
2458 * @brief SPI Serial Interface Mode selection.[set]
2459 *
2460 * @param ctx Read / write interface definitions
2461 * @param val Change the values of sim in reg CTRL3_C
2462 * @retval Interface status (MANDATORY: return 0 -> no Error).
2463 *
2464 */
lsm6dsl_spi_mode_set(stmdev_ctx_t * ctx,lsm6dsl_sim_t val)2465 int32_t lsm6dsl_spi_mode_set(stmdev_ctx_t *ctx, lsm6dsl_sim_t val)
2466 {
2467 lsm6dsl_ctrl3_c_t ctrl3_c;
2468 int32_t ret;
2469
2470 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2471
2472 if (ret == 0)
2473 {
2474 ctrl3_c.sim = (uint8_t) val;
2475 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2476 }
2477
2478 return ret;
2479 }
2480
2481 /**
2482 * @brief SPI Serial Interface Mode selection.[get]
2483 *
2484 * @param ctx Read / write interface definitions
2485 * @param val Get the values of sim in reg CTRL3_C
2486 * @retval Interface status (MANDATORY: return 0 -> no Error).
2487 *
2488 */
lsm6dsl_spi_mode_get(stmdev_ctx_t * ctx,lsm6dsl_sim_t * val)2489 int32_t lsm6dsl_spi_mode_get(stmdev_ctx_t *ctx, lsm6dsl_sim_t *val)
2490 {
2491 lsm6dsl_ctrl3_c_t ctrl3_c;
2492 int32_t ret;
2493
2494 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2495
2496 switch (ctrl3_c.sim)
2497 {
2498 case LSM6DSL_SPI_4_WIRE:
2499 *val = LSM6DSL_SPI_4_WIRE;
2500 break;
2501
2502 case LSM6DSL_SPI_3_WIRE:
2503 *val = LSM6DSL_SPI_3_WIRE;
2504 break;
2505
2506 default:
2507 *val = LSM6DSL_SPI_MODE_ND;
2508 break;
2509 }
2510
2511 return ret;
2512 }
2513
2514 /**
2515 * @brief Disable / Enable I2C interface.[set]
2516 *
2517 * @param ctx Read / write interface definitions
2518 * @param val Change the values of i2c_disable in reg CTRL4_C
2519 * @retval Interface status (MANDATORY: return 0 -> no Error).
2520 *
2521 */
lsm6dsl_i2c_interface_set(stmdev_ctx_t * ctx,lsm6dsl_i2c_disable_t val)2522 int32_t lsm6dsl_i2c_interface_set(stmdev_ctx_t *ctx,
2523 lsm6dsl_i2c_disable_t val)
2524 {
2525 lsm6dsl_ctrl4_c_t ctrl4_c;
2526 int32_t ret;
2527
2528 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2529
2530 if (ret == 0)
2531 {
2532 ctrl4_c.i2c_disable = (uint8_t)val;
2533 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2534 }
2535
2536 return ret;
2537 }
2538
2539 /**
2540 * @brief Disable / Enable I2C interface.[get]
2541 *
2542 * @param ctx Read / write interface definitions
2543 * @param val Get the values of i2c_disable in reg CTRL4_C
2544 * @retval Interface status (MANDATORY: return 0 -> no Error).
2545 *
2546 */
lsm6dsl_i2c_interface_get(stmdev_ctx_t * ctx,lsm6dsl_i2c_disable_t * val)2547 int32_t lsm6dsl_i2c_interface_get(stmdev_ctx_t *ctx,
2548 lsm6dsl_i2c_disable_t *val)
2549 {
2550 lsm6dsl_ctrl4_c_t ctrl4_c;
2551 int32_t ret;
2552
2553 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2554
2555 switch (ctrl4_c.i2c_disable)
2556 {
2557 case LSM6DSL_I2C_ENABLE:
2558 *val = LSM6DSL_I2C_ENABLE;
2559 break;
2560
2561 case LSM6DSL_I2C_DISABLE:
2562 *val = LSM6DSL_I2C_DISABLE;
2563 break;
2564
2565 default:
2566 *val = LSM6DSL_I2C_MODE_ND;
2567 break;
2568 }
2569
2570 return ret;
2571 }
2572
2573 /**
2574 * @}
2575 *
2576 */
2577
2578 /**
2579 * @defgroup LSM6DSL_interrupt_pins
2580 * @brief This section groups all the functions that manage
2581 * interrupt pins
2582 * @{
2583 *
2584 */
2585
2586 /**
2587 * @brief Select the signal that need to route on int1 pad[set]
2588 *
2589 * @param ctx Read / write interface definitions
2590 * @param val configure INT1_CTRL, MD1_CFG, CTRL4_C(den_drdy_int1),
2591 * MASTER_CONFIG(drdy_on_int1)
2592 * @retval Interface status (MANDATORY: return 0 -> no Error).
2593 *
2594 */
lsm6dsl_pin_int1_route_set(stmdev_ctx_t * ctx,lsm6dsl_int1_route_t val)2595 int32_t lsm6dsl_pin_int1_route_set(stmdev_ctx_t *ctx,
2596 lsm6dsl_int1_route_t val)
2597 {
2598 lsm6dsl_master_config_t master_config;
2599 lsm6dsl_int1_ctrl_t int1_ctrl;
2600 lsm6dsl_md1_cfg_t md1_cfg;
2601 lsm6dsl_md2_cfg_t md2_cfg;
2602 lsm6dsl_ctrl4_c_t ctrl4_c;
2603 lsm6dsl_tap_cfg_t tap_cfg;
2604 int32_t ret;
2605
2606 ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
2607
2608 if (ret == 0)
2609 {
2610 int1_ctrl.int1_drdy_xl = val.int1_drdy_xl;
2611 int1_ctrl.int1_drdy_g = val.int1_drdy_g;
2612 int1_ctrl.int1_boot = val.int1_boot;
2613 int1_ctrl.int1_fth = val.int1_fth;
2614 int1_ctrl.int1_fifo_ovr = val.int1_fifo_ovr;
2615 int1_ctrl.int1_full_flag = val.int1_full_flag;
2616 int1_ctrl.int1_sign_mot = val.int1_sign_mot;
2617 int1_ctrl.int1_step_detector = val.int1_step_detector;
2618 ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
2619 }
2620
2621 if (ret == 0)
2622 {
2623 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD1_CFG, (uint8_t *)&md1_cfg, 1);
2624 }
2625
2626 if (ret == 0)
2627 {
2628 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2629 }
2630
2631 if (ret == 0)
2632 {
2633 md1_cfg.int1_timer = val.int1_timer;
2634 md1_cfg.int1_tilt = val.int1_tilt;
2635 md1_cfg.int1_6d = val.int1_6d;
2636 md1_cfg.int1_double_tap = val.int1_double_tap;
2637 md1_cfg.int1_ff = val.int1_ff;
2638 md1_cfg.int1_wu = val.int1_wu;
2639 md1_cfg.int1_single_tap = val.int1_single_tap;
2640 md1_cfg.int1_inact_state = val.int1_inact_state;
2641 ret = lsm6dsl_write_reg(ctx, LSM6DSL_MD1_CFG, (uint8_t *)&md1_cfg, 1);
2642 }
2643
2644 if (ret == 0)
2645 {
2646 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2647 }
2648
2649 if (ret == 0)
2650 {
2651 ctrl4_c.den_drdy_int1 = val.den_drdy_int1;
2652 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2653 }
2654
2655 if (ret == 0)
2656 {
2657 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
2658 (uint8_t *)&master_config, 1);
2659 }
2660
2661 if (ret == 0)
2662 {
2663 master_config.drdy_on_int1 = val.den_drdy_int1;
2664 ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG,
2665 (uint8_t *)&master_config, 1);
2666 }
2667
2668 if (ret == 0)
2669 {
2670 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
2671
2672 if ((val.int1_6d != 0x00U) ||
2673 (val.int1_ff != 0x00U) ||
2674 (val.int1_wu != 0x00U) ||
2675 (val.int1_single_tap != 0x00U) ||
2676 (val.int1_double_tap != 0x00U) ||
2677 (val.int1_inact_state != 0x00U) ||
2678 (md2_cfg.int2_6d != 0x00U) ||
2679 (md2_cfg.int2_ff != 0x00U) ||
2680 (md2_cfg.int2_wu != 0x00U) ||
2681 (md2_cfg.int2_single_tap != 0x00U) ||
2682 (md2_cfg.int2_double_tap != 0x00U) ||
2683 (md2_cfg.int2_inact_state != 0x00U))
2684 {
2685 tap_cfg.interrupts_enable = PROPERTY_ENABLE;
2686 }
2687
2688 else
2689 {
2690 tap_cfg.interrupts_enable = PROPERTY_DISABLE;
2691 }
2692 }
2693
2694 if (ret == 0)
2695 {
2696 ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
2697 }
2698
2699 return ret;
2700 }
2701
2702 /**
2703 * @brief Select the signal that need to route on int1 pad[get]
2704 *
2705 * @param ctx Read / write interface definitions
2706 * @param val read INT1_CTRL, MD1_CFG, CTRL4_C(den_drdy_int1),
2707 * MASTER_CONFIG(drdy_on_int1)
2708 * @retval Interface status (MANDATORY: return 0 -> no Error).
2709 *
2710 */
lsm6dsl_pin_int1_route_get(stmdev_ctx_t * ctx,lsm6dsl_int1_route_t * val)2711 int32_t lsm6dsl_pin_int1_route_get(stmdev_ctx_t *ctx,
2712 lsm6dsl_int1_route_t *val)
2713 {
2714 lsm6dsl_master_config_t master_config;
2715 lsm6dsl_int1_ctrl_t int1_ctrl;
2716 lsm6dsl_md1_cfg_t md1_cfg;
2717 lsm6dsl_ctrl4_c_t ctrl4_c;
2718 int32_t ret;
2719
2720 ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT1_CTRL, (uint8_t *)&int1_ctrl, 1);
2721
2722 if (ret == 0)
2723 {
2724 val->int1_drdy_xl = int1_ctrl.int1_drdy_xl;
2725 val->int1_drdy_g = int1_ctrl.int1_drdy_g;
2726 val->int1_boot = int1_ctrl.int1_boot;
2727 val->int1_fth = int1_ctrl.int1_fth;
2728 val->int1_fifo_ovr = int1_ctrl.int1_fifo_ovr;
2729 val->int1_full_flag = int1_ctrl.int1_full_flag;
2730 val->int1_sign_mot = int1_ctrl.int1_sign_mot;
2731 val->int1_step_detector = int1_ctrl.int1_step_detector ;
2732 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD1_CFG, (uint8_t *)&md1_cfg, 1);
2733
2734 if (ret == 0)
2735 {
2736 val->int1_timer = md1_cfg.int1_timer;
2737 val->int1_tilt = md1_cfg.int1_tilt;
2738 val->int1_6d = md1_cfg.int1_6d;
2739 val->int1_double_tap = md1_cfg.int1_double_tap;
2740 val->int1_ff = md1_cfg.int1_ff;
2741 val->int1_wu = md1_cfg.int1_wu;
2742 val->int1_single_tap = md1_cfg.int1_single_tap;
2743 val->int1_inact_state = md1_cfg.int1_inact_state;
2744 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
2745
2746 if (ret == 0)
2747 {
2748 val->den_drdy_int1 = ctrl4_c.den_drdy_int1;
2749 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
2750 (uint8_t *)&master_config, 1);
2751 val->den_drdy_int1 = master_config.drdy_on_int1;
2752 }
2753 }
2754 }
2755
2756 return ret;
2757 }
2758
2759 /**
2760 * @brief Select the signal that need to route on int2 pad[set]
2761 *
2762 * @param ctx Read / write interface definitions
2763 * @param val INT2_CTRL, DRDY_PULSE_CFG(int2_wrist_tilt), MD2_CFG
2764 * @retval Interface status (MANDATORY: return 0 -> no Error).
2765 *
2766 */
lsm6dsl_pin_int2_route_set(stmdev_ctx_t * ctx,lsm6dsl_int2_route_t val)2767 int32_t lsm6dsl_pin_int2_route_set(stmdev_ctx_t *ctx,
2768 lsm6dsl_int2_route_t val)
2769 {
2770 lsm6dsl_int2_ctrl_t int2_ctrl;
2771 lsm6dsl_md1_cfg_t md1_cfg;
2772 lsm6dsl_md2_cfg_t md2_cfg;
2773 lsm6dsl_drdy_pulse_cfg_g_t drdy_pulse_cfg_g;
2774 lsm6dsl_tap_cfg_t tap_cfg;
2775 int32_t ret;
2776
2777 ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2778
2779 if (ret == 0)
2780 {
2781 int2_ctrl.int2_drdy_xl = val.int2_drdy_xl;
2782 int2_ctrl.int2_drdy_g = val.int2_drdy_g;
2783 int2_ctrl.int2_drdy_temp = val.int2_drdy_temp;
2784 int2_ctrl.int2_fth = val.int2_fth;
2785 int2_ctrl.int2_fifo_ovr = val.int2_fifo_ovr;
2786 int2_ctrl.int2_full_flag = val.int2_full_flag;
2787 int2_ctrl.int2_step_count_ov = val.int2_step_count_ov;
2788 int2_ctrl.int2_step_delta = val.int2_step_delta;
2789 ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2790 }
2791
2792 if (ret == 0)
2793 {
2794 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD1_CFG, (uint8_t *)&md1_cfg, 1);
2795 }
2796
2797 if (ret == 0)
2798 {
2799 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2800 }
2801
2802 if (ret == 0)
2803 {
2804 md2_cfg.int2_iron = val.int2_iron;
2805 md2_cfg.int2_tilt = val.int2_tilt;
2806 md2_cfg.int2_6d = val.int2_6d;
2807 md2_cfg.int2_double_tap = val.int2_double_tap;
2808 md2_cfg.int2_ff = val.int2_ff;
2809 md2_cfg.int2_wu = val.int2_wu;
2810 md2_cfg.int2_single_tap = val.int2_single_tap;
2811 md2_cfg.int2_inact_state = val.int2_inact_state;
2812 ret = lsm6dsl_write_reg(ctx, LSM6DSL_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2813 }
2814
2815 if (ret == 0)
2816 {
2817 ret = lsm6dsl_read_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G,
2818 (uint8_t *)&drdy_pulse_cfg_g, 1);
2819 }
2820
2821 if (ret == 0)
2822 {
2823 drdy_pulse_cfg_g.int2_wrist_tilt = val.int2_wrist_tilt;
2824 ret = lsm6dsl_write_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G,
2825 (uint8_t *)&drdy_pulse_cfg_g, 1);
2826 }
2827
2828 if (ret == 0)
2829 {
2830 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
2831
2832 if ((md1_cfg.int1_6d != 0x00U) ||
2833 (md1_cfg.int1_ff != 0x00U) ||
2834 (md1_cfg.int1_wu != 0x00U) ||
2835 (md1_cfg.int1_single_tap != 0x00U) ||
2836 (md1_cfg.int1_double_tap != 0x00U) ||
2837 (md1_cfg.int1_inact_state != 0x00U) ||
2838 (val.int2_6d != 0x00U) ||
2839 (val.int2_ff != 0x00U) ||
2840 (val.int2_wu != 0x00U) ||
2841 (val.int2_single_tap != 0x00U) ||
2842 (val.int2_double_tap != 0x00U) ||
2843 (val.int2_inact_state != 0x00U))
2844 {
2845 tap_cfg.interrupts_enable = PROPERTY_ENABLE;
2846 }
2847
2848 else
2849 {
2850 tap_cfg.interrupts_enable = PROPERTY_DISABLE;
2851 }
2852 }
2853
2854 if (ret == 0)
2855 {
2856 ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
2857 }
2858
2859 return ret;
2860 }
2861
2862 /**
2863 * @brief Select the signal that need to route on int2 pad[get]
2864 *
2865 * @param ctx Read / write interface definitions
2866 * @param val INT2_CTRL, DRDY_PULSE_CFG(int2_wrist_tilt), MD2_CFG
2867 * @retval Interface status (MANDATORY: return 0 -> no Error).
2868 *
2869 */
lsm6dsl_pin_int2_route_get(stmdev_ctx_t * ctx,lsm6dsl_int2_route_t * val)2870 int32_t lsm6dsl_pin_int2_route_get(stmdev_ctx_t *ctx,
2871 lsm6dsl_int2_route_t *val)
2872 {
2873 lsm6dsl_int2_ctrl_t int2_ctrl;
2874 lsm6dsl_md2_cfg_t md2_cfg;
2875 lsm6dsl_drdy_pulse_cfg_g_t drdy_pulse_cfg_g;
2876 int32_t ret;
2877
2878 ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT2_CTRL, (uint8_t *)&int2_ctrl, 1);
2879
2880 if (ret == 0)
2881 {
2882 val->int2_drdy_xl = int2_ctrl.int2_drdy_xl;
2883 val->int2_drdy_g = int2_ctrl.int2_drdy_g;
2884 val->int2_drdy_temp = int2_ctrl.int2_drdy_temp;
2885 val->int2_fth = int2_ctrl.int2_fth;
2886 val->int2_fifo_ovr = int2_ctrl.int2_fifo_ovr;
2887 val->int2_full_flag = int2_ctrl.int2_full_flag;
2888 val->int2_step_count_ov = int2_ctrl.int2_step_count_ov;
2889 val->int2_step_delta = int2_ctrl.int2_step_delta;
2890 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MD2_CFG, (uint8_t *)&md2_cfg, 1);
2891
2892 if (ret == 0)
2893 {
2894 val->int2_iron = md2_cfg.int2_iron;
2895 val->int2_tilt = md2_cfg.int2_tilt;
2896 val->int2_6d = md2_cfg.int2_6d;
2897 val->int2_double_tap = md2_cfg.int2_double_tap;
2898 val->int2_ff = md2_cfg.int2_ff;
2899 val->int2_wu = md2_cfg.int2_wu;
2900 val->int2_single_tap = md2_cfg.int2_single_tap;
2901 val->int2_inact_state = md2_cfg.int2_inact_state;
2902 ret = lsm6dsl_read_reg(ctx, LSM6DSL_DRDY_PULSE_CFG_G,
2903 (uint8_t *)&drdy_pulse_cfg_g, 1);
2904 val->int2_wrist_tilt = drdy_pulse_cfg_g.int2_wrist_tilt;
2905 }
2906 }
2907
2908 return ret;
2909 }
2910
2911 /**
2912 * @brief Push-pull/open drain selection on interrupt pads.[set]
2913 *
2914 * @param ctx Read / write interface definitions
2915 * @param val Change the values of pp_od in reg CTRL3_C
2916 * @retval Interface status (MANDATORY: return 0 -> no Error).
2917 *
2918 */
lsm6dsl_pin_mode_set(stmdev_ctx_t * ctx,lsm6dsl_pp_od_t val)2919 int32_t lsm6dsl_pin_mode_set(stmdev_ctx_t *ctx, lsm6dsl_pp_od_t val)
2920 {
2921 lsm6dsl_ctrl3_c_t ctrl3_c;
2922 int32_t ret;
2923
2924 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2925
2926 if (ret == 0)
2927 {
2928 ctrl3_c.pp_od = (uint8_t) val;
2929 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2930 }
2931
2932 return ret;
2933 }
2934
2935 /**
2936 * @brief Push-pull/open drain selection on interrupt pads.[get]
2937 *
2938 * @param ctx Read / write interface definitions
2939 * @param val Get the values of pp_od in reg CTRL3_C
2940 * @retval Interface status (MANDATORY: return 0 -> no Error).
2941 *
2942 */
lsm6dsl_pin_mode_get(stmdev_ctx_t * ctx,lsm6dsl_pp_od_t * val)2943 int32_t lsm6dsl_pin_mode_get(stmdev_ctx_t *ctx, lsm6dsl_pp_od_t *val)
2944 {
2945 lsm6dsl_ctrl3_c_t ctrl3_c;
2946 int32_t ret;
2947
2948 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2949
2950 switch (ctrl3_c.pp_od)
2951 {
2952 case LSM6DSL_PUSH_PULL:
2953 *val = LSM6DSL_PUSH_PULL;
2954 break;
2955
2956 case LSM6DSL_OPEN_DRAIN:
2957 *val = LSM6DSL_OPEN_DRAIN;
2958 break;
2959
2960 default:
2961 *val = LSM6DSL_PIN_MODE_ND;
2962 break;
2963 }
2964
2965 return ret;
2966 }
2967
2968 /**
2969 * @brief Interrupt active-high/low.[set]
2970 *
2971 * @param ctx Read / write interface definitions
2972 * @param val Change the values of h_lactive in reg CTRL3_C
2973 * @retval Interface status (MANDATORY: return 0 -> no Error).
2974 *
2975 */
lsm6dsl_pin_polarity_set(stmdev_ctx_t * ctx,lsm6dsl_h_lactive_t val)2976 int32_t lsm6dsl_pin_polarity_set(stmdev_ctx_t *ctx,
2977 lsm6dsl_h_lactive_t val)
2978 {
2979 lsm6dsl_ctrl3_c_t ctrl3_c;
2980 int32_t ret;
2981
2982 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2983
2984 if (ret == 0)
2985 {
2986 ctrl3_c.h_lactive = (uint8_t) val;
2987 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
2988 }
2989
2990 return ret;
2991 }
2992
2993 /**
2994 * @brief Interrupt active-high/low.[get]
2995 *
2996 * @param ctx Read / write interface definitions
2997 * @param val Get the values of h_lactive in reg CTRL3_C
2998 * @retval Interface status (MANDATORY: return 0 -> no Error).
2999 *
3000 */
lsm6dsl_pin_polarity_get(stmdev_ctx_t * ctx,lsm6dsl_h_lactive_t * val)3001 int32_t lsm6dsl_pin_polarity_get(stmdev_ctx_t *ctx,
3002 lsm6dsl_h_lactive_t *val)
3003 {
3004 lsm6dsl_ctrl3_c_t ctrl3_c;
3005 int32_t ret;
3006
3007 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL3_C, (uint8_t *)&ctrl3_c, 1);
3008
3009 switch (ctrl3_c.h_lactive)
3010 {
3011 case LSM6DSL_ACTIVE_HIGH:
3012 *val = LSM6DSL_ACTIVE_HIGH;
3013 break;
3014
3015 case LSM6DSL_ACTIVE_LOW:
3016 *val = LSM6DSL_ACTIVE_LOW;
3017 break;
3018
3019 default:
3020 *val = LSM6DSL_POLARITY_ND;
3021 break;
3022 }
3023
3024 return ret;
3025 }
3026
3027 /**
3028 * @brief All interrupt signals become available on INT1 pin.[set]
3029 *
3030 * @param ctx Read / write interface definitions
3031 * @param val Change the values of int2_on_int1 in reg CTRL4_C
3032 * @retval Interface status (MANDATORY: return 0 -> no Error).
3033 *
3034 */
lsm6dsl_all_on_int1_set(stmdev_ctx_t * ctx,uint8_t val)3035 int32_t lsm6dsl_all_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
3036 {
3037 lsm6dsl_ctrl4_c_t ctrl4_c;
3038 int32_t ret;
3039
3040 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3041
3042 if (ret == 0)
3043 {
3044 ctrl4_c.int2_on_int1 = val;
3045 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3046 }
3047
3048 return ret;
3049 }
3050
3051 /**
3052 * @brief All interrupt signals become available on INT1 pin.[get]
3053 *
3054 * @param ctx Read / write interface definitions
3055 * @param val Change the values of int2_on_int1 in reg CTRL4_C
3056 * @retval Interface status (MANDATORY: return 0 -> no Error).
3057 *
3058 */
lsm6dsl_all_on_int1_get(stmdev_ctx_t * ctx,uint8_t * val)3059 int32_t lsm6dsl_all_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
3060 {
3061 lsm6dsl_ctrl4_c_t ctrl4_c;
3062 int32_t ret;
3063
3064 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3065 *val = ctrl4_c.int2_on_int1;
3066
3067 return ret;
3068 }
3069
3070 /**
3071 * @brief Latched/pulsed interrupt.[set]
3072 *
3073 * @param ctx Read / write interface definitions
3074 * @param val Change the values of lir in reg TAP_CFG
3075 * @retval Interface status (MANDATORY: return 0 -> no Error).
3076 *
3077 */
lsm6dsl_int_notification_set(stmdev_ctx_t * ctx,lsm6dsl_lir_t val)3078 int32_t lsm6dsl_int_notification_set(stmdev_ctx_t *ctx,
3079 lsm6dsl_lir_t val)
3080 {
3081 lsm6dsl_tap_cfg_t tap_cfg;
3082 int32_t ret;
3083
3084 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3085
3086 if (ret == 0)
3087 {
3088 tap_cfg.lir = (uint8_t) val;
3089 ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3090 }
3091
3092 return ret;
3093 }
3094
3095 /**
3096 * @brief Latched/pulsed interrupt.[get]
3097 *
3098 * @param ctx Read / write interface definitions
3099 * @param val Get the values of lir in reg TAP_CFG
3100 * @retval Interface status (MANDATORY: return 0 -> no Error).
3101 *
3102 */
lsm6dsl_int_notification_get(stmdev_ctx_t * ctx,lsm6dsl_lir_t * val)3103 int32_t lsm6dsl_int_notification_get(stmdev_ctx_t *ctx,
3104 lsm6dsl_lir_t *val)
3105 {
3106 lsm6dsl_tap_cfg_t tap_cfg;
3107 int32_t ret;
3108
3109 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3110
3111 switch (tap_cfg.lir)
3112 {
3113 case LSM6DSL_INT_PULSED:
3114 *val = LSM6DSL_INT_PULSED;
3115 break;
3116
3117 case LSM6DSL_INT_LATCHED:
3118 *val = LSM6DSL_INT_LATCHED;
3119 break;
3120
3121 default:
3122 *val = LSM6DSL_INT_MODE;
3123 break;
3124 }
3125
3126 return ret;
3127 }
3128
3129 /**
3130 * @}
3131 *
3132 */
3133
3134 /**
3135 * @defgroup LSM6DSL_Wake_Up_event
3136 * @brief This section groups all the functions that manage the
3137 * Wake Up event generation.
3138 * @{
3139 *
3140 */
3141
3142 /**
3143 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set]
3144 *
3145 * @param ctx Read / write interface definitions
3146 * @param val Change the values of wk_ths in reg WAKE_UP_THS
3147 * @retval Interface status (MANDATORY: return 0 -> no Error).
3148 *
3149 */
lsm6dsl_wkup_threshold_set(stmdev_ctx_t * ctx,uint8_t val)3150 int32_t lsm6dsl_wkup_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
3151 {
3152 lsm6dsl_wake_up_ths_t wake_up_ths;
3153 int32_t ret;
3154
3155 ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_THS,
3156 (uint8_t *)&wake_up_ths, 1);
3157
3158 if (ret == 0)
3159 {
3160 wake_up_ths.wk_ths = val;
3161 ret = lsm6dsl_write_reg(ctx, LSM6DSL_WAKE_UP_THS,
3162 (uint8_t *)&wake_up_ths, 1);
3163 }
3164
3165 return ret;
3166 }
3167
3168 /**
3169 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get]
3170 *
3171 * @param ctx Read / write interface definitions
3172 * @param val Change the values of wk_ths in reg WAKE_UP_THS
3173 * @retval Interface status (MANDATORY: return 0 -> no Error).
3174 *
3175 */
lsm6dsl_wkup_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)3176 int32_t lsm6dsl_wkup_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
3177 {
3178 lsm6dsl_wake_up_ths_t wake_up_ths;
3179 int32_t ret;
3180
3181 ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_THS,
3182 (uint8_t *)&wake_up_ths, 1);
3183 *val = wake_up_ths.wk_ths;
3184
3185 return ret;
3186 }
3187
3188 /**
3189 * @brief Wake up duration event.1LSb = 1 / ODR[set]
3190 *
3191 * @param ctx Read / write interface definitions
3192 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
3193 * @retval Interface status (MANDATORY: return 0 -> no Error).
3194 *
3195 */
lsm6dsl_wkup_dur_set(stmdev_ctx_t * ctx,uint8_t val)3196 int32_t lsm6dsl_wkup_dur_set(stmdev_ctx_t *ctx, uint8_t val)
3197 {
3198 lsm6dsl_wake_up_dur_t wake_up_dur;
3199 int32_t ret;
3200
3201 ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR,
3202 (uint8_t *)&wake_up_dur, 1);
3203
3204 if (ret == 0)
3205 {
3206 wake_up_dur.wake_dur = val;
3207 ret = lsm6dsl_write_reg(ctx, LSM6DSL_WAKE_UP_DUR,
3208 (uint8_t *)&wake_up_dur, 1);
3209 }
3210
3211 return ret;
3212 }
3213
3214 /**
3215 * @brief Wake up duration event.1LSb = 1 / ODR[get]
3216 *
3217 * @param ctx Read / write interface definitions
3218 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
3219 * @retval Interface status (MANDATORY: return 0 -> no Error).
3220 *
3221 */
lsm6dsl_wkup_dur_get(stmdev_ctx_t * ctx,uint8_t * val)3222 int32_t lsm6dsl_wkup_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
3223 {
3224 lsm6dsl_wake_up_dur_t wake_up_dur;
3225 int32_t ret;
3226
3227 ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR,
3228 (uint8_t *)&wake_up_dur, 1);
3229 *val = wake_up_dur.wake_dur;
3230
3231 return ret;
3232 }
3233
3234 /**
3235 * @}
3236 *
3237 */
3238
3239 /**
3240 * @defgroup LSM6DSL_Activity/Inactivity_detection
3241 * @brief This section groups all the functions concerning
3242 * activity/inactivity detection.
3243 * @{
3244 *
3245 */
3246
3247 /**
3248 * @brief Enables gyroscope Sleep mode.[set]
3249 *
3250 * @param ctx Read / write interface definitions
3251 * @param val Change the values of sleep in reg CTRL4_C
3252 * @retval Interface status (MANDATORY: return 0 -> no Error).
3253 *
3254 */
lsm6dsl_gy_sleep_mode_set(stmdev_ctx_t * ctx,uint8_t val)3255 int32_t lsm6dsl_gy_sleep_mode_set(stmdev_ctx_t *ctx, uint8_t val)
3256 {
3257 lsm6dsl_ctrl4_c_t ctrl4_c;
3258 int32_t ret;
3259
3260 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3261
3262 if (ret == 0)
3263 {
3264 ctrl4_c.sleep = val;
3265 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3266 }
3267
3268 return ret;
3269 }
3270
3271 /**
3272 * @brief Enables gyroscope Sleep mode.[get]
3273 *
3274 * @param ctx Read / write interface definitions
3275 * @param val Change the values of sleep in reg CTRL4_C
3276 * @retval Interface status (MANDATORY: return 0 -> no Error).
3277 *
3278 */
lsm6dsl_gy_sleep_mode_get(stmdev_ctx_t * ctx,uint8_t * val)3279 int32_t lsm6dsl_gy_sleep_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
3280 {
3281 lsm6dsl_ctrl4_c_t ctrl4_c;
3282 int32_t ret;
3283
3284 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
3285 *val = ctrl4_c.sleep;
3286
3287 return ret;
3288 }
3289
3290 /**
3291 * @brief Enable inactivity function.[set]
3292 *
3293 * @param ctx Read / write interface definitions
3294 * @param val Change the values of inact_en in reg TAP_CFG
3295 * @retval Interface status (MANDATORY: return 0 -> no Error).
3296 *
3297 */
lsm6dsl_act_mode_set(stmdev_ctx_t * ctx,lsm6dsl_inact_en_t val)3298 int32_t lsm6dsl_act_mode_set(stmdev_ctx_t *ctx,
3299 lsm6dsl_inact_en_t val)
3300 {
3301 lsm6dsl_tap_cfg_t tap_cfg;
3302 int32_t ret;
3303
3304 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3305
3306 if (ret == 0)
3307 {
3308 tap_cfg.inact_en = (uint8_t) val;
3309 ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3310 }
3311
3312 return ret;
3313 }
3314
3315 /**
3316 * @brief Enable inactivity function.[get]
3317 *
3318 * @param ctx Read / write interface definitions
3319 * @param val Get the values of inact_en in reg TAP_CFG
3320 * @retval Interface status (MANDATORY: return 0 -> no Error).
3321 *
3322 */
lsm6dsl_act_mode_get(stmdev_ctx_t * ctx,lsm6dsl_inact_en_t * val)3323 int32_t lsm6dsl_act_mode_get(stmdev_ctx_t *ctx,
3324 lsm6dsl_inact_en_t *val)
3325 {
3326 lsm6dsl_tap_cfg_t tap_cfg;
3327 int32_t ret;
3328
3329 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3330
3331 switch (tap_cfg.inact_en)
3332 {
3333 case LSM6DSL_PROPERTY_DISABLE:
3334 *val = LSM6DSL_PROPERTY_DISABLE;
3335 break;
3336
3337 case LSM6DSL_XL_12Hz5_GY_NOT_AFFECTED:
3338 *val = LSM6DSL_XL_12Hz5_GY_NOT_AFFECTED;
3339 break;
3340
3341 case LSM6DSL_XL_12Hz5_GY_SLEEP:
3342 *val = LSM6DSL_XL_12Hz5_GY_SLEEP;
3343 break;
3344
3345 case LSM6DSL_XL_12Hz5_GY_PD:
3346 *val = LSM6DSL_XL_12Hz5_GY_PD;
3347 break;
3348
3349 default:
3350 *val = LSM6DSL_ACT_MODE_ND;
3351 break;
3352 }
3353
3354 return ret;
3355 }
3356
3357 /**
3358 * @brief Duration to go in sleep mode.1 LSb = 512 / ODR[set]
3359 *
3360 * @param ctx Read / write interface definitions
3361 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
3362 * @retval Interface status (MANDATORY: return 0 -> no Error).
3363 *
3364 */
lsm6dsl_act_sleep_dur_set(stmdev_ctx_t * ctx,uint8_t val)3365 int32_t lsm6dsl_act_sleep_dur_set(stmdev_ctx_t *ctx, uint8_t val)
3366 {
3367 lsm6dsl_wake_up_dur_t wake_up_dur;
3368 int32_t ret;
3369
3370 ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR,
3371 (uint8_t *)&wake_up_dur, 1);
3372
3373 if (ret == 0)
3374 {
3375 wake_up_dur.sleep_dur = val;
3376 ret = lsm6dsl_write_reg(ctx, LSM6DSL_WAKE_UP_DUR,
3377 (uint8_t *)&wake_up_dur, 1);
3378 }
3379
3380 return ret;
3381 }
3382
3383 /**
3384 * @brief Duration to go in sleep mode. 1 LSb = 512 / ODR[get]
3385 *
3386 * @param ctx Read / write interface definitions
3387 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
3388 * @retval Interface status (MANDATORY: return 0 -> no Error).
3389 *
3390 */
lsm6dsl_act_sleep_dur_get(stmdev_ctx_t * ctx,uint8_t * val)3391 int32_t lsm6dsl_act_sleep_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
3392 {
3393 lsm6dsl_wake_up_dur_t wake_up_dur;
3394 int32_t ret;
3395
3396 ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR,
3397 (uint8_t *)&wake_up_dur, 1);
3398 *val = wake_up_dur.sleep_dur;
3399
3400 return ret;
3401 }
3402
3403 /**
3404 * @}
3405 *
3406 */
3407
3408 /**
3409 * @defgroup LSM6DSL_tap_generator
3410 * @brief This section groups all the functions that manage the
3411 * tap and double tap event generation.
3412 * @{
3413 *
3414 */
3415
3416 /**
3417 * @brief Read the tap / double tap source register.[get]
3418 *
3419 * @param ctx Read / write interface definitions
3420 * @param val Structure of registers from TAP_SRC
3421 * @retval Interface status (MANDATORY: return 0 -> no Error).
3422 *
3423 */
lsm6dsl_tap_src_get(stmdev_ctx_t * ctx,lsm6dsl_tap_src_t * val)3424 int32_t lsm6dsl_tap_src_get(stmdev_ctx_t *ctx, lsm6dsl_tap_src_t *val)
3425 {
3426 int32_t ret;
3427
3428 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_SRC, (uint8_t *) val, 1);
3429
3430 return ret;
3431 }
3432
3433 /**
3434 * @brief Enable Z direction in tap recognition.[set]
3435 *
3436 * @param ctx Read / write interface definitions
3437 * @param val Change the values of tap_z_en in reg TAP_CFG
3438 *
3439 */
lsm6dsl_tap_detection_on_z_set(stmdev_ctx_t * ctx,uint8_t val)3440 int32_t lsm6dsl_tap_detection_on_z_set(stmdev_ctx_t *ctx, uint8_t val)
3441 {
3442 lsm6dsl_tap_cfg_t tap_cfg;
3443 int32_t ret;
3444
3445 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3446
3447 if (ret == 0)
3448 {
3449 tap_cfg.tap_z_en = val;
3450 ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3451 }
3452
3453 return ret;
3454 }
3455
3456 /**
3457 * @brief Enable Z direction in tap recognition.[get]
3458 *
3459 * @param ctx Read / write interface definitions
3460 * @param val Change the values of tap_z_en in reg TAP_CFG
3461 * @retval Interface status (MANDATORY: return 0 -> no Error).
3462 *
3463 */
lsm6dsl_tap_detection_on_z_get(stmdev_ctx_t * ctx,uint8_t * val)3464 int32_t lsm6dsl_tap_detection_on_z_get(stmdev_ctx_t *ctx,
3465 uint8_t *val)
3466 {
3467 lsm6dsl_tap_cfg_t tap_cfg;
3468 int32_t ret;
3469
3470 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3471 *val = tap_cfg.tap_z_en;
3472
3473 return ret;
3474 }
3475
3476 /**
3477 * @brief Enable Y direction in tap recognition.[set]
3478 *
3479 * @param ctx Read / write interface definitions
3480 * @param val Change the values of tap_y_en in reg TAP_CFG
3481 * @retval Interface status (MANDATORY: return 0 -> no Error).
3482 *
3483 */
lsm6dsl_tap_detection_on_y_set(stmdev_ctx_t * ctx,uint8_t val)3484 int32_t lsm6dsl_tap_detection_on_y_set(stmdev_ctx_t *ctx, uint8_t val)
3485 {
3486 lsm6dsl_tap_cfg_t tap_cfg;
3487 int32_t ret;
3488
3489 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3490
3491 if (ret == 0)
3492 {
3493 tap_cfg.tap_y_en = val;
3494 ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3495 }
3496
3497 return ret;
3498 }
3499
3500 /**
3501 * @brief Enable Y direction in tap recognition.[get]
3502 *
3503 * @param ctx Read / write interface definitions
3504 * @param val Change the values of tap_y_en in reg TAP_CFG
3505 * @retval Interface status (MANDATORY: return 0 -> no Error).
3506 *
3507 */
lsm6dsl_tap_detection_on_y_get(stmdev_ctx_t * ctx,uint8_t * val)3508 int32_t lsm6dsl_tap_detection_on_y_get(stmdev_ctx_t *ctx,
3509 uint8_t *val)
3510 {
3511 lsm6dsl_tap_cfg_t tap_cfg;
3512 int32_t ret;
3513
3514 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3515 *val = tap_cfg.tap_y_en;
3516
3517 return ret;
3518 }
3519
3520 /**
3521 * @brief Enable X direction in tap recognition.[set]
3522 *
3523 * @param ctx Read / write interface definitions
3524 * @param val Change the values of tap_x_en in reg TAP_CFG
3525 * @retval Interface status (MANDATORY: return 0 -> no Error).
3526 *
3527 */
lsm6dsl_tap_detection_on_x_set(stmdev_ctx_t * ctx,uint8_t val)3528 int32_t lsm6dsl_tap_detection_on_x_set(stmdev_ctx_t *ctx, uint8_t val)
3529 {
3530 lsm6dsl_tap_cfg_t tap_cfg;
3531 int32_t ret;
3532
3533 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3534
3535 if (ret == 0)
3536 {
3537 tap_cfg.tap_x_en = val;
3538 ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3539 }
3540
3541 return ret;
3542 }
3543
3544 /**
3545 * @brief Enable X direction in tap recognition.[get]
3546 *
3547 * @param ctx Read / write interface definitions
3548 * @param val Change the values of tap_x_en in reg TAP_CFG
3549 * @retval Interface status (MANDATORY: return 0 -> no Error).
3550 *
3551 */
lsm6dsl_tap_detection_on_x_get(stmdev_ctx_t * ctx,uint8_t * val)3552 int32_t lsm6dsl_tap_detection_on_x_get(stmdev_ctx_t *ctx,
3553 uint8_t *val)
3554 {
3555 lsm6dsl_tap_cfg_t tap_cfg;
3556 int32_t ret;
3557
3558 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_CFG, (uint8_t *)&tap_cfg, 1);
3559 *val = tap_cfg.tap_x_en;
3560
3561 return ret;
3562 }
3563
3564 /**
3565 * @brief Threshold for tap recognition.[set]
3566 *
3567 * @param ctx Read / write interface definitions
3568 * @param val Change the values of tap_ths in reg TAP_THS_6D
3569 * @retval Interface status (MANDATORY: return 0 -> no Error).
3570 *
3571 */
lsm6dsl_tap_threshold_x_set(stmdev_ctx_t * ctx,uint8_t val)3572 int32_t lsm6dsl_tap_threshold_x_set(stmdev_ctx_t *ctx, uint8_t val)
3573 {
3574 lsm6dsl_tap_ths_6d_t tap_ths_6d;
3575 int32_t ret;
3576
3577 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D,
3578 (uint8_t *)&tap_ths_6d, 1);
3579
3580 if (ret == 0)
3581 {
3582 tap_ths_6d.tap_ths = val;
3583 ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_THS_6D,
3584 (uint8_t *)&tap_ths_6d, 1);
3585 }
3586
3587 return ret;
3588 }
3589
3590 /**
3591 * @brief Threshold for tap recognition.[get]
3592 *
3593 * @param ctx Read / write interface definitions
3594 * @param val Change the values of tap_ths in reg TAP_THS_6D
3595 * @retval Interface status (MANDATORY: return 0 -> no Error).
3596 *
3597 */
lsm6dsl_tap_threshold_x_get(stmdev_ctx_t * ctx,uint8_t * val)3598 int32_t lsm6dsl_tap_threshold_x_get(stmdev_ctx_t *ctx, uint8_t *val)
3599 {
3600 lsm6dsl_tap_ths_6d_t tap_ths_6d;
3601 int32_t ret;
3602
3603 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D,
3604 (uint8_t *)&tap_ths_6d, 1);
3605 *val = tap_ths_6d.tap_ths;
3606
3607 return ret;
3608 }
3609
3610 /**
3611 * @brief Maximum duration is the maximum time of an overthreshold signal
3612 * detection to be recognized as a tap event.
3613 * The default value of these bits is 00b which corresponds to
3614 * 4*ODR_XL time.
3615 * If the SHOCK[1:0] bits are set to a different
3616 * value, 1LSB corresponds to 8*ODR_XL time.[set]
3617 *
3618 * @param ctx Read / write interface definitions
3619 * @param val Change the values of shock in reg INT_DUR2
3620 * @retval Interface status (MANDATORY: return 0 -> no Error).
3621 *
3622 */
lsm6dsl_tap_shock_set(stmdev_ctx_t * ctx,uint8_t val)3623 int32_t lsm6dsl_tap_shock_set(stmdev_ctx_t *ctx, uint8_t val)
3624 {
3625 lsm6dsl_int_dur2_t int_dur2;
3626 int32_t ret;
3627
3628 ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1);
3629
3630 if (ret == 0)
3631 {
3632 int_dur2.shock = val;
3633 ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1);
3634 }
3635
3636 return ret;
3637 }
3638
3639 /**
3640 * @brief Maximum duration is the maximum time of an overthreshold signal
3641 * detection to be recognized as a tap event.
3642 * The default value of these bits is 00b which corresponds to
3643 * 4*ODR_XL time.
3644 * If the SHOCK[1:0] bits are set to a different value, 1LSB
3645 * corresponds to 8*ODR_XL time.[get]
3646 *
3647 * @param ctx Read / write interface definitions
3648 * @param val Change the values of shock in reg INT_DUR2
3649 * @retval Interface status (MANDATORY: return 0 -> no Error).
3650 *
3651 */
lsm6dsl_tap_shock_get(stmdev_ctx_t * ctx,uint8_t * val)3652 int32_t lsm6dsl_tap_shock_get(stmdev_ctx_t *ctx, uint8_t *val)
3653 {
3654 lsm6dsl_int_dur2_t int_dur2;
3655 int32_t ret;
3656
3657 ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1);
3658 *val = int_dur2.shock;
3659
3660 return ret;
3661 }
3662
3663 /**
3664 * @brief Quiet time is the time after the first detected tap in which there
3665 * must not be any overthreshold event.
3666 * The default value of these bits is 00b which corresponds to
3667 * 2*ODR_XL time.
3668 * If the QUIET[1:0] bits are set to a different value, 1LSB
3669 * corresponds to 4*ODR_XL time.[set]
3670 *
3671 * @param ctx Read / write interface definitions
3672 * @param val Change the values of quiet in reg INT_DUR2
3673 * @retval Interface status (MANDATORY: return 0 -> no Error).
3674 *
3675 */
lsm6dsl_tap_quiet_set(stmdev_ctx_t * ctx,uint8_t val)3676 int32_t lsm6dsl_tap_quiet_set(stmdev_ctx_t *ctx, uint8_t val)
3677 {
3678 lsm6dsl_int_dur2_t int_dur2;
3679 int32_t ret;
3680
3681 ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1);
3682
3683 if (ret == 0)
3684 {
3685 int_dur2.quiet = val;
3686 ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1);
3687 }
3688
3689 return ret;
3690 }
3691
3692 /**
3693 * @brief Quiet time is the time after the first detected tap in which there
3694 * must not be any overthreshold event.
3695 * The default value of these bits is 00b which corresponds to
3696 * 2*ODR_XL time.
3697 * If the QUIET[1:0] bits are set to a different value, 1LSB
3698 * corresponds to 4*ODR_XL time.[get]
3699 *
3700 * @param ctx Read / write interface definitions
3701 * @param val Change the values of quiet in reg INT_DUR2
3702 * @retval Interface status (MANDATORY: return 0 -> no Error).
3703 *
3704 */
lsm6dsl_tap_quiet_get(stmdev_ctx_t * ctx,uint8_t * val)3705 int32_t lsm6dsl_tap_quiet_get(stmdev_ctx_t *ctx, uint8_t *val)
3706 {
3707 lsm6dsl_int_dur2_t int_dur2;
3708 int32_t ret;
3709
3710 ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1);
3711 *val = int_dur2.quiet;
3712
3713 return ret;
3714 }
3715
3716 /**
3717 * @brief When double tap recognition is enabled, this register expresses the
3718 * maximum time between two consecutive detected taps to determine a
3719 * double tap event.
3720 * The default value of these bits is 0000b which corresponds to
3721 * 16*ODR_XL time.
3722 * If the DUR[3:0] bits are set to a different value,1LSB corresponds
3723 * to 32*ODR_XL time.[set]
3724 *
3725 * @param ctx Read / write interface definitions
3726 * @param val Change the values of dur in reg INT_DUR2
3727 * @retval Interface status (MANDATORY: return 0 -> no Error).
3728 *
3729 */
lsm6dsl_tap_dur_set(stmdev_ctx_t * ctx,uint8_t val)3730 int32_t lsm6dsl_tap_dur_set(stmdev_ctx_t *ctx, uint8_t val)
3731 {
3732 lsm6dsl_int_dur2_t int_dur2;
3733 int32_t ret;
3734
3735 ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1);
3736
3737 if (ret == 0)
3738 {
3739 int_dur2.dur = val;
3740 ret = lsm6dsl_write_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1);
3741 }
3742
3743 return ret;
3744 }
3745
3746 /**
3747 * @brief When double tap recognition is enabled, this register expresses the
3748 * maximum time between two consecutive detected taps to determine a
3749 * double tap event.
3750 * The default value of these bits is 0000b which corresponds to
3751 * 16*ODR_XL time.
3752 * If the DUR[3:0] bits are set to a different value,1LSB corresponds
3753 * to 32*ODR_XL time.[get]
3754 *
3755 * @param ctx Read / write interface definitions
3756 * @param val Change the values of dur in reg INT_DUR2
3757 * @retval Interface status (MANDATORY: return 0 -> no Error).
3758 *
3759 */
lsm6dsl_tap_dur_get(stmdev_ctx_t * ctx,uint8_t * val)3760 int32_t lsm6dsl_tap_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
3761 {
3762 lsm6dsl_int_dur2_t int_dur2;
3763 int32_t ret;
3764
3765 ret = lsm6dsl_read_reg(ctx, LSM6DSL_INT_DUR2, (uint8_t *)&int_dur2, 1);
3766 *val = int_dur2.dur;
3767
3768 return ret;
3769 }
3770
3771 /**
3772 * @brief Single/double-tap event enable/disable.[set]
3773 *
3774 * @param ctx Read / write interface definitions
3775 * @param val Change the values of
3776 * single_double_tap in reg WAKE_UP_THS
3777 * @retval Interface status (MANDATORY: return 0 -> no Error).
3778 *
3779 */
lsm6dsl_tap_mode_set(stmdev_ctx_t * ctx,lsm6dsl_single_double_tap_t val)3780 int32_t lsm6dsl_tap_mode_set(stmdev_ctx_t *ctx,
3781 lsm6dsl_single_double_tap_t val)
3782 {
3783 lsm6dsl_wake_up_ths_t wake_up_ths;
3784 int32_t ret;
3785
3786 ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_THS,
3787 (uint8_t *)&wake_up_ths, 1);
3788
3789 if (ret == 0)
3790 {
3791 wake_up_ths.single_double_tap = (uint8_t) val;
3792 ret = lsm6dsl_write_reg(ctx, LSM6DSL_WAKE_UP_THS,
3793 (uint8_t *)&wake_up_ths, 1);
3794 }
3795
3796 return ret;
3797 }
3798
3799 /**
3800 * @brief Single/double-tap event enable/disable.[get]
3801 *
3802 * @param ctx Read / write interface definitions
3803 * @param val Get the values of single_double_tap
3804 * in reg WAKE_UP_THS
3805 * @retval Interface status (MANDATORY: return 0 -> no Error).
3806 *
3807 */
lsm6dsl_tap_mode_get(stmdev_ctx_t * ctx,lsm6dsl_single_double_tap_t * val)3808 int32_t lsm6dsl_tap_mode_get(stmdev_ctx_t *ctx,
3809 lsm6dsl_single_double_tap_t *val)
3810 {
3811 lsm6dsl_wake_up_ths_t wake_up_ths;
3812 int32_t ret;
3813
3814 ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_THS,
3815 (uint8_t *)&wake_up_ths, 1);
3816
3817 switch (wake_up_ths.single_double_tap)
3818 {
3819 case LSM6DSL_ONLY_SINGLE:
3820 *val = LSM6DSL_ONLY_SINGLE;
3821 break;
3822
3823 case LSM6DSL_BOTH_SINGLE_DOUBLE:
3824 *val = LSM6DSL_BOTH_SINGLE_DOUBLE;
3825 break;
3826
3827 default:
3828 *val = LSM6DSL_TAP_MODE_ND;
3829 break;
3830 }
3831
3832 return ret;
3833 }
3834
3835 /**
3836 * @}
3837 *
3838 */
3839
3840 /**
3841 * @defgroup LSM6DSL_ Six_position_detection(6D/4D)
3842 * @brief This section groups all the functions concerning six
3843 * position detection (6D).
3844 * @{
3845 *
3846 */
3847
3848 /**
3849 * @brief LPF2 feed 6D function selection.[set]
3850 *
3851 * @param ctx Read / write interface definitions
3852 * @param val Change the values of low_pass_on_6d in
3853 * reg CTRL8_XL
3854 * @retval Interface status (MANDATORY: return 0 -> no Error).
3855 *
3856 */
lsm6dsl_6d_feed_data_set(stmdev_ctx_t * ctx,lsm6dsl_low_pass_on_6d_t val)3857 int32_t lsm6dsl_6d_feed_data_set(stmdev_ctx_t *ctx,
3858 lsm6dsl_low_pass_on_6d_t val)
3859 {
3860 lsm6dsl_ctrl8_xl_t ctrl8_xl;
3861 int32_t ret;
3862
3863 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
3864
3865 if (ret == 0)
3866 {
3867 ctrl8_xl.low_pass_on_6d = (uint8_t) val;
3868 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
3869 }
3870
3871 return ret;
3872 }
3873
3874 /**
3875 * @brief LPF2 feed 6D function selection.[get]
3876 *
3877 * @param ctx Read / write interface definitions
3878 * @param val Get the values of low_pass_on_6d in reg CTRL8_XL
3879 * @retval Interface status (MANDATORY: return 0 -> no Error).
3880 *
3881 */
lsm6dsl_6d_feed_data_get(stmdev_ctx_t * ctx,lsm6dsl_low_pass_on_6d_t * val)3882 int32_t lsm6dsl_6d_feed_data_get(stmdev_ctx_t *ctx,
3883 lsm6dsl_low_pass_on_6d_t *val)
3884 {
3885 lsm6dsl_ctrl8_xl_t ctrl8_xl;
3886 int32_t ret;
3887
3888 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL8_XL, (uint8_t *)&ctrl8_xl, 1);
3889
3890 switch (ctrl8_xl.low_pass_on_6d)
3891 {
3892 case LSM6DSL_ODR_DIV_2_FEED:
3893 *val = LSM6DSL_ODR_DIV_2_FEED;
3894 break;
3895
3896 case LSM6DSL_LPF2_FEED:
3897 *val = LSM6DSL_LPF2_FEED;
3898 break;
3899
3900 default:
3901 *val = LSM6DSL_6D_FEED_ND;
3902 break;
3903 }
3904
3905 return ret;
3906 }
3907
3908 /**
3909 * @brief Threshold for 4D/6D function.[set]
3910 *
3911 * @param ctx Read / write interface definitions
3912 * @param val Change the values of sixd_ths in reg TAP_THS_6D
3913 * @retval Interface status (MANDATORY: return 0 -> no Error).
3914 *
3915 */
lsm6dsl_6d_threshold_set(stmdev_ctx_t * ctx,lsm6dsl_sixd_ths_t val)3916 int32_t lsm6dsl_6d_threshold_set(stmdev_ctx_t *ctx,
3917 lsm6dsl_sixd_ths_t val)
3918 {
3919 lsm6dsl_tap_ths_6d_t tap_ths_6d;
3920 int32_t ret;
3921
3922 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D,
3923 (uint8_t *)&tap_ths_6d, 1);
3924
3925 if (ret == 0)
3926 {
3927 tap_ths_6d.sixd_ths = (uint8_t) val;
3928 ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_THS_6D,
3929 (uint8_t *)&tap_ths_6d, 1);
3930 }
3931
3932 return ret;
3933 }
3934
3935 /**
3936 * @brief Threshold for 4D/6D function.[get]
3937 *
3938 * @param ctx Read / write interface definitions
3939 * @param val Get the values of sixd_ths in reg TAP_THS_6D
3940 * @retval Interface status (MANDATORY: return 0 -> no Error).
3941 *
3942 */
lsm6dsl_6d_threshold_get(stmdev_ctx_t * ctx,lsm6dsl_sixd_ths_t * val)3943 int32_t lsm6dsl_6d_threshold_get(stmdev_ctx_t *ctx,
3944 lsm6dsl_sixd_ths_t *val)
3945 {
3946 lsm6dsl_tap_ths_6d_t tap_ths_6d;
3947 int32_t ret;
3948
3949 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D,
3950 (uint8_t *)&tap_ths_6d, 1);
3951
3952 switch (tap_ths_6d.sixd_ths)
3953 {
3954 case LSM6DSL_DEG_80:
3955 *val = LSM6DSL_DEG_80;
3956 break;
3957
3958 case LSM6DSL_DEG_70:
3959 *val = LSM6DSL_DEG_70;
3960 break;
3961
3962 case LSM6DSL_DEG_60:
3963 *val = LSM6DSL_DEG_60;
3964 break;
3965
3966 case LSM6DSL_DEG_50:
3967 *val = LSM6DSL_DEG_50;
3968 break;
3969
3970 default:
3971 *val = LSM6DSL_6D_TH_ND;
3972 break;
3973 }
3974
3975 return ret;
3976 }
3977
3978 /**
3979 * @brief 4D orientation detection enable.[set]
3980 *
3981 * @param ctx Read / write interface definitions
3982 * @param val Change the values of d4d_en in reg TAP_THS_6D
3983 * @retval Interface status (MANDATORY: return 0 -> no Error).
3984 *
3985 */
lsm6dsl_4d_mode_set(stmdev_ctx_t * ctx,uint8_t val)3986 int32_t lsm6dsl_4d_mode_set(stmdev_ctx_t *ctx, uint8_t val)
3987 {
3988 lsm6dsl_tap_ths_6d_t tap_ths_6d;
3989 int32_t ret;
3990
3991 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D,
3992 (uint8_t *)&tap_ths_6d, 1);
3993
3994 if (ret == 0)
3995 {
3996 tap_ths_6d.d4d_en = val;
3997 ret = lsm6dsl_write_reg(ctx, LSM6DSL_TAP_THS_6D,
3998 (uint8_t *)&tap_ths_6d, 1);
3999 }
4000
4001 return ret;
4002 }
4003
4004 /**
4005 * @brief 4D orientation detection enable.[get]
4006 *
4007 * @param ctx Read / write interface definitions
4008 * @param val Change the values of d4d_en in reg TAP_THS_6D
4009 * @retval Interface status (MANDATORY: return 0 -> no Error).
4010 *
4011 */
lsm6dsl_4d_mode_get(stmdev_ctx_t * ctx,uint8_t * val)4012 int32_t lsm6dsl_4d_mode_get(stmdev_ctx_t *ctx, uint8_t *val)
4013 {
4014 lsm6dsl_tap_ths_6d_t tap_ths_6d;
4015 int32_t ret;
4016
4017 ret = lsm6dsl_read_reg(ctx, LSM6DSL_TAP_THS_6D,
4018 (uint8_t *)&tap_ths_6d, 1);
4019 *val = tap_ths_6d.d4d_en;
4020
4021 return ret;
4022 }
4023
4024 /**
4025 * @}
4026 *
4027 */
4028
4029 /**
4030 * @defgroup LSM6DSL_free_fall
4031 * @brief This section group all the functions concerning the free
4032 * fall detection.
4033 * @{
4034 *
4035 */
4036
4037 /**
4038 * @brief Free-fall duration event. 1LSb = 1 / ODR[set]
4039 *
4040 * @param ctx Read / write interface definitions
4041 * @param val Change the values of ff_dur in reg WAKE_UP_DUR
4042 * @retval Interface status (MANDATORY: return 0 -> no Error).
4043 *
4044 */
lsm6dsl_ff_dur_set(stmdev_ctx_t * ctx,uint8_t val)4045 int32_t lsm6dsl_ff_dur_set(stmdev_ctx_t *ctx, uint8_t val)
4046 {
4047 lsm6dsl_wake_up_dur_t wake_up_dur;
4048 lsm6dsl_free_fall_t free_fall;
4049 int32_t ret;
4050
4051 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1);
4052
4053 if (ret == 0)
4054 {
4055 free_fall.ff_dur = (val & 0x1FU);
4056 ret = lsm6dsl_write_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1);
4057
4058 if (ret == 0)
4059 {
4060 ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR,
4061 (uint8_t *)&wake_up_dur, 1);
4062
4063 if (ret == 0)
4064 {
4065 wake_up_dur.ff_dur = (val & 0x20U) >> 5;
4066 ret = lsm6dsl_write_reg(ctx, LSM6DSL_WAKE_UP_DUR,
4067 (uint8_t *)&wake_up_dur, 1);
4068 }
4069 }
4070 }
4071
4072 return ret;
4073 }
4074
4075 /**
4076 * @brief Free-fall duration event. 1LSb = 1 / ODR[get]
4077 *
4078 * @param ctx Read / write interface definitions
4079 * @param val Change the values of ff_dur in reg WAKE_UP_DUR
4080 * @retval Interface status (MANDATORY: return 0 -> no Error).
4081 *
4082 */
lsm6dsl_ff_dur_get(stmdev_ctx_t * ctx,uint8_t * val)4083 int32_t lsm6dsl_ff_dur_get(stmdev_ctx_t *ctx, uint8_t *val)
4084 {
4085 lsm6dsl_wake_up_dur_t wake_up_dur;
4086 lsm6dsl_free_fall_t free_fall;
4087 int32_t ret;
4088
4089 ret = lsm6dsl_read_reg(ctx, LSM6DSL_WAKE_UP_DUR,
4090 (uint8_t *)&wake_up_dur, 1);
4091
4092 if (ret == 0)
4093 {
4094 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1);
4095 }
4096
4097 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
4098
4099 return ret;
4100 }
4101
4102 /**
4103 * @brief Free fall threshold setting.[set]
4104 *
4105 * @param ctx Read / write interface definitions
4106 * @param val Change the values of ff_ths in reg FREE_FALL
4107 * @retval Interface status (MANDATORY: return 0 -> no Error).
4108 *
4109 */
lsm6dsl_ff_threshold_set(stmdev_ctx_t * ctx,lsm6dsl_ff_ths_t val)4110 int32_t lsm6dsl_ff_threshold_set(stmdev_ctx_t *ctx,
4111 lsm6dsl_ff_ths_t val)
4112 {
4113 lsm6dsl_free_fall_t free_fall;
4114 int32_t ret;
4115
4116 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1);
4117
4118 if (ret == 0)
4119 {
4120 free_fall.ff_ths = (uint8_t) val;
4121 ret = lsm6dsl_write_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1);
4122 }
4123
4124 return ret;
4125 }
4126
4127 /**
4128 * @brief Free fall threshold setting.[get]
4129 *
4130 * @param ctx Read / write interface definitions
4131 * @param val Get the values of ff_ths in reg FREE_FALL
4132 * @retval Interface status (MANDATORY: return 0 -> no Error).
4133 *
4134 */
lsm6dsl_ff_threshold_get(stmdev_ctx_t * ctx,lsm6dsl_ff_ths_t * val)4135 int32_t lsm6dsl_ff_threshold_get(stmdev_ctx_t *ctx,
4136 lsm6dsl_ff_ths_t *val)
4137 {
4138 lsm6dsl_free_fall_t free_fall;
4139 int32_t ret;
4140
4141 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FREE_FALL, (uint8_t *)&free_fall, 1);
4142
4143 switch (free_fall.ff_ths)
4144 {
4145 case LSM6DSL_FF_TSH_156mg:
4146 *val = LSM6DSL_FF_TSH_156mg;
4147 break;
4148
4149 case LSM6DSL_FF_TSH_219mg:
4150 *val = LSM6DSL_FF_TSH_219mg;
4151 break;
4152
4153 case LSM6DSL_FF_TSH_250mg:
4154 *val = LSM6DSL_FF_TSH_250mg;
4155 break;
4156
4157 case LSM6DSL_FF_TSH_312mg:
4158 *val = LSM6DSL_FF_TSH_312mg;
4159 break;
4160
4161 case LSM6DSL_FF_TSH_344mg:
4162 *val = LSM6DSL_FF_TSH_344mg;
4163 break;
4164
4165 case LSM6DSL_FF_TSH_406mg:
4166 *val = LSM6DSL_FF_TSH_406mg;
4167 break;
4168
4169 case LSM6DSL_FF_TSH_469mg:
4170 *val = LSM6DSL_FF_TSH_469mg;
4171 break;
4172
4173 case LSM6DSL_FF_TSH_500mg:
4174 *val = LSM6DSL_FF_TSH_500mg;
4175 break;
4176
4177 default:
4178 *val = LSM6DSL_FF_TSH_ND;
4179 break;
4180 }
4181
4182 return ret;
4183 }
4184
4185 /**
4186 * @}
4187 *
4188 */
4189
4190 /**
4191 * @defgroup LSM6DSL_fifo
4192 * @brief This section group all the functions concerning the
4193 * fifo usage
4194 * @{
4195 *
4196 */
4197
4198 /**
4199 * @brief FIFO watermark level selection.[set]
4200 *
4201 * @param ctx Read / write interface definitions
4202 * @param val Change the values of fth in reg FIFO_CTRL1
4203 * @retval Interface status (MANDATORY: return 0 -> no Error).
4204 *
4205 */
lsm6dsl_fifo_watermark_set(stmdev_ctx_t * ctx,uint16_t val)4206 int32_t lsm6dsl_fifo_watermark_set(stmdev_ctx_t *ctx, uint16_t val)
4207 {
4208 lsm6dsl_fifo_ctrl1_t fifo_ctrl1;
4209 lsm6dsl_fifo_ctrl2_t fifo_ctrl2;
4210 int32_t ret;
4211
4212 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2,
4213 (uint8_t *)&fifo_ctrl2, 1);
4214
4215 if (ret == 0)
4216 {
4217 fifo_ctrl1.fth = (uint8_t)(0x00FFU & val);
4218 fifo_ctrl2.fth = (uint8_t)((0x0700U & val) >> 8);
4219 ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL1,
4220 (uint8_t *)&fifo_ctrl1, 1);
4221
4222 if (ret == 0)
4223 {
4224 ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL2,
4225 (uint8_t *)&fifo_ctrl2, 1);
4226 }
4227 }
4228
4229 return ret;
4230 }
4231
4232 /**
4233 * @brief FIFO watermark level selection.[get]
4234 *
4235 * @param ctx Read / write interface definitions
4236 * @param val Change the values of fth in reg FIFO_CTRL1
4237 * @retval Interface status (MANDATORY: return 0 -> no Error).
4238 *
4239 */
lsm6dsl_fifo_watermark_get(stmdev_ctx_t * ctx,uint16_t * val)4240 int32_t lsm6dsl_fifo_watermark_get(stmdev_ctx_t *ctx, uint16_t *val)
4241 {
4242 lsm6dsl_fifo_ctrl1_t fifo_ctrl1;
4243 lsm6dsl_fifo_ctrl2_t fifo_ctrl2;
4244 int32_t ret;
4245
4246 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL1,
4247 (uint8_t *)&fifo_ctrl1, 1);
4248
4249 if (ret == 0)
4250 {
4251 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2,
4252 (uint8_t *)&fifo_ctrl2, 1);
4253 }
4254
4255 *val = ((uint16_t)fifo_ctrl2.fth << 8) + (uint16_t)fifo_ctrl1.fth;
4256
4257 return ret;
4258 }
4259
4260 /**
4261 * @brief FIFO data level.[get]
4262 *
4263 * @param ctx Read / write interface definitions
4264 * @param val get the values of diff_fifo in reg FIFO_STATUS1 and
4265 * FIFO_STATUS2(diff_fifo), it is recommended to set the
4266 * BDU bit.
4267 * @retval Interface status (MANDATORY: return 0 -> no Error).
4268 *
4269 */
lsm6dsl_fifo_data_level_get(stmdev_ctx_t * ctx,uint16_t * val)4270 int32_t lsm6dsl_fifo_data_level_get(stmdev_ctx_t *ctx, uint16_t *val)
4271 {
4272 lsm6dsl_fifo_status1_t fifo_status1;
4273 lsm6dsl_fifo_status2_t fifo_status2;
4274 int32_t ret;
4275
4276 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS1,
4277 (uint8_t *)&fifo_status1, 1);
4278
4279 if (ret == 0)
4280 {
4281 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS2,
4282 (uint8_t *)&fifo_status2, 1);
4283 *val = ((uint16_t) fifo_status2.diff_fifo << 8) +
4284 (uint16_t) fifo_status1.diff_fifo;
4285 }
4286
4287 return ret;
4288 }
4289
4290 /**
4291 * @brief FIFO watermark.[get]
4292 *
4293 * @param ctx Read / write interface definitions
4294 * @param val get the values of watermark in reg FIFO_STATUS2 and
4295 * @retval Interface status (MANDATORY: return 0 -> no Error).
4296 *
4297 */
lsm6dsl_fifo_wtm_flag_get(stmdev_ctx_t * ctx,uint8_t * val)4298 int32_t lsm6dsl_fifo_wtm_flag_get(stmdev_ctx_t *ctx, uint8_t *val)
4299 {
4300 lsm6dsl_fifo_status2_t fifo_status2;
4301 int32_t ret;
4302
4303 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS2,
4304 (uint8_t *)&fifo_status2, 1);
4305 *val = fifo_status2.waterm;
4306
4307 return ret;
4308 }
4309
4310 /**
4311 * @brief FIFO pattern.[get]
4312 *
4313 * @param ctx Read / write interface definitions
4314 * @param val get the values of fifo_pattern in reg FIFO_STATUS3 and
4315 * FIFO_STATUS4, it is recommended to set the BDU bit
4316 * @retval Interface status (MANDATORY: return 0 -> no Error).
4317 *
4318 */
lsm6dsl_fifo_pattern_get(stmdev_ctx_t * ctx,uint16_t * val)4319 int32_t lsm6dsl_fifo_pattern_get(stmdev_ctx_t *ctx, uint16_t *val)
4320 {
4321 lsm6dsl_fifo_status3_t fifo_status3;
4322 lsm6dsl_fifo_status4_t fifo_status4;
4323 int32_t ret;
4324
4325 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS3,
4326 (uint8_t *)&fifo_status3, 1);
4327
4328 if (ret == 0)
4329 {
4330 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_STATUS4,
4331 (uint8_t *)&fifo_status4, 1);
4332 *val = ((uint16_t)fifo_status4.fifo_pattern << 8) +
4333 fifo_status3.fifo_pattern;
4334 }
4335
4336 return ret;
4337 }
4338
4339 /**
4340 * @brief Batching of temperature data[set]
4341 *
4342 * @param ctx Read / write interface definitions
4343 * @param val Change the values of fifo_temp_en in reg FIFO_CTRL2
4344 * @retval Interface status (MANDATORY: return 0 -> no Error).
4345 *
4346 */
lsm6dsl_fifo_temp_batch_set(stmdev_ctx_t * ctx,uint8_t val)4347 int32_t lsm6dsl_fifo_temp_batch_set(stmdev_ctx_t *ctx, uint8_t val)
4348 {
4349 lsm6dsl_fifo_ctrl2_t fifo_ctrl2;
4350 int32_t ret;
4351
4352 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2,
4353 (uint8_t *)&fifo_ctrl2, 1);
4354
4355 if (ret == 0)
4356 {
4357 fifo_ctrl2.fifo_temp_en = val;
4358 ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL2,
4359 (uint8_t *)&fifo_ctrl2, 1);
4360 }
4361
4362 return ret;
4363 }
4364
4365 /**
4366 * @brief Batching of temperature data[get]
4367 *
4368 * @param ctx Read / write interface definitions
4369 * @param val Change the values of fifo_temp_en in reg FIFO_CTRL2
4370 * @retval Interface status (MANDATORY: return 0 -> no Error).
4371 *
4372 */
lsm6dsl_fifo_temp_batch_get(stmdev_ctx_t * ctx,uint8_t * val)4373 int32_t lsm6dsl_fifo_temp_batch_get(stmdev_ctx_t *ctx, uint8_t *val)
4374 {
4375 lsm6dsl_fifo_ctrl2_t fifo_ctrl2;
4376 int32_t ret;
4377
4378 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2,
4379 (uint8_t *)&fifo_ctrl2, 1);
4380 *val = fifo_ctrl2.fifo_temp_en;
4381
4382 return ret;
4383 }
4384
4385 /**
4386 * @brief Trigger signal for FIFO write operation.[set]
4387 *
4388 * @param ctx Read / write interface definitions
4389 * @param val act on FIFO_CTRL2(timer_pedo_fifo_drdy)
4390 * and MASTER_CONFIG(data_valid_sel_fifo)
4391 * @retval Interface status (MANDATORY: return 0 -> no Error).
4392 *
4393 */
lsm6dsl_fifo_write_trigger_set(stmdev_ctx_t * ctx,lsm6dsl_trigger_fifo_t val)4394 int32_t lsm6dsl_fifo_write_trigger_set(stmdev_ctx_t *ctx,
4395 lsm6dsl_trigger_fifo_t val)
4396 {
4397 lsm6dsl_fifo_ctrl2_t fifo_ctrl2;
4398 lsm6dsl_master_config_t master_config;
4399 int32_t ret;
4400
4401 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2,
4402 (uint8_t *)&fifo_ctrl2, 1);
4403
4404 if (ret == 0)
4405 {
4406 fifo_ctrl2.timer_pedo_fifo_drdy = (uint8_t)val & 0x01U;
4407 ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL2,
4408 (uint8_t *)&fifo_ctrl2, 1);
4409
4410 if (ret == 0)
4411 {
4412 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
4413 (uint8_t *)&master_config, 1);
4414
4415 if (ret == 0)
4416 {
4417 master_config.data_valid_sel_fifo = (((uint8_t)val & 0x02U) >> 1);
4418 ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG,
4419 (uint8_t *)&master_config, 1);
4420 }
4421 }
4422 }
4423
4424 return ret;
4425 }
4426
4427 /**
4428 * @brief Trigger signal for FIFO write operation.[get]
4429 *
4430 * @param ctx Read / write interface definitions
4431 * @param val act on FIFO_CTRL2(timer_pedo_fifo_drdy)
4432 * and MASTER_CONFIG(data_valid_sel_fifo)
4433 * @retval Interface status (MANDATORY: return 0 -> no Error).
4434 *
4435 */
lsm6dsl_fifo_write_trigger_get(stmdev_ctx_t * ctx,lsm6dsl_trigger_fifo_t * val)4436 int32_t lsm6dsl_fifo_write_trigger_get(stmdev_ctx_t *ctx,
4437 lsm6dsl_trigger_fifo_t *val)
4438 {
4439 lsm6dsl_fifo_ctrl2_t fifo_ctrl2;
4440 lsm6dsl_master_config_t master_config;
4441 int32_t ret;
4442
4443 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2,
4444 (uint8_t *)&fifo_ctrl2, 1);
4445
4446 if (ret == 0)
4447 {
4448 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
4449 (uint8_t *)&master_config, 1);
4450
4451 switch ((fifo_ctrl2.timer_pedo_fifo_drdy << 1) +
4452 fifo_ctrl2. timer_pedo_fifo_drdy)
4453 {
4454 case LSM6DSL_TRG_XL_GY_DRDY:
4455 *val = LSM6DSL_TRG_XL_GY_DRDY;
4456 break;
4457
4458 case LSM6DSL_TRG_STEP_DETECT:
4459 *val = LSM6DSL_TRG_STEP_DETECT;
4460 break;
4461
4462 case LSM6DSL_TRG_SH_DRDY:
4463 *val = LSM6DSL_TRG_SH_DRDY;
4464 break;
4465
4466 default:
4467 *val = LSM6DSL_TRG_SH_ND;
4468 break;
4469 }
4470 }
4471
4472 return ret;
4473 }
4474
4475 /**
4476 * @brief Enable pedometer step counter and timestamp as 4th
4477 * FIFO data set.[set]
4478 *
4479 * @param ctx Read / write interface definitions
4480 * @param val Change the values of timer_pedo_fifo_en in reg FIFO_CTRL2
4481 * @retval Interface status (MANDATORY: return 0 -> no Error).
4482 *
4483 */
lsm6dsl_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t * ctx,uint8_t val)4484 int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t *ctx,
4485 uint8_t val)
4486 {
4487 lsm6dsl_fifo_ctrl2_t fifo_ctrl2;
4488 int32_t ret;
4489
4490 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2,
4491 (uint8_t *)&fifo_ctrl2, 1);
4492
4493 if (ret == 0)
4494 {
4495 fifo_ctrl2.timer_pedo_fifo_en = val;
4496 ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL2,
4497 (uint8_t *)&fifo_ctrl2, 1);
4498 }
4499
4500 return ret;
4501 }
4502
4503 /**
4504 * @brief Enable pedometer step counter and timestamp as 4th
4505 * FIFO data set.[get]
4506 *
4507 * @param ctx Read / write interface definitions
4508 * @param val Change the values of timer_pedo_fifo_en in reg FIFO_CTRL2
4509 * @retval Interface status (MANDATORY: return 0 -> no Error).
4510 *
4511 */
lsm6dsl_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t * ctx,uint8_t * val)4512 int32_t lsm6dsl_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t *ctx,
4513 uint8_t *val)
4514 {
4515 lsm6dsl_fifo_ctrl2_t fifo_ctrl2;
4516 int32_t ret;
4517
4518 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL2,
4519 (uint8_t *)&fifo_ctrl2, 1);
4520 *val = fifo_ctrl2.timer_pedo_fifo_en;
4521
4522 return ret;
4523 }
4524
4525 /**
4526 * @brief Selects Batching Data Rate (writing frequency in FIFO) for
4527 * accelerometer data.[set]
4528 *
4529 * @param ctx Read / write interface definitions
4530 * @param val Change the values of dec_fifo_xl in reg FIFO_CTRL3
4531 * @retval Interface status (MANDATORY: return 0 -> no Error).
4532 *
4533 */
lsm6dsl_fifo_xl_batch_set(stmdev_ctx_t * ctx,lsm6dsl_dec_fifo_xl_t val)4534 int32_t lsm6dsl_fifo_xl_batch_set(stmdev_ctx_t *ctx,
4535 lsm6dsl_dec_fifo_xl_t val)
4536 {
4537 lsm6dsl_fifo_ctrl3_t fifo_ctrl3;
4538 int32_t ret;
4539
4540 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL3,
4541 (uint8_t *)&fifo_ctrl3, 1);
4542
4543 if (ret == 0)
4544 {
4545 fifo_ctrl3.dec_fifo_xl = (uint8_t)val;
4546 ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL3,
4547 (uint8_t *)&fifo_ctrl3, 1);
4548 }
4549
4550 return ret;
4551 }
4552
4553 /**
4554 * @brief Selects Batching Data Rate (writing frequency in FIFO) for
4555 * accelerometer data.[get]
4556 *
4557 * @param ctx Read / write interface definitions
4558 * @param val Get the values of dec_fifo_xl in reg FIFO_CTRL3
4559 * @retval Interface status (MANDATORY: return 0 -> no Error).
4560 *
4561 */
lsm6dsl_fifo_xl_batch_get(stmdev_ctx_t * ctx,lsm6dsl_dec_fifo_xl_t * val)4562 int32_t lsm6dsl_fifo_xl_batch_get(stmdev_ctx_t *ctx,
4563 lsm6dsl_dec_fifo_xl_t *val)
4564 {
4565 lsm6dsl_fifo_ctrl3_t fifo_ctrl3;
4566 int32_t ret;
4567
4568 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL3,
4569 (uint8_t *)&fifo_ctrl3, 1);
4570
4571 switch (fifo_ctrl3.dec_fifo_xl)
4572 {
4573 case LSM6DSL_FIFO_XL_DISABLE:
4574 *val = LSM6DSL_FIFO_XL_DISABLE;
4575 break;
4576
4577 case LSM6DSL_FIFO_XL_NO_DEC:
4578 *val = LSM6DSL_FIFO_XL_NO_DEC;
4579 break;
4580
4581 case LSM6DSL_FIFO_XL_DEC_2:
4582 *val = LSM6DSL_FIFO_XL_DEC_2;
4583 break;
4584
4585 case LSM6DSL_FIFO_XL_DEC_3:
4586 *val = LSM6DSL_FIFO_XL_DEC_3;
4587 break;
4588
4589 case LSM6DSL_FIFO_XL_DEC_4:
4590 *val = LSM6DSL_FIFO_XL_DEC_4;
4591 break;
4592
4593 case LSM6DSL_FIFO_XL_DEC_8:
4594 *val = LSM6DSL_FIFO_XL_DEC_8;
4595 break;
4596
4597 case LSM6DSL_FIFO_XL_DEC_16:
4598 *val = LSM6DSL_FIFO_XL_DEC_16;
4599 break;
4600
4601 case LSM6DSL_FIFO_XL_DEC_32:
4602 *val = LSM6DSL_FIFO_XL_DEC_32;
4603 break;
4604
4605 default:
4606 *val = LSM6DSL_FIFO_XL_DEC_ND;
4607 break;
4608 }
4609
4610 return ret;
4611 }
4612
4613 /**
4614 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4615 * for gyroscope data.[set]
4616 *
4617 * @param ctx Read / write interface definitions
4618 * @param val Change the values of dec_fifo_gyro in reg FIFO_CTRL3
4619 * @retval Interface status (MANDATORY: return 0 -> no Error).
4620 *
4621 */
lsm6dsl_fifo_gy_batch_set(stmdev_ctx_t * ctx,lsm6dsl_dec_fifo_gyro_t val)4622 int32_t lsm6dsl_fifo_gy_batch_set(stmdev_ctx_t *ctx,
4623 lsm6dsl_dec_fifo_gyro_t val)
4624 {
4625 lsm6dsl_fifo_ctrl3_t fifo_ctrl3;
4626 int32_t ret;
4627
4628 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL3,
4629 (uint8_t *)&fifo_ctrl3, 1);
4630
4631 if (ret == 0)
4632 {
4633 fifo_ctrl3.dec_fifo_gyro = (uint8_t)val;
4634 ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL3,
4635 (uint8_t *)&fifo_ctrl3, 1);
4636 }
4637
4638 return ret;
4639 }
4640
4641 /**
4642 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4643 * for gyroscope data.[get]
4644 *
4645 * @param ctx Read / write interface definitions
4646 * @param val Get the values of dec_fifo_gyro in reg FIFO_CTRL3
4647 * @retval Interface status (MANDATORY: return 0 -> no Error).
4648 *
4649 */
lsm6dsl_fifo_gy_batch_get(stmdev_ctx_t * ctx,lsm6dsl_dec_fifo_gyro_t * val)4650 int32_t lsm6dsl_fifo_gy_batch_get(stmdev_ctx_t *ctx,
4651 lsm6dsl_dec_fifo_gyro_t *val)
4652 {
4653 lsm6dsl_fifo_ctrl3_t fifo_ctrl3;
4654 int32_t ret;
4655
4656 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL3,
4657 (uint8_t *)&fifo_ctrl3, 1);
4658
4659 switch (fifo_ctrl3.dec_fifo_gyro)
4660 {
4661 case LSM6DSL_FIFO_GY_DISABLE:
4662 *val = LSM6DSL_FIFO_GY_DISABLE;
4663 break;
4664
4665 case LSM6DSL_FIFO_GY_NO_DEC:
4666 *val = LSM6DSL_FIFO_GY_NO_DEC;
4667 break;
4668
4669 case LSM6DSL_FIFO_GY_DEC_2:
4670 *val = LSM6DSL_FIFO_GY_DEC_2;
4671 break;
4672
4673 case LSM6DSL_FIFO_GY_DEC_3:
4674 *val = LSM6DSL_FIFO_GY_DEC_3;
4675 break;
4676
4677 case LSM6DSL_FIFO_GY_DEC_4:
4678 *val = LSM6DSL_FIFO_GY_DEC_4;
4679 break;
4680
4681 case LSM6DSL_FIFO_GY_DEC_8:
4682 *val = LSM6DSL_FIFO_GY_DEC_8;
4683 break;
4684
4685 case LSM6DSL_FIFO_GY_DEC_16:
4686 *val = LSM6DSL_FIFO_GY_DEC_16;
4687 break;
4688
4689 case LSM6DSL_FIFO_GY_DEC_32:
4690 *val = LSM6DSL_FIFO_GY_DEC_32;
4691 break;
4692
4693 default:
4694 *val = LSM6DSL_FIFO_GY_DEC_ND;
4695 break;
4696 }
4697
4698 return ret;
4699 }
4700
4701 /**
4702 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4703 * for third data set.[set]
4704 *
4705 * @param ctx Read / write interface definitions
4706 * @param val Change the values of dec_ds3_fifo in reg FIFO_CTRL4
4707 * @retval Interface status (MANDATORY: return 0 -> no Error).
4708 *
4709 */
lsm6dsl_fifo_dataset_3_batch_set(stmdev_ctx_t * ctx,lsm6dsl_dec_ds3_fifo_t val)4710 int32_t lsm6dsl_fifo_dataset_3_batch_set(stmdev_ctx_t *ctx,
4711 lsm6dsl_dec_ds3_fifo_t val)
4712 {
4713 lsm6dsl_fifo_ctrl4_t fifo_ctrl4;
4714 int32_t ret;
4715
4716 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4,
4717 (uint8_t *)&fifo_ctrl4, 1);
4718
4719 if (ret == 0)
4720 {
4721 fifo_ctrl4.dec_ds3_fifo = (uint8_t)val;
4722 ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL4,
4723 (uint8_t *)&fifo_ctrl4, 1);
4724 }
4725
4726 return ret;
4727 }
4728
4729 /**
4730 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4731 * for third data set.[get]
4732 *
4733 * @param ctx Read / write interface definitions
4734 * @param val Get the values of dec_ds3_fifo in reg FIFO_CTRL4
4735 * @retval Interface status (MANDATORY: return 0 -> no Error).
4736 *
4737 */
lsm6dsl_fifo_dataset_3_batch_get(stmdev_ctx_t * ctx,lsm6dsl_dec_ds3_fifo_t * val)4738 int32_t lsm6dsl_fifo_dataset_3_batch_get(stmdev_ctx_t *ctx,
4739 lsm6dsl_dec_ds3_fifo_t *val)
4740 {
4741 lsm6dsl_fifo_ctrl4_t fifo_ctrl4;
4742 int32_t ret;
4743
4744 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4,
4745 (uint8_t *)&fifo_ctrl4, 1);
4746
4747 switch (fifo_ctrl4.dec_ds3_fifo)
4748 {
4749 case LSM6DSL_FIFO_DS3_DISABLE:
4750 *val = LSM6DSL_FIFO_DS3_DISABLE;
4751 break;
4752
4753 case LSM6DSL_FIFO_DS3_NO_DEC:
4754 *val = LSM6DSL_FIFO_DS3_NO_DEC;
4755 break;
4756
4757 case LSM6DSL_FIFO_DS3_DEC_2:
4758 *val = LSM6DSL_FIFO_DS3_DEC_2;
4759 break;
4760
4761 case LSM6DSL_FIFO_DS3_DEC_3:
4762 *val = LSM6DSL_FIFO_DS3_DEC_3;
4763 break;
4764
4765 case LSM6DSL_FIFO_DS3_DEC_4:
4766 *val = LSM6DSL_FIFO_DS3_DEC_4;
4767 break;
4768
4769 case LSM6DSL_FIFO_DS3_DEC_8:
4770 *val = LSM6DSL_FIFO_DS3_DEC_8;
4771 break;
4772
4773 case LSM6DSL_FIFO_DS3_DEC_16:
4774 *val = LSM6DSL_FIFO_DS3_DEC_16;
4775 break;
4776
4777 case LSM6DSL_FIFO_DS3_DEC_32:
4778 *val = LSM6DSL_FIFO_DS3_DEC_32;
4779 break;
4780
4781 default:
4782 *val = LSM6DSL_FIFO_DS3_DEC_ND;
4783 break;
4784 }
4785
4786 return ret;
4787 }
4788
4789 /**
4790 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4791 * for fourth data set.[set]
4792 *
4793 * @param ctx Read / write interface definitions
4794 * @param val Change the values of dec_ds4_fifo in reg FIFO_CTRL4
4795 * @retval Interface status (MANDATORY: return 0 -> no Error).
4796 *
4797 */
lsm6dsl_fifo_dataset_4_batch_set(stmdev_ctx_t * ctx,lsm6dsl_dec_ds4_fifo_t val)4798 int32_t lsm6dsl_fifo_dataset_4_batch_set(stmdev_ctx_t *ctx,
4799 lsm6dsl_dec_ds4_fifo_t val)
4800 {
4801 lsm6dsl_fifo_ctrl4_t fifo_ctrl4;
4802 int32_t ret;
4803
4804 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4,
4805 (uint8_t *)&fifo_ctrl4, 1);
4806
4807 if (ret == 0)
4808 {
4809 fifo_ctrl4.dec_ds4_fifo = (uint8_t)val;
4810 ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL4,
4811 (uint8_t *)&fifo_ctrl4, 1);
4812 }
4813
4814 return ret;
4815 }
4816
4817 /**
4818 * @brief Selects Batching Data Rate (writing frequency in FIFO) for
4819 * fourth data set.[get]
4820 *
4821 * @param ctx Read / write interface definitions
4822 * @param val Get the values of dec_ds4_fifo in reg FIFO_CTRL4
4823 * @retval Interface status (MANDATORY: return 0 -> no Error).
4824 *
4825 */
lsm6dsl_fifo_dataset_4_batch_get(stmdev_ctx_t * ctx,lsm6dsl_dec_ds4_fifo_t * val)4826 int32_t lsm6dsl_fifo_dataset_4_batch_get(stmdev_ctx_t *ctx,
4827 lsm6dsl_dec_ds4_fifo_t *val)
4828 {
4829 lsm6dsl_fifo_ctrl4_t fifo_ctrl4;
4830 int32_t ret;
4831
4832 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4,
4833 (uint8_t *)&fifo_ctrl4, 1);
4834
4835 switch (fifo_ctrl4.dec_ds4_fifo)
4836 {
4837 case LSM6DSL_FIFO_DS4_DISABLE:
4838 *val = LSM6DSL_FIFO_DS4_DISABLE;
4839 break;
4840
4841 case LSM6DSL_FIFO_DS4_NO_DEC:
4842 *val = LSM6DSL_FIFO_DS4_NO_DEC;
4843 break;
4844
4845 case LSM6DSL_FIFO_DS4_DEC_2:
4846 *val = LSM6DSL_FIFO_DS4_DEC_2;
4847 break;
4848
4849 case LSM6DSL_FIFO_DS4_DEC_3:
4850 *val = LSM6DSL_FIFO_DS4_DEC_3;
4851 break;
4852
4853 case LSM6DSL_FIFO_DS4_DEC_4:
4854 *val = LSM6DSL_FIFO_DS4_DEC_4;
4855 break;
4856
4857 case LSM6DSL_FIFO_DS4_DEC_8:
4858 *val = LSM6DSL_FIFO_DS4_DEC_8;
4859 break;
4860
4861 case LSM6DSL_FIFO_DS4_DEC_16:
4862 *val = LSM6DSL_FIFO_DS4_DEC_16;
4863 break;
4864
4865 case LSM6DSL_FIFO_DS4_DEC_32:
4866 *val = LSM6DSL_FIFO_DS4_DEC_32;
4867 break;
4868
4869 default:
4870 *val = LSM6DSL_FIFO_DS4_DEC_ND;
4871 break;
4872 }
4873
4874 return ret;
4875 }
4876
4877 /**
4878 * @brief 8-bit data storage in FIFO.[set]
4879 *
4880 * @param ctx Read / write interface definitions
4881 * @param val Change the values of only_high_data in reg FIFO_CTRL4
4882 * @retval Interface status (MANDATORY: return 0 -> no Error).
4883 *
4884 */
lsm6dsl_fifo_xl_gy_8bit_format_set(stmdev_ctx_t * ctx,uint8_t val)4885 int32_t lsm6dsl_fifo_xl_gy_8bit_format_set(stmdev_ctx_t *ctx,
4886 uint8_t val)
4887 {
4888 lsm6dsl_fifo_ctrl4_t fifo_ctrl4;
4889 int32_t ret;
4890
4891 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4,
4892 (uint8_t *)&fifo_ctrl4, 1);
4893
4894 if (ret == 0)
4895 {
4896 fifo_ctrl4.only_high_data = val;
4897 ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL4,
4898 (uint8_t *)&fifo_ctrl4, 1);
4899 }
4900
4901 return ret;
4902 }
4903
4904 /**
4905 * @brief 8-bit data storage in FIFO.[get]
4906 *
4907 * @param ctx Read / write interface definitions
4908 * @param val Change the values of only_high_data in reg FIFO_CTRL4
4909 * @retval Interface status (MANDATORY: return 0 -> no Error).
4910 *
4911 */
lsm6dsl_fifo_xl_gy_8bit_format_get(stmdev_ctx_t * ctx,uint8_t * val)4912 int32_t lsm6dsl_fifo_xl_gy_8bit_format_get(stmdev_ctx_t *ctx,
4913 uint8_t *val)
4914 {
4915 lsm6dsl_fifo_ctrl4_t fifo_ctrl4;
4916 int32_t ret;
4917
4918 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4,
4919 (uint8_t *)&fifo_ctrl4, 1);
4920 *val = fifo_ctrl4.only_high_data;
4921
4922 return ret;
4923 }
4924
4925 /**
4926 * @brief Sensing chain FIFO stop values memorization at threshold
4927 * level.[set]
4928 *
4929 * @param ctx Read / write interface definitions
4930 * @param val Change the values of stop_on_fth in reg FIFO_CTRL4
4931 * @retval Interface status (MANDATORY: return 0 -> no Error).
4932 *
4933 */
lsm6dsl_fifo_stop_on_wtm_set(stmdev_ctx_t * ctx,uint8_t val)4934 int32_t lsm6dsl_fifo_stop_on_wtm_set(stmdev_ctx_t *ctx, uint8_t val)
4935 {
4936 lsm6dsl_fifo_ctrl4_t fifo_ctrl4;
4937 int32_t ret;
4938
4939 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4,
4940 (uint8_t *)&fifo_ctrl4, 1);
4941
4942 if (ret == 0)
4943 {
4944 fifo_ctrl4.stop_on_fth = val;
4945 ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL4,
4946 (uint8_t *)&fifo_ctrl4, 1);
4947 }
4948
4949 return ret;
4950 }
4951
4952 /**
4953 * @brief Sensing chain FIFO stop values memorization at threshold
4954 * level.[get]
4955 *
4956 * @param ctx Read / write interface definitions
4957 * @param val Change the values of stop_on_fth in reg FIFO_CTRL4
4958 * @retval Interface status (MANDATORY: return 0 -> no Error).
4959 *
4960 */
lsm6dsl_fifo_stop_on_wtm_get(stmdev_ctx_t * ctx,uint8_t * val)4961 int32_t lsm6dsl_fifo_stop_on_wtm_get(stmdev_ctx_t *ctx, uint8_t *val)
4962 {
4963 lsm6dsl_fifo_ctrl4_t fifo_ctrl4;
4964 int32_t ret;
4965
4966 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL4,
4967 (uint8_t *)&fifo_ctrl4, 1);
4968 *val = fifo_ctrl4.stop_on_fth;
4969
4970 return ret;
4971 }
4972
4973 /**
4974 * @brief FIFO mode selection.[set]
4975 *
4976 * @param ctx Read / write interface definitions
4977 * @param val Change the values of fifo_mode in reg FIFO_CTRL5
4978 * @retval Interface status (MANDATORY: return 0 -> no Error).
4979 *
4980 */
lsm6dsl_fifo_mode_set(stmdev_ctx_t * ctx,lsm6dsl_fifo_mode_t val)4981 int32_t lsm6dsl_fifo_mode_set(stmdev_ctx_t *ctx,
4982 lsm6dsl_fifo_mode_t val)
4983 {
4984 lsm6dsl_fifo_ctrl5_t fifo_ctrl5;
4985 int32_t ret;
4986
4987 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL5,
4988 (uint8_t *)&fifo_ctrl5, 1);
4989
4990 if (ret == 0)
4991 {
4992 fifo_ctrl5.fifo_mode = (uint8_t)val;
4993 ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL5,
4994 (uint8_t *)&fifo_ctrl5, 1);
4995 }
4996
4997 return ret;
4998 }
4999
5000 /**
5001 * @brief FIFO mode selection.[get]
5002 *
5003 * @param ctx Read / write interface definitions
5004 * @param val Get the values of fifo_mode in reg FIFO_CTRL5
5005 * @retval Interface status (MANDATORY: return 0 -> no Error).
5006 *
5007 */
lsm6dsl_fifo_mode_get(stmdev_ctx_t * ctx,lsm6dsl_fifo_mode_t * val)5008 int32_t lsm6dsl_fifo_mode_get(stmdev_ctx_t *ctx,
5009 lsm6dsl_fifo_mode_t *val)
5010 {
5011 lsm6dsl_fifo_ctrl5_t fifo_ctrl5;
5012 int32_t ret;
5013
5014 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL5,
5015 (uint8_t *)&fifo_ctrl5, 1);
5016
5017 switch (fifo_ctrl5.fifo_mode)
5018 {
5019 case LSM6DSL_BYPASS_MODE:
5020 *val = LSM6DSL_BYPASS_MODE;
5021 break;
5022
5023 case LSM6DSL_FIFO_MODE:
5024 *val = LSM6DSL_FIFO_MODE;
5025 break;
5026
5027 case LSM6DSL_STREAM_TO_FIFO_MODE:
5028 *val = LSM6DSL_STREAM_TO_FIFO_MODE;
5029 break;
5030
5031 case LSM6DSL_BYPASS_TO_STREAM_MODE:
5032 *val = LSM6DSL_BYPASS_TO_STREAM_MODE;
5033 break;
5034
5035 case LSM6DSL_STREAM_MODE:
5036 *val = LSM6DSL_STREAM_MODE;
5037 break;
5038
5039 default:
5040 *val = LSM6DSL_FIFO_MODE_ND;
5041 break;
5042 }
5043
5044 return ret;
5045 }
5046
5047 /**
5048 * @brief FIFO ODR selection, setting FIFO_MODE also.[set]
5049 *
5050 * @param ctx Read / write interface definitions
5051 * @param val Change the values of odr_fifo in reg FIFO_CTRL5
5052 * @retval Interface status (MANDATORY: return 0 -> no Error).
5053 *
5054 */
lsm6dsl_fifo_data_rate_set(stmdev_ctx_t * ctx,lsm6dsl_odr_fifo_t val)5055 int32_t lsm6dsl_fifo_data_rate_set(stmdev_ctx_t *ctx,
5056 lsm6dsl_odr_fifo_t val)
5057 {
5058 lsm6dsl_fifo_ctrl5_t fifo_ctrl5;
5059 int32_t ret;
5060
5061 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL5,
5062 (uint8_t *)&fifo_ctrl5, 1);
5063
5064 if (ret == 0)
5065 {
5066 fifo_ctrl5.odr_fifo = (uint8_t)val;
5067 ret = lsm6dsl_write_reg(ctx, LSM6DSL_FIFO_CTRL5,
5068 (uint8_t *)&fifo_ctrl5, 1);
5069 }
5070
5071 return ret;
5072 }
5073
5074 /**
5075 * @brief FIFO ODR selection, setting FIFO_MODE also.[get]
5076 *
5077 * @param ctx Read / write interface definitions
5078 * @param val Get the values of odr_fifo in reg FIFO_CTRL5
5079 * @retval Interface status (MANDATORY: return 0 -> no Error).
5080 *
5081 */
lsm6dsl_fifo_data_rate_get(stmdev_ctx_t * ctx,lsm6dsl_odr_fifo_t * val)5082 int32_t lsm6dsl_fifo_data_rate_get(stmdev_ctx_t *ctx,
5083 lsm6dsl_odr_fifo_t *val)
5084 {
5085 lsm6dsl_fifo_ctrl5_t fifo_ctrl5;
5086 int32_t ret;
5087
5088 ret = lsm6dsl_read_reg(ctx, LSM6DSL_FIFO_CTRL5,
5089 (uint8_t *)&fifo_ctrl5, 1);
5090
5091 switch (fifo_ctrl5.odr_fifo)
5092 {
5093 case LSM6DSL_FIFO_DISABLE:
5094 *val = LSM6DSL_FIFO_DISABLE;
5095 break;
5096
5097 case LSM6DSL_FIFO_12Hz5:
5098 *val = LSM6DSL_FIFO_12Hz5;
5099 break;
5100
5101 case LSM6DSL_FIFO_26Hz:
5102 *val = LSM6DSL_FIFO_26Hz;
5103 break;
5104
5105 case LSM6DSL_FIFO_52Hz:
5106 *val = LSM6DSL_FIFO_52Hz;
5107 break;
5108
5109 case LSM6DSL_FIFO_104Hz:
5110 *val = LSM6DSL_FIFO_104Hz;
5111 break;
5112
5113 case LSM6DSL_FIFO_208Hz:
5114 *val = LSM6DSL_FIFO_208Hz;
5115 break;
5116
5117 case LSM6DSL_FIFO_416Hz:
5118 *val = LSM6DSL_FIFO_416Hz;
5119 break;
5120
5121 case LSM6DSL_FIFO_833Hz:
5122 *val = LSM6DSL_FIFO_833Hz;
5123 break;
5124
5125 case LSM6DSL_FIFO_1k66Hz:
5126 *val = LSM6DSL_FIFO_1k66Hz;
5127 break;
5128
5129 case LSM6DSL_FIFO_3k33Hz:
5130 *val = LSM6DSL_FIFO_3k33Hz;
5131 break;
5132
5133 case LSM6DSL_FIFO_6k66Hz:
5134 *val = LSM6DSL_FIFO_6k66Hz;
5135 break;
5136
5137 default:
5138 *val = LSM6DSL_FIFO_RATE_ND;
5139 break;
5140 }
5141
5142 return ret;
5143 }
5144
5145 /**
5146 * @}
5147 *
5148 */
5149
5150 /**
5151 * @defgroup LSM6DSL_DEN_functionality
5152 * @brief This section groups all the functions concerning DEN
5153 * functionality.
5154 * @{
5155 *
5156 */
5157
5158 /**
5159 * @brief DEN active level configuration.[set]
5160 *
5161 * @param ctx Read / write interface definitions
5162 * @param val Change the values of den_lh in reg CTRL5_C
5163 * @retval Interface status (MANDATORY: return 0 -> no Error).
5164 *
5165 */
lsm6dsl_den_polarity_set(stmdev_ctx_t * ctx,lsm6dsl_den_lh_t val)5166 int32_t lsm6dsl_den_polarity_set(stmdev_ctx_t *ctx,
5167 lsm6dsl_den_lh_t val)
5168 {
5169 lsm6dsl_ctrl5_c_t ctrl5_c;
5170 int32_t ret;
5171
5172 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
5173
5174 if (ret == 0)
5175 {
5176 ctrl5_c.den_lh = (uint8_t)val;
5177 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
5178 }
5179
5180 return ret;
5181 }
5182
5183 /**
5184 * @brief DEN active level configuration.[get]
5185 *
5186 * @param ctx Read / write interface definitions
5187 * @param val Get the values of den_lh in reg CTRL5_C
5188 * @retval Interface status (MANDATORY: return 0 -> no Error).
5189 *
5190 */
lsm6dsl_den_polarity_get(stmdev_ctx_t * ctx,lsm6dsl_den_lh_t * val)5191 int32_t lsm6dsl_den_polarity_get(stmdev_ctx_t *ctx,
5192 lsm6dsl_den_lh_t *val)
5193 {
5194 lsm6dsl_ctrl5_c_t ctrl5_c;
5195 int32_t ret;
5196
5197 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL5_C, (uint8_t *)&ctrl5_c, 1);
5198
5199 switch (ctrl5_c.den_lh)
5200 {
5201 case LSM6DSL_DEN_ACT_LOW:
5202 *val = LSM6DSL_DEN_ACT_LOW;
5203 break;
5204
5205 case LSM6DSL_DEN_ACT_HIGH:
5206 *val = LSM6DSL_DEN_ACT_HIGH;
5207 break;
5208
5209 default:
5210 *val = LSM6DSL_DEN_POL_ND;
5211 break;
5212 }
5213
5214 return ret;
5215 }
5216
5217 /**
5218 * @brief DEN functionality marking mode[set]
5219 *
5220 * @param ctx Read / write interface definitions
5221 * @param val Change the values of den_mode in reg CTRL6_C
5222 * @retval Interface status (MANDATORY: return 0 -> no Error).
5223 *
5224 */
lsm6dsl_den_mode_set(stmdev_ctx_t * ctx,lsm6dsl_den_mode_t val)5225 int32_t lsm6dsl_den_mode_set(stmdev_ctx_t *ctx,
5226 lsm6dsl_den_mode_t val)
5227 {
5228 lsm6dsl_ctrl6_c_t ctrl6_c;
5229 int32_t ret;
5230
5231 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
5232
5233 if (ret == 0)
5234 {
5235 ctrl6_c.den_mode = (uint8_t)val;
5236 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
5237 }
5238
5239 return ret;
5240 }
5241
5242 /**
5243 * @brief DEN functionality marking mode[get]
5244 *
5245 * @param ctx Read / write interface definitions
5246 * @param val Change the values of den_mode in reg CTRL6_C
5247 * @retval Interface status (MANDATORY: return 0 -> no Error).
5248 *
5249 */
lsm6dsl_den_mode_get(stmdev_ctx_t * ctx,lsm6dsl_den_mode_t * val)5250 int32_t lsm6dsl_den_mode_get(stmdev_ctx_t *ctx,
5251 lsm6dsl_den_mode_t *val)
5252 {
5253 lsm6dsl_ctrl6_c_t ctrl6_c;
5254 int32_t ret;
5255
5256 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL6_C, (uint8_t *)&ctrl6_c, 1);
5257
5258 switch (ctrl6_c.den_mode)
5259 {
5260 case LSM6DSL_DEN_DISABLE:
5261 *val = LSM6DSL_DEN_DISABLE;
5262 break;
5263
5264 case LSM6DSL_LEVEL_LETCHED:
5265 *val = LSM6DSL_LEVEL_LETCHED;
5266 break;
5267
5268 case LSM6DSL_LEVEL_TRIGGER:
5269 *val = LSM6DSL_LEVEL_TRIGGER;
5270 break;
5271
5272 case LSM6DSL_EDGE_TRIGGER:
5273 *val = LSM6DSL_EDGE_TRIGGER;
5274 break;
5275
5276 default:
5277 *val = LSM6DSL_DEN_MODE_ND;
5278 break;
5279 }
5280
5281 return ret;
5282 }
5283
5284 /**
5285 * @brief Extend DEN functionality to accelerometer sensor.[set]
5286 *
5287 * @param ctx Read / write interface definitions
5288 * @param val Change the values of den_xl_g in reg CTRL9_XL
5289 * and den_xl_en in CTRL4_C.
5290 * @retval Interface status (MANDATORY: return 0 -> no Error).
5291 *
5292 */
lsm6dsl_den_enable_set(stmdev_ctx_t * ctx,lsm6dsl_den_xl_en_t val)5293 int32_t lsm6dsl_den_enable_set(stmdev_ctx_t *ctx,
5294 lsm6dsl_den_xl_en_t val)
5295 {
5296 lsm6dsl_ctrl4_c_t ctrl4_c;
5297 lsm6dsl_ctrl9_xl_t ctrl9_xl;
5298 int32_t ret;
5299
5300 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5301
5302 if (ret == 0)
5303 {
5304 ctrl9_xl.den_xl_g = (uint8_t)val & 0x01U;
5305 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5306
5307 if (ret == 0)
5308 {
5309 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
5310
5311 if (ret == 0)
5312 {
5313 ctrl4_c.den_xl_en = (uint8_t)val & 0x02U;
5314 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
5315 }
5316 }
5317 }
5318
5319 return ret;
5320 }
5321
5322 /**
5323 * @brief Extend DEN functionality to accelerometer sensor. [get]
5324 *
5325 * @param ctx Read / write interface definitions
5326 * @param val Get the values of den_xl_g in reg CTRL9_XL
5327 * and den_xl_en in CTRL4_C.
5328 * @retval Interface status (MANDATORY: return 0 -> no Error).
5329 *
5330 */
lsm6dsl_den_enable_get(stmdev_ctx_t * ctx,lsm6dsl_den_xl_en_t * val)5331 int32_t lsm6dsl_den_enable_get(stmdev_ctx_t *ctx,
5332 lsm6dsl_den_xl_en_t *val)
5333 {
5334 lsm6dsl_ctrl4_c_t ctrl4_c;
5335 lsm6dsl_ctrl9_xl_t ctrl9_xl;
5336 int32_t ret;
5337
5338 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL4_C, (uint8_t *)&ctrl4_c, 1);
5339
5340 if (ret == 0)
5341 {
5342 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5343
5344 switch ((ctrl4_c.den_xl_en << 1) + ctrl9_xl.den_xl_g)
5345 {
5346 case LSM6DSL_STAMP_IN_GY_DATA:
5347 *val = LSM6DSL_STAMP_IN_GY_DATA;
5348 break;
5349
5350 case LSM6DSL_STAMP_IN_XL_DATA:
5351 *val = LSM6DSL_STAMP_IN_XL_DATA;
5352 break;
5353
5354 case LSM6DSL_STAMP_IN_GY_XL_DATA:
5355 *val = LSM6DSL_STAMP_IN_GY_XL_DATA;
5356 break;
5357
5358 default:
5359 *val = LSM6DSL_DEN_STAMP_ND;
5360 break;
5361 }
5362 }
5363
5364 return ret;
5365 }
5366
5367 /**
5368 * @brief DEN value stored in LSB of Z-axis.[set]
5369 *
5370 * @param ctx Read / write interface definitions
5371 * @param val Change the values of den_z in reg CTRL9_XL
5372 * @retval Interface status (MANDATORY: return 0 -> no Error).
5373 *
5374 */
lsm6dsl_den_mark_axis_z_set(stmdev_ctx_t * ctx,uint8_t val)5375 int32_t lsm6dsl_den_mark_axis_z_set(stmdev_ctx_t *ctx, uint8_t val)
5376 {
5377 lsm6dsl_ctrl9_xl_t ctrl9_xl;
5378 int32_t ret;
5379
5380 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5381
5382 if (ret == 0)
5383 {
5384 ctrl9_xl.den_z = val;
5385 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5386 }
5387
5388 return ret;
5389 }
5390
5391 /**
5392 * @brief DEN value stored in LSB of Z-axis.[get]
5393 *
5394 * @param ctx Read / write interface definitions
5395 * @param val Change the values of den_z in reg CTRL9_XL
5396 * @retval Interface status (MANDATORY: return 0 -> no Error).
5397 *
5398 */
lsm6dsl_den_mark_axis_z_get(stmdev_ctx_t * ctx,uint8_t * val)5399 int32_t lsm6dsl_den_mark_axis_z_get(stmdev_ctx_t *ctx, uint8_t *val)
5400 {
5401 lsm6dsl_ctrl9_xl_t ctrl9_xl;
5402 int32_t ret;
5403
5404 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5405 *val = ctrl9_xl.den_z;
5406
5407 return ret;
5408 }
5409
5410 /**
5411 * @brief DEN value stored in LSB of Y-axis.[set]
5412 *
5413 * @param ctx Read / write interface definitions
5414 * @param val Change the values of den_y in reg CTRL9_XL
5415 * @retval Interface status (MANDATORY: return 0 -> no Error).
5416 *
5417 */
lsm6dsl_den_mark_axis_y_set(stmdev_ctx_t * ctx,uint8_t val)5418 int32_t lsm6dsl_den_mark_axis_y_set(stmdev_ctx_t *ctx, uint8_t val)
5419 {
5420 lsm6dsl_ctrl9_xl_t ctrl9_xl;
5421 int32_t ret;
5422
5423 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5424
5425 if (ret == 0)
5426 {
5427 ctrl9_xl.den_y = val;
5428 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5429 }
5430
5431 return ret;
5432 }
5433
5434 /**
5435 * @brief DEN value stored in LSB of Y-axis.[get]
5436 *
5437 * @param ctx Read / write interface definitions
5438 * @param val Change the values of den_y in reg CTRL9_XL
5439 * @retval Interface status (MANDATORY: return 0 -> no Error).
5440 *
5441 */
lsm6dsl_den_mark_axis_y_get(stmdev_ctx_t * ctx,uint8_t * val)5442 int32_t lsm6dsl_den_mark_axis_y_get(stmdev_ctx_t *ctx, uint8_t *val)
5443 {
5444 lsm6dsl_ctrl9_xl_t ctrl9_xl;
5445 int32_t ret;
5446
5447 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5448 *val = ctrl9_xl.den_y;
5449
5450 return ret;
5451 }
5452
5453 /**
5454 * @brief DEN value stored in LSB of X-axis.[set]
5455 *
5456 * @param ctx Read / write interface definitions
5457 * @param val Change the values of den_x in reg CTRL9_XL
5458 * @retval Interface status (MANDATORY: return 0 -> no Error).
5459 *
5460 */
lsm6dsl_den_mark_axis_x_set(stmdev_ctx_t * ctx,uint8_t val)5461 int32_t lsm6dsl_den_mark_axis_x_set(stmdev_ctx_t *ctx, uint8_t val)
5462 {
5463 lsm6dsl_ctrl9_xl_t ctrl9_xl;
5464 int32_t ret;
5465
5466 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5467
5468 if (ret == 0)
5469 {
5470 ctrl9_xl.den_x = val;
5471 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5472 }
5473
5474 return ret;
5475 }
5476
5477 /**
5478 * @brief DEN value stored in LSB of X-axis.[get]
5479 *
5480 * @param ctx Read / write interface definitions
5481 * @param val Change the values of den_x in reg CTRL9_XL
5482 * @retval Interface status (MANDATORY: return 0 -> no Error).
5483 *
5484 */
lsm6dsl_den_mark_axis_x_get(stmdev_ctx_t * ctx,uint8_t * val)5485 int32_t lsm6dsl_den_mark_axis_x_get(stmdev_ctx_t *ctx, uint8_t *val)
5486 {
5487 lsm6dsl_ctrl9_xl_t ctrl9_xl;
5488 int32_t ret;
5489
5490 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
5491 *val = ctrl9_xl.den_x;
5492
5493 return ret;
5494 }
5495
5496 /**
5497 * @}
5498 *
5499 */
5500
5501 /**
5502 * @defgroup LSM6DSL_Pedometer
5503 * @brief This section groups all the functions that manage pedometer.
5504 * @{
5505 *
5506 */
5507
5508 /**
5509 * @brief Reset pedometer step counter.[set]
5510 *
5511 * @param ctx Read / write interface definitions
5512 * @param val Change the values of pedo_rst_step in reg CTRL10_C
5513 * @retval Interface status (MANDATORY: return 0 -> no Error).
5514 *
5515 */
lsm6dsl_pedo_step_reset_set(stmdev_ctx_t * ctx,uint8_t val)5516 int32_t lsm6dsl_pedo_step_reset_set(stmdev_ctx_t *ctx, uint8_t val)
5517 {
5518 lsm6dsl_ctrl10_c_t ctrl10_c;
5519 int32_t ret;
5520
5521 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
5522
5523 if (ret == 0)
5524 {
5525 ctrl10_c.pedo_rst_step = val;
5526 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
5527 }
5528
5529 return ret;
5530 }
5531
5532 /**
5533 * @brief Reset pedometer step counter.[get]
5534 *
5535 * @param ctx Read / write interface definitions
5536 * @param val Change the values of pedo_rst_step in reg CTRL10_C
5537 * @retval Interface status (MANDATORY: return 0 -> no Error).
5538 *
5539 */
lsm6dsl_pedo_step_reset_get(stmdev_ctx_t * ctx,uint8_t * val)5540 int32_t lsm6dsl_pedo_step_reset_get(stmdev_ctx_t *ctx, uint8_t *val)
5541 {
5542 lsm6dsl_ctrl10_c_t ctrl10_c;
5543 int32_t ret;
5544
5545 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
5546 *val = ctrl10_c.pedo_rst_step;
5547
5548 return ret;
5549 }
5550
5551 /**
5552 * @brief Enable pedometer algorithm.[set]
5553 *
5554 * @param ctx Read / write interface definitions
5555 * @param val Change the values of pedo_en in reg CTRL10_C
5556 * @retval Interface status (MANDATORY: return 0 -> no Error).
5557 *
5558 */
lsm6dsl_pedo_sens_set(stmdev_ctx_t * ctx,uint8_t val)5559 int32_t lsm6dsl_pedo_sens_set(stmdev_ctx_t *ctx, uint8_t val)
5560 {
5561 lsm6dsl_ctrl10_c_t ctrl10_c;
5562 int32_t ret;
5563
5564 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
5565
5566 if (ret == 0)
5567 {
5568 ctrl10_c.pedo_en = val;
5569
5570 if (val != 0x00U)
5571 {
5572 ctrl10_c.func_en = val;
5573 }
5574
5575 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
5576 }
5577
5578 return ret;
5579 }
5580
5581 /**
5582 * @brief pedo_sens: Enable pedometer algorithm.[get]
5583 *
5584 * @param ctx Read / write interface definitions
5585 * @param val Change the values of pedo_en in reg CTRL10_C
5586 * @retval Interface status (MANDATORY: return 0 -> no Error).
5587 *
5588 */
lsm6dsl_pedo_sens_get(stmdev_ctx_t * ctx,uint8_t * val)5589 int32_t lsm6dsl_pedo_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
5590 {
5591 lsm6dsl_ctrl10_c_t ctrl10_c;
5592 int32_t ret;
5593
5594 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
5595 *val = ctrl10_c.pedo_en;
5596
5597 return ret;
5598 }
5599
5600 /**
5601 * @brief Minimum threshold to detect a peak. Default is 10h.[set]
5602 *
5603 * @param ctx Read / write interface definitions
5604 * @param val Change the values of ths_min in reg
5605 * CONFIG_PEDO_THS_MIN
5606 * @retval Interface status (MANDATORY: return 0 -> no Error).
5607 *
5608 */
lsm6dsl_pedo_threshold_set(stmdev_ctx_t * ctx,uint8_t val)5609 int32_t lsm6dsl_pedo_threshold_set(stmdev_ctx_t *ctx, uint8_t val)
5610 {
5611 lsm6dsl_config_pedo_ths_min_t config_pedo_ths_min;
5612 int32_t ret;
5613
5614 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
5615
5616 if (ret == 0)
5617 {
5618 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN,
5619 (uint8_t *)&config_pedo_ths_min, 1);
5620
5621 if (ret == 0)
5622 {
5623 config_pedo_ths_min.ths_min = val;
5624 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN,
5625 (uint8_t *)&config_pedo_ths_min, 1);
5626
5627 if (ret == 0)
5628 {
5629 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
5630 }
5631 }
5632 }
5633
5634 return ret;
5635 }
5636
5637 /**
5638 * @brief Minimum threshold to detect a peak. Default is 10h.[get]
5639 *
5640 * @param ctx Read / write interface definitions
5641 * @param val Change the values of ths_min in reg CONFIG_PEDO_THS_MIN
5642 * @retval Interface status (MANDATORY: return 0 -> no Error).
5643 *
5644 */
lsm6dsl_pedo_threshold_get(stmdev_ctx_t * ctx,uint8_t * val)5645 int32_t lsm6dsl_pedo_threshold_get(stmdev_ctx_t *ctx, uint8_t *val)
5646 {
5647 lsm6dsl_config_pedo_ths_min_t config_pedo_ths_min;
5648 int32_t ret;
5649
5650 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
5651
5652 if (ret == 0)
5653 {
5654 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN,
5655 (uint8_t *)&config_pedo_ths_min, 1);
5656
5657 if (ret == 0)
5658 {
5659 *val = config_pedo_ths_min.ths_min;
5660 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
5661 }
5662 }
5663
5664 return ret;
5665 }
5666
5667 /**
5668 * @brief pedo_full_scale: Pedometer data range.[set]
5669 *
5670 * @param ctx Read / write interface definitions
5671 * @param val Change the values of pedo_fs in
5672 * reg CONFIG_PEDO_THS_MIN
5673 * @retval Interface status (MANDATORY: return 0 -> no Error).
5674 *
5675 */
lsm6dsl_pedo_full_scale_set(stmdev_ctx_t * ctx,lsm6dsl_pedo_fs_t val)5676 int32_t lsm6dsl_pedo_full_scale_set(stmdev_ctx_t *ctx,
5677 lsm6dsl_pedo_fs_t val)
5678 {
5679 lsm6dsl_config_pedo_ths_min_t config_pedo_ths_min;
5680 int32_t ret;
5681
5682 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
5683
5684 if (ret == 0)
5685 {
5686 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN,
5687 (uint8_t *)&config_pedo_ths_min, 1);
5688
5689 if (ret == 0)
5690 {
5691 config_pedo_ths_min.pedo_fs = (uint8_t) val;
5692 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN,
5693 (uint8_t *)&config_pedo_ths_min, 1);
5694
5695 if (ret == 0)
5696 {
5697 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
5698 }
5699 }
5700 }
5701
5702 return ret;
5703 }
5704
5705 /**
5706 * @brief Pedometer data range.[get]
5707 *
5708 * @param ctx Read / write interface definitions
5709 * @param val Get the values of pedo_fs in
5710 * reg CONFIG_PEDO_THS_MIN
5711 * @retval Interface status (MANDATORY: return 0 -> no Error).
5712 *
5713 */
lsm6dsl_pedo_full_scale_get(stmdev_ctx_t * ctx,lsm6dsl_pedo_fs_t * val)5714 int32_t lsm6dsl_pedo_full_scale_get(stmdev_ctx_t *ctx,
5715 lsm6dsl_pedo_fs_t *val)
5716 {
5717 lsm6dsl_config_pedo_ths_min_t config_pedo_ths_min;
5718 int32_t ret;
5719
5720 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
5721
5722 if (ret == 0)
5723 {
5724 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CONFIG_PEDO_THS_MIN,
5725 (uint8_t *)&config_pedo_ths_min, 1);
5726
5727 if (ret == 0)
5728 {
5729 switch (config_pedo_ths_min.pedo_fs)
5730 {
5731 case LSM6DSL_PEDO_AT_2g:
5732 *val = LSM6DSL_PEDO_AT_2g;
5733 break;
5734
5735 case LSM6DSL_PEDO_AT_4g:
5736 *val = LSM6DSL_PEDO_AT_4g;
5737 break;
5738
5739 default:
5740 *val = LSM6DSL_PEDO_FS_ND;
5741 break;
5742 }
5743
5744 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
5745 }
5746 }
5747
5748 return ret;
5749 }
5750
5751 /**
5752 * @brief Pedometer debounce configuration register (r/w).[set]
5753 *
5754 * @param ctx Read / write interface definitions
5755 * @param val Change the values of deb_step in reg PEDO_DEB_REG
5756 * @retval Interface status (MANDATORY: return 0 -> no Error).
5757 *
5758 */
lsm6dsl_pedo_debounce_steps_set(stmdev_ctx_t * ctx,uint8_t val)5759 int32_t lsm6dsl_pedo_debounce_steps_set(stmdev_ctx_t *ctx,
5760 uint8_t val)
5761 {
5762 lsm6dsl_pedo_deb_reg_t pedo_deb_reg;
5763 int32_t ret;
5764
5765 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
5766
5767 if (ret == 0)
5768 {
5769 ret = lsm6dsl_read_reg(ctx, LSM6DSL_PEDO_DEB_REG,
5770 (uint8_t *)&pedo_deb_reg, 1);
5771
5772 if (ret == 0)
5773 {
5774 pedo_deb_reg.deb_step = val;
5775 ret = lsm6dsl_write_reg(ctx, LSM6DSL_PEDO_DEB_REG,
5776 (uint8_t *)&pedo_deb_reg, 1);
5777
5778 if (ret == 0)
5779 {
5780 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
5781 }
5782 }
5783 }
5784
5785 return ret;
5786 }
5787
5788 /**
5789 * @brief Pedometer debounce configuration register (r/w).[get]
5790 *
5791 * @param ctx Read / write interface definitions
5792 * @param val Change the values of deb_step in reg PEDO_DEB_REG
5793 * @retval Interface status (MANDATORY: return 0 -> no Error).
5794 *
5795 */
lsm6dsl_pedo_debounce_steps_get(stmdev_ctx_t * ctx,uint8_t * val)5796 int32_t lsm6dsl_pedo_debounce_steps_get(stmdev_ctx_t *ctx,
5797 uint8_t *val)
5798 {
5799 lsm6dsl_pedo_deb_reg_t pedo_deb_reg;
5800 int32_t ret;
5801
5802 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
5803
5804 if (ret == 0)
5805 {
5806 ret = lsm6dsl_read_reg(ctx, LSM6DSL_PEDO_DEB_REG,
5807 (uint8_t *)&pedo_deb_reg, 1);
5808
5809 if (ret == 0)
5810 {
5811 *val = pedo_deb_reg.deb_step;
5812 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
5813 }
5814 }
5815
5816 return ret;
5817 }
5818
5819 /**
5820 * @brief Debounce time. If the time between two consecutive steps is
5821 * greater than DEB_TIME*80ms, the debouncer is reactivated.
5822 * Default value: 01101[set]
5823 *
5824 * @param ctx Read / write interface definitions
5825 * @param val Change the values of deb_time in reg PEDO_DEB_REG
5826 * @retval Interface status (MANDATORY: return 0 -> no Error).
5827 *
5828 */
lsm6dsl_pedo_timeout_set(stmdev_ctx_t * ctx,uint8_t val)5829 int32_t lsm6dsl_pedo_timeout_set(stmdev_ctx_t *ctx, uint8_t val)
5830 {
5831 lsm6dsl_pedo_deb_reg_t pedo_deb_reg;
5832 int32_t ret;
5833
5834 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
5835
5836 if (ret == 0)
5837 {
5838 ret = lsm6dsl_read_reg(ctx, LSM6DSL_PEDO_DEB_REG,
5839 (uint8_t *)&pedo_deb_reg, 1);
5840
5841 if (ret == 0)
5842 {
5843 pedo_deb_reg.deb_time = val;
5844 ret = lsm6dsl_write_reg(ctx, LSM6DSL_PEDO_DEB_REG,
5845 (uint8_t *)&pedo_deb_reg, 1);
5846
5847 if (ret == 0)
5848 {
5849 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
5850 }
5851 }
5852 }
5853
5854 return ret;
5855 }
5856
5857 /**
5858 * @brief Debounce time. If the time between two consecutive steps is
5859 * greater than DEB_TIME*80ms, the debouncer is reactivated.
5860 * Default value: 01101[get]
5861 *
5862 * @param ctx Read / write interface definitions
5863 * @param val Change the values of deb_time in reg PEDO_DEB_REG
5864 * @retval Interface status (MANDATORY: return 0 -> no Error).
5865 *
5866 */
lsm6dsl_pedo_timeout_get(stmdev_ctx_t * ctx,uint8_t * val)5867 int32_t lsm6dsl_pedo_timeout_get(stmdev_ctx_t *ctx, uint8_t *val)
5868 {
5869 lsm6dsl_pedo_deb_reg_t pedo_deb_reg;
5870 int32_t ret;
5871
5872 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
5873
5874 if (ret == 0)
5875 {
5876 ret = lsm6dsl_read_reg(ctx, LSM6DSL_PEDO_DEB_REG,
5877 (uint8_t *)&pedo_deb_reg, 1);
5878
5879 if (ret == 0)
5880 {
5881 *val = pedo_deb_reg.deb_time;
5882 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
5883 }
5884 }
5885
5886 return ret;
5887 }
5888
5889 /**
5890 * @brief Time period register for step detection on delta time (r/w).[set]
5891 *
5892 * @param ctx Read / write interface definitions
5893 * @param buff Buffer that contains data to write
5894 * @retval Interface status (MANDATORY: return 0 -> no Error).
5895 *
5896 */
lsm6dsl_pedo_steps_period_set(stmdev_ctx_t * ctx,uint8_t * buff)5897 int32_t lsm6dsl_pedo_steps_period_set(stmdev_ctx_t *ctx,
5898 uint8_t *buff)
5899 {
5900 int32_t ret;
5901
5902 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
5903
5904 if (ret == 0)
5905 {
5906 ret = lsm6dsl_write_reg(ctx, LSM6DSL_STEP_COUNT_DELTA, buff, 1);
5907
5908 if (ret == 0)
5909 {
5910 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
5911 }
5912 }
5913
5914 return ret;
5915 }
5916
5917 /**
5918 * @brief Time period register for step detection on delta time (r/w).[get]
5919 *
5920 * @param ctx Read / write interface definitions
5921 * @param buff Buffer that stores data read
5922 * @retval Interface status (MANDATORY: return 0 -> no Error).
5923 *
5924 */
lsm6dsl_pedo_steps_period_get(stmdev_ctx_t * ctx,uint8_t * buff)5925 int32_t lsm6dsl_pedo_steps_period_get(stmdev_ctx_t *ctx,
5926 uint8_t *buff)
5927 {
5928 int32_t ret;
5929
5930 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
5931
5932 if (ret == 0)
5933 {
5934 ret = lsm6dsl_read_reg(ctx, LSM6DSL_STEP_COUNT_DELTA, buff, 1);
5935
5936 if (ret == 0)
5937 {
5938 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
5939 }
5940 }
5941
5942 return ret;
5943 }
5944
5945 /**
5946 * @}
5947 *
5948 */
5949
5950 /**
5951 * @defgroup LSM6DSL_significant_motion
5952 * @brief This section groups all the functions that manage the
5953 * significant motion detection.
5954 * @{
5955 *
5956 */
5957
5958 /**
5959 * @brief Enable significant motion detection function.[set]
5960 *
5961 * @param ctx Read / write interface definitions
5962 * @param val Change the values of sign_motion_en in reg CTRL10_C
5963 * @retval Interface status (MANDATORY: return 0 -> no Error).
5964 *
5965 */
lsm6dsl_motion_sens_set(stmdev_ctx_t * ctx,uint8_t val)5966 int32_t lsm6dsl_motion_sens_set(stmdev_ctx_t *ctx, uint8_t val)
5967 {
5968 lsm6dsl_ctrl10_c_t ctrl10_c;
5969 int32_t ret;
5970
5971 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
5972
5973 if (ret == 0)
5974 {
5975 ctrl10_c.sign_motion_en = val;
5976
5977 if (val != 0x00U)
5978 {
5979 ctrl10_c.func_en = val;
5980 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
5981 }
5982 }
5983
5984 return ret;
5985 }
5986
5987 /**
5988 * @brief Enable significant motion detection function.[get]
5989 *
5990 * @param ctx Read / write interface definitions
5991 * @param val Change the values of sign_motion_en in reg CTRL10_C
5992 * @retval Interface status (MANDATORY: return 0 -> no Error).
5993 *
5994 */
lsm6dsl_motion_sens_get(stmdev_ctx_t * ctx,uint8_t * val)5995 int32_t lsm6dsl_motion_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
5996 {
5997 lsm6dsl_ctrl10_c_t ctrl10_c;
5998 int32_t ret;
5999
6000 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6001 *val = ctrl10_c.sign_motion_en;
6002
6003 return ret;
6004 }
6005
6006 /**
6007 * @brief Significant motion threshold.[set]
6008 *
6009 * @param ctx Read / write interface definitions
6010 * @param buff Buffer that store significant motion threshold.
6011 * @retval Interface status (MANDATORY: return 0 -> no Error).
6012 *
6013 */
lsm6dsl_motion_threshold_set(stmdev_ctx_t * ctx,uint8_t * buff)6014 int32_t lsm6dsl_motion_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
6015 {
6016 int32_t ret;
6017
6018 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
6019
6020 if (ret == 0)
6021 {
6022 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SM_THS, buff, 1);
6023
6024 if (ret == 0)
6025 {
6026 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
6027 }
6028 }
6029
6030 return ret;
6031 }
6032
6033 /**
6034 * @brief Significant motion threshold.[get]
6035 *
6036 * @param ctx Read / write interface definitions
6037 * @param buff Buffer that store significant motion threshold.
6038 * @retval Interface status (MANDATORY: return 0 -> no Error).
6039 *
6040 */
lsm6dsl_motion_threshold_get(stmdev_ctx_t * ctx,uint8_t * buff)6041 int32_t lsm6dsl_motion_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
6042 {
6043 int32_t ret;
6044
6045 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
6046
6047 if (ret == 0)
6048 {
6049 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SM_THS, buff, 1);
6050
6051 if (ret == 0)
6052 {
6053 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
6054 }
6055 }
6056
6057 return ret;
6058 }
6059
6060 /**
6061 * @}
6062 *
6063 */
6064
6065 /**
6066 * @defgroup LSM6DSL_tilt_detection
6067 * @brief This section groups all the functions that manage the tilt
6068 * event detection.
6069 * @{
6070 *
6071 */
6072
6073 /**
6074 * @brief Enable tilt calculation.[set]
6075 *
6076 * @param ctx Read / write interface definitions
6077 * @param val Change the values of tilt_en in reg CTRL10_C
6078 * @retval Interface status (MANDATORY: return 0 -> no Error).
6079 *
6080 */
lsm6dsl_tilt_sens_set(stmdev_ctx_t * ctx,uint8_t val)6081 int32_t lsm6dsl_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
6082 {
6083 lsm6dsl_ctrl10_c_t ctrl10_c;
6084 int32_t ret;
6085
6086 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6087
6088 if (ret == 0)
6089 {
6090 ctrl10_c.tilt_en = val;
6091
6092 if (val != 0x00U)
6093 {
6094 ctrl10_c.func_en = val;
6095 }
6096
6097 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6098 }
6099
6100 return ret;
6101 }
6102
6103 /**
6104 * @brief Enable tilt calculation.[get]
6105 *
6106 * @param ctx Read / write interface definitions
6107 * @param val Change the values of tilt_en in reg CTRL10_C
6108 * @retval Interface status (MANDATORY: return 0 -> no Error).
6109 *
6110 */
lsm6dsl_tilt_sens_get(stmdev_ctx_t * ctx,uint8_t * val)6111 int32_t lsm6dsl_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
6112 {
6113 lsm6dsl_ctrl10_c_t ctrl10_c;
6114 int32_t ret;
6115
6116 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6117 *val = ctrl10_c.tilt_en;
6118
6119 return ret;
6120 }
6121
6122 /**
6123 * @brief Enable tilt calculation.[set]
6124 *
6125 * @param ctx Read / write interface definitions
6126 * @param val Change the values of tilt_en in reg CTRL10_C
6127 * @retval Interface status (MANDATORY: return 0 -> no Error).
6128 *
6129 */
lsm6dsl_wrist_tilt_sens_set(stmdev_ctx_t * ctx,uint8_t val)6130 int32_t lsm6dsl_wrist_tilt_sens_set(stmdev_ctx_t *ctx, uint8_t val)
6131 {
6132 lsm6dsl_ctrl10_c_t ctrl10_c;
6133 int32_t ret;
6134
6135 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6136
6137 if (ret == 0)
6138 {
6139 ctrl10_c.wrist_tilt_en = val;
6140
6141 if (val != 0x00U)
6142 {
6143 ctrl10_c.func_en = val;
6144 }
6145
6146 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6147 }
6148
6149 return ret;
6150 }
6151
6152 /**
6153 * @brief Enable tilt calculation.[get]
6154 *
6155 * @param ctx Read / write interface definitions
6156 * @param val Change the values of tilt_en in reg CTRL10_C
6157 * @retval Interface status (MANDATORY: return 0 -> no Error).
6158 *
6159 */
lsm6dsl_wrist_tilt_sens_get(stmdev_ctx_t * ctx,uint8_t * val)6160 int32_t lsm6dsl_wrist_tilt_sens_get(stmdev_ctx_t *ctx, uint8_t *val)
6161 {
6162 lsm6dsl_ctrl10_c_t ctrl10_c;
6163 int32_t ret;
6164
6165 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6166 *val = ctrl10_c.wrist_tilt_en;
6167
6168 return ret;
6169 }
6170
6171 /**
6172 * @brief Absolute Wrist Tilt latency register (r/w).
6173 * Absolute wrist tilt latency parameters.
6174 * 1 LSB = 40 ms. Default value: 0Fh (600 ms).[set]
6175 *
6176 * @param ctx Read / write interface definitions
6177 * @param buff Buffer that contains data to write
6178 * @retval Interface status (MANDATORY: return 0 -> no Error).
6179 *
6180 */
lsm6dsl_tilt_latency_set(stmdev_ctx_t * ctx,uint8_t * buff)6181 int32_t lsm6dsl_tilt_latency_set(stmdev_ctx_t *ctx, uint8_t *buff)
6182 {
6183 int32_t ret;
6184
6185 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B);
6186
6187 if (ret == 0)
6188 {
6189 ret = lsm6dsl_write_reg(ctx, LSM6DSL_A_WRIST_TILT_LAT, buff, 1);
6190
6191 if (ret == 0)
6192 {
6193 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
6194 }
6195 }
6196
6197 return ret;
6198 }
6199
6200 /**
6201 * @brief Absolute Wrist Tilt latency register (r/w).
6202 * Absolute wrist tilt latency parameters.
6203 * 1 LSB = 40 ms. Default value: 0Fh (600 ms).[get]
6204 *
6205 * @param ctx Read / write interface definitions
6206 * @param buff Buffer that stores data read
6207 * @retval Interface status (MANDATORY: return 0 -> no Error).
6208 *
6209 */
lsm6dsl_tilt_latency_get(stmdev_ctx_t * ctx,uint8_t * buff)6210 int32_t lsm6dsl_tilt_latency_get(stmdev_ctx_t *ctx, uint8_t *buff)
6211 {
6212 int32_t ret;
6213
6214 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B);
6215
6216 if (ret == 0)
6217 {
6218 ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_LAT, buff, 1);
6219
6220 if (ret == 0)
6221 {
6222 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
6223 }
6224 }
6225
6226 return ret;
6227 }
6228
6229 /**
6230 * @brief Absolute Wrist Tilt threshold register(r/w).
6231 * Absolute wrist tilt threshold parameters.
6232 * 1 LSB = 15.625 mg.Default value: 20h (500 mg).[set]
6233 *
6234 * @param ctx Read / write interface definitions
6235 * @param buff Buffer that contains data to write
6236 * @retval Interface status (MANDATORY: return 0 -> no Error).
6237 *
6238 */
lsm6dsl_tilt_threshold_set(stmdev_ctx_t * ctx,uint8_t * buff)6239 int32_t lsm6dsl_tilt_threshold_set(stmdev_ctx_t *ctx, uint8_t *buff)
6240 {
6241 int32_t ret;
6242
6243 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B);
6244
6245 if (ret == 0)
6246 {
6247 ret = lsm6dsl_write_reg(ctx, LSM6DSL_A_WRIST_TILT_THS, buff, 1);
6248
6249 if (ret == 0)
6250 {
6251 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
6252 }
6253 }
6254
6255 return ret;
6256 }
6257
6258 /**
6259 * @brief Absolute Wrist Tilt threshold register(r/w).
6260 * Absolute wrist tilt threshold parameters.
6261 * 1 LSB = 15.625 mg.Default value: 20h (500 mg).[get]
6262 *
6263 * @param ctx Read / write interface definitions
6264 * @param buff Buffer that stores data read
6265 * @retval Interface status (MANDATORY: return 0 -> no Error).
6266 *
6267 */
lsm6dsl_tilt_threshold_get(stmdev_ctx_t * ctx,uint8_t * buff)6268 int32_t lsm6dsl_tilt_threshold_get(stmdev_ctx_t *ctx, uint8_t *buff)
6269 {
6270 int32_t ret;
6271
6272 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B);
6273
6274 if (ret == 0)
6275 {
6276 ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_THS, buff, 1);
6277
6278 if (ret == 0)
6279 {
6280 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
6281 }
6282 }
6283
6284 return ret;
6285 }
6286
6287 /**
6288 * @brief Absolute Wrist Tilt mask register (r/w).[set]
6289 *
6290 * @param ctx Read / write interface definitions
6291 * @param val Registers A_WRIST_TILT_MASK
6292 * @retval Interface status (MANDATORY: return 0 -> no Error).
6293 *
6294 */
lsm6dsl_tilt_src_set(stmdev_ctx_t * ctx,lsm6dsl_a_wrist_tilt_mask_t * val)6295 int32_t lsm6dsl_tilt_src_set(stmdev_ctx_t *ctx,
6296 lsm6dsl_a_wrist_tilt_mask_t *val)
6297 {
6298 int32_t ret;
6299
6300 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B);
6301
6302 if (ret == 0)
6303 {
6304 ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_MASK,
6305 (uint8_t *) val, 1);
6306
6307 if (ret == 0)
6308 {
6309 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
6310 }
6311 }
6312
6313 return ret;
6314 }
6315
6316 /**
6317 * @brief Absolute Wrist Tilt mask register (r/w).[get]
6318 *
6319 * @param ctx Read / write interface definitions
6320 * @param val Registers A_WRIST_TILT_MASK
6321 * @retval Interface status (MANDATORY: return 0 -> no Error).
6322 *
6323 */
lsm6dsl_tilt_src_get(stmdev_ctx_t * ctx,lsm6dsl_a_wrist_tilt_mask_t * val)6324 int32_t lsm6dsl_tilt_src_get(stmdev_ctx_t *ctx,
6325 lsm6dsl_a_wrist_tilt_mask_t *val)
6326 {
6327 int32_t ret;
6328
6329 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_B);
6330
6331 if (ret == 0)
6332 {
6333 ret = lsm6dsl_read_reg(ctx, LSM6DSL_A_WRIST_TILT_MASK,
6334 (uint8_t *) val, 1);
6335
6336 if (ret == 0)
6337 {
6338 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
6339 }
6340 }
6341
6342 return ret;
6343 }
6344
6345 /**
6346 * @}
6347 *
6348 */
6349
6350 /**
6351 * @defgroup LSM6DSL_ magnetometer_sensor
6352 * @brief This section groups all the functions that manage additional
6353 * magnetometer sensor.
6354 * @{
6355 *
6356 */
6357
6358 /**
6359 * @brief Enable soft-iron correction algorithm for magnetometer.[set]
6360 *
6361 * @param ctx Read / write interface definitions
6362 * @param val Change the values of soft_en in reg CTRL9_XL
6363 * @retval Interface status (MANDATORY: return 0 -> no Error).
6364 *
6365 */
lsm6dsl_mag_soft_iron_set(stmdev_ctx_t * ctx,uint8_t val)6366 int32_t lsm6dsl_mag_soft_iron_set(stmdev_ctx_t *ctx, uint8_t val)
6367 {
6368 lsm6dsl_ctrl9_xl_t ctrl9_xl;
6369 int32_t ret;
6370
6371 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6372
6373 if (ret == 0)
6374 {
6375 ctrl9_xl.soft_en = val;
6376 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6377 }
6378
6379 return ret;
6380 }
6381
6382 /**
6383 * @brief Enable soft-iron correction algorithm for magnetometer.[get]
6384 *
6385 * @param ctx Read / write interface definitions
6386 * @param val Change the values of soft_en in reg CTRL9_XL
6387 * @retval Interface status (MANDATORY: return 0 -> no Error).
6388 *
6389 */
lsm6dsl_mag_soft_iron_get(stmdev_ctx_t * ctx,uint8_t * val)6390 int32_t lsm6dsl_mag_soft_iron_get(stmdev_ctx_t *ctx, uint8_t *val)
6391 {
6392 lsm6dsl_ctrl9_xl_t ctrl9_xl;
6393 int32_t ret;
6394
6395 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL9_XL, (uint8_t *)&ctrl9_xl, 1);
6396 *val = ctrl9_xl.soft_en;
6397
6398 return ret;
6399 }
6400
6401 /**
6402 * @brief Enable hard-iron correction algorithm for magnetometer.[set]
6403 *
6404 * @param ctx Read / write interface definitions
6405 * @param val Change the values of iron_en in reg MASTER_CONFIG
6406 * @retval Interface status (MANDATORY: return 0 -> no Error).
6407 *
6408 */
lsm6dsl_mag_hard_iron_set(stmdev_ctx_t * ctx,uint8_t val)6409 int32_t lsm6dsl_mag_hard_iron_set(stmdev_ctx_t *ctx, uint8_t val)
6410 {
6411 lsm6dsl_master_config_t master_config;
6412 lsm6dsl_ctrl10_c_t ctrl10_c;
6413 int32_t ret;
6414
6415 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
6416 (uint8_t *)&master_config, 1);
6417
6418 if (ret == 0)
6419 {
6420 master_config.iron_en = val;
6421 ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG,
6422 (uint8_t *)&master_config, 1);
6423
6424 if (ret == 0)
6425 {
6426 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6427
6428 if (ret == 0)
6429 {
6430 if (val != 0x00U)
6431 {
6432 ctrl10_c.func_en = val;
6433 }
6434
6435 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C,
6436 (uint8_t *)&ctrl10_c, 1);
6437 }
6438 }
6439 }
6440
6441 return ret;
6442 }
6443
6444 /**
6445 * @brief Enable hard-iron correction algorithm for magnetometer.[get]
6446 *
6447 * @param ctx Read / write interface definitions
6448 * @param val Change the values of iron_en in reg MASTER_CONFIG
6449 * @retval Interface status (MANDATORY: return 0 -> no Error).
6450 *
6451 */
lsm6dsl_mag_hard_iron_get(stmdev_ctx_t * ctx,uint8_t * val)6452 int32_t lsm6dsl_mag_hard_iron_get(stmdev_ctx_t *ctx, uint8_t *val)
6453 {
6454 lsm6dsl_master_config_t master_config;
6455 int32_t ret;
6456
6457 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
6458 (uint8_t *)&master_config, 1);
6459 *val = master_config.iron_en;
6460
6461 return ret;
6462 }
6463
6464 /**
6465 * @brief Soft iron 3x3 matrix. Value are expressed in sign-module format.
6466 * (Es. SVVVVVVVb where S is the sign 0/+1/- and V is the value).[set]
6467 *
6468 * @param ctx Read / write interface definitions
6469 * @param buff Buffer that contains data to write
6470 * @retval Interface status (MANDATORY: return 0 -> no Error).
6471 *
6472 */
lsm6dsl_mag_soft_iron_mat_set(stmdev_ctx_t * ctx,uint8_t * buff)6473 int32_t lsm6dsl_mag_soft_iron_mat_set(stmdev_ctx_t *ctx,
6474 uint8_t *buff)
6475 {
6476 int32_t ret;
6477
6478 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
6479
6480 if (ret == 0)
6481 {
6482 ret = lsm6dsl_write_reg(ctx, LSM6DSL_MAG_SI_XX, buff, 9);
6483
6484 if (ret == 0)
6485 {
6486 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
6487 }
6488 }
6489
6490 return ret;
6491 }
6492
6493 /**
6494 * @brief Soft iron 3x3 matrix. Value are expressed in sign-module format.
6495 * (Es. SVVVVVVVb where S is the sign 0/+1/- and V is the value).[get]
6496 *
6497 * @param ctx Read / write interface definitions
6498 * @param buff Buffer that stores data read
6499 * @retval Interface status (MANDATORY: return 0 -> no Error).
6500 *
6501 */
lsm6dsl_mag_soft_iron_mat_get(stmdev_ctx_t * ctx,uint8_t * buff)6502 int32_t lsm6dsl_mag_soft_iron_mat_get(stmdev_ctx_t *ctx,
6503 uint8_t *buff)
6504 {
6505 int32_t ret;
6506
6507 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
6508
6509 if (ret == 0)
6510 {
6511 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MAG_SI_XX, buff, 9);
6512
6513 if (ret == 0)
6514 {
6515 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
6516 }
6517 }
6518
6519 return ret;
6520 }
6521
6522 /**
6523 * @brief Offset for hard-iron compensation register (r/w). The value is
6524 * expressed as a 16-bit word in two’s complement.[set]
6525 *
6526 * @param ctx Read / write interface definitions
6527 * @param buff Buffer that contains data to write
6528 * @retval Interface status (MANDATORY: return 0 -> no Error).
6529 *
6530 */
lsm6dsl_mag_offset_set(stmdev_ctx_t * ctx,int16_t * val)6531 int32_t lsm6dsl_mag_offset_set(stmdev_ctx_t *ctx, int16_t *val)
6532 {
6533 uint8_t buff[6];
6534 int32_t ret;
6535
6536 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
6537
6538 if (ret == 0)
6539 {
6540 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
6541 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
6542 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
6543 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
6544 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
6545 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
6546 ret = lsm6dsl_write_reg(ctx, LSM6DSL_MAG_OFFX_L, buff, 6);
6547
6548 if (ret == 0)
6549 {
6550 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
6551 }
6552 }
6553
6554 return ret;
6555 }
6556
6557 /**
6558 * @brief Offset for hard-iron compensation register(r/w).
6559 * The value is expressed as a 16-bit word in two’s complement.[get]
6560 *
6561 * @param ctx Read / write interface definitions
6562 * @param buff Buffer that stores data read
6563 * @retval Interface status (MANDATORY: return 0 -> no Error).
6564 *
6565 */
lsm6dsl_mag_offset_get(stmdev_ctx_t * ctx,int16_t * val)6566 int32_t lsm6dsl_mag_offset_get(stmdev_ctx_t *ctx, int16_t *val)
6567 {
6568 uint8_t buff[6];
6569 int32_t ret;
6570
6571 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
6572
6573 if (ret == 0)
6574 {
6575 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MAG_OFFX_L, buff, 6);
6576 val[0] = (int16_t)buff[1];
6577 val[0] = (val[0] * 256) + (int16_t)buff[0];
6578 val[1] = (int16_t)buff[3];
6579 val[1] = (val[1] * 256) + (int16_t)buff[2];
6580 val[2] = (int16_t)buff[5];
6581 val[2] = (val[2] * 256) + (int16_t)buff[4];
6582
6583 if (ret == 0)
6584 {
6585 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
6586 }
6587 }
6588
6589 return ret;
6590 }
6591
6592 /**
6593 * @}
6594 *
6595 */
6596
6597 /**
6598 * @defgroup LSM6DSL_Sensor_hub
6599 * @brief This section groups all the functions that manage the sensor
6600 * hub functionality.
6601 * @{
6602 *
6603 */
6604
6605 /**
6606 * @brief Enable function.[set]
6607 *
6608 * @param ctx Read / write interface definitions
6609 * @param val Change the values func_en
6610 * @retval Interface status (MANDATORY: return 0 -> no Error).
6611 *
6612 */
lsm6dsl_func_en_set(stmdev_ctx_t * ctx,uint8_t val)6613 int32_t lsm6dsl_func_en_set(stmdev_ctx_t *ctx, uint8_t val)
6614 {
6615 lsm6dsl_ctrl10_c_t ctrl10_c;
6616 int32_t ret;
6617
6618 ret = lsm6dsl_read_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6619
6620 if (ret == 0)
6621 {
6622 ctrl10_c.func_en = val;
6623 ret = lsm6dsl_write_reg(ctx, LSM6DSL_CTRL10_C, (uint8_t *)&ctrl10_c, 1);
6624 }
6625
6626 return ret;
6627 }
6628
6629 /**
6630 * @brief Sensor synchronization time frame with the step of 500 ms and
6631 * full range of 5s. Unsigned 8-bit.[set]
6632 *
6633 * @param ctx Read / write interface definitions
6634 * @param val Change the values of tph in reg SENSOR_SYNC_TIME_FRAME
6635 * @retval Interface status (MANDATORY: return 0 -> no Error).
6636 *
6637 */
lsm6dsl_sh_sync_sens_frame_set(stmdev_ctx_t * ctx,uint8_t val)6638 int32_t lsm6dsl_sh_sync_sens_frame_set(stmdev_ctx_t *ctx, uint8_t val)
6639 {
6640 lsm6dsl_sensor_sync_time_frame_t sensor_sync_time_frame;
6641 int32_t ret;
6642
6643 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSOR_SYNC_TIME_FRAME,
6644 (uint8_t *)&sensor_sync_time_frame, 1);
6645
6646 if (ret == 0)
6647 {
6648 sensor_sync_time_frame.tph = val;
6649 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SENSOR_SYNC_TIME_FRAME,
6650 (uint8_t *)&sensor_sync_time_frame, 1);
6651 }
6652
6653 return ret;
6654 }
6655
6656 /**
6657 * @brief Sensor synchronization time frame with the step of 500 ms and
6658 * full range of 5s. Unsigned 8-bit.[get]
6659 *
6660 * @param ctx Read / write interface definitions
6661 * @param val Change the values of tph in reg SENSOR_SYNC_TIME_FRAME
6662 * @retval Interface status (MANDATORY: return 0 -> no Error).
6663 *
6664 */
lsm6dsl_sh_sync_sens_frame_get(stmdev_ctx_t * ctx,uint8_t * val)6665 int32_t lsm6dsl_sh_sync_sens_frame_get(stmdev_ctx_t *ctx,
6666 uint8_t *val)
6667 {
6668 lsm6dsl_sensor_sync_time_frame_t sensor_sync_time_frame;
6669 int32_t ret;
6670
6671 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSOR_SYNC_TIME_FRAME,
6672 (uint8_t *)&sensor_sync_time_frame, 1);
6673 *val = sensor_sync_time_frame.tph;
6674
6675 return ret;
6676 }
6677
6678 /**
6679 * @brief Resolution ratio of error code for sensor synchronization.[set]
6680 *
6681 * @param ctx Read / write interface definitions
6682 * @param val Change the values of rr in reg SENSOR_SYNC_RES_RATIO
6683 * @retval Interface status (MANDATORY: return 0 -> no Error).
6684 *
6685 */
lsm6dsl_sh_sync_sens_ratio_set(stmdev_ctx_t * ctx,lsm6dsl_rr_t val)6686 int32_t lsm6dsl_sh_sync_sens_ratio_set(stmdev_ctx_t *ctx,
6687 lsm6dsl_rr_t val)
6688 {
6689 lsm6dsl_sensor_sync_res_ratio_t sensor_sync_res_ratio;
6690 int32_t ret;
6691
6692 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSOR_SYNC_RES_RATIO,
6693 (uint8_t *)&sensor_sync_res_ratio, 1);
6694
6695 if (ret == 0)
6696 {
6697 sensor_sync_res_ratio.rr = (uint8_t) val;
6698 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SENSOR_SYNC_RES_RATIO,
6699 (uint8_t *)&sensor_sync_res_ratio, 1);
6700 }
6701
6702 return ret;
6703 }
6704
6705 /**
6706 * @brief Resolution ratio of error code for sensor synchronization.[get]
6707 *
6708 * @param ctx Read / write interface definitions
6709 * @param val Get the values of rr in reg SENSOR_SYNC_RES_RATIO
6710 * @retval Interface status (MANDATORY: return 0 -> no Error).
6711 *
6712 */
lsm6dsl_sh_sync_sens_ratio_get(stmdev_ctx_t * ctx,lsm6dsl_rr_t * val)6713 int32_t lsm6dsl_sh_sync_sens_ratio_get(stmdev_ctx_t *ctx,
6714 lsm6dsl_rr_t *val)
6715 {
6716 lsm6dsl_sensor_sync_res_ratio_t sensor_sync_res_ratio;
6717 int32_t ret;
6718
6719 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSOR_SYNC_RES_RATIO,
6720 (uint8_t *)&sensor_sync_res_ratio, 1);
6721
6722 switch (sensor_sync_res_ratio.rr)
6723 {
6724 case LSM6DSL_RES_RATIO_2_11:
6725 *val = LSM6DSL_RES_RATIO_2_11;
6726 break;
6727
6728 case LSM6DSL_RES_RATIO_2_12:
6729 *val = LSM6DSL_RES_RATIO_2_12;
6730 break;
6731
6732 case LSM6DSL_RES_RATIO_2_13:
6733 *val = LSM6DSL_RES_RATIO_2_13;
6734 break;
6735
6736 case LSM6DSL_RES_RATIO_2_14:
6737 *val = LSM6DSL_RES_RATIO_2_14;
6738 break;
6739
6740 default:
6741 *val = LSM6DSL_RES_RATIO_ND;
6742 break;
6743 }
6744
6745 return ret;
6746 }
6747
6748 /**
6749 * @brief Sensor hub I2C master enable.[set]
6750 *
6751 * @param ctx Read / write interface definitions
6752 * @param val Change the values of master_on in reg MASTER_CONFIG
6753 * @retval Interface status (MANDATORY: return 0 -> no Error).
6754 *
6755 */
lsm6dsl_sh_master_set(stmdev_ctx_t * ctx,uint8_t val)6756 int32_t lsm6dsl_sh_master_set(stmdev_ctx_t *ctx, uint8_t val)
6757 {
6758 lsm6dsl_master_config_t master_config;
6759 int32_t ret;
6760
6761 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
6762 (uint8_t *)&master_config, 1);
6763
6764 if (ret == 0)
6765 {
6766 master_config.master_on = val;
6767 ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG,
6768 (uint8_t *)&master_config, 1);
6769 }
6770
6771 return ret;
6772 }
6773
6774 /**
6775 * @brief Sensor hub I2C master enable.[get]
6776 *
6777 * @param ctx Read / write interface definitions
6778 * @param val Change the values of master_on in reg MASTER_CONFIG
6779 * @retval Interface status (MANDATORY: return 0 -> no Error).
6780 *
6781 */
lsm6dsl_sh_master_get(stmdev_ctx_t * ctx,uint8_t * val)6782 int32_t lsm6dsl_sh_master_get(stmdev_ctx_t *ctx, uint8_t *val)
6783 {
6784 lsm6dsl_master_config_t master_config;
6785 int32_t ret;
6786
6787 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
6788 (uint8_t *)&master_config, 1);
6789 *val = master_config.master_on;
6790
6791 return ret;
6792 }
6793
6794 /**
6795 * @brief I2C interface pass-through.[set]
6796 *
6797 * @param ctx Read / write interface definitions
6798 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
6799 * @retval Interface status (MANDATORY: return 0 -> no Error).
6800 *
6801 */
lsm6dsl_sh_pass_through_set(stmdev_ctx_t * ctx,uint8_t val)6802 int32_t lsm6dsl_sh_pass_through_set(stmdev_ctx_t *ctx, uint8_t val)
6803 {
6804 lsm6dsl_master_config_t master_config;
6805 int32_t ret;
6806
6807 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
6808 (uint8_t *)&master_config, 1);
6809
6810 if (ret == 0)
6811 {
6812 master_config.pass_through_mode = val;
6813 ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG,
6814 (uint8_t *)&master_config, 1);
6815 }
6816
6817 return ret;
6818 }
6819
6820 /**
6821 * @brief I2C interface pass-through.[get]
6822 *
6823 * @param ctx Read / write interface definitions
6824 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
6825 * @retval Interface status (MANDATORY: return 0 -> no Error).
6826 *
6827 */
lsm6dsl_sh_pass_through_get(stmdev_ctx_t * ctx,uint8_t * val)6828 int32_t lsm6dsl_sh_pass_through_get(stmdev_ctx_t *ctx, uint8_t *val)
6829 {
6830 lsm6dsl_master_config_t master_config;
6831 int32_t ret;
6832
6833 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
6834 (uint8_t *)&master_config, 1);
6835 *val = master_config.pass_through_mode;
6836
6837 return ret;
6838 }
6839
6840 /**
6841 * @brief Master I2C pull-up enable/disable.[set]
6842 *
6843 * @param ctx Read / write interface definitions
6844 * @param val Change the values of pull_up_en in reg MASTER_CONFIG
6845 * @retval Interface status (MANDATORY: return 0 -> no Error).
6846 *
6847 */
lsm6dsl_sh_pin_mode_set(stmdev_ctx_t * ctx,lsm6dsl_pull_up_en_t val)6848 int32_t lsm6dsl_sh_pin_mode_set(stmdev_ctx_t *ctx,
6849 lsm6dsl_pull_up_en_t val)
6850 {
6851 lsm6dsl_master_config_t master_config;
6852 int32_t ret;
6853
6854 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
6855 (uint8_t *)&master_config, 1);
6856
6857 if (ret == 0)
6858 {
6859 master_config.pull_up_en = (uint8_t) val;
6860 ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG,
6861 (uint8_t *)&master_config, 1);
6862 }
6863
6864 return ret;
6865 }
6866
6867 /**
6868 * @brief Master I2C pull-up enable/disable.[get]
6869 *
6870 * @param ctx Read / write interface definitions
6871 * @param val Get the values of pull_up_en in reg MASTER_CONFIG
6872 * @retval Interface status (MANDATORY: return 0 -> no Error).
6873 *
6874 */
lsm6dsl_sh_pin_mode_get(stmdev_ctx_t * ctx,lsm6dsl_pull_up_en_t * val)6875 int32_t lsm6dsl_sh_pin_mode_get(stmdev_ctx_t *ctx,
6876 lsm6dsl_pull_up_en_t *val)
6877 {
6878 lsm6dsl_master_config_t master_config;
6879 int32_t ret;
6880
6881 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
6882 (uint8_t *)&master_config, 1);
6883
6884 switch (master_config.pull_up_en)
6885 {
6886 case LSM6DSL_EXT_PULL_UP:
6887 *val = LSM6DSL_EXT_PULL_UP;
6888 break;
6889
6890 case LSM6DSL_INTERNAL_PULL_UP:
6891 *val = LSM6DSL_INTERNAL_PULL_UP;
6892 break;
6893
6894 default:
6895 *val = LSM6DSL_SH_PIN_MODE;
6896 break;
6897 }
6898
6899 return ret;
6900 }
6901
6902 /**
6903 * @brief Sensor hub trigger signal selection.[set]
6904 *
6905 * @param ctx Read / write interface definitions
6906 * @param val Change the values of start_config in reg MASTER_CONFIG
6907 * @retval Interface status (MANDATORY: return 0 -> no Error).
6908 *
6909 */
lsm6dsl_sh_syncro_mode_set(stmdev_ctx_t * ctx,lsm6dsl_start_config_t val)6910 int32_t lsm6dsl_sh_syncro_mode_set(stmdev_ctx_t *ctx,
6911 lsm6dsl_start_config_t val)
6912 {
6913 lsm6dsl_master_config_t master_config;
6914 int32_t ret;
6915
6916 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
6917 (uint8_t *)&master_config, 1);
6918
6919 if (ret == 0)
6920 {
6921 master_config.start_config = (uint8_t)val;
6922 ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG,
6923 (uint8_t *)&master_config, 1);
6924 }
6925
6926 return ret;
6927 }
6928
6929 /**
6930 * @brief Sensor hub trigger signal selection.[get]
6931 *
6932 * @param ctx Read / write interface definitions
6933 * @param val Get the values of start_config in reg MASTER_CONFIG
6934 * @retval Interface status (MANDATORY: return 0 -> no Error).
6935 *
6936 */
lsm6dsl_sh_syncro_mode_get(stmdev_ctx_t * ctx,lsm6dsl_start_config_t * val)6937 int32_t lsm6dsl_sh_syncro_mode_get(stmdev_ctx_t *ctx,
6938 lsm6dsl_start_config_t *val)
6939 {
6940 lsm6dsl_master_config_t master_config;
6941 int32_t ret;
6942
6943 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
6944 (uint8_t *)&master_config, 1);
6945
6946 switch (master_config.start_config)
6947 {
6948 case LSM6DSL_XL_GY_DRDY:
6949 *val = LSM6DSL_XL_GY_DRDY;
6950 break;
6951
6952 case LSM6DSL_EXT_ON_INT2_PIN:
6953 *val = LSM6DSL_EXT_ON_INT2_PIN;
6954 break;
6955
6956 default:
6957 *val = LSM6DSL_SH_SYNCRO_ND;
6958 break;
6959 }
6960
6961 return ret;
6962 }
6963
6964 /**
6965 * @brief Manage the Master DRDY signal on INT1 pad.[set]
6966 *
6967 * @param ctx Read / write interface definitions
6968 * @param val Change the values of drdy_on_int1 in reg MASTER_CONFIG
6969 * @retval Interface status (MANDATORY: return 0 -> no Error).
6970 *
6971 */
lsm6dsl_sh_drdy_on_int1_set(stmdev_ctx_t * ctx,uint8_t val)6972 int32_t lsm6dsl_sh_drdy_on_int1_set(stmdev_ctx_t *ctx, uint8_t val)
6973 {
6974 lsm6dsl_master_config_t master_config;
6975 int32_t ret;
6976
6977 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
6978 (uint8_t *)&master_config, 1);
6979
6980 if (ret == 0)
6981 {
6982 master_config.drdy_on_int1 = val;
6983 ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CONFIG,
6984 (uint8_t *)&master_config, 1);
6985 }
6986
6987 return ret;
6988 }
6989
6990 /**
6991 * @brief Manage the Master DRDY signal on INT1 pad.[get]
6992 *
6993 * @param ctx Read / write interface definitions
6994 * @param val Change the values of drdy_on_int1 in reg MASTER_CONFIG
6995 * @retval Interface status (MANDATORY: return 0 -> no Error).
6996 *
6997 */
lsm6dsl_sh_drdy_on_int1_get(stmdev_ctx_t * ctx,uint8_t * val)6998 int32_t lsm6dsl_sh_drdy_on_int1_get(stmdev_ctx_t *ctx, uint8_t *val)
6999 {
7000 lsm6dsl_master_config_t master_config;
7001 int32_t ret;
7002
7003 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CONFIG,
7004 (uint8_t *)&master_config, 1);
7005 *val = master_config.drdy_on_int1;
7006
7007 return ret;
7008 }
7009
7010 /**
7011 * @brief Sensor hub output registers.[get]
7012 *
7013 * @param ctx Read / write interface definitions
7014 * @param val Structure of registers from SENSORHUB1_REG
7015 * @retval Interface status (MANDATORY: return 0 -> no Error).
7016 *
7017 */
lsm6dsl_sh_read_data_raw_get(stmdev_ctx_t * ctx,lsm6dsl_emb_sh_read_t * val)7018 int32_t lsm6dsl_sh_read_data_raw_get(stmdev_ctx_t *ctx,
7019 lsm6dsl_emb_sh_read_t *val)
7020 {
7021 int32_t ret;
7022
7023 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSORHUB1_REG,
7024 (uint8_t *) & (val->sh_byte_1), 12);
7025
7026 if (ret == 0)
7027 {
7028 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENSORHUB13_REG,
7029 (uint8_t *) & (val->sh_byte_13), 6);
7030 }
7031
7032 return ret;
7033 }
7034
7035 /**
7036 * @brief Master command code used for stamping for sensor sync.[set]
7037 *
7038 * @param ctx Read / write interface definitions
7039 * @param val Change the values of master_cmd_code in
7040 * reg MASTER_CMD_CODE
7041 * @retval Interface status (MANDATORY: return 0 -> no Error).
7042 *
7043 */
lsm6dsl_sh_cmd_sens_sync_set(stmdev_ctx_t * ctx,uint8_t val)7044 int32_t lsm6dsl_sh_cmd_sens_sync_set(stmdev_ctx_t *ctx, uint8_t val)
7045 {
7046 lsm6dsl_master_cmd_code_t master_cmd_code;
7047 int32_t ret;
7048
7049 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CMD_CODE,
7050 (uint8_t *)&master_cmd_code, 1);
7051
7052 if (ret == 0)
7053 {
7054 master_cmd_code.master_cmd_code = val;
7055 ret = lsm6dsl_write_reg(ctx, LSM6DSL_MASTER_CMD_CODE,
7056 (uint8_t *)&master_cmd_code, 1);
7057 }
7058
7059 return ret;
7060 }
7061
7062 /**
7063 * @brief Master command code used for stamping for sensor sync.[get]
7064 *
7065 * @param ctx Read / write interface definitions
7066 * @param val Change the values of master_cmd_code in
7067 * reg MASTER_CMD_CODE
7068 * @retval Interface status (MANDATORY: return 0 -> no Error).
7069 *
7070 */
lsm6dsl_sh_cmd_sens_sync_get(stmdev_ctx_t * ctx,uint8_t * val)7071 int32_t lsm6dsl_sh_cmd_sens_sync_get(stmdev_ctx_t *ctx, uint8_t *val)
7072 {
7073 lsm6dsl_master_cmd_code_t master_cmd_code;
7074 int32_t ret;
7075
7076 ret = lsm6dsl_read_reg(ctx, LSM6DSL_MASTER_CMD_CODE,
7077 (uint8_t *)&master_cmd_code, 1);
7078 *val = master_cmd_code.master_cmd_code;
7079
7080 return ret;
7081 }
7082
7083 /**
7084 * @brief Error code used for sensor synchronization.[set]
7085 *
7086 * @param ctx Read / write interface definitions
7087 * @param val Change the values of error_code in
7088 * reg SENS_SYNC_SPI_ERROR_CODE.
7089 * @retval Interface status (MANDATORY: return 0 -> no Error).
7090 *
7091 */
lsm6dsl_sh_spi_sync_error_set(stmdev_ctx_t * ctx,uint8_t val)7092 int32_t lsm6dsl_sh_spi_sync_error_set(stmdev_ctx_t *ctx, uint8_t val)
7093 {
7094 lsm6dsl_sens_sync_spi_error_code_t sens_sync_spi_error_code;
7095 int32_t ret;
7096
7097 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENS_SYNC_SPI_ERROR_CODE,
7098 (uint8_t *)&sens_sync_spi_error_code, 1);
7099
7100 if (ret == 0)
7101 {
7102 sens_sync_spi_error_code.error_code = val;
7103 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SENS_SYNC_SPI_ERROR_CODE,
7104 (uint8_t *)&sens_sync_spi_error_code, 1);
7105 }
7106
7107 return ret;
7108 }
7109
7110 /**
7111 * @brief Error code used for sensor synchronization.[get]
7112 *
7113 * @param ctx Read / write interface definitions
7114 * @param val Change the values of error_code in
7115 * reg SENS_SYNC_SPI_ERROR_CODE.
7116 * @retval Interface status (MANDATORY: return 0 -> no Error).
7117 *
7118 */
lsm6dsl_sh_spi_sync_error_get(stmdev_ctx_t * ctx,uint8_t * val)7119 int32_t lsm6dsl_sh_spi_sync_error_get(stmdev_ctx_t *ctx, uint8_t *val)
7120 {
7121 lsm6dsl_sens_sync_spi_error_code_t sens_sync_spi_error_code;
7122 int32_t ret;
7123
7124 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SENS_SYNC_SPI_ERROR_CODE,
7125 (uint8_t *)&sens_sync_spi_error_code, 1);
7126 *val = sens_sync_spi_error_code.error_code;
7127
7128 return ret;
7129 }
7130
7131 /**
7132 * @brief Number of external sensors to be read by the sensor hub.[set]
7133 *
7134 * @param ctx Read / write interface definitions
7135 * @param val Change the values of aux_sens_on in reg SLAVE0_CONFIG.
7136 * @retval Interface status (MANDATORY: return 0 -> no Error).
7137 *
7138 */
lsm6dsl_sh_num_of_dev_connected_set(stmdev_ctx_t * ctx,lsm6dsl_aux_sens_on_t val)7139 int32_t lsm6dsl_sh_num_of_dev_connected_set(stmdev_ctx_t *ctx,
7140 lsm6dsl_aux_sens_on_t val)
7141 {
7142 lsm6dsl_slave0_config_t slave0_config;
7143 int32_t ret;
7144
7145 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
7146
7147 if (ret == 0)
7148 {
7149 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE0_CONFIG,
7150 (uint8_t *)&slave0_config, 1);
7151
7152 if (ret == 0)
7153 {
7154 slave0_config.aux_sens_on = (uint8_t) val;
7155 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE0_CONFIG,
7156 (uint8_t *)&slave0_config, 1);
7157
7158 if (ret == 0)
7159 {
7160 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
7161 }
7162 }
7163 }
7164
7165 return ret;
7166 }
7167
7168 /**
7169 * @brief Number of external sensors to be read by the sensor hub.[get]
7170 *
7171 * @param ctx Read / write interface definitions
7172 * @param val Get the values of aux_sens_on in reg SLAVE0_CONFIG.
7173 * @retval Interface status (MANDATORY: return 0 -> no Error).
7174 *
7175 */
lsm6dsl_sh_num_of_dev_connected_get(stmdev_ctx_t * ctx,lsm6dsl_aux_sens_on_t * val)7176 int32_t lsm6dsl_sh_num_of_dev_connected_get(stmdev_ctx_t *ctx,
7177 lsm6dsl_aux_sens_on_t *val)
7178 {
7179 lsm6dsl_slave0_config_t slave0_config;
7180 int32_t ret;
7181
7182 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
7183
7184 if (ret == 0)
7185 {
7186 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE0_CONFIG,
7187 (uint8_t *)&slave0_config, 1);
7188
7189 if (ret == 0)
7190 {
7191 switch (slave0_config.aux_sens_on)
7192 {
7193 case LSM6DSL_SLV_0:
7194 *val = LSM6DSL_SLV_0;
7195 break;
7196
7197 case LSM6DSL_SLV_0_1:
7198 *val = LSM6DSL_SLV_0_1;
7199 break;
7200
7201 case LSM6DSL_SLV_0_1_2:
7202 *val = LSM6DSL_SLV_0_1_2;
7203 break;
7204
7205 case LSM6DSL_SLV_0_1_2_3:
7206 *val = LSM6DSL_SLV_0_1_2_3;
7207 break;
7208
7209 default:
7210 *val = LSM6DSL_SLV_EN_ND;
7211 break;
7212 }
7213
7214 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
7215 }
7216 }
7217
7218 return ret;
7219 }
7220
7221 /**
7222 * @brief Configure slave 0 for perform a write.[set]
7223 *
7224 * @param ctx Read / write interface definitions
7225 * @param val Structure that contain:
7226 * - uint8_t slv_add; 8 bit i2c device address
7227 * - uint8_t slv_subadd; 8 bit register device address
7228 * - uint8_t slv_data; 8 bit data to write
7229 * @retval Interface status (MANDATORY: return 0 -> no Error).
7230 *
7231 */
lsm6dsl_sh_cfg_write(stmdev_ctx_t * ctx,lsm6dsl_sh_cfg_write_t * val)7232 int32_t lsm6dsl_sh_cfg_write(stmdev_ctx_t *ctx,
7233 lsm6dsl_sh_cfg_write_t *val)
7234 {
7235 lsm6dsl_slv0_add_t slv0_add;
7236 int32_t ret;
7237
7238 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
7239
7240 if (ret == 0)
7241 {
7242 slv0_add.slave0_add = val->slv0_add;
7243 slv0_add.rw_0 = 0;
7244 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV0_ADD, (uint8_t *)&slv0_add, 1);
7245
7246 if (ret == 0)
7247 {
7248 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV0_SUBADD,
7249 &(val->slv0_subadd), 1);
7250
7251 if (ret == 0)
7252 {
7253 ret = lsm6dsl_write_reg(ctx, LSM6DSL_DATAWRITE_SRC_MODE_SUB_SLV0,
7254 &(val->slv0_data), 1);
7255
7256 if (ret == 0)
7257 {
7258 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
7259 }
7260 }
7261 }
7262 }
7263
7264 return ret;
7265 }
7266
7267 /**
7268 * @brief Configure slave 0 for perform a read.[get]
7269 *
7270 * @param ctx Read / write interface definitions
7271 * @param val Structure that contain:
7272 * - uint8_t slv_add; 8 bit i2c device address
7273 * - uint8_t slv_subadd; 8 bit register device address
7274 * - uint8_t slv_len; num of bit to read
7275 * @retval Interface status (MANDATORY: return 0 -> no Error).
7276 *
7277 */
lsm6dsl_sh_slv0_cfg_read(stmdev_ctx_t * ctx,lsm6dsl_sh_cfg_read_t * val)7278 int32_t lsm6dsl_sh_slv0_cfg_read(stmdev_ctx_t *ctx,
7279 lsm6dsl_sh_cfg_read_t *val)
7280 {
7281 lsm6dsl_slave0_config_t slave0_config;
7282 lsm6dsl_slv0_add_t slv0_add;
7283 int32_t ret;
7284
7285 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
7286
7287 if (ret == 0)
7288 {
7289 slv0_add.slave0_add = val->slv_add;
7290 slv0_add.rw_0 = 1;
7291 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV0_ADD, (uint8_t *)&slv0_add, 1);
7292
7293 if (ret == 0)
7294 {
7295 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV0_SUBADD,
7296 &(val->slv_subadd), 1);
7297
7298 if (ret == 0)
7299 {
7300 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE0_CONFIG,
7301 (uint8_t *)&slave0_config, 1);
7302 slave0_config.slave0_numop = val->slv_len;
7303
7304 if (ret == 0)
7305 {
7306 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE0_CONFIG,
7307 (uint8_t *)&slave0_config, 1);
7308
7309 if (ret == 0)
7310 {
7311 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
7312 }
7313 }
7314 }
7315 }
7316 }
7317
7318 return ret;
7319 }
7320
7321 /**
7322 * @brief Configure slave 1 for perform a read.[get]
7323 *
7324 * @param ctx Read / write interface definitions
7325 * @param val Structure that contain:
7326 * - uint8_t slv_add; 8 bit i2c device address
7327 * - uint8_t slv_subadd; 8 bit register device address
7328 * - uint8_t slv_len; num of bit to read
7329 * @retval Interface status (MANDATORY: return 0 -> no Error).
7330 *
7331 */
lsm6dsl_sh_slv1_cfg_read(stmdev_ctx_t * ctx,lsm6dsl_sh_cfg_read_t * val)7332 int32_t lsm6dsl_sh_slv1_cfg_read(stmdev_ctx_t *ctx,
7333 lsm6dsl_sh_cfg_read_t *val)
7334 {
7335 lsm6dsl_slave1_config_t slave1_config;
7336 lsm6dsl_slv1_add_t slv1_add;
7337 int32_t ret;
7338
7339 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
7340
7341 if (ret == 0)
7342 {
7343 slv1_add.slave1_add = val->slv_add;
7344 slv1_add.r_1 = 1;
7345 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV1_ADD, (uint8_t *)&slv1_add, 1);
7346
7347 if (ret == 0)
7348 {
7349 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV1_SUBADD,
7350 &(val->slv_subadd), 1);
7351
7352 if (ret == 0)
7353 {
7354 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
7355 (uint8_t *)&slave1_config, 1);
7356 slave1_config.slave1_numop = val->slv_len;
7357
7358 if (ret == 0)
7359 {
7360 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
7361 (uint8_t *)&slave1_config, 1);
7362
7363 if (ret == 0)
7364 {
7365 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
7366 }
7367 }
7368 }
7369 }
7370 }
7371
7372 return ret;
7373 }
7374
7375 /**
7376 * @brief Configure slave 2 for perform a read.[get]
7377 *
7378 * @param ctx Read / write interface definitions
7379 * @param val Structure that contain:
7380 * - uint8_t slv_add; 8 bit i2c device address
7381 * - uint8_t slv_subadd; 8 bit register device address
7382 * - uint8_t slv_len; num of bit to read
7383 * @retval Interface status (MANDATORY: return 0 -> no Error).
7384 *
7385 */
lsm6dsl_sh_slv2_cfg_read(stmdev_ctx_t * ctx,lsm6dsl_sh_cfg_read_t * val)7386 int32_t lsm6dsl_sh_slv2_cfg_read(stmdev_ctx_t *ctx,
7387 lsm6dsl_sh_cfg_read_t *val)
7388 {
7389 lsm6dsl_slv2_add_t slv2_add;
7390 lsm6dsl_slave2_config_t slave2_config;
7391 int32_t ret;
7392
7393 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
7394
7395 if (ret == 0)
7396 {
7397 slv2_add.slave2_add = val->slv_add;
7398 slv2_add.r_2 = 1;
7399 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV2_ADD, (uint8_t *)&slv2_add, 1);
7400
7401 if (ret == 0)
7402 {
7403 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV2_SUBADD,
7404 &(val->slv_subadd), 1);
7405
7406 if (ret == 0)
7407 {
7408 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE2_CONFIG,
7409 (uint8_t *)&slave2_config, 1);
7410
7411 if (ret == 0)
7412 {
7413 slave2_config.slave2_numop = val->slv_len;
7414 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE2_CONFIG,
7415 (uint8_t *)&slave2_config, 1);
7416
7417 if (ret == 0)
7418 {
7419 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
7420 }
7421 }
7422 }
7423 }
7424 }
7425
7426 return ret;
7427 }
7428
7429 /**
7430 * @brief Configure slave 3 for perform a read.[get]
7431 *
7432 * @param ctx Read / write interface definitions
7433 * @param val Structure that contain:
7434 * - uint8_t slv_add; 8 bit i2c device address
7435 * - uint8_t slv_subadd; 8 bit register device address
7436 * - uint8_t slv_len; num of bit to read
7437 * @retval Interface status (MANDATORY: return 0 -> no Error).
7438 *
7439 */
lsm6dsl_sh_slv3_cfg_read(stmdev_ctx_t * ctx,lsm6dsl_sh_cfg_read_t * val)7440 int32_t lsm6dsl_sh_slv3_cfg_read(stmdev_ctx_t *ctx,
7441 lsm6dsl_sh_cfg_read_t *val)
7442 {
7443 lsm6dsl_slave3_config_t slave3_config;
7444 lsm6dsl_slv3_add_t slv3_add;
7445 int32_t ret;
7446
7447 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
7448
7449 if (ret == 0)
7450 {
7451 slv3_add.slave3_add = val->slv_add;
7452 slv3_add.r_3 = 1;
7453 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV3_ADD, (uint8_t *)&slv3_add, 1);
7454
7455 if (ret == 0)
7456 {
7457 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLV3_SUBADD,
7458 (uint8_t *) & (val->slv_subadd), 1);
7459
7460 if (ret == 0)
7461 {
7462 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE3_CONFIG,
7463 (uint8_t *)&slave3_config, 1);
7464
7465 if (ret == 0)
7466 {
7467 slave3_config.slave3_numop = val->slv_len;
7468 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE3_CONFIG,
7469 (uint8_t *)&slave3_config, 1);
7470
7471 if (ret == 0)
7472 {
7473 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
7474 }
7475 }
7476 }
7477 }
7478 }
7479
7480 return ret;
7481 }
7482
7483 /**
7484 * @brief Decimation of read operation on Slave 0 starting from the
7485 * sensor hub trigger.[set]
7486 *
7487 * @param ctx Read / write interface definitions
7488 * @param val Change the values of slave0_rate in reg SLAVE0_CONFIG
7489 * @retval Interface status (MANDATORY: return 0 -> no Error).
7490 *
7491 */
lsm6dsl_sh_slave_0_dec_set(stmdev_ctx_t * ctx,lsm6dsl_slave0_rate_t val)7492 int32_t lsm6dsl_sh_slave_0_dec_set(stmdev_ctx_t *ctx,
7493 lsm6dsl_slave0_rate_t val)
7494 {
7495 lsm6dsl_slave0_config_t slave0_config;
7496 int32_t ret;
7497
7498 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
7499
7500 if (ret == 0)
7501 {
7502 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE0_CONFIG,
7503 (uint8_t *)&slave0_config, 1);
7504
7505 if (ret == 0)
7506 {
7507 slave0_config.slave0_rate = (uint8_t) val;
7508 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE0_CONFIG,
7509 (uint8_t *)&slave0_config, 1);
7510
7511 if (ret == 0)
7512 {
7513 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
7514 }
7515 }
7516 }
7517
7518 return ret;
7519 }
7520
7521 /**
7522 * @brief Decimation of read operation on Slave 0 starting from the
7523 * sensor hub trigger.[get]
7524 *
7525 * @param ctx Read / write interface definitions
7526 * @param val Get the values of slave0_rate in reg SLAVE0_CONFIG
7527 * @retval Interface status (MANDATORY: return 0 -> no Error).
7528 *
7529 */
lsm6dsl_sh_slave_0_dec_get(stmdev_ctx_t * ctx,lsm6dsl_slave0_rate_t * val)7530 int32_t lsm6dsl_sh_slave_0_dec_get(stmdev_ctx_t *ctx,
7531 lsm6dsl_slave0_rate_t *val)
7532 {
7533 lsm6dsl_slave0_config_t slave0_config;
7534 int32_t ret;
7535
7536 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
7537
7538 if (ret == 0)
7539 {
7540 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE0_CONFIG,
7541 (uint8_t *)&slave0_config, 1);
7542
7543 if (ret == 0)
7544 {
7545 switch (slave0_config.slave0_rate)
7546 {
7547 case LSM6DSL_SL0_NO_DEC:
7548 *val = LSM6DSL_SL0_NO_DEC;
7549 break;
7550
7551 case LSM6DSL_SL0_DEC_2:
7552 *val = LSM6DSL_SL0_DEC_2;
7553 break;
7554
7555 case LSM6DSL_SL0_DEC_4:
7556 *val = LSM6DSL_SL0_DEC_4;
7557 break;
7558
7559 case LSM6DSL_SL0_DEC_8:
7560 *val = LSM6DSL_SL0_DEC_8;
7561 break;
7562
7563 default:
7564 *val = LSM6DSL_SL0_DEC_ND;
7565 break;
7566 }
7567
7568 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
7569 }
7570 }
7571
7572 return ret;
7573 }
7574
7575 /**
7576 * @brief Slave 0 write operation is performed only at the first sensor
7577 * hub cycle.
7578 * This is effective if the Aux_sens_on[1:0] field in
7579 * SLAVE0_CONFIG(04h) is set to a value other than 00.[set]
7580 *
7581 * @param ctx Read / write interface definitions
7582 * @param val Change the values of write_once in reg SLAVE1_CONFIG
7583 * @retval Interface status (MANDATORY: return 0 -> no Error).
7584 *
7585 */
lsm6dsl_sh_write_mode_set(stmdev_ctx_t * ctx,lsm6dsl_write_once_t val)7586 int32_t lsm6dsl_sh_write_mode_set(stmdev_ctx_t *ctx,
7587 lsm6dsl_write_once_t val)
7588 {
7589 lsm6dsl_slave1_config_t slave1_config;
7590 int32_t ret;
7591
7592 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
7593
7594 if (ret == 0)
7595 {
7596 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
7597 (uint8_t *)&slave1_config, 1);
7598 slave1_config.write_once = (uint8_t) val;
7599
7600 if (ret == 0)
7601 {
7602 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
7603 (uint8_t *)&slave1_config, 1);
7604
7605 if (ret == 0)
7606 {
7607 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
7608 }
7609 }
7610 }
7611
7612 return ret;
7613 }
7614
7615 /**
7616 * @brief Slave 0 write operation is performed only at the first sensor
7617 * hub cycle.
7618 * This is effective if the Aux_sens_on[1:0] field in
7619 * SLAVE0_CONFIG(04h) is set to a value other than 00.[get]
7620 *
7621 * @param ctx Read / write interface definitions
7622 * @param val Get the values of write_once in reg SLAVE1_CONFIG
7623 * @retval Interface status (MANDATORY: return 0 -> no Error).
7624 *
7625 */
lsm6dsl_sh_write_mode_get(stmdev_ctx_t * ctx,lsm6dsl_write_once_t * val)7626 int32_t lsm6dsl_sh_write_mode_get(stmdev_ctx_t *ctx,
7627 lsm6dsl_write_once_t *val)
7628 {
7629 lsm6dsl_slave1_config_t slave1_config;
7630 int32_t ret;
7631
7632 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
7633
7634 if (ret == 0)
7635 {
7636 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
7637 (uint8_t *)&slave1_config, 1);
7638
7639 if (ret == 0)
7640 {
7641 switch (slave1_config.write_once)
7642 {
7643 case LSM6DSL_EACH_SH_CYCLE:
7644 *val = LSM6DSL_EACH_SH_CYCLE;
7645 break;
7646
7647 case LSM6DSL_ONLY_FIRST_CYCLE:
7648 *val = LSM6DSL_ONLY_FIRST_CYCLE;
7649 break;
7650
7651 default:
7652 *val = LSM6DSL_SH_WR_MODE_ND;
7653 break;
7654 }
7655
7656 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
7657 }
7658 }
7659
7660 return ret;
7661 }
7662
7663 /**
7664 * @brief Decimation of read operation on Slave 1 starting from the
7665 * sensor hub trigger.[set]
7666 *
7667 * @param ctx Read / write interface definitions
7668 * @param val Change the values of slave1_rate in reg SLAVE1_CONFIG
7669 * @retval Interface status (MANDATORY: return 0 -> no Error).
7670 *
7671 */
lsm6dsl_sh_slave_1_dec_set(stmdev_ctx_t * ctx,lsm6dsl_slave1_rate_t val)7672 int32_t lsm6dsl_sh_slave_1_dec_set(stmdev_ctx_t *ctx,
7673 lsm6dsl_slave1_rate_t val)
7674 {
7675 lsm6dsl_slave1_config_t slave1_config;
7676 int32_t ret;
7677
7678 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
7679
7680 if (ret == 0)
7681 {
7682 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
7683 (uint8_t *)&slave1_config, 1);
7684
7685 if (ret == 0)
7686 {
7687 slave1_config.slave1_rate = (uint8_t) val;
7688 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
7689 (uint8_t *)&slave1_config, 1);
7690
7691 if (ret == 0)
7692 {
7693 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
7694 }
7695 }
7696 }
7697
7698 return ret;
7699 }
7700
7701 /**
7702 * @brief Decimation of read operation on Slave 1 starting from the
7703 * sensor hub trigger.[get]
7704 *
7705 * @param ctx Read / write interface definitions reg SLAVE1_CONFIG
7706 * @retval Interface status (MANDATORY: return 0 -> no Error).
7707 *
7708 */
lsm6dsl_sh_slave_1_dec_get(stmdev_ctx_t * ctx,lsm6dsl_slave1_rate_t * val)7709 int32_t lsm6dsl_sh_slave_1_dec_get(stmdev_ctx_t *ctx,
7710 lsm6dsl_slave1_rate_t *val)
7711 {
7712 lsm6dsl_slave1_config_t slave1_config;
7713 int32_t ret;
7714
7715 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
7716
7717 if (ret == 0)
7718 {
7719 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE1_CONFIG,
7720 (uint8_t *)&slave1_config, 1);
7721
7722 if (ret == 0)
7723 {
7724 switch (slave1_config.slave1_rate)
7725 {
7726 case LSM6DSL_SL1_NO_DEC:
7727 *val = LSM6DSL_SL1_NO_DEC;
7728 break;
7729
7730 case LSM6DSL_SL1_DEC_2:
7731 *val = LSM6DSL_SL1_DEC_2;
7732 break;
7733
7734 case LSM6DSL_SL1_DEC_4:
7735 *val = LSM6DSL_SL1_DEC_4;
7736 break;
7737
7738 case LSM6DSL_SL1_DEC_8:
7739 *val = LSM6DSL_SL1_DEC_8;
7740 break;
7741
7742 default:
7743 *val = LSM6DSL_SL1_DEC_ND;
7744 break;
7745 }
7746
7747 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
7748 }
7749 }
7750
7751 return ret;
7752 }
7753
7754 /**
7755 * @brief Decimation of read operation on Slave 2 starting from the
7756 * sensor hub trigger.[set]
7757 *
7758 * @param ctx Read / write interface definitions
7759 * @param val Change the values of slave2_rate in reg SLAVE2_CONFIG
7760 * @retval Interface status (MANDATORY: return 0 -> no Error).
7761 *
7762 */
lsm6dsl_sh_slave_2_dec_set(stmdev_ctx_t * ctx,lsm6dsl_slave2_rate_t val)7763 int32_t lsm6dsl_sh_slave_2_dec_set(stmdev_ctx_t *ctx,
7764 lsm6dsl_slave2_rate_t val)
7765 {
7766 lsm6dsl_slave2_config_t slave2_config;
7767 int32_t ret;
7768
7769 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
7770
7771 if (ret == 0)
7772 {
7773 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE2_CONFIG,
7774 (uint8_t *)&slave2_config, 1);
7775
7776 if (ret == 0)
7777 {
7778 slave2_config.slave2_rate = (uint8_t) val;
7779 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE2_CONFIG,
7780 (uint8_t *)&slave2_config, 1);
7781
7782 if (ret == 0)
7783 {
7784 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
7785 }
7786 }
7787 }
7788
7789 return ret;
7790 }
7791
7792 /**
7793 * @brief Decimation of read operation on Slave 2 starting from the
7794 * sensor hub trigger.[get]
7795 *
7796 * @param ctx Read / write interface definitions
7797 * @param val Get the values of slave2_rate in reg SLAVE2_CONFIG
7798 * @retval Interface status (MANDATORY: return 0 -> no Error).
7799 *
7800 */
lsm6dsl_sh_slave_2_dec_get(stmdev_ctx_t * ctx,lsm6dsl_slave2_rate_t * val)7801 int32_t lsm6dsl_sh_slave_2_dec_get(stmdev_ctx_t *ctx,
7802 lsm6dsl_slave2_rate_t *val)
7803 {
7804 lsm6dsl_slave2_config_t slave2_config;
7805 int32_t ret;
7806
7807 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
7808
7809 if (ret == 0)
7810 {
7811 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE2_CONFIG,
7812 (uint8_t *)&slave2_config, 1);
7813
7814 if (ret == 0)
7815 {
7816 switch (slave2_config.slave2_rate)
7817 {
7818 case LSM6DSL_SL2_NO_DEC:
7819 *val = LSM6DSL_SL2_NO_DEC;
7820 break;
7821
7822 case LSM6DSL_SL2_DEC_2:
7823 *val = LSM6DSL_SL2_DEC_2;
7824 break;
7825
7826 case LSM6DSL_SL2_DEC_4:
7827 *val = LSM6DSL_SL2_DEC_4;
7828 break;
7829
7830 case LSM6DSL_SL2_DEC_8:
7831 *val = LSM6DSL_SL2_DEC_8;
7832 break;
7833
7834 default:
7835 *val = LSM6DSL_SL2_DEC_ND;
7836 break;
7837 }
7838
7839 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
7840 }
7841 }
7842
7843 return ret;
7844 }
7845
7846 /**
7847 * @brief Decimation of read operation on Slave 3 starting from the
7848 * sensor hub trigger.[set]
7849 *
7850 * @param ctx Read / write interface definitions
7851 * @param val Change the values of slave3_rate in reg SLAVE3_CONFIG
7852 * @retval Interface status (MANDATORY: return 0 -> no Error).
7853 *
7854 */
lsm6dsl_sh_slave_3_dec_set(stmdev_ctx_t * ctx,lsm6dsl_slave3_rate_t val)7855 int32_t lsm6dsl_sh_slave_3_dec_set(stmdev_ctx_t *ctx,
7856 lsm6dsl_slave3_rate_t val)
7857 {
7858 lsm6dsl_slave3_config_t slave3_config;
7859 int32_t ret;
7860
7861 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
7862
7863 if (ret == 0)
7864 {
7865 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE3_CONFIG,
7866 (uint8_t *)&slave3_config, 1);
7867 slave3_config.slave3_rate = (uint8_t)val;
7868
7869 if (ret == 0)
7870 {
7871 ret = lsm6dsl_write_reg(ctx, LSM6DSL_SLAVE3_CONFIG,
7872 (uint8_t *)&slave3_config, 1);
7873
7874 if (ret == 0)
7875 {
7876 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
7877 }
7878 }
7879 }
7880
7881 return ret;
7882 }
7883
7884 /**
7885 * @brief Decimation of read operation on Slave 3 starting from the
7886 * sensor hub trigger.[get]
7887 *
7888 * @param ctx Read / write interface definitions
7889 * @param val Get the values of slave3_rate in reg SLAVE3_CONFIG.
7890 * @retval Interface status (MANDATORY: return 0 -> no Error).
7891 *
7892 */
lsm6dsl_sh_slave_3_dec_get(stmdev_ctx_t * ctx,lsm6dsl_slave3_rate_t * val)7893 int32_t lsm6dsl_sh_slave_3_dec_get(stmdev_ctx_t *ctx,
7894 lsm6dsl_slave3_rate_t *val)
7895 {
7896 lsm6dsl_slave3_config_t slave3_config;
7897 int32_t ret;
7898
7899 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_BANK_A);
7900
7901 if (ret == 0)
7902 {
7903 ret = lsm6dsl_read_reg(ctx, LSM6DSL_SLAVE3_CONFIG,
7904 (uint8_t *)&slave3_config, 1);
7905
7906 if (ret == 0)
7907 {
7908 switch (slave3_config.slave3_rate)
7909 {
7910 case LSM6DSL_SL3_NO_DEC:
7911 *val = LSM6DSL_SL3_NO_DEC;
7912 break;
7913
7914 case LSM6DSL_SL3_DEC_2:
7915 *val = LSM6DSL_SL3_DEC_2;
7916 break;
7917
7918 case LSM6DSL_SL3_DEC_4:
7919 *val = LSM6DSL_SL3_DEC_4;
7920 break;
7921
7922 case LSM6DSL_SL3_DEC_8:
7923 *val = LSM6DSL_SL3_DEC_8;
7924 break;
7925
7926 default:
7927 *val = LSM6DSL_SL3_DEC_ND;
7928 break;
7929 }
7930
7931 ret = lsm6dsl_mem_bank_set(ctx, LSM6DSL_USER_BANK);
7932 }
7933 }
7934
7935 return ret;
7936 }
7937
7938 /**
7939 * @}
7940 *
7941 */
7942
7943 /**
7944 * @}
7945 *
7946 */
7947
7948 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
7949
