1 /**
2 ******************************************************************************
3 * @file lsm6ds3tr_c_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM6DS3TR_C driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm6ds3tr-c_reg.h"
21
22 /**
23 * @defgroup LSM6DS3TR_C
24 * @brief This file provides a set of functions needed to drive the
25 * lsm6ds3tr_c enanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LSM6DS3TR_C_interfaces_functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm6ds3tr_c_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm6ds3tr_c_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx read / write interface definitions(ptr)
69 * @param reg register to write
70 * @param data pointer to data to write in register reg(ptr)
71 * @param len number of consecutive register to write
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lsm6ds3tr_c_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lsm6ds3tr_c_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup LSM6DS3TR_C_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
102
lsm6ds3tr_c_from_fs2g_to_mg(int16_t lsb)103 float_t lsm6ds3tr_c_from_fs2g_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb * 0.061f);
106 }
107
lsm6ds3tr_c_from_fs4g_to_mg(int16_t lsb)108 float_t lsm6ds3tr_c_from_fs4g_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb * 0.122f);
111 }
112
lsm6ds3tr_c_from_fs8g_to_mg(int16_t lsb)113 float_t lsm6ds3tr_c_from_fs8g_to_mg(int16_t lsb)
114 {
115 return ((float_t)lsb * 0.244f);
116 }
117
lsm6ds3tr_c_from_fs16g_to_mg(int16_t lsb)118 float_t lsm6ds3tr_c_from_fs16g_to_mg(int16_t lsb)
119 {
120 return ((float_t)lsb * 0.488f);
121 }
122
lsm6ds3tr_c_from_fs125dps_to_mdps(int16_t lsb)123 float_t lsm6ds3tr_c_from_fs125dps_to_mdps(int16_t lsb)
124 {
125 return ((float_t)lsb * 4.375f);
126 }
127
lsm6ds3tr_c_from_fs250dps_to_mdps(int16_t lsb)128 float_t lsm6ds3tr_c_from_fs250dps_to_mdps(int16_t lsb)
129 {
130 return ((float_t)lsb * 8.750f);
131 }
132
lsm6ds3tr_c_from_fs500dps_to_mdps(int16_t lsb)133 float_t lsm6ds3tr_c_from_fs500dps_to_mdps(int16_t lsb)
134 {
135 return ((float_t)lsb * 17.50f);
136 }
137
lsm6ds3tr_c_from_fs1000dps_to_mdps(int16_t lsb)138 float_t lsm6ds3tr_c_from_fs1000dps_to_mdps(int16_t lsb)
139 {
140 return ((float_t)lsb * 35.0f);
141 }
142
lsm6ds3tr_c_from_fs2000dps_to_mdps(int16_t lsb)143 float_t lsm6ds3tr_c_from_fs2000dps_to_mdps(int16_t lsb)
144 {
145 return ((float_t)lsb * 70.0f);
146 }
147
lsm6ds3tr_c_from_lsb_to_celsius(int16_t lsb)148 float_t lsm6ds3tr_c_from_lsb_to_celsius(int16_t lsb)
149 {
150 return (((float_t)lsb / 256.0f) + 25.0f);
151 }
152
153 /**
154 * @}
155 *
156 */
157
158
159 /**
160 * @defgroup LSM6DS3TR_C_data_generation
161 * @brief This section groups all the functions concerning data
162 * generation
163 * @{
164 *
165 */
166
167 /**
168 * @brief Accelerometer full-scale selection.[set]
169 *
170 * @param ctx Read / write interface definitions
171 * @param val Change the values of fs_xl in reg CTRL1_XL
172 * @retval Interface status (MANDATORY: return 0 -> no Error).
173 *
174 */
lsm6ds3tr_c_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_fs_xl_t val)175 int32_t lsm6ds3tr_c_xl_full_scale_set(const stmdev_ctx_t *ctx,
176 lsm6ds3tr_c_fs_xl_t val)
177 {
178 lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl;
179 int32_t ret;
180
181 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
182 (uint8_t *)&ctrl1_xl, 1);
183
184 if (ret == 0)
185 {
186 ctrl1_xl.fs_xl = (uint8_t) val;
187 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
188 (uint8_t *)&ctrl1_xl, 1);
189 }
190
191 return ret;
192 }
193
194 /**
195 * @brief Accelerometer full-scale selection.[get]
196 *
197 * @param ctx Read / write interface definitions
198 * @param val Get the values of fs_xl in reg CTRL1_XL
199 * @retval Interface status (MANDATORY: return 0 -> no Error).
200 *
201 */
lsm6ds3tr_c_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_fs_xl_t * val)202 int32_t lsm6ds3tr_c_xl_full_scale_get(const stmdev_ctx_t *ctx,
203 lsm6ds3tr_c_fs_xl_t *val)
204 {
205 lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl;
206 int32_t ret;
207
208 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
209 (uint8_t *)&ctrl1_xl, 1);
210
211 switch (ctrl1_xl.fs_xl)
212 {
213 case LSM6DS3TR_C_2g:
214 *val = LSM6DS3TR_C_2g;
215 break;
216
217 case LSM6DS3TR_C_16g:
218 *val = LSM6DS3TR_C_16g;
219 break;
220
221 case LSM6DS3TR_C_4g:
222 *val = LSM6DS3TR_C_4g;
223 break;
224
225 case LSM6DS3TR_C_8g:
226 *val = LSM6DS3TR_C_8g;
227 break;
228
229 default:
230 *val = LSM6DS3TR_C_XL_FS_ND;
231 break;
232 }
233
234 return ret;
235 }
236
237 /**
238 * @brief Accelerometer data rate selection.[set]
239 *
240 * @param ctx Read / write interface definitions
241 * @param val Change the values of odr_xl in reg CTRL1_XL
242 * @retval Interface status (MANDATORY: return 0 -> no Error).
243 *
244 */
lsm6ds3tr_c_xl_data_rate_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_odr_xl_t val)245 int32_t lsm6ds3tr_c_xl_data_rate_set(const stmdev_ctx_t *ctx,
246 lsm6ds3tr_c_odr_xl_t val)
247 {
248 lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl;
249 int32_t ret;
250
251 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
252 (uint8_t *)&ctrl1_xl, 1);
253
254 if (ret == 0)
255 {
256 ctrl1_xl.odr_xl = (uint8_t) val;
257 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
258 (uint8_t *)&ctrl1_xl, 1);
259 }
260
261 return ret;
262 }
263
264 /**
265 * @brief Accelerometer data rate selection.[get]
266 *
267 * @param ctx Read / write interface definitions
268 * @param val Get the values of odr_xl in reg CTRL1_XL
269 * @retval Interface status (MANDATORY: return 0 -> no Error).
270 *
271 */
lsm6ds3tr_c_xl_data_rate_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_odr_xl_t * val)272 int32_t lsm6ds3tr_c_xl_data_rate_get(const stmdev_ctx_t *ctx,
273 lsm6ds3tr_c_odr_xl_t *val)
274 {
275 lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl;
276 int32_t ret;
277
278 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
279 (uint8_t *)&ctrl1_xl, 1);
280
281 switch (ctrl1_xl.odr_xl)
282 {
283 case LSM6DS3TR_C_XL_ODR_OFF:
284 *val = LSM6DS3TR_C_XL_ODR_OFF;
285 break;
286
287 case LSM6DS3TR_C_XL_ODR_12Hz5:
288 *val = LSM6DS3TR_C_XL_ODR_12Hz5;
289 break;
290
291 case LSM6DS3TR_C_XL_ODR_26Hz:
292 *val = LSM6DS3TR_C_XL_ODR_26Hz;
293 break;
294
295 case LSM6DS3TR_C_XL_ODR_52Hz:
296 *val = LSM6DS3TR_C_XL_ODR_52Hz;
297 break;
298
299 case LSM6DS3TR_C_XL_ODR_104Hz:
300 *val = LSM6DS3TR_C_XL_ODR_104Hz;
301 break;
302
303 case LSM6DS3TR_C_XL_ODR_208Hz:
304 *val = LSM6DS3TR_C_XL_ODR_208Hz;
305 break;
306
307 case LSM6DS3TR_C_XL_ODR_416Hz:
308 *val = LSM6DS3TR_C_XL_ODR_416Hz;
309 break;
310
311 case LSM6DS3TR_C_XL_ODR_833Hz:
312 *val = LSM6DS3TR_C_XL_ODR_833Hz;
313 break;
314
315 case LSM6DS3TR_C_XL_ODR_1k66Hz:
316 *val = LSM6DS3TR_C_XL_ODR_1k66Hz;
317 break;
318
319 case LSM6DS3TR_C_XL_ODR_3k33Hz:
320 *val = LSM6DS3TR_C_XL_ODR_3k33Hz;
321 break;
322
323 case LSM6DS3TR_C_XL_ODR_6k66Hz:
324 *val = LSM6DS3TR_C_XL_ODR_6k66Hz;
325 break;
326
327 case LSM6DS3TR_C_XL_ODR_1Hz6:
328 *val = LSM6DS3TR_C_XL_ODR_1Hz6;
329 break;
330
331 default:
332 *val = LSM6DS3TR_C_XL_ODR_ND;
333 break;
334 }
335
336 return ret;
337 }
338
339 /**
340 * @brief Gyroscope chain full-scale selection.[set]
341 *
342 * @param ctx Read / write interface definitions
343 * @param val Change the values of fs_g in reg CTRL2_G
344 * @retval Interface status (MANDATORY: return 0 -> no Error).
345 *
346 */
lsm6ds3tr_c_gy_full_scale_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_fs_g_t val)347 int32_t lsm6ds3tr_c_gy_full_scale_set(const stmdev_ctx_t *ctx,
348 lsm6ds3tr_c_fs_g_t val)
349 {
350 lsm6ds3tr_c_ctrl2_g_t ctrl2_g;
351 int32_t ret;
352
353 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL2_G,
354 (uint8_t *)&ctrl2_g, 1);
355
356 if (ret == 0)
357 {
358 ctrl2_g.fs_g = (uint8_t) val;
359 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL2_G,
360 (uint8_t *)&ctrl2_g, 1);
361 }
362
363 return ret;
364 }
365
366 /**
367 * @brief Gyroscope chain full-scale selection.[get]
368 *
369 * @param ctx Read / write interface definitions
370 * @param val Get the values of fs_g in reg CTRL2_G
371 * @retval Interface status (MANDATORY: return 0 -> no Error).
372 *
373 */
lsm6ds3tr_c_gy_full_scale_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_fs_g_t * val)374 int32_t lsm6ds3tr_c_gy_full_scale_get(const stmdev_ctx_t *ctx,
375 lsm6ds3tr_c_fs_g_t *val)
376 {
377 lsm6ds3tr_c_ctrl2_g_t ctrl2_g;
378 int32_t ret;
379
380 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL2_G,
381 (uint8_t *)&ctrl2_g, 1);
382
383 switch (ctrl2_g.fs_g)
384 {
385 case LSM6DS3TR_C_250dps:
386 *val = LSM6DS3TR_C_250dps;
387 break;
388
389 case LSM6DS3TR_C_125dps:
390 *val = LSM6DS3TR_C_125dps;
391 break;
392
393 case LSM6DS3TR_C_500dps:
394 *val = LSM6DS3TR_C_500dps;
395 break;
396
397 case LSM6DS3TR_C_1000dps:
398 *val = LSM6DS3TR_C_1000dps;
399 break;
400
401 case LSM6DS3TR_C_2000dps:
402 *val = LSM6DS3TR_C_2000dps;
403 break;
404
405 default:
406 *val = LSM6DS3TR_C_GY_FS_ND;
407 break;
408 }
409
410 return ret;
411 }
412
413 /**
414 * @brief Gyroscope data rate selection.[set]
415 *
416 * @param ctx Read / write interface definitions
417 * @param val Change the values of odr_g in reg CTRL2_G
418 * @retval Interface status (MANDATORY: return 0 -> no Error).
419 *
420 */
lsm6ds3tr_c_gy_data_rate_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_odr_g_t val)421 int32_t lsm6ds3tr_c_gy_data_rate_set(const stmdev_ctx_t *ctx,
422 lsm6ds3tr_c_odr_g_t val)
423 {
424 lsm6ds3tr_c_ctrl2_g_t ctrl2_g;
425 int32_t ret;
426
427 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL2_G,
428 (uint8_t *)&ctrl2_g, 1);
429
430 if (ret == 0)
431 {
432 ctrl2_g.odr_g = (uint8_t) val;
433 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL2_G,
434 (uint8_t *)&ctrl2_g, 1);
435 }
436
437 return ret;
438 }
439
440 /**
441 * @brief Gyroscope data rate selection.[get]
442 *
443 * @param ctx Read / write interface definitions
444 * @param val Get the values of odr_g in reg CTRL2_G
445 * @retval Interface status (MANDATORY: return 0 -> no Error).
446 *
447 */
lsm6ds3tr_c_gy_data_rate_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_odr_g_t * val)448 int32_t lsm6ds3tr_c_gy_data_rate_get(const stmdev_ctx_t *ctx,
449 lsm6ds3tr_c_odr_g_t *val)
450 {
451 lsm6ds3tr_c_ctrl2_g_t ctrl2_g;
452 int32_t ret;
453
454 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL2_G,
455 (uint8_t *)&ctrl2_g, 1);
456
457 switch (ctrl2_g.odr_g)
458 {
459 case LSM6DS3TR_C_GY_ODR_OFF:
460 *val = LSM6DS3TR_C_GY_ODR_OFF;
461 break;
462
463 case LSM6DS3TR_C_GY_ODR_12Hz5:
464 *val = LSM6DS3TR_C_GY_ODR_12Hz5;
465 break;
466
467 case LSM6DS3TR_C_GY_ODR_26Hz:
468 *val = LSM6DS3TR_C_GY_ODR_26Hz;
469 break;
470
471 case LSM6DS3TR_C_GY_ODR_52Hz:
472 *val = LSM6DS3TR_C_GY_ODR_52Hz;
473 break;
474
475 case LSM6DS3TR_C_GY_ODR_104Hz:
476 *val = LSM6DS3TR_C_GY_ODR_104Hz;
477 break;
478
479 case LSM6DS3TR_C_GY_ODR_208Hz:
480 *val = LSM6DS3TR_C_GY_ODR_208Hz;
481 break;
482
483 case LSM6DS3TR_C_GY_ODR_416Hz:
484 *val = LSM6DS3TR_C_GY_ODR_416Hz;
485 break;
486
487 case LSM6DS3TR_C_GY_ODR_833Hz:
488 *val = LSM6DS3TR_C_GY_ODR_833Hz;
489 break;
490
491 case LSM6DS3TR_C_GY_ODR_1k66Hz:
492 *val = LSM6DS3TR_C_GY_ODR_1k66Hz;
493 break;
494
495 case LSM6DS3TR_C_GY_ODR_3k33Hz:
496 *val = LSM6DS3TR_C_GY_ODR_3k33Hz;
497 break;
498
499 case LSM6DS3TR_C_GY_ODR_6k66Hz:
500 *val = LSM6DS3TR_C_GY_ODR_6k66Hz;
501 break;
502
503 default:
504 *val = LSM6DS3TR_C_GY_ODR_ND;
505 break;
506 }
507
508 return ret;
509 }
510
511 /**
512 * @brief Block data update.[set]
513 *
514 * @param ctx Read / write interface definitions
515 * @param val Change the values of bdu in reg CTRL3_C
516 * @retval Interface status (MANDATORY: return 0 -> no Error).
517 *
518 */
lsm6ds3tr_c_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)519 int32_t lsm6ds3tr_c_block_data_update_set(const stmdev_ctx_t *ctx,
520 uint8_t val)
521 {
522 lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
523 int32_t ret;
524
525 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
526 (uint8_t *)&ctrl3_c, 1);
527
528 if (ret == 0)
529 {
530 ctrl3_c.bdu = val;
531 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C,
532 (uint8_t *)&ctrl3_c, 1);
533 }
534
535 return ret;
536 }
537
538 /**
539 * @brief Block data update.[get]
540 *
541 * @param ctx Read / write interface definitions
542 * @param val Change the values of bdu in reg CTRL3_C
543 * @retval Interface status (MANDATORY: return 0 -> no Error).
544 *
545 */
lsm6ds3tr_c_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)546 int32_t lsm6ds3tr_c_block_data_update_get(const stmdev_ctx_t *ctx,
547 uint8_t *val)
548 {
549 lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
550 int32_t ret;
551
552 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
553 (uint8_t *)&ctrl3_c, 1);
554 *val = ctrl3_c.bdu;
555
556 return ret;
557 }
558
559 /**
560 * @brief Weight of XL user offset bits of registers
561 * X_OFS_USR(73h), Y_OFS_USR(74h), Z_OFS_USR(75h).[set]
562 *
563 * @param ctx Read / write interface definitions
564 * @param val Change the values of usr_off_w in reg CTRL6_C
565 * @retval Interface status (MANDATORY: return 0 -> no Error).
566 *
567 */
lsm6ds3tr_c_xl_offset_weight_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_usr_off_w_t val)568 int32_t lsm6ds3tr_c_xl_offset_weight_set(const stmdev_ctx_t *ctx,
569 lsm6ds3tr_c_usr_off_w_t val)
570 {
571 lsm6ds3tr_c_ctrl6_c_t ctrl6_c;
572 int32_t ret;
573
574 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C,
575 (uint8_t *)&ctrl6_c, 1);
576
577 if (ret == 0)
578 {
579 ctrl6_c.usr_off_w = (uint8_t) val;
580 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL6_C,
581 (uint8_t *)&ctrl6_c, 1);
582 }
583
584 return ret;
585 }
586
587 /**
588 * @brief Weight of XL user offset bits of registers
589 * X_OFS_USR(73h), Y_OFS_USR(74h), Z_OFS_USR(75h).[get]
590 *
591 * @param ctx Read / write interface definitions
592 * @param val Get the values of usr_off_w in reg CTRL6_C
593 * @retval Interface status (MANDATORY: return 0 -> no Error).
594 *
595 */
lsm6ds3tr_c_xl_offset_weight_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_usr_off_w_t * val)596 int32_t lsm6ds3tr_c_xl_offset_weight_get(const stmdev_ctx_t *ctx,
597 lsm6ds3tr_c_usr_off_w_t *val)
598 {
599 lsm6ds3tr_c_ctrl6_c_t ctrl6_c;
600 int32_t ret;
601
602 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C,
603 (uint8_t *)&ctrl6_c, 1);
604
605 switch (ctrl6_c.usr_off_w)
606 {
607 case LSM6DS3TR_C_LSb_1mg:
608 *val = LSM6DS3TR_C_LSb_1mg;
609 break;
610
611 case LSM6DS3TR_C_LSb_16mg:
612 *val = LSM6DS3TR_C_LSb_16mg;
613 break;
614
615 default:
616 *val = LSM6DS3TR_C_WEIGHT_ND;
617 break;
618 }
619
620 return ret;
621 }
622
623 /**
624 * @brief High-performance operating mode for accelerometer[set]
625 *
626 * @param ctx Read / write interface definitions
627 * @param val Change the values of xl_hm_mode in reg CTRL6_C
628 * @retval Interface status (MANDATORY: return 0 -> no Error).
629 *
630 */
lsm6ds3tr_c_xl_power_mode_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_xl_hm_mode_t val)631 int32_t lsm6ds3tr_c_xl_power_mode_set(const stmdev_ctx_t *ctx,
632 lsm6ds3tr_c_xl_hm_mode_t val)
633 {
634 lsm6ds3tr_c_ctrl6_c_t ctrl6_c;
635 int32_t ret;
636
637 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C,
638 (uint8_t *)&ctrl6_c, 1);
639
640 if (ret == 0)
641 {
642 ctrl6_c.xl_hm_mode = (uint8_t) val;
643 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL6_C,
644 (uint8_t *)&ctrl6_c, 1);
645 }
646
647 return ret;
648 }
649
650 /**
651 * @brief High-performance operating mode for accelerometer.[get]
652 *
653 * @param ctx Read / write interface definitions
654 * @param val Get the values of xl_hm_mode in reg CTRL6_C
655 * @retval Interface status (MANDATORY: return 0 -> no Error).
656 *
657 */
lsm6ds3tr_c_xl_power_mode_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_xl_hm_mode_t * val)658 int32_t lsm6ds3tr_c_xl_power_mode_get(const stmdev_ctx_t *ctx,
659 lsm6ds3tr_c_xl_hm_mode_t *val)
660 {
661 lsm6ds3tr_c_ctrl6_c_t ctrl6_c;
662 int32_t ret;
663
664 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C,
665 (uint8_t *)&ctrl6_c, 1);
666
667 switch (ctrl6_c.xl_hm_mode)
668 {
669 case LSM6DS3TR_C_XL_HIGH_PERFORMANCE:
670 *val = LSM6DS3TR_C_XL_HIGH_PERFORMANCE;
671 break;
672
673 case LSM6DS3TR_C_XL_NORMAL:
674 *val = LSM6DS3TR_C_XL_NORMAL;
675 break;
676
677 default:
678 *val = LSM6DS3TR_C_XL_PW_MODE_ND;
679 break;
680 }
681
682 return ret;
683 }
684
685 /**
686 * @brief Source register rounding function on WAKE_UP_SRC (1Bh),
687 * TAP_SRC (1Ch), D6D_SRC (1Dh), STATUS_REG (1Eh) and
688 * FUNC_SRC1 (53h) registers in the primary interface.[set]
689 *
690 * @param ctx Read / write interface definitions
691 * @param val Change the values of rounding_status in reg CTRL7_G
692 * @retval Interface status (MANDATORY: return 0 -> no Error).
693 *
694 */
lsm6ds3tr_c_rounding_on_status_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_rounding_status_t val)695 int32_t lsm6ds3tr_c_rounding_on_status_set(const stmdev_ctx_t *ctx,
696 lsm6ds3tr_c_rounding_status_t val)
697 {
698 lsm6ds3tr_c_ctrl7_g_t ctrl7_g;
699 int32_t ret;
700
701 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G,
702 (uint8_t *)&ctrl7_g, 1);
703
704 if (ret == 0)
705 {
706 ctrl7_g.rounding_status = (uint8_t) val;
707 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL7_G,
708 (uint8_t *)&ctrl7_g, 1);
709 }
710
711 return ret;
712 }
713
714 /**
715 * @brief Source register rounding function on WAKE_UP_SRC (1Bh),
716 * TAP_SRC (1Ch), D6D_SRC (1Dh), STATUS_REG (1Eh) and
717 * FUNC_SRC1 (53h) registers in the primary interface.[get]
718 *
719 * @param ctx Read / write interface definitions
720 * @param val Get the values of rounding_status in reg CTRL7_G
721 * @retval Interface status (MANDATORY: return 0 -> no Error).
722 *
723 */
lsm6ds3tr_c_rounding_on_status_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_rounding_status_t * val)724 int32_t lsm6ds3tr_c_rounding_on_status_get(const stmdev_ctx_t *ctx,
725 lsm6ds3tr_c_rounding_status_t *val)
726 {
727 lsm6ds3tr_c_ctrl7_g_t ctrl7_g;
728 int32_t ret;
729
730 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G,
731 (uint8_t *)&ctrl7_g, 1);
732
733 switch (ctrl7_g.rounding_status)
734 {
735 case LSM6DS3TR_C_STAT_RND_DISABLE:
736 *val = LSM6DS3TR_C_STAT_RND_DISABLE;
737 break;
738
739 case LSM6DS3TR_C_STAT_RND_ENABLE:
740 *val = LSM6DS3TR_C_STAT_RND_ENABLE;
741 break;
742
743 default:
744 *val = LSM6DS3TR_C_STAT_RND_ND;
745 break;
746 }
747
748 return ret;
749 }
750
751 /**
752 * @brief High-performance operating mode disable for gyroscope.[set]
753 *
754 * @param ctx Read / write interface definitions
755 * @param val Change the values of g_hm_mode in reg CTRL7_G
756 * @retval Interface status (MANDATORY: return 0 -> no Error).
757 *
758 */
lsm6ds3tr_c_gy_power_mode_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_g_hm_mode_t val)759 int32_t lsm6ds3tr_c_gy_power_mode_set(const stmdev_ctx_t *ctx,
760 lsm6ds3tr_c_g_hm_mode_t val)
761 {
762 lsm6ds3tr_c_ctrl7_g_t ctrl7_g;
763 int32_t ret;
764
765 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G,
766 (uint8_t *)&ctrl7_g, 1);
767
768 if (ret == 0)
769 {
770 ctrl7_g.g_hm_mode = (uint8_t) val;
771 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL7_G,
772 (uint8_t *)&ctrl7_g, 1);
773 }
774
775 return ret;
776 }
777
778 /**
779 * @brief High-performance operating mode disable for gyroscope.[get]
780 *
781 * @param ctx Read / write interface definitions
782 * @param val Get the values of g_hm_mode in reg CTRL7_G
783 * @retval Interface status (MANDATORY: return 0 -> no Error).
784 *
785 */
lsm6ds3tr_c_gy_power_mode_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_g_hm_mode_t * val)786 int32_t lsm6ds3tr_c_gy_power_mode_get(const stmdev_ctx_t *ctx,
787 lsm6ds3tr_c_g_hm_mode_t *val)
788 {
789 lsm6ds3tr_c_ctrl7_g_t ctrl7_g;
790 int32_t ret;
791
792 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G,
793 (uint8_t *)&ctrl7_g, 1);
794
795 switch (ctrl7_g.g_hm_mode)
796 {
797 case LSM6DS3TR_C_GY_HIGH_PERFORMANCE:
798 *val = LSM6DS3TR_C_GY_HIGH_PERFORMANCE;
799 break;
800
801 case LSM6DS3TR_C_GY_NORMAL:
802 *val = LSM6DS3TR_C_GY_NORMAL;
803 break;
804
805 default:
806 *val = LSM6DS3TR_C_GY_PW_MODE_ND;
807 break;
808 }
809
810 return ret;
811 }
812
813 /**
814 * @brief Read all the interrupt/status flag of the device.[get]
815 *
816 * @param ctx Read / write interface definitions
817 * @param val WAKE_UP_SRC, TAP_SRC, D6D_SRC, STATUS_REG,
818 * FUNC_SRC1, FUNC_SRC2, WRIST_TILT_IA, A_WRIST_TILT_Mask
819 * @retval Interface status (MANDATORY: return 0 -> no Error).
820 *
821 */
lsm6ds3tr_c_all_sources_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_all_sources_t * val)822 int32_t lsm6ds3tr_c_all_sources_get(const stmdev_ctx_t *ctx,
823 lsm6ds3tr_c_all_sources_t *val)
824 {
825 int32_t ret;
826
827 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_SRC,
828 (uint8_t *) & (val->wake_up_src), 1);
829
830 if (ret == 0)
831 {
832 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_SRC,
833 (uint8_t *) & (val->tap_src), 1);
834 }
835
836 if (ret == 0)
837 {
838 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_D6D_SRC,
839 (uint8_t *) & (val->d6d_src), 1);
840 }
841
842 if (ret == 0)
843 {
844 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG,
845 (uint8_t *) & (val->status_reg), 1);
846 }
847
848 if (ret == 0)
849 {
850 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FUNC_SRC1,
851 (uint8_t *) & (val->func_src1), 1);
852 }
853
854 if (ret == 0)
855 {
856 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FUNC_SRC2,
857 (uint8_t *) & (val->func_src2), 1);
858 }
859
860 if (ret == 0)
861 {
862 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WRIST_TILT_IA,
863 (uint8_t *) & (val->wrist_tilt_ia), 1);
864 }
865
866 if (ret == 0)
867 {
868 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B);
869 }
870
871 if (ret == 0)
872 {
873 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_MASK,
874 (uint8_t *) & (val->a_wrist_tilt_mask), 1);
875 }
876
877 if (ret == 0)
878 {
879 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
880 }
881
882 return ret;
883 }
884 /**
885 * @brief The STATUS_REG register is read by the primary interface[get]
886 *
887 * @param ctx Read / write interface definitions
888 * @param val Registers STATUS_REG
889 * @retval Interface status (MANDATORY: return 0 -> no Error).
890 *
891 */
lsm6ds3tr_c_status_reg_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_status_reg_t * val)892 int32_t lsm6ds3tr_c_status_reg_get(const stmdev_ctx_t *ctx,
893 lsm6ds3tr_c_status_reg_t *val)
894 {
895 int32_t ret;
896
897 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG,
898 (uint8_t *) val, 1);
899
900 return ret;
901 }
902
903 /**
904 * @brief Accelerometer new data available.[get]
905 *
906 * @param ctx Read / write interface definitions
907 * @param val Change the values of xlda in reg STATUS_REG
908 * @retval Interface status (MANDATORY: return 0 -> no Error).
909 *
910 */
lsm6ds3tr_c_xl_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)911 int32_t lsm6ds3tr_c_xl_flag_data_ready_get(const stmdev_ctx_t *ctx,
912 uint8_t *val)
913 {
914 lsm6ds3tr_c_status_reg_t status_reg;
915 int32_t ret;
916
917 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG,
918 (uint8_t *)&status_reg, 1);
919 *val = status_reg.xlda;
920
921 return ret;
922 }
923
924 /**
925 * @brief Gyroscope new data available.[get]
926 *
927 * @param ctx Read / write interface definitions
928 * @param val Change the values of gda in reg STATUS_REG
929 * @retval Interface status (MANDATORY: return 0 -> no Error).
930 *
931 */
lsm6ds3tr_c_gy_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)932 int32_t lsm6ds3tr_c_gy_flag_data_ready_get(const stmdev_ctx_t *ctx,
933 uint8_t *val)
934 {
935 lsm6ds3tr_c_status_reg_t status_reg;
936 int32_t ret;
937
938 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG,
939 (uint8_t *)&status_reg, 1);
940 *val = status_reg.gda;
941
942 return ret;
943 }
944
945 /**
946 * @brief Temperature new data available.[get]
947 *
948 * @param ctx Read / write interface definitions
949 * @param val Change the values of tda in reg STATUS_REG
950 * @retval Interface status (MANDATORY: return 0 -> no Error).
951 *
952 */
lsm6ds3tr_c_temp_flag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)953 int32_t lsm6ds3tr_c_temp_flag_data_ready_get(const stmdev_ctx_t *ctx,
954 uint8_t *val)
955 {
956 lsm6ds3tr_c_status_reg_t status_reg;
957 int32_t ret;
958
959 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STATUS_REG,
960 (uint8_t *)&status_reg, 1);
961 *val = status_reg.tda;
962
963 return ret;
964 }
965
966 /**
967 * @brief Accelerometer axis user offset correction expressed in two’s
968 * complement, weight depends on USR_OFF_W in CTRL6_C.
969 * The value must be in the range [-127 127].[set]
970 *
971 * @param ctx Read / write interface definitions
972 * @param buff Buffer that contains data to write
973 * @retval Interface status (MANDATORY: return 0 -> no Error).
974 *
975 */
lsm6ds3tr_c_xl_usr_offset_set(const stmdev_ctx_t * ctx,uint8_t * buff)976 int32_t lsm6ds3tr_c_xl_usr_offset_set(const stmdev_ctx_t *ctx,
977 uint8_t *buff)
978 {
979 int32_t ret;
980
981 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_X_OFS_USR, buff, 3);
982
983 return ret;
984 }
985
986 /**
987 * @brief Accelerometer axis user offset correction xpressed in two’s
988 * complement, weight depends on USR_OFF_W in CTRL6_C.
989 * The value must be in the range [-127 127].[get]
990 *
991 * @param ctx Read / write interface definitions
992 * @param buff Buffer that stores data read
993 * @retval Interface status (MANDATORY: return 0 -> no Error).
994 *
995 */
lsm6ds3tr_c_xl_usr_offset_get(const stmdev_ctx_t * ctx,uint8_t * buff)996 int32_t lsm6ds3tr_c_xl_usr_offset_get(const stmdev_ctx_t *ctx,
997 uint8_t *buff)
998 {
999 int32_t ret;
1000
1001 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_X_OFS_USR, buff, 3);
1002
1003 return ret;
1004 }
1005
1006 /**
1007 * @}
1008 *
1009 */
1010
1011 /**
1012 * @defgroup LSM6DS3TR_C_Timestamp
1013 * @brief This section groups all the functions that manage the
1014 * timestamp generation.
1015 * @{
1016 *
1017 */
1018
1019 /**
1020 * @brief Enable timestamp count. The count is saved in TIMESTAMP0_REG (40h),
1021 * TIMESTAMP1_REG (41h) and TIMESTAMP2_REG (42h).[set]
1022 *
1023 * @param ctx Read / write interface definitions
1024 * @param val Change the values of timer_en in reg CTRL10_C
1025 * @retval Interface status (MANDATORY: return 0 -> no Error).
1026 *
1027 */
lsm6ds3tr_c_timestamp_set(const stmdev_ctx_t * ctx,uint8_t val)1028 int32_t lsm6ds3tr_c_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val)
1029 {
1030 lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
1031 int32_t ret;
1032
1033 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
1034 (uint8_t *)&ctrl10_c, 1);
1035
1036 if (ret == 0)
1037 {
1038 ctrl10_c.timer_en = val;
1039
1040 if (val != 0x00U)
1041 {
1042 ctrl10_c.func_en = val;
1043 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C,
1044 (uint8_t *)&ctrl10_c, 1);
1045 }
1046 }
1047
1048 return ret;
1049 }
1050
1051 /**
1052 * @brief Enable timestamp count. The count is saved in TIMESTAMP0_REG (40h),
1053 * TIMESTAMP1_REG (41h) and TIMESTAMP2_REG (42h).[get]
1054 *
1055 * @param ctx Read / write interface definitions
1056 * @param val Change the values of timer_en in reg CTRL10_C
1057 * @retval Interface status (MANDATORY: return 0 -> no Error).
1058 *
1059 */
lsm6ds3tr_c_timestamp_get(const stmdev_ctx_t * ctx,uint8_t * val)1060 int32_t lsm6ds3tr_c_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val)
1061 {
1062 lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
1063 int32_t ret;
1064
1065 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
1066 (uint8_t *)&ctrl10_c, 1);
1067 *val = ctrl10_c.timer_en;
1068
1069 return ret;
1070 }
1071
1072 /**
1073 * @brief Timestamp register resolution setting.
1074 * Configuration of this bit affects
1075 * TIMESTAMP0_REG(40h), TIMESTAMP1_REG(41h),
1076 * TIMESTAMP2_REG(42h), STEP_TIMESTAMP_L(49h),
1077 * STEP_TIMESTAMP_H(4Ah) and
1078 * STEP_COUNT_DELTA(15h) registers.[set]
1079 *
1080 * @param ctx Read / write interface definitions
1081 * @param val Change the values of timer_hr in reg WAKE_UP_DUR
1082 * @retval Interface status (MANDATORY: return 0 -> no Error).
1083 *
1084 */
lsm6ds3tr_c_timestamp_res_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_timer_hr_t val)1085 int32_t lsm6ds3tr_c_timestamp_res_set(const stmdev_ctx_t *ctx,
1086 lsm6ds3tr_c_timer_hr_t val)
1087 {
1088 lsm6ds3tr_c_wake_up_dur_t wake_up_dur;
1089 int32_t ret;
1090
1091 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
1092 (uint8_t *)&wake_up_dur, 1);
1093
1094 if (ret == 0)
1095 {
1096 wake_up_dur.timer_hr = (uint8_t) val;
1097 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
1098 (uint8_t *)&wake_up_dur, 1);
1099 }
1100
1101 return ret;
1102 }
1103
1104 /**
1105 * @brief Timestamp register resolution setting.
1106 * Configuration of this bit affects
1107 * TIMESTAMP0_REG(40h), TIMESTAMP1_REG(41h),
1108 * TIMESTAMP2_REG(42h), STEP_TIMESTAMP_L(49h),
1109 * STEP_TIMESTAMP_H(4Ah) and
1110 * STEP_COUNT_DELTA(15h) registers.[get]
1111 *
1112 * @param ctx Read / write interface definitions
1113 * @param val Get the values of timer_hr in reg WAKE_UP_DUR
1114 * @retval Interface status (MANDATORY: return 0 -> no Error).
1115 *
1116 */
lsm6ds3tr_c_timestamp_res_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_timer_hr_t * val)1117 int32_t lsm6ds3tr_c_timestamp_res_get(const stmdev_ctx_t *ctx,
1118 lsm6ds3tr_c_timer_hr_t *val)
1119 {
1120 lsm6ds3tr_c_wake_up_dur_t wake_up_dur;
1121 int32_t ret;
1122
1123 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
1124 (uint8_t *)&wake_up_dur, 1);
1125
1126 switch (wake_up_dur.timer_hr)
1127 {
1128 case LSM6DS3TR_C_LSB_6ms4:
1129 *val = LSM6DS3TR_C_LSB_6ms4;
1130 break;
1131
1132 case LSM6DS3TR_C_LSB_25us:
1133 *val = LSM6DS3TR_C_LSB_25us;
1134 break;
1135
1136 default:
1137 *val = LSM6DS3TR_C_TS_RES_ND;
1138 break;
1139 }
1140
1141 return ret;
1142 }
1143
1144 /**
1145 * @}
1146 *
1147 */
1148
1149 /**
1150 * @defgroup LSM6DS3TR_C_Dataoutput
1151 * @brief This section groups all the data output functions.
1152 * @{
1153 *
1154 */
1155
1156 /**
1157 * @brief Circular burst-mode (rounding) read from output registers
1158 * through the primary interface.[set]
1159 *
1160 * @param ctx Read / write interface definitions
1161 * @param val Change the values of rounding in reg CTRL5_C
1162 * @retval Interface status (MANDATORY: return 0 -> no Error).
1163 *
1164 */
lsm6ds3tr_c_rounding_mode_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_rounding_t val)1165 int32_t lsm6ds3tr_c_rounding_mode_set(const stmdev_ctx_t *ctx,
1166 lsm6ds3tr_c_rounding_t val)
1167 {
1168 lsm6ds3tr_c_ctrl5_c_t ctrl5_c;
1169 int32_t ret;
1170
1171 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C,
1172 (uint8_t *)&ctrl5_c, 1);
1173
1174 if (ret == 0)
1175 {
1176 ctrl5_c.rounding = (uint8_t) val;
1177 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL5_C,
1178 (uint8_t *)&ctrl5_c, 1);
1179 }
1180
1181 return ret;
1182 }
1183
1184 /**
1185 * @brief Circular burst-mode (rounding) read from output registers
1186 * through the primary interface.[get]
1187 *
1188 * @param ctx Read / write interface definitions
1189 * @param val Get the values of rounding in reg CTRL5_C
1190 * @retval Interface status (MANDATORY: return 0 -> no Error).
1191 *
1192 */
lsm6ds3tr_c_rounding_mode_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_rounding_t * val)1193 int32_t lsm6ds3tr_c_rounding_mode_get(const stmdev_ctx_t *ctx,
1194 lsm6ds3tr_c_rounding_t *val)
1195 {
1196 lsm6ds3tr_c_ctrl5_c_t ctrl5_c;
1197 int32_t ret;
1198
1199 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C,
1200 (uint8_t *)&ctrl5_c, 1);
1201
1202 switch (ctrl5_c.rounding)
1203 {
1204 case LSM6DS3TR_C_ROUND_DISABLE:
1205 *val = LSM6DS3TR_C_ROUND_DISABLE;
1206 break;
1207
1208 case LSM6DS3TR_C_ROUND_XL:
1209 *val = LSM6DS3TR_C_ROUND_XL;
1210 break;
1211
1212 case LSM6DS3TR_C_ROUND_GY:
1213 *val = LSM6DS3TR_C_ROUND_GY;
1214 break;
1215
1216 case LSM6DS3TR_C_ROUND_GY_XL:
1217 *val = LSM6DS3TR_C_ROUND_GY_XL;
1218 break;
1219
1220 case LSM6DS3TR_C_ROUND_SH1_TO_SH6:
1221 *val = LSM6DS3TR_C_ROUND_SH1_TO_SH6;
1222 break;
1223
1224 case LSM6DS3TR_C_ROUND_XL_SH1_TO_SH6:
1225 *val = LSM6DS3TR_C_ROUND_XL_SH1_TO_SH6;
1226 break;
1227
1228 case LSM6DS3TR_C_ROUND_GY_XL_SH1_TO_SH12:
1229 *val = LSM6DS3TR_C_ROUND_GY_XL_SH1_TO_SH12;
1230 break;
1231
1232 case LSM6DS3TR_C_ROUND_GY_XL_SH1_TO_SH6:
1233 *val = LSM6DS3TR_C_ROUND_GY_XL_SH1_TO_SH6;
1234 break;
1235
1236 default:
1237 *val = LSM6DS3TR_C_ROUND_OUT_ND;
1238 break;
1239 }
1240
1241 return ret;
1242 }
1243
1244 /**
1245 * @brief Temperature data output register (r). L and H registers together
1246 * express a 16-bit word in two’s complement.[get]
1247 *
1248 * @param ctx Read / write interface definitions
1249 * @param buff Buffer that stores data read
1250 * @retval Interface status (MANDATORY: return 0 -> no Error).
1251 *
1252 */
lsm6ds3tr_c_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1253 int32_t lsm6ds3tr_c_temperature_raw_get(const stmdev_ctx_t *ctx,
1254 int16_t *val)
1255 {
1256 uint8_t buff[2];
1257 int32_t ret;
1258
1259 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_OUT_TEMP_L, buff, 2);
1260 *val = (int16_t)buff[1];
1261 *val = (*val * 256) + (int16_t)buff[0];
1262
1263 return ret;
1264 }
1265
1266 /**
1267 * @brief Angular rate sensor. The value is expressed as a 16-bit word in
1268 * two’s complement.[get]
1269 *
1270 * @param ctx Read / write interface definitions
1271 * @param buff Buffer that stores data read
1272 * @retval Interface status (MANDATORY: return 0 -> no Error).
1273 *
1274 */
lsm6ds3tr_c_angular_rate_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1275 int32_t lsm6ds3tr_c_angular_rate_raw_get(const stmdev_ctx_t *ctx,
1276 int16_t *val)
1277 {
1278 uint8_t buff[6];
1279 int32_t ret;
1280
1281 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_OUTX_L_G, buff, 6);
1282 val[0] = (int16_t)buff[1];
1283 val[0] = (val[0] * 256) + (int16_t)buff[0];
1284 val[1] = (int16_t)buff[3];
1285 val[1] = (val[1] * 256) + (int16_t)buff[2];
1286 val[2] = (int16_t)buff[5];
1287 val[2] = (val[2] * 256) + (int16_t)buff[4];
1288
1289 return ret;
1290 }
1291
1292 /**
1293 * @brief Linear acceleration output register. The value is expressed
1294 * as a 16-bit word in two’s complement.[get]
1295 *
1296 * @param ctx Read / write interface definitions
1297 * @param buff Buffer that stores data read
1298 * @retval Interface status (MANDATORY: return 0 -> no Error).
1299 *
1300 */
lsm6ds3tr_c_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1301 int32_t lsm6ds3tr_c_acceleration_raw_get(const stmdev_ctx_t *ctx,
1302 int16_t *val)
1303 {
1304 uint8_t buff[6];
1305 int32_t ret;
1306
1307 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_OUTX_L_XL, buff, 6);
1308 val[0] = (int16_t)buff[1];
1309 val[0] = (val[0] * 256) + (int16_t)buff[0];
1310 val[1] = (int16_t)buff[3];
1311 val[1] = (val[1] * 256) + (int16_t)buff[2];
1312 val[2] = (int16_t)buff[5];
1313 val[2] = (val[2] * 256) + (int16_t)buff[4];
1314
1315 return ret;
1316 }
1317
1318 /**
1319 * @brief External magnetometer raw data.[get]
1320 *
1321 * @param ctx Read / write interface definitions
1322 * @param buff Buffer that stores data read
1323 * @retval Interface status (MANDATORY: return 0 -> no Error).
1324 *
1325 */
lsm6ds3tr_c_mag_calibrated_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1326 int32_t lsm6ds3tr_c_mag_calibrated_raw_get(const stmdev_ctx_t *ctx,
1327 int16_t *val)
1328 {
1329 uint8_t buff[6];
1330 int32_t ret;
1331
1332 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_OUT_MAG_RAW_X_L, buff, 6);
1333 val[0] = (int16_t)buff[1];
1334 val[0] = (val[0] * 256) + (int16_t)buff[0];
1335 val[1] = (int16_t)buff[3];
1336 val[1] = (val[1] * 256) + (int16_t)buff[2];
1337 val[2] = (int16_t)buff[5];
1338 val[2] = (val[2] * 256) + (int16_t)buff[4];
1339
1340 return ret;
1341 }
1342
1343 /**
1344 * @brief Read data in FIFO.[get]
1345 *
1346 * @param ctx Read / write interface definitions
1347 * @param buffer Data buffer to store FIFO data.
1348 * @param len Number of data to read from FIFO.
1349 * @retval Interface status (MANDATORY: return 0 -> no Error).
1350 *
1351 */
lsm6ds3tr_c_fifo_raw_data_get(const stmdev_ctx_t * ctx,uint8_t * buffer,uint8_t len)1352 int32_t lsm6ds3tr_c_fifo_raw_data_get(const stmdev_ctx_t *ctx,
1353 uint8_t *buffer,
1354 uint8_t len)
1355 {
1356 int32_t ret;
1357
1358 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_DATA_OUT_L, buffer,
1359 len);
1360
1361 return ret;
1362 }
1363
1364 /**
1365 * @}
1366 *
1367 */
1368
1369 /**
1370 * @defgroup LSM6DS3TR_C_common
1371 * @brief This section groups common useful functions.
1372 * @{
1373 *
1374 */
1375
1376 /**
1377 * @brief Enable access to the embedded functions/sensor hub
1378 * configuration registers[set]
1379 *
1380 * @param ctx Read / write interface definitions
1381 * @param val Change the values of func_cfg_en in reg FUNC_CFG_ACCESS
1382 * @retval Interface status (MANDATORY: return 0 -> no Error).
1383 *
1384 */
lsm6ds3tr_c_mem_bank_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_func_cfg_en_t val)1385 int32_t lsm6ds3tr_c_mem_bank_set(const stmdev_ctx_t *ctx,
1386 lsm6ds3tr_c_func_cfg_en_t val)
1387 {
1388 lsm6ds3tr_c_func_cfg_access_t func_cfg_access;
1389 int32_t ret;
1390
1391 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FUNC_CFG_ACCESS,
1392 (uint8_t *)&func_cfg_access, 1);
1393
1394 if (ret == 0)
1395 {
1396 func_cfg_access.func_cfg_en = (uint8_t) val;
1397 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FUNC_CFG_ACCESS,
1398 (uint8_t *)&func_cfg_access, 1);
1399 }
1400
1401 return ret;
1402 }
1403
1404 /**
1405 * @brief Enable access to the embedded functions/sensor hub configuration
1406 * registers[get]
1407 *
1408 * @param ctx Read / write interface definitions
1409 * @param val Get the values of func_cfg_en in reg FUNC_CFG_ACCESS
1410 * @retval Interface status (MANDATORY: return 0 -> no Error).
1411 *
1412 */
lsm6ds3tr_c_mem_bank_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_func_cfg_en_t * val)1413 int32_t lsm6ds3tr_c_mem_bank_get(const stmdev_ctx_t *ctx,
1414 lsm6ds3tr_c_func_cfg_en_t *val)
1415 {
1416 lsm6ds3tr_c_func_cfg_access_t func_cfg_access;
1417 int32_t ret;
1418
1419 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FUNC_CFG_ACCESS,
1420 (uint8_t *)&func_cfg_access, 1);
1421
1422 switch (func_cfg_access.func_cfg_en)
1423 {
1424 case LSM6DS3TR_C_USER_BANK:
1425 *val = LSM6DS3TR_C_USER_BANK;
1426 break;
1427
1428 case LSM6DS3TR_C_BANK_B:
1429 *val = LSM6DS3TR_C_BANK_B;
1430 break;
1431
1432 default:
1433 *val = LSM6DS3TR_C_BANK_ND;
1434 break;
1435 }
1436
1437 return ret;
1438 }
1439
1440 /**
1441 * @brief Data-ready pulsed / letched mode[set]
1442 *
1443 * @param ctx Read / write interface definitions
1444 * @param val Change the values of drdy_pulsed in reg DRDY_PULSE_CFG
1445 * @retval Interface status (MANDATORY: return 0 -> no Error).
1446 *
1447 */
lsm6ds3tr_c_data_ready_mode_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_drdy_pulsed_g_t val)1448 int32_t lsm6ds3tr_c_data_ready_mode_set(const stmdev_ctx_t *ctx,
1449 lsm6ds3tr_c_drdy_pulsed_g_t val)
1450 {
1451 lsm6ds3tr_c_drdy_pulse_cfg_g_t drdy_pulse_cfg_g;
1452 int32_t ret;
1453
1454 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G,
1455 (uint8_t *)&drdy_pulse_cfg_g, 1);
1456
1457 if (ret == 0)
1458 {
1459 drdy_pulse_cfg_g.drdy_pulsed = (uint8_t) val;
1460 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G,
1461 (uint8_t *)&drdy_pulse_cfg_g, 1);
1462 }
1463
1464 return ret;
1465 }
1466
1467 /**
1468 * @brief Data-ready pulsed / letched mode[get]
1469 *
1470 * @param ctx Read / write interface definitions
1471 * @param val Get the values of drdy_pulsed in reg DRDY_PULSE_CFG
1472 * @retval Interface status (MANDATORY: return 0 -> no Error).
1473 *
1474 */
lsm6ds3tr_c_data_ready_mode_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_drdy_pulsed_g_t * val)1475 int32_t lsm6ds3tr_c_data_ready_mode_get(const stmdev_ctx_t *ctx,
1476 lsm6ds3tr_c_drdy_pulsed_g_t *val)
1477 {
1478 lsm6ds3tr_c_drdy_pulse_cfg_g_t drdy_pulse_cfg_g;
1479 int32_t ret;
1480
1481 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G,
1482 (uint8_t *)&drdy_pulse_cfg_g, 1);
1483
1484 switch (drdy_pulse_cfg_g.drdy_pulsed)
1485 {
1486 case LSM6DS3TR_C_DRDY_LATCHED:
1487 *val = LSM6DS3TR_C_DRDY_LATCHED;
1488 break;
1489
1490 case LSM6DS3TR_C_DRDY_PULSED:
1491 *val = LSM6DS3TR_C_DRDY_PULSED;
1492 break;
1493
1494 default:
1495 *val = LSM6DS3TR_C_DRDY_ND;
1496 break;
1497 }
1498
1499 return ret;
1500 }
1501
1502 /**
1503 * @brief DeviceWhoamI.[get]
1504 *
1505 * @param ctx Read / write interface definitions
1506 * @param buff Buffer that stores data read
1507 * @retval Interface status (MANDATORY: return 0 -> no Error).
1508 *
1509 */
lsm6ds3tr_c_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)1510 int32_t lsm6ds3tr_c_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1511 {
1512 int32_t ret;
1513
1514 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WHO_AM_I, buff, 1);
1515
1516 return ret;
1517 }
1518
1519 /**
1520 * @brief Software reset. Restore the default values in user registers[set]
1521 *
1522 * @param ctx Read / write interface definitions
1523 * @param val Change the values of sw_reset in reg CTRL3_C
1524 * @retval Interface status (MANDATORY: return 0 -> no Error).
1525 *
1526 */
lsm6ds3tr_c_reset_set(const stmdev_ctx_t * ctx,uint8_t val)1527 int32_t lsm6ds3tr_c_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
1528 {
1529 lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
1530 int32_t ret;
1531
1532 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
1533 (uint8_t *)&ctrl3_c, 1);
1534
1535 if (ret == 0)
1536 {
1537 ctrl3_c.sw_reset = val;
1538 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C,
1539 (uint8_t *)&ctrl3_c, 1);
1540 }
1541
1542 return ret;
1543 }
1544
1545 /**
1546 * @brief Software reset. Restore the default values in user registers[get]
1547 *
1548 * @param ctx Read / write interface definitions
1549 * @param val Change the values of sw_reset in reg CTRL3_C
1550 * @retval Interface status (MANDATORY: return 0 -> no Error).
1551 *
1552 */
lsm6ds3tr_c_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)1553 int32_t lsm6ds3tr_c_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
1554 {
1555 lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
1556 int32_t ret;
1557
1558 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
1559 (uint8_t *)&ctrl3_c, 1);
1560 *val = ctrl3_c.sw_reset;
1561
1562 return ret;
1563 }
1564
1565 /**
1566 * @brief Big/Little Endian Data selection.[set]
1567 *
1568 * @param ctx Read / write interface definitions
1569 * @param val Change the values of ble in reg CTRL3_C
1570 * @retval Interface status (MANDATORY: return 0 -> no Error).
1571 *
1572 */
lsm6ds3tr_c_data_format_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_ble_t val)1573 int32_t lsm6ds3tr_c_data_format_set(const stmdev_ctx_t *ctx,
1574 lsm6ds3tr_c_ble_t val)
1575 {
1576 lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
1577 int32_t ret;
1578
1579 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
1580 (uint8_t *)&ctrl3_c, 1);
1581
1582 if (ret == 0)
1583 {
1584 ctrl3_c.ble = (uint8_t) val;
1585 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C,
1586 (uint8_t *)&ctrl3_c, 1);
1587 }
1588
1589 return ret;
1590 }
1591
1592 /**
1593 * @brief Big/Little Endian Data selection.[get]
1594 *
1595 * @param ctx Read / write interface definitions
1596 * @param val Get the values of ble in reg CTRL3_C
1597 * @retval Interface status (MANDATORY: return 0 -> no Error).
1598 *
1599 */
lsm6ds3tr_c_data_format_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_ble_t * val)1600 int32_t lsm6ds3tr_c_data_format_get(const stmdev_ctx_t *ctx,
1601 lsm6ds3tr_c_ble_t *val)
1602 {
1603 lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
1604 int32_t ret;
1605
1606 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
1607 (uint8_t *)&ctrl3_c, 1);
1608
1609 switch (ctrl3_c.ble)
1610 {
1611 case LSM6DS3TR_C_LSB_AT_LOW_ADD:
1612 *val = LSM6DS3TR_C_LSB_AT_LOW_ADD;
1613 break;
1614
1615 case LSM6DS3TR_C_MSB_AT_LOW_ADD:
1616 *val = LSM6DS3TR_C_MSB_AT_LOW_ADD;
1617 break;
1618
1619 default:
1620 *val = LSM6DS3TR_C_DATA_FMT_ND;
1621 break;
1622 }
1623
1624 return ret;
1625 }
1626
1627 /**
1628 * @brief Register address automatically incremented during a multiple byte
1629 * access with a serial interface.[set]
1630 *
1631 * @param ctx Read / write interface definitions
1632 * @param val Change the values of if_inc in reg CTRL3_C
1633 * @retval Interface status (MANDATORY: return 0 -> no Error).
1634 *
1635 */
lsm6ds3tr_c_auto_increment_set(const stmdev_ctx_t * ctx,uint8_t val)1636 int32_t lsm6ds3tr_c_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val)
1637 {
1638 lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
1639 int32_t ret;
1640
1641 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
1642 (uint8_t *)&ctrl3_c, 1);
1643
1644 if (ret == 0)
1645 {
1646 ctrl3_c.if_inc = val;
1647 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C,
1648 (uint8_t *)&ctrl3_c, 1);
1649 }
1650
1651 return ret;
1652 }
1653
1654 /**
1655 * @brief Register address automatically incremented during a multiple byte
1656 * access with a serial interface.[get]
1657 *
1658 * @param ctx Read / write interface definitions
1659 * @param val Change the values of if_inc in reg CTRL3_C
1660 * @retval Interface status (MANDATORY: return 0 -> no Error).
1661 *
1662 */
lsm6ds3tr_c_auto_increment_get(const stmdev_ctx_t * ctx,uint8_t * val)1663 int32_t lsm6ds3tr_c_auto_increment_get(const stmdev_ctx_t *ctx,
1664 uint8_t *val)
1665 {
1666 lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
1667 int32_t ret;
1668
1669 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
1670 (uint8_t *)&ctrl3_c, 1);
1671 *val = ctrl3_c.if_inc;
1672
1673 return ret;
1674 }
1675
1676 /**
1677 * @brief Reboot memory content. Reload the calibration parameters.[set]
1678 *
1679 * @param ctx Read / write interface definitions
1680 * @param val Change the values of boot in reg CTRL3_C
1681 * @retval Interface status (MANDATORY: return 0 -> no Error).
1682 *
1683 */
lsm6ds3tr_c_boot_set(const stmdev_ctx_t * ctx,uint8_t val)1684 int32_t lsm6ds3tr_c_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
1685 {
1686 lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
1687 int32_t ret;
1688
1689 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
1690 (uint8_t *)&ctrl3_c, 1);
1691
1692 if (ret == 0)
1693 {
1694 ctrl3_c.boot = val;
1695 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C,
1696 (uint8_t *)&ctrl3_c, 1);
1697 }
1698
1699 return ret;
1700 }
1701
1702 /**
1703 * @brief Reboot memory content. Reload the calibration parameters.[get]
1704 *
1705 * @param ctx Read / write interface definitions
1706 * @param val Change the values of boot in reg CTRL3_C
1707 * @retval Interface status (MANDATORY: return 0 -> no Error).
1708 *
1709 */
lsm6ds3tr_c_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)1710 int32_t lsm6ds3tr_c_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
1711 {
1712 lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
1713 int32_t ret;
1714
1715 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
1716 (uint8_t *)&ctrl3_c, 1);
1717 *val = ctrl3_c.boot;
1718
1719 return ret;
1720 }
1721
1722 /**
1723 * @brief Linear acceleration sensor self-test enable.[set]
1724 *
1725 * @param ctx Read / write interface definitions
1726 * @param val Change the values of st_xl in reg CTRL5_C
1727 * @retval Interface status (MANDATORY: return 0 -> no Error).
1728 *
1729 */
lsm6ds3tr_c_xl_self_test_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_st_xl_t val)1730 int32_t lsm6ds3tr_c_xl_self_test_set(const stmdev_ctx_t *ctx,
1731 lsm6ds3tr_c_st_xl_t val)
1732 {
1733 lsm6ds3tr_c_ctrl5_c_t ctrl5_c;
1734 int32_t ret;
1735
1736 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C,
1737 (uint8_t *)&ctrl5_c, 1);
1738
1739 if (ret == 0)
1740 {
1741 ctrl5_c.st_xl = (uint8_t) val;
1742 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL5_C,
1743 (uint8_t *)&ctrl5_c, 1);
1744 }
1745
1746 return ret;
1747 }
1748
1749 /**
1750 * @brief Linear acceleration sensor self-test enable.[get]
1751 *
1752 * @param ctx Read / write interface definitions
1753 * @param val Get the values of st_xl in reg CTRL5_C
1754 * @retval Interface status (MANDATORY: return 0 -> no Error).
1755 *
1756 */
lsm6ds3tr_c_xl_self_test_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_st_xl_t * val)1757 int32_t lsm6ds3tr_c_xl_self_test_get(const stmdev_ctx_t *ctx,
1758 lsm6ds3tr_c_st_xl_t *val)
1759 {
1760 lsm6ds3tr_c_ctrl5_c_t ctrl5_c;
1761 int32_t ret;
1762
1763 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C,
1764 (uint8_t *)&ctrl5_c, 1);
1765
1766 switch (ctrl5_c.st_xl)
1767 {
1768 case LSM6DS3TR_C_XL_ST_DISABLE:
1769 *val = LSM6DS3TR_C_XL_ST_DISABLE;
1770 break;
1771
1772 case LSM6DS3TR_C_XL_ST_POSITIVE:
1773 *val = LSM6DS3TR_C_XL_ST_POSITIVE;
1774 break;
1775
1776 case LSM6DS3TR_C_XL_ST_NEGATIVE:
1777 *val = LSM6DS3TR_C_XL_ST_NEGATIVE;
1778 break;
1779
1780 default:
1781 *val = LSM6DS3TR_C_XL_ST_ND;
1782 break;
1783 }
1784
1785 return ret;
1786 }
1787
1788 /**
1789 * @brief Angular rate sensor self-test enable.[set]
1790 *
1791 * @param ctx Read / write interface definitions
1792 * @param val Change the values of st_g in reg CTRL5_C
1793 * @retval Interface status (MANDATORY: return 0 -> no Error).
1794 *
1795 */
lsm6ds3tr_c_gy_self_test_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_st_g_t val)1796 int32_t lsm6ds3tr_c_gy_self_test_set(const stmdev_ctx_t *ctx,
1797 lsm6ds3tr_c_st_g_t val)
1798 {
1799 lsm6ds3tr_c_ctrl5_c_t ctrl5_c;
1800 int32_t ret;
1801
1802 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C,
1803 (uint8_t *)&ctrl5_c, 1);
1804
1805 if (ret == 0)
1806 {
1807 ctrl5_c.st_g = (uint8_t) val;
1808 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL5_C,
1809 (uint8_t *)&ctrl5_c, 1);
1810 }
1811
1812 return ret;
1813 }
1814
1815 /**
1816 * @brief Angular rate sensor self-test enable.[get]
1817 *
1818 * @param ctx Read / write interface definitions
1819 * @param val Get the values of st_g in reg CTRL5_C
1820 * @retval Interface status (MANDATORY: return 0 -> no Error).
1821 *
1822 */
lsm6ds3tr_c_gy_self_test_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_st_g_t * val)1823 int32_t lsm6ds3tr_c_gy_self_test_get(const stmdev_ctx_t *ctx,
1824 lsm6ds3tr_c_st_g_t *val)
1825 {
1826 lsm6ds3tr_c_ctrl5_c_t ctrl5_c;
1827 int32_t ret;
1828
1829 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C,
1830 (uint8_t *)&ctrl5_c, 1);
1831
1832 switch (ctrl5_c.st_g)
1833 {
1834 case LSM6DS3TR_C_GY_ST_DISABLE:
1835 *val = LSM6DS3TR_C_GY_ST_DISABLE;
1836 break;
1837
1838 case LSM6DS3TR_C_GY_ST_POSITIVE:
1839 *val = LSM6DS3TR_C_GY_ST_POSITIVE;
1840 break;
1841
1842 case LSM6DS3TR_C_GY_ST_NEGATIVE:
1843 *val = LSM6DS3TR_C_GY_ST_NEGATIVE;
1844 break;
1845
1846 default:
1847 *val = LSM6DS3TR_C_GY_ST_ND;
1848 break;
1849 }
1850
1851 return ret;
1852 }
1853
1854 /**
1855 * @}
1856 *
1857 */
1858
1859 /**
1860 * @defgroup LSM6DS3TR_C_filters
1861 * @brief This section group all the functions concerning the filters
1862 * configuration that impact both accelerometer and gyro.
1863 * @{
1864 *
1865 */
1866
1867 /**
1868 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
1869 * (XL and Gyro independently masked).[set]
1870 *
1871 * @param ctx Read / write interface definitions
1872 * @param val Change the values of drdy_mask in reg CTRL4_C
1873 * @retval Interface status (MANDATORY: return 0 -> no Error).
1874 *
1875 */
lsm6ds3tr_c_filter_settling_mask_set(const stmdev_ctx_t * ctx,uint8_t val)1876 int32_t lsm6ds3tr_c_filter_settling_mask_set(const stmdev_ctx_t *ctx,
1877 uint8_t val)
1878 {
1879 lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
1880 int32_t ret;
1881
1882 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
1883 (uint8_t *)&ctrl4_c, 1);
1884
1885 if (ret == 0)
1886 {
1887 ctrl4_c.drdy_mask = val;
1888 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C,
1889 (uint8_t *)&ctrl4_c, 1);
1890 }
1891
1892 return ret;
1893 }
1894
1895 /**
1896 * @brief Mask DRDY on pin (both XL & Gyro) until filter settling ends
1897 * (XL and Gyro independently masked).[get]
1898 *
1899 * @param ctx Read / write interface definitions
1900 * @param val Change the values of drdy_mask in reg CTRL4_C
1901 * @retval Interface status (MANDATORY: return 0 -> no Error).
1902 *
1903 */
lsm6ds3tr_c_filter_settling_mask_get(const stmdev_ctx_t * ctx,uint8_t * val)1904 int32_t lsm6ds3tr_c_filter_settling_mask_get(const stmdev_ctx_t *ctx,
1905 uint8_t *val)
1906 {
1907 lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
1908 int32_t ret;
1909
1910 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
1911 (uint8_t *)&ctrl4_c, 1);
1912 *val = ctrl4_c.drdy_mask;
1913
1914 return ret;
1915 }
1916
1917 /**
1918 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
1919 * functions.[set]
1920 *
1921 * @param ctx Read / write interface definitions
1922 * @param val Change the values of slope_fds in reg TAP_CFG
1923 * @retval Interface status (MANDATORY: return 0 -> no Error).
1924 *
1925 */
lsm6ds3tr_c_xl_hp_path_internal_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_slope_fds_t val)1926 int32_t lsm6ds3tr_c_xl_hp_path_internal_set(const stmdev_ctx_t *ctx,
1927 lsm6ds3tr_c_slope_fds_t val)
1928 {
1929 lsm6ds3tr_c_tap_cfg_t tap_cfg;
1930 int32_t ret;
1931
1932 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
1933 (uint8_t *)&tap_cfg, 1);
1934
1935 if (ret == 0)
1936 {
1937 tap_cfg.slope_fds = (uint8_t) val;
1938 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG,
1939 (uint8_t *)&tap_cfg, 1);
1940 }
1941
1942 return ret;
1943 }
1944
1945 /**
1946 * @brief HPF or SLOPE filter selection on wake-up and Activity/Inactivity
1947 * functions.[get]
1948 *
1949 * @param ctx Read / write interface definitions
1950 * @param val Get the values of slope_fds in reg TAP_CFG
1951 * @retval Interface status (MANDATORY: return 0 -> no Error).
1952 *
1953 */
lsm6ds3tr_c_xl_hp_path_internal_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_slope_fds_t * val)1954 int32_t lsm6ds3tr_c_xl_hp_path_internal_get(const stmdev_ctx_t *ctx,
1955 lsm6ds3tr_c_slope_fds_t *val)
1956 {
1957 lsm6ds3tr_c_tap_cfg_t tap_cfg;
1958 int32_t ret;
1959
1960 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
1961 (uint8_t *)&tap_cfg, 1);
1962
1963 switch (tap_cfg.slope_fds)
1964 {
1965 case LSM6DS3TR_C_USE_SLOPE:
1966 *val = LSM6DS3TR_C_USE_SLOPE;
1967 break;
1968
1969 case LSM6DS3TR_C_USE_HPF:
1970 *val = LSM6DS3TR_C_USE_HPF;
1971 break;
1972
1973 default:
1974 *val = LSM6DS3TR_C_HP_PATH_ND;
1975 break;
1976 }
1977
1978 return ret;
1979 }
1980
1981 /**
1982 * @}
1983 *
1984 */
1985
1986 /**
1987 * @defgroup LSM6DS3TR_C_accelerometer_filters
1988 * @brief This section group all the functions concerning the filters
1989 * configuration that impact accelerometer in every mode.
1990 * @{
1991 *
1992 */
1993
1994 /**
1995 * @brief Accelerometer analog chain bandwidth selection (only for
1996 * accelerometer ODR ≥ 1.67 kHz).[set]
1997 *
1998 * @param ctx Read / write interface definitions
1999 * @param val Change the values of bw0_xl in reg CTRL1_XL
2000 * @retval Interface status (MANDATORY: return 0 -> no Error).
2001 *
2002 */
lsm6ds3tr_c_xl_filter_analog_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_bw0_xl_t val)2003 int32_t lsm6ds3tr_c_xl_filter_analog_set(const stmdev_ctx_t *ctx,
2004 lsm6ds3tr_c_bw0_xl_t val)
2005 {
2006 lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl;
2007 int32_t ret;
2008
2009 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
2010 (uint8_t *)&ctrl1_xl, 1);
2011
2012 if (ret == 0)
2013 {
2014 ctrl1_xl.bw0_xl = (uint8_t) val;
2015 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
2016 (uint8_t *)&ctrl1_xl, 1);
2017 }
2018
2019 return ret;
2020 }
2021
2022 /**
2023 * @brief Accelerometer analog chain bandwidth selection (only for
2024 * accelerometer ODR ≥ 1.67 kHz).[get]
2025 *
2026 * @param ctx Read / write interface definitions
2027 * @param val Get the values of bw0_xl in reg CTRL1_XL
2028 * @retval Interface status (MANDATORY: return 0 -> no Error).
2029 *
2030 */
lsm6ds3tr_c_xl_filter_analog_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_bw0_xl_t * val)2031 int32_t lsm6ds3tr_c_xl_filter_analog_get(const stmdev_ctx_t *ctx,
2032 lsm6ds3tr_c_bw0_xl_t *val)
2033 {
2034 lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl;
2035 int32_t ret;
2036
2037 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
2038 (uint8_t *)&ctrl1_xl, 1);
2039
2040 switch (ctrl1_xl.bw0_xl)
2041 {
2042 case LSM6DS3TR_C_XL_ANA_BW_1k5Hz:
2043 *val = LSM6DS3TR_C_XL_ANA_BW_1k5Hz;
2044 break;
2045
2046 case LSM6DS3TR_C_XL_ANA_BW_400Hz:
2047 *val = LSM6DS3TR_C_XL_ANA_BW_400Hz;
2048 break;
2049
2050 default:
2051 *val = LSM6DS3TR_C_XL_ANA_BW_ND;
2052 break;
2053 }
2054
2055 return ret;
2056 }
2057
2058 /**
2059 * @}
2060 *
2061 */
2062
2063 /**
2064 * @defgroup LSM6DS3TR_C_accelerometer_filters
2065 * @brief This section group all the functions concerning the filters
2066 * configuration that impact accelerometer.
2067 * @{
2068 *
2069 */
2070
2071 /**
2072 * @brief Accelerometer digital LPF (LPF1) bandwidth selection LPF2 is
2073 * not used.[set]
2074 *
2075 * @param ctx Read / write interface definitions
2076 * @param val Change the values of lpf1_bw_sel in reg CTRL1_XL
2077 * @retval Interface status (MANDATORY: return 0 -> no Error).
2078 *
2079 */
lsm6ds3tr_c_xl_lp1_bandwidth_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_lpf1_bw_sel_t val)2080 int32_t lsm6ds3tr_c_xl_lp1_bandwidth_set(const stmdev_ctx_t *ctx,
2081 lsm6ds3tr_c_lpf1_bw_sel_t val)
2082 {
2083 lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl;
2084 lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
2085 int32_t ret;
2086
2087 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
2088 (uint8_t *)&ctrl1_xl, 1);
2089
2090 if (ret == 0)
2091 {
2092 ctrl1_xl.lpf1_bw_sel = (uint8_t) val;
2093 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
2094 (uint8_t *)&ctrl1_xl, 1);
2095
2096 if (ret == 0)
2097 {
2098 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
2099 (uint8_t *)&ctrl8_xl, 1);
2100
2101 if (ret == 0)
2102 {
2103 ctrl8_xl.lpf2_xl_en = 0;
2104 ctrl8_xl.hp_slope_xl_en = 0;
2105 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
2106 (uint8_t *)&ctrl8_xl, 1);
2107 }
2108 }
2109 }
2110
2111 return ret;
2112 }
2113
2114 /**
2115 * @brief Accelerometer digital LPF (LPF1) bandwidth selection LPF2
2116 * is not used.[get]
2117 *
2118 * @param ctx Read / write interface definitions
2119 * @param val Get the values of lpf1_bw_sel in reg CTRL1_XL
2120 * @retval Interface status (MANDATORY: return 0 -> no Error).
2121 *
2122 */
lsm6ds3tr_c_xl_lp1_bandwidth_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_lpf1_bw_sel_t * val)2123 int32_t lsm6ds3tr_c_xl_lp1_bandwidth_get(const stmdev_ctx_t *ctx,
2124 lsm6ds3tr_c_lpf1_bw_sel_t *val)
2125 {
2126 lsm6ds3tr_c_ctrl1_xl_t ctrl1_xl;
2127 lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
2128 int32_t ret;
2129
2130 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
2131 (uint8_t *)&ctrl8_xl, 1);
2132
2133 if (ret == 0)
2134 {
2135 if ((ctrl8_xl.lpf2_xl_en != 0x00U) ||
2136 (ctrl8_xl.hp_slope_xl_en != 0x00U))
2137 {
2138 *val = LSM6DS3TR_C_XL_LP1_NA;
2139 }
2140
2141 else
2142 {
2143 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL1_XL,
2144 (uint8_t *)&ctrl1_xl, 1);
2145
2146 switch (ctrl1_xl.lpf1_bw_sel)
2147 {
2148 case LSM6DS3TR_C_XL_LP1_ODR_DIV_2:
2149 *val = LSM6DS3TR_C_XL_LP1_ODR_DIV_2;
2150 break;
2151
2152 case LSM6DS3TR_C_XL_LP1_ODR_DIV_4:
2153 *val = LSM6DS3TR_C_XL_LP1_ODR_DIV_4;
2154 break;
2155
2156 default:
2157 *val = LSM6DS3TR_C_XL_LP1_NA;
2158 break;
2159 }
2160 }
2161 }
2162
2163 return ret;
2164 }
2165
2166 /**
2167 * @brief LPF2 on outputs[set]
2168 *
2169 * @param ctx Read / write interface definitions
2170 * @param val Change the values of input_composite in reg CTRL8_XL
2171 * @retval Interface status (MANDATORY: return 0 -> no Error).
2172 *
2173 */
lsm6ds3tr_c_xl_lp2_bandwidth_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_input_composite_t val)2174 int32_t lsm6ds3tr_c_xl_lp2_bandwidth_set(const stmdev_ctx_t *ctx,
2175 lsm6ds3tr_c_input_composite_t val)
2176 {
2177 lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
2178 int32_t ret;
2179
2180 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
2181 (uint8_t *)&ctrl8_xl, 1);
2182
2183 if (ret == 0)
2184 {
2185 ctrl8_xl.input_composite = ((uint8_t) val & 0x10U) >> 4;
2186 ctrl8_xl.hpcf_xl = (uint8_t) val & 0x03U;
2187 ctrl8_xl.lpf2_xl_en = 1;
2188 ctrl8_xl.hp_slope_xl_en = 0;
2189 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
2190 (uint8_t *)&ctrl8_xl, 1);
2191 }
2192
2193 return ret;
2194 }
2195
2196 /**
2197 * @brief LPF2 on outputs[get]
2198 *
2199 * @param ctx Read / write interface definitions
2200 * @param val Get the values of input_composite in reg CTRL8_XL
2201 * @retval Interface status (MANDATORY: return 0 -> no Error).
2202 *
2203 */
lsm6ds3tr_c_xl_lp2_bandwidth_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_input_composite_t * val)2204 int32_t lsm6ds3tr_c_xl_lp2_bandwidth_get(const stmdev_ctx_t *ctx,
2205 lsm6ds3tr_c_input_composite_t *val)
2206 {
2207 lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
2208 int32_t ret;
2209
2210 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
2211 (uint8_t *)&ctrl8_xl, 1);
2212
2213 if (ret == 0)
2214 {
2215 if ((ctrl8_xl.lpf2_xl_en == 0x00U) ||
2216 (ctrl8_xl.hp_slope_xl_en != 0x00U))
2217 {
2218 *val = LSM6DS3TR_C_XL_LP_NA;
2219 }
2220
2221 else
2222 {
2223 switch ((ctrl8_xl.input_composite << 4) + ctrl8_xl.hpcf_xl)
2224 {
2225 case LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_50:
2226 *val = LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_50;
2227 break;
2228
2229 case LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_100:
2230 *val = LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_100;
2231 break;
2232
2233 case LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_9:
2234 *val = LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_9;
2235 break;
2236
2237 case LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_400:
2238 *val = LSM6DS3TR_C_XL_LOW_LAT_LP_ODR_DIV_400;
2239 break;
2240
2241 case LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_50:
2242 *val = LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_50;
2243 break;
2244
2245 case LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_100:
2246 *val = LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_100;
2247 break;
2248
2249 case LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_9:
2250 *val = LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_9;
2251 break;
2252
2253 case LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_400:
2254 *val = LSM6DS3TR_C_XL_LOW_NOISE_LP_ODR_DIV_400;
2255 break;
2256
2257 default:
2258 *val = LSM6DS3TR_C_XL_LP_NA;
2259 break;
2260 }
2261 }
2262 }
2263
2264 return ret;
2265 }
2266
2267 /**
2268 * @brief Enable HP filter reference mode.[set]
2269 *
2270 * @param ctx Read / write interface definitions
2271 * @param val Change the values of hp_ref_mode in reg CTRL8_XL
2272 * @retval Interface status (MANDATORY: return 0 -> no Error).
2273 *
2274 */
lsm6ds3tr_c_xl_reference_mode_set(const stmdev_ctx_t * ctx,uint8_t val)2275 int32_t lsm6ds3tr_c_xl_reference_mode_set(const stmdev_ctx_t *ctx,
2276 uint8_t val)
2277 {
2278 lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
2279 int32_t ret;
2280
2281 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
2282 (uint8_t *)&ctrl8_xl, 1);
2283
2284 if (ret == 0)
2285 {
2286 ctrl8_xl.hp_ref_mode = val;
2287 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
2288 (uint8_t *)&ctrl8_xl, 1);
2289 }
2290
2291 return ret;
2292 }
2293
2294 /**
2295 * @brief Enable HP filter reference mode.[get]
2296 *
2297 * @param ctx Read / write interface definitions
2298 * @param val Change the values of hp_ref_mode in reg CTRL8_XL
2299 * @retval Interface status (MANDATORY: return 0 -> no Error).
2300 *
2301 */
lsm6ds3tr_c_xl_reference_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)2302 int32_t lsm6ds3tr_c_xl_reference_mode_get(const stmdev_ctx_t *ctx,
2303 uint8_t *val)
2304 {
2305 lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
2306 int32_t ret;
2307
2308 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
2309 (uint8_t *)&ctrl8_xl, 1);
2310 *val = ctrl8_xl.hp_ref_mode;
2311
2312 return ret;
2313 }
2314
2315 /**
2316 * @brief High pass/Slope on outputs.[set]
2317 *
2318 * @param ctx Read / write interface definitions
2319 * @param val Change the values of hpcf_xl in reg CTRL8_XL
2320 * @retval Interface status (MANDATORY: return 0 -> no Error).
2321 *
2322 */
lsm6ds3tr_c_xl_hp_bandwidth_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_hpcf_xl_t val)2323 int32_t lsm6ds3tr_c_xl_hp_bandwidth_set(const stmdev_ctx_t *ctx,
2324 lsm6ds3tr_c_hpcf_xl_t val)
2325 {
2326 lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
2327 int32_t ret;
2328
2329 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
2330 (uint8_t *)&ctrl8_xl, 1);
2331
2332 if (ret == 0)
2333 {
2334 ctrl8_xl.input_composite = 0;
2335 ctrl8_xl.hpcf_xl = (uint8_t)val & 0x03U;
2336 ctrl8_xl.hp_slope_xl_en = 1;
2337 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
2338 (uint8_t *)&ctrl8_xl, 1);
2339 }
2340
2341 return ret;
2342 }
2343
2344 /**
2345 * @brief High pass/Slope on outputs.[get]
2346 *
2347 * @param ctx Read / write interface definitions
2348 * @param val Get the values of hpcf_xl in reg CTRL8_XL
2349 * @retval Interface status (MANDATORY: return 0 -> no Error).
2350 *
2351 */
lsm6ds3tr_c_xl_hp_bandwidth_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_hpcf_xl_t * val)2352 int32_t lsm6ds3tr_c_xl_hp_bandwidth_get(const stmdev_ctx_t *ctx,
2353 lsm6ds3tr_c_hpcf_xl_t *val)
2354 {
2355 lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
2356 int32_t ret;
2357
2358 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
2359 (uint8_t *)&ctrl8_xl, 1);
2360
2361 if (ctrl8_xl.hp_slope_xl_en == 0x00U)
2362 {
2363 *val = LSM6DS3TR_C_XL_HP_NA;
2364 }
2365
2366 switch (ctrl8_xl.hpcf_xl)
2367 {
2368 case LSM6DS3TR_C_XL_HP_ODR_DIV_4:
2369 *val = LSM6DS3TR_C_XL_HP_ODR_DIV_4;
2370 break;
2371
2372 case LSM6DS3TR_C_XL_HP_ODR_DIV_100:
2373 *val = LSM6DS3TR_C_XL_HP_ODR_DIV_100;
2374 break;
2375
2376 case LSM6DS3TR_C_XL_HP_ODR_DIV_9:
2377 *val = LSM6DS3TR_C_XL_HP_ODR_DIV_9;
2378 break;
2379
2380 case LSM6DS3TR_C_XL_HP_ODR_DIV_400:
2381 *val = LSM6DS3TR_C_XL_HP_ODR_DIV_400;
2382 break;
2383
2384 default:
2385 *val = LSM6DS3TR_C_XL_HP_NA;
2386 break;
2387 }
2388
2389 return ret;
2390 }
2391
2392 /**
2393 * @}
2394 *
2395 */
2396
2397 /**
2398 * @defgroup LSM6DS3TR_C_gyroscope_filters
2399 * @brief This section group all the functions concerning the filters
2400 * configuration that impact gyroscope.
2401 * @{
2402 *
2403 */
2404
2405 /**
2406 * @brief Gyroscope low pass path bandwidth.[set]
2407 *
2408 * @param ctx Read / write interface definitions
2409 * @param val gyroscope filtering chain configuration.
2410 * @retval Interface status (MANDATORY: return 0 -> no Error).
2411 *
2412 */
lsm6ds3tr_c_gy_band_pass_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_lpf1_sel_g_t val)2413 int32_t lsm6ds3tr_c_gy_band_pass_set(const stmdev_ctx_t *ctx,
2414 lsm6ds3tr_c_lpf1_sel_g_t val)
2415 {
2416 lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
2417 lsm6ds3tr_c_ctrl6_c_t ctrl6_c;
2418 lsm6ds3tr_c_ctrl7_g_t ctrl7_g;
2419 int32_t ret;
2420
2421 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G,
2422 (uint8_t *)&ctrl7_g, 1);
2423
2424 if (ret == 0)
2425 {
2426 ctrl7_g.hpm_g = ((uint8_t)val & 0x30U) >> 4;
2427 ctrl7_g.hp_en_g = ((uint8_t)val & 0x80U) >> 7;
2428 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL7_G,
2429 (uint8_t *)&ctrl7_g, 1);
2430
2431 if (ret == 0)
2432 {
2433 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C,
2434 (uint8_t *)&ctrl6_c, 1);
2435
2436 if (ret == 0)
2437 {
2438 ctrl6_c.ftype = (uint8_t)val & 0x03U;
2439 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL6_C,
2440 (uint8_t *)&ctrl6_c, 1);
2441
2442 if (ret == 0)
2443 {
2444 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
2445 (uint8_t *)&ctrl4_c, 1);
2446
2447 if (ret == 0)
2448 {
2449 ctrl4_c.lpf1_sel_g = ((uint8_t)val & 0x08U) >> 3;
2450 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C,
2451 (uint8_t *)&ctrl4_c, 1);
2452 }
2453 }
2454 }
2455 }
2456 }
2457
2458 return ret;
2459 }
2460
2461 /**
2462 * @brief Gyroscope low pass path bandwidth.[get]
2463 *
2464 * @param ctx Read / write interface definitions
2465 * @param val gyroscope filtering chain
2466 * @retval Interface status (MANDATORY: return 0 -> no Error).
2467 *
2468 */
lsm6ds3tr_c_gy_band_pass_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_lpf1_sel_g_t * val)2469 int32_t lsm6ds3tr_c_gy_band_pass_get(const stmdev_ctx_t *ctx,
2470 lsm6ds3tr_c_lpf1_sel_g_t *val)
2471 {
2472 lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
2473 lsm6ds3tr_c_ctrl6_c_t ctrl6_c;
2474 lsm6ds3tr_c_ctrl7_g_t ctrl7_g;
2475 int32_t ret;
2476
2477 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C,
2478 (uint8_t *)&ctrl6_c, 1);
2479
2480 if (ret == 0)
2481 {
2482 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
2483 (uint8_t *)&ctrl4_c, 1);
2484
2485 if (ret == 0)
2486 {
2487 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL7_G,
2488 (uint8_t *)&ctrl7_g, 1);
2489
2490 switch ((ctrl7_g.hp_en_g << 7) + (ctrl7_g.hpm_g << 4) +
2491 (ctrl4_c.lpf1_sel_g << 3) + ctrl6_c.ftype)
2492 {
2493 case LSM6DS3TR_C_HP_16mHz_LP2:
2494 *val = LSM6DS3TR_C_HP_16mHz_LP2;
2495 break;
2496
2497 case LSM6DS3TR_C_HP_65mHz_LP2:
2498 *val = LSM6DS3TR_C_HP_65mHz_LP2;
2499 break;
2500
2501 case LSM6DS3TR_C_HP_260mHz_LP2:
2502 *val = LSM6DS3TR_C_HP_260mHz_LP2;
2503 break;
2504
2505 case LSM6DS3TR_C_HP_1Hz04_LP2:
2506 *val = LSM6DS3TR_C_HP_1Hz04_LP2;
2507 break;
2508
2509 case LSM6DS3TR_C_HP_DISABLE_LP1_LIGHT:
2510 *val = LSM6DS3TR_C_HP_DISABLE_LP1_LIGHT;
2511 break;
2512
2513 case LSM6DS3TR_C_HP_DISABLE_LP1_NORMAL:
2514 *val = LSM6DS3TR_C_HP_DISABLE_LP1_NORMAL;
2515 break;
2516
2517 case LSM6DS3TR_C_HP_DISABLE_LP_STRONG:
2518 *val = LSM6DS3TR_C_HP_DISABLE_LP_STRONG;
2519 break;
2520
2521 case LSM6DS3TR_C_HP_DISABLE_LP1_AGGRESSIVE:
2522 *val = LSM6DS3TR_C_HP_DISABLE_LP1_AGGRESSIVE;
2523 break;
2524
2525 case LSM6DS3TR_C_HP_16mHz_LP1_LIGHT:
2526 *val = LSM6DS3TR_C_HP_16mHz_LP1_LIGHT;
2527 break;
2528
2529 case LSM6DS3TR_C_HP_65mHz_LP1_NORMAL:
2530 *val = LSM6DS3TR_C_HP_65mHz_LP1_NORMAL;
2531 break;
2532
2533 case LSM6DS3TR_C_HP_260mHz_LP1_STRONG:
2534 *val = LSM6DS3TR_C_HP_260mHz_LP1_STRONG;
2535 break;
2536
2537 case LSM6DS3TR_C_HP_1Hz04_LP1_AGGRESSIVE:
2538 *val = LSM6DS3TR_C_HP_1Hz04_LP1_AGGRESSIVE;
2539 break;
2540
2541 default:
2542 *val = LSM6DS3TR_C_HP_GY_BAND_NA;
2543 break;
2544 }
2545 }
2546 }
2547
2548 return ret;
2549 }
2550
2551 /**
2552 * @}
2553 *
2554 */
2555
2556 /**
2557 * @defgroup LSM6DS3TR_C_serial_interface
2558 * @brief This section groups all the functions concerning serial
2559 * interface management
2560 * @{
2561 *
2562 */
2563
2564 /**
2565 * @brief SPI Serial Interface Mode selection.[set]
2566 *
2567 * @param ctx Read / write interface definitions
2568 * @param val Change the values of sim in reg CTRL3_C
2569 * @retval Interface status (MANDATORY: return 0 -> no Error).
2570 *
2571 */
lsm6ds3tr_c_spi_mode_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_sim_t val)2572 int32_t lsm6ds3tr_c_spi_mode_set(const stmdev_ctx_t *ctx,
2573 lsm6ds3tr_c_sim_t val)
2574 {
2575 lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
2576 int32_t ret;
2577
2578 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
2579 (uint8_t *)&ctrl3_c, 1);
2580
2581 if (ret == 0)
2582 {
2583 ctrl3_c.sim = (uint8_t) val;
2584 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C,
2585 (uint8_t *)&ctrl3_c, 1);
2586 }
2587
2588 return ret;
2589 }
2590
2591 /**
2592 * @brief SPI Serial Interface Mode selection.[get]
2593 *
2594 * @param ctx Read / write interface definitions
2595 * @param val Get the values of sim in reg CTRL3_C
2596 * @retval Interface status (MANDATORY: return 0 -> no Error).
2597 *
2598 */
lsm6ds3tr_c_spi_mode_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_sim_t * val)2599 int32_t lsm6ds3tr_c_spi_mode_get(const stmdev_ctx_t *ctx,
2600 lsm6ds3tr_c_sim_t *val)
2601 {
2602 lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
2603 int32_t ret;
2604
2605 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
2606 (uint8_t *)&ctrl3_c, 1);
2607
2608 switch (ctrl3_c.sim)
2609 {
2610 case LSM6DS3TR_C_SPI_4_WIRE:
2611 *val = LSM6DS3TR_C_SPI_4_WIRE;
2612 break;
2613
2614 case LSM6DS3TR_C_SPI_3_WIRE:
2615 *val = LSM6DS3TR_C_SPI_3_WIRE;
2616 break;
2617
2618 default:
2619 *val = LSM6DS3TR_C_SPI_MODE_ND;
2620 break;
2621 }
2622
2623 return ret;
2624 }
2625
2626 /**
2627 * @brief Disable / Enable I2C interface.[set]
2628 *
2629 * @param ctx Read / write interface definitions
2630 * @param val Change the values of i2c_disable in reg CTRL4_C
2631 * @retval Interface status (MANDATORY: return 0 -> no Error).
2632 *
2633 */
lsm6ds3tr_c_i2c_interface_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_i2c_disable_t val)2634 int32_t lsm6ds3tr_c_i2c_interface_set(const stmdev_ctx_t *ctx,
2635 lsm6ds3tr_c_i2c_disable_t val)
2636 {
2637 lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
2638 int32_t ret;
2639
2640 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
2641 (uint8_t *)&ctrl4_c, 1);
2642
2643 if (ret == 0)
2644 {
2645 ctrl4_c.i2c_disable = (uint8_t)val;
2646 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C,
2647 (uint8_t *)&ctrl4_c, 1);
2648 }
2649
2650 return ret;
2651 }
2652
2653 /**
2654 * @brief Disable / Enable I2C interface.[get]
2655 *
2656 * @param ctx Read / write interface definitions
2657 * @param val Get the values of i2c_disable in reg CTRL4_C
2658 * @retval Interface status (MANDATORY: return 0 -> no Error).
2659 *
2660 */
lsm6ds3tr_c_i2c_interface_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_i2c_disable_t * val)2661 int32_t lsm6ds3tr_c_i2c_interface_get(const stmdev_ctx_t *ctx,
2662 lsm6ds3tr_c_i2c_disable_t *val)
2663 {
2664 lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
2665 int32_t ret;
2666
2667 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
2668 (uint8_t *)&ctrl4_c, 1);
2669
2670 switch (ctrl4_c.i2c_disable)
2671 {
2672 case LSM6DS3TR_C_I2C_ENABLE:
2673 *val = LSM6DS3TR_C_I2C_ENABLE;
2674 break;
2675
2676 case LSM6DS3TR_C_I2C_DISABLE:
2677 *val = LSM6DS3TR_C_I2C_DISABLE;
2678 break;
2679
2680 default:
2681 *val = LSM6DS3TR_C_I2C_MODE_ND;
2682 break;
2683 }
2684
2685 return ret;
2686 }
2687
2688 /**
2689 * @}
2690 *
2691 */
2692
2693 /**
2694 * @defgroup LSM6DS3TR_C_interrupt_pins
2695 * @brief This section groups all the functions that manage
2696 * interrupt pins
2697 * @{
2698 *
2699 */
2700
2701 /**
2702 * @brief Select the signal that need to route on int1 pad[set]
2703 *
2704 * @param ctx Read / write interface definitions
2705 * @param val configure INT1_CTRL, MD1_CFG, CTRL4_C(den_drdy_int1),
2706 * MASTER_CONFIG(drdy_on_int1)
2707 * @retval Interface status (MANDATORY: return 0 -> no Error).
2708 *
2709 */
lsm6ds3tr_c_pin_int1_route_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_int1_route_t val)2710 int32_t lsm6ds3tr_c_pin_int1_route_set(const stmdev_ctx_t *ctx,
2711 lsm6ds3tr_c_int1_route_t val)
2712 {
2713 lsm6ds3tr_c_master_config_t master_config;
2714 lsm6ds3tr_c_int1_ctrl_t int1_ctrl;
2715 lsm6ds3tr_c_md1_cfg_t md1_cfg;
2716 lsm6ds3tr_c_md2_cfg_t md2_cfg;
2717 lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
2718 lsm6ds3tr_c_tap_cfg_t tap_cfg;
2719 int32_t ret;
2720
2721 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT1_CTRL,
2722 (uint8_t *)&int1_ctrl, 1);
2723
2724 if (ret == 0)
2725 {
2726 int1_ctrl.int1_drdy_xl = val.int1_drdy_xl;
2727 int1_ctrl.int1_drdy_g = val.int1_drdy_g;
2728 int1_ctrl.int1_boot = val.int1_boot;
2729 int1_ctrl.int1_fth = val.int1_fth;
2730 int1_ctrl.int1_fifo_ovr = val.int1_fifo_ovr;
2731 int1_ctrl.int1_full_flag = val.int1_full_flag;
2732 int1_ctrl.int1_sign_mot = val.int1_sign_mot;
2733 int1_ctrl.int1_step_detector = val.int1_step_detector;
2734 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT1_CTRL,
2735 (uint8_t *)&int1_ctrl, 1);
2736 }
2737
2738 if (ret == 0)
2739 {
2740 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD1_CFG,
2741 (uint8_t *)&md1_cfg, 1);
2742 }
2743
2744 if (ret == 0)
2745 {
2746 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD2_CFG,
2747 (uint8_t *)&md2_cfg, 1);
2748 }
2749
2750 if (ret == 0)
2751 {
2752 md1_cfg.int1_timer = val.int1_timer;
2753 md1_cfg.int1_tilt = val.int1_tilt;
2754 md1_cfg.int1_6d = val.int1_6d;
2755 md1_cfg.int1_double_tap = val.int1_double_tap;
2756 md1_cfg.int1_ff = val.int1_ff;
2757 md1_cfg.int1_wu = val.int1_wu;
2758 md1_cfg.int1_single_tap = val.int1_single_tap;
2759 md1_cfg.int1_inact_state = val.int1_inact_state;
2760 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MD1_CFG,
2761 (uint8_t *)&md1_cfg, 1);
2762 }
2763
2764 if (ret == 0)
2765 {
2766 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
2767 (uint8_t *)&ctrl4_c, 1);
2768 }
2769
2770 if (ret == 0)
2771 {
2772 ctrl4_c.den_drdy_int1 = val.den_drdy_int1;
2773 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C,
2774 (uint8_t *)&ctrl4_c, 1);
2775 }
2776
2777 if (ret == 0)
2778 {
2779 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
2780 (uint8_t *)&master_config, 1);
2781 }
2782
2783 if (ret == 0)
2784 {
2785 master_config.drdy_on_int1 = val.den_drdy_int1;
2786 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
2787 (uint8_t *)&master_config, 1);
2788 }
2789
2790 if (ret == 0)
2791 {
2792 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
2793 (uint8_t *)&tap_cfg, 1);
2794
2795 if ((val.int1_6d != 0x00U) ||
2796 (val.int1_ff != 0x00U) ||
2797 (val.int1_wu != 0x00U) ||
2798 (val.int1_single_tap != 0x00U) ||
2799 (val.int1_double_tap != 0x00U) ||
2800 (val.int1_inact_state != 0x00U) ||
2801 (md2_cfg.int2_6d != 0x00U) ||
2802 (md2_cfg.int2_ff != 0x00U) ||
2803 (md2_cfg.int2_wu != 0x00U) ||
2804 (md2_cfg.int2_single_tap != 0x00U) ||
2805 (md2_cfg.int2_double_tap != 0x00U) ||
2806 (md2_cfg.int2_inact_state != 0x00U))
2807 {
2808 tap_cfg.interrupts_enable = PROPERTY_ENABLE;
2809 }
2810
2811 else
2812 {
2813 tap_cfg.interrupts_enable = PROPERTY_DISABLE;
2814 }
2815 }
2816
2817 if (ret == 0)
2818 {
2819 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG,
2820 (uint8_t *)&tap_cfg, 1);
2821 }
2822
2823 return ret;
2824 }
2825
2826 /**
2827 * @brief Select the signal that need to route on int1 pad[get]
2828 *
2829 * @param ctx Read / write interface definitions
2830 * @param val read INT1_CTRL, MD1_CFG, CTRL4_C(den_drdy_int1),
2831 * MASTER_CONFIG(drdy_on_int1)
2832 * @retval Interface status (MANDATORY: return 0 -> no Error).
2833 *
2834 */
lsm6ds3tr_c_pin_int1_route_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_int1_route_t * val)2835 int32_t lsm6ds3tr_c_pin_int1_route_get(const stmdev_ctx_t *ctx,
2836 lsm6ds3tr_c_int1_route_t *val)
2837 {
2838 lsm6ds3tr_c_master_config_t master_config;
2839 lsm6ds3tr_c_int1_ctrl_t int1_ctrl;
2840 lsm6ds3tr_c_md1_cfg_t md1_cfg;
2841 lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
2842 int32_t ret;
2843
2844 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT1_CTRL,
2845 (uint8_t *)&int1_ctrl, 1);
2846
2847 if (ret == 0)
2848 {
2849 val->int1_drdy_xl = int1_ctrl.int1_drdy_xl;
2850 val->int1_drdy_g = int1_ctrl.int1_drdy_g;
2851 val->int1_boot = int1_ctrl.int1_boot;
2852 val->int1_fth = int1_ctrl.int1_fth;
2853 val->int1_fifo_ovr = int1_ctrl.int1_fifo_ovr;
2854 val->int1_full_flag = int1_ctrl.int1_full_flag;
2855 val->int1_sign_mot = int1_ctrl.int1_sign_mot;
2856 val->int1_step_detector = int1_ctrl.int1_step_detector ;
2857 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD1_CFG,
2858 (uint8_t *)&md1_cfg, 1);
2859
2860 if (ret == 0)
2861 {
2862 val->int1_timer = md1_cfg.int1_timer;
2863 val->int1_tilt = md1_cfg.int1_tilt;
2864 val->int1_6d = md1_cfg.int1_6d;
2865 val->int1_double_tap = md1_cfg.int1_double_tap;
2866 val->int1_ff = md1_cfg.int1_ff;
2867 val->int1_wu = md1_cfg.int1_wu;
2868 val->int1_single_tap = md1_cfg.int1_single_tap;
2869 val->int1_inact_state = md1_cfg.int1_inact_state;
2870 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
2871 (uint8_t *)&ctrl4_c, 1);
2872
2873 if (ret == 0)
2874 {
2875 val->den_drdy_int1 = ctrl4_c.den_drdy_int1;
2876 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
2877 (uint8_t *)&master_config, 1);
2878 val->den_drdy_int1 = master_config.drdy_on_int1;
2879 }
2880 }
2881 }
2882
2883 return ret;
2884 }
2885
2886 /**
2887 * @brief Select the signal that need to route on int2 pad[set]
2888 *
2889 * @param ctx Read / write interface definitions
2890 * @param val INT2_CTRL, DRDY_PULSE_CFG(int2_wrist_tilt), MD2_CFG
2891 * @retval Interface status (MANDATORY: return 0 -> no Error).
2892 *
2893 */
lsm6ds3tr_c_pin_int2_route_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_int2_route_t val)2894 int32_t lsm6ds3tr_c_pin_int2_route_set(const stmdev_ctx_t *ctx,
2895 lsm6ds3tr_c_int2_route_t val)
2896 {
2897 lsm6ds3tr_c_int2_ctrl_t int2_ctrl;
2898 lsm6ds3tr_c_md1_cfg_t md1_cfg;
2899 lsm6ds3tr_c_md2_cfg_t md2_cfg;
2900 lsm6ds3tr_c_drdy_pulse_cfg_g_t drdy_pulse_cfg_g;
2901 lsm6ds3tr_c_tap_cfg_t tap_cfg;
2902 int32_t ret;
2903
2904 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT2_CTRL,
2905 (uint8_t *)&int2_ctrl, 1);
2906
2907 if (ret == 0)
2908 {
2909 int2_ctrl.int2_drdy_xl = val.int2_drdy_xl;
2910 int2_ctrl.int2_drdy_g = val.int2_drdy_g;
2911 int2_ctrl.int2_drdy_temp = val.int2_drdy_temp;
2912 int2_ctrl.int2_fth = val.int2_fth;
2913 int2_ctrl.int2_fifo_ovr = val.int2_fifo_ovr;
2914 int2_ctrl.int2_full_flag = val.int2_full_flag;
2915 int2_ctrl.int2_step_count_ov = val.int2_step_count_ov;
2916 int2_ctrl.int2_step_delta = val.int2_step_delta;
2917 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT2_CTRL,
2918 (uint8_t *)&int2_ctrl, 1);
2919 }
2920
2921 if (ret == 0)
2922 {
2923 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD1_CFG,
2924 (uint8_t *)&md1_cfg, 1);
2925 }
2926
2927 if (ret == 0)
2928 {
2929 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD2_CFG,
2930 (uint8_t *)&md2_cfg, 1);
2931 }
2932
2933 if (ret == 0)
2934 {
2935 md2_cfg.int2_iron = val.int2_iron;
2936 md2_cfg.int2_tilt = val.int2_tilt;
2937 md2_cfg.int2_6d = val.int2_6d;
2938 md2_cfg.int2_double_tap = val.int2_double_tap;
2939 md2_cfg.int2_ff = val.int2_ff;
2940 md2_cfg.int2_wu = val.int2_wu;
2941 md2_cfg.int2_single_tap = val.int2_single_tap;
2942 md2_cfg.int2_inact_state = val.int2_inact_state;
2943 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MD2_CFG,
2944 (uint8_t *)&md2_cfg, 1);
2945 }
2946
2947 if (ret == 0)
2948 {
2949 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G,
2950 (uint8_t *)&drdy_pulse_cfg_g, 1);
2951 }
2952
2953 if (ret == 0)
2954 {
2955 drdy_pulse_cfg_g.int2_wrist_tilt = val.int2_wrist_tilt;
2956 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G,
2957 (uint8_t *)&drdy_pulse_cfg_g, 1);
2958 }
2959
2960 if (ret == 0)
2961 {
2962 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
2963 (uint8_t *)&tap_cfg, 1);
2964
2965 if ((md1_cfg.int1_6d != 0x00U) ||
2966 (md1_cfg.int1_ff != 0x00U) ||
2967 (md1_cfg.int1_wu != 0x00U) ||
2968 (md1_cfg.int1_single_tap != 0x00U) ||
2969 (md1_cfg.int1_double_tap != 0x00U) ||
2970 (md1_cfg.int1_inact_state != 0x00U) ||
2971 (val.int2_6d != 0x00U) ||
2972 (val.int2_ff != 0x00U) ||
2973 (val.int2_wu != 0x00U) ||
2974 (val.int2_single_tap != 0x00U) ||
2975 (val.int2_double_tap != 0x00U) ||
2976 (val.int2_inact_state != 0x00U))
2977 {
2978 tap_cfg.interrupts_enable = PROPERTY_ENABLE;
2979 }
2980
2981 else
2982 {
2983 tap_cfg.interrupts_enable = PROPERTY_DISABLE;
2984 }
2985 }
2986
2987 if (ret == 0)
2988 {
2989 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG,
2990 (uint8_t *)&tap_cfg, 1);
2991 }
2992
2993 return ret;
2994 }
2995
2996 /**
2997 * @brief Select the signal that need to route on int2 pad[get]
2998 *
2999 * @param ctx Read / write interface definitions
3000 * @param val INT2_CTRL, DRDY_PULSE_CFG(int2_wrist_tilt), MD2_CFG
3001 * @retval Interface status (MANDATORY: return 0 -> no Error).
3002 *
3003 */
lsm6ds3tr_c_pin_int2_route_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_int2_route_t * val)3004 int32_t lsm6ds3tr_c_pin_int2_route_get(const stmdev_ctx_t *ctx,
3005 lsm6ds3tr_c_int2_route_t *val)
3006 {
3007 lsm6ds3tr_c_int2_ctrl_t int2_ctrl;
3008 lsm6ds3tr_c_md2_cfg_t md2_cfg;
3009 lsm6ds3tr_c_drdy_pulse_cfg_g_t drdy_pulse_cfg_g;
3010 int32_t ret;
3011
3012 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT2_CTRL,
3013 (uint8_t *)&int2_ctrl, 1);
3014
3015 if (ret == 0)
3016 {
3017 val->int2_drdy_xl = int2_ctrl.int2_drdy_xl;
3018 val->int2_drdy_g = int2_ctrl.int2_drdy_g;
3019 val->int2_drdy_temp = int2_ctrl.int2_drdy_temp;
3020 val->int2_fth = int2_ctrl.int2_fth;
3021 val->int2_fifo_ovr = int2_ctrl.int2_fifo_ovr;
3022 val->int2_full_flag = int2_ctrl.int2_full_flag;
3023 val->int2_step_count_ov = int2_ctrl.int2_step_count_ov;
3024 val->int2_step_delta = int2_ctrl.int2_step_delta;
3025 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MD2_CFG,
3026 (uint8_t *)&md2_cfg, 1);
3027
3028 if (ret == 0)
3029 {
3030 val->int2_iron = md2_cfg.int2_iron;
3031 val->int2_tilt = md2_cfg.int2_tilt;
3032 val->int2_6d = md2_cfg.int2_6d;
3033 val->int2_double_tap = md2_cfg.int2_double_tap;
3034 val->int2_ff = md2_cfg.int2_ff;
3035 val->int2_wu = md2_cfg.int2_wu;
3036 val->int2_single_tap = md2_cfg.int2_single_tap;
3037 val->int2_inact_state = md2_cfg.int2_inact_state;
3038 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_DRDY_PULSE_CFG_G,
3039 (uint8_t *)&drdy_pulse_cfg_g, 1);
3040 val->int2_wrist_tilt = drdy_pulse_cfg_g.int2_wrist_tilt;
3041 }
3042 }
3043
3044 return ret;
3045 }
3046
3047 /**
3048 * @brief Push-pull/open drain selection on interrupt pads.[set]
3049 *
3050 * @param ctx Read / write interface definitions
3051 * @param val Change the values of pp_od in reg CTRL3_C
3052 * @retval Interface status (MANDATORY: return 0 -> no Error).
3053 *
3054 */
lsm6ds3tr_c_pin_mode_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_pp_od_t val)3055 int32_t lsm6ds3tr_c_pin_mode_set(const stmdev_ctx_t *ctx,
3056 lsm6ds3tr_c_pp_od_t val)
3057 {
3058 lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
3059 int32_t ret;
3060
3061 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
3062 (uint8_t *)&ctrl3_c, 1);
3063
3064 if (ret == 0)
3065 {
3066 ctrl3_c.pp_od = (uint8_t) val;
3067 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C,
3068 (uint8_t *)&ctrl3_c, 1);
3069 }
3070
3071 return ret;
3072 }
3073
3074 /**
3075 * @brief Push-pull/open drain selection on interrupt pads.[get]
3076 *
3077 * @param ctx Read / write interface definitions
3078 * @param val Get the values of pp_od in reg CTRL3_C
3079 * @retval Interface status (MANDATORY: return 0 -> no Error).
3080 *
3081 */
lsm6ds3tr_c_pin_mode_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_pp_od_t * val)3082 int32_t lsm6ds3tr_c_pin_mode_get(const stmdev_ctx_t *ctx,
3083 lsm6ds3tr_c_pp_od_t *val)
3084 {
3085 lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
3086 int32_t ret;
3087
3088 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
3089 (uint8_t *)&ctrl3_c, 1);
3090
3091 switch (ctrl3_c.pp_od)
3092 {
3093 case LSM6DS3TR_C_PUSH_PULL:
3094 *val = LSM6DS3TR_C_PUSH_PULL;
3095 break;
3096
3097 case LSM6DS3TR_C_OPEN_DRAIN:
3098 *val = LSM6DS3TR_C_OPEN_DRAIN;
3099 break;
3100
3101 default:
3102 *val = LSM6DS3TR_C_PIN_MODE_ND;
3103 break;
3104 }
3105
3106 return ret;
3107 }
3108
3109 /**
3110 * @brief Interrupt active-high/low.[set]
3111 *
3112 * @param ctx Read / write interface definitions
3113 * @param val Change the values of h_lactive in reg CTRL3_C
3114 * @retval Interface status (MANDATORY: return 0 -> no Error).
3115 *
3116 */
lsm6ds3tr_c_pin_polarity_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_h_lactive_t val)3117 int32_t lsm6ds3tr_c_pin_polarity_set(const stmdev_ctx_t *ctx,
3118 lsm6ds3tr_c_h_lactive_t val)
3119 {
3120 lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
3121 int32_t ret;
3122
3123 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
3124 (uint8_t *)&ctrl3_c, 1);
3125
3126 if (ret == 0)
3127 {
3128 ctrl3_c.h_lactive = (uint8_t) val;
3129 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL3_C,
3130 (uint8_t *)&ctrl3_c, 1);
3131 }
3132
3133 return ret;
3134 }
3135
3136 /**
3137 * @brief Interrupt active-high/low.[get]
3138 *
3139 * @param ctx Read / write interface definitions
3140 * @param val Get the values of h_lactive in reg CTRL3_C
3141 * @retval Interface status (MANDATORY: return 0 -> no Error).
3142 *
3143 */
lsm6ds3tr_c_pin_polarity_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_h_lactive_t * val)3144 int32_t lsm6ds3tr_c_pin_polarity_get(const stmdev_ctx_t *ctx,
3145 lsm6ds3tr_c_h_lactive_t *val)
3146 {
3147 lsm6ds3tr_c_ctrl3_c_t ctrl3_c;
3148 int32_t ret;
3149
3150 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL3_C,
3151 (uint8_t *)&ctrl3_c, 1);
3152
3153 switch (ctrl3_c.h_lactive)
3154 {
3155 case LSM6DS3TR_C_ACTIVE_HIGH:
3156 *val = LSM6DS3TR_C_ACTIVE_HIGH;
3157 break;
3158
3159 case LSM6DS3TR_C_ACTIVE_LOW:
3160 *val = LSM6DS3TR_C_ACTIVE_LOW;
3161 break;
3162
3163 default:
3164 *val = LSM6DS3TR_C_POLARITY_ND;
3165 break;
3166 }
3167
3168 return ret;
3169 }
3170
3171 /**
3172 * @brief All interrupt signals become available on INT1 pin.[set]
3173 *
3174 * @param ctx Read / write interface definitions
3175 * @param val Change the values of int2_on_int1 in reg CTRL4_C
3176 * @retval Interface status (MANDATORY: return 0 -> no Error).
3177 *
3178 */
lsm6ds3tr_c_all_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)3179 int32_t lsm6ds3tr_c_all_on_int1_set(const stmdev_ctx_t *ctx, uint8_t val)
3180 {
3181 lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
3182 int32_t ret;
3183
3184 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
3185 (uint8_t *)&ctrl4_c, 1);
3186
3187 if (ret == 0)
3188 {
3189 ctrl4_c.int2_on_int1 = val;
3190 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C,
3191 (uint8_t *)&ctrl4_c, 1);
3192 }
3193
3194 return ret;
3195 }
3196
3197 /**
3198 * @brief All interrupt signals become available on INT1 pin.[get]
3199 *
3200 * @param ctx Read / write interface definitions
3201 * @param val Change the values of int2_on_int1 in reg CTRL4_C
3202 * @retval Interface status (MANDATORY: return 0 -> no Error).
3203 *
3204 */
lsm6ds3tr_c_all_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)3205 int32_t lsm6ds3tr_c_all_on_int1_get(const stmdev_ctx_t *ctx, uint8_t *val)
3206 {
3207 lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
3208 int32_t ret;
3209
3210 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
3211 (uint8_t *)&ctrl4_c, 1);
3212 *val = ctrl4_c.int2_on_int1;
3213
3214 return ret;
3215 }
3216
3217 /**
3218 * @brief Latched/pulsed interrupt.[set]
3219 *
3220 * @param ctx Read / write interface definitions
3221 * @param val Change the values of lir in reg TAP_CFG
3222 * @retval Interface status (MANDATORY: return 0 -> no Error).
3223 *
3224 */
lsm6ds3tr_c_int_notification_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_lir_t val)3225 int32_t lsm6ds3tr_c_int_notification_set(const stmdev_ctx_t *ctx,
3226 lsm6ds3tr_c_lir_t val)
3227 {
3228 lsm6ds3tr_c_tap_cfg_t tap_cfg;
3229 int32_t ret;
3230
3231 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
3232 (uint8_t *)&tap_cfg, 1);
3233
3234 if (ret == 0)
3235 {
3236 tap_cfg.lir = (uint8_t) val;
3237 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG,
3238 (uint8_t *)&tap_cfg, 1);
3239 }
3240
3241 return ret;
3242 }
3243
3244 /**
3245 * @brief Latched/pulsed interrupt.[get]
3246 *
3247 * @param ctx Read / write interface definitions
3248 * @param val Get the values of lir in reg TAP_CFG
3249 * @retval Interface status (MANDATORY: return 0 -> no Error).
3250 *
3251 */
lsm6ds3tr_c_int_notification_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_lir_t * val)3252 int32_t lsm6ds3tr_c_int_notification_get(const stmdev_ctx_t *ctx,
3253 lsm6ds3tr_c_lir_t *val)
3254 {
3255 lsm6ds3tr_c_tap_cfg_t tap_cfg;
3256 int32_t ret;
3257
3258 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
3259 (uint8_t *)&tap_cfg, 1);
3260
3261 switch (tap_cfg.lir)
3262 {
3263 case LSM6DS3TR_C_INT_PULSED:
3264 *val = LSM6DS3TR_C_INT_PULSED;
3265 break;
3266
3267 case LSM6DS3TR_C_INT_LATCHED:
3268 *val = LSM6DS3TR_C_INT_LATCHED;
3269 break;
3270
3271 default:
3272 *val = LSM6DS3TR_C_INT_MODE;
3273 break;
3274 }
3275
3276 return ret;
3277 }
3278
3279 /**
3280 * @}
3281 *
3282 */
3283
3284 /**
3285 * @defgroup LSM6DS3TR_C_Wake_Up_event
3286 * @brief This section groups all the functions that manage the
3287 * Wake Up event generation.
3288 * @{
3289 *
3290 */
3291
3292 /**
3293 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[set]
3294 *
3295 * @param ctx Read / write interface definitions
3296 * @param val Change the values of wk_ths in reg WAKE_UP_THS
3297 * @retval Interface status (MANDATORY: return 0 -> no Error).
3298 *
3299 */
lsm6ds3tr_c_wkup_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)3300 int32_t lsm6ds3tr_c_wkup_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
3301 {
3302 lsm6ds3tr_c_wake_up_ths_t wake_up_ths;
3303 int32_t ret;
3304
3305 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS,
3306 (uint8_t *)&wake_up_ths, 1);
3307
3308 if (ret == 0)
3309 {
3310 wake_up_ths.wk_ths = val;
3311 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS,
3312 (uint8_t *)&wake_up_ths, 1);
3313 }
3314
3315 return ret;
3316 }
3317
3318 /**
3319 * @brief Threshold for wakeup.1 LSB = FS_XL / 64.[get]
3320 *
3321 * @param ctx Read / write interface definitions
3322 * @param val Change the values of wk_ths in reg WAKE_UP_THS
3323 * @retval Interface status (MANDATORY: return 0 -> no Error).
3324 *
3325 */
lsm6ds3tr_c_wkup_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)3326 int32_t lsm6ds3tr_c_wkup_threshold_get(const stmdev_ctx_t *ctx,
3327 uint8_t *val)
3328 {
3329 lsm6ds3tr_c_wake_up_ths_t wake_up_ths;
3330 int32_t ret;
3331
3332 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS,
3333 (uint8_t *)&wake_up_ths, 1);
3334 *val = wake_up_ths.wk_ths;
3335
3336 return ret;
3337 }
3338
3339 /**
3340 * @brief Wake up duration event.1LSb = 1 / ODR[set]
3341 *
3342 * @param ctx Read / write interface definitions
3343 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
3344 * @retval Interface status (MANDATORY: return 0 -> no Error).
3345 *
3346 */
lsm6ds3tr_c_wkup_dur_set(const stmdev_ctx_t * ctx,uint8_t val)3347 int32_t lsm6ds3tr_c_wkup_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
3348 {
3349 lsm6ds3tr_c_wake_up_dur_t wake_up_dur;
3350 int32_t ret;
3351
3352 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
3353 (uint8_t *)&wake_up_dur, 1);
3354
3355 if (ret == 0)
3356 {
3357 wake_up_dur.wake_dur = val;
3358 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
3359 (uint8_t *)&wake_up_dur, 1);
3360 }
3361
3362 return ret;
3363 }
3364
3365 /**
3366 * @brief Wake up duration event.1LSb = 1 / ODR[get]
3367 *
3368 * @param ctx Read / write interface definitions
3369 * @param val Change the values of wake_dur in reg WAKE_UP_DUR
3370 * @retval Interface status (MANDATORY: return 0 -> no Error).
3371 *
3372 */
lsm6ds3tr_c_wkup_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)3373 int32_t lsm6ds3tr_c_wkup_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
3374 {
3375 lsm6ds3tr_c_wake_up_dur_t wake_up_dur;
3376 int32_t ret;
3377
3378 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
3379 (uint8_t *)&wake_up_dur, 1);
3380 *val = wake_up_dur.wake_dur;
3381
3382 return ret;
3383 }
3384
3385 /**
3386 * @}
3387 *
3388 */
3389
3390 /**
3391 * @defgroup LSM6DS3TR_C_Activity/Inactivity_detection
3392 * @brief This section groups all the functions concerning
3393 * activity/inactivity detection.
3394 * @{
3395 *
3396 */
3397
3398 /**
3399 * @brief Enables gyroscope Sleep mode.[set]
3400 *
3401 * @param ctx Read / write interface definitions
3402 * @param val Change the values of sleep in reg CTRL4_C
3403 * @retval Interface status (MANDATORY: return 0 -> no Error).
3404 *
3405 */
lsm6ds3tr_c_gy_sleep_mode_set(const stmdev_ctx_t * ctx,uint8_t val)3406 int32_t lsm6ds3tr_c_gy_sleep_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
3407 {
3408 lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
3409 int32_t ret;
3410
3411 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
3412 (uint8_t *)&ctrl4_c, 1);
3413
3414 if (ret == 0)
3415 {
3416 ctrl4_c.sleep = val;
3417 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C,
3418 (uint8_t *)&ctrl4_c, 1);
3419 }
3420
3421 return ret;
3422 }
3423
3424 /**
3425 * @brief Enables gyroscope Sleep mode.[get]
3426 *
3427 * @param ctx Read / write interface definitions
3428 * @param val Change the values of sleep in reg CTRL4_C
3429 * @retval Interface status (MANDATORY: return 0 -> no Error).
3430 *
3431 */
lsm6ds3tr_c_gy_sleep_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)3432 int32_t lsm6ds3tr_c_gy_sleep_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
3433 {
3434 lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
3435 int32_t ret;
3436
3437 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
3438 (uint8_t *)&ctrl4_c, 1);
3439 *val = ctrl4_c.sleep;
3440
3441 return ret;
3442 }
3443
3444 /**
3445 * @brief Enable inactivity function.[set]
3446 *
3447 * @param ctx Read / write interface definitions
3448 * @param val Change the values of inact_en in reg TAP_CFG
3449 * @retval Interface status (MANDATORY: return 0 -> no Error).
3450 *
3451 */
lsm6ds3tr_c_act_mode_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_inact_en_t val)3452 int32_t lsm6ds3tr_c_act_mode_set(const stmdev_ctx_t *ctx,
3453 lsm6ds3tr_c_inact_en_t val)
3454 {
3455 lsm6ds3tr_c_tap_cfg_t tap_cfg;
3456 int32_t ret;
3457
3458 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
3459 (uint8_t *)&tap_cfg, 1);
3460
3461 if (ret == 0)
3462 {
3463 tap_cfg.inact_en = (uint8_t) val;
3464 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG,
3465 (uint8_t *)&tap_cfg, 1);
3466 }
3467
3468 return ret;
3469 }
3470
3471 /**
3472 * @brief Enable inactivity function.[get]
3473 *
3474 * @param ctx Read / write interface definitions
3475 * @param val Get the values of inact_en in reg TAP_CFG
3476 * @retval Interface status (MANDATORY: return 0 -> no Error).
3477 *
3478 */
lsm6ds3tr_c_act_mode_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_inact_en_t * val)3479 int32_t lsm6ds3tr_c_act_mode_get(const stmdev_ctx_t *ctx,
3480 lsm6ds3tr_c_inact_en_t *val)
3481 {
3482 lsm6ds3tr_c_tap_cfg_t tap_cfg;
3483 int32_t ret;
3484
3485 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
3486 (uint8_t *)&tap_cfg, 1);
3487
3488 switch (tap_cfg.inact_en)
3489 {
3490 case LSM6DS3TR_C_PROPERTY_DISABLE:
3491 *val = LSM6DS3TR_C_PROPERTY_DISABLE;
3492 break;
3493
3494 case LSM6DS3TR_C_XL_12Hz5_GY_NOT_AFFECTED:
3495 *val = LSM6DS3TR_C_XL_12Hz5_GY_NOT_AFFECTED;
3496 break;
3497
3498 case LSM6DS3TR_C_XL_12Hz5_GY_SLEEP:
3499 *val = LSM6DS3TR_C_XL_12Hz5_GY_SLEEP;
3500 break;
3501
3502 case LSM6DS3TR_C_XL_12Hz5_GY_PD:
3503 *val = LSM6DS3TR_C_XL_12Hz5_GY_PD;
3504 break;
3505
3506 default:
3507 *val = LSM6DS3TR_C_ACT_MODE_ND;
3508 break;
3509 }
3510
3511 return ret;
3512 }
3513
3514 /**
3515 * @brief Duration to go in sleep mode.1 LSb = 512 / ODR[set]
3516 *
3517 * @param ctx Read / write interface definitions
3518 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
3519 * @retval Interface status (MANDATORY: return 0 -> no Error).
3520 *
3521 */
lsm6ds3tr_c_act_sleep_dur_set(const stmdev_ctx_t * ctx,uint8_t val)3522 int32_t lsm6ds3tr_c_act_sleep_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
3523 {
3524 lsm6ds3tr_c_wake_up_dur_t wake_up_dur;
3525 int32_t ret;
3526
3527 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
3528 (uint8_t *)&wake_up_dur, 1);
3529
3530 if (ret == 0)
3531 {
3532 wake_up_dur.sleep_dur = val;
3533 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
3534 (uint8_t *)&wake_up_dur, 1);
3535 }
3536
3537 return ret;
3538 }
3539
3540 /**
3541 * @brief Duration to go in sleep mode. 1 LSb = 512 / ODR[get]
3542 *
3543 * @param ctx Read / write interface definitions
3544 * @param val Change the values of sleep_dur in reg WAKE_UP_DUR
3545 * @retval Interface status (MANDATORY: return 0 -> no Error).
3546 *
3547 */
lsm6ds3tr_c_act_sleep_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)3548 int32_t lsm6ds3tr_c_act_sleep_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
3549 {
3550 lsm6ds3tr_c_wake_up_dur_t wake_up_dur;
3551 int32_t ret;
3552
3553 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
3554 (uint8_t *)&wake_up_dur, 1);
3555 *val = wake_up_dur.sleep_dur;
3556
3557 return ret;
3558 }
3559
3560 /**
3561 * @}
3562 *
3563 */
3564
3565 /**
3566 * @defgroup LSM6DS3TR_C_tap_generator
3567 * @brief This section groups all the functions that manage the
3568 * tap and double tap event generation.
3569 * @{
3570 *
3571 */
3572
3573 /**
3574 * @brief Read the tap / double tap source register.[get]
3575 *
3576 * @param ctx Read / write interface definitions
3577 * @param val Structure of registers from TAP_SRC
3578 * @retval Interface status (MANDATORY: return 0 -> no Error).
3579 *
3580 */
lsm6ds3tr_c_tap_src_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_tap_src_t * val)3581 int32_t lsm6ds3tr_c_tap_src_get(const stmdev_ctx_t *ctx,
3582 lsm6ds3tr_c_tap_src_t *val)
3583 {
3584 int32_t ret;
3585
3586 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_SRC, (uint8_t *) val, 1);
3587
3588 return ret;
3589 }
3590
3591 /**
3592 * @brief Enable Z direction in tap recognition.[set]
3593 *
3594 * @param ctx Read / write interface definitions
3595 * @param val Change the values of tap_z_en in reg TAP_CFG
3596 *
3597 */
lsm6ds3tr_c_tap_detection_on_z_set(const stmdev_ctx_t * ctx,uint8_t val)3598 int32_t lsm6ds3tr_c_tap_detection_on_z_set(const stmdev_ctx_t *ctx,
3599 uint8_t val)
3600 {
3601 lsm6ds3tr_c_tap_cfg_t tap_cfg;
3602 int32_t ret;
3603
3604 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
3605 (uint8_t *)&tap_cfg, 1);
3606
3607 if (ret == 0)
3608 {
3609 tap_cfg.tap_z_en = val;
3610 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG,
3611 (uint8_t *)&tap_cfg, 1);
3612 }
3613
3614 return ret;
3615 }
3616
3617 /**
3618 * @brief Enable Z direction in tap recognition.[get]
3619 *
3620 * @param ctx Read / write interface definitions
3621 * @param val Change the values of tap_z_en in reg TAP_CFG
3622 * @retval Interface status (MANDATORY: return 0 -> no Error).
3623 *
3624 */
lsm6ds3tr_c_tap_detection_on_z_get(const stmdev_ctx_t * ctx,uint8_t * val)3625 int32_t lsm6ds3tr_c_tap_detection_on_z_get(const stmdev_ctx_t *ctx,
3626 uint8_t *val)
3627 {
3628 lsm6ds3tr_c_tap_cfg_t tap_cfg;
3629 int32_t ret;
3630
3631 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
3632 (uint8_t *)&tap_cfg, 1);
3633 *val = tap_cfg.tap_z_en;
3634
3635 return ret;
3636 }
3637
3638 /**
3639 * @brief Enable Y direction in tap recognition.[set]
3640 *
3641 * @param ctx Read / write interface definitions
3642 * @param val Change the values of tap_y_en in reg TAP_CFG
3643 * @retval Interface status (MANDATORY: return 0 -> no Error).
3644 *
3645 */
lsm6ds3tr_c_tap_detection_on_y_set(const stmdev_ctx_t * ctx,uint8_t val)3646 int32_t lsm6ds3tr_c_tap_detection_on_y_set(const stmdev_ctx_t *ctx,
3647 uint8_t val)
3648 {
3649 lsm6ds3tr_c_tap_cfg_t tap_cfg;
3650 int32_t ret;
3651
3652 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
3653 (uint8_t *)&tap_cfg, 1);
3654
3655 if (ret == 0)
3656 {
3657 tap_cfg.tap_y_en = val;
3658 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG,
3659 (uint8_t *)&tap_cfg, 1);
3660 }
3661
3662 return ret;
3663 }
3664
3665 /**
3666 * @brief Enable Y direction in tap recognition.[get]
3667 *
3668 * @param ctx Read / write interface definitions
3669 * @param val Change the values of tap_y_en in reg TAP_CFG
3670 * @retval Interface status (MANDATORY: return 0 -> no Error).
3671 *
3672 */
lsm6ds3tr_c_tap_detection_on_y_get(const stmdev_ctx_t * ctx,uint8_t * val)3673 int32_t lsm6ds3tr_c_tap_detection_on_y_get(const stmdev_ctx_t *ctx,
3674 uint8_t *val)
3675 {
3676 lsm6ds3tr_c_tap_cfg_t tap_cfg;
3677 int32_t ret;
3678
3679 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
3680 (uint8_t *)&tap_cfg, 1);
3681 *val = tap_cfg.tap_y_en;
3682
3683 return ret;
3684 }
3685
3686 /**
3687 * @brief Enable X direction in tap recognition.[set]
3688 *
3689 * @param ctx Read / write interface definitions
3690 * @param val Change the values of tap_x_en in reg TAP_CFG
3691 * @retval Interface status (MANDATORY: return 0 -> no Error).
3692 *
3693 */
lsm6ds3tr_c_tap_detection_on_x_set(const stmdev_ctx_t * ctx,uint8_t val)3694 int32_t lsm6ds3tr_c_tap_detection_on_x_set(const stmdev_ctx_t *ctx,
3695 uint8_t val)
3696 {
3697 lsm6ds3tr_c_tap_cfg_t tap_cfg;
3698 int32_t ret;
3699
3700 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
3701 (uint8_t *)&tap_cfg, 1);
3702
3703 if (ret == 0)
3704 {
3705 tap_cfg.tap_x_en = val;
3706 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_CFG,
3707 (uint8_t *)&tap_cfg, 1);
3708 }
3709
3710 return ret;
3711 }
3712
3713 /**
3714 * @brief Enable X direction in tap recognition.[get]
3715 *
3716 * @param ctx Read / write interface definitions
3717 * @param val Change the values of tap_x_en in reg TAP_CFG
3718 * @retval Interface status (MANDATORY: return 0 -> no Error).
3719 *
3720 */
lsm6ds3tr_c_tap_detection_on_x_get(const stmdev_ctx_t * ctx,uint8_t * val)3721 int32_t lsm6ds3tr_c_tap_detection_on_x_get(const stmdev_ctx_t *ctx,
3722 uint8_t *val)
3723 {
3724 lsm6ds3tr_c_tap_cfg_t tap_cfg;
3725 int32_t ret;
3726
3727 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_CFG,
3728 (uint8_t *)&tap_cfg, 1);
3729 *val = tap_cfg.tap_x_en;
3730
3731 return ret;
3732 }
3733
3734 /**
3735 * @brief Threshold for tap recognition.[set]
3736 *
3737 * @param ctx Read / write interface definitions
3738 * @param val Change the values of tap_ths in reg TAP_THS_6D
3739 * @retval Interface status (MANDATORY: return 0 -> no Error).
3740 *
3741 */
lsm6ds3tr_c_tap_threshold_x_set(const stmdev_ctx_t * ctx,uint8_t val)3742 int32_t lsm6ds3tr_c_tap_threshold_x_set(const stmdev_ctx_t *ctx,
3743 uint8_t val)
3744 {
3745 lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d;
3746 int32_t ret;
3747
3748 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D,
3749 (uint8_t *)&tap_ths_6d, 1);
3750
3751 if (ret == 0)
3752 {
3753 tap_ths_6d.tap_ths = val;
3754 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_THS_6D,
3755 (uint8_t *)&tap_ths_6d, 1);
3756 }
3757
3758 return ret;
3759 }
3760
3761 /**
3762 * @brief Threshold for tap recognition.[get]
3763 *
3764 * @param ctx Read / write interface definitions
3765 * @param val Change the values of tap_ths in reg TAP_THS_6D
3766 * @retval Interface status (MANDATORY: return 0 -> no Error).
3767 *
3768 */
lsm6ds3tr_c_tap_threshold_x_get(const stmdev_ctx_t * ctx,uint8_t * val)3769 int32_t lsm6ds3tr_c_tap_threshold_x_get(const stmdev_ctx_t *ctx,
3770 uint8_t *val)
3771 {
3772 lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d;
3773 int32_t ret;
3774
3775 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D,
3776 (uint8_t *)&tap_ths_6d, 1);
3777 *val = tap_ths_6d.tap_ths;
3778
3779 return ret;
3780 }
3781
3782 /**
3783 * @brief Maximum duration is the maximum time of an overthreshold signal
3784 * detection to be recognized as a tap event.
3785 * The default value of these bits is 00b which corresponds to
3786 * 4*ODR_XL time.
3787 * If the SHOCK[1:0] bits are set to a different
3788 * value, 1LSB corresponds to 8*ODR_XL time.[set]
3789 *
3790 * @param ctx Read / write interface definitions
3791 * @param val Change the values of shock in reg INT_DUR2
3792 * @retval Interface status (MANDATORY: return 0 -> no Error).
3793 *
3794 */
lsm6ds3tr_c_tap_shock_set(const stmdev_ctx_t * ctx,uint8_t val)3795 int32_t lsm6ds3tr_c_tap_shock_set(const stmdev_ctx_t *ctx, uint8_t val)
3796 {
3797 lsm6ds3tr_c_int_dur2_t int_dur2;
3798 int32_t ret;
3799
3800 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2,
3801 (uint8_t *)&int_dur2, 1);
3802
3803 if (ret == 0)
3804 {
3805 int_dur2.shock = val;
3806 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT_DUR2,
3807 (uint8_t *)&int_dur2, 1);
3808 }
3809
3810 return ret;
3811 }
3812
3813 /**
3814 * @brief Maximum duration is the maximum time of an overthreshold signal
3815 * detection to be recognized as a tap event.
3816 * The default value of these bits is 00b which corresponds to
3817 * 4*ODR_XL time.
3818 * If the SHOCK[1:0] bits are set to a different value, 1LSB
3819 * corresponds to 8*ODR_XL time.[get]
3820 *
3821 * @param ctx Read / write interface definitions
3822 * @param val Change the values of shock in reg INT_DUR2
3823 * @retval Interface status (MANDATORY: return 0 -> no Error).
3824 *
3825 */
lsm6ds3tr_c_tap_shock_get(const stmdev_ctx_t * ctx,uint8_t * val)3826 int32_t lsm6ds3tr_c_tap_shock_get(const stmdev_ctx_t *ctx, uint8_t *val)
3827 {
3828 lsm6ds3tr_c_int_dur2_t int_dur2;
3829 int32_t ret;
3830
3831 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2,
3832 (uint8_t *)&int_dur2, 1);
3833 *val = int_dur2.shock;
3834
3835 return ret;
3836 }
3837
3838 /**
3839 * @brief Quiet time is the time after the first detected tap in which there
3840 * must not be any overthreshold event.
3841 * The default value of these bits is 00b which corresponds to
3842 * 2*ODR_XL time.
3843 * If the QUIET[1:0] bits are set to a different value, 1LSB
3844 * corresponds to 4*ODR_XL time.[set]
3845 *
3846 * @param ctx Read / write interface definitions
3847 * @param val Change the values of quiet in reg INT_DUR2
3848 * @retval Interface status (MANDATORY: return 0 -> no Error).
3849 *
3850 */
lsm6ds3tr_c_tap_quiet_set(const stmdev_ctx_t * ctx,uint8_t val)3851 int32_t lsm6ds3tr_c_tap_quiet_set(const stmdev_ctx_t *ctx, uint8_t val)
3852 {
3853 lsm6ds3tr_c_int_dur2_t int_dur2;
3854 int32_t ret;
3855
3856 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2,
3857 (uint8_t *)&int_dur2, 1);
3858
3859 if (ret == 0)
3860 {
3861 int_dur2.quiet = val;
3862 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT_DUR2,
3863 (uint8_t *)&int_dur2, 1);
3864 }
3865
3866 return ret;
3867 }
3868
3869 /**
3870 * @brief Quiet time is the time after the first detected tap in which there
3871 * must not be any overthreshold event.
3872 * The default value of these bits is 00b which corresponds to
3873 * 2*ODR_XL time.
3874 * If the QUIET[1:0] bits are set to a different value, 1LSB
3875 * corresponds to 4*ODR_XL time.[get]
3876 *
3877 * @param ctx Read / write interface definitions
3878 * @param val Change the values of quiet in reg INT_DUR2
3879 * @retval Interface status (MANDATORY: return 0 -> no Error).
3880 *
3881 */
lsm6ds3tr_c_tap_quiet_get(const stmdev_ctx_t * ctx,uint8_t * val)3882 int32_t lsm6ds3tr_c_tap_quiet_get(const stmdev_ctx_t *ctx, uint8_t *val)
3883 {
3884 lsm6ds3tr_c_int_dur2_t int_dur2;
3885 int32_t ret;
3886
3887 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2,
3888 (uint8_t *)&int_dur2, 1);
3889 *val = int_dur2.quiet;
3890
3891 return ret;
3892 }
3893
3894 /**
3895 * @brief When double tap recognition is enabled, this register expresses the
3896 * maximum time between two consecutive detected taps to determine a
3897 * double tap event.
3898 * The default value of these bits is 0000b which corresponds to
3899 * 16*ODR_XL time.
3900 * If the DUR[3:0] bits are set to a different value,1LSB corresponds
3901 * to 32*ODR_XL time.[set]
3902 *
3903 * @param ctx Read / write interface definitions
3904 * @param val Change the values of dur in reg INT_DUR2
3905 * @retval Interface status (MANDATORY: return 0 -> no Error).
3906 *
3907 */
lsm6ds3tr_c_tap_dur_set(const stmdev_ctx_t * ctx,uint8_t val)3908 int32_t lsm6ds3tr_c_tap_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
3909 {
3910 lsm6ds3tr_c_int_dur2_t int_dur2;
3911 int32_t ret;
3912
3913 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2,
3914 (uint8_t *)&int_dur2, 1);
3915
3916 if (ret == 0)
3917 {
3918 int_dur2.dur = val;
3919 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_INT_DUR2,
3920 (uint8_t *)&int_dur2, 1);
3921 }
3922
3923 return ret;
3924 }
3925
3926 /**
3927 * @brief When double tap recognition is enabled, this register expresses the
3928 * maximum time between two consecutive detected taps to determine a
3929 * double tap event.
3930 * The default value of these bits is 0000b which corresponds to
3931 * 16*ODR_XL time.
3932 * If the DUR[3:0] bits are set to a different value,1LSB corresponds
3933 * to 32*ODR_XL time.[get]
3934 *
3935 * @param ctx Read / write interface definitions
3936 * @param val Change the values of dur in reg INT_DUR2
3937 * @retval Interface status (MANDATORY: return 0 -> no Error).
3938 *
3939 */
lsm6ds3tr_c_tap_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)3940 int32_t lsm6ds3tr_c_tap_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
3941 {
3942 lsm6ds3tr_c_int_dur2_t int_dur2;
3943 int32_t ret;
3944
3945 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_INT_DUR2,
3946 (uint8_t *)&int_dur2, 1);
3947 *val = int_dur2.dur;
3948
3949 return ret;
3950 }
3951
3952 /**
3953 * @brief Single/double-tap event enable/disable.[set]
3954 *
3955 * @param ctx Read / write interface definitions
3956 * @param val Change the values of
3957 * single_double_tap in reg WAKE_UP_THS
3958 * @retval Interface status (MANDATORY: return 0 -> no Error).
3959 *
3960 */
lsm6ds3tr_c_tap_mode_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_single_double_tap_t val)3961 int32_t lsm6ds3tr_c_tap_mode_set(const stmdev_ctx_t *ctx,
3962 lsm6ds3tr_c_single_double_tap_t val)
3963 {
3964 lsm6ds3tr_c_wake_up_ths_t wake_up_ths;
3965 int32_t ret;
3966
3967 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS,
3968 (uint8_t *)&wake_up_ths, 1);
3969
3970 if (ret == 0)
3971 {
3972 wake_up_ths.single_double_tap = (uint8_t) val;
3973 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS,
3974 (uint8_t *)&wake_up_ths, 1);
3975 }
3976
3977 return ret;
3978 }
3979
3980 /**
3981 * @brief Single/double-tap event enable/disable.[get]
3982 *
3983 * @param ctx Read / write interface definitions
3984 * @param val Get the values of single_double_tap
3985 * in reg WAKE_UP_THS
3986 * @retval Interface status (MANDATORY: return 0 -> no Error).
3987 *
3988 */
lsm6ds3tr_c_tap_mode_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_single_double_tap_t * val)3989 int32_t lsm6ds3tr_c_tap_mode_get(const stmdev_ctx_t *ctx,
3990 lsm6ds3tr_c_single_double_tap_t *val)
3991 {
3992 lsm6ds3tr_c_wake_up_ths_t wake_up_ths;
3993 int32_t ret;
3994
3995 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_THS,
3996 (uint8_t *)&wake_up_ths, 1);
3997
3998 switch (wake_up_ths.single_double_tap)
3999 {
4000 case LSM6DS3TR_C_ONLY_SINGLE:
4001 *val = LSM6DS3TR_C_ONLY_SINGLE;
4002 break;
4003
4004 case LSM6DS3TR_C_BOTH_SINGLE_DOUBLE:
4005 *val = LSM6DS3TR_C_BOTH_SINGLE_DOUBLE;
4006 break;
4007
4008 default:
4009 *val = LSM6DS3TR_C_TAP_MODE_ND;
4010 break;
4011 }
4012
4013 return ret;
4014 }
4015
4016 /**
4017 * @}
4018 *
4019 */
4020
4021 /**
4022 * @defgroup LSM6DS3TR_C_ Six_position_detection(6D/4D)
4023 * @brief This section groups all the functions concerning six
4024 * position detection (6D).
4025 * @{
4026 *
4027 */
4028
4029 /**
4030 * @brief LPF2 feed 6D function selection.[set]
4031 *
4032 * @param ctx Read / write interface definitions
4033 * @param val Change the values of low_pass_on_6d in
4034 * reg CTRL8_XL
4035 * @retval Interface status (MANDATORY: return 0 -> no Error).
4036 *
4037 */
lsm6ds3tr_c_6d_feed_data_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_low_pass_on_6d_t val)4038 int32_t lsm6ds3tr_c_6d_feed_data_set(const stmdev_ctx_t *ctx,
4039 lsm6ds3tr_c_low_pass_on_6d_t val)
4040 {
4041 lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
4042 int32_t ret;
4043
4044 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
4045 (uint8_t *)&ctrl8_xl, 1);
4046
4047 if (ret == 0)
4048 {
4049 ctrl8_xl.low_pass_on_6d = (uint8_t) val;
4050 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
4051 (uint8_t *)&ctrl8_xl, 1);
4052 }
4053
4054 return ret;
4055 }
4056
4057 /**
4058 * @brief LPF2 feed 6D function selection.[get]
4059 *
4060 * @param ctx Read / write interface definitions
4061 * @param val Get the values of low_pass_on_6d in reg CTRL8_XL
4062 * @retval Interface status (MANDATORY: return 0 -> no Error).
4063 *
4064 */
lsm6ds3tr_c_6d_feed_data_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_low_pass_on_6d_t * val)4065 int32_t lsm6ds3tr_c_6d_feed_data_get(const stmdev_ctx_t *ctx,
4066 lsm6ds3tr_c_low_pass_on_6d_t *val)
4067 {
4068 lsm6ds3tr_c_ctrl8_xl_t ctrl8_xl;
4069 int32_t ret;
4070
4071 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL8_XL,
4072 (uint8_t *)&ctrl8_xl, 1);
4073
4074 switch (ctrl8_xl.low_pass_on_6d)
4075 {
4076 case LSM6DS3TR_C_ODR_DIV_2_FEED:
4077 *val = LSM6DS3TR_C_ODR_DIV_2_FEED;
4078 break;
4079
4080 case LSM6DS3TR_C_LPF2_FEED:
4081 *val = LSM6DS3TR_C_LPF2_FEED;
4082 break;
4083
4084 default:
4085 *val = LSM6DS3TR_C_6D_FEED_ND;
4086 break;
4087 }
4088
4089 return ret;
4090 }
4091
4092 /**
4093 * @brief Threshold for 4D/6D function.[set]
4094 *
4095 * @param ctx Read / write interface definitions
4096 * @param val Change the values of sixd_ths in reg TAP_THS_6D
4097 * @retval Interface status (MANDATORY: return 0 -> no Error).
4098 *
4099 */
lsm6ds3tr_c_6d_threshold_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_sixd_ths_t val)4100 int32_t lsm6ds3tr_c_6d_threshold_set(const stmdev_ctx_t *ctx,
4101 lsm6ds3tr_c_sixd_ths_t val)
4102 {
4103 lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d;
4104 int32_t ret;
4105
4106 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D,
4107 (uint8_t *)&tap_ths_6d, 1);
4108
4109 if (ret == 0)
4110 {
4111 tap_ths_6d.sixd_ths = (uint8_t) val;
4112 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_THS_6D,
4113 (uint8_t *)&tap_ths_6d, 1);
4114 }
4115
4116 return ret;
4117 }
4118
4119 /**
4120 * @brief Threshold for 4D/6D function.[get]
4121 *
4122 * @param ctx Read / write interface definitions
4123 * @param val Get the values of sixd_ths in reg TAP_THS_6D
4124 * @retval Interface status (MANDATORY: return 0 -> no Error).
4125 *
4126 */
lsm6ds3tr_c_6d_threshold_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_sixd_ths_t * val)4127 int32_t lsm6ds3tr_c_6d_threshold_get(const stmdev_ctx_t *ctx,
4128 lsm6ds3tr_c_sixd_ths_t *val)
4129 {
4130 lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d;
4131 int32_t ret;
4132
4133 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D,
4134 (uint8_t *)&tap_ths_6d, 1);
4135
4136 switch (tap_ths_6d.sixd_ths)
4137 {
4138 case LSM6DS3TR_C_DEG_80:
4139 *val = LSM6DS3TR_C_DEG_80;
4140 break;
4141
4142 case LSM6DS3TR_C_DEG_70:
4143 *val = LSM6DS3TR_C_DEG_70;
4144 break;
4145
4146 case LSM6DS3TR_C_DEG_60:
4147 *val = LSM6DS3TR_C_DEG_60;
4148 break;
4149
4150 case LSM6DS3TR_C_DEG_50:
4151 *val = LSM6DS3TR_C_DEG_50;
4152 break;
4153
4154 default:
4155 *val = LSM6DS3TR_C_6D_TH_ND;
4156 break;
4157 }
4158
4159 return ret;
4160 }
4161
4162 /**
4163 * @brief 4D orientation detection enable.[set]
4164 *
4165 * @param ctx Read / write interface definitions
4166 * @param val Change the values of d4d_en in reg TAP_THS_6D
4167 * @retval Interface status (MANDATORY: return 0 -> no Error).
4168 *
4169 */
lsm6ds3tr_c_4d_mode_set(const stmdev_ctx_t * ctx,uint8_t val)4170 int32_t lsm6ds3tr_c_4d_mode_set(const stmdev_ctx_t *ctx, uint8_t val)
4171 {
4172 lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d;
4173 int32_t ret;
4174
4175 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D,
4176 (uint8_t *)&tap_ths_6d, 1);
4177
4178 if (ret == 0)
4179 {
4180 tap_ths_6d.d4d_en = val;
4181 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_TAP_THS_6D,
4182 (uint8_t *)&tap_ths_6d, 1);
4183 }
4184
4185 return ret;
4186 }
4187
4188 /**
4189 * @brief 4D orientation detection enable.[get]
4190 *
4191 * @param ctx Read / write interface definitions
4192 * @param val Change the values of d4d_en in reg TAP_THS_6D
4193 * @retval Interface status (MANDATORY: return 0 -> no Error).
4194 *
4195 */
lsm6ds3tr_c_4d_mode_get(const stmdev_ctx_t * ctx,uint8_t * val)4196 int32_t lsm6ds3tr_c_4d_mode_get(const stmdev_ctx_t *ctx, uint8_t *val)
4197 {
4198 lsm6ds3tr_c_tap_ths_6d_t tap_ths_6d;
4199 int32_t ret;
4200
4201 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_TAP_THS_6D,
4202 (uint8_t *)&tap_ths_6d, 1);
4203 *val = tap_ths_6d.d4d_en;
4204
4205 return ret;
4206 }
4207
4208 /**
4209 * @}
4210 *
4211 */
4212
4213 /**
4214 * @defgroup LSM6DS3TR_C_free_fall
4215 * @brief This section group all the functions concerning the free
4216 * fall detection.
4217 * @{
4218 *
4219 */
4220
4221 /**
4222 * @brief Free-fall duration event. 1LSb = 1 / ODR[set]
4223 *
4224 * @param ctx Read / write interface definitions
4225 * @param val Change the values of ff_dur in reg WAKE_UP_DUR
4226 * @retval Interface status (MANDATORY: return 0 -> no Error).
4227 *
4228 */
lsm6ds3tr_c_ff_dur_set(const stmdev_ctx_t * ctx,uint8_t val)4229 int32_t lsm6ds3tr_c_ff_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
4230 {
4231 lsm6ds3tr_c_wake_up_dur_t wake_up_dur;
4232 lsm6ds3tr_c_free_fall_t free_fall;
4233 int32_t ret;
4234
4235 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FREE_FALL,
4236 (uint8_t *)&free_fall, 1);
4237
4238 if (ret == 0)
4239 {
4240 free_fall.ff_dur = (val & 0x1FU);
4241 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FREE_FALL,
4242 (uint8_t *)&free_fall, 1);
4243
4244 if (ret == 0)
4245 {
4246 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
4247 (uint8_t *)&wake_up_dur, 1);
4248
4249 if (ret == 0)
4250 {
4251 wake_up_dur.ff_dur = (val & 0x20U) >> 5;
4252 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
4253 (uint8_t *)&wake_up_dur, 1);
4254 }
4255 }
4256 }
4257
4258 return ret;
4259 }
4260
4261 /**
4262 * @brief Free-fall duration event. 1LSb = 1 / ODR[get]
4263 *
4264 * @param ctx Read / write interface definitions
4265 * @param val Change the values of ff_dur in reg WAKE_UP_DUR
4266 * @retval Interface status (MANDATORY: return 0 -> no Error).
4267 *
4268 */
lsm6ds3tr_c_ff_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)4269 int32_t lsm6ds3tr_c_ff_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
4270 {
4271 lsm6ds3tr_c_wake_up_dur_t wake_up_dur;
4272 lsm6ds3tr_c_free_fall_t free_fall;
4273 int32_t ret;
4274
4275 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_WAKE_UP_DUR,
4276 (uint8_t *)&wake_up_dur, 1);
4277
4278 if (ret == 0)
4279 {
4280 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FREE_FALL,
4281 (uint8_t *)&free_fall, 1);
4282 }
4283
4284 *val = (wake_up_dur.ff_dur << 5) + free_fall.ff_dur;
4285
4286 return ret;
4287 }
4288
4289 /**
4290 * @brief Free fall threshold setting.[set]
4291 *
4292 * @param ctx Read / write interface definitions
4293 * @param val Change the values of ff_ths in reg FREE_FALL
4294 * @retval Interface status (MANDATORY: return 0 -> no Error).
4295 *
4296 */
lsm6ds3tr_c_ff_threshold_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_ff_ths_t val)4297 int32_t lsm6ds3tr_c_ff_threshold_set(const stmdev_ctx_t *ctx,
4298 lsm6ds3tr_c_ff_ths_t val)
4299 {
4300 lsm6ds3tr_c_free_fall_t free_fall;
4301 int32_t ret;
4302
4303 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FREE_FALL,
4304 (uint8_t *)&free_fall, 1);
4305
4306 if (ret == 0)
4307 {
4308 free_fall.ff_ths = (uint8_t) val;
4309 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FREE_FALL,
4310 (uint8_t *)&free_fall, 1);
4311 }
4312
4313 return ret;
4314 }
4315
4316 /**
4317 * @brief Free fall threshold setting.[get]
4318 *
4319 * @param ctx Read / write interface definitions
4320 * @param val Get the values of ff_ths in reg FREE_FALL
4321 * @retval Interface status (MANDATORY: return 0 -> no Error).
4322 *
4323 */
lsm6ds3tr_c_ff_threshold_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_ff_ths_t * val)4324 int32_t lsm6ds3tr_c_ff_threshold_get(const stmdev_ctx_t *ctx,
4325 lsm6ds3tr_c_ff_ths_t *val)
4326 {
4327 lsm6ds3tr_c_free_fall_t free_fall;
4328 int32_t ret;
4329
4330 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FREE_FALL,
4331 (uint8_t *)&free_fall, 1);
4332
4333 switch (free_fall.ff_ths)
4334 {
4335 case LSM6DS3TR_C_FF_TSH_156mg:
4336 *val = LSM6DS3TR_C_FF_TSH_156mg;
4337 break;
4338
4339 case LSM6DS3TR_C_FF_TSH_219mg:
4340 *val = LSM6DS3TR_C_FF_TSH_219mg;
4341 break;
4342
4343 case LSM6DS3TR_C_FF_TSH_250mg:
4344 *val = LSM6DS3TR_C_FF_TSH_250mg;
4345 break;
4346
4347 case LSM6DS3TR_C_FF_TSH_312mg:
4348 *val = LSM6DS3TR_C_FF_TSH_312mg;
4349 break;
4350
4351 case LSM6DS3TR_C_FF_TSH_344mg:
4352 *val = LSM6DS3TR_C_FF_TSH_344mg;
4353 break;
4354
4355 case LSM6DS3TR_C_FF_TSH_406mg:
4356 *val = LSM6DS3TR_C_FF_TSH_406mg;
4357 break;
4358
4359 case LSM6DS3TR_C_FF_TSH_469mg:
4360 *val = LSM6DS3TR_C_FF_TSH_469mg;
4361 break;
4362
4363 case LSM6DS3TR_C_FF_TSH_500mg:
4364 *val = LSM6DS3TR_C_FF_TSH_500mg;
4365 break;
4366
4367 default:
4368 *val = LSM6DS3TR_C_FF_TSH_ND;
4369 break;
4370 }
4371
4372 return ret;
4373 }
4374
4375 /**
4376 * @}
4377 *
4378 */
4379
4380 /**
4381 * @defgroup LSM6DS3TR_C_fifo
4382 * @brief This section group all the functions concerning the
4383 * fifo usage
4384 * @{
4385 *
4386 */
4387
4388 /**
4389 * @brief FIFO watermark level selection.[set]
4390 *
4391 * @param ctx Read / write interface definitions
4392 * @param val Change the values of fth in reg FIFO_CTRL1
4393 * @retval Interface status (MANDATORY: return 0 -> no Error).
4394 *
4395 */
lsm6ds3tr_c_fifo_watermark_set(const stmdev_ctx_t * ctx,uint16_t val)4396 int32_t lsm6ds3tr_c_fifo_watermark_set(const stmdev_ctx_t *ctx,
4397 uint16_t val)
4398 {
4399 lsm6ds3tr_c_fifo_ctrl1_t fifo_ctrl1;
4400 lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2;
4401 int32_t ret;
4402
4403 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
4404 (uint8_t *)&fifo_ctrl2, 1);
4405
4406 if (ret == 0)
4407 {
4408 fifo_ctrl1.fth = (uint8_t)(0x00FFU & val);
4409 fifo_ctrl2.fth = (uint8_t)((0x0700U & val) >> 8);
4410 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL1,
4411 (uint8_t *)&fifo_ctrl1, 1);
4412
4413 if (ret == 0)
4414 {
4415 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
4416 (uint8_t *)&fifo_ctrl2, 1);
4417 }
4418 }
4419
4420 return ret;
4421 }
4422
4423 /**
4424 * @brief FIFO watermark level selection.[get]
4425 *
4426 * @param ctx Read / write interface definitions
4427 * @param val Change the values of fth in reg FIFO_CTRL1
4428 * @retval Interface status (MANDATORY: return 0 -> no Error).
4429 *
4430 */
lsm6ds3tr_c_fifo_watermark_get(const stmdev_ctx_t * ctx,uint16_t * val)4431 int32_t lsm6ds3tr_c_fifo_watermark_get(const stmdev_ctx_t *ctx,
4432 uint16_t *val)
4433 {
4434 lsm6ds3tr_c_fifo_ctrl1_t fifo_ctrl1;
4435 lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2;
4436 int32_t ret;
4437
4438 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL1,
4439 (uint8_t *)&fifo_ctrl1, 1);
4440
4441 if (ret == 0)
4442 {
4443 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
4444 (uint8_t *)&fifo_ctrl2, 1);
4445 }
4446
4447 *val = ((uint16_t)fifo_ctrl2.fth << 8) + (uint16_t)fifo_ctrl1.fth;
4448
4449 return ret;
4450 }
4451
4452 /**
4453 * @brief FIFO data level.[get]
4454 *
4455 * @param ctx Read / write interface definitions
4456 * @param val get the values of diff_fifo in reg FIFO_STATUS1 and
4457 * FIFO_STATUS2(diff_fifo), it is recommended to set the
4458 * BDU bit.
4459 * @retval Interface status (MANDATORY: return 0 -> no Error).
4460 *
4461 */
lsm6ds3tr_c_fifo_data_level_get(const stmdev_ctx_t * ctx,uint16_t * val)4462 int32_t lsm6ds3tr_c_fifo_data_level_get(const stmdev_ctx_t *ctx,
4463 uint16_t *val)
4464 {
4465 lsm6ds3tr_c_fifo_status1_t fifo_status1;
4466 lsm6ds3tr_c_fifo_status2_t fifo_status2;
4467 int32_t ret;
4468
4469 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS1,
4470 (uint8_t *)&fifo_status1, 1);
4471
4472 if (ret == 0)
4473 {
4474 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS2,
4475 (uint8_t *)&fifo_status2, 1);
4476 *val = ((uint16_t) fifo_status2.diff_fifo << 8) +
4477 (uint16_t) fifo_status1.diff_fifo;
4478 }
4479
4480 return ret;
4481 }
4482
4483 /**
4484 * @brief FIFO watermark.[get]
4485 *
4486 * @param ctx Read / write interface definitions
4487 * @param val get the values of watermark in reg FIFO_STATUS2 and
4488 * @retval Interface status (MANDATORY: return 0 -> no Error).
4489 *
4490 */
lsm6ds3tr_c_fifo_wtm_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)4491 int32_t lsm6ds3tr_c_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val)
4492 {
4493 lsm6ds3tr_c_fifo_status2_t fifo_status2;
4494 int32_t ret;
4495
4496 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS2,
4497 (uint8_t *)&fifo_status2, 1);
4498 *val = fifo_status2.waterm;
4499
4500 return ret;
4501 }
4502
4503 /**
4504 * @brief FIFO pattern.[get]
4505 *
4506 * @param ctx Read / write interface definitions
4507 * @param val get the values of fifo_pattern in reg FIFO_STATUS3 and
4508 * FIFO_STATUS4, it is recommended to set the BDU bit
4509 * @retval Interface status (MANDATORY: return 0 -> no Error).
4510 *
4511 */
lsm6ds3tr_c_fifo_pattern_get(const stmdev_ctx_t * ctx,uint16_t * val)4512 int32_t lsm6ds3tr_c_fifo_pattern_get(const stmdev_ctx_t *ctx, uint16_t *val)
4513 {
4514 lsm6ds3tr_c_fifo_status3_t fifo_status3;
4515 lsm6ds3tr_c_fifo_status4_t fifo_status4;
4516 int32_t ret;
4517
4518 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS3,
4519 (uint8_t *)&fifo_status3, 1);
4520
4521 if (ret == 0)
4522 {
4523 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_STATUS4,
4524 (uint8_t *)&fifo_status4, 1);
4525 *val = ((uint16_t)fifo_status4.fifo_pattern << 8) +
4526 fifo_status3.fifo_pattern;
4527 }
4528
4529 return ret;
4530 }
4531
4532 /**
4533 * @brief Batching of temperature data[set]
4534 *
4535 * @param ctx Read / write interface definitions
4536 * @param val Change the values of fifo_temp_en in reg FIFO_CTRL2
4537 * @retval Interface status (MANDATORY: return 0 -> no Error).
4538 *
4539 */
lsm6ds3tr_c_fifo_temp_batch_set(const stmdev_ctx_t * ctx,uint8_t val)4540 int32_t lsm6ds3tr_c_fifo_temp_batch_set(const stmdev_ctx_t *ctx,
4541 uint8_t val)
4542 {
4543 lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2;
4544 int32_t ret;
4545
4546 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
4547 (uint8_t *)&fifo_ctrl2, 1);
4548
4549 if (ret == 0)
4550 {
4551 fifo_ctrl2.fifo_temp_en = val;
4552 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
4553 (uint8_t *)&fifo_ctrl2, 1);
4554 }
4555
4556 return ret;
4557 }
4558
4559 /**
4560 * @brief Batching of temperature data[get]
4561 *
4562 * @param ctx Read / write interface definitions
4563 * @param val Change the values of fifo_temp_en in reg FIFO_CTRL2
4564 * @retval Interface status (MANDATORY: return 0 -> no Error).
4565 *
4566 */
lsm6ds3tr_c_fifo_temp_batch_get(const stmdev_ctx_t * ctx,uint8_t * val)4567 int32_t lsm6ds3tr_c_fifo_temp_batch_get(const stmdev_ctx_t *ctx,
4568 uint8_t *val)
4569 {
4570 lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2;
4571 int32_t ret;
4572
4573 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
4574 (uint8_t *)&fifo_ctrl2, 1);
4575 *val = fifo_ctrl2.fifo_temp_en;
4576
4577 return ret;
4578 }
4579
4580 /**
4581 * @brief Trigger signal for FIFO write operation.[set]
4582 *
4583 * @param ctx Read / write interface definitions
4584 * @param val act on FIFO_CTRL2(timer_pedo_fifo_drdy)
4585 * and MASTER_CONFIG(data_valid_sel_fifo)
4586 * @retval Interface status (MANDATORY: return 0 -> no Error).
4587 *
4588 */
lsm6ds3tr_c_fifo_write_trigger_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_trigger_fifo_t val)4589 int32_t lsm6ds3tr_c_fifo_write_trigger_set(const stmdev_ctx_t *ctx,
4590 lsm6ds3tr_c_trigger_fifo_t val)
4591 {
4592 lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2;
4593 lsm6ds3tr_c_master_config_t master_config;
4594 int32_t ret;
4595
4596 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
4597 (uint8_t *)&fifo_ctrl2, 1);
4598
4599 if (ret == 0)
4600 {
4601 fifo_ctrl2.timer_pedo_fifo_drdy = (uint8_t)val & 0x01U;
4602 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
4603 (uint8_t *)&fifo_ctrl2, 1);
4604
4605 if (ret == 0)
4606 {
4607 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
4608 (uint8_t *)&master_config, 1);
4609
4610 if (ret == 0)
4611 {
4612 master_config.data_valid_sel_fifo = (((uint8_t)val & 0x02U) >> 1);
4613 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
4614 (uint8_t *)&master_config, 1);
4615 }
4616 }
4617 }
4618
4619 return ret;
4620 }
4621
4622 /**
4623 * @brief Trigger signal for FIFO write operation.[get]
4624 *
4625 * @param ctx Read / write interface definitions
4626 * @param val act on FIFO_CTRL2(timer_pedo_fifo_drdy)
4627 * and MASTER_CONFIG(data_valid_sel_fifo)
4628 * @retval Interface status (MANDATORY: return 0 -> no Error).
4629 *
4630 */
lsm6ds3tr_c_fifo_write_trigger_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_trigger_fifo_t * val)4631 int32_t lsm6ds3tr_c_fifo_write_trigger_get(const stmdev_ctx_t *ctx,
4632 lsm6ds3tr_c_trigger_fifo_t *val)
4633 {
4634 lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2;
4635 lsm6ds3tr_c_master_config_t master_config;
4636 int32_t ret;
4637
4638 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
4639 (uint8_t *)&fifo_ctrl2, 1);
4640
4641 if (ret == 0)
4642 {
4643 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
4644 (uint8_t *)&master_config, 1);
4645
4646 switch ((fifo_ctrl2.timer_pedo_fifo_drdy << 1) +
4647 fifo_ctrl2. timer_pedo_fifo_drdy)
4648 {
4649 case LSM6DS3TR_C_TRG_XL_GY_DRDY:
4650 *val = LSM6DS3TR_C_TRG_XL_GY_DRDY;
4651 break;
4652
4653 case LSM6DS3TR_C_TRG_STEP_DETECT:
4654 *val = LSM6DS3TR_C_TRG_STEP_DETECT;
4655 break;
4656
4657 case LSM6DS3TR_C_TRG_SH_DRDY:
4658 *val = LSM6DS3TR_C_TRG_SH_DRDY;
4659 break;
4660
4661 default:
4662 *val = LSM6DS3TR_C_TRG_SH_ND;
4663 break;
4664 }
4665 }
4666
4667 return ret;
4668 }
4669
4670 /**
4671 * @brief Enable pedometer step counter and timestamp as 4th
4672 * FIFO data set.[set]
4673 *
4674 * @param ctx Read / write interface definitions
4675 * @param val Change the values of timer_pedo_fifo_en in reg FIFO_CTRL2
4676 * @retval Interface status (MANDATORY: return 0 -> no Error).
4677 *
4678 */
lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_set(stmdev_ctx_t * ctx,uint8_t val)4679 int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_set(
4680 stmdev_ctx_t *ctx,
4681 uint8_t val)
4682 {
4683 lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2;
4684 int32_t ret;
4685
4686 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
4687 (uint8_t *)&fifo_ctrl2, 1);
4688
4689 if (ret == 0)
4690 {
4691 fifo_ctrl2.timer_pedo_fifo_en = val;
4692 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
4693 (uint8_t *)&fifo_ctrl2, 1);
4694 }
4695
4696 return ret;
4697 }
4698
4699 /**
4700 * @brief Enable pedometer step counter and timestamp as 4th
4701 * FIFO data set.[get]
4702 *
4703 * @param ctx Read / write interface definitions
4704 * @param val Change the values of timer_pedo_fifo_en in reg FIFO_CTRL2
4705 * @retval Interface status (MANDATORY: return 0 -> no Error).
4706 *
4707 */
lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_get(stmdev_ctx_t * ctx,uint8_t * val)4708 int32_t lsm6ds3tr_c_fifo_pedo_and_timestamp_batch_get(
4709 stmdev_ctx_t *ctx,
4710 uint8_t *val)
4711 {
4712 lsm6ds3tr_c_fifo_ctrl2_t fifo_ctrl2;
4713 int32_t ret;
4714
4715 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL2,
4716 (uint8_t *)&fifo_ctrl2, 1);
4717 *val = fifo_ctrl2.timer_pedo_fifo_en;
4718
4719 return ret;
4720 }
4721
4722 /**
4723 * @brief Selects Batching Data Rate (writing frequency in FIFO) for
4724 * accelerometer data.[set]
4725 *
4726 * @param ctx Read / write interface definitions
4727 * @param val Change the values of dec_fifo_xl in reg FIFO_CTRL3
4728 * @retval Interface status (MANDATORY: return 0 -> no Error).
4729 *
4730 */
lsm6ds3tr_c_fifo_xl_batch_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_dec_fifo_xl_t val)4731 int32_t lsm6ds3tr_c_fifo_xl_batch_set(const stmdev_ctx_t *ctx,
4732 lsm6ds3tr_c_dec_fifo_xl_t val)
4733 {
4734 lsm6ds3tr_c_fifo_ctrl3_t fifo_ctrl3;
4735 int32_t ret;
4736
4737 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3,
4738 (uint8_t *)&fifo_ctrl3, 1);
4739
4740 if (ret == 0)
4741 {
4742 fifo_ctrl3.dec_fifo_xl = (uint8_t)val;
4743 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3,
4744 (uint8_t *)&fifo_ctrl3, 1);
4745 }
4746
4747 return ret;
4748 }
4749
4750 /**
4751 * @brief Selects Batching Data Rate (writing frequency in FIFO) for
4752 * accelerometer data.[get]
4753 *
4754 * @param ctx Read / write interface definitions
4755 * @param val Get the values of dec_fifo_xl in reg FIFO_CTRL3
4756 * @retval Interface status (MANDATORY: return 0 -> no Error).
4757 *
4758 */
lsm6ds3tr_c_fifo_xl_batch_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_dec_fifo_xl_t * val)4759 int32_t lsm6ds3tr_c_fifo_xl_batch_get(const stmdev_ctx_t *ctx,
4760 lsm6ds3tr_c_dec_fifo_xl_t *val)
4761 {
4762 lsm6ds3tr_c_fifo_ctrl3_t fifo_ctrl3;
4763 int32_t ret;
4764
4765 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3,
4766 (uint8_t *)&fifo_ctrl3, 1);
4767
4768 switch (fifo_ctrl3.dec_fifo_xl)
4769 {
4770 case LSM6DS3TR_C_FIFO_XL_DISABLE:
4771 *val = LSM6DS3TR_C_FIFO_XL_DISABLE;
4772 break;
4773
4774 case LSM6DS3TR_C_FIFO_XL_NO_DEC:
4775 *val = LSM6DS3TR_C_FIFO_XL_NO_DEC;
4776 break;
4777
4778 case LSM6DS3TR_C_FIFO_XL_DEC_2:
4779 *val = LSM6DS3TR_C_FIFO_XL_DEC_2;
4780 break;
4781
4782 case LSM6DS3TR_C_FIFO_XL_DEC_3:
4783 *val = LSM6DS3TR_C_FIFO_XL_DEC_3;
4784 break;
4785
4786 case LSM6DS3TR_C_FIFO_XL_DEC_4:
4787 *val = LSM6DS3TR_C_FIFO_XL_DEC_4;
4788 break;
4789
4790 case LSM6DS3TR_C_FIFO_XL_DEC_8:
4791 *val = LSM6DS3TR_C_FIFO_XL_DEC_8;
4792 break;
4793
4794 case LSM6DS3TR_C_FIFO_XL_DEC_16:
4795 *val = LSM6DS3TR_C_FIFO_XL_DEC_16;
4796 break;
4797
4798 case LSM6DS3TR_C_FIFO_XL_DEC_32:
4799 *val = LSM6DS3TR_C_FIFO_XL_DEC_32;
4800 break;
4801
4802 default:
4803 *val = LSM6DS3TR_C_FIFO_XL_DEC_ND;
4804 break;
4805 }
4806
4807 return ret;
4808 }
4809
4810 /**
4811 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4812 * for gyroscope data.[set]
4813 *
4814 * @param ctx Read / write interface definitions
4815 * @param val Change the values of dec_fifo_gyro in reg FIFO_CTRL3
4816 * @retval Interface status (MANDATORY: return 0 -> no Error).
4817 *
4818 */
lsm6ds3tr_c_fifo_gy_batch_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_dec_fifo_gyro_t val)4819 int32_t lsm6ds3tr_c_fifo_gy_batch_set(const stmdev_ctx_t *ctx,
4820 lsm6ds3tr_c_dec_fifo_gyro_t val)
4821 {
4822 lsm6ds3tr_c_fifo_ctrl3_t fifo_ctrl3;
4823 int32_t ret;
4824
4825 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3,
4826 (uint8_t *)&fifo_ctrl3, 1);
4827
4828 if (ret == 0)
4829 {
4830 fifo_ctrl3.dec_fifo_gyro = (uint8_t)val;
4831 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3,
4832 (uint8_t *)&fifo_ctrl3, 1);
4833 }
4834
4835 return ret;
4836 }
4837
4838 /**
4839 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4840 * for gyroscope data.[get]
4841 *
4842 * @param ctx Read / write interface definitions
4843 * @param val Get the values of dec_fifo_gyro in reg FIFO_CTRL3
4844 * @retval Interface status (MANDATORY: return 0 -> no Error).
4845 *
4846 */
lsm6ds3tr_c_fifo_gy_batch_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_dec_fifo_gyro_t * val)4847 int32_t lsm6ds3tr_c_fifo_gy_batch_get(const stmdev_ctx_t *ctx,
4848 lsm6ds3tr_c_dec_fifo_gyro_t *val)
4849 {
4850 lsm6ds3tr_c_fifo_ctrl3_t fifo_ctrl3;
4851 int32_t ret;
4852
4853 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL3,
4854 (uint8_t *)&fifo_ctrl3, 1);
4855
4856 switch (fifo_ctrl3.dec_fifo_gyro)
4857 {
4858 case LSM6DS3TR_C_FIFO_GY_DISABLE:
4859 *val = LSM6DS3TR_C_FIFO_GY_DISABLE;
4860 break;
4861
4862 case LSM6DS3TR_C_FIFO_GY_NO_DEC:
4863 *val = LSM6DS3TR_C_FIFO_GY_NO_DEC;
4864 break;
4865
4866 case LSM6DS3TR_C_FIFO_GY_DEC_2:
4867 *val = LSM6DS3TR_C_FIFO_GY_DEC_2;
4868 break;
4869
4870 case LSM6DS3TR_C_FIFO_GY_DEC_3:
4871 *val = LSM6DS3TR_C_FIFO_GY_DEC_3;
4872 break;
4873
4874 case LSM6DS3TR_C_FIFO_GY_DEC_4:
4875 *val = LSM6DS3TR_C_FIFO_GY_DEC_4;
4876 break;
4877
4878 case LSM6DS3TR_C_FIFO_GY_DEC_8:
4879 *val = LSM6DS3TR_C_FIFO_GY_DEC_8;
4880 break;
4881
4882 case LSM6DS3TR_C_FIFO_GY_DEC_16:
4883 *val = LSM6DS3TR_C_FIFO_GY_DEC_16;
4884 break;
4885
4886 case LSM6DS3TR_C_FIFO_GY_DEC_32:
4887 *val = LSM6DS3TR_C_FIFO_GY_DEC_32;
4888 break;
4889
4890 default:
4891 *val = LSM6DS3TR_C_FIFO_GY_DEC_ND;
4892 break;
4893 }
4894
4895 return ret;
4896 }
4897
4898 /**
4899 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4900 * for third data set.[set]
4901 *
4902 * @param ctx Read / write interface definitions
4903 * @param val Change the values of dec_ds3_fifo in reg FIFO_CTRL4
4904 * @retval Interface status (MANDATORY: return 0 -> no Error).
4905 *
4906 */
lsm6ds3tr_c_fifo_dataset_3_batch_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_dec_ds3_fifo_t val)4907 int32_t lsm6ds3tr_c_fifo_dataset_3_batch_set(const stmdev_ctx_t *ctx,
4908 lsm6ds3tr_c_dec_ds3_fifo_t val)
4909 {
4910 lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4;
4911 int32_t ret;
4912
4913 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
4914 (uint8_t *)&fifo_ctrl4, 1);
4915
4916 if (ret == 0)
4917 {
4918 fifo_ctrl4.dec_ds3_fifo = (uint8_t)val;
4919 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
4920 (uint8_t *)&fifo_ctrl4, 1);
4921 }
4922
4923 return ret;
4924 }
4925
4926 /**
4927 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4928 * for third data set.[get]
4929 *
4930 * @param ctx Read / write interface definitions
4931 * @param val Get the values of dec_ds3_fifo in reg FIFO_CTRL4
4932 * @retval Interface status (MANDATORY: return 0 -> no Error).
4933 *
4934 */
lsm6ds3tr_c_fifo_dataset_3_batch_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_dec_ds3_fifo_t * val)4935 int32_t lsm6ds3tr_c_fifo_dataset_3_batch_get(const stmdev_ctx_t *ctx,
4936 lsm6ds3tr_c_dec_ds3_fifo_t *val)
4937 {
4938 lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4;
4939 int32_t ret;
4940
4941 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
4942 (uint8_t *)&fifo_ctrl4, 1);
4943
4944 switch (fifo_ctrl4.dec_ds3_fifo)
4945 {
4946 case LSM6DS3TR_C_FIFO_DS3_DISABLE:
4947 *val = LSM6DS3TR_C_FIFO_DS3_DISABLE;
4948 break;
4949
4950 case LSM6DS3TR_C_FIFO_DS3_NO_DEC:
4951 *val = LSM6DS3TR_C_FIFO_DS3_NO_DEC;
4952 break;
4953
4954 case LSM6DS3TR_C_FIFO_DS3_DEC_2:
4955 *val = LSM6DS3TR_C_FIFO_DS3_DEC_2;
4956 break;
4957
4958 case LSM6DS3TR_C_FIFO_DS3_DEC_3:
4959 *val = LSM6DS3TR_C_FIFO_DS3_DEC_3;
4960 break;
4961
4962 case LSM6DS3TR_C_FIFO_DS3_DEC_4:
4963 *val = LSM6DS3TR_C_FIFO_DS3_DEC_4;
4964 break;
4965
4966 case LSM6DS3TR_C_FIFO_DS3_DEC_8:
4967 *val = LSM6DS3TR_C_FIFO_DS3_DEC_8;
4968 break;
4969
4970 case LSM6DS3TR_C_FIFO_DS3_DEC_16:
4971 *val = LSM6DS3TR_C_FIFO_DS3_DEC_16;
4972 break;
4973
4974 case LSM6DS3TR_C_FIFO_DS3_DEC_32:
4975 *val = LSM6DS3TR_C_FIFO_DS3_DEC_32;
4976 break;
4977
4978 default:
4979 *val = LSM6DS3TR_C_FIFO_DS3_DEC_ND;
4980 break;
4981 }
4982
4983 return ret;
4984 }
4985
4986 /**
4987 * @brief Selects Batching Data Rate (writing frequency in FIFO)
4988 * for fourth data set.[set]
4989 *
4990 * @param ctx Read / write interface definitions
4991 * @param val Change the values of dec_ds4_fifo in reg FIFO_CTRL4
4992 * @retval Interface status (MANDATORY: return 0 -> no Error).
4993 *
4994 */
lsm6ds3tr_c_fifo_dataset_4_batch_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_dec_ds4_fifo_t val)4995 int32_t lsm6ds3tr_c_fifo_dataset_4_batch_set(const stmdev_ctx_t *ctx,
4996 lsm6ds3tr_c_dec_ds4_fifo_t val)
4997 {
4998 lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4;
4999 int32_t ret;
5000
5001 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
5002 (uint8_t *)&fifo_ctrl4, 1);
5003
5004 if (ret == 0)
5005 {
5006 fifo_ctrl4.dec_ds4_fifo = (uint8_t)val;
5007 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
5008 (uint8_t *)&fifo_ctrl4, 1);
5009 }
5010
5011 return ret;
5012 }
5013
5014 /**
5015 * @brief Selects Batching Data Rate (writing frequency in FIFO) for
5016 * fourth data set.[get]
5017 *
5018 * @param ctx Read / write interface definitions
5019 * @param val Get the values of dec_ds4_fifo in reg FIFO_CTRL4
5020 * @retval Interface status (MANDATORY: return 0 -> no Error).
5021 *
5022 */
lsm6ds3tr_c_fifo_dataset_4_batch_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_dec_ds4_fifo_t * val)5023 int32_t lsm6ds3tr_c_fifo_dataset_4_batch_get(const stmdev_ctx_t *ctx,
5024 lsm6ds3tr_c_dec_ds4_fifo_t *val)
5025 {
5026 lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4;
5027 int32_t ret;
5028
5029 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
5030 (uint8_t *)&fifo_ctrl4, 1);
5031
5032 switch (fifo_ctrl4.dec_ds4_fifo)
5033 {
5034 case LSM6DS3TR_C_FIFO_DS4_DISABLE:
5035 *val = LSM6DS3TR_C_FIFO_DS4_DISABLE;
5036 break;
5037
5038 case LSM6DS3TR_C_FIFO_DS4_NO_DEC:
5039 *val = LSM6DS3TR_C_FIFO_DS4_NO_DEC;
5040 break;
5041
5042 case LSM6DS3TR_C_FIFO_DS4_DEC_2:
5043 *val = LSM6DS3TR_C_FIFO_DS4_DEC_2;
5044 break;
5045
5046 case LSM6DS3TR_C_FIFO_DS4_DEC_3:
5047 *val = LSM6DS3TR_C_FIFO_DS4_DEC_3;
5048 break;
5049
5050 case LSM6DS3TR_C_FIFO_DS4_DEC_4:
5051 *val = LSM6DS3TR_C_FIFO_DS4_DEC_4;
5052 break;
5053
5054 case LSM6DS3TR_C_FIFO_DS4_DEC_8:
5055 *val = LSM6DS3TR_C_FIFO_DS4_DEC_8;
5056 break;
5057
5058 case LSM6DS3TR_C_FIFO_DS4_DEC_16:
5059 *val = LSM6DS3TR_C_FIFO_DS4_DEC_16;
5060 break;
5061
5062 case LSM6DS3TR_C_FIFO_DS4_DEC_32:
5063 *val = LSM6DS3TR_C_FIFO_DS4_DEC_32;
5064 break;
5065
5066 default:
5067 *val = LSM6DS3TR_C_FIFO_DS4_DEC_ND;
5068 break;
5069 }
5070
5071 return ret;
5072 }
5073
5074 /**
5075 * @brief 8-bit data storage in FIFO.[set]
5076 *
5077 * @param ctx Read / write interface definitions
5078 * @param val Change the values of only_high_data in reg FIFO_CTRL4
5079 * @retval Interface status (MANDATORY: return 0 -> no Error).
5080 *
5081 */
lsm6ds3tr_c_fifo_xl_gy_8bit_format_set(const stmdev_ctx_t * ctx,uint8_t val)5082 int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_set(const stmdev_ctx_t *ctx,
5083 uint8_t val)
5084 {
5085 lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4;
5086 int32_t ret;
5087
5088 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
5089 (uint8_t *)&fifo_ctrl4, 1);
5090
5091 if (ret == 0)
5092 {
5093 fifo_ctrl4.only_high_data = val;
5094 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
5095 (uint8_t *)&fifo_ctrl4, 1);
5096 }
5097
5098 return ret;
5099 }
5100
5101 /**
5102 * @brief 8-bit data storage in FIFO.[get]
5103 *
5104 * @param ctx Read / write interface definitions
5105 * @param val Change the values of only_high_data in reg FIFO_CTRL4
5106 * @retval Interface status (MANDATORY: return 0 -> no Error).
5107 *
5108 */
lsm6ds3tr_c_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t * ctx,uint8_t * val)5109 int32_t lsm6ds3tr_c_fifo_xl_gy_8bit_format_get(const stmdev_ctx_t *ctx,
5110 uint8_t *val)
5111 {
5112 lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4;
5113 int32_t ret;
5114
5115 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
5116 (uint8_t *)&fifo_ctrl4, 1);
5117 *val = fifo_ctrl4.only_high_data;
5118
5119 return ret;
5120 }
5121
5122 /**
5123 * @brief Sensing chain FIFO stop values memorization at threshold
5124 * level.[set]
5125 *
5126 * @param ctx Read / write interface definitions
5127 * @param val Change the values of stop_on_fth in reg FIFO_CTRL4
5128 * @retval Interface status (MANDATORY: return 0 -> no Error).
5129 *
5130 */
lsm6ds3tr_c_fifo_stop_on_wtm_set(const stmdev_ctx_t * ctx,uint8_t val)5131 int32_t lsm6ds3tr_c_fifo_stop_on_wtm_set(const stmdev_ctx_t *ctx,
5132 uint8_t val)
5133 {
5134 lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4;
5135 int32_t ret;
5136
5137 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
5138 (uint8_t *)&fifo_ctrl4, 1);
5139
5140 if (ret == 0)
5141 {
5142 fifo_ctrl4.stop_on_fth = val;
5143 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
5144 (uint8_t *)&fifo_ctrl4, 1);
5145 }
5146
5147 return ret;
5148 }
5149
5150 /**
5151 * @brief Sensing chain FIFO stop values memorization at threshold
5152 * level.[get]
5153 *
5154 * @param ctx Read / write interface definitions
5155 * @param val Change the values of stop_on_fth in reg FIFO_CTRL4
5156 * @retval Interface status (MANDATORY: return 0 -> no Error).
5157 *
5158 */
lsm6ds3tr_c_fifo_stop_on_wtm_get(const stmdev_ctx_t * ctx,uint8_t * val)5159 int32_t lsm6ds3tr_c_fifo_stop_on_wtm_get(const stmdev_ctx_t *ctx,
5160 uint8_t *val)
5161 {
5162 lsm6ds3tr_c_fifo_ctrl4_t fifo_ctrl4;
5163 int32_t ret;
5164
5165 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL4,
5166 (uint8_t *)&fifo_ctrl4, 1);
5167 *val = fifo_ctrl4.stop_on_fth;
5168
5169 return ret;
5170 }
5171
5172 /**
5173 * @brief FIFO mode selection.[set]
5174 *
5175 * @param ctx Read / write interface definitions
5176 * @param val Change the values of fifo_mode in reg FIFO_CTRL5
5177 * @retval Interface status (MANDATORY: return 0 -> no Error).
5178 *
5179 */
lsm6ds3tr_c_fifo_mode_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_fifo_mode_t val)5180 int32_t lsm6ds3tr_c_fifo_mode_set(const stmdev_ctx_t *ctx,
5181 lsm6ds3tr_c_fifo_mode_t val)
5182 {
5183 lsm6ds3tr_c_fifo_ctrl5_t fifo_ctrl5;
5184 int32_t ret;
5185
5186 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5,
5187 (uint8_t *)&fifo_ctrl5, 1);
5188
5189 if (ret == 0)
5190 {
5191 fifo_ctrl5.fifo_mode = (uint8_t)val;
5192 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5,
5193 (uint8_t *)&fifo_ctrl5, 1);
5194 }
5195
5196 return ret;
5197 }
5198
5199 /**
5200 * @brief FIFO mode selection.[get]
5201 *
5202 * @param ctx Read / write interface definitions
5203 * @param val Get the values of fifo_mode in reg FIFO_CTRL5
5204 * @retval Interface status (MANDATORY: return 0 -> no Error).
5205 *
5206 */
lsm6ds3tr_c_fifo_mode_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_fifo_mode_t * val)5207 int32_t lsm6ds3tr_c_fifo_mode_get(const stmdev_ctx_t *ctx,
5208 lsm6ds3tr_c_fifo_mode_t *val)
5209 {
5210 lsm6ds3tr_c_fifo_ctrl5_t fifo_ctrl5;
5211 int32_t ret;
5212
5213 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5,
5214 (uint8_t *)&fifo_ctrl5, 1);
5215
5216 switch (fifo_ctrl5.fifo_mode)
5217 {
5218 case LSM6DS3TR_C_BYPASS_MODE:
5219 *val = LSM6DS3TR_C_BYPASS_MODE;
5220 break;
5221
5222 case LSM6DS3TR_C_FIFO_MODE:
5223 *val = LSM6DS3TR_C_FIFO_MODE;
5224 break;
5225
5226 case LSM6DS3TR_C_STREAM_TO_FIFO_MODE:
5227 *val = LSM6DS3TR_C_STREAM_TO_FIFO_MODE;
5228 break;
5229
5230 case LSM6DS3TR_C_BYPASS_TO_STREAM_MODE:
5231 *val = LSM6DS3TR_C_BYPASS_TO_STREAM_MODE;
5232 break;
5233
5234 case LSM6DS3TR_C_STREAM_MODE:
5235 *val = LSM6DS3TR_C_STREAM_MODE;
5236 break;
5237
5238 default:
5239 *val = LSM6DS3TR_C_FIFO_MODE_ND;
5240 break;
5241 }
5242
5243 return ret;
5244 }
5245
5246 /**
5247 * @brief FIFO ODR selection, setting FIFO_MODE also.[set]
5248 *
5249 * @param ctx Read / write interface definitions
5250 * @param val Change the values of odr_fifo in reg FIFO_CTRL5
5251 * @retval Interface status (MANDATORY: return 0 -> no Error).
5252 *
5253 */
lsm6ds3tr_c_fifo_data_rate_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_odr_fifo_t val)5254 int32_t lsm6ds3tr_c_fifo_data_rate_set(const stmdev_ctx_t *ctx,
5255 lsm6ds3tr_c_odr_fifo_t val)
5256 {
5257 lsm6ds3tr_c_fifo_ctrl5_t fifo_ctrl5;
5258 int32_t ret;
5259
5260 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5,
5261 (uint8_t *)&fifo_ctrl5, 1);
5262
5263 if (ret == 0)
5264 {
5265 fifo_ctrl5.odr_fifo = (uint8_t)val;
5266 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5,
5267 (uint8_t *)&fifo_ctrl5, 1);
5268 }
5269
5270 return ret;
5271 }
5272
5273 /**
5274 * @brief FIFO ODR selection, setting FIFO_MODE also.[get]
5275 *
5276 * @param ctx Read / write interface definitions
5277 * @param val Get the values of odr_fifo in reg FIFO_CTRL5
5278 * @retval Interface status (MANDATORY: return 0 -> no Error).
5279 *
5280 */
lsm6ds3tr_c_fifo_data_rate_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_odr_fifo_t * val)5281 int32_t lsm6ds3tr_c_fifo_data_rate_get(const stmdev_ctx_t *ctx,
5282 lsm6ds3tr_c_odr_fifo_t *val)
5283 {
5284 lsm6ds3tr_c_fifo_ctrl5_t fifo_ctrl5;
5285 int32_t ret;
5286
5287 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_FIFO_CTRL5,
5288 (uint8_t *)&fifo_ctrl5, 1);
5289
5290 switch (fifo_ctrl5.odr_fifo)
5291 {
5292 case LSM6DS3TR_C_FIFO_DISABLE:
5293 *val = LSM6DS3TR_C_FIFO_DISABLE;
5294 break;
5295
5296 case LSM6DS3TR_C_FIFO_12Hz5:
5297 *val = LSM6DS3TR_C_FIFO_12Hz5;
5298 break;
5299
5300 case LSM6DS3TR_C_FIFO_26Hz:
5301 *val = LSM6DS3TR_C_FIFO_26Hz;
5302 break;
5303
5304 case LSM6DS3TR_C_FIFO_52Hz:
5305 *val = LSM6DS3TR_C_FIFO_52Hz;
5306 break;
5307
5308 case LSM6DS3TR_C_FIFO_104Hz:
5309 *val = LSM6DS3TR_C_FIFO_104Hz;
5310 break;
5311
5312 case LSM6DS3TR_C_FIFO_208Hz:
5313 *val = LSM6DS3TR_C_FIFO_208Hz;
5314 break;
5315
5316 case LSM6DS3TR_C_FIFO_416Hz:
5317 *val = LSM6DS3TR_C_FIFO_416Hz;
5318 break;
5319
5320 case LSM6DS3TR_C_FIFO_833Hz:
5321 *val = LSM6DS3TR_C_FIFO_833Hz;
5322 break;
5323
5324 case LSM6DS3TR_C_FIFO_1k66Hz:
5325 *val = LSM6DS3TR_C_FIFO_1k66Hz;
5326 break;
5327
5328 case LSM6DS3TR_C_FIFO_3k33Hz:
5329 *val = LSM6DS3TR_C_FIFO_3k33Hz;
5330 break;
5331
5332 case LSM6DS3TR_C_FIFO_6k66Hz:
5333 *val = LSM6DS3TR_C_FIFO_6k66Hz;
5334 break;
5335
5336 default:
5337 *val = LSM6DS3TR_C_FIFO_RATE_ND;
5338 break;
5339 }
5340
5341 return ret;
5342 }
5343
5344 /**
5345 * @}
5346 *
5347 */
5348
5349 /**
5350 * @defgroup LSM6DS3TR_C_DEN_functionality
5351 * @brief This section groups all the functions concerning DEN
5352 * functionality.
5353 * @{
5354 *
5355 */
5356
5357 /**
5358 * @brief DEN active level configuration.[set]
5359 *
5360 * @param ctx Read / write interface definitions
5361 * @param val Change the values of den_lh in reg CTRL5_C
5362 * @retval Interface status (MANDATORY: return 0 -> no Error).
5363 *
5364 */
lsm6ds3tr_c_den_polarity_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_den_lh_t val)5365 int32_t lsm6ds3tr_c_den_polarity_set(const stmdev_ctx_t *ctx,
5366 lsm6ds3tr_c_den_lh_t val)
5367 {
5368 lsm6ds3tr_c_ctrl5_c_t ctrl5_c;
5369 int32_t ret;
5370
5371 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C,
5372 (uint8_t *)&ctrl5_c, 1);
5373
5374 if (ret == 0)
5375 {
5376 ctrl5_c.den_lh = (uint8_t)val;
5377 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL5_C,
5378 (uint8_t *)&ctrl5_c, 1);
5379 }
5380
5381 return ret;
5382 }
5383
5384 /**
5385 * @brief DEN active level configuration.[get]
5386 *
5387 * @param ctx Read / write interface definitions
5388 * @param val Get the values of den_lh in reg CTRL5_C
5389 * @retval Interface status (MANDATORY: return 0 -> no Error).
5390 *
5391 */
lsm6ds3tr_c_den_polarity_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_den_lh_t * val)5392 int32_t lsm6ds3tr_c_den_polarity_get(const stmdev_ctx_t *ctx,
5393 lsm6ds3tr_c_den_lh_t *val)
5394 {
5395 lsm6ds3tr_c_ctrl5_c_t ctrl5_c;
5396 int32_t ret;
5397
5398 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL5_C,
5399 (uint8_t *)&ctrl5_c, 1);
5400
5401 switch (ctrl5_c.den_lh)
5402 {
5403 case LSM6DS3TR_C_DEN_ACT_LOW:
5404 *val = LSM6DS3TR_C_DEN_ACT_LOW;
5405 break;
5406
5407 case LSM6DS3TR_C_DEN_ACT_HIGH:
5408 *val = LSM6DS3TR_C_DEN_ACT_HIGH;
5409 break;
5410
5411 default:
5412 *val = LSM6DS3TR_C_DEN_POL_ND;
5413 break;
5414 }
5415
5416 return ret;
5417 }
5418
5419 /**
5420 * @brief DEN functionality marking mode[set]
5421 *
5422 * @param ctx Read / write interface definitions
5423 * @param val Change the values of den_mode in reg CTRL6_C
5424 * @retval Interface status (MANDATORY: return 0 -> no Error).
5425 *
5426 */
lsm6ds3tr_c_den_mode_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_den_mode_t val)5427 int32_t lsm6ds3tr_c_den_mode_set(const stmdev_ctx_t *ctx,
5428 lsm6ds3tr_c_den_mode_t val)
5429 {
5430 lsm6ds3tr_c_ctrl6_c_t ctrl6_c;
5431 int32_t ret;
5432
5433 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C,
5434 (uint8_t *)&ctrl6_c, 1);
5435
5436 if (ret == 0)
5437 {
5438 ctrl6_c.den_mode = (uint8_t)val;
5439 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL6_C,
5440 (uint8_t *)&ctrl6_c, 1);
5441 }
5442
5443 return ret;
5444 }
5445
5446 /**
5447 * @brief DEN functionality marking mode[get]
5448 *
5449 * @param ctx Read / write interface definitions
5450 * @param val Change the values of den_mode in reg CTRL6_C
5451 * @retval Interface status (MANDATORY: return 0 -> no Error).
5452 *
5453 */
lsm6ds3tr_c_den_mode_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_den_mode_t * val)5454 int32_t lsm6ds3tr_c_den_mode_get(const stmdev_ctx_t *ctx,
5455 lsm6ds3tr_c_den_mode_t *val)
5456 {
5457 lsm6ds3tr_c_ctrl6_c_t ctrl6_c;
5458 int32_t ret;
5459
5460 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL6_C,
5461 (uint8_t *)&ctrl6_c, 1);
5462
5463 switch (ctrl6_c.den_mode)
5464 {
5465 case LSM6DS3TR_C_DEN_DISABLE:
5466 *val = LSM6DS3TR_C_DEN_DISABLE;
5467 break;
5468
5469 case LSM6DS3TR_C_LEVEL_LETCHED:
5470 *val = LSM6DS3TR_C_LEVEL_LETCHED;
5471 break;
5472
5473 case LSM6DS3TR_C_LEVEL_TRIGGER:
5474 *val = LSM6DS3TR_C_LEVEL_TRIGGER;
5475 break;
5476
5477 case LSM6DS3TR_C_EDGE_TRIGGER:
5478 *val = LSM6DS3TR_C_EDGE_TRIGGER;
5479 break;
5480
5481 default:
5482 *val = LSM6DS3TR_C_DEN_MODE_ND;
5483 break;
5484 }
5485
5486 return ret;
5487 }
5488
5489 /**
5490 * @brief Extend DEN functionality to accelerometer sensor.[set]
5491 *
5492 * @param ctx Read / write interface definitions
5493 * @param val Change the values of den_xl_g in reg CTRL9_XL
5494 * and den_xl_en in CTRL4_C.
5495 * @retval Interface status (MANDATORY: return 0 -> no Error).
5496 *
5497 */
lsm6ds3tr_c_den_enable_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_den_xl_en_t val)5498 int32_t lsm6ds3tr_c_den_enable_set(const stmdev_ctx_t *ctx,
5499 lsm6ds3tr_c_den_xl_en_t val)
5500 {
5501 lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
5502 lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
5503 int32_t ret;
5504
5505 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
5506 (uint8_t *)&ctrl9_xl, 1);
5507
5508 if (ret == 0)
5509 {
5510 ctrl9_xl.den_xl_g = (uint8_t)val & 0x01U;
5511 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
5512 (uint8_t *)&ctrl9_xl, 1);
5513
5514 if (ret == 0)
5515 {
5516 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
5517 (uint8_t *)&ctrl4_c, 1);
5518
5519 if (ret == 0)
5520 {
5521 ctrl4_c.den_xl_en = (uint8_t)val & 0x02U;
5522 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL4_C,
5523 (uint8_t *)&ctrl4_c, 1);
5524 }
5525 }
5526 }
5527
5528 return ret;
5529 }
5530
5531 /**
5532 * @brief Extend DEN functionality to accelerometer sensor. [get]
5533 *
5534 * @param ctx Read / write interface definitions
5535 * @param val Get the values of den_xl_g in reg CTRL9_XL
5536 * and den_xl_en in CTRL4_C.
5537 * @retval Interface status (MANDATORY: return 0 -> no Error).
5538 *
5539 */
lsm6ds3tr_c_den_enable_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_den_xl_en_t * val)5540 int32_t lsm6ds3tr_c_den_enable_get(const stmdev_ctx_t *ctx,
5541 lsm6ds3tr_c_den_xl_en_t *val)
5542 {
5543 lsm6ds3tr_c_ctrl4_c_t ctrl4_c;
5544 lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
5545 int32_t ret;
5546
5547 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL4_C,
5548 (uint8_t *)&ctrl4_c, 1);
5549
5550 if (ret == 0)
5551 {
5552 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
5553 (uint8_t *)&ctrl9_xl, 1);
5554
5555 switch ((ctrl4_c.den_xl_en << 1) + ctrl9_xl.den_xl_g)
5556 {
5557 case LSM6DS3TR_C_STAMP_IN_GY_DATA:
5558 *val = LSM6DS3TR_C_STAMP_IN_GY_DATA;
5559 break;
5560
5561 case LSM6DS3TR_C_STAMP_IN_XL_DATA:
5562 *val = LSM6DS3TR_C_STAMP_IN_XL_DATA;
5563 break;
5564
5565 case LSM6DS3TR_C_STAMP_IN_GY_XL_DATA:
5566 *val = LSM6DS3TR_C_STAMP_IN_GY_XL_DATA;
5567 break;
5568
5569 default:
5570 *val = LSM6DS3TR_C_DEN_STAMP_ND;
5571 break;
5572 }
5573 }
5574
5575 return ret;
5576 }
5577
5578 /**
5579 * @brief DEN value stored in LSB of Z-axis.[set]
5580 *
5581 * @param ctx Read / write interface definitions
5582 * @param val Change the values of den_z in reg CTRL9_XL
5583 * @retval Interface status (MANDATORY: return 0 -> no Error).
5584 *
5585 */
lsm6ds3tr_c_den_mark_axis_z_set(const stmdev_ctx_t * ctx,uint8_t val)5586 int32_t lsm6ds3tr_c_den_mark_axis_z_set(const stmdev_ctx_t *ctx,
5587 uint8_t val)
5588 {
5589 lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
5590 int32_t ret;
5591
5592 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
5593 (uint8_t *)&ctrl9_xl, 1);
5594
5595 if (ret == 0)
5596 {
5597 ctrl9_xl.den_z = val;
5598 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
5599 (uint8_t *)&ctrl9_xl, 1);
5600 }
5601
5602 return ret;
5603 }
5604
5605 /**
5606 * @brief DEN value stored in LSB of Z-axis.[get]
5607 *
5608 * @param ctx Read / write interface definitions
5609 * @param val Change the values of den_z in reg CTRL9_XL
5610 * @retval Interface status (MANDATORY: return 0 -> no Error).
5611 *
5612 */
lsm6ds3tr_c_den_mark_axis_z_get(const stmdev_ctx_t * ctx,uint8_t * val)5613 int32_t lsm6ds3tr_c_den_mark_axis_z_get(const stmdev_ctx_t *ctx,
5614 uint8_t *val)
5615 {
5616 lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
5617 int32_t ret;
5618
5619 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
5620 (uint8_t *)&ctrl9_xl, 1);
5621 *val = ctrl9_xl.den_z;
5622
5623 return ret;
5624 }
5625
5626 /**
5627 * @brief DEN value stored in LSB of Y-axis.[set]
5628 *
5629 * @param ctx Read / write interface definitions
5630 * @param val Change the values of den_y in reg CTRL9_XL
5631 * @retval Interface status (MANDATORY: return 0 -> no Error).
5632 *
5633 */
lsm6ds3tr_c_den_mark_axis_y_set(const stmdev_ctx_t * ctx,uint8_t val)5634 int32_t lsm6ds3tr_c_den_mark_axis_y_set(const stmdev_ctx_t *ctx,
5635 uint8_t val)
5636 {
5637 lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
5638 int32_t ret;
5639
5640 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
5641 (uint8_t *)&ctrl9_xl, 1);
5642
5643 if (ret == 0)
5644 {
5645 ctrl9_xl.den_y = val;
5646 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
5647 (uint8_t *)&ctrl9_xl, 1);
5648 }
5649
5650 return ret;
5651 }
5652
5653 /**
5654 * @brief DEN value stored in LSB of Y-axis.[get]
5655 *
5656 * @param ctx Read / write interface definitions
5657 * @param val Change the values of den_y in reg CTRL9_XL
5658 * @retval Interface status (MANDATORY: return 0 -> no Error).
5659 *
5660 */
lsm6ds3tr_c_den_mark_axis_y_get(const stmdev_ctx_t * ctx,uint8_t * val)5661 int32_t lsm6ds3tr_c_den_mark_axis_y_get(const stmdev_ctx_t *ctx,
5662 uint8_t *val)
5663 {
5664 lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
5665 int32_t ret;
5666
5667 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
5668 (uint8_t *)&ctrl9_xl, 1);
5669 *val = ctrl9_xl.den_y;
5670
5671 return ret;
5672 }
5673
5674 /**
5675 * @brief DEN value stored in LSB of X-axis.[set]
5676 *
5677 * @param ctx Read / write interface definitions
5678 * @param val Change the values of den_x in reg CTRL9_XL
5679 * @retval Interface status (MANDATORY: return 0 -> no Error).
5680 *
5681 */
lsm6ds3tr_c_den_mark_axis_x_set(const stmdev_ctx_t * ctx,uint8_t val)5682 int32_t lsm6ds3tr_c_den_mark_axis_x_set(const stmdev_ctx_t *ctx,
5683 uint8_t val)
5684 {
5685 lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
5686 int32_t ret;
5687
5688 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
5689 (uint8_t *)&ctrl9_xl, 1);
5690
5691 if (ret == 0)
5692 {
5693 ctrl9_xl.den_x = val;
5694 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
5695 (uint8_t *)&ctrl9_xl, 1);
5696 }
5697
5698 return ret;
5699 }
5700
5701 /**
5702 * @brief DEN value stored in LSB of X-axis.[get]
5703 *
5704 * @param ctx Read / write interface definitions
5705 * @param val Change the values of den_x in reg CTRL9_XL
5706 * @retval Interface status (MANDATORY: return 0 -> no Error).
5707 *
5708 */
lsm6ds3tr_c_den_mark_axis_x_get(const stmdev_ctx_t * ctx,uint8_t * val)5709 int32_t lsm6ds3tr_c_den_mark_axis_x_get(const stmdev_ctx_t *ctx,
5710 uint8_t *val)
5711 {
5712 lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
5713 int32_t ret;
5714
5715 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
5716 (uint8_t *)&ctrl9_xl, 1);
5717 *val = ctrl9_xl.den_x;
5718
5719 return ret;
5720 }
5721
5722 /**
5723 * @}
5724 *
5725 */
5726
5727 /**
5728 * @defgroup LSM6DS3TR_C_Pedometer
5729 * @brief This section groups all the functions that manage pedometer.
5730 * @{
5731 *
5732 */
5733
5734 /**
5735 * @brief Reset pedometer step counter.[set]
5736 *
5737 * @param ctx Read / write interface definitions
5738 * @param val Change the values of pedo_rst_step in reg CTRL10_C
5739 * @retval Interface status (MANDATORY: return 0 -> no Error).
5740 *
5741 */
lsm6ds3tr_c_pedo_step_reset_set(const stmdev_ctx_t * ctx,uint8_t val)5742 int32_t lsm6ds3tr_c_pedo_step_reset_set(const stmdev_ctx_t *ctx,
5743 uint8_t val)
5744 {
5745 lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
5746 int32_t ret;
5747
5748 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
5749 (uint8_t *)&ctrl10_c, 1);
5750
5751 if (ret == 0)
5752 {
5753 ctrl10_c.pedo_rst_step = val;
5754 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C,
5755 (uint8_t *)&ctrl10_c, 1);
5756 }
5757
5758 return ret;
5759 }
5760
5761 /**
5762 * @brief Reset pedometer step counter.[get]
5763 *
5764 * @param ctx Read / write interface definitions
5765 * @param val Change the values of pedo_rst_step in reg CTRL10_C
5766 * @retval Interface status (MANDATORY: return 0 -> no Error).
5767 *
5768 */
lsm6ds3tr_c_pedo_step_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)5769 int32_t lsm6ds3tr_c_pedo_step_reset_get(const stmdev_ctx_t *ctx,
5770 uint8_t *val)
5771 {
5772 lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
5773 int32_t ret;
5774
5775 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
5776 (uint8_t *)&ctrl10_c, 1);
5777 *val = ctrl10_c.pedo_rst_step;
5778
5779 return ret;
5780 }
5781
5782 /**
5783 * @brief Enable pedometer algorithm.[set]
5784 *
5785 * @param ctx Read / write interface definitions
5786 * @param val Change the values of pedo_en in reg CTRL10_C
5787 * @retval Interface status (MANDATORY: return 0 -> no Error).
5788 *
5789 */
lsm6ds3tr_c_pedo_sens_set(const stmdev_ctx_t * ctx,uint8_t val)5790 int32_t lsm6ds3tr_c_pedo_sens_set(const stmdev_ctx_t *ctx, uint8_t val)
5791 {
5792 lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
5793 int32_t ret;
5794
5795 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
5796 (uint8_t *)&ctrl10_c, 1);
5797
5798 if (ret == 0)
5799 {
5800 ctrl10_c.pedo_en = val;
5801
5802 if (val != 0x00U)
5803 {
5804 ctrl10_c.func_en = val;
5805 }
5806
5807 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C,
5808 (uint8_t *)&ctrl10_c, 1);
5809 }
5810
5811 return ret;
5812 }
5813
5814 /**
5815 * @brief pedo_sens: Enable pedometer algorithm.[get]
5816 *
5817 * @param ctx Read / write interface definitions
5818 * @param val Change the values of pedo_en in reg CTRL10_C
5819 * @retval Interface status (MANDATORY: return 0 -> no Error).
5820 *
5821 */
lsm6ds3tr_c_pedo_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)5822 int32_t lsm6ds3tr_c_pedo_sens_get(const stmdev_ctx_t *ctx, uint8_t *val)
5823 {
5824 lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
5825 int32_t ret;
5826
5827 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
5828 (uint8_t *)&ctrl10_c, 1);
5829 *val = ctrl10_c.pedo_en;
5830
5831 return ret;
5832 }
5833
5834 /**
5835 * @brief Minimum threshold to detect a peak. Default is 10h.[set]
5836 *
5837 * @param ctx Read / write interface definitions
5838 * @param val Change the values of ths_min in reg
5839 * CONFIG_PEDO_THS_MIN
5840 * @retval Interface status (MANDATORY: return 0 -> no Error).
5841 *
5842 */
lsm6ds3tr_c_pedo_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)5843 int32_t lsm6ds3tr_c_pedo_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
5844 {
5845 lsm6ds3tr_c_config_pedo_ths_min_t config_pedo_ths_min;
5846 int32_t ret;
5847
5848 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
5849
5850 if (ret == 0)
5851 {
5852 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN,
5853 (uint8_t *)&config_pedo_ths_min, 1);
5854
5855 if (ret == 0)
5856 {
5857 config_pedo_ths_min.ths_min = val;
5858 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN,
5859 (uint8_t *)&config_pedo_ths_min, 1);
5860
5861 if (ret == 0)
5862 {
5863 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
5864 }
5865 }
5866 }
5867
5868 return ret;
5869 }
5870
5871 /**
5872 * @brief Minimum threshold to detect a peak. Default is 10h.[get]
5873 *
5874 * @param ctx Read / write interface definitions
5875 * @param val Change the values of ths_min in reg CONFIG_PEDO_THS_MIN
5876 * @retval Interface status (MANDATORY: return 0 -> no Error).
5877 *
5878 */
lsm6ds3tr_c_pedo_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)5879 int32_t lsm6ds3tr_c_pedo_threshold_get(const stmdev_ctx_t *ctx,
5880 uint8_t *val)
5881 {
5882 lsm6ds3tr_c_config_pedo_ths_min_t config_pedo_ths_min;
5883 int32_t ret;
5884
5885 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
5886
5887 if (ret == 0)
5888 {
5889 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN,
5890 (uint8_t *)&config_pedo_ths_min, 1);
5891
5892 if (ret == 0)
5893 {
5894 *val = config_pedo_ths_min.ths_min;
5895 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
5896 }
5897 }
5898
5899 return ret;
5900 }
5901
5902 /**
5903 * @brief pedo_full_scale: Pedometer data range.[set]
5904 *
5905 * @param ctx Read / write interface definitions
5906 * @param val Change the values of pedo_fs in
5907 * reg CONFIG_PEDO_THS_MIN
5908 * @retval Interface status (MANDATORY: return 0 -> no Error).
5909 *
5910 */
lsm6ds3tr_c_pedo_full_scale_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_pedo_fs_t val)5911 int32_t lsm6ds3tr_c_pedo_full_scale_set(const stmdev_ctx_t *ctx,
5912 lsm6ds3tr_c_pedo_fs_t val)
5913 {
5914 lsm6ds3tr_c_config_pedo_ths_min_t config_pedo_ths_min;
5915 int32_t ret;
5916
5917 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
5918
5919 if (ret == 0)
5920 {
5921 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN,
5922 (uint8_t *)&config_pedo_ths_min, 1);
5923
5924 if (ret == 0)
5925 {
5926 config_pedo_ths_min.pedo_fs = (uint8_t) val;
5927 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN,
5928 (uint8_t *)&config_pedo_ths_min, 1);
5929
5930 if (ret == 0)
5931 {
5932 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
5933 }
5934 }
5935 }
5936
5937 return ret;
5938 }
5939
5940 /**
5941 * @brief Pedometer data range.[get]
5942 *
5943 * @param ctx Read / write interface definitions
5944 * @param val Get the values of pedo_fs in
5945 * reg CONFIG_PEDO_THS_MIN
5946 * @retval Interface status (MANDATORY: return 0 -> no Error).
5947 *
5948 */
lsm6ds3tr_c_pedo_full_scale_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_pedo_fs_t * val)5949 int32_t lsm6ds3tr_c_pedo_full_scale_get(const stmdev_ctx_t *ctx,
5950 lsm6ds3tr_c_pedo_fs_t *val)
5951 {
5952 lsm6ds3tr_c_config_pedo_ths_min_t config_pedo_ths_min;
5953 int32_t ret;
5954
5955 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
5956
5957 if (ret == 0)
5958 {
5959 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CONFIG_PEDO_THS_MIN,
5960 (uint8_t *)&config_pedo_ths_min, 1);
5961
5962 if (ret == 0)
5963 {
5964 switch (config_pedo_ths_min.pedo_fs)
5965 {
5966 case LSM6DS3TR_C_PEDO_AT_2g:
5967 *val = LSM6DS3TR_C_PEDO_AT_2g;
5968 break;
5969
5970 case LSM6DS3TR_C_PEDO_AT_4g:
5971 *val = LSM6DS3TR_C_PEDO_AT_4g;
5972 break;
5973
5974 default:
5975 *val = LSM6DS3TR_C_PEDO_FS_ND;
5976 break;
5977 }
5978
5979 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
5980 }
5981 }
5982
5983 return ret;
5984 }
5985
5986 /**
5987 * @brief Pedometer debounce configuration register (r/w).[set]
5988 *
5989 * @param ctx Read / write interface definitions
5990 * @param val Change the values of deb_step in reg PEDO_DEB_REG
5991 * @retval Interface status (MANDATORY: return 0 -> no Error).
5992 *
5993 */
lsm6ds3tr_c_pedo_debounce_steps_set(const stmdev_ctx_t * ctx,uint8_t val)5994 int32_t lsm6ds3tr_c_pedo_debounce_steps_set(const stmdev_ctx_t *ctx,
5995 uint8_t val)
5996 {
5997 lsm6ds3tr_c_pedo_deb_reg_t pedo_deb_reg;
5998 int32_t ret;
5999
6000 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
6001
6002 if (ret == 0)
6003 {
6004 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG,
6005 (uint8_t *)&pedo_deb_reg, 1);
6006
6007 if (ret == 0)
6008 {
6009 pedo_deb_reg.deb_step = val;
6010 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG,
6011 (uint8_t *)&pedo_deb_reg, 1);
6012
6013 if (ret == 0)
6014 {
6015 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
6016 }
6017 }
6018 }
6019
6020 return ret;
6021 }
6022
6023 /**
6024 * @brief Pedometer debounce configuration register (r/w).[get]
6025 *
6026 * @param ctx Read / write interface definitions
6027 * @param val Change the values of deb_step in reg PEDO_DEB_REG
6028 * @retval Interface status (MANDATORY: return 0 -> no Error).
6029 *
6030 */
lsm6ds3tr_c_pedo_debounce_steps_get(const stmdev_ctx_t * ctx,uint8_t * val)6031 int32_t lsm6ds3tr_c_pedo_debounce_steps_get(const stmdev_ctx_t *ctx,
6032 uint8_t *val)
6033 {
6034 lsm6ds3tr_c_pedo_deb_reg_t pedo_deb_reg;
6035 int32_t ret;
6036
6037 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
6038
6039 if (ret == 0)
6040 {
6041 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG,
6042 (uint8_t *)&pedo_deb_reg, 1);
6043
6044 if (ret == 0)
6045 {
6046 *val = pedo_deb_reg.deb_step;
6047 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
6048 }
6049 }
6050
6051 return ret;
6052 }
6053
6054 /**
6055 * @brief Debounce time. If the time between two consecutive steps is
6056 * greater than DEB_TIME*80ms, the debouncer is reactivated.
6057 * Default value: 01101[set]
6058 *
6059 * @param ctx Read / write interface definitions
6060 * @param val Change the values of deb_time in reg PEDO_DEB_REG
6061 * @retval Interface status (MANDATORY: return 0 -> no Error).
6062 *
6063 */
lsm6ds3tr_c_pedo_timeout_set(const stmdev_ctx_t * ctx,uint8_t val)6064 int32_t lsm6ds3tr_c_pedo_timeout_set(const stmdev_ctx_t *ctx, uint8_t val)
6065 {
6066 lsm6ds3tr_c_pedo_deb_reg_t pedo_deb_reg;
6067 int32_t ret;
6068
6069 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
6070
6071 if (ret == 0)
6072 {
6073 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG,
6074 (uint8_t *)&pedo_deb_reg, 1);
6075
6076 if (ret == 0)
6077 {
6078 pedo_deb_reg.deb_time = val;
6079 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG,
6080 (uint8_t *)&pedo_deb_reg, 1);
6081
6082 if (ret == 0)
6083 {
6084 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
6085 }
6086 }
6087 }
6088
6089 return ret;
6090 }
6091
6092 /**
6093 * @brief Debounce time. If the time between two consecutive steps is
6094 * greater than DEB_TIME*80ms, the debouncer is reactivated.
6095 * Default value: 01101[get]
6096 *
6097 * @param ctx Read / write interface definitions
6098 * @param val Change the values of deb_time in reg PEDO_DEB_REG
6099 * @retval Interface status (MANDATORY: return 0 -> no Error).
6100 *
6101 */
lsm6ds3tr_c_pedo_timeout_get(const stmdev_ctx_t * ctx,uint8_t * val)6102 int32_t lsm6ds3tr_c_pedo_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val)
6103 {
6104 lsm6ds3tr_c_pedo_deb_reg_t pedo_deb_reg;
6105 int32_t ret;
6106
6107 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
6108
6109 if (ret == 0)
6110 {
6111 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_PEDO_DEB_REG,
6112 (uint8_t *)&pedo_deb_reg, 1);
6113
6114 if (ret == 0)
6115 {
6116 *val = pedo_deb_reg.deb_time;
6117 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
6118 }
6119 }
6120
6121 return ret;
6122 }
6123
6124 /**
6125 * @brief Time period register for step detection on delta time (r/w).[set]
6126 *
6127 * @param ctx Read / write interface definitions
6128 * @param buff Buffer that contains data to write
6129 * @retval Interface status (MANDATORY: return 0 -> no Error).
6130 *
6131 */
lsm6ds3tr_c_pedo_steps_period_set(const stmdev_ctx_t * ctx,uint8_t * buff)6132 int32_t lsm6ds3tr_c_pedo_steps_period_set(const stmdev_ctx_t *ctx,
6133 uint8_t *buff)
6134 {
6135 int32_t ret;
6136
6137 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
6138
6139 if (ret == 0)
6140 {
6141 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_STEP_COUNT_DELTA, buff, 1);
6142
6143 if (ret == 0)
6144 {
6145 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
6146 }
6147 }
6148
6149 return ret;
6150 }
6151
6152 /**
6153 * @brief Time period register for step detection on delta time (r/w).[get]
6154 *
6155 * @param ctx Read / write interface definitions
6156 * @param buff Buffer that stores data read
6157 * @retval Interface status (MANDATORY: return 0 -> no Error).
6158 *
6159 */
lsm6ds3tr_c_pedo_steps_period_get(const stmdev_ctx_t * ctx,uint8_t * buff)6160 int32_t lsm6ds3tr_c_pedo_steps_period_get(const stmdev_ctx_t *ctx,
6161 uint8_t *buff)
6162 {
6163 int32_t ret;
6164
6165 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
6166
6167 if (ret == 0)
6168 {
6169 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_STEP_COUNT_DELTA, buff, 1);
6170
6171 if (ret == 0)
6172 {
6173 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
6174 }
6175 }
6176
6177 return ret;
6178 }
6179
6180 /**
6181 * @}
6182 *
6183 */
6184
6185 /**
6186 * @defgroup LSM6DS3TR_C_significant_motion
6187 * @brief This section groups all the functions that manage the
6188 * significant motion detection.
6189 * @{
6190 *
6191 */
6192
6193 /**
6194 * @brief Enable significant motion detection function.[set]
6195 *
6196 * @param ctx Read / write interface definitions
6197 * @param val Change the values of sign_motion_en in reg CTRL10_C
6198 * @retval Interface status (MANDATORY: return 0 -> no Error).
6199 *
6200 */
lsm6ds3tr_c_motion_sens_set(const stmdev_ctx_t * ctx,uint8_t val)6201 int32_t lsm6ds3tr_c_motion_sens_set(const stmdev_ctx_t *ctx, uint8_t val)
6202 {
6203 lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
6204 int32_t ret;
6205
6206 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
6207 (uint8_t *)&ctrl10_c, 1);
6208
6209 if (ret == 0)
6210 {
6211 ctrl10_c.sign_motion_en = val;
6212
6213 if (val != 0x00U)
6214 {
6215 ctrl10_c.func_en = val;
6216 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C,
6217 (uint8_t *)&ctrl10_c, 1);
6218 }
6219 }
6220
6221 return ret;
6222 }
6223
6224 /**
6225 * @brief Enable significant motion detection function.[get]
6226 *
6227 * @param ctx Read / write interface definitions
6228 * @param val Change the values of sign_motion_en in reg CTRL10_C
6229 * @retval Interface status (MANDATORY: return 0 -> no Error).
6230 *
6231 */
lsm6ds3tr_c_motion_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)6232 int32_t lsm6ds3tr_c_motion_sens_get(const stmdev_ctx_t *ctx, uint8_t *val)
6233 {
6234 lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
6235 int32_t ret;
6236
6237 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
6238 (uint8_t *)&ctrl10_c, 1);
6239 *val = ctrl10_c.sign_motion_en;
6240
6241 return ret;
6242 }
6243
6244 /**
6245 * @brief Significant motion threshold.[set]
6246 *
6247 * @param ctx Read / write interface definitions
6248 * @param buff Buffer that store significant motion threshold.
6249 * @retval Interface status (MANDATORY: return 0 -> no Error).
6250 *
6251 */
lsm6ds3tr_c_motion_threshold_set(const stmdev_ctx_t * ctx,uint8_t * buff)6252 int32_t lsm6ds3tr_c_motion_threshold_set(const stmdev_ctx_t *ctx,
6253 uint8_t *buff)
6254 {
6255 int32_t ret;
6256
6257 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
6258
6259 if (ret == 0)
6260 {
6261 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SM_THS, buff, 1);
6262
6263 if (ret == 0)
6264 {
6265 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
6266 }
6267 }
6268
6269 return ret;
6270 }
6271
6272 /**
6273 * @brief Significant motion threshold.[get]
6274 *
6275 * @param ctx Read / write interface definitions
6276 * @param buff Buffer that store significant motion threshold.
6277 * @retval Interface status (MANDATORY: return 0 -> no Error).
6278 *
6279 */
lsm6ds3tr_c_motion_threshold_get(const stmdev_ctx_t * ctx,uint8_t * buff)6280 int32_t lsm6ds3tr_c_motion_threshold_get(const stmdev_ctx_t *ctx,
6281 uint8_t *buff)
6282 {
6283 int32_t ret;
6284
6285 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
6286
6287 if (ret == 0)
6288 {
6289 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SM_THS, buff, 1);
6290
6291 if (ret == 0)
6292 {
6293 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
6294 }
6295 }
6296
6297 return ret;
6298 }
6299
6300 /**
6301 * @}
6302 *
6303 */
6304
6305 /**
6306 * @defgroup LSM6DS3TR_C_tilt_detection
6307 * @brief This section groups all the functions that manage the tilt
6308 * event detection.
6309 * @{
6310 *
6311 */
6312
6313 /**
6314 * @brief Enable tilt calculation.[set]
6315 *
6316 * @param ctx Read / write interface definitions
6317 * @param val Change the values of tilt_en in reg CTRL10_C
6318 * @retval Interface status (MANDATORY: return 0 -> no Error).
6319 *
6320 */
lsm6ds3tr_c_tilt_sens_set(const stmdev_ctx_t * ctx,uint8_t val)6321 int32_t lsm6ds3tr_c_tilt_sens_set(const stmdev_ctx_t *ctx, uint8_t val)
6322 {
6323 lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
6324 int32_t ret;
6325
6326 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
6327 (uint8_t *)&ctrl10_c, 1);
6328
6329 if (ret == 0)
6330 {
6331 ctrl10_c.tilt_en = val;
6332
6333 if (val != 0x00U)
6334 {
6335 ctrl10_c.func_en = val;
6336 }
6337
6338 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C,
6339 (uint8_t *)&ctrl10_c, 1);
6340 }
6341
6342 return ret;
6343 }
6344
6345 /**
6346 * @brief Enable tilt calculation.[get]
6347 *
6348 * @param ctx Read / write interface definitions
6349 * @param val Change the values of tilt_en in reg CTRL10_C
6350 * @retval Interface status (MANDATORY: return 0 -> no Error).
6351 *
6352 */
lsm6ds3tr_c_tilt_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)6353 int32_t lsm6ds3tr_c_tilt_sens_get(const stmdev_ctx_t *ctx, uint8_t *val)
6354 {
6355 lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
6356 int32_t ret;
6357
6358 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
6359 (uint8_t *)&ctrl10_c, 1);
6360 *val = ctrl10_c.tilt_en;
6361
6362 return ret;
6363 }
6364
6365 /**
6366 * @brief Enable tilt calculation.[set]
6367 *
6368 * @param ctx Read / write interface definitions
6369 * @param val Change the values of tilt_en in reg CTRL10_C
6370 * @retval Interface status (MANDATORY: return 0 -> no Error).
6371 *
6372 */
lsm6ds3tr_c_wrist_tilt_sens_set(const stmdev_ctx_t * ctx,uint8_t val)6373 int32_t lsm6ds3tr_c_wrist_tilt_sens_set(const stmdev_ctx_t *ctx,
6374 uint8_t val)
6375 {
6376 lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
6377 int32_t ret;
6378
6379 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
6380 (uint8_t *)&ctrl10_c, 1);
6381
6382 if (ret == 0)
6383 {
6384 ctrl10_c.wrist_tilt_en = val;
6385
6386 if (val != 0x00U)
6387 {
6388 ctrl10_c.func_en = val;
6389 }
6390
6391 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C,
6392 (uint8_t *)&ctrl10_c, 1);
6393 }
6394
6395 return ret;
6396 }
6397
6398 /**
6399 * @brief Enable tilt calculation.[get]
6400 *
6401 * @param ctx Read / write interface definitions
6402 * @param val Change the values of tilt_en in reg CTRL10_C
6403 * @retval Interface status (MANDATORY: return 0 -> no Error).
6404 *
6405 */
lsm6ds3tr_c_wrist_tilt_sens_get(const stmdev_ctx_t * ctx,uint8_t * val)6406 int32_t lsm6ds3tr_c_wrist_tilt_sens_get(const stmdev_ctx_t *ctx,
6407 uint8_t *val)
6408 {
6409 lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
6410 int32_t ret;
6411
6412 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
6413 (uint8_t *)&ctrl10_c, 1);
6414 *val = ctrl10_c.wrist_tilt_en;
6415
6416 return ret;
6417 }
6418
6419 /**
6420 * @brief Absolute Wrist Tilt latency register (r/w).
6421 * Absolute wrist tilt latency parameters.
6422 * 1 LSB = 40 ms. Default value: 0Fh (600 ms).[set]
6423 *
6424 * @param ctx Read / write interface definitions
6425 * @param buff Buffer that contains data to write
6426 * @retval Interface status (MANDATORY: return 0 -> no Error).
6427 *
6428 */
lsm6ds3tr_c_tilt_latency_set(const stmdev_ctx_t * ctx,uint8_t * buff)6429 int32_t lsm6ds3tr_c_tilt_latency_set(const stmdev_ctx_t *ctx, uint8_t *buff)
6430 {
6431 int32_t ret;
6432
6433 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B);
6434
6435 if (ret == 0)
6436 {
6437 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_LAT, buff, 1);
6438
6439 if (ret == 0)
6440 {
6441 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
6442 }
6443 }
6444
6445 return ret;
6446 }
6447
6448 /**
6449 * @brief Absolute Wrist Tilt latency register (r/w).
6450 * Absolute wrist tilt latency parameters.
6451 * 1 LSB = 40 ms. Default value: 0Fh (600 ms).[get]
6452 *
6453 * @param ctx Read / write interface definitions
6454 * @param buff Buffer that stores data read
6455 * @retval Interface status (MANDATORY: return 0 -> no Error).
6456 *
6457 */
lsm6ds3tr_c_tilt_latency_get(const stmdev_ctx_t * ctx,uint8_t * buff)6458 int32_t lsm6ds3tr_c_tilt_latency_get(const stmdev_ctx_t *ctx, uint8_t *buff)
6459 {
6460 int32_t ret;
6461
6462 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B);
6463
6464 if (ret == 0)
6465 {
6466 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_LAT, buff, 1);
6467
6468 if (ret == 0)
6469 {
6470 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
6471 }
6472 }
6473
6474 return ret;
6475 }
6476
6477 /**
6478 * @brief Absolute Wrist Tilt threshold register(r/w).
6479 * Absolute wrist tilt threshold parameters.
6480 * 1 LSB = 15.625 mg.Default value: 20h (500 mg).[set]
6481 *
6482 * @param ctx Read / write interface definitions
6483 * @param buff Buffer that contains data to write
6484 * @retval Interface status (MANDATORY: return 0 -> no Error).
6485 *
6486 */
lsm6ds3tr_c_tilt_threshold_set(const stmdev_ctx_t * ctx,uint8_t * buff)6487 int32_t lsm6ds3tr_c_tilt_threshold_set(const stmdev_ctx_t *ctx,
6488 uint8_t *buff)
6489 {
6490 int32_t ret;
6491
6492 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B);
6493
6494 if (ret == 0)
6495 {
6496 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_THS, buff, 1);
6497
6498 if (ret == 0)
6499 {
6500 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
6501 }
6502 }
6503
6504 return ret;
6505 }
6506
6507 /**
6508 * @brief Absolute Wrist Tilt threshold register(r/w).
6509 * Absolute wrist tilt threshold parameters.
6510 * 1 LSB = 15.625 mg.Default value: 20h (500 mg).[get]
6511 *
6512 * @param ctx Read / write interface definitions
6513 * @param buff Buffer that stores data read
6514 * @retval Interface status (MANDATORY: return 0 -> no Error).
6515 *
6516 */
lsm6ds3tr_c_tilt_threshold_get(const stmdev_ctx_t * ctx,uint8_t * buff)6517 int32_t lsm6ds3tr_c_tilt_threshold_get(const stmdev_ctx_t *ctx,
6518 uint8_t *buff)
6519 {
6520 int32_t ret;
6521
6522 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B);
6523
6524 if (ret == 0)
6525 {
6526 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_THS, buff, 1);
6527
6528 if (ret == 0)
6529 {
6530 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
6531 }
6532 }
6533
6534 return ret;
6535 }
6536
6537 /**
6538 * @brief Absolute Wrist Tilt mask register (r/w).[set]
6539 *
6540 * @param ctx Read / write interface definitions
6541 * @param val Registers A_WRIST_TILT_MASK
6542 * @retval Interface status (MANDATORY: return 0 -> no Error).
6543 *
6544 */
lsm6ds3tr_c_tilt_src_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_a_wrist_tilt_mask_t * val)6545 int32_t lsm6ds3tr_c_tilt_src_set(const stmdev_ctx_t *ctx,
6546 lsm6ds3tr_c_a_wrist_tilt_mask_t *val)
6547 {
6548 int32_t ret;
6549
6550 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B);
6551
6552 if (ret == 0)
6553 {
6554 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_MASK,
6555 (uint8_t *) val, 1);
6556
6557 if (ret == 0)
6558 {
6559 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
6560 }
6561 }
6562
6563 return ret;
6564 }
6565
6566 /**
6567 * @brief Absolute Wrist Tilt mask register (r/w).[get]
6568 *
6569 * @param ctx Read / write interface definitions
6570 * @param val Registers A_WRIST_TILT_MASK
6571 * @retval Interface status (MANDATORY: return 0 -> no Error).
6572 *
6573 */
lsm6ds3tr_c_tilt_src_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_a_wrist_tilt_mask_t * val)6574 int32_t lsm6ds3tr_c_tilt_src_get(const stmdev_ctx_t *ctx,
6575 lsm6ds3tr_c_a_wrist_tilt_mask_t *val)
6576 {
6577 int32_t ret;
6578
6579 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_B);
6580
6581 if (ret == 0)
6582 {
6583 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_A_WRIST_TILT_MASK,
6584 (uint8_t *) val, 1);
6585
6586 if (ret == 0)
6587 {
6588 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
6589 }
6590 }
6591
6592 return ret;
6593 }
6594
6595 /**
6596 * @}
6597 *
6598 */
6599
6600 /**
6601 * @defgroup LSM6DS3TR_C_ magnetometer_sensor
6602 * @brief This section groups all the functions that manage additional
6603 * magnetometer sensor.
6604 * @{
6605 *
6606 */
6607
6608 /**
6609 * @brief Enable soft-iron correction algorithm for magnetometer.[set]
6610 *
6611 * @param ctx Read / write interface definitions
6612 * @param val Change the values of soft_en in reg CTRL9_XL
6613 * @retval Interface status (MANDATORY: return 0 -> no Error).
6614 *
6615 */
lsm6ds3tr_c_mag_soft_iron_set(const stmdev_ctx_t * ctx,uint8_t val)6616 int32_t lsm6ds3tr_c_mag_soft_iron_set(const stmdev_ctx_t *ctx, uint8_t val)
6617 {
6618 lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
6619 int32_t ret;
6620
6621 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
6622 (uint8_t *)&ctrl9_xl, 1);
6623
6624 if (ret == 0)
6625 {
6626 ctrl9_xl.soft_en = val;
6627 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
6628 (uint8_t *)&ctrl9_xl, 1);
6629 }
6630
6631 return ret;
6632 }
6633
6634 /**
6635 * @brief Enable soft-iron correction algorithm for magnetometer.[get]
6636 *
6637 * @param ctx Read / write interface definitions
6638 * @param val Change the values of soft_en in reg CTRL9_XL
6639 * @retval Interface status (MANDATORY: return 0 -> no Error).
6640 *
6641 */
lsm6ds3tr_c_mag_soft_iron_get(const stmdev_ctx_t * ctx,uint8_t * val)6642 int32_t lsm6ds3tr_c_mag_soft_iron_get(const stmdev_ctx_t *ctx, uint8_t *val)
6643 {
6644 lsm6ds3tr_c_ctrl9_xl_t ctrl9_xl;
6645 int32_t ret;
6646
6647 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL9_XL,
6648 (uint8_t *)&ctrl9_xl, 1);
6649 *val = ctrl9_xl.soft_en;
6650
6651 return ret;
6652 }
6653
6654 /**
6655 * @brief Enable hard-iron correction algorithm for magnetometer.[set]
6656 *
6657 * @param ctx Read / write interface definitions
6658 * @param val Change the values of iron_en in reg MASTER_CONFIG
6659 * @retval Interface status (MANDATORY: return 0 -> no Error).
6660 *
6661 */
lsm6ds3tr_c_mag_hard_iron_set(const stmdev_ctx_t * ctx,uint8_t val)6662 int32_t lsm6ds3tr_c_mag_hard_iron_set(const stmdev_ctx_t *ctx, uint8_t val)
6663 {
6664 lsm6ds3tr_c_master_config_t master_config;
6665 lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
6666 int32_t ret;
6667
6668 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
6669 (uint8_t *)&master_config, 1);
6670
6671 if (ret == 0)
6672 {
6673 master_config.iron_en = val;
6674 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
6675 (uint8_t *)&master_config, 1);
6676
6677 if (ret == 0)
6678 {
6679 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
6680 (uint8_t *)&ctrl10_c, 1);
6681
6682 if (ret == 0)
6683 {
6684 if (val != 0x00U)
6685 {
6686 ctrl10_c.func_en = val;
6687 }
6688
6689 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C,
6690 (uint8_t *)&ctrl10_c, 1);
6691 }
6692 }
6693 }
6694
6695 return ret;
6696 }
6697
6698 /**
6699 * @brief Enable hard-iron correction algorithm for magnetometer.[get]
6700 *
6701 * @param ctx Read / write interface definitions
6702 * @param val Change the values of iron_en in reg MASTER_CONFIG
6703 * @retval Interface status (MANDATORY: return 0 -> no Error).
6704 *
6705 */
lsm6ds3tr_c_mag_hard_iron_get(const stmdev_ctx_t * ctx,uint8_t * val)6706 int32_t lsm6ds3tr_c_mag_hard_iron_get(const stmdev_ctx_t *ctx, uint8_t *val)
6707 {
6708 lsm6ds3tr_c_master_config_t master_config;
6709 int32_t ret;
6710
6711 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
6712 (uint8_t *)&master_config, 1);
6713 *val = master_config.iron_en;
6714
6715 return ret;
6716 }
6717
6718 /**
6719 * @brief Soft iron 3x3 matrix. Value are expressed in sign-module format.
6720 * (Es. SVVVVVVVb where S is the sign 0/+1/- and V is the value).[set]
6721 *
6722 * @param ctx Read / write interface definitions
6723 * @param buff Buffer that contains data to write
6724 * @retval Interface status (MANDATORY: return 0 -> no Error).
6725 *
6726 */
lsm6ds3tr_c_mag_soft_iron_mat_set(const stmdev_ctx_t * ctx,uint8_t * buff)6727 int32_t lsm6ds3tr_c_mag_soft_iron_mat_set(const stmdev_ctx_t *ctx,
6728 uint8_t *buff)
6729 {
6730 int32_t ret;
6731
6732 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
6733
6734 if (ret == 0)
6735 {
6736 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MAG_SI_XX, buff, 9);
6737
6738 if (ret == 0)
6739 {
6740 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
6741 }
6742 }
6743
6744 return ret;
6745 }
6746
6747 /**
6748 * @brief Soft iron 3x3 matrix. Value are expressed in sign-module format.
6749 * (Es. SVVVVVVVb where S is the sign 0/+1/- and V is the value).[get]
6750 *
6751 * @param ctx Read / write interface definitions
6752 * @param buff Buffer that stores data read
6753 * @retval Interface status (MANDATORY: return 0 -> no Error).
6754 *
6755 */
lsm6ds3tr_c_mag_soft_iron_mat_get(const stmdev_ctx_t * ctx,uint8_t * buff)6756 int32_t lsm6ds3tr_c_mag_soft_iron_mat_get(const stmdev_ctx_t *ctx,
6757 uint8_t *buff)
6758 {
6759 int32_t ret;
6760
6761 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
6762
6763 if (ret == 0)
6764 {
6765 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MAG_SI_XX, buff, 9);
6766
6767 if (ret == 0)
6768 {
6769 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
6770 }
6771 }
6772
6773 return ret;
6774 }
6775
6776 /**
6777 * @brief Offset for hard-iron compensation register (r/w). The value is
6778 * expressed as a 16-bit word in two’s complement.[set]
6779 *
6780 * @param ctx Read / write interface definitions
6781 * @param buff Buffer that contains data to write
6782 * @retval Interface status (MANDATORY: return 0 -> no Error).
6783 *
6784 */
lsm6ds3tr_c_mag_offset_set(const stmdev_ctx_t * ctx,int16_t * val)6785 int32_t lsm6ds3tr_c_mag_offset_set(const stmdev_ctx_t *ctx, int16_t *val)
6786 {
6787 uint8_t buff[6];
6788 int32_t ret;
6789
6790 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
6791
6792 if (ret == 0)
6793 {
6794 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
6795 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
6796 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
6797 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
6798 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
6799 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
6800 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MAG_OFFX_L, buff, 6);
6801
6802 if (ret == 0)
6803 {
6804 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
6805 }
6806 }
6807
6808 return ret;
6809 }
6810
6811 /**
6812 * @brief Offset for hard-iron compensation register(r/w).
6813 * The value is expressed as a 16-bit word in two’s complement.[get]
6814 *
6815 * @param ctx Read / write interface definitions
6816 * @param buff Buffer that stores data read
6817 * @retval Interface status (MANDATORY: return 0 -> no Error).
6818 *
6819 */
lsm6ds3tr_c_mag_offset_get(const stmdev_ctx_t * ctx,int16_t * val)6820 int32_t lsm6ds3tr_c_mag_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
6821 {
6822 uint8_t buff[6];
6823 int32_t ret;
6824
6825 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
6826
6827 if (ret == 0)
6828 {
6829 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MAG_OFFX_L, buff, 6);
6830
6831 if (ret == 0)
6832 {
6833 val[0] = (int16_t)buff[1];
6834 val[0] = (val[0] * 256) + (int16_t)buff[0];
6835 val[1] = (int16_t)buff[3];
6836 val[1] = (val[1] * 256) + (int16_t)buff[2];
6837 val[2] = (int16_t)buff[5];
6838 val[2] = (val[2] * 256) + (int16_t)buff[4];
6839 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
6840 }
6841 }
6842
6843 return ret;
6844 }
6845
6846 /**
6847 * @}
6848 *
6849 */
6850
6851 /**
6852 * @defgroup LSM6DS3TR_C_Sensor_hub
6853 * @brief This section groups all the functions that manage the sensor
6854 * hub functionality.
6855 * @{
6856 *
6857 */
6858
6859 /**
6860 * @brief Enable function.[set]
6861 *
6862 * @param ctx Read / write interface definitions
6863 * @param val Change the values func_en
6864 * @retval Interface status (MANDATORY: return 0 -> no Error).
6865 *
6866 */
lsm6ds3tr_c_func_en_set(const stmdev_ctx_t * ctx,uint8_t val)6867 int32_t lsm6ds3tr_c_func_en_set(const stmdev_ctx_t *ctx, uint8_t val)
6868 {
6869 lsm6ds3tr_c_ctrl10_c_t ctrl10_c;
6870 int32_t ret;
6871
6872 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_CTRL10_C,
6873 (uint8_t *)&ctrl10_c, 1);
6874
6875 if (ret == 0)
6876 {
6877 ctrl10_c.func_en = val;
6878 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_CTRL10_C,
6879 (uint8_t *)&ctrl10_c, 1);
6880 }
6881
6882 return ret;
6883 }
6884
6885 /**
6886 * @brief Sensor synchronization time frame with the step of 500 ms and
6887 * full range of 5s. Unsigned 8-bit.[set]
6888 *
6889 * @param ctx Read / write interface definitions
6890 * @param val Change the values of tph in reg SENSOR_SYNC_TIME_FRAME
6891 * @retval Interface status (MANDATORY: return 0 -> no Error).
6892 *
6893 */
lsm6ds3tr_c_sh_sync_sens_frame_set(const stmdev_ctx_t * ctx,uint8_t val)6894 int32_t lsm6ds3tr_c_sh_sync_sens_frame_set(const stmdev_ctx_t *ctx,
6895 uint8_t val)
6896 {
6897 lsm6ds3tr_c_sensor_sync_time_frame_t sensor_sync_time_frame;
6898 int32_t ret;
6899
6900 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_TIME_FRAME,
6901 (uint8_t *)&sensor_sync_time_frame, 1);
6902
6903 if (ret == 0)
6904 {
6905 sensor_sync_time_frame.tph = val;
6906 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_TIME_FRAME,
6907 (uint8_t *)&sensor_sync_time_frame, 1);
6908 }
6909
6910 return ret;
6911 }
6912
6913 /**
6914 * @brief Sensor synchronization time frame with the step of 500 ms and
6915 * full range of 5s. Unsigned 8-bit.[get]
6916 *
6917 * @param ctx Read / write interface definitions
6918 * @param val Change the values of tph in reg SENSOR_SYNC_TIME_FRAME
6919 * @retval Interface status (MANDATORY: return 0 -> no Error).
6920 *
6921 */
lsm6ds3tr_c_sh_sync_sens_frame_get(const stmdev_ctx_t * ctx,uint8_t * val)6922 int32_t lsm6ds3tr_c_sh_sync_sens_frame_get(const stmdev_ctx_t *ctx,
6923 uint8_t *val)
6924 {
6925 lsm6ds3tr_c_sensor_sync_time_frame_t sensor_sync_time_frame;
6926 int32_t ret;
6927
6928 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_TIME_FRAME,
6929 (uint8_t *)&sensor_sync_time_frame, 1);
6930 *val = sensor_sync_time_frame.tph;
6931
6932 return ret;
6933 }
6934
6935 /**
6936 * @brief Resolution ratio of error code for sensor synchronization.[set]
6937 *
6938 * @param ctx Read / write interface definitions
6939 * @param val Change the values of rr in reg SENSOR_SYNC_RES_RATIO
6940 * @retval Interface status (MANDATORY: return 0 -> no Error).
6941 *
6942 */
lsm6ds3tr_c_sh_sync_sens_ratio_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_rr_t val)6943 int32_t lsm6ds3tr_c_sh_sync_sens_ratio_set(const stmdev_ctx_t *ctx,
6944 lsm6ds3tr_c_rr_t val)
6945 {
6946 lsm6ds3tr_c_sensor_sync_res_ratio_t sensor_sync_res_ratio;
6947 int32_t ret;
6948
6949 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_RES_RATIO,
6950 (uint8_t *)&sensor_sync_res_ratio, 1);
6951
6952 if (ret == 0)
6953 {
6954 sensor_sync_res_ratio.rr = (uint8_t) val;
6955 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_RES_RATIO,
6956 (uint8_t *)&sensor_sync_res_ratio, 1);
6957 }
6958
6959 return ret;
6960 }
6961
6962 /**
6963 * @brief Resolution ratio of error code for sensor synchronization.[get]
6964 *
6965 * @param ctx Read / write interface definitions
6966 * @param val Get the values of rr in reg SENSOR_SYNC_RES_RATIO
6967 * @retval Interface status (MANDATORY: return 0 -> no Error).
6968 *
6969 */
lsm6ds3tr_c_sh_sync_sens_ratio_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_rr_t * val)6970 int32_t lsm6ds3tr_c_sh_sync_sens_ratio_get(const stmdev_ctx_t *ctx,
6971 lsm6ds3tr_c_rr_t *val)
6972 {
6973 lsm6ds3tr_c_sensor_sync_res_ratio_t sensor_sync_res_ratio;
6974 int32_t ret;
6975
6976 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSOR_SYNC_RES_RATIO,
6977 (uint8_t *)&sensor_sync_res_ratio, 1);
6978
6979 switch (sensor_sync_res_ratio.rr)
6980 {
6981 case LSM6DS3TR_C_RES_RATIO_2_11:
6982 *val = LSM6DS3TR_C_RES_RATIO_2_11;
6983 break;
6984
6985 case LSM6DS3TR_C_RES_RATIO_2_12:
6986 *val = LSM6DS3TR_C_RES_RATIO_2_12;
6987 break;
6988
6989 case LSM6DS3TR_C_RES_RATIO_2_13:
6990 *val = LSM6DS3TR_C_RES_RATIO_2_13;
6991 break;
6992
6993 case LSM6DS3TR_C_RES_RATIO_2_14:
6994 *val = LSM6DS3TR_C_RES_RATIO_2_14;
6995 break;
6996
6997 default:
6998 *val = LSM6DS3TR_C_RES_RATIO_ND;
6999 break;
7000 }
7001
7002 return ret;
7003 }
7004
7005 /**
7006 * @brief Sensor hub I2C master enable.[set]
7007 *
7008 * @param ctx Read / write interface definitions
7009 * @param val Change the values of master_on in reg MASTER_CONFIG
7010 * @retval Interface status (MANDATORY: return 0 -> no Error).
7011 *
7012 */
lsm6ds3tr_c_sh_master_set(const stmdev_ctx_t * ctx,uint8_t val)7013 int32_t lsm6ds3tr_c_sh_master_set(const stmdev_ctx_t *ctx, uint8_t val)
7014 {
7015 lsm6ds3tr_c_master_config_t master_config;
7016 int32_t ret;
7017
7018 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
7019 (uint8_t *)&master_config, 1);
7020
7021 if (ret == 0)
7022 {
7023 master_config.master_on = val;
7024 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
7025 (uint8_t *)&master_config, 1);
7026 }
7027
7028 return ret;
7029 }
7030
7031 /**
7032 * @brief Sensor hub I2C master enable.[get]
7033 *
7034 * @param ctx Read / write interface definitions
7035 * @param val Change the values of master_on in reg MASTER_CONFIG
7036 * @retval Interface status (MANDATORY: return 0 -> no Error).
7037 *
7038 */
lsm6ds3tr_c_sh_master_get(const stmdev_ctx_t * ctx,uint8_t * val)7039 int32_t lsm6ds3tr_c_sh_master_get(const stmdev_ctx_t *ctx, uint8_t *val)
7040 {
7041 lsm6ds3tr_c_master_config_t master_config;
7042 int32_t ret;
7043
7044 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
7045 (uint8_t *)&master_config, 1);
7046 *val = master_config.master_on;
7047
7048 return ret;
7049 }
7050
7051 /**
7052 * @brief I2C interface pass-through.[set]
7053 *
7054 * @param ctx Read / write interface definitions
7055 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
7056 * @retval Interface status (MANDATORY: return 0 -> no Error).
7057 *
7058 */
lsm6ds3tr_c_sh_pass_through_set(const stmdev_ctx_t * ctx,uint8_t val)7059 int32_t lsm6ds3tr_c_sh_pass_through_set(const stmdev_ctx_t *ctx,
7060 uint8_t val)
7061 {
7062 lsm6ds3tr_c_master_config_t master_config;
7063 int32_t ret;
7064
7065 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
7066 (uint8_t *)&master_config, 1);
7067
7068 if (ret == 0)
7069 {
7070 master_config.pass_through_mode = val;
7071 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
7072 (uint8_t *)&master_config, 1);
7073 }
7074
7075 return ret;
7076 }
7077
7078 /**
7079 * @brief I2C interface pass-through.[get]
7080 *
7081 * @param ctx Read / write interface definitions
7082 * @param val Change the values of pass_through_mode in reg MASTER_CONFIG
7083 * @retval Interface status (MANDATORY: return 0 -> no Error).
7084 *
7085 */
lsm6ds3tr_c_sh_pass_through_get(const stmdev_ctx_t * ctx,uint8_t * val)7086 int32_t lsm6ds3tr_c_sh_pass_through_get(const stmdev_ctx_t *ctx,
7087 uint8_t *val)
7088 {
7089 lsm6ds3tr_c_master_config_t master_config;
7090 int32_t ret;
7091
7092 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
7093 (uint8_t *)&master_config, 1);
7094 *val = master_config.pass_through_mode;
7095
7096 return ret;
7097 }
7098
7099 /**
7100 * @brief Master I2C pull-up enable/disable.[set]
7101 *
7102 * @param ctx Read / write interface definitions
7103 * @param val Change the values of pull_up_en in reg MASTER_CONFIG
7104 * @retval Interface status (MANDATORY: return 0 -> no Error).
7105 *
7106 */
lsm6ds3tr_c_sh_pin_mode_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_pull_up_en_t val)7107 int32_t lsm6ds3tr_c_sh_pin_mode_set(const stmdev_ctx_t *ctx,
7108 lsm6ds3tr_c_pull_up_en_t val)
7109 {
7110 lsm6ds3tr_c_master_config_t master_config;
7111 int32_t ret;
7112
7113 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
7114 (uint8_t *)&master_config, 1);
7115
7116 if (ret == 0)
7117 {
7118 master_config.pull_up_en = (uint8_t) val;
7119 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
7120 (uint8_t *)&master_config, 1);
7121 }
7122
7123 return ret;
7124 }
7125
7126 /**
7127 * @brief Master I2C pull-up enable/disable.[get]
7128 *
7129 * @param ctx Read / write interface definitions
7130 * @param val Get the values of pull_up_en in reg MASTER_CONFIG
7131 * @retval Interface status (MANDATORY: return 0 -> no Error).
7132 *
7133 */
lsm6ds3tr_c_sh_pin_mode_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_pull_up_en_t * val)7134 int32_t lsm6ds3tr_c_sh_pin_mode_get(const stmdev_ctx_t *ctx,
7135 lsm6ds3tr_c_pull_up_en_t *val)
7136 {
7137 lsm6ds3tr_c_master_config_t master_config;
7138 int32_t ret;
7139
7140 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
7141 (uint8_t *)&master_config, 1);
7142
7143 switch (master_config.pull_up_en)
7144 {
7145 case LSM6DS3TR_C_EXT_PULL_UP:
7146 *val = LSM6DS3TR_C_EXT_PULL_UP;
7147 break;
7148
7149 case LSM6DS3TR_C_INTERNAL_PULL_UP:
7150 *val = LSM6DS3TR_C_INTERNAL_PULL_UP;
7151 break;
7152
7153 default:
7154 *val = LSM6DS3TR_C_SH_PIN_MODE;
7155 break;
7156 }
7157
7158 return ret;
7159 }
7160
7161 /**
7162 * @brief Sensor hub trigger signal selection.[set]
7163 *
7164 * @param ctx Read / write interface definitions
7165 * @param val Change the values of start_config in reg MASTER_CONFIG
7166 * @retval Interface status (MANDATORY: return 0 -> no Error).
7167 *
7168 */
lsm6ds3tr_c_sh_syncro_mode_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_start_config_t val)7169 int32_t lsm6ds3tr_c_sh_syncro_mode_set(const stmdev_ctx_t *ctx,
7170 lsm6ds3tr_c_start_config_t val)
7171 {
7172 lsm6ds3tr_c_master_config_t master_config;
7173 int32_t ret;
7174
7175 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
7176 (uint8_t *)&master_config, 1);
7177
7178 if (ret == 0)
7179 {
7180 master_config.start_config = (uint8_t)val;
7181 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
7182 (uint8_t *)&master_config, 1);
7183 }
7184
7185 return ret;
7186 }
7187
7188 /**
7189 * @brief Sensor hub trigger signal selection.[get]
7190 *
7191 * @param ctx Read / write interface definitions
7192 * @param val Get the values of start_config in reg MASTER_CONFIG
7193 * @retval Interface status (MANDATORY: return 0 -> no Error).
7194 *
7195 */
lsm6ds3tr_c_sh_syncro_mode_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_start_config_t * val)7196 int32_t lsm6ds3tr_c_sh_syncro_mode_get(const stmdev_ctx_t *ctx,
7197 lsm6ds3tr_c_start_config_t *val)
7198 {
7199 lsm6ds3tr_c_master_config_t master_config;
7200 int32_t ret;
7201
7202 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
7203 (uint8_t *)&master_config, 1);
7204
7205 switch (master_config.start_config)
7206 {
7207 case LSM6DS3TR_C_XL_GY_DRDY:
7208 *val = LSM6DS3TR_C_XL_GY_DRDY;
7209 break;
7210
7211 case LSM6DS3TR_C_EXT_ON_INT2_PIN:
7212 *val = LSM6DS3TR_C_EXT_ON_INT2_PIN;
7213 break;
7214
7215 default:
7216 *val = LSM6DS3TR_C_SH_SYNCRO_ND;
7217 break;
7218 }
7219
7220 return ret;
7221 }
7222
7223 /**
7224 * @brief Manage the Master DRDY signal on INT1 pad.[set]
7225 *
7226 * @param ctx Read / write interface definitions
7227 * @param val Change the values of drdy_on_int1 in reg MASTER_CONFIG
7228 * @retval Interface status (MANDATORY: return 0 -> no Error).
7229 *
7230 */
lsm6ds3tr_c_sh_drdy_on_int1_set(const stmdev_ctx_t * ctx,uint8_t val)7231 int32_t lsm6ds3tr_c_sh_drdy_on_int1_set(const stmdev_ctx_t *ctx,
7232 uint8_t val)
7233 {
7234 lsm6ds3tr_c_master_config_t master_config;
7235 int32_t ret;
7236
7237 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
7238 (uint8_t *)&master_config, 1);
7239
7240 if (ret == 0)
7241 {
7242 master_config.drdy_on_int1 = val;
7243 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
7244 (uint8_t *)&master_config, 1);
7245 }
7246
7247 return ret;
7248 }
7249
7250 /**
7251 * @brief Manage the Master DRDY signal on INT1 pad.[get]
7252 *
7253 * @param ctx Read / write interface definitions
7254 * @param val Change the values of drdy_on_int1 in reg MASTER_CONFIG
7255 * @retval Interface status (MANDATORY: return 0 -> no Error).
7256 *
7257 */
lsm6ds3tr_c_sh_drdy_on_int1_get(const stmdev_ctx_t * ctx,uint8_t * val)7258 int32_t lsm6ds3tr_c_sh_drdy_on_int1_get(const stmdev_ctx_t *ctx,
7259 uint8_t *val)
7260 {
7261 lsm6ds3tr_c_master_config_t master_config;
7262 int32_t ret;
7263
7264 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CONFIG,
7265 (uint8_t *)&master_config, 1);
7266 *val = master_config.drdy_on_int1;
7267
7268 return ret;
7269 }
7270
7271 /**
7272 * @brief Sensor hub output registers.[get]
7273 *
7274 * @param ctx Read / write interface definitions
7275 * @param val Structure of registers from SENSORHUB1_REG
7276 * @retval Interface status (MANDATORY: return 0 -> no Error).
7277 *
7278 */
lsm6ds3tr_c_sh_read_data_raw_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_emb_sh_read_t * val)7279 int32_t lsm6ds3tr_c_sh_read_data_raw_get(const stmdev_ctx_t *ctx,
7280 lsm6ds3tr_c_emb_sh_read_t *val)
7281 {
7282 int32_t ret;
7283
7284 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSORHUB1_REG,
7285 (uint8_t *) & (val->sh_byte_1), 12);
7286
7287 if (ret == 0)
7288 {
7289 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENSORHUB13_REG,
7290 (uint8_t *) & (val->sh_byte_13), 6);
7291 }
7292
7293 return ret;
7294 }
7295
7296 /**
7297 * @brief Master command code used for stamping for sensor sync.[set]
7298 *
7299 * @param ctx Read / write interface definitions
7300 * @param val Change the values of master_cmd_code in
7301 * reg MASTER_CMD_CODE
7302 * @retval Interface status (MANDATORY: return 0 -> no Error).
7303 *
7304 */
lsm6ds3tr_c_sh_cmd_sens_sync_set(const stmdev_ctx_t * ctx,uint8_t val)7305 int32_t lsm6ds3tr_c_sh_cmd_sens_sync_set(const stmdev_ctx_t *ctx,
7306 uint8_t val)
7307 {
7308 lsm6ds3tr_c_master_cmd_code_t master_cmd_code;
7309 int32_t ret;
7310
7311 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CMD_CODE,
7312 (uint8_t *)&master_cmd_code, 1);
7313
7314 if (ret == 0)
7315 {
7316 master_cmd_code.master_cmd_code = val;
7317 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_MASTER_CMD_CODE,
7318 (uint8_t *)&master_cmd_code, 1);
7319 }
7320
7321 return ret;
7322 }
7323
7324 /**
7325 * @brief Master command code used for stamping for sensor sync.[get]
7326 *
7327 * @param ctx Read / write interface definitions
7328 * @param val Change the values of master_cmd_code in
7329 * reg MASTER_CMD_CODE
7330 * @retval Interface status (MANDATORY: return 0 -> no Error).
7331 *
7332 */
lsm6ds3tr_c_sh_cmd_sens_sync_get(const stmdev_ctx_t * ctx,uint8_t * val)7333 int32_t lsm6ds3tr_c_sh_cmd_sens_sync_get(const stmdev_ctx_t *ctx,
7334 uint8_t *val)
7335 {
7336 lsm6ds3tr_c_master_cmd_code_t master_cmd_code;
7337 int32_t ret;
7338
7339 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_MASTER_CMD_CODE,
7340 (uint8_t *)&master_cmd_code, 1);
7341 *val = master_cmd_code.master_cmd_code;
7342
7343 return ret;
7344 }
7345
7346 /**
7347 * @brief Error code used for sensor synchronization.[set]
7348 *
7349 * @param ctx Read / write interface definitions
7350 * @param val Change the values of error_code in
7351 * reg SENS_SYNC_SPI_ERROR_CODE.
7352 * @retval Interface status (MANDATORY: return 0 -> no Error).
7353 *
7354 */
lsm6ds3tr_c_sh_spi_sync_error_set(const stmdev_ctx_t * ctx,uint8_t val)7355 int32_t lsm6ds3tr_c_sh_spi_sync_error_set(const stmdev_ctx_t *ctx,
7356 uint8_t val)
7357 {
7358 lsm6ds3tr_c_sens_sync_spi_error_code_t sens_sync_spi_error_code;
7359 int32_t ret;
7360
7361 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENS_SYNC_SPI_ERROR_CODE,
7362 (uint8_t *)&sens_sync_spi_error_code, 1);
7363
7364 if (ret == 0)
7365 {
7366 sens_sync_spi_error_code.error_code = val;
7367 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SENS_SYNC_SPI_ERROR_CODE,
7368 (uint8_t *)&sens_sync_spi_error_code, 1);
7369 }
7370
7371 return ret;
7372 }
7373
7374 /**
7375 * @brief Error code used for sensor synchronization.[get]
7376 *
7377 * @param ctx Read / write interface definitions
7378 * @param val Change the values of error_code in
7379 * reg SENS_SYNC_SPI_ERROR_CODE.
7380 * @retval Interface status (MANDATORY: return 0 -> no Error).
7381 *
7382 */
lsm6ds3tr_c_sh_spi_sync_error_get(const stmdev_ctx_t * ctx,uint8_t * val)7383 int32_t lsm6ds3tr_c_sh_spi_sync_error_get(const stmdev_ctx_t *ctx,
7384 uint8_t *val)
7385 {
7386 lsm6ds3tr_c_sens_sync_spi_error_code_t sens_sync_spi_error_code;
7387 int32_t ret;
7388
7389 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SENS_SYNC_SPI_ERROR_CODE,
7390 (uint8_t *)&sens_sync_spi_error_code, 1);
7391 *val = sens_sync_spi_error_code.error_code;
7392
7393 return ret;
7394 }
7395
7396 /**
7397 * @brief Number of external sensors to be read by the sensor hub.[set]
7398 *
7399 * @param ctx Read / write interface definitions
7400 * @param val Change the values of aux_sens_on in reg SLAVE0_CONFIG.
7401 * @retval Interface status (MANDATORY: return 0 -> no Error).
7402 *
7403 */
lsm6ds3tr_c_sh_num_of_dev_connected_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_aux_sens_on_t val)7404 int32_t lsm6ds3tr_c_sh_num_of_dev_connected_set(const stmdev_ctx_t *ctx,
7405 lsm6ds3tr_c_aux_sens_on_t val)
7406 {
7407 lsm6ds3tr_c_slave0_config_t slave0_config;
7408 int32_t ret;
7409
7410 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
7411
7412 if (ret == 0)
7413 {
7414 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG,
7415 (uint8_t *)&slave0_config, 1);
7416
7417 if (ret == 0)
7418 {
7419 slave0_config.aux_sens_on = (uint8_t) val;
7420 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG,
7421 (uint8_t *)&slave0_config, 1);
7422
7423 if (ret == 0)
7424 {
7425 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
7426 }
7427 }
7428 }
7429
7430 return ret;
7431 }
7432
7433 /**
7434 * @brief Number of external sensors to be read by the sensor hub.[get]
7435 *
7436 * @param ctx Read / write interface definitions
7437 * @param val Get the values of aux_sens_on in reg SLAVE0_CONFIG.
7438 * @retval Interface status (MANDATORY: return 0 -> no Error).
7439 *
7440 */
lsm6ds3tr_c_sh_num_of_dev_connected_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_aux_sens_on_t * val)7441 int32_t lsm6ds3tr_c_sh_num_of_dev_connected_get(const stmdev_ctx_t *ctx,
7442 lsm6ds3tr_c_aux_sens_on_t *val)
7443 {
7444 lsm6ds3tr_c_slave0_config_t slave0_config;
7445 int32_t ret;
7446
7447 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
7448
7449 if (ret == 0)
7450 {
7451 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG,
7452 (uint8_t *)&slave0_config, 1);
7453
7454 if (ret == 0)
7455 {
7456 switch (slave0_config.aux_sens_on)
7457 {
7458 case LSM6DS3TR_C_SLV_0:
7459 *val = LSM6DS3TR_C_SLV_0;
7460 break;
7461
7462 case LSM6DS3TR_C_SLV_0_1:
7463 *val = LSM6DS3TR_C_SLV_0_1;
7464 break;
7465
7466 case LSM6DS3TR_C_SLV_0_1_2:
7467 *val = LSM6DS3TR_C_SLV_0_1_2;
7468 break;
7469
7470 case LSM6DS3TR_C_SLV_0_1_2_3:
7471 *val = LSM6DS3TR_C_SLV_0_1_2_3;
7472 break;
7473
7474 default:
7475 *val = LSM6DS3TR_C_SLV_EN_ND;
7476 break;
7477 }
7478
7479 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
7480 }
7481 }
7482
7483 return ret;
7484 }
7485
7486 /**
7487 * @brief Configure slave 0 for perform a write.[set]
7488 *
7489 * @param ctx Read / write interface definitions
7490 * @param val Structure that contain:
7491 * - uint8_t slv_add; 8 bit i2c device address
7492 * - uint8_t slv_subadd; 8 bit register device address
7493 * - uint8_t slv_data; 8 bit data to write
7494 * @retval Interface status (MANDATORY: return 0 -> no Error).
7495 *
7496 */
lsm6ds3tr_c_sh_cfg_write(const stmdev_ctx_t * ctx,lsm6ds3tr_c_sh_cfg_write_t * val)7497 int32_t lsm6ds3tr_c_sh_cfg_write(const stmdev_ctx_t *ctx,
7498 lsm6ds3tr_c_sh_cfg_write_t *val)
7499 {
7500 lsm6ds3tr_c_slv0_add_t slv0_add;
7501 int32_t ret;
7502
7503 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
7504
7505 if (ret == 0)
7506 {
7507 slv0_add.slave0_add = val->slv0_add;
7508 slv0_add.rw_0 = 0;
7509 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV0_ADD,
7510 (uint8_t *)&slv0_add, 1);
7511
7512 if (ret == 0)
7513 {
7514 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV0_SUBADD,
7515 &(val->slv0_subadd), 1);
7516
7517 if (ret == 0)
7518 {
7519 ret = lsm6ds3tr_c_write_reg(ctx,
7520 LSM6DS3TR_C_DATAWRITE_SRC_MODE_SUB_SLV0,
7521 &(val->slv0_data), 1);
7522
7523 if (ret == 0)
7524 {
7525 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
7526 }
7527 }
7528 }
7529 }
7530
7531 return ret;
7532 }
7533
7534 /**
7535 * @brief Configure slave 0 for perform a read.[get]
7536 *
7537 * @param ctx Read / write interface definitions
7538 * @param val Structure that contain:
7539 * - uint8_t slv_add; 8 bit i2c device address
7540 * - uint8_t slv_subadd; 8 bit register device address
7541 * - uint8_t slv_len; num of bit to read
7542 * @retval Interface status (MANDATORY: return 0 -> no Error).
7543 *
7544 */
lsm6ds3tr_c_sh_slv0_cfg_read(const stmdev_ctx_t * ctx,lsm6ds3tr_c_sh_cfg_read_t * val)7545 int32_t lsm6ds3tr_c_sh_slv0_cfg_read(const stmdev_ctx_t *ctx,
7546 lsm6ds3tr_c_sh_cfg_read_t *val)
7547 {
7548 lsm6ds3tr_c_slave0_config_t slave0_config;
7549 lsm6ds3tr_c_slv0_add_t slv0_add;
7550 int32_t ret;
7551
7552 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
7553
7554 if (ret == 0)
7555 {
7556 slv0_add.slave0_add = val->slv_add;
7557 slv0_add.rw_0 = 1;
7558 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV0_ADD,
7559 (uint8_t *)&slv0_add, 1);
7560
7561 if (ret == 0)
7562 {
7563 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV0_SUBADD,
7564 &(val->slv_subadd), 1);
7565
7566 if (ret == 0)
7567 {
7568 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG,
7569 (uint8_t *)&slave0_config, 1);
7570 slave0_config.slave0_numop = val->slv_len;
7571
7572 if (ret == 0)
7573 {
7574 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG,
7575 (uint8_t *)&slave0_config, 1);
7576
7577 if (ret == 0)
7578 {
7579 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
7580 }
7581 }
7582 }
7583 }
7584 }
7585
7586 return ret;
7587 }
7588
7589 /**
7590 * @brief Configure slave 1 for perform a read.[get]
7591 *
7592 * @param ctx Read / write interface definitions
7593 * @param val Structure that contain:
7594 * - uint8_t slv_add; 8 bit i2c device address
7595 * - uint8_t slv_subadd; 8 bit register device address
7596 * - uint8_t slv_len; num of bit to read
7597 * @retval Interface status (MANDATORY: return 0 -> no Error).
7598 *
7599 */
lsm6ds3tr_c_sh_slv1_cfg_read(const stmdev_ctx_t * ctx,lsm6ds3tr_c_sh_cfg_read_t * val)7600 int32_t lsm6ds3tr_c_sh_slv1_cfg_read(const stmdev_ctx_t *ctx,
7601 lsm6ds3tr_c_sh_cfg_read_t *val)
7602 {
7603 lsm6ds3tr_c_slave1_config_t slave1_config;
7604 lsm6ds3tr_c_slv1_add_t slv1_add;
7605 int32_t ret;
7606
7607 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
7608
7609 if (ret == 0)
7610 {
7611 slv1_add.slave1_add = val->slv_add;
7612 slv1_add.r_1 = 1;
7613 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV1_ADD,
7614 (uint8_t *)&slv1_add, 1);
7615
7616 if (ret == 0)
7617 {
7618 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV1_SUBADD,
7619 &(val->slv_subadd), 1);
7620
7621 if (ret == 0)
7622 {
7623 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
7624 (uint8_t *)&slave1_config, 1);
7625 slave1_config.slave1_numop = val->slv_len;
7626
7627 if (ret == 0)
7628 {
7629 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
7630 (uint8_t *)&slave1_config, 1);
7631
7632 if (ret == 0)
7633 {
7634 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
7635 }
7636 }
7637 }
7638 }
7639 }
7640
7641 return ret;
7642 }
7643
7644 /**
7645 * @brief Configure slave 2 for perform a read.[get]
7646 *
7647 * @param ctx Read / write interface definitions
7648 * @param val Structure that contain:
7649 * - uint8_t slv_add; 8 bit i2c device address
7650 * - uint8_t slv_subadd; 8 bit register device address
7651 * - uint8_t slv_len; num of bit to read
7652 * @retval Interface status (MANDATORY: return 0 -> no Error).
7653 *
7654 */
lsm6ds3tr_c_sh_slv2_cfg_read(const stmdev_ctx_t * ctx,lsm6ds3tr_c_sh_cfg_read_t * val)7655 int32_t lsm6ds3tr_c_sh_slv2_cfg_read(const stmdev_ctx_t *ctx,
7656 lsm6ds3tr_c_sh_cfg_read_t *val)
7657 {
7658 lsm6ds3tr_c_slv2_add_t slv2_add;
7659 lsm6ds3tr_c_slave2_config_t slave2_config;
7660 int32_t ret;
7661
7662 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
7663
7664 if (ret == 0)
7665 {
7666 slv2_add.slave2_add = val->slv_add;
7667 slv2_add.r_2 = 1;
7668 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV2_ADD,
7669 (uint8_t *)&slv2_add, 1);
7670
7671 if (ret == 0)
7672 {
7673 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV2_SUBADD,
7674 &(val->slv_subadd), 1);
7675
7676 if (ret == 0)
7677 {
7678 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG,
7679 (uint8_t *)&slave2_config, 1);
7680
7681 if (ret == 0)
7682 {
7683 slave2_config.slave2_numop = val->slv_len;
7684 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG,
7685 (uint8_t *)&slave2_config, 1);
7686
7687 if (ret == 0)
7688 {
7689 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
7690 }
7691 }
7692 }
7693 }
7694 }
7695
7696 return ret;
7697 }
7698
7699 /**
7700 * @brief Configure slave 3 for perform a read.[get]
7701 *
7702 * @param ctx Read / write interface definitions
7703 * @param val Structure that contain:
7704 * - uint8_t slv_add; 8 bit i2c device address
7705 * - uint8_t slv_subadd; 8 bit register device address
7706 * - uint8_t slv_len; num of bit to read
7707 * @retval Interface status (MANDATORY: return 0 -> no Error).
7708 *
7709 */
lsm6ds3tr_c_sh_slv3_cfg_read(const stmdev_ctx_t * ctx,lsm6ds3tr_c_sh_cfg_read_t * val)7710 int32_t lsm6ds3tr_c_sh_slv3_cfg_read(const stmdev_ctx_t *ctx,
7711 lsm6ds3tr_c_sh_cfg_read_t *val)
7712 {
7713 lsm6ds3tr_c_slave3_config_t slave3_config;
7714 lsm6ds3tr_c_slv3_add_t slv3_add;
7715 int32_t ret;
7716
7717 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
7718
7719 if (ret == 0)
7720 {
7721 slv3_add.slave3_add = val->slv_add;
7722 slv3_add.r_3 = 1;
7723 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV3_ADD,
7724 (uint8_t *)&slv3_add, 1);
7725
7726 if (ret == 0)
7727 {
7728 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLV3_SUBADD,
7729 (uint8_t *) & (val->slv_subadd), 1);
7730
7731 if (ret == 0)
7732 {
7733 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG,
7734 (uint8_t *)&slave3_config, 1);
7735
7736 if (ret == 0)
7737 {
7738 slave3_config.slave3_numop = val->slv_len;
7739 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG,
7740 (uint8_t *)&slave3_config, 1);
7741
7742 if (ret == 0)
7743 {
7744 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
7745 }
7746 }
7747 }
7748 }
7749 }
7750
7751 return ret;
7752 }
7753
7754 /**
7755 * @brief Decimation of read operation on Slave 0 starting from the
7756 * sensor hub trigger.[set]
7757 *
7758 * @param ctx Read / write interface definitions
7759 * @param val Change the values of slave0_rate in reg SLAVE0_CONFIG
7760 * @retval Interface status (MANDATORY: return 0 -> no Error).
7761 *
7762 */
lsm6ds3tr_c_sh_slave_0_dec_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_slave0_rate_t val)7763 int32_t lsm6ds3tr_c_sh_slave_0_dec_set(const stmdev_ctx_t *ctx,
7764 lsm6ds3tr_c_slave0_rate_t val)
7765 {
7766 lsm6ds3tr_c_slave0_config_t slave0_config;
7767 int32_t ret;
7768
7769 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
7770
7771 if (ret == 0)
7772 {
7773 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG,
7774 (uint8_t *)&slave0_config, 1);
7775
7776 if (ret == 0)
7777 {
7778 slave0_config.slave0_rate = (uint8_t) val;
7779 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG,
7780 (uint8_t *)&slave0_config, 1);
7781
7782 if (ret == 0)
7783 {
7784 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
7785 }
7786 }
7787 }
7788
7789 return ret;
7790 }
7791
7792 /**
7793 * @brief Decimation of read operation on Slave 0 starting from the
7794 * sensor hub trigger.[get]
7795 *
7796 * @param ctx Read / write interface definitions
7797 * @param val Get the values of slave0_rate in reg SLAVE0_CONFIG
7798 * @retval Interface status (MANDATORY: return 0 -> no Error).
7799 *
7800 */
lsm6ds3tr_c_sh_slave_0_dec_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_slave0_rate_t * val)7801 int32_t lsm6ds3tr_c_sh_slave_0_dec_get(const stmdev_ctx_t *ctx,
7802 lsm6ds3tr_c_slave0_rate_t *val)
7803 {
7804 lsm6ds3tr_c_slave0_config_t slave0_config;
7805 int32_t ret;
7806
7807 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
7808
7809 if (ret == 0)
7810 {
7811 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE0_CONFIG,
7812 (uint8_t *)&slave0_config, 1);
7813
7814 if (ret == 0)
7815 {
7816 switch (slave0_config.slave0_rate)
7817 {
7818 case LSM6DS3TR_C_SL0_NO_DEC:
7819 *val = LSM6DS3TR_C_SL0_NO_DEC;
7820 break;
7821
7822 case LSM6DS3TR_C_SL0_DEC_2:
7823 *val = LSM6DS3TR_C_SL0_DEC_2;
7824 break;
7825
7826 case LSM6DS3TR_C_SL0_DEC_4:
7827 *val = LSM6DS3TR_C_SL0_DEC_4;
7828 break;
7829
7830 case LSM6DS3TR_C_SL0_DEC_8:
7831 *val = LSM6DS3TR_C_SL0_DEC_8;
7832 break;
7833
7834 default:
7835 *val = LSM6DS3TR_C_SL0_DEC_ND;
7836 break;
7837 }
7838
7839 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
7840 }
7841 }
7842
7843 return ret;
7844 }
7845
7846 /**
7847 * @brief Slave 0 write operation is performed only at the first sensor
7848 * hub cycle.
7849 * This is effective if the Aux_sens_on[1:0] field in
7850 * SLAVE0_CONFIG(04h) is set to a value other than 00.[set]
7851 *
7852 * @param ctx Read / write interface definitions
7853 * @param val Change the values of write_once in reg SLAVE1_CONFIG
7854 * @retval Interface status (MANDATORY: return 0 -> no Error).
7855 *
7856 */
lsm6ds3tr_c_sh_write_mode_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_write_once_t val)7857 int32_t lsm6ds3tr_c_sh_write_mode_set(const stmdev_ctx_t *ctx,
7858 lsm6ds3tr_c_write_once_t val)
7859 {
7860 lsm6ds3tr_c_slave1_config_t slave1_config;
7861 int32_t ret;
7862
7863 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
7864
7865 if (ret == 0)
7866 {
7867 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
7868 (uint8_t *)&slave1_config, 1);
7869 slave1_config.write_once = (uint8_t) val;
7870
7871 if (ret == 0)
7872 {
7873 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
7874 (uint8_t *)&slave1_config, 1);
7875
7876 if (ret == 0)
7877 {
7878 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
7879 }
7880 }
7881 }
7882
7883 return ret;
7884 }
7885
7886 /**
7887 * @brief Slave 0 write operation is performed only at the first sensor
7888 * hub cycle.
7889 * This is effective if the Aux_sens_on[1:0] field in
7890 * SLAVE0_CONFIG(04h) is set to a value other than 00.[get]
7891 *
7892 * @param ctx Read / write interface definitions
7893 * @param val Get the values of write_once in reg SLAVE1_CONFIG
7894 * @retval Interface status (MANDATORY: return 0 -> no Error).
7895 *
7896 */
lsm6ds3tr_c_sh_write_mode_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_write_once_t * val)7897 int32_t lsm6ds3tr_c_sh_write_mode_get(const stmdev_ctx_t *ctx,
7898 lsm6ds3tr_c_write_once_t *val)
7899 {
7900 lsm6ds3tr_c_slave1_config_t slave1_config;
7901 int32_t ret;
7902
7903 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
7904
7905 if (ret == 0)
7906 {
7907 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
7908 (uint8_t *)&slave1_config, 1);
7909
7910 if (ret == 0)
7911 {
7912 switch (slave1_config.write_once)
7913 {
7914 case LSM6DS3TR_C_EACH_SH_CYCLE:
7915 *val = LSM6DS3TR_C_EACH_SH_CYCLE;
7916 break;
7917
7918 case LSM6DS3TR_C_ONLY_FIRST_CYCLE:
7919 *val = LSM6DS3TR_C_ONLY_FIRST_CYCLE;
7920 break;
7921
7922 default:
7923 *val = LSM6DS3TR_C_SH_WR_MODE_ND;
7924 break;
7925 }
7926
7927 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
7928 }
7929 }
7930
7931 return ret;
7932 }
7933
7934 /**
7935 * @brief Decimation of read operation on Slave 1 starting from the
7936 * sensor hub trigger.[set]
7937 *
7938 * @param ctx Read / write interface definitions
7939 * @param val Change the values of slave1_rate in reg SLAVE1_CONFIG
7940 * @retval Interface status (MANDATORY: return 0 -> no Error).
7941 *
7942 */
lsm6ds3tr_c_sh_slave_1_dec_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_slave1_rate_t val)7943 int32_t lsm6ds3tr_c_sh_slave_1_dec_set(const stmdev_ctx_t *ctx,
7944 lsm6ds3tr_c_slave1_rate_t val)
7945 {
7946 lsm6ds3tr_c_slave1_config_t slave1_config;
7947 int32_t ret;
7948
7949 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
7950
7951 if (ret == 0)
7952 {
7953 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
7954 (uint8_t *)&slave1_config, 1);
7955
7956 if (ret == 0)
7957 {
7958 slave1_config.slave1_rate = (uint8_t) val;
7959 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
7960 (uint8_t *)&slave1_config, 1);
7961
7962 if (ret == 0)
7963 {
7964 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
7965 }
7966 }
7967 }
7968
7969 return ret;
7970 }
7971
7972 /**
7973 * @brief Decimation of read operation on Slave 1 starting from the
7974 * sensor hub trigger.[get]
7975 *
7976 * @param ctx Read / write interface definitions reg SLAVE1_CONFIG
7977 * @retval Interface status (MANDATORY: return 0 -> no Error).
7978 *
7979 */
lsm6ds3tr_c_sh_slave_1_dec_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_slave1_rate_t * val)7980 int32_t lsm6ds3tr_c_sh_slave_1_dec_get(const stmdev_ctx_t *ctx,
7981 lsm6ds3tr_c_slave1_rate_t *val)
7982 {
7983 lsm6ds3tr_c_slave1_config_t slave1_config;
7984 int32_t ret;
7985
7986 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
7987
7988 if (ret == 0)
7989 {
7990 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE1_CONFIG,
7991 (uint8_t *)&slave1_config, 1);
7992
7993 if (ret == 0)
7994 {
7995 switch (slave1_config.slave1_rate)
7996 {
7997 case LSM6DS3TR_C_SL1_NO_DEC:
7998 *val = LSM6DS3TR_C_SL1_NO_DEC;
7999 break;
8000
8001 case LSM6DS3TR_C_SL1_DEC_2:
8002 *val = LSM6DS3TR_C_SL1_DEC_2;
8003 break;
8004
8005 case LSM6DS3TR_C_SL1_DEC_4:
8006 *val = LSM6DS3TR_C_SL1_DEC_4;
8007 break;
8008
8009 case LSM6DS3TR_C_SL1_DEC_8:
8010 *val = LSM6DS3TR_C_SL1_DEC_8;
8011 break;
8012
8013 default:
8014 *val = LSM6DS3TR_C_SL1_DEC_ND;
8015 break;
8016 }
8017
8018 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
8019 }
8020 }
8021
8022 return ret;
8023 }
8024
8025 /**
8026 * @brief Decimation of read operation on Slave 2 starting from the
8027 * sensor hub trigger.[set]
8028 *
8029 * @param ctx Read / write interface definitions
8030 * @param val Change the values of slave2_rate in reg SLAVE2_CONFIG
8031 * @retval Interface status (MANDATORY: return 0 -> no Error).
8032 *
8033 */
lsm6ds3tr_c_sh_slave_2_dec_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_slave2_rate_t val)8034 int32_t lsm6ds3tr_c_sh_slave_2_dec_set(const stmdev_ctx_t *ctx,
8035 lsm6ds3tr_c_slave2_rate_t val)
8036 {
8037 lsm6ds3tr_c_slave2_config_t slave2_config;
8038 int32_t ret;
8039
8040 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
8041
8042 if (ret == 0)
8043 {
8044 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG,
8045 (uint8_t *)&slave2_config, 1);
8046
8047 if (ret == 0)
8048 {
8049 slave2_config.slave2_rate = (uint8_t) val;
8050 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG,
8051 (uint8_t *)&slave2_config, 1);
8052
8053 if (ret == 0)
8054 {
8055 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
8056 }
8057 }
8058 }
8059
8060 return ret;
8061 }
8062
8063 /**
8064 * @brief Decimation of read operation on Slave 2 starting from the
8065 * sensor hub trigger.[get]
8066 *
8067 * @param ctx Read / write interface definitions
8068 * @param val Get the values of slave2_rate in reg SLAVE2_CONFIG
8069 * @retval Interface status (MANDATORY: return 0 -> no Error).
8070 *
8071 */
lsm6ds3tr_c_sh_slave_2_dec_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_slave2_rate_t * val)8072 int32_t lsm6ds3tr_c_sh_slave_2_dec_get(const stmdev_ctx_t *ctx,
8073 lsm6ds3tr_c_slave2_rate_t *val)
8074 {
8075 lsm6ds3tr_c_slave2_config_t slave2_config;
8076 int32_t ret;
8077
8078 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
8079
8080 if (ret == 0)
8081 {
8082 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE2_CONFIG,
8083 (uint8_t *)&slave2_config, 1);
8084
8085 if (ret == 0)
8086 {
8087 switch (slave2_config.slave2_rate)
8088 {
8089 case LSM6DS3TR_C_SL2_NO_DEC:
8090 *val = LSM6DS3TR_C_SL2_NO_DEC;
8091 break;
8092
8093 case LSM6DS3TR_C_SL2_DEC_2:
8094 *val = LSM6DS3TR_C_SL2_DEC_2;
8095 break;
8096
8097 case LSM6DS3TR_C_SL2_DEC_4:
8098 *val = LSM6DS3TR_C_SL2_DEC_4;
8099 break;
8100
8101 case LSM6DS3TR_C_SL2_DEC_8:
8102 *val = LSM6DS3TR_C_SL2_DEC_8;
8103 break;
8104
8105 default:
8106 *val = LSM6DS3TR_C_SL2_DEC_ND;
8107 break;
8108 }
8109
8110 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
8111 }
8112 }
8113
8114 return ret;
8115 }
8116
8117 /**
8118 * @brief Decimation of read operation on Slave 3 starting from the
8119 * sensor hub trigger.[set]
8120 *
8121 * @param ctx Read / write interface definitions
8122 * @param val Change the values of slave3_rate in reg SLAVE3_CONFIG
8123 * @retval Interface status (MANDATORY: return 0 -> no Error).
8124 *
8125 */
lsm6ds3tr_c_sh_slave_3_dec_set(const stmdev_ctx_t * ctx,lsm6ds3tr_c_slave3_rate_t val)8126 int32_t lsm6ds3tr_c_sh_slave_3_dec_set(const stmdev_ctx_t *ctx,
8127 lsm6ds3tr_c_slave3_rate_t val)
8128 {
8129 lsm6ds3tr_c_slave3_config_t slave3_config;
8130 int32_t ret;
8131
8132 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
8133
8134 if (ret == 0)
8135 {
8136 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG,
8137 (uint8_t *)&slave3_config, 1);
8138 slave3_config.slave3_rate = (uint8_t)val;
8139
8140 if (ret == 0)
8141 {
8142 ret = lsm6ds3tr_c_write_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG,
8143 (uint8_t *)&slave3_config, 1);
8144
8145 if (ret == 0)
8146 {
8147 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
8148 }
8149 }
8150 }
8151
8152 return ret;
8153 }
8154
8155 /**
8156 * @brief Decimation of read operation on Slave 3 starting from the
8157 * sensor hub trigger.[get]
8158 *
8159 * @param ctx Read / write interface definitions
8160 * @param val Get the values of slave3_rate in reg SLAVE3_CONFIG.
8161 * @retval Interface status (MANDATORY: return 0 -> no Error).
8162 *
8163 */
lsm6ds3tr_c_sh_slave_3_dec_get(const stmdev_ctx_t * ctx,lsm6ds3tr_c_slave3_rate_t * val)8164 int32_t lsm6ds3tr_c_sh_slave_3_dec_get(const stmdev_ctx_t *ctx,
8165 lsm6ds3tr_c_slave3_rate_t *val)
8166 {
8167 lsm6ds3tr_c_slave3_config_t slave3_config;
8168 int32_t ret;
8169
8170 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_BANK_A);
8171
8172 if (ret == 0)
8173 {
8174 ret = lsm6ds3tr_c_read_reg(ctx, LSM6DS3TR_C_SLAVE3_CONFIG,
8175 (uint8_t *)&slave3_config, 1);
8176
8177 if (ret == 0)
8178 {
8179 switch (slave3_config.slave3_rate)
8180 {
8181 case LSM6DS3TR_C_SL3_NO_DEC:
8182 *val = LSM6DS3TR_C_SL3_NO_DEC;
8183 break;
8184
8185 case LSM6DS3TR_C_SL3_DEC_2:
8186 *val = LSM6DS3TR_C_SL3_DEC_2;
8187 break;
8188
8189 case LSM6DS3TR_C_SL3_DEC_4:
8190 *val = LSM6DS3TR_C_SL3_DEC_4;
8191 break;
8192
8193 case LSM6DS3TR_C_SL3_DEC_8:
8194 *val = LSM6DS3TR_C_SL3_DEC_8;
8195 break;
8196
8197 default:
8198 *val = LSM6DS3TR_C_SL3_DEC_ND;
8199 break;
8200 }
8201
8202 ret = lsm6ds3tr_c_mem_bank_set(ctx, LSM6DS3TR_C_USER_BANK);
8203 }
8204 }
8205
8206 return ret;
8207 }
8208
8209 /**
8210 * @}
8211 *
8212 */
8213
8214 /**
8215 * @}
8216 *
8217 */
8218
8219 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
8220
