1 /**
2 ******************************************************************************
3 * @file lsm303agr_reg.c
4 * @author Sensors Software Solution Team
5 * @brief LSM303AGR driver file
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2021 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 #include "lsm303agr_reg.h"
21
22 /**
23 * @defgroup LSM303AGR
24 * @brief This file provides a set of functions needed to drive the
25 * lsm303agr enhanced inertial module.
26 * @{
27 *
28 */
29
30 /**
31 * @defgroup LSM303AGR_Interfaces_Functions
32 * @brief This section provide a set of functions used to read and
33 * write a generic register of the device.
34 * MANDATORY: return 0 -> no Error.
35 * @{
36 *
37 */
38
39 /**
40 * @brief Read generic device register
41 *
42 * @param ctx read / write interface definitions(ptr)
43 * @param reg register to read
44 * @param data pointer to buffer that store the data read(ptr)
45 * @param len number of consecutive register to read
46 * @retval interface status (MANDATORY: return 0 -> no Error)
47 *
48 */
lsm303agr_read_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)49 int32_t __weak lsm303agr_read_reg(const stmdev_ctx_t *ctx, uint8_t reg,
50 uint8_t *data,
51 uint16_t len)
52 {
53 int32_t ret;
54
55 if (ctx == NULL)
56 {
57 return -1;
58 }
59
60 ret = ctx->read_reg(ctx->handle, reg, data, len);
61
62 return ret;
63 }
64
65 /**
66 * @brief Write generic device register
67 *
68 * @param ctx read / write interface definitions(ptr)
69 * @param reg register to write
70 * @param data pointer to data to write in register reg(ptr)
71 * @param len number of consecutive register to write
72 * @retval interface status (MANDATORY: return 0 -> no Error)
73 *
74 */
lsm303agr_write_reg(const stmdev_ctx_t * ctx,uint8_t reg,uint8_t * data,uint16_t len)75 int32_t __weak lsm303agr_write_reg(const stmdev_ctx_t *ctx, uint8_t reg,
76 uint8_t *data,
77 uint16_t len)
78 {
79 int32_t ret;
80
81 if (ctx == NULL)
82 {
83 return -1;
84 }
85
86 ret = ctx->write_reg(ctx->handle, reg, data, len);
87
88 return ret;
89 }
90
91 /**
92 * @}
93 *
94 */
95
96 /**
97 * @defgroup LSM303AGR_Sensitivity
98 * @brief These functions convert raw-data into engineering units.
99 * @{
100 *
101 */
102
lsm303agr_from_fs_2g_hr_to_mg(int16_t lsb)103 float_t lsm303agr_from_fs_2g_hr_to_mg(int16_t lsb)
104 {
105 return ((float_t)lsb / 16.0f) * 0.98f;
106 }
107
lsm303agr_from_fs_4g_hr_to_mg(int16_t lsb)108 float_t lsm303agr_from_fs_4g_hr_to_mg(int16_t lsb)
109 {
110 return ((float_t)lsb / 16.0f) * 1.95f;
111 }
112
lsm303agr_from_fs_8g_hr_to_mg(int16_t lsb)113 float_t lsm303agr_from_fs_8g_hr_to_mg(int16_t lsb)
114 {
115 return ((float_t)lsb / 16.0f) * 3.9f;
116 }
117
lsm303agr_from_fs_16g_hr_to_mg(int16_t lsb)118 float_t lsm303agr_from_fs_16g_hr_to_mg(int16_t lsb)
119 {
120 return ((float_t)lsb / 16.0f) * 11.72f;
121 }
122
lsm303agr_from_lsb_hr_to_celsius(int16_t lsb)123 float_t lsm303agr_from_lsb_hr_to_celsius(int16_t lsb)
124 {
125 return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
126 }
127
lsm303agr_from_fs_2g_nm_to_mg(int16_t lsb)128 float_t lsm303agr_from_fs_2g_nm_to_mg(int16_t lsb)
129 {
130 return ((float_t)lsb / 64.0f) * 3.9f;
131 }
132
lsm303agr_from_fs_4g_nm_to_mg(int16_t lsb)133 float_t lsm303agr_from_fs_4g_nm_to_mg(int16_t lsb)
134 {
135 return ((float_t)lsb / 64.0f) * 7.82f;
136 }
137
lsm303agr_from_fs_8g_nm_to_mg(int16_t lsb)138 float_t lsm303agr_from_fs_8g_nm_to_mg(int16_t lsb)
139 {
140 return ((float_t)lsb / 64.0f) * 15.63f;
141 }
142
lsm303agr_from_fs_16g_nm_to_mg(int16_t lsb)143 float_t lsm303agr_from_fs_16g_nm_to_mg(int16_t lsb)
144 {
145 return ((float_t)lsb / 64.0f) * 46.9f;
146 }
147
lsm303agr_from_lsb_nm_to_celsius(int16_t lsb)148 float_t lsm303agr_from_lsb_nm_to_celsius(int16_t lsb)
149 {
150 return (((float_t)lsb / 64.0f) / 4.0f) + 25.0f;
151 }
152
lsm303agr_from_fs_2g_lp_to_mg(int16_t lsb)153 float_t lsm303agr_from_fs_2g_lp_to_mg(int16_t lsb)
154 {
155 return ((float_t)lsb / 256.0f) * 15.63f;
156 }
157
lsm303agr_from_fs_4g_lp_to_mg(int16_t lsb)158 float_t lsm303agr_from_fs_4g_lp_to_mg(int16_t lsb)
159 {
160 return ((float_t)lsb / 256.0f) * 31.26f;
161 }
162
lsm303agr_from_fs_8g_lp_to_mg(int16_t lsb)163 float_t lsm303agr_from_fs_8g_lp_to_mg(int16_t lsb)
164 {
165 return ((float_t)lsb / 256.0f) * 62.52f;
166 }
167
lsm303agr_from_fs_16g_lp_to_mg(int16_t lsb)168 float_t lsm303agr_from_fs_16g_lp_to_mg(int16_t lsb)
169 {
170 return ((float_t)lsb / 256.0f) * 187.58f;
171 }
172
lsm303agr_from_lsb_lp_to_celsius(int16_t lsb)173 float_t lsm303agr_from_lsb_lp_to_celsius(int16_t lsb)
174 {
175 return (((float_t)lsb / 256.0f) * 1.0f) + 25.0f;
176 }
177
lsm303agr_from_lsb_to_mgauss(int16_t lsb)178 float_t lsm303agr_from_lsb_to_mgauss(int16_t lsb)
179 {
180 return (float_t)lsb * 1.5f;
181 }
182
183 /**
184 * @}
185 *
186 */
187
188 /**
189 * @defgroup LSM303AGR_Data_generation
190 * @brief This section group all the functions concerning data generation
191 * @{
192 *
193 */
194
195 /**
196 * @brief Temperature status register.[get]
197 *
198 * @param ctx Read / write interface definitions.(ptr)
199 * @param buff Buffer that stores the data read.(ptr)
200 * @retval Interface status (MANDATORY: return 0 -> no Error).
201 *
202 */
lsm303agr_temp_status_reg_get(const stmdev_ctx_t * ctx,uint8_t * buff)203 int32_t lsm303agr_temp_status_reg_get(const stmdev_ctx_t *ctx,
204 uint8_t *buff)
205 {
206 int32_t ret;
207
208 ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_AUX_A, buff, 1);
209
210 return ret;
211 }
212
213 /**
214 * @brief Temperature data available.[get]
215 *
216 * @param ctx Read / write interface definitions.(ptr)
217 * @param val Get the values of tda in reg STATUS_REG_AUX_A.(ptr)
218 * @retval Interface status (MANDATORY: return 0 -> no Error).
219 *
220 */
lsm303agr_temp_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)221 int32_t lsm303agr_temp_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
222 {
223 lsm303agr_status_reg_aux_a_t status_reg_aux_a;
224 int32_t ret;
225
226 ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_AUX_A,
227 (uint8_t *)&status_reg_aux_a, 1);
228 *val = status_reg_aux_a.tda;
229
230 return ret;
231 }
232
233 /**
234 * @brief Temperature data overrun.[get]
235 *
236 * @param ctx Read / write interface definitions.(ptr)
237 * @param val Get the values of tor in reg STATUS_REG_AUX_A.(ptr)
238 * @retval Interface status (MANDATORY: return 0 -> no Error).
239 *
240 */
lsm303agr_temp_data_ovr_get(const stmdev_ctx_t * ctx,uint8_t * val)241 int32_t lsm303agr_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val)
242 {
243 lsm303agr_status_reg_aux_a_t status_reg_aux_a;
244 int32_t ret;
245
246 ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_AUX_A,
247 (uint8_t *)&status_reg_aux_a, 1);
248 *val = status_reg_aux_a.tor;
249
250 return ret;
251 }
252
253 /**
254 * @brief Temperature output value.[get]
255 *
256 * @param ctx Read / write interface definitions.(ptr)
257 * @param buff Buffer that stores the data read.(ptr)
258 * @retval Interface status (MANDATORY: return 0 -> no Error).
259 *
260 */
lsm303agr_temperature_raw_get(const stmdev_ctx_t * ctx,int16_t * val)261 int32_t lsm303agr_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
262 {
263 uint8_t buff[2];
264 int32_t ret;
265
266 ret = lsm303agr_read_reg(ctx, LSM303AGR_OUT_TEMP_L_A, buff, 2);
267 val[0] = (int16_t)buff[1];
268 val[0] = (val[0] * 256) + (int16_t)buff[0];
269
270 return ret;
271 }
272
273 /**
274 * @brief Temperature sensor enable.[set]
275 *
276 * @param ctx Read / write interface definitions.(ptr)
277 * @param val Change the values of temp_en in reg TEMP_CFG_REG_A.
278 * @retval Interface status (MANDATORY: return 0 -> no Error).
279 *
280 */
lsm303agr_temperature_meas_set(const stmdev_ctx_t * ctx,lsm303agr_temp_en_a_t val)281 int32_t lsm303agr_temperature_meas_set(const stmdev_ctx_t *ctx,
282 lsm303agr_temp_en_a_t val)
283 {
284 lsm303agr_temp_cfg_reg_a_t temp_cfg_reg_a;
285 int32_t ret;
286
287 ret = lsm303agr_read_reg(ctx, LSM303AGR_TEMP_CFG_REG_A,
288 (uint8_t *)&temp_cfg_reg_a, 1);
289
290 if (ret == 0)
291 {
292 temp_cfg_reg_a.temp_en = (uint8_t)val;
293 ret = lsm303agr_write_reg(ctx, LSM303AGR_TEMP_CFG_REG_A,
294 (uint8_t *)&temp_cfg_reg_a, 1);
295 }
296
297 return ret;
298 }
299
300 /**
301 * @brief Temperature sensor enable.[get]
302 *
303 * @param ctx Read / write interface definitions.(ptr)
304 * @param val Get the values of temp_en in reg TEMP_CFG_REG_A.(ptr)
305 * @retval Interface status (MANDATORY: return 0 -> no Error).
306 *
307 */
lsm303agr_temperature_meas_get(const stmdev_ctx_t * ctx,lsm303agr_temp_en_a_t * val)308 int32_t lsm303agr_temperature_meas_get(const stmdev_ctx_t *ctx,
309 lsm303agr_temp_en_a_t *val)
310 {
311 lsm303agr_temp_cfg_reg_a_t temp_cfg_reg_a;
312 int32_t ret;
313
314 ret = lsm303agr_read_reg(ctx, LSM303AGR_TEMP_CFG_REG_A,
315 (uint8_t *)&temp_cfg_reg_a, 1);
316
317 switch (temp_cfg_reg_a.temp_en)
318 {
319 case LSM303AGR_TEMP_DISABLE:
320 *val = LSM303AGR_TEMP_DISABLE;
321 break;
322
323 case LSM303AGR_TEMP_ENABLE:
324 *val = LSM303AGR_TEMP_ENABLE;
325 break;
326
327 default:
328 *val = LSM303AGR_TEMP_DISABLE;
329 break;
330 }
331
332 return ret;
333 }
334
335 /**
336 * @brief Operating mode selection.[set]
337 *
338 * @param ctx Read / write interface definitions.(ptr)
339 * @param val Change the values of lpen in reg
340 * CTRL_REG1_A and HR in reg CTRL_REG4_A
341 * @retval Interface status (MANDATORY: return 0 -> no Error).
342 *
343 */
lsm303agr_xl_operating_mode_set(const stmdev_ctx_t * ctx,lsm303agr_op_md_a_t val)344 int32_t lsm303agr_xl_operating_mode_set(const stmdev_ctx_t *ctx,
345 lsm303agr_op_md_a_t val)
346 {
347 lsm303agr_ctrl_reg1_a_t ctrl_reg1_a;
348 lsm303agr_ctrl_reg4_a_t ctrl_reg4_a;
349 int32_t ret;
350
351 uint8_t lpen, hr;
352
353 if (val == LSM303AGR_HR_12bit)
354 {
355 lpen = 0;
356 hr = 1;
357 }
358
359 else if (val == LSM303AGR_NM_10bit)
360 {
361 lpen = 0;
362 hr = 0;
363 }
364
365 else
366 {
367 lpen = 1;
368 hr = 0;
369 }
370
371 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG1_A,
372 (uint8_t *)&ctrl_reg1_a, 1);
373 ctrl_reg1_a.lpen = (uint8_t)lpen;
374
375 if (ret == 0)
376 {
377 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG1_A,
378 (uint8_t *)&ctrl_reg1_a, 1);
379 }
380
381 if (ret == 0)
382 {
383 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
384 (uint8_t *)&ctrl_reg4_a, 1);
385 }
386
387 if (ret == 0)
388 {
389 ctrl_reg4_a.hr = hr;
390 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG4_A,
391 (uint8_t *)&ctrl_reg4_a, 1);
392 }
393
394 return ret;
395 }
396
397 /**
398 * @brief Operating mode selection.[get]
399 *
400 * @param ctx Read / write interface definitions.(ptr)
401 * @param val Get the values of lpen in reg CTRL_REG1_A and HR in
402 * reg CTRL_REG4_AG1_A.(ptr)
403 * @retval Interface status (MANDATORY: return 0 -> no Error).
404 *
405 */
lsm303agr_xl_operating_mode_get(const stmdev_ctx_t * ctx,lsm303agr_op_md_a_t * val)406 int32_t lsm303agr_xl_operating_mode_get(const stmdev_ctx_t *ctx,
407 lsm303agr_op_md_a_t *val)
408 {
409 lsm303agr_ctrl_reg4_a_t ctrl_reg4_a;
410 lsm303agr_ctrl_reg1_a_t ctrl_reg1_a;
411 int32_t ret;
412
413 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG1_A,
414 (uint8_t *)&ctrl_reg1_a, 1);
415
416 if (ret == 0)
417 {
418 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
419 (uint8_t *)&ctrl_reg4_a, 1);
420 }
421
422 if (ctrl_reg1_a.lpen != PROPERTY_DISABLE)
423 {
424 *val = LSM303AGR_LP_8bit;
425 }
426
427 else if (ctrl_reg4_a.hr != PROPERTY_DISABLE)
428 {
429 *val = LSM303AGR_HR_12bit;
430 }
431
432 else
433 {
434 *val = LSM303AGR_NM_10bit;
435 }
436
437 return ret;
438 }
439
440 /**
441 * @brief Output data rate selection.[set]
442 *
443 * @param ctx Read / write interface definitions.(ptr)
444 * @param val Change the values of odr in reg CTRL_REG1_A
445 * @retval Interface status (MANDATORY: return 0 -> no Error).
446 *
447 */
lsm303agr_xl_data_rate_set(const stmdev_ctx_t * ctx,lsm303agr_odr_a_t val)448 int32_t lsm303agr_xl_data_rate_set(const stmdev_ctx_t *ctx,
449 lsm303agr_odr_a_t val)
450 {
451 lsm303agr_ctrl_reg1_a_t ctrl_reg1_a;
452 int32_t ret;
453
454 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG1_A,
455 (uint8_t *)&ctrl_reg1_a, 1);
456
457 if (ret == 0)
458 {
459 ctrl_reg1_a.odr = (uint8_t)val;
460 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG1_A,
461 (uint8_t *)&ctrl_reg1_a, 1);
462 }
463
464 return ret;
465 }
466
467 /**
468 * @brief Output data rate selection.[get]
469 *
470 * @param ctx Read / write interface definitions.(ptr)
471 * @param val Get the values of odr in reg CTRL_REG1_A.(ptr)
472 * @retval Interface status (MANDATORY: return 0 -> no Error).
473 *
474 */
lsm303agr_xl_data_rate_get(const stmdev_ctx_t * ctx,lsm303agr_odr_a_t * val)475 int32_t lsm303agr_xl_data_rate_get(const stmdev_ctx_t *ctx,
476 lsm303agr_odr_a_t *val)
477 {
478 lsm303agr_ctrl_reg1_a_t ctrl_reg1_a;
479 int32_t ret;
480
481 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG1_A,
482 (uint8_t *)&ctrl_reg1_a, 1);
483
484 switch (ctrl_reg1_a.odr)
485 {
486 case LSM303AGR_XL_POWER_DOWN:
487 *val = LSM303AGR_XL_POWER_DOWN;
488 break;
489
490 case LSM303AGR_XL_ODR_1Hz:
491 *val = LSM303AGR_XL_ODR_1Hz;
492 break;
493
494 case LSM303AGR_XL_ODR_10Hz:
495 *val = LSM303AGR_XL_ODR_10Hz;
496 break;
497
498 case LSM303AGR_XL_ODR_25Hz:
499 *val = LSM303AGR_XL_ODR_25Hz;
500 break;
501
502 case LSM303AGR_XL_ODR_50Hz:
503 *val = LSM303AGR_XL_ODR_50Hz;
504 break;
505
506 case LSM303AGR_XL_ODR_100Hz:
507 *val = LSM303AGR_XL_ODR_100Hz;
508 break;
509
510 case LSM303AGR_XL_ODR_200Hz:
511 *val = LSM303AGR_XL_ODR_200Hz;
512 break;
513
514 case LSM303AGR_XL_ODR_400Hz:
515 *val = LSM303AGR_XL_ODR_400Hz;
516 break;
517
518 case LSM303AGR_XL_ODR_1kHz620_LP:
519 *val = LSM303AGR_XL_ODR_1kHz620_LP;
520 break;
521
522 case LSM303AGR_XL_ODR_1kHz344_NM_HP_5kHz376_LP:
523 *val = LSM303AGR_XL_ODR_1kHz344_NM_HP_5kHz376_LP;
524 break;
525
526 default:
527 *val = LSM303AGR_XL_POWER_DOWN;
528 break;
529 }
530
531 return ret;
532 }
533
534 /**
535 * @brief High pass data from internal filter sent to output register and FIFO.[set]
536 *
537 * @param ctx Read / write interface definitions.(ptr)
538 * @param val Change the values of fds in reg CTRL_REG2_A
539 * @retval Interface status (MANDATORY: return 0 -> no Error).
540 *
541 */
lsm303agr_xl_high_pass_on_outputs_set(const stmdev_ctx_t * ctx,uint8_t val)542 int32_t lsm303agr_xl_high_pass_on_outputs_set(const stmdev_ctx_t *ctx,
543 uint8_t val)
544 {
545 lsm303agr_ctrl_reg2_a_t ctrl_reg2_a;
546 int32_t ret;
547
548 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A,
549 (uint8_t *)&ctrl_reg2_a, 1);
550
551 if (ret == 0)
552 {
553 ctrl_reg2_a.fds = (uint8_t)val;
554 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG2_A,
555 (uint8_t *)&ctrl_reg2_a, 1);
556 }
557
558 return ret;
559 }
560
561 /**
562 * @brief High pass data from internal filter sent to output
563 * register and FIFO.[get]
564 *
565 * @param ctx Read / write interface definitions.(ptr)
566 * @param val Get the values of fds in reg CTRL_REG2_A.(ptr)
567 * @retval Interface status (MANDATORY: return 0 -> no Error).
568 *
569 */
lsm303agr_xl_high_pass_on_outputs_get(const stmdev_ctx_t * ctx,uint8_t * val)570 int32_t lsm303agr_xl_high_pass_on_outputs_get(const stmdev_ctx_t *ctx,
571 uint8_t *val)
572 {
573 lsm303agr_ctrl_reg2_a_t ctrl_reg2_a;
574 int32_t ret;
575
576 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A,
577 (uint8_t *)&ctrl_reg2_a, 1);
578 *val = ctrl_reg2_a.fds;
579
580 return ret;
581 }
582
583 /**
584 * @brief High-pass filter cutoff frequency selection.[set]
585 *
586 *
587 * @param ctx Read / write interface definitions.(ptr)
588 * @param val Change the values of hpcf in reg CTRL_REG2_A
589 *
590 * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz
591 * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz
592 * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz
593 * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz
594 * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz
595 * @retval Interface status (MANDATORY: return 0 -> no Error).
596 *
597 */
lsm303agr_xl_high_pass_bandwidth_set(const stmdev_ctx_t * ctx,lsm303agr_hpcf_a_t val)598 int32_t lsm303agr_xl_high_pass_bandwidth_set(const stmdev_ctx_t *ctx,
599 lsm303agr_hpcf_a_t val)
600 {
601 lsm303agr_ctrl_reg2_a_t ctrl_reg2_a;
602 int32_t ret;
603
604 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A,
605 (uint8_t *)&ctrl_reg2_a, 1);
606
607 if (ret == 0)
608 {
609 ctrl_reg2_a.hpcf = (uint8_t)val;
610 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG2_A,
611 (uint8_t *)&ctrl_reg2_a, 1);
612 }
613
614 return ret;
615 }
616
617 /**
618 * @brief High-pass filter cutoff frequency selection.[get]
619 *
620 * @param ctx Read / write interface definitions.(ptr)
621 * @param val Get the values of hpcf in reg CTRL_REG2_A.(ptr)
622 *
623 * HPCF[2:1]\ft @1Hz @10Hz @25Hz @50Hz @100Hz @200Hz @400Hz @1kHz6 ft@5kHz
624 * AGGRESSIVE 0.02Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 8Hz 32Hz 100Hz
625 * STRONG 0.008Hz 0.08Hz 0.2Hz 0.5Hz 1Hz 2Hz 4Hz 16Hz 50Hz
626 * MEDIUM 0.004Hz 0.04Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 2Hz 8Hz 25Hz
627 * LIGHT 0.002Hz 0.02Hz 0.05Hz 0.1Hz 0.2Hz 0.5Hz 1Hz 4Hz 12Hz
628 *
629 * @retval Interface status (MANDATORY: return 0 -> no Error).
630 *
631 */
lsm303agr_xl_high_pass_bandwidth_get(const stmdev_ctx_t * ctx,lsm303agr_hpcf_a_t * val)632 int32_t lsm303agr_xl_high_pass_bandwidth_get(const stmdev_ctx_t *ctx,
633 lsm303agr_hpcf_a_t *val)
634 {
635 lsm303agr_ctrl_reg2_a_t ctrl_reg2_a;
636 int32_t ret;
637
638 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A,
639 (uint8_t *)&ctrl_reg2_a, 1);
640
641 switch (ctrl_reg2_a.hpcf)
642 {
643 case LSM303AGR_AGGRESSIVE:
644 *val = LSM303AGR_AGGRESSIVE;
645 break;
646
647 case LSM303AGR_STRONG:
648 *val = LSM303AGR_STRONG;
649 break;
650
651 case LSM303AGR_MEDIUM:
652 *val = LSM303AGR_MEDIUM;
653 break;
654
655 case LSM303AGR_LIGHT:
656 *val = LSM303AGR_LIGHT;
657 break;
658
659 default:
660 *val = LSM303AGR_AGGRESSIVE;
661 break;
662 }
663
664 return ret;
665 }
666
667 /**
668 * @brief High-pass filter mode selection.[set]
669 *
670 * @param ctx Read / write interface definitions.(ptr)
671 * @param val Change the values of hpm in reg CTRL_REG2_A
672 * @retval Interface status (MANDATORY: return 0 -> no Error).
673 *
674 */
lsm303agr_xl_high_pass_mode_set(const stmdev_ctx_t * ctx,lsm303agr_hpm_a_t val)675 int32_t lsm303agr_xl_high_pass_mode_set(const stmdev_ctx_t *ctx,
676 lsm303agr_hpm_a_t val)
677 {
678 lsm303agr_ctrl_reg2_a_t ctrl_reg2_a;
679 int32_t ret;
680
681 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A,
682 (uint8_t *)&ctrl_reg2_a, 1);
683
684 if (ret == 0)
685 {
686 ctrl_reg2_a.hpm = (uint8_t)val;
687 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG2_A,
688 (uint8_t *)&ctrl_reg2_a, 1);
689 }
690
691 return ret;
692 }
693
694 /**
695 * @brief High-pass filter mode selection.[get]
696 *
697 * @param ctx Read / write interface definitions.(ptr)
698 * @param val Get the values of hpm in reg CTRL_REG2_A.(ptr)
699 * @retval Interface status (MANDATORY: return 0 -> no Error).
700 *
701 */
lsm303agr_xl_high_pass_mode_get(const stmdev_ctx_t * ctx,lsm303agr_hpm_a_t * val)702 int32_t lsm303agr_xl_high_pass_mode_get(const stmdev_ctx_t *ctx,
703 lsm303agr_hpm_a_t *val)
704 {
705 lsm303agr_ctrl_reg2_a_t ctrl_reg2_a;
706 int32_t ret;
707
708 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A,
709 (uint8_t *)&ctrl_reg2_a, 1);
710
711 switch (ctrl_reg2_a.hpm)
712 {
713 case LSM303AGR_NORMAL_WITH_RST:
714 *val = LSM303AGR_NORMAL_WITH_RST;
715 break;
716
717 case LSM303AGR_REFERENCE_MODE:
718 *val = LSM303AGR_REFERENCE_MODE;
719 break;
720
721 case LSM303AGR_NORMAL:
722 *val = LSM303AGR_NORMAL;
723 break;
724
725 case LSM303AGR_AUTORST_ON_INT:
726 *val = LSM303AGR_AUTORST_ON_INT;
727 break;
728
729 default:
730 *val = LSM303AGR_NORMAL_WITH_RST;
731 break;
732 }
733
734 return ret;
735 }
736
737 /**
738 * @brief Full-scale configuration.[set]
739 *
740 * @param ctx Read / write interface definitions.(ptr)
741 * @param val Change the values of fs in reg CTRL_REG4_A
742 * @retval Interface status (MANDATORY: return 0 -> no Error).
743 *
744 */
lsm303agr_xl_full_scale_set(const stmdev_ctx_t * ctx,lsm303agr_fs_a_t val)745 int32_t lsm303agr_xl_full_scale_set(const stmdev_ctx_t *ctx,
746 lsm303agr_fs_a_t val)
747 {
748 lsm303agr_ctrl_reg4_a_t ctrl_reg4_a;
749 int32_t ret;
750
751 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
752 (uint8_t *)&ctrl_reg4_a, 1);
753
754 if (ret == 0)
755 {
756 ctrl_reg4_a.fs = (uint8_t)val;
757 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG4_A,
758 (uint8_t *)&ctrl_reg4_a, 1);
759 }
760
761 return ret;
762 }
763
764 /**
765 * @brief Full-scale configuration.[get]
766 *
767 * @param ctx Read / write interface definitions.(ptr)
768 * @param val Get the values of fs in reg CTRL_REG4_A.(ptr)
769 * @retval Interface status (MANDATORY: return 0 -> no Error).
770 *
771 */
lsm303agr_xl_full_scale_get(const stmdev_ctx_t * ctx,lsm303agr_fs_a_t * val)772 int32_t lsm303agr_xl_full_scale_get(const stmdev_ctx_t *ctx,
773 lsm303agr_fs_a_t *val)
774 {
775 lsm303agr_ctrl_reg4_a_t ctrl_reg4_a;
776 int32_t ret;
777
778 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
779 (uint8_t *)&ctrl_reg4_a, 1);
780
781 switch (ctrl_reg4_a.fs)
782 {
783 case LSM303AGR_2g:
784 *val = LSM303AGR_2g;
785 break;
786
787 case LSM303AGR_4g:
788 *val = LSM303AGR_4g;
789 break;
790
791 case LSM303AGR_8g:
792 *val = LSM303AGR_8g;
793 break;
794
795 case LSM303AGR_16g:
796 *val = LSM303AGR_16g;
797 break;
798
799 default:
800 *val = LSM303AGR_2g;
801 break;
802 }
803
804 return ret;
805 }
806
807 /**
808 * @brief Block data update.[set]
809 *
810 * @param ctx Read / write interface definitions.(ptr)
811 * @param val Change the values of bdu in reg CTRL_REG4_A
812 * @retval Interface status (MANDATORY: return 0 -> no Error).
813 *
814 */
lsm303agr_xl_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)815 int32_t lsm303agr_xl_block_data_update_set(const stmdev_ctx_t *ctx,
816 uint8_t val)
817 {
818 lsm303agr_ctrl_reg4_a_t ctrl_reg4_a;
819 int32_t ret;
820
821 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
822 (uint8_t *)&ctrl_reg4_a, 1);
823
824 if (ret == 0)
825 {
826 ctrl_reg4_a.bdu = (uint8_t)val;
827 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG4_A,
828 (uint8_t *)&ctrl_reg4_a, 1);
829 }
830
831 return ret;
832 }
833
834 /**
835 * @brief Block data update.[get]
836 *
837 * @param ctx Read / write interface definitions.(ptr)
838 * @param val Get the values of bdu in reg CTRL_REG4_A.(ptr)
839 * @retval Interface status (MANDATORY: return 0 -> no Error).
840 *
841 */
lsm303agr_xl_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)842 int32_t lsm303agr_xl_block_data_update_get(const stmdev_ctx_t *ctx,
843 uint8_t *val)
844 {
845 lsm303agr_ctrl_reg4_a_t ctrl_reg4_a;
846 int32_t ret;
847
848 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
849 (uint8_t *)&ctrl_reg4_a, 1);
850 *val = ctrl_reg4_a.bdu;
851
852 return ret;
853 }
854
855 /**
856 * @brief Reference value for interrupt generation.[set]
857 * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g
858 *
859 * @param ctx Read / write interface definitions.(ptr)
860 * @param buff Buffer that contains data to write.(ptr)
861 * @retval Interface status (MANDATORY: return 0 -> no Error).
862 *
863 */
lsm303agr_xl_filter_reference_set(const stmdev_ctx_t * ctx,uint8_t * buff)864 int32_t lsm303agr_xl_filter_reference_set(const stmdev_ctx_t *ctx,
865 uint8_t *buff)
866 {
867 int32_t ret;
868
869 ret = lsm303agr_write_reg(ctx, LSM303AGR_REFERENCE_A, buff, 1);
870
871 return ret;
872 }
873
874 /**
875 * @brief Reference value for interrupt generation.[get]
876 * LSB = ~16@2g / ~31@4g / ~63@8g / ~127@16g
877 *
878 * @param ctx Read / write interface definitions.(ptr)
879 * @param buff Buffer that stores data read.(ptr)
880 * @retval Interface status (MANDATORY: return 0 -> no Error).
881 *
882 */
lsm303agr_xl_filter_reference_get(const stmdev_ctx_t * ctx,uint8_t * buff)883 int32_t lsm303agr_xl_filter_reference_get(const stmdev_ctx_t *ctx,
884 uint8_t *buff)
885 {
886 int32_t ret;
887
888 ret = lsm303agr_read_reg(ctx, LSM303AGR_REFERENCE_A, buff, 1);
889
890 return ret;
891 }
892
893 /**
894 * @brief Acceleration set of data available.[get]
895 *
896 * @param ctx Read / write interface definitions.(ptr)
897 * @param val Get the values of zyxda in reg STATUS_REG_A.(ptr)
898 * @retval Interface status (MANDATORY: return 0 -> no Error).
899 *
900 */
lsm303agr_xl_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)901 int32_t lsm303agr_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
902 {
903 lsm303agr_status_reg_a_t status_reg_a;
904 int32_t ret;
905
906 ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_A,
907 (uint8_t *)&status_reg_a, 1);
908 *val = status_reg_a.zyxda;
909
910 return ret;
911 }
912
913 /**
914 * @brief Acceleration set of data overrun.[get]
915 *
916 * @param ctx Read / write interface definitions.(ptr)
917 * @param val Get the values of zyxor in reg STATUS_REG_A.(ptr)
918 * @retval Interface status (MANDATORY: return 0 -> no Error).
919 *
920 */
lsm303agr_xl_data_ovr_get(const stmdev_ctx_t * ctx,uint8_t * val)921 int32_t lsm303agr_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val)
922 {
923 lsm303agr_status_reg_a_t status_reg_a;
924 int32_t ret;
925
926 ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_A,
927 (uint8_t *)&status_reg_a, 1);
928 *val = status_reg_a.zyxor;
929
930 return ret;
931 }
932
933 /**
934 * @brief Acceleration output value.[get]
935 *
936 * @param ctx Read / write interface definitions.(ptr)
937 * @param buff Buffer that stores data read.(ptr)
938 * @retval Interface status (MANDATORY: return 0 -> no Error).
939 *
940 */
lsm303agr_acceleration_raw_get(const stmdev_ctx_t * ctx,int16_t * val)941 int32_t lsm303agr_acceleration_raw_get(const stmdev_ctx_t *ctx,
942 int16_t *val)
943 {
944 uint8_t buff[6];
945 int32_t ret;
946
947 ret = lsm303agr_read_reg(ctx, LSM303AGR_OUT_X_L_A, buff, 6);
948 val[0] = (int16_t)buff[1];
949 val[0] = (val[0] * 256) + (int16_t)buff[0];
950 val[1] = (int16_t)buff[3];
951 val[1] = (val[1] * 256) + (int16_t)buff[2];
952 val[2] = (int16_t)buff[5];
953 val[2] = (val[2] * 256) + (int16_t)buff[4];
954
955 return ret;
956 }
957
958 /**
959 * @brief These registers comprise a 3 group of
960 * 16-bit number and represent hard-iron
961 * offset in order to compensate environmental
962 * effects. Data format is the same of
963 * output data raw: two’s complement with
964 * 1LSb = 1.5mG. These values act on the
965 * magnetic output data value in order to
966 * delete the environmental offset.[set]
967 *
968 * @param ctx Read / write interface definitions.(ptr)
969 * @param buff Buffer that contains data to write.(ptr)
970 * @retval Interface status (MANDATORY: return 0 -> no Error).
971 *
972 */
lsm303agr_mag_user_offset_set(const stmdev_ctx_t * ctx,int16_t * val)973 int32_t lsm303agr_mag_user_offset_set(const stmdev_ctx_t *ctx, int16_t *val)
974 {
975 uint8_t buff[6];
976 int32_t ret;
977
978 buff[1] = (uint8_t)((uint16_t)val[0] / 256U);
979 buff[0] = (uint8_t)((uint16_t)val[0] - (buff[1] * 256U));
980 buff[3] = (uint8_t)((uint16_t)val[1] / 256U);
981 buff[2] = (uint8_t)((uint16_t)val[1] - (buff[3] * 256U));
982 buff[5] = (uint8_t)((uint16_t)val[2] / 256U);
983 buff[4] = (uint8_t)((uint16_t)val[2] - (buff[5] * 256U));
984 ret = lsm303agr_write_reg(ctx, LSM303AGR_OFFSET_X_REG_L_M, buff, 6);
985
986 return ret;
987 }
988
989 /**
990 * @brief These registers comprise a 3 group of
991 * 16-bit number and represent hard-iron
992 * offset in order to compensate environmental
993 * effects. Data format is the same of
994 * output data raw: two’s complement with
995 * 1LSb = 1.5mG. These values act on the
996 * magnetic output data value in order to
997 * delete the environmental offset.[get]
998 *
999 * @param ctx Read / write interface definitions.(ptr)
1000 * @param buff Buffer that stores data read.(ptr)
1001 * @retval Interface status (MANDATORY: return 0 -> no Error).
1002 *
1003 */
lsm303agr_mag_user_offset_get(const stmdev_ctx_t * ctx,int16_t * val)1004 int32_t lsm303agr_mag_user_offset_get(const stmdev_ctx_t *ctx, int16_t *val)
1005 {
1006 uint8_t buff[6];
1007 int32_t ret;
1008
1009 ret = lsm303agr_read_reg(ctx, LSM303AGR_OFFSET_X_REG_L_M, buff, 6);
1010 val[0] = (int16_t)buff[1];
1011 val[0] = (val[0] * 256) + (int16_t)buff[0];
1012 val[1] = (int16_t)buff[3];
1013 val[1] = (val[1] * 256) + (int16_t)buff[2];
1014 val[2] = (int16_t)buff[5];
1015 val[2] = (val[2] * 256) + (int16_t)buff[4];
1016
1017 return ret;
1018 }
1019
1020 /**
1021 * @brief Operating mode selection.[set]
1022 *
1023 * @param ctx Read / write interface definitions.(ptr)
1024 * @param val Change the values of md in reg CFG_REG_A_M
1025 * @retval Interface status (MANDATORY: return 0 -> no Error).
1026 *
1027 */
lsm303agr_mag_operating_mode_set(const stmdev_ctx_t * ctx,lsm303agr_md_m_t val)1028 int32_t lsm303agr_mag_operating_mode_set(const stmdev_ctx_t *ctx,
1029 lsm303agr_md_m_t val)
1030 {
1031 lsm303agr_cfg_reg_a_m_t cfg_reg_a_m;
1032 int32_t ret;
1033
1034 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
1035 (uint8_t *)&cfg_reg_a_m, 1);
1036
1037 if (ret == 0)
1038 {
1039 cfg_reg_a_m.md = (uint8_t)val;
1040 ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_A_M,
1041 (uint8_t *)&cfg_reg_a_m, 1);
1042 }
1043
1044 return ret;
1045 }
1046
1047 /**
1048 * @brief Operating mode selection.[get]
1049 *
1050 * @param ctx Read / write interface definitions.(ptr)
1051 * @param val Get the values of md in reg CFG_REG_A_M.(ptr)
1052 * @retval Interface status (MANDATORY: return 0 -> no Error).
1053 *
1054 */
lsm303agr_mag_operating_mode_get(const stmdev_ctx_t * ctx,lsm303agr_md_m_t * val)1055 int32_t lsm303agr_mag_operating_mode_get(const stmdev_ctx_t *ctx,
1056 lsm303agr_md_m_t *val)
1057 {
1058 lsm303agr_cfg_reg_a_m_t cfg_reg_a_m;
1059 int32_t ret;
1060
1061 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
1062 (uint8_t *)&cfg_reg_a_m, 1);
1063
1064 switch (cfg_reg_a_m.md)
1065 {
1066 case LSM303AGR_CONTINUOUS_MODE:
1067 *val = LSM303AGR_CONTINUOUS_MODE;
1068 break;
1069
1070 case LSM303AGR_SINGLE_TRIGGER:
1071 *val = LSM303AGR_SINGLE_TRIGGER;
1072 break;
1073
1074 case LSM303AGR_POWER_DOWN:
1075 *val = LSM303AGR_POWER_DOWN;
1076 break;
1077
1078 default:
1079 *val = LSM303AGR_CONTINUOUS_MODE;
1080 break;
1081 }
1082
1083 return ret;
1084 }
1085
1086 /**
1087 * @brief Output data rate selection.[set]
1088 *
1089 * @param ctx Read / write interface definitions.(ptr)
1090 * @param val Change the values of odr in reg CFG_REG_A_M
1091 * @retval Interface status (MANDATORY: return 0 -> no Error).
1092 *
1093 */
lsm303agr_mag_data_rate_set(const stmdev_ctx_t * ctx,lsm303agr_mg_odr_m_t val)1094 int32_t lsm303agr_mag_data_rate_set(const stmdev_ctx_t *ctx,
1095 lsm303agr_mg_odr_m_t val)
1096 {
1097 lsm303agr_cfg_reg_a_m_t cfg_reg_a_m;
1098 int32_t ret;
1099
1100 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
1101 (uint8_t *)&cfg_reg_a_m, 1);
1102
1103 if (ret == 0)
1104 {
1105 cfg_reg_a_m.odr = (uint8_t)val;
1106 ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_A_M,
1107 (uint8_t *)&cfg_reg_a_m, 1);
1108 }
1109
1110 return ret;
1111 }
1112
1113 /**
1114 * @brief Output data rate selection.[get]
1115 *
1116 * @param ctx Read / write interface definitions.(ptr)
1117 * @param val Get the values of odr in reg CFG_REG_A_M.(ptr)
1118 * @retval Interface status (MANDATORY: return 0 -> no Error).
1119 *
1120 */
lsm303agr_mag_data_rate_get(const stmdev_ctx_t * ctx,lsm303agr_mg_odr_m_t * val)1121 int32_t lsm303agr_mag_data_rate_get(const stmdev_ctx_t *ctx,
1122 lsm303agr_mg_odr_m_t *val)
1123 {
1124 lsm303agr_cfg_reg_a_m_t cfg_reg_a_m;
1125 int32_t ret;
1126
1127 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
1128 (uint8_t *)&cfg_reg_a_m, 1);
1129
1130 switch (cfg_reg_a_m.odr)
1131 {
1132 case LSM303AGR_MG_ODR_10Hz:
1133 *val = LSM303AGR_MG_ODR_10Hz;
1134 break;
1135
1136 case LSM303AGR_MG_ODR_20Hz:
1137 *val = LSM303AGR_MG_ODR_20Hz;
1138 break;
1139
1140 case LSM303AGR_MG_ODR_50Hz:
1141 *val = LSM303AGR_MG_ODR_50Hz;
1142 break;
1143
1144 case LSM303AGR_MG_ODR_100Hz:
1145 *val = LSM303AGR_MG_ODR_100Hz;
1146 break;
1147
1148 default:
1149 *val = LSM303AGR_MG_ODR_10Hz;
1150 break;
1151 }
1152
1153 return ret;
1154 }
1155
1156 /**
1157 * @brief Enables high-resolution/low-power mode.[set]
1158 *
1159 * @param ctx Read / write interface definitions.(ptr)
1160 * @param val Change the values of lp in reg CFG_REG_A_M
1161 * @retval Interface status (MANDATORY: return 0 -> no Error).
1162 *
1163 */
lsm303agr_mag_power_mode_set(const stmdev_ctx_t * ctx,lsm303agr_lp_m_t val)1164 int32_t lsm303agr_mag_power_mode_set(const stmdev_ctx_t *ctx,
1165 lsm303agr_lp_m_t val)
1166 {
1167 lsm303agr_cfg_reg_a_m_t cfg_reg_a_m;
1168 int32_t ret;
1169
1170 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
1171 (uint8_t *)&cfg_reg_a_m, 1);
1172
1173 if (ret == 0)
1174 {
1175 cfg_reg_a_m.lp = (uint8_t)val;
1176 ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_A_M,
1177 (uint8_t *)&cfg_reg_a_m, 1);
1178 }
1179
1180 return ret;
1181 }
1182
1183 /**
1184 * @brief Enables high-resolution/low-power mode.[get]
1185 *
1186 * @param ctx Read / write interface definitions.(ptr)
1187 * @param val Get the values of lp in reg CFG_REG_A_M.(ptr)
1188 * @retval Interface status (MANDATORY: return 0 -> no Error).
1189 *
1190 */
lsm303agr_mag_power_mode_get(const stmdev_ctx_t * ctx,lsm303agr_lp_m_t * val)1191 int32_t lsm303agr_mag_power_mode_get(const stmdev_ctx_t *ctx,
1192 lsm303agr_lp_m_t *val)
1193 {
1194 lsm303agr_cfg_reg_a_m_t cfg_reg_a_m;
1195 int32_t ret;
1196
1197 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
1198 (uint8_t *)&cfg_reg_a_m, 1);
1199
1200 switch (cfg_reg_a_m.lp)
1201 {
1202 case LSM303AGR_HIGH_RESOLUTION:
1203 *val = LSM303AGR_HIGH_RESOLUTION;
1204 break;
1205
1206 case LSM303AGR_LOW_POWER:
1207 *val = LSM303AGR_LOW_POWER;
1208 break;
1209
1210 default:
1211 *val = LSM303AGR_HIGH_RESOLUTION;
1212 break;
1213 }
1214
1215 return ret;
1216 }
1217
1218 /**
1219 * @brief Enables the magnetometer temperature compensation.[set]
1220 *
1221 * @param ctx Read / write interface definitions.(ptr)
1222 * @param val Change the values of comp_temp_en in reg CFG_REG_A_M
1223 * @retval Interface status (MANDATORY: return 0 -> no Error).
1224 *
1225 */
lsm303agr_mag_offset_temp_comp_set(const stmdev_ctx_t * ctx,uint8_t val)1226 int32_t lsm303agr_mag_offset_temp_comp_set(const stmdev_ctx_t *ctx,
1227 uint8_t val)
1228 {
1229 lsm303agr_cfg_reg_a_m_t cfg_reg_a_m;
1230 int32_t ret;
1231
1232 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
1233 (uint8_t *)&cfg_reg_a_m, 1);
1234
1235 if (ret == 0)
1236 {
1237 cfg_reg_a_m.comp_temp_en = (uint8_t)val;
1238 ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_A_M,
1239 (uint8_t *)&cfg_reg_a_m, 1);
1240 }
1241
1242 return ret;
1243 }
1244
1245 /**
1246 * @brief Enables the magnetometer temperature compensation.[get]
1247 *
1248 * @param ctx Read / write interface definitions.(ptr)
1249 * @param val Get the values of comp_temp_en in reg CFG_REG_A_M.(ptr)
1250 * @retval Interface status (MANDATORY: return 0 -> no Error).
1251 *
1252 */
lsm303agr_mag_offset_temp_comp_get(const stmdev_ctx_t * ctx,uint8_t * val)1253 int32_t lsm303agr_mag_offset_temp_comp_get(const stmdev_ctx_t *ctx,
1254 uint8_t *val)
1255 {
1256 lsm303agr_cfg_reg_a_m_t cfg_reg_a_m;
1257 int32_t ret;
1258
1259 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
1260 (uint8_t *)&cfg_reg_a_m, 1);
1261 *val = cfg_reg_a_m.comp_temp_en;
1262
1263 return ret;
1264 }
1265
1266 /**
1267 * @brief Low-pass bandwidth selection.[set]
1268 *
1269 * @param ctx Read / write interface definitions.(ptr)
1270 * @param val Change the values of lpf in reg CFG_REG_B_M
1271 * @retval Interface status (MANDATORY: return 0 -> no Error).
1272 *
1273 */
lsm303agr_mag_low_pass_bandwidth_set(const stmdev_ctx_t * ctx,lsm303agr_lpf_m_t val)1274 int32_t lsm303agr_mag_low_pass_bandwidth_set(const stmdev_ctx_t *ctx,
1275 lsm303agr_lpf_m_t val)
1276 {
1277 lsm303agr_cfg_reg_b_m_t cfg_reg_b_m;
1278 int32_t ret;
1279
1280 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M,
1281 (uint8_t *)&cfg_reg_b_m, 1);
1282
1283 if (ret == 0)
1284 {
1285 cfg_reg_b_m.lpf = (uint8_t)val;
1286 ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_B_M,
1287 (uint8_t *)&cfg_reg_b_m, 1);
1288 }
1289
1290 return ret;
1291 }
1292
1293 /**
1294 * @brief Low-pass bandwidth selection.[get]
1295 *
1296 * @param ctx Read / write interface definitions.(ptr)
1297 * @param val Get the values of lpf in reg CFG_REG_B_M.(ptr)
1298 * @retval Interface status (MANDATORY: return 0 -> no Error).
1299 *
1300 */
lsm303agr_mag_low_pass_bandwidth_get(const stmdev_ctx_t * ctx,lsm303agr_lpf_m_t * val)1301 int32_t lsm303agr_mag_low_pass_bandwidth_get(const stmdev_ctx_t *ctx,
1302 lsm303agr_lpf_m_t *val)
1303 {
1304 lsm303agr_cfg_reg_b_m_t cfg_reg_b_m;
1305 int32_t ret;
1306
1307 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M,
1308 (uint8_t *)&cfg_reg_b_m, 1);
1309
1310 switch (cfg_reg_b_m.lpf)
1311 {
1312 case LSM303AGR_ODR_DIV_2:
1313 *val = LSM303AGR_ODR_DIV_2;
1314 break;
1315
1316 case LSM303AGR_ODR_DIV_4:
1317 *val = LSM303AGR_ODR_DIV_4;
1318 break;
1319
1320 default:
1321 *val = LSM303AGR_ODR_DIV_2;
1322 break;
1323 }
1324
1325 return ret;
1326 }
1327
1328 /**
1329 * @brief Magnetometer sampling mode.[set]
1330 *
1331 * @param ctx Read / write interface definitions.(ptr)
1332 * @param val Change the values of set_rst in reg CFG_REG_B_M
1333 * @retval Interface status (MANDATORY: return 0 -> no Error).
1334 *
1335 */
lsm303agr_mag_set_rst_mode_set(const stmdev_ctx_t * ctx,lsm303agr_set_rst_m_t val)1336 int32_t lsm303agr_mag_set_rst_mode_set(const stmdev_ctx_t *ctx,
1337 lsm303agr_set_rst_m_t val)
1338 {
1339 lsm303agr_cfg_reg_b_m_t cfg_reg_b_m;
1340 int32_t ret;
1341
1342 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M,
1343 (uint8_t *)&cfg_reg_b_m, 1);
1344
1345 if (ret == 0)
1346 {
1347 cfg_reg_b_m.set_rst = (uint8_t)val;
1348 ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_B_M,
1349 (uint8_t *)&cfg_reg_b_m, 1);
1350 }
1351
1352 return ret;
1353 }
1354
1355 /**
1356 * @brief Magnetometer sampling mode.[get]
1357 *
1358 * @param ctx Read / write interface definitions.(ptr)
1359 * @param val Get the values of set_rst in reg CFG_REG_B_M.(ptr)
1360 * @retval Interface status (MANDATORY: return 0 -> no Error).
1361 *
1362 */
lsm303agr_mag_set_rst_mode_get(const stmdev_ctx_t * ctx,lsm303agr_set_rst_m_t * val)1363 int32_t lsm303agr_mag_set_rst_mode_get(const stmdev_ctx_t *ctx,
1364 lsm303agr_set_rst_m_t *val)
1365 {
1366 lsm303agr_cfg_reg_b_m_t cfg_reg_b_m;
1367 int32_t ret;
1368
1369 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M,
1370 (uint8_t *)&cfg_reg_b_m, 1);
1371
1372 switch (cfg_reg_b_m.set_rst)
1373 {
1374 case LSM303AGR_SET_SENS_ODR_DIV_63:
1375 *val = LSM303AGR_SET_SENS_ODR_DIV_63;
1376 break;
1377
1378 case LSM303AGR_SENS_OFF_CANC_EVERY_ODR:
1379 *val = LSM303AGR_SENS_OFF_CANC_EVERY_ODR;
1380 break;
1381
1382 case LSM303AGR_SET_SENS_ONLY_AT_POWER_ON:
1383 *val = LSM303AGR_SET_SENS_ONLY_AT_POWER_ON;
1384 break;
1385
1386 default:
1387 *val = LSM303AGR_SET_SENS_ODR_DIV_63;
1388 break;
1389 }
1390
1391 return ret;
1392 }
1393
1394 /**
1395 * @brief Enables offset cancellation in single measurement mode.
1396 * The OFF_CANC bit must be set
1397 * to 1 when enabling offset
1398 * cancellation in single measurement
1399 * mode this means a call function:
1400 * mag_set_rst_mode
1401 * (SENS_OFF_CANC_EVERY_ODR) is need.[set]
1402 *
1403 * @param ctx Read / write interface definitions.(ptr)
1404 * @param val Change the values of off_canc_one_shot in reg CFG_REG_B_M
1405 * @retval Interface status (MANDATORY: return 0 -> no Error).
1406 *
1407 */
lsm303agr_mag_set_rst_sensor_single_set(const stmdev_ctx_t * ctx,uint8_t val)1408 int32_t lsm303agr_mag_set_rst_sensor_single_set(const stmdev_ctx_t *ctx,
1409 uint8_t val)
1410 {
1411 lsm303agr_cfg_reg_b_m_t cfg_reg_b_m;
1412 int32_t ret;
1413
1414 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M,
1415 (uint8_t *)&cfg_reg_b_m, 1);
1416
1417 if (ret == 0)
1418 {
1419 cfg_reg_b_m.off_canc_one_shot = (uint8_t)val;
1420 ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_B_M,
1421 (uint8_t *)&cfg_reg_b_m, 1);
1422 }
1423
1424 return ret;
1425 }
1426
1427 /**
1428 * @brief Enables offset cancellation in single measurement mode.
1429 * The OFF_CANC bit must be set to
1430 * 1 when enabling offset cancellation
1431 * in single measurement mode this
1432 * means a call function:
1433 * mag_set_rst_mode
1434 * (SENS_OFF_CANC_EVERY_ODR) is need.[get]
1435 *
1436 * @param ctx Read / write interface definitions.(ptr)
1437 * @param val Get the values of off_canc_one_shot in
1438 * reg CFG_REG_B_M.(ptr)
1439 * @retval Interface status (MANDATORY: return 0 -> no Error).
1440 *
1441 */
lsm303agr_mag_set_rst_sensor_single_get(const stmdev_ctx_t * ctx,uint8_t * val)1442 int32_t lsm303agr_mag_set_rst_sensor_single_get(const stmdev_ctx_t *ctx,
1443 uint8_t *val)
1444 {
1445 lsm303agr_cfg_reg_b_m_t cfg_reg_b_m;
1446 int32_t ret;
1447
1448 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M,
1449 (uint8_t *)&cfg_reg_b_m, 1);
1450 *val = cfg_reg_b_m.off_canc_one_shot;
1451
1452 return ret;
1453 }
1454
1455 /**
1456 * @brief Blockdataupdate.[set]
1457 *
1458 * @param ctx Read / write interface definitions.(ptr)
1459 * @param val Change the values of bdu in reg CFG_REG_C_M
1460 * @retval Interface status (MANDATORY: return 0 -> no Error).
1461 *
1462 */
lsm303agr_mag_block_data_update_set(const stmdev_ctx_t * ctx,uint8_t val)1463 int32_t lsm303agr_mag_block_data_update_set(const stmdev_ctx_t *ctx,
1464 uint8_t val)
1465 {
1466 lsm303agr_cfg_reg_c_m_t cfg_reg_c_m;
1467 int32_t ret;
1468
1469 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
1470 (uint8_t *)&cfg_reg_c_m, 1);
1471
1472 if (ret == 0)
1473 {
1474 cfg_reg_c_m.bdu = (uint8_t)val;
1475 ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_C_M,
1476 (uint8_t *)&cfg_reg_c_m, 1);
1477 }
1478
1479 return ret;
1480 }
1481
1482 /**
1483 * @brief Blockdataupdate.[get]
1484 *
1485 * @param ctx Read / write interface definitions.(ptr)
1486 * @param val Get the values of bdu in reg CFG_REG_C_M.(ptr)
1487 * @retval Interface status (MANDATORY: return 0 -> no Error).
1488 *
1489 */
lsm303agr_mag_block_data_update_get(const stmdev_ctx_t * ctx,uint8_t * val)1490 int32_t lsm303agr_mag_block_data_update_get(const stmdev_ctx_t *ctx,
1491 uint8_t *val)
1492 {
1493 lsm303agr_cfg_reg_c_m_t cfg_reg_c_m;
1494 int32_t ret;
1495
1496 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
1497 (uint8_t *)&cfg_reg_c_m, 1);
1498 *val = cfg_reg_c_m.bdu;
1499
1500 return ret;
1501 }
1502
1503 /**
1504 * @brief Magnetic set of data available.[get]
1505 *
1506 * @param ctx Read / write interface definitions.(ptr)
1507 * @param val Get the values of zyxda in reg STATUS_REG_M.(ptr)
1508 * @retval Interface status (MANDATORY: return 0 -> no Error).
1509 *
1510 */
lsm303agr_mag_data_ready_get(const stmdev_ctx_t * ctx,uint8_t * val)1511 int32_t lsm303agr_mag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val)
1512 {
1513 lsm303agr_status_reg_m_t status_reg_m;
1514 int32_t ret;
1515
1516 ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_M,
1517 (uint8_t *)&status_reg_m, 1);
1518 *val = status_reg_m.zyxda;
1519
1520 return ret;
1521 }
1522
1523 /**
1524 * @brief Magnetic set of data overrun.[get]
1525 *
1526 * @param ctx Read / write interface definitions.(ptr)
1527 * @param val Get the values of zyxor in reg STATUS_REG_M.(ptr)
1528 * @retval Interface status (MANDATORY: return 0 -> no Error).
1529 *
1530 */
lsm303agr_mag_data_ovr_get(const stmdev_ctx_t * ctx,uint8_t * val)1531 int32_t lsm303agr_mag_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val)
1532 {
1533 lsm303agr_status_reg_m_t status_reg_m;
1534 int32_t ret;
1535
1536 ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_M,
1537 (uint8_t *)&status_reg_m, 1);
1538 *val = status_reg_m.zyxor;
1539
1540 return ret;
1541 }
1542
1543 /**
1544 * @brief Magnetic output value.[get]
1545 *
1546 * @param ctx Read / write interface definitions.(ptr)
1547 * @param buff Buffer that stores data read.(ptr)
1548 * @retval Interface status (MANDATORY: return 0 -> no Error).
1549 *
1550 */
lsm303agr_magnetic_raw_get(const stmdev_ctx_t * ctx,int16_t * val)1551 int32_t lsm303agr_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val)
1552 {
1553 uint8_t buff[6];
1554 int32_t ret;
1555
1556 ret = lsm303agr_read_reg(ctx, LSM303AGR_OUTX_L_REG_M, buff, 6);
1557 val[0] = (int16_t)buff[1];
1558 val[0] = (val[0] * 256) + (int16_t)buff[0];
1559 val[1] = (int16_t)buff[3];
1560 val[1] = (val[1] * 256) + (int16_t)buff[2];
1561 val[2] = (int16_t)buff[5];
1562 val[2] = (val[2] * 256) + (int16_t)buff[4];
1563
1564 return ret;
1565 }
1566
1567 /**
1568 * @}
1569 *
1570 */
1571
1572 /**
1573 * @addtogroup common
1574 * @brief This section group common useful functions
1575 * @{
1576 *
1577 */
1578
1579 /**
1580 * @brief DeviceWhoamI.[get]
1581 *
1582 * @param ctx Read / write interface definitions.(ptr)
1583 * @param buff Buffer that stores data read.(ptr)
1584 * @retval Interface status (MANDATORY: return 0 -> no Error).
1585 *
1586 */
lsm303agr_xl_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)1587 int32_t lsm303agr_xl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1588 {
1589 int32_t ret;
1590
1591 ret = lsm303agr_read_reg(ctx, LSM303AGR_WHO_AM_I_A, buff, 1);
1592
1593 return ret;
1594 }
1595
1596 /**
1597 * @brief Self-test.[set]
1598 *
1599 * @param ctx Read / write interface definitions.(ptr)
1600 * @param val Change the values of st in reg CTRL_REG4_A
1601 * @retval Interface status (MANDATORY: return 0 -> no Error).
1602 *
1603 */
lsm303agr_xl_self_test_set(const stmdev_ctx_t * ctx,lsm303agr_st_a_t val)1604 int32_t lsm303agr_xl_self_test_set(const stmdev_ctx_t *ctx,
1605 lsm303agr_st_a_t val)
1606 {
1607 lsm303agr_ctrl_reg4_a_t ctrl_reg4_a;
1608 int32_t ret;
1609
1610 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
1611 (uint8_t *)&ctrl_reg4_a, 1);
1612
1613 if (ret == 0)
1614 {
1615 ctrl_reg4_a.st = (uint8_t)val;
1616 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG4_A,
1617 (uint8_t *)&ctrl_reg4_a, 1);
1618 }
1619
1620 return ret;
1621 }
1622
1623 /**
1624 * @brief Self-test.[get]
1625 *
1626 * @param ctx Read / write interface definitions.(ptr)
1627 * @param val Get the values of st in reg CTRL_REG4_A.(ptr)
1628 * @retval Interface status (MANDATORY: return 0 -> no Error).
1629 *
1630 */
lsm303agr_xl_self_test_get(const stmdev_ctx_t * ctx,lsm303agr_st_a_t * val)1631 int32_t lsm303agr_xl_self_test_get(const stmdev_ctx_t *ctx,
1632 lsm303agr_st_a_t *val)
1633 {
1634 lsm303agr_ctrl_reg4_a_t ctrl_reg4_a;
1635 int32_t ret;
1636
1637 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
1638 (uint8_t *)&ctrl_reg4_a, 1);
1639
1640 switch (ctrl_reg4_a.st)
1641 {
1642 case LSM303AGR_ST_DISABLE:
1643 *val = LSM303AGR_ST_DISABLE;
1644 break;
1645
1646 case LSM303AGR_ST_POSITIVE:
1647 *val = LSM303AGR_ST_POSITIVE;
1648 break;
1649
1650 case LSM303AGR_ST_NEGATIVE:
1651 *val = LSM303AGR_ST_NEGATIVE;
1652 break;
1653
1654 default:
1655 *val = LSM303AGR_ST_DISABLE;
1656 break;
1657 }
1658
1659 return ret;
1660 }
1661
1662 /**
1663 * @brief Big/Little Endian data selection.[set]
1664 *
1665 * @param ctx Read / write interface definitions.(ptr)
1666 * @param val Change the values of ble in reg CTRL_REG4_A
1667 * @retval Interface status (MANDATORY: return 0 -> no Error).
1668 *
1669 */
lsm303agr_xl_data_format_set(const stmdev_ctx_t * ctx,lsm303agr_ble_a_t val)1670 int32_t lsm303agr_xl_data_format_set(const stmdev_ctx_t *ctx,
1671 lsm303agr_ble_a_t val)
1672 {
1673 lsm303agr_ctrl_reg4_a_t ctrl_reg4_a;
1674 int32_t ret;
1675
1676 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
1677 (uint8_t *)&ctrl_reg4_a, 1);
1678
1679 if (ret == 0)
1680 {
1681 ctrl_reg4_a.ble = (uint8_t)val;
1682 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG4_A,
1683 (uint8_t *)&ctrl_reg4_a, 1);
1684 }
1685
1686 return ret;
1687 }
1688
1689 /**
1690 * @brief Big/Little Endian data selection.[get]
1691 *
1692 * @param ctx Read / write interface definitions.(ptr)
1693 * @param val Get the values of ble in reg CTRL_REG4_A.(ptr)
1694 * @retval Interface status (MANDATORY: return 0 -> no Error).
1695 *
1696 */
lsm303agr_xl_data_format_get(const stmdev_ctx_t * ctx,lsm303agr_ble_a_t * val)1697 int32_t lsm303agr_xl_data_format_get(const stmdev_ctx_t *ctx,
1698 lsm303agr_ble_a_t *val)
1699 {
1700 lsm303agr_ctrl_reg4_a_t ctrl_reg4_a;
1701 int32_t ret;
1702
1703 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
1704 (uint8_t *)&ctrl_reg4_a, 1);
1705
1706 switch (ctrl_reg4_a.ble)
1707 {
1708 case LSM303AGR_XL_LSB_AT_LOW_ADD:
1709 *val = LSM303AGR_XL_LSB_AT_LOW_ADD;
1710 break;
1711
1712 case LSM303AGR_XL_MSB_AT_LOW_ADD:
1713 *val = LSM303AGR_XL_MSB_AT_LOW_ADD;
1714 break;
1715
1716 default:
1717 *val = LSM303AGR_XL_LSB_AT_LOW_ADD;
1718 break;
1719 }
1720
1721 return ret;
1722 }
1723
1724 /**
1725 * @brief Reboot memory content. Reload the calibration parameters.[set]
1726 *
1727 * @param ctx Read / write interface definitions.(ptr)
1728 * @param val Change the values of boot in reg CTRL_REG5_A
1729 * @retval Interface status (MANDATORY: return 0 -> no Error).
1730 *
1731 */
lsm303agr_xl_boot_set(const stmdev_ctx_t * ctx,uint8_t val)1732 int32_t lsm303agr_xl_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
1733 {
1734 lsm303agr_ctrl_reg5_a_t ctrl_reg5_a;
1735 int32_t ret;
1736
1737 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
1738 (uint8_t *)&ctrl_reg5_a, 1);
1739
1740 if (ret == 0)
1741 {
1742 ctrl_reg5_a.boot = (uint8_t)val;
1743 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG5_A,
1744 (uint8_t *)&ctrl_reg5_a, 1);
1745 }
1746
1747 return ret;
1748 }
1749
1750 /**
1751 * @brief Reboot memory content. Reload the calibration parameters.[get]
1752 *
1753 * @param ctx Read / write interface definitions.(ptr)
1754 * @param val Get the values of boot in reg CTRL_REG5_A.(ptr)
1755 * @retval Interface status (MANDATORY: return 0 -> no Error).
1756 *
1757 */
lsm303agr_xl_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)1758 int32_t lsm303agr_xl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
1759 {
1760 lsm303agr_ctrl_reg5_a_t ctrl_reg5_a;
1761 int32_t ret;
1762
1763 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
1764 (uint8_t *)&ctrl_reg5_a, 1);
1765 *val = ctrl_reg5_a.boot;
1766
1767 return ret;
1768 }
1769
1770 /**
1771 * @brief Info about device status.[get]
1772 *
1773 * @param ctx Read / write interface definitions.(ptr)
1774 * @param val Get register STATUS_REG_A.(ptr)
1775 * @retval Interface status (MANDATORY: return 0 -> no Error).
1776 *
1777 */
lsm303agr_xl_status_get(const stmdev_ctx_t * ctx,lsm303agr_status_reg_a_t * val)1778 int32_t lsm303agr_xl_status_get(const stmdev_ctx_t *ctx,
1779 lsm303agr_status_reg_a_t *val)
1780 {
1781 int32_t ret;
1782
1783 ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_A, (uint8_t *) val, 1);
1784
1785 return ret;
1786 }
1787
1788 /**
1789 * @brief DeviceWhoamI.[get]
1790 *
1791 * @param ctx Read / write interface definitions.(ptr)
1792 * @param buff Buffer that stores data read.(ptr)
1793 * @retval Interface status (MANDATORY: return 0 -> no Error).
1794 *
1795 */
lsm303agr_mag_device_id_get(const stmdev_ctx_t * ctx,uint8_t * buff)1796 int32_t lsm303agr_mag_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff)
1797 {
1798 int32_t ret;
1799
1800 ret = lsm303agr_read_reg(ctx, LSM303AGR_WHO_AM_I_M, buff, 1);
1801
1802 return ret;
1803 }
1804
1805 /**
1806 * @brief Software reset. Restore the default values in user registers.[set]
1807 *
1808 * @param ctx Read / write interface definitions.(ptr)
1809 * @param val Change the values of soft_rst in reg CFG_REG_A_M
1810 * @retval Interface status (MANDATORY: return 0 -> no Error).
1811 *
1812 */
lsm303agr_mag_reset_set(const stmdev_ctx_t * ctx,uint8_t val)1813 int32_t lsm303agr_mag_reset_set(const stmdev_ctx_t *ctx, uint8_t val)
1814 {
1815 lsm303agr_cfg_reg_a_m_t cfg_reg_a_m;
1816 int32_t ret;
1817
1818 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
1819 (uint8_t *)&cfg_reg_a_m, 1);
1820
1821 if (ret == 0)
1822 {
1823 cfg_reg_a_m.soft_rst = (uint8_t)val;
1824 ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_A_M,
1825 (uint8_t *)&cfg_reg_a_m, 1);
1826 }
1827
1828 return ret;
1829 }
1830
1831 /**
1832 * @brief Software reset. Restore the default values in user registers.[get]
1833 *
1834 * @param ctx Read / write interface definitions.(ptr)
1835 * @param val Change the values of soft_rst in reg CFG_REG_A_M.(ptr)
1836 * @retval Interface status (MANDATORY: return 0 -> no Error).
1837 *
1838 */
lsm303agr_mag_reset_get(const stmdev_ctx_t * ctx,uint8_t * val)1839 int32_t lsm303agr_mag_reset_get(const stmdev_ctx_t *ctx, uint8_t *val)
1840 {
1841 lsm303agr_cfg_reg_a_m_t cfg_reg_a_m;
1842 int32_t ret;
1843
1844 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
1845 (uint8_t *)&cfg_reg_a_m, 1);
1846 *val = cfg_reg_a_m.soft_rst;
1847
1848 return ret;
1849 }
1850
1851 /**
1852 * @brief Reboot memory content. Reload the calibration parameters.[set]
1853 *
1854 * @param ctx Read / write interface definitions.(ptr)
1855 * @param val Change the values of reboot in reg CFG_REG_A_M
1856 * @retval Interface status (MANDATORY: return 0 -> no Error).
1857 *
1858 */
lsm303agr_mag_boot_set(const stmdev_ctx_t * ctx,uint8_t val)1859 int32_t lsm303agr_mag_boot_set(const stmdev_ctx_t *ctx, uint8_t val)
1860 {
1861 lsm303agr_cfg_reg_a_m_t cfg_reg_a_m;
1862 int32_t ret;
1863
1864 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
1865 (uint8_t *)&cfg_reg_a_m, 1);
1866
1867 if (ret == 0)
1868 {
1869 cfg_reg_a_m.reboot = (uint8_t)val;
1870 ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_A_M,
1871 (uint8_t *)&cfg_reg_a_m, 1);
1872 }
1873
1874 return ret;
1875 }
1876
1877 /**
1878 * @brief Reboot memory content. Reload the calibration parameters.[get]
1879 *
1880 * @param ctx Read / write interface definitions.(ptr)
1881 * @param val Get the values of reboot in reg CFG_REG_A_M.(ptr)
1882 * @retval Interface status (MANDATORY: return 0 -> no Error).
1883 *
1884 */
lsm303agr_mag_boot_get(const stmdev_ctx_t * ctx,uint8_t * val)1885 int32_t lsm303agr_mag_boot_get(const stmdev_ctx_t *ctx, uint8_t *val)
1886 {
1887 lsm303agr_cfg_reg_a_m_t cfg_reg_a_m;
1888 int32_t ret;
1889
1890 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_A_M,
1891 (uint8_t *)&cfg_reg_a_m, 1);
1892 *val = cfg_reg_a_m.reboot;
1893
1894 return ret;
1895 }
1896
1897 /**
1898 * @brief Selftest.[set]
1899 *
1900 * @param ctx Read / write interface definitions.(ptr)
1901 * @param val Change the values of self_test in reg CFG_REG_C_M
1902 * @retval Interface status (MANDATORY: return 0 -> no Error).
1903 *
1904 */
lsm303agr_mag_self_test_set(const stmdev_ctx_t * ctx,uint8_t val)1905 int32_t lsm303agr_mag_self_test_set(const stmdev_ctx_t *ctx, uint8_t val)
1906 {
1907 lsm303agr_cfg_reg_c_m_t cfg_reg_c_m;
1908 int32_t ret;
1909
1910 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
1911 (uint8_t *)&cfg_reg_c_m, 1);
1912
1913 if (ret == 0)
1914 {
1915 cfg_reg_c_m.self_test = (uint8_t)val;
1916 ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_C_M,
1917 (uint8_t *)&cfg_reg_c_m, 1);
1918 }
1919
1920 return ret;
1921 }
1922
1923 /**
1924 * @brief Selftest.[get]
1925 *
1926 * @param ctx Read / write interface definitions.(ptr)
1927 * @param val Get the values of self_test in reg CFG_REG_C_M.(ptr)
1928 * @retval Interface status (MANDATORY: return 0 -> no Error).
1929 *
1930 */
lsm303agr_mag_self_test_get(const stmdev_ctx_t * ctx,uint8_t * val)1931 int32_t lsm303agr_mag_self_test_get(const stmdev_ctx_t *ctx, uint8_t *val)
1932 {
1933 lsm303agr_cfg_reg_c_m_t cfg_reg_c_m;
1934 int32_t ret;
1935
1936 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
1937 (uint8_t *)&cfg_reg_c_m, 1);
1938 *val = cfg_reg_c_m.self_test;
1939
1940 return ret;
1941 }
1942
1943 /**
1944 * @brief Big/Little Endian data selection.[set]
1945 *
1946 * @param ctx Read / write interface definitions.(ptr)
1947 * @param val Change the values of ble in reg CFG_REG_C_M
1948 * @retval Interface status (MANDATORY: return 0 -> no Error).
1949 *
1950 */
lsm303agr_mag_data_format_set(const stmdev_ctx_t * ctx,lsm303agr_ble_m_t val)1951 int32_t lsm303agr_mag_data_format_set(const stmdev_ctx_t *ctx,
1952 lsm303agr_ble_m_t val)
1953 {
1954 lsm303agr_cfg_reg_c_m_t cfg_reg_c_m;
1955 int32_t ret;
1956
1957 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
1958 (uint8_t *)&cfg_reg_c_m, 1);
1959
1960 if (ret == 0)
1961 {
1962 cfg_reg_c_m.ble = (uint8_t)val;
1963 ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_C_M,
1964 (uint8_t *)&cfg_reg_c_m, 1);
1965 }
1966
1967 return ret;
1968 }
1969
1970 /**
1971 * @brief Big/Little Endian data selection.[get]
1972 *
1973 * @param ctx Read / write interface definitions.(ptr)
1974 * @param val Get the values of ble in reg CFG_REG_C_M.(ptr)
1975 * @retval Interface status (MANDATORY: return 0 -> no Error).
1976 *
1977 */
lsm303agr_mag_data_format_get(const stmdev_ctx_t * ctx,lsm303agr_ble_m_t * val)1978 int32_t lsm303agr_mag_data_format_get(const stmdev_ctx_t *ctx,
1979 lsm303agr_ble_m_t *val)
1980 {
1981 lsm303agr_cfg_reg_c_m_t cfg_reg_c_m;
1982 int32_t ret;
1983
1984 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
1985 (uint8_t *)&cfg_reg_c_m, 1);
1986
1987 switch (cfg_reg_c_m.ble)
1988 {
1989 case LSM303AGR_MG_LSB_AT_LOW_ADD:
1990 *val = LSM303AGR_MG_LSB_AT_LOW_ADD;
1991 break;
1992
1993 case LSM303AGR_MG_MSB_AT_LOW_ADD:
1994 *val = LSM303AGR_MG_MSB_AT_LOW_ADD;
1995 break;
1996
1997 default:
1998 *val = LSM303AGR_MG_LSB_AT_LOW_ADD;
1999 break;
2000 }
2001
2002 return ret;
2003 }
2004
2005 /**
2006 * @brief Info about device status.[get]
2007 *
2008 * @param ctx Read / write interface definitions.(ptr)
2009 * @param val Get registers STATUS_REG_M.(ptr)
2010 * @retval Interface status (MANDATORY: return 0 -> no Error).
2011 *
2012 */
lsm303agr_mag_status_get(const stmdev_ctx_t * ctx,lsm303agr_status_reg_m_t * val)2013 int32_t lsm303agr_mag_status_get(const stmdev_ctx_t *ctx,
2014 lsm303agr_status_reg_m_t *val)
2015 {
2016 int32_t ret;
2017
2018 ret = lsm303agr_read_reg(ctx, LSM303AGR_STATUS_REG_M, (uint8_t *) val, 1);
2019
2020 return ret;
2021 }
2022
2023 /**
2024 * @}
2025 *
2026 */
2027
2028 /**
2029 * @addtogroup interrupts_generator_1_for_xl
2030 * @brief This section group all the functions that manage the first
2031 * interrupts generator of accelerometer
2032 * @{
2033 *
2034 */
2035
2036 /**
2037 * @brief Interrupt generator 1 configuration register.[set]
2038 *
2039 * @param ctx Read / write interface definitions.(ptr)
2040 * @param val Change register INT1_CFG_A.(ptr)
2041 * @retval Interface status (MANDATORY: return 0 -> no Error).
2042 *
2043 */
lsm303agr_xl_int1_gen_conf_set(const stmdev_ctx_t * ctx,lsm303agr_int1_cfg_a_t * val)2044 int32_t lsm303agr_xl_int1_gen_conf_set(const stmdev_ctx_t *ctx,
2045 lsm303agr_int1_cfg_a_t *val)
2046 {
2047 int32_t ret;
2048
2049 ret = lsm303agr_write_reg(ctx, LSM303AGR_INT1_CFG_A, (uint8_t *) val, 1);
2050
2051 return ret;
2052 }
2053
2054 /**
2055 * @brief Interrupt generator 1 configuration register.[get]
2056 *
2057 * @param ctx Read / write interface definitions.(ptr)
2058 * @param val Get register INT1_CFG_A.(ptr)
2059 * @retval Interface status (MANDATORY: return 0 -> no Error).
2060 *
2061 */
lsm303agr_xl_int1_gen_conf_get(const stmdev_ctx_t * ctx,lsm303agr_int1_cfg_a_t * val)2062 int32_t lsm303agr_xl_int1_gen_conf_get(const stmdev_ctx_t *ctx,
2063 lsm303agr_int1_cfg_a_t *val)
2064 {
2065 int32_t ret;
2066
2067 ret = lsm303agr_read_reg(ctx, LSM303AGR_INT1_CFG_A, (uint8_t *) val, 1);
2068
2069 return ret;
2070 }
2071
2072 /**
2073 * @brief Interrupt generator 1 source register.[get]
2074 *
2075 * @param ctx Read / write interface definitions.(ptr)
2076 * @param val Get registers INT1_SRC_A.(ptr)
2077 * @retval Interface status (MANDATORY: return 0 -> no Error).
2078 *
2079 */
lsm303agr_xl_int1_gen_source_get(const stmdev_ctx_t * ctx,lsm303agr_int1_src_a_t * val)2080 int32_t lsm303agr_xl_int1_gen_source_get(const stmdev_ctx_t *ctx,
2081 lsm303agr_int1_src_a_t *val)
2082 {
2083 int32_t ret;
2084
2085 ret = lsm303agr_read_reg(ctx, LSM303AGR_INT1_SRC_A, (uint8_t *) val, 1);
2086
2087 return ret;
2088 }
2089
2090 /**
2091 * @brief User-defined threshold value for xl
2092 * interrupt event on generator 1.[set]
2093 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
2094 *
2095 * @param ctx Read / write interface definitions.(ptr)
2096 * @param val Change the values of ths in reg INT1_THS_A
2097 * @retval Interface status (MANDATORY: return 0 -> no Error).
2098 *
2099 */
lsm303agr_xl_int1_gen_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2100 int32_t lsm303agr_xl_int1_gen_threshold_set(const stmdev_ctx_t *ctx,
2101 uint8_t val)
2102 {
2103 lsm303agr_int1_ths_a_t int1_ths_a;
2104 int32_t ret;
2105
2106 ret = lsm303agr_read_reg(ctx, LSM303AGR_INT1_THS_A,
2107 (uint8_t *)&int1_ths_a, 1);
2108
2109 if (ret == 0)
2110 {
2111 int1_ths_a.ths = (uint8_t)val;
2112 ret = lsm303agr_write_reg(ctx, LSM303AGR_INT1_THS_A,
2113 (uint8_t *)&int1_ths_a, 1);
2114 }
2115
2116 return ret;
2117 }
2118
2119 /**
2120 * @brief User-defined threshold value for xl
2121 * interrupt event on generator 1.[get]
2122 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
2123 *
2124 * @param ctx Read / write interface definitions.(ptr)
2125 * @param val Get the values of ths in reg INT1_THS_A.(ptr)
2126 * @retval Interface status (MANDATORY: return 0 -> no Error).
2127 *
2128 */
lsm303agr_xl_int1_gen_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2129 int32_t lsm303agr_xl_int1_gen_threshold_get(const stmdev_ctx_t *ctx,
2130 uint8_t *val)
2131 {
2132 lsm303agr_int1_ths_a_t int1_ths_a;
2133 int32_t ret;
2134
2135 ret = lsm303agr_read_reg(ctx, LSM303AGR_INT1_THS_A,
2136 (uint8_t *)&int1_ths_a, 1);
2137 *val = int1_ths_a.ths;
2138
2139 return ret;
2140 }
2141
2142 /**
2143 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
2144 * recognized.[set]
2145 *
2146 * @param ctx Read / write interface definitions.(ptr)
2147 * @param val Change the values of d in reg INT1_DURATION_A
2148 * @retval Interface status (MANDATORY: return 0 -> no Error).
2149 *
2150 */
lsm303agr_xl_int1_gen_duration_set(const stmdev_ctx_t * ctx,uint8_t val)2151 int32_t lsm303agr_xl_int1_gen_duration_set(const stmdev_ctx_t *ctx,
2152 uint8_t val)
2153 {
2154 lsm303agr_int1_duration_a_t int1_duration_a;
2155 int32_t ret;
2156
2157 ret = lsm303agr_read_reg(ctx, LSM303AGR_INT1_DURATION_A,
2158 (uint8_t *)&int1_duration_a, 1);
2159
2160 if (ret == 0)
2161 {
2162 int1_duration_a.d = (uint8_t)val;
2163 ret = lsm303agr_write_reg(ctx, LSM303AGR_INT1_DURATION_A,
2164 (uint8_t *)&int1_duration_a, 1);
2165 }
2166
2167 return ret;
2168 }
2169
2170 /**
2171 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
2172 * recognized.[get]
2173 *
2174 * @param ctx Read / write interface definitions.(ptr)
2175 * @param val Get the values of d in reg INT1_DURATION_A.(ptr)
2176 * @retval Interface status (MANDATORY: return 0 -> no Error).
2177 *
2178 */
lsm303agr_xl_int1_gen_duration_get(const stmdev_ctx_t * ctx,uint8_t * val)2179 int32_t lsm303agr_xl_int1_gen_duration_get(const stmdev_ctx_t *ctx,
2180 uint8_t *val)
2181 {
2182 lsm303agr_int1_duration_a_t int1_duration_a;
2183 int32_t ret;
2184
2185 ret = lsm303agr_read_reg(ctx, LSM303AGR_INT1_DURATION_A,
2186 (uint8_t *)&int1_duration_a, 1);
2187 *val = int1_duration_a.d;
2188
2189 return ret;
2190 }
2191
2192 /**
2193 * @}
2194 *
2195 */
2196
2197 /**
2198 * @addtogroup interrupts_generator_2_for_xl
2199 * @brief This section group all the functions that manage the second
2200 * interrupts generator for accelerometer
2201 * @{
2202 *
2203 */
2204
2205 /**
2206 * @brief Interrupt generator 2 configuration register.[set]
2207 *
2208 * @param ctx Read / write interface definitions.(ptr)
2209 * @param val Change registers INT2_CFG_A.(ptr)
2210 * @retval Interface status (MANDATORY: return 0 -> no Error).
2211 *
2212 */
lsm303agr_xl_int2_gen_conf_set(const stmdev_ctx_t * ctx,lsm303agr_int2_cfg_a_t * val)2213 int32_t lsm303agr_xl_int2_gen_conf_set(const stmdev_ctx_t *ctx,
2214 lsm303agr_int2_cfg_a_t *val)
2215 {
2216 int32_t ret;
2217
2218 ret = lsm303agr_write_reg(ctx, LSM303AGR_INT2_CFG_A, (uint8_t *) val, 1);
2219
2220 return ret;
2221 }
2222
2223 /**
2224 * @brief Interrupt generator 2 configuration register.[get]
2225 *
2226 * @param ctx Read / write interface definitions.(ptr)
2227 * @param val Get registers INT2_CFG_A.(ptr)
2228 * @retval Interface status (MANDATORY: return 0 -> no Error).
2229 *
2230 */
lsm303agr_xl_int2_gen_conf_get(const stmdev_ctx_t * ctx,lsm303agr_int2_cfg_a_t * val)2231 int32_t lsm303agr_xl_int2_gen_conf_get(const stmdev_ctx_t *ctx,
2232 lsm303agr_int2_cfg_a_t *val)
2233 {
2234 int32_t ret;
2235
2236 ret = lsm303agr_read_reg(ctx, LSM303AGR_INT2_CFG_A, (uint8_t *) val, 1);
2237
2238 return ret;
2239 }
2240
2241 /**
2242 * @brief Interrupt generator 2 source register.[get]
2243 *
2244 * @param ctx Read / write interface definitions.(ptr)
2245 * @param val Get registers INT2_SRC_A.(ptr)
2246 * @retval Interface status (MANDATORY: return 0 -> no Error).
2247 *
2248 */
lsm303agr_xl_int2_gen_source_get(const stmdev_ctx_t * ctx,lsm303agr_int2_src_a_t * val)2249 int32_t lsm303agr_xl_int2_gen_source_get(const stmdev_ctx_t *ctx,
2250 lsm303agr_int2_src_a_t *val)
2251 {
2252 int32_t ret;
2253
2254 ret = lsm303agr_read_reg(ctx, LSM303AGR_INT2_SRC_A, (uint8_t *) val, 1);
2255
2256 return ret;
2257 }
2258
2259 /**
2260 * @brief User-defined threshold value for xl
2261 * interrupt event on generator 2.[set]
2262 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
2263 *
2264 * @param ctx Read / write interface definitions.(ptr)
2265 * @param val Change the values of ths in reg INT2_THS_A
2266 * @retval Interface status (MANDATORY: return 0 -> no Error).
2267 *
2268 */
lsm303agr_xl_int2_gen_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)2269 int32_t lsm303agr_xl_int2_gen_threshold_set(const stmdev_ctx_t *ctx,
2270 uint8_t val)
2271 {
2272 lsm303agr_int2_ths_a_t int2_ths_a;
2273 int32_t ret;
2274
2275 ret = lsm303agr_read_reg(ctx, LSM303AGR_INT2_THS_A,
2276 (uint8_t *)&int2_ths_a, 1);
2277
2278 if (ret == 0)
2279 {
2280 int2_ths_a.ths = (uint8_t)val;
2281 ret = lsm303agr_write_reg(ctx, LSM303AGR_INT2_THS_A,
2282 (uint8_t *)&int2_ths_a, 1);
2283 }
2284
2285 return ret;
2286 }
2287
2288 /**
2289 * @brief User-defined threshold value for
2290 * xl interrupt event on generator 2.[get]
2291 * LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
2292 *
2293 * @param ctx Read / write interface definitions.(ptr)
2294 * @param val Get the values of ths in reg INT2_THS_A.(ptr)
2295 * @retval Interface status (MANDATORY: return 0 -> no Error).
2296 *
2297 */
lsm303agr_xl_int2_gen_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)2298 int32_t lsm303agr_xl_int2_gen_threshold_get(const stmdev_ctx_t *ctx,
2299 uint8_t *val)
2300 {
2301 lsm303agr_int2_ths_a_t int2_ths_a;
2302 int32_t ret;
2303
2304 ret = lsm303agr_read_reg(ctx, LSM303AGR_INT2_THS_A,
2305 (uint8_t *)&int2_ths_a, 1);
2306 *val = int2_ths_a.ths;
2307
2308 return ret;
2309 }
2310
2311 /**
2312 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
2313 * recognized.[set]
2314 *
2315 * @param ctx Read / write interface definitions.(ptr)
2316 * @param val Change the values of d in reg INT2_DURATION_A
2317 * @retval Interface status (MANDATORY: return 0 -> no Error).
2318 *
2319 */
lsm303agr_xl_int2_gen_duration_set(const stmdev_ctx_t * ctx,uint8_t val)2320 int32_t lsm303agr_xl_int2_gen_duration_set(const stmdev_ctx_t *ctx,
2321 uint8_t val)
2322 {
2323 lsm303agr_int2_duration_a_t int2_duration_a;
2324 int32_t ret;
2325
2326 ret = lsm303agr_read_reg(ctx, LSM303AGR_INT2_DURATION_A,
2327 (uint8_t *)&int2_duration_a, 1);
2328
2329 if (ret == 0)
2330 {
2331 int2_duration_a.d = (uint8_t)val;
2332 ret = lsm303agr_write_reg(ctx, LSM303AGR_INT2_DURATION_A,
2333 (uint8_t *)&int2_duration_a, 1);
2334 }
2335
2336 return ret;
2337 }
2338
2339 /**
2340 * @brief The minimum duration (LSb = 1/ODR) of the Interrupt 1 event to be
2341 * recognized.[get]
2342 *
2343 * @param ctx Read / write interface definitions.(ptr)
2344 * @param val Get the values of d in reg INT2_DURATION_A.(ptr)
2345 * @retval Interface status (MANDATORY: return 0 -> no Error).
2346 *
2347 */
lsm303agr_xl_int2_gen_duration_get(const stmdev_ctx_t * ctx,uint8_t * val)2348 int32_t lsm303agr_xl_int2_gen_duration_get(const stmdev_ctx_t *ctx,
2349 uint8_t *val)
2350 {
2351 lsm303agr_int2_duration_a_t int2_duration_a;
2352 int32_t ret;
2353
2354 ret = lsm303agr_read_reg(ctx, LSM303AGR_INT2_DURATION_A,
2355 (uint8_t *)&int2_duration_a, 1);
2356 *val = int2_duration_a.d;
2357
2358 return ret;
2359 }
2360
2361 /**
2362 * @}
2363 *
2364 */
2365
2366 /**
2367 * @addtogroup interrupt_pins_xl
2368 * @brief This section group all the functions that manage interrupt
2369 * pins of accelerometer
2370 * @{
2371 *
2372 */
2373
2374 /**
2375 * @brief High-pass filter on interrupts/tap generator.[set]
2376 *
2377 * @param ctx Read / write interface definitions.(ptr)
2378 * @param val Change the values of hp in reg CTRL_REG2_A
2379 * @retval Interface status (MANDATORY: return 0 -> no Error).
2380 *
2381 */
lsm303agr_xl_high_pass_int_conf_set(const stmdev_ctx_t * ctx,lsm303agr_hp_a_t val)2382 int32_t lsm303agr_xl_high_pass_int_conf_set(const stmdev_ctx_t *ctx,
2383 lsm303agr_hp_a_t val)
2384 {
2385 lsm303agr_ctrl_reg2_a_t ctrl_reg2_a;
2386 int32_t ret;
2387
2388 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A,
2389 (uint8_t *)&ctrl_reg2_a, 1);
2390
2391 if (ret == 0)
2392 {
2393 ctrl_reg2_a.hp = (uint8_t)val;
2394 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG2_A,
2395 (uint8_t *)&ctrl_reg2_a, 1);
2396 }
2397
2398 return ret;
2399 }
2400
2401 /**
2402 * @brief High-pass filter on interrupts/tap generator.[get]
2403 *
2404 * @param ctx Read / write interface definitions.(ptr)
2405 * @param val Get the values of hp in reg CTRL_REG2_A.(ptr)
2406 * @retval Interface status (MANDATORY: return 0 -> no Error).
2407 *
2408 */
lsm303agr_xl_high_pass_int_conf_get(const stmdev_ctx_t * ctx,lsm303agr_hp_a_t * val)2409 int32_t lsm303agr_xl_high_pass_int_conf_get(const stmdev_ctx_t *ctx,
2410 lsm303agr_hp_a_t *val)
2411 {
2412 lsm303agr_ctrl_reg2_a_t ctrl_reg2_a;
2413 int32_t ret;
2414
2415 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG2_A,
2416 (uint8_t *)&ctrl_reg2_a, 1);
2417
2418 switch (ctrl_reg2_a.hp)
2419 {
2420 case LSM303AGR_DISC_FROM_INT_GENERATOR:
2421 *val = LSM303AGR_DISC_FROM_INT_GENERATOR;
2422 break;
2423
2424 case LSM303AGR_ON_INT1_GEN:
2425 *val = LSM303AGR_ON_INT1_GEN;
2426 break;
2427
2428 case LSM303AGR_ON_INT2_GEN:
2429 *val = LSM303AGR_ON_INT2_GEN;
2430 break;
2431
2432 case LSM303AGR_ON_TAP_GEN:
2433 *val = LSM303AGR_ON_TAP_GEN;
2434 break;
2435
2436 case LSM303AGR_ON_INT1_INT2_GEN:
2437 *val = LSM303AGR_ON_INT1_INT2_GEN;
2438 break;
2439
2440 case LSM303AGR_ON_INT1_TAP_GEN:
2441 *val = LSM303AGR_ON_INT1_TAP_GEN;
2442 break;
2443
2444 case LSM303AGR_ON_INT2_TAP_GEN:
2445 *val = LSM303AGR_ON_INT2_TAP_GEN;
2446 break;
2447
2448 case LSM303AGR_ON_INT1_INT2_TAP_GEN:
2449 *val = LSM303AGR_ON_INT1_INT2_TAP_GEN;
2450 break;
2451
2452 default:
2453 *val = LSM303AGR_DISC_FROM_INT_GENERATOR;
2454 break;
2455 }
2456
2457 return ret;
2458 }
2459
2460 /**
2461 * @brief Int1 pin routing configuration register.[set]
2462 *
2463 * @param ctx Read / write interface definitions.(ptr)
2464 * @param val Change registers CTRL_REG3_A.(ptr)
2465 * @retval Interface status (MANDATORY: return 0 -> no Error).
2466 *
2467 */
lsm303agr_xl_pin_int1_config_set(const stmdev_ctx_t * ctx,lsm303agr_ctrl_reg3_a_t * val)2468 int32_t lsm303agr_xl_pin_int1_config_set(const stmdev_ctx_t *ctx,
2469 lsm303agr_ctrl_reg3_a_t *val)
2470 {
2471 int32_t ret;
2472
2473 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG3_A, (uint8_t *) val, 1);
2474
2475 return ret;
2476 }
2477
2478 /**
2479 * @brief Int1 pin routing configuration register.[get]
2480 *
2481 * @param ctx Read / write interface definitions.(ptr)
2482 * @param val Get registers CTRL_REG3_A.(ptr)
2483 * @retval Interface status (MANDATORY: return 0 -> no Error).
2484 *
2485 */
lsm303agr_xl_pin_int1_config_get(const stmdev_ctx_t * ctx,lsm303agr_ctrl_reg3_a_t * val)2486 int32_t lsm303agr_xl_pin_int1_config_get(const stmdev_ctx_t *ctx,
2487 lsm303agr_ctrl_reg3_a_t *val)
2488 {
2489 int32_t ret;
2490
2491 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG3_A, (uint8_t *) val, 1);
2492
2493 return ret;
2494 }
2495
2496 /**
2497 * @brief 4D detection is enabled on INT2 pin when 6D bit on
2498 * INT2_CFG_A (34h) is set to 1.[set]
2499 *
2500 * @param ctx Read / write interface definitions.(ptr)
2501 * @param val Change the values of d4d_int2 in reg CTRL_REG5_A
2502 * @retval Interface status (MANDATORY: return 0 -> no Error).
2503 *
2504 */
lsm303agr_xl_int2_pin_detect_4d_set(const stmdev_ctx_t * ctx,uint8_t val)2505 int32_t lsm303agr_xl_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx,
2506 uint8_t val)
2507 {
2508 lsm303agr_ctrl_reg5_a_t ctrl_reg5_a;
2509 int32_t ret;
2510
2511 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
2512 (uint8_t *)&ctrl_reg5_a, 1);
2513
2514 if (ret == 0)
2515 {
2516 ctrl_reg5_a.d4d_int2 = (uint8_t)val;
2517 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG5_A,
2518 (uint8_t *)&ctrl_reg5_a, 1);
2519 }
2520
2521 return ret;
2522 }
2523
2524 /**
2525 * @brief 4D detection is enabled on INT2 pin when 6D bit on
2526 * INT2_CFG_A (34h) is set to 1.[get]
2527 *
2528 * @param ctx Read / write interface definitions.(ptr)
2529 * @param val Change the values of d4d_int2 in reg CTRL_REG5_A.(ptr)
2530 * @retval Interface status (MANDATORY: return 0 -> no Error).
2531 *
2532 */
lsm303agr_xl_int2_pin_detect_4d_get(const stmdev_ctx_t * ctx,uint8_t * val)2533 int32_t lsm303agr_xl_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx,
2534 uint8_t *val)
2535 {
2536 lsm303agr_ctrl_reg5_a_t ctrl_reg5_a;
2537 int32_t ret;
2538
2539 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
2540 (uint8_t *)&ctrl_reg5_a, 1);
2541 *val = ctrl_reg5_a.d4d_int2;
2542
2543 return ret;
2544 }
2545
2546 /**
2547 * @brief Latch interrupt request on INT2_SRC_A (35h) register, with
2548 * INT2_SRC_A (35h) register cleared by reading
2549 * INT2_SRC_A (35h) itself.[set]
2550 *
2551 * @param ctx Read / write interface definitions.(ptr)
2552 * @param val Change the values of lir_int2 in reg CTRL_REG5_A
2553 * @retval Interface status (MANDATORY: return 0 -> no Error).
2554 *
2555 */
lsm303agr_xl_int2pin_notification_mode_set(const stmdev_ctx_t * ctx,lsm303agr_lir_int2_a_t val)2556 int32_t lsm303agr_xl_int2pin_notification_mode_set(const stmdev_ctx_t *ctx,
2557 lsm303agr_lir_int2_a_t val)
2558 {
2559 lsm303agr_ctrl_reg5_a_t ctrl_reg5_a;
2560 int32_t ret;
2561
2562 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
2563 (uint8_t *)&ctrl_reg5_a, 1);
2564
2565 if (ret == 0)
2566 {
2567 ctrl_reg5_a.lir_int2 = (uint8_t)val;
2568 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG5_A,
2569 (uint8_t *)&ctrl_reg5_a, 1);
2570 }
2571
2572 return ret;
2573 }
2574
2575 /**
2576 * @brief Latch interrupt request on INT2_SRC_A (35h) register, with
2577 * INT2_SRC_A (35h) register cleared by reading
2578 * INT2_SRC_A (35h) itself.[get]
2579 *
2580 * @param ctx Read / write interface definitions.(ptr)
2581 * @param val Get the values of lir_int2 in reg CTRL_REG5_A.(ptr)
2582 * @retval Interface status (MANDATORY: return 0 -> no Error).
2583 *
2584 */
lsm303agr_xl_int2pin_notification_mode_get(const stmdev_ctx_t * ctx,lsm303agr_lir_int2_a_t * val)2585 int32_t lsm303agr_xl_int2pin_notification_mode_get(const stmdev_ctx_t *ctx,
2586 lsm303agr_lir_int2_a_t *val)
2587 {
2588 lsm303agr_ctrl_reg5_a_t ctrl_reg5_a;
2589 int32_t ret;
2590
2591 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
2592 (uint8_t *)&ctrl_reg5_a, 1);
2593
2594 switch (ctrl_reg5_a.lir_int2)
2595 {
2596 case LSM303AGR_INT2_PULSED:
2597 *val = LSM303AGR_INT2_PULSED;
2598 break;
2599
2600 case LSM303AGR_INT2_LATCHED:
2601 *val = LSM303AGR_INT2_LATCHED;
2602 break;
2603
2604 default:
2605 *val = LSM303AGR_INT2_PULSED;
2606 break;
2607 }
2608
2609 return ret;
2610 }
2611
2612 /**
2613 * @brief 4D detection is enabled on INT1 pin when 6D bit on
2614 * INT1_CFG_A (30h) is set to 1.[set]
2615 *
2616 * @param ctx Read / write interface definitions.(ptr)
2617 * @param val Change the values of d4d_int1 in reg CTRL_REG5_A
2618 * @retval Interface status (MANDATORY: return 0 -> no Error).
2619 *
2620 */
lsm303agr_xl_int1_pin_detect_4d_set(const stmdev_ctx_t * ctx,uint8_t val)2621 int32_t lsm303agr_xl_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx,
2622 uint8_t val)
2623 {
2624 lsm303agr_ctrl_reg5_a_t ctrl_reg5_a;
2625 int32_t ret;
2626
2627 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
2628 (uint8_t *)&ctrl_reg5_a, 1);
2629
2630 if (ret == 0)
2631 {
2632 ctrl_reg5_a.d4d_int1 = (uint8_t)val;
2633 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG5_A,
2634 (uint8_t *)&ctrl_reg5_a, 1);
2635 }
2636
2637 return ret;
2638 }
2639
2640 /**
2641 * @brief 4D detection is enabled on INT1 pin when 6D bit on
2642 * INT1_CFG_A (30h) is set to 1.[get]
2643 *
2644 * @param ctx Read / write interface definitions.(ptr)
2645 * @param val Get the values of d4d_int1 in reg CTRL_REG5_A.(ptr)
2646 * @retval Interface status (MANDATORY: return 0 -> no Error).
2647 *
2648 */
lsm303agr_xl_int1_pin_detect_4d_get(const stmdev_ctx_t * ctx,uint8_t * val)2649 int32_t lsm303agr_xl_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx,
2650 uint8_t *val)
2651 {
2652 lsm303agr_ctrl_reg5_a_t ctrl_reg5_a;
2653 int32_t ret;
2654
2655 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
2656 (uint8_t *)&ctrl_reg5_a, 1);
2657 *val = ctrl_reg5_a.d4d_int1;
2658
2659 return ret;
2660 }
2661
2662 /**
2663 * @brief Latch interrupt request on INT1_SRC_A (31h), with
2664 * INT1_SRC_A(31h) register cleared by reading
2665 * INT1_SRC_A (31h) itself.[set]
2666 *
2667 * @param ctx Read / write interface definitions.(ptr)
2668 * @param val Change the values of lir_int1 in reg CTRL_REG5_A
2669 * @retval Interface status (MANDATORY: return 0 -> no Error).
2670 *
2671 */
lsm303agr_xl_int1pin_notification_mode_set(const stmdev_ctx_t * ctx,lsm303agr_lir_int1_a_t val)2672 int32_t lsm303agr_xl_int1pin_notification_mode_set(const stmdev_ctx_t *ctx,
2673 lsm303agr_lir_int1_a_t val)
2674 {
2675 lsm303agr_ctrl_reg5_a_t ctrl_reg5_a;
2676 int32_t ret;
2677
2678 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
2679 (uint8_t *)&ctrl_reg5_a, 1);
2680
2681 if (ret == 0)
2682 {
2683 ctrl_reg5_a.lir_int1 = (uint8_t)val;
2684 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG5_A,
2685 (uint8_t *)&ctrl_reg5_a, 1);
2686 }
2687
2688 return ret;
2689 }
2690
2691 /**
2692 * @brief Latch interrupt request on INT1_SRC_A (31h), with
2693 * INT1_SRC_A(31h) register cleared by reading
2694 * INT1_SRC_A (31h) itself.[get]
2695 *
2696 * @param ctx Read / write interface definitions.(ptr)
2697 * @param val Get the values of lir_int1 in reg CTRL_REG5_A.(ptr)
2698 * @retval Interface status (MANDATORY: return 0 -> no Error).
2699 *
2700 */
lsm303agr_xl_int1pin_notification_mode_get(const stmdev_ctx_t * ctx,lsm303agr_lir_int1_a_t * val)2701 int32_t lsm303agr_xl_int1pin_notification_mode_get(const stmdev_ctx_t *ctx,
2702 lsm303agr_lir_int1_a_t *val)
2703 {
2704 lsm303agr_ctrl_reg5_a_t ctrl_reg5_a;
2705 int32_t ret;
2706
2707 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
2708 (uint8_t *)&ctrl_reg5_a, 1);
2709
2710 switch (ctrl_reg5_a.lir_int1)
2711 {
2712 case LSM303AGR_INT1_PULSED:
2713 *val = LSM303AGR_INT1_PULSED;
2714 break;
2715
2716 case LSM303AGR_INT1_LATCHED:
2717 *val = LSM303AGR_INT1_LATCHED;
2718 break;
2719
2720 default:
2721 *val = LSM303AGR_INT1_PULSED;
2722 break;
2723 }
2724
2725 return ret;
2726 }
2727
2728 /**
2729 * @brief Int2 pin routing configuration register.[set]
2730 *
2731 * @param ctx Read / write interface definitions.(ptr)
2732 * @param val Change registers CTRL_REG6_A.(ptr)
2733 * @retval Interface status (MANDATORY: return 0 -> no Error).
2734 *
2735 */
lsm303agr_xl_pin_int2_config_set(const stmdev_ctx_t * ctx,lsm303agr_ctrl_reg6_a_t * val)2736 int32_t lsm303agr_xl_pin_int2_config_set(const stmdev_ctx_t *ctx,
2737 lsm303agr_ctrl_reg6_a_t *val)
2738 {
2739 int32_t ret;
2740
2741 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG6_A, (uint8_t *) val, 1);
2742
2743 return ret;
2744 }
2745
2746 /**
2747 * @brief Int2 pin routing configuration register.[get]
2748 *
2749 * @param ctx Read / write interface definitions.(ptr)
2750 * @param val Get registers CTRL_REG6_A.(ptr)
2751 * @retval Interface status (MANDATORY: return 0 -> no Error).
2752 *
2753 */
lsm303agr_xl_pin_int2_config_get(const stmdev_ctx_t * ctx,lsm303agr_ctrl_reg6_a_t * val)2754 int32_t lsm303agr_xl_pin_int2_config_get(const stmdev_ctx_t *ctx,
2755 lsm303agr_ctrl_reg6_a_t *val)
2756 {
2757 int32_t ret;
2758
2759 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG6_A, (uint8_t *) val, 1);
2760
2761 return ret;
2762 }
2763
2764 /**
2765 * @}
2766 *
2767 */
2768
2769 /**
2770 * @addtogroup magnetometer interrupts
2771 * @brief This section group all the functions that manage the
2772 * magnetometer interrupts
2773 * @{
2774 *
2775 */
2776
2777 /**
2778 * @brief The interrupt block recognition checks
2779 * data after/before the hard-iron correction
2780 * to discover the interrupt.[set]
2781 *
2782 * @param ctx Read / write interface definitions.(ptr)
2783 * @param val Change the values of int_on_dataoff in reg CFG_REG_B_M
2784 * @retval Interface status (MANDATORY: return 0 -> no Error).
2785 *
2786 */
lsm303agr_mag_offset_int_conf_set(const stmdev_ctx_t * ctx,lsm303agr_int_on_dataoff_m_t val)2787 int32_t lsm303agr_mag_offset_int_conf_set(const stmdev_ctx_t *ctx,
2788 lsm303agr_int_on_dataoff_m_t val)
2789 {
2790 lsm303agr_cfg_reg_b_m_t cfg_reg_b_m;
2791 int32_t ret;
2792
2793 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M,
2794 (uint8_t *)&cfg_reg_b_m, 1);
2795
2796 if (ret == 0)
2797 {
2798 cfg_reg_b_m.int_on_dataoff = (uint8_t)val;
2799 ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_B_M,
2800 (uint8_t *)&cfg_reg_b_m, 1);
2801 }
2802
2803 return ret;
2804 }
2805
2806 /**
2807 * @brief The interrupt block recognition checks
2808 * data after/before the hard-iron correction
2809 * to discover the interrupt.[get]
2810 *
2811 * @param ctx Read / write interface definitions.(ptr)
2812 * @param val Get the values of int_on_dataoff in reg CFG_REG_B_M.(ptr)
2813 * @retval Interface status (MANDATORY: return 0 -> no Error).
2814 *
2815 */
lsm303agr_mag_offset_int_conf_get(const stmdev_ctx_t * ctx,lsm303agr_int_on_dataoff_m_t * val)2816 int32_t lsm303agr_mag_offset_int_conf_get(const stmdev_ctx_t *ctx,
2817 lsm303agr_int_on_dataoff_m_t *val)
2818 {
2819 lsm303agr_cfg_reg_b_m_t cfg_reg_b_m;
2820 int32_t ret;
2821
2822 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_B_M,
2823 (uint8_t *)&cfg_reg_b_m, 1);
2824
2825 switch (cfg_reg_b_m.int_on_dataoff)
2826 {
2827 case LSM303AGR_CHECK_BEFORE:
2828 *val = LSM303AGR_CHECK_BEFORE;
2829 break;
2830
2831 case LSM303AGR_CHECK_AFTER:
2832 *val = LSM303AGR_CHECK_AFTER;
2833 break;
2834
2835 default:
2836 *val = LSM303AGR_CHECK_BEFORE;
2837 break;
2838 }
2839
2840 return ret;
2841 }
2842
2843 /**
2844 * @brief Data-ready signal on INT_DRDY pin.[set]
2845 *
2846 * @param ctx Read / write interface definitions.(ptr)
2847 * @param val Change the values of drdy_on_pin in reg CFG_REG_C_M
2848 * @retval Interface status (MANDATORY: return 0 -> no Error).
2849 *
2850 */
lsm303agr_mag_drdy_on_pin_set(const stmdev_ctx_t * ctx,uint8_t val)2851 int32_t lsm303agr_mag_drdy_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val)
2852 {
2853 lsm303agr_cfg_reg_c_m_t cfg_reg_c_m;
2854 int32_t ret;
2855
2856 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
2857 (uint8_t *)&cfg_reg_c_m, 1);
2858
2859 if (ret == 0)
2860 {
2861 cfg_reg_c_m.int_mag = (uint8_t)val;
2862 ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_C_M,
2863 (uint8_t *)&cfg_reg_c_m, 1);
2864 }
2865
2866 return ret;
2867 }
2868
2869 /**
2870 * @brief Data-ready signal on INT_DRDY pin.[get]
2871 *
2872 * @param ctx Read / write interface definitions.(ptr)
2873 * @param val Get the values of drdy_on_pin in reg CFG_REG_C_M.(ptr)
2874 * @retval Interface status (MANDATORY: return 0 -> no Error).
2875 *
2876 */
lsm303agr_mag_drdy_on_pin_get(const stmdev_ctx_t * ctx,uint8_t * val)2877 int32_t lsm303agr_mag_drdy_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val)
2878 {
2879 lsm303agr_cfg_reg_c_m_t cfg_reg_c_m;
2880 int32_t ret;
2881
2882 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
2883 (uint8_t *)&cfg_reg_c_m, 1);
2884 *val = cfg_reg_c_m.int_mag;
2885
2886 return ret;
2887 }
2888
2889 /**
2890 * @brief Interrupt signal on INT_DRDY pin.[set]
2891 *
2892 * @param ctx Read / write interface definitions.(ptr)
2893 * @param val Change the values of int_on_pin in reg CFG_REG_C_M
2894 * @retval Interface status (MANDATORY: return 0 -> no Error).
2895 *
2896 */
lsm303agr_mag_int_on_pin_set(const stmdev_ctx_t * ctx,uint8_t val)2897 int32_t lsm303agr_mag_int_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val)
2898 {
2899 lsm303agr_cfg_reg_c_m_t cfg_reg_c_m;
2900 int32_t ret;
2901
2902 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
2903 (uint8_t *)&cfg_reg_c_m, 1);
2904
2905 if (ret == 0)
2906 {
2907 cfg_reg_c_m.int_mag_pin = (uint8_t)val;
2908 ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_C_M,
2909 (uint8_t *)&cfg_reg_c_m, 1);
2910 }
2911
2912 return ret;
2913 }
2914
2915 /**
2916 * @brief Interrupt signal on INT_DRDY pin.[get]
2917 *
2918 * @param ctx Read / write interface definitions.(ptr)
2919 * @param val Get the values of int_on_pin in reg CFG_REG_C_M.(ptr)
2920 * @retval Interface status (MANDATORY: return 0 -> no Error).
2921 *
2922 */
lsm303agr_mag_int_on_pin_get(const stmdev_ctx_t * ctx,uint8_t * val)2923 int32_t lsm303agr_mag_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val)
2924 {
2925 lsm303agr_cfg_reg_c_m_t cfg_reg_c_m;
2926 int32_t ret;
2927
2928 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
2929 (uint8_t *)&cfg_reg_c_m, 1);
2930 *val = cfg_reg_c_m.int_mag_pin;
2931
2932 return ret;
2933 }
2934
2935 /**
2936 * @brief Interrupt generator configuration register.[set]
2937 *
2938 * @param ctx Read / write interface definitions.(ptr)
2939 * @param val Change registers INT_CRTL_REG_M.(ptr)
2940 * @retval Interface status (MANDATORY: return 0 -> no Error).
2941 *
2942 */
lsm303agr_mag_int_gen_conf_set(const stmdev_ctx_t * ctx,lsm303agr_int_crtl_reg_m_t * val)2943 int32_t lsm303agr_mag_int_gen_conf_set(const stmdev_ctx_t *ctx,
2944 lsm303agr_int_crtl_reg_m_t *val)
2945 {
2946 int32_t ret;
2947
2948 ret = lsm303agr_write_reg(ctx, LSM303AGR_INT_CRTL_REG_M,
2949 (uint8_t *) val, 1);
2950
2951 return ret;
2952 }
2953
2954 /**
2955 * @brief Interrupt generator configuration register.[get]
2956 *
2957 * @param ctx Read / write interface definitions.(ptr)
2958 * @param val Get registers INT_CRTL_REG_M.(ptr)
2959 * @retval Interface status (MANDATORY: return 0 -> no Error).
2960 *
2961 */
lsm303agr_mag_int_gen_conf_get(const stmdev_ctx_t * ctx,lsm303agr_int_crtl_reg_m_t * val)2962 int32_t lsm303agr_mag_int_gen_conf_get(const stmdev_ctx_t *ctx,
2963 lsm303agr_int_crtl_reg_m_t *val)
2964 {
2965 int32_t ret;
2966
2967 ret = lsm303agr_read_reg(ctx, LSM303AGR_INT_CRTL_REG_M,
2968 (uint8_t *) val, 1);
2969
2970 return ret;
2971 }
2972
2973 /**
2974 * @brief Interrupt generator source register.[get]
2975 *
2976 * @param ctx Read / write interface definitions.(ptr)
2977 * @param val Get registers INT_SOURCE_REG_M.(ptr)
2978 * @retval Interface status (MANDATORY: return 0 -> no Error).
2979 *
2980 */
lsm303agr_mag_int_gen_source_get(const stmdev_ctx_t * ctx,lsm303agr_int_source_reg_m_t * val)2981 int32_t lsm303agr_mag_int_gen_source_get(const stmdev_ctx_t *ctx,
2982 lsm303agr_int_source_reg_m_t *val)
2983 {
2984 int32_t ret;
2985
2986 ret = lsm303agr_read_reg(ctx, LSM303AGR_INT_SOURCE_REG_M,
2987 (uint8_t *) val, 1);
2988
2989 return ret;
2990 }
2991
2992 /**
2993 * @brief User-defined threshold value for xl interrupt event on generator.
2994 * Data format is the same of output
2995 * data raw: two’s complement with
2996 * 1LSb = 1.5mG.[set]
2997 *
2998 * @param ctx Read / write interface definitions.(ptr)
2999 * @param buff Buffer that contains data to write.(ptr)
3000 * @retval Interface status (MANDATORY: return 0 -> no Error).
3001 *
3002 */
lsm303agr_mag_int_gen_threshold_set(const stmdev_ctx_t * ctx,int16_t val)3003 int32_t lsm303agr_mag_int_gen_threshold_set(const stmdev_ctx_t *ctx,
3004 int16_t val)
3005 {
3006 uint8_t buff[6];
3007 int32_t ret;
3008
3009 buff[1] = (uint8_t)((uint16_t)val / 256U);
3010 buff[0] = (uint8_t)((uint16_t)val - (buff[1] * 256U));
3011 ret = lsm303agr_write_reg(ctx, LSM303AGR_INT_THS_L_REG_M, buff, 2);
3012
3013 return ret;
3014 }
3015
3016 /**
3017 * @brief User-defined threshold value for xl interrupt event on generator.
3018 * Data format is the same of output
3019 * data raw: two’s complement with
3020 * 1LSb = 1.5mG.[get]
3021 *
3022 * @param ctx Read / write interface definitions.(ptr)
3023 * @param buff Buffer that stores data read.(ptr)
3024 * @retval Interface status (MANDATORY: return 0 -> no Error).
3025 *
3026 */
lsm303agr_mag_int_gen_threshold_get(const stmdev_ctx_t * ctx,int16_t * val)3027 int32_t lsm303agr_mag_int_gen_threshold_get(const stmdev_ctx_t *ctx,
3028 int16_t *val)
3029 {
3030 uint8_t buff[2];
3031 int32_t ret;
3032
3033 ret = lsm303agr_read_reg(ctx, LSM303AGR_INT_THS_L_REG_M, buff, 2);
3034 val[0] = (int16_t)buff[1];
3035 val[0] = (val[0] * 256) + (int16_t)buff[0];
3036
3037 return ret;
3038 }
3039
3040 /**
3041 * @}
3042 *
3043 */
3044
3045 /**
3046 * @addtogroup accelerometer_fifo
3047 * @brief This section group all the functions concerning the xl
3048 * fifo usage
3049 * @{
3050 *
3051 */
3052
3053 /**
3054 * @brief FIFOenable.[set]
3055 *
3056 * @param ctx Read / write interface definitions.(ptr)
3057 * @param val Change the values of fifo_en in reg CTRL_REG5_A
3058 * @retval Interface status (MANDATORY: return 0 -> no Error).
3059 *
3060 */
lsm303agr_xl_fifo_set(const stmdev_ctx_t * ctx,uint8_t val)3061 int32_t lsm303agr_xl_fifo_set(const stmdev_ctx_t *ctx, uint8_t val)
3062 {
3063 lsm303agr_ctrl_reg5_a_t ctrl_reg5_a;
3064 int32_t ret;
3065
3066 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
3067 (uint8_t *)&ctrl_reg5_a, 1);
3068
3069 if (ret == 0)
3070 {
3071 ctrl_reg5_a.fifo_en = (uint8_t)val;
3072 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG5_A,
3073 (uint8_t *)&ctrl_reg5_a, 1);
3074 }
3075
3076 return ret;
3077 }
3078
3079 /**
3080 * @brief FIFOenable.[get]
3081 *
3082 * @param ctx Read / write interface definitions.(ptr)
3083 * @param val Get the values of fifo_en in reg CTRL_REG5_A.(ptr)
3084 * @retval Interface status (MANDATORY: return 0 -> no Error).
3085 *
3086 */
lsm303agr_xl_fifo_get(const stmdev_ctx_t * ctx,uint8_t * val)3087 int32_t lsm303agr_xl_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val)
3088 {
3089 lsm303agr_ctrl_reg5_a_t ctrl_reg5_a;
3090 int32_t ret;
3091
3092 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG5_A,
3093 (uint8_t *)&ctrl_reg5_a, 1);
3094 *val = ctrl_reg5_a.fifo_en;
3095
3096 return ret;
3097 }
3098
3099 /**
3100 * @brief FIFO watermark level selection.[set]
3101 *
3102 * @param ctx Read / write interface definitions.(ptr)
3103 * @param val Change the values of fth in reg FIFO_CTRL_REG_A
3104 * @retval Interface status (MANDATORY: return 0 -> no Error).
3105 *
3106 */
lsm303agr_xl_fifo_watermark_set(const stmdev_ctx_t * ctx,uint8_t val)3107 int32_t lsm303agr_xl_fifo_watermark_set(const stmdev_ctx_t *ctx,
3108 uint8_t val)
3109 {
3110 lsm303agr_fifo_ctrl_reg_a_t fifo_ctrl_reg_a;
3111 int32_t ret;
3112
3113 ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A,
3114 (uint8_t *)&fifo_ctrl_reg_a, 1);
3115
3116 if (ret == 0)
3117 {
3118 fifo_ctrl_reg_a.fth = (uint8_t)val;
3119 ret = lsm303agr_write_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A,
3120 (uint8_t *)&fifo_ctrl_reg_a, 1);
3121 }
3122
3123 return ret;
3124 }
3125
3126 /**
3127 * @brief FIFO watermark level selection.[get]
3128 *
3129 * @param ctx Read / write interface definitions.(ptr)
3130 * @param val Get the values of fth in reg FIFO_CTRL_REG_A.(ptr)
3131 * @retval Interface status (MANDATORY: return 0 -> no Error).
3132 *
3133 */
lsm303agr_xl_fifo_watermark_get(const stmdev_ctx_t * ctx,uint8_t * val)3134 int32_t lsm303agr_xl_fifo_watermark_get(const stmdev_ctx_t *ctx,
3135 uint8_t *val)
3136 {
3137 lsm303agr_fifo_ctrl_reg_a_t fifo_ctrl_reg_a;
3138 int32_t ret;
3139
3140 ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A,
3141 (uint8_t *)&fifo_ctrl_reg_a, 1);
3142 *val = fifo_ctrl_reg_a.fth;
3143
3144 return ret;
3145 }
3146
3147 /**
3148 * @brief Trigger FIFO selection.[set]
3149 *
3150 * @param ctx Read / write interface definitions.(ptr)
3151 * @param val Change the values of tr in reg FIFO_CTRL_REG_A
3152 * @retval Interface status (MANDATORY: return 0 -> no Error).
3153 *
3154 */
lsm303agr_xl_fifo_trigger_event_set(const stmdev_ctx_t * ctx,lsm303agr_tr_a_t val)3155 int32_t lsm303agr_xl_fifo_trigger_event_set(const stmdev_ctx_t *ctx,
3156 lsm303agr_tr_a_t val)
3157 {
3158 lsm303agr_fifo_ctrl_reg_a_t fifo_ctrl_reg_a;
3159 int32_t ret;
3160
3161 ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A,
3162 (uint8_t *)&fifo_ctrl_reg_a, 1);
3163
3164 if (ret == 0)
3165 {
3166 fifo_ctrl_reg_a.tr = (uint8_t)val;
3167 ret = lsm303agr_write_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A,
3168 (uint8_t *)&fifo_ctrl_reg_a, 1);
3169 }
3170
3171 return ret;
3172 }
3173
3174 /**
3175 * @brief Trigger FIFO selection.[get]
3176 *
3177 * @param ctx Read / write interface definitions.(ptr)
3178 * @param val Get the values of tr in reg FIFO_CTRL_REG_A.(ptr)
3179 * @retval Interface status (MANDATORY: return 0 -> no Error).
3180 *
3181 */
lsm303agr_xl_fifo_trigger_event_get(const stmdev_ctx_t * ctx,lsm303agr_tr_a_t * val)3182 int32_t lsm303agr_xl_fifo_trigger_event_get(const stmdev_ctx_t *ctx,
3183 lsm303agr_tr_a_t *val)
3184 {
3185 lsm303agr_fifo_ctrl_reg_a_t fifo_ctrl_reg_a;
3186 int32_t ret;
3187
3188 ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A,
3189 (uint8_t *)&fifo_ctrl_reg_a, 1);
3190
3191 switch (fifo_ctrl_reg_a.tr)
3192 {
3193 case LSM303AGR_INT1_GEN:
3194 *val = LSM303AGR_INT1_GEN;
3195 break;
3196
3197 case LSM303AGR_INT2_GEN:
3198 *val = LSM303AGR_INT2_GEN;
3199 break;
3200
3201 default:
3202 *val = LSM303AGR_INT1_GEN;
3203 break;
3204 }
3205
3206 return ret;
3207 }
3208
3209 /**
3210 * @brief FIFO mode selection.[set]
3211 *
3212 * @param ctx Read / write interface definitions.(ptr)
3213 * @param val Change the values of fm in reg FIFO_CTRL_REG_A
3214 * @retval Interface status (MANDATORY: return 0 -> no Error).
3215 *
3216 */
lsm303agr_xl_fifo_mode_set(const stmdev_ctx_t * ctx,lsm303agr_fm_a_t val)3217 int32_t lsm303agr_xl_fifo_mode_set(const stmdev_ctx_t *ctx,
3218 lsm303agr_fm_a_t val)
3219 {
3220 lsm303agr_fifo_ctrl_reg_a_t fifo_ctrl_reg_a;
3221 int32_t ret;
3222
3223 ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A,
3224 (uint8_t *)&fifo_ctrl_reg_a, 1);
3225
3226 if (ret == 0)
3227 {
3228 fifo_ctrl_reg_a.fm = (uint8_t)val;
3229 ret = lsm303agr_write_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A,
3230 (uint8_t *)&fifo_ctrl_reg_a, 1);
3231 }
3232
3233 return ret;
3234 }
3235
3236 /**
3237 * @brief FIFO mode selection.[get]
3238 *
3239 * @param ctx Read / write interface definitions.(ptr)
3240 * @param val Get the values of fm in reg FIFO_CTRL_REG_A.(ptr)
3241 * @retval Interface status (MANDATORY: return 0 -> no Error).
3242 *
3243 */
lsm303agr_xl_fifo_mode_get(const stmdev_ctx_t * ctx,lsm303agr_fm_a_t * val)3244 int32_t lsm303agr_xl_fifo_mode_get(const stmdev_ctx_t *ctx,
3245 lsm303agr_fm_a_t *val)
3246 {
3247 lsm303agr_fifo_ctrl_reg_a_t fifo_ctrl_reg_a;
3248 int32_t ret;
3249
3250 ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_CTRL_REG_A,
3251 (uint8_t *)&fifo_ctrl_reg_a, 1);
3252
3253 switch (fifo_ctrl_reg_a.fm)
3254 {
3255 case LSM303AGR_BYPASS_MODE:
3256 *val = LSM303AGR_BYPASS_MODE;
3257 break;
3258
3259 case LSM303AGR_FIFO_MODE:
3260 *val = LSM303AGR_FIFO_MODE;
3261 break;
3262
3263 case LSM303AGR_DYNAMIC_STREAM_MODE:
3264 *val = LSM303AGR_DYNAMIC_STREAM_MODE;
3265 break;
3266
3267 case LSM303AGR_STREAM_TO_FIFO_MODE:
3268 *val = LSM303AGR_STREAM_TO_FIFO_MODE;
3269 break;
3270
3271 default:
3272 *val = LSM303AGR_BYPASS_MODE;
3273 break;
3274 }
3275
3276 return ret;
3277 }
3278
3279 /**
3280 * @brief FIFO status register.[get]
3281 *
3282 * @param ctx Read / write interface definitions.(ptr)
3283 * @param val Get registers FIFO_SRC_REG_A.(ptr)
3284 * @retval Interface status (MANDATORY: return 0 -> no Error).
3285 *
3286 */
lsm303agr_xl_fifo_status_get(const stmdev_ctx_t * ctx,lsm303agr_fifo_src_reg_a_t * val)3287 int32_t lsm303agr_xl_fifo_status_get(const stmdev_ctx_t *ctx,
3288 lsm303agr_fifo_src_reg_a_t *val)
3289 {
3290 int32_t ret;
3291
3292 ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_SRC_REG_A,
3293 (uint8_t *) val, 1);
3294
3295 return ret;
3296 }
3297
3298 /**
3299 * @brief FIFO stored data level.[get]
3300 *
3301 * @param ctx Read / write interface definitions.(ptr)
3302 * @param val Get the values of fss in reg FIFO_SRC_REG_A.(ptr)
3303 * @retval Interface status (MANDATORY: return 0 -> no Error).
3304 *
3305 */
lsm303agr_xl_fifo_data_level_get(const stmdev_ctx_t * ctx,uint8_t * val)3306 int32_t lsm303agr_xl_fifo_data_level_get(const stmdev_ctx_t *ctx,
3307 uint8_t *val)
3308 {
3309 lsm303agr_fifo_src_reg_a_t fifo_src_reg_a;
3310 int32_t ret;
3311
3312 ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_SRC_REG_A,
3313 (uint8_t *)&fifo_src_reg_a, 1);
3314 *val = fifo_src_reg_a.fss;
3315
3316 return ret;
3317 }
3318
3319 /**
3320 * @brief Empty FIFO status flag.[get]
3321 *
3322 * @param ctx Read / write interface definitions.(ptr)
3323 * @param val Get the values of empty in reg FIFO_SRC_REG_A.(ptr)
3324 * @retval Interface status (MANDATORY: return 0 -> no Error).
3325 *
3326 */
lsm303agr_xl_fifo_empty_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)3327 int32_t lsm303agr_xl_fifo_empty_flag_get(const stmdev_ctx_t *ctx,
3328 uint8_t *val)
3329 {
3330 lsm303agr_fifo_src_reg_a_t fifo_src_reg_a;
3331 int32_t ret;
3332
3333 ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_SRC_REG_A,
3334 (uint8_t *)&fifo_src_reg_a, 1);
3335 *val = fifo_src_reg_a.empty;
3336
3337 return ret;
3338 }
3339
3340 /**
3341 * @brief FIFO overrun status flag.[get]
3342 *
3343 * @param ctx Read / write interface definitions.(ptr)
3344 * @param val Get the values of ovrn_fifo in reg FIFO_SRC_REG_A.(ptr)
3345 * @retval Interface status (MANDATORY: return 0 -> no Error).
3346 *
3347 */
lsm303agr_xl_fifo_ovr_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)3348 int32_t lsm303agr_xl_fifo_ovr_flag_get(const stmdev_ctx_t *ctx,
3349 uint8_t *val)
3350 {
3351 lsm303agr_fifo_src_reg_a_t fifo_src_reg_a;
3352 int32_t ret;
3353
3354 ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_SRC_REG_A,
3355 (uint8_t *)&fifo_src_reg_a, 1);
3356 *val = fifo_src_reg_a.ovrn_fifo;
3357
3358 return ret;
3359 }
3360
3361 /**
3362 * @brief FIFO watermark status.[get]
3363 *
3364 * @param ctx Read / write interface definitions.(ptr)
3365 * @param val Get the values of wtm in reg FIFO_SRC_REG_A.(ptr)
3366 * @retval Interface status (MANDATORY: return 0 -> no Error).
3367 *
3368 */
lsm303agr_xl_fifo_fth_flag_get(const stmdev_ctx_t * ctx,uint8_t * val)3369 int32_t lsm303agr_xl_fifo_fth_flag_get(const stmdev_ctx_t *ctx,
3370 uint8_t *val)
3371 {
3372 lsm303agr_fifo_src_reg_a_t fifo_src_reg_a;
3373 int32_t ret;
3374
3375 ret = lsm303agr_read_reg(ctx, LSM303AGR_FIFO_SRC_REG_A,
3376 (uint8_t *)&fifo_src_reg_a, 1);
3377 *val = fifo_src_reg_a.wtm;
3378
3379 return ret;
3380 }
3381
3382 /**
3383 * @}
3384 *
3385 */
3386
3387 /**
3388 * @addtogroup tap_generator
3389 * @brief This section group all the functions that manage the tap and
3390 * double tap event generation
3391 * @{
3392 *
3393 */
3394
3395 /**
3396 * @brief Tap/Double Tap generator configuration register.[set]
3397 *
3398 * @param ctx Read / write interface definitions.(ptr)
3399 * @param val Change registers CLICK_CFG_A.(ptr)
3400 * @retval Interface status (MANDATORY: return 0 -> no Error).
3401 *
3402 */
lsm303agr_tap_conf_set(const stmdev_ctx_t * ctx,lsm303agr_click_cfg_a_t * val)3403 int32_t lsm303agr_tap_conf_set(const stmdev_ctx_t *ctx,
3404 lsm303agr_click_cfg_a_t *val)
3405 {
3406 int32_t ret;
3407
3408 ret = lsm303agr_write_reg(ctx, LSM303AGR_CLICK_CFG_A, (uint8_t *) val, 1);
3409
3410 return ret;
3411 }
3412
3413 /**
3414 * @brief Tap/Double Tap generator configuration register.[get]
3415 *
3416 * @param ctx Read / write interface definitions.(ptr)
3417 * @param val Get registers CLICK_CFG_A.(ptr)
3418 * @retval Interface status (MANDATORY: return 0 -> no Error).
3419 *
3420 */
lsm303agr_tap_conf_get(const stmdev_ctx_t * ctx,lsm303agr_click_cfg_a_t * val)3421 int32_t lsm303agr_tap_conf_get(const stmdev_ctx_t *ctx,
3422 lsm303agr_click_cfg_a_t *val)
3423 {
3424 int32_t ret;
3425
3426 ret = lsm303agr_read_reg(ctx, LSM303AGR_CLICK_CFG_A, (uint8_t *) val, 1);
3427
3428 return ret;
3429 }
3430
3431 /**
3432 * @brief Tap/Double Tap generator source register.[get]
3433 *
3434 * @param ctx Read / write interface definitions.(ptr)
3435 * @param val Get registers CLICK_SRC_A.(ptr)
3436 * @retval Interface status (MANDATORY: return 0 -> no Error).
3437 *
3438 */
lsm303agr_tap_source_get(const stmdev_ctx_t * ctx,lsm303agr_click_src_a_t * val)3439 int32_t lsm303agr_tap_source_get(const stmdev_ctx_t *ctx,
3440 lsm303agr_click_src_a_t *val)
3441 {
3442 int32_t ret;
3443
3444 ret = lsm303agr_read_reg(ctx, LSM303AGR_CLICK_SRC_A, (uint8_t *) val, 1);
3445
3446 return ret;
3447 }
3448
3449 /**
3450 * @brief User-defined threshold value for Tap/Double Tap event.
3451 * (1 LSB = full scale/128)[set]
3452 *
3453 * @param ctx Read / write interface definitions.(ptr)
3454 * @param val Change the values of ths in reg CLICK_THS_A
3455 * @retval Interface status (MANDATORY: return 0 -> no Error).
3456 *
3457 */
lsm303agr_tap_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)3458 int32_t lsm303agr_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
3459 {
3460 lsm303agr_click_ths_a_t click_ths_a;
3461 int32_t ret;
3462
3463 ret = lsm303agr_read_reg(ctx, LSM303AGR_CLICK_THS_A,
3464 (uint8_t *)&click_ths_a, 1);
3465
3466 if (ret == 0)
3467 {
3468 click_ths_a.ths = (uint8_t)val;
3469 ret = lsm303agr_write_reg(ctx, LSM303AGR_CLICK_THS_A,
3470 (uint8_t *)&click_ths_a, 1);
3471 }
3472
3473 return ret;
3474 }
3475
3476 /**
3477 * @brief User-defined threshold value for Tap/Double Tap event.
3478 * (1 LSB = full scale/128)[get]
3479 *
3480 * @param ctx Read / write interface definitions.(ptr)
3481 * @param val Get the values of ths in reg CLICK_THS_A.(ptr)
3482 * @retval Interface status (MANDATORY: return 0 -> no Error).
3483 *
3484 */
lsm303agr_tap_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)3485 int32_t lsm303agr_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
3486 {
3487 lsm303agr_click_ths_a_t click_ths_a;
3488 int32_t ret;
3489
3490 ret = lsm303agr_read_reg(ctx, LSM303AGR_CLICK_THS_A,
3491 (uint8_t *)&click_ths_a, 1);
3492 *val = click_ths_a.ths;
3493
3494 return ret;
3495 }
3496
3497 /**
3498 * @brief The maximum time (1 LSB = 1/ODR) interval that can
3499 * elapse between the start of the click-detection procedure
3500 * and when the acceleration falls back below the threshold.[set]
3501 *
3502 * @param ctx Read / write interface definitions.(ptr)
3503 * @param val Change the values of tli in reg TIME_LIMIT_A
3504 * @retval Interface status (MANDATORY: return 0 -> no Error).
3505 *
3506 */
lsm303agr_shock_dur_set(const stmdev_ctx_t * ctx,uint8_t val)3507 int32_t lsm303agr_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
3508 {
3509 lsm303agr_time_limit_a_t time_limit_a;
3510 int32_t ret;
3511
3512 ret = lsm303agr_read_reg(ctx, LSM303AGR_TIME_LIMIT_A,
3513 (uint8_t *)&time_limit_a, 1);
3514
3515 if (ret == 0)
3516 {
3517 time_limit_a.tli = (uint8_t)val;
3518 ret = lsm303agr_write_reg(ctx, LSM303AGR_TIME_LIMIT_A,
3519 (uint8_t *)&time_limit_a, 1);
3520 }
3521
3522 return ret;
3523 }
3524
3525 /**
3526 * @brief The maximum time (1 LSB = 1/ODR) interval that can
3527 * elapse between the start of the click-detection procedure
3528 * and when the acceleration falls back below the threshold.[get]
3529 *
3530 * @param ctx Read / write interface definitions.(ptr)
3531 * @param val Get the values of tli in reg TIME_LIMIT_A.(ptr)
3532 * @retval Interface status (MANDATORY: return 0 -> no Error).
3533 *
3534 */
lsm303agr_shock_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)3535 int32_t lsm303agr_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
3536 {
3537 lsm303agr_time_limit_a_t time_limit_a;
3538 int32_t ret;
3539
3540 ret = lsm303agr_read_reg(ctx, LSM303AGR_TIME_LIMIT_A,
3541 (uint8_t *)&time_limit_a, 1);
3542 *val = time_limit_a.tli;
3543
3544 return ret;
3545 }
3546
3547 /**
3548 * @brief The time (1 LSB = 1/ODR) interval that starts after the
3549 * first click detection where the click-detection procedure
3550 * is disabled, in cases where the device is configured for
3551 * double-click detection.[set]
3552 *
3553 * @param ctx Read / write interface definitions.(ptr)
3554 * @param val Change the values of tla in reg TIME_LATENCY_A
3555 * @retval Interface status (MANDATORY: return 0 -> no Error).
3556 *
3557 */
lsm303agr_quiet_dur_set(const stmdev_ctx_t * ctx,uint8_t val)3558 int32_t lsm303agr_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val)
3559 {
3560 lsm303agr_time_latency_a_t time_latency_a;
3561 int32_t ret;
3562
3563 ret = lsm303agr_read_reg(ctx, LSM303AGR_TIME_LATENCY_A,
3564 (uint8_t *)&time_latency_a, 1);
3565
3566 if (ret == 0)
3567 {
3568 time_latency_a.tla = (uint8_t)val;
3569 ret = lsm303agr_write_reg(ctx, LSM303AGR_TIME_LATENCY_A,
3570 (uint8_t *)&time_latency_a, 1);
3571 }
3572
3573 return ret;
3574 }
3575
3576 /**
3577 * @brief The time (1 LSB = 1/ODR) interval that starts after the first click
3578 * detection where the click-detection procedure is disabled, in cases
3579 * where the device is configured for double-click detection.[get]
3580 *
3581 * @param ctx Read / write interface definitions.(ptr)
3582 * @param val Get the values of tla in reg TIME_LATENCY_A.(ptr)
3583 * @retval Interface status (MANDATORY: return 0 -> no Error).
3584 *
3585 */
lsm303agr_quiet_dur_get(const stmdev_ctx_t * ctx,uint8_t * val)3586 int32_t lsm303agr_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val)
3587 {
3588 lsm303agr_time_latency_a_t time_latency_a;
3589 int32_t ret;
3590
3591 ret = lsm303agr_read_reg(ctx, LSM303AGR_TIME_LATENCY_A,
3592 (uint8_t *)&time_latency_a, 1);
3593 *val = time_latency_a.tla;
3594
3595 return ret;
3596 }
3597
3598 /**
3599 * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse after
3600 * the end of the latency interval in which the click-detection
3601 * procedure can start, in cases where the device is configured for
3602 * double-click detection.[set]
3603 *
3604 * @param ctx Read / write interface definitions.(ptr)
3605 * @param val Change the values of tw in reg TIME_WINDOW_A
3606 * @retval Interface status (MANDATORY: return 0 -> no Error).
3607 *
3608 */
lsm303agr_double_tap_timeout_set(const stmdev_ctx_t * ctx,uint8_t val)3609 int32_t lsm303agr_double_tap_timeout_set(const stmdev_ctx_t *ctx,
3610 uint8_t val)
3611 {
3612 lsm303agr_time_window_a_t time_window_a;
3613 int32_t ret;
3614
3615 ret = lsm303agr_read_reg(ctx, LSM303AGR_TIME_WINDOW_A,
3616 (uint8_t *)&time_window_a, 1);
3617
3618 if (ret == 0)
3619 {
3620 time_window_a.tw = (uint8_t)val;
3621 ret = lsm303agr_write_reg(ctx, LSM303AGR_TIME_WINDOW_A,
3622 (uint8_t *)&time_window_a, 1);
3623 }
3624
3625 return ret;
3626 }
3627
3628 /**
3629 * @brief The maximum interval of time (1 LSB = 1/ODR) that can elapse after
3630 * the end of the latency interval in which the click-detection
3631 * procedure can start, in cases where the device is configured for
3632 * double-click detection.[get]
3633 *
3634 * @param ctx Read / write interface definitions.(ptr)
3635 * @param val Get the values of tw in reg TIME_WINDOW_A.(ptr)
3636 * @retval Interface status (MANDATORY: return 0 -> no Error).
3637 *
3638 */
lsm303agr_double_tap_timeout_get(const stmdev_ctx_t * ctx,uint8_t * val)3639 int32_t lsm303agr_double_tap_timeout_get(const stmdev_ctx_t *ctx,
3640 uint8_t *val)
3641 {
3642 lsm303agr_time_window_a_t time_window_a;
3643 int32_t ret;
3644
3645 ret = lsm303agr_read_reg(ctx, LSM303AGR_TIME_WINDOW_A,
3646 (uint8_t *)&time_window_a, 1);
3647 *val = time_window_a.tw;
3648
3649 return ret;
3650 }
3651
3652 /**
3653 * @}
3654 *
3655 */
3656
3657 /**
3658 * @addtogroup activity_inactivity_xl
3659 * @brief This section group all the functions concerning activity
3660 * inactivity functionality foe accelerometer
3661 * @{
3662 *
3663 */
3664
3665 /**
3666 * @brief Sleep-to-wake, return-to-sleep activation
3667 * threshold in low-power mode.[set]
3668 * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
3669 *
3670 * @param ctx Read / write interface definitions.(ptr)
3671 * @param val Change the values of acth in reg ACT_THS_A
3672 * @retval Interface status (MANDATORY: return 0 -> no Error).
3673 *
3674 */
lsm303agr_act_threshold_set(const stmdev_ctx_t * ctx,uint8_t val)3675 int32_t lsm303agr_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val)
3676 {
3677 lsm303agr_act_ths_a_t act_ths_a;
3678 int32_t ret;
3679
3680 ret = lsm303agr_read_reg(ctx, LSM303AGR_ACT_THS_A,
3681 (uint8_t *)&act_ths_a, 1);
3682
3683 if (ret == 0)
3684 {
3685 act_ths_a.acth = (uint8_t)val;
3686 ret = lsm303agr_write_reg(ctx, LSM303AGR_ACT_THS_A,
3687 (uint8_t *)&act_ths_a, 1);
3688 }
3689
3690 return ret;
3691 }
3692
3693 /**
3694 * @brief Sleep-to-wake, return-to-sleep activation
3695 * threshold in low-power mode.[get]
3696 * 1 LSb = 16mg@2g / 32mg@4g / 62mg@8g / 186mg@16g
3697 *
3698 * @param ctx Read / write interface definitions.(ptr)
3699 * @param val Get the values of acth in reg ACT_THS_A.(ptr)
3700 * @retval Interface status (MANDATORY: return 0 -> no Error).
3701 *
3702 */
lsm303agr_act_threshold_get(const stmdev_ctx_t * ctx,uint8_t * val)3703 int32_t lsm303agr_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val)
3704 {
3705 lsm303agr_act_ths_a_t act_ths_a;
3706 int32_t ret;
3707
3708 ret = lsm303agr_read_reg(ctx, LSM303AGR_ACT_THS_A,
3709 (uint8_t *)&act_ths_a, 1);
3710 *val = act_ths_a.acth;
3711
3712 return ret;
3713 }
3714
3715 /**
3716 * @brief Sleep-to-wake, return-to-sleep duration = (8*1[LSb]+1)/ODR.[set]
3717 *
3718 * @param ctx Read / write interface definitions.(ptr)
3719 * @param val Change the values of actd in reg ACT_DUR_A
3720 * @retval Interface status (MANDATORY: return 0 -> no Error).
3721 *
3722 */
lsm303agr_act_timeout_set(const stmdev_ctx_t * ctx,uint8_t val)3723 int32_t lsm303agr_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val)
3724 {
3725 lsm303agr_act_dur_a_t act_dur_a;
3726 int32_t ret;
3727
3728 ret = lsm303agr_read_reg(ctx, LSM303AGR_ACT_DUR_A,
3729 (uint8_t *)&act_dur_a, 1);
3730
3731 if (ret == 0)
3732 {
3733 act_dur_a.actd = (uint8_t)val;
3734 ret = lsm303agr_write_reg(ctx, LSM303AGR_ACT_DUR_A,
3735 (uint8_t *)&act_dur_a, 1);
3736 }
3737
3738 return ret;
3739 }
3740
3741 /**
3742 * @brief Sleep-to-wake, return-to-sleep duration = (8*1[LSb]+1)/ODR.[get]
3743 *
3744 * @param ctx Read / write interface definitions.(ptr)
3745 * @param val Get the values of actd in reg ACT_DUR_A.(ptr)
3746 * @retval Interface status (MANDATORY: return 0 -> no Error).
3747 *
3748 */
lsm303agr_act_timeout_get(const stmdev_ctx_t * ctx,uint8_t * val)3749 int32_t lsm303agr_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val)
3750 {
3751 lsm303agr_act_dur_a_t act_dur_a;
3752 int32_t ret;
3753
3754 ret = lsm303agr_read_reg(ctx, LSM303AGR_ACT_DUR_A,
3755 (uint8_t *)&act_dur_a, 1);
3756 *val = act_dur_a.actd;
3757
3758 return ret;
3759 }
3760
3761 /**
3762 * @}
3763 *
3764 */
3765
3766 /**
3767 * @addtogroup serial_interface
3768 * @brief This section group all the functions concerning serial
3769 * interface management
3770 * @{
3771 *
3772 */
3773
3774 /**
3775 * @brief SPI Serial Interface Mode selection.[set]
3776 *
3777 * @param ctx Read / write interface definitions.(ptr)
3778 * @param val Change the values of sim in reg CTRL_REG4_A
3779 * @retval Interface status (MANDATORY: return 0 -> no Error).
3780 *
3781 */
lsm303agr_xl_spi_mode_set(const stmdev_ctx_t * ctx,lsm303agr_sim_a_t val)3782 int32_t lsm303agr_xl_spi_mode_set(const stmdev_ctx_t *ctx,
3783 lsm303agr_sim_a_t val)
3784 {
3785 lsm303agr_ctrl_reg4_a_t ctrl_reg4_a;
3786 int32_t ret;
3787
3788 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
3789 (uint8_t *)&ctrl_reg4_a, 1);
3790
3791 if (ret == 0)
3792 {
3793 ctrl_reg4_a.spi_enable = (uint8_t)val;
3794 ret = lsm303agr_write_reg(ctx, LSM303AGR_CTRL_REG4_A,
3795 (uint8_t *)&ctrl_reg4_a, 1);
3796 }
3797
3798 return ret;
3799 }
3800
3801 /**
3802 * @brief SPI Serial Interface Mode selection.[get]
3803 *
3804 * @param ctx Read / write interface definitions.(ptr)
3805 * @param val Get the values of sim in reg CTRL_REG4_A.(ptr)
3806 * @retval Interface status (MANDATORY: return 0 -> no Error).
3807 *
3808 */
lsm303agr_xl_spi_mode_get(const stmdev_ctx_t * ctx,lsm303agr_sim_a_t * val)3809 int32_t lsm303agr_xl_spi_mode_get(const stmdev_ctx_t *ctx,
3810 lsm303agr_sim_a_t *val)
3811 {
3812 lsm303agr_ctrl_reg4_a_t ctrl_reg4_a;
3813 int32_t ret;
3814
3815 ret = lsm303agr_read_reg(ctx, LSM303AGR_CTRL_REG4_A,
3816 (uint8_t *)&ctrl_reg4_a, 1);
3817
3818 switch (ctrl_reg4_a.spi_enable)
3819 {
3820 case LSM303AGR_SPI_4_WIRE:
3821 *val = LSM303AGR_SPI_4_WIRE;
3822 break;
3823
3824 case LSM303AGR_SPI_3_WIRE:
3825 *val = LSM303AGR_SPI_3_WIRE;
3826 break;
3827
3828 default:
3829 *val = LSM303AGR_SPI_4_WIRE;
3830 break;
3831 }
3832
3833 return ret;
3834 }
3835
3836 /**
3837 * @brief Enable/Disable I2C interface.[set]
3838 *
3839 * @param ctx Read / write interface definitions.(ptr)
3840 * @param val Change the values of i2c_dis in reg CFG_REG_C_M
3841 * @retval Interface status (MANDATORY: return 0 -> no Error).
3842 *
3843 */
lsm303agr_mag_i2c_interface_set(const stmdev_ctx_t * ctx,lsm303agr_i2c_dis_m_t val)3844 int32_t lsm303agr_mag_i2c_interface_set(const stmdev_ctx_t *ctx,
3845 lsm303agr_i2c_dis_m_t val)
3846 {
3847 lsm303agr_cfg_reg_c_m_t cfg_reg_c_m;
3848 int32_t ret;
3849
3850 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
3851 (uint8_t *)&cfg_reg_c_m, 1);
3852
3853 if (ret == 0)
3854 {
3855 cfg_reg_c_m.i2c_dis = (uint8_t)val;
3856 ret = lsm303agr_write_reg(ctx, LSM303AGR_CFG_REG_C_M,
3857 (uint8_t *)&cfg_reg_c_m, 1);
3858 }
3859
3860 return ret;
3861 }
3862
3863 /**
3864 * @brief Enable/Disable I2C interface.[get]
3865 *
3866 * @param ctx Read / write interface definitions.(ptr)
3867 * @param val Get the values of i2c_dis in reg CFG_REG_C_M.(ptr)
3868 * @retval Interface status (MANDATORY: return 0 -> no Error).
3869 *
3870 */
lsm303agr_mag_i2c_interface_get(const stmdev_ctx_t * ctx,lsm303agr_i2c_dis_m_t * val)3871 int32_t lsm303agr_mag_i2c_interface_get(const stmdev_ctx_t *ctx,
3872 lsm303agr_i2c_dis_m_t *val)
3873 {
3874 lsm303agr_cfg_reg_c_m_t cfg_reg_c_m;
3875 int32_t ret;
3876
3877 ret = lsm303agr_read_reg(ctx, LSM303AGR_CFG_REG_C_M,
3878 (uint8_t *)&cfg_reg_c_m, 1);
3879
3880 switch (cfg_reg_c_m.i2c_dis)
3881 {
3882 case LSM303AGR_I2C_ENABLE:
3883 *val = LSM303AGR_I2C_ENABLE;
3884 break;
3885
3886 case LSM303AGR_I2C_DISABLE:
3887 *val = LSM303AGR_I2C_DISABLE;
3888 break;
3889
3890 default:
3891 *val = LSM303AGR_I2C_ENABLE;
3892 break;
3893 }
3894
3895 return ret;
3896 }
3897
3898 /**
3899 * @}
3900 *
3901 */
3902
3903 /**
3904 * @}
3905 *
3906 */
3907
3908 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
3909
