1 /** 2 ****************************************************************************** 3 * @file lsm303agr_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * lsm303agr_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef LSM303AGR_REGS_H 23 #define LSM303AGR_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup LSM303AGR 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup lsm303agr_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format**/ 172 #define LSM303AGR_I2C_ADD_XL 0x33U 173 #define LSM303AGR_I2C_ADD_MG 0x3DU 174 175 /** Device Identification (Who am I) **/ 176 #define LSM303AGR_ID_XL 0x33U 177 #define LSM303AGR_ID_MG 0x40U 178 179 /** 180 * @} 181 * 182 */ 183 184 #define LSM303AGR_STATUS_REG_AUX_A 0x07U 185 typedef struct 186 { 187 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 188 uint8_t not_used_01 : 2; 189 uint8_t tda : 1; 190 uint8_t not_used_02 : 3; 191 uint8_t tor : 1; 192 uint8_t not_used_03 : 1; 193 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 194 uint8_t not_used_03 : 1; 195 uint8_t tor : 1; 196 uint8_t not_used_02 : 3; 197 uint8_t tda : 1; 198 uint8_t not_used_01 : 2; 199 #endif /* DRV_BYTE_ORDER */ 200 } lsm303agr_status_reg_aux_a_t; 201 202 #define LSM303AGR_OUT_TEMP_L_A 0x0CU 203 #define LSM303AGR_OUT_TEMP_H_A 0x0DU 204 #define LSM303AGR_INT_COUNTER_REG_A 0x0EU 205 #define LSM303AGR_WHO_AM_I_A 0x0FU 206 207 #define LSM303AGR_TEMP_CFG_REG_A 0x1FU 208 typedef struct 209 { 210 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 211 uint8_t not_used_01 : 6; 212 uint8_t temp_en : 2; 213 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 214 uint8_t temp_en : 2; 215 uint8_t not_used_01 : 6; 216 #endif /* DRV_BYTE_ORDER */ 217 } lsm303agr_temp_cfg_reg_a_t; 218 219 #define LSM303AGR_CTRL_REG1_A 0x20U 220 typedef struct 221 { 222 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 223 uint8_t xen : 1; 224 uint8_t yen : 1; 225 uint8_t zen : 1; 226 uint8_t lpen : 1; 227 uint8_t odr : 4; 228 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 229 uint8_t odr : 4; 230 uint8_t lpen : 1; 231 uint8_t zen : 1; 232 uint8_t yen : 1; 233 uint8_t xen : 1; 234 #endif /* DRV_BYTE_ORDER */ 235 } lsm303agr_ctrl_reg1_a_t; 236 237 #define LSM303AGR_CTRL_REG2_A 0x21U 238 typedef struct 239 { 240 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 241 uint8_t hp : 3; /* HPCLICK + HPIS2 + HPIS1 -> HP */ 242 uint8_t fds : 1; 243 uint8_t hpcf : 2; 244 uint8_t hpm : 2; 245 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 246 uint8_t hpm : 2; 247 uint8_t hpcf : 2; 248 uint8_t fds : 1; 249 uint8_t hp : 3; /* HPCLICK + HPIS2 + HPIS1 -> HP */ 250 #endif /* DRV_BYTE_ORDER */ 251 } lsm303agr_ctrl_reg2_a_t; 252 253 #define LSM303AGR_CTRL_REG3_A 0x22U 254 typedef struct 255 { 256 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 257 uint8_t not_used_01 : 1; 258 uint8_t i1_overrun : 1; 259 uint8_t i1_wtm : 1; 260 uint8_t i1_drdy2 : 1; 261 uint8_t i1_drdy1 : 1; 262 uint8_t i1_aoi2 : 1; 263 uint8_t i1_aoi1 : 1; 264 uint8_t i1_click : 1; 265 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 266 uint8_t i1_click : 1; 267 uint8_t i1_aoi1 : 1; 268 uint8_t i1_aoi2 : 1; 269 uint8_t i1_drdy1 : 1; 270 uint8_t i1_drdy2 : 1; 271 uint8_t i1_wtm : 1; 272 uint8_t i1_overrun : 1; 273 uint8_t not_used_01 : 1; 274 #endif /* DRV_BYTE_ORDER */ 275 } lsm303agr_ctrl_reg3_a_t; 276 277 #define LSM303AGR_CTRL_REG4_A 0x23U 278 typedef struct 279 { 280 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 281 uint8_t spi_enable : 1; 282 uint8_t st : 2; 283 uint8_t hr : 1; 284 uint8_t fs : 2; 285 uint8_t ble : 1; 286 uint8_t bdu : 1; 287 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 288 uint8_t bdu : 1; 289 uint8_t ble : 1; 290 uint8_t fs : 2; 291 uint8_t hr : 1; 292 uint8_t st : 2; 293 uint8_t spi_enable : 1; 294 #endif /* DRV_BYTE_ORDER */ 295 } lsm303agr_ctrl_reg4_a_t; 296 297 #define LSM303AGR_CTRL_REG5_A 0x24U 298 typedef struct 299 { 300 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 301 uint8_t d4d_int2 : 1; 302 uint8_t lir_int2 : 1; 303 uint8_t d4d_int1 : 1; 304 uint8_t lir_int1 : 1; 305 uint8_t not_used_01 : 2; 306 uint8_t fifo_en : 1; 307 uint8_t boot : 1; 308 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 309 uint8_t boot : 1; 310 uint8_t fifo_en : 1; 311 uint8_t not_used_01 : 2; 312 uint8_t lir_int1 : 1; 313 uint8_t d4d_int1 : 1; 314 uint8_t lir_int2 : 1; 315 uint8_t d4d_int2 : 1; 316 #endif /* DRV_BYTE_ORDER */ 317 } lsm303agr_ctrl_reg5_a_t; 318 319 #define LSM303AGR_CTRL_REG6_A 0x25U 320 typedef struct 321 { 322 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 323 uint8_t not_used_01 : 1; 324 uint8_t h_lactive : 1; 325 uint8_t not_used_02 : 1; 326 uint8_t p2_act : 1; 327 uint8_t boot_i2 : 1; 328 uint8_t i2_int2 : 1; 329 uint8_t i2_int1 : 1; 330 uint8_t i2_clicken : 1; 331 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 332 uint8_t i2_clicken : 1; 333 uint8_t i2_int1 : 1; 334 uint8_t i2_int2 : 1; 335 uint8_t boot_i2 : 1; 336 uint8_t p2_act : 1; 337 uint8_t not_used_02 : 1; 338 uint8_t h_lactive : 1; 339 uint8_t not_used_01 : 1; 340 #endif /* DRV_BYTE_ORDER */ 341 } lsm303agr_ctrl_reg6_a_t; 342 343 #define LSM303AGR_REFERENCE_A 0x26U 344 #define LSM303AGR_STATUS_REG_A 0x27U 345 typedef struct 346 { 347 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 348 uint8_t xda : 1; 349 uint8_t yda : 1; 350 uint8_t zda : 1; 351 uint8_t zyxda : 1; 352 uint8_t _xor : 1; 353 uint8_t yor : 1; 354 uint8_t zor : 1; 355 uint8_t zyxor : 1; 356 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 357 uint8_t zyxor : 1; 358 uint8_t zor : 1; 359 uint8_t yor : 1; 360 uint8_t _xor : 1; 361 uint8_t zyxda : 1; 362 uint8_t zda : 1; 363 uint8_t yda : 1; 364 uint8_t xda : 1; 365 #endif /* DRV_BYTE_ORDER */ 366 } lsm303agr_status_reg_a_t; 367 368 #define LSM303AGR_OUT_X_L_A 0x28U 369 #define LSM303AGR_OUT_X_H_A 0x29U 370 #define LSM303AGR_OUT_Y_L_A 0x2AU 371 #define LSM303AGR_OUT_Y_H_A 0x2BU 372 #define LSM303AGR_OUT_Z_L_A 0x2CU 373 #define LSM303AGR_OUT_Z_H_A 0x2DU 374 #define LSM303AGR_FIFO_CTRL_REG_A 0x2EU 375 typedef struct 376 { 377 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 378 uint8_t fth : 5; 379 uint8_t tr : 1; 380 uint8_t fm : 2; 381 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 382 uint8_t fm : 2; 383 uint8_t tr : 1; 384 uint8_t fth : 5; 385 #endif /* DRV_BYTE_ORDER */ 386 } lsm303agr_fifo_ctrl_reg_a_t; 387 388 #define LSM303AGR_FIFO_SRC_REG_A 0x2FU 389 typedef struct 390 { 391 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 392 uint8_t fss : 5; 393 uint8_t empty : 1; 394 uint8_t ovrn_fifo : 1; 395 uint8_t wtm : 1; 396 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 397 uint8_t wtm : 1; 398 uint8_t ovrn_fifo : 1; 399 uint8_t empty : 1; 400 uint8_t fss : 5; 401 #endif /* DRV_BYTE_ORDER */ 402 } lsm303agr_fifo_src_reg_a_t; 403 404 #define LSM303AGR_INT1_CFG_A 0x30U 405 typedef struct 406 { 407 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 408 uint8_t xlie : 1; /* or XDOWNE */ 409 uint8_t xhie : 1; /* or XUPE */ 410 uint8_t ylie : 1; /* or YDOWNE */ 411 uint8_t yhie : 1; /* or YUPE */ 412 uint8_t zlie : 1; /* or ZDOWNE */ 413 uint8_t zhie : 1; /* or ZUPE */ 414 uint8_t _6d : 1; 415 uint8_t aoi : 1; 416 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 417 uint8_t aoi : 1; 418 uint8_t _6d : 1; 419 uint8_t zhie : 1; /* or ZUPE */ 420 uint8_t zlie : 1; /* or ZDOWNE */ 421 uint8_t yhie : 1; /* or YUPE */ 422 uint8_t ylie : 1; /* or YDOWNE */ 423 uint8_t xhie : 1; /* or XUPE */ 424 uint8_t xlie : 1; /* or XDOWNE */ 425 #endif /* DRV_BYTE_ORDER */ 426 } lsm303agr_int1_cfg_a_t; 427 428 #define LSM303AGR_INT1_SRC_A 0x31U 429 typedef struct 430 { 431 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 432 uint8_t xl : 1; 433 uint8_t xh : 1; 434 uint8_t yl : 1; 435 uint8_t yh : 1; 436 uint8_t zl : 1; 437 uint8_t zh : 1; 438 uint8_t ia : 1; 439 uint8_t not_used_01 : 1; 440 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 441 uint8_t not_used_01 : 1; 442 uint8_t ia : 1; 443 uint8_t zh : 1; 444 uint8_t zl : 1; 445 uint8_t yh : 1; 446 uint8_t yl : 1; 447 uint8_t xh : 1; 448 uint8_t xl : 1; 449 #endif /* DRV_BYTE_ORDER */ 450 } lsm303agr_int1_src_a_t; 451 452 #define LSM303AGR_INT1_THS_A 0x32U 453 typedef struct 454 { 455 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 456 uint8_t ths : 7; 457 uint8_t not_used_01 : 1; 458 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 459 uint8_t not_used_01 : 1; 460 uint8_t ths : 7; 461 #endif /* DRV_BYTE_ORDER */ 462 } lsm303agr_int1_ths_a_t; 463 464 #define LSM303AGR_INT1_DURATION_A 0x33U 465 typedef struct 466 { 467 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 468 uint8_t d : 7; 469 uint8_t not_used_01 : 1; 470 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 471 uint8_t not_used_01 : 1; 472 uint8_t d : 7; 473 #endif /* DRV_BYTE_ORDER */ 474 } lsm303agr_int1_duration_a_t; 475 476 #define LSM303AGR_INT2_CFG_A 0x34U 477 typedef struct 478 { 479 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 480 uint8_t xlie : 1; 481 uint8_t xhie : 1; 482 uint8_t ylie : 1; 483 uint8_t yhie : 1; 484 uint8_t zlie : 1; 485 uint8_t zhie : 1; 486 uint8_t _6d : 1; 487 uint8_t aoi : 1; 488 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 489 uint8_t aoi : 1; 490 uint8_t _6d : 1; 491 uint8_t zhie : 1; 492 uint8_t zlie : 1; 493 uint8_t yhie : 1; 494 uint8_t ylie : 1; 495 uint8_t xhie : 1; 496 uint8_t xlie : 1; 497 #endif /* DRV_BYTE_ORDER */ 498 } lsm303agr_int2_cfg_a_t; 499 500 #define LSM303AGR_INT2_SRC_A 0x35U 501 typedef struct 502 { 503 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 504 uint8_t xl : 1; 505 uint8_t xh : 1; 506 uint8_t yl : 1; 507 uint8_t yh : 1; 508 uint8_t zl : 1; 509 uint8_t zh : 1; 510 uint8_t ia : 1; 511 uint8_t not_used_01 : 1; 512 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 513 uint8_t not_used_01 : 1; 514 uint8_t ia : 1; 515 uint8_t zh : 1; 516 uint8_t zl : 1; 517 uint8_t yh : 1; 518 uint8_t yl : 1; 519 uint8_t xh : 1; 520 uint8_t xl : 1; 521 #endif /* DRV_BYTE_ORDER */ 522 } lsm303agr_int2_src_a_t; 523 524 #define LSM303AGR_INT2_THS_A 0x36U 525 typedef struct 526 { 527 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 528 uint8_t ths : 7; 529 uint8_t not_used_01 : 1; 530 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 531 uint8_t not_used_01 : 1; 532 uint8_t ths : 7; 533 #endif /* DRV_BYTE_ORDER */ 534 } lsm303agr_int2_ths_a_t; 535 536 #define LSM303AGR_INT2_DURATION_A 0x37U 537 typedef struct 538 { 539 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 540 uint8_t d : 7; 541 uint8_t not_used_01 : 1; 542 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 543 uint8_t not_used_01 : 1; 544 uint8_t d : 7; 545 #endif /* DRV_BYTE_ORDER */ 546 } lsm303agr_int2_duration_a_t; 547 548 #define LSM303AGR_CLICK_CFG_A 0x38U 549 typedef struct 550 { 551 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 552 uint8_t xs : 1; 553 uint8_t xd : 1; 554 uint8_t ys : 1; 555 uint8_t yd : 1; 556 uint8_t zs : 1; 557 uint8_t zd : 1; 558 uint8_t not_used_01 : 2; 559 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 560 uint8_t not_used_01 : 2; 561 uint8_t zd : 1; 562 uint8_t zs : 1; 563 uint8_t yd : 1; 564 uint8_t ys : 1; 565 uint8_t xd : 1; 566 uint8_t xs : 1; 567 #endif /* DRV_BYTE_ORDER */ 568 } lsm303agr_click_cfg_a_t; 569 570 #define LSM303AGR_CLICK_SRC_A 0x39U 571 typedef struct 572 { 573 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 574 uint8_t x : 1; 575 uint8_t y : 1; 576 uint8_t z : 1; 577 uint8_t sign : 1; 578 uint8_t sclick : 1; 579 uint8_t dclick : 1; 580 uint8_t ia : 1; 581 uint8_t not_used_01 : 1; 582 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 583 uint8_t not_used_01 : 1; 584 uint8_t ia : 1; 585 uint8_t dclick : 1; 586 uint8_t sclick : 1; 587 uint8_t sign : 1; 588 uint8_t z : 1; 589 uint8_t y : 1; 590 uint8_t x : 1; 591 #endif /* DRV_BYTE_ORDER */ 592 } lsm303agr_click_src_a_t; 593 594 #define LSM303AGR_CLICK_THS_A 0x3AU 595 typedef struct 596 { 597 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 598 uint8_t ths : 7; 599 uint8_t not_used_01 : 1; 600 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 601 uint8_t not_used_01 : 1; 602 uint8_t ths : 7; 603 #endif /* DRV_BYTE_ORDER */ 604 } lsm303agr_click_ths_a_t; 605 606 #define LSM303AGR_TIME_LIMIT_A 0x3BU 607 typedef struct 608 { 609 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 610 uint8_t tli : 7; 611 uint8_t not_used_01 : 1; 612 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 613 uint8_t not_used_01 : 1; 614 uint8_t tli : 7; 615 #endif /* DRV_BYTE_ORDER */ 616 } lsm303agr_time_limit_a_t; 617 618 #define LSM303AGR_TIME_LATENCY_A 0x3CU 619 typedef struct 620 { 621 uint8_t tla : 8; 622 } lsm303agr_time_latency_a_t; 623 624 #define LSM303AGR_TIME_WINDOW_A 0x3DU 625 typedef struct 626 { 627 uint8_t tw : 8; 628 } lsm303agr_time_window_a_t; 629 630 #define LSM303AGR_ACT_THS_A 0x3EU 631 typedef struct 632 { 633 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 634 uint8_t acth : 7; 635 uint8_t not_used_01 : 1; 636 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 637 uint8_t not_used_01 : 1; 638 uint8_t acth : 7; 639 #endif /* DRV_BYTE_ORDER */ 640 } lsm303agr_act_ths_a_t; 641 642 #define LSM303AGR_ACT_DUR_A 0x3FU 643 typedef struct 644 { 645 uint8_t actd : 8; 646 } lsm303agr_act_dur_a_t; 647 648 #define LSM303AGR_OFFSET_X_REG_L_M 0x45U 649 #define LSM303AGR_OFFSET_X_REG_H_M 0x46U 650 #define LSM303AGR_OFFSET_Y_REG_L_M 0x47U 651 #define LSM303AGR_OFFSET_Y_REG_H_M 0x48U 652 #define LSM303AGR_OFFSET_Z_REG_L_M 0x49U 653 #define LSM303AGR_OFFSET_Z_REG_H_M 0x4AU 654 #define LSM303AGR_WHO_AM_I_M 0x4FU 655 #define LSM303AGR_CFG_REG_A_M 0x60U 656 typedef struct 657 { 658 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 659 uint8_t md : 2; 660 uint8_t odr : 2; 661 uint8_t lp : 1; 662 uint8_t soft_rst : 1; 663 uint8_t reboot : 1; 664 uint8_t comp_temp_en : 1; 665 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 666 uint8_t comp_temp_en : 1; 667 uint8_t reboot : 1; 668 uint8_t soft_rst : 1; 669 uint8_t lp : 1; 670 uint8_t odr : 2; 671 uint8_t md : 2; 672 #endif /* DRV_BYTE_ORDER */ 673 } lsm303agr_cfg_reg_a_m_t; 674 675 #define LSM303AGR_CFG_REG_B_M 0x61U 676 typedef struct 677 { 678 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 679 uint8_t lpf : 1; 680 uint8_t set_rst : 2; /* OFF_CANC + Set_FREQ */ 681 uint8_t int_on_dataoff : 1; 682 uint8_t off_canc_one_shot : 1; 683 uint8_t not_used_01 : 3; 684 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 685 uint8_t not_used_01 : 3; 686 uint8_t off_canc_one_shot : 1; 687 uint8_t int_on_dataoff : 1; 688 uint8_t set_rst : 2; /* OFF_CANC + Set_FREQ */ 689 uint8_t lpf : 1; 690 #endif /* DRV_BYTE_ORDER */ 691 } lsm303agr_cfg_reg_b_m_t; 692 693 #define LSM303AGR_CFG_REG_C_M 0x62U 694 typedef struct 695 { 696 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 697 uint8_t int_mag : 1; 698 uint8_t self_test : 1; 699 uint8_t not_used_01 : 1; 700 uint8_t ble : 1; 701 uint8_t bdu : 1; 702 uint8_t i2c_dis : 1; 703 uint8_t int_mag_pin : 1; 704 uint8_t not_used_02 : 1; 705 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 706 uint8_t not_used_02 : 1; 707 uint8_t int_mag_pin : 1; 708 uint8_t i2c_dis : 1; 709 uint8_t bdu : 1; 710 uint8_t ble : 1; 711 uint8_t not_used_01 : 1; 712 uint8_t self_test : 1; 713 uint8_t int_mag : 1; 714 #endif /* DRV_BYTE_ORDER */ 715 } lsm303agr_cfg_reg_c_m_t; 716 717 #define LSM303AGR_INT_CRTL_REG_M 0x63U 718 typedef struct 719 { 720 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 721 uint8_t ien : 1; 722 uint8_t iel : 1; 723 uint8_t iea : 1; 724 uint8_t not_used_01 : 2; 725 uint8_t zien : 1; 726 uint8_t yien : 1; 727 uint8_t xien : 1; 728 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 729 uint8_t xien : 1; 730 uint8_t yien : 1; 731 uint8_t zien : 1; 732 uint8_t not_used_01 : 2; 733 uint8_t iea : 1; 734 uint8_t iel : 1; 735 uint8_t ien : 1; 736 #endif /* DRV_BYTE_ORDER */ 737 } lsm303agr_int_crtl_reg_m_t; 738 739 #define LSM303AGR_INT_SOURCE_REG_M 0x64U 740 typedef struct 741 { 742 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 743 uint8_t _int : 1; 744 uint8_t mroi : 1; 745 uint8_t n_th_s_z : 1; 746 uint8_t n_th_s_y : 1; 747 uint8_t n_th_s_x : 1; 748 uint8_t p_th_s_z : 1; 749 uint8_t p_th_s_y : 1; 750 uint8_t p_th_s_x : 1; 751 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 752 uint8_t p_th_s_x : 1; 753 uint8_t p_th_s_y : 1; 754 uint8_t p_th_s_z : 1; 755 uint8_t n_th_s_x : 1; 756 uint8_t n_th_s_y : 1; 757 uint8_t n_th_s_z : 1; 758 uint8_t mroi : 1; 759 uint8_t _int : 1; 760 #endif /* DRV_BYTE_ORDER */ 761 } lsm303agr_int_source_reg_m_t; 762 763 #define LSM303AGR_INT_THS_L_REG_M 0x65U 764 #define LSM303AGR_INT_THS_H_REG_M 0x66U 765 #define LSM303AGR_STATUS_REG_M 0x67U 766 typedef struct 767 { 768 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 769 uint8_t xda : 1; 770 uint8_t yda : 1; 771 uint8_t zda : 1; 772 uint8_t zyxda : 1; 773 uint8_t _xor : 1; 774 uint8_t yor : 1; 775 uint8_t zor : 1; 776 uint8_t zyxor : 1; 777 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 778 uint8_t zyxor : 1; 779 uint8_t zor : 1; 780 uint8_t yor : 1; 781 uint8_t _xor : 1; 782 uint8_t zyxda : 1; 783 uint8_t zda : 1; 784 uint8_t yda : 1; 785 uint8_t xda : 1; 786 #endif /* DRV_BYTE_ORDER */ 787 } lsm303agr_status_reg_m_t; 788 789 #define LSM303AGR_OUTX_L_REG_M 0x68U 790 #define LSM303AGR_OUTX_H_REG_M 0x69U 791 #define LSM303AGR_OUTY_L_REG_M 0x6AU 792 #define LSM303AGR_OUTY_H_REG_M 0x6BU 793 #define LSM303AGR_OUTZ_L_REG_M 0x6CU 794 #define LSM303AGR_OUTZ_H_REG_M 0x6DU 795 796 /** 797 * @defgroup LSM303AGR_Register_Union 798 * @brief This union group all the registers having a bit-field 799 * description. 800 * This union is useful but it's not needed by the driver. 801 * 802 * REMOVING this union you are compliant with: 803 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 804 * 805 * @{ 806 * 807 */ 808 typedef union 809 { 810 lsm303agr_status_reg_aux_a_t status_reg_aux_a; 811 lsm303agr_temp_cfg_reg_a_t temp_cfg_reg_a; 812 lsm303agr_ctrl_reg1_a_t ctrl_reg1_a; 813 lsm303agr_ctrl_reg2_a_t ctrl_reg2_a; 814 lsm303agr_ctrl_reg3_a_t ctrl_reg3_a; 815 lsm303agr_ctrl_reg4_a_t ctrl_reg4_a; 816 lsm303agr_ctrl_reg5_a_t ctrl_reg5_a; 817 lsm303agr_ctrl_reg6_a_t ctrl_reg6_a; 818 lsm303agr_status_reg_a_t status_reg_a; 819 lsm303agr_fifo_ctrl_reg_a_t fifo_ctrl_reg_a; 820 lsm303agr_fifo_src_reg_a_t fifo_src_reg_a; 821 lsm303agr_int1_cfg_a_t int1_cfg_a; 822 lsm303agr_int1_src_a_t int1_src_a; 823 lsm303agr_int1_ths_a_t int1_ths_a; 824 lsm303agr_int1_duration_a_t int1_duration_a; 825 lsm303agr_int2_cfg_a_t int2_cfg_a; 826 lsm303agr_int2_src_a_t int2_src_a; 827 lsm303agr_int2_ths_a_t int2_ths_a; 828 lsm303agr_int2_duration_a_t int2_duration_a; 829 lsm303agr_click_cfg_a_t click_cfg_a; 830 lsm303agr_click_src_a_t click_src_a; 831 lsm303agr_click_ths_a_t click_ths_a; 832 lsm303agr_time_limit_a_t time_limit_a; 833 lsm303agr_time_latency_a_t time_latency_a; 834 lsm303agr_time_window_a_t time_window_a; 835 lsm303agr_act_ths_a_t act_ths_a; 836 lsm303agr_act_dur_a_t act_dur_a; 837 lsm303agr_cfg_reg_a_m_t cfg_reg_a_m; 838 lsm303agr_cfg_reg_b_m_t cfg_reg_b_m; 839 lsm303agr_cfg_reg_c_m_t cfg_reg_c_m; 840 lsm303agr_int_crtl_reg_m_t int_crtl_reg_m; 841 lsm303agr_int_source_reg_m_t int_source_reg_m; 842 lsm303agr_status_reg_m_t status_reg_m; 843 bitwise_t bitwise; 844 uint8_t byte; 845 } lsm303agr_reg_t; 846 847 /** 848 * @} 849 * 850 */ 851 852 #ifndef __weak 853 #define __weak __attribute__((weak)) 854 #endif /* __weak */ 855 856 /* 857 * These are the basic platform dependent I/O routines to read 858 * and write device registers connected on a standard bus. 859 * The driver keeps offering a default implementation based on function 860 * pointers to read/write routines for backward compatibility. 861 * The __weak directive allows the final application to overwrite 862 * them with a custom implementation. 863 */ 864 865 int32_t lsm303agr_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 866 uint8_t *data, 867 uint16_t len); 868 int32_t lsm303agr_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 869 uint8_t *data, 870 uint16_t len); 871 872 float_t lsm303agr_from_fs_2g_hr_to_mg(int16_t lsb); 873 float_t lsm303agr_from_fs_4g_hr_to_mg(int16_t lsb); 874 float_t lsm303agr_from_fs_8g_hr_to_mg(int16_t lsb); 875 float_t lsm303agr_from_fs_16g_hr_to_mg(int16_t lsb); 876 float_t lsm303agr_from_lsb_hr_to_celsius(int16_t lsb); 877 878 float_t lsm303agr_from_fs_2g_nm_to_mg(int16_t lsb); 879 float_t lsm303agr_from_fs_4g_nm_to_mg(int16_t lsb); 880 float_t lsm303agr_from_fs_8g_nm_to_mg(int16_t lsb); 881 float_t lsm303agr_from_fs_16g_nm_to_mg(int16_t lsb); 882 float_t lsm303agr_from_lsb_nm_to_celsius(int16_t lsb); 883 884 float_t lsm303agr_from_fs_2g_lp_to_mg(int16_t lsb); 885 float_t lsm303agr_from_fs_4g_lp_to_mg(int16_t lsb); 886 float_t lsm303agr_from_fs_8g_lp_to_mg(int16_t lsb); 887 float_t lsm303agr_from_fs_16g_lp_to_mg(int16_t lsb); 888 float_t lsm303agr_from_lsb_lp_to_celsius(int16_t lsb); 889 890 float_t lsm303agr_from_lsb_to_mgauss(int16_t lsb); 891 892 int32_t lsm303agr_temp_status_reg_get(const stmdev_ctx_t *ctx, 893 uint8_t *buff); 894 895 int32_t lsm303agr_temp_data_ready_get(const stmdev_ctx_t *ctx, 896 uint8_t *val); 897 898 int32_t lsm303agr_temp_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); 899 900 int32_t lsm303agr_temperature_raw_get(const stmdev_ctx_t *ctx, 901 int16_t *val); 902 903 typedef enum 904 { 905 LSM303AGR_TEMP_DISABLE = 0, 906 LSM303AGR_TEMP_ENABLE = 3, 907 } lsm303agr_temp_en_a_t; 908 int32_t lsm303agr_temperature_meas_set(const stmdev_ctx_t *ctx, 909 lsm303agr_temp_en_a_t val); 910 int32_t lsm303agr_temperature_meas_get(const stmdev_ctx_t *ctx, 911 lsm303agr_temp_en_a_t *val); 912 913 typedef enum 914 { 915 LSM303AGR_HR_12bit = 0, 916 LSM303AGR_NM_10bit = 1, 917 LSM303AGR_LP_8bit = 2, 918 } lsm303agr_op_md_a_t; 919 int32_t lsm303agr_xl_operating_mode_set(const stmdev_ctx_t *ctx, 920 lsm303agr_op_md_a_t val); 921 int32_t lsm303agr_xl_operating_mode_get(const stmdev_ctx_t *ctx, 922 lsm303agr_op_md_a_t *val); 923 924 typedef enum 925 { 926 LSM303AGR_XL_POWER_DOWN = 0, 927 LSM303AGR_XL_ODR_1Hz = 1, 928 LSM303AGR_XL_ODR_10Hz = 2, 929 LSM303AGR_XL_ODR_25Hz = 3, 930 LSM303AGR_XL_ODR_50Hz = 4, 931 LSM303AGR_XL_ODR_100Hz = 5, 932 LSM303AGR_XL_ODR_200Hz = 6, 933 LSM303AGR_XL_ODR_400Hz = 7, 934 LSM303AGR_XL_ODR_1kHz620_LP = 8, 935 LSM303AGR_XL_ODR_1kHz344_NM_HP_5kHz376_LP = 9, 936 } lsm303agr_odr_a_t; 937 int32_t lsm303agr_xl_data_rate_set(const stmdev_ctx_t *ctx, 938 lsm303agr_odr_a_t val); 939 int32_t lsm303agr_xl_data_rate_get(const stmdev_ctx_t *ctx, 940 lsm303agr_odr_a_t *val); 941 942 int32_t lsm303agr_xl_high_pass_on_outputs_set(const stmdev_ctx_t *ctx, 943 uint8_t val); 944 int32_t lsm303agr_xl_high_pass_on_outputs_get(const stmdev_ctx_t *ctx, 945 uint8_t *val); 946 947 typedef enum 948 { 949 LSM303AGR_AGGRESSIVE = 0, 950 LSM303AGR_STRONG = 1, 951 LSM303AGR_MEDIUM = 2, 952 LSM303AGR_LIGHT = 3, 953 } lsm303agr_hpcf_a_t; 954 int32_t lsm303agr_xl_high_pass_bandwidth_set(const stmdev_ctx_t *ctx, 955 lsm303agr_hpcf_a_t val); 956 int32_t lsm303agr_xl_high_pass_bandwidth_get(const stmdev_ctx_t *ctx, 957 lsm303agr_hpcf_a_t *val); 958 959 typedef enum 960 { 961 LSM303AGR_NORMAL_WITH_RST = 0, 962 LSM303AGR_REFERENCE_MODE = 1, 963 LSM303AGR_NORMAL = 2, 964 LSM303AGR_AUTORST_ON_INT = 3, 965 } lsm303agr_hpm_a_t; 966 int32_t lsm303agr_xl_high_pass_mode_set(const stmdev_ctx_t *ctx, 967 lsm303agr_hpm_a_t val); 968 int32_t lsm303agr_xl_high_pass_mode_get(const stmdev_ctx_t *ctx, 969 lsm303agr_hpm_a_t *val); 970 971 typedef enum 972 { 973 LSM303AGR_2g = 0, 974 LSM303AGR_4g = 1, 975 LSM303AGR_8g = 2, 976 LSM303AGR_16g = 3, 977 } lsm303agr_fs_a_t; 978 int32_t lsm303agr_xl_full_scale_set(const stmdev_ctx_t *ctx, 979 lsm303agr_fs_a_t val); 980 int32_t lsm303agr_xl_full_scale_get(const stmdev_ctx_t *ctx, 981 lsm303agr_fs_a_t *val); 982 983 int32_t lsm303agr_xl_block_data_update_set(const stmdev_ctx_t *ctx, 984 uint8_t val); 985 int32_t lsm303agr_xl_block_data_update_get(const stmdev_ctx_t *ctx, 986 uint8_t *val); 987 988 int32_t lsm303agr_xl_filter_reference_set(const stmdev_ctx_t *ctx, 989 uint8_t *buff); 990 int32_t lsm303agr_xl_filter_reference_get(const stmdev_ctx_t *ctx, 991 uint8_t *buff); 992 993 int32_t lsm303agr_xl_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 994 995 int32_t lsm303agr_xl_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); 996 997 int32_t lsm303agr_acceleration_raw_get(const stmdev_ctx_t *ctx, 998 int16_t *val); 999 1000 int32_t lsm303agr_xl_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 1001 1002 typedef enum 1003 { 1004 LSM303AGR_ST_DISABLE = 0, 1005 LSM303AGR_ST_POSITIVE = 1, 1006 LSM303AGR_ST_NEGATIVE = 2, 1007 } lsm303agr_st_a_t; 1008 int32_t lsm303agr_xl_self_test_set(const stmdev_ctx_t *ctx, 1009 lsm303agr_st_a_t val); 1010 int32_t lsm303agr_xl_self_test_get(const stmdev_ctx_t *ctx, 1011 lsm303agr_st_a_t *val); 1012 1013 typedef enum 1014 { 1015 LSM303AGR_XL_LSB_AT_LOW_ADD = 0, 1016 LSM303AGR_XL_MSB_AT_LOW_ADD = 1, 1017 } lsm303agr_ble_a_t; 1018 int32_t lsm303agr_xl_data_format_set(const stmdev_ctx_t *ctx, 1019 lsm303agr_ble_a_t val); 1020 int32_t lsm303agr_xl_data_format_get(const stmdev_ctx_t *ctx, 1021 lsm303agr_ble_a_t *val); 1022 1023 int32_t lsm303agr_xl_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 1024 int32_t lsm303agr_xl_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 1025 1026 int32_t lsm303agr_xl_status_get(const stmdev_ctx_t *ctx, 1027 lsm303agr_status_reg_a_t *val); 1028 1029 int32_t lsm303agr_xl_int1_gen_conf_set(const stmdev_ctx_t *ctx, 1030 lsm303agr_int1_cfg_a_t *val); 1031 int32_t lsm303agr_xl_int1_gen_conf_get(const stmdev_ctx_t *ctx, 1032 lsm303agr_int1_cfg_a_t *val); 1033 1034 int32_t lsm303agr_xl_int1_gen_source_get(const stmdev_ctx_t *ctx, 1035 lsm303agr_int1_src_a_t *val); 1036 1037 int32_t lsm303agr_xl_int1_gen_threshold_set(const stmdev_ctx_t *ctx, 1038 uint8_t val); 1039 int32_t lsm303agr_xl_int1_gen_threshold_get(const stmdev_ctx_t *ctx, 1040 uint8_t *val); 1041 1042 int32_t lsm303agr_xl_int1_gen_duration_set(const stmdev_ctx_t *ctx, 1043 uint8_t val); 1044 int32_t lsm303agr_xl_int1_gen_duration_get(const stmdev_ctx_t *ctx, 1045 uint8_t *val); 1046 1047 int32_t lsm303agr_xl_int2_gen_conf_set(const stmdev_ctx_t *ctx, 1048 lsm303agr_int2_cfg_a_t *val); 1049 int32_t lsm303agr_xl_int2_gen_conf_get(const stmdev_ctx_t *ctx, 1050 lsm303agr_int2_cfg_a_t *val); 1051 1052 int32_t lsm303agr_xl_int2_gen_source_get(const stmdev_ctx_t *ctx, 1053 lsm303agr_int2_src_a_t *val); 1054 1055 int32_t lsm303agr_xl_int2_gen_threshold_set(const stmdev_ctx_t *ctx, 1056 uint8_t val); 1057 int32_t lsm303agr_xl_int2_gen_threshold_get(const stmdev_ctx_t *ctx, 1058 uint8_t *val); 1059 1060 int32_t lsm303agr_xl_int2_gen_duration_set(const stmdev_ctx_t *ctx, 1061 uint8_t val); 1062 int32_t lsm303agr_xl_int2_gen_duration_get(const stmdev_ctx_t *ctx, 1063 uint8_t *val); 1064 1065 typedef enum 1066 { 1067 LSM303AGR_DISC_FROM_INT_GENERATOR = 0, 1068 LSM303AGR_ON_INT1_GEN = 1, 1069 LSM303AGR_ON_INT2_GEN = 2, 1070 LSM303AGR_ON_TAP_GEN = 4, 1071 LSM303AGR_ON_INT1_INT2_GEN = 3, 1072 LSM303AGR_ON_INT1_TAP_GEN = 5, 1073 LSM303AGR_ON_INT2_TAP_GEN = 6, 1074 LSM303AGR_ON_INT1_INT2_TAP_GEN = 7, 1075 } lsm303agr_hp_a_t; 1076 int32_t lsm303agr_xl_high_pass_int_conf_set(const stmdev_ctx_t *ctx, 1077 lsm303agr_hp_a_t val); 1078 int32_t lsm303agr_xl_high_pass_int_conf_get(const stmdev_ctx_t *ctx, 1079 lsm303agr_hp_a_t *val); 1080 1081 int32_t lsm303agr_xl_pin_int1_config_set(const stmdev_ctx_t *ctx, 1082 lsm303agr_ctrl_reg3_a_t *val); 1083 int32_t lsm303agr_xl_pin_int1_config_get(const stmdev_ctx_t *ctx, 1084 lsm303agr_ctrl_reg3_a_t *val); 1085 1086 int32_t lsm303agr_xl_int2_pin_detect_4d_set(const stmdev_ctx_t *ctx, 1087 uint8_t val); 1088 int32_t lsm303agr_xl_int2_pin_detect_4d_get(const stmdev_ctx_t *ctx, 1089 uint8_t *val); 1090 1091 typedef enum 1092 { 1093 LSM303AGR_INT2_PULSED = 0, 1094 LSM303AGR_INT2_LATCHED = 1, 1095 } lsm303agr_lir_int2_a_t; 1096 int32_t lsm303agr_xl_int2pin_notification_mode_set(const stmdev_ctx_t *ctx, 1097 lsm303agr_lir_int2_a_t val); 1098 int32_t lsm303agr_xl_int2pin_notification_mode_get(const stmdev_ctx_t *ctx, 1099 lsm303agr_lir_int2_a_t *val); 1100 1101 int32_t lsm303agr_xl_int1_pin_detect_4d_set(const stmdev_ctx_t *ctx, 1102 uint8_t val); 1103 int32_t lsm303agr_xl_int1_pin_detect_4d_get(const stmdev_ctx_t *ctx, 1104 uint8_t *val); 1105 1106 typedef enum 1107 { 1108 LSM303AGR_INT1_PULSED = 0, 1109 LSM303AGR_INT1_LATCHED = 1, 1110 } lsm303agr_lir_int1_a_t; 1111 int32_t lsm303agr_xl_int1pin_notification_mode_set(const stmdev_ctx_t *ctx, 1112 lsm303agr_lir_int1_a_t val); 1113 int32_t lsm303agr_xl_int1pin_notification_mode_get(const stmdev_ctx_t *ctx, 1114 lsm303agr_lir_int1_a_t *val); 1115 1116 int32_t lsm303agr_xl_pin_int2_config_set(const stmdev_ctx_t *ctx, 1117 lsm303agr_ctrl_reg6_a_t *val); 1118 int32_t lsm303agr_xl_pin_int2_config_get(const stmdev_ctx_t *ctx, 1119 lsm303agr_ctrl_reg6_a_t *val); 1120 1121 int32_t lsm303agr_xl_fifo_set(const stmdev_ctx_t *ctx, uint8_t val); 1122 int32_t lsm303agr_xl_fifo_get(const stmdev_ctx_t *ctx, uint8_t *val); 1123 1124 int32_t lsm303agr_xl_fifo_watermark_set(const stmdev_ctx_t *ctx, 1125 uint8_t val); 1126 int32_t lsm303agr_xl_fifo_watermark_get(const stmdev_ctx_t *ctx, 1127 uint8_t *val); 1128 1129 typedef enum 1130 { 1131 LSM303AGR_INT1_GEN = 0, 1132 LSM303AGR_INT2_GEN = 1, 1133 } lsm303agr_tr_a_t; 1134 int32_t lsm303agr_xl_fifo_trigger_event_set(const stmdev_ctx_t *ctx, 1135 lsm303agr_tr_a_t val); 1136 int32_t lsm303agr_xl_fifo_trigger_event_get(const stmdev_ctx_t *ctx, 1137 lsm303agr_tr_a_t *val); 1138 1139 typedef enum 1140 { 1141 LSM303AGR_BYPASS_MODE = 0, 1142 LSM303AGR_FIFO_MODE = 1, 1143 LSM303AGR_DYNAMIC_STREAM_MODE = 2, 1144 LSM303AGR_STREAM_TO_FIFO_MODE = 3, 1145 } lsm303agr_fm_a_t; 1146 int32_t lsm303agr_xl_fifo_mode_set(const stmdev_ctx_t *ctx, 1147 lsm303agr_fm_a_t val); 1148 int32_t lsm303agr_xl_fifo_mode_get(const stmdev_ctx_t *ctx, 1149 lsm303agr_fm_a_t *val); 1150 1151 int32_t lsm303agr_xl_fifo_status_get(const stmdev_ctx_t *ctx, 1152 lsm303agr_fifo_src_reg_a_t *val); 1153 1154 int32_t lsm303agr_xl_fifo_data_level_get(const stmdev_ctx_t *ctx, 1155 uint8_t *val); 1156 1157 int32_t lsm303agr_xl_fifo_empty_flag_get(const stmdev_ctx_t *ctx, 1158 uint8_t *val); 1159 1160 int32_t lsm303agr_xl_fifo_ovr_flag_get(const stmdev_ctx_t *ctx, 1161 uint8_t *val); 1162 1163 int32_t lsm303agr_xl_fifo_fth_flag_get(const stmdev_ctx_t *ctx, 1164 uint8_t *val); 1165 1166 int32_t lsm303agr_tap_conf_set(const stmdev_ctx_t *ctx, 1167 lsm303agr_click_cfg_a_t *val); 1168 int32_t lsm303agr_tap_conf_get(const stmdev_ctx_t *ctx, 1169 lsm303agr_click_cfg_a_t *val); 1170 1171 int32_t lsm303agr_tap_source_get(const stmdev_ctx_t *ctx, 1172 lsm303agr_click_src_a_t *val); 1173 1174 int32_t lsm303agr_tap_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 1175 int32_t lsm303agr_tap_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 1176 1177 int32_t lsm303agr_shock_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1178 int32_t lsm303agr_shock_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1179 1180 int32_t lsm303agr_quiet_dur_set(const stmdev_ctx_t *ctx, uint8_t val); 1181 int32_t lsm303agr_quiet_dur_get(const stmdev_ctx_t *ctx, uint8_t *val); 1182 1183 int32_t lsm303agr_double_tap_timeout_set(const stmdev_ctx_t *ctx, 1184 uint8_t val); 1185 int32_t lsm303agr_double_tap_timeout_get(const stmdev_ctx_t *ctx, 1186 uint8_t *val); 1187 1188 int32_t lsm303agr_act_threshold_set(const stmdev_ctx_t *ctx, uint8_t val); 1189 int32_t lsm303agr_act_threshold_get(const stmdev_ctx_t *ctx, uint8_t *val); 1190 1191 int32_t lsm303agr_act_timeout_set(const stmdev_ctx_t *ctx, uint8_t val); 1192 int32_t lsm303agr_act_timeout_get(const stmdev_ctx_t *ctx, uint8_t *val); 1193 1194 typedef enum 1195 { 1196 LSM303AGR_SPI_4_WIRE = 0, 1197 LSM303AGR_SPI_3_WIRE = 1, 1198 } lsm303agr_sim_a_t; 1199 int32_t lsm303agr_xl_spi_mode_set(const stmdev_ctx_t *ctx, 1200 lsm303agr_sim_a_t val); 1201 int32_t lsm303agr_xl_spi_mode_get(const stmdev_ctx_t *ctx, 1202 lsm303agr_sim_a_t *val); 1203 1204 int32_t lsm303agr_mag_user_offset_set(const stmdev_ctx_t *ctx, 1205 int16_t *val); 1206 int32_t lsm303agr_mag_user_offset_get(const stmdev_ctx_t *ctx, 1207 int16_t *val); 1208 1209 typedef enum 1210 { 1211 LSM303AGR_CONTINUOUS_MODE = 0, 1212 LSM303AGR_SINGLE_TRIGGER = 1, 1213 LSM303AGR_POWER_DOWN = 2, 1214 } lsm303agr_md_m_t; 1215 int32_t lsm303agr_mag_operating_mode_set(const stmdev_ctx_t *ctx, 1216 lsm303agr_md_m_t val); 1217 int32_t lsm303agr_mag_operating_mode_get(const stmdev_ctx_t *ctx, 1218 lsm303agr_md_m_t *val); 1219 1220 typedef enum 1221 { 1222 LSM303AGR_MG_ODR_10Hz = 0, 1223 LSM303AGR_MG_ODR_20Hz = 1, 1224 LSM303AGR_MG_ODR_50Hz = 2, 1225 LSM303AGR_MG_ODR_100Hz = 3, 1226 } lsm303agr_mg_odr_m_t; 1227 int32_t lsm303agr_mag_data_rate_set(const stmdev_ctx_t *ctx, 1228 lsm303agr_mg_odr_m_t val); 1229 int32_t lsm303agr_mag_data_rate_get(const stmdev_ctx_t *ctx, 1230 lsm303agr_mg_odr_m_t *val); 1231 1232 typedef enum 1233 { 1234 LSM303AGR_HIGH_RESOLUTION = 0, 1235 LSM303AGR_LOW_POWER = 1, 1236 } lsm303agr_lp_m_t; 1237 int32_t lsm303agr_mag_power_mode_set(const stmdev_ctx_t *ctx, 1238 lsm303agr_lp_m_t val); 1239 int32_t lsm303agr_mag_power_mode_get(const stmdev_ctx_t *ctx, 1240 lsm303agr_lp_m_t *val); 1241 1242 int32_t lsm303agr_mag_offset_temp_comp_set(const stmdev_ctx_t *ctx, 1243 uint8_t val); 1244 int32_t lsm303agr_mag_offset_temp_comp_get(const stmdev_ctx_t *ctx, 1245 uint8_t *val); 1246 1247 typedef enum 1248 { 1249 LSM303AGR_ODR_DIV_2 = 0, 1250 LSM303AGR_ODR_DIV_4 = 1, 1251 } lsm303agr_lpf_m_t; 1252 int32_t lsm303agr_mag_low_pass_bandwidth_set(const stmdev_ctx_t *ctx, 1253 lsm303agr_lpf_m_t val); 1254 int32_t lsm303agr_mag_low_pass_bandwidth_get(const stmdev_ctx_t *ctx, 1255 lsm303agr_lpf_m_t *val); 1256 1257 typedef enum 1258 { 1259 LSM303AGR_SET_SENS_ODR_DIV_63 = 0, 1260 LSM303AGR_SENS_OFF_CANC_EVERY_ODR = 1, 1261 LSM303AGR_SET_SENS_ONLY_AT_POWER_ON = 2, 1262 } lsm303agr_set_rst_m_t; 1263 int32_t lsm303agr_mag_set_rst_mode_set(const stmdev_ctx_t *ctx, 1264 lsm303agr_set_rst_m_t val); 1265 int32_t lsm303agr_mag_set_rst_mode_get(const stmdev_ctx_t *ctx, 1266 lsm303agr_set_rst_m_t *val); 1267 1268 int32_t lsm303agr_mag_set_rst_sensor_single_set(const stmdev_ctx_t *ctx, 1269 uint8_t val); 1270 int32_t lsm303agr_mag_set_rst_sensor_single_get(const stmdev_ctx_t *ctx, 1271 uint8_t *val); 1272 1273 int32_t lsm303agr_mag_block_data_update_set(const stmdev_ctx_t *ctx, 1274 uint8_t val); 1275 int32_t lsm303agr_mag_block_data_update_get(const stmdev_ctx_t *ctx, 1276 uint8_t *val); 1277 1278 int32_t lsm303agr_mag_data_ready_get(const stmdev_ctx_t *ctx, uint8_t *val); 1279 1280 int32_t lsm303agr_mag_data_ovr_get(const stmdev_ctx_t *ctx, uint8_t *val); 1281 1282 int32_t lsm303agr_magnetic_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 1283 1284 int32_t lsm303agr_mag_device_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 1285 1286 int32_t lsm303agr_mag_reset_set(const stmdev_ctx_t *ctx, uint8_t val); 1287 int32_t lsm303agr_mag_reset_get(const stmdev_ctx_t *ctx, uint8_t *val); 1288 1289 int32_t lsm303agr_mag_boot_set(const stmdev_ctx_t *ctx, uint8_t val); 1290 int32_t lsm303agr_mag_boot_get(const stmdev_ctx_t *ctx, uint8_t *val); 1291 1292 int32_t lsm303agr_mag_self_test_set(const stmdev_ctx_t *ctx, 1293 uint8_t val); 1294 int32_t lsm303agr_mag_self_test_get(const stmdev_ctx_t *ctx, 1295 uint8_t *val); 1296 1297 typedef enum 1298 { 1299 LSM303AGR_MG_LSB_AT_LOW_ADD = 0, 1300 LSM303AGR_MG_MSB_AT_LOW_ADD = 1, 1301 } lsm303agr_ble_m_t; 1302 int32_t lsm303agr_mag_data_format_set(const stmdev_ctx_t *ctx, 1303 lsm303agr_ble_m_t val); 1304 int32_t lsm303agr_mag_data_format_get(const stmdev_ctx_t *ctx, 1305 lsm303agr_ble_m_t *val); 1306 1307 int32_t lsm303agr_mag_status_get(const stmdev_ctx_t *ctx, 1308 lsm303agr_status_reg_m_t *val); 1309 1310 typedef enum 1311 { 1312 LSM303AGR_CHECK_BEFORE = 0, 1313 LSM303AGR_CHECK_AFTER = 1, 1314 } lsm303agr_int_on_dataoff_m_t; 1315 int32_t lsm303agr_mag_offset_int_conf_set(const stmdev_ctx_t *ctx, 1316 lsm303agr_int_on_dataoff_m_t val); 1317 int32_t lsm303agr_mag_offset_int_conf_get(const stmdev_ctx_t *ctx, 1318 lsm303agr_int_on_dataoff_m_t *val); 1319 1320 int32_t lsm303agr_mag_drdy_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val); 1321 int32_t lsm303agr_mag_drdy_on_pin_get(const stmdev_ctx_t *ctx, 1322 uint8_t *val); 1323 1324 int32_t lsm303agr_mag_int_on_pin_set(const stmdev_ctx_t *ctx, uint8_t val); 1325 int32_t lsm303agr_mag_int_on_pin_get(const stmdev_ctx_t *ctx, uint8_t *val); 1326 1327 int32_t lsm303agr_mag_int_gen_conf_set(const stmdev_ctx_t *ctx, 1328 lsm303agr_int_crtl_reg_m_t *val); 1329 int32_t lsm303agr_mag_int_gen_conf_get(const stmdev_ctx_t *ctx, 1330 lsm303agr_int_crtl_reg_m_t *val); 1331 1332 int32_t lsm303agr_mag_int_gen_source_get(const stmdev_ctx_t *ctx, 1333 lsm303agr_int_source_reg_m_t *val); 1334 1335 int32_t lsm303agr_mag_int_gen_threshold_set(const stmdev_ctx_t *ctx, 1336 int16_t val); 1337 int32_t lsm303agr_mag_int_gen_threshold_get(const stmdev_ctx_t *ctx, 1338 int16_t *val); 1339 1340 typedef enum 1341 { 1342 LSM303AGR_I2C_ENABLE = 0, 1343 LSM303AGR_I2C_DISABLE = 1, 1344 } lsm303agr_i2c_dis_m_t; 1345 int32_t lsm303agr_mag_i2c_interface_set(const stmdev_ctx_t *ctx, 1346 lsm303agr_i2c_dis_m_t val); 1347 int32_t lsm303agr_mag_i2c_interface_get(const stmdev_ctx_t *ctx, 1348 lsm303agr_i2c_dis_m_t *val); 1349 1350 /** 1351 * @} 1352 * 1353 */ 1354 1355 #ifdef __cplusplus 1356 } 1357 #endif 1358 1359 #endif /* LSM303AGR_REGS_H */ 1360 1361 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1362
