1 /** 2 * @file pwrseq_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup pwrseq_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_PWRSEQ_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_PWRSEQ_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup pwrseq 67 * @defgroup pwrseq_registers PWRSEQ_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 69 * @details Power Sequencer / Low Power Control Register. 70 */ 71 72 /** 73 * @ingroup pwrseq_registers 74 * Structure type to access the PWRSEQ Registers. 75 */ 76 typedef struct { 77 __IO uint32_t lpcn; /**< <tt>\b 0x00:</tt> PWRSEQ LPCN Register */ 78 __IO uint32_t lpwkst0; /**< <tt>\b 0x04:</tt> PWRSEQ LPWKST0 Register */ 79 __IO uint32_t lpwken0; /**< <tt>\b 0x08:</tt> PWRSEQ LPWKEN0 Register */ 80 __IO uint32_t lpwkst1; /**< <tt>\b 0x0C:</tt> PWRSEQ LPWKST1 Register */ 81 __IO uint32_t lpwken1; /**< <tt>\b 0x10:</tt> PWRSEQ LPWKEN1 Register */ 82 __IO uint32_t lpwkst2; /**< <tt>\b 0x14:</tt> PWRSEQ LPWKST2 Register */ 83 __IO uint32_t lpwken2; /**< <tt>\b 0x18:</tt> PWRSEQ LPWKEN2 Register */ 84 __IO uint32_t lpwkst3; /**< <tt>\b 0x1C:</tt> PWRSEQ LPWKST3 Register */ 85 __IO uint32_t lpwken3; /**< <tt>\b 0x20:</tt> PWRSEQ LPWKEN3 Register */ 86 __IO uint32_t lpwkst4; /**< <tt>\b 0x24:</tt> PWRSEQ LPWKST4 Register */ 87 __IO uint32_t lpwken4; /**< <tt>\b 0x28:</tt> PWRSEQ LPWKEN4 Register */ 88 __R uint32_t rsv_0x2c; 89 __IO uint32_t lppwst; /**< <tt>\b 0x30:</tt> PWRSEQ LPPWST Register */ 90 __IO uint32_t lppwen; /**< <tt>\b 0x34:</tt> PWRSEQ LPPWEN Register */ 91 __R uint32_t rsv_0x38_0x47[4]; 92 __IO uint32_t gp0; /**< <tt>\b 0x48:</tt> PWRSEQ GP0 Register */ 93 __IO uint32_t gp1; /**< <tt>\b 0x4C:</tt> PWRSEQ GP1 Register */ 94 } mxc_pwrseq_regs_t; 95 96 /* Register offsets for module PWRSEQ */ 97 /** 98 * @ingroup pwrseq_registers 99 * @defgroup PWRSEQ_Register_Offsets Register Offsets 100 * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. 101 * @{ 102 */ 103 #define MXC_R_PWRSEQ_LPCN ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0000</tt> */ 104 #define MXC_R_PWRSEQ_LPWKST0 ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0004</tt> */ 105 #define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */ 106 #define MXC_R_PWRSEQ_LPWKST1 ((uint32_t)0x0000000CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x000C</tt> */ 107 #define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0010</tt> */ 108 #define MXC_R_PWRSEQ_LPWKST2 ((uint32_t)0x00000014UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0014</tt> */ 109 #define MXC_R_PWRSEQ_LPWKEN2 ((uint32_t)0x00000018UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0018</tt> */ 110 #define MXC_R_PWRSEQ_LPWKST3 ((uint32_t)0x0000001CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x001C</tt> */ 111 #define MXC_R_PWRSEQ_LPWKEN3 ((uint32_t)0x00000020UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0020</tt> */ 112 #define MXC_R_PWRSEQ_LPWKST4 ((uint32_t)0x00000024UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0024</tt> */ 113 #define MXC_R_PWRSEQ_LPWKEN4 ((uint32_t)0x00000028UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0028</tt> */ 114 #define MXC_R_PWRSEQ_LPPWST ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0030</tt> */ 115 #define MXC_R_PWRSEQ_LPPWEN ((uint32_t)0x00000034UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0034</tt> */ 116 #define MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0048</tt> */ 117 #define MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x004C</tt> */ 118 /**@} end of group pwrseq_registers */ 119 120 /** 121 * @ingroup pwrseq_registers 122 * @defgroup PWRSEQ_LPCN PWRSEQ_LPCN 123 * @brief Low Power Control Register. 124 * @{ 125 */ 126 #define MXC_F_PWRSEQ_LPCN_RAMRET0_POS 0 /**< LPCN_RAMRET0 Position */ 127 #define MXC_F_PWRSEQ_LPCN_RAMRET0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET0_POS)) /**< LPCN_RAMRET0 Mask */ 128 129 #define MXC_F_PWRSEQ_LPCN_RAMRET1_POS 1 /**< LPCN_RAMRET1 Position */ 130 #define MXC_F_PWRSEQ_LPCN_RAMRET1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET1_POS)) /**< LPCN_RAMRET1 Mask */ 131 132 #define MXC_F_PWRSEQ_LPCN_RAMRET2_POS 2 /**< LPCN_RAMRET2 Position */ 133 #define MXC_F_PWRSEQ_LPCN_RAMRET2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET2_POS)) /**< LPCN_RAMRET2 Mask */ 134 135 #define MXC_F_PWRSEQ_LPCN_RAMRET3_POS 3 /**< LPCN_RAMRET3 Position */ 136 #define MXC_F_PWRSEQ_LPCN_RAMRET3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET3_POS)) /**< LPCN_RAMRET3 Mask */ 137 138 #define MXC_F_PWRSEQ_LPCN_RAMRET4_POS 4 /**< LPCN_RAMRET4 Position */ 139 #define MXC_F_PWRSEQ_LPCN_RAMRET4 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET4_POS)) /**< LPCN_RAMRET4 Mask */ 140 141 #define MXC_F_PWRSEQ_LPCN_RAMRET5_POS 5 /**< LPCN_RAMRET5 Position */ 142 #define MXC_F_PWRSEQ_LPCN_RAMRET5 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET5_POS)) /**< LPCN_RAMRET5 Mask */ 143 144 #define MXC_F_PWRSEQ_LPCN_RAMRET6_POS 6 /**< LPCN_RAMRET6 Position */ 145 #define MXC_F_PWRSEQ_LPCN_RAMRET6 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET6_POS)) /**< LPCN_RAMRET6 Mask */ 146 147 #define MXC_F_PWRSEQ_LPCN_RAMRET8_POS 7 /**< LPCN_RAMRET8 Position */ 148 #define MXC_F_PWRSEQ_LPCN_RAMRET8 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAMRET8_POS)) /**< LPCN_RAMRET8 Mask */ 149 150 #define MXC_F_PWRSEQ_LPCN_ISOCLK_SELECT_POS 8 /**< LPCN_ISOCLK_SELECT Position */ 151 #define MXC_F_PWRSEQ_LPCN_ISOCLK_SELECT ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_ISOCLK_SELECT_POS)) /**< LPCN_ISOCLK_SELECT Mask */ 152 153 #define MXC_F_PWRSEQ_LPCN_FAST_ENTRY_DIS_POS 9 /**< LPCN_FAST_ENTRY_DIS Position */ 154 #define MXC_F_PWRSEQ_LPCN_FAST_ENTRY_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FAST_ENTRY_DIS_POS)) /**< LPCN_FAST_ENTRY_DIS Mask */ 155 156 #define MXC_F_PWRSEQ_LPCN_BGOFF_POS 11 /**< LPCN_BGOFF Position */ 157 #define MXC_F_PWRSEQ_LPCN_BGOFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BGOFF_POS)) /**< LPCN_BGOFF Mask */ 158 159 #define MXC_F_PWRSEQ_LPCN_WKRST_POS 31 /**< LPCN_WKRST Position */ 160 #define MXC_F_PWRSEQ_LPCN_WKRST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_WKRST_POS)) /**< LPCN_WKRST Mask */ 161 162 /**@} end of group PWRSEQ_LPCN_Register */ 163 164 /** 165 * @ingroup pwrseq_registers 166 * @defgroup PWRSEQ_LPWKST0 PWRSEQ_LPWKST0 167 * @brief Low Power I/O Wakeup Status Register 0. This register indicates the low power 168 * wakeup status for GPIO0. 169 * @{ 170 */ 171 #define MXC_F_PWRSEQ_LPWKST0_WAKEST_POS 0 /**< LPWKST0_WAKEST Position */ 172 #define MXC_F_PWRSEQ_LPWKST0_WAKEST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPWKST0_WAKEST_POS)) /**< LPWKST0_WAKEST Mask */ 173 174 /**@} end of group PWRSEQ_LPWKST0_Register */ 175 176 /** 177 * @ingroup pwrseq_registers 178 * @defgroup PWRSEQ_LPWKEN0 PWRSEQ_LPWKEN0 179 * @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup 180 * functionality for GPIO0. 181 * @{ 182 */ 183 #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS 0 /**< LPWKEN0_WAKEEN Position */ 184 #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS)) /**< LPWKEN0_WAKEEN Mask */ 185 186 /**@} end of group PWRSEQ_LPWKEN0_Register */ 187 188 /** 189 * @ingroup pwrseq_registers 190 * @defgroup PWRSEQ_LPWKST1 PWRSEQ_LPWKST1 191 * @brief Low Power I/O Wakeup Status Register 1. This register indicates the low power 192 * wakeup status for GPIO1. 193 * @{ 194 */ 195 #define MXC_F_PWRSEQ_LPWKST1_WAKEST_POS 0 /**< LPWKST1_WAKEST Position */ 196 #define MXC_F_PWRSEQ_LPWKST1_WAKEST ((uint32_t)(0x3FFUL << MXC_F_PWRSEQ_LPWKST1_WAKEST_POS)) /**< LPWKST1_WAKEST Mask */ 197 198 /**@} end of group PWRSEQ_LPWKST1_Register */ 199 200 /** 201 * @ingroup pwrseq_registers 202 * @defgroup PWRSEQ_LPWKEN1 PWRSEQ_LPWKEN1 203 * @brief Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup 204 * functionality for GPIO1. 205 * @{ 206 */ 207 #define MXC_F_PWRSEQ_LPWKEN1_WAKEEN_POS 0 /**< LPWKEN1_WAKEEN Position */ 208 #define MXC_F_PWRSEQ_LPWKEN1_WAKEEN ((uint32_t)(0x3FFUL << MXC_F_PWRSEQ_LPWKEN1_WAKEEN_POS)) /**< LPWKEN1_WAKEEN Mask */ 209 210 /**@} end of group PWRSEQ_LPWKEN1_Register */ 211 212 /** 213 * @ingroup pwrseq_registers 214 * @defgroup PWRSEQ_LPWKST2 PWRSEQ_LPWKST2 215 * @brief Low Power I/O Wakeup Status Register 2. This register indicates the low power 216 * wakeup status for GPIO2. 217 * @{ 218 */ 219 #define MXC_F_PWRSEQ_LPWKST2_WAKEST_POS 0 /**< LPWKST2_WAKEST Position */ 220 #define MXC_F_PWRSEQ_LPWKST2_WAKEST ((uint32_t)(0xFFUL << MXC_F_PWRSEQ_LPWKST2_WAKEST_POS)) /**< LPWKST2_WAKEST Mask */ 221 222 /**@} end of group PWRSEQ_LPWKST2_Register */ 223 224 /** 225 * @ingroup pwrseq_registers 226 * @defgroup PWRSEQ_LPWKEN2 PWRSEQ_LPWKEN2 227 * @brief Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup 228 * functionality for GPIO2. 229 * @{ 230 */ 231 #define MXC_F_PWRSEQ_LPWKEN2_WAKEEN_POS 0 /**< LPWKEN2_WAKEEN Position */ 232 #define MXC_F_PWRSEQ_LPWKEN2_WAKEEN ((uint32_t)(0xFFUL << MXC_F_PWRSEQ_LPWKEN2_WAKEEN_POS)) /**< LPWKEN2_WAKEEN Mask */ 233 234 /**@} end of group PWRSEQ_LPWKEN2_Register */ 235 236 /** 237 * @ingroup pwrseq_registers 238 * @defgroup PWRSEQ_LPWKST3 PWRSEQ_LPWKST3 239 * @brief Low Power I/O Wakeup Status Register 3. This register indicates the low power 240 * wakeup status for GPIO3. 241 * @{ 242 */ 243 #define MXC_F_PWRSEQ_LPWKST3_WAKEST_POS 0 /**< LPWKST3_WAKEST Position */ 244 #define MXC_F_PWRSEQ_LPWKST3_WAKEST ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKST3_WAKEST_POS)) /**< LPWKST3_WAKEST Mask */ 245 246 /**@} end of group PWRSEQ_LPWKST3_Register */ 247 248 /** 249 * @ingroup pwrseq_registers 250 * @defgroup PWRSEQ_LPWKEN3 PWRSEQ_LPWKEN3 251 * @brief Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup 252 * functionality for GPIO3. 253 * @{ 254 */ 255 #define MXC_F_PWRSEQ_LPWKEN3_WAKEEN_POS 0 /**< LPWKEN3_WAKEEN Position */ 256 #define MXC_F_PWRSEQ_LPWKEN3_WAKEEN ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKEN3_WAKEEN_POS)) /**< LPWKEN3_WAKEEN Mask */ 257 258 /**@} end of group PWRSEQ_LPWKEN3_Register */ 259 260 /** 261 * @ingroup pwrseq_registers 262 * @defgroup PWRSEQ_LPWKST4 PWRSEQ_LPWKST4 263 * @brief Low Power I/O Wakeup Status Register 4. This register indicates the low power 264 * wakeup status for GPIO4. 265 * @{ 266 */ 267 #define MXC_F_PWRSEQ_LPWKST4_WAKEST_POS 0 /**< LPWKST4_WAKEST Position */ 268 #define MXC_F_PWRSEQ_LPWKST4_WAKEST ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKST4_WAKEST_POS)) /**< LPWKST4_WAKEST Mask */ 269 270 /**@} end of group PWRSEQ_LPWKST4_Register */ 271 272 /** 273 * @ingroup pwrseq_registers 274 * @defgroup PWRSEQ_LPWKEN4 PWRSEQ_LPWKEN4 275 * @brief Low Power I/O Wakeup Enable Register 4. This register enables low power wakeup 276 * functionality for GPIO4. 277 * @{ 278 */ 279 #define MXC_F_PWRSEQ_LPWKEN4_WAKEEN_POS 0 /**< LPWKEN4_WAKEEN Position */ 280 #define MXC_F_PWRSEQ_LPWKEN4_WAKEEN ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKEN4_WAKEEN_POS)) /**< LPWKEN4_WAKEEN Mask */ 281 282 /**@} end of group PWRSEQ_LPWKEN4_Register */ 283 284 /** 285 * @ingroup pwrseq_registers 286 * @defgroup PWRSEQ_LPPWST PWRSEQ_LPPWST 287 * @brief Low Power Peripheral Wakeup Status Register. 288 * @{ 289 */ 290 #define MXC_F_PWRSEQ_LPPWST_AINCOMP0_POS 4 /**< LPPWST_AINCOMP0 Position */ 291 #define MXC_F_PWRSEQ_LPPWST_AINCOMP0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP0_POS)) /**< LPPWST_AINCOMP0 Mask */ 292 293 #define MXC_F_PWRSEQ_LPPWST_BACKUP_POS 16 /**< LPPWST_BACKUP Position */ 294 #define MXC_F_PWRSEQ_LPPWST_BACKUP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_BACKUP_POS)) /**< LPPWST_BACKUP Mask */ 295 296 #define MXC_F_PWRSEQ_LPPWST_RESET_POS 17 /**< LPPWST_RESET Position */ 297 #define MXC_F_PWRSEQ_LPPWST_RESET ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_RESET_POS)) /**< LPPWST_RESET Mask */ 298 299 /**@} end of group PWRSEQ_LPPWST_Register */ 300 301 /** 302 * @ingroup pwrseq_registers 303 * @defgroup PWRSEQ_LPPWEN PWRSEQ_LPPWEN 304 * @brief Low Power Peripheral Wakeup Enable Register. 305 * @{ 306 */ 307 #define MXC_F_PWRSEQ_LPPWEN_USBLS_POS 0 /**< LPPWEN_USBLS Position */ 308 #define MXC_F_PWRSEQ_LPPWEN_USBLS ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWEN_USBLS_POS)) /**< LPPWEN_USBLS Mask */ 309 310 #define MXC_F_PWRSEQ_LPPWEN_USBVBUS_POS 2 /**< LPPWEN_USBVBUS Position */ 311 #define MXC_F_PWRSEQ_LPPWEN_USBVBUS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_USBVBUS_POS)) /**< LPPWEN_USBVBUS Mask */ 312 313 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP0_POS 4 /**< LPPWEN_AINCOMP0 Position */ 314 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP0_POS)) /**< LPPWEN_AINCOMP0 Mask */ 315 316 #define MXC_F_PWRSEQ_LPPWEN_WDT0_POS 8 /**< LPPWEN_WDT0 Position */ 317 #define MXC_F_PWRSEQ_LPPWEN_WDT0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_WDT0_POS)) /**< LPPWEN_WDT0 Mask */ 318 319 #define MXC_F_PWRSEQ_LPPWEN_WDT1_POS 9 /**< LPPWEN_WDT1 Position */ 320 #define MXC_F_PWRSEQ_LPPWEN_WDT1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_WDT1_POS)) /**< LPPWEN_WDT1 Mask */ 321 322 #define MXC_F_PWRSEQ_LPPWEN_CPU1_POS 10 /**< LPPWEN_CPU1 Position */ 323 #define MXC_F_PWRSEQ_LPPWEN_CPU1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_CPU1_POS)) /**< LPPWEN_CPU1 Mask */ 324 325 #define MXC_F_PWRSEQ_LPPWEN_TMR0_POS 11 /**< LPPWEN_TMR0 Position */ 326 #define MXC_F_PWRSEQ_LPPWEN_TMR0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR0_POS)) /**< LPPWEN_TMR0 Mask */ 327 328 #define MXC_F_PWRSEQ_LPPWEN_TMR1_POS 12 /**< LPPWEN_TMR1 Position */ 329 #define MXC_F_PWRSEQ_LPPWEN_TMR1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR1_POS)) /**< LPPWEN_TMR1 Mask */ 330 331 #define MXC_F_PWRSEQ_LPPWEN_TMR2_POS 13 /**< LPPWEN_TMR2 Position */ 332 #define MXC_F_PWRSEQ_LPPWEN_TMR2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR2_POS)) /**< LPPWEN_TMR2 Mask */ 333 334 #define MXC_F_PWRSEQ_LPPWEN_TMR3_POS 14 /**< LPPWEN_TMR3 Position */ 335 #define MXC_F_PWRSEQ_LPPWEN_TMR3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR3_POS)) /**< LPPWEN_TMR3 Mask */ 336 337 #define MXC_F_PWRSEQ_LPPWEN_TMR4_POS 15 /**< LPPWEN_TMR4 Position */ 338 #define MXC_F_PWRSEQ_LPPWEN_TMR4 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR4_POS)) /**< LPPWEN_TMR4 Mask */ 339 340 #define MXC_F_PWRSEQ_LPPWEN_TMR5_POS 16 /**< LPPWEN_TMR5 Position */ 341 #define MXC_F_PWRSEQ_LPPWEN_TMR5 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_TMR5_POS)) /**< LPPWEN_TMR5 Mask */ 342 343 #define MXC_F_PWRSEQ_LPPWEN_UART0_POS 17 /**< LPPWEN_UART0 Position */ 344 #define MXC_F_PWRSEQ_LPPWEN_UART0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_UART0_POS)) /**< LPPWEN_UART0 Mask */ 345 346 #define MXC_F_PWRSEQ_LPPWEN_UART1_POS 18 /**< LPPWEN_UART1 Position */ 347 #define MXC_F_PWRSEQ_LPPWEN_UART1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_UART1_POS)) /**< LPPWEN_UART1 Mask */ 348 349 #define MXC_F_PWRSEQ_LPPWEN_UART2_POS 19 /**< LPPWEN_UART2 Position */ 350 #define MXC_F_PWRSEQ_LPPWEN_UART2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_UART2_POS)) /**< LPPWEN_UART2 Mask */ 351 352 #define MXC_F_PWRSEQ_LPPWEN_UART3_POS 20 /**< LPPWEN_UART3 Position */ 353 #define MXC_F_PWRSEQ_LPPWEN_UART3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_UART3_POS)) /**< LPPWEN_UART3 Mask */ 354 355 #define MXC_F_PWRSEQ_LPPWEN_I2C0_POS 21 /**< LPPWEN_I2C0 Position */ 356 #define MXC_F_PWRSEQ_LPPWEN_I2C0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_I2C0_POS)) /**< LPPWEN_I2C0 Mask */ 357 358 #define MXC_F_PWRSEQ_LPPWEN_I2C1_POS 22 /**< LPPWEN_I2C1 Position */ 359 #define MXC_F_PWRSEQ_LPPWEN_I2C1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_I2C1_POS)) /**< LPPWEN_I2C1 Mask */ 360 361 #define MXC_F_PWRSEQ_LPPWEN_I2C2_POS 23 /**< LPPWEN_I2C2 Position */ 362 #define MXC_F_PWRSEQ_LPPWEN_I2C2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_I2C2_POS)) /**< LPPWEN_I2C2 Mask */ 363 364 #define MXC_F_PWRSEQ_LPPWEN_I2S_POS 24 /**< LPPWEN_I2S Position */ 365 #define MXC_F_PWRSEQ_LPPWEN_I2S ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_I2S_POS)) /**< LPPWEN_I2S Mask */ 366 367 #define MXC_F_PWRSEQ_LPPWEN_SPI0_POS 25 /**< LPPWEN_SPI0 Position */ 368 #define MXC_F_PWRSEQ_LPPWEN_SPI0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_SPI0_POS)) /**< LPPWEN_SPI0 Mask */ 369 370 #define MXC_F_PWRSEQ_LPPWEN_LPCMP_POS 26 /**< LPPWEN_LPCMP Position */ 371 #define MXC_F_PWRSEQ_LPPWEN_LPCMP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_LPCMP_POS)) /**< LPPWEN_LPCMP Mask */ 372 373 #define MXC_F_PWRSEQ_LPPWEN_BTLE_POS 27 /**< LPPWEN_BTLE Position */ 374 #define MXC_F_PWRSEQ_LPPWEN_BTLE ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_BTLE_POS)) /**< LPPWEN_BTLE Mask */ 375 376 #define MXC_F_PWRSEQ_LPPWEN_SPI1_POS 28 /**< LPPWEN_SPI1 Position */ 377 #define MXC_F_PWRSEQ_LPPWEN_SPI1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_SPI1_POS)) /**< LPPWEN_SPI1 Mask */ 378 379 #define MXC_F_PWRSEQ_LPPWEN_SPI2_POS 29 /**< LPPWEN_SPI2 Position */ 380 #define MXC_F_PWRSEQ_LPPWEN_SPI2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_SPI2_POS)) /**< LPPWEN_SPI2 Mask */ 381 382 #define MXC_F_PWRSEQ_LPPWEN_CAN0_POS 30 /**< LPPWEN_CAN0 Position */ 383 #define MXC_F_PWRSEQ_LPPWEN_CAN0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_CAN0_POS)) /**< LPPWEN_CAN0 Mask */ 384 385 #define MXC_F_PWRSEQ_LPPWEN_CAN1_POS 31 /**< LPPWEN_CAN1 Position */ 386 #define MXC_F_PWRSEQ_LPPWEN_CAN1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_CAN1_POS)) /**< LPPWEN_CAN1 Mask */ 387 388 /**@} end of group PWRSEQ_LPPWEN_Register */ 389 390 #ifdef __cplusplus 391 } 392 #endif 393 394 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_PWRSEQ_REGS_H_ 395
