1 /*!
2 \file gd32l23x_lpuart.c
3 \brief LPUART driver
4
5 \version 2021-08-04, V1.0.0, firmware for GD32L23x
6 */
7
8 /*
9 Copyright (c) 2021, GigaDevice Semiconductor Inc.
10
11 Redistribution and use in source and binary forms, with or without modification,
12 are permitted provided that the following conditions are met:
13
14 1. Redistributions of source code must retain the above copyright notice, this
15 list of conditions and the following disclaimer.
16 2. Redistributions in binary form must reproduce the above copyright notice,
17 this list of conditions and the following disclaimer in the documentation
18 and/or other materials provided with the distribution.
19 3. Neither the name of the copyright holder nor the names of its contributors
20 may be used to endorse or promote products derived from this software without
21 specific prior written permission.
22
23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
32 OF SUCH DAMAGE.
33 */
34
35 #include "gd32l23x_lpuart.h"
36
37 /*!
38 \brief reset LPUART
39 \param[in] none
40 \param[out] none
41 \retval none
42 */
lpuart_deinit(void)43 void lpuart_deinit(void)
44 {
45 rcu_periph_reset_enable(RCU_LPUARTRST);
46 rcu_periph_reset_disable(RCU_LPUARTRST);
47 }
48
49 /*!
50 \brief configure LPUART baud rate value
51 \param[in] baudval: baud rate value
52 \param[out] none
53 \retval none
54 */
lpuart_baudrate_set(uint32_t baudval)55 void lpuart_baudrate_set(uint32_t baudval)
56 {
57 uint32_t lpuclk = 0U, lpudiv = 0U;
58 lpuclk = rcu_clock_freq_get(CK_LPUART);
59
60 lpudiv = (lpuclk / 100U * 256U + baudval / 200U) / (baudval / 100U);
61
62 LPUART_BAUD = (LPUART_BAUD_BRR & lpudiv);
63 }
64
65 /*!
66 \brief configure LPUART parity
67 \param[in] paritycfg: LPUART parity configure
68 only one parameter can be selected which is shown as below:
69 \arg LPUART_PM_NONE: no parity
70 \arg LPUART_PM_ODD: odd parity
71 \arg LPUART_PM_EVEN: even parity
72 \param[out] none
73 \retval none
74 */
lpuart_parity_config(uint32_t paritycfg)75 void lpuart_parity_config(uint32_t paritycfg)
76 {
77 /* disable LPUART */
78 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
79 /* clear LPUART_CTL0 PM,PCEN bits */
80 LPUART_CTL0 &= ~(LPUART_CTL0_PM | LPUART_CTL0_PCEN);
81 /* configure LPUART parity mode */
82 LPUART_CTL0 |= paritycfg;
83 }
84
85 /*!
86 \brief configure LPUART word length
87 \param[in] wlen: LPUART word length configure
88 only one parameter can be selected which is shown as below:
89 \arg LPUART_WL_7BIT: 7 bits
90 \arg LPUART_WL_8BIT: 8 bits
91 \arg LPUART_WL_9BIT: 9 bits
92 \param[out] none
93 \retval none
94 */
lpuart_word_length_set(uint32_t wlen)95 void lpuart_word_length_set(uint32_t wlen)
96 {
97 /* disable LPUART */
98 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
99 /* clear LPUART_CTL0 WL bit */
100 LPUART_CTL0 &= ~(LPUART_CTL0_WL0 | LPUART_CTL0_WL1);
101 /* configure LPUART word length */
102 LPUART_CTL0 |= wlen;
103 }
104
105 /*!
106 \brief configure LPUART stop bit length
107 \param[in] stblen: LPUART stop bit configure
108 only one parameter can be selected which is shown as below:
109 \arg LPUART_STB_1BIT: 1 bit
110 \arg LPUART_STB_2BIT: 2 bits
111 \param[out] none
112 \retval none
113 */
lpuart_stop_bit_set(uint32_t stblen)114 void lpuart_stop_bit_set(uint32_t stblen)
115 {
116 /* disable LPUART */
117 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
118 /* clear LPUART_CTL1 STB bits */
119 LPUART_CTL1 &= ~LPUART_CTL1_STB;
120 LPUART_CTL1 |= stblen;
121 }
122
123 /*!
124 \brief enable LPUART
125 \param[in] none
126 \param[out] none
127 \retval none
128 */
lpuart_enable(void)129 void lpuart_enable(void)
130 {
131 LPUART_CTL0 |= LPUART_CTL0_UEN;
132 }
133
134 /*!
135 \brief disable LPUART
136 \param[in] none
137 \param[out] none
138 \retval none
139 */
lpuart_disable(void)140 void lpuart_disable(void)
141 {
142 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
143 }
144
145 /*!
146 \brief configure LPUART transmitter
147 \param[in] txconfig: enable or disable LPUART transmitter
148 only one parameter can be selected which is shown as below:
149 \arg LPUART_TRANSMIT_ENABLE: enable LPUART transmission
150 \arg LPUART_TRANSMIT_DISABLE: enable LPUART transmission
151 \param[out] none
152 \retval none
153 */
lpuart_transmit_config(uint32_t txconfig)154 void lpuart_transmit_config(uint32_t txconfig)
155 {
156 LPUART_CTL0 &= ~LPUART_CTL0_TEN;
157 /* configure transfer mode */
158 LPUART_CTL0 |= txconfig;
159 }
160
161 /*!
162 \brief configure LPUART receiver
163 \param[in] rxconfig: enable or disable LPUART receiver
164 only one parameter can be selected which is shown as below:
165 \arg LPUART_RECEIVE_ENABLE: enable LPUART reception
166 \arg LPUART_RECEIVE_DISABLE: disable LPUART reception
167 \param[out] none
168 \retval none
169 */
lpuart_receive_config(uint32_t rxconfig)170 void lpuart_receive_config(uint32_t rxconfig)
171 {
172 LPUART_CTL0 &= ~LPUART_CTL0_REN;
173 /* configure receiver mode */
174 LPUART_CTL0 |= rxconfig;
175 }
176
177 /*!
178 \brief data is transmitted/received with the LSB/MSB first
179 \param[in] msbf: LSB/MSB
180 only one parameter can be selected which is shown as below:
181 \arg LPUART_MSBF_LSB: LSB first
182 \arg LPUART_MSBF_MSB: MSB first
183 \param[out] none
184 \retval none
185 */
lpuart_data_first_config(uint32_t msbf)186 void lpuart_data_first_config(uint32_t msbf)
187 {
188 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
189 /* configure LSB or MSB first */
190 LPUART_CTL1 &= ~(LPUART_CTL1_MSBF);
191 LPUART_CTL1 |= (LPUART_CTL1_MSBF & msbf);
192 }
193
194 /*!
195 \brief configure LPUART inverted
196 \param[in] invertpara: refer to lpuart_invert_enum
197 only one parameter can be selected which is shown as below:
198 \arg LPUART_DINV_ENABLE: data bit level inversion
199 \arg LPUART_DINV_DISABLE: data bit level not inversion
200 \arg LPUART_TXPIN_ENABLE: TX pin level inversion
201 \arg LPUART_TXPIN_DISABLE: TX pin level not inversion
202 \arg LPUART_RXPIN_ENABLE: RX pin level inversion
203 \arg LPUART_RXPIN_DISABLE: RX pin level not inversion
204 \arg LPUART_SWAP_ENABLE: swap TX/RX pins
205 \arg LPUART_SWAP_DISABLE: not swap TX/RX pins
206 \param[out] none
207 \retval none
208 */
lpuart_invert_config(lpuart_invert_enum invertpara)209 void lpuart_invert_config(lpuart_invert_enum invertpara)
210 {
211 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
212 /* inverted or not the specified signal */
213 switch(invertpara) {
214 case LPUART_DINV_ENABLE:
215 LPUART_CTL1 |= LPUART_CTL1_DINV;
216 break;
217 case LPUART_DINV_DISABLE:
218 LPUART_CTL1 &= ~(LPUART_CTL1_DINV);
219 break;
220 case LPUART_TXPIN_ENABLE:
221 LPUART_CTL1 |= LPUART_CTL1_TINV;
222 break;
223 case LPUART_TXPIN_DISABLE:
224 LPUART_CTL1 &= ~(LPUART_CTL1_TINV);
225 break;
226 case LPUART_RXPIN_ENABLE:
227 LPUART_CTL1 |= LPUART_CTL1_RINV;
228 break;
229 case LPUART_RXPIN_DISABLE:
230 LPUART_CTL1 &= ~(LPUART_CTL1_RINV);
231 break;
232 case LPUART_SWAP_ENABLE:
233 LPUART_CTL1 |= LPUART_CTL1_STRP;
234 break;
235 case LPUART_SWAP_DISABLE:
236 LPUART_CTL1 &= ~(LPUART_CTL1_STRP);
237 break;
238 default:
239 break;
240 }
241 }
242
243 /*!
244 \brief enable the LPUART overrun function
245 \param[in] none
246 \param[out] none
247 \retval none
248 */
lpuart_overrun_enable(void)249 void lpuart_overrun_enable(void)
250 {
251 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
252 /* enable overrun function */
253 LPUART_CTL2 &= ~(LPUART_CTL2_OVRD);
254 }
255
256 /*!
257 \brief disable the LPUART overrun function
258 \param[in] none
259 \param[out] none
260 \retval none
261 */
lpuart_overrun_disable(void)262 void lpuart_overrun_disable(void)
263 {
264 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
265 /* disable overrun function */
266 LPUART_CTL2 |= LPUART_CTL2_OVRD;
267 }
268
269 /*!
270 \brief LPUART transmit data function
271 \param[in] data: data of transmission
272 \param[out] none
273 \retval none
274 */
lpuart_data_transmit(uint32_t data)275 void lpuart_data_transmit(uint32_t data)
276 {
277 LPUART_TDATA = (LPUART_TDATA_TDATA & data);
278 }
279
280 /*!
281 \brief LPUART receive data function
282 \param[in] none
283 \param[out] none
284 \retval data of received
285 */
lpuart_data_receive(void)286 uint16_t lpuart_data_receive(void)
287 {
288 return (uint16_t)(GET_BITS(LPUART_RDATA, 0U, 8U));
289 }
290
291 /*!
292 \brief enable LPUART command
293 \param[in] cmdtype: command type
294 only one parameter can be selected which is shown as below:
295 \arg LPUART_CMD_MMCMD: mute mode command
296 \arg LPUART_CMD_RXFCMD: receive data flush command
297 \param[out] none
298 \retval none
299 */
lpuart_command_enable(uint32_t cmdtype)300 void lpuart_command_enable(uint32_t cmdtype)
301 {
302 LPUART_CMD |= (cmdtype);
303 }
304
305 /*!
306 \brief configure address of the LPUART
307 \param[in] addr: 0x00-0xFF, address of LPUART terminal
308 \param[out] none
309 \retval none
310 */
lpuart_address_config(uint8_t addr)311 void lpuart_address_config(uint8_t addr)
312 {
313 /* disable LPUART */
314 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
315
316 LPUART_CTL1 &= ~(LPUART_CTL1_ADDR);
317 LPUART_CTL1 |= (LPUART_CTL1_ADDR & (((uint32_t)addr) << 24U));
318 }
319
320 /*!
321 \brief configure address detection mode
322 \param[in] addmod: address detection mode
323 only one parameter can be selected which is shown as below:
324 \arg LPUART_ADDM_4BIT: 4 bits
325 \arg LPUART_ADDM_FULLBIT: full bits
326 \param[out] none
327 \retval none
328 */
lpuart_address_detection_mode_config(uint32_t addmod)329 void lpuart_address_detection_mode_config(uint32_t addmod)
330 {
331 /* disable LPUART */
332 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
333
334 LPUART_CTL1 &= ~(LPUART_CTL1_ADDM);
335 LPUART_CTL1 |= LPUART_CTL1_ADDM & (addmod);
336 }
337
338 /*!
339 \brief enable mute mode
340 \param[in] none
341 \param[out] none
342 \retval none
343 */
lpuart_mute_mode_enable(void)344 void lpuart_mute_mode_enable(void)
345 {
346 LPUART_CTL0 |= LPUART_CTL0_MEN;
347 }
348
349 /*!
350 \brief disable mute mode
351 \param[in] none
352 \param[out] none
353 \retval none
354 */
lpuart_mute_mode_disable(void)355 void lpuart_mute_mode_disable(void)
356 {
357 LPUART_CTL0 &= ~(LPUART_CTL0_MEN);
358 }
359
360 /*!
361 \brief configure wakeup method in mute mode
362 \param[in] wmethod: two methods be used to enter or exit the mute mode
363 only one parameter can be selected which is shown as below:
364 \arg LPUART_WM_IDLE: idle line
365 \arg LPUART_WM_ADDR: address mark
366 \param[out] none
367 \retval none
368 */
lpuart_mute_mode_wakeup_config(uint32_t wmethod)369 void lpuart_mute_mode_wakeup_config(uint32_t wmethod)
370 {
371 /* disable LPUART */
372 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
373
374 LPUART_CTL0 &= ~(LPUART_CTL0_WM);
375 LPUART_CTL0 |= wmethod;
376 }
377
378 /*!
379 \brief enable half-duplex mode
380 \param[in] none
381 \param[out] none
382 \retval none
383 */
lpuart_halfduplex_enable(void)384 void lpuart_halfduplex_enable(void)
385 {
386 /* disable LPUART */
387 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
388
389 LPUART_CTL2 |= LPUART_CTL2_HDEN;
390 }
391
392 /*!
393 \brief disable half-duplex mode
394 \param[in] none
395 \param[out] none
396 \retval none
397 */
lpuart_halfduplex_disable(void)398 void lpuart_halfduplex_disable(void)
399 {
400 /* disable LPUART */
401 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
402
403 LPUART_CTL2 &= ~(LPUART_CTL2_HDEN);
404 }
405
406 /*!
407 \brief configure hardware flow control RTS
408 \param[in] rtsconfig: enable or disable RTS
409 only one parameter can be selected which is shown as below:
410 \arg LPUART_RTS_ENABLE: enable RTS
411 \arg LPUART_RTS_DISABLE: disable RTS
412 \param[out] none
413 \retval none
414 */
lpuart_hardware_flow_rts_config(uint32_t rtsconfig)415 void lpuart_hardware_flow_rts_config(uint32_t rtsconfig)
416 {
417 /* disable LPUART */
418 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
419
420 LPUART_CTL2 &= ~(LPUART_CTL2_RTSEN);
421 LPUART_CTL2 |= rtsconfig;
422 }
423
424 /*!
425 \brief configure hardware flow control CTS
426 \param[in] ctsconfig: enable or disable CTS
427 only one parameter can be selected which is shown as below:
428 \arg LPUART_CTS_ENABLE: enable CTS
429 \arg LPUART_CTS_DISABLE: disable CTS
430 \param[out] none
431 \retval none
432 */
lpuart_hardware_flow_cts_config(uint32_t ctsconfig)433 void lpuart_hardware_flow_cts_config(uint32_t ctsconfig)
434 {
435 /* disable LPUART */
436 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
437
438 LPUART_CTL2 &= ~LPUART_CTL2_CTSEN;
439 LPUART_CTL2 |= ctsconfig;
440 }
441
442 /*!
443 \brief configure hardware flow control coherence mode
444 \param[in] hcm:
445 only one parameter can be selected which is shown as below:
446 \arg LPUART_HCM_NONE: nRTS signal equals to the RBNE status register
447 \arg LPUART_HCM_EN: nRTS signal is set when the last data bit has been sampled
448 \param[out] none
449 \retval none
450 */
lpuart_hardware_flow_coherence_config(uint32_t hcm)451 void lpuart_hardware_flow_coherence_config(uint32_t hcm)
452 {
453 LPUART_CHC &= ~(LPUART_CHC_HCM);
454 LPUART_CHC |= (LPUART_CHC_HCM & hcm);
455 }
456
457 /*!
458 \brief enable RS485 driver
459 \param[in] none
460 \param[out] none
461 \retval none
462 */
lpuart_rs485_driver_enable(void)463 void lpuart_rs485_driver_enable(void)
464 {
465 /* disable LPUART */
466 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
467
468 LPUART_CTL2 |= LPUART_CTL2_DEM;
469 }
470
471 /*!
472 \brief disable RS485 driver
473 \param[in] none
474 \param[out] none
475 \retval none
476 */
lpuart_rs485_driver_disable(void)477 void lpuart_rs485_driver_disable(void)
478 {
479 /* disable LPUART */
480 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
481
482 LPUART_CTL2 &= ~(LPUART_CTL2_DEM);
483 }
484
485 /*!
486 \brief configure driver enable assertion time
487 \param[in] deatime: 0x00000000-0x0000001F
488 \param[out] none
489 \retval none
490 */
lpuart_driver_assertime_config(uint32_t deatime)491 void lpuart_driver_assertime_config(uint32_t deatime)
492 {
493 /* disable LPUART */
494 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
495
496 LPUART_CTL0 &= ~(LPUART_CTL0_DEA);
497 LPUART_CTL0 |= (LPUART_CTL0_DEA & ((deatime) << 21U));
498 }
499
500 /*!
501 \brief configure driver enable de-assertion time
502 \param[in] dedtime: 0x00000000-0x0000001F
503 \param[out] none
504 \retval none
505 */
lpuart_driver_deassertime_config(uint32_t dedtime)506 void lpuart_driver_deassertime_config(uint32_t dedtime)
507 {
508 /* disable LPUART */
509 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
510
511 LPUART_CTL0 &= ~(LPUART_CTL0_DED);
512 LPUART_CTL0 |= (LPUART_CTL0_DED & ((dedtime) << 16U));
513 }
514
515 /*!
516 \brief configure driver enable polarity mode
517 \param[in] dep: DE signal
518 only one parameter can be selected which is shown as below:
519 \arg LPUART_DEP_HIGH: DE signal is active high
520 \arg LPUART_DEP_LOW: DE signal is active low
521 \param[out] none
522 \retval none
523 */
lpuart_depolarity_config(uint32_t dep)524 void lpuart_depolarity_config(uint32_t dep)
525 {
526 /* disable LPUART */
527 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
528 /* reset DEP bit */
529 LPUART_CTL2 &= ~(LPUART_CTL2_DEP);
530 LPUART_CTL2 |= (LPUART_CTL2_DEP & dep);
531 }
532
533 /*!
534 \brief configure LPUART DMA for reception
535 \param[in] dmacmd: enable or disable DMA for reception
536 only one parameter can be selected which is shown as below:
537 \arg LPUART_DENR_ENABLE: DMA enable for reception
538 \arg LPUART_DENR_DISABLE: DMA disable for reception
539 \param[out] none
540 \retval none
541 */
lpuart_dma_receive_config(uint32_t dmacmd)542 void lpuart_dma_receive_config(uint32_t dmacmd)
543 {
544 LPUART_CTL2 &= ~LPUART_CTL2_DENR;
545 /* configure DMA reception */
546 LPUART_CTL2 |= dmacmd;
547 }
548
549 /*!
550 \brief configure LPUART DMA for transmission
551 \param[in] dmacmd: enable or disable DMA for transmission
552 only one parameter can be selected which is shown as below:
553 \arg LPUART_DENT_ENABLE: DMA enable for transmission
554 \arg LPUART_DENT_DISABLE: DMA disable for transmission
555 \param[out] none
556 \retval none
557 */
lpuart_dma_transmit_config(uint32_t dmacmd)558 void lpuart_dma_transmit_config(uint32_t dmacmd)
559 {
560 LPUART_CTL2 &= ~LPUART_CTL2_DENT;
561 /* configure DMA transmission */
562 LPUART_CTL2 |= dmacmd;
563 }
564
565 /*!
566 \brief disable DMA on reception error
567 \param[in] none
568 \param[out] none
569 \retval none
570 */
lpuart_reception_error_dma_disable(void)571 void lpuart_reception_error_dma_disable(void)
572 {
573 /* disable LPUART */
574 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
575
576 LPUART_CTL2 |= LPUART_CTL2_DDRE;
577 }
578
579 /*!
580 \brief enable DMA on reception error
581 \param[in] none
582 \param[out] none
583 \retval none
584 */
lpuart_reception_error_dma_enable(void)585 void lpuart_reception_error_dma_enable(void)
586 {
587 /* disable LPUART */
588 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
589
590 LPUART_CTL2 &= ~(LPUART_CTL2_DDRE);
591 }
592
593 /*!
594 \brief enable LPUART to wakeup the mcu from deep-sleep mode
595 \param[in] none
596 \param[out] none
597 \retval none
598 */
lpuart_wakeup_enable(void)599 void lpuart_wakeup_enable(void)
600 {
601 LPUART_CTL0 |= LPUART_CTL0_UESM;
602 }
603
604 /*!
605 \brief disable LPUART to wakeup the mcu from deep-sleep mode
606 \param[in] none
607 \param[out] none
608 \retval none
609 */
lpuart_wakeup_disable(void)610 void lpuart_wakeup_disable(void)
611 {
612 LPUART_CTL0 &= ~(LPUART_CTL0_UESM);
613 }
614
615 /*!
616 \brief configure the LPUART wakeup mode from deep-sleep mode
617 \param[in] wum: wakeup mode
618 only one parameter can be selected which is shown as below:
619 \arg LPUART_WUM_ADDR: WUF active on address match
620 \arg LPUART_WUM_STARTB: WUF active on start bit
621 \arg LPUART_WUM_RBNE: WUF active on RBNE
622 \param[out] none
623 \retval none
624 */
lpuart_wakeup_mode_config(uint32_t wum)625 void lpuart_wakeup_mode_config(uint32_t wum)
626 {
627 /* disable LPUART */
628 LPUART_CTL0 &= ~(LPUART_CTL0_UEN);
629 /* reset WUM bit */
630 LPUART_CTL2 &= ~(LPUART_CTL2_WUM);
631 LPUART_CTL2 |= LPUART_CTL2_WUM & (wum);
632 }
633
634 /*!
635 \brief get flag in STAT/CHC register
636 \param[in] flag: flag type
637 only one parameter can be selected which is shown as below:
638 \arg LPUART_FLAG_PERR: parity error flag
639 \arg LPUART_FLAG_FERR: frame error flag
640 \arg LPUART_FLAG_NERR: noise error flag
641 \arg LPUART_FLAG_ORERR: overrun error
642 \arg LPUART_FLAG_IDLE: idle line detected flag
643 \arg LPUART_FLAG_RBNE: read data buffer not empty
644 \arg LPUART_FLAG_TC: transmission completed
645 \arg LPUART_FLAG_TBE: transmit data register empty
646 \arg LPUART_FLAG_CTSF: CTS change flag
647 \arg LPUART_FLAG_CTS: CTS level
648 \arg LPUART_FLAG_BSY: busy flag
649 \arg LPUART_FLAG_AM: address match flag
650 \arg LPUART_FLAG_RWU: receiver wakeup from mute mode.
651 \arg LPUART_FLAG_WU: wakeup from deep-sleep mode flag
652 \arg LPUART_FLAG_TEA: transmit enable acknowledge flag
653 \arg LPUART_FLAG_REA: receive enable acknowledge flag
654 \arg LPUART_FLAG_EPERR: early parity error flag
655 \param[out] none
656 \retval FlagStatus: SET or RESET
657 */
lpuart_flag_get(lpuart_flag_enum flag)658 FlagStatus lpuart_flag_get(lpuart_flag_enum flag)
659 {
660 if(RESET != (LPUART_REG_VAL(LPUART, flag) & BIT(LPUART_BIT_POS(flag)))) {
661 return SET;
662 } else {
663 return RESET;
664 }
665 }
666
667 /*!
668 \brief clear LPUART status
669 \param[in] flag: flag type
670 only one parameter can be selected which is shown as below:
671 \arg LPUART_FLAG_PERR: parity error flag
672 \arg LPUART_FLAG_FERR: frame error flag
673 \arg LPUART_FLAG_NERR: noise detected flag
674 \arg LPUART_FLAG_ORERR: overrun error flag
675 \arg LPUART_FLAG_IDLE: idle line detected flag
676 \arg LPUART_FLAG_TC: transmission complete flag
677 \arg LPUART_FLAG_CTSF: CTS change flag
678 \arg LPUART_FLAG_AM: address match flag
679 \arg LPUART_FLAG_WU: wakeup from deep-sleep mode flag
680 \arg LPUART_FLAG_EPERR: early parity error flag
681 \param[out] none
682 \retval none
683 */
lpuart_flag_clear(lpuart_flag_enum flag)684 void lpuart_flag_clear(lpuart_flag_enum flag)
685 {
686 LPUART_INTC |= BIT(LPUART_BIT_POS(flag));
687 }
688
689 /*!
690 \brief enable LPUART interrupt
691 \param[in] interrupt: interrupt type
692 only one parameter can be selected which is shown as below:
693 \arg LPUART_INT_IDLE: idle interrupt
694 \arg LPUART_INT_RBNE: read data buffer not empty interrupt and
695 overrun error interrupt enable interrupt
696 \arg LPUART_INT_TC: transmission complete interrupt
697 \arg LPUART_INT_TBE: transmit data register empty interrupt
698 \arg LPUART_INT_PERR: parity error interrupt
699 \arg LPUART_INT_AM: address match interrupt
700 \arg LPUART_INT_ERR: error interrupt enable in multibuffer communication
701 \arg LPUART_INT_CTS: CTS interrupt
702 \arg LPUART_INT_WU: wakeup from deep-sleep mode interrupt
703 \param[out] none
704 \retval none
705 */
lpuart_interrupt_enable(lpuart_interrupt_enum interrupt)706 void lpuart_interrupt_enable(lpuart_interrupt_enum interrupt)
707 {
708 LPUART_REG_VAL(LPUART, interrupt) |= BIT(LPUART_BIT_POS(interrupt));
709 }
710
711 /*!
712 \brief disable LPUART interrupt
713 \param[in] interrupt: interrupt type
714 only one parameter can be selected which is shown as below:
715 \arg LPUART_INT_IDLE: idle interrupt
716 \arg LPUART_INT_RBNE: read data buffer not empty interrupt and
717 overrun error interrupt enable interrupt
718 \arg LPUART_INT_TC: transmission complete interrupt
719 \arg LPUART_INT_TBE: transmit data register empty interrupt
720 \arg LPUART_INT_PERR: parity error interrupt
721 \arg LPUART_INT_AM: address match interrupt
722 \arg LPUART_INT_LBD: LIN break detection interrupt
723 \arg LPUART_INT_ERR: error interrupt enable in multibuffer communication
724 \arg LPUART_INT_CTS: CTS interrupt
725 \arg LPUART_INT_WU: wakeup from deep-sleep mode interrupt
726 \param[out] none
727 \retval none
728 */
lpuart_interrupt_disable(lpuart_interrupt_enum interrupt)729 void lpuart_interrupt_disable(lpuart_interrupt_enum interrupt)
730 {
731 LPUART_REG_VAL(LPUART, interrupt) &= ~BIT(LPUART_BIT_POS(interrupt));
732 }
733
734 /*!
735 \brief get LPUART interrupt and flag status
736 \param[in] int_flag: interrupt and flag type, refer to lpuart_interrupt_flag_enum
737 only one parameter can be selected which is shown as below:
738 \arg LPUART_INT_FLAG_AM: address match interrupt and flag
739 \arg LPUART_INT_FLAG_PERR: parity error interrupt and flag
740 \arg LPUART_INT_FLAG_TBE: transmitter buffer empty interrupt and flag
741 \arg LPUART_INT_FLAG_TC: transmission complete interrupt and flag
742 \arg LPUART_INT_FLAG_RBNE: read data buffer not empty interrupt and flag
743 \arg LPUART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag
744 \arg LPUART_INT_FLAG_IDLE: IDLE line detected interrupt and flag
745 \arg LPUART_INT_FLAG_WU: wakeup from deep-sleep mode interrupt and flag
746 \arg LPUART_INT_FLAG_CTS: CTS interrupt and flag
747 \arg LPUART_INT_FLAG_ERR_NERR: error interrupt and noise error flag
748 \arg LPUART_INT_FLAG_ERR_ORERR: error interrupt and overrun error
749 \arg LPUART_INT_FLAG_ERR_FERR: error interrupt and frame error flag
750 \param[out] none
751 \retval FlagStatus: SET or RESET
752 */
lpuart_interrupt_flag_get(lpuart_interrupt_flag_enum int_flag)753 FlagStatus lpuart_interrupt_flag_get(lpuart_interrupt_flag_enum int_flag)
754 {
755 uint32_t intenable = 0U, flagstatus = 0U;
756 /* get the interrupt enable bit status */
757 intenable = (LPUART_REG_VAL(LPUART, int_flag) & BIT(LPUART_BIT_POS(int_flag)));
758 /* get the corresponding flag bit status */
759 flagstatus = (LPUART_REG_VAL2(LPUART, int_flag) & BIT(LPUART_BIT_POS2(int_flag)));
760
761 if(flagstatus && intenable) {
762 return SET;
763 } else {
764 return RESET;
765 }
766 }
767
768 /*!
769 \brief clear LPUART interrupt flag
770 \param[in] int_flag: LPUART interrupt flag
771 only one parameter can be selected which is shown as below:
772 \arg LPUART_INT_FLAG_PERR: parity error flag
773 \arg LPUART_INT_FLAG_ERR_FERR: frame error flag
774 \arg LPUART_INT_FLAG_ERR_NERR: noise detected flag
775 \arg LPUART_INT_FLAG_RBNE_ORERR: read data buffer not empty interrupt and overrun error flag
776 \arg LPUART_INT_FLAG_ERR_ORERR: error interrupt and overrun error
777 \arg LPUART_INT_FLAG_IDLE: idle line detected flag
778 \arg LPUART_INT_FLAG_TC: transmission complete flag
779 \arg LPUART_INT_FLAG_CTS: CTS change flag
780 \arg LPUART_INT_FLAG_AM: address match flag
781 \arg LPUART_INT_FLAG_WU: wakeup from deep-sleep mode flag
782 \param[out] none
783 \retval none
784 */
lpuart_interrupt_flag_clear(lpuart_interrupt_flag_enum int_flag)785 void lpuart_interrupt_flag_clear(lpuart_interrupt_flag_enum int_flag)
786 {
787 LPUART_INTC |= BIT(LPUART_BIT_POS2(int_flag));
788 }
789
