1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017, 2023 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef FSL_LPTMR_H_
9 #define FSL_LPTMR_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup lptmr
15 * @{
16 */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 /*! Driver Version */
25 #define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
26 /*@}*/
27
28 /*! @brief LPTMR pin selection used in pulse counter mode.*/
29 typedef enum _lptmr_pin_select
30 {
31 kLPTMR_PinSelectInput_0 = 0x0U, /*!< Pulse counter input 0 is selected */
32 kLPTMR_PinSelectInput_1 = 0x1U, /*!< Pulse counter input 1 is selected */
33 kLPTMR_PinSelectInput_2 = 0x2U, /*!< Pulse counter input 2 is selected */
34 kLPTMR_PinSelectInput_3 = 0x3U /*!< Pulse counter input 3 is selected */
35 } lptmr_pin_select_t;
36
37 /*! @brief LPTMR pin polarity used in pulse counter mode.*/
38 typedef enum _lptmr_pin_polarity
39 {
40 kLPTMR_PinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high */
41 kLPTMR_PinPolarityActiveLow = 0x1U /*!< Pulse Counter input source is active-low */
42 } lptmr_pin_polarity_t;
43
44 /*! @brief LPTMR timer mode selection.*/
45 typedef enum _lptmr_timer_mode
46 {
47 kLPTMR_TimerModeTimeCounter = 0x0U, /*!< Time Counter mode */
48 kLPTMR_TimerModePulseCounter = 0x1U /*!< Pulse Counter mode */
49 } lptmr_timer_mode_t;
50
51 /*! @brief LPTMR prescaler/glitch filter values*/
52 typedef enum _lptmr_prescaler_glitch_value
53 {
54 kLPTMR_Prescale_Glitch_0 = 0x0U, /*!< Prescaler divide 2, glitch filter does not support this setting */
55 kLPTMR_Prescale_Glitch_1 = 0x1U, /*!< Prescaler divide 4, glitch filter 2 */
56 kLPTMR_Prescale_Glitch_2 = 0x2U, /*!< Prescaler divide 8, glitch filter 4 */
57 kLPTMR_Prescale_Glitch_3 = 0x3U, /*!< Prescaler divide 16, glitch filter 8 */
58 kLPTMR_Prescale_Glitch_4 = 0x4U, /*!< Prescaler divide 32, glitch filter 16 */
59 kLPTMR_Prescale_Glitch_5 = 0x5U, /*!< Prescaler divide 64, glitch filter 32 */
60 kLPTMR_Prescale_Glitch_6 = 0x6U, /*!< Prescaler divide 128, glitch filter 64 */
61 kLPTMR_Prescale_Glitch_7 = 0x7U, /*!< Prescaler divide 256, glitch filter 128 */
62 kLPTMR_Prescale_Glitch_8 = 0x8U, /*!< Prescaler divide 512, glitch filter 256 */
63 kLPTMR_Prescale_Glitch_9 = 0x9U, /*!< Prescaler divide 1024, glitch filter 512*/
64 kLPTMR_Prescale_Glitch_10 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024 */
65 kLPTMR_Prescale_Glitch_11 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048 */
66 kLPTMR_Prescale_Glitch_12 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096 */
67 kLPTMR_Prescale_Glitch_13 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192 */
68 kLPTMR_Prescale_Glitch_14 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384 */
69 kLPTMR_Prescale_Glitch_15 = 0xFU /*!< Prescaler divide 65536, glitch filter 32768 */
70 } lptmr_prescaler_glitch_value_t;
71
72 /*!
73 * @brief LPTMR prescaler/glitch filter clock select.
74 * @note Clock connections are SoC-specific
75 */
76 typedef enum _lptmr_prescaler_clock_select
77 {
78 #if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT) && \
79 FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT)
80 kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */
81 #endif
82
83 #if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) && \
84 FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT)
85 kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */
86 #endif /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT */
87
88 #if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT) && \
89 FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT)
90 kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */
91 #endif
92
93 #if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) && \
94 FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT)
95 kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */
96 #endif /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT */
97 } lptmr_prescaler_clock_select_t;
98
99 /*! @brief List of the LPTMR interrupts */
100 typedef enum _lptmr_interrupt_enable
101 {
102 kLPTMR_TimerInterruptEnable = LPTMR_CSR_TIE_MASK, /*!< Timer interrupt enable */
103 } lptmr_interrupt_enable_t;
104
105 /*! @brief List of the LPTMR status flags */
106 typedef enum _lptmr_status_flags
107 {
108 kLPTMR_TimerCompareFlag = LPTMR_CSR_TCF_MASK, /*!< Timer compare flag */
109 } lptmr_status_flags_t;
110
111 /*!
112 * @brief LPTMR config structure
113 *
114 * This structure holds the configuration settings for the LPTMR peripheral. To initialize this
115 * structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a
116 * pointer to your configuration structure instance.
117 *
118 * The configuration struct can be made constant so it resides in flash.
119 */
120 typedef struct _lptmr_config
121 {
122 lptmr_timer_mode_t timerMode; /*!< Time counter mode or pulse counter mode */
123 lptmr_pin_select_t pinSelect; /*!< LPTMR pulse input pin select; used only in pulse counter mode */
124 lptmr_pin_polarity_t pinPolarity; /*!< LPTMR pulse input pin polarity; used only in pulse counter mode */
125 bool enableFreeRunning; /*!< True: enable free running, counter is reset on overflow
126 False: counter is reset when the compare flag is set */
127 bool bypassPrescaler; /*!< True: bypass prescaler; false: use clock from prescaler */
128 lptmr_prescaler_clock_select_t prescalerClockSource; /*!< LPTMR clock source */
129 lptmr_prescaler_glitch_value_t value; /*!< Prescaler or glitch filter value */
130 } lptmr_config_t;
131
132 /*******************************************************************************
133 * API
134 ******************************************************************************/
135
136 #if defined(__cplusplus)
137 extern "C" {
138 #endif
139
140 /*!
141 * @name Initialization and deinitialization
142 * @{
143 */
144
145 /*!
146 * @brief Ungates the LPTMR clock and configures the peripheral for a basic operation.
147 *
148 * @note This API should be called at the beginning of the application using the LPTMR driver.
149 *
150 * @param base LPTMR peripheral base address
151 * @param config A pointer to the LPTMR configuration structure.
152 */
153 void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config);
154
155 /*!
156 * @brief Gates the LPTMR clock.
157 *
158 * @param base LPTMR peripheral base address
159 */
160 void LPTMR_Deinit(LPTMR_Type *base);
161
162 /*!
163 * @brief Fills in the LPTMR configuration structure with default settings.
164 *
165 * The default values are as follows.
166 * @code
167 * config->timerMode = kLPTMR_TimerModeTimeCounter;
168 * config->pinSelect = kLPTMR_PinSelectInput_0;
169 * config->pinPolarity = kLPTMR_PinPolarityActiveHigh;
170 * config->enableFreeRunning = false;
171 * config->bypassPrescaler = true;
172 * config->prescalerClockSource = kLPTMR_PrescalerClock_1;
173 * config->value = kLPTMR_Prescale_Glitch_0;
174 * @endcode
175 * @param config A pointer to the LPTMR configuration structure.
176 */
177 void LPTMR_GetDefaultConfig(lptmr_config_t *config);
178
179 /*! @}*/
180
181 /*!
182 * @name Interrupt Interface
183 * @{
184 */
185
186 /*!
187 * @brief Enables the selected LPTMR interrupts.
188 *
189 * @param base LPTMR peripheral base address
190 * @param mask The interrupts to enable. This is a logical OR of members of the
191 * enumeration ::lptmr_interrupt_enable_t
192 */
LPTMR_EnableInterrupts(LPTMR_Type * base,uint32_t mask)193 static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask)
194 {
195 uint32_t reg = base->CSR;
196
197 /* Clear the TCF bit so that we don't clear this w1c bit when writing back */
198 reg &= ~(LPTMR_CSR_TCF_MASK);
199 reg |= mask;
200 base->CSR = reg;
201 }
202
203 /*!
204 * @brief Disables the selected LPTMR interrupts.
205 *
206 * @param base LPTMR peripheral base address
207 * @param mask The interrupts to disable. This is a logical OR of members of the
208 * enumeration ::lptmr_interrupt_enable_t.
209 */
LPTMR_DisableInterrupts(LPTMR_Type * base,uint32_t mask)210 static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask)
211 {
212 uint32_t reg = base->CSR;
213
214 /* Clear the TCF bit so that we don't clear this w1c bit when writing back */
215 reg &= ~(LPTMR_CSR_TCF_MASK);
216 reg &= ~mask;
217 base->CSR = reg;
218 }
219
220 /*!
221 * @brief Gets the enabled LPTMR interrupts.
222 *
223 * @param base LPTMR peripheral base address
224 *
225 * @return The enabled interrupts. This is the logical OR of members of the
226 * enumeration ::lptmr_interrupt_enable_t
227 */
LPTMR_GetEnabledInterrupts(LPTMR_Type * base)228 static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base)
229 {
230 return (base->CSR & LPTMR_CSR_TIE_MASK);
231 }
232
233 /*! @}*/
234
235 #if defined(FSL_FEATURE_LPTMR_HAS_CSR_TDRE) && (FSL_FEATURE_LPTMR_HAS_CSR_TDRE)
236 /*!
237 * @brief Enable or disable timer DMA request
238 *
239 * @param base base LPTMR peripheral base address
240 * @param enable Switcher of timer DMA feature. "true" means to enable, "false" means to disable.
241 */
LPTMR_EnableTimerDMA(LPTMR_Type * base,bool enable)242 static inline void LPTMR_EnableTimerDMA(LPTMR_Type *base, bool enable)
243 {
244 if (enable)
245 {
246 base->CSR |= LPTMR_CSR_TDRE_MASK;
247 }
248 else
249 {
250 base->CSR &= ~(LPTMR_CSR_TDRE_MASK);
251 }
252 }
253 #endif /* FSL_FEATURE_LPTMR_HAS_CSR_TDRE */
254
255 /*!
256 * @name Status Interface
257 * @{
258 */
259
260 /*!
261 * @brief Gets the LPTMR status flags.
262 *
263 * @param base LPTMR peripheral base address
264 *
265 * @return The status flags. This is the logical OR of members of the
266 * enumeration ::lptmr_status_flags_t
267 */
LPTMR_GetStatusFlags(LPTMR_Type * base)268 static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base)
269 {
270 return (base->CSR & LPTMR_CSR_TCF_MASK);
271 }
272
273 /*!
274 * @brief Clears the LPTMR status flags.
275 *
276 * @param base LPTMR peripheral base address
277 * @param mask The status flags to clear. This is a logical OR of members of the
278 * enumeration ::lptmr_status_flags_t.
279 */
LPTMR_ClearStatusFlags(LPTMR_Type * base,uint32_t mask)280 static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask)
281 {
282 base->CSR |= mask;
283 }
284
285 /*! @}*/
286
287 /*!
288 * @name Read and write the timer period
289 * @{
290 */
291
292 /*!
293 * @brief Sets the timer period in units of count.
294 *
295 * Timers counts from 0 until it equals the count value set here. The count value is written to
296 * the CMR register.
297 *
298 * @note
299 * 1. The TCF flag is set with the CNR equals the count provided here and then increments.
300 * 2. Call the utility macros provided in the fsl_common.h to convert to ticks.
301 *
302 * @param base LPTMR peripheral base address
303 * @param ticks A timer period in units of ticks, which should be equal or greater than 1.
304 */
LPTMR_SetTimerPeriod(LPTMR_Type * base,uint32_t ticks)305 static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint32_t ticks)
306 {
307 assert(ticks > 0U);
308 base->CMR = LPTMR_CMR_COMPARE(ticks - 1U);
309 }
310
311 /*!
312 * @brief Reads the current timer counting value.
313 *
314 * This function returns the real-time timer counting value in a range from 0 to a
315 * timer period.
316 *
317 * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.
318 *
319 * @param base LPTMR peripheral base address
320 *
321 * @return The current counter value in ticks
322 */
LPTMR_GetCurrentTimerCount(LPTMR_Type * base)323 static inline uint32_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base)
324 {
325 /* Must first write any value to the CNR. This synchronizes and registers the current value
326 * of the CNR into a temporary register which can then be read
327 */
328 base->CNR = 0U;
329 return (uint32_t)((base->CNR & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COUNTER_SHIFT);
330 }
331
332 /*! @}*/
333
334 /*!
335 * @name Timer Start and Stop
336 * @{
337 */
338
339 /*!
340 * @brief Starts the timer.
341 *
342 * After calling this function, the timer counts up to the CMR register value.
343 * Each time the timer reaches the CMR value and then increments, it generates a
344 * trigger pulse and sets the timeout interrupt flag. An interrupt is also
345 * triggered if the timer interrupt is enabled.
346 *
347 * @param base LPTMR peripheral base address
348 */
LPTMR_StartTimer(LPTMR_Type * base)349 static inline void LPTMR_StartTimer(LPTMR_Type *base)
350 {
351 uint32_t reg = base->CSR;
352
353 /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */
354 reg &= ~(LPTMR_CSR_TCF_MASK);
355 reg |= LPTMR_CSR_TEN_MASK;
356 base->CSR = reg;
357 }
358
359 /*!
360 * @brief Stops the timer.
361 *
362 * This function stops the timer and resets the timer's counter register.
363 *
364 * @param base LPTMR peripheral base address
365 */
LPTMR_StopTimer(LPTMR_Type * base)366 static inline void LPTMR_StopTimer(LPTMR_Type *base)
367 {
368 uint32_t reg = base->CSR;
369
370 /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */
371 reg &= ~(LPTMR_CSR_TCF_MASK);
372 reg &= ~LPTMR_CSR_TEN_MASK;
373 base->CSR = reg;
374 }
375
376 /*! @}*/
377
378 #if defined(__cplusplus)
379 }
380 #endif
381
382 /*! @}*/
383
384 #endif /* FSL_LPTMR_H_ */
385
